blob: 19f496705396890e44d3d63c90a59447f167b72a [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001/*
2 * (C) Copyright 2016 ZXIC Inc.
3 *
4 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/arch/top_clock.h>
9#include <board.h>
10
11
12void clk_init (void)
13{
14 __REG(MPLL_CFG0_REG) = 0x08040c11;
15 //__REG(APLL_CFG0_REG) = 0x08081009; /*APLL ,832M*/
16 __REG(UPLL_CFG0_REG) = 0x08347811;
17 __REG(GPLL_CFG0_REG) = 0x08347d29;
18 //__REG(DPLL_CFG0_REG) = 0x0a040c19; /*DPLL,26M*/
19
20 //__REG(PLL_LOCK_CNT0) = 0x03e003e0; /*PLL_LOCK_CNT0*/
21 //__REG(PLL_LOCK_CNT1) = 0x03e003e0; /*PLL_LOCK_CNT1*/
22 //__REG(RMCORE_CLK_CFG_REG) = 0x80000100; /*rm apb div 4*/
23 while( !(__REG(MPLL_CFG0_REG) & (0x1 << 30) ));
24 while( !(__REG(UPLL_CFG0_REG) & (0x1 << 30) ));
25 while( !(__REG(GPLL_CFG0_REG) & (0x1 << 30) ));
26
27 //M0 select 104M, bit0-1, 0=104, 1=26, 2=78, 3=32k
28 __REG(M0_CORE_SEL) = 0x00000005;
29 //hs_ahb_clk select 104M, bit4-5, 0=104, 1=26, 2=78, 3=32k
30 __REG(HS_AHB_CLK) = 0x00000010;
31
32 __REG(MATRIX_AXI_SEL) = 0x00010001; /*AXI select 156M*/
33 __REG(PS_CORE_SEL) = 0x00000001; /*R7 select 624M*/
34 __REG(PHY_CORE_SEL) = 0x00000001; /*ZSP880 select 491M*/
35 __REG(AP_CORE_SEL) = 0x00000001; /*AP A53 select 624M*/
36
37 //__REG(RM_MOD_CLKSEL) = 0x80000034;/*high speed aclk 156M*/
38}
39