lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2016 ZXIC Inc. |
| 3 | */ |
| 4 | |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/arch/denali.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <bbt.h> |
| 10 | |
| 11 | #include "flash.h" |
| 12 | |
| 13 | |
| 14 | static struct nand_flash_device_para *nand_info = NULL; |
| 15 | /* nand flash parameter config */ |
| 16 | static const struct nand_flash_device_para nand_flash_para[] = { |
| 17 | /* MT29F4G08ABBDAH4 for 7520V5 evb 512MB X 8 */ |
| 18 | {0x2C, 0xAC, 0x90, 0, 4, 2048,11, 64, 17, 4096, 0x20000}, |
| 19 | /* MT29F2G08ABBEA for 7520 evb 256MB X 8 */ |
| 20 | {0x2C, 0xAA, 0x90, 0, 4, 2048,11, 64, 17, 2048, 0x20000}, |
| 21 | |
| 22 | /* K9F2G08U0B for 7520 FPGA */ |
| 23 | {0xEC, 0xDA, 0x10, 0, 4, 2048,11, 64, 17,2048, 0x20000}, |
| 24 | |
| 25 | /* JSFBA3YHABB for 7510 evb 256MB X 8 ---> DDR 128M*/ |
| 26 | {0xAD, 0xAA, 0x90, 0, 8, 2048, 11, 128, 17,2048, 0x20000}, |
| 27 | |
| 28 | /* FM6BD2G1GA for 7510 evb 256MB X 8 ---> DDR 128M */ |
| 29 | {0xC8, 0xAA, 0x90, 0, 4, 2048, 11, 64, 17, 2048, 0x20000}, |
| 30 | |
| 31 | /* H9TA4GG4GDMCPR for 7510 evb 512MB X 8 ---> DDR 512M */ |
| 32 | {0xAD, 0xAC, 0x90, 0, 8, 2048, 11, 128, 17, 4096, 0x20000}, |
| 33 | |
| 34 | /* JSFCBX3Y7ABB for 7510 evb 512MB X 8 ---> DDR 256M */ |
| 35 | {0x01, 0xAC, 0x90, 0, 8, 2048, 11, 128, 17, 4096, 0x20000}, |
| 36 | |
| 37 | /* FM6BD4G2GA for 7510 evb 512MB X 8 ---> DDR 256M*/ |
| 38 | {0xC8, 0xAC, 0x90, 0, 4, 2048, 11, 64, 17, 4096, 0x20000}, |
| 39 | |
| 40 | /* NM1281KSLAXAJ for 7510 evb 256MB X 8 ---> DDR 128M*/ |
| 41 | {0x98, 0xAA, 0x90, 0, 8, 2048, 11, 128, 17, 2048, 0x20000}, |
| 42 | |
| 43 | /* W71NW20GF3FW for 7520 evb 256MB X 8 */ |
| 44 | {0xEF, 0xAA, 0x90, 0, 4, 2048,11, 64, 17, 2048, 0x20000}, |
| 45 | {0} |
| 46 | }; |
| 47 | |
| 48 | |
| 49 | |
| 50 | |
| 51 | /******************************************************************************* |
| 52 | * Function: |
| 53 | * Description: |
| 54 | * Parameters: |
| 55 | * Input: |
| 56 | * |
| 57 | * Output: |
| 58 | * |
| 59 | * Returns: |
| 60 | * |
| 61 | * |
| 62 | * Others: |
| 63 | ********************************************************************************/ |
| 64 | static uint32_t wait_for_ready(uint32_t status_type) |
| 65 | { |
| 66 | uint32_t status = 0; |
| 67 | while (!(readl(INTR_STATUS(0)) & status_type)); |
| 68 | status = readl(INTR_STATUS(0)); |
| 69 | writew(0xffff, INTR_STATUS(0)); |
| 70 | return status; |
| 71 | } |
| 72 | |
| 73 | |
| 74 | /******************************************************************************* |
| 75 | * Function: |
| 76 | * Description: |
| 77 | * Parameters: |
| 78 | * Input: |
| 79 | * |
| 80 | * Output: |
| 81 | * |
| 82 | * Returns: |
| 83 | * |
| 84 | * |
| 85 | * Others: |
| 86 | ********************************************************************************/ |
| 87 | static void index_addr(uint32_t address, uint32_t data) |
| 88 | { |
| 89 | writel(address, NAND_DATA); |
| 90 | writel(data, NAND_DATA_10); |
| 91 | } |
| 92 | |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * Function: |
| 96 | * Description: |
| 97 | * Parameters: |
| 98 | * Input: |
| 99 | * |
| 100 | * Output: |
| 101 | * |
| 102 | * Returns: |
| 103 | * |
| 104 | * |
| 105 | * Others: |
| 106 | ********************************************************************************/ |
| 107 | static void index_addr_read_data(uint32_t address, uint32_t *pdata) |
| 108 | { |
| 109 | writel(address, NAND_DATA); |
| 110 | *pdata = readl(NAND_DATA_10); |
| 111 | } |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * Function: |
| 115 | * Description: |
| 116 | * Parameters: |
| 117 | * Input: |
| 118 | * |
| 119 | * Output: |
| 120 | * |
| 121 | * Returns: |
| 122 | * |
| 123 | * |
| 124 | * Others: |
| 125 | ********************************************************************************/ |
| 126 | void nand_read_oob(uint8_t *buf, uint32_t offset, uint32_t len) |
| 127 | { |
| 128 | uint32_t cmd, i, status_type; |
| 129 | uint32_t *buf32 = NULL; |
| 130 | uint32_t addr = offset >> (nand_info->page_size_shift); //addr = bank0 | page |
| 131 | |
| 132 | /* 0. disable ECC */ |
| 133 | writel(ECC_DISABLE__FLAG, ECC_ENABLE); |
| 134 | |
| 135 | writel(0xffff, INTR_STATUS(0)); |
| 136 | |
| 137 | writel(TRANSFER_SPARE_REG__FLAG, TRANSFER_SPARE_REG); |
| 138 | |
| 139 | /* setup page read request for SPARE_ACCESS read */ |
| 140 | cmd = MODE_10 | addr; |
| 141 | index_addr((uint32_t)cmd, SPARE_ACCESS); |
| 142 | |
| 143 | cmd = MODE_10 | addr; |
| 144 | index_addr((uint32_t)cmd, 0x2001); |
| 145 | |
| 146 | /* page 33 of the NAND controller spec indicates we should not |
| 147 | use the pipeline commands in Spare area only mode. So we |
| 148 | don't. |
| 149 | */ |
| 150 | cmd = MODE_01 | addr; |
| 151 | writel(cmd, NAND_DATA); |
| 152 | |
| 153 | status_type = wait_for_ready(INTR_STATUS__LOAD_COMP | INTR_STATUS__TIME_OUT); |
| 154 | if (status_type & INTR_STATUS__TIME_OUT) |
| 155 | printf("[OT]\n"); /* OOB TIMEOUT */ |
| 156 | |
| 157 | /* 0. read oob data */ |
| 158 | buf32 = (uint32_t *)buf; |
| 159 | for (i = 0; i < len / 4; i++) |
| 160 | *buf32++ = readl(NAND_DATA_10); |
| 161 | |
| 162 | /* We set the device back to MAIN_ACCESS here as I observed |
| 163 | * instability with the controller if you do a block erase |
| 164 | * and the last transaction was a SPARE_ACCESS. Block erase |
| 165 | * is reliable (according to the MTD test infrastructure) |
| 166 | * if you are in MAIN_ACCESS. |
| 167 | */ |
| 168 | cmd = MODE_10 | addr; |
| 169 | index_addr((uint32_t)cmd, MAIN_ACCESS); |
| 170 | |
| 171 | } |
| 172 | |
| 173 | |
| 174 | void clear_intr(void) |
| 175 | { |
| 176 | while(readl(INTR_STATUS(0))) |
| 177 | { |
| 178 | writew(0xffff, INTR_STATUS(0)); |
| 179 | |
| 180 | } |
| 181 | writew(0xffff, INTR_STATUS(0)); |
| 182 | |
| 183 | nsdelay(400000);//0.02s |
| 184 | } |
| 185 | |
| 186 | /******************************************************************************* |
| 187 | * Function: |
| 188 | * Description: |
| 189 | * Parameters: |
| 190 | * Input: |
| 191 | * |
| 192 | * Output: |
| 193 | * |
| 194 | * Returns: |
| 195 | * |
| 196 | * |
| 197 | * Others: |
| 198 | ********************************************************************************/ |
| 199 | int32_t read_page(uint32_t buf, uint32_t offset) |
| 200 | { |
| 201 | uint32_t status = 0; |
| 202 | int32_t ecc_status = 0; |
| 203 | uint32_t page = offset >> (nand_info->page_size_shift); |
| 204 | uint32_t mode = MODE_10; /* MODE_10 | BANK(denali->flash_bank) */ |
| 205 | |
| 206 | if((buf & 0x3) != 0) /* DMAµØÖ·ÒªÇó4×Ö½Ú¶ÔÆë */ |
| 207 | { |
| 208 | printf("[AE]\n"); /* [read_page]:ADDR ERROR */ |
| 209 | return -1; |
| 210 | } |
| 211 | |
| 212 | ecc_status =readl(ECC_CORRECTION); |
| 213 | |
| 214 | if(page < 64) |
| 215 | { |
| 216 | writel(0x8, ECC_CORRECTION); |
| 217 | } |
| 218 | |
| 219 | /* clear status */ |
| 220 | writew(0xffff, INTR_STATUS(0)); |
| 221 | |
| 222 | writel(TRANSFER_MAIN_REG__FLAG, TRANSFER_SPARE_REG); |
| 223 | |
| 224 | /* enable DMA */ |
| 225 | writel(DMA_ENABLE__FLAG, DMA_ENABLE); |
| 226 | |
| 227 | /* setup transfer type and # of pages -FOR DMA */ |
| 228 | index_addr(mode | page, 0x2001); //mode10(0x08000000) | bank0(0) | page, |
| 229 | // 0x2000 | DENALI_READ(0) | 1 |
| 230 | |
| 231 | /* set memory high address bits 23:8 -FOR DMA */ |
| 232 | index_addr(mode | ((uint16_t)(buf >> 16) << 8), 0x2200); |
| 233 | |
| 234 | /* set memory low address bits 23:8 -FOR DMA */ |
| 235 | index_addr(mode | ((uint16_t)buf << 8), 0x2300); |
| 236 | |
| 237 | /* interrupt when complete, burst len = 64 bytes -FOR DMA*/ |
| 238 | index_addr( mode | 0x14000, 0x2400); //zhouqi not interrupt 0X40 |
| 239 | |
| 240 | /* wait_for_ready */ |
| 241 | status = wait_for_ready (INTR_STATUS__DMA_CMD_COMP | INTR_STATUS__ECC_ERR); |
| 242 | if (status & INTR_STATUS__ECC_ERR ) |
| 243 | { |
| 244 | printf("[EE]\n"); /* [read_page]: ECC ERROR */ |
| 245 | /* 0. clear status */ |
| 246 | clear_intr(); |
| 247 | return -1; |
| 248 | } |
| 249 | |
| 250 | |
| 251 | if (status & INTR_STATUS__TIME_OUT) |
| 252 | { |
| 253 | printf("TO\n"); /* [read_page]: TIME OUT */ |
| 254 | /* clear status */ |
| 255 | clear_intr(); |
| 256 | return -1; |
| 257 | } |
| 258 | |
| 259 | writel(ecc_status, ECC_CORRECTION); |
| 260 | |
| 261 | /* disable DMA */ |
| 262 | writel(DMA_DISABLE__FLAG, DMA_ENABLE); |
| 263 | |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | |
| 268 | /******************************************************************************* |
| 269 | * from: must page align |
| 270 | len: must page align |
| 271 | */ |
| 272 | /******************************************************************************* |
| 273 | * Function: |
| 274 | * Description: |
| 275 | * Parameters: |
| 276 | * Input: |
| 277 | * |
| 278 | * Output: |
| 279 | * |
| 280 | * Returns: |
| 281 | * |
| 282 | * |
| 283 | * Others: |
| 284 | ********************************************************************************/ |
| 285 | int32_t nand_read(uint32_t from, uint32_t len, uint32_t to) |
| 286 | { |
| 287 | uint32_t offset = from; |
| 288 | uint32_t left_to_read = len; |
| 289 | uint32_t p_to = to; |
| 290 | int32_t ret = 0; |
| 291 | int32_t page_size = (nand_info->page_size); |
| 292 | |
| 293 | if((offset & (page_size - 1)) || (len & (page_size - 1))) |
| 294 | { |
| 295 | printf("param err.\n"); |
| 296 | return -1; |
| 297 | } |
| 298 | |
| 299 | while(left_to_read > 0) |
| 300 | { |
| 301 | ret = read_page(p_to, offset); |
| 302 | if(ret != 0) |
| 303 | { |
| 304 | return -1; |
| 305 | } |
| 306 | |
| 307 | left_to_read -= page_size; |
| 308 | offset += page_size; |
| 309 | p_to += page_size; |
| 310 | } |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | |
| 315 | /******************************************************************************* |
| 316 | * Function: |
| 317 | * Description: |
| 318 | * Parameters: |
| 319 | * Input: |
| 320 | * |
| 321 | * Output: |
| 322 | * |
| 323 | * Returns: |
| 324 | * |
| 325 | * |
| 326 | * Others: |
| 327 | ********************************************************************************/ |
| 328 | int32_t read_data(uint32_t from, uint32_t len, uint32_t to) |
| 329 | { |
| 330 | uint32_t offset = from; |
| 331 | uint32_t left_to_read = len; |
| 332 | uint32_t p_to = to; |
| 333 | int32_t ret = 0; |
| 334 | int32_t block_size = (nand_info->block_size); |
| 335 | |
| 336 | while( left_to_read > 0 ) |
| 337 | { |
| 338 | uint32_t block_offset = offset & (block_size - 1); |
| 339 | uint32_t read_length; |
| 340 | |
| 341 | if( nand_block_isbad(offset) ) |
| 342 | { |
| 343 | offset += block_size; |
| 344 | continue; |
| 345 | } |
| 346 | |
| 347 | if (left_to_read < (block_size - block_offset)) |
| 348 | read_length = left_to_read; |
| 349 | else |
| 350 | read_length = block_size - block_offset; |
| 351 | |
| 352 | ret = nand_read(offset, read_length, p_to); |
| 353 | if(ret != 0) |
| 354 | { |
| 355 | return -1; |
| 356 | } |
| 357 | |
| 358 | left_to_read -= read_length; |
| 359 | offset += read_length; |
| 360 | p_to += read_length; |
| 361 | } |
| 362 | |
| 363 | return 0; |
| 364 | } |
| 365 | |
| 366 | |
| 367 | |
| 368 | /******************************************************************************* |
| 369 | * Function: |
| 370 | * Description: |
| 371 | * Parameters: |
| 372 | * Input: |
| 373 | * |
| 374 | * Output: |
| 375 | * |
| 376 | * Returns: |
| 377 | * |
| 378 | * |
| 379 | * Others: |
| 380 | ********************************************************************************/ |
| 381 | int32_t nand_read_id (void) |
| 382 | { |
| 383 | uint32_t id[5]; |
| 384 | uint32_t i = 0; |
| 385 | uint32_t addr = (uint32_t)MODE_11; /* | BANK(0) */ |
| 386 | struct nand_flash_device_para *nand = &nand_flash_para[0]; |
| 387 | |
| 388 | index_addr(addr | 0, 0x90); |
| 389 | index_addr(addr | 1, 0); |
| 390 | for (i = 0; i < 5; i++) |
| 391 | { |
| 392 | index_addr_read_data(addr | 2, &id[i]); |
| 393 | } |
| 394 | |
| 395 | i = 0; |
| 396 | while( nand->manuf_id != 0 ) |
| 397 | { |
| 398 | if( ((uint8_t)id[0] == nand->manuf_id) && |
| 399 | ((uint8_t)id[1] == nand->device_id) && |
| 400 | ((uint8_t)id[2] == nand->res_id)) |
| 401 | { |
| 402 | nand_info = nand; |
| 403 | |
| 404 | writel(nand_info->bus_num, DEVICE_WIDTH); |
| 405 | writel(nand_info->page_size, DEVICE_MAIN_AREA_SIZE); |
| 406 | writel(nand_info->page_size, LOGICAL_PAGE_DATA_SIZE); |
| 407 | writel(nand_info->oob_size, DEVICE_SPARE_AREA_SIZE); |
| 408 | writel(nand_info->ecc_strength, ECC_CORRECTION); |
| 409 | return 0; |
| 410 | }; |
| 411 | nand++; |
| 412 | i++; |
| 413 | } |
| 414 | |
| 415 | return 1; |
| 416 | } |
| 417 | |
| 418 | |
| 419 | /******************************************************************************* |
| 420 | * Function: |
| 421 | * Description: |
| 422 | * Parameters: |
| 423 | * Input: |
| 424 | * |
| 425 | * Output: |
| 426 | * |
| 427 | * Returns: |
| 428 | * |
| 429 | * |
| 430 | * Others: |
| 431 | ********************************************************************************/ |
| 432 | int32_t nand_init (void) |
| 433 | { |
| 434 | int32_t ret = 0; |
| 435 | writel(ECC_DISABLE__FLAG, ECC_ENABLE); /* ecc_enable */ |
| 436 | writel(2, SPARE_AREA_SKIP_BYTES); |
| 437 | |
| 438 | ret = nand_read_id(); |
| 439 | if( ret != 0 ) |
| 440 | return -1; |
| 441 | |
| 442 | flash.flash_type = NAND_BOOT; |
| 443 | flash.manuf_id = nand_info->manuf_id; |
| 444 | flash.device_id = nand_info->device_id; |
| 445 | flash.page_size = nand_info->page_size; |
| 446 | flash.page_size_shift = nand_info->page_size_shift; |
| 447 | flash.oob_size = nand_info->oob_size; |
| 448 | flash.block_size = nand_info->block_size; |
| 449 | flash.block_size_shift = nand_info->block_size_shift; |
| 450 | flash.block_num = nand_info->block_num; |
| 451 | flash.read = read_data; |
| 452 | flash.read_oob = nand_read_oob; |
| 453 | |
| 454 | return 0; |
| 455 | |
| 456 | } |
| 457 | |
| 458 | |
| 459 | /* |
| 460 | ****************************************************************************** |
| 461 | * Function: |
| 462 | * Description: |
| 463 | * Parameters: |
| 464 | * Input: |
| 465 | * Output: |
| 466 | * Returns: |
| 467 | * Others: |
| 468 | ******************************************************************************* |
| 469 | */ |
| 470 | int board_flash_init(void) |
| 471 | { |
| 472 | int ret = 0; |
| 473 | char boot_mode = 0; |
| 474 | |
| 475 | boot_mode = get_boot_mode(); |
| 476 | if(boot_mode != NAND_BOOT) |
| 477 | { |
| 478 | printf("not nand flash.\n"); |
| 479 | return -1; |
| 480 | } |
| 481 | |
| 482 | writel(CFG_START_MODE_NAND, CFG_BOOT_MODE_START_MODE_FOR_UBOOT); |
| 483 | ret = nand_init(); |
| 484 | if(ret != 0) |
| 485 | { |
| 486 | printf("nand init err.\n"); |
| 487 | return -1; |
| 488 | } |
| 489 | printf("nand init ok.\n"); |
| 490 | |
| 491 | nand_creat_bbt(); |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | |