| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame^] | 1 | /* |
| 2 | *********************************************************** |
| 3 | */ |
| 4 | |
| 5 | #include <common.h> |
| 6 | #include <asm/io.h> |
| 7 | #include <sdio.h> |
| 8 | |
| 9 | #include "efuse.h" |
| 10 | |
| 11 | |
| 12 | |
| 13 | void efuse_init(void) |
| 14 | { |
| 15 | //start read efuse all 256bit |
| 16 | while((REG32(SYS_EFUSE_BASE + 0x4) & 1) == 1);// bit0=1 ctl is busy |
| 17 | REG32(SYS_EFUSE_BASE + 0x4) = 1; |
| 18 | while((REG32(SYS_EFUSE_BASE + 0x14) & 2) == 0);//bit1=0 read not over |
| 19 | } |
| 20 | |
| 21 | int get_ddr_flag(void) |
| 22 | { |
| 23 | efuse_struct *psEfuseInfo = NULL; |
| 24 | int ddr_flag = 0; |
| 25 | |
| 26 | |
| 27 | psEfuseInfo = (efuse_struct*)EFUSE_RAM_BASE; |
| 28 | |
| 29 | /* get chip flag */ |
| 30 | if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_WINBD_256M_DDR) |
| 31 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_WINBD_256M_DDR) |
| 32 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_UNILC_256M_DDR) |
| 33 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_UNILC_256M_DDR) |
| 34 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_APM_256M_DDR) |
| 35 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_APM_256M_DDR)) |
| 36 | { |
| 37 | ddr_flag = CHIP_DDR_32M; |
| 38 | } |
| 39 | else if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_UNILC_512M_DDR) |
| 40 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_APM_512M_DDR) |
| 41 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_ESMT_512M_DDR) |
| 42 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_UNILC_512M_DDR) |
| 43 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_AZW_UNILC_512M_DDR) |
| 44 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_APM_512M_DDR) |
| 45 | ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_ESMT_512M_DDR)) |
| 46 | { |
| 47 | ddr_flag = CHIP_DDR_64M; |
| 48 | } |
| 49 | else if((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSC_GW_NYC_2G_DDR) |
| 50 | { |
| 51 | ddr_flag = CHIP_DDR_256M; |
| 52 | } |
| 53 | else |
| 54 | { |
| 55 | ddr_flag = CHIP_DDR_128M; |
| 56 | } |
| 57 | |
| 58 | return ddr_flag; |
| 59 | } |
| 60 | |
| 61 | int get_secure_verify_status(void) |
| 62 | { |
| 63 | u32 uiLen; |
| 64 | efuse_struct *psEfuseInfo = NULL; |
| 65 | |
| 66 | if((REG32(EFUSE_BYPASS) & 1) == 1) //Secure Verify. 1->Disable, 0->Enable. |
| 67 | { |
| 68 | return SECURE_VERIFY_DISABLE; |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * 0. Èç¹ûsecure flag²»µÈÓÚ0xFF£¬Í˳ö°²È«boot¡£ |
| 73 | */ |
| 74 | psEfuseInfo = (efuse_struct*)EFUSE_RAM_BASE; |
| 75 | if((psEfuseInfo->secure_flag & 0xFF) != 0xFF) |
| 76 | { |
| 77 | return SECURE_VERIFY_DISABLE; |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * 1.´ÓefuseÖжÁ³öpuk_hash[127:0], ÅжÏÈç¹ûÈ«²¿Îª0Í˳ö°²È«boot¡£ |
| 82 | */ |
| 83 | for(uiLen = 0; uiLen < 4; uiLen++) |
| 84 | { |
| 85 | if(psEfuseInfo->puk_hash[uiLen] != 0) |
| 86 | { |
| 87 | break; |
| 88 | } |
| 89 | if(uiLen == 3) |
| 90 | { |
| 91 | return SECURE_VERIFY_DISABLE; |
| 92 | } |
| 93 | } |
| 94 | printf("SecureVerify->enable.\n"); |
| 95 | |
| 96 | return SECURE_VERIFY_ENABLE; |
| 97 | } |
| 98 | |
| 99 | |
| 100 | |