| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame^] | 1 | /* |
| 2 | *********************************************************** |
| 3 | */ |
| 4 | |
| 5 | #ifndef __EFUSE_H__ |
| 6 | #define __EFUSE_H__ |
| 7 | |
| 8 | |
| 9 | /* -------- efuse ¼Ä´æÆ÷-------------*/ |
| 10 | #define SYS_EFUSE_BASE 0x0121b000 |
| 11 | #define EFUSE_RAM_BASE (SYS_EFUSE_BASE+0x40) |
| 12 | |
| 13 | #define SYS_CTRL_BASE 0x00140000 |
| 14 | #define EFUSE_BYPASS (SYS_CTRL_BASE+0x140) |
| 15 | |
| 16 | |
| 17 | #define CHIP_DDR_32M 0 |
| 18 | #define CHIP_DDR_64M 1 |
| 19 | #define CHIP_DDR_128M 2 |
| 20 | #define CHIP_DDR_256M 3 |
| 21 | |
| 22 | |
| 23 | #define SECURE_VERIFY_ENABLE 0 |
| 24 | #define SECURE_VERIFY_DISABLE 1 |
| 25 | |
| 26 | #define ZX297520V3_GW_NYB_1G_DDR 0xF86302 |
| 27 | #define ZX297520V3_GW_NYC_1G_DDR 0xF86303 |
| 28 | #define ZX297520V3ECO_GW_UNILC_512M_DDR 0xF86304 |
| 29 | #define ZX297520V3ECO_GW_APM_512M_DDR 0xF86305 |
| 30 | #define ZX297520V3ECO_GW_NYB_1G_DDR 0xF86306 |
| 31 | #define ZX297520V3ECO_GW_NYC_1G_DDR 0xF86307 |
| 32 | #define ZX297520V3ECO_GW_WINBD_256M_DDR 0xF86308 |
| 33 | #define ZX297520V3ECO_GW_UNILC_256M_DDR 0xF86309 |
| 34 | #define ZX297520V3ECO_GW_APM_256M_DDR 0xF8630a |
| 35 | #define ZX297520V3ECO_GW_ESMT_512M_DDR 0xF8630b |
| 36 | #define ZX297520V3SC_GW_NYC_1G_DDR 0xF8630c |
| 37 | #define ZX297520V3ECOSCC_GW_UNILC_1G_DDR 0xF8630d |
| 38 | #define ZX297520V3ECOSCC_GW_NYC_1G_DDR 0xF8630e |
| 39 | #define ZX297520V3ECOSC_GW_NYC_1G_DDR 0xF8630f |
| 40 | #define ZX297520V3ECOSC_GW_UNILC_1G_DDR 0xF86310 |
| 41 | #define ZX297520V3ECOSC_GW_NYC_2G_DDR 0xF86311 |
| 42 | |
| 43 | #define ZX297520V3_ZW_NYB_1G_DDR 0x1E871E |
| 44 | #define ZX297520V3_ZW_NYC_1G_DDR 0x1E871F |
| 45 | #define ZX297520V3ECO_ZW_UNILC_512M_DDR 0x1E8720 |
| 46 | #define ZX297520V3ECO_ZW_APM_512M_DDR 0x1E8721 |
| 47 | #define ZX297520V3ECO_ZW_NYB_1G_DDR 0x1E8722 |
| 48 | #define ZX297520V3ECO_ZW_NYC_1G_DDR 0x1E8723 |
| 49 | #define ZX297520V3ECO_ZW_WINBD_256M_DDR 0x1E8724 |
| 50 | #define ZX297520V3ECO_ZW_UNILC_256M_DDR 0x1E8725 |
| 51 | #define ZX297520V3ECO_ZW_APM_256M_DDR 0x1E8726 |
| 52 | #define ZX297520V3ECO_ZW_ESMT_512M_DDR 0x1E8727 |
| 53 | |
| 54 | #define ZX297520V3ECO_AZW_UNILC_512M_DDR 0x1F9801 |
| 55 | |
| 56 | |
| 57 | /*ΪÁË¿´ÆðÀ´·½±ã, hashºÍkeyÔÚbufferµÄ´æ·Å˳ÐòΪµÍµØÖ··Å¸ßλÊý¾Ý*/ |
| 58 | // ¶¨Òå½á¹¹ |
| 59 | typedef volatile struct |
| 60 | { |
| 61 | u32 secure_flag; |
| 62 | u32 puk_hash[4]; |
| 63 | } efuse_struct; |
| 64 | |
| 65 | |
| 66 | |
| 67 | void efuse_init(void); |
| 68 | int get_ddr_flag(void); |
| 69 | int get_secure_verify_status(void); |
| 70 | |
| 71 | |
| 72 | #endif /* __EFUSE_H__ */ |