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192.168.1.100 / T106_DC / 9ed821d7e5d875a3395740a9cc2545671fa429b7 / . / cp / ps / driver / inc / misc / drvs_dma.h
blob: 93d089281b0f9e1e8ba76a155b863a5b5f5eb1b5 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame^]1/*******************************************************************************
2 * Copyright (C) 2014, ZTE Corporation.
3 *
4 * File Name: drvs_dma.h
5 * File Mark:
6 * Description:
7 * Others:
8 * Version: v0.1
9 * Author: limeifeng
10 * Date: 2014-03-03
11 * History 1:
12 * Date:
13 * Version:
14 * Author:
15 * Modification:
16 * History 2:
17 ********************************************************************************/
18
19#ifndef _DRVS_DMA_H
20#define _DRVS_DMA_H
21/****************************************************************************
22* Include files
23****************************************************************************/
24
25/****************************************************************************
26* Macros
27****************************************************************************/
28#if defined (_CHIP_ZX297520V3)
29#define DMAC0_CH_NUM 23 /*dmac0¿ØÖÆÆ÷µÄͨµÀÊý*/
30#elif defined (_CHIP_ZX297520V2)
31#define DMAC0_CH_NUM 19 /*dmac0¿ØÖÆÆ÷µÄͨµÀÊý*/
32#endif
33
34//#define DMAC1_CH_NUM 9 /*dmac1¿ØÖÆÆ÷µÄͨµÀÊý*/
35#define DMAC_CH_MAX DMAC0_CH_NUM
36/****************************************************************************
37* Type
38****************************************************************************/
39typedef enum _T_ZDrv_DmaId
40{
41 DMAC0=0,
42 DMAC_NUM
43}T_ZDrv_DmaId;
44
45/*ÊÇ·ñΪ×èÈû·½Ê½´«Êä*/
46typedef enum _T_ZDrvDma_IsBlock
47{
48 DMA_NOT_BLOCK=0,
49 DMA_BLOCK=1,
50}T_ZDrvDma_IsBlock;
51
52#if defined (_CHIP_ZX297520V3)
53typedef enum
54{
55/*DMAC0ͨµÀºÅ¶¨Òå*/
56 DMAC0_CH_UART0_TX = 0,
57 DMAC0_CH_UART0_RX,
58 DMAC0_CH_UART1_TX,
59 DMAC0_CH_UART1_RX, /* or DMAC0_CH_HASH_RX*/
60 DMAC0_CH_SSP0_TX,
61 DMAC0_CH_SSP0_RX,
62 DMAC0_CH_GPRS0,
63 DMAC0_CH_GPRS1,
64 DMAC0_CH_USIM,
65 DMAC0_CH_I2S0_TX, /*or DMAC0_CH_TDM_TX*/
66 DMAC0_CH_I2S0_RX0, /*or DMAC0_CH_TDM_RX*/
67 DMAC0_CH_I2S1_TX, /*or DMAC0_CH_TDM_TX*/
68 DMAC0_CH_I2S1_RX0, /*or DMAC0_CH_TDM_RX*/
69 DMAC0_CH_SPIFC0_TX,
70 DMAC0_CH_SPIFC0_RX,
71 DMAC0_CH_SSP1_TX,
72 DMAC0_CH_SSP1_RX,
73 DMAC0_CH_UART2_TX, /*or DMAC0_CH_I2S0_RX1*/
74 DMAC0_CH_UART2_RX, /*or DMAC0_CH_I2S1_RX1*/
75 DMAC0_CH_EMBMS,
76 DMAC0_CH_USIM1,
77 DMAC0_CH_M2M_TX,
78 DMAC0_CH_M2M_RX,
79 DMAC0_CH_MEMORY, /*ÓÃÓÚÉêÇëDMAC0ÉϵĿÕÏÐͨµÀ*/
80}T_Dma_Peripheral_Id;
81#elif defined (_CHIP_ZX297520V2)
82typedef enum
83{
84/*DMAC0ͨµÀºÅ¶¨Òå*/
85 DMAC0_CH_UART0_TX = 0,
86 DMAC0_CH_UART0_RX,
87 DMAC0_CH_UART1_TX,
88 DMAC0_CH_UART1_RX,
89 DMAC0_CH_SSP0_TX,
90 DMAC0_CH_SSP0_RX,
91 DMAC0_CH_GPRS0,
92 DMAC0_CH_GPRS1,
93 DMAC0_CH_USIM,
94 DMAC0_CH_I2S0_TX,
95 DMAC0_CH_I2S0_RX,
96 DMAC0_CH_I2S1_TX,
97 DMAC0_CH_I2S1_RX,
98 DMAC0_CH_SPIFC0_TX,
99 DMAC0_CH_SPIFC0_RX,
100 DMAC0_CH_SSP1_TX,
101 DMAC0_CH_SSP1_RX,
102 DMAC0_CH_UART2_TX,
103 DMAC0_CH_UART2_RX,
104 DMAC0_CH_MEMORY, /*ÓÃÓÚÉêÇëDMAC0ÉϵĿÕÏÐͨµÀ*/
105}T_Dma_Peripheral_Id;
106#endif
107
108/*----DMA Transfer Control Set------*/
109typedef enum
110{
111 DMA_DISABLE = 0, /*disable DMA transmission*/
112 DMA_ENABLE = 1, /*enable DMA transmission*/
113
114 DMA_ENABLE_ALL
115}T_DMA_ENABLE;
116
117
118/*----DMA Request mode set------*/
119typedef enum
120{
121 DMA_PERIPHERAL_REQ = 0, /*peripheral request*/
122 DMA_SOFT_REQ = 1, /*soft request for single transfer*/
123 DMA_REQ_MOD_ALL
124}T_DMA_REQ_MOD;
125
126/*----DMA Source or Dest address mode------*/
127typedef enum
128{
129 DMA_ADDRMOD_RAM = 0, /*RAM mode, address will increase when transmission*/
130 DMA_ADDRMOD_FIFO = 1, /*FIFO mode, address will not change during transmission*/
131
132 DMA_ADDRMOD_ALL
133}T_DMA_ADDR_MOD;
134
135/*----DMA IRQ Mode------*/
136typedef enum
137{
138 DMA_ALL_IRQ_DISABLE = 0, /*½ûÄÜËùÓÐÖжÏ*/
139 DMA_TC_IRQ_ENABLE = 1, /*Íê³ÉÖжÏʹÄÜ*/
140 DMA_ERR_IRQ_ENABLE =2, /*´«ÊäºÍÅäÖôíÎóÖжÏʹÄÜ*/
141 DMA_ALL_IRQ_ENABLE = 3, /*ʹÄÜËùÓÐÖжÏ*/
142
143 DMA_IRQMOD_ALL
144}T_DMA_IRQ_MOD;
145
146/*----DMA Burst Size------*/
147typedef enum
148{
149 DMA_BURST_SIZE_8BIT = 0,
150 DMA_BURST_SIZE_16BIT = 1,
151 DMA_BURST_SIZE_32BIT = 2,
152 DMA_BURST_SIZE_64BIT = 3,
153 DMA_BURST_SIZE_128BIT = 4,
154 DMA_BURST_SIZE_ALL
155}
156T_DMA_BURST_SIZE;
157
158
159/*----DMA Burst Len------*/
160typedef enum
161{
162 DMA_BURST_LEN_1 = 0, /* 1 tranfer in each burst*/
163 DMA_BURST_LEN_2 , /* 2 tranfers in each burst*/
164 DMA_BURST_LEN_3 , /* 3 tranfers in each burst*/
165 DMA_BURST_LEN_4 , /* 4 tranfers in each burst*/
166 DMA_BURST_LEN_5 , /* 5 tranfers in each burst*/
167 DMA_BURST_LEN_6 , /* 6 tranfers in each burst*/
168 DMA_BURST_LEN_7 , /* 7 tranfers in each burst*/
169 DMA_BURST_LEN_8 , /* 8 tranfers in each burst*/
170 DMA_BURST_LEN_9 , /* 9 tranfers in each burst*/
171 DMA_BURST_LEN_10, /* 10 tranfers in each burst*/
172 DMA_BURST_LEN_11 , /* 11 tranfers in each burst*/
173 DMA_BURST_LEN_12 , /* 12 tranfers in each burst*/
174 DMA_BURST_LEN_13 , /* 13 tranfers in each burst*/
175 DMA_BURST_LEN_14 , /* 14 tranfers in each burst*/
176 DMA_BURST_LEN_15 , /* 15 tranfers in each burst*/
177 DMA_BURST_LEN_16 , /* 16 tranfers in each burst*/
178
179 DMA_BURST_LEN_ALL
180}
181T_DMA_BURST_LEN;
182
183/*----DMA Int Select------*/
184typedef enum
185{
186 DMA_INT_TO_PS,
187 DMA_INT_TO_PHY,
188 DMA_INT_TO_M0,
189 DMA_INT_SEL_ALL
190}T_DMA_INT_SEL;
191typedef enum
192{
193 DMA_INT_ERR, /*transmission error*/
194 DMA_INT_END, /*transmission done*/
195
196 MAX_DMA_INT
197} T_ZDrvDma_IntStatus; /*T_HalDma_IntStatus;*/
198
199/*----DMA Control reg para------*/
200typedef struct _T_DMA_CONTROL
201{
202 T_DMA_REQ_MOD BurstReqMod; /*DMA Request mode*/
203 T_DMA_ADDR_MOD SrcMod; /*DMA Source address mode*/
204 T_DMA_ADDR_MOD DestMod; /*DMA Destination address mode*/
205 T_DMA_IRQ_MOD IrqMod;
206 T_DMA_BURST_SIZE SrcBurstSize; /*DMA burst size£¬ÍâÉèÄÚ´æ¼ä´«ÊäʱҪÂú×ãCountÊÇ
207 max(SrcBurstSize,DestBurstSize)µÄÕûÊý±¶*/
208 T_DMA_BURST_LEN SrcBurstLen;
209 T_DMA_BURST_SIZE DestBurstSize; /*DMA burst size£¬ÍâÉèÄÚ´æ¼ä´«ÊäʱҪÂú×ãCountÊÇ
210 max(SrcBurstSize,DestBurstSize)µÄÕûÊý±¶*/
211 T_DMA_INT_SEL IntSel; /* select witch core will deal with the dma int*/
212} T_DMA_CONTROL;
213
214/*----DMA channel para ------*/
215typedef struct
216{
217 UINT32 SrcAddr; /*DMA source address*/
218 UINT32 DestAddr; /*DMA Destination address*/
219 UINT16 Count; /*һά´«Êäʱ´«ÊäµÄÊý¾Ý×Ü×Ö½ÚÊý*/
220 UINT16 YCount; /*һά´«ÊäʱΪ0*/
221 UINT16 ZCount; /*һά´«ÊäʱΪ0*/
222 UINT16 SrcYstep; /*һά´«ÊäʱΪ0*/
223 UINT16 SrcZstep; /*һά´«ÊäʱΪ0*/
224 UINT16 DestYstep; /*һά´«ÊäʱΪ0*/
225 UINT16 DestZstep; /*һά´«ÊäʱΪ0*/
226 UINT32 LLI; /*Á´±íµØÖ·£¬²»ÊÇÁ´±í´«Êäʱһ¶¨ÒªÉèΪ0*/
227 T_DMA_CONTROL CONTROL;
228}T_ZDrvDma_ChannelDef;
229
230typedef struct
231{
232 UINT32 SrcAddr; /*DMA source address*/
233 UINT32 DestAddr; /*DMA Destination address*/
234 UINT16 Count; /*һά´«Êäʱ´«ÊäµÄÊý¾Ý×Ü×Ö½ÚÊý*/
235}T_ZDrvDma_EmbmsChannelDef;
236
237/*----DMA Group------*/
238typedef enum
239{
240 DMA_GROUP_1234_5678 = 0,
241 DMA_GROUP_2341_5678 ,
242 DMA_GROUP_3412_5678 ,
243 DMA_GROUP_4123_5678 ,
244 DMA_GROUP_1234_6785 ,
245 DMA_GROUP_2341_6785 ,
246 DMA_GROUP_3412_6785 ,
247 DMA_GROUP_4123_6785 ,
248 DMA_GROUP_1234_7856 ,
249 DMA_GROUP_2341_7856 ,
250 DMA_GROUP_3412_7856 ,
251 DMA_GROUP_4123_7856 ,
252 DMA_GROUP_1234_8567 ,
253 DMA_GROUP_2341_8567 ,
254 DMA_GROUP_3412_8567 ,
255 DMA_GROUP_4123_8567 ,
256 DMA_GROUP_5678_1234 ,
257 DMA_GROUP_5678_2341 ,
258 DMA_GROUP_5678_3412 ,
259 DMA_GROUP_5678_4123 ,
260 DMA_GROUP_6785_1234 ,
261 DMA_GROUP_6785_2341 ,
262 DMA_GROUP_6785_3412 ,
263 DMA_GROUP_6785_4123 ,
264 DMA_GROUP_7856_1234 ,
265 DMA_GROUP_7856_2341 ,
266 DMA_GROUP_7856_3412 ,
267 DMA_GROUP_7856_4123 ,
268 DMA_GROUP_8567_1234 ,
269 DMA_GROUP_8567_2341 ,
270 DMA_GROUP_8567_3412 ,
271 DMA_GROUP_8567_4123 ,
272 DMA_GROUP_ALL
273}
274T_DMA_GROUP_ORDER;
275
276/*----DMA Group Arbi Mode------*/
277typedef enum
278{
279 DMA_MODE_RR = 0, /*ÂÖѯ·½Ê½,DMA·Ö×éÎÞЧ*/
280 DMA_MODE_8PRI, /*ÿËĸöͨµÀÒ»×飬°´ÇëÇóÏß´ÓµÍλµ½¸ßλ·Ö³É8×é
281 Àý:1234_5678,1>2>3>4>5>6>7>8*/
282 DMA_MODE_4PRI, /*Àý:1234_5678,1>2>3>4,5>6>7>8,1234Óë5678×é¼äͬÓÅÏȼ¶*/
283 DMA_MODE_2PRI, /*Àý:1234_5678,1234>5678*/
284 DMA_MODE_ALL
285}
286T_DMA_GROUP_MODE;
287
288/*----T_DMA_STATUS------*/
289typedef enum
290{
291 DMA_TRANSFER_DONE = 0,
292 DMA_CFG_ERROR,
293 DMA_NOT_DONE,
294
295 DMA_STATUS_ALL
296}
297T_DMA_STATUS;
298
299typedef VOID (*zDrvDma_CallbackFunc)(T_ZDrvDma_IntStatus);
300
301/****************************************************************************
302* Global Function Prototypes
303****************************************************************************/
304/*******************************************************************************
305* Function: zDrvDma_SetPriority
306* Description:
307* Parameters:dmacID :DMAC0¡¢DMAC1
308* groupOrder:ÓÅÏȼ¶·Ö×é˳Ðò1 2 3 4 5 6 7 8 ÿËĸöͨµÀÒ»×飬°´ÇëÇóÏߴӵ͵½¸ß
309 ·ÖΪ8×é¡£
310 groupMode:ÓÅÏȼ¶·Ö×éģʽ£¬ DMA_MODE_RR : ÂÖѯ·½Ê½£¬²»·Ö×飬ÎÞÓÅÏȼ¶²î±ð
311 DMA_MODE_8PRI:ÿËĸöͨµÀÒ»×飬°´ÇëÇóÏß´ÓµÍλµ½¸ßλ·Ö³É8×é
312 Àý:1234_5678,1>2>3>4>5>6>7>8
313 DMA_MODE_4PRI: Àý:1234_5678,1>2>3>4,5>6>7>8,1234Óë5678×é¼äͬÓÅÏȼ¶
314 DMA_MODE_2PRI: Àý:1234_5678,1234>5678
315* Input:
316*
317* Output:
318*
319* Returns:
320*
321* Others:
322********************************************************************************/
323SINT32 zDrvDma_SetPriority(T_ZDrv_DmaId dmacID, T_DMA_GROUP_ORDER groupOrder, T_DMA_GROUP_MODE groupMode);
324
325/*******************************************************************************
326* Function: zDrvDma_Initiate
327* Description: reset dma controller,the reset line will hold 2ms
328* Parameters:
329* Input:
330*
331* Output:
332*
333* Returns:
334*
335* Others:
336********************************************************************************/
337SINT32 zDrvDma_Initiate(VOID);
338
339
340/*******************************************************************************
341* Function: zDrvDma_AllocChannel
342* Description:
343 for users, they don't konw with channel chould be used to do the transfer.
344 so they should first call this function to get a free channel id;
345
346 afer dma transfer is over , zDrvDma_DeAllocChannel should be called to release the
347 channedl resoure
348* Parameters:
349* Input:
350* peripheralID: peripheral request line defined by structure T_Dma_Peripheral_Id
351
352* Output:
353*
354* Returns:
355*
356* Others:
357********************************************************************************/
358SINT32 zDrvDma_AllocChannel(T_Dma_Peripheral_Id peripheralID);
359
360
361/**************************************************************************
362* Function: zDrvDma_ConfigChannel
363* Description:
364* Parameters:
365* Input:
366* channelID: the return value from zDrvDma_AllocChannel
367* tChanPar:parameter of channel
368* CallBack:when dma transfer is over, isr will call cbk
369
370* Output: None
371* Returns:
372* T_ZDrvDma_Ret
373* Others:
374* 1. ÔÚÔ´»òÄ¿µÄµØÖ·Ö»ÒªÓÐÒ»¶ËÓй̶¨µØÖ·£¬¼´T_DMA_ADDR_MODΪ
375* DMA_ADDRMOD_FIFOʱ£¬tChanPar µÄCount ±ØÐëÊǽϴóburstsize
376* µÄÕûÊý±¶!!!
377* 2.ÔÚ BurstReqMod = DMA_PERIPHERAL_REQʱ£¬ÐèÒªÌرð×¢Òâ:Èç¹û¶ÔÓ¦ÍâÉèÖ»ÄܲúÉú
378* burstÇëÇó¶øûÓÐsingleÇëÇóÊä³ö¹¦ÄÜ£¬ÄÇôtChanPar µÄCount ±ØÐëÊÇburstsize*burstlen
379* µÄÕûÊý±¶!!!
380* 3.SrcAddrºÍDestAddrÒªÇóΪburstsizeµÄÕûÊý±¶£¬¼´ÒÔburstsizeΪµ¥Î»µØÖ·¶ÔÆë¡£
381* 4.tChanPar µÄ²ÎÊýCount µÄȡֵҪСÓÚµÈÓÚ64K-1×Ö½Ú£¬Countµ¥Î»Îª×Ö½Ú!!
382**************************************************************************/
383SINT32 zDrvDma_ConfigChannel(UINT32 channelID,T_ZDrvDma_ChannelDef tChanPar);
384
385/**************************************************************************
386* Function: zDrvDma_StartChannel
387* Description:
388* Parameters:
389* Input:
390* channelID: the return value from zDrvDma_AllocChannel
391* CallBack:if not null, when dma transfer is over, 'callback' will be called in the dma isr
392 isBlock: if set true, the process will be suspended until the dma transfer is done
393* Output: None
394* Returns:
395* T_ZDrvDma_Ret
396* Others: None
397**************************************************************************/
398SINT32 zDrvDma_StartChannel(UINT32 channelID, zDrvDma_CallbackFunc CallBack, T_ZDrvDma_IsBlock isBlock);
399
400
401/*******************************************************************************
402* Function: zDrvDma_DeAllocChannel
403* Description:ÊÍ·ÅÒѾ­ÉêÇë³É¹¦µÄDMA ͨµÀ£¬ÈçûÓÐÉêÇë³É¹¦Ôò²»ÄÜÊÍ·Å
404* Ò»°ãÔÚ¸ÃDMAͨµÀÅäÖ÷µ»Ø´íÎóÐÅÏ¢»òʹÓÃÕß²»ÔÙʹÓøÃDMAͨµÀ
405* ʱµ÷Óô˺¯Êý¡£
406* Parameters:
407* Input:
408*
409* Output:
410*
411* Returns:
412*
413* Others:ÈôΪ×èÈû´«Êä(zDrvDma_StartChannelµÄisBlock²ÎÊýΪTRUE)
414* ÏàͬͨµÀµÄzDrvDma_DeAllocChannel±ØÐëÔÚºÍzDrvDma_StartChannelͬһ¸öÏ̱߳»µ÷ÓÃ
415* ·ñÔò¿ÉÄܻᵼÖµ÷ÓÃzDrvDma_StartChannelµÄÏß³ÌÒòdmaδÀ´Íê³ÉÖж϶øÓÀÔ¶ÏÝËÀ
416********************************************************************************/
417SINT32 zDrvDma_DeAllocChannel(UINT32 channelID);
418/**************************************************************************
419* Function: zDrvDma_GetTransferNumber
420* Description:»ñÈ¡ucChannel ´ú±íµÄͨµÀµÄÊý¾ÝµÄ´«ÊäÊ£Óà´óС
421* Parameters:
422* Input: zDrvDma_AllocChannel µÄ·µ»ØÖµ:¸ß16λ:dma¿ØÖÆÆ÷µÍ16λ:ͨµÀºÅ(0~15)
423* Output: None
424* Output: None
425* Returns:
426* None
427* Others: None
428**************************************************************************/
429UINT32 zDrvDma_GetTransferNumber(UINT32 ucChannel);
430
431/**************************************************************************
432* Function: zDrvDma_DisableChannel
433* Description: Ç¿ÖÆÍ£Ö¹ucChannelËùָͨµÀºÅµÄ´«Êä¡£
434* Í£Ö¹ºóÈôÏëÖØÐÂÆô¶¯´«Ê䣬ÐèÖØÐÂÅäÖòÎÊý¡£
435* Parameters:
436* Input:
437* ucChannel: zDrvDma_AllocChannelµÄ·µ»ØÖµ¡£
438* Output: None
439* Returns:
440*
441* Others: ´Ëº¯ÊýÍ£Ö¹DMA´«Ê䣬²»ÊÇÔÝÍ£¡£
442**************************************************************************/
443SINT32 zDrvDma_DisableChannel(UINT32 ucChannel);
444
445/**************************************************************************
446* Function: zDrvDma_GetStatus
447* Description:Ê¡µçרÓýӿڣ¬ÓÃÓÚ²»²úÉúÖжϵÄDMA´«Êä
448* Parameters:
449* Input: zDrvDma_AllocChannel µÄ·µ»ØÖµ:¸ß16λ:dma¿ØÖÆÆ÷µÍ16λ:ͨµÀºÅ(0~15)
450* Output: None
451* Returns:
452* DMA_TRANSFER_DONE: channelID 's dma transfer has done.
453* DMA_CFG_ERROR:something wrong with channelID's dma configuration
454* DMA_NOT_DONE: if dma not done and dma config has no problem,return this value.
455*
456* Others: None
457**************************************************************************/
458T_DMA_STATUS zDrvDma_GetStatus(UINT32 channelID);
459
460/**************************************************************************
461* Function: zDrvDma_ConfigLLI
462* Description:Ê¡µçרÓýӿڣ¬ÓÃÓÚ²»²úÉúÖжϵÄDMA´«Êä
463* Parameters:
464* Input: channelID:zDrvDma_AllocChannel µÄ·µ»ØÖµ:¸ß16λ:dma¿ØÖÆÆ÷µÍ16λ:ͨµÀºÅ(0~15)
465 channelaPara:DMA²ÎÊýÊý×é
466 LLIParaCnt:Êý×éÔªËظöÊý:×î´óΪ32
467 isLoop:TRUE--Ñ­»·´«ËÍ FALSE--normal
468* Output: None
469* Returns:
470*
471* Others: None
472**************************************************************************/
473SINT32 zDrvDma_ConfigLLI(UINT32 channelID,T_ZDrvDma_ChannelDef channelaPara[], UINT32 LLIParaCnt, BOOL isLoop);
474
475/*******************************************************************************
476* Function: zDrvDma_Mem2MemForEmbms
477* Description:
478 this function implement a mem to mem dma transfer function,
479 note: the memery involved must be set to non-cacheable
480* Parameters:
481* Input:
482* embmsChannel:
483 LLIParaCnt:number of embmsChannel[]
484 CallBack: callback func
485* Output:
486*
487* Returns:
488*
489* Others:
490********************************************************************************/
491SINT32 zDrvDma_Mem2MemForEmbms(T_ZDrvDma_EmbmsChannelDef embmsChannel[], UINT32 LLIParaCnt, zDrvDma_CallbackFunc CallBack);
492
493#endif/*_DRVS_DMA_H*/
494