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192.168.1.100 / T106_DC / 9ed821d7e5d875a3395740a9cc2545671fa429b7 / . / cp / ps / driver / inc / misc / drvs_sys.h
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lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame^]1/*******************************************************************************
2 * Copyright (C) 2014, ZTE Corporation.
3 *
4 * File Name:
5 * File Mark:
6 * Description: definition of clock name and frequency for zx297520
7 * Others:
8 * Version: v1.0
9 * Author: xuzhiguo
10 * Date: 2014-07-01
11 * History 1:
12 * Date:
13 * Version:
14 * Author:
15 * Modification:
16 * History 2:
17 ********************************************************************************/
18
19#ifndef _DRVS_SYS_H
20#define _DRVS_SYS_H
21
22/****************************************************************************
23* Macros
24****************************************************************************/
25
26/****************************************************************************
27* Types
28****************************************************************************/
29#if 0//modify by xxx def _OS_LINUX
30
31#define DRV_USE_MODEM_TYPE
32
33#include <mach/clk.h> /*use linux define*/
34
35#else
36
37#if defined (_CHIP_ZX297520V3)
38/*
39* ACLK: AXI BUS CLOCK
40* HCLK: AHB BUS CLOCK
41* PCLK: APB BUS CLOCK
42*/
43typedef enum
44{
45 /*
46 * PS mg input clock
47 */
48 CLK_PS_CORE,
49 CLK_PS_CORE_IDLE,
50 CLK_TODDR_ACLK,
51 CLK_TOMATIRX_ACLK,
52 CLK_FROMMATIRX_PCLK,
53 CLK_PSMATIRX_AXI,
54
55
56 #if 0
57 CLK_R7INT,
58 CLK_R7CRM_PCLK,
59 CLK_AXI2AXI_APB_AS_FOR_TCM,
60 CLK_AXI2AXI_AS_M1,
61 CLK_AXI2AXI_APB_AS,
62 CLK_R7CFG_APBMUX_PCLK,
63 #endif
64 /*
65 * lsp mg input clock
66 */
67 CLK_LSP32K,
68 CLK_LSP26M,
69 CLK_LSP52M,
70 CLK_LSP78M,
71 CLK_LSP124M8,
72 CLK_LSP156M,
73 CLK_LSP104M,
74 CLK_LSP122M88,
75 CLK_LSPTDM,
76 CLK_LSPAPB,
77
78 /*
79 * USB
80 */
81 /*CLK_USB_HCLK,
82 CLK_USB_CTRL_WCLK,
83 CLK_USB_12M_PHY_WCLK,
84
85 CLK_HSIC_HCLK,
86 CLK_HSIC_12M_PHY_WCLK,
87 CLK_HSIC_480M_PHY_WCLK,
88 CLK_HSIC_CTRL_WCLK,*/
89
90 /*
91 *dma
92 */
93 CLK_DMA0_PCLK,
94 CLK_DMA0_ACLK,
95
96 /*
97 * M2_AXI2AHB
98 */
99 //CLK_M2_ACLK,
100 //CLK_M2_HCLK,
101
102 /*
103 * edcp in matrix blcok
104 */
105 CLK_EDCP_HCLK,
106 CLK_EDCPASYNC_ACLK,
107 CLK_EDCPSYNC_ACLK,
108
109 /*
110 * nand
111 */
112 /*CLK_4M1SNAND_HCLK,*/
113 CLK_NAND_HCLK ,
114 CLK_NAND_WCLK,
115
116 /*
117 * sd
118 */
119 CLK_SD0_HCLK,
120 CLK_SD1_HCLK,
121
122 CLK_SD0_32K,
123 CLK_SD1_32K,
124
125 CLK_SD0_WCLK,
126 CLK_SD1_WCLK,
127
128 /*i2s in lsp*/
129 CLK_I2S0_PCLK,
130 CLK_I2S1_PCLK,
131
132 CLK_I2S0_WCLK,
133 CLK_I2S1_WCLK,
134
135 /*spifc in lsp*/
136 CLK_SPIFC_PCLK,
137 CLK_SPIFC_WCLK,
138
139 /* ssp in lsp*/
140 CLK_SSP0_PCLK,
141 CLK_SSP1_PCLK,
142
143 CLK_SSP0_WCLK,
144 CLK_SSP1_WCLK,
145
146 /*uart0 in rm,uart1&2 in lsp*/
147 CLK_UART0_PCLK,
148 CLK_UART1_PCLK,
149 CLK_UART2_PCLK,
150
151 CLK_UART0_WCLK,
152 CLK_UART1_WCLK,
153 CLK_UART2_WCLK,
154
155 /*i2c0 in rm, i2c1 in lsp*/
156 CLK_RMI2C_PCLK,
157 CLK_I2C1_PCLK,
158
159 CLK_RMI2C_WCLK,
160 CLK_I2C1_WCLK,
161
162 /*gpio0&1 in rm*/
163 CLK_GPIO0_PCLK,
164 CLK_GPIO1_PCLK,
165
166 /*gsm in rm*/
167 CLK_GSM_156M,
168 CLK_GSM_104M,
169 CLK_GSM_48M,
170 CLK_GSM_32K,
171 CLK_GSM_MAIN,
172
173 /*tdm in lsp*/
174 CLK_TDM_PCLK,
175 CLK_TDM_WCLK,
176
177 /*ps timer1&2&rm timer1 in rm, ps timer0&ps-rm timer in lsp*/
178 CLK_TIMER0_PCLK,/*ps timer0*/
179 CLK_TIMER4_PCLK,/*ps rm timer*/
180 CLK_TIMER1_PCLK,/*ps timer1*/
181 CLK_TIMER2_PCLK,/*ps timer2*/
182 CLK_TIMER3_PCLK,/*rm timer1*/
183
184 CLK_TIMER0_WCLK,/*ps timer0*/
185 CLK_TIMER4_WCLK,/*ps rm timer*/
186 CLK_TIMER1_WCLK,/*ps timer1*/
187 CLK_TIMER2_WCLK,/*ps timer2*/
188 CLK_TIMER3_WCLK,/*rm timer1*/
189
190 /*
191 * usim
192 */
193 CLK_USIM_PCLK,
194 CLK_USIM_WCLK,
195
196 /*
197 * mpll
198 */
199 CLK_MPLL_156M_CLK,
200 CLK_MPLL_48M_CLK,
201 CLK_AON_DPLL_491M52_CLK,
202
203 /*
204 * rtc
205 */
206 //CLK_RTC_PCLK,
207 //CLK_RTC_WCLK,
208
209 /*wdt in lsp*/
210 CLK_WDT_PCLK,
211 CLK_WDT_WCLK,
212
213 /*key in rm*/
214 CLK_KEY_PCLK,
215 CLK_KEY_WCLK,
216 /*VOU */
217 CLK_OSD_PCLK,
218 CLK_OSD_ACLK,
219 CLK_OSD_VEDIO_CLK,
220 CLK_OSD_GRAPHIC_CLK,
221 CLK_OSD_MAINMIX_CLK,
222 CLK_OSD_PPU_CLK,
223 CLK_CSC_WCLK,
224 CLK_CSC_PCLK,
225 CLK_VOU_ACLK,
226 CLK_VOU_PCLK,
227 CLK_VOU_WCLK,
228 CLK_MCU_WCLK,
229 CLK_MCU_PCLK,
230 /*
231 * gsmlpm
232 */
233 CLK_GSMLPM_PCLK,
234 CLK_GSMLPM_WCLK,
235
236 /*matrix ps block*/
237 CLK_PS2MATRIX_ACLK,
238 CLK_PS2DDR_ACLK,
239
240 /*matrix block*/
241 CLK_DPLL_122M88,
242
243 /*matrix ssc block*/
244 CLK_SSC_WCLK,
245 CLK_SSC_PCLK,
246 CLK_RFFE_WCLK,
247
248} T_ZDrvSysClk_Name;
249
250
251
252
253/*
254* bits domain definition for clock frequency
255* base clock name same clock number reserved clock selection frequency division
256* 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0
257* invalid value:
258* 0xff 0xf or 0x0 0x0 or ignore 0xff 0xff
259*/
260
261typedef enum
262{
263 /*fixed frequency*/
264 FIXED_FREQ =0xffffffff,
265
266 /*ps core & ps core idle*/
267 PS_CORE_26M = (CLK_PS_CORE << 24) | 0x00200000,
268 PS_CORE_624M = (CLK_PS_CORE << 24) | 0x00200100,
269 PS_CORE_312M = (CLK_PS_CORE << 24) | 0x00200200,
270 PS_CORE_156M = (CLK_PS_CORE << 24) | 0x00200300,
271
272 /*ps matrix axi*/
273 PS_MATRIX_AXI_26M = (CLK_PSMATIRX_AXI << 24) | 0x00100000,
274 PS_MATRIX_AXI_156M = (CLK_PSMATIRX_AXI << 24) | 0x00100100,
275 PS_MATRIX_AXI_124M8 = (CLK_PSMATIRX_AXI << 24) | 0x00100200,
276 PS_MATRIX_AXI_104M = (CLK_PSMATIRX_AXI << 24) | 0x00100300,
277 PS_MATRIX_AXI_78M = (CLK_PSMATIRX_AXI << 24) | 0x00100400,
278 PS_MATRIX_AXI_52M = (CLK_PSMATIRX_AXI << 24) | 0x00100500,
279 PS_MATRIX_AXI_39M = (CLK_PSMATIRX_AXI << 24) | 0x00100600,
280 PS_MATRIX_AXI_6M5 = (CLK_PSMATIRX_AXI << 24) | 0x00100700,
281
282 /*TDM WCLK*/
283 WCLK_TDM_26M = (CLK_LSPTDM << 24) | 0x00100000,
284 WCLK_TDM_122M88 = (CLK_LSPTDM << 24) | 0x00100100,
285 WCLK_TDM_104M = (CLK_LSPTDM << 24) | 0x00100200,
286
287 /* EDCP WCLK*/
288 WCLK_EDCP_26M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100000,
289 WCLK_EDCP_208M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100100,
290 WCLK_EDCP_156M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100200,
291 WCLK_EDCP_104M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100300,
292
293 /*NAND WCLK*/
294 WCLK_NAND_26M = (CLK_NAND_WCLK << 24) | 0x00100000,
295 WCLK_NAND_104M = (CLK_NAND_WCLK << 24) | 0x00100100,
296 WCLK_NAND_78M = (CLK_NAND_WCLK << 24) | 0x00100200,
297
298 /* SD0 WCLK*/
299 WCLK_SD0_26M = (CLK_SD0_WCLK << 24) | 0x00100000,
300 WCLK_SD0_156M = (CLK_SD0_WCLK << 24) | 0x00100100,
301 WCLK_SD0_100M = (CLK_SD0_WCLK << 24) | 0x00100200,
302 WCLK_SD0_78M = (CLK_SD0_WCLK << 24) | 0x00100300,
303 WCLK_SD0_50M = (CLK_SD0_WCLK << 24) | 0x00100400,
304 WCLK_SD0_25M = (CLK_SD0_WCLK << 24) | 0x00100500,
305
306 /* SD1 WCLK*/
307 WCLK_SD1_26M = (CLK_SD1_WCLK << 24) | 0x00100000,
308 WCLK_SD1_100M = (CLK_SD1_WCLK << 24) | 0x00100100,
309 WCLK_SD1_78M = (CLK_SD1_WCLK << 24) | 0x00100200,
310 WCLK_SD1_50M = (CLK_SD1_WCLK << 24) | 0x00100300,
311 WCLK_SD1_39M = (CLK_SD1_WCLK << 24) | 0x00100400,
312 WCLK_SD1_25M = (CLK_SD1_WCLK << 24) | 0x00100500,
313
314 /* I2S0&1 WCLK*/
315 WCLK_I2S_26M = (CLK_I2S0_WCLK << 24) | 0x00200000,
316 WCLK_I2S_122M88 = (CLK_I2S0_WCLK << 24) | 0x00200100,
317 WCLK_I2S_104M = (CLK_I2S0_WCLK << 24) | 0x00200200,
318
319 /*SPIFC WCLK*/
320 WCLK_SPIFC_26M = (CLK_SPIFC_WCLK << 24) | 0x00100000,
321 WCLK_SPIFC_156M = (CLK_SPIFC_WCLK << 24) | 0x00100100,
322 WCLK_SPIFC_124M8 = (CLK_SPIFC_WCLK << 24) | 0x00100200,
323 WCLK_SPIFC_104M = (CLK_SPIFC_WCLK << 24) | 0x00100300,
324 WCLK_SPIFC_78M = (CLK_SPIFC_WCLK << 24) | 0x00100400,
325 WCLK_SPIFC_52M = (CLK_SPIFC_WCLK << 24) | 0x00100500,
326
327 /* SSP0&1 WCLK*/
328 WCLK_SSP_26M = (CLK_SSP0_WCLK << 24) | 0x00200000,
329 WCLK_SSP_13M = (CLK_SSP0_WCLK << 24) | 0x00200001,
330 WCLK_SSP_6M5 = (CLK_SSP0_WCLK << 24) | 0x00200003,
331 WCLK_SSP_156M = (CLK_SSP0_WCLK << 24) | 0x00200100,
332 WCLK_SSP_78M = (CLK_SSP0_WCLK << 24) | 0x00200101,
333 WCLK_SSP_19M5 = (CLK_SSP0_WCLK << 24) | 0x00200107,
334 WCLK_SSP_104M = (CLK_SSP0_WCLK << 24) | 0x00200200,
335 WCLK_SSP_52M = (CLK_SSP0_WCLK << 24) | 0x00200201,
336
337 /*ps timer1& ps timer2& rm timer1*/
338 WCLK_AON_TIMER_32K = (CLK_TIMER1_WCLK << 24) | 0x00300000,
339 WCLK_AON_TIMER_26M = (CLK_TIMER1_WCLK << 24) | 0x00300100, /* 1 div*/
340 WCLK_AON_TIMER_13M = (CLK_TIMER1_WCLK << 24) | 0x00300101, /* 2 div*/
341
342 /*ps timer0&ps rm timer*/
343 WCLK_LSP_TIMER_32K = (CLK_TIMER0_WCLK << 24) | 0x00200000,
344 WCLK_LSP_TIMER_26M = (CLK_TIMER0_WCLK << 24) | 0x00200100, /* 1 div*/
345 WCLK_LSP_TIMER_13M = (CLK_TIMER0_WCLK << 24) | 0x00200101, /* 2 div*/
346
347 /* I2C0&1 WCLK*/
348 WCLK_I2C_26M = (CLK_RMI2C_WCLK << 24) | 0x00200000,
349 WCLK_I2C_104M = (CLK_RMI2C_WCLK << 24) | 0x00200100,
350
351 /* UART0&1&2 WCLK*/
352 WCLK_UART_26M = (CLK_UART0_WCLK << 24) | 0x00300000,
353 WCLK_UART_104M = (CLK_UART0_WCLK << 24) | 0x00300100,
354
355 /*PS WDT WCLK*/
356 WCLK_WDT_32K = (CLK_WDT_WCLK << 24) | 0x00100000,
357 WCLK_WDT_26M = (CLK_WDT_WCLK << 24) | 0x00100100,
358 WCLK_WDT_13M = (CLK_WDT_WCLK << 24) | 0x00100101,
359
360 /* USIM WCLK */
361 /* usim work clock is fixed 13MHz*/
362 /*WCLK_USIM_13M = (CLK_USIM_WCLK << 24) | 0x0010ffff,*/
363
364 /* RTC WCLK */
365 /* rtc work clock is fixed 32KHz*/
366 /*WCLK_RTC_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
367
368 /* KEY WCLK */
369 /* KEY work clock is fixed 32KHz*/
370 /*WCLK_KEY_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
371
372
373} T_ZDrvSysClk_Freq;
374#elif defined (_CHIP_ZX297520V2)
375/*
376* ACLK: AXI BUS CLOCK
377* HCLK: AHB BUS CLOCK
378* ACLK: APB BUS CLOCK
379*/
380typedef enum
381{
382 /*
383 * PS
384 */
385 CLK_PS_CORE,
386 CLK_PS_CORE_IDLE,
387 CLK_R7INT,
388 CLK_R7CRM_PCLK,
389 CLK_AXI2AXI_APB_AS_FOR_TCM,
390 CLK_AXI2AXI_AS_M1,
391 CLK_AXI2AXI_APB_AS,
392 CLK_R7CFG_APBMUX_PCLK,
393 CLK_FROMMATIRX_ACLK,
394 CLK_TOMATIRX_ACLK,
395 CLK_TODDR3_ACLK,
396
397 /*
398 * lsp mg input clock
399 */
400 CLK_LSP124M8,
401 CLK_LSP156M,
402 CLK_LSP104M,
403 CLK_LSP78M,
404 CLK_LSP52M,
405 CLK_LSP26M,
406 CLK_LSP32K,
407 CLK_LSPAPB,
408 CLK_LSPTDM,
409
410 /*
411 * USB
412 */
413 /*CLK_USB_HCLK,
414 CLK_USB_CTRL_WCLK,
415 CLK_USB_12M_PHY_WCLK,
416
417 CLK_HSIC_HCLK,
418 CLK_HSIC_12M_PHY_WCLK,
419 CLK_HSIC_480M_PHY_WCLK,
420 CLK_HSIC_CTRL_WCLK,*/
421
422 /*
423 *dma
424 */
425 CLK_DMA0_PCLK,
426 CLK_DMA0_ACLK,
427
428 /*
429 * M2_AXI2AHB
430 */
431 //CLK_M2_ACLK,
432 //CLK_M2_HCLK,
433
434 /*
435 * edcp
436 */
437 CLK_EDCP_HCLK,
438 CLK_EDCPASYNC_ACLK,
439 CLK_EDCPSYNC_ACLK,
440
441 /*
442 * nand
443 */
444 /*CLK_4M1SNAND_HCLK,*/
445 CLK_NAND_HCLK ,
446 CLK_NAND_WCLK,
447
448 /*
449 * sd
450 */
451 CLK_SD0_HCLK,
452 CLK_SD1_HCLK,
453
454 CLK_SD0_32K,
455 CLK_SD1_32K,
456
457 CLK_SD0_WCLK,
458 CLK_SD1_WCLK,
459
460 /*
461 * i2s
462 */
463 CLK_I2S0_PCLK,
464 CLK_I2S1_PCLK,
465
466 CLK_I2S0_WCLK,
467 CLK_I2S1_WCLK,
468
469 /*
470 * spifc
471 */
472 CLK_SPIFC_PCLK,
473 CLK_SPIFC_WCLK,
474
475 /*
476 * ssp
477 */
478 CLK_SSP0_PCLK,
479 CLK_SSP1_PCLK,
480
481 CLK_SSP0_WCLK,
482 CLK_SSP1_WCLK,
483
484 /*
485 * uart0
486 */
487 CLK_UART0_PCLK,
488 CLK_UART1_PCLK,
489 CLK_UART2_PCLK,
490
491 CLK_UART0_WCLK,
492 CLK_UART1_WCLK,
493 CLK_UART2_WCLK,
494
495 /*
496 * i2c
497 */
498 CLK_RMI2C_PCLK,
499 CLK_I2C1_PCLK,
500
501 CLK_RMI2C_WCLK,
502 CLK_I2C1_WCLK,
503
504 /*
505 * gpio
506 */
507 CLK_GPIO0_PCLK,
508 CLK_GPIO1_PCLK,
509
510 /*
511 * gsm
512 */
513 CLK_GSM_PCLK,
514 CLK_GSM_32K,
515 CLK_GSM_MAIN,
516 CLK_GSM_48M,
517 CLK_GSM_104M,
518 CLK_GSM_156M,
519 CLK_GSM_SYS_26M,
520
521 /*
522 * tdm
523 */
524 CLK_TDM_PCLK,
525 CLK_TDM_WCLK,
526
527 /*
528 * timer
529 */
530 CLK_TIMER1_PCLK,
531 CLK_TIMER2_PCLK,
532 CLK_TIMER3_PCLK,/*m0 rm timer1*/
533
534 CLK_TIMER0_PCLK,
535 CLK_TIMER4_PCLK,/*ps rm timer*/
536
537 CLK_TIMER1_WCLK,
538 CLK_TIMER2_WCLK,
539 CLK_TIMER3_WCLK,/*m0 rm timer1*/
540
541 CLK_TIMER0_WCLK,
542 CLK_TIMER4_WCLK,/*ps rm timer*/
543
544 /*
545 * usim
546 */
547 //CLK_USIM_PCLK,
548 //CLK_USIM_WCLK,
549
550 /*
551 * rtc
552 */
553 //CLK_RTC_PCLK,
554 //CLK_RTC_WCLK,
555
556 /*
557 * wdt
558 */
559 CLK_WDT_PCLK,
560 CLK_WDT_WCLK,
561
562 /*
563 * key
564 */
565 CLK_KEY_PCLK,
566 CLK_KEY_WCLK,
567
568 /*
569 * gsmlpm
570 */
571 //CLK_GSMLPM_PCLK,
572 //CLK_GSMLPM_WCLK,
573 //CLK_WIFI_BT
574} T_ZDrvSysClk_Name;
575
576
577
578
579/*
580* bits domain definition for clock frequency
581* base clock name same clock number reserved clock selection frequency division
582* 31...28 27...24 23...20 19...16 15...12 11...8 7...4 3...0
583* invalid value:
584* 0xff 0xf or 0x0 0x0 or ignore 0xff 0xff
585*/
586
587typedef enum
588{
589 /*fixed frequency*/
590 FIXED_FREQ =0xffffffff,
591 /*
592 *ps core
593 */
594 PS_CORE_624M = (CLK_PS_CORE << 24) | 0x00100000,
595 PS_CORE_26M = (CLK_PS_CORE << 24) | 0x00100100,
596 PS_CORE_491M52 = (CLK_PS_CORE << 24) | 0x00100200,
597 PS_CORE_312M = (CLK_PS_CORE << 24) | 0x00100300,
598 PS_CORE_208M = (CLK_PS_CORE << 24) | 0x00100400,
599 PS_CORE_104M = (CLK_PS_CORE << 24) | 0x00100500,
600 PS_CORE_78M = (CLK_PS_CORE << 24) | 0x00100600,
601 PS_CORE_52M = (CLK_PS_CORE << 24) | 0x00100700,
602
603 /*
604 *ps core idle
605 */
606 PS_CORE_IDLE_624 = (CLK_PS_CORE << 24) | 0x00100000,
607 PS_CORE_IDLE_26M = (CLK_PS_CORE << 24) | 0x00100100,
608 PS_CORE_IDLE_491M52 = (CLK_PS_CORE << 24) | 0x00100200,
609 PS_CORE_IDLE_312M = (CLK_PS_CORE << 24) | 0x00100300,
610 PS_CORE_IDLE_208M = (CLK_PS_CORE << 24) | 0x00100400,
611 PS_CORE_IDLE_104M = (CLK_PS_CORE << 24) | 0x00100500,
612 PS_CORE_IDLE_78M = (CLK_PS_CORE << 24) | 0x00100600,
613 PS_CORE_IDLE_52M = (CLK_PS_CORE << 24) | 0x00100700,
614
615 /* EDCP WCLK*/
616 WCLK_EDCP_208M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100000,
617 WCLK_EDCP_26M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100100,
618 WCLK_EDCP_156M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100200,
619 WCLK_EDCP_104M = (CLK_EDCPASYNC_ACLK << 24) | 0x00100300,
620
621 /*NAND WCLK*/
622 WCLK_NAND_104M = (CLK_NAND_WCLK << 24) | 0x00100000,
623 WCLK_NAND_26M = (CLK_NAND_WCLK << 24) | 0x00100100,
624 WCLK_NAND_78M = (CLK_NAND_WCLK << 24) | 0x00100200,
625 WCLK_NAND_52M = (CLK_NAND_WCLK << 24) | 0x00100300,
626
627 /* SD0 WCLK*/
628 WCLK_SD0_200M = (CLK_SD0_WCLK << 24) | 0x00100000,
629 WCLK_SD0_26M = (CLK_SD0_WCLK << 24) | 0x00100100,
630 WCLK_SD0_156M = (CLK_SD0_WCLK << 24) | 0x00100200,
631 WCLK_SD0_100M = (CLK_SD0_WCLK << 24) | 0x00100300,
632 WCLK_SD0_78M = (CLK_SD0_WCLK << 24) | 0x00100400,
633 WCLK_SD0_50M = (CLK_SD0_WCLK << 24) | 0x00100500,
634 WCLK_SD0_178M = (CLK_SD0_WCLK << 24) | 0x00100600,
635 WCLK_SD0_25M = (CLK_SD0_WCLK << 24) | 0x00100700,
636
637 /* SD1 WCLK*/
638 WCLK_SD1_100M = (CLK_SD1_WCLK << 24) | 0x00100000,
639 WCLK_SD1_26M = (CLK_SD1_WCLK << 24) | 0x00100100,
640 WCLK_SD1_78M = (CLK_SD1_WCLK << 24) | 0x00100200,
641 WCLK_SD1_50M = (CLK_SD1_WCLK << 24) | 0x00100300,
642 WCLK_SD1_39M = (CLK_SD1_WCLK << 24) | 0x00100400,
643 WCLK_SD1_25M = (CLK_SD1_WCLK << 24) | 0x00100500,
644
645
646 /* I2S WCLK*/
647 /*I2S not be used in zx297520, so ignore it's clock*/
648 WCLK_I2S_26M = (CLK_I2S0_WCLK << 24) | 0x00200000,
649 WCLK_I2S_104M = (CLK_I2S0_WCLK << 24) | 0x00200100,
650
651 /* BLG WCLK*/
652 /* blg work clock used default 32KHz*/
653
654 /*SPIFC WCLK*/
655 WCLK_SPIFC_156M = (CLK_SPIFC_WCLK << 24) | 0x00100000,
656 WCLK_SPIFC_26M = (CLK_SPIFC_WCLK << 24) | 0x00100100,
657 WCLK_SPIFC_124M8 = (CLK_SPIFC_WCLK << 24) | 0x00100200,
658 WCLK_SPIFC_104M = (CLK_SPIFC_WCLK << 24) | 0x00100300,
659 WCLK_SPIFC_78M = (CLK_SPIFC_WCLK << 24) | 0x00100400,
660 WCLK_SPIFC_52M = (CLK_SPIFC_WCLK << 24) | 0x00100500,
661
662 /*AON TIMER WCLK timer1&timer2&timer3*/
663 WCLK_AON_TIMER_32K = (CLK_TIMER1_WCLK << 24) | 0x00300100,
664 WCLK_AON_TIMER_26M = (CLK_TIMER1_WCLK << 24) | 0x00300000, /* 1 div*/
665 WCLK_AON_TIMER_13M = (CLK_TIMER1_WCLK << 24) | 0x00300001, /* 2 div*/
666
667 /*LSP TIMER0 WCLK timer0&timer4*/
668 WCLK_LSP_TIMER_32K = (CLK_TIMER0_WCLK << 24) | 0x00200000,
669 WCLK_LSP_TIMER_26M = (CLK_TIMER0_WCLK << 24) | 0x00200100, /* 1 div*/
670 WCLK_LSP_TIMER_13M = (CLK_TIMER0_WCLK << 24) | 0x00200101, /* 2 div*/
671
672 /* RM I2C WCLK*/
673 WCLK_RMI2C_26M = (CLK_RMI2C_WCLK << 24) | 0x00100100,
674 WCLK_RMI2C_104M = (CLK_RMI2C_WCLK << 24) | 0x00100000,
675
676 /* I2C1 WCLK*/
677 WCLK_I2C1_26M = (CLK_I2C1_WCLK << 24) | 0x00100000,
678 WCLK_I2C1_104M = (CLK_I2C1_WCLK << 24) | 0x00100100,
679
680
681 /* UART WCLK*/
682 WCLK_UART0_26M = (CLK_UART0_WCLK << 24) | 0x00100100,
683 WCLK_UART0_104M = (CLK_UART0_WCLK << 24) | 0x00100000,
684
685 WCLK_UART12_26M = (CLK_UART1_WCLK << 24) | 0x00200000,
686 WCLK_UART12_104M = (CLK_UART1_WCLK << 24) | 0x00200100,
687
688 /* SSP WCLK*/
689 WCLK_SSP_0M = (CLK_SSP0_WCLK << 24) | 0x00200301,
690 WCLK_SSP_6M5 = (CLK_SSP0_WCLK << 24) | 0x00200203,
691 WCLK_SSP_13M = (CLK_SSP0_WCLK << 24) | 0x00200201,
692 WCLK_SSP_26M = (CLK_SSP0_WCLK << 24) | 0x00200200,
693 WCLK_SSP_52M = (CLK_SSP0_WCLK << 24) | 0x00200101,
694 WCLK_SSP_78M = (CLK_SSP0_WCLK << 24) | 0x00200001,
695 WCLK_SSP_156M = (CLK_SSP0_WCLK << 24) | 0x00200000,
696
697 /* WDT WCLK*/
698 WCLK_WDT_32K = (CLK_WDT_WCLK << 24) | 0x00100000,
699 WCLK_WDT_26M = (CLK_WDT_WCLK << 24) | 0x00100100,
700
701 /* USIM WCLK */
702 /* usim work clock is fixed 13MHz*/
703 /*WCLK_USIM_13M = (CLK_USIM_WCLK << 24) | 0x0010ffff,*/
704
705 /* RTC WCLK */
706 /* rtc work clock is fixed 32KHz*/
707 /*WCLK_RTC_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
708
709 /* KEY WCLK */
710 /* KEY work clock is fixed 32KHz*/
711 /*WCLK_KEY_32K = (CLK_RTC_WCLK << 24) | 0x0010ffff,*/
712
713 /*AON_CLK_OUT1*/
714 /*
715 CLK_OUT1_40M = (CLK_WIFI_BT << 24) | 0x00100300,
716 CLK_OUT1_20M = (CLK_WIFI_BT << 24) | 0x00100200,
717 CLK_OUT1_26M = (CLK_WIFI_BT << 24) | 0x00100100,
718 CLK_OUT1_13M = (CLK_WIFI_BT << 24) | 0x00100000,
719 */
720
721} T_ZDrvSysClk_Freq;
722
723#endif
724
725
726typedef enum
727{
728 SYSCLK_DISABLE = 0x100, /*disable software gate */
729 SYSCLK_ENABLE, /*enable software gate */
730 SYSCLK_DISAUTO, /*disable hardware gate */
731 SYSCLK_AUTO, /*enable hardware gate */
732} T_ZDrvSysClk_Gate;
733
734
735/****************************************************************************
736* function
737****************************************************************************/
738/*******************************************************************************
739* Function: zDrvSys_PreInit
740* Description: system previous initialization
741* Parameters:
742* Input:
743*
744* Output:
745*
746* Returns:
747*
748* Others:
749********************************************************************************/
750SINT32 zDrvSys_PreInit(void);
751
752/*******************************************************************************
753* Function: zDrvSys_Initiate
754* Description: system initialization
755* Parameters:
756* Input:
757*
758* Output:
759*
760* Returns:
761*
762* Others:
763********************************************************************************/
764SINT32 zDrvSys_Initiate(void);
765
766/*******************************************************************************
767* Function: zDrvSysClk_IsEnable
768* Description: get clock software gate status
769* Parameters:
770* Input:
771* name: clock number
772*
773* Output: NULL
774*
775* Returns: 0: software gate disable
776* 1: software gate enable
777* DRV_ERR_INVALID_PARAM: invalid parameter
778*
779* Others:
780********************************************************************************/
781SINT32 zDrvSysClk_IsEnable(T_ZDrvSysClk_Name name);
782
783
784/*******************************************************************************
785* Function: zDrvSysClk_IsAutoGate
786* Description: get clock hardware gate status
787* Parameters:
788* Input:
789* name: clock number
790*
791* Output: NULL
792*
793* Returns: 0: hardware gate disable
794* 1: hardware gate enable
795* DRV_ERR_INVALID_PARAM:invalid parameter
796*
797* Others:
798********************************************************************************/
799SINT32 zDrvSysClk_IsAutoGate(T_ZDrvSysClk_Name name);
800
801
802/*******************************************************************************
803 * Function: zDrvSysClk_Reset
804 * Description: set logic to reset status
805 * Parameters:
806 * Input:
807 * name: clock number
808 *
809 * Output: NULL
810 *
811 * Returns: DRV_SUCCESS
812 * DRV_ERR_INVALID_PARAM
813 *
814 * Others:
815 ********************************************************************************/
816SINT32 zDrvSysClk_Reset(T_ZDrvSysClk_Name name);
817
818/*******************************************************************************
819 * Function: zDrvSysClk_Release
820 * Description: set logic out of reset status
821 * Parameters:
822 * Input:
823 * name: clock number
824 *
825 * Output: NULL
826 *
827 * Returns: DRV_SUCCESS
828 * DRV_ERR_INVALID_PARAM
829 *
830 * Others:
831 ********************************************************************************/
832SINT32 zDrvSysClk_Release(T_ZDrvSysClk_Name name);
833
834/*******************************************************************************
835* Function: zDrvSysClk_SetGate
836* Description: set clock gate status
837* Parameters:
838* Input:
839* name: clock number
840* gate: gate status
841* Output: NULL
842*
843* Returns: DRV_SUCCESS
844* DRV_ERR_INVALID_PARAM
845*
846* Others:
847********************************************************************************/
848SINT32 zDrvSysClk_SetGate(T_ZDrvSysClk_Name name, T_ZDrvSysClk_Gate gate);
849
850/*******************************************************************************
851* Function: zDrvSysClk_SetFreq
852* Description: set clock frequency which defined in drvs_sys.h by T_ZDrvSysClk_Freq
853* Parameters:
854 * Input:
855 * name: clock number
856* freq: clock frequency
857* Output: NULL
858*
859* Returns: DRV_SUCCESS
860* DRV_ERR_INVALID_PARAM
861* Others:
862********************************************************************************/
863SINT32 zDrvSysClk_SetFreq(T_ZDrvSysClk_Name name, T_ZDrvSysClk_Freq freq);
864
865#endif
866
867#endif
868