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192.168.1.100 / T106_DC / 9ed821d7e5d875a3395740a9cc2545671fa429b7 / . / pub / include / ps_phy / l1_count_latch.h
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lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame^]1/*****************************************************************************
2 * °æ±¾ËùÓÐ (C)2010ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
3 *
4 * Ä£¿éÃû £º
5 * ÎļþÃû £ºl1_count_latch.h
6 * Îļþ±êʶ£º
7 * Ïà¹ØÎļþ£º
8 * ʵÏÖ¹¦ÄÜ£º
9 * ×÷Õß £º
10 * °æ±¾ £º
11 * Íê³ÉÈÕÆÚ£º
12 * ÆäËü˵Ã÷£ºÐ½¨
13 *
14 *****************************************************************************/
15
16
17#ifndef _L1_COUNT_LATCH_H
18#define _L1_COUNT_LATCH_H
19
20
21/**************************************************************************
22 * Í·Îļþ°üº¬ *
23 **************************************************************************/
24/* ±ê×¼¿âÍ·Îļþ */
25#include "oss_api.h"
26
27#ifdef DDR_BASE_ADDR_LINUX_VA
28#include <mach/iomap.h>
29#endif
30
31/* ·Ç±ê×¼¿âÍ·Îļþ */
32
33
34/**************************************************************************
35 * ³£Á¿¶¨Òå *
36 **************************************************************************/
37
38/**************************************************************************
39 * È«¾Öºê¶¨Òå *
40 **************************************************************************/
41//¼Ä´æÆ÷8'h15 (0x6d80_1054)£º¶àÄ£count latch¿ØÖƼĴæÆ÷
42/*
434.4.1.22 ¼Ä´æÆ÷8'h15 (0x6d80_1054)£º¶àÄ£count latch¿ØÖƼĴæÆ÷
44Bit[31:14] R ±£Áô 0
45Bit[13] W/R Gsm_clk_gsm_en_sel 0
46Bit[12] W/R Gsm_clk_gsm_reg 0
47Bit[11:9] R ±£Áô 0
48Bit[8] W/R Gsm_pwr_en 0
49Bit[7:3] R ±£Áô 0
50Bit[2] WR latch_top_en 0
51Bit[1] WR gsm_gsictrl1 0
52Bit[0] WR gsm_gsictrl0 0
53*/
54/*ÖµÎÞЧֻΪ±àÒëͨ¹ý zhangpei*/
55/**************************************************************************
56 * È«¾ÖÊý¾ÝÀàÐͶ¨Òå *
57 **************************************************************************/
58
59typedef struct
60{
61 UINT32 wTick;/*0~9999*/
62 UINT32 wFrame;/*0~2715647*/
63}T_zPHY_GSM_Tstamp;
64typedef struct
65{
66 UINT32 wChip; /*0~6399 chip*/
67 UINT32 wSubFrame; /* ×ÓÖ¡ºÅ£¬ ·¶Î§ 0 - 8191*/
68}T_zPHY_TD_Tstamp;
69typedef struct
70{
71 UINT32 wTs; /*ʱ¼äÐÅÏ¢µ¥Î»TS*/
72 UINT32 wSubFrame; /*ʱ¼äÐÅÏ¢×ÓÖ¡ºÅ*/
73 UINT32 wFrame; /*ʱ¼äÐÅÏ¢Ö¡ºÅ*/
74
75}T_zPHY_LTE_Tstamp;
76typedef struct
77{
78 UINT32 wFrame; /*ʱ¼äÐÅÏ¢×ÓÖ¡ºÅ*/
79 UINT32 wChip; /*ʱ¼äÐÅÏ¢Ö¡ºÅ*/
80}T_zPHY_W_Tstamp;
81
82typedef struct
83{
84 T_zPHY_LTE_Tstamp tLteTstamp; //LTE Ëø´æʱ¼ä£¨ÍøÂçʱ¼ä£©
85 T_zPHY_TD_Tstamp tTDTstamp; //TD Ëø´æʱ¼ä£¨ÍøÂçʱ¼ä£©
86 T_zPHY_W_Tstamp tWTstamp; //W Ëø´æʱ¼ä£¨ÍøÂçʱ¼ä£©
87 T_zPHY_GSM_Tstamp tGsmTstamp; // GSM Ëø´æʱ¼ä£¨ÍøÂçʱ¼ä£©
88}T_zMULM_Timing_Stamp;
89
90
91/* MRTR¿ìÕÕ¿ØÖƼĴæÆ÷ */
92typedef struct
93{
94 UINT32 latch_signal : 1; /* ¿ìÕÕËø´æÐźŠ-w */
95 UINT32 Reserve_0 : 15;
96 UINT32 latch_flag_done : 1; /* Ëø´æÍê³É±êÖ¾ -rd */
97 UINT32 Reserve_1 : 15;
98}T_COUNT_LATCH_LPM_CTRL_REG;
99
100
101/*ÃèÊö£ºMrtr¼ÆÊý¼Ä´æÆ÷*/
102/***************************************************************************
103 BIT |31 30 |29 28 27 26 25 24 23 22 21 20 19 18 | 17 16 15 14 | 13 12 11 10 | 9 8 7 6 5 4 3 2 | 1 0 |
104 ---------------------------------------------------------------------------
105 Function |reserv| RadioFrame | slot | symobol | chip |smple|
106****************************************************************************/
107typedef struct{
108 UINT32 dSample :2;
109 UINT32 dChip :8;
110 UINT32 dSymbol :4;
111 UINT32 dSlot :4;
112 UINT32 dFrame :12;
113 UINT32 dReserved :2;
114}T_regWLpmLatchCnt;
115
116/*TD*/
117/***************************************************************************
118 BIT | 15 14 13 | 12 11 10 9 8 7 6 5 4 3 2 1 0 |
119 ---------------------------------------------------------------------------
120 Function | Reserved | Sub-frame Cnt (nt sub-frame sync)(0~8191) |
121****************************************************************************/
122typedef struct{
123 UINT32 wNtSubFrmValue1 :13;
124 UINT32 wReserved :19;
125}T_regTdLpmLatchSfn;
126/***************************************************************************
127 BIT | 15 | 14 13 12 11 10 9 8 7 6 5 4 3 2 | 1 0 |
128 ---------------------------------------------------------------------------
129 Function | Reserved | Chip Cnt(0~6399)(sync nt sub-frame)| Sample cnt(0~3)|
130****************************************************************************/
131typedef struct{
132 UINT32 wSyncSamcntValue0 :3;
133 UINT32 wSyncChipcntValue0 :13;
134 UINT32 wReserved :16;
135}T_regTdLpmLatchChip;
136
137
138/**************************************************************************
139 * È«¾Ö±äÁ¿ÉùÃ÷ *
140 **************************************************************************/
141
142/**************************************************************************
143 * È«¾Öº¯ÊýÔ­ÐÍ *
144 **************************************************************************/
145/*****************************************************************************
146 * º¯ÊýÃû £º
147 * ¹¦ÄÜ £º
148 * ÊäÈë²ÎÊý £º
149 * Êä³ö²ÎÊý £º
150 * ·µ»Øֵ˵Ã÷ £º
151 * ÆäËû˵Ã÷ £º
152 *****************************************************************************/
153extern void zPHY_emulm_GetMulmTimingStamp(T_zMULM_Timing_Stamp *ptMulmTimingStamp);
154extern void zPHY_emulm_GetMulmMrtrStamp(T_zMULM_Timing_Stamp *ptMulmTimingStamp);
155
156// cym_start: Ôö¼Ó»ñÈ¡Ö÷ÖÆʽÍøÂçʱ¼ä¿ìÕյŦÄܺ¯ÊýÉùÃ÷£¬ 2016-2-1
157void zPHY_emulm_GetMulmLocalStamp(T_zMULM_Timing_Stamp *ptMulmTimingStamp);
158// cym_end
159
160/* »ñÈ¡±äÁ¿µÚbitµÄÖµ£¬±ÈÈçval=0B'01010101, BIT_GET(val, 2) = 0B'1*/
161#define BIT_GET(name, bit) (( (name) >> (bit)) & 0x01)
162
163#if (defined _CHIP_ZX297520)
164#define REG_GSM_LPM_BASE (0x0013F000)
165#elif (defined _CHIP_ZX297520V2) || (defined _CHIP_ZX297520V3)
166#ifdef DDR_BASE_ADDR_LINUX_VA
167#define REG_GSM_LPM_BASE ((unsigned long)ZX_LPM_BASE)
168#else
169#define REG_GSM_LPM_BASE (0x00134000)
170#endif
171#else
172#define REG_GSM_LPM_BASE (0x0013F000)
173#endif
174
175#define REG_LPM_LATCH_ENABLE (*(volatile WORD32*)((REG_GSM_LPM_BASE + 0x60*4)>>CPU_SHIFT))
176#define REG_COUNTER32K_LATCH_T1 (*(volatile WORD32*)((REG_GSM_LPM_BASE + 0x31*4)>>CPU_SHIFT))
177#define REG_COUNTER32K_LATCH_T2 (*(volatile WORD32*)((REG_GSM_LPM_BASE + 0x32*4)>>CPU_SHIFT))
178#define REG_COUNTER32K_LATCH_RESET (*(volatile WORD32*)((REG_GSM_LPM_BASE + 0x33*4)>>CPU_SHIFT))
179
180#define REG_COUNTER32K_LATCH_FLAG (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x34*4)>>CPU_SHIFT))
181#define REG_LTE_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x48*4)>>CPU_SHIFT))
182#define REG_LTE_LOCAL_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x49*4)>>CPU_SHIFT))
183#define REG_LTE_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x58*4)>>CPU_SHIFT))
184#define REG_LTE_LOCAL_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x59*4)>>CPU_SHIFT))
185#define REG_W_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x46*4)>>CPU_SHIFT))
186#define REG_W_LOCAL_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x47*4)>>CPU_SHIFT))
187#define REG_W_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x56*4)>>CPU_SHIFT))
188#define REG_W_LOCAL_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x57*4)>>CPU_SHIFT))
189
190#define REG_TD_RTSFN_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x4a*4)>>CPU_SHIFT))
191#define REG_TD_RTCHIP_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x4b*4)>>CPU_SHIFT))
192#define REG_TD_NTSFN_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x4c*4)>>CPU_SHIFT))
193#define REG_TD_NTCHIP_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x4d*4)>>CPU_SHIFT))
194
195#define REG_TD_RTSFN_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x5a*4)>>CPU_SHIFT))
196#define REG_TD_RTCHIP_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x5b*4)>>CPU_SHIFT))
197#define REG_TD_NTSFN_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x5c*4)>>CPU_SHIFT))
198#define REG_TD_NTCHIP_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x5d*4)>>CPU_SHIFT))
199
200#define REG_GSM_RTFRAME_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x44*4)>>CPU_SHIFT))
201#define REG_GSM_RTTICK_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x45*4)>>CPU_SHIFT))
202#define REG_GSM_RTFRAME_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x54*4)>>CPU_SHIFT))
203#define REG_GSM_RTTICK_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x55*4)>>CPU_SHIFT))
204
205#define REG_GSM_NTFRAME_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x40*4)>>CPU_SHIFT))
206#define REG_GSM_NTTICK_MRTR_LATCH1 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x41*4)>>CPU_SHIFT))
207#define REG_GSM_NTFRAME_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x50*4)>>CPU_SHIFT))
208#define REG_GSM_NTTICK_MRTR_LATCH2 (*(volatile UINT32*)((REG_GSM_LPM_BASE + 0x51*4)>>CPU_SHIFT))
209
210#endif /* _ZX297500_L1_COUNT_LATCH_H */
211
212