| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame^] | 1 | /*******************************************************************************
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| 2 | * Copyright (C) 2014, ZTE Corporation.
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| 3 | *
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| 4 | * File Name: drvs_ADDR_regmap.inc
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| 5 | * File Mark:
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| 6 | * Description: This file contains the register map.
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| 7 | * Others:
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| 8 | * Version: V1.0
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| 9 | * Author: zhangdongdong
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| 10 | * Date: 2015-07-31
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| 11 | * History 1:
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| 12 | *
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| 13 | *********************************************************************************/
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| 14 | #ifndef _DRVS_REGMAP_H
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| 15 | #define _DRVS_REGMAP_H
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| 16 |
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| 17 | /* M2 */
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| 18 | #define ADDR_IROM 0x00000000
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| 19 |
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| 20 | /* M3 */
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| 21 | #define ADDR_IRAM2 0x00080000
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| 22 |
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| 23 | /* M4 -- A1 CFG */
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| 24 | #define ADDR_IRAM1 0x00100000
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| 25 | #define ADDR_KEY 0x00130000
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| 26 | #define ADDR_UART0 0x00131000
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| 27 | #define ADDR_I2C_PMIC 0x00132000
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| 28 | #define ADDR_RTC 0x00133000
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| 29 | #define ADDR_LPM_GSM 0x00134000
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| 30 | #define ADDR_LPM_LTE 0x00134200
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| 31 | #define ADDR_LPM_TD 0x00134400
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| 32 | #define ADDR_LPM_W 0x00134600
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| 33 | #define ADDR_PS_TIMER1 0x00138000
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| 34 | #define ADDR_PS_TIMER2 0x00139000
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| 35 | #define ADDR_PCU 0x0013A000
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| 36 | #define ADDR_TOP_CRM 0x0013B000
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| 37 | #define ADDR_PAD_CTRL_A0 0x0013C000
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| 38 | #define ADDR_GPIO0 0x0013D000
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| 39 | #define ADDR_GPIO1 0x0013E000
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| 40 | #define ADDR_SOC_SYS 0x00140000
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| 41 | #define ADDR_RM_TIMER0 0x00142000
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| 42 | #define ADDR_AP_TIMER1 0x00143000
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| 43 | #define ADDR_AP_TIMER2 0x00144000
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| 44 | #define ADDR_RM_TIMER1 0x00145000
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| 45 | #define ADDR_AP_TIMER3 0x00146000
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| 46 | #define ADDR_PHY_TIMER1 0x00147000
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| 47 | #define ADDR_RM_WDT 0x00148000
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| 48 | #define ADDR_DDR_CTRL 0x00150000
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| 49 | #define ADDR_DDR_PHY 0x00154000
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| 50 | #define ADDR_DDR_FFC 0x00155000
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| 51 | #define ADDR_USIM1 0x00156000
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| 52 | #define ADDR_RM2MATRIX 0x00200000
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| 53 |
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| 54 | #define ADDR_NIC400_MATRIX1_CFG 0x10500000
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| 55 |
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| 56 | /* M2 -- AHB CFG0 */
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| 57 | #define ADDR_EDCP 0x01200000
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| 58 | #define ADDR_SD0 0x01210000
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| 59 | #define ADDR_SD1 0x01211000
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| 60 | #define ADDR_NAND_REG 0x01214000
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| 61 | #define ADDR_NAND_DATA 0x01215000
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| 62 | #define ADDR_EFUSE 0x0121B000
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| 63 | #define ADDR_RSA 0x0121C000
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| 64 | #define ADDR_HASH 0x0121D000
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| 65 | #define ADDR_USB 0x01500000
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| 66 | #define ADDR_HSIC 0x01600000
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| 67 |
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| 68 | /* M2 -- AHB2APB */
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| 69 | #define ADDR_DMA_PHY 0x01300000
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| 70 | #define ADDR_DMA_PS 0x01301000
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| 71 | #define ADDR_ICP 0x01302000
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| 72 | #define ADDR_AP_CPU_SLAVE 0x03000000
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| 73 | #define ADDR_PS_CPU_SLAVE 0x06000000
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| 74 |
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| 75 | /* M2 -- APB LITE 0 */
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| 76 | #define ADDR_PIN_MUX 0x01303000
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| 77 | #define ADDR_SSC 0x01304000
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| 78 | #define ADDR_STD_CRM 0x01306000 /*matrix crm*/
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| 79 | #define ADDR_GMAC 0x01307000
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| 80 | #define ADDR_VOU_CFG 0x01380000
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| 81 |
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| 82 | /* M1 -- LSP */
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| 83 | #define ADDR_LSP_CRM 0x01400000
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| 84 | #define ADDR_LSP_PS_TIMER0 0x01401000
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| 85 | #define ADDR_LSP_PHY_WDT 0x01402000
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| 86 | #define ADDR_LSP_PS_WDT 0x01403000
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| 87 | #define ADDR_LSP_PWM 0x01404000
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| 88 | #define ADDR_LSP_I2S0 0x01405000
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| 89 | #define ADDR_LSP_I2S1 0x01406000
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| 90 | #define ADDR_LSP_SPIFC0 0x01407000
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| 91 | #define ADDR_LSP_UART1 0x01408000
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| 92 | #define ADDR_LSP_I2C1 0x01409000
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| 93 | #define ADDR_LSP_SSP0 0x0140A000
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| 94 | #define ADDR_LSP_PS_RM_TIMER 0x0140B000
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| 95 | #define ADDR_LSP_PHY_TIMER0 0x0140C000
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| 96 | #define ADDR_LSP_UART2 0x0140D000
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| 97 | #define ADDR_LSP_AP_WDT 0x0140E000
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| 98 | #define ADDR_LSP_AP_TIMER0 0x0140F000
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| 99 | #define ADDR_LSP_SSP1 0x01410000
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| 100 | #define ADDR_LSP_AP_TIMER4 0x01411000
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| 101 | #define ADDR_LSP_TDM 0x01412000
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| 102 |
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| 103 | /* DDR */
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| 104 | #define ADDR_DDR_BASE 0x20000000
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| 105 |
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| 106 | /* GSM */
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| 107 | #define ADDR_GSM_CFG 0xF3000000
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| 108 | #define ADDR_GSM_MODEM1 0xF4000000
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| 109 | #define ADDR_GSM_MODEM2 0xF6000000
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| 110 |
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| 111 | /* PHY CPU SALVE */
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| 112 | #define ADDR_PHY_L2TCM 0x600C0000
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| 113 | #define ADDR_PHY_DTCM 0x81000000
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| 114 | #define ADDR_PHY_ITCM 0x81040000
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| 115 | #define ADDR_PHY_CRM 0x81800000
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| 116 | #define ADDR_PHY_ICU 0x81801000
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| 117 |
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| 118 | /* IRAM0 */
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| 119 | #define ADDR_IRAM0 0x82000000
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| 120 |
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| 121 | /* PS MG */
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| 122 | #define ADDR_MG_CRM 0xF2200000
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| 123 |
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| 124 | #define ADDR_MG_GICC 0x02900000
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| 125 | #define ADDR_MG_GICD 0xF2000000
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| 126 | #define ADDR_MG_GICR 0xF2040000
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| 127 |
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| 128 | /*need confirm*/
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| 129 | #define ADDR_MG_CFG 0x00801000
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| 130 | #define ADDR_MG_SCU 0xEF000000
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| 131 |
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| 132 | /* M2 MODEM */
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| 133 | #define ADDR_LTE_MODEM_D 0xF8000000
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| 134 | #define ADDR_WD_MODEM_D 0xF8100000
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| 135 | #define ADDR_TD_MODEM_D 0xF8200000
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| 136 |
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| 137 | /* M1 MODEM */
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| 138 | #define ADDR_LTE_MODEM_C 0xFC000000
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| 139 | #define ADDR_WD_MODEM_C 0xFC100000
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| 140 | #define ADDR_TD_MODEM_C 0xFC200000
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| 141 |
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| 142 | #define ADDR_NIC400_MATRIX0_CFG 0xF7500000
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| 143 |
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| 144 |
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| 145 | #endif
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