| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003-2004 Intel |
| 3 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) |
| 4 | */ |
| 5 | |
| 6 | #ifndef MSI_H |
| 7 | #define MSI_H |
| 8 | |
| 9 | #define msi_control_reg(base) (base + PCI_MSI_FLAGS) |
| 10 | #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) |
| 11 | #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) |
| 12 | #define msi_data_reg(base, is64bit) \ |
| 13 | (base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32)) |
| 14 | #define msi_mask_reg(base, is64bit) \ |
| 15 | (base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32)) |
| 16 | #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) |
| 17 | #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) |
| 18 | |
| 19 | #define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE) |
| 20 | #define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA) |
| 21 | #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) |
| 22 | #define multi_msix_capable(control) msix_table_size((control)) |
| 23 | |
| 24 | #endif /* MSI_H */ |