| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /*******************************************************************************
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| 2 | * °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
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| 3 | *
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| 4 | * ÎļþÃû³Æ£º config.h
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| 5 | * Îļþ±êʶ£º /include/config.h
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| 6 | * ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
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| 7 | * ÆäËü˵Ã÷£º
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| 8 | * µ±Ç°°æ±¾£º 1.0
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| 9 | * ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
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| 10 | * Íê³ÉÈÕÆÚ£º 2010-9-30
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| 11 | *
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| 12 | *
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| 13 | *******************************************************************************/
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| 14 | #ifndef __INCLUDE_CONFIG_H_
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| 15 | #define __INCLUDE_CONFIG_H_
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| 16 | /*********************************************************************************
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| 17 | 1:open 0:close
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| 18 | * ¹¦ÄÜ SIM_EN USE_ASIC SYNC_USB_CTRL SYNC_USB_HSIC SYNC_SETADDRESS
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| 19 | * FPGA 1 0 0 0 0
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| 20 | * usb_ctrlÑéÖ¤ 0 1 1 1 1
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| 21 | * usb_hsicÑéÖ¤ 0 1 1 1 1
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| 22 | * usbtimeoutÑéÖ¤0 1 1 1 1
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| 23 | * asic 1 1 0 0 0
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| 24 | **********************************************************************************/
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| 25 | #define SIM_EN 1
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| 26 | #define USE_ASIC 1
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| 27 | #define SYNC_USB_CTRL 0
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| 28 | #define SYNC_USB_HSIC 0
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| 29 | #define SYNC_SETADDRESS 0
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| 30 |
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| 31 | #if !USE_ASIC ///0:fpga 1:asic
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| 32 | // CPUʱÖÓƵÂÊ
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| 33 | #define SYS_CPU_FREQ 50000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
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| 34 | #define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
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| 35 | #define SYS_UART_CLK_CONFIG_PLL 25000000 // ʱÖÓƵÂÊ
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| 36 | #else
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| 37 | // CPUʱÖÓƵÂÊ
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| 38 | #define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
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| 39 | #define SYS_UART_CLK (26000000/6) // ʱÖÓƵÂÊ
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| 40 | #define SYS_UART_CLK_CONFIG_PLL 104000000 // ʱÖÓƵÂÊ
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| 41 | #define ZX_TOP_CRM_BASE 0x0013B000
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| 42 | #define ZX_SOC_SYS_BASE 0x00140000
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| 43 |
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| 44 | #endif
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| 45 | // Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
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| 46 | #define SYS_BOOTSEL_BASE 0x0013b004 // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
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| 47 |
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| 48 | #define SOC_CRM_BASE (0x0010c000)
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| 49 | #define BOOT_SEL (0x3c)
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| 50 | #define NAND_CFG (0x34)
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| 51 | #define SOC_MOD_CLKEN0 ZX_TOP_CRM_BASE+0x6c
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| 52 | #define SOC_MOD_CLKEN1 ZX_TOP_CRM_BASE+0x6c
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| 53 | #define SOC_MOD_RSTEN ZX_TOP_CRM_BASE + 0x80
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| 54 | #define SOC_MOD_USBSTATECTRL ZX_TOP_CRM_BASE + 0x84
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| 55 | #define SOC_MOD_RSTEN1 (0x0010c064)
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| 56 |
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| 57 | #define CFG_STACK_TOP 0x0008AFE0 // ¶¨ÒåÁËÕ»¶¥
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| 58 |
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| 59 | // UART ²ÎÊý
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| 60 | #define SYS_UART_BASE 0x00102000 // »ùµØÖ·
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| 61 | //#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
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| 62 | #define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
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| 63 | #define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
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| 64 | #if !USE_ASIC
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| 65 | // USB ²ÎÊý
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| 66 | #define SYS_USB_BASE 0x01500000 // »ùµØÖ·
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| 67 | #define SYS_USB_HSIC_BASE 0x01600000 // »ùµØÖ·
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| 68 | #else
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| 69 | #define SYS_USB_BASE 0x01500000 // »ùµØÖ·
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| 70 | #define SYS_USB_HSIC_BASE 0x01600000 // »ùµØÖ·
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| 71 | #endif
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| 72 |
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| 73 |
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| 74 | // NAND FLASH ²ÎÊý
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| 75 | #define SYS_NAND_BASE 0x01207000 // ¼Ä´æÆ÷»ùµØÖ·
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| 76 | #define SYS_NAND_DATA 0x01208000 // Êý¾Ý»ùµØÖ·
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| 77 |
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| 78 | // ͨÓòÎÊý
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| 79 | #define CFG_LOAD_BASE 0x0008B000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
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| 80 | #define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
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| 81 | #define CFG_PRINT_BUF_SIZE 256
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| 82 |
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| 83 | #define POWER_DOMAIN_ISO ZX_SOC_SYS_BASE+0x110
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| 84 | #define POWER_DOMAIN_POWERON ZX_SOC_SYS_BASE+0x114
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| 85 | #define POWER_DOMAIN_RST ZX_SOC_SYS_BASE+0x10C
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| 86 |
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| 87 | //ÑéÖ¤ÐèÒª
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| 88 | #if SYNC_USB_CTRL
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| 89 | #define ARM_PORTA (0x102040)
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| 90 | #endif
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| 91 |
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| 92 | #if SYNC_USB_HSIC
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| 93 | #define REG_GPIO_OUT 0x01400014
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| 94 | #define REG_GPIO_IN 0x01409020
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| 95 | #endif
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| 96 | #endif
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