blob: 2b2cc08db14574bac39131ae42881cb657230a4e [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001/*
2 ***********************************************************
3 */
4
5#include <common.h>
6#include <asm/io.h>
7#include <sdio.h>
8
9#include "efuse.h"
10
11
12
13void efuse_init(void)
14{
15 //start read efuse all 256bit
16 while((REG32(SYS_EFUSE_BASE + 0x4) & 1) == 1);// bit0=1 ctl is busy
17 REG32(SYS_EFUSE_BASE + 0x4) = 1;
18 while((REG32(SYS_EFUSE_BASE + 0x14) & 2) == 0);//bit1=0 read not over
19}
20
21int get_ddr_flag(void)
22{
23 efuse_struct *psEfuseInfo = NULL;
24 int ddr_flag = 0;
25
26
27 psEfuseInfo = (efuse_struct*)EFUSE_RAM_BASE;
28
29 /* get chip flag */
30 if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_WINBD_256M_DDR)
31 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_WINBD_256M_DDR)
32 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_UNILC_256M_DDR)
33 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_UNILC_256M_DDR)
34 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_APM_256M_DDR)
35 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_APM_256M_DDR))
36 {
37 ddr_flag = CHIP_DDR_32M;
38 }
39 else if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_UNILC_512M_DDR)
40 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_APM_512M_DDR)
41 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_GW_ESMT_512M_DDR)
42 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_UNILC_512M_DDR)
43 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_AZW_UNILC_512M_DDR)
44 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_APM_512M_DDR)
45 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECO_ZW_ESMT_512M_DDR))
46 {
47 ddr_flag = CHIP_DDR_64M;
48 }
lh758261d2023-07-13 05:52:04 -070049 else if(((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSC_GW_NYC_2G_DDR)
xf.liaa4d92f2023-09-13 00:18:58 -070050 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOGG_GW_NYC_2G_DDR)
51 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOGG_GW_NYC_NOR_2G_DDR)
52 ||((psEfuseInfo->secure_flag >> 8) == ZX297520V3ECOSC_GW_NYC_NOR_2G_DDR))
lh9ed821d2023-04-07 01:36:19 -070053 {
54 ddr_flag = CHIP_DDR_256M;
55 }
56 else
57 {
58 ddr_flag = CHIP_DDR_128M;
59 }
60
61 return ddr_flag;
62}
63
64int get_secure_verify_status(void)
65{
66 u32 uiLen;
67 efuse_struct *psEfuseInfo = NULL;
68
69 if((REG32(EFUSE_BYPASS) & 1) == 1) //Secure Verify. 1->Disable, 0->Enable.
70 {
71 return SECURE_VERIFY_DISABLE;
72 }
73
74 /*
75 * 0. Èç¹ûsecure flag²»µÈÓÚ0xFF£¬Í˳ö°²È«boot¡£
76 */
77 psEfuseInfo = (efuse_struct*)EFUSE_RAM_BASE;
78 if((psEfuseInfo->secure_flag & 0xFF) != 0xFF)
79 {
80 return SECURE_VERIFY_DISABLE;
81 }
82
83 /*
84 * 1.´ÓefuseÖжÁ³öpuk_hash[127:0], ÅжÏÈç¹ûÈ«²¿Îª0Í˳ö°²È«boot¡£
85 */
86 for(uiLen = 0; uiLen < 4; uiLen++)
87 {
88 if(psEfuseInfo->puk_hash[uiLen] != 0)
89 {
90 break;
91 }
92 if(uiLen == 3)
93 {
94 return SECURE_VERIFY_DISABLE;
95 }
96 }
97 printf("SecureVerify->enable.\n");
98
99 return SECURE_VERIFY_ENABLE;
100}
101
102
103