lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /********************************************************************* |
| 2 | Copyright 2016 by ZXIC Corporation. |
| 3 | * |
| 4 | * FileName:: spifc.c |
| 5 | * File Mark: |
| 6 | * Description: |
| 7 | * Others: |
| 8 | * Version: |
| 9 | * Author: |
| 10 | * Date: |
| 11 | |
| 12 | * History 1: |
| 13 | * Date: |
| 14 | * Version: |
| 15 | * Author: |
| 16 | * Modification: |
| 17 | * History 2: |
| 18 | **********************************************************************/ |
| 19 | #include <common.h> |
| 20 | #include <asm/arch/spifc.h> |
| 21 | #include <asm/io.h> |
| 22 | #include <bbt.h> |
| 23 | |
| 24 | #include "flash.h" |
| 25 | |
| 26 | |
| 27 | static const struct spi_flash_device_para *spi_flash_info = NULL; |
| 28 | /* spi flash parameter config */ |
| 29 | static const struct spi_flash_device_para spi_flash_para[] = { |
| 30 | /* GIGADEVICE GD5F1GQ4R 128MB 1.8V SPI-NAND */ |
| 31 | {0xC8, 0xC1, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 32 | /* GIGADEVICE GD5F1GQ5RExxG 128MB 1.8V SPI-NAND */ |
| 33 | {0xC8, 0x41, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 34 | /* GIGADEVICE GD5F2GQ4R 256MB SPI-NAND */ |
| 35 | {0xC8, 0xC2, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 1}, |
| 36 | /* GIGADEVICE GD5F4GQ4U 512MB SPI-NAND */ |
| 37 | {0xC8, 0xC4, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1}, |
| 38 | /* GIGADEVICE GD5F4GQ6REY2G 512MB SPI-NAND*/ |
| 39 | {0xC8, 0x45, 0x77, 2048, 11, 128, 17, 4096, 0x20000, 1}, |
| 40 | |
| 41 | /* PARAGON PN26Q01AWSIUG 128MB SPI-NAND */ |
| 42 | {0xA1, 0xC1, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 43 | /* PN26Q02AWSIUG 1.8V 2G-BIT SPI NAND */ |
| 44 | {0xA1, 0xC2, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 1}, |
| 45 | |
| 46 | /* HYF1GQ4IAACAE SPI-NAND */ |
| 47 | {0xC9, 0x51, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 48 | /* HYF2GQ4IAACAE SPI-NAND */ |
| 49 | {0xC9, 0x52, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 1}, |
| 50 | /*winbond W25N01G*/ |
| 51 | {0xEF, 0xBA, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 52 | /*winbond W25N02G*/ |
| 53 | {0xEF, 0xBB, 0x77, 2048, 11, 64, 17, 2048, 0x20000, 1}, |
| 54 | /* TOSHIBA TC58CYG0S3HRAIG 128MB SPI-NAND*/ |
| 55 | {0x98, 0xB2, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 56 | /* TOSHIBA TC58CYG1S3HRAIG 256MB SPI-NAND*/ |
| 57 | {0x98, 0xBB, 0x77, 2048, 11, 64, 17, 2048, 0x20000, 1}, |
| 58 | /* ZETTA ZD35X1GAXXX 128MB SPI-NAND*/ |
| 59 | {0xBA, 0x21, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 60 | /* DOSILICON DS35X1GAXXX 128MB SPI-NAND*/ |
| 61 | {0xE5, 0x21, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 62 | /* DOSILICON DS35X12BXXX 64MB SPI-NAND*/ |
| 63 | {0xE5, 0xA5, 0x77, 2048, 11, 128, 17, 512, 0x20000, 1}, |
| 64 | /* FUDANWEI FM25LS01 128MB SPI-NAND*/ |
| 65 | {0xA1, 0xA5, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 66 | /* hosin HG-SPIXGb-1XAIA 128MB SPI-NAND*/ |
| 67 | {0xD6, 0x21, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 68 | /* EMST F50D1G41LB (2M) 128MB SPI-NAND */ |
| 69 | {0xC8, 0x11, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 70 | /* FORESEE F35UQA001G 128MB SPI-NAND */ |
| 71 | {0xCD, 0x61, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 72 | /* FORESEE F35UQA512M 64MB SPI-NAND */ |
| 73 | {0xCD, 0x60, 0x77, 2048, 11, 64, 17, 512, 0x20000, 1}, |
| 74 | /* micron-MT29F2G01ABAGDWB-ITG 256MB SPI-NAND */ |
| 75 | {0x2C, 0x25, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 2}, |
| 76 | /* ESMT F50D44G41XB (2X) 512MB SPI-NAND*/ |
| 77 | {0x2C, 0x35, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1}, |
lh | 758261d | 2023-07-13 05:52:04 -0700 | [diff] [blame] | 78 | /*XTX XT26Q04D 512M SPI-NAND*/ |
| 79 | {0x0B, 0x53, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1}, |
xf.li | aa4d92f | 2023-09-13 00:18:58 -0700 | [diff] [blame^] | 80 | /*UNIM UM19A0LISW 128M SPI-NAND*/ |
| 81 | {0xB0, 0x15, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 82 | {0} |
| 83 | }; |
| 84 | |
| 85 | |
| 86 | /* |
| 87 | ****************************************************************************** |
| 88 | * Function: spifc_enable |
| 89 | * Description: |
| 90 | * Parameters: |
| 91 | * Input: |
| 92 | * Output: |
| 93 | * Returns: |
| 94 | * Others: |
| 95 | ******************************************************************************* |
| 96 | */ |
| 97 | static void spifc_enable(void) |
| 98 | { |
| 99 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 100 | |
| 101 | if( spi->SFC_EN & FC_EN_BACK ) |
| 102 | return; |
| 103 | |
| 104 | spi->SFC_EN |= FC_EN; |
| 105 | spi->SFC_CTRL0 |= FC_SCLK_PAUSE_EN; |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | ****************************************************************************** |
| 110 | * Function: spifc_clear_fifo |
| 111 | * Description: |
| 112 | * Parameters: |
| 113 | * Input: |
| 114 | * Output: |
| 115 | * Returns: |
| 116 | * Others: |
| 117 | ******************************************************************************* |
| 118 | */ |
| 119 | void spifc_clear_fifo( void ) |
| 120 | { |
| 121 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 122 | |
| 123 | spi->SFC_CTRL0 |= (FC_RXFIFO_THRES | FC_TXFIFO_THRES | |
| 124 | FC_RXFIFO_CLR | FC_TXFIFO_CLR); |
| 125 | } |
| 126 | |
| 127 | |
| 128 | /* |
| 129 | ****************************************************************************** |
| 130 | * Function: spifc_setup_cmd |
| 131 | * Description: |
| 132 | * Parameters: |
| 133 | * Input: |
| 134 | * Output: |
| 135 | * Returns: |
| 136 | * Others: |
| 137 | ******************************************************************************* |
| 138 | */ |
| 139 | static void spifc_setup_cmd( struct spiflash_cmd_t *cmd, |
| 140 | uint32_t addr, uint32_t len ) |
| 141 | { |
| 142 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 143 | uint32_t wrap = 0; |
| 144 | uint32_t tmp = 0; |
| 145 | |
| 146 | /* ÃüÁîÂë */ |
| 147 | spi->SFC_INS = cmd->cmd; |
| 148 | |
| 149 | /* Êý¾Ý³¤¶È */ |
| 150 | if( len ) |
| 151 | spi->SFC_BYTE_NUM = len - 1; |
| 152 | else |
| 153 | spi->SFC_BYTE_NUM = 0; |
| 154 | |
| 155 | switch( len ) |
| 156 | { |
| 157 | case 2048: |
| 158 | wrap = WRAP_SIZE_MAIN; |
| 159 | break; |
| 160 | case 2112: |
| 161 | wrap = WRAP_SIZE_MAIN_OOB;; |
| 162 | break; |
| 163 | case 64: |
| 164 | wrap = WRAP_SIZE_OOB;; |
| 165 | break; |
| 166 | default: |
| 167 | wrap = 0; |
| 168 | break; |
| 169 | } |
| 170 | |
| 171 | /* µØÖ·Âë */ |
| 172 | switch( spi->SFC_INS ) |
| 173 | { |
| 174 | case CMD_READ_FROM_CACHE: |
| 175 | // case CMD_READ_FROM_CACHE_X2: |
| 176 | case CMD_READ_FROM_CACHE_X4: |
| 177 | case CMD_READ_FROM_CACHE_QIO: |
| 178 | case CMD_PROGRAM_LOAD: |
| 179 | case CMD_PROGRAM_LOAD_X4: |
| 180 | // case CMD_PROGRAM_LOAD_RANDOM: |
| 181 | // case CMD_PROGRAM_LOAD_RANDOM_X4: |
| 182 | //case CMD_PROGRAM_LOAD_RANDOM_QIO: |
| 183 | addr |= wrap; |
| 184 | break; |
| 185 | |
| 186 | default: |
| 187 | addr = addr; |
| 188 | break; |
| 189 | } |
| 190 | spi->SFC_ADDR = addr; |
| 191 | |
| 192 | /* µØÖ·Âë¡¢¿ÕÖÜÆÚ¡¢¶Á/д ʹÄÜÉèÖà */ |
| 193 | spi->SFC_CTRL1 = 0; |
| 194 | spi->SFC_CTRL1 = ((cmd->addr_tx_en << FC_ADDR_TX_EN) | |
| 195 | (cmd->dumy_tx_en << FC_DUMMY_TX_EN) | |
| 196 | (cmd->data_rx_en << FC_READ_DAT_EN) | |
| 197 | (cmd->data_tx_en << FC_WRITE_DAT_EN)); |
| 198 | |
| 199 | |
| 200 | /* ¿ÕÖÜÆÚÊý¡¢µØÖ·¿í¶È(1£¬2£¬3£¬4×Ö½Ú)¡¢ |
| 201 | * µØÖ·/Êý¾ÝÏß¶È¡¢´«Êäģʽ |
| 202 | */ |
| 203 | #if 0 |
| 204 | tmp = spi->SFC_CTRL2; |
| 205 | tmp &= 0x1f; |
| 206 | tmp |= ((cmd->dumy_bytes << FC_DUMMY_BYTE_NUM) | |
| 207 | (cmd->dumy_bits << FC_DUMMY_BIT_NUM) | |
| 208 | (cmd->addr_width << FC_ADDR_BYTE_NUM)); |
| 209 | spi->SFC_CTRL2 = tmp; |
| 210 | #else |
| 211 | spi->SFC_CTRL2 = 0; |
| 212 | tmp |= ((cmd->dumy_bytes << FC_DUMMY_BYTE_NUM) | |
| 213 | (cmd->dumy_bits << FC_DUMMY_BIT_NUM) | |
| 214 | (cmd->addr_width << FC_ADDR_BYTE_NUM)); |
| 215 | tmp &= ~0x700; |
| 216 | spi->SFC_CTRL2 = tmp; |
| 217 | #endif |
| 218 | |
| 219 | } |
| 220 | |
| 221 | |
| 222 | /* |
| 223 | ****************************************************************************** |
| 224 | * Function: spifc_clear_int |
| 225 | * Description: |
| 226 | * Parameters: |
| 227 | * Input: |
| 228 | * Output: |
| 229 | * Returns: |
| 230 | * Others: |
| 231 | ******************************************************************************* |
| 232 | */ |
| 233 | void spifc_clear_int( void ) |
| 234 | { |
| 235 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 236 | |
| 237 | if(spi->SFC_INT_RAW & 0x2) |
| 238 | printf("\n"); |
| 239 | |
| 240 | spi->SFC_INT_SW_CLR = 0xFF; //clear int ? |
| 241 | } |
| 242 | |
| 243 | |
| 244 | /* |
| 245 | ****************************************************************************** |
| 246 | * Function: spifc_wait_cmd_end |
| 247 | * Description: |
| 248 | * Parameters: |
| 249 | * Input: |
| 250 | * Output: |
| 251 | * Returns: |
| 252 | * Others: |
| 253 | ******************************************************************************* |
| 254 | */ |
| 255 | static int spifc_wait_cmd_end( void ) |
| 256 | { |
| 257 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 258 | uint32_t int_status = 0; |
| 259 | |
| 260 | while(!(spi->SFC_INT_RAW & FC_INT_RAW_MASK)); |
| 261 | |
| 262 | int_status = spi->SFC_INT_RAW; |
| 263 | spi->SFC_INT_SW_CLR = int_status; /* clear intrrupt */ |
| 264 | |
| 265 | if(int_status & FC_INT_RAW_CMD_END) |
| 266 | { |
| 267 | return 0; |
| 268 | } |
| 269 | else |
| 270 | { |
| 271 | printf("intr err.\n"); |
| 272 | return -1; |
| 273 | } |
| 274 | |
| 275 | } |
| 276 | |
| 277 | |
| 278 | /* |
| 279 | ****************************************************************************** |
| 280 | * Function: spifc_read_fifo_one_byte |
| 281 | * Description: |
| 282 | * Parameters: |
| 283 | * Input: |
| 284 | * Output: |
| 285 | * Returns: |
| 286 | * |
| 287 | * Others: only for: |
| 288 | [Instruction] |--addr width is 8 bit |
| 289 | [addr] |--get feature |
| 290 | [data_rx] |
| 291 | ******************************************************************************* |
| 292 | */ |
| 293 | static int spifc_read_fifo_one_byte( uint8_t *value ) |
| 294 | { |
| 295 | uint32_t sw = 0; |
| 296 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 297 | |
| 298 | sw = spi->SFC_SW; |
| 299 | |
| 300 | if( ((sw >> FC_RX_FIFO_CNT) & FC_RX_FIFO_CNT_MASK) != 1 ) |
| 301 | { |
| 302 | return -1; |
| 303 | } |
| 304 | |
| 305 | *value = (uint8_t)spi->SFC_DATA; |
| 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
| 310 | |
| 311 | /* |
| 312 | ****************************************************************************** |
| 313 | * Function: spifc_read_fifo |
| 314 | * Description: |
| 315 | * Parameters: |
| 316 | * Input: |
| 317 | * Output: |
| 318 | * Returns: |
| 319 | * Others: |
| 320 | ******************************************************************************* |
| 321 | */ |
| 322 | static uint32_t spifc_read_fifo( uint32_t len, uint8_t *buf ) |
| 323 | { |
| 324 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 325 | uint32_t *p = (uint32_t *)buf; |
| 326 | uint32_t cnt = 0; |
| 327 | |
| 328 | while(cnt < ((len+3)>>2)) |
| 329 | { |
| 330 | if(spi->SFC_SW & (FC_RX_FIFO_CNT_MASK<<FC_RX_FIFO_CNT))//rx fifo not empty |
| 331 | { |
| 332 | p[cnt++]= spi->SFC_DATA; |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | return (cnt<<2); |
| 337 | } |
| 338 | |
| 339 | |
| 340 | /* |
| 341 | ****************************************************************************** |
| 342 | * Function: spifc_start |
| 343 | * Description: |
| 344 | * Parameters: |
| 345 | * Input: |
| 346 | * Output: |
| 347 | * Returns: |
| 348 | * Others: |
| 349 | ******************************************************************************* |
| 350 | */ |
| 351 | static void spifc_start( void ) |
| 352 | { |
| 353 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 354 | |
| 355 | spi->SFC_START |= FC_START; |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | ****************************************************************************** |
| 360 | * Function: spifc_get_feature |
| 361 | * Description: |
| 362 | * Parameters: |
| 363 | * Input: |
| 364 | * Output: |
| 365 | * Returns: |
| 366 | * |
| 367 | * Others: [Instruction] |--addr width is 8 bit |
| 368 | [addr] |--get feature |
| 369 | [data_rx] |--read id |
| 370 | |
| 371 | ******************************************************************************* |
| 372 | */ |
| 373 | static int spifc_get_feature( uint32_t reg_addr, uint8_t *value) |
| 374 | { |
| 375 | int ret = 0; |
| 376 | |
| 377 | struct spiflash_cmd_t cmd = {CMD_GET_FEATURE, |
| 378 | 1, |
| 379 | FC_ADDR_BYTE_NUM_8, |
| 380 | 0, |
| 381 | 1, |
| 382 | 0, |
| 383 | 0, |
| 384 | 0 |
| 385 | }; |
| 386 | |
| 387 | spifc_clear_fifo(); |
| 388 | spifc_clear_int(); |
| 389 | |
| 390 | spifc_setup_cmd(&cmd, reg_addr, 1); |
| 391 | spifc_start(); |
| 392 | ret = spifc_wait_cmd_end(); |
| 393 | if(ret != 0) |
| 394 | { |
| 395 | return ret; |
| 396 | } |
| 397 | |
| 398 | ret = spifc_read_fifo_one_byte(value); |
| 399 | if(ret != 0) |
| 400 | { |
| 401 | return ret; |
| 402 | } |
| 403 | |
| 404 | return 0; |
| 405 | } |
| 406 | |
| 407 | /* |
| 408 | ****************************************************************************** |
| 409 | * Function: spifc_read_id |
| 410 | * Description: |
| 411 | * Parameters: |
| 412 | * Input: |
| 413 | * Output: |
| 414 | * Returns: |
| 415 | * |
| 416 | * Others: [Instruction] |--addr width is 8 bit |
| 417 | [addr] |--get feature |
| 418 | [data_rx] |--read id |
| 419 | ******************************************************************************* |
| 420 | */ |
| 421 | static int spifc_read_id(uint32_t reg_addr, uint8_t *value, uint8_t len) |
| 422 | { |
| 423 | int ret = 0; |
| 424 | |
| 425 | struct spiflash_cmd_t cmd = { CMD_READ_ID, |
| 426 | 1, |
| 427 | FC_ADDR_BYTE_NUM_8, |
| 428 | 0, |
| 429 | 1, |
| 430 | 0, |
| 431 | 0, |
| 432 | 0 |
| 433 | }; |
| 434 | |
| 435 | spifc_clear_fifo(); |
| 436 | spifc_clear_int(); |
| 437 | spifc_setup_cmd(&cmd, reg_addr, len); |
| 438 | spifc_start(); |
| 439 | ret = spifc_wait_cmd_end(); |
| 440 | if(ret != 0) |
| 441 | { |
| 442 | return ret; |
| 443 | } |
| 444 | |
| 445 | ret = spifc_read_fifo(len, value); |
| 446 | if(ret != 0) |
| 447 | { |
| 448 | return ret; |
| 449 | } |
| 450 | |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | |
| 455 | /* |
| 456 | ****************************************************************************** |
| 457 | * Function: spifc_read_page_to_cache |
| 458 | * Description: |
| 459 | * Parameters: |
| 460 | * Input: |
| 461 | * Output: |
| 462 | * Returns: |
| 463 | * Others: [Instruction] |--addr width is 24 bit(page/block addr!!!!) |
| 464 | [addr] |--page read |
| 465 | |--block erase |
| 466 | |--program execute |
| 467 | ******************************************************************************* |
| 468 | */ |
| 469 | static int spifc_read_page_to_cache(uint32_t page_addr) |
| 470 | { |
| 471 | int ret = 0; |
| 472 | uint8_t status = 0; |
| 473 | |
| 474 | struct spiflash_cmd_t cmd = { CMD_READ_PAGE_TO_CACHE, |
| 475 | 1, |
| 476 | FC_ADDR_BYTE_NUM_24, |
| 477 | 0, |
| 478 | 0, |
| 479 | 0, |
| 480 | 0, |
| 481 | 0 |
| 482 | }; |
| 483 | |
| 484 | spifc_clear_fifo(); |
| 485 | spifc_clear_int(); |
| 486 | spifc_setup_cmd(&cmd, page_addr, 0); |
| 487 | spifc_start(); |
| 488 | ret = spifc_wait_cmd_end(); |
| 489 | if(ret != 0) |
| 490 | { |
| 491 | return ret; |
| 492 | } |
| 493 | |
| 494 | do |
| 495 | { |
| 496 | spifc_get_feature(REG_STATUS, &status); |
| 497 | }while( status & OIP); |
| 498 | |
| 499 | return 0; |
| 500 | } |
| 501 | |
| 502 | /* |
| 503 | ****************************************************************************** |
| 504 | * Function: spifc_read_from_cache |
| 505 | * Description: |
| 506 | * Parameters: |
| 507 | * Input: |
| 508 | * Output: |
| 509 | * Returns: |
| 510 | * Others: [Instruction] |--addr width is 16 bit |
| 511 | [addr] |--dummy cycel 8/4/2 |
| 512 | [dummy] |--read form cache(X1,X2,X4) |
| 513 | [data_rx] |--read form cache(dual,quad)IO |
| 514 | ******************************************************************************* |
| 515 | */ |
| 516 | static int spifc_read_from_cache(uint32_t column_addr, uint32_t len, uint8_t *buf) |
| 517 | { |
| 518 | int ret = 0; |
| 519 | |
| 520 | uint32_t len_tmp = 0; |
| 521 | struct spiflash_cmd_t cmd; |
| 522 | |
| 523 | cmd.cmd = CMD_READ_FROM_CACHE; |
| 524 | cmd.dumy_bytes = 1; |
| 525 | cmd.dumy_bits = 0; |
| 526 | cmd.addr_tx_en = 1; |
| 527 | cmd.addr_width = FC_ADDR_BYTE_NUM_16; |
| 528 | cmd.data_tx_en = 0; |
| 529 | cmd.data_rx_en = 1; |
| 530 | cmd.dumy_tx_en = 1; |
| 531 | |
| 532 | spifc_clear_fifo(); |
| 533 | spifc_clear_int(); |
| 534 | spifc_setup_cmd(&cmd, column_addr, len); |
| 535 | spifc_start(); |
| 536 | |
| 537 | len_tmp = spifc_read_fifo(len, buf); |
| 538 | if( len_tmp != len ) |
| 539 | { |
| 540 | ret = -2; |
| 541 | return ret; |
| 542 | } |
| 543 | |
| 544 | ret = spifc_wait_cmd_end(); |
| 545 | if( ret != 0 ) |
| 546 | { |
| 547 | return ret; |
| 548 | } |
| 549 | |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | |
| 554 | /* |
| 555 | ****************************************************************************** |
| 556 | * Function: nand_read_oob |
| 557 | * Description: |
| 558 | * Parameters: |
| 559 | * Input: |
| 560 | * Output: |
| 561 | * Returns: |
| 562 | * Others: |
| 563 | ******************************************************************************* |
| 564 | */ |
| 565 | void spifc_read_oob(uint8_t *buf, uint32_t offset, uint32_t len) |
| 566 | { |
| 567 | uint32_t column_offset = spi_flash_info->page_size; |
| 568 | uint32_t page = offset >> (spi_flash_info->page_size_shift); |
| 569 | uint32_t blocks = offset >> (spi_flash_info->block_size_shift); |
| 570 | |
| 571 | spifc_read_page_to_cache(page); |
| 572 | |
| 573 | if((spi_flash_info->planes == 2) && ((blocks%2) != 0)) |
| 574 | { |
| 575 | column_offset |= (0x1 << 12); |
| 576 | } |
| 577 | spifc_read_from_cache(column_offset, spi_flash_info->oob_size, buf); |
| 578 | } |
| 579 | |
| 580 | |
| 581 | /* |
| 582 | ****************************************************************************** |
| 583 | * Function: read_page |
| 584 | * Description: |
| 585 | * Parameters: |
| 586 | * Input: |
| 587 | * Output: |
| 588 | * Returns: |
| 589 | * Others: |
| 590 | ******************************************************************************* |
| 591 | */ |
| 592 | int32_t spifc_read_page(uint32_t buf, uint32_t offset) |
| 593 | { |
| 594 | int ret = 0; |
| 595 | uint8_t feature = 0x0; |
| 596 | |
| 597 | uint32_t page = offset >> (spi_flash_info->page_size_shift); |
| 598 | uint32_t blocks = offset >> (spi_flash_info->block_size_shift); |
| 599 | uint32_t column_offset = 0; |
| 600 | |
| 601 | if( (buf & 0x3) != 0 ) /* DMAµØÖ·ÒªÇó4×Ö½Ú¶ÔÆë */ |
| 602 | { |
| 603 | printf("addr err.\n"); |
| 604 | return -1; |
| 605 | } |
| 606 | |
| 607 | ret = spifc_read_page_to_cache(page); |
| 608 | if( ret != 0 ) |
| 609 | return ret; |
| 610 | |
| 611 | ret = spifc_get_feature(REG_STATUS, &feature); |
| 612 | if(ret != 0) |
| 613 | return ret; |
| 614 | |
| 615 | if((feature>>ECC_ERR_BIT & 0x3) == 0x2) |
| 616 | { |
| 617 | printf("ecc err.\n"); |
| 618 | return -1; |
| 619 | } |
| 620 | if((spi_flash_info->planes == 2) && ((blocks%2) != 0)) |
| 621 | { |
| 622 | column_offset |= (0x1 << 12); |
| 623 | } |
| 624 | ret = spifc_read_from_cache(column_offset, spi_flash_info->page_size, (uint8_t *)buf); |
| 625 | if(ret != 0) |
| 626 | return ret; |
| 627 | |
| 628 | return 0; |
| 629 | } |
| 630 | |
| 631 | /* |
| 632 | ****************************************************************************** |
| 633 | * Function: read_page |
| 634 | * Description: |
| 635 | * Parameters: |
| 636 | * Input: |
| 637 | * Output: |
| 638 | * Returns: |
| 639 | * Others: |
| 640 | ******************************************************************************* |
| 641 | */ |
| 642 | int32_t spifc_read_page_raw(uint32_t buf, uint32_t offset) |
| 643 | { |
| 644 | int ret = 0; |
| 645 | uint8_t feature = 0x0; |
| 646 | |
| 647 | uint32_t page = offset >> (spi_flash_info->page_size_shift); |
| 648 | |
| 649 | if( (buf & 0x3) != 0 ) /* DMAµØÖ·ÒªÇó4×Ö½Ú¶ÔÆë */ |
| 650 | { |
| 651 | printf("addr err.\n"); |
| 652 | return -1; |
| 653 | } |
| 654 | |
| 655 | ret = spifc_read_page_to_cache(page); |
| 656 | if( ret != 0 ) |
| 657 | return ret; |
| 658 | |
| 659 | ret = spifc_read_from_cache(0, spi_flash_info->page_size, (uint8_t *)buf); |
| 660 | if(ret != 0) |
| 661 | return ret; |
| 662 | |
| 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | |
| 667 | /* |
| 668 | ****************************************************************************** |
| 669 | * Function: nand_read |
| 670 | * Description: |
| 671 | * Parameters: |
| 672 | * Input: |
| 673 | * Output: |
| 674 | * Returns: |
| 675 | * Others: from: must page align len: must page align |
| 676 | ******************************************************************************* |
| 677 | */ |
| 678 | int32_t spifc_read(uint32_t from, uint32_t len, uint32_t to) |
| 679 | { |
| 680 | uint32_t offset = from; |
| 681 | uint32_t left_to_read = len; |
| 682 | uint32_t p_to = to; |
| 683 | int32_t ret = 0; |
| 684 | int32_t page_size = (spi_flash_info->page_size); |
| 685 | |
| 686 | if((offset & (page_size - 1)) || (len & (page_size - 1)) ) |
| 687 | { |
| 688 | return -1; |
| 689 | } |
| 690 | |
| 691 | while( left_to_read > 0 ) |
| 692 | { |
| 693 | ret = spifc_read_page(p_to, offset); |
| 694 | if(ret != 0) |
| 695 | { |
| 696 | return -1; |
| 697 | } |
| 698 | |
| 699 | left_to_read -= page_size; |
| 700 | offset += page_size; |
| 701 | p_to += page_size; |
| 702 | } |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | |
| 707 | /******************************************************************************* |
| 708 | * Function: nand_read_id |
| 709 | * Description: |
| 710 | * Parameters: |
| 711 | * Input: |
| 712 | * |
| 713 | * Output: |
| 714 | * |
| 715 | * Returns: |
| 716 | * |
| 717 | * |
| 718 | * Others: |
| 719 | ********************************************************************************/ |
| 720 | int32_t read_id (void) |
| 721 | { |
| 722 | uint8_t id[4]; |
| 723 | const struct spi_flash_device_para *spi_flash = &spi_flash_para[0]; |
| 724 | |
| 725 | spifc_read_id(0x0, id, 2); |
| 726 | |
| 727 | while( spi_flash->manuf_id != 0 ) |
| 728 | { |
| 729 | if( ((uint8_t)id[0] == spi_flash->manuf_id) && |
| 730 | ((uint8_t)id[1] == spi_flash->device_id) ) |
| 731 | { |
| 732 | spi_flash_info = spi_flash; |
| 733 | return 0; |
| 734 | }; |
| 735 | spi_flash++; |
| 736 | } |
| 737 | |
| 738 | return -1; |
| 739 | } |
| 740 | |
| 741 | /******************************************************************************* |
| 742 | * Function: |
| 743 | * Description: |
| 744 | * Parameters: |
| 745 | * Input: |
| 746 | * |
| 747 | * Output: |
| 748 | * |
| 749 | * Returns: |
| 750 | * |
| 751 | * |
| 752 | * Others: |
| 753 | ********************************************************************************/ |
| 754 | int32_t read_data(uint32_t from, uint32_t len, uint32_t to) |
| 755 | { |
| 756 | uint32_t offset = from; |
| 757 | uint32_t left_to_read = len; |
| 758 | uint32_t p_to = to; |
| 759 | int32_t ret = 0; |
| 760 | int32_t block_size = (spi_flash_info->block_size); |
| 761 | |
| 762 | while(left_to_read > 0) |
| 763 | { |
| 764 | uint32_t block_offset = offset & (block_size - 1); |
| 765 | uint32_t read_length; |
| 766 | |
| 767 | if( nand_block_isbad(offset) ) |
| 768 | { |
| 769 | offset += block_size; |
| 770 | continue; |
| 771 | } |
| 772 | |
| 773 | if (left_to_read < (block_size - block_offset)) |
| 774 | read_length = left_to_read; |
| 775 | else |
| 776 | read_length = block_size - block_offset; |
| 777 | |
| 778 | ret = spifc_read(offset, read_length, p_to); |
| 779 | if(ret != 0) |
| 780 | { |
| 781 | return -1; |
| 782 | } |
| 783 | |
| 784 | left_to_read -= read_length; |
| 785 | offset += read_length; |
| 786 | p_to += read_length; |
| 787 | } |
| 788 | |
| 789 | return 0; |
| 790 | } |
| 791 | |
| 792 | /******************************************************************************* |
| 793 | * Function: nand_init |
| 794 | * Description: |
| 795 | * Parameters: |
| 796 | * Input: |
| 797 | * |
| 798 | * Output: |
| 799 | * |
| 800 | * Returns: |
| 801 | * |
| 802 | * |
| 803 | * Others: |
| 804 | ********************************************************************************/ |
| 805 | int32_t spifc_init (void) |
| 806 | { |
| 807 | int32_t ret = 0; |
| 808 | spifc_enable(); |
| 809 | ret = read_id(); |
| 810 | if(ret != 0) |
| 811 | { |
| 812 | printf("id err!\n"); |
| 813 | return -1; |
| 814 | } |
| 815 | |
| 816 | flash.flash_type = SPI_NAND_BOOT; |
| 817 | flash.manuf_id = spi_flash_info->manuf_id; |
| 818 | flash.device_id = spi_flash_info->device_id; |
| 819 | flash.page_size = spi_flash_info->page_size; |
| 820 | flash.page_size_shift = spi_flash_info->page_size_shift; |
| 821 | flash.oob_size = spi_flash_info->oob_size; |
| 822 | flash.block_size = spi_flash_info->block_size; |
| 823 | flash.block_size_shift = spi_flash_info->block_size_shift; |
| 824 | flash.block_num = spi_flash_info->block_num; |
| 825 | flash.read_page_raw = spifc_read_page_raw; |
| 826 | flash.read_oob = spifc_read_oob; |
| 827 | flash.read = read_data; |
| 828 | |
| 829 | return 0; |
| 830 | |
| 831 | } |
| 832 | |
| 833 | /* |
| 834 | ****************************************************************************** |
| 835 | * Function: |
| 836 | * Description: |
| 837 | * Parameters: |
| 838 | * Input: |
| 839 | * Output: |
| 840 | * Returns: |
| 841 | * Others: |
| 842 | ******************************************************************************* |
| 843 | */ |
| 844 | int board_flash_init(void) |
| 845 | { |
| 846 | int ret = 0; |
| 847 | char boot_mode = 0; |
| 848 | |
| 849 | printf("spi-nand:"); |
| 850 | |
| 851 | boot_mode = get_boot_mode(); |
xf.li | aa4d92f | 2023-09-13 00:18:58 -0700 | [diff] [blame^] | 852 | #if defined(CONFIG_ZX297520V3E_VEHICLE_DC) || defined(CONFIG_ZX297520V3E_VEHICLE_DC_REF) |
| 853 | if(boot_mode == NOR_BOOT) |
| 854 | { |
| 855 | writel(CFG_START_MODE_SPI_NAND, CFG_BOOT_MODE_START_MODE_FOR_UBOOT); |
| 856 | return 0; |
| 857 | } |
| 858 | #else |
lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 859 | if(boot_mode != SPI_NAND_BOOT) |
| 860 | { |
| 861 | printf("mode err.\n"); |
| 862 | return -1; |
| 863 | } |
xf.li | aa4d92f | 2023-09-13 00:18:58 -0700 | [diff] [blame^] | 864 | #endif |
lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 865 | writel(CFG_START_MODE_SPI_NAND, CFG_BOOT_MODE_START_MODE_FOR_UBOOT); |
| 866 | ret = spifc_init(); |
| 867 | if(ret != 0) |
| 868 | { |
| 869 | printf("init err.\n"); |
| 870 | return -1; |
| 871 | } |
| 872 | printf("init ok.\n"); |
| 873 | |
| 874 | // nand_creat_bbt(); |
| 875 | nand_creat_ram_bbt(); |
| 876 | |
| 877 | return 0; |
| 878 | } |
| 879 | |
| 880 | |