| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | ;--------------------------------------------------------------------------
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| 2 | ; Initialize SERIAL 0 as console for zx297520v3_fpga linux: 115200 8/N/1
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| 3 | ; created by xuzhiguo / ZTE-TSP at 03.18.2013
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| 4 | ;--------------------------------------------------------------------------
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| 5 | &UART_BASE_SYS=0x1408000 // UART1 Base Address
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| 6 |
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| 7 | &DBGU_DR=&UART_BASE_SYS+0x4 // data Register
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| 8 | &DBGU_SC=&UART_BASE_SYS+0x8 // special character Register
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| 9 | &DBGU_FR=&UART_BASE_SYS+0x14 // flag Register
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| 10 | &DBGU_IBRD=&UART_BASE_SYS+0x24 // integer Baud Rate Generator Register
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| 11 | &DBGU_FBRD=&UART_BASE_SYS+0x28 // fractional Baud Rate Generator Register
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| 12 | &DBGU_LCR_H=&UART_BASE_SYS+0x30 // Line Control Register
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| 13 | &DBGU_CR=&UART_BASE_SYS+0x34 // Control Register
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| 14 | &DBGU_IMSC=&UART_BASE_SYS+0x40 // Interrupt Mask Register
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| 15 |
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| 16 | &TOP_FUNC_SEL_BASE=0x0013C000 // 0-AON FUNC
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| 17 | &AON_FUNC_SEL_BASE=0x0013C000 // 0-rxd or txd func
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| 18 | &UART0_TOP_FUNC=&TOP_FUNC_SEL_BASE+0x10
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| 19 | &UART0_AON_FUNC=&AON_FUNC_SEL_BASE+0
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| 20 |
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| 21 | // set gpio function to UART0 TX and RX
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| 22 | ;&tmp=data.long(D:&UART0_TOP_FUNC)
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| 23 | ;&tmp=&tmp&0xFFE7FFFF // AON func
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| 24 | ;&tmp=data.long(D:&UART0_AON_FUNC)
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| 25 | ;&tmp=&tmp&0xFFFF0FFF // UART FUNC
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| 26 |
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| 27 | //set uart1 works clock divison to 1
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| 28 | ; it is done in evb297510.cmm
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| 29 |
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| 30 | //disable uart
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| 31 | data.set &DBGU_CR %LONG 0x0
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| 32 |
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| 33 | // mask all interrupt
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| 34 | data.set &DBGU_IMSC %LONG 0x0
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| 35 |
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| 36 | // Set baud rate 115200
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| 37 | data.set &DBGU_IBRD %LONG 0xD //on FPGA platform, uart work clock is 25MHz
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| 38 | data.set &DBGU_FBRD %LONG 0x24
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| 39 |
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| 40 | // set the port to no parity, no loopback, 8/N/1, enable FIFO
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| 41 | data.set &DBGU_LCR_H %LONG 0x70
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| 42 |
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| 43 | // Enable
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| 44 | data.set &DBGU_CR %LONG 0x301
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| 45 |
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| 46 | print "printing 'UART OK' on console"
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| 47 | data.set &DBGU_DR %BYTE 0x0a //next line
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| 48 | wait 10.ms
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| 49 | data.set &DBGU_DR %BYTE 0x0d //enter
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| 50 | wait 10.ms
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| 51 | data.set &DBGU_DR %BYTE 0x55 //U
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| 52 | wait 10.ms
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| 53 | data.set &DBGU_DR %BYTE 0x41 //A
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| 54 | wait 10.ms
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| 55 | data.set &DBGU_DR %BYTE 0x52 //R
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| 56 | wait 10.ms
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| 57 | data.set &DBGU_DR %BYTE 0x54 //T
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| 58 | wait 10.ms
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| 59 | data.set &DBGU_DR %BYTE 0x20 //space
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| 60 | wait 10.ms
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| 61 | data.set &DBGU_DR %BYTE 0x4f //O
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| 62 | wait 10.ms
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| 63 | data.set &DBGU_DR %BYTE 0x4b //K
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| 64 | wait 10.ms
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| 65 | data.set &DBGU_DR %BYTE 0x0a //next line
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| 66 | wait 10.ms
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| 67 | data.set &DBGU_DR %BYTE 0x0d //enter
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| 68 | wait 10.ms
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| 69 |
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| 70 | enddo
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| 71 |
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