lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /********************************************************************* |
| 2 | Copyright 2016 by ZXIC Corporation. |
| 3 | * |
| 4 | * FileName:: spifc.c |
| 5 | * File Mark: |
| 6 | * Description: |
| 7 | * Others: |
| 8 | * Version: |
| 9 | * Author: |
| 10 | * Date: |
| 11 | |
| 12 | * History 1: |
| 13 | * Date: |
| 14 | * Version: |
| 15 | * Author: |
| 16 | * Modification: |
| 17 | * History 2: |
| 18 | **********************************************************************/ |
| 19 | #include <common.h> |
| 20 | #include <asm/arch/spifc.h> |
| 21 | #include <asm/io.h> |
| 22 | #include <bbt.h> |
| 23 | |
| 24 | #include "flash.h" |
| 25 | |
| 26 | |
| 27 | static const struct spi_flash_device_para *spi_flash_info = NULL; |
| 28 | /* spi flash parameter config */ |
| 29 | static const struct spi_flash_device_para spi_flash_para[] = { |
| 30 | /* GIGADEVICE GD5F1GQ4R 128MB 1.8V SPI-NAND */ |
| 31 | {0xC8, 0xC1, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 32 | /* GIGADEVICE GD5F1GQ5RExxG 128MB 1.8V SPI-NAND */ |
| 33 | {0xC8, 0x41, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 34 | /* GIGADEVICE GD5F2GQ4R 256MB SPI-NAND */ |
| 35 | {0xC8, 0xC2, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 1}, |
| 36 | /* GIGADEVICE GD5F4GQ4U 512MB SPI-NAND */ |
| 37 | {0xC8, 0xC4, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1}, |
| 38 | /* GIGADEVICE GD5F4GQ6REY2G 512MB SPI-NAND*/ |
| 39 | {0xC8, 0x45, 0x77, 2048, 11, 128, 17, 4096, 0x20000, 1}, |
| 40 | |
| 41 | /* PARAGON PN26Q01AWSIUG 128MB SPI-NAND */ |
| 42 | {0xA1, 0xC1, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 43 | /* PN26Q02AWSIUG 1.8V 2G-BIT SPI NAND */ |
| 44 | {0xA1, 0xC2, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 1}, |
| 45 | |
| 46 | /* HYF1GQ4IAACAE SPI-NAND */ |
| 47 | {0xC9, 0x51, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 48 | /* HYF2GQ4IAACAE SPI-NAND */ |
| 49 | {0xC9, 0x52, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 1}, |
| 50 | /*winbond W25N01G*/ |
| 51 | {0xEF, 0xBA, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 52 | /*winbond W25N02G*/ |
| 53 | {0xEF, 0xBB, 0x77, 2048, 11, 64, 17, 2048, 0x20000, 1}, |
| 54 | /* TOSHIBA TC58CYG0S3HRAIG 128MB SPI-NAND*/ |
| 55 | {0x98, 0xB2, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 56 | /* TOSHIBA TC58CYG1S3HRAIG 256MB SPI-NAND*/ |
| 57 | {0x98, 0xBB, 0x77, 2048, 11, 64, 17, 2048, 0x20000, 1}, |
| 58 | /* ZETTA ZD35X1GAXXX 128MB SPI-NAND*/ |
| 59 | {0xBA, 0x21, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 60 | /* DOSILICON DS35X1GAXXX 128MB SPI-NAND*/ |
| 61 | {0xE5, 0x21, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 62 | /* DOSILICON DS35X12BXXX 64MB SPI-NAND*/ |
| 63 | {0xE5, 0xA5, 0x77, 2048, 11, 128, 17, 512, 0x20000, 1}, |
| 64 | /* FUDANWEI FM25LS01 128MB SPI-NAND*/ |
| 65 | {0xA1, 0xA5, 0x77, 2048, 11, 128, 17, 1024, 0x20000, 1}, |
| 66 | /* hosin HG-SPIXGb-1XAIA 128MB SPI-NAND*/ |
| 67 | {0xD6, 0x21, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 68 | /* EMST F50D1G41LB (2M) 128MB SPI-NAND */ |
| 69 | {0xC8, 0x11, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 70 | /* FORESEE F35UQA001G 128MB SPI-NAND */ |
| 71 | {0xCD, 0x61, 0x77, 2048, 11, 64, 17, 1024, 0x20000, 1}, |
| 72 | /* FORESEE F35UQA512M 64MB SPI-NAND */ |
| 73 | {0xCD, 0x60, 0x77, 2048, 11, 64, 17, 512, 0x20000, 1}, |
| 74 | /* micron-MT29F2G01ABAGDWB-ITG 256MB SPI-NAND */ |
| 75 | {0x2C, 0x25, 0x77, 2048, 11, 128, 17, 2048, 0x20000, 2}, |
| 76 | /* ESMT F50D44G41XB (2X) 512MB SPI-NAND*/ |
| 77 | {0x2C, 0x35, 0x77, 4096, 12, 256, 18, 2048, 0x40000, 1}, |
| 78 | {0} |
| 79 | }; |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | ****************************************************************************** |
| 84 | * Function: spifc_enable |
| 85 | * Description: |
| 86 | * Parameters: |
| 87 | * Input: |
| 88 | * Output: |
| 89 | * Returns: |
| 90 | * Others: |
| 91 | ******************************************************************************* |
| 92 | */ |
| 93 | static void spifc_enable(void) |
| 94 | { |
| 95 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 96 | |
| 97 | if( spi->SFC_EN & FC_EN_BACK ) |
| 98 | return; |
| 99 | |
| 100 | spi->SFC_EN |= FC_EN; |
| 101 | spi->SFC_CTRL0 |= FC_SCLK_PAUSE_EN; |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | ****************************************************************************** |
| 106 | * Function: spifc_clear_fifo |
| 107 | * Description: |
| 108 | * Parameters: |
| 109 | * Input: |
| 110 | * Output: |
| 111 | * Returns: |
| 112 | * Others: |
| 113 | ******************************************************************************* |
| 114 | */ |
| 115 | void spifc_clear_fifo( void ) |
| 116 | { |
| 117 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 118 | |
| 119 | spi->SFC_CTRL0 |= (FC_RXFIFO_THRES | FC_TXFIFO_THRES | |
| 120 | FC_RXFIFO_CLR | FC_TXFIFO_CLR); |
| 121 | } |
| 122 | |
| 123 | |
| 124 | /* |
| 125 | ****************************************************************************** |
| 126 | * Function: spifc_setup_cmd |
| 127 | * Description: |
| 128 | * Parameters: |
| 129 | * Input: |
| 130 | * Output: |
| 131 | * Returns: |
| 132 | * Others: |
| 133 | ******************************************************************************* |
| 134 | */ |
| 135 | static void spifc_setup_cmd( struct spiflash_cmd_t *cmd, |
| 136 | uint32_t addr, uint32_t len ) |
| 137 | { |
| 138 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 139 | uint32_t wrap = 0; |
| 140 | uint32_t tmp = 0; |
| 141 | |
| 142 | /* ÃüÁîÂë */ |
| 143 | spi->SFC_INS = cmd->cmd; |
| 144 | |
| 145 | /* Êý¾Ý³¤¶È */ |
| 146 | if( len ) |
| 147 | spi->SFC_BYTE_NUM = len - 1; |
| 148 | else |
| 149 | spi->SFC_BYTE_NUM = 0; |
| 150 | |
| 151 | switch( len ) |
| 152 | { |
| 153 | case 2048: |
| 154 | wrap = WRAP_SIZE_MAIN; |
| 155 | break; |
| 156 | case 2112: |
| 157 | wrap = WRAP_SIZE_MAIN_OOB;; |
| 158 | break; |
| 159 | case 64: |
| 160 | wrap = WRAP_SIZE_OOB;; |
| 161 | break; |
| 162 | default: |
| 163 | wrap = 0; |
| 164 | break; |
| 165 | } |
| 166 | |
| 167 | /* µØÖ·Âë */ |
| 168 | switch( spi->SFC_INS ) |
| 169 | { |
| 170 | case CMD_READ_FROM_CACHE: |
| 171 | // case CMD_READ_FROM_CACHE_X2: |
| 172 | case CMD_READ_FROM_CACHE_X4: |
| 173 | case CMD_READ_FROM_CACHE_QIO: |
| 174 | case CMD_PROGRAM_LOAD: |
| 175 | case CMD_PROGRAM_LOAD_X4: |
| 176 | // case CMD_PROGRAM_LOAD_RANDOM: |
| 177 | // case CMD_PROGRAM_LOAD_RANDOM_X4: |
| 178 | //case CMD_PROGRAM_LOAD_RANDOM_QIO: |
| 179 | addr |= wrap; |
| 180 | break; |
| 181 | |
| 182 | default: |
| 183 | addr = addr; |
| 184 | break; |
| 185 | } |
| 186 | spi->SFC_ADDR = addr; |
| 187 | |
| 188 | /* µØÖ·Âë¡¢¿ÕÖÜÆÚ¡¢¶Á/д ʹÄÜÉèÖà */ |
| 189 | spi->SFC_CTRL1 = 0; |
| 190 | spi->SFC_CTRL1 = ((cmd->addr_tx_en << FC_ADDR_TX_EN) | |
| 191 | (cmd->dumy_tx_en << FC_DUMMY_TX_EN) | |
| 192 | (cmd->data_rx_en << FC_READ_DAT_EN) | |
| 193 | (cmd->data_tx_en << FC_WRITE_DAT_EN)); |
| 194 | |
| 195 | |
| 196 | /* ¿ÕÖÜÆÚÊý¡¢µØÖ·¿í¶È(1£¬2£¬3£¬4×Ö½Ú)¡¢ |
| 197 | * µØÖ·/Êý¾ÝÏß¶È¡¢´«Êäģʽ |
| 198 | */ |
| 199 | #if 0 |
| 200 | tmp = spi->SFC_CTRL2; |
| 201 | tmp &= 0x1f; |
| 202 | tmp |= ((cmd->dumy_bytes << FC_DUMMY_BYTE_NUM) | |
| 203 | (cmd->dumy_bits << FC_DUMMY_BIT_NUM) | |
| 204 | (cmd->addr_width << FC_ADDR_BYTE_NUM)); |
| 205 | spi->SFC_CTRL2 = tmp; |
| 206 | #else |
| 207 | spi->SFC_CTRL2 = 0; |
| 208 | tmp |= ((cmd->dumy_bytes << FC_DUMMY_BYTE_NUM) | |
| 209 | (cmd->dumy_bits << FC_DUMMY_BIT_NUM) | |
| 210 | (cmd->addr_width << FC_ADDR_BYTE_NUM)); |
| 211 | tmp &= ~0x700; |
| 212 | spi->SFC_CTRL2 = tmp; |
| 213 | #endif |
| 214 | |
| 215 | } |
| 216 | |
| 217 | |
| 218 | /* |
| 219 | ****************************************************************************** |
| 220 | * Function: spifc_clear_int |
| 221 | * Description: |
| 222 | * Parameters: |
| 223 | * Input: |
| 224 | * Output: |
| 225 | * Returns: |
| 226 | * Others: |
| 227 | ******************************************************************************* |
| 228 | */ |
| 229 | void spifc_clear_int( void ) |
| 230 | { |
| 231 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 232 | |
| 233 | if(spi->SFC_INT_RAW & 0x2) |
| 234 | printf("\n"); |
| 235 | |
| 236 | spi->SFC_INT_SW_CLR = 0xFF; //clear int ? |
| 237 | } |
| 238 | |
| 239 | |
| 240 | /* |
| 241 | ****************************************************************************** |
| 242 | * Function: spifc_wait_cmd_end |
| 243 | * Description: |
| 244 | * Parameters: |
| 245 | * Input: |
| 246 | * Output: |
| 247 | * Returns: |
| 248 | * Others: |
| 249 | ******************************************************************************* |
| 250 | */ |
| 251 | static int spifc_wait_cmd_end( void ) |
| 252 | { |
| 253 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 254 | uint32_t int_status = 0; |
| 255 | |
| 256 | while(!(spi->SFC_INT_RAW & FC_INT_RAW_MASK)); |
| 257 | |
| 258 | int_status = spi->SFC_INT_RAW; |
| 259 | spi->SFC_INT_SW_CLR = int_status; /* clear intrrupt */ |
| 260 | |
| 261 | if(int_status & FC_INT_RAW_CMD_END) |
| 262 | { |
| 263 | return 0; |
| 264 | } |
| 265 | else |
| 266 | { |
| 267 | printf("intr err.\n"); |
| 268 | return -1; |
| 269 | } |
| 270 | |
| 271 | } |
| 272 | |
| 273 | |
| 274 | /* |
| 275 | ****************************************************************************** |
| 276 | * Function: spifc_read_fifo_one_byte |
| 277 | * Description: |
| 278 | * Parameters: |
| 279 | * Input: |
| 280 | * Output: |
| 281 | * Returns: |
| 282 | * |
| 283 | * Others: only for: |
| 284 | [Instruction] |--addr width is 8 bit |
| 285 | [addr] |--get feature |
| 286 | [data_rx] |
| 287 | ******************************************************************************* |
| 288 | */ |
| 289 | static int spifc_read_fifo_one_byte( uint8_t *value ) |
| 290 | { |
| 291 | uint32_t sw = 0; |
| 292 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 293 | |
| 294 | sw = spi->SFC_SW; |
| 295 | |
| 296 | if( ((sw >> FC_RX_FIFO_CNT) & FC_RX_FIFO_CNT_MASK) != 1 ) |
| 297 | { |
| 298 | return -1; |
| 299 | } |
| 300 | |
| 301 | *value = (uint8_t)spi->SFC_DATA; |
| 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | |
| 307 | /* |
| 308 | ****************************************************************************** |
| 309 | * Function: spifc_read_fifo |
| 310 | * Description: |
| 311 | * Parameters: |
| 312 | * Input: |
| 313 | * Output: |
| 314 | * Returns: |
| 315 | * Others: |
| 316 | ******************************************************************************* |
| 317 | */ |
| 318 | static uint32_t spifc_read_fifo( uint32_t len, uint8_t *buf ) |
| 319 | { |
| 320 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 321 | uint32_t *p = (uint32_t *)buf; |
| 322 | uint32_t cnt = 0; |
| 323 | |
| 324 | while(cnt < ((len+3)>>2)) |
| 325 | { |
| 326 | if(spi->SFC_SW & (FC_RX_FIFO_CNT_MASK<<FC_RX_FIFO_CNT))//rx fifo not empty |
| 327 | { |
| 328 | p[cnt++]= spi->SFC_DATA; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | return (cnt<<2); |
| 333 | } |
| 334 | |
| 335 | |
| 336 | /* |
| 337 | ****************************************************************************** |
| 338 | * Function: spifc_start |
| 339 | * Description: |
| 340 | * Parameters: |
| 341 | * Input: |
| 342 | * Output: |
| 343 | * Returns: |
| 344 | * Others: |
| 345 | ******************************************************************************* |
| 346 | */ |
| 347 | static void spifc_start( void ) |
| 348 | { |
| 349 | volatile struct spi_t* spi = (struct spi_t*)SYS_SPI_NAND_BASE; |
| 350 | |
| 351 | spi->SFC_START |= FC_START; |
| 352 | } |
| 353 | |
| 354 | /* |
| 355 | ****************************************************************************** |
| 356 | * Function: spifc_get_feature |
| 357 | * Description: |
| 358 | * Parameters: |
| 359 | * Input: |
| 360 | * Output: |
| 361 | * Returns: |
| 362 | * |
| 363 | * Others: [Instruction] |--addr width is 8 bit |
| 364 | [addr] |--get feature |
| 365 | [data_rx] |--read id |
| 366 | |
| 367 | ******************************************************************************* |
| 368 | */ |
| 369 | static int spifc_get_feature( uint32_t reg_addr, uint8_t *value) |
| 370 | { |
| 371 | int ret = 0; |
| 372 | |
| 373 | struct spiflash_cmd_t cmd = {CMD_GET_FEATURE, |
| 374 | 1, |
| 375 | FC_ADDR_BYTE_NUM_8, |
| 376 | 0, |
| 377 | 1, |
| 378 | 0, |
| 379 | 0, |
| 380 | 0 |
| 381 | }; |
| 382 | |
| 383 | spifc_clear_fifo(); |
| 384 | spifc_clear_int(); |
| 385 | |
| 386 | spifc_setup_cmd(&cmd, reg_addr, 1); |
| 387 | spifc_start(); |
| 388 | ret = spifc_wait_cmd_end(); |
| 389 | if(ret != 0) |
| 390 | { |
| 391 | return ret; |
| 392 | } |
| 393 | |
| 394 | ret = spifc_read_fifo_one_byte(value); |
| 395 | if(ret != 0) |
| 396 | { |
| 397 | return ret; |
| 398 | } |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | /* |
| 404 | ****************************************************************************** |
| 405 | * Function: spifc_read_id |
| 406 | * Description: |
| 407 | * Parameters: |
| 408 | * Input: |
| 409 | * Output: |
| 410 | * Returns: |
| 411 | * |
| 412 | * Others: [Instruction] |--addr width is 8 bit |
| 413 | [addr] |--get feature |
| 414 | [data_rx] |--read id |
| 415 | ******************************************************************************* |
| 416 | */ |
| 417 | static int spifc_read_id(uint32_t reg_addr, uint8_t *value, uint8_t len) |
| 418 | { |
| 419 | int ret = 0; |
| 420 | |
| 421 | struct spiflash_cmd_t cmd = { CMD_READ_ID, |
| 422 | 1, |
| 423 | FC_ADDR_BYTE_NUM_8, |
| 424 | 0, |
| 425 | 1, |
| 426 | 0, |
| 427 | 0, |
| 428 | 0 |
| 429 | }; |
| 430 | |
| 431 | spifc_clear_fifo(); |
| 432 | spifc_clear_int(); |
| 433 | spifc_setup_cmd(&cmd, reg_addr, len); |
| 434 | spifc_start(); |
| 435 | ret = spifc_wait_cmd_end(); |
| 436 | if(ret != 0) |
| 437 | { |
| 438 | return ret; |
| 439 | } |
| 440 | |
| 441 | ret = spifc_read_fifo(len, value); |
| 442 | if(ret != 0) |
| 443 | { |
| 444 | return ret; |
| 445 | } |
| 446 | |
| 447 | return 0; |
| 448 | } |
| 449 | |
| 450 | |
| 451 | /* |
| 452 | ****************************************************************************** |
| 453 | * Function: spifc_read_page_to_cache |
| 454 | * Description: |
| 455 | * Parameters: |
| 456 | * Input: |
| 457 | * Output: |
| 458 | * Returns: |
| 459 | * Others: [Instruction] |--addr width is 24 bit(page/block addr!!!!) |
| 460 | [addr] |--page read |
| 461 | |--block erase |
| 462 | |--program execute |
| 463 | ******************************************************************************* |
| 464 | */ |
| 465 | static int spifc_read_page_to_cache(uint32_t page_addr) |
| 466 | { |
| 467 | int ret = 0; |
| 468 | uint8_t status = 0; |
| 469 | |
| 470 | struct spiflash_cmd_t cmd = { CMD_READ_PAGE_TO_CACHE, |
| 471 | 1, |
| 472 | FC_ADDR_BYTE_NUM_24, |
| 473 | 0, |
| 474 | 0, |
| 475 | 0, |
| 476 | 0, |
| 477 | 0 |
| 478 | }; |
| 479 | |
| 480 | spifc_clear_fifo(); |
| 481 | spifc_clear_int(); |
| 482 | spifc_setup_cmd(&cmd, page_addr, 0); |
| 483 | spifc_start(); |
| 484 | ret = spifc_wait_cmd_end(); |
| 485 | if(ret != 0) |
| 486 | { |
| 487 | return ret; |
| 488 | } |
| 489 | |
| 490 | do |
| 491 | { |
| 492 | spifc_get_feature(REG_STATUS, &status); |
| 493 | }while( status & OIP); |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | /* |
| 499 | ****************************************************************************** |
| 500 | * Function: spifc_read_from_cache |
| 501 | * Description: |
| 502 | * Parameters: |
| 503 | * Input: |
| 504 | * Output: |
| 505 | * Returns: |
| 506 | * Others: [Instruction] |--addr width is 16 bit |
| 507 | [addr] |--dummy cycel 8/4/2 |
| 508 | [dummy] |--read form cache(X1,X2,X4) |
| 509 | [data_rx] |--read form cache(dual,quad)IO |
| 510 | ******************************************************************************* |
| 511 | */ |
| 512 | static int spifc_read_from_cache(uint32_t column_addr, uint32_t len, uint8_t *buf) |
| 513 | { |
| 514 | int ret = 0; |
| 515 | |
| 516 | uint32_t len_tmp = 0; |
| 517 | struct spiflash_cmd_t cmd; |
| 518 | |
| 519 | cmd.cmd = CMD_READ_FROM_CACHE; |
| 520 | cmd.dumy_bytes = 1; |
| 521 | cmd.dumy_bits = 0; |
| 522 | cmd.addr_tx_en = 1; |
| 523 | cmd.addr_width = FC_ADDR_BYTE_NUM_16; |
| 524 | cmd.data_tx_en = 0; |
| 525 | cmd.data_rx_en = 1; |
| 526 | cmd.dumy_tx_en = 1; |
| 527 | |
| 528 | spifc_clear_fifo(); |
| 529 | spifc_clear_int(); |
| 530 | spifc_setup_cmd(&cmd, column_addr, len); |
| 531 | spifc_start(); |
| 532 | |
| 533 | len_tmp = spifc_read_fifo(len, buf); |
| 534 | if( len_tmp != len ) |
| 535 | { |
| 536 | ret = -2; |
| 537 | return ret; |
| 538 | } |
| 539 | |
| 540 | ret = spifc_wait_cmd_end(); |
| 541 | if( ret != 0 ) |
| 542 | { |
| 543 | return ret; |
| 544 | } |
| 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | |
| 550 | /* |
| 551 | ****************************************************************************** |
| 552 | * Function: nand_read_oob |
| 553 | * Description: |
| 554 | * Parameters: |
| 555 | * Input: |
| 556 | * Output: |
| 557 | * Returns: |
| 558 | * Others: |
| 559 | ******************************************************************************* |
| 560 | */ |
| 561 | void spifc_read_oob(uint8_t *buf, uint32_t offset, uint32_t len) |
| 562 | { |
| 563 | uint32_t column_offset = spi_flash_info->page_size; |
| 564 | uint32_t page = offset >> (spi_flash_info->page_size_shift); |
| 565 | uint32_t blocks = offset >> (spi_flash_info->block_size_shift); |
| 566 | |
| 567 | spifc_read_page_to_cache(page); |
| 568 | |
| 569 | if((spi_flash_info->planes == 2) && ((blocks%2) != 0)) |
| 570 | { |
| 571 | column_offset |= (0x1 << 12); |
| 572 | } |
| 573 | spifc_read_from_cache(column_offset, spi_flash_info->oob_size, buf); |
| 574 | } |
| 575 | |
| 576 | |
| 577 | /* |
| 578 | ****************************************************************************** |
| 579 | * Function: read_page |
| 580 | * Description: |
| 581 | * Parameters: |
| 582 | * Input: |
| 583 | * Output: |
| 584 | * Returns: |
| 585 | * Others: |
| 586 | ******************************************************************************* |
| 587 | */ |
| 588 | int32_t spifc_read_page(uint32_t buf, uint32_t offset) |
| 589 | { |
| 590 | int ret = 0; |
| 591 | uint8_t feature = 0x0; |
| 592 | |
| 593 | uint32_t page = offset >> (spi_flash_info->page_size_shift); |
| 594 | uint32_t blocks = offset >> (spi_flash_info->block_size_shift); |
| 595 | uint32_t column_offset = 0; |
| 596 | |
| 597 | if( (buf & 0x3) != 0 ) /* DMAµØÖ·ÒªÇó4×Ö½Ú¶ÔÆë */ |
| 598 | { |
| 599 | printf("addr err.\n"); |
| 600 | return -1; |
| 601 | } |
| 602 | |
| 603 | ret = spifc_read_page_to_cache(page); |
| 604 | if( ret != 0 ) |
| 605 | return ret; |
| 606 | |
| 607 | ret = spifc_get_feature(REG_STATUS, &feature); |
| 608 | if(ret != 0) |
| 609 | return ret; |
| 610 | |
| 611 | if((feature>>ECC_ERR_BIT & 0x3) == 0x2) |
| 612 | { |
| 613 | printf("ecc err.\n"); |
| 614 | return -1; |
| 615 | } |
| 616 | if((spi_flash_info->planes == 2) && ((blocks%2) != 0)) |
| 617 | { |
| 618 | column_offset |= (0x1 << 12); |
| 619 | } |
| 620 | ret = spifc_read_from_cache(column_offset, spi_flash_info->page_size, (uint8_t *)buf); |
| 621 | if(ret != 0) |
| 622 | return ret; |
| 623 | |
| 624 | return 0; |
| 625 | } |
| 626 | |
| 627 | /* |
| 628 | ****************************************************************************** |
| 629 | * Function: read_page |
| 630 | * Description: |
| 631 | * Parameters: |
| 632 | * Input: |
| 633 | * Output: |
| 634 | * Returns: |
| 635 | * Others: |
| 636 | ******************************************************************************* |
| 637 | */ |
| 638 | int32_t spifc_read_page_raw(uint32_t buf, uint32_t offset) |
| 639 | { |
| 640 | int ret = 0; |
| 641 | uint8_t feature = 0x0; |
| 642 | |
| 643 | uint32_t page = offset >> (spi_flash_info->page_size_shift); |
| 644 | |
| 645 | if( (buf & 0x3) != 0 ) /* DMAµØÖ·ÒªÇó4×Ö½Ú¶ÔÆë */ |
| 646 | { |
| 647 | printf("addr err.\n"); |
| 648 | return -1; |
| 649 | } |
| 650 | |
| 651 | ret = spifc_read_page_to_cache(page); |
| 652 | if( ret != 0 ) |
| 653 | return ret; |
| 654 | |
| 655 | ret = spifc_read_from_cache(0, spi_flash_info->page_size, (uint8_t *)buf); |
| 656 | if(ret != 0) |
| 657 | return ret; |
| 658 | |
| 659 | return 0; |
| 660 | } |
| 661 | |
| 662 | |
| 663 | /* |
| 664 | ****************************************************************************** |
| 665 | * Function: nand_read |
| 666 | * Description: |
| 667 | * Parameters: |
| 668 | * Input: |
| 669 | * Output: |
| 670 | * Returns: |
| 671 | * Others: from: must page align len: must page align |
| 672 | ******************************************************************************* |
| 673 | */ |
| 674 | int32_t spifc_read(uint32_t from, uint32_t len, uint32_t to) |
| 675 | { |
| 676 | uint32_t offset = from; |
| 677 | uint32_t left_to_read = len; |
| 678 | uint32_t p_to = to; |
| 679 | int32_t ret = 0; |
| 680 | int32_t page_size = (spi_flash_info->page_size); |
| 681 | |
| 682 | if((offset & (page_size - 1)) || (len & (page_size - 1)) ) |
| 683 | { |
| 684 | return -1; |
| 685 | } |
| 686 | |
| 687 | while( left_to_read > 0 ) |
| 688 | { |
| 689 | ret = spifc_read_page(p_to, offset); |
| 690 | if(ret != 0) |
| 691 | { |
| 692 | return -1; |
| 693 | } |
| 694 | |
| 695 | left_to_read -= page_size; |
| 696 | offset += page_size; |
| 697 | p_to += page_size; |
| 698 | } |
| 699 | return 0; |
| 700 | } |
| 701 | |
| 702 | |
| 703 | /******************************************************************************* |
| 704 | * Function: nand_read_id |
| 705 | * Description: |
| 706 | * Parameters: |
| 707 | * Input: |
| 708 | * |
| 709 | * Output: |
| 710 | * |
| 711 | * Returns: |
| 712 | * |
| 713 | * |
| 714 | * Others: |
| 715 | ********************************************************************************/ |
| 716 | int32_t read_id (void) |
| 717 | { |
| 718 | uint8_t id[4]; |
| 719 | const struct spi_flash_device_para *spi_flash = &spi_flash_para[0]; |
| 720 | |
| 721 | spifc_read_id(0x0, id, 2); |
| 722 | |
| 723 | while( spi_flash->manuf_id != 0 ) |
| 724 | { |
| 725 | if( ((uint8_t)id[0] == spi_flash->manuf_id) && |
| 726 | ((uint8_t)id[1] == spi_flash->device_id) ) |
| 727 | { |
| 728 | spi_flash_info = spi_flash; |
| 729 | return 0; |
| 730 | }; |
| 731 | spi_flash++; |
| 732 | } |
| 733 | |
| 734 | return -1; |
| 735 | } |
| 736 | |
| 737 | /******************************************************************************* |
| 738 | * Function: |
| 739 | * Description: |
| 740 | * Parameters: |
| 741 | * Input: |
| 742 | * |
| 743 | * Output: |
| 744 | * |
| 745 | * Returns: |
| 746 | * |
| 747 | * |
| 748 | * Others: |
| 749 | ********************************************************************************/ |
| 750 | int32_t read_data(uint32_t from, uint32_t len, uint32_t to) |
| 751 | { |
| 752 | uint32_t offset = from; |
| 753 | uint32_t left_to_read = len; |
| 754 | uint32_t p_to = to; |
| 755 | int32_t ret = 0; |
| 756 | int32_t block_size = (spi_flash_info->block_size); |
| 757 | |
| 758 | while(left_to_read > 0) |
| 759 | { |
| 760 | uint32_t block_offset = offset & (block_size - 1); |
| 761 | uint32_t read_length; |
| 762 | |
| 763 | if( nand_block_isbad(offset) ) |
| 764 | { |
| 765 | offset += block_size; |
| 766 | continue; |
| 767 | } |
| 768 | |
| 769 | if (left_to_read < (block_size - block_offset)) |
| 770 | read_length = left_to_read; |
| 771 | else |
| 772 | read_length = block_size - block_offset; |
| 773 | |
| 774 | ret = spifc_read(offset, read_length, p_to); |
| 775 | if(ret != 0) |
| 776 | { |
| 777 | return -1; |
| 778 | } |
| 779 | |
| 780 | left_to_read -= read_length; |
| 781 | offset += read_length; |
| 782 | p_to += read_length; |
| 783 | } |
| 784 | |
| 785 | return 0; |
| 786 | } |
| 787 | |
| 788 | /******************************************************************************* |
| 789 | * Function: nand_init |
| 790 | * Description: |
| 791 | * Parameters: |
| 792 | * Input: |
| 793 | * |
| 794 | * Output: |
| 795 | * |
| 796 | * Returns: |
| 797 | * |
| 798 | * |
| 799 | * Others: |
| 800 | ********************************************************************************/ |
| 801 | int32_t spifc_init (void) |
| 802 | { |
| 803 | int32_t ret = 0; |
| 804 | spifc_enable(); |
| 805 | ret = read_id(); |
| 806 | if(ret != 0) |
| 807 | { |
| 808 | printf("id err!\n"); |
| 809 | return -1; |
| 810 | } |
| 811 | |
| 812 | flash.flash_type = SPI_NAND_BOOT; |
| 813 | flash.manuf_id = spi_flash_info->manuf_id; |
| 814 | flash.device_id = spi_flash_info->device_id; |
| 815 | flash.page_size = spi_flash_info->page_size; |
| 816 | flash.page_size_shift = spi_flash_info->page_size_shift; |
| 817 | flash.oob_size = spi_flash_info->oob_size; |
| 818 | flash.block_size = spi_flash_info->block_size; |
| 819 | flash.block_size_shift = spi_flash_info->block_size_shift; |
| 820 | flash.block_num = spi_flash_info->block_num; |
| 821 | flash.read_page_raw = spifc_read_page_raw; |
| 822 | flash.read_oob = spifc_read_oob; |
| 823 | flash.read = read_data; |
| 824 | |
| 825 | return 0; |
| 826 | |
| 827 | } |
| 828 | |
| 829 | /* |
| 830 | ****************************************************************************** |
| 831 | * Function: |
| 832 | * Description: |
| 833 | * Parameters: |
| 834 | * Input: |
| 835 | * Output: |
| 836 | * Returns: |
| 837 | * Others: |
| 838 | ******************************************************************************* |
| 839 | */ |
| 840 | int board_flash_init(void) |
| 841 | { |
| 842 | int ret = 0; |
| 843 | char boot_mode = 0; |
| 844 | |
| 845 | printf("spi-nand:"); |
| 846 | |
| 847 | boot_mode = get_boot_mode(); |
| 848 | if(boot_mode != SPI_NAND_BOOT) |
| 849 | { |
| 850 | printf("mode err.\n"); |
| 851 | return -1; |
| 852 | } |
| 853 | |
| 854 | writel(CFG_START_MODE_SPI_NAND, CFG_BOOT_MODE_START_MODE_FOR_UBOOT); |
| 855 | ret = spifc_init(); |
| 856 | if(ret != 0) |
| 857 | { |
| 858 | printf("init err.\n"); |
| 859 | return -1; |
| 860 | } |
| 861 | printf("init ok.\n"); |
| 862 | |
| 863 | // nand_creat_bbt(); |
| 864 | nand_creat_ram_bbt(); |
| 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
| 869 | |