blob: b5fa51db73cbcc58d75fc51e5fc8053712f1ff78 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001config ARM
2 bool
3 default y
4 select HAVE_DMA_API_DEBUG
5 select HAVE_IDE if PCI || ISA || PCMCIA
6 select HAVE_MEMBLOCK
7 select RTC_LIB
8 select SYS_SUPPORTS_APM_EMULATION
9 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
10 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
11 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
12 select HAVE_ARCH_KGDB
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
20 select HAVE_GENERIC_DMA_COHERENT
21 select HAVE_KERNEL_GZIP
22 select HAVE_KERNEL_LZO
23 select HAVE_KERNEL_LZMA
24 select HAVE_KERNEL_XZ
25 select HAVE_IRQ_WORK
26 select HAVE_PERF_EVENTS
27 select PERF_USE_VMALLOC
28 select HAVE_REGS_AND_STACK_ACCESS_API
29 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_GENERIC_HARDIRQS
32 select GENERIC_IRQ_SHOW
33 select IRQ_FORCED_THREADING
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
37 help
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
44
45config ARM_HAS_SG_CHAIN
46 bool
47
48config HAVE_PWM
49 bool
50
51config MIGHT_HAVE_PCI
52 bool
53
54config SYS_SUPPORTS_APM_EMULATION
55 bool
56
57config GENERIC_GPIO
58 bool
59
60config ARCH_USES_GETTIMEOFFSET
61 bool
62 default n
63
64config GENERIC_CLOCKEVENTS
65 bool
66
67config GENERIC_CLOCKEVENTS_BROADCAST
68 bool
69 depends on GENERIC_CLOCKEVENTS
70 default y if SMP
71
72config KTIME_SCALAR
73 bool
74 default y
75
76config HAVE_TCM
77 bool
78 select GENERIC_ALLOCATOR
79
80config HAVE_PROC_CPU
81 bool
82
83config NO_IOPORT
84 bool
85
86config EISA
87 bool
88 ---help---
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
91
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
96
97 Say Y here if you are building a kernel for an EISA-based machine.
98
99 Otherwise, say N.
100
101config SBUS
102 bool
103
104config MCA
105 bool
106 help
107 MicroChannel Architecture is found in some IBM PS/2 machines and
108 laptops. It is a bus system similar to PCI or ISA. See
109 <file:Documentation/mca.txt> (and especially the web page given
110 there) before attempting to build an MCA bus kernel.
111
112config STACKTRACE_SUPPORT
113 bool
114 default y
115
116config HAVE_LATENCYTOP_SUPPORT
117 bool
118 depends on !SMP
119 default y
120
121config LOCKDEP_SUPPORT
122 bool
123 default y
124
125config TRACE_IRQFLAGS_SUPPORT
126 bool
127 default y
128
129config HARDIRQS_SW_RESEND
130 bool
131 default y
132
133config GENERIC_IRQ_PROBE
134 bool
135 default y
136
137config GENERIC_LOCKBREAK
138 bool
139 default y
140 depends on SMP && PREEMPT
141
142config RWSEM_GENERIC_SPINLOCK
143 bool
144 default y
145
146config RWSEM_XCHGADD_ALGORITHM
147 bool
148
149config ARCH_HAS_ILOG2_U32
150 bool
151
152config ARCH_HAS_ILOG2_U64
153 bool
154
155config ARCH_HAS_CPUFREQ
156 bool
157 help
158 Internal node to signify that the ARCH has CPUFREQ support
159 and that the relevant menu configurations are displayed for
160 it.
161
162config ARCH_HAS_CPU_IDLE_WAIT
163 def_bool y
164
165config GENERIC_HWEIGHT
166 bool
167 default y
168
169config GENERIC_CALIBRATE_DELAY
170 bool
171 default y
172
173config ARCH_MAY_HAVE_PC_FDC
174 bool
175
176config ZONE_DMA
177 bool
178
179config NEED_DMA_MAP_STATE
180 def_bool y
181
182config ARCH_HAS_DMA_SET_COHERENT_MASK
183 bool
184
185config GENERIC_ISA_DMA
186 bool
187
188config FIQ
189 bool
190
191config NEED_RET_TO_USER
192 bool
193
194config ARCH_MTD_XIP
195 bool
196
197config VECTORS_BASE
198 hex
199 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
200 default DRAM_BASE if REMAP_VECTORS_TO_RAM
201 default 0x00000000
202 help
203 The base address of exception vectors.
204
205config ARM_PATCH_PHYS_VIRT
206 bool "Patch physical to virtual translations at runtime" if EMBEDDED
207 default y
208 depends on !XIP_KERNEL && MMU
209 depends on !ARCH_REALVIEW || !SPARSEMEM
210 help
211 Patch phys-to-virt and virt-to-phys translation functions at
212 boot and module load time according to the position of the
213 kernel in system memory.
214
215 This can only be used with non-XIP MMU kernels where the base
216 of physical memory is at a 16MB boundary.
217
218 Only disable this option if you know that you do not require
219 this feature (eg, building a kernel for a single machine) and
220 you need to shrink the kernel to the minimal size.
221
222config NEED_MACH_IO_H
223 bool
224 help
225 Select this when mach/io.h is required to provide special
226 definitions for this platform. The need for mach/io.h should
227 be avoided when possible.
228
229config NEED_MACH_MEMORY_H
230 bool
231 help
232 Select this when mach/memory.h is required to provide special
233 definitions for this platform. The need for mach/memory.h should
234 be avoided when possible.
235
236config PHYS_OFFSET
237 hex "Physical address of main memory" if MMU
238 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
239 default DRAM_BASE if !MMU
240 help
241 Please provide the physical address corresponding to the
242 location of main memory in your system.
243
244config GENERIC_BUG
245 def_bool y
246 depends on BUG
247
248source "init/Kconfig"
249
250source "kernel/Kconfig.freezer"
251
252menu "System Type"
253
254config MMU
255 bool "MMU-based Paged Memory Management Support"
256 default y
257 help
258 Select if you want MMU-based virtualised addressing space
259 support by paged memory management. If unsure, say 'Y'.
260
261#
262# The "ARM system type" choice list is ordered alphabetically by option
263# text. Please add new entries in the option alphabetic order.
264#
265choice
266 prompt "ARM system type"
267 default ARCH_VERSATILE
268
269config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
271 select ARM_AMBA
272 select ARCH_HAS_CPUFREQ
273 select CLKDEV_LOOKUP
274 select HAVE_MACH_CLKDEV
275 select HAVE_TCM
276 select ICST
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_IO_H
281 select NEED_MACH_MEMORY_H
282 select SPARSE_IRQ
283 help
284 Support for ARM's Integrator platform.
285
286config ARCH_REALVIEW
287 bool "ARM Ltd. RealView family"
288 select ARM_AMBA
289 select CLKDEV_LOOKUP
290 select HAVE_MACH_CLKDEV
291 select ICST
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select ARM_TIMER_SP804
297 select GPIO_PL061 if GPIOLIB
298 select NEED_MACH_MEMORY_H
299 help
300 This enables support for ARM Ltd RealView boards.
301
302config ARCH_VERSATILE
303 bool "ARM Ltd. Versatile family"
304 select ARM_AMBA
305 select ARM_VIC
306 select CLKDEV_LOOKUP
307 select HAVE_MACH_CLKDEV
308 select ICST
309 select GENERIC_CLOCKEVENTS
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
313 select PLAT_VERSATILE_FPGA_IRQ
314 select ARM_TIMER_SP804
315 help
316 This enables support for ARM Ltd Versatile board.
317
318config ARCH_VEXPRESS
319 bool "ARM Ltd. Versatile Express family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_AMBA
322 select ARM_TIMER_SP804
323 select CLKDEV_LOOKUP
324 select HAVE_MACH_CLKDEV
325 select GENERIC_CLOCKEVENTS
326 select HAVE_CLK
327 select HAVE_PATA_PLATFORM
328 select ICST
329 select NO_IOPORT
330 select PLAT_VERSATILE
331 select PLAT_VERSATILE_CLCD
332 help
333 This enables support for the ARM Ltd Versatile Express boards.
334
335config ARCH_AT91
336 bool "Atmel AT91"
337 select ARCH_REQUIRE_GPIOLIB
338 select HAVE_CLK
339 select CLKDEV_LOOKUP
340 select IRQ_DOMAIN
341 select NEED_MACH_IO_H if PCCARD
342 help
343 This enables support for systems based on the Atmel AT91RM9200,
344 AT91SAM9 processors.
345
346config ARCH_BCMRING
347 bool "Broadcom BCMRING"
348 depends on MMU
349 select CPU_V6
350 select ARM_AMBA
351 select ARM_TIMER_SP804
352 select CLKDEV_LOOKUP
353 select GENERIC_CLOCKEVENTS
354 select ARCH_WANT_OPTIONAL_GPIOLIB
355 help
356 Support for Broadcom's BCMRing platform.
357
358config ARCH_HIGHBANK
359 bool "Calxeda Highbank-based"
360 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_AMBA
362 select ARM_GIC
363 select ARM_TIMER_SP804
364 select CACHE_L2X0
365 select CLKDEV_LOOKUP
366 select CPU_V7
367 select GENERIC_CLOCKEVENTS
368 select HAVE_ARM_SCU
369 select HAVE_SMP
370 select SPARSE_IRQ
371 select USE_OF
372 help
373 Support for the Calxeda Highbank SoC based boards.
374
375config ARCH_CLPS711X
376 bool "Cirrus Logic CLPS711x/EP721x-based"
377 select CPU_ARM720T
378 select ARCH_USES_GETTIMEOFFSET
379 select NEED_MACH_MEMORY_H
380 help
381 Support for Cirrus Logic 711x/721x based boards.
382
383config ARCH_CNS3XXX
384 bool "Cavium Networks CNS3XXX family"
385 select CPU_V6K
386 select GENERIC_CLOCKEVENTS
387 select ARM_GIC
388 select MIGHT_HAVE_CACHE_L2X0
389 select MIGHT_HAVE_PCI
390 select PCI_DOMAINS if PCI
391 help
392 Support for Cavium Networks CNS3XXX platform.
393
394config ARCH_GEMINI
395 bool "Cortina Systems Gemini"
396 select CPU_FA526
397 select ARCH_REQUIRE_GPIOLIB
398 select ARCH_USES_GETTIMEOFFSET
399 help
400 Support for the Cortina Systems Gemini family SoCs
401
402config ARCH_PRIMA2
403 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
404 select CPU_V7
405 select NO_IOPORT
406 select GENERIC_CLOCKEVENTS
407 select CLKDEV_LOOKUP
408 select GENERIC_IRQ_CHIP
409 select MIGHT_HAVE_CACHE_L2X0
410 select USE_OF
411 select ZONE_DMA
412 help
413 Support for CSR SiRFSoC ARM Cortex A9 Platform
414
415config ARCH_EBSA110
416 bool "EBSA-110"
417 select CPU_SA110
418 select ISA
419 select NO_IOPORT
420 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_IO_H
422 select NEED_MACH_MEMORY_H
423 help
424 This is an evaluation board for the StrongARM processor available
425 from Digital. It has limited hardware on-board, including an
426 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 parallel port.
428
429config ARCH_EP93XX
430 bool "EP93xx-based"
431 select CPU_ARM920T
432 select ARM_AMBA
433 select ARM_VIC
434 select CLKDEV_LOOKUP
435 select ARCH_REQUIRE_GPIOLIB
436 select ARCH_HAS_HOLES_MEMORYMODEL
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_MEMORY_H
439 help
440 This enables support for the Cirrus EP93xx series of CPUs.
441
442config ARCH_FOOTBRIDGE
443 bool "FootBridge"
444 select CPU_SA110
445 select FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
447 select HAVE_IDE
448 select NEED_MACH_IO_H
449 select NEED_MACH_MEMORY_H
450 help
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
453
454config ARCH_MXC
455 bool "Freescale MXC/iMX-based"
456 select GENERIC_CLOCKEVENTS
457 select ARCH_REQUIRE_GPIOLIB
458 select CLKDEV_LOOKUP
459 select CLKSRC_MMIO
460 select GENERIC_IRQ_CHIP
461 select MULTI_IRQ_HANDLER
462 help
463 Support for Freescale MXC/iMX-based family of processors
464
465config ARCH_MXS
466 bool "Freescale MXS-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
469 select CLKDEV_LOOKUP
470 select CLKSRC_MMIO
471 select HAVE_CLK_PREPARE
472 help
473 Support for Freescale MXS-based family of processors
474
475config ARCH_NETX
476 bool "Hilscher NetX based"
477 select CLKSRC_MMIO
478 select CPU_ARM926T
479 select ARM_VIC
480 select GENERIC_CLOCKEVENTS
481 help
482 This enables support for systems based on the Hilscher NetX Soc
483
484config ARCH_H720X
485 bool "Hynix HMS720x-based"
486 select CPU_ARM720T
487 select ISA_DMA_API
488 select ARCH_USES_GETTIMEOFFSET
489 help
490 This enables support for systems based on the Hynix HMS720x
491
492config ARCH_IOP13XX
493 bool "IOP13xx-based"
494 depends on MMU
495 select CPU_XSC3
496 select PLAT_IOP
497 select PCI
498 select ARCH_SUPPORTS_MSI
499 select VMSPLIT_1G
500 select NEED_MACH_IO_H
501 select NEED_MACH_MEMORY_H
502 select NEED_RET_TO_USER
503 help
504 Support for Intel's IOP13XX (XScale) family of processors.
505
506config ARCH_IOP32X
507 bool "IOP32x-based"
508 depends on MMU
509 select CPU_XSCALE
510 select NEED_MACH_IO_H
511 select NEED_RET_TO_USER
512 select PLAT_IOP
513 select PCI
514 select ARCH_REQUIRE_GPIOLIB
515 help
516 Support for Intel's 80219 and IOP32X (XScale) family of
517 processors.
518
519config ARCH_IOP33X
520 bool "IOP33x-based"
521 depends on MMU
522 select CPU_XSCALE
523 select NEED_MACH_IO_H
524 select NEED_RET_TO_USER
525 select PLAT_IOP
526 select PCI
527 select ARCH_REQUIRE_GPIOLIB
528 help
529 Support for Intel's IOP33X (XScale) family of processors.
530
531config ARCH_IXP23XX
532 bool "IXP23XX-based"
533 depends on MMU
534 select CPU_XSC3
535 select PCI
536 select ARCH_USES_GETTIMEOFFSET
537 select NEED_MACH_IO_H
538 select NEED_MACH_MEMORY_H
539 help
540 Support for Intel's IXP23xx (XScale) family of processors.
541
542config ARCH_IXP2000
543 bool "IXP2400/2800-based"
544 depends on MMU
545 select CPU_XSCALE
546 select PCI
547 select ARCH_USES_GETTIMEOFFSET
548 select NEED_MACH_IO_H
549 select NEED_MACH_MEMORY_H
550 help
551 Support for Intel's IXP2400/2800 (XScale) family of processors.
552
553config ARCH_IXP4XX
554 bool "IXP4xx-based"
555 depends on MMU
556 select ARCH_HAS_DMA_SET_COHERENT_MASK
557 select CLKSRC_MMIO
558 select CPU_XSCALE
559 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
561 select MIGHT_HAVE_PCI
562 select NEED_MACH_IO_H
563 select DMABOUNCE if PCI
564 help
565 Support for Intel's IXP4XX (XScale) family of processors.
566
567config ARCH_DOVE
568 bool "Marvell Dove"
569 select CPU_V7
570 select PCI
571 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_IO_H
574 select PLAT_ORION
575 help
576 Support for the Marvell Dove SoC 88AP510
577
578config ARCH_KIRKWOOD
579 bool "Marvell Kirkwood"
580 select CPU_FEROCEON
581 select PCI
582 select PCI_QUIRKS
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
585 select NEED_MACH_IO_H
586 select PLAT_ORION
587 help
588 Support for the following Marvell Kirkwood series SoCs:
589 88F6180, 88F6192 and 88F6281.
590
591config ARCH_LPC32XX
592 bool "NXP LPC32XX"
593 select CLKSRC_MMIO
594 select CPU_ARM926T
595 select ARCH_REQUIRE_GPIOLIB
596 select HAVE_IDE
597 select ARM_AMBA
598 select USB_ARCH_HAS_OHCI
599 select CLKDEV_LOOKUP
600 select GENERIC_CLOCKEVENTS
601 help
602 Support for the NXP LPC32XX family of processors
603
604config ARCH_MV78XX0
605 bool "Marvell MV78xx0"
606 select CPU_FEROCEON
607 select PCI
608 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select NEED_MACH_IO_H
611 select PLAT_ORION
612 help
613 Support for the following Marvell MV78xx0 series SoCs:
614 MV781x0, MV782x0.
615
616config ARCH_ORION5X
617 bool "Marvell Orion"
618 depends on MMU
619 select CPU_FEROCEON
620 select PCI
621 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS
623 select PLAT_ORION
624 help
625 Support for the following Marvell Orion 5x series SoCs:
626 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
627 Orion-2 (5281), Orion-1-90 (6183).
628
629config ARCH_MMP
630 bool "Marvell PXA168/910/MMP2"
631 depends on MMU
632 select ARCH_REQUIRE_GPIOLIB
633 select CLKDEV_LOOKUP
634 select GENERIC_CLOCKEVENTS
635 select GPIO_PXA
636 select TICK_ONESHOT
637 select PLAT_PXA
638 select SPARSE_IRQ
639 select GENERIC_ALLOCATOR
640 help
641 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
642
643config ARCH_KS8695
644 bool "Micrel/Kendin KS8695"
645 select CPU_ARM922T
646 select ARCH_REQUIRE_GPIOLIB
647 select ARCH_USES_GETTIMEOFFSET
648 select NEED_MACH_MEMORY_H
649 help
650 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
651 System-on-Chip devices.
652
653config ARCH_W90X900
654 bool "Nuvoton W90X900 CPU"
655 select CPU_ARM926T
656 select ARCH_REQUIRE_GPIOLIB
657 select CLKDEV_LOOKUP
658 select CLKSRC_MMIO
659 select GENERIC_CLOCKEVENTS
660 help
661 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
662 At present, the w90x900 has been renamed nuc900, regarding
663 the ARM series product line, you can login the following
664 link address to know more.
665
666 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
667 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
668
669config ARCH_TEGRA
670 bool "NVIDIA Tegra"
671 select CLKDEV_LOOKUP
672 select CLKSRC_MMIO
673 select GENERIC_CLOCKEVENTS
674 select GENERIC_GPIO
675 select HAVE_CLK
676 select HAVE_SMP
677 select MIGHT_HAVE_CACHE_L2X0
678 select NEED_MACH_IO_H if PCI
679 select ARCH_HAS_CPUFREQ
680 help
681 This enables support for NVIDIA Tegra based systems (Tegra APX,
682 Tegra 6xx and Tegra 2 series).
683
684config ARCH_PICOXCELL
685 bool "Picochip picoXcell"
686 select ARCH_REQUIRE_GPIOLIB
687 select ARM_PATCH_PHYS_VIRT
688 select ARM_VIC
689 select CPU_V6K
690 select DW_APB_TIMER
691 select GENERIC_CLOCKEVENTS
692 select GENERIC_GPIO
693 select HAVE_TCM
694 select NO_IOPORT
695 select SPARSE_IRQ
696 select USE_OF
697 help
698 This enables support for systems based on the Picochip picoXcell
699 family of Femtocell devices. The picoxcell support requires device tree
700 for all boards.
701
702config ARCH_PNX4008
703 bool "Philips Nexperia PNX4008 Mobile"
704 select CPU_ARM926T
705 select CLKDEV_LOOKUP
706 select ARCH_USES_GETTIMEOFFSET
707 help
708 This enables support for Philips PNX4008 mobile platform.
709
710config ARCH_PXA
711 bool "PXA2xx/PXA3xx-based"
712 depends on MMU
713 select ARCH_MTD_XIP
714 select ARCH_HAS_CPUFREQ
715 select CLKDEV_LOOKUP
716 select CLKSRC_MMIO
717 select ARCH_REQUIRE_GPIOLIB
718 select GENERIC_CLOCKEVENTS
719 select GPIO_PXA
720 select TICK_ONESHOT
721 select PLAT_PXA
722 select SPARSE_IRQ
723 select AUTO_ZRELADDR
724 select MULTI_IRQ_HANDLER
725 select ARM_CPU_SUSPEND if PM
726 select HAVE_IDE
727 help
728 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
729
730config ARCH_MSM
731 bool "Qualcomm MSM"
732 select HAVE_CLK
733 select GENERIC_CLOCKEVENTS
734 select ARCH_REQUIRE_GPIOLIB
735 select CLKDEV_LOOKUP
736 help
737 Support for Qualcomm MSM/QSD based systems. This runs on the
738 apps processor of the MSM/QSD and depends on a shared memory
739 interface to the modem processor which runs the baseband
740 stack and controls some vital subsystems
741 (clock and power control, etc).
742
743config ARCH_SHMOBILE
744 bool "Renesas SH-Mobile / R-Mobile"
745 select HAVE_CLK
746 select CLKDEV_LOOKUP
747 select HAVE_MACH_CLKDEV
748 select HAVE_SMP
749 select GENERIC_CLOCKEVENTS
750 select MIGHT_HAVE_CACHE_L2X0
751 select NO_IOPORT
752 select SPARSE_IRQ
753 select MULTI_IRQ_HANDLER
754 select PM_GENERIC_DOMAINS if PM
755 select NEED_MACH_MEMORY_H
756 help
757 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
758
759config ARCH_RPC
760 bool "RiscPC"
761 select ARCH_ACORN
762 select FIQ
763 select ARCH_MAY_HAVE_PC_FDC
764 select HAVE_PATA_PLATFORM
765 select ISA_DMA_API
766 select NO_IOPORT
767 select ARCH_SPARSEMEM_ENABLE
768 select ARCH_USES_GETTIMEOFFSET
769 select HAVE_IDE
770 select NEED_MACH_IO_H
771 select NEED_MACH_MEMORY_H
772 help
773 On the Acorn Risc-PC, Linux can support the internal IDE disk and
774 CD-ROM interface, serial and parallel port, and the floppy drive.
775
776config ARCH_SA1100
777 bool "SA1100-based"
778 select CLKSRC_MMIO
779 select CPU_SA1100
780 select ISA
781 select ARCH_SPARSEMEM_ENABLE
782 select ARCH_MTD_XIP
783 select ARCH_HAS_CPUFREQ
784 select CPU_FREQ
785 select GENERIC_CLOCKEVENTS
786 select CLKDEV_LOOKUP
787 select TICK_ONESHOT
788 select ARCH_REQUIRE_GPIOLIB
789 select HAVE_IDE
790 select NEED_MACH_MEMORY_H
791 select SPARSE_IRQ
792 help
793 Support for StrongARM 11x0 based boards.
794
795config ARCH_S3C24XX
796 bool "Samsung S3C24XX SoCs"
797 select GENERIC_GPIO
798 select ARCH_HAS_CPUFREQ
799 select HAVE_CLK
800 select CLKDEV_LOOKUP
801 select ARCH_USES_GETTIMEOFFSET
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C_RTC if RTC_CLASS
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select NEED_MACH_IO_H
806 help
807 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
808 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
809 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
810 Samsung SMDK2410 development board (and derivatives).
811
812config ARCH_S3C64XX
813 bool "Samsung S3C64XX"
814 select PLAT_SAMSUNG
815 select CPU_V6
816 select ARM_VIC
817 select HAVE_CLK
818 select HAVE_TCM
819 select CLKDEV_LOOKUP
820 select NO_IOPORT
821 select ARCH_USES_GETTIMEOFFSET
822 select ARCH_HAS_CPUFREQ
823 select ARCH_REQUIRE_GPIOLIB
824 select SAMSUNG_CLKSRC
825 select SAMSUNG_IRQ_VIC_TIMER
826 select S3C_GPIO_TRACK
827 select S3C_DEV_NAND
828 select USB_ARCH_HAS_OHCI
829 select SAMSUNG_GPIOLIB_4BIT
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
832 help
833 Samsung S3C64XX series based systems
834
835config ARCH_S5P64X0
836 bool "Samsung S5P6440 S5P6450"
837 select CPU_V6
838 select GENERIC_GPIO
839 select HAVE_CLK
840 select CLKDEV_LOOKUP
841 select CLKSRC_MMIO
842 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 select GENERIC_CLOCKEVENTS
844 select HAVE_S3C2410_I2C if I2C
845 select HAVE_S3C_RTC if RTC_CLASS
846 help
847 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
848 SMDK6450.
849
850config ARCH_S5PC100
851 bool "Samsung S5PC100"
852 select GENERIC_GPIO
853 select HAVE_CLK
854 select CLKDEV_LOOKUP
855 select CPU_V7
856 select ARCH_USES_GETTIMEOFFSET
857 select HAVE_S3C2410_I2C if I2C
858 select HAVE_S3C_RTC if RTC_CLASS
859 select HAVE_S3C2410_WATCHDOG if WATCHDOG
860 help
861 Samsung S5PC100 series based systems
862
863config ARCH_S5PV210
864 bool "Samsung S5PV210/S5PC110"
865 select CPU_V7
866 select ARCH_SPARSEMEM_ENABLE
867 select ARCH_HAS_HOLES_MEMORYMODEL
868 select GENERIC_GPIO
869 select HAVE_CLK
870 select CLKDEV_LOOKUP
871 select CLKSRC_MMIO
872 select ARCH_HAS_CPUFREQ
873 select GENERIC_CLOCKEVENTS
874 select HAVE_S3C2410_I2C if I2C
875 select HAVE_S3C_RTC if RTC_CLASS
876 select HAVE_S3C2410_WATCHDOG if WATCHDOG
877 select NEED_MACH_MEMORY_H
878 help
879 Samsung S5PV210/S5PC110 series based systems
880
881config ARCH_EXYNOS
882 bool "SAMSUNG EXYNOS"
883 select CPU_V7
884 select ARCH_SPARSEMEM_ENABLE
885 select ARCH_HAS_HOLES_MEMORYMODEL
886 select GENERIC_GPIO
887 select HAVE_CLK
888 select CLKDEV_LOOKUP
889 select ARCH_HAS_CPUFREQ
890 select GENERIC_CLOCKEVENTS
891 select HAVE_S3C_RTC if RTC_CLASS
892 select HAVE_S3C2410_I2C if I2C
893 select HAVE_S3C2410_WATCHDOG if WATCHDOG
894 select NEED_MACH_MEMORY_H
895 help
896 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
897
898config ARCH_SHARK
899 bool "Shark"
900 select CPU_SA110
901 select ISA
902 select ISA_DMA
903 select ZONE_DMA
904 select PCI
905 select ARCH_USES_GETTIMEOFFSET
906 select NEED_MACH_MEMORY_H
907 select NEED_MACH_IO_H
908 help
909 Support for the StrongARM based Digital DNARD machine, also known
910 as "Shark" (<http://www.shark-linux.de/shark.html>).
911
912config ARCH_U300
913 bool "ST-Ericsson U300 Series"
914 depends on MMU
915 select CLKSRC_MMIO
916 select CPU_ARM926T
917 select HAVE_TCM
918 select ARM_AMBA
919 select ARM_PATCH_PHYS_VIRT
920 select ARM_VIC
921 select GENERIC_CLOCKEVENTS
922 select CLKDEV_LOOKUP
923 select HAVE_MACH_CLKDEV
924 select GENERIC_GPIO
925 select ARCH_REQUIRE_GPIOLIB
926 help
927 Support for ST-Ericsson U300 series mobile platforms.
928
929config ARCH_U8500
930 bool "ST-Ericsson U8500 Series"
931 depends on MMU
932 select CPU_V7
933 select ARM_AMBA
934 select GENERIC_CLOCKEVENTS
935 select CLKDEV_LOOKUP
936 select ARCH_REQUIRE_GPIOLIB
937 select ARCH_HAS_CPUFREQ
938 select HAVE_SMP
939 select MIGHT_HAVE_CACHE_L2X0
940 help
941 Support for ST-Ericsson's Ux500 architecture
942
943config ARCH_NOMADIK
944 bool "STMicroelectronics Nomadik"
945 select ARM_AMBA
946 select ARM_VIC
947 select CPU_ARM926T
948 select CLKDEV_LOOKUP
949 select GENERIC_CLOCKEVENTS
950 select MIGHT_HAVE_CACHE_L2X0
951 select ARCH_REQUIRE_GPIOLIB
952 help
953 Support for the Nomadik platform by ST-Ericsson
954
955config ARCH_DAVINCI
956 bool "TI DaVinci"
957 select GENERIC_CLOCKEVENTS
958 select ARCH_REQUIRE_GPIOLIB
959 select ZONE_DMA
960 select HAVE_IDE
961 select CLKDEV_LOOKUP
962 select GENERIC_ALLOCATOR
963 select GENERIC_IRQ_CHIP
964 select ARCH_HAS_HOLES_MEMORYMODEL
965 help
966 Support for TI's DaVinci platform.
967
968config ARCH_OMAP
969 bool "TI OMAP"
970 select HAVE_CLK
971 select ARCH_REQUIRE_GPIOLIB
972 select ARCH_HAS_CPUFREQ
973 select CLKSRC_MMIO
974 select GENERIC_CLOCKEVENTS
975 select ARCH_HAS_HOLES_MEMORYMODEL
976 help
977 Support for TI's OMAP platform (OMAP1/2/3/4).
978
979config PLAT_SPEAR
980 bool "ST SPEAr"
981 select ARM_AMBA
982 select ARCH_REQUIRE_GPIOLIB
983 select CLKDEV_LOOKUP
984 select CLKSRC_MMIO
985 select GENERIC_CLOCKEVENTS
986 select HAVE_CLK
987 help
988 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
989
990config ARCH_VT8500
991 bool "VIA/WonderMedia 85xx"
992 select CPU_ARM926T
993 select GENERIC_GPIO
994 select ARCH_HAS_CPUFREQ
995 select GENERIC_CLOCKEVENTS
996 select ARCH_REQUIRE_GPIOLIB
997 select HAVE_PWM
998 help
999 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1000
1001config ARCH_ZYNQ
1002 bool "Xilinx Zynq ARM Cortex A9 Platform"
1003 select CPU_V7
1004 select GENERIC_CLOCKEVENTS
1005 select CLKDEV_LOOKUP
1006 select ARM_GIC
1007 select ARM_AMBA
1008 select ICST
1009 select MIGHT_HAVE_CACHE_L2X0
1010 select USE_OF
1011 help
1012 Support for Xilinx Zynq ARM Cortex A9 Platform
1013
1014config ARCH_ZX297510
1015 bool "ZTE-TSP ZX297510"
1016 select CPU_V7
1017 select HAVE_CLK
1018 select GENERIC_CLOCKEVENTS
1019 select CLKDEV_LOOKUP
1020 select ARCH_REQUIRE_GPIOLIB
1021 select MULTI_IRQ_HANDLER
1022 select IRQ_DOMAIN
1023 select MIGHT_HAVE_CACHE_L2X0
1024 select ARCH_HAS_CPUFREQ
1025 help
1026 ZTE-TSP ZX297510 based systems
1027
1028config ARCH_ZX297520V2
1029 bool "ZTE-TSP ZX297520V2"
1030 select CPU_V7
1031 select HAVE_CLK
1032 select GENERIC_CLOCKEVENTS
1033 select CLKDEV_LOOKUP
1034 select ARCH_REQUIRE_GPIOLIB
1035 select MULTI_IRQ_HANDLER
1036 select IRQ_DOMAIN
1037 select MIGHT_HAVE_CACHE_L2X0
1038 select ARCH_HAS_CPUFREQ
1039 select PLAT_ZTE
1040 select NEED_MACH_MEMORY_H
1041 help
1042 ZTE-TSP ZX297520V2 based systems
1043
1044config ARCH_ZX297520V3
1045 bool "ZTE-TSP ZX297520V3"
1046 select CPU_V7
1047 select HAVE_CLK
1048 select GENERIC_CLOCKEVENTS
1049 select CLKDEV_LOOKUP
1050 select ARCH_REQUIRE_GPIOLIB
1051 select MULTI_IRQ_HANDLER
1052 select IRQ_DOMAIN
1053 select ARCH_HAS_CPUFREQ
1054 select PLAT_ZTE
1055 select NEED_MACH_MEMORY_H
1056 help
1057 ZTE-TSP ZX297520V3 based systems
1058
1059endchoice
1060
1061#
1062# This is sorted alphabetically by mach-* pathname. However, plat-*
1063# Kconfigs may be included either alphabetically (according to the
1064# plat- suffix) or along side the corresponding mach-* source.
1065#
1066source "arch/arm/mach-at91/Kconfig"
1067
1068source "arch/arm/mach-bcmring/Kconfig"
1069
1070source "arch/arm/mach-clps711x/Kconfig"
1071
1072source "arch/arm/mach-cns3xxx/Kconfig"
1073
1074source "arch/arm/mach-davinci/Kconfig"
1075
1076source "arch/arm/mach-dove/Kconfig"
1077
1078source "arch/arm/mach-ep93xx/Kconfig"
1079
1080source "arch/arm/mach-footbridge/Kconfig"
1081
1082source "arch/arm/mach-gemini/Kconfig"
1083
1084source "arch/arm/mach-h720x/Kconfig"
1085
1086source "arch/arm/mach-integrator/Kconfig"
1087
1088source "arch/arm/mach-iop32x/Kconfig"
1089
1090source "arch/arm/mach-iop33x/Kconfig"
1091
1092source "arch/arm/mach-iop13xx/Kconfig"
1093
1094source "arch/arm/mach-ixp4xx/Kconfig"
1095
1096source "arch/arm/mach-ixp2000/Kconfig"
1097
1098source "arch/arm/mach-ixp23xx/Kconfig"
1099
1100source "arch/arm/mach-kirkwood/Kconfig"
1101
1102source "arch/arm/mach-ks8695/Kconfig"
1103
1104source "arch/arm/mach-lpc32xx/Kconfig"
1105
1106source "arch/arm/mach-msm/Kconfig"
1107
1108source "arch/arm/mach-mv78xx0/Kconfig"
1109
1110source "arch/arm/plat-mxc/Kconfig"
1111
1112source "arch/arm/mach-mxs/Kconfig"
1113
1114source "arch/arm/mach-netx/Kconfig"
1115
1116source "arch/arm/mach-nomadik/Kconfig"
1117source "arch/arm/plat-nomadik/Kconfig"
1118
1119source "arch/arm/plat-omap/Kconfig"
1120
1121source "arch/arm/mach-omap1/Kconfig"
1122
1123source "arch/arm/mach-omap2/Kconfig"
1124
1125source "arch/arm/mach-orion5x/Kconfig"
1126
1127source "arch/arm/mach-pxa/Kconfig"
1128source "arch/arm/plat-pxa/Kconfig"
1129
1130source "arch/arm/mach-mmp/Kconfig"
1131
1132source "arch/arm/mach-realview/Kconfig"
1133
1134source "arch/arm/mach-sa1100/Kconfig"
1135
1136source "arch/arm/plat-samsung/Kconfig"
1137source "arch/arm/plat-s3c24xx/Kconfig"
1138source "arch/arm/plat-s5p/Kconfig"
1139
1140source "arch/arm/plat-spear/Kconfig"
1141
1142source "arch/arm/mach-s3c24xx/Kconfig"
1143if ARCH_S3C24XX
1144source "arch/arm/mach-s3c2412/Kconfig"
1145source "arch/arm/mach-s3c2440/Kconfig"
1146endif
1147
1148if ARCH_S3C64XX
1149source "arch/arm/mach-s3c64xx/Kconfig"
1150endif
1151
1152source "arch/arm/mach-s5p64x0/Kconfig"
1153
1154source "arch/arm/mach-s5pc100/Kconfig"
1155
1156source "arch/arm/mach-s5pv210/Kconfig"
1157
1158source "arch/arm/mach-exynos/Kconfig"
1159
1160source "arch/arm/mach-shmobile/Kconfig"
1161
1162source "arch/arm/mach-tegra/Kconfig"
1163
1164source "arch/arm/mach-u300/Kconfig"
1165
1166source "arch/arm/mach-ux500/Kconfig"
1167
1168source "arch/arm/mach-versatile/Kconfig"
1169
1170source "arch/arm/mach-vexpress/Kconfig"
1171source "arch/arm/plat-versatile/Kconfig"
1172
1173source "arch/arm/mach-vt8500/Kconfig"
1174
1175source "arch/arm/mach-w90x900/Kconfig"
1176
1177source "arch/arm/mach-zx297510/Kconfig"
1178
1179source "arch/arm/mach-zx297520v2/Kconfig"
1180
1181source "arch/arm/mach-zx297520v3/Kconfig"
1182# Definitions to make life easier
1183config PLAT_ZTE
1184 bool
1185
1186config STACK_SIZE
1187 bool "enable kernel stack size optimize"
1188 default y
1189
1190config ARCH_ACORN
1191 bool
1192
1193config PLAT_IOP
1194 bool
1195 select GENERIC_CLOCKEVENTS
1196
1197config PLAT_ORION
1198 bool
1199 select CLKSRC_MMIO
1200 select GENERIC_IRQ_CHIP
1201
1202config PLAT_PXA
1203 bool
1204
1205config PLAT_VERSATILE
1206 bool
1207
1208config ARM_TIMER_SP804
1209 bool
1210 select CLKSRC_MMIO
1211 select HAVE_SCHED_CLOCK
1212
1213source arch/arm/mm/Kconfig
1214
1215config ARM_NR_BANKS
1216 int
1217 default 16 if ARCH_EP93XX
1218 default 8
1219
1220config IWMMXT
1221 bool "Enable iWMMXt support"
1222 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1223 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1224 help
1225 Enable support for iWMMXt context switching at run time if
1226 running on a CPU that supports it.
1227
1228config XSCALE_PMU
1229 bool
1230 depends on CPU_XSCALE
1231 default y
1232
1233config CPU_HAS_PMU
1234 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1235 (!ARCH_OMAP3 || OMAP3_EMU)
1236 default y
1237 bool
1238
1239config MULTI_IRQ_HANDLER
1240 bool
1241 help
1242 Allow each machine to specify it's own IRQ handler at run time.
1243
1244if !MMU
1245source "arch/arm/Kconfig-nommu"
1246endif
1247
1248config ARM_ERRATA_326103
1249 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1250 depends on CPU_V6
1251 help
1252 Executing a SWP instruction to read-only memory does not set bit 11
1253 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1254 treat the access as a read, preventing a COW from occurring and
1255 causing the faulting task to livelock.
1256
1257config ARM_ERRATA_411920
1258 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1259 depends on CPU_V6 || CPU_V6K
1260 help
1261 Invalidation of the Instruction Cache operation can
1262 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1263 It does not affect the MPCore. This option enables the ARM Ltd.
1264 recommended workaround.
1265
1266config ARM_ERRATA_430973
1267 bool "ARM errata: Stale prediction on replaced interworking branch"
1268 depends on CPU_V7
1269 help
1270 This option enables the workaround for the 430973 Cortex-A8
1271 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1272 interworking branch is replaced with another code sequence at the
1273 same virtual address, whether due to self-modifying code or virtual
1274 to physical address re-mapping, Cortex-A8 does not recover from the
1275 stale interworking branch prediction. This results in Cortex-A8
1276 executing the new code sequence in the incorrect ARM or Thumb state.
1277 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1278 and also flushes the branch target cache at every context switch.
1279 Note that setting specific bits in the ACTLR register may not be
1280 available in non-secure mode.
1281
1282config ARM_ERRATA_458693
1283 bool "ARM errata: Processor deadlock when a false hazard is created"
1284 depends on CPU_V7
1285 help
1286 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1287 erratum. For very specific sequences of memory operations, it is
1288 possible for a hazard condition intended for a cache line to instead
1289 be incorrectly associated with a different cache line. This false
1290 hazard might then cause a processor deadlock. The workaround enables
1291 the L1 caching of the NEON accesses and disables the PLD instruction
1292 in the ACTLR register. Note that setting specific bits in the ACTLR
1293 register may not be available in non-secure mode.
1294
1295config ARM_ERRATA_460075
1296 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1297 depends on CPU_V7
1298 help
1299 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1300 erratum. Any asynchronous access to the L2 cache may encounter a
1301 situation in which recent store transactions to the L2 cache are lost
1302 and overwritten with stale memory contents from external memory. The
1303 workaround disables the write-allocate mode for the L2 cache via the
1304 ACTLR register. Note that setting specific bits in the ACTLR register
1305 may not be available in non-secure mode.
1306
1307config ARM_ERRATA_742230
1308 bool "ARM errata: DMB operation may be faulty"
1309 depends on CPU_V7 && SMP
1310 help
1311 This option enables the workaround for the 742230 Cortex-A9
1312 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1313 between two write operations may not ensure the correct visibility
1314 ordering of the two writes. This workaround sets a specific bit in
1315 the diagnostic register of the Cortex-A9 which causes the DMB
1316 instruction to behave as a DSB, ensuring the correct behaviour of
1317 the two writes.
1318
1319config ARM_ERRATA_742231
1320 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1321 depends on CPU_V7 && SMP
1322 help
1323 This option enables the workaround for the 742231 Cortex-A9
1324 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1325 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1326 accessing some data located in the same cache line, may get corrupted
1327 data due to bad handling of the address hazard when the line gets
1328 replaced from one of the CPUs at the same time as another CPU is
1329 accessing it. This workaround sets specific bits in the diagnostic
1330 register of the Cortex-A9 which reduces the linefill issuing
1331 capabilities of the processor.
1332
1333config PL310_ERRATA_588369
1334 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1335 depends on CACHE_L2X0
1336 help
1337 The PL310 L2 cache controller implements three types of Clean &
1338 Invalidate maintenance operations: by Physical Address
1339 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1340 They are architecturally defined to behave as the execution of a
1341 clean operation followed immediately by an invalidate operation,
1342 both performing to the same memory location. This functionality
1343 is not correctly implemented in PL310 as clean lines are not
1344 invalidated as a result of these operations.
1345
1346config ARM_ERRATA_720789
1347 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1348 depends on CPU_V7
1349 help
1350 This option enables the workaround for the 720789 Cortex-A9 (prior to
1351 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1352 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1353 As a consequence of this erratum, some TLB entries which should be
1354 invalidated are not, resulting in an incoherency in the system page
1355 tables. The workaround changes the TLB flushing routines to invalidate
1356 entries regardless of the ASID.
1357
1358config PL310_ERRATA_727915
1359 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1360 depends on CACHE_L2X0
1361 help
1362 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1363 operation (offset 0x7FC). This operation runs in background so that
1364 PL310 can handle normal accesses while it is in progress. Under very
1365 rare circumstances, due to this erratum, write data can be lost when
1366 PL310 treats a cacheable write transaction during a Clean &
1367 Invalidate by Way operation.
1368
1369config ARM_ERRATA_743622
1370 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1371 depends on CPU_V7
1372 help
1373 This option enables the workaround for the 743622 Cortex-A9
1374 (r2p*) erratum. Under very rare conditions, a faulty
1375 optimisation in the Cortex-A9 Store Buffer may lead to data
1376 corruption. This workaround sets a specific bit in the diagnostic
1377 register of the Cortex-A9 which disables the Store Buffer
1378 optimisation, preventing the defect from occurring. This has no
1379 visible impact on the overall performance or power consumption of the
1380 processor.
1381
1382config ARM_ERRATA_751472
1383 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1384 depends on CPU_V7
1385 help
1386 This option enables the workaround for the 751472 Cortex-A9 (prior
1387 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1388 completion of a following broadcasted operation if the second
1389 operation is received by a CPU before the ICIALLUIS has completed,
1390 potentially leading to corrupted entries in the cache or TLB.
1391
1392config PL310_ERRATA_753970
1393 bool "PL310 errata: cache sync operation may be faulty"
1394 depends on CACHE_PL310
1395 help
1396 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1397
1398 Under some condition the effect of cache sync operation on
1399 the store buffer still remains when the operation completes.
1400 This means that the store buffer is always asked to drain and
1401 this prevents it from merging any further writes. The workaround
1402 is to replace the normal offset of cache sync operation (0x730)
1403 by another offset targeting an unmapped PL310 register 0x740.
1404 This has the same effect as the cache sync operation: store buffer
1405 drain and waiting for all buffers empty.
1406
1407config ARM_ERRATA_754322
1408 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1409 depends on CPU_V7
1410 help
1411 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1412 r3p*) erratum. A speculative memory access may cause a page table walk
1413 which starts prior to an ASID switch but completes afterwards. This
1414 can populate the micro-TLB with a stale entry which may be hit with
1415 the new ASID. This workaround places two dsb instructions in the mm
1416 switching code so that no page table walks can cross the ASID switch.
1417
1418config ARM_ERRATA_754327
1419 bool "ARM errata: no automatic Store Buffer drain"
1420 depends on CPU_V7 && SMP
1421 help
1422 This option enables the workaround for the 754327 Cortex-A9 (prior to
1423 r2p0) erratum. The Store Buffer does not have any automatic draining
1424 mechanism and therefore a livelock may occur if an external agent
1425 continuously polls a memory location waiting to observe an update.
1426 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1427 written polling loops from denying visibility of updates to memory.
1428
1429config ARM_ERRATA_364296
1430 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1431 depends on CPU_V6 && !SMP
1432 help
1433 This options enables the workaround for the 364296 ARM1136
1434 r0p2 erratum (possible cache data corruption with
1435 hit-under-miss enabled). It sets the undocumented bit 31 in
1436 the auxiliary control register and the FI bit in the control
1437 register, thus disabling hit-under-miss without putting the
1438 processor into full low interrupt latency mode. ARM11MPCore
1439 is not affected.
1440
1441config ARM_ERRATA_764369
1442 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1443 depends on CPU_V7 && SMP
1444 help
1445 This option enables the workaround for erratum 764369
1446 affecting Cortex-A9 MPCore with two or more processors (all
1447 current revisions). Under certain timing circumstances, a data
1448 cache line maintenance operation by MVA targeting an Inner
1449 Shareable memory region may fail to proceed up to either the
1450 Point of Coherency or to the Point of Unification of the
1451 system. This workaround adds a DSB instruction before the
1452 relevant cache maintenance functions and sets a specific bit
1453 in the diagnostic control register of the SCU.
1454
1455config PL310_ERRATA_769419
1456 bool "PL310 errata: no automatic Store Buffer drain"
1457 depends on CACHE_L2X0
1458 help
1459 On revisions of the PL310 prior to r3p2, the Store Buffer does
1460 not automatically drain. This can cause normal, non-cacheable
1461 writes to be retained when the memory system is idle, leading
1462 to suboptimal I/O performance for drivers using coherent DMA.
1463 This option adds a write barrier to the cpu_idle loop so that,
1464 on systems with an outer cache, the store buffer is drained
1465 explicitly.
1466
1467config ARM_ERRATA_775420
1468 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1469 depends on CPU_V7
1470 help
1471 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1472 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1473 operation aborts with MMU exception, it might cause the processor
1474 to deadlock. This workaround puts DSB before executing ISB if
1475 an abort may occur on cache maintenance.
1476
1477endmenu
1478
1479source "arch/arm/common/Kconfig"
1480
1481menu "Bus support"
1482
1483config ARM_AMBA
1484 bool
1485
1486config ISA
1487 bool
1488 help
1489 Find out whether you have ISA slots on your motherboard. ISA is the
1490 name of a bus system, i.e. the way the CPU talks to the other stuff
1491 inside your box. Other bus systems are PCI, EISA, MicroChannel
1492 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1493 newer boards don't support it. If you have ISA, say Y, otherwise N.
1494
1495# Select ISA DMA controller support
1496config ISA_DMA
1497 bool
1498 select ISA_DMA_API
1499
1500# Select ISA DMA interface
1501config ISA_DMA_API
1502 bool
1503
1504config PCI
1505 bool "PCI support" if MIGHT_HAVE_PCI
1506 help
1507 Find out whether you have a PCI motherboard. PCI is the name of a
1508 bus system, i.e. the way the CPU talks to the other stuff inside
1509 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1510 VESA. If you have PCI, say Y, otherwise N.
1511
1512config PCI_DOMAINS
1513 bool
1514 depends on PCI
1515
1516config PCI_NANOENGINE
1517 bool "BSE nanoEngine PCI support"
1518 depends on SA1100_NANOENGINE
1519 help
1520 Enable PCI on the BSE nanoEngine board.
1521
1522config PCI_SYSCALL
1523 def_bool PCI
1524
1525# Select the host bridge type
1526config PCI_HOST_VIA82C505
1527 bool
1528 depends on PCI && ARCH_SHARK
1529 default y
1530
1531config PCI_HOST_ITE8152
1532 bool
1533 depends on PCI && MACH_ARMCORE
1534 default y
1535 select DMABOUNCE
1536
1537source "drivers/pci/Kconfig"
1538
1539source "drivers/pcmcia/Kconfig"
1540
1541endmenu
1542
1543menu "Kernel Features"
1544
1545source "kernel/time/Kconfig"
1546
1547config HAVE_SMP
1548 bool
1549 help
1550 This option should be selected by machines which have an SMP-
1551 capable CPU.
1552
1553 The only effect of this option is to make the SMP-related
1554 options available to the user for configuration.
1555
1556config SMP
1557 bool "Symmetric Multi-Processing"
1558 depends on CPU_V6K || CPU_V7
1559 depends on GENERIC_CLOCKEVENTS
1560 depends on HAVE_SMP
1561 depends on MMU
1562 select USE_GENERIC_SMP_HELPERS
1563 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1564 help
1565 This enables support for systems with more than one CPU. If you have
1566 a system with only one CPU, like most personal computers, say N. If
1567 you have a system with more than one CPU, say Y.
1568
1569 If you say N here, the kernel will run on single and multiprocessor
1570 machines, but will use only one CPU of a multiprocessor machine. If
1571 you say Y here, the kernel will run on many, but not all, single
1572 processor machines. On a single processor machine, the kernel will
1573 run faster if you say N here.
1574
1575 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1576 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1577 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1578
1579 If you don't know what to do here, say N.
1580
1581config SMP_ON_UP
1582 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1583 depends on EXPERIMENTAL
1584 depends on SMP && !XIP_KERNEL
1585 default y
1586 help
1587 SMP kernels contain instructions which fail on non-SMP processors.
1588 Enabling this option allows the kernel to modify itself to make
1589 these instructions safe. Disabling it allows about 1K of space
1590 savings.
1591
1592 If you don't know what to do here, say Y.
1593
1594config ARM_CPU_TOPOLOGY
1595 bool "Support cpu topology definition"
1596 depends on SMP && CPU_V7
1597 default y
1598 help
1599 Support ARM cpu topology definition. The MPIDR register defines
1600 affinity between processors which is then used to describe the cpu
1601 topology of an ARM System.
1602
1603config SCHED_MC
1604 bool "Multi-core scheduler support"
1605 depends on ARM_CPU_TOPOLOGY
1606 help
1607 Multi-core scheduler support improves the CPU scheduler's decision
1608 making when dealing with multi-core CPU chips at a cost of slightly
1609 increased overhead in some places. If unsure say N here.
1610
1611config SCHED_SMT
1612 bool "SMT scheduler support"
1613 depends on ARM_CPU_TOPOLOGY
1614 help
1615 Improves the CPU scheduler's decision making when dealing with
1616 MultiThreading at a cost of slightly increased overhead in some
1617 places. If unsure say N here.
1618
1619config HAVE_ARM_SCU
1620 bool
1621 help
1622 This option enables support for the ARM system coherency unit
1623
1624config HAVE_ARM_TWD
1625 bool
1626 depends on SMP
1627 select TICK_ONESHOT
1628 help
1629 This options enables support for the ARM timer and watchdog unit
1630
1631choice
1632 prompt "Memory split"
1633 default VMSPLIT_3G
1634 help
1635 Select the desired split between kernel and user memory.
1636
1637 If you are not absolutely sure what you are doing, leave this
1638 option alone!
1639
1640 config VMSPLIT_3G
1641 bool "3G/1G user/kernel split"
1642 config VMSPLIT_2G
1643 bool "2G/2G user/kernel split"
1644 config VMSPLIT_1G
1645 bool "1G/3G user/kernel split"
1646endchoice
1647
1648config PAGE_OFFSET
1649 hex
1650 default 0x40000000 if VMSPLIT_1G
1651 default 0x80000000 if VMSPLIT_2G
1652 default 0xC0040000
1653
1654config NR_CPUS
1655 int "Maximum number of CPUs (2-32)"
1656 range 2 32
1657 depends on SMP
1658 default "4"
1659
1660config HOTPLUG_CPU
1661 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1662 depends on SMP && HOTPLUG && EXPERIMENTAL
1663 help
1664 Say Y here to experiment with turning CPUs off and on. CPUs
1665 can be controlled through /sys/devices/system/cpu.
1666
1667config LOCAL_TIMERS
1668 bool "Use local timer interrupts"
1669 depends on SMP
1670 default y
1671 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1672 help
1673 Enable support for local timers on SMP platforms, rather then the
1674 legacy IPI broadcast method. Local timers allows the system
1675 accounting to be spread across the timer interval, preventing a
1676 "thundering herd" at every timer tick.
1677
1678config ARCH_NR_GPIO
1679 int
1680 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1681 default 355 if ARCH_U8500
1682 default 264 if MACH_H4700
1683 default 0
1684 help
1685 Maximum number of GPIOs in the system.
1686
1687 If unsure, leave the default value.
1688
1689source kernel/Kconfig.preempt
1690
1691config HZ
1692 int
1693 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1694 ARCH_S5PV210 || ARCH_EXYNOS4
1695 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1696 default AT91_TIMER_HZ if ARCH_AT91
1697 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1698 default ZX29_TIMER_HZ if ARCH_ZX297510 || ARCH_ZX297520V2 || ARCH_ZX297520V3
1699 default 100
1700
1701config THUMB2_KERNEL
1702 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1703 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1704 select AEABI
1705 select ARM_ASM_UNIFIED
1706 select ARM_UNWIND
1707 help
1708 By enabling this option, the kernel will be compiled in
1709 Thumb-2 mode. A compiler/assembler that understand the unified
1710 ARM-Thumb syntax is needed.
1711
1712 If unsure, say N.
1713
1714config THUMB2_AVOID_R_ARM_THM_JUMP11
1715 bool "Work around buggy Thumb-2 short branch relocations in gas"
1716 depends on THUMB2_KERNEL && MODULES
1717 default y
1718 help
1719 Various binutils versions can resolve Thumb-2 branches to
1720 locally-defined, preemptible global symbols as short-range "b.n"
1721 branch instructions.
1722
1723 This is a problem, because there's no guarantee the final
1724 destination of the symbol, or any candidate locations for a
1725 trampoline, are within range of the branch. For this reason, the
1726 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1727 relocation in modules at all, and it makes little sense to add
1728 support.
1729
1730 The symptom is that the kernel fails with an "unsupported
1731 relocation" error when loading some modules.
1732
1733 Until fixed tools are available, passing
1734 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1735 code which hits this problem, at the cost of a bit of extra runtime
1736 stack usage in some cases.
1737
1738 The problem is described in more detail at:
1739 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1740
1741 Only Thumb-2 kernels are affected.
1742
1743 Unless you are sure your tools don't have this problem, say Y.
1744
1745config ARM_ASM_UNIFIED
1746 bool
1747
1748config AEABI
1749 bool "Use the ARM EABI to compile the kernel"
1750 help
1751 This option allows for the kernel to be compiled using the latest
1752 ARM ABI (aka EABI). This is only useful if you are using a user
1753 space environment that is also compiled with EABI.
1754
1755 Since there are major incompatibilities between the legacy ABI and
1756 EABI, especially with regard to structure member alignment, this
1757 option also changes the kernel syscall calling convention to
1758 disambiguate both ABIs and allow for backward compatibility support
1759 (selected with CONFIG_OABI_COMPAT).
1760
1761 To use this you need GCC version 4.0.0 or later.
1762
1763config OABI_COMPAT
1764 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1765 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1766 default y
1767 help
1768 This option preserves the old syscall interface along with the
1769 new (ARM EABI) one. It also provides a compatibility layer to
1770 intercept syscalls that have structure arguments which layout
1771 in memory differs between the legacy ABI and the new ARM EABI
1772 (only for non "thumb" binaries). This option adds a tiny
1773 overhead to all syscalls and produces a slightly larger kernel.
1774 If you know you'll be using only pure EABI user space then you
1775 can say N here. If this option is not selected and you attempt
1776 to execute a legacy ABI binary then the result will be
1777 UNPREDICTABLE (in fact it can be predicted that it won't work
1778 at all). If in doubt say Y.
1779
1780config ARCH_HAS_HOLES_MEMORYMODEL
1781 bool
1782
1783config ARCH_SPARSEMEM_ENABLE
1784 bool
1785
1786config ARCH_SPARSEMEM_DEFAULT
1787 def_bool ARCH_SPARSEMEM_ENABLE
1788
1789config ARCH_SELECT_MEMORY_MODEL
1790 def_bool ARCH_SPARSEMEM_ENABLE
1791
1792config HAVE_ARCH_PFN_VALID
1793 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1794
1795config HIGHMEM
1796 bool "High Memory Support"
1797 depends on MMU && !PREEMPT_RT_FULL
1798 help
1799 The address space of ARM processors is only 4 Gigabytes large
1800 and it has to accommodate user address space, kernel address
1801 space as well as some memory mapped IO. That means that, if you
1802 have a large amount of physical memory and/or IO, not all of the
1803 memory can be "permanently mapped" by the kernel. The physical
1804 memory that is not permanently mapped is called "high memory".
1805
1806 Depending on the selected kernel/user memory split, minimum
1807 vmalloc space and actual amount of RAM, you may not need this
1808 option which should result in a slightly faster kernel.
1809
1810 If unsure, say n.
1811
1812config HIGHPTE
1813 bool "Allocate 2nd-level pagetables from highmem"
1814 depends on HIGHMEM
1815
1816config HW_PERF_EVENTS
1817 bool "Enable hardware performance counter support for perf events"
1818 depends on PERF_EVENTS && CPU_HAS_PMU
1819 default y
1820 help
1821 Enable hardware performance counter support for perf events. If
1822 disabled, perf events will use software events only.
1823
1824source "mm/Kconfig"
1825
1826config FORCE_MAX_ZONEORDER
1827 int "Maximum zone order" if ARCH_SHMOBILE
1828 range 11 64 if ARCH_SHMOBILE
1829 default "9" if SA1111
1830 default "11"
1831 help
1832 The kernel memory allocator divides physically contiguous memory
1833 blocks into "zones", where each zone is a power of two number of
1834 pages. This option selects the largest power of two that the kernel
1835 keeps in the memory allocator. If you need to allocate very large
1836 blocks of physically contiguous memory, then you may need to
1837 increase this value.
1838
1839 This config option is actually maximum order plus one. For example,
1840 a value of 11 means that the largest free memory block is 2^10 pages.
1841
1842config LEDS
1843 bool "Timer and CPU usage LEDs"
1844 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1845 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1846 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1847 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1848 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1849 ARCH_AT91 || ARCH_DAVINCI || \
1850 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1851 help
1852 If you say Y here, the LEDs on your machine will be used
1853 to provide useful information about your current system status.
1854
1855 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1856 be able to select which LEDs are active using the options below. If
1857 you are compiling a kernel for the EBSA-110 or the LART however, the
1858 red LED will simply flash regularly to indicate that the system is
1859 still functional. It is safe to say Y here if you have a CATS
1860 system, but the driver will do nothing.
1861
1862config LEDS_TIMER
1863 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1864 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1865 || MACH_OMAP_PERSEUS2
1866 depends on LEDS
1867 depends on !GENERIC_CLOCKEVENTS
1868 default y if ARCH_EBSA110
1869 help
1870 If you say Y here, one of the system LEDs (the green one on the
1871 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1872 will flash regularly to indicate that the system is still
1873 operational. This is mainly useful to kernel hackers who are
1874 debugging unstable kernels.
1875
1876 The LART uses the same LED for both Timer LED and CPU usage LED
1877 functions. You may choose to use both, but the Timer LED function
1878 will overrule the CPU usage LED.
1879
1880config LEDS_CPU
1881 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1882 !ARCH_OMAP) \
1883 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1884 || MACH_OMAP_PERSEUS2
1885 depends on LEDS
1886 help
1887 If you say Y here, the red LED will be used to give a good real
1888 time indication of CPU usage, by lighting whenever the idle task
1889 is not currently executing.
1890
1891 The LART uses the same LED for both Timer LED and CPU usage LED
1892 functions. You may choose to use both, but the Timer LED function
1893 will overrule the CPU usage LED.
1894
1895config ALIGNMENT_TRAP
1896 bool
1897 depends on CPU_CP15_MMU
1898 default y if !ARCH_EBSA110
1899 select HAVE_PROC_CPU if PROC_FS
1900 help
1901 ARM processors cannot fetch/store information which is not
1902 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1903 address divisible by 4. On 32-bit ARM processors, these non-aligned
1904 fetch/store instructions will be emulated in software if you say
1905 here, which has a severe performance impact. This is necessary for
1906 correct operation of some network protocols. With an IP-only
1907 configuration it is safe to say N, otherwise say Y.
1908
1909config UACCESS_WITH_MEMCPY
1910 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1911 depends on MMU && EXPERIMENTAL
1912 default y if CPU_FEROCEON
1913 help
1914 Implement faster copy_to_user and clear_user methods for CPU
1915 cores where a 8-word STM instruction give significantly higher
1916 memory write throughput than a sequence of individual 32bit stores.
1917
1918 A possible side effect is a slight increase in scheduling latency
1919 between threads sharing the same address space if they invoke
1920 such copy operations with large buffers.
1921
1922 However, if the CPU data cache is using a write-allocate mode,
1923 this option is unlikely to provide any performance gain.
1924
1925config SECCOMP
1926 bool
1927 prompt "Enable seccomp to safely compute untrusted bytecode"
1928 ---help---
1929 This kernel feature is useful for number crunching applications
1930 that may need to compute untrusted bytecode during their
1931 execution. By using pipes or other transports made available to
1932 the process as file descriptors supporting the read/write
1933 syscalls, it's possible to isolate those applications in
1934 their own address space using seccomp. Once seccomp is
1935 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1936 and the task is only allowed to execute a few safe syscalls
1937 defined by each seccomp mode.
1938
1939config CC_STACKPROTECTOR
1940 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1941 depends on EXPERIMENTAL
1942 help
1943 This option turns on the -fstack-protector GCC feature. This
1944 feature puts, at the beginning of functions, a canary value on
1945 the stack just before the return address, and validates
1946 the value just before actually returning. Stack based buffer
1947 overflows (that need to overwrite this return address) now also
1948 overwrite the canary, which gets detected and the attack is then
1949 neutralized via a kernel panic.
1950 This feature requires gcc version 4.2 or above.
1951
1952config DEPRECATED_PARAM_STRUCT
1953 bool "Provide old way to pass kernel parameters"
1954 help
1955 This was deprecated in 2001 and announced to live on for 5 years.
1956 Some old boot loaders still use this way.
1957
1958config ARM_FLUSH_CONSOLE_ON_RESTART
1959 bool "Force flush the console on restart"
1960 help
1961 If the console is locked while the system is rebooted, the messages
1962 in the temporary logbuffer would not have propogated to all the
1963 console drivers. This option forces the console lock to be
1964 released if it failed to be acquired, which will cause all the
1965 pending messages to be flushed.
1966
1967config THREAD_DEBUG
1968 bool "Enable thread trace"
1969 default no
1970 help
1971 Enable thread trace
1972
1973config INT_DEBUG
1974 bool "Enable irq trace"
1975 default no
1976 help
1977 Enable irq trace
1978
1979endmenu
1980
1981menu "Boot options"
1982
1983config USE_OF
1984 bool "Flattened Device Tree support"
1985 select OF
1986 select OF_EARLY_FLATTREE
1987 select IRQ_DOMAIN
1988 help
1989 Include support for flattened device tree machine descriptions.
1990
1991# Compressed boot loader in ROM. Yes, we really want to ask about
1992# TEXT and BSS so we preserve their values in the config files.
1993config ZBOOT_ROM_TEXT
1994 hex "Compressed ROM boot loader base address"
1995 default "0"
1996 help
1997 The physical address at which the ROM-able zImage is to be
1998 placed in the target. Platforms which normally make use of
1999 ROM-able zImage formats normally set this to a suitable
2000 value in their defconfig file.
2001
2002 If ZBOOT_ROM is not enabled, this has no effect.
2003
2004config ZBOOT_ROM_BSS
2005 hex "Compressed ROM boot loader BSS address"
2006 default "0"
2007 help
2008 The base address of an area of read/write memory in the target
2009 for the ROM-able zImage which must be available while the
2010 decompressor is running. It must be large enough to hold the
2011 entire decompressed kernel plus an additional 128 KiB.
2012 Platforms which normally make use of ROM-able zImage formats
2013 normally set this to a suitable value in their defconfig file.
2014
2015 If ZBOOT_ROM is not enabled, this has no effect.
2016
2017config ZBOOT_ROM
2018 bool "Compressed boot loader in ROM/flash"
2019 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
2020 help
2021 Say Y here if you intend to execute your compressed kernel image
2022 (zImage) directly from ROM or flash. If unsure, say N.
2023
2024choice
2025 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2026 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
2027 default ZBOOT_ROM_NONE
2028 help
2029 Include experimental SD/MMC loading code in the ROM-able zImage.
2030 With this enabled it is possible to write the the ROM-able zImage
2031 kernel image to an MMC or SD card and boot the kernel straight
2032 from the reset vector. At reset the processor Mask ROM will load
2033 the first part of the the ROM-able zImage which in turn loads the
2034 rest the kernel image to RAM.
2035
2036config ZBOOT_ROM_NONE
2037 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2038 help
2039 Do not load image from SD or MMC
2040
2041config ZBOOT_ROM_MMCIF
2042 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2043 help
2044 Load image from MMCIF hardware block.
2045
2046config ZBOOT_ROM_SH_MOBILE_SDHI
2047 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2048 help
2049 Load image from SDHI hardware block
2050
2051endchoice
2052
2053config ARM_APPENDED_DTB
2054 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2055 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
2056 help
2057 With this option, the boot code will look for a device tree binary
2058 (DTB) appended to zImage
2059 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2060
2061 This is meant as a backward compatibility convenience for those
2062 systems with a bootloader that can't be upgraded to accommodate
2063 the documented boot protocol using a device tree.
2064
2065 Beware that there is very little in terms of protection against
2066 this option being confused by leftover garbage in memory that might
2067 look like a DTB header after a reboot if no actual DTB is appended
2068 to zImage. Do not leave this option active in a production kernel
2069 if you don't intend to always append a DTB. Proper passing of the
2070 location into r2 of a bootloader provided DTB is always preferable
2071 to this option.
2072
2073config ARM_ATAG_DTB_COMPAT
2074 bool "Supplement the appended DTB with traditional ATAG information"
2075 depends on ARM_APPENDED_DTB
2076 help
2077 Some old bootloaders can't be updated to a DTB capable one, yet
2078 they provide ATAGs with memory configuration, the ramdisk address,
2079 the kernel cmdline string, etc. Such information is dynamically
2080 provided by the bootloader and can't always be stored in a static
2081 DTB. To allow a device tree enabled kernel to be used with such
2082 bootloaders, this option allows zImage to extract the information
2083 from the ATAG list and store it at run time into the appended DTB.
2084
2085config CMDLINE
2086 string "Default kernel command string"
2087 default ""
2088 help
2089 On some architectures (EBSA110 and CATS), there is currently no way
2090 for the boot loader to pass arguments to the kernel. For these
2091 architectures, you should supply some command-line options at build
2092 time by entering them here. As a minimum, you should specify the
2093 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2094
2095choice
2096 prompt "Kernel command line type" if CMDLINE != ""
2097 default CMDLINE_FROM_BOOTLOADER
2098
2099config CMDLINE_FROM_BOOTLOADER
2100 bool "Use bootloader kernel arguments if available"
2101 help
2102 Uses the command-line options passed by the boot loader. If
2103 the boot loader doesn't provide any, the default kernel command
2104 string provided in CMDLINE will be used.
2105
2106config CMDLINE_EXTEND
2107 bool "Extend bootloader kernel arguments"
2108 help
2109 The command-line arguments provided by the boot loader will be
2110 appended to the default kernel command string.
2111
2112config CMDLINE_FORCE
2113 bool "Always use the default kernel command string"
2114 help
2115 Always use the default kernel command string, even if the boot
2116 loader passes other arguments to the kernel.
2117 This is useful if you cannot or don't want to change the
2118 command-line options your boot loader passes to the kernel.
2119endchoice
2120
2121choice
2122 prompt "Kernel run mode"
2123 default SYSTEM_NORMAL
2124 help
2125 kernel can run normal recovery or cap mode.
2126
2127config SYSTEM_NORMAL
2128 bool "normal"
2129 help
2130 normal mode on cpuap core.
2131
2132config SYSTEM_RECOVERY
2133 bool "recovery"
2134 help
2135 recovery mode for FOTA on cpuap core.
2136
2137config SYSTEM_CAP
2138 bool "cap"
2139 help
2140 cap mode on cpucap core.
2141
2142endchoice
2143
2144config CPPS_KO
2145 bool "use CPPS KO"
2146 default n
2147 help
2148 Use CPPS KO
2149
2150config BOOT_WITHOUT_UBOOT
2151 bool "boot without uboot"
2152 default n
2153 help
2154 boot without uboot for cap system
2155
2156config BOOT_WITHOUT_UBOOT_ADDR
2157 hex "boot get r0/r1/r2 mem address without uboot"
2158 depends on BOOT_WITHOUT_UBOOT
2159 default "0"
2160 help
2161 boot get r0/r1/r2 mem address without uboot
2162
2163config XIP_KERNEL
2164 bool "Kernel Execute-In-Place from ROM"
2165 depends on !ZBOOT_ROM && !ARM_LPAE
2166 help
2167 Execute-In-Place allows the kernel to run from non-volatile storage
2168 directly addressable by the CPU, such as NOR flash. This saves RAM
2169 space since the text section of the kernel is not loaded from flash
2170 to RAM. Read-write sections, such as the data section and stack,
2171 are still copied to RAM. The XIP kernel is not compressed since
2172 it has to run directly from flash, so it will take more space to
2173 store it. The flash address used to link the kernel object files,
2174 and for storing it, is configuration dependent. Therefore, if you
2175 say Y here, you must know the proper physical address where to
2176 store the kernel image depending on your own flash memory usage.
2177
2178 Also note that the make target becomes "make xipImage" rather than
2179 "make zImage" or "make Image". The final kernel binary to put in
2180 ROM memory will be arch/arm/boot/xipImage.
2181
2182 If unsure, say N.
2183
2184config XIP_PHYS_ADDR
2185 hex "XIP Kernel Physical Location"
2186 depends on XIP_KERNEL
2187 default "0x00080000"
2188 help
2189 This is the physical address in your flash memory the kernel will
2190 be linked for and stored to. This address is dependent on your
2191 own flash usage.
2192
2193config KEXEC
2194 bool "Kexec system call (EXPERIMENTAL)"
2195 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2196 help
2197 kexec is a system call that implements the ability to shutdown your
2198 current kernel, and to start another kernel. It is like a reboot
2199 but it is independent of the system firmware. And like a reboot
2200 you can start any kernel with it, not just Linux.
2201
2202 It is an ongoing process to be certain the hardware in a machine
2203 is properly shutdown, so do not be surprised if this code does not
2204 initially work for you. It may help to enable device hotplugging
2205 support.
2206
2207config ATAGS_PROC
2208 bool "Export atags in procfs"
2209 depends on KEXEC
2210 default y
2211 help
2212 Should the atags used to boot the kernel be exported in an "atags"
2213 file in procfs. Useful with kexec.
2214
2215config CRASH_DUMP
2216 bool "Build kdump crash kernel (EXPERIMENTAL)"
2217 depends on EXPERIMENTAL
2218 help
2219 Generate crash dump after being started by kexec. This should
2220 be normally only set in special crash dump kernels which are
2221 loaded in the main kernel with kexec-tools into a specially
2222 reserved region and then later executed after a crash by
2223 kdump/kexec. The crash dump kernel must be compiled to a
2224 memory address not used by the main kernel
2225
2226 For more details see Documentation/kdump/kdump.txt
2227
2228config AUTO_ZRELADDR
2229 bool "Auto calculation of the decompressed kernel image address"
2230 depends on !ZBOOT_ROM && !ARCH_U300
2231 help
2232 ZRELADDR is the physical address where the decompressed kernel
2233 image will be placed. If AUTO_ZRELADDR is selected, the address
2234 will be determined at run-time by masking the current IP with
2235 0xf8000000. This assumes the zImage being placed in the first 128MB
2236 from start of memory.
2237
2238endmenu
2239
2240menu "CPU Power Management"
2241
2242if ARCH_HAS_CPUFREQ
2243
2244source "drivers/cpufreq/Kconfig"
2245
2246config CPU_FREQ_IMX
2247 tristate "CPUfreq driver for i.MX CPUs"
2248 depends on ARCH_MXC && CPU_FREQ
2249 select CPU_FREQ_TABLE
2250 help
2251 This enables the CPUfreq driver for i.MX CPUs.
2252
2253config CPU_FREQ_SA1100
2254 bool
2255
2256config CPU_FREQ_SA1110
2257 bool
2258
2259config CPU_FREQ_INTEGRATOR
2260 tristate "CPUfreq driver for ARM Integrator CPUs"
2261 depends on ARCH_INTEGRATOR && CPU_FREQ
2262 default y
2263 help
2264 This enables the CPUfreq driver for ARM Integrator CPUs.
2265
2266 For details, take a look at <file:Documentation/cpu-freq>.
2267
2268 If in doubt, say Y.
2269
2270config CPU_FREQ_PXA
2271 bool
2272 depends on CPU_FREQ && ARCH_PXA && PXA25x
2273 default y
2274 select CPU_FREQ_TABLE
2275 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2276
2277config CPU_FREQ_S3C
2278 bool
2279 help
2280 Internal configuration node for common cpufreq on Samsung SoC
2281
2282config CPU_FREQ_S3C24XX
2283 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2284 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2285 select CPU_FREQ_S3C
2286 help
2287 This enables the CPUfreq driver for the Samsung S3C24XX family
2288 of CPUs.
2289
2290 For details, take a look at <file:Documentation/cpu-freq>.
2291
2292 If in doubt, say N.
2293
2294config CPU_FREQ_S3C24XX_PLL
2295 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2296 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2297 help
2298 Compile in support for changing the PLL frequency from the
2299 S3C24XX series CPUfreq driver. The PLL takes time to settle
2300 after a frequency change, so by default it is not enabled.
2301
2302 This also means that the PLL tables for the selected CPU(s) will
2303 be built which may increase the size of the kernel image.
2304
2305config CPU_FREQ_S3C24XX_DEBUG
2306 bool "Debug CPUfreq Samsung driver core"
2307 depends on CPU_FREQ_S3C24XX
2308 help
2309 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2310
2311config CPU_FREQ_S3C24XX_IODEBUG
2312 bool "Debug CPUfreq Samsung driver IO timing"
2313 depends on CPU_FREQ_S3C24XX
2314 help
2315 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2316
2317config CPU_FREQ_S3C24XX_DEBUGFS
2318 bool "Export debugfs for CPUFreq"
2319 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2320 help
2321 Export status information via debugfs.
2322
2323endif
2324
2325source "drivers/cpuidle/Kconfig"
2326
2327endmenu
2328
2329menu "Floating point emulation"
2330
2331comment "At least one emulation must be selected"
2332
2333config FPE_NWFPE
2334 bool "NWFPE math emulation"
2335 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2336 ---help---
2337 Say Y to include the NWFPE floating point emulator in the kernel.
2338 This is necessary to run most binaries. Linux does not currently
2339 support floating point hardware so you need to say Y here even if
2340 your machine has an FPA or floating point co-processor podule.
2341
2342 You may say N here if you are going to load the Acorn FPEmulator
2343 early in the bootup.
2344
2345config FPE_NWFPE_XP
2346 bool "Support extended precision"
2347 depends on FPE_NWFPE
2348 help
2349 Say Y to include 80-bit support in the kernel floating-point
2350 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2351 Note that gcc does not generate 80-bit operations by default,
2352 so in most cases this option only enlarges the size of the
2353 floating point emulator without any good reason.
2354
2355 You almost surely want to say N here.
2356
2357config FPE_FASTFPE
2358 bool "FastFPE math emulation (EXPERIMENTAL)"
2359 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2360 ---help---
2361 Say Y here to include the FAST floating point emulator in the kernel.
2362 This is an experimental much faster emulator which now also has full
2363 precision for the mantissa. It does not support any exceptions.
2364 It is very simple, and approximately 3-6 times faster than NWFPE.
2365
2366 It should be sufficient for most programs. It may be not suitable
2367 for scientific calculations, but you have to check this for yourself.
2368 If you do not feel you need a faster FP emulation you should better
2369 choose NWFPE.
2370
2371config VFP
2372 bool "VFP-format floating point maths"
2373 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2374 help
2375 Say Y to include VFP support code in the kernel. This is needed
2376 if your hardware includes a VFP unit.
2377
2378 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2379 release notes and additional status information.
2380
2381 Say N if your target does not have VFP hardware.
2382
2383config VFPv3
2384 bool
2385 depends on VFP
2386 default y if CPU_V7
2387
2388config NEON
2389 bool "Advanced SIMD (NEON) Extension support"
2390 depends on VFPv3 && CPU_V7
2391 help
2392 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2393 Extension.
2394
2395endmenu
2396
2397menu "Userspace binary formats"
2398
2399source "fs/Kconfig.binfmt"
2400
2401config ARTHUR
2402 tristate "RISC OS personality"
2403 depends on !AEABI
2404 help
2405 Say Y here to include the kernel code necessary if you want to run
2406 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2407 experimental; if this sounds frightening, say N and sleep in peace.
2408 You can also say M here to compile this support as a module (which
2409 will be called arthur).
2410
2411endmenu
2412
2413menu "Power management options"
2414
2415source "kernel/power/Kconfig"
2416
2417config ARCH_SUSPEND_POSSIBLE
2418 depends on !ARCH_S5PC100
2419 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2420 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2421 def_bool y
2422
2423config ARM_CPU_SUSPEND
2424 def_bool PM_SLEEP
2425
2426endmenu
2427
2428source "net/Kconfig"
2429
2430source "drivers/Kconfig"
2431
2432source "fs/Kconfig"
2433
2434source "arch/arm/Kconfig.debug"
2435
2436source "security/Kconfig"
2437
2438source "crypto/Kconfig"
2439
2440source "lib/Kconfig"