| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 ZXIC Inc. |
| 3 | * |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/io.h> |
| 8 | #include <asm/arch/gpio.h> |
| 9 | #include <load_mode.h> |
| 10 | #include <asm/arch/top_clock.h> |
| 11 | #include <asm/arch/cpu.h> |
| 12 | #include <board.h> |
| 13 | #include <jtag.h> |
| 14 | |
| 15 | #if _ZLOADER_TRACE_DEBUG |
| 16 | |
| 17 | uint32_t patch = 0; /* ûÓÐÈκÎ×÷Óã¬ÓÃÀ´ÅäºÏBSS¶ÎÇåÁã */ |
| 18 | |
| 19 | void debug_config(void) |
| 20 | { |
| 21 | unsigned int tmp = 0; |
| 22 | int ret = 0; |
| 23 | patch = patch; |
| 24 | |
| 25 | /*¿½±´½Å±¾µÄʱÖÓ³õʼ»¯*/ |
| 26 | #ifdef CONFIG_BOARD_7520_UFI |
| 27 | /* |
| 28 | * Jtag0 |
| 29 | * 0:M0Jtag, 1:function, 2:gpio, 3:psJtag, 4:phyJtag, 5:dspJtag, 6:ufiJtag, 7:gpio |
| 30 | */ |
| 31 | |
| 32 | #ifdef CONFIG_BOARD_7520_JTAG0_M0 |
| 33 | #define JTAG0_CONNECT 0 |
| 34 | #endif |
| 35 | |
| 36 | #ifdef CONFIG_BOARD_7520_JTAG0_PS |
| 37 | #define JTAG0_CONNECT 3 |
| 38 | #endif |
| 39 | tmp = __REG(0x00143030); |
| 40 | tmp &= 0xff0000f0; |
| 41 | tmp |= JTAG0_CONNECT|(JTAG0_CONNECT<<8)|(JTAG0_CONNECT<<12)|(JTAG0_CONNECT<<16)|(JTAG0_CONNECT<<20); |
| 42 | __REG(0x00143030) = tmp; |
| 43 | |
| 44 | __REG(0x100000) = 0xeafffffe; /*ps release*/ |
| 45 | writel(CPU_UFI_SW_RSTEN, CPU_R7_SUBSYS_CFG); |
| 46 | #endif |
| 47 | |
| 48 | /* |
| 49 | * D0/Jtag1 |
| 50 | * 0:gpio, 1:sd0, 2:M0Jtag, 3:psJtag, 4:phyJtag, 5:dspJtag, 6:ufiJtag, 7:testpin |
| 51 | */ |
| 52 | #ifdef CONFIG_BOARD_7520_EVB |
| 53 | #define JTAG1_CONNECT 3 |
| 54 | tmp=__REG(0x00143028); |
| 55 | tmp=tmp&0xf0000ff0|0x03333003; |
| 56 | __REG(0x00143028) = tmp; |
| 57 | |
| 58 | __REG(0x100000) = 0xeafffffe; /*ps release*/ |
| 59 | writel(CPU_UFI_SW_RSTEN, CPU_R7_SUBSYS_CFG); |
| 60 | #endif |
| 61 | |
| 62 | #if 0 |
| 63 | /* ps */ |
| 64 | __REG(SYS_IRAM2_BASE) = 0xEAFFFFFE; /* while(1) */ |
| 65 | __REG(CPU_PS_SUBSYS_CFG) = CPU_PS_SW_RSTEN; |
| 66 | |
| 67 | /* phy */ |
| 68 | __REG(SYS_IRAM3_BASE) = 0xEAFFFFFE; /* while(1) */ /* while(1) */ |
| 69 | __REG(CPU_PHY_SUBSYS_CFG) = CPU_PHY_SW_RSTEN; |
| 70 | |
| 71 | /* A9 */ |
| 72 | __REG(SYS_IRAM6_BASE) = 0xEAFFFFFE; /* while(1) */ |
| 73 | __REG(CPU_UFI_SUBSYS_CFG) = CPU_UFI_SW_RSTEN; |
| 74 | |
| 75 | /* release core reset */ |
| 76 | __REG(0x0010c044) = 1; // phy |
| 77 | __REG(0x0010c048) = 1; // ps |
| 78 | __REG(0x0010c04c) = 1; // ufi |
| 79 | __REG(0x0010c050) = 1; // zsp |
| 80 | |
| 81 | ret = nand_init(); |
| 82 | if( ret != 0 ) |
| 83 | while(1); |
| 84 | |
| 85 | ddr_init(); |
| 86 | |
| 87 | #ifdef CONFIG_BOARD_7520_EVB |
| 88 | /*light gpio9*/ |
| 89 | tmp = __REG(0x10d440); /* ¹¦ÄÜÒý½Å */ |
| 90 | tmp |= (0x1 << 24); |
| 91 | __REG(0x10d440) = tmp; |
| 92 | |
| 93 | |
| 94 | tmp = __REG(0x10dC04); /* config OUT */ |
| 95 | tmp &= (~(0x1<<9)); |
| 96 | __REG(0x10dC04) = tmp; |
| 97 | |
| 98 | tmp = __REG(0x10dC08); |
| 99 | tmp |= (0x1<<9); /* OUT 1 */ |
| 100 | __REG(0x10dC08) = tmp; |
| 101 | #endif |
| 102 | #endif |
| 103 | while(1); |
| 104 | } |
| 105 | |
| 106 | #endif |