| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 |
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| 2 | #if 0
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| 3 |
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| 4 | /*******************************************************************************
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| 5 | * °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
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| 6 | *
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| 7 | * ÎļþÃû³Æ£º config.h
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| 8 | * Îļþ±êʶ£º /include/config.h
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| 9 | * ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
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| 10 | * ÆäËü˵Ã÷£º
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| 11 | * µ±Ç°°æ±¾£º 1.0
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| 12 | * ×÷¡¡¡¡Õߣº ÎÌÔÆ·å
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| 13 | * Íê³ÉÈÕÆÚ£º 2010-9-30
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| 14 | *
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| 15 | *
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| 16 |
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| 17 | *******************************************************************************/
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| 18 |
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| 19 |
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| 20 |
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| 21 | #ifndef __INCLUDE_CONFIG_H_
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| 22 | #define __INCLUDE_CONFIG_H_
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| 23 | /*********************************************************************************
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| 24 | 1:open 0:close
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| 25 | * ¹¦ÄÜ SIM_EN USE_ASIC SYNC_USB_CTRL SYNC_USB_HSIC SYNC_SETADDRESS
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| 26 | * FPGA 1 0 0 0 0
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| 27 | * usb_ctrlÑéÖ¤ 0 1 1 1 1
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| 28 | * usb_hsicÑéÖ¤ 0 1 1 1 1
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| 29 | * usbtimeoutÑéÖ¤0 1 1 1 1
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| 30 | * asic 1 1 0 0 0
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| 31 | **********************************************************************************/
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| 32 | #define SIM_EN 1
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| 33 | #define USE_ASIC 0
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| 34 | #define SYNC_USB_CTRL 0
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| 35 | #define SYNC_USB_HSIC 0
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| 36 | #define SYNC_SETADDRESS 0
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| 37 |
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| 38 | #if !USE_ASIC ///0:fpga 1:asic
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| 39 | // CPUʱÖÓƵÂÊ
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| 40 | #define SYS_CPU_FREQ 50000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
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| 41 | #define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
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| 42 | #define SYS_UART_CLK_CONFIG_PLL 25000000 // ʱÖÓƵÂÊ
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| 43 | #else
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| 44 | // CPUʱÖÓƵÂÊ
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| 45 | #define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
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| 46 | #define SYS_UART_CLK (26000000/6) // ʱÖÓƵÂÊ
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| 47 | #define SYS_UART_CLK_CONFIG_PLL 104000000 // ʱÖÓƵÂÊ
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| 48 | #endif
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| 49 | // Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
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| 50 | #define SYS_BOOTSEL_BASE 0x0010c03c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
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| 51 |
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| 52 | #define SOC_CRM_BASE (0x0010c000)
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| 53 | #define BOOT_SEL (0x3c)
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| 54 | #define NAND_CFG (0x34)
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| 55 | #define SOC_MOD_CLKEN0 (0x0010c00c)
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| 56 | #define SOC_MOD_CLKEN1 (0x0010c010)
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| 57 | #define SOC_MOD_RSTEN (0x0010c018)
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| 58 | #define SOC_MOD_USBSTATECTRL (0x0010c05c)
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| 59 | #define SOC_MOD_RSTEN1 (0x0010c064)
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| 60 |
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| 61 | #define CFG_STACK_TOP 0x0008AFE0 // ¶¨ÒåÁËÕ»¶¥
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| 62 |
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| 63 | // UART ²ÎÊý
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| 64 | #define SYS_UART_BASE 0x00102000 // »ùµØÖ·
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| 65 | //#define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
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| 66 | #define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
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| 67 | #define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
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| 68 | #if !USE_ASIC
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| 69 | // USB ²ÎÊý
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| 70 | #define SYS_USB_BASE 0x01240000 // »ùµØÖ·
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| 71 | #define SYS_USB_HSIC_BASE 0x01280000 // »ùµØÖ·
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| 72 | #else
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| 73 | #define SYS_USB_BASE 0x01280000 // »ùµØÖ·
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| 74 | #define SYS_USB_HSIC_BASE 0x01240000 // »ùµØÖ·
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| 75 | #endif
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| 76 |
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| 77 |
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| 78 | // NAND FLASH ²ÎÊý
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| 79 | #define SYS_NAND_BASE 0x01207000 // ¼Ä´æÆ÷»ùµØÖ·
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| 80 | #define SYS_NAND_DATA 0x01208000 // Êý¾Ý»ùµØÖ·
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| 81 |
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| 82 | // ͨÓòÎÊý
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| 83 | #define CFG_LOAD_BASE 0x0008B000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
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| 84 | #define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
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| 85 | #define CFG_PRINT_BUF_SIZE 256
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| 86 |
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| 87 | #define POWER_DOMAIN_ISO (0x0010d200+0x41*4)
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| 88 | #define POWER_DOMAIN_POWERON (0x0010d200+0x42*4)
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| 89 | #define POWER_DOMAIN_RST (0x0010d200+0x40*4)
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| 90 |
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| 91 | //ÑéÖ¤ÐèÒª
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| 92 | #if SYNC_USB_CTRL
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| 93 | #define ARM_PORTA (0x102040)
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| 94 | #endif
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| 95 |
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| 96 | #if SYNC_USB_HSIC
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| 97 | #define REG_GPIO_OUT 0x01400014
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| 98 | #define REG_GPIO_IN 0x01409020
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| 99 | #endif
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| 100 | #define CFG_USB30_LOAD_BASE 0x62000000 //USB30 ÄÚ²¿DMAÊý¾ÝÏÂÔصØÖ·
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| 101 | #endif
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| 102 | #endif
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| 103 | /******************************************************************************/
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| 104 | /*******************************************************************************
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| 105 | * °æȨËùÓÐ (C)2010, ÉîÛÚÊÐÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
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| 106 | *
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| 107 | * ÎļþÃû³Æ£º config.h
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| 108 | * Îļþ±êʶ£º /include/config.h
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| 109 | * ÄÚÈÝÕªÒª£º ÒýÈ뿪·¢°åµÄÅäÖÃÎļþ
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| 110 | * ÆäËü˵Ã÷£º
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| 111 | * µ±Ç°°æ±¾£º 1.0
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| 112 | * ×÷¡¡¡¡Õߣº
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| 113 | * Íê³ÉÈÕÆÚ£º
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| 114 | *
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| 115 | *
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| 116 | *******************************************************************************/
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| 117 | #ifndef __INCLUDE_CONFIG_H_
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| 118 | #define __INCLUDE_CONFIG_H_
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| 119 |
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| 120 | #define FPGA 0
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| 121 | #define ASIC 1
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| 122 | #define EMULATION 2
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| 123 | #define ULPI 0
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| 124 | #define UTMI 1
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| 125 |
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| 126 | /*ͨ¹ýºê¶¨ÒåÀ´Ñ¡Ôñ°æ±¾·½Ê½*/
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| 127 | #define SIM_EN FPGA
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| 128 |
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| 129 | #define USB_PHY UTMI
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| 130 |
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| 131 | //IRAM0 0x62000000 IRAM2 0x80000 IRAM1 0x100000(δÓÃ)
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| 132 | #define CFG_USB30_LOAD_BASE 0x62000000 //USB30 ÄÚ²¿DMAÊý¾ÝÏÂÔصØÖ·
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| 133 | #define CFG_SDIO_LOAD_BASE 0x62000000 // SDIO DMA Êý¾Ý°áÔ˵ØÖ·
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| 134 | #define CFG_LOAD_BASE 0x00087000 // ¼ÓÔØ´úÂëµ½¸ÃµØÖ·,±ØÐë4K¶ÔÆë
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| 135 | #define SYS_LOAD_LEN 0x1000 // ¼ÓÔس¤¶È
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| 136 | #define CFG_PRINT_BUF_SIZE 256
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| 137 | #define CFG_STACK_TOP 0x86800
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| 138 |
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| 139 | #if ((SIM_EN == ASIC)||(SIM_EN == EMULATION))
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| 140 | // CPUʱÖÓƵÂÊ,usb³¬Ê±»úÖƼÆʱ²ÉÓÃtick£¬Óëm0ͬƵ£¬ÇÒusb bootÐèpllʱÖÓÅäÖá£
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| 141 | #define SYS_CPU_FREQ 208000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
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| 142 | #define SYS_UART_CLK 26000000 // ʱÖÓƵÂÊ
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| 143 | #define PLL_8X(x) ((x)>>3) //pllδÅäÖÃÇ°£¬´æÔÚ8±¶µÄ¹Øϵ
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| 144 | #elif (SIM_EN == FPGA)
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| 145 | // CPUʱÖÓƵÂÊ
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| 146 | #define SYS_CPU_FREQ 30000000 // ¶¨ÒåCPUʱÖÓ,ÓÃÓÚ¼Æʱ
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| 147 | #define SYS_UART_CLK 25000000 // ʱÖÓƵÂÊ
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| 148 | #define PLL_8X(x) (x) //²»´æÔÚ±¶Êý²îÒì
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| 149 | #endif
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| 150 |
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| 151 | // Æô¶¯Ä£Ê½Ñ¡Ôñ¼Ä´æÆ÷
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| 152 | /*bootsel_info*/
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| 153 | /*[0:3] bootsel0,bootsel1,bootsel2,bootsel3
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| 154 | [4:5] nand page size
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| 155 | [6] nand data width
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| 156 | [7] nand addr cycles*/
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| 157 | /*
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| 158 | #define SYS_BOOTSEL_INFO 0x0013b04c // ¶¨ÒåBOOTSEL¼Ä´æÆ÷µØÖ·
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| 159 | #define SYS_STD_CRM_BASE 0x1307000
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| 160 | #define SYS_LSP_CRM_BASE 0x01400000
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| 161 | #define SYS_SOC_CRM_BASE 0x0013b000
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| 162 | #define SYS_PAD_CTRL0_BASE 0x143000
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| 163 | */
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| 164 |
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| 165 | #define SOC_CRM_BASE (0x0013b000)
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| 166 | #define BOOT_SEL (0x3c)
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| 167 | #define NAND_CFG (0x34)
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| 168 | #define SOC_MOD_CLKEN0 (0x0013b06c)
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| 169 | #define SOC_MOD_CLKEN1 (0x0013b06c)
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| 170 | #define SOC_MOD_RSTEN (0x0013b080)
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| 171 | #define SOC_MOD_USBSTATECTRL (0x0010c05c)
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| 172 | #define SOC_MOD_RSTEN1 (0x0010c064)
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| 173 |
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| 174 |
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| 175 |
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| 176 |
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| 177 |
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| 178 | /*UART ²ÎÊý*/
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| 179 | #define SYS_UART_BASE 0x0138000 // UART0 »ùµØÖ· //
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| 180 |
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| 181 | #define CFG_UART_BAUDRATE 115200 // ²¨ÌØÂÊ
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| 182 | #define CFG_BUF_SIZE 64 // Êý¾Ý»º³åÇø´óС
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| 183 |
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| 184 | /*USB BASE ADDRESS*/
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| 185 | //#define SYS_USB_BASE 0x02000000 // 3.0»ùµØÖ·
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| 186 | //#define SYS_USB_HSIC_BASE 0x01500000 // HSIC»ùµØÖ·
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| 187 |
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| 188 | #define SYS_USB_BASE 0x01500000 // 2.0»ùµØÖ·
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| 189 | #define SYS_USB_HSIC_BASE 0x01600000 // HSIC»ùµØÖ·
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| 190 | //ÒÔÉÏÊÇ7520V2оƬÖж¨ÒåµÄUSB»ùÖ·
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| 191 |
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| 192 |
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| 193 |
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| 194 |
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| 195 | /* NAND FLASH ²ÎÊý*/
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| 196 | #define SYS_NAND_BASE 0x01211000 // ¼Ä´æÆ÷»ùµØÖ·
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| 197 | #define SYS_NAND_DATA 0x01212000 // Êý¾Ý»ùµØÖ·
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| 198 |
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| 199 | /*SPI_FLASH²ÎÊý*/
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| 200 | #define SYS_SPI_FLASH_BASE 0x140c000
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| 201 |
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| 202 | /*SD/MMC ²ÎÊý*/
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| 203 | #define SYS_EMMC_REGS_BASE 0x01210000 //SD0
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| 204 | #define CFG_EMMC_CLK_REF 26000000
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| 205 | #define CFG_EMMC_CLK_ENUM 400000
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| 206 | #define CFG_EMMC_CLK_WORK 26000000
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| 207 |
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| 208 | /*SDIO SLAVE ²ÎÊý*/
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| 209 | #define SYS_SDIO_REGS_BASE 0x01540000 //SD1
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| 210 |
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| 211 |
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| 212 | #define POWER_DOMAIN_ISO (0x00140110)
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| 213 | #define POWER_DOMAIN_POWERON (0x00140114)
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| 214 | #define POWER_DOMAIN_RST (0x0014010c)
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| 215 |
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| 216 |
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| 217 | //ÑéÖ¤ÐèÒª
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| 218 | #if SIM_EN == EMULATION
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| 219 | /*USB2.0*/
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| 220 | #define ARM_PORTA (REG_GPIO_OUT)
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| 221 | /*HSIC*/
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| 222 | #define REG_GPIO_OUT 0x00145060 //7520
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| 223 | #define REG_GPIO_IN 0x00145014
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| 224 | #endif
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| 225 | #endif
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| 226 |
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