| lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | #ifndef EDCPTEST_H
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| 2 | #define EDCPTEST_H
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| 3 | void memcpy_edcp(U32* pCopyTo, U32* pSource, U32 num_index, U32 num_word);
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| 4 | void data_pre(void);
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| 5 |
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| 6 | void ul_asyn_dat_cmp( void);
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| 7 | void ul_syn_dat_cmp( void);
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| 8 | void dl_asyn_dat_cmp( void);
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| 9 |
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| 10 | void EDCP_SW_ENCRYPT(void);
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| 11 |
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| 12 |
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| 13 | //ddr data ram src addr
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| 14 | #define DDR_SRC_DATA_UL 0x24010000//0x24200000//ddr data ram base ddr 2M byte if 1496 byte enough for 1000 pdcp pdu
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| 15 | #define DDR_SRC_DATA_EMAC 0x24205000//0x24600000//ddr data ram base ddr
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| 16 | #define DDR_SRC_DATA_DL 0x245F0000//0x24A00000//ddr data ram base ddr
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| 17 | //#define DDR_SRC_DATA_CHECKSUM 0x250b0000//0x24E00000//ddr data ram base ddr
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| 18 |
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| 19 | //ddr data ram des addr
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| 20 | #define DDR_DES_DATA_UL 0x25300000// allocate to UL SYN
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| 21 | #define DDR_DES_DATA_EMAC 0x254F5000//0x25700000
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| 22 | #define DDR_DES_DATA_DL 0x25BE0000//0x25B00000
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| 23 | //#define DDR_DES_DATA_CHECKSUM 0x266A0000//0x25F00000
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| 24 |
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| 25 | #define DDR_ADDR_INTERVAL 0x2000//0x1f40//8000 //0x7D0 //2000
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| 26 |
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| 27 |
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| 28 | #define DDR_SRC_UL_ENC_DL 0x26400000
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| 29 | #define DDR_DES_UL_ENC_DL 0x27000000
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| 30 |
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| 31 | #endif /* #ifndef EDCPTEST_H */
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