blob: 2b8b72e6230a309983fb7cecf90705023e71b532 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#ifndef __DWMMC_HW_H
22#define __DWMMC_HW_H
23
24#include <asm/io.h>
25#include <mmc.h>
26
27#define DWMCI_CTRL 0x000
28#define DWMCI_PWREN 0x004
29#define DWMCI_CLKDIV 0x008
30#define DWMCI_CLKSRC 0x00C
31#define DWMCI_CLKENA 0x010
32#define DWMCI_TMOUT 0x014
33#define DWMCI_CTYPE 0x018
34#define DWMCI_BLKSIZ 0x01C
35#define DWMCI_BYTCNT 0x020
36#define DWMCI_INTMASK 0x024
37#define DWMCI_CMDARG 0x028
38#define DWMCI_CMD 0x02C
39#define DWMCI_RESP0 0x030
40#define DWMCI_RESP1 0x034
41#define DWMCI_RESP2 0x038
42#define DWMCI_RESP3 0x03C
43#define DWMCI_MINTSTS 0x040
44#define DWMCI_RINTSTS 0x044
45#define DWMCI_STATUS 0x048
46#define DWMCI_FIFOTH 0x04C
47#define DWMCI_CDETECT 0x050
48#define DWMCI_WRTPRT 0x054
49#define DWMCI_GPIO 0x058
50#define DWMCI_TCMCNT 0x05C
51#define DWMCI_TBBCNT 0x060
52#define DWMCI_DEBNCE 0x064
53#define DWMCI_USRID 0x068
54#define DWMCI_VERID 0x06C
55#define DWMCI_HCON 0x070
56#define DWMCI_UHS_REG 0x074
57#define DWMCI_BMOD 0x080
58#define DWMCI_PLDMND 0x084
59#define DWMCI_DBADDR 0x088
60#define DWMCI_IDSTS 0x08C
61#define DWMCI_IDINTEN 0x090
62#define DWMCI_DSCADDR 0x094
63#define DWMCI_BUFADDR 0x098
64#define DWMCI_CARDRDTHRCTRL 0x100
65#define DWMCI_DATA 0x200 //7520
66//#define DWMCI_DATA 0x100 //7510
67
68
69/* Interrupt Mask register */
70#define DWMCI_INTMSK_ALL 0xffffffff
71#define DWMCI_INTMSK_RE (1 << 1)
72#define DWMCI_INTMSK_CDONE (1 << 2)
73#define DWMCI_INTMSK_DTO (1 << 3)
74#define DWMCI_INTMSK_TXDR (1 << 4)
75#define DWMCI_INTMSK_RXDR (1 << 5)
76#define DWMCI_INTMSK_DCRC (1 << 7)
77#define DWMCI_INTMSK_RTO (1 << 8)
78#define DWMCI_INTMSK_DRTO (1 << 9)
79#define DWMCI_INTMSK_HTO (1 << 10)
80#define DWMCI_INTMSK_FRUN (1 << 11)
81#define DWMCI_INTMSK_HLE (1 << 12)
82#define DWMCI_INTMSK_SBE (1 << 13)
83#define DWMCI_INTMSK_ACD (1 << 14)
84#define DWMCI_INTMSK_EBE (1 << 15)
85
86/* Raw interrupt Regsiter */
87#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
88 DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
89#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
90/* CTRL register */
91#define DWMCI_CTRL_RESET (1 << 0)
92#define DWMCI_CTRL_FIFO_RESET (1 << 1)
93#define DWMCI_CTRL_DMA_RESET (1 << 2)
94#define DWMCI_DMA_EN (1 << 5)
95#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
96#define DWMCI_IDMAC_EN (1 << 25)
97#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
98 DWMCI_CTRL_DMA_RESET)
99
100/* CMD register */
101#define DWMCI_CMD_RESP_EXP (1 << 6)
102#define DWMCI_CMD_RESP_LENGTH (1 << 7)
103#define DWMCI_CMD_CHECK_CRC (1 << 8)
104#define DWMCI_CMD_DATA_EXP (1 << 9)
105#define DWMCI_CMD_RW (1 << 10)
106#define DWMCI_CMD_SEND_STOP (1 << 12)
107#define DWMCI_CMD_ABORT_STOP (1 << 14)
108#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
109#define DWMCI_CMD_UPD_CLK (1 << 21)
110#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
111#define DWMCI_CMD_START (1 << 31)
112#define DWMCI_CMD_SEND_INIT (1 << 15)
113
114
115/* CLKENA register */
116#define DWMCI_CLKEN_ENABLE (1 << 0)
117#define DWMCI_CLKEN_LOW_PWR (1 << 16)
118
119/* Card-type registe */
120#define DWMCI_CTYPE_1BIT 0
121#define DWMCI_CTYPE_4BIT (1 << 0)
122#define DWMCI_CTYPE_8BIT (1 << 16)
123
124/* Status Register */
125#define DWMCI_BUSY (1 << 9)
126
127/* FIFOTH Register */
128#define MSIZE(x) ((x) << 28)
129#define RX_WMARK(x) ((x) << 16)
130#define TX_WMARK(x) (x)
131
132#define DWMCI_IDMAC_OWN (1 << 31)
133#define DWMCI_IDMAC_CES (1 << 30)
134#define DWMCI_IDMAC_CH (1 << 4)
135#define DWMCI_IDMAC_FS (1 << 3)
136#define DWMCI_IDMAC_LD (1 << 2)
137#define DWMCI_IDMAC_ER (1 << 5)
138#define DWMCI_IDMAC_DIC (1 << 1)
139
140/* Bus Mode Register */
141#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
142#define DWMCI_BMOD_IDMAC_FB (1 << 1)
143#define DWMCI_BMOD_IDMAC_EN (1 << 7)
144
145#define ZX29_SDMMC0_BASE (0x01210000) //7520
146#define SYS_STD_CRM_BASE 0x1307000
147//#define ZX29_SDMMC0_BASE (0x01415000) //7510
148#define SD1_CAR_DET (0x0010d464) //7510
149#define CLKDIV_CLKSEL (0x0010c004)
150#define CRPM_CLKSEL (0x01400000)
151#define CRPM_CLKDIV2 (0x01400028)
152#define CRPM_MODCLK_EN (0x0140002c)
153
154/* cpu transfer */
155#define MMC_STATUS_FIFO_FULL (1 << 3)
156#define MMC_STATUS_FIFO_EMPTY (1 << 2)
157#define MMC_FIFO_DEPTH 128
158#define MMC_FIFO_WIDTH 32
159#define MMC_WIDTH_LEN (MMC_FIFO_WIDTH/8) //width length, in byte unit
160#define MMC_FIFO_LEN (MMC_FIFO_DEPTH * MMC_WIDTH_LEN) //FIFO length, in byte unit
161#define DWMCI_USE_IDMA 1
162
163struct dwmci_host {
164 char *name;
165 void *ioaddr;
166 unsigned int quirks;
167 unsigned int caps;
168 unsigned int version;
169 unsigned int clock;
170 unsigned int bus_hz;
171 int dev_index;
172 int buswidth;
173 u32 fifoth_val;
174 struct mmc *mmc;
175
176 void (*clksel)(struct dwmci_host *host);
177 unsigned int (*mmc_clk)(int dev_index);
178};
179
180struct dwmci_idmac {
181 u32 flags;
182 u32 cnt;
183 u32 addr;
184 u32 next_addr;
185};
186
187static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
188{
189 writel(val, host->ioaddr + reg);
190}
191
192static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
193{
194 writew(val, host->ioaddr + reg);
195}
196
197static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
198{
199 writeb(val, host->ioaddr + reg);
200}
201static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
202{
203 return readl(host->ioaddr + reg);
204}
205
206static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
207{
208 return readw(host->ioaddr + reg);
209}
210
211static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
212{
213 return readb(host->ioaddr + reg);
214}
215
216int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
217
218int zx29_dwmci_init(u32 regbase,int bus_width,int index);
219
220int board_mmc_init(bd_t *bis);
221
222void dwmci_jtag_change(void);
223
224
225
226
227#endif /* __DWMMC_HW_H */