lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2016, ZIXC Corporation. |
| 3 | * |
| 4 | */ |
| 5 | |
| 6 | #ifndef __ZX234290_H__ |
| 7 | #define __ZX234290_H__ |
| 8 | #include <drvs_gpio.h> |
| 9 | //#define PS_HOLD_PIN GPIO51 |
| 10 | |
| 11 | #define ZX234290_I2C_SLAVE_ADDR 0x12 |
| 12 | #define ZX234296_REG_PWRKEY_CTRL2 0x43 |
| 13 | #define ZX234290_REG_ADDR_STSA 0x04 |
| 14 | |
| 15 | #define INTR_A 0x0 |
| 16 | #define INTR_B 0x1 |
| 17 | |
| 18 | #define INTR_MASK_A 0x2 |
| 19 | #define INTR_EOADC (0x1 << 2) |
| 20 | #define INTR_PWR_ON_SHORT_PRESS (0x1 << 3) |
| 21 | #define INTR_PWR_ON_LONG_PRESS (0x1 << 4) |
| 22 | #define INTR_PWR_ON (0x1 << 5) |
| 23 | |
| 24 | #define INTR_MASK_B 0x3 |
| 25 | |
| 26 | #define STATUS_A 0x4 |
| 27 | #define STATUS_EOADC (0x1 << 2) |
| 28 | #define STATUS_PWR_ON (0x1 << 5) |
| 29 | #define STATUS_B 0x5 |
| 30 | #define STATUS_RTC_ALARM (0x1 << 0) |
| 31 | |
| 32 | #define START_UP_STATUS 0x6 |
| 33 | #define PWR_ON_START_UP (0x1 << 0) |
| 34 | #define RTC_ALARM_START_UP (0x1 << 1) |
| 35 | #define PS_HOLD_START_UP (0x1 << 2) |
| 36 | #define LLP_RESTART_UP (0x1 << 3) |
| 37 | |
| 38 | #define SYS_CONTROL 0x7 |
| 39 | //#define SINK1_ENABLE (0x1 << 0) |
| 40 | //#define SINK2_ENABLE (0x1 << 1) |
| 41 | #define ADC1_ENABLE (0x1 << 3) |
| 42 | #define ADC2_ENABLE (0x1 << 4) |
| 43 | |
| 44 | #define BUCK_MODE_CONTROL0 0xe |
| 45 | #define BUCK_MODE_CONTROL1 0xf |
| 46 | #define MMC_CTRL 0x15 |
| 47 | #define ZX234290_REG_ADDR_LDO78_VOL 0x15 |
| 48 | #define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B |
| 49 | |
| 50 | #define ZX234290_LDO8_VSEL_LSH (4) |
| 51 | #define ZX234290_LDO8_SLP_VSEL_LSH (4) |
| 52 | |
| 53 | #define ZX234290_REG_LDO_EN1 0x21 /* LDO8-1 */ |
| 54 | #define ZX234290_REG_ADC_ADC2MSB 0x27 /* CHANNEL 2 */ |
| 55 | #define ZX234290_REG_ADC_ADC2LSB 0x28 |
| 56 | #define ZX234290_REG_ADC_ADC1MSB 0x25 /* CHANNEL 2 */ |
| 57 | #define ZX234290_REG_ADC_ADC1LSB 0x26 |
| 58 | #define ZX234290_REG_ADC_VBATMSB 0x23 /* CHANNEL 2 */ |
| 59 | #define ZX234290_REG_ADC_VBATLSB 0x24 |
xf.li | e31de8b | 2023-12-26 23:38:58 -0800 | [diff] [blame^] | 60 | #define ZX234297_REG_ADDR_SINK_CONTROL 0X29 |
lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 61 | |
| 62 | #define ZX234290_REG_RTC_CONTROL2 0x31 |
| 63 | #define RTC_CONTROL2_TIE (1 << 0) |
| 64 | #define RTC_CONTROL2_AIE (1 << 1) |
| 65 | #define RTC_CONTROL2_TF (1 << 2) |
| 66 | #define RTC_CONTROL2_AF (1 << 3) |
| 67 | |
| 68 | #define ZX234290_REG_USER 0x50 |
| 69 | |
| 70 | /*define reset flag*/ |
| 71 | #define ZX234290_USER_RST_FLAG (0x0<<4)/*0x00*/ |
| 72 | #define ZX234290_WDT_RST_FLAG (0x1<<4)/*0x10*/ |
| 73 | #define ZX234290_USER_RST_UNDEFINE (0x0<<0)/*0x0*/ |
| 74 | #define ZX234290_USER_RST_TO_NORMAL (0x1<<0)/*0x1*/ |
| 75 | #define ZX234290_USER_RST_TO_CHARGER (0x2<<0)/*0x2*/ |
| 76 | #define ZX234290_USER_RST_TO_ALARM (0x3<<0)/*0x3*/ |
| 77 | #define ZX234290_USER_RST_TO_EXCEPT (0x4<<0)/*0x4*/ |
| 78 | |
| 79 | |
| 80 | #define ZX234290_REG_INTA 0x00 /* INTERRUPT */ |
| 81 | #define ZX234290_REG_INTB 0x01 |
| 82 | |
| 83 | |
| 84 | #define ZX234290_REG_SYS_CTRL 0x07 |
| 85 | /* sink control */ |
| 86 | #define ZX234297_REG_ADDR_SINK_CONTROL 0x29 |
| 87 | #define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/ |
| 88 | |
| 89 | /* 0x22 */ |
| 90 | #define ZX234297_SINK1_ON_LSH (2) |
| 91 | #define ZX234297_SINK2_ON_LSH (3) |
| 92 | #define ZX234297_SINK_ON_WID (1) |
| 93 | /* 0x29 */ |
| 94 | #define ZX234297_SINK1_CURRENT_LSH (0) |
| 95 | #define ZX234297_SINK2_CURRENT_LSH (4) |
| 96 | #define ZX234297_SINK_CURRENT_WID (4) |
| 97 | |
| 98 | typedef enum _T_ZX234290_SINK |
| 99 | { |
| 100 | SINK_1 = 0, |
| 101 | SINK_2 = 1, |
| 102 | SINK_MAX |
| 103 | }T_ZX234290_SINK; |
| 104 | |
| 105 | typedef enum _T_ZX234290_SINK_CURRENT |
| 106 | { |
| 107 | SINK_CURRENT_5MA, |
| 108 | SINK_CURRENT_10MA, |
| 109 | SINK_CURRENT_15MA, |
| 110 | SINK_CURRENT_20MA, |
| 111 | SINK_CURRENT_30MA, |
| 112 | SINK_CURRENT_40MA, |
| 113 | SINK_CURRENT_50MA, |
| 114 | SINK_CURRENT_60MA, |
| 115 | SINK_CURRENT_70MA, |
| 116 | SINK_CURRENT_80MA, |
| 117 | SINK_CURRENT_90MA, |
| 118 | SINK_CURRENT_100MA, |
| 119 | SINK_CURRENT_110MA, |
| 120 | SINK_CURRENT_120MA, |
| 121 | |
| 122 | SINK_CURRENT_MAX |
| 123 | }T_ZX234297_SINK_CURRENT; |
| 124 | |
| 125 | typedef enum _T_ZDrvZx234290_VldoD |
| 126 | { |
| 127 | VLDOD_1_400 = 0, |
| 128 | VLDOD_1_500 = 1, |
| 129 | VLDOD_1_600 = 2, |
| 130 | VLDOD_1_800 = 3, |
| 131 | VLDOD_1_850 = 4, |
| 132 | VLDOD_2_000 = 5, |
| 133 | VLDOD_2_050 = 6, |
| 134 | VLDOD_2_500 = 7, |
| 135 | VLDOD_2_550 = 8, |
| 136 | VLDOD_2_700 = 9, |
| 137 | VLDOD_2_750 = 10, |
| 138 | VLDOD_2_800 = 11, |
| 139 | VLDOD_2_850 = 12, |
| 140 | VLDOD_2_900 = 13, |
| 141 | VLDOD_2_950 = 14, |
| 142 | VLDOD_3_000 = 15, |
| 143 | |
| 144 | VLDOD_MAX |
| 145 | |
| 146 | }T_ZDrvZx234290_VldoD; |
| 147 | |
| 148 | |
| 149 | /* pwr_on long pressed time */ |
| 150 | #define ZX234290_REG_ADDR_PWRON 0x42 |
| 151 | |
| 152 | int zx234290_reset_flag(void); |
| 153 | int zx234290_write_flag(UINT8 val); |
| 154 | int pmu_pull_off_ps_hold(void); |
| 155 | int pmu_pull_on_ps_hold(void); |
| 156 | |
| 157 | /*get the poweron key state 1: poweron press 0:poweron up*/ |
| 158 | int zx234290_get_poweron_state(void); |
| 159 | int zx234290_get_rtc_state(void); |
| 160 | int zx234290_get_adc1_voltage(void); |
| 161 | int zx234290_get_adc2_voltage(void); |
| 162 | int zx234290_get_vbat_voltage(void); |
| 163 | int zx234290_set_softon(int on); |
| 164 | int zx234290_ldo8_enable(int enable); |
| 165 | int zx234290_set_sink(T_ZX234290_SINK sink_num, int is_on, T_ZX234297_SINK_CURRENT sink_current); |
| 166 | |
| 167 | |
| 168 | #endif /* __ZX234290_H__ */ |