lh | 9ed821d | 2023-04-07 01:36:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * zx297510 spi controller driver |
| 3 | * Author: ZTER |
| 4 | * from original zx297510 driver |
| 5 | * |
| 6 | * Copyright (C) 2005, 2006 ZTE Corporation |
| 7 | * Author: ZTER |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/platform_device.h> |
| 31 | #include <linux/err.h> |
| 32 | #include <linux/clk.h> |
| 33 | #include <linux/io.h> |
| 34 | #include <linux/gpio.h> |
| 35 | #include <linux/slab.h> |
| 36 | #include <linux/dmaengine.h> |
| 37 | #include <linux/dma-mapping.h> |
| 38 | #include <linux/scatterlist.h> |
| 39 | #include <linux/pm_runtime.h> |
| 40 | |
| 41 | #include <linux/spi/spi.h> |
| 42 | |
| 43 | #include <mach/clock.h> |
| 44 | #include <mach/spi.h> |
| 45 | #include <mach/gpio.h> |
| 46 | /* |
| 47 | * This macro is used to define some register default values. |
| 48 | * reg is masked with mask, the OR:ed with an (again masked) |
| 49 | * val shifted sb steps to the left. |
| 50 | */ |
| 51 | #define SPI_WRITE_BITS(reg, val, mask, sb) \ |
| 52 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) |
| 53 | |
| 54 | /* |
| 55 | * This macro is also used to define some default values. |
| 56 | * It will just shift val by sb steps to the left and mask |
| 57 | * the result with mask. |
| 58 | */ |
| 59 | #define GEN_MASK_BITS(val, mask, sb) \ |
| 60 | (((val)<<(sb)) & (mask)) |
| 61 | |
| 62 | #define DRIVE_TX 0 |
| 63 | #define DO_NOT_DRIVE_TX 1 |
| 64 | |
| 65 | #define DO_NOT_QUEUE_DMA 0 |
| 66 | #define QUEUE_DMA 1 |
| 67 | |
| 68 | #define RX_TRANSFER 1 |
| 69 | #define TX_TRANSFER 2 |
| 70 | |
| 71 | /* registers */ |
| 72 | #define SPI_VER_REG(r) (r + 0x00) |
| 73 | #define SPI_COM_CTRL(r) (r + 0x04) |
| 74 | #define SPI_FMT_CTRL(r) (r + 0x08) |
| 75 | #define SPI_DR(r) (r + 0x0C) |
| 76 | #define SPI_FIFO_CTRL(r) (r + 0x10) |
| 77 | #define SPI_FIFO_SR(r) (r + 0x14) |
| 78 | #define SPI_INTR_EN(r) (r + 0x18) |
| 79 | #define SPI_INTR_SR_SCLR(r) (r + 0x1C) |
| 80 | |
| 81 | /* |
| 82 | * SPI Version Register - SPI_VER_REG |
| 83 | */ |
| 84 | #define SPI_VER_REG_MASK_Y (0xFFUL << 16) |
| 85 | #define SPI_VER_REG_MASK_X (0xFFUL << 24) |
| 86 | |
| 87 | /* |
| 88 | * SPI Common Control Register - SPI_COM_CTRL |
| 89 | */ |
| 90 | #define SPI_COM_CTRL_MASK_LBM (0x1UL << 0) |
| 91 | #define SPI_COM_CTRL_MASK_SSPE (0x1UL << 1) |
| 92 | #define SPI_COM_CTRL_MASK_MS (0x1UL << 2) |
| 93 | #define SPI_COM_CTRL_MASK_SOD (0x1UL << 3) |
| 94 | |
| 95 | /* |
| 96 | * SPI Format Control Register - SPI_FMT_CTRL |
| 97 | */ |
| 98 | #define SPI_FMT_CTRL_MASK_FRF (0x3UL << 0) |
| 99 | #define SPI_FMT_CTRL_MASK_POL (0x1UL << 2) |
| 100 | #define SPI_FMT_CTRL_MASK_PHA (0x1UL << 3) |
| 101 | #define SPI_FMT_CTRL_MASK_DSS (0x1FUL << 4) |
| 102 | |
| 103 | /* |
| 104 | * SPI FIFO Control Register - SPI_FIFO_CTRL |
| 105 | */ |
| 106 | #define SPI_FIFO_CTRL_MASK_RX_DMA_EN (0x1UL << 2) |
| 107 | #define SPI_FIFO_CTRL_MASK_TX_DMA_EN (0x1UL << 3) |
| 108 | #define SPI_FIFO_CTRL_MASK_RX_FIFO_THRES (0xFUL << 4) |
| 109 | #define SPI_FIFO_CTRL_MASK_TX_FIFO_THRES (0xFUL << 8) |
| 110 | /* |
| 111 | * SPI FIFO Status Register - SPI_FIFO_SR |
| 112 | */ |
| 113 | |
| 114 | #define SPI_FIFO_SR_MASK_RX_BEYOND_THRES (0x1UL << 0) |
| 115 | #define SPI_FIFO_SR_MASK_TX_BEYOND_THRES (0x1UL << 1) |
| 116 | #define SPI_FIFO_SR_MASK_RX_FIFO_FULL (0x1UL << 2) |
| 117 | #define SPI_FIFO_SR_MASK_TX_FIFO_EMPTY (0x1UL << 3) |
| 118 | #define SPI_FIFO_SR_MASK_BUSY (0x1UL << 4) |
| 119 | #define SPI_FIFO_SR_MASK_RX_FIFO_CNTR (0x1FUL << 5) |
| 120 | #define SPI_FIFO_SR_MASK_TX_FIFO_CNTR (0x1FUL << 10) |
| 121 | |
| 122 | /* |
| 123 | * SPI Interrupt Enable Register - SPI_INTR_EN |
| 124 | */ |
| 125 | #define SPI_INTR_EN_MASK_RX_OVERRUN_IE (0x1UL << 0) |
| 126 | #define SPI_INTR_EN_MASK_TX_UNDERRUN_IE (0x1UL << 1) |
| 127 | #define SPI_INTR_EN_MASK_RX_FULL_IE (0x1UL << 2) |
| 128 | #define SPI_INTR_EN_MASK_TX_EMPTY_IE (0x1UL << 3) |
| 129 | #define SPI_INTR_EN_MASK_RX_THRES_IE (0x1UL << 4) |
| 130 | #define SPI_INTR_EN_MASK_TX_THRES_IE (0x1UL << 5) |
| 131 | |
| 132 | /* |
| 133 | * SPI Interrupt Status Register OR Interrupt Clear Register - SPI_INTR_SR_SCLR |
| 134 | */ |
| 135 | |
| 136 | #define SPI_INTR_SR_SCLR_MASK_RX_OVERRUN_INTR (0x1UL << 0) |
| 137 | #define SPI_INTR_SR_SCLR_MASK_TX_UNDERRUN_INTR (0x1UL << 1) |
| 138 | #define SPI_INTR_SR_SCLR_MASK_RX_FULL_INTR (0x1UL << 2) |
| 139 | #define SPI_INTR_SR_SCLR_MASK_TX_EMPTY_INTR (0x1UL << 3) |
| 140 | #define SPI_INTR_SR_SCLR_MASK_RX_THRES_INTR (0x1UL << 4) |
| 141 | #define SPI_INTR_SR_SCLR_MASK_TX_THRES_INTR (0x1UL << 5) |
| 142 | |
| 143 | /* SPI State */ |
| 144 | #define SPI_RUNNING 0 |
| 145 | #define SPI_SHUTDOWN 1 |
| 146 | |
| 147 | /* SPI WCLK Freqency */ |
| 148 | #define SPI_SPICLK_FREQ_104M 104000000 |
| 149 | |
| 150 | #define CLEAR_ALL_INTERRUPTS 0x3FUL |
| 151 | #define ENABLE_ALL_INTERRUPTS 0x3FUL |
| 152 | #define DISABLE_ALL_INTERRUPTS 0x0UL |
| 153 | /* |
| 154 | * Message State |
| 155 | * we use the spi_message.state (void *) pointer to |
| 156 | * hold a single state value, that's why all this |
| 157 | * (void *) casting is done here. |
| 158 | */ |
| 159 | #define STATE_START ((void *) 0) |
| 160 | #define STATE_RUNNING ((void *) 1) |
| 161 | #define STATE_DONE ((void *) 2) |
| 162 | #define STATE_ERROR ((void *) -1) |
| 163 | |
| 164 | /* |
| 165 | * SPI State - Whether Enabled or Disabled |
| 166 | */ |
| 167 | #define SPI_DISABLED (0) |
| 168 | #define SPI_ENABLED (1) |
| 169 | |
| 170 | /* |
| 171 | * SPI DMA State - Whether DMA Enabled or Disabled |
| 172 | */ |
| 173 | #define SPI_DMA_DISABLED (0) |
| 174 | #define SPI_DMA_ENABLED (1) |
| 175 | |
| 176 | /* |
| 177 | * SPI SOD State - Whether SOD Enabled or Disabled |
| 178 | */ |
| 179 | #define SPI_SOD_DISABLED (1) |
| 180 | #define SPI_SOD_ENABLED (0) |
| 181 | |
| 182 | |
| 183 | enum spi_fifo_threshold_level { |
| 184 | SPI_FIFO_THRES_1, |
| 185 | SPI_FIFO_THRES_2, |
| 186 | SPI_FIFO_THRES_3, |
| 187 | SPI_FIFO_THRES_4, |
| 188 | SPI_FIFO_THRES_5, |
| 189 | SPI_FIFO_THRES_6, |
| 190 | SPI_FIFO_THRES_7, |
| 191 | SPI_FIFO_THRES_8, |
| 192 | SPI_FIFO_THRES_9, |
| 193 | SPI_FIFO_THRES_10, |
| 194 | SPI_FIFO_THRES_11, |
| 195 | SPI_FIFO_THRES_12, |
| 196 | SPI_FIFO_THRES_13, |
| 197 | SPI_FIFO_THRES_14, |
| 198 | SPI_FIFO_THRES_15, |
| 199 | SPI_FIFO_THRES_16 |
| 200 | |
| 201 | }; |
| 202 | |
| 203 | |
| 204 | /* |
| 205 | * SPI Clock Parameter ranges |
| 206 | */ |
| 207 | #define DIV_MIN 0x00 |
| 208 | #define DIV_MAX 0x0F |
| 209 | |
| 210 | #define SPI_POLLING_TIMEOUT 1000 |
| 211 | |
| 212 | /* |
| 213 | * The type of reading going on on this chip |
| 214 | */ |
| 215 | enum spi_reading { |
| 216 | READING_NULL, |
| 217 | READING_U8, |
| 218 | READING_U16, |
| 219 | READING_U32 |
| 220 | }; |
| 221 | |
| 222 | /** |
| 223 | * The type of writing going on on this chip |
| 224 | */ |
| 225 | enum spi_writing { |
| 226 | WRITING_NULL, |
| 227 | WRITING_U8, |
| 228 | WRITING_U16, |
| 229 | WRITING_U32 |
| 230 | }; |
| 231 | |
| 232 | /** |
| 233 | * struct vendor_data - vendor-specific config parameters |
| 234 | * for PL022 derivates |
| 235 | * @fifodepth: depth of FIFOs (both) |
| 236 | * @max_bpw: maximum number of bits per word |
| 237 | * @unidir: supports unidirection transfers |
| 238 | * @extended_cr: 32 bit wide control register 0 with extra |
| 239 | * features and extra features in CR1 as found in the ST variants |
| 240 | * @pl023: supports a subset of the ST extensions called "PL023" |
| 241 | */ |
| 242 | struct vendor_data { |
| 243 | int fifodepth; |
| 244 | int max_bpw; |
| 245 | bool loopback; |
| 246 | }; |
| 247 | /** |
| 248 | * struct pl022 - This is the private SSP driver data structure |
| 249 | * @adev: AMBA device model hookup |
| 250 | * @vendor: vendor data for the IP block |
| 251 | * @phybase: the physical memory where the SSP device resides |
| 252 | * @virtbase: the virtual memory where the SSP is mapped |
| 253 | * @clk: outgoing clock "SPICLK" for the SPI bus |
| 254 | * @master: SPI framework hookup |
| 255 | * @master_info: controller-specific data from machine setup |
| 256 | * @kworker: thread struct for message pump |
| 257 | * @kworker_task: pointer to task for message pump kworker thread |
| 258 | * @pump_messages: work struct for scheduling work to the message pump |
| 259 | * @queue_lock: spinlock to syncronise access to message queue |
| 260 | * @queue: message queue |
| 261 | * @busy: message pump is busy |
| 262 | * @running: message pump is running |
| 263 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
| 264 | * @cur_msg: Pointer to current spi_message being processed |
| 265 | * @cur_transfer: Pointer to current spi_transfer |
| 266 | * @cur_chip: pointer to current clients chip(assigned from controller_state) |
| 267 | * @next_msg_cs_active: the next message in the queue has been examined |
| 268 | * and it was found that it uses the same chip select as the previous |
| 269 | * message, so we left it active after the previous transfer, and it's |
| 270 | * active already. |
| 271 | * @tx: current position in TX buffer to be read |
| 272 | * @tx_end: end position in TX buffer to be read |
| 273 | * @rx: current position in RX buffer to be written |
| 274 | * @rx_end: end position in RX buffer to be written |
| 275 | * @read: the type of read currently going on |
| 276 | * @write: the type of write currently going on |
| 277 | * @exp_fifo_level: expected FIFO level |
| 278 | * @dma_rx_channel: optional channel for RX DMA |
| 279 | * @dma_tx_channel: optional channel for TX DMA |
| 280 | * @sgt_rx: scattertable for the RX transfer |
| 281 | * @sgt_tx: scattertable for the TX transfer |
| 282 | * @dummypage: a dummy page used for driving data on the bus with DMA |
| 283 | */ |
| 284 | struct zx297510_spi { |
| 285 | struct platform_device *pdev; |
| 286 | struct vendor_data *vendor; |
| 287 | resource_size_t phybase; |
| 288 | void __iomem *virtbase; |
| 289 | struct clk *pclk;/* spi controller work clock */ |
| 290 | struct clk *spi_clk;/* spi clk line clock */ |
| 291 | u32 clkfreq; |
| 292 | struct spi_master *master; |
| 293 | struct zx297510_spi_controller *master_info; |
| 294 | /* Message per-transfer pump */ |
| 295 | struct tasklet_struct pump_transfers; |
| 296 | struct spi_message *cur_msg; |
| 297 | struct spi_transfer *cur_transfer; |
| 298 | struct chip_data *cur_chip; |
| 299 | bool next_msg_cs_active; |
| 300 | void *tx; |
| 301 | void *tx_end; |
| 302 | void *rx; |
| 303 | void *rx_end; |
| 304 | enum spi_reading read; |
| 305 | enum spi_writing write; |
| 306 | u32 exp_fifo_level; |
| 307 | enum spi_rx_level_trig rx_lev_trig; |
| 308 | enum spi_tx_level_trig tx_lev_trig; |
| 309 | /* DMA settings */ |
| 310 | #ifdef CONFIG_DMA_ENGINE |
| 311 | struct dma_chan *dma_rx_channel; |
| 312 | struct dma_chan *dma_tx_channel; |
| 313 | struct sg_table sgt_rx; |
| 314 | struct sg_table sgt_tx; |
| 315 | char *dummypage; |
| 316 | bool dma_running; |
| 317 | #endif |
| 318 | }; |
| 319 | |
| 320 | /** |
| 321 | * struct chip_data - To maintain runtime state of SSP for each client chip |
| 322 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
| 323 | * register is 32 bits wide rather than just 16 |
| 324 | * @cr1: Value of control register CR1 of SSP |
| 325 | * @dmacr: Value of DMA control Register of SSP |
| 326 | * @cpsr: Value of Clock prescale register |
| 327 | * @cs: Value of cs register |
| 328 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client |
| 329 | * @enable_dma: Whether to enable DMA or not |
| 330 | * @read: function ptr to be used to read when doing xfer for this chip |
| 331 | * @write: function ptr to be used to write when doing xfer for this chip |
| 332 | * @cs_control: chip select callback provided by chip |
| 333 | * @xfer_type: polling/interrupt/DMA |
| 334 | * |
| 335 | * Runtime state of the SSP controller, maintained per chip, |
| 336 | * This would be set according to the current message that would be served |
| 337 | */ |
| 338 | struct chip_data { |
| 339 | u32 ver_reg; |
| 340 | u32 com_ctrl; |
| 341 | u32 fmt_ctrl; |
| 342 | u32 fifo_ctrl; |
| 343 | // u32 intr_en; |
| 344 | u8 n_bytes; |
| 345 | u8 clk_div;/* spi clk divider */ |
| 346 | bool enable_dma; |
| 347 | enum spi_reading read; |
| 348 | enum spi_writing write; |
| 349 | //void (*cs_control) (u32 command); |
| 350 | int xfer_type; |
| 351 | }; |
| 352 | /** |
| 353 | * null_cs_control - Dummy chip select function |
| 354 | * @command: select/delect the chip |
| 355 | * |
| 356 | * If no chip select function is provided by client this is used as dummy |
| 357 | * chip select |
| 358 | */ |
| 359 | static void null_cs_control(u32 command) |
| 360 | { |
| 361 | pr_debug("zx297510 spi: dummy chip select control, CS=0x%x\n", command); |
| 362 | } |
| 363 | |
| 364 | /** |
| 365 | * giveback - current spi_message is over, schedule next message and call |
| 366 | * callback of this message. Assumes that caller already |
| 367 | * set message->status; dma and pio irqs are blocked |
| 368 | * @pl022: SSP driver private data structure |
| 369 | */ |
| 370 | static void giveback(struct zx297510_spi *zx297510spi) |
| 371 | { |
| 372 | struct spi_transfer *last_transfer; |
| 373 | zx297510spi->next_msg_cs_active = false; |
| 374 | |
| 375 | last_transfer = list_entry(zx297510spi->cur_msg->transfers.prev, |
| 376 | struct spi_transfer, |
| 377 | transfer_list); |
| 378 | |
| 379 | /* Delay if requested before any change in chip select */ |
| 380 | if (last_transfer->delay_usecs) |
| 381 | /* |
| 382 | * FIXME: This runs in interrupt context. |
| 383 | * Is this really smart? |
| 384 | */ |
| 385 | udelay(last_transfer->delay_usecs); |
| 386 | |
| 387 | if (!last_transfer->cs_change) { |
| 388 | struct spi_message *next_msg; |
| 389 | |
| 390 | /* |
| 391 | * cs_change was not set. We can keep the chip select |
| 392 | * enabled if there is message in the queue and it is |
| 393 | * for the same spi device. |
| 394 | * |
| 395 | * We cannot postpone this until pump_messages, because |
| 396 | * after calling msg->complete (below) the driver that |
| 397 | * sent the current message could be unloaded, which |
| 398 | * could invalidate the cs_control() callback... |
| 399 | */ |
| 400 | /* get a pointer to the next message, if any */ |
| 401 | next_msg = spi_get_next_queued_message(zx297510spi->master); |
| 402 | |
| 403 | /* |
| 404 | * see if the next and current messages point |
| 405 | * to the same spi device. |
| 406 | */ |
| 407 | if (next_msg && next_msg->spi != zx297510spi->cur_msg->spi) |
| 408 | next_msg = NULL; |
| 409 | //if (!next_msg || zx297510spi->cur_msg->state == STATE_ERROR) |
| 410 | // zx297510spi->cur_chip->cs_control(SSP_CHIP_DESELECT); |
| 411 | //else |
| 412 | // zx297510spi->next_msg_cs_active = true; |
| 413 | |
| 414 | } |
| 415 | |
| 416 | zx297510spi->cur_msg = NULL; |
| 417 | zx297510spi->cur_transfer = NULL; |
| 418 | zx297510spi->cur_chip = NULL; |
| 419 | spi_finalize_current_message(zx297510spi->master); |
| 420 | } |
| 421 | |
| 422 | /** |
| 423 | * flush - flush the FIFO to reach a clean state |
| 424 | * @pl022: SSP driver private data structure |
| 425 | */ |
| 426 | static int flush(struct zx297510_spi *zx297510spi) |
| 427 | { |
| 428 | unsigned long limit = loops_per_jiffy << 1; |
| 429 | |
| 430 | dev_dbg(&zx297510spi->pdev->dev, "flush\n"); |
| 431 | do { |
| 432 | while (readl(SPI_FIFO_SR(zx297510spi->virtbase)) & SPI_FIFO_SR_MASK_RX_FIFO_CNTR) |
| 433 | readl(SPI_DR(zx297510spi->virtbase)); |
| 434 | } while ((readl(SPI_FIFO_SR(zx297510spi->virtbase)) & SPI_FIFO_SR_MASK_BUSY) && limit--); |
| 435 | |
| 436 | zx297510spi->exp_fifo_level = 0; |
| 437 | |
| 438 | return limit; |
| 439 | } |
| 440 | |
| 441 | /** |
| 442 | * restore_state - Load configuration of current chip |
| 443 | * @pl022: SSP driver private data structure |
| 444 | */ |
| 445 | static void restore_state(struct zx297510_spi *zx297510spi) |
| 446 | { |
| 447 | struct chip_data *chip = zx297510spi->cur_chip; |
| 448 | |
| 449 | writel(chip->com_ctrl, SPI_COM_CTRL(zx297510spi->virtbase)); |
| 450 | writel(chip->fmt_ctrl, SPI_FMT_CTRL(zx297510spi->virtbase)); |
| 451 | writel(chip->fifo_ctrl, SPI_FIFO_CTRL(zx297510spi->virtbase)); |
| 452 | // writel(chip->intr_en, SPI_INTR_EN(zx297510spi->virtbase)); |
| 453 | /* disable all interrupts */ |
| 454 | writel(DISABLE_ALL_INTERRUPTS, SPI_INTR_EN(zx297510spi->virtbase)); |
| 455 | writel(CLEAR_ALL_INTERRUPTS, SPI_INTR_SR_SCLR(zx297510spi->virtbase)); |
| 456 | } |
| 457 | |
| 458 | /* |
| 459 | * Default spi Register Values |
| 460 | */ |
| 461 | #define DEFAULT_SPI_COM_CTRL ( \ |
| 462 | GEN_MASK_BITS(LOOPBACK_DISABLED, SPI_COM_CTRL_MASK_LBM, 0) | \ |
| 463 | GEN_MASK_BITS(SPI_DISABLED, SPI_COM_CTRL_MASK_SSPE, 1) | \ |
| 464 | GEN_MASK_BITS(SPI_MASTER, SPI_COM_CTRL_MASK_MS, 2) | \ |
| 465 | GEN_MASK_BITS(SPI_SOD_DISABLED, SPI_COM_CTRL_MASK_SOD, 3) \ |
| 466 | ) |
| 467 | |
| 468 | #define DEFAULT_SPI_FMT_CTRL ( \ |
| 469 | GEN_MASK_BITS(SPI_INTERFACE_MOTOROLA_SPI, SPI_FMT_CTRL_MASK_FRF, 0) | \ |
| 470 | GEN_MASK_BITS(SPI_CLK_POL_IDLE_LOW, SPI_FMT_CTRL_MASK_POL, 2) | \ |
| 471 | GEN_MASK_BITS(SPI_CLK_FIRST_EDGE, SPI_FMT_CTRL_MASK_PHA, 3) | \ |
| 472 | GEN_MASK_BITS(SPI_DATA_BITS_8, SPI_FMT_CTRL_MASK_DSS, 4) \ |
| 473 | ) |
| 474 | |
| 475 | #define DEFAULT_SPI_FIFO_CTRL ( \ |
| 476 | GEN_MASK_BITS(SPI_DMA_DISABLED, SPI_FIFO_CTRL_MASK_RX_DMA_EN, 2) | \ |
| 477 | GEN_MASK_BITS(SPI_DMA_DISABLED, SPI_FIFO_CTRL_MASK_TX_DMA_EN, 3) | \ |
| 478 | GEN_MASK_BITS(SPI_FIFO_THRES_8, SPI_FIFO_CTRL_MASK_RX_FIFO_THRES, 4) | \ |
| 479 | GEN_MASK_BITS(SPI_FIFO_THRES_8, SPI_FIFO_CTRL_MASK_TX_FIFO_THRES, 8) \ |
| 480 | ) |
| 481 | |
| 482 | |
| 483 | /** |
| 484 | * load_ssp_default_config - Load default configuration for SSP |
| 485 | * @pl022: SSP driver private data structure |
| 486 | */ |
| 487 | static void load_spi_default_config(struct zx297510_spi *zx297510spi) |
| 488 | { |
| 489 | writel(DEFAULT_SPI_COM_CTRL, SPI_COM_CTRL(zx297510spi->virtbase)); |
| 490 | writel(DEFAULT_SPI_FMT_CTRL, SPI_FMT_CTRL(zx297510spi->virtbase)); |
| 491 | writel(DEFAULT_SPI_FIFO_CTRL, SPI_FIFO_CTRL(zx297510spi->virtbase)); |
| 492 | writel(CLEAR_ALL_INTERRUPTS, SPI_INTR_SR_SCLR(zx297510spi->virtbase)); |
| 493 | writel(DISABLE_ALL_INTERRUPTS, SPI_INTR_EN(zx297510spi->virtbase)); |
| 494 | } |
| 495 | |
| 496 | /** |
| 497 | * This will write to TX according to the parameters |
| 498 | * set in pl022. |
| 499 | */ |
| 500 | static void write(struct zx297510_spi *zx297510spi) |
| 501 | { |
| 502 | |
| 503 | /* |
| 504 | * The FIFO depth is different between primecell variants. |
| 505 | * I believe filling in too much in the FIFO might cause |
| 506 | * errons in 8bit wide transfers on ARM variants (just 8 words |
| 507 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
| 508 | * |
| 509 | * To prevent this issue, the TX FIFO is only filled to the |
| 510 | * unused RX FIFO fill length, regardless of what the TX |
| 511 | * FIFO status flag indicates. |
| 512 | */ |
| 513 | dev_dbg(&zx297510spi->pdev->dev, |
| 514 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
| 515 | __func__, zx297510spi->rx, zx297510spi->rx_end, zx297510spi->tx, zx297510spi->tx_end); |
| 516 | |
| 517 | while ((readl(SPI_FIFO_SR(zx297510spi->virtbase)) & SPI_FIFO_SR_MASK_TX_FIFO_EMPTY) |
| 518 | && (zx297510spi->tx < zx297510spi->tx_end)) { |
| 519 | switch (zx297510spi->write) { |
| 520 | case WRITING_NULL: |
| 521 | writew(0x0, SPI_DR(zx297510spi->virtbase)); |
| 522 | break; |
| 523 | case WRITING_U8: |
| 524 | writew(*(u8 *) (zx297510spi->tx), SPI_DR(zx297510spi->virtbase)); |
| 525 | break; |
| 526 | case WRITING_U16: |
| 527 | writew((*(u16 *) (zx297510spi->tx)), SPI_DR(zx297510spi->virtbase)); |
| 528 | break; |
| 529 | case WRITING_U32: |
| 530 | writel(*(u32 *) (zx297510spi->tx), SPI_DR(zx297510spi->virtbase)); |
| 531 | break; |
| 532 | } |
| 533 | while(readl(SPI_FIFO_SR(zx297510spi->virtbase)) & SPI_FIFO_SR_MASK_BUSY) ; |
| 534 | zx297510spi->tx += (zx297510spi->cur_chip->n_bytes); |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | /** |
| 539 | * This will write to TX and read from RX according to the parameters |
| 540 | * set in pl022. |
| 541 | */ |
| 542 | static void readwriter(struct zx297510_spi *zx297510spi) |
| 543 | { |
| 544 | |
| 545 | /* |
| 546 | * The FIFO depth is different between primecell variants. |
| 547 | * I believe filling in too much in the FIFO might cause |
| 548 | * errons in 8bit wide transfers on ARM variants (just 8 words |
| 549 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
| 550 | * |
| 551 | * To prevent this issue, the TX FIFO is only filled to the |
| 552 | * unused RX FIFO fill length, regardless of what the TX |
| 553 | * FIFO status flag indicates. |
| 554 | */ |
| 555 | dev_dbg(&zx297510spi->pdev->dev, |
| 556 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
| 557 | __func__, zx297510spi->rx, zx297510spi->rx_end, zx297510spi->tx, zx297510spi->tx_end); |
| 558 | |
| 559 | /* Read as much as you can */ |
| 560 | while ((readl(SPI_FIFO_SR(zx297510spi->virtbase)) & SPI_FIFO_SR_MASK_RX_FIFO_CNTR) |
| 561 | && (zx297510spi->rx < zx297510spi->rx_end)) { |
| 562 | switch (zx297510spi->read) { |
| 563 | case READING_NULL: |
| 564 | readl(SPI_DR(zx297510spi->virtbase)); |
| 565 | break; |
| 566 | case READING_U8: |
| 567 | *(u8 *) (zx297510spi->rx) = |
| 568 | readw(SPI_DR(zx297510spi->virtbase)) & 0xFFU; |
| 569 | break; |
| 570 | case READING_U16: |
| 571 | *(u16 *) (zx297510spi->rx) = |
| 572 | (u16) readw(SPI_DR(zx297510spi->virtbase)); |
| 573 | break; |
| 574 | case READING_U32: |
| 575 | *(u32 *) (zx297510spi->rx) = |
| 576 | readl(SPI_DR(zx297510spi->virtbase)); |
| 577 | break; |
| 578 | } |
| 579 | zx297510spi->rx += (zx297510spi->cur_chip->n_bytes); |
| 580 | zx297510spi->exp_fifo_level--; |
| 581 | } |
| 582 | /* |
| 583 | * Write as much as possible up to the TX FIFO size |
| 584 | */ |
| 585 | while ((zx297510spi->exp_fifo_level < zx297510spi->vendor->fifodepth) |
| 586 | && (zx297510spi->tx < zx297510spi->tx_end)) { |
| 587 | switch (zx297510spi->write) { |
| 588 | case WRITING_NULL: |
| 589 | writew(0x0, SPI_DR(zx297510spi->virtbase)); |
| 590 | break; |
| 591 | case WRITING_U8: |
| 592 | writew(*(u8 *) (zx297510spi->tx), SPI_DR(zx297510spi->virtbase)); |
| 593 | break; |
| 594 | case WRITING_U16: |
| 595 | writew((*(u16 *) (zx297510spi->tx)), SPI_DR(zx297510spi->virtbase)); |
| 596 | break; |
| 597 | case WRITING_U32: |
| 598 | writel(*(u32 *) (zx297510spi->tx), SPI_DR(zx297510spi->virtbase)); |
| 599 | break; |
| 600 | } |
| 601 | zx297510spi->tx += (zx297510spi->cur_chip->n_bytes); |
| 602 | zx297510spi->exp_fifo_level++; |
| 603 | /* |
| 604 | * This inner reader takes care of things appearing in the RX |
| 605 | * FIFO as we're transmitting. This will happen a lot since the |
| 606 | * clock starts running when you put things into the TX FIFO, |
| 607 | * and then things are continuously clocked into the RX FIFO. |
| 608 | */ |
| 609 | while ((readl(SPI_FIFO_SR(zx297510spi->virtbase)) & SPI_FIFO_SR_MASK_RX_FIFO_CNTR) |
| 610 | && (zx297510spi->rx < zx297510spi->rx_end)) { |
| 611 | switch (zx297510spi->read) { |
| 612 | case READING_NULL: |
| 613 | readw(SPI_DR(zx297510spi->virtbase)); |
| 614 | break; |
| 615 | case READING_U8: |
| 616 | *(u8 *) (zx297510spi->rx) = |
| 617 | readw(SPI_DR(zx297510spi->virtbase)) & 0xFFU; |
| 618 | break; |
| 619 | case READING_U16: |
| 620 | *(u16 *) (zx297510spi->rx) = |
| 621 | (u16) readw(SPI_DR(zx297510spi->virtbase)); |
| 622 | break; |
| 623 | case READING_U32: |
| 624 | *(u32 *) (zx297510spi->rx) = |
| 625 | readl(SPI_DR(zx297510spi->virtbase)); |
| 626 | break; |
| 627 | } |
| 628 | zx297510spi->rx += (zx297510spi->cur_chip->n_bytes); |
| 629 | zx297510spi->exp_fifo_level--; |
| 630 | } |
| 631 | } |
| 632 | /* |
| 633 | * When we exit here the TX FIFO should be full and the RX FIFO |
| 634 | * should be empty |
| 635 | */ |
| 636 | } |
| 637 | |
| 638 | /** |
| 639 | * next_transfer - Move to the Next transfer in the current spi message |
| 640 | * @pl022: SSP driver private data structure |
| 641 | * |
| 642 | * This function moves though the linked list of spi transfers in the |
| 643 | * current spi message and returns with the state of current spi |
| 644 | * message i.e whether its last transfer is done(STATE_DONE) or |
| 645 | * Next transfer is ready(STATE_RUNNING) |
| 646 | */ |
| 647 | static void *next_transfer(struct zx297510_spi *zx297510spi) |
| 648 | { |
| 649 | struct spi_message *msg = zx297510spi->cur_msg; |
| 650 | struct spi_transfer *trans = zx297510spi->cur_transfer; |
| 651 | |
| 652 | /* Move to next transfer */ |
| 653 | if (trans->transfer_list.next != &msg->transfers) { |
| 654 | zx297510spi->cur_transfer = |
| 655 | list_entry(trans->transfer_list.next, |
| 656 | struct spi_transfer, transfer_list); |
| 657 | return STATE_RUNNING; |
| 658 | } |
| 659 | return STATE_DONE; |
| 660 | } |
| 661 | |
| 662 | /* |
| 663 | * This DMA functionality is only compiled in if we have |
| 664 | * access to the generic DMA devices/DMA engine. |
| 665 | */ |
| 666 | #ifdef CONFIG_DMA_ENGINE |
| 667 | static void unmap_free_dma_scatter(struct zx297510_spi *zx297510spi) |
| 668 | { |
| 669 | /* Unmap and free the SG tables */ |
| 670 | dma_unmap_sg(zx297510spi->dma_tx_channel->device->dev, zx297510spi->sgt_tx.sgl, |
| 671 | zx297510spi->sgt_tx.nents, DMA_TO_DEVICE); |
| 672 | dma_unmap_sg(zx297510spi->dma_rx_channel->device->dev, zx297510spi->sgt_rx.sgl, |
| 673 | zx297510spi->sgt_rx.nents, DMA_FROM_DEVICE); |
| 674 | sg_free_table(&zx297510spi->sgt_rx); |
| 675 | sg_free_table(&zx297510spi->sgt_tx); |
| 676 | } |
| 677 | |
| 678 | static void dma_callback(void *data) |
| 679 | { |
| 680 | struct zx297510_spi *zx297510spi = data; |
| 681 | struct spi_message *msg = zx297510spi->cur_msg; |
| 682 | |
| 683 | BUG_ON(!zx297510spi->sgt_rx.sgl); |
| 684 | |
| 685 | #ifdef VERBOSE_DEBUG |
| 686 | /* |
| 687 | * Optionally dump out buffers to inspect contents, this is |
| 688 | * good if you want to convince yourself that the loopback |
| 689 | * read/write contents are the same, when adopting to a new |
| 690 | * DMA engine. |
| 691 | */ |
| 692 | { |
| 693 | struct scatterlist *sg; |
| 694 | unsigned int i; |
| 695 | |
| 696 | dma_sync_sg_for_cpu(&zx297510spi->adev->dev, |
| 697 | zx297510spi->sgt_rx.sgl, |
| 698 | zx297510spi->sgt_rx.nents, |
| 699 | DMA_FROM_DEVICE); |
| 700 | |
| 701 | for_each_sg(zx297510spi->sgt_rx.sgl, sg, zx297510spi->sgt_rx.nents, i) { |
| 702 | dev_dbg(&zx297510spi->adev->dev, "SPI RX SG ENTRY: %d", i); |
| 703 | print_hex_dump(KERN_ERR, "SPI RX: ", |
| 704 | DUMP_PREFIX_OFFSET, |
| 705 | 16, |
| 706 | 1, |
| 707 | sg_virt(sg), |
| 708 | sg_dma_len(sg), |
| 709 | 1); |
| 710 | } |
| 711 | for_each_sg(zx297510spi->sgt_tx.sgl, sg, zx297510spi->sgt_tx.nents, i) { |
| 712 | dev_dbg(&zx297510spi->adev->dev, "SPI TX SG ENTRY: %d", i); |
| 713 | print_hex_dump(KERN_ERR, "SPI TX: ", |
| 714 | DUMP_PREFIX_OFFSET, |
| 715 | 16, |
| 716 | 1, |
| 717 | sg_virt(sg), |
| 718 | sg_dma_len(sg), |
| 719 | 1); |
| 720 | } |
| 721 | } |
| 722 | #endif |
| 723 | |
| 724 | unmap_free_dma_scatter(zx297510spi); |
| 725 | |
| 726 | /* Update total bytes transferred */ |
| 727 | msg->actual_length += zx297510spi->cur_transfer->len; |
| 728 | /*if (zx297510spi->cur_transfer->cs_change) |
| 729 | zx297510spi->cur_chip-> |
| 730 | cs_control(SSP_CHIP_DESELECT);*/ |
| 731 | |
| 732 | /* Move to next transfer */ |
| 733 | msg->state = next_transfer(zx297510spi); |
| 734 | tasklet_schedule(&zx297510spi->pump_transfers); |
| 735 | } |
| 736 | |
| 737 | static void setup_dma_scatter(struct zx297510_spi *zx297510spi, |
| 738 | void *buffer, |
| 739 | unsigned int length, |
| 740 | struct sg_table *sgtab) |
| 741 | { |
| 742 | struct scatterlist *sg; |
| 743 | int bytesleft = length; |
| 744 | void *bufp = buffer; |
| 745 | int mapbytes; |
| 746 | int i; |
| 747 | |
| 748 | if (buffer) { |
| 749 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
| 750 | /* |
| 751 | * If there are less bytes left than what fits |
| 752 | * in the current page (plus page alignment offset) |
| 753 | * we just feed in this, else we stuff in as much |
| 754 | * as we can. |
| 755 | */ |
| 756 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) |
| 757 | mapbytes = bytesleft; |
| 758 | else |
| 759 | mapbytes = PAGE_SIZE - offset_in_page(bufp); |
| 760 | sg_set_page(sg, virt_to_page(bufp), |
| 761 | mapbytes, offset_in_page(bufp)); |
| 762 | bufp += mapbytes; |
| 763 | bytesleft -= mapbytes; |
| 764 | dev_dbg(&zx297510spi->pdev->dev, |
| 765 | "set RX/TX target page @ %p, %d bytes, %d left\n", |
| 766 | bufp, mapbytes, bytesleft); |
| 767 | } |
| 768 | } else { |
| 769 | /* Map the dummy buffer on every page */ |
| 770 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
| 771 | if (bytesleft < PAGE_SIZE) |
| 772 | mapbytes = bytesleft; |
| 773 | else |
| 774 | mapbytes = PAGE_SIZE; |
| 775 | sg_set_page(sg, virt_to_page(zx297510spi->dummypage), |
| 776 | mapbytes, 0); |
| 777 | bytesleft -= mapbytes; |
| 778 | dev_dbg(&zx297510spi->pdev->dev, |
| 779 | "set RX/TX to dummy page %d bytes, %d left\n", |
| 780 | mapbytes, bytesleft); |
| 781 | |
| 782 | } |
| 783 | } |
| 784 | BUG_ON(bytesleft); |
| 785 | } |
| 786 | |
| 787 | /** |
| 788 | * configure_dma - configures the channels for the next transfer |
| 789 | * @pl022: SSP driver's private data structure |
| 790 | */ |
| 791 | static int configure_dma(struct zx297510_spi *zx297510spi) |
| 792 | { |
| 793 | struct dma_slave_config rx_conf = { |
| 794 | .src_addr = SPI_DR(zx297510spi->phybase), |
| 795 | .direction = DMA_DEV_TO_MEM, |
| 796 | .device_fc = false, |
| 797 | }; |
| 798 | struct dma_slave_config tx_conf = { |
| 799 | .dst_addr = SPI_DR(zx297510spi->phybase), |
| 800 | .direction = DMA_MEM_TO_DEV, |
| 801 | .device_fc = false, |
| 802 | }; |
| 803 | unsigned int pages; |
| 804 | int ret; |
| 805 | int rx_sglen, tx_sglen; |
| 806 | struct dma_chan *rxchan = zx297510spi->dma_rx_channel; |
| 807 | struct dma_chan *txchan = zx297510spi->dma_tx_channel; |
| 808 | struct dma_async_tx_descriptor *rxdesc; |
| 809 | struct dma_async_tx_descriptor *txdesc; |
| 810 | |
| 811 | /* Check that the channels are available */ |
| 812 | if (!rxchan || !txchan) |
| 813 | return -ENODEV; |
| 814 | |
| 815 | /* |
| 816 | * If supplied, the DMA burstsize should equal the FIFO trigger level. |
| 817 | * Notice that the DMA engine uses one-to-one mapping. Since we can |
| 818 | * not trigger on 2 elements this needs explicit mapping rather than |
| 819 | * calculation. |
| 820 | */ |
| 821 | switch (zx297510spi->rx_lev_trig) { |
| 822 | case SPI_RX_1_OR_MORE_ELEM: |
| 823 | rx_conf.src_maxburst = 1; |
| 824 | break; |
| 825 | case SPI_RX_4_OR_MORE_ELEM: |
| 826 | rx_conf.src_maxburst = 4; |
| 827 | break; |
| 828 | case SPI_RX_8_OR_MORE_ELEM: |
| 829 | rx_conf.src_maxburst = 8; |
| 830 | break; |
| 831 | case SPI_RX_16_OR_MORE_ELEM: |
| 832 | rx_conf.src_maxburst = 16; |
| 833 | break; |
| 834 | case SPI_RX_32_OR_MORE_ELEM: |
| 835 | rx_conf.src_maxburst = 32; |
| 836 | break; |
| 837 | default: |
| 838 | rx_conf.src_maxburst = zx297510spi->vendor->fifodepth >> 1; |
| 839 | break; |
| 840 | } |
| 841 | |
| 842 | switch (zx297510spi->tx_lev_trig) { |
| 843 | case SPI_TX_1_OR_MORE_EMPTY_LOC: |
| 844 | tx_conf.dst_maxburst = 1; |
| 845 | break; |
| 846 | case SPI_TX_4_OR_MORE_EMPTY_LOC: |
| 847 | tx_conf.dst_maxburst = 4; |
| 848 | break; |
| 849 | case SPI_TX_8_OR_MORE_EMPTY_LOC: |
| 850 | tx_conf.dst_maxburst = 8; |
| 851 | break; |
| 852 | case SPI_TX_16_OR_MORE_EMPTY_LOC: |
| 853 | tx_conf.dst_maxburst = 16; |
| 854 | break; |
| 855 | case SPI_TX_32_OR_MORE_EMPTY_LOC: |
| 856 | tx_conf.dst_maxburst = 32; |
| 857 | break; |
| 858 | default: |
| 859 | tx_conf.dst_maxburst = zx297510spi->vendor->fifodepth >> 1; |
| 860 | break; |
| 861 | } |
| 862 | |
| 863 | switch (zx297510spi->read) { |
| 864 | case READING_NULL: |
| 865 | /* Use the same as for writing */ |
| 866 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 867 | break; |
| 868 | case READING_U8: |
| 869 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 870 | break; |
| 871 | case READING_U16: |
| 872 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 873 | break; |
| 874 | case READING_U32: |
| 875 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 876 | break; |
| 877 | } |
| 878 | |
| 879 | switch (zx297510spi->write) { |
| 880 | case WRITING_NULL: |
| 881 | /* Use the same as for reading */ |
| 882 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 883 | break; |
| 884 | case WRITING_U8: |
| 885 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 886 | break; |
| 887 | case WRITING_U16: |
| 888 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 889 | break; |
| 890 | case WRITING_U32: |
| 891 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 892 | break; |
| 893 | } |
| 894 | |
| 895 | /* SPI pecularity: we need to read and write the same width */ |
| 896 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 897 | rx_conf.src_addr_width = tx_conf.dst_addr_width; |
| 898 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 899 | tx_conf.dst_addr_width = rx_conf.src_addr_width; |
| 900 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); |
| 901 | |
| 902 | dmaengine_slave_config(rxchan, &rx_conf); |
| 903 | dmaengine_slave_config(txchan, &tx_conf); |
| 904 | |
| 905 | /* Create sglists for the transfers */ |
| 906 | pages = DIV_ROUND_UP(zx297510spi->cur_transfer->len, PAGE_SIZE); |
| 907 | dev_dbg(&zx297510spi->pdev->dev, "using %d pages for transfer\n", pages); |
| 908 | |
| 909 | ret = sg_alloc_table(&zx297510spi->sgt_rx, pages, GFP_ATOMIC); |
| 910 | if (ret) |
| 911 | goto err_alloc_rx_sg; |
| 912 | |
| 913 | ret = sg_alloc_table(&zx297510spi->sgt_tx, pages, GFP_ATOMIC); |
| 914 | if (ret) |
| 915 | goto err_alloc_tx_sg; |
| 916 | |
| 917 | /* Fill in the scatterlists for the RX+TX buffers */ |
| 918 | setup_dma_scatter(zx297510spi, zx297510spi->rx, |
| 919 | zx297510spi->cur_transfer->len, &zx297510spi->sgt_rx); |
| 920 | setup_dma_scatter(zx297510spi, zx297510spi->tx, |
| 921 | zx297510spi->cur_transfer->len, &zx297510spi->sgt_tx); |
| 922 | |
| 923 | /* Map DMA buffers */ |
| 924 | rx_sglen = dma_map_sg(rxchan->device->dev, zx297510spi->sgt_rx.sgl, |
| 925 | zx297510spi->sgt_rx.nents, DMA_FROM_DEVICE); |
| 926 | if (!rx_sglen) |
| 927 | goto err_rx_sgmap; |
| 928 | |
| 929 | tx_sglen = dma_map_sg(txchan->device->dev, zx297510spi->sgt_tx.sgl, |
| 930 | zx297510spi->sgt_tx.nents, DMA_TO_DEVICE); |
| 931 | if (!tx_sglen) |
| 932 | goto err_tx_sgmap; |
| 933 | |
| 934 | /* Send both scatterlists */ |
| 935 | rxdesc = dmaengine_prep_slave_sg(rxchan, |
| 936 | zx297510spi->sgt_rx.sgl, |
| 937 | rx_sglen, |
| 938 | DMA_DEV_TO_MEM, |
| 939 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 940 | if (!rxdesc) |
| 941 | goto err_rxdesc; |
| 942 | |
| 943 | txdesc = dmaengine_prep_slave_sg(txchan, |
| 944 | zx297510spi->sgt_tx.sgl, |
| 945 | tx_sglen, |
| 946 | DMA_MEM_TO_DEV, |
| 947 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 948 | if (!txdesc) |
| 949 | goto err_txdesc; |
| 950 | |
| 951 | /* Put the callback on the RX transfer only, that should finish last */ |
| 952 | rxdesc->callback = dma_callback; |
| 953 | rxdesc->callback_param = zx297510spi; |
| 954 | |
| 955 | /* Submit and fire RX and TX with TX last so we're ready to read! */ |
| 956 | dmaengine_submit(rxdesc); |
| 957 | dmaengine_submit(txdesc); |
| 958 | dma_async_issue_pending(rxchan); |
| 959 | dma_async_issue_pending(txchan); |
| 960 | zx297510spi->dma_running = true; |
| 961 | |
| 962 | return 0; |
| 963 | |
| 964 | err_txdesc: |
| 965 | dmaengine_terminate_all(txchan); |
| 966 | err_rxdesc: |
| 967 | dmaengine_terminate_all(rxchan); |
| 968 | dma_unmap_sg(txchan->device->dev, zx297510spi->sgt_tx.sgl, |
| 969 | zx297510spi->sgt_tx.nents, DMA_TO_DEVICE); |
| 970 | err_tx_sgmap: |
| 971 | dma_unmap_sg(rxchan->device->dev, zx297510spi->sgt_rx.sgl, |
| 972 | zx297510spi->sgt_tx.nents, DMA_FROM_DEVICE); |
| 973 | err_rx_sgmap: |
| 974 | sg_free_table(&zx297510spi->sgt_tx); |
| 975 | err_alloc_tx_sg: |
| 976 | sg_free_table(&zx297510spi->sgt_rx); |
| 977 | err_alloc_rx_sg: |
| 978 | return -ENOMEM; |
| 979 | } |
| 980 | |
| 981 | static int __devinit zx297510_dma_probe(struct zx297510_spi *zx297510spi) |
| 982 | { |
| 983 | dma_cap_mask_t mask; |
| 984 | |
| 985 | /* Try to acquire a generic DMA engine slave channel */ |
| 986 | dma_cap_zero(mask); |
| 987 | dma_cap_set(DMA_SLAVE, mask); |
| 988 | /* |
| 989 | * We need both RX and TX channels to do DMA, else do none |
| 990 | * of them. |
| 991 | */ |
| 992 | zx297510spi->dma_rx_channel = dma_request_channel(mask, |
| 993 | zx297510spi->master_info->dma_filter, |
| 994 | zx297510spi->master_info->dma_rx_param); |
| 995 | if (!zx297510spi->dma_rx_channel) { |
| 996 | dev_dbg(&zx297510spi->pdev->dev, "no RX DMA channel!\n"); |
| 997 | goto err_no_rxchan; |
| 998 | } |
| 999 | |
| 1000 | zx297510spi->dma_tx_channel = dma_request_channel(mask, |
| 1001 | zx297510spi->master_info->dma_filter, |
| 1002 | zx297510spi->master_info->dma_tx_param); |
| 1003 | if (!zx297510spi->dma_tx_channel) { |
| 1004 | dev_dbg(&zx297510spi->pdev->dev, "no TX DMA channel!\n"); |
| 1005 | goto err_no_txchan; |
| 1006 | } |
| 1007 | |
| 1008 | zx297510spi->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
| 1009 | if (!zx297510spi->dummypage) { |
| 1010 | dev_dbg(&zx297510spi->pdev->dev, "no DMA dummypage!\n"); |
| 1011 | goto err_no_dummypage; |
| 1012 | } |
| 1013 | |
| 1014 | dev_info(&zx297510spi->pdev->dev, "setup for DMA on RX %s, TX %s\n", |
| 1015 | dma_chan_name(zx297510spi->dma_rx_channel), |
| 1016 | dma_chan_name(zx297510spi->dma_tx_channel)); |
| 1017 | |
| 1018 | return 0; |
| 1019 | |
| 1020 | err_no_dummypage: |
| 1021 | dma_release_channel(zx297510spi->dma_tx_channel); |
| 1022 | err_no_txchan: |
| 1023 | dma_release_channel(zx297510spi->dma_rx_channel); |
| 1024 | zx297510spi->dma_rx_channel = NULL; |
| 1025 | err_no_rxchan: |
| 1026 | dev_err(&zx297510spi->pdev->dev, |
| 1027 | "Failed to work in dma mode, work without dma!\n"); |
| 1028 | return -ENODEV; |
| 1029 | } |
| 1030 | |
| 1031 | static void terminate_dma(struct zx297510_spi *zx297510spi) |
| 1032 | { |
| 1033 | struct dma_chan *rxchan = zx297510spi->dma_rx_channel; |
| 1034 | struct dma_chan *txchan = zx297510spi->dma_tx_channel; |
| 1035 | |
| 1036 | dmaengine_terminate_all(rxchan); |
| 1037 | dmaengine_terminate_all(txchan); |
| 1038 | unmap_free_dma_scatter(zx297510spi); |
| 1039 | zx297510spi->dma_running = false; |
| 1040 | } |
| 1041 | |
| 1042 | static void zx297510_dma_remove(struct zx297510_spi *zx297510spi) |
| 1043 | { |
| 1044 | if (zx297510spi->dma_running) |
| 1045 | terminate_dma(zx297510spi); |
| 1046 | if (zx297510spi->dma_tx_channel) |
| 1047 | dma_release_channel(zx297510spi->dma_tx_channel); |
| 1048 | if (zx297510spi->dma_rx_channel) |
| 1049 | dma_release_channel(zx297510spi->dma_rx_channel); |
| 1050 | kfree(zx297510spi->dummypage); |
| 1051 | } |
| 1052 | |
| 1053 | #else |
| 1054 | static inline int configure_dma(struct zx297510_spi *zx297510spi) |
| 1055 | { |
| 1056 | return -ENODEV; |
| 1057 | } |
| 1058 | |
| 1059 | static inline int zx297510_dma_probe(struct zx297510_spi *zx297510spi) |
| 1060 | { |
| 1061 | return 0; |
| 1062 | } |
| 1063 | |
| 1064 | static inline void zx297510_dma_remove(struct zx297510_spi *zx297510spi) |
| 1065 | { |
| 1066 | } |
| 1067 | #endif |
| 1068 | |
| 1069 | /** |
| 1070 | * pl022_interrupt_handler - Interrupt handler for SSP controller |
| 1071 | * |
| 1072 | * This function handles interrupts generated for an interrupt based transfer. |
| 1073 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the |
| 1074 | * current message's state as STATE_ERROR and schedule the tasklet |
| 1075 | * pump_transfers which will do the postprocessing of the current message by |
| 1076 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no |
| 1077 | * more data, and writes data in TX FIFO till it is not full. If we complete |
| 1078 | * the transfer we move to the next transfer and schedule the tasklet. |
| 1079 | */ |
| 1080 | static irqreturn_t zx297510_interrupt_handler(int irq, void *dev_id) |
| 1081 | { |
| 1082 | struct zx297510_spi *zx297510spi = dev_id; |
| 1083 | struct spi_message *msg = zx297510spi->cur_msg; |
| 1084 | u32 irq_status = 0; |
| 1085 | u16 flag = 0; |
| 1086 | |
| 1087 | dev_dbg(&zx297510spi->pdev->dev,"in function %s \n", __FUNCTION__); |
| 1088 | |
| 1089 | if (unlikely(!msg)) { |
| 1090 | dev_err(&zx297510spi->pdev->dev, |
| 1091 | "bad message state in interrupt handler"); |
| 1092 | /* Never fail */ |
| 1093 | return IRQ_HANDLED; |
| 1094 | } |
| 1095 | |
| 1096 | /* Read the Interrupt Status Register */ |
| 1097 | irq_status = readl(SPI_INTR_SR_SCLR(zx297510spi->virtbase)); |
| 1098 | /* clear all Interrupt */ |
| 1099 | writel(CLEAR_ALL_INTERRUPTS, SPI_INTR_SR_SCLR(zx297510spi->virtbase)); |
| 1100 | |
| 1101 | dev_dbg(&zx297510spi->pdev->dev, "irq status 0x%X", irq_status); |
| 1102 | |
| 1103 | if (unlikely(!irq_status)) |
| 1104 | return IRQ_NONE; |
| 1105 | |
| 1106 | /* |
| 1107 | * This handles the FIFO interrupts, the timeout |
| 1108 | * interrupts are flatly ignored, they cannot be |
| 1109 | * trusted. |
| 1110 | */ |
| 1111 | if ( unlikely(irq_status & SPI_INTR_SR_SCLR_MASK_RX_OVERRUN_INTR) |
| 1112 | || unlikely(irq_status & SPI_INTR_SR_SCLR_MASK_TX_UNDERRUN_INTR) ) { |
| 1113 | /* |
| 1114 | * Overrun interrupt - bail out since our Data has been |
| 1115 | * corrupted |
| 1116 | */ |
| 1117 | if ( unlikely(irq_status & SPI_INTR_SR_SCLR_MASK_RX_OVERRUN_INTR) ) |
| 1118 | dev_err(&zx297510spi->pdev->dev, "RXFIFO is OVERRUN \n"); |
| 1119 | if ( unlikely(irq_status & SPI_INTR_SR_SCLR_MASK_TX_UNDERRUN_INTR)) |
| 1120 | dev_err(&zx297510spi->pdev->dev, "TXFIFO is UNDERRUN \n"); |
| 1121 | |
| 1122 | /* |
| 1123 | * Disable and clear interrupts, disable SSP, |
| 1124 | * mark message with bad status so it can be |
| 1125 | * retried. |
| 1126 | */ |
| 1127 | writel(DISABLE_ALL_INTERRUPTS, SPI_INTR_EN(zx297510spi->virtbase)); |
| 1128 | writel(CLEAR_ALL_INTERRUPTS, SPI_INTR_SR_SCLR(zx297510spi->virtbase)); |
| 1129 | writel((readl(SPI_COM_CTRL(zx297510spi->virtbase)) & (~SPI_COM_CTRL_MASK_SSPE)), |
| 1130 | SPI_COM_CTRL(zx297510spi->virtbase)); |
| 1131 | msg->state = STATE_ERROR; |
| 1132 | |
| 1133 | /* Schedule message queue handler */ |
| 1134 | tasklet_schedule(&zx297510spi->pump_transfers); |
| 1135 | return IRQ_HANDLED; |
| 1136 | } |
| 1137 | |
| 1138 | if (zx297510spi->rx != NULL ) |
| 1139 | readwriter(zx297510spi); |
| 1140 | else |
| 1141 | write(zx297510spi); |
| 1142 | |
| 1143 | dev_dbg( &zx297510spi->pdev->dev, "%s tx %p tx_end %p rx %p rx_end %p\n", __FUNCTION__, |
| 1144 | zx297510spi->tx, |
| 1145 | zx297510spi->tx_end, |
| 1146 | zx297510spi->rx, |
| 1147 | zx297510spi->rx_end); |
| 1148 | |
| 1149 | if ((zx297510spi->tx == zx297510spi->tx_end) && (flag == 0)) { |
| 1150 | u32 irq_flag = SPI_INTR_EN_MASK_RX_FULL_IE|SPI_INTR_EN_MASK_RX_OVERRUN_IE|SPI_INTR_EN_MASK_RX_THRES_IE; |
| 1151 | flag = 1; |
| 1152 | /* Disable Transmit interrupt, enable receive interrupt */ |
| 1153 | /*writel((readl(SPI_INTR_EN(zx297510spi->virtbase)) & |
| 1154 | ~SSP_CR1_MASK_TIE) | SSP_CR1_MASK_RIE, |
| 1155 | SSP_CR1(zx297502ssp->virtbase));*/ |
| 1156 | writel(irq_flag, SPI_INTR_EN(zx297510spi ->virtbase)); |
| 1157 | } |
| 1158 | |
| 1159 | /* |
| 1160 | * Since all transactions must write as much as shall be read, |
| 1161 | * we can conclude the entire transaction once RX is complete. |
| 1162 | * At this point, all TX will always be finished. |
| 1163 | */ |
| 1164 | if (zx297510spi->rx >= zx297510spi->rx_end) { |
| 1165 | /*writew(DISABLE_ALL_INTERRUPTS, |
| 1166 | SSP_IMSC(pl022->virtbase));*/ |
| 1167 | writel(DISABLE_ALL_INTERRUPTS, SPI_INTR_EN(zx297510spi->virtbase)); |
| 1168 | writel(CLEAR_ALL_INTERRUPTS, SPI_INTR_SR_SCLR(zx297510spi->virtbase)); |
| 1169 | if (unlikely(zx297510spi->rx > zx297510spi->rx_end)) { |
| 1170 | dev_warn(&zx297510spi->pdev->dev, "read %u surplus " |
| 1171 | "bytes (did you request an odd " |
| 1172 | "number of bytes on a 16bit bus?)\n", |
| 1173 | (u32) (zx297510spi->rx - zx297510spi->rx_end)); |
| 1174 | } |
| 1175 | /* Update total bytes transferred */ |
| 1176 | msg->actual_length += zx297510spi->cur_transfer->len; |
| 1177 | // if (zx297502ssp->cur_transfer->cs_change) |
| 1178 | // zx297502ssp->cur_chip->cs_control(SSP_CHIP_DESELECT); |
| 1179 | /* Move to next transfer */ |
| 1180 | msg->state = next_transfer(zx297510spi); |
| 1181 | tasklet_schedule(&zx297510spi->pump_transfers); |
| 1182 | return IRQ_HANDLED; |
| 1183 | } |
| 1184 | return IRQ_HANDLED; |
| 1185 | } |
| 1186 | |
| 1187 | /** |
| 1188 | * This sets up the pointers to memory for the next message to |
| 1189 | * send out on the SPI bus. |
| 1190 | */ |
| 1191 | static int set_up_next_transfer(struct zx297510_spi *zx297510spi, |
| 1192 | struct spi_transfer *transfer) |
| 1193 | { |
| 1194 | int residue; |
| 1195 | |
| 1196 | /* Sanity check the message for this bus width */ |
| 1197 | residue = zx297510spi->cur_transfer->len % zx297510spi->cur_chip->n_bytes; |
| 1198 | if (unlikely(residue != 0)) { |
| 1199 | dev_err(&zx297510spi->pdev->dev, |
| 1200 | "message of %u bytes to transmit but the current " |
| 1201 | "chip bus has a data width of %u bytes!\n", |
| 1202 | zx297510spi->cur_transfer->len, |
| 1203 | zx297510spi->cur_chip->n_bytes); |
| 1204 | dev_err(&zx297510spi->pdev->dev, "skipping this message\n"); |
| 1205 | return -EIO; |
| 1206 | } |
| 1207 | if((void *)transfer->tx_buf != NULL){ |
| 1208 | zx297510spi->tx = (void *)transfer->tx_buf; |
| 1209 | zx297510spi->tx_end = zx297510spi->tx + zx297510spi->cur_transfer->len; |
| 1210 | } |
| 1211 | if((void *)transfer->rx_buf != NULL){ |
| 1212 | zx297510spi->rx = (void *)transfer->rx_buf; |
| 1213 | zx297510spi->rx_end = zx297510spi->rx + zx297510spi->cur_transfer->len; |
| 1214 | } |
| 1215 | zx297510spi->write = |
| 1216 | zx297510spi->tx ? zx297510spi->cur_chip->write : WRITING_NULL; |
| 1217 | zx297510spi->read = zx297510spi->rx ? zx297510spi->cur_chip->read : READING_NULL; |
| 1218 | return 0; |
| 1219 | } |
| 1220 | |
| 1221 | /** |
| 1222 | * pump_transfers - Tasklet function which schedules next transfer |
| 1223 | * when running in interrupt or DMA transfer mode. |
| 1224 | * @data: SSP driver private data structure |
| 1225 | * |
| 1226 | */ |
| 1227 | static void pump_transfers(unsigned long data) |
| 1228 | { |
| 1229 | struct zx297510_spi *zx297510spi = (struct zx297510_spi *) data; |
| 1230 | struct spi_message *message = NULL; |
| 1231 | struct spi_transfer *transfer = NULL; |
| 1232 | struct spi_transfer *previous = NULL; |
| 1233 | |
| 1234 | dev_dbg(&zx297510spi->pdev->dev,"in function %s\n", __FUNCTION__); |
| 1235 | |
| 1236 | /* Get current state information */ |
| 1237 | message = zx297510spi->cur_msg; |
| 1238 | transfer = zx297510spi->cur_transfer; |
| 1239 | |
| 1240 | /* Handle for abort */ |
| 1241 | if (message->state == STATE_ERROR) { |
| 1242 | message->status = -EIO; |
| 1243 | giveback(zx297510spi); |
| 1244 | return; |
| 1245 | } |
| 1246 | |
| 1247 | /* Handle end of message */ |
| 1248 | if (message->state == STATE_DONE) { |
| 1249 | message->status = 0; |
| 1250 | giveback(zx297510spi); |
| 1251 | return; |
| 1252 | } |
| 1253 | |
| 1254 | /* Delay if requested at end of transfer before CS change */ |
| 1255 | if (message->state == STATE_RUNNING) { |
| 1256 | previous = list_entry(transfer->transfer_list.prev, |
| 1257 | struct spi_transfer, |
| 1258 | transfer_list); |
| 1259 | if (previous->delay_usecs) |
| 1260 | /* |
| 1261 | * FIXME: This runs in interrupt context. |
| 1262 | * Is this really smart? |
| 1263 | */ |
| 1264 | udelay(previous->delay_usecs); |
| 1265 | |
| 1266 | /* Reselect chip select only if cs_change was requested */ |
| 1267 | // if (previous->cs_change) |
| 1268 | // zx297510spi->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1269 | } else { |
| 1270 | /* STATE_START */ |
| 1271 | message->state = STATE_RUNNING; |
| 1272 | } |
| 1273 | |
| 1274 | if (set_up_next_transfer(zx297510spi, transfer)) { |
| 1275 | message->state = STATE_ERROR; |
| 1276 | message->status = -EIO; |
| 1277 | giveback(zx297510spi); |
| 1278 | return; |
| 1279 | } |
| 1280 | /* Flush the FIFOs and let's go! */ |
| 1281 | flush(zx297510spi); |
| 1282 | |
| 1283 | if (zx297510spi->cur_chip->enable_dma) { |
| 1284 | if (configure_dma(zx297510spi)) { |
| 1285 | dev_dbg(&zx297510spi->pdev->dev, |
| 1286 | "configuration of DMA failed, fall back to interrupt mode\n"); |
| 1287 | goto err_config_dma; |
| 1288 | } |
| 1289 | return; |
| 1290 | } |
| 1291 | |
| 1292 | err_config_dma: |
| 1293 | /* enable all interrupts except RX */ |
| 1294 | writel( (SPI_INTR_EN_MASK_TX_UNDERRUN_IE | SPI_INTR_EN_MASK_TX_THRES_IE | SPI_INTR_EN_MASK_TX_EMPTY_IE), |
| 1295 | SPI_INTR_EN(zx297510spi->virtbase) ); |
| 1296 | // writew((readl(SSP_CR1(zx297502ssp->virtbase))|SSP_CR1_MASK_TIE|SSP_CR1_MASK_RORIE)&(~SSP_CR1_MASK_RIE), |
| 1297 | // SSP_CR1(zx297502ssp->virtbase)); |
| 1298 | } |
| 1299 | |
| 1300 | static void do_interrupt_dma_transfer(struct zx297510_spi *zx297510spi) |
| 1301 | { |
| 1302 | /* |
| 1303 | * Default is to enable all interrupts except RX - |
| 1304 | * this will be enabled once TX is complete |
| 1305 | */ |
| 1306 | u32 irqflags = ENABLE_ALL_INTERRUPTS; |
| 1307 | |
| 1308 | dev_dbg(&zx297510spi->pdev->dev,"in function %s\n", __FUNCTION__); |
| 1309 | |
| 1310 | /* Enable target chip, if not already active */ |
| 1311 | //if (!zx297502ssp->next_msg_cs_active) |
| 1312 | // zx297502ssp->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1313 | |
| 1314 | if (set_up_next_transfer(zx297510spi, zx297510spi->cur_transfer)) { |
| 1315 | /* Error path */ |
| 1316 | zx297510spi->cur_msg->state = STATE_ERROR; |
| 1317 | zx297510spi->cur_msg->status = -EIO; |
| 1318 | giveback(zx297510spi); |
| 1319 | return; |
| 1320 | } |
| 1321 | /* If we're using DMA, set up DMA here */ |
| 1322 | if (zx297510spi->cur_chip->enable_dma) { |
| 1323 | /* Configure DMA transfer */ |
| 1324 | if (configure_dma(zx297510spi)) { |
| 1325 | dev_dbg(&zx297510spi->pdev->dev, |
| 1326 | "configuration of DMA failed, fall back to interrupt mode\n"); |
| 1327 | goto err_config_dma; |
| 1328 | } |
| 1329 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ |
| 1330 | irqflags = DISABLE_ALL_INTERRUPTS; |
| 1331 | } |
| 1332 | |
| 1333 | if(zx297510spi ->tx != NULL && zx297510spi ->rx != NULL){ |
| 1334 | /* enable all interrupts */ |
| 1335 | irqflags = ENABLE_ALL_INTERRUPTS; |
| 1336 | }else if(zx297510spi->tx != NULL){ |
| 1337 | /*enable tx interrupts*/ |
| 1338 | irqflags = SPI_INTR_EN_MASK_TX_EMPTY_IE |
| 1339 | |SPI_INTR_EN_MASK_TX_THRES_IE |
| 1340 | |SPI_INTR_EN_MASK_TX_UNDERRUN_IE; |
| 1341 | } |
| 1342 | err_config_dma: |
| 1343 | /* Enable SSP, turn on interrupts */ |
| 1344 | writel(readl(SPI_COM_CTRL(zx297510spi->virtbase)) | SPI_COM_CTRL_MASK_SSPE, |
| 1345 | SPI_COM_CTRL(zx297510spi->virtbase)); |
| 1346 | |
| 1347 | /* config interrupts */ |
| 1348 | writel(irqflags, SPI_INTR_EN(zx297510spi->virtbase)); |
| 1349 | |
| 1350 | /*writew(irqflags, SSP_IMSC(zx297502ssp->virtbase));*/ |
| 1351 | } |
| 1352 | |
| 1353 | static void do_polling_transfer(struct zx297510_spi *zx297510spi) |
| 1354 | { |
| 1355 | struct spi_message *message = NULL; |
| 1356 | struct spi_transfer *transfer = NULL; |
| 1357 | struct spi_transfer *previous = NULL; |
| 1358 | struct chip_data *chip; |
| 1359 | unsigned long time, timeout; |
| 1360 | |
| 1361 | chip = zx297510spi->cur_chip; |
| 1362 | message = zx297510spi->cur_msg; |
| 1363 | |
| 1364 | while (message->state != STATE_DONE) { |
| 1365 | /* Handle for abort */ |
| 1366 | if (message->state == STATE_ERROR) |
| 1367 | break; |
| 1368 | transfer = zx297510spi->cur_transfer; |
| 1369 | |
| 1370 | /* Delay if requested at end of transfer */ |
| 1371 | if (message->state == STATE_RUNNING) { |
| 1372 | previous = |
| 1373 | list_entry(transfer->transfer_list.prev, |
| 1374 | struct spi_transfer, transfer_list); |
| 1375 | if (previous->delay_usecs) |
| 1376 | udelay(previous->delay_usecs); |
| 1377 | //if (previous->cs_change) |
| 1378 | // zx297502ssp->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1379 | } else { |
| 1380 | /* STATE_START */ |
| 1381 | message->state = STATE_RUNNING; |
| 1382 | //if (!zx297502ssp->next_msg_cs_active) |
| 1383 | // zx297502ssp->cur_chip->cs_control(SSP_CHIP_SELECT); |
| 1384 | } |
| 1385 | |
| 1386 | /* Configuration Changing Per Transfer */ |
| 1387 | if (set_up_next_transfer(zx297510spi, transfer)) { |
| 1388 | /* Error path */ |
| 1389 | message->state = STATE_ERROR; |
| 1390 | break; |
| 1391 | } |
| 1392 | /* Flush FIFOs and enable SSP */ |
| 1393 | flush(zx297510spi); |
| 1394 | //writel((readl(SSP_CR1(zx297502ssp->virtbase)) | SSP_CR1_MASK_SSE), |
| 1395 | // SSP_CR1(zx297502ssp->virtbase)); |
| 1396 | writel(readl(SPI_COM_CTRL(zx297510spi->virtbase)) | SPI_COM_CTRL_MASK_SSPE, |
| 1397 | SPI_COM_CTRL(zx297510spi->virtbase)); |
| 1398 | |
| 1399 | dev_dbg(&zx297510spi->pdev->dev, "polling transfer ongoing ...\n"); |
| 1400 | |
| 1401 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); |
| 1402 | |
| 1403 | if(zx297510spi->tx != NULL && zx297510spi->rx != NULL ) |
| 1404 | { /*read and write*/ |
| 1405 | while (zx297510spi->tx < zx297510spi->tx_end || zx297510spi->rx < zx297510spi->rx_end) { |
| 1406 | time = jiffies; |
| 1407 | readwriter(zx297510spi); |
| 1408 | if (time_after(time, timeout)) { |
| 1409 | dev_warn(&zx297510spi->pdev->dev, |
| 1410 | "%s: timeout!\n", __func__); |
| 1411 | message->state = STATE_ERROR; |
| 1412 | goto out; |
| 1413 | } |
| 1414 | cpu_relax(); |
| 1415 | } |
| 1416 | } |
| 1417 | else if (zx297510spi->tx != NULL ) |
| 1418 | {/* only write */ |
| 1419 | while (zx297510spi->tx < zx297510spi->tx_end ) { |
| 1420 | time = jiffies; |
| 1421 | write(zx297510spi); |
| 1422 | if (time_after(time, timeout)) { |
| 1423 | dev_warn(&zx297510spi->pdev->dev, |
| 1424 | "%s: timeout!\n", __func__); |
| 1425 | message->state = STATE_ERROR; |
| 1426 | goto out; |
| 1427 | } |
| 1428 | cpu_relax(); |
| 1429 | } |
| 1430 | } |
| 1431 | /* Update total byte transferred */ |
| 1432 | message->actual_length += zx297510spi->cur_transfer->len; |
| 1433 | // if (zx297510spi->cur_transfer->cs_change) |
| 1434 | // zx297510spi->cur_chip->cs_control(SSP_CHIP_DESELECT); |
| 1435 | /* Move to next transfer */ |
| 1436 | message->state = next_transfer(zx297510spi); |
| 1437 | } |
| 1438 | out: |
| 1439 | /* Handle end of message */ |
| 1440 | if (message->state == STATE_DONE) |
| 1441 | message->status = 0; |
| 1442 | else |
| 1443 | message->status = -EIO; |
| 1444 | |
| 1445 | giveback(zx297510spi); |
| 1446 | return; |
| 1447 | } |
| 1448 | |
| 1449 | static int zx297510_transfer_one_message(struct spi_master *master, |
| 1450 | struct spi_message *msg) |
| 1451 | { |
| 1452 | struct zx297510_spi *zx297510spi = spi_master_get_devdata(master); |
| 1453 | |
| 1454 | //printk(KERN_INFO "ssp:in function %s \n", __FUNCTION__); |
| 1455 | |
| 1456 | /* Initial message state */ |
| 1457 | zx297510spi->cur_msg = msg; |
| 1458 | msg->state = STATE_START; |
| 1459 | |
| 1460 | zx297510spi->cur_transfer = list_entry(msg->transfers.next, |
| 1461 | struct spi_transfer, transfer_list); |
| 1462 | |
| 1463 | /* Setup the SPI using the per chip configuration */ |
| 1464 | zx297510spi->cur_chip = spi_get_ctldata(msg->spi); |
| 1465 | |
| 1466 | restore_state(zx297510spi); |
| 1467 | flush(zx297510spi); |
| 1468 | |
| 1469 | if (zx297510spi->cur_chip->xfer_type == POLLING_TRANSFER) |
| 1470 | do_polling_transfer(zx297510spi); |
| 1471 | else |
| 1472 | do_interrupt_dma_transfer(zx297510spi); |
| 1473 | |
| 1474 | return 0; |
| 1475 | } |
| 1476 | |
| 1477 | static int zx297510_prepare_transfer_hardware(struct spi_master *master) |
| 1478 | { |
| 1479 | // struct zx297510_spi *zx297510spi = spi_master_get_devdata(master); |
| 1480 | |
| 1481 | //dev_warn(&zx297502ssp->pdev->dev,"in function %s\n", __FUNCTION__); |
| 1482 | |
| 1483 | #if 0 |
| 1484 | /* |
| 1485 | * Just make sure we have all we need to run the transfer by syncing |
| 1486 | * with the runtime PM framework. |
| 1487 | */ |
| 1488 | pm_runtime_get_sync(&pl022->adev->dev); |
| 1489 | #endif |
| 1490 | return 0; |
| 1491 | } |
| 1492 | |
| 1493 | static int zx297510_unprepare_transfer_hardware(struct spi_master *master) |
| 1494 | { |
| 1495 | struct zx297510_spi *zx297510spi = spi_master_get_devdata(master); |
| 1496 | |
| 1497 | //dev_warn(&zx297502ssp->pdev->dev,"in function %s\n", __FUNCTION__); |
| 1498 | |
| 1499 | /* nothing more to do - disable spi/ssp and power off */ |
| 1500 | writel(readl(SPI_COM_CTRL(zx297510spi->virtbase)) & ~ SPI_COM_CTRL_MASK_SSPE, |
| 1501 | SPI_COM_CTRL(zx297510spi->virtbase)); |
| 1502 | #if 0 |
| 1503 | if (pl022->master_info->autosuspend_delay > 0) { |
| 1504 | pm_runtime_mark_last_busy(&pl022->adev->dev); |
| 1505 | pm_runtime_put_autosuspend(&pl022->adev->dev); |
| 1506 | } else { |
| 1507 | pm_runtime_put(&pl022->adev->dev); |
| 1508 | } |
| 1509 | #endif |
| 1510 | return 0; |
| 1511 | } |
| 1512 | |
| 1513 | static int verify_controller_parameters(struct zx297510_spi *zx297510spi, |
| 1514 | struct spi_config_chip const *chip_info) |
| 1515 | { |
| 1516 | if ((chip_info->iface < SPI_INTERFACE_MOTOROLA_SPI) |
| 1517 | || (chip_info->iface > SPI_INTERFACE_TI_SYNC_SERIAL)) { |
| 1518 | dev_err(&zx297510spi->pdev->dev, |
| 1519 | "interface is configured incorrectly\n"); |
| 1520 | return -EINVAL; |
| 1521 | } |
| 1522 | |
| 1523 | if ((chip_info->hierarchy != SPI_MASTER) |
| 1524 | && (chip_info->hierarchy != SPI_SLAVE)) { |
| 1525 | dev_err(&zx297510spi->pdev->dev, |
| 1526 | "hierarchy is configured incorrectly\n"); |
| 1527 | return -EINVAL; |
| 1528 | } |
| 1529 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
| 1530 | && (chip_info->com_mode != DMA_TRANSFER) |
| 1531 | && (chip_info->com_mode != POLLING_TRANSFER)) { |
| 1532 | dev_err(&zx297510spi->pdev->dev, |
| 1533 | "Communication mode is configured incorrectly\n"); |
| 1534 | return -EINVAL; |
| 1535 | } |
| 1536 | switch (chip_info->rx_lev_trig) { |
| 1537 | case SPI_RX_1_OR_MORE_ELEM: |
| 1538 | case SPI_RX_4_OR_MORE_ELEM: |
| 1539 | case SPI_RX_8_OR_MORE_ELEM: |
| 1540 | /* These are always OK, all variants can handle this */ |
| 1541 | break; |
| 1542 | case SPI_RX_16_OR_MORE_ELEM: |
| 1543 | if (zx297510spi->vendor->fifodepth < 16) { |
| 1544 | dev_err(&zx297510spi->pdev->dev, |
| 1545 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1546 | return -EINVAL; |
| 1547 | } |
| 1548 | break; |
| 1549 | case SPI_RX_32_OR_MORE_ELEM: |
| 1550 | if (zx297510spi->vendor->fifodepth < 32) { |
| 1551 | dev_err(&zx297510spi->pdev->dev, |
| 1552 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1553 | return -EINVAL; |
| 1554 | } |
| 1555 | break; |
| 1556 | default: |
| 1557 | dev_err(&zx297510spi->pdev->dev, |
| 1558 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1559 | return -EINVAL; |
| 1560 | break; |
| 1561 | } |
| 1562 | switch (chip_info->tx_lev_trig) { |
| 1563 | case SPI_TX_1_OR_MORE_EMPTY_LOC: |
| 1564 | case SPI_TX_4_OR_MORE_EMPTY_LOC: |
| 1565 | case SPI_TX_8_OR_MORE_EMPTY_LOC: |
| 1566 | /* These are always OK, all variants can handle this */ |
| 1567 | break; |
| 1568 | case SPI_TX_16_OR_MORE_EMPTY_LOC: |
| 1569 | if (zx297510spi->vendor->fifodepth < 16) { |
| 1570 | dev_err(&zx297510spi->pdev->dev, |
| 1571 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1572 | return -EINVAL; |
| 1573 | } |
| 1574 | break; |
| 1575 | case SPI_TX_32_OR_MORE_EMPTY_LOC: |
| 1576 | if (zx297510spi->vendor->fifodepth < 32) { |
| 1577 | dev_err(&zx297510spi->pdev->dev, |
| 1578 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1579 | return -EINVAL; |
| 1580 | } |
| 1581 | break; |
| 1582 | default: |
| 1583 | dev_err(&zx297510spi->pdev->dev, |
| 1584 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1585 | return -EINVAL; |
| 1586 | break; |
| 1587 | } |
| 1588 | |
| 1589 | return 0; |
| 1590 | } |
| 1591 | |
| 1592 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) |
| 1593 | { |
| 1594 | return rate / (cpsdvsr * (1 + scr)); |
| 1595 | } |
| 1596 | |
| 1597 | static int calculate_effective_freq(struct zx297510_spi *zx297510spi, u32 freq, u8* div) |
| 1598 | { |
| 1599 | u8 clk_div; |
| 1600 | /*div from src clk 104M*/ |
| 1601 | /* f(ssp_clk) = 2*f(ssp_sclk_out) */ |
| 1602 | clk_div = zx297510spi->clkfreq /( freq *2); |
| 1603 | if( clk_div < DIV_MIN+1 || clk_div > DIV_MAX+1 ) |
| 1604 | { |
| 1605 | dev_err(&zx297510spi->pdev->dev, "error!!! speed is %d Hz out of rang",freq ); |
| 1606 | return -ENOTSUPP; |
| 1607 | } |
| 1608 | *div = clk_div; |
| 1609 | return 0; |
| 1610 | } |
| 1611 | |
| 1612 | static struct vendor_data vendor_arm = { |
| 1613 | .fifodepth = 16, |
| 1614 | .max_bpw = 32, |
| 1615 | .loopback = true, |
| 1616 | }; |
| 1617 | static struct resource spi_gpio_resources[] ={ |
| 1618 | [0]={ |
| 1619 | .start = GPIO_AP_SPI_TXD, |
| 1620 | .end = GPIO_AP_SPI_TXD, |
| 1621 | .name = "txd", |
| 1622 | .flags = IORESOURCE_IO, |
| 1623 | }, |
| 1624 | [1]={ |
| 1625 | .start = GPIO_AP_SPI_CLK, |
| 1626 | .end = GPIO_AP_SPI_CLK, |
| 1627 | .name = "clk", |
| 1628 | .flags = IORESOURCE_IO, |
| 1629 | }, |
| 1630 | [2]={ |
| 1631 | .start = GPIO_AP_SPI_CS, |
| 1632 | .end = GPIO_AP_SPI_CS, |
| 1633 | .name = "cs", |
| 1634 | .flags = IORESOURCE_IO, |
| 1635 | }, |
| 1636 | #if 0 |
| 1637 | [3]={ |
| 1638 | .start = GPIO_AP_SPI_RXD, |
| 1639 | .end = GPIO_AP_SPI_RXD, |
| 1640 | .name = "rxd", |
| 1641 | .flags = IORESOURCE_IO, |
| 1642 | } |
| 1643 | #endif |
| 1644 | }; |
| 1645 | /* |
| 1646 | * A piece of default chip info unless the platform |
| 1647 | * supplies it. |
| 1648 | */ |
| 1649 | static const struct spi_config_chip spi_default_chip_info = { |
| 1650 | .com_mode = POLLING_TRANSFER, |
| 1651 | .iface = SPI_INTERFACE_MOTOROLA_SPI, |
| 1652 | .hierarchy = SPI_MASTER, |
| 1653 | .slave_tx_disable = DO_NOT_DRIVE_TX, |
| 1654 | .rx_lev_trig = SPI_RX_8_OR_MORE_ELEM, |
| 1655 | .tx_lev_trig = SPI_TX_8_OR_MORE_EMPTY_LOC, |
| 1656 | // .ctrl_len = SSP_BITS_8, |
| 1657 | // .wait_state = SSP_MWIRE_WAIT_ZERO, |
| 1658 | // .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
| 1659 | .cs_control = null_cs_control, |
| 1660 | }; |
| 1661 | |
| 1662 | /* |
| 1663 | * spi ʹÓÃGPIOģʽ¶ÁÈ¡LCD µÄID Begin |
| 1664 | */ |
| 1665 | #define SPI_GPIO_FUNCTION 1 |
| 1666 | #define SPI_GPIO_GPIO 0 |
| 1667 | |
| 1668 | #define SPI_GPIO_HIGH 1 |
| 1669 | #define SPI_GPIO_LOW 0 |
| 1670 | |
| 1671 | static void spi_set_gpio_function(void) |
| 1672 | { |
| 1673 | //TODO:ÉèÖÃGPIOΪ¹¦ÄܽŠ|
| 1674 | zx29_gpio1v8_function_sel(GPIO_AP_SPI_CS, SPI_GPIO_FUNCTION); |
| 1675 | zx29_gpio1v8_function_sel(GPIO_AP_SPI_CLK,SPI_GPIO_FUNCTION); |
| 1676 | // zx29_gpio1v8_function_sel(GPIO_AP_SPI_RXD,SPI_GPIO_FUNCTION); |
| 1677 | zx29_gpio1v8_function_sel(GPIO_AP_SPI_TXD,SPI_GPIO_FUNCTION); |
| 1678 | } |
| 1679 | static void spi_set_gpio_gpio(void) |
| 1680 | { |
| 1681 | //TODO:ÉèÖÃGPIOΪGPIO½Å |
| 1682 | zx29_gpio1v8_function_sel(GPIO_AP_SPI_CS, SPI_GPIO_GPIO); |
| 1683 | zx29_gpio1v8_function_sel(GPIO_AP_SPI_CLK,SPI_GPIO_GPIO); |
| 1684 | // zx29_gpio1v8_function_sel(GPIO_AP_SPI_RXD,SPI_GPIO_GPIO); |
| 1685 | zx29_gpio1v8_function_sel(GPIO_AP_SPI_TXD,SPI_GPIO_GPIO); |
| 1686 | } |
| 1687 | static void spi_set_gpio_val(int gpio_num, int val) |
| 1688 | { |
| 1689 | gpio_direction_output(gpio_num, val); |
| 1690 | } |
| 1691 | |
| 1692 | static int spi_get_gpio_val(int gpio_num) |
| 1693 | { |
| 1694 | gpio_direction_input(gpio_num); |
| 1695 | |
| 1696 | return gpio_get_value(gpio_num); |
| 1697 | } |
| 1698 | |
| 1699 | static void spi_time_delay(int delay/*us*/) |
| 1700 | { |
| 1701 | udelay(delay); |
| 1702 | } |
| 1703 | |
| 1704 | void spi_gpio_mode_start(void) |
| 1705 | { |
| 1706 | /* set clk tx rx cs to gpio */ |
| 1707 | spi_set_gpio_gpio(); |
| 1708 | |
| 1709 | spi_set_gpio_val(GPIO_AP_SPI_CS, SPI_GPIO_HIGH);/* CSµÍÓÐЧ */ |
| 1710 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_LOW);/* clk¿ÕÏÐʱΪµÍ */ |
| 1711 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_LOW); |
| 1712 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_LOW); |
| 1713 | } |
| 1714 | EXPORT_SYMBOL(spi_gpio_mode_start); |
| 1715 | void spi_gpio_mode_stop(void) |
| 1716 | { |
| 1717 | /* set clk tx rx cs to function */ |
| 1718 | spi_set_gpio_function(); |
| 1719 | } |
| 1720 | EXPORT_SYMBOL(spi_gpio_mode_stop); |
| 1721 | /******************************************************************************* |
| 1722 | * Function: |
| 1723 | * Description: |
| 1724 | * Parameters: |
| 1725 | * Input: |
| 1726 | * |
| 1727 | * Output: |
| 1728 | * |
| 1729 | * Returns: |
| 1730 | * |
| 1731 | * |
| 1732 | * Others: |
| 1733 | ********************************************************************************/ |
| 1734 | void spi_gpio_write_single8(unsigned char data) |
| 1735 | { |
| 1736 | int i; |
| 1737 | |
| 1738 | spi_set_gpio_val(GPIO_AP_SPI_CS, SPI_GPIO_LOW);/* CSµÍÓÐЧ */ |
| 1739 | |
| 1740 | for( i=7; i>=0; i-- ) |
| 1741 | { |
| 1742 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_LOW); |
| 1743 | if ((data >> i) & 0x1) |
| 1744 | { |
| 1745 | spi_set_gpio_val(GPIO_AP_SPI_TXD, SPI_GPIO_HIGH); |
| 1746 | } |
| 1747 | else |
| 1748 | { |
| 1749 | spi_set_gpio_val(GPIO_AP_SPI_TXD, SPI_GPIO_LOW); |
| 1750 | } |
| 1751 | spi_time_delay(50); |
| 1752 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_HIGH); |
| 1753 | spi_time_delay(50); |
| 1754 | } |
| 1755 | |
| 1756 | } |
| 1757 | EXPORT_SYMBOL(spi_gpio_write_single8); |
| 1758 | /******************************************************************************* |
| 1759 | * Function: |
| 1760 | * Description: |
| 1761 | * Parameters: |
| 1762 | * Input: |
| 1763 | * |
| 1764 | * Output: |
| 1765 | * |
| 1766 | * Returns: |
| 1767 | * |
| 1768 | * |
| 1769 | * Others: |
| 1770 | ********************************************************************************/ |
| 1771 | unsigned char spi_gpio_read_single8(void) |
| 1772 | { |
| 1773 | int i; |
| 1774 | unsigned char readData = 0; |
| 1775 | |
| 1776 | spi_set_gpio_val(GPIO_AP_SPI_CS, SPI_GPIO_LOW);/* CSµÍÓÐЧ */ |
| 1777 | |
| 1778 | for( i=7; i>=0; i-- ) |
| 1779 | { |
| 1780 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_LOW); |
| 1781 | spi_time_delay(50); |
| 1782 | spi_set_gpio_val(GPIO_AP_SPI_CLK, SPI_GPIO_HIGH); |
| 1783 | if( spi_get_gpio_val(GPIO_AP_SPI_TXD) )/* lcd ¸´ÓÃtx rx */ |
| 1784 | { |
| 1785 | readData |= (1 << i); |
| 1786 | } |
| 1787 | spi_time_delay(50); |
| 1788 | } |
| 1789 | |
| 1790 | return readData; |
| 1791 | } |
| 1792 | EXPORT_SYMBOL(spi_gpio_read_single8); |
| 1793 | |
| 1794 | /* |
| 1795 | * spi ʹÓÃGPIOģʽ¶ÁÈ¡LCD µÄID End |
| 1796 | */ |
| 1797 | |
| 1798 | /** |
| 1799 | * pl022_setup - setup function registered to SPI master framework |
| 1800 | * @spi: spi device which is requesting setup |
| 1801 | * |
| 1802 | * This function is registered to the SPI framework for this SPI master |
| 1803 | * controller. If it is the first time when setup is called by this device, |
| 1804 | * this function will initialize the runtime state for this chip and save |
| 1805 | * the same in the device structure. Else it will update the runtime info |
| 1806 | * with the updated chip info. Nothing is really being written to the |
| 1807 | * controller hardware here, that is not done until the actual transfer |
| 1808 | * commence. |
| 1809 | */ |
| 1810 | static int zx297510_setup(struct spi_device *spi) |
| 1811 | { |
| 1812 | struct spi_config_chip const *chip_info; |
| 1813 | struct chip_data *chip; |
| 1814 | u8 clk_div = 0; |
| 1815 | int status = 0; |
| 1816 | struct zx297510_spi *zx297510spi = spi_master_get_devdata(spi->master); |
| 1817 | unsigned int bits = spi->bits_per_word; |
| 1818 | u32 tmp; |
| 1819 | |
| 1820 | |
| 1821 | if (!spi->max_speed_hz) |
| 1822 | return -EINVAL; |
| 1823 | |
| 1824 | /* Get controller_state if one is supplied */ |
| 1825 | chip = spi_get_ctldata(spi); |
| 1826 | |
| 1827 | if (chip == NULL) { |
| 1828 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
| 1829 | if (!chip) { |
| 1830 | dev_err(&spi->dev, |
| 1831 | "cannot allocate controller state\n"); |
| 1832 | return -ENOMEM; |
| 1833 | } |
| 1834 | dev_dbg(&spi->dev, |
| 1835 | "allocated memory for controller's runtime state\n"); |
| 1836 | } |
| 1837 | |
| 1838 | /* Get controller data if one is supplied */ |
| 1839 | chip_info = spi->controller_data; |
| 1840 | |
| 1841 | if (chip_info == NULL) { |
| 1842 | chip_info = &spi_default_chip_info; |
| 1843 | /* spi_board_info.controller_data not is supplied */ |
| 1844 | dev_dbg(&spi->dev, |
| 1845 | "using default controller_data settings\n"); |
| 1846 | } else |
| 1847 | dev_dbg(&spi->dev, |
| 1848 | "using user supplied controller_data settings\n"); |
| 1849 | |
| 1850 | /* |
| 1851 | * We can override with custom divisors, else we use the board |
| 1852 | * frequency setting |
| 1853 | */ |
| 1854 | |
| 1855 | status = calculate_effective_freq(zx297510spi, |
| 1856 | spi->max_speed_hz, |
| 1857 | &clk_div); |
| 1858 | if (status < 0) |
| 1859 | goto err_config_params; |
| 1860 | |
| 1861 | chip ->clk_div = clk_div; |
| 1862 | |
| 1863 | dev_dbg(&spi->dev, "clk dividor is %d\n", clk_div); |
| 1864 | |
| 1865 | /* enable ssp clock source */ |
| 1866 | clk_enable(zx297510spi->spi_clk); |
| 1867 | |
| 1868 | /* set spi clock source at 104MHz/1 */ |
| 1869 | // zx297510spi->spi_clk->ops->set_division(zx297510spi->spi_clk,chip ->clk_div-1); |
| 1870 | //writel(chip ->clk_div-1, M0_SSP_CLKDIV_REG_VA); |
| 1871 | clk_set_rate(zx297510spi->spi_clk, spi->max_speed_hz*2); /* f(ssp_clk) = 2*f(ssp_sclk_out) */ |
| 1872 | |
| 1873 | status = verify_controller_parameters(zx297510spi, chip_info); |
| 1874 | if (status) { |
| 1875 | dev_err(&spi->dev, "controller data is incorrect"); |
| 1876 | goto err_config_params; |
| 1877 | } |
| 1878 | |
| 1879 | zx297510spi->rx_lev_trig = chip_info->rx_lev_trig; |
| 1880 | zx297510spi->tx_lev_trig = chip_info->tx_lev_trig; |
| 1881 | |
| 1882 | /* Now set controller state based on controller data */ |
| 1883 | chip->xfer_type = chip_info->com_mode; |
| 1884 | /* |
| 1885 | if (!chip_info->cs_control) { |
| 1886 | chip->cs_control = null_cs_control; |
| 1887 | dev_warn(&spi->dev, |
| 1888 | "chip select function is NULL for this chip\n"); |
| 1889 | } else |
| 1890 | chip->cs_control = chip_info->cs_control;*/ |
| 1891 | |
| 1892 | /* Check bits per word with vendor specific range */ |
| 1893 | if ((bits <= 3) || (bits > zx297510spi->vendor->max_bpw)) { |
| 1894 | status = -ENOTSUPP; |
| 1895 | dev_err(&spi->dev, "illegal data size for this controller!\n"); |
| 1896 | dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", |
| 1897 | zx297510spi->vendor->max_bpw); |
| 1898 | goto err_config_params; |
| 1899 | } else if (bits <= 8) { |
| 1900 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); |
| 1901 | chip->n_bytes = 1; |
| 1902 | chip->read = READING_U8; |
| 1903 | chip->write = WRITING_U8; |
| 1904 | } else if (bits <= 16) { |
| 1905 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
| 1906 | chip->n_bytes = 2; |
| 1907 | chip->read = READING_U16; |
| 1908 | chip->write = WRITING_U16; |
| 1909 | } else { |
| 1910 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
| 1911 | chip->n_bytes = 4; |
| 1912 | chip->read = READING_U32; |
| 1913 | chip->write = WRITING_U32; |
| 1914 | } |
| 1915 | |
| 1916 | /* Now Initialize all register settings required for this chip */ |
| 1917 | chip->com_ctrl = 0; |
| 1918 | chip->fmt_ctrl = 0; |
| 1919 | chip->fifo_ctrl = 0; |
| 1920 | |
| 1921 | if ((chip_info->com_mode == DMA_TRANSFER) |
| 1922 | && ((zx297510spi->master_info)->enable_dma)) { |
| 1923 | chip->enable_dma = true; |
| 1924 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
| 1925 | SPI_WRITE_BITS(chip->fifo_ctrl, SPI_DMA_ENABLED, |
| 1926 | SPI_FIFO_CTRL_MASK_RX_DMA_EN, 2); |
| 1927 | SPI_WRITE_BITS(chip->fifo_ctrl, |
| 1928 | SPI_DMA_ENABLED, SPI_FIFO_CTRL_MASK_TX_DMA_EN, 3); |
| 1929 | } else { |
| 1930 | chip->enable_dma = false; |
| 1931 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
| 1932 | SPI_WRITE_BITS(chip->fifo_ctrl, |
| 1933 | SPI_DMA_DISABLED, SPI_FIFO_CTRL_MASK_RX_DMA_EN, 2); |
| 1934 | SPI_WRITE_BITS(chip->fifo_ctrl, |
| 1935 | SPI_DMA_DISABLED, SPI_FIFO_CTRL_MASK_TX_DMA_EN, 3); |
| 1936 | } |
| 1937 | |
| 1938 | |
| 1939 | SPI_WRITE_BITS(chip->fifo_ctrl, |
| 1940 | SPI_FIFO_THRES_8, SPI_FIFO_CTRL_MASK_RX_FIFO_THRES, 4); |
| 1941 | SPI_WRITE_BITS(chip->fifo_ctrl, |
| 1942 | SPI_FIFO_THRES_8, SPI_FIFO_CTRL_MASK_TX_FIFO_THRES, 8); |
| 1943 | |
| 1944 | SPI_WRITE_BITS(chip->fmt_ctrl, bits - 1,SPI_FMT_CTRL_MASK_DSS, 4); |
| 1945 | SPI_WRITE_BITS(chip->fmt_ctrl, chip_info->iface, SPI_FMT_CTRL_MASK_FRF, 0); |
| 1946 | |
| 1947 | /* Stuff that is common for all versions */ |
| 1948 | if (spi->mode & SPI_CPOL) |
| 1949 | tmp = SPI_CLK_POL_IDLE_HIGH; |
| 1950 | else |
| 1951 | tmp = SPI_CLK_POL_IDLE_LOW; |
| 1952 | SPI_WRITE_BITS(chip->fmt_ctrl, tmp, SPI_FMT_CTRL_MASK_POL,2); |
| 1953 | |
| 1954 | if (spi->mode & SPI_CPHA) |
| 1955 | tmp = SPI_CLK_SECOND_EDGE; |
| 1956 | else |
| 1957 | tmp = SPI_CLK_FIRST_EDGE; |
| 1958 | |
| 1959 | SPI_WRITE_BITS(chip->fmt_ctrl, tmp, SPI_FMT_CTRL_MASK_PHA, 3); |
| 1960 | |
| 1961 | /* Loopback is available on all versions except PL023 */ |
| 1962 | if (zx297510spi->vendor->loopback) { |
| 1963 | if (spi->mode & SPI_LOOP) |
| 1964 | tmp = LOOPBACK_ENABLED; |
| 1965 | else |
| 1966 | tmp = LOOPBACK_DISABLED; |
| 1967 | SPI_WRITE_BITS(chip->com_ctrl, tmp, SPI_COM_CTRL_MASK_LBM, 0); |
| 1968 | } |
| 1969 | SPI_WRITE_BITS(chip->com_ctrl, SPI_ENABLED, SPI_COM_CTRL_MASK_SSPE, 1); |
| 1970 | SPI_WRITE_BITS(chip->com_ctrl, chip_info->hierarchy, SPI_COM_CTRL_MASK_MS, 2); |
| 1971 | SPI_WRITE_BITS(chip->com_ctrl, chip_info->slave_tx_disable, SPI_COM_CTRL_MASK_SOD, 3); |
| 1972 | |
| 1973 | /* Save controller_state */ |
| 1974 | spi_set_ctldata(spi, chip); |
| 1975 | return status; |
| 1976 | err_config_params: |
| 1977 | spi_set_ctldata(spi, NULL); |
| 1978 | kfree(chip); |
| 1979 | return status; |
| 1980 | } |
| 1981 | |
| 1982 | /** |
| 1983 | * pl022_cleanup - cleanup function registered to SPI master framework |
| 1984 | * @spi: spi device which is requesting cleanup |
| 1985 | * |
| 1986 | * This function is registered to the SPI framework for this SPI master |
| 1987 | * controller. It will free the runtime state of chip. |
| 1988 | */ |
| 1989 | static void zx297510_cleanup(struct spi_device *spi) |
| 1990 | { |
| 1991 | struct chip_data *chip = spi_get_ctldata(spi); |
| 1992 | |
| 1993 | spi_set_ctldata(spi, NULL); |
| 1994 | kfree(chip); |
| 1995 | } |
| 1996 | |
| 1997 | static int __devinit zx297510_spi_probe(struct platform_device *pdev) |
| 1998 | { |
| 1999 | struct device *dev = &pdev->dev; |
| 2000 | struct zx297510_spi_controller *platform_info = pdev->dev.platform_data; |
| 2001 | struct spi_master *master; |
| 2002 | struct zx297510_spi *zx297510spi = NULL; /*Data for this driver */ |
| 2003 | struct resource * regs = NULL; |
| 2004 | struct resource * gpio = NULL; |
| 2005 | struct resource * irq = NULL; |
| 2006 | int status = 0, i; |
| 2007 | |
| 2008 | printk(KERN_INFO "spi:zx297510_spi_probe \n"); |
| 2009 | |
| 2010 | |
| 2011 | if (platform_info == NULL) { |
| 2012 | dev_err(&pdev->dev, "probe - no platform data supplied\n"); |
| 2013 | status = -ENODEV; |
| 2014 | goto err_no_pdata; |
| 2015 | } |
| 2016 | |
| 2017 | /* Allocate master with space for data */ |
| 2018 | master = spi_alloc_master(dev, sizeof(struct zx297510_spi)); |
| 2019 | if (master == NULL) { |
| 2020 | dev_err(&pdev->dev, "probe - cannot alloc SPI master\n"); |
| 2021 | status = -ENOMEM; |
| 2022 | goto err_no_master; |
| 2023 | } |
| 2024 | |
| 2025 | zx297510spi = spi_master_get_devdata(master); |
| 2026 | zx297510spi->master = master; |
| 2027 | zx297510spi->master_info = platform_info; |
| 2028 | zx297510spi->pdev = pdev; |
| 2029 | zx297510spi->vendor = &vendor_arm; |
| 2030 | |
| 2031 | dev_set_drvdata(&pdev->dev, zx297510spi); |
| 2032 | /* |
| 2033 | * Bus Number Which has been Assigned to this SSP controller |
| 2034 | * on this board |
| 2035 | */ |
| 2036 | master->bus_num = platform_info->bus_id; |
| 2037 | master->num_chipselect = platform_info->num_chipselect; |
| 2038 | master->cleanup = zx297510_cleanup; |
| 2039 | master->setup = zx297510_setup; |
| 2040 | master->prepare_transfer_hardware = zx297510_prepare_transfer_hardware; |
| 2041 | master->transfer_one_message = zx297510_transfer_one_message; |
| 2042 | master->unprepare_transfer_hardware = zx297510_unprepare_transfer_hardware; |
| 2043 | master->rt = platform_info->rt; |
| 2044 | |
| 2045 | /* |
| 2046 | * Supports mode 0-3, loopback, and active low CS. Transfers are |
| 2047 | * always MS bit first on the original pl022. |
| 2048 | */ |
| 2049 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_NO_CS; |
| 2050 | |
| 2051 | dev_dbg(&pdev->dev, "BUSNO: %d\n", master->bus_num); |
| 2052 | |
| 2053 | /* registers */ |
| 2054 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2055 | if ( regs == NULL ){ |
| 2056 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); |
| 2057 | status = -ENOENT; |
| 2058 | goto err_no_registers; |
| 2059 | } |
| 2060 | |
| 2061 | zx297510spi->phybase = regs->start; |
| 2062 | zx297510spi->virtbase = ioremap(regs->start, resource_size(regs)); |
| 2063 | |
| 2064 | if (zx297510spi->virtbase == NULL) { |
| 2065 | status = -ENOMEM; |
| 2066 | goto err_no_ioremap; |
| 2067 | } |
| 2068 | dev_dbg( &pdev->dev," mapped registers from 0x%08x to 0x%p\n", |
| 2069 | regs->start, zx297510spi->virtbase); |
| 2070 | |
| 2071 | /* gpios txd rxd sclk cs */ |
| 2072 | for(i = 0; i < ARRAY_SIZE(spi_gpio_resources); i++){ |
| 2073 | //gpio = platform_get_resource(pdev, IORESOURCE_IO, i); |
| 2074 | gpio = &spi_gpio_resources[i]; |
| 2075 | if( gpio == NULL ) |
| 2076 | { |
| 2077 | dev_err(&pdev->dev, "Cannot get IORESOURCE_IO\n"); |
| 2078 | status = -ENOENT; |
| 2079 | goto err_gpios; |
| 2080 | } |
| 2081 | dev_dbg(&pdev->dev, "used gpio num %d as %s \n", gpio->start, gpio ->name); |
| 2082 | |
| 2083 | status = gpio_request(gpio->start,gpio->name); |
| 2084 | if( status < 0 ) |
| 2085 | goto err_gpios; |
| 2086 | //zte_gpio_config(gpio->start, SET_FUNCTION); |
| 2087 | zx29_gpio1v8_function_sel(gpio->start,1); |
| 2088 | } |
| 2089 | |
| 2090 | /* work clock */ |
| 2091 | zx297510spi->spi_clk = clk_get(&pdev->dev, "work_clk"); |
| 2092 | if (IS_ERR(zx297510spi->spi_clk)) { |
| 2093 | status = PTR_ERR(zx297510spi->spi_clk); |
| 2094 | dev_err(&pdev->dev, "could not retrieve SPI work clock\n"); |
| 2095 | goto err_no_clk; |
| 2096 | } |
| 2097 | /* enable spiclk at function zx297510_setup */ |
| 2098 | |
| 2099 | zx297510spi->clkfreq = SPI_SPICLK_FREQ_104M; |
| 2100 | |
| 2101 | |
| 2102 | /* apb clock */ |
| 2103 | zx297510spi->pclk = clk_get(&pdev->dev, "apb_clk"); |
| 2104 | if (IS_ERR(zx297510spi->pclk)) { |
| 2105 | status = PTR_ERR(zx297510spi->pclk); |
| 2106 | dev_err(&pdev->dev, "could not retrieve SPI work clock\n"); |
| 2107 | goto err_no_clk; |
| 2108 | } |
| 2109 | /* enable ssp clock source */ |
| 2110 | clk_enable(zx297510spi->pclk); |
| 2111 | |
| 2112 | /* Initialize transfer pump */ |
| 2113 | tasklet_init(&zx297510spi->pump_transfers, pump_transfers, |
| 2114 | (unsigned long)zx297510spi); |
| 2115 | |
| 2116 | /* Disable SPI */ |
| 2117 | writel((readl(SPI_COM_CTRL(zx297510spi->virtbase)) & (~SPI_COM_CTRL_MASK_SSPE)), |
| 2118 | SPI_COM_CTRL(zx297510spi->virtbase)); |
| 2119 | |
| 2120 | load_spi_default_config(zx297510spi); |
| 2121 | |
| 2122 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 2123 | if( irq == NULL ){ |
| 2124 | dev_err(&pdev->dev, "Cannot get IORESOURCE_IRQ\n"); |
| 2125 | status = -ENOENT; |
| 2126 | goto err_no_irq; |
| 2127 | } |
| 2128 | |
| 2129 | dev_dbg(&pdev->dev, "used interrupt num is %d\n", irq->start); |
| 2130 | |
| 2131 | status = request_irq(irq->start, zx297510_interrupt_handler, 0, "zx297510_spi", |
| 2132 | zx297510spi); |
| 2133 | if (status < 0) { |
| 2134 | dev_err(&pdev->dev, "probe - cannot get IRQ (%d)\n", status); |
| 2135 | goto err_no_irq; |
| 2136 | } |
| 2137 | |
| 2138 | /* Get DMA channels */ |
| 2139 | if (platform_info->enable_dma) { |
| 2140 | status = zx297510_dma_probe(zx297510spi); |
| 2141 | if (status != 0) |
| 2142 | platform_info->enable_dma = 0; |
| 2143 | } |
| 2144 | |
| 2145 | status = spi_register_master(master); |
| 2146 | if (status != 0) { |
| 2147 | dev_err(&pdev->dev, |
| 2148 | "probe - problem registering spi master\n"); |
| 2149 | goto err_spi_register; |
| 2150 | } |
| 2151 | dev_dbg(&pdev->dev," probe succeeded\n"); |
| 2152 | |
| 2153 | /* let runtime pm put suspend */ |
| 2154 | if (platform_info->autosuspend_delay > 0) { |
| 2155 | dev_info(&pdev->dev, |
| 2156 | "will use autosuspend for runtime pm, delay %dms\n", |
| 2157 | platform_info->autosuspend_delay); |
| 2158 | pm_runtime_set_autosuspend_delay(dev, |
| 2159 | platform_info->autosuspend_delay); |
| 2160 | pm_runtime_use_autosuspend(dev); |
| 2161 | pm_runtime_put_autosuspend(dev); |
| 2162 | } else { |
| 2163 | pm_runtime_put(dev); |
| 2164 | } |
| 2165 | return 0; |
| 2166 | |
| 2167 | err_spi_register: |
| 2168 | if (platform_info->enable_dma) |
| 2169 | zx297510_dma_remove(zx297510spi); |
| 2170 | |
| 2171 | free_irq(irq->start, zx297510spi); |
| 2172 | err_no_irq: |
| 2173 | clk_disable(zx297510spi->spi_clk); |
| 2174 | // err_no_clk_en: |
| 2175 | //clk_unprepare(pl022->clk); |
| 2176 | //err_clk_prep: |
| 2177 | clk_put(zx297510spi->spi_clk); |
| 2178 | err_no_clk: |
| 2179 | iounmap(zx297510spi->virtbase); |
| 2180 | err_gpios: |
| 2181 | /* add */ |
| 2182 | err_no_ioremap: |
| 2183 | err_no_registers: |
| 2184 | spi_master_put(master); |
| 2185 | err_no_master: |
| 2186 | err_no_pdata: |
| 2187 | return status; |
| 2188 | } |
| 2189 | |
| 2190 | static int __exit zx297510_spi_remove(struct platform_device *pdev) |
| 2191 | { |
| 2192 | struct zx297510_spi *zx297510spi = dev_get_drvdata(&pdev->dev); |
| 2193 | struct resource * gpio = NULL; |
| 2194 | struct resource * irq = NULL; |
| 2195 | int i; |
| 2196 | |
| 2197 | if (!zx297510spi) |
| 2198 | return 0; |
| 2199 | |
| 2200 | /* |
| 2201 | * undo pm_runtime_put() in probe. I assume that we're not |
| 2202 | * accessing the primecell here. |
| 2203 | */ |
| 2204 | pm_runtime_get_noresume(&pdev->dev); |
| 2205 | |
| 2206 | load_spi_default_config(zx297510spi); |
| 2207 | if (zx297510spi->master_info->enable_dma) |
| 2208 | zx297510_dma_remove(zx297510spi); |
| 2209 | |
| 2210 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 2211 | if( irq != NULL ) |
| 2212 | { |
| 2213 | free_irq(irq->start, zx297510spi); |
| 2214 | } |
| 2215 | |
| 2216 | clk_disable(zx297510spi->spi_clk); |
| 2217 | clk_put(zx297510spi->spi_clk); |
| 2218 | |
| 2219 | clk_disable(zx297510spi->pclk); |
| 2220 | clk_put(zx297510spi->pclk); |
| 2221 | |
| 2222 | /* gpios txd rxd sclk sfr */ |
| 2223 | for(i = 0; i < ARRAY_SIZE(spi_gpio_resources); i++){ |
| 2224 | //gpio = platform_get_resource(pdev, IORESOURCE_IO, i); |
| 2225 | gpio = &spi_gpio_resources[i]; |
| 2226 | |
| 2227 | if( gpio != NULL ) |
| 2228 | { |
| 2229 | gpio_free(gpio->start); |
| 2230 | } |
| 2231 | } |
| 2232 | |
| 2233 | iounmap(zx297510spi->virtbase); |
| 2234 | //amba_release_regions(adev); |
| 2235 | tasklet_disable(&zx297510spi->pump_transfers); |
| 2236 | spi_unregister_master(zx297510spi->master); |
| 2237 | spi_master_put(zx297510spi->master); |
| 2238 | //amba_set_drvdata(adev, NULL); |
| 2239 | dev_set_drvdata(&pdev->dev, NULL); |
| 2240 | return 0; |
| 2241 | } |
| 2242 | |
| 2243 | static struct platform_driver zx297510_spi_driver = { |
| 2244 | .driver = { |
| 2245 | .name = "zx297510_ssp", |
| 2246 | .owner = THIS_MODULE, |
| 2247 | }, |
| 2248 | .probe = zx297510_spi_probe, |
| 2249 | .remove = __exit_p(zx297510_spi_remove), |
| 2250 | }; |
| 2251 | |
| 2252 | static int __init zx297510_spi_init(void) |
| 2253 | { |
| 2254 | return platform_driver_register(&zx297510_spi_driver); |
| 2255 | } |
| 2256 | |
| 2257 | static void __exit zx297510_spi_exit(void) |
| 2258 | { |
| 2259 | platform_driver_unregister(&zx297510_spi_driver); |
| 2260 | } |
| 2261 | |
| 2262 | module_init(zx297510_spi_init); |
| 2263 | module_exit(zx297510_spi_exit); |
| 2264 | |
| 2265 | MODULE_DESCRIPTION("zx297510 spi controller driver"); |
| 2266 | MODULE_AUTHOR("ZTER"); |
| 2267 | MODULE_LICENSE("ZTE"); |
| 2268 | |