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192.168.1.100 / T106_DC / f233062cffb24a4dec2c0a0f44e784946daad5ed / . / boot / common / src / uboot / drivers / wdt / wdt.c
blob: 8a85cac4a8d5fc1dc9204974f2509f6a4eb00728 [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame]1/*******************************************************************************
2 * Copyright (C) 2016, ZXIC Corporation.
3 *
4 * File Name:
5 * File Mark:
6 * Description:
7 * Others:
8 * Version: 1.0
9 * Author: zxic
10 * Date: 2016.12.15
11 * modify
12 ********************************************************************************/
13
14/****************************************************************************
15* Include files
16****************************************************************************/
17#include <malloc.h>
18#include <errno.h>
19#include <asm/io.h>
20#include <linux/mtd/mtd.h>
21#include <asm-generic/ioctl.h>
22#include <config.h>
23#include <common.h>
24#include <command.h>
25#include <boot_mode.h>
26#include <watchdog.h>
27#include <asm/arch/lsp_crpm.h>
28
xf.libdd93d52023-05-12 07:10:14 -0700[diff] [blame]29
lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame]30/****************************************************************************
31* Local Macros
32****************************************************************************/
33/*used in wdt*/
34#define WDT_DIABLE (0x44495341) /*ascii: DISA*/
35#define WDT_OFF (0x57445446) //ascii:WDTF
36
lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame]37
38/*open and close wdt function for long time operation in boot.*/
39#define RM_WDT_BASE (0x00148000)
40#define RM_WDT_START_REG (0x0014801C) /* Watchdog start or stop register */
41
42#define WDT_RESET_TYPE (TOP_SYSCLK_BASE+0x2c)
43#define RM_MOD_RST (TOP_SYSCLK_BASE+0x74)
44
45#define reg32(addr) (*(volatile unsigned long *)(addr))
46
47
48/****************************************************************************
49* Local Types
50****************************************************************************/
51
52
53/****************************************************************************
54* Global Value
55****************************************************************************/
56
57
58/****************************************************************************
59* Local Funcs
60****************************************************************************/
61
62int wdt_open(void)
63{
64 reg32(RM_WDT_START_REG) = 0x12340001;//open
65 return 0;
66}
67
68int wdt_close(void)
69{
70 reg32(RM_WDT_START_REG) = 0x12340000;//close
71 return 0;
72}
73void wdt_restart(void)
74{
75 volatile u32 tmp = 0;
76
77 //reset
78 reg32(WDT_RESET_TYPE) |= (0x3);
79 //reg32(RM_MOD_RST) &=~(0x3<<12);
80 //reg32(RM_MOD_RST) |=(0x3<<12);
81
82 //clk sel default, clk div
83 tmp =reg32(RM_WDT_BASE + 0x04);
84 tmp &=~(0xff<<8);
85 tmp |=(31<<8);
86 reg32(RM_WDT_BASE + 0x04) = 0x12340000|tmp;
87
88 /*set value int */
89 reg32(RM_WDT_BASE + 0x14) = 0x12340000|0x8;
90
91 /*set load value*/
92 reg32(RM_WDT_BASE + 0x08) = 0x12340000|0x10;
93
94 /*refresh config*/
95 tmp =reg32(RM_WDT_BASE + 0x18);
96 tmp ^=0x3f;
97 reg32(RM_WDT_BASE + 0x18) = 0x12340000|tmp;
98
99 /*wait for refresh ack*/
100 while(1)
101 {
102 if(((reg32(RM_WDT_BASE + 0x10)>>4)&0x3f) == tmp)
103 break;
104 }
105
106 /*start wdt*/
xf.li742dd022023-06-08 01:43:32 -0700[diff] [blame]107 do{
108 reg32(RM_WDT_START_REG) =0x12340001;
109 }while(1);
lh9ed821d2023-04-07 01:36:19 -0700[diff] [blame]110}
111
112int wdt_get_reboot_reason(void)
113{
114 if(reg32(WDT_REBOOT_RECORD_BASE) == 1)
115 printf( "[sys_entry_wdt]: PS watchdog reset! global_cnt = %d; core_cnt = %d\n", (int)reg32(WDT_REBOOT_RECORD_BASE+0x8), (int)reg32(WDT_REBOOT_RECORD_BASE+0xc));
116 else if(reg32(WDT_REBOOT_RECORD_BASE) == 2)
117 printf( "[sys_entry_wdt]: AP watchdog reset! global_cnt = %d; core_cnt = %d\n", (int)reg32(WDT_REBOOT_RECORD_BASE+0x8), (int)reg32(WDT_REBOOT_RECORD_BASE+0xc));
118 else if(reg32(WDT_REBOOT_RECORD_BASE) == 3)
119 printf( "[sys_entry_wdt]: PHY watchdog reset! global_cnt = %d; core_cnt = %d\n", (int)reg32(WDT_REBOOT_RECORD_BASE+0x8), (int)reg32(WDT_REBOOT_RECORD_BASE+0xc));
120 else if(reg32(WDT_REBOOT_RECORD_BASE) == 4)
121 printf( "[sys_entry_wdt]: Rpm watchdog reset! global_cnt = %d; core_cnt = %d\n", (int)reg32(WDT_REBOOT_RECORD_BASE+0x8), (int)reg32(WDT_REBOOT_RECORD_BASE+0xc));
122 else
123 printf( "[sys_entry_wdt]: watchdog no reset!\n");
124
125 return 0;
126}
127
128int wdt_init(void)
129{
130 unsigned int *poweron_type = (unsigned int *)POWERON_TYPE_ADDR; //ÁÙʱʹÓÃ
131
132 /*ap wdt disbale*/
133 /*¸ù¾ÝÆô¶¯ÀàÐÍ£¬¹Ø±Õ²»¼ÓÔغ˵Äwatchdog*/
134 #ifndef CONFIG_ZX297520V3E_WATCH_CAP
135 reg32(WDT_AP_SWITCH_ADDR) = WDT_DIABLE; // larry
136 #endif
137 //reg32(WDT_NV_ADDR) = WDT_OFF;
138
139 if(*poweron_type == POWER_ON_FOTA)
140 {
141 /*turn off PS PHY AP watchdog monitor and close m0 wdt*/
142 reg32(WDT_NV_ADDR) = WDT_OFF;
143 reg32(WDT_PS_SWITCH_ADDR) = WDT_DIABLE;
144 reg32(WDT_PHY_SWITCH_ADDR) = WDT_DIABLE;
145 reg32(WDT_AP_SWITCH_ADDR) = WDT_DIABLE;
146 printf( "[sys_entry]: turn off PS PHY AP watchdog monitor and close m0 wdt! \n");
147 }
148 else if(*poweron_type == POWER_ON_CHARGING)
149 {
150 /*turn off PHY watchdog monitor*/
151 reg32(WDT_PHY_SWITCH_ADDR) = WDT_DIABLE;
152 printf( "[sys_entry]: turn off PHY watchdog monitor! \n");
153
154 }
155
156 return 0;
157}
158
159
160