blob: be775df587fff1f6bada5f8b18d874aa4a26e82b [file] [log] [blame]
lh9ed821d2023-04-07 01:36:19 -07001/*******************************************************************************
2 * Copyright (C) 2016, ZIXC Corporation.
3 *
4 * File Name:
5 * File Mark:
6 * Description:
7 * Others:
8 * Version:
9 * Author:
10 * Date:
11 * History 1:
12 * Date:
13 * Version:
14 * Author:
15 * Modification:
16 * History 2:
17 ********************************************************************************/
18#ifndef __SDIO_H__
19#define __SDIO_H__
20
21
22#include <linux/types.h>
23
24typedef u8 BYTE;
25typedef u32 WORD32;
26typedef u16 WORD16;
27
28#if 0
29typedef int int32_t;
30typedef u32 uint32_t;
31typedef u16 uint16_t;
32typedef u8 uint8_t;
33#endif
34
35#define NULL (void *)0
36
37#define MIN(x,y) ((x) < (y) ? (x) : (y))
38#define MAX(x,y) ((x) > (y) ? (x) : (y))
39#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
40#define REG(x) (*(volatile u32*)(x))
41#define REG8(x) (*(volatile u8*)(x))
42#define REG16(x) (*(volatile u16*)(x))
43#define REG32(x) (*(volatile u32*)(x))
44#define DWC_READ_REG32(a) (*(volatile u32 *)(a))
45#define DWC_WRITE_REG32(a,v) ((*(volatile u32 *)(a)) = v)
46
47
48/*SDIO ²ÎÊý*/
49#define SYS_SDIO_REGS_BASE 0x01540000 //SD1
50#define CFG_SDIO_LOAD_BASE 0x20000000 // SDIO DMA Êý¾Ý°áÔ˵ØÖ
51
52#define SDIO_CMD0 0 /* GO_IDLE_STATE bc */
53#define SDIO_CMD1 1 /* SEND_OP_COND bcr [31:0] OCR R3 */
54#define SDIO_CMD2 2 /* ALL_SEND_CID bcr R2 */
55#define SDIO_CMD3 3 /* SET_RELATIVE_ADDR ac [31:16] RCA R1 */
56#define SDIO_CMD4 4 /* SET_DSR bc [31:16] RCA */
57#define SDIO_CMD5 5 /* IO_SEND_OP_COND ?? ?? */
58#define SDIO_CMD6 6 /* SWITCH FUNC ac R1 */
59 /* For ACMD6:SET_BUS_WIDTH ?? ?? */
60#define SDIO_CMD7 7 /* SELECT_CARD ac [31:16] RCA R1 */
61#define SDIO_CMD8 8 /* SEND_IF_COND adtc [31:16] RCA R1 */
62#define SDIO_CMD9 9 /* SEND_CSD ac [31:16] RCA R2 */
63/* class 7 */
64#define SDIO_CMD52 52 /* SDIO_RW_DIRECT ?? R5 */
65#define SDIO_CMD53 53 /* SDIO_RW_EXTENDED ?? R5 */
66
67/*¼Ä´æÆ÷Æ«ÒÆ*/
68#define SDIO_SLAVE_REGS SYS_SDIO_REGS_BASE
69#define SDIO_SLAVE_CTRL (SDIO_SLAVE_REGS+0x00)
70#define SDIO_SLAVE_CMD (SDIO_SLAVE_REGS+0x04)
71#define SDIO_SLAVE_ARGU (SDIO_SLAVE_REGS+0x08)
72#define SDIO_SLAVE_BLKCNT (SDIO_SLAVE_REGS+0x0C)
73#define SDIO_SLAVE_DMA1ADDR (SDIO_SLAVE_REGS+0x10)
74#define SDIO_SLAVE_DMA1CTRL (SDIO_SLAVE_REGS+0x14)
75
76#define SDIO_SLAVE_ERASE_W_BLKSTART (SDIO_SLAVE_REGS+0x20)
77#define SDIO_SLAVE_ERASE_W_BLKEND (SDIO_SLAVE_REGS+0x24)
78#define SDIO_SLAVE_PASSLE (SDIO_SLAVE_REGS+0x28)
79#define SDIO_SLAVE_SECBLKCNT (SDIO_SLAVE_REGS+0x2C)
80
81#define SDIO_SLAVE_INTSTATUS (SDIO_SLAVE_REGS+0x3C)
82#define SDIO_SLAVE_INTSTATUS_EN (SDIO_SLAVE_REGS+0x40)
83#define SDIO_SLAVE_INTSIGNAL_EN (SDIO_SLAVE_REGS+0x44)
84#define SDIO_SLAVE_CARD_ADDR (SDIO_SLAVE_REGS+0x48)
85#define SDIO_SLAVE_CARD_DATA (SDIO_SLAVE_REGS+0x4C)
86#define SDIO_SLAVE_IOREADY (SDIO_SLAVE_REGS+0x50)
87#define SDIO_SLAVE_FUN1CTRL (SDIO_SLAVE_REGS+0x54)
88#define SDIO_SLAVE_FUN2CTRL (SDIO_SLAVE_REGS+0x58)
89#define SDIO_SLAVE_SDIO_CCCR_CTRL (SDIO_SLAVE_REGS+0x5C)
90#define SDIO_SLAVE_SDIO_FBRx_CTRL (SDIO_SLAVE_REGS+0x60) /* **sdio fbrx ctrl 0x60-0x7c*/
91
92#define SDIO_SLAVE_CARD_SIZE (SDIO_SLAVE_REGS+0x80)
93#define SDIO_SLAVE_CARD_OCR (SDIO_SLAVE_REGS+0x84)
94#define SDIO_SLAVE_CTRL2 (SDIO_SLAVE_REGS+0x88)
95
96#define SDIO_SLAVE_FUN3CTRL (SDIO_SLAVE_REGS+0x90)
97#define SDIO_SLAVE_FUN4CTRL (SDIO_SLAVE_REGS+0x94)
98#define SDIO_SLAVE_FUN5CTRL (SDIO_SLAVE_REGS+0x98)
99#define SDIO_SLAVE_INT_STATUS2 (SDIO_SLAVE_REGS+0x9C)
100#define SDIO_SLAVE_INT_STATUS_EN2 (SDIO_SLAVE_REGS+0xA0)
101#define SDIO_SLAVE_INT_SIGNAL_EN2 (SDIO_SLAVE_REGS+0xA4)
102/*#define SDIO_SLAVE_PASS_127_96 (SDIO_SLAVE_REGS+0xA8)
103#define SDIO_SLAVE_PASS_95_64 (SDIO_SLAVE_REGS+0xAC)
104#define SDIO_SLAVE_PASS_63_32 (SDIO_SLAVE_REGS+0xB0)
105#define SDIO_SLAVE_PASS_31_0 (SDIO_SLAVE_REGS+0xB4)
106#define SDIO_SLAVE_ADMA_ERR_STATUS (SDIO_SLAVE_REGS+0xB8)
107#define SDIO_SLAVE_RCA (SDIO_SLAVE_REGS+0xBC)
108#define SDIO_SLAVE_DBG0 (SDIO_SLAVE_REGS+0xC0)
109#define SDIO_SLAVE_DBG1 (SDIO_SLAVE_REGS+0xC4)
110#define SDIO_SLAVE_DBG2 (SDIO_SLAVE_REGS+0xC8)
111#define SDIO_SLAVE_DBG3 (SDIO_SLAVE_REGS+0xCC)
112#define SDIO_SLAVE_DBG4 (SDIO_SLAVE_REGS+0xD0)
113#define SDIO_SLAVE_DBG5 (SDIO_SLAVE_REGS+0xD4)
114#define SDIO_SLAVE_DBG6 (SDIO_SLAVE_REGS+0xD8)
115#define SDIO_SLAVE_AHB (SDIO_SLAVE_REGS+0xDC)
116#define SDIO_SLAVE_ARGU2 (SDIO_SLAVE_REGS+0xE0)*/
117
118
119/*SDIO_SLAVE_INT_STATUS*/
120#define SDIO_STS_B_C (1<<31) //BOOT COMPLETE
121#define SDIO_STS_LRST (1<<30) //LRST
122#define SDIO_STS_F_A (1<<29) //FUNCTIONX Abort
123#define SDIO_STS_F_CRC_E (1<<28) //FunctionX CRC End Error
124#define SDIO_STS_CMD_R1B (1<<27) //CMD R1B
125#define SDIO_STS_CMD40 (1<<26) //CMD40
126#define SDIO_STS_PRG_ST (1<<25) //PROGRAM START
127#define SDIO_STS_CMD11_C_ST (1<<24) //CMD11 CLK START
128#define SDIO_STS_CMD11_C_SP (1<<23) //CMD11 CLK STOP
129#define SDIO_STS_F2_R (1<<22) //Funtion2 reset
130#define SDIO_STS_F1_R (1<<21) //Funtion1 reset
131#define SDIO_STS_BS (1<<20) //Boot Start
132#define SDIO_STS_CMD4 (1<<19) //CMD4
133#define SDIO_STS_CMD20 (1<<17) //CMD20
134#define SDIO_STS_ACMD23 (1<<16) //ACMD23
135#define SDIO_STS_P_CSD (1<<15) //Program CSD interrupt
136#define SDIO_STS_CMD6_SD (1<<14) //CMD6-Switch Done
137#define SDIO_STS_CMD6_CD (1<<13) //CMD6-Check Done
138#define SDIO_STS_CMD2_CMD52 (1<<12) //Soft Reset
139#define SDIO_STS_CMD11 (1<<11) //Command11 Voltage switch interrupt
140#define SDIO_STS_E (1<<10) //Erase
141#define SDIO_STS_FE (1<<9) //Force Erase
142#define SDIO_STS_UC (1<<8) //Unlock Card
143#define SDIO_STS_LC (1<<7) //Lock Card
144#define SDIO_STS_PR (1<<6) //Password Reset
145#define SDIO_STS_PS (1<<5) //Password Set
146#define SDIO_STS_RS (1<<4) //Read Start
147#define SDIO_STS_WS (1<<3) //Write Start
148#define SDIO_STS_SA (1<<2) //Sleep awake
149#define SDIO_STS_DMA1 (1<<1) //Dma1 interrupt
150#define SDIO_STS_TC (1<<0) //Transfer Complete interrupt
151
152
153void sdio_slave_process(void);
154
155
156
157#endif /* __SDIO_DRV_H__ */
158
159