[Feature][T106_eSDK]17.09(SDK4.8)diff_18.03(SDK4.9)
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: Iee71a4669c8e76c2ae49b66e98054491ab03ad13
diff --git a/Uboot/boot/common/src/uboot/arch/arm/lib/bootm.c b/Uboot/boot/common/src/uboot/arch/arm/lib/bootm.c
new file mode 100755
index 0000000..914259d
--- /dev/null
+++ b/Uboot/boot/common/src/uboot/arch/arm/lib/bootm.c
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <bootimg.h>
+#include <load_image.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <asm/arch/efuse.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+static void setup_start_tag (bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags (bd_t *bd);
+# endif
+static void setup_commandline_tag (bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag (bd_t *bd, ulong initrd_start,
+ ulong initrd_end);
+# endif
+static void setup_end_tag (bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+static ulong get_sp(void);
+#if defined(CONFIG_OF_LIBFDT)
+static int bootm_linux_fdt(int machid, bootm_headers_t *images);
+#endif
+extern int rd_offset ;
+extern int rd_size;
+extern unsigned int g_sys_kernel_sdram_size;
+extern unsigned char g_ddr_size_flag;
+
+#define reg32(addr) (*(volatile unsigned long *)(addr))
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp;
+
+ /*
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
+ */
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+ /* adjust sp by 1K to be safe */
+ sp -= 1024;
+ lmb_reserve(lmb, sp,
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+}
+
+static void announce_and_cleanup(void)
+{
+ printf("\nStarting kernel ...\n");
+
+#ifdef CONFIG_USB_DEVICE
+ {
+ extern void udc_disconnect(void);
+ udc_disconnect();
+ }
+#endif
+ cleanup_before_linux();
+}
+
+//#ifdef CONFIG_ZX297520V3E_WATCH_CAP
+#if defined(CONFIG_ZX297520V3E_WATCH_CAP) || defined (CONFIG_ZX297520V3E_VEHICLE_DC) || defined (CONFIG_ZX297520V3E_VEHICLE_DC_REF)
+#define SYS_CPUCAP_PARAM_ADDR 0x10200C
+extern uint32_t arm_cpucap_ep;
+void set_cpucap_tag(int arch, uint parameter)
+{
+ uint32_t cap_tag_addr = 0;
+
+ cap_tag_addr = arm_cpucap_ep - 0x8000 + 0x100;
+
+ writel(0x0, SYS_CPUCAP_PARAM_ADDR);
+ writel(arch, SYS_CPUCAP_PARAM_ADDR+0x4);
+ writel(cap_tag_addr, SYS_CPUCAP_PARAM_ADDR+0x8);
+
+ memcpy(cap_tag_addr, parameter, 0x800);
+}
+#endif
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv ("bootargs");
+#endif
+
+ if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+ {
+ return 1;
+ }
+
+
+ s = getenv ("machid");
+ if (s)
+ {
+ machid = simple_strtoul (s, NULL, 16);
+ printf ("Using machid 0x%x from environment\n", machid);
+ }
+
+ show_boot_progress (15);
+
+#ifdef CONFIG_OF_LIBFDT
+#if 0
+ if (images->ft_len)
+ {
+ debug("start device tree...\n");
+ //return bootm_linux_fdt(machid, images);
+ bootm_linux_fdt(machid, images);
+ }
+#endif
+#if defined(CONFIG_ZX297520V3E_VEHICLE_DC) || defined(CONFIG_ZX297520V3E_VEHICLE_DC_REF)
+ debug("start device tree...\n");
+ bootm_linux_fdt(machid, images);
+ //fdt_chosen(images->ft_addr, 1);
+#endif
+
+#endif
+
+ kernel_entry = (void (*)(int, int, uint))images->ep;
+
+ debug ("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+ setup_start_tag (bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag (¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag (¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags (bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag (bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (images->rd_start && images->rd_end)
+ setup_initrd_tag (bd, images->rd_start, images->rd_end);
+#endif
+ setup_end_tag(bd);
+#endif
+
+//#ifdef CONFIG_ZX297520V3E_WATCH_CAP
+#if defined(CONFIG_ZX297520V3E_WATCH_CAP) || defined (CONFIG_ZX297520V3E_VEHICLE_DC) || defined (CONFIG_ZX297520V3E_VEHICLE_DC_REF)
+ memset(ICP_CAP_BUF_ADDR, 0, ICP_CAP_BUF_LEN);
+ memset(IRAM_BASE_ADDR_SYS_TRACE, 0, IRAM_BASE_LEN_SYS_TRACE);
+ if(!read_fota_update_flag())
+ {
+ cap_poweron();
+ set_cpucap_tag(machid, bd->bi_boot_params);
+ start_cpucap_cores();
+ }
+#endif
+ printf("===chiid=0x%x,boot_params=0x%x\n", machid, bd->bi_boot_params);
+ announce_and_cleanup();
+ kernel_entry(0, machid, bd->bi_boot_params);
+
+ /* does not return */
+ return 1;
+}
+
+//add by zhouqi
+int do_booti_linux( boot_img_hdr *hdr )
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv ("bootargs");
+#endif
+
+ s = getenv ("machid");
+ if (s) {
+ machid = simple_strtoul (s, NULL, 16);
+ printf ("Using machid 0x%x from environment\n", machid);
+ }
+
+ show_boot_progress (15);
+
+#ifdef CONFIG_OF_LIBFDT
+ //if (images->ft_len)
+ //return bootm_linux_fdt(machid, images);
+#endif
+
+ kernel_entry = (void (*)(int, int, uint))hdr->kernel_addr;
+
+ debug ("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+ setup_start_tag (bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag (¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag (¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags (bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag (bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (hdr->ramdisk_size)
+ setup_initrd_tag (bd, hdr->ramdisk_addr, hdr->ramdisk_size + hdr->ramdisk_addr);
+#endif
+ setup_end_tag(bd);
+#endif
+
+ announce_and_cleanup();
+
+ kernel_entry(0, machid, bd->bi_boot_params);
+ /* does not return */
+
+ return 1;
+}
+
+
+#if defined(CONFIG_OF_LIBFDT)
+static int fixup_memory_node(void *blob)
+{
+ bd_t *bd = gd->bd;
+ int bank;
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ //start[bank] = bd->bi_dram[bank].start;
+ //size[bank] = bd->bi_dram[bank].size;
+ start[bank] = DDR_BASE_ADDR_CAP;
+ if(g_ddr_size_flag == CHIP_DDR_IS_128M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = DDR_BASE_LEN_CAP;
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_256M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP + 0x8000000;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = (DDR_BASE_LEN_CAP + 0x8000000);
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_512M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP + 0x18000000;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = (DDR_BASE_LEN_CAP + 0x18000000);
+ }
+ else
+ {
+ debug("ddr size is error.\n");
+ return 0;
+ }
+ }
+ debug("size is 0x%llx\n",size[0]);
+ return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+
+static int bootm_linux_fdt(int machid, bootm_headers_t *images)
+{
+ ulong rd_len;
+ void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ ulong *initrd_start = &images->initrd_start;
+ ulong *initrd_end = &images->initrd_end;
+ struct lmb *lmb = &images->lmb;
+ int ret;
+
+ kernel_entry = (void (*)(int, int, void *))images->ep;
+
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ rd_len = images->rd_end - images->rd_start;
+ ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
+ initrd_start, initrd_end);
+ if (ret)
+ return ret;
+
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+ fdt_chosen(*of_flat_tree, 1);
+
+ fixup_memory_node(*of_flat_tree);
+
+#if 0
+ fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ announce_and_cleanup();
+
+ kernel_entry(0, machid, *of_flat_tree);
+ /* does not return */
+#endif
+ return 1;
+}
+#endif
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+static void setup_start_tag (bd_t *bd)
+{
+ params = (struct tag *) bd->bi_boot_params;
+
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size (tag_core);
+
+ params->u.core.flags = 0x1;//0;
+ params->u.core.pagesize =0x1000; //0;
+ params->u.core.rootdev = 0x0;//0;
+
+ params = tag_next (params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags (bd_t *bd)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size (tag_mem32);
+
+ /* modify by zhouqi 2013/06/27 */
+ params->u.mem.start = read_sys_ddr_kernel_start();
+ params->u.mem.size = g_sys_kernel_sdram_size; //CONFIG_SYS_SDRAM_A9_SIZE;
+
+ params = tag_next (params);
+ }
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag (bd_t *bd, char *commandline)
+{
+ char *p;
+
+ if (!commandline)
+ return;
+
+ /* eat leading white space */
+ for (p = commandline; *p == ' '; p++);
+
+ /* skip non-existent command lines so the kernel will still
+ * use its default command line.
+ */
+ if (*p == '\0')
+ return;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof (struct tag_header) + strlen (p) + 1 + 4) >> 2;
+
+ strcpy (params->u.cmdline.cmdline, p);
+
+ params = tag_next (params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+ /* an ATAG_INITRD node tells the kernel where the compressed
+ * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+ */
+ params->hdr.tag = ATAG_INITRD2;
+ params->hdr.size = tag_size (tag_initrd);
+
+ params->u.initrd.start = rd_offset;//initrd_start;
+ params->u.initrd.size =rd_size;//initrd_end - initrd_start;
+
+
+ params = tag_next (params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag (struct tag **tmp)
+{
+ struct tag *params = *tmp;
+ struct tag_serialnr serialnr;
+ void get_board_serial(struct tag_serialnr *serialnr);
+
+ get_board_serial(&serialnr);
+ params->hdr.tag = ATAG_SERIAL;
+ params->hdr.size = tag_size (tag_serialnr);
+ params->u.serialnr.low = serialnr.low;
+ params->u.serialnr.high= serialnr.high;
+ params = tag_next (params);
+ *tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+ u32 rev = 0;
+ u32 get_board_rev(void);
+
+ rev = get_board_rev();
+ params->hdr.tag = ATAG_REVISION;
+ params->hdr.size = tag_size (tag_revision);
+ params->u.revision.rev = rev;
+ params = tag_next (params);
+}
+#endif /* CONFIG_REVISION_TAG */
+
+static void setup_end_tag (bd_t *bd)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
diff --git a/Uboot/boot/common/src/uboot/drivers/power/zx234290.c b/Uboot/boot/common/src/uboot/drivers/power/zx234290.c
new file mode 100755
index 0000000..6e82f81
--- /dev/null
+++ b/Uboot/boot/common/src/uboot/drivers/power/zx234290.c
@@ -0,0 +1,938 @@
+/*********************************************************************
+ Copyright 2016 by ZIXC Corporation.
+*
+* FileName:: zx234290.c
+* File Mark:
+* Description:
+* Others:
+* Version:
+* Author:
+* Date:
+
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+#include <common.h>
+#include <errno.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <boot_mode.h>
+#include <i2c.h>
+#include <drvs_gpio.h>
+#include <power.h>
+#include <zx234290.h>
+#include <zx234502.h>
+#include <watchdog.h>
+
+int zx234290_write_flag(UINT8 val);
+
+#define PIN_PSHOLD_NUM GPIO24
+#define GPIO_PSHOLD_FUNC_SEL GPIO24_GPIO24
+
+static boot_reason_t s_boot_reason = UNKNOWN_BOOT_REASON;
+unsigned int g_pmu_type = PMU_TYPE_MAX;
+
+/*******************************************************************************
+ * Function: zx234290_i2c_read_reg
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_i2c_read_reg(ushort reg, uchar *val)
+{
+ return i2c_read(0, ZX234290_I2C_SLAVE_ADDR, reg, 8, val, 1);
+}
+
+/*******************************************************************************
+ * Function: zx234290_i2c_write_reg
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_i2c_write_reg(ushort reg, uchar *val)
+{
+ return i2c_write(0, ZX234290_I2C_SLAVE_ADDR, reg, 8, val, 1);
+}
+
+int zx234290_reset_flag(void)
+{
+#if 0
+ int ret = 0;
+ int val = 0;
+
+ /*
+ int val = 0xff;
+ ret = zx234290_i2c_write_reg(0x0f,&val);
+ */
+ ret = zx234290_i2c_read_reg(BUCK_MODE_CONTROL0, &val);
+ val &= (~0x30);
+ ret += zx234290_i2c_write_reg(BUCK_MODE_CONTROL0, &val);
+
+ return ret;
+#else
+ return zx234290_write_flag(ZX234290_USER_RST_UNDEFINE);
+#endif
+}
+
+int zx234290_write_flag(UINT8 val)
+{
+#if 0
+ int ret = 0;
+ int tmp = 0;
+
+ if(val > 3)
+ {
+ return -1;
+ }
+ ret = zx234290_i2c_read_reg(BUCK_MODE_CONTROL0, &tmp);
+ tmp &= (~0x30);
+ tmp |= (val<<4);
+ ret += zx234290_i2c_write_reg(BUCK_MODE_CONTROL0, &tmp);
+
+ return ret;
+#else
+ int ret = 0;
+ uchar tmp = 0;
+
+ /*
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_USER_RESERVED, &tmp);
+ tmp &= ~(0x03<<2);
+ tmp |= (val<<2);
+ */
+ tmp = val;
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_USER, &tmp);
+
+ return ret;
+#endif
+}
+
+
+void zx234290_set_rtc_alarm_off(void)
+{
+ int ret = 0;
+ uchar tmp = 0;
+
+ //set alarm active bit 1 disable
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_MINUTE, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_MINUTE, &tmp);
+
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_HOUR, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_HOUR, &tmp);
+
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_DAY, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_DAY, &tmp);
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_WEEK, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_WEEK, &tmp);
+
+
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_SECOND, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_SECOND, &tmp);
+
+ /*disable AIE bit && AF*/
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_RTC_CONTROL2, &tmp);
+ tmp &= ~(RTC_CONTROL2_AIE|RTC_CONTROL2_AF);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_RTC_CONTROL2, &tmp);
+
+ if(ret)
+ printf( "[%s] fail ret=%d...\n", __FUNCTION__, ret);
+
+}
+/*******************************************************************************
+ * Function: zx234290_get_boot_reason
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_get_boot_reason(boot_reason_t *boot_reason)
+{
+ if (boot_reason == NULL)
+ {
+ return -1;
+ }
+
+ if(s_boot_reason == UNKNOWN_BOOT_REASON)
+ {
+ return -EIO;
+ }
+ *boot_reason = s_boot_reason;
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_get_boot_reason
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+static int zx234290_get_boot_reason_prev(void)
+{
+ int ret = 0;
+ uchar reg_user = ZX234290_USER_RST_UNDEFINE;
+ uchar reg_start = 0;
+ uchar reg_write = 0;
+
+ /* ¶Á²¢ÇåSTART_UP_STATUS */
+ ret = zx234290_i2c_read_reg(START_UP_STATUS, ®_start);
+ if( ret != 0 )
+ {
+ return -EIO;
+ }
+ printf( " [%s][START_UP_STATUS = 0x%X] ...\n", __FUNCTION__, reg_start);
+ (*(volatile unsigned long *)(START_UP_STATUS_BASE))=reg_start;
+
+ /* ¶Á²¢ÇåZX234290_REG_USER */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_USER, ®_user);
+ if(reg_user != ZX234290_USER_RST_UNDEFINE)
+ {
+ reg_write = ZX234290_USER_RST_UNDEFINE; /* write back the reset value */
+
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_USER, ®_write);
+ }
+ if ( ret != 0 )
+ {
+ return -EIO;
+ }
+ printf( " [%s][USER_RESERVED = 0x%X] ...\n", __FUNCTION__, reg_user);
+ (*(volatile unsigned long *)(USER_RESERVED_BASE)) =reg_user;
+
+ /* 1. Õý³£¿ª»ú¼ì²â */
+ if( reg_start & PWR_ON_START_UP )
+ /* ϵͳÖØÆô,Èç¹ûZX234290_REG_USER²»Îª³õÖµ£¬ÔòΪÖØÆô */
+ {
+ s_boot_reason = RB_POWER_KEY;
+ return 0;
+ }
+ else if( reg_start & PS_HOLD_START_UP )
+ {
+ s_boot_reason = RB_USB_INSERT;
+
+ /* ZX234290_REG_USERΪÉϵ縴λֵ»ò·Ç·¨Öµ */
+ return 0;
+ }
+ else if( reg_start & RTC_ALARM_START_UP )
+ /* 2. Õý³£¿ª»ú¼ì²â */
+ {
+ uchar rtc_ctrl2 = 0xF0;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_RTC_CONTROL2, &rtc_ctrl2);
+ printf( " [%s][RTC_CONTROL2 = 0x%X]\n", __FUNCTION__, rtc_ctrl2);
+
+ if (rtc_ctrl2 & RTC_CONTROL2_AF) {
+ s_boot_reason = RB_RTC;
+ zx234290_set_rtc_alarm_off();
+ } else if (rtc_ctrl2 & RTC_CONTROL2_TF) {
+ s_boot_reason = RB_RESET_NOMAL;
+ }
+
+ return ret;
+ }
+ else if( reg_start & LLP_RESTART_UP )
+ {
+ s_boot_reason = RB_POWER_KEY_LONG;
+ return 0;
+ }
+ /* reg_startΪ0£¬¼´reg_start¶ÁÇåÖ®ºóδµôµç£¬¼´ÏµÍ³ÖØÆô */
+
+ /* 2. ÖØÆô¼ì²â */
+
+ /* ϵͳÖØÆô,Èç¹ûZX234290_REG_USER²»Îª³õÖµ£¬ÔòΪÖØÆô */
+ switch (reg_user)
+ {
+ case ZX234290_USER_RST_TO_NORMAL:
+ {
+ s_boot_reason = RB_RESET_NOMAL;
+ return 0;
+ }
+
+ case ZX234290_USER_RST_TO_CHARGER:
+ {
+ s_boot_reason = RB_RESET_USB_OFF;
+ return 0;
+ }
+
+ case ZX234290_USER_RST_TO_ALARM:
+ {
+ s_boot_reason = RB_RESET_ALARM;
+ return 0;
+ }
+
+ /* ZX234290_REG_USERΪÉϵ縴λֵ»ò·Ç·¨Öµ */
+ default:
+ {
+ if ((reg_user & 0xF0) == ZX234290_WDT_RST_FLAG) {
+ s_boot_reason = reg_user;
+ return 0;
+ }
+ break;
+ }
+ }
+
+ s_boot_reason = RB_USB_INSERT;
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_ps_hold_pull_on
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_ps_hold_pull_on(void)
+{
+ zDrvGpio_PullUpDown(PIN_PSHOLD_NUM, 0);
+ //gpio_set_reuse(PS_HOLD_PIN, 0);
+ zDrvGpio_SetFunc(PIN_PSHOLD_NUM,GPIO_PSHOLD_FUNC_SEL);
+ zDrvGpio_SetDirection(PIN_PSHOLD_NUM,GPIO_IN); //set output;v3 gpio24(pshold) direction is reverse
+ zDrvGpio_SetOutputValue(PIN_PSHOLD_NUM,GPIO_HIGH);
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_ps_hold_pull_off
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_ps_hold_pull_off(void)
+{
+ zDrvGpio_PullUpDown(PIN_PSHOLD_NUM, 0);
+ //gpio_set_reuse(PS_HOLD_PIN, 0);
+ //gpio_direction_output(PS_HOLD_PIN, GPIO_LOW);
+ zDrvGpio_SetFunc(PIN_PSHOLD_NUM,GPIO_PSHOLD_FUNC_SEL);
+ zDrvGpio_SetDirection(PIN_PSHOLD_NUM,GPIO_IN); //set output;v3 gpio24(pshold) direction is reverse
+ zDrvGpio_SetOutputValue(PIN_PSHOLD_NUM,GPIO_LOW);
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_power_off
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_power_off(void)
+{
+ return zx234290_ps_hold_pull_off();
+}
+
+/*******************************************************************************
+ * Function:
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int pmu_init(void)
+{
+ int ret = 0;
+ uchar reg_val = 0;
+ uchar reg_val1 = 0;
+ struct pmu_opt pmu = {NULL};
+
+ /* GPIO init */
+ //gpio_set_reuse(PS_HOLD_PIN, 0x0);
+ //gpio_direction_output(PS_HOLD_PIN,GPIO_LOW);
+
+ // gpio_set_reuse(POWER_KEY_PIN,0x0);
+ // gpio_direction_input(POWER_KEY_PIN);
+
+ // gpio_noaction(POWER_KEY_PIN);
+
+ /* register pmu opt */
+ pmu.read_reg = zx234290_i2c_read_reg;
+ pmu.write_reg = zx234290_i2c_write_reg;
+ pmu.get_boot_reason = zx234290_get_boot_reason;
+ pmu.ps_hold_pull_on = pmu_pull_on_ps_hold;
+ pmu.ps_hold_pull_off = pmu_pull_off_ps_hold;
+ pmu.power_off = zx234290_power_off;
+ ret = register_pmu_opt(&pmu);
+ if( ret != 0 )
+ {
+ return -EIO;
+ }
+
+ ret = zx234290_get_boot_reason_prev();
+ ret +=zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL,®_val);
+ ret +=zx234290_i2c_read_reg(ZX234290_REG_ADDR_TYPE,®_val1);
+ if(reg_val==0x7f){//means 296G C
+ reg_val = 0xff;//define to 296
+ ret+=zx234290_i2c_write_reg(ZX234297_REG_ADDR_SINK_CONTROL,®_val);
+ }
+
+ if (ret != SUCCESS)
+ {
+ printf( "[%s]set 0x29 error ret=0x%x!\n", __FUNCTION__,ret);
+ return ret;
+ }
+
+ if(0xff == reg_val)//296&296G
+ {
+ if(0==reg_val1)
+ g_pmu_type = PMU_TYPE_296G;
+ else
+ g_pmu_type = PMU_TYPE_296;
+ }
+ else//297
+ {
+ if(0==reg_val1)
+ g_pmu_type = PMU_TYPE_296H;
+ else
+ g_pmu_type = PMU_TYPE_297;
+ }
+ return ret;
+}
+
+/* ================================================================================
+ * pmu_init:
+ */
+int pmu_pull_off_ps_hold(void)
+{
+ return zx234290_ps_hold_pull_off();
+}
+
+/* ================================================================================
+ * pmu_init:
+ */
+int pmu_pull_on_ps_hold(void)
+{
+ return zx234290_ps_hold_pull_on();
+}
+
+/* ================================================================================
+ * system_power_off:
+ */
+void system_power_off(void)
+{
+ zx234290_power_off();
+}
+
+int zx234290_get_adc2_voltage(void)
+{
+ int nTempAdc = 0, ret = -1;
+ int adcReadInt = -1;
+ int msb=0, lsb=0;
+ int num;
+ uchar status_a=0;
+ uchar adcEnable = 0x28;
+ uchar sys_ctrl;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ sys_ctrl = (sys_ctrl & (1 << 7)) | adcEnable;
+
+ /*enable adc*/
+#if 0
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL,&sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+#else
+ for(num=1; num <= 50; num++)
+ {
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ udelay((100000/3000)*5); /* delay 5ms */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_STSA, &status_a);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ if(status_a & 0x04)
+ {
+ printf( "adc2 get adc,break num =%d ...\n", num);
+ break;
+ }
+ }
+#endif
+ udelay((100000/3000)*20); /* delay 20ms */
+
+ /*read adc*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC2MSB, &msb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC2LSB, &lsb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ /*clear int*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_INTA, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret =zx234290_i2c_read_reg(ZX234290_REG_INTB, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ nTempAdc = ((msb<<4)|(lsb>>4));
+
+ nTempAdc = (int)((double)(5000-0)*(nTempAdc)/4096);
+
+ return nTempAdc;
+}
+
+int zx234290_get_adc1_voltage(void) /*read adc1*/
+{
+ int nTempAdc = 0,adcEnable = 0,ret = -1;
+ int adcReadInt = -1;
+ int msb=0, lsb=0;
+ int num;
+ uchar status_a=0;
+ adcEnable = 0x30; /*read adc1*/
+ uchar sys_ctrl;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ sys_ctrl = (sys_ctrl & (1 << 7)) | adcEnable;
+
+ /*enable adc*/
+#if 0
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL,&sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+#else
+ for(num=1; num <= 50; num++)
+ {
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ udelay((100000/3000)*5); /* delay 5ms */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_STSA, &status_a);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ if(status_a & 0x04)
+ {
+ printf( "adc1 get adc,break num =%d ...\n", num);
+ break;
+ }
+ }
+#endif
+
+ udelay((100000/3000)*20); /* delay 20ms */
+
+ /*read adc*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1MSB, &msb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1LSB, &lsb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ /*clear int*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_INTA, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret =zx234290_i2c_read_reg(ZX234290_REG_INTB, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ nTempAdc = ((msb<<4)|(lsb>>4));
+
+ nTempAdc = (int)((double)(5000-0)*(nTempAdc)/4096);
+
+ return nTempAdc;
+}
+
+int zx234290_get_vbat_voltage(void)
+{
+ int nTempAdc = 0,adcEnable = 0,ret = -1;
+ int adcReadInt = -1;
+ int msb=0, lsb=0;
+ int num;
+ uchar status_a=0;
+ //adcEnable = 0x30;
+ adcEnable = 0x20;
+ uchar sys_ctrl;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ sys_ctrl = (sys_ctrl & (1 << 7)) | adcEnable;
+
+#if 0
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL,&sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+#else
+ for(num=1; num <= 50; num++)
+ {
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ udelay((100000/3000)*5); /* delay 5ms */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_STSA, &status_a);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ if(status_a & 0x04)
+ {
+ printf( "vbat get adc,break num =%d ...\n", num);
+ break;
+ }
+ }
+#endif
+ //ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1MSB, &msb);
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_VBATMSB, &msb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ //ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1LSB, &lsb);
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_VBATLSB, &lsb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_INTA, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret =zx234290_i2c_read_reg(ZX234290_REG_INTB, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ nTempAdc = ((msb<<4)|(lsb>>4));
+ nTempAdc = (int)((double)(5000-0)*(nTempAdc)/4096);
+ return nTempAdc;
+}
+
+int zx234290_set_llp_enable(void)
+{
+ int ret = -1;
+ ushort reg=ZX234290_REG_ADDR_PWRON;
+ uchar val=0x05;
+
+ ret = zx234290_i2c_write_reg(reg, &val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ return ret;
+}
+
+/*get the poweron key state 0x1<<5: poweron press 0:poweron up*/
+int zx234290_get_poweron_state(void)
+{
+ int val = 0,ret = -1;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(STATUS_A,®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ val = reg&STATUS_PWR_ON;
+ return val;
+}
+
+/* get the rtc_alarm status: bit0 in reg 0x05 */
+int zx234290_get_rtc_state(void)
+{
+ int val = 0,ret = -1;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(STATUS_B, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ val = reg & STATUS_RTC_ALARM;
+ return val;
+}
+
+/* Set or clear SoftOn bit in ZX234290_REG_SYS_CTRL */
+int zx234290_set_softon(int on)
+{
+ uchar reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ if ((reg >> 7) != on) {
+ reg ^= (0x01<<7);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ }
+ return 0;
+}
+
+/*set ldo8 SD VOL*/
+int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol)
+{
+ int ret = 0;
+ unsigned char reg_addr=0, reg_val=0;
+
+ if(vol > VLDOD_MAX)
+ {
+ return -EINVAL;
+ }
+ reg_addr = ZX234290_REG_ADDR_LDO78_VOL;
+ ret = zx234290_i2c_read_reg(reg_addr,®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg_val &= ~(0xf<<ZX234290_LDO8_VSEL_LSH);
+ reg_val |= (vol<<ZX234290_LDO8_VSEL_LSH);
+
+ ret = zx234290_i2c_write_reg(reg_addr, ®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int zx234290_set_ldo8_sleep_voltage(T_ZDrvZx234290_VldoD vol)
+{
+ int ret = 0;
+ unsigned char reg_addr=0, reg_val=0;
+
+ if(vol > VLDOD_MAX)
+ {
+ return -EINVAL;
+ }
+ reg_addr = ZX234290_REG_ADDR_LDO78_VOL;
+ ret = zx234290_i2c_read_reg(reg_addr,®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg_val &= ~(0xf<<ZX234290_LDO8_SLP_VSEL_LSH);
+ reg_val |= (vol<<ZX234290_LDO8_SLP_VSEL_LSH);
+
+ ret = zx234290_i2c_write_reg(reg_addr, ®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
+/* clear SoftOn bit in ZX234290_REG_SYS_CTRL bit7 */
+int zx234290_ldo8_enable(int enable)
+{
+ int ret = -1;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_LDO_EN1, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg &= ~(0x01<<7);
+ reg |= (enable<<7);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_LDO_EN1, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ return 0;
+}
+int zx234290_set_sink(T_ZX234290_SINK sink_num, int is_on, T_ZX234297_SINK_CURRENT sink_current)
+{
+ int ret = 0;
+ unsigned char lsh_on, lsh_current;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ if(0xff==reg){
+ printf("pmu zx234296 no sink\n");
+ return SUCCESS;
+ }
+ if (sink_num == SINK_1) {
+ lsh_on = ZX234297_SINK1_ON_LSH;
+ lsh_current = ZX234297_SINK1_CURRENT_LSH;
+ } else if (sink_num == SINK_2) {
+ lsh_on = ZX234297_SINK2_ON_LSH;
+ lsh_current = ZX234297_SINK2_CURRENT_LSH;
+ } else
+ return -EINVAL;
+
+ if (is_on) {
+ if (sink_current >= SINK_CURRENT_MAX)
+ sink_current = SINK_CURRENT_120MA;
+
+ ret = zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg &= ~(0xf<<lsh_current);
+ reg |= (sink_current<<lsh_current);
+ ret = zx234290_i2c_write_reg(ZX234297_REG_ADDR_SINK_CONTROL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ }
+
+ is_on = !!is_on;
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_LDO_EN2, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg &= ~(0x1<<lsh_on);
+ reg |= (is_on<<lsh_on);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_ADDR_LDO_EN2, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+#if 0
+int zx234290_SetVldo8(Zx234290_VldoD vol)
+{
+ int reg = 0,val = 0,ret = -1;
+ ret = zx234290_i2c_read_reg(ZX234290_REG_LD78_VOL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ BOOT_PRINTF(UBOOT_ERR, "********First REG0x15=0x%x!!!\n",reg);
+ reg &= 0xf;/*00001111*/
+ reg |= (vol<<4);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_LD78_VOL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_LD78_VOL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ BOOT_PRINTF(UBOOT_ERR, "********Last REG0x15=0x%x!!!\n",reg);
+ return 0;
+}
+
+#endif
+
+
diff --git a/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
new file mode 100755
index 0000000..c3de9f3
--- /dev/null
+++ b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
Binary files differ
diff --git a/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
new file mode 100755
index 0000000..4a7e274
--- /dev/null
+++ b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
@@ -0,0 +1,14691 @@
+Mapfile generated by: ZView-4.1.0-Windows
+Archive member included because of file (symbol)
+
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o (_odo_zsp_do_int)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o (_create_process)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o (_odo_panic)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_sys)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_main)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_process_entry)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o) (_send)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_start_zcos)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_go_search)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o) (_alloc)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o) (_odo_arch_init_interrupts)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_ZSP_DCacheUseDCFGRDescribe)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_ZSP_DCacheEnableNCSRAM)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o) (___zsp_dc_mba)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor_addr.o)
+ T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o) (___zsp_dc_mba_value)
+T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o) (_odo_pool_list)
+T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_TIMER0_ISR)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_BspTimerInit1)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_DrvPhyTimer1Init)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_L1_SysErrHnd)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_LoadStaticIDNCSRAM)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_SysEntry)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_g_atHookInfo)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_dwMacroSupport_ZX7520_PHY_SP_PS)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_w_assert)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_InitComAtNv)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_save_zsp880_reg)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_L1_DrvL2CacheTcmEnable)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_L1_DrvCacheDisable)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_DrvDmaInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_zDrvRpMsg_CreateChannel)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_LpmLatchInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o) (_g_dwPHY_USE_PSM)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_LpcDrvChangeCpuPhyFreq)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_tL1IratLpCtrl)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_aeClkSelToCpuFreq)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_PhyPowerOffSaveContext)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_PhyPowerOff)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_DrvWDTFeedDog)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_printk)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_iomemcpy_32)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o) (_L1_DrvL1CacheInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o) (_g_atDmaRegCh)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(dmc_zsp_0x140_lp.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_dei_handler_lp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheDsc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheDisableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheEnableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_ZSP_ICacheFlush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheLoadNCSRAM)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheUseICFGRDescribe)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheNonCacheableDisable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheDisableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheEnableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_ZSP_DCacheFlush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_DCacheLoadNCSRAM)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheClean)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheSetWriteThruRegion)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteAllocateEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteThruEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteThruDisable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheNonCacheableEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheExtraNonCacheableEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor_addr.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o) (___zsp_ic_mba_value)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_g_L1wPriTaskPid)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_g_tL1wNvBb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_BchTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DevMeasGetPreSyncInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_HspaTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DevRtxRxPchCfgReq)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_L1w_DevRfSleepInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevPcPilotIntInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o) (_g_tL1wHsdpaDbgInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_wL1wLessCfgIdx)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DrvDpramRxWriteClearData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_g_tUlRfTbl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevTxGetDchState)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1W_DevHsupaInitMacro)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_eDivState)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_DlsTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o) (_TAB_L1W_HSDPA_HSDPCCH_ACK_CODING)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_wPiAiAfcIntCnt)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o) (_L1w_DevCsrIntInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (_tPcCalcDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (_g_awL1wEngTempBuffer)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_g_tTxTrchInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRxSccpchDtrParam)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o) (_L1w_DevHsdpaCqiCalcPos)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o) (_L1w_DevRtxRxDecodePcch)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o) (_g_eL1wHsupaTaskType)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_L1w_DevRtxRxIntDataInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o) (_g_tL1wDchDlsPsrReq)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_L1w_DevHsupaIsEfachActive)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_bIsWUsePsm)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_tAfcErrorPrint)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o) (_g_atL1wTpuRegNtFixedEventInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_atDevBchAfcdb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRxInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o) (_L1w_DevRtxRxDsReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_atRfcDcLog)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DrvGetPiAiEnPara)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvLpcModemIntCtrl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_URegLpmTime1CtrlCmd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_g_awL1wRamUtrData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o) (_L1_DrvCsrInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_L1w_DrvSetTop01GdtrHdtrBitSet)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o) (_g_atL1wTpuIntStaticNtPara)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_dRfcSpiReadData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o) (_g_tRegTpuReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_L1w_DrvTxReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o) (_g_atL1wDrvMeasResultInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o) (_g_tRegPsrWinPosCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_g_bL1wHsdschConfigFlg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o) (_g_tL1wEutrParaConf)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvDpramIsEmpty)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o) (_g_tRegTxReg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvRxInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_top.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_wL1wTop00SoftReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_L1w_DrvDtrSetCsServiceFlg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DrvBchReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o) (_g_tRegCsrFpgaVersion)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_L1w_DrvUtrReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_uL1wRegIcSubFrameHead)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_L1w_DrvRfcAbbCsfHpfCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_g_tRegRxRakeChipLvl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o) (_L1w_DrvPsrStartPosCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o) (_g_atBandInfoTX)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o) (_g_tRegMeasBufOffline)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o) (_g_tRegPiAiEnble)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_TxCfgOver)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_SchedMainTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_g_tL1wRachProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_L1w_SchMeasQueryCellInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_tL1wCtrlDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCs1ProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_g_tServCellDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o) (_g_tL1wMeasProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_L1w_SchedHsupaGetUpaSchedDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCmProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_sc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o) (_L1w_SchedCs1SetStrategy)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_g_tL1wResCtrl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wBchProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_amt.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_g_tL1wAmtProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCs0ProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wHspaProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFachProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wPageProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_dch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wDchProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o) (_L1w_SchedHsdpaFachActive)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wGapProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o) (_g_tL1wHsdpaProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o) (_L1w_SchedHspaEraInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFmoProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFSProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o) (_L1w_MathFloatAdd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o) (_L1w_DevHsupaCalcSubFrmBitmap)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o) (_L1w_DevPcHspaReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o) (_L1w_DevTxRaInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRmReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_L1w_DevHsdpaSendPcTtiInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_bL1wHsdpaDmaBusy)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o) (_L1w_DevPcRachReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_g_atL1wHsupaDlCmPattern)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o) (_g_tRegRtxDtrReg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o) (_g_uRegBchTxdMode)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_L1w_DrvDmaReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o) (_L1w_SchedHsdpaPchCfgPSCmd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_g_L1LteAPriTaskPid)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_NVInit)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_etmtlog_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_LTE_TPU_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_ecsi_CSIAThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_edls_PDschIsr)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o) (_wPchUseSibFlag)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_erfc_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_wCNT)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_epbch_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_zPHY_edls_tDlsCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_atCqiCommonInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_t_zPHY_Dls2UlsDciValue)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_ptRxp_Ops)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_t_zPHY_eula_CtrlBlock)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_tL1lLpCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_zPHY_erfc_SupSampleRateSet)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_ZPHY_ecsrm_tMeasState)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o) (_g_zPHY_ecsrm_bHalfFrame)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_UL_CSI_CombThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_Tx2Rx2_NL2_PMICalc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o) (_g_tRxpCirCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_aswOutdata)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_SumLOGNoSqrt_RICalc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o) (_g_tLteA1DlaRxCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_EDFE_SYSTEM_INFO)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eula_Entry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_t_zPHY_DlaCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eula_ProInitial)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_Int_dwDFEIntType_agc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eulpc_GetConfigParas)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (_g_awL1lEngTempBuffer)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o) (_zEasn1p_DcT_zEurrc_PCCH_Message)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_zPHY_edla_PdcchBlindDetectProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_CqiSinglePort_TX1_RX1_NL1)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_g_bIsRarNewTrans)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_ACP405_AFC_DIFF)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_DevDlsDecodeDciF1A)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_gadwCsiRsPosCalculated)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_zPHY_eulpc_PucchPowCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_ac_zPHY_edls_TddSubframeType)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_DrvDdtrResetCfg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o) (_zPHY_DrvTopIntAbleBitSet)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_L1L_TpuDrvReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_g_tzPHY_eulpc_At2UlPc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o) (_g_zPHY_tLpcPwrDomainState)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_eltx_SoftReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_zPHY_ecsrm_MeasHwReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_adw_Drv_Rx_FixFirCoeff_16QAM)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_elutr_SoftReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o) (_L1e_DrvRxMimoReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_L1e_DrvMimoCaRstCfg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_zPHY_erfc_atCurrentSFConfig)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o) (_g_atzPHY_erfc_atRFABBMainSyncEvent)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_zPHY_erfc_cTddOrFddSel)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_cAGCCalMode)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o) (_g_CsrGapInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_erapc_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_g_awAgcNoBalance)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_g_wSibPrintCtrlCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o) (_g_L1e_tDlRfcCfgInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_g_L1e_ConnIntraRptCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_zPHY_emc_ProPhyStateCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_g_zPHY_erapc_tCtrlBlock)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_zPHY_ecsrc_SatAdd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_g_zPHY_ecsrc_tMulmInactiveTimeInd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_g_RxOpenPara)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o) (_EventHandler)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_L1e_SchedMbmsInit)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_g_zPHY_emc_bDrxActvieFlag)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_zPHY_emc_ProRadioLink_SetFIUpdateInd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_gtAmtCellSyncProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_g_sbFixTaAutoAdjFlg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_tHandoverReq)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_g_wPreSyncInterval)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_zPHY_ecscMeas_LogMeasConfigReq)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_LogDlDlsDciDetInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_zPHY_ecsc_LogMibReqCellInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_zPHY_ecsm_LogMeasHwInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o) (_zPHY_ecsccs_LogRSStart)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_L1e_LogDlRxMbsfnCirInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_emulm_LogCsrSlaveStateChange)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o) (_L1e_logCmnMbmsMbsfnSubfListInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_L1e_csrs_LogSetFtErrorList)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o) (_zPHY_ecsm_LogBlackCell)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_zPHY_Float2Fixpoint)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_zPHY_SID)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_L1l_CmnAssert)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_zPHY_eula_PucchSrsRelease)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_adw_zPHY_Rx_NormalSfnTypeValue)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_at_zPHY_NxtHiQuadPosTab)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_wNotSyncAgcIntCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_zPHY_eulpc_SrsPowCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_euls_Entry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_aswTwf)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_g_tzPHY_ecsrs_FSPara)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o) (_zPHY_euls_ReleaseSPSMode)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetPssStartInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_g_ai_zPHY_Tdd_MiTab)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_eula_PuschAckProcess)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o) (_zPHY_eulpc_UlsRelativePuscchPowCtrlProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_wRxLog2Dagc0)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o) (_zEasn1p_per_dcOctStr)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_G_EULPC_RARTPCVAL)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetCfoStartInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_zPHY_edla_PcfichProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetNearValidTime)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o) (_g_atEcsrSearchPeakdatabase)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_ptTi_Ctl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_g_CsrDrvCfgInfor)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1_ref.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (_GainValueConfig_TDD)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o) (_L1e_FS_LogAddSearchResult)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o) (_zPHY_ecsrs_ListAdd)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_s_create_pool)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_create_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o) (_current_process)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o) (_delay)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_free_buf)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_get_pri)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_get_ticks)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_g_pcZcosVersion)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_kill_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_receive)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o) (_s_alloc_nil)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o) (_sender)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_set_pri)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_signal_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_start)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_zcos_sysd_init)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o) (_tick)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_wait_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_odo_hunt_find_name)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_restore)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_send_w_s)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_zDrvEfuse_IsSpe)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(32.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___modhi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___addsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(compare_IEEE.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___lthf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convert.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___floatunshihf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convertqi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___floatqihf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(div.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (___divqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Div.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___divsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(divzi3_v2.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (___divzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(errno.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o) (_ierrno)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ftou.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___ieee754_ftou)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o) (_memcmp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy16.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (___memcpy16)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_memcpy)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memset.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_memset)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mod.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (___modqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(modzi3_v2.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o) (___modzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Mul.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___mulsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pnan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o) (___ieee754_propagate_nan)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_sprintf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strchr.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strchr)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcmp.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_strcmp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcpy.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strcpy)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strlen.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strlen)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Sub.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___subsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udiv.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (___udivqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udivzi3_v2.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___udivzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(umod.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (___umodqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(umodzi3_v2.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___umodzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(vsprintf.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o) (_vsprintf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o) (___adddf3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___fixsfhi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___fixsfhi)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatsisf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o) (___floatsisf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatunsisf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___floatunsisf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___gesf2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___gesf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___gtsf2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o) (___gtsf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___muldf3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_packFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_packFloat64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_addFloat64Sigs.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o) (_staticFunc_addFloat64Sigs)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeFloat64Subnormal.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_normalizeFloat64Subnormal)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeRoundAndPackFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatsisf.o) (_staticFunc_normalizeRoundAndPackFloat64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_propagateFloat64NaN)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_roundAndPackFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_roundAndPackFloat64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_subFloat64Sigs.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o) (_staticFunc_subFloat64Sigs)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___subdf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_(short, bool __restrict, double, float, _v2))
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o) (__vfsprintf_sdsp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrli3.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (___lshrli3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrzi3.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrli3.o) (___lshrzi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mul64To128.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_mul64To128)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(shift64RightJamming.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_addFloat64Sigs.o) (_shift64RightJamming_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_data.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_roundAndPackFloat64.o) (_float_rounding_mode)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_extractFloat64Exp.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___fixsfhi.o) (_extractFloat64Exp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_float64_is_nan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o) (_float64_is_nan)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_float64_is_signaling_nan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o) (_float64_is_signaling_nan)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_countLeadingZeros64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeFloat64Subnormal.o) (_staticFunc_countLeadingZeros64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(atoi.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (_atoi)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ctype.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (___ctype)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (_fputc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fwrite_8bit.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (_fwrite_8bit)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o) (__zsim_fputc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fwrite_8bit.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fwrite_8bit.o) (__zsim_fwrite_8bit)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fflush.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o) (_fflush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pr_routines.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o) (___zsim_fputc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o) (_ZSPgetUserDevice)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fwrite.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fflush.o) (__zsim_fwrite)
+
+Allocating common symbols
+Common symbol size file
+
+_g_awSyncMsgBuff 0x2ee0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_tL1wDevDbHsdpaCfgReqB
+ 0x7c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_zPHY_edfe_wAgcEnEventFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_L1l_LpmCaliIdx 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_ThreadIntraCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_dwOffsetDelta 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_atDevBchAfcdb 0x7a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_dwL1lPreHookEntry
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_g_tTempDCOffsetComp
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_atL1wCellType 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_wLastBand 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+_g_tL1wDevDbUlDpchCfgReqA
+ 0x3d6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_atEcsrSearchPeakdatabase
+ 0xf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_tL1lCallStackInfo
+ 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+_g_eTxCalibrationStep
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+_g_tL1wCmCfnN0123Bitmap
+ 0x5a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_tL1wDevDbHsdpaCfgReqA
+ 0x7c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_awPSeqCellIDDiv30
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_zPHY_erfc_tempDac
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_dL1wDprICPSSFN 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+_g_zPHY_bDdtrWorkFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+_g_wAdrIcCellState 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+_g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+_g_awFHopSeq4SubBands
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_tRfRxOffsetCfgInfo
+ 0x5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_tTTIBundlingDB 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_adL1wTpuTaskID 0x1a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+_g_tLteAmtCellSyncPara
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_edfe_wRxLinDagc1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_tWUpaStdlogStatisitcInfo
+ 0xe T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+_g_tWcdmaUserNv 0xbec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+_g_dwTpcPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_tUEIdInfo 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+_g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_atL1RfSegInfo 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_EUL_SrsStatisticsInfo
+ 0x158 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_awL1wStandardMsgRpt
+ 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+_g_atL1wTpuRegRtVarEventInfo
+ 0x235 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+_g_zPHY_edfe_swAgcMeanPwr1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_swPrintProNoInt 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+_g_tL1wDevMeasInfo 0x3eb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+_g_tTimerCnt 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_zPHY_euls_tTpcCommands
+ 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_zPHY_emc_tCommonConfigReq
+ 0x96 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_CsContext 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_g_tzPHY_ecsrs_FSPara
+ 0xd91 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+_g_wRLMATQInFlg 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_erfc_TempStartRecordFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_awMbmsClusterNum
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+_gL1l_MissLogInfo 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_g_zPHY_ecsrm_wNextIntFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+_g_adw_zPHY_erfc_profile_DB
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+_g_sdRLMATQIn 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_emc_wSIDataBufSel
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_ecsrc_wPiPeriod
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_dwOffsetFlag 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
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+_g_wLayerNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+_g_wSssHwRestartCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_slot0_nRBNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_wCsrs_RX_Sib1_Read_Flag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_tUlReportBlerInfo
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_zPHY_edfe_tRxAgcBalance
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_gtLteRfcRpiPwrCtl 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_tWUpaDlDebugInfo
+ 0x6b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+_g_tHsdpaResetInfo 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+_g_zPHY_ecsrc_swBackupCFOFreqOffset
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_erfc_tpu 0x60 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+_g_tIqMappingCon 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_awCsiRsCheCfgVal
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_tRfcTmpReadInfo 0x5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+_g_w_FirstFlgSet 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_zPHY_AMT_SrvCellRsrp
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_LtePhySleepCnt
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_zPHY_edfe_wAgcDagcGain
+ 0x1f0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_g_L1e_mulm_40msGapCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_l1wATSetAPCFlag 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+_g_zPHY_erfc_RfStateMap
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_PchBlerInfo_2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_EDL_AT_INFO 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_tDchAscPara 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+_g_wTpuNtRegLpcSave
+ 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+_g_FreqScanData 0x86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_zPHY_edfe_tMbsfnAgcInfo
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_TotalPuschNumTB0 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_EUL_wPrachPowerIdx
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_Next2SubFrameDrxActiveSidFlag
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+_g_tL1wCmInfoForN4N9
+ 0xca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_ThreadCfoCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_aiInitSequence 0x200 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+_g_ThreadInterCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_sL1wUlAdujstFlag
+ 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_tWDevDbHspaPlusFachCfgReq
+ 0x544 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_awMaxLayerNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+_g_at_zPHY_erfc_atReloadData
+ 0x40 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+_g_ThreadMulmCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_pSemId_TXIntPulse
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+_g_L1e_ConnIntraRptCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_TmtLogCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_edfe_tMbsfnAgcGain
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_tPcInfoDb 0x146 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_awFHopSeq3SubBands_Scell
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_pSemId_INTH2 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+_g_zPHY_emulm_tMulmIdlePeriodReqFlag
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_tL1wAddionCtrl 0x1a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+_g_PchTiCfgInd_2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_zPHY_emc_tRadioLinkCtrlInfo
+ 0xf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+_g_zPHY_emulm_tMulmAfcPara
+ 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_wRfSegNum 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_dOldUlTiming 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_atRfcOpen 0x3a0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+_g_zPHY_erfc_dwConFr33RefClk
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+_g_tL1wDpaRlReqInfo
+ 0x2f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_awTempMeanPower0
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_eRfcRamState 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+_g_atMeasSpsrInfo 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+_g_t_zPHY_etx_RarUlGrant
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_zPHY_ecsrc_atSlaveMeasInfo
+ 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_emulm_tFilterMeas
+ 0x621 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_emc_tReleaseCtrlParam
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_dwFdt10MsCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_erfc_Meas0SubfDef
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_wCNT 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+_g_zPHY_sdwRxAnt1OffsetValue
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+_gdwTmtFlowCount 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_emc_tReadSib1Req
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_ps2phy_chinfo 0x300 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_tzPHY_eulpc_PowerCtrlParas
+ 0x13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+_g_adwDebug 0xc8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_EUL_PrachStatisticsInfo
+ 0xd9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_dwCalibration_amp
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+_g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_emc_tRaMsgHoldFlag
+ 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_zPHY_edfe_wRxLog2Dagc0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_g_L1l_MrtrAfterSleep
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_gIramHookCnt 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+_g_DbgMibPerStat 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_zPHY_AMT_Frequency
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_Int_dwDFEIntType_agc
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+_g_tRtxPcPrachMessageInfo
+ 0x13 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+_gt_zPHY_Rx_CsiRsExistInd
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_L1e_wSiTimingNeibState
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+_g_atL1wDrvMeasResultInfo
+ 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+_g_tL1wPsCmConfigBuffer
+ 0x7e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_sdAtCtl_ApcOffsetTime
+ 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+_g_wL1lRemainLen 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_gRpMsgReadMutex 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_awL1eRxDrsAccNum
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+_g_zPHY_edfe_wAgcdBGain1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_L1e_tDlRfcCfgInfo
+ 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_L1eTempAdc 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_ecsrc_tMulmIratMeasConfig
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_wCsiWorkFlg 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+_g_L1e_tMibRfcBackUp
+ 0xb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_TpuCfgOver 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+_g_L1e_Csrc_bCellSearchPbch
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_tMprTest 0xcb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_dwUlHarqFailCount
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+INCSRAM 0x00000000 0x00008000
+//OLINCSRAM 0x00000000 0x00000000
+DNCSRAM 0x00010000 0x00007000
+OLDNSCRAM 0x00015400 0x00001c00
+HEAP_STACK 0x00017000 0x00001000
+IRAM 0x41000000 0x00008000
+IRAM1 0x00080800 0x00000600
+DDR 0x10000000 0x00180000
+L2_CODE_TCM_STA 0x30060000 0x00004000
+L2_CODE_TCM_DYN 0x30064000 0x00004000
+L2_DATA_TCM_STA 0x30068000 0x00004000
+L2_DATA_TCM_DYN 0x3006c000 0x00004000
+DMA_REG 0x00980000 0x00001000
+ICP_REG 0x0098101c 0x00000030
+ICP_REG_M0 0x009810f4 0x00000030
+ICU_REG 0x00400800 0x00001000
+UART_REG 0x00a00800 0x00001000
+SLOTBUF_LTE_REG 0x7e010140 0x00000008
+TOP_REG 0x7e080000 0x00000800
+TPU_REG 0x7e080800 0x00001800
+RFC_REG 0x7e082000 0x00002800
+//DFE_RX_REG 0x7e084000 0x00000400
+//DFE_TX_REG 0x7e084400 0x00000400
+CSR_REG 0x7e084800 0x00000a00
+MEAS_REG 0x7e085200 0x00000e00
+CSR_FULLSCAN_REG 0x7e086000 0x00000200
+BCH_REG 0x7e086200 0x00000600
+PSR_REG 0x7e086800 0x00000100
+TX_REG 0x7e087000 0x00000200
+UTR_REG 0x7e087600 0x00000200
+EUTR_REG 0x7e087c00 0x00000400
+//RAKE_REG 0x7e088000 0x00000000
+RX_REG1 0x7e088000 0x00000800
+RX_REG2 0x7e088800 0x00000800
+RX_REG3 0x7e089000 0x00000800
+RX_REG4 0x7e089800 0x00000800
+GDTR_REG 0x7e08a000 0x00002000
+EAGCH_REG 0x7e08c000 0x00000400
+ADR_REG 0x7e08c400 0x00000200
+IC_REG 0x7e08c600 0x00001a00
+HDTR_REG 0x7e08e000 0x00000400
+HSSCCH_REG 0x7e08e400 0x00000400
+PICH_REG 0x7e08e800 0x00000200
+SLOTBUF_REG 0x7e08f000 0x00000200
+HDTR_LESS_REG 0x7e08f400 0x00000c00
+CSR_RAM 0x7c080000 0x00000400
+MEAS_RAM 0x7c080400 0x00000200
+BCH_RAM 0x7c080600 0x00007a00
+PSR_DATA_RAM 0x7c088000 0x00000400
+TX_RAM0 0x7c08e000 0x00002000
+TX_RAM1 0x7c090000 0x00002000
+UTR_RAM 0x7c092000 0x00004000
+EUTR_RAM 0x7c096000 0x00002000
+RX_RAM1 0x7c09a000 0x00000140
+RX_RAM2 0x7c09a140 0x00000040
+RX_RAM3 0x7c09a180 0x00000040
+RX_RAM4 0x7c09a1c0 0x00000100
+RX_RAM5 0x7c09a240 0x000005c0
+RX_RAM6 0x7c09a800 0x00000400
+RX_RAM7 0x7c09ac00 0x00000020
+RX_RAM8 0x7c09ac20 0x000013e0
+RX_RAM9 0x7c09c000 0x00000800
+RX_RAM10 0x7c09c800 0x00001000
+RX_RAM15 0x7c09d800 0x00000100
+RX_RAM16 0x7c09d900 0x00000300
+RX_RAM17 0x7c09dc00 0x00000040
+RX_RAM18 0x7c09dc40 0x00000040
+RX_RAM19 0x7c09dc80 0x00000040
+RX_RAM20 0x7c09dcc0 0x00000040
+RX_RAM21 0x7c09dd00 0x00000040
+RX_RAM22 0x7c09dd40 0x00000040
+RX_RAM23 0x7c09dd80 0x00000040
+RX_RAM24 0x7c09ddc0 0x00000140
+RX_RAM25 0x7c09df00 0x00000020
+RX_RAM26 0x7c09df20 0x000020e0
+GDTR_RAM 0x7c0a0000 0x00000400
+ADR_RAM 0x7c0b0000 0x00010000
+HDTR_RAM 0x7c0c0000 0x00008000
+PIAI_RAM 0x7c0c8000 0x00000100
+SLOTBUF_RAM 0x7c0e0000 0x00008000
+SLEEP_REG 0x0009a300 0x00000040
+RFFE_REG 0x7c250000 0x00000208
+SPI_REG 0x7c250208 0x00000010
+TD_TOP_REG 0x7e100000 0x00000080
+TD_TPU_REG 0x7e100400 0x00000040
+TD_AFC_REG 0x7e100800 0x00000400
+TD_CSR_REG 0x7e100c00 0x00000400
+TD_DST_REG 0x7e101000 0x00000080
+TD_RX_REG 0x7e101400 0x00000200
+TD_GDTR_REG 0x7e101800 0x00000100
+TD_HDTR_REG 0x7e101c00 0x00000040
+TD_UTR_REG 0x7e102000 0x00000079
+TD_ULC_REG 0x7e102079 0x00000187
+TD_HSUPA_REG 0x7e102200 0x00000080
+TD_DM_RDB_REG 0x7e103000 0x00000010
+TD_RFC_REG 0x7e104000 0x00005000
+TD_TFCI_REG 0x7e103400 0x00000020
+TD_SLEEP_REG 0x0009a200 0x00000080
+TD_PSLPM_REG 0x0009a280 0x00000080
+TD_VITERBI_REG 0x7e103400 0x00000020
+TD_CSR_DPRAM_MEM 0x7c100400 0x00000800
+TD_DST_DPRAM_MEM 0x7c104000 0x00000400
+TD_DST_DPRAM_INTERF_MEM 0x7c104800 0x00000400
+TD_UL_DPRAM_MEM 0x7c108000 0x00000400
+TD_HSUPA_MEM 0x7c10a000 0x00002000
+TD_RX_DPRAM_MEM2 0x7c10c000 0x00001000
+TD_GDTR_DPRAM_MEM 0x7c114000 0x00004000
+//TD_GDTR_DPRAM_TEST_MEM 0x7c118000 0x00004000
+TD_HDTR_DPRAM_MEM 0x7c11c000 0x00004400
+DST_SLOT_BUF 0x7c122000 0x00008000
+*default* 0x00000000 0xffffffff
+RAKE_REG 0x00000000 0xffffffff
+
+Linker script and memory map
+
+START GROUP
+LOAD T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a
+LOAD T:/cp/phy/rtos/zcos/os_krn/libczspfft.a
+LOAD T:/cp/phy/rtos/zcos/os_krn/libzspcache.a
+LOAD T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a
+LOAD T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libm.a
+LOAD T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a
+LOAD T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a
+LOAD /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+END GROUP
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a
+ 0x10000000 . = 0x10000000
+
+.text 0x10000000 0xa7b05
+ 0x10000000 _stext = .
+ *(.ddr_vectors)
+ .ddr_vectors 0x10000000 0x8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ *(.text)
+ .text 0x10000008 0x83 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ 0x10000008 0x80 __start
+ 0x10000088 0x3 __finished
+ .text 0x1000008b 0xe3 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ 0x1000008b 0x2e _L1_DrvIcuIntStart
+ 0x100000b9 0x1b _L1_DrvIcuIntMask
+ 0x100000d4 0x1a _L1_DrvIcuIntUnMask
+ 0x100000ee 0x27 _ICU_ISR
+ 0x10000115 0x2 _L1_DrvIcuError
+ 0x10000117 0x57 _L1_DrvIcuInit
+ .text 0x1000016e 0xbe T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ 0x1000016e 0x5 _L1_DrvIntInit
+ 0x10000173 0x5 _L1_DrvIntMaskAll
+ 0x10000178 0x27 _L1_DrvIntMask
+ 0x1000019f 0x26 _L1_DrvIntUnMask
+ 0x100001c5 0x67 _L1_DrvInstallIsr
+ .text 0x1000022c 0x19a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ 0x1000022c 0xc8 _odo_create_process
+ 0x100002f4 0x72 _s_create_process
+ 0x10000366 0x60 _create_process
+ .text 0x100003c6 0x8d T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x100003c6 0x54 _odo_error
+ 0x1000041a 0x5 _error
+ 0x1000041f 0x5 _error2
+ 0x10000424 0x20 _odo_panic
+ 0x10000444 0x3 _odo_panic2
+ 0x10000447 0x9 _odo_panic_nonfatal
+ 0x10000450 0x3 _odo_panic_nonfatal2
+ .text 0x10000453 0x179 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x10000453 0x31 _creat_pcb
+ 0x10000484 0x8e _odo_init_os_stage2
+ 0x10000512 0x4d _creat_idlepcb
+ 0x1000055f 0x6d _odo_init_os
+ .text 0x100005cc 0xc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ 0x100005cc 0xc _main
+ .text 0x100005d8 0xf7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ 0x100005d8 0x21 _odo_process_entry
+ 0x100005f9 0x3f _odo_alloc_pcb
+ 0x10000638 0x20 _odo_init_process
+ 0x10000658 0x77 _odo_init_pcb
+ .text 0x100006cf 0xa4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ 0x100006cf 0xa4 _send
+ .text 0x10000773 0x26 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ 0x10000773 0x26 _start_zcos
+ .text 0x10000799 0xee T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ 0x10000799 0x1e _odo_go_search
+ 0x100007b7 0x6b _odo_do_swap
+ 0x10000822 0x2d _odo_wait
+ 0x1000084f 0x38 _odo_swap_if_necessary
+ .text 0x10000887 0x90 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ 0x10000887 0x90 _alloc
+ .text 0x10000917 0x94 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ 0x10000917 0x1b _update_mask_list
+ 0x10000932 0x8 _odo_arch_init_interrupts
+ 0x1000093a 0x5c _odo_arch_create_osint
+ 0x10000996 0x15 _odo_arch_init
+ .text 0x100009ab 0x16 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ 0x100009ab 0x16 _ZSP_DCacheUseDCFGRDescribe
+ .text 0x100009c1 0xa T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o)
+ 0x100009c1 0xa _ZSP_DCacheEnableNCSRAM
+ .text 0x100009cb 0x104 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x100009cb 0x5b _odo_config_init_pools
+ 0x10000a26 0x44 _odo_config_start_handler1
+ 0x10000a6a 0x65 _odo_config_start_handler2
+ .text 0x10000acf 0x23 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ 0x10000acf 0x5 _L1_TIMER0_ISR
+ 0x10000ad4 0x1e _L1_SysIdleTask
+ .text 0x10000af2 0x6e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ 0x10000af2 0x1b _BspTimerInit1
+ 0x10000b0d 0xd _BspTimerInit2
+ 0x10000b1a 0x1b _BspTimerGet
+ 0x10000b35 0x1c _BspTimerCallbackReg
+ 0x10000b51 0xf _Timer0_ISR
+ .text 0x10000b60 0xf5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ 0x10000b60 0x4d _L1_DrvTimer
+ 0x10000bad 0x6 _L1_DrvTimerStop
+ 0x10000bb3 0x42 _L1_DrvPhyTimer1Init
+ 0x10000bf5 0x1e _L1_DrvSwDelay
+ 0x10000c13 0x6 _L1_DrvGetTimeCnt
+ 0x10000c19 0x10 _L1_DrvCalcTimeElapse
+ 0x10000c29 0x10 _L1_DrvTimer0Init
+ 0x10000c39 0xf _L1_DrvTimer1Init
+ 0x10000c48 0x6 _TIMER0_INT
+ 0x10000c4e 0x7 _TIMER1_INT
+ .text 0x10000c55 0x2cc T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x10000c55 0x1a _L1_SysSendRamDumpIcp
+ 0x10000c6f 0x1e9 _ramdump_client_cmm_create_sde
+ 0x10000e58 0x36 _L1_SysErrHnd
+ 0x10000e8e 0x42 _RAMDUMP_ICP_ISR
+ 0x10000ed0 0x33 _L1_AllocHookDebug
+ 0x10000f03 0x1e _L1_FreeHookDebug
+ .text 0x10000f21 0x1ed T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x10000f21 0x90 _LoadStaticIDNCSRAM
+ 0x10000fb1 0xd _CpyDdrBetweenL2Tcm
+ 0x10000fbe 0x6c _FirstLoadL2Tcm
+ 0x1000102a 0x1 _DynamicLoadL2CodeTcm
+ 0x1000102b 0x4f _CopyBackL2TcmData
+ 0x1000107a 0x94 _UpdateL2TcmDynamic
+ .text 0x1000110e 0x215 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ 0x1000110e 0x105 _L1_InitMacro
+ 0x10001213 0x110 _L1_SysEntry
+ .text 0x10001323 0x63 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x10001323 0x1a __ASSERT
+ 0x1000133d 0x35 __AllocMsg
+ 0x10001372 0xb _ZSP_DelayChip
+ 0x1000137d 0x7 _ZSP_delay_clock
+ 0x10001384 0x2 _erfc_tpu_state
+ .text 0x10001386 0x132f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x10001386 0x11 _phy_memcpy
+ 0x10001397 0x1 _TD_WD_L1_Init
+ 0x10001398 0x22 _L1_RfcSscConfig
+ 0x100013ba 0xa _L1_RfcSscClkEnDisable
+ 0x100013c4 0x59 _L1_RfcSpiWriteSleep
+ 0x1000141d 0x59 _L1_RfcAbbSpiWriteSleep
+ 0x10001476 0x8 _L1_RfcGetSpiRdDataSleep
+ 0x1000147e 0x10 _L1_RfcMipiRffeWrite
+ 0x1000148e 0x44 _L1_RfcMipiInit
+ 0x100014d2 0x16 _L1_RfcDcxoTempDacInit
+ 0x100014e8 0x1b _L1_RfcDcxoTempDacBSearch
+ 0x10001503 0x36 _L1_RfcDcxoGetTempFromDac
+ 0x10001539 0x30 _L1_RfcDcxoGetTempDegree
+ 0x10001569 0x1a _L1_Rf220TxOff
+ 0x10001583 0x1a _L1_Rf220TxOn
+ 0x1000159d 0x12 _L1_Rf220A1IsoOn
+ 0x100015af 0x12 _L1_Rf220A1IsoOff
+ 0x100015c1 0x17 _L1_Abb128TxOff
+ 0x100015d8 0x18 _L1_Abb128TxOn
+ 0x100015f0 0x1 _L1_Rf220GsmWakeUpOn
+ 0x100015f1 0x1 _L1_Rf220GsmWakeUpOff
+ 0x100015f2 0x8 _L1_Abb128WakeUpOff
+ 0x100015fa 0x9 _L1_Abb128WakeUpOn
+ 0x10001603 0x12 _L1_Abb128ResetOff
+ 0x10001615 0x30 _L1_Abb128ResetOn
+ 0x10001645 0x8 _L1_AbbIsoEnOff
+ 0x1000164d 0x9 _L1_AbbIsoEnOn
+ 0x10001656 0x1b9 _L1_Abb128DRXFilterCnfLTE20
+ 0x1000180f 0x1b4 _L1_Abb128DRXFilterCnfLTE15
+ 0x100019c3 0x1b4 _L1_Abb128DRXFilterCnfLTE10
+ 0x10001b77 0x1b4 _L1_Abb128DRXFilterCnfLTE5
+ 0x10001d2b 0x1c2 _L1_Abb128DRXFilterCnfLTE3
+ 0x10001eed 0x1a2 _L1_Abb128DRXFilterCnfLTE1_4
+ 0x1000208f 0x197 _L1_Abb128DRXFilterCnfWcdma
+ 0x10002226 0x1ad _L1_Abb128DRXFilterCnfTdscdma
+ 0x100023d3 0xac _L1_Abb128DRXFilterCnfHpf
+ 0x1000247f 0x20 _L1_RfGpioPinMuxReCfg
+ 0x1000249f 0x8 _L1_Rfc_IratShare_Lock
+ 0x100024a7 0xa _L1_Rfc_IratShare_UnLock
+ 0x100024b1 0x13 _L1_AbbClkEnCtrl
+ 0x100024c4 0xbc _L1_RfcIdleToSleepForLp
+ 0x10002580 0x135 _L1_RfcSleepToIdleForLp
+ .text 0x100026b5 0xa0 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x100026b5 0x75 _w_assert
+ 0x1000272a 0x15 _delay_ms
+ 0x1000273f 0x16 _delay_10us
+ .text 0x10002755 0x9cb T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x10002755 0x25 _L1_InitComAtNv
+ 0x1000277a 0x79 _L1_MmcPrioLteReset
+ 0x100027f3 0x74 _L1_MmcPrioLteMaster
+ 0x10002867 0x79 _L1_MmcPrioLteSlave
+ 0x100028e0 0x5 _L1_MmcPrioLteSlaveInFsPostPro
+ 0x100028e5 0x5 _L1_MmcPrioLteSlaveOutFsPostPro
+ 0x100028ea 0x17 _L1_MmcPrioLteEIcp
+ 0x10002901 0x17 _L1_MmcPrioLteEIcpRestore
+ 0x10002918 0x5 _L1_MmcPrioLteSleep
+ 0x1000291d 0x5 _L1_MmcPrioLteWakeup
+ 0x10002922 0x49 _L1_MmcPrioWReset
+ 0x1000296b 0x49 _L1_MmcPrioWMaster
+ 0x100029b4 0x49 _L1_MmcPrioWSlave
+ 0x100029fd 0x5 _L1_MmcPrioWSleep
+ 0x10002a02 0x5 _L1_MmcPrioWWakeup
+ 0x10002a07 0x7 _L1_MmcSetResetPrio
+ 0x10002a0e 0x2f _L1_MmcGetLteStamp
+ 0x10002a3d 0x34 _L1_MmcGetWStamp
+ 0x10002a71 0x34 _L1_MmcGetTdsStamp
+ 0x10002aa5 0x39 _L1_MmcGetGsmStamp
+ 0x10002ade 0x20 _L1_MmcTimeTransLte2Ms
+ 0x10002afe 0x2b _L1_MmcTimeTransW2Ms
+ 0x10002b29 0x2a _L1_MmcTimeTransTds2Ms
+ 0x10002b53 0x28 _L1_MmcTimeTransGsm2Ms
+ 0x10002b7b 0x1d _L1_MmcTimeTransMs2Lte
+ 0x10002b98 0x20 _L1_MmcTimeTransMs2W
+ 0x10002bb8 0x1f _L1_MmcTimeTransMs2Tds
+ 0x10002bd7 0x32 _L1_MmcTimeTransMs2Gsm
+ 0x10002c09 0x17 _L1_MmcTimeTransLte2W
+ 0x10002c20 0x17 _L1_MmcTimeTransLte2Tds
+ 0x10002c37 0x17 _L1_MmcTimeTransLte2Gsm
+ 0x10002c4e 0x17 _L1_MmcTimeTransW2Lte
+ 0x10002c65 0x17 _L1_MmcTimeTransW2Gsm
+ 0x10002c7c 0x17 _L1_MmcTimeTransTds2Lte
+ 0x10002c93 0x17 _L1_MmcTimeTransTds2Gsm
+ 0x10002caa 0x17 _L1_MmcTimeTransGsm2Lte
+ 0x10002cc1 0x17 _L1_MmcTimeTransGsm2W
+ 0x10002cd8 0x17 _L1_MmcTimeTransGsm2Tds
+ 0x10002cef 0x4e _L1_MmcPosTransLte2Gsm
+ 0x10002d3d 0x49 _L1_MmcPosTransGsm2Lte
+ 0x10002d86 0x47 _L1_MmcPosTransW2Gsm
+ 0x10002dcd 0x38 _L1_MmcPosTransGsm2W
+ 0x10002e05 0x47 _L1_MmcPosTransTds2Gsm
+ 0x10002e4c 0x31 _L1_MmcPosTransGsm2Tds
+ 0x10002e7d 0x34 _L1_MmcLteTimePlus
+ 0x10002eb1 0x27 _L1_MmcWTimePlus
+ 0x10002ed8 0x27 _L1_MmcTdsTimePlus
+ 0x10002eff 0x33 _L1_MmcGsmTimePlus
+ 0x10002f32 0x6e _L1_MmcLteTimeMinus
+ 0x10002fa0 0x5c _L1_MmcWTimeMinus
+ 0x10002ffc 0x53 _L1_MmcTdsTimeMinus
+ 0x1000304f 0xa3 _L1_MmcGsmTimeMinus
+ 0x100030f2 0x2e _L1_MMcGsmPosMove
+ .text 0x10003120 0x24b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ 0x10003120 0x25 _L1_DrvL2CachePrefetchCfg
+ 0x10003145 0xa _L1_DrvL2CachePowerModeCfg
+ 0x1000314f 0x41 _L1_DrvL2CacheGetInfo
+ 0x10003190 0x4d _L1_DrvL2CacheEnable
+ 0x100031dd 0x18 _L1_DrvL2CacheDisable
+ 0x100031f5 0x11 _L1_DrvL2CacheSync
+ 0x10003206 0x27 _L1_DrvL2CacheClean
+ 0x1000322d 0x27 _L1_DrvL2CacheInv
+ 0x10003254 0x27 _L1_DrvL2CacheCleanInv
+ 0x1000327b 0x1d _L1_DrvL2CacheCleanByWay
+ 0x10003298 0x1d _L1_DrvL2CacheInvByWay
+ 0x100032b5 0x1d _L1_DrvL2CacheCleanInvByWay
+ 0x100032d2 0xd _L1_DrvL2CacheIntEnable
+ 0x100032df 0xe _L1_DrvL2CacheIntDisable
+ 0x100032ed 0xa _L1_DrvL2CacheGetMaskIntStatus
+ 0x100032f7 0xa _L1_DrvL2CacheClearIntStatus
+ 0x10003301 0x1e _L1_DrvL2CacheCfgEventCounter
+ 0x1000331f 0xa _L1_DrvL2CacheEventCounterEnable
+ 0x10003329 0x9 _L1_DrvL2CacheEventCounterDisable
+ 0x10003332 0x13 _L1_DrvL2CacheGetEventCounterVal
+ 0x10003345 0x1a _L1_DrvL2CacheTcmEnable
+ 0x1000335f 0xc _L1_DrvL2CacheTcmDisable
+ .text 0x1000336b 0x98 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ 0x1000336b 0x1b _L1_DrvCacheDisable
+ 0x10003386 0x3b _L1_DrvCacheEnable
+ 0x100033c1 0x24 _L1_DrvCacheWb
+ 0x100033e5 0x1e _L1_DrvCacheWbAll
+ .text 0x10003403 0x179 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ 0x10003403 0xb _L1_DrvDmaReset
+ 0x1000340e 0x15 _L1_DrvDmaCfg
+ 0x10003423 0x41 _L1_DrvDmaClear
+ 0x10003464 0x2 _L1_DrvDmaError
+ 0x10003466 0x41 _L1_DrvDmaInit
+ 0x100034a7 0x21 _L1_DrvDmaStart
+ 0x100034c8 0x26 _L1_DrvDmaIsr
+ 0x100034ee 0x4e _L1_DrvDmaCfgChParam
+ 0x1000353c 0x33 _L1_DrvDmaCfgLLI
+ 0x1000356f 0xd _L1_DrvDmaTcEnd
+ .text 0x1000357c 0x101a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x1000357c 0x1 _RPMSG_ERR
+ 0x1000357d 0x3e _rpMsg_MaskInt
+ 0x100035bb 0x40 _rpMsg_UnmaskInt
+ 0x100035fb 0x39 _rpMsg_GetIntState
+ 0x10003634 0x38 _rpMsg_ClearState
+ 0x1000366c 0xd2 _rpMsg_SetInt
+ 0x1000373e 0x184 _rpMsg_DispatchMsg
+ 0x100038c2 0xcc _zDrvRpMsg_CreateChannel
+ 0x1000398e 0x32 _zDrvRpMsg_RegCallBack
+ 0x100039c0 0xfa _zDrvRpMsg_Write
+ 0x10003aba 0x107 _zDrvRpMsg_WriteWithId
+ 0x10003bc1 0xd7 _zDrvRpMsg_WriteLockIrq
+ 0x10003c98 0x146 _zDrvRpMsg_Read
+ 0x10003dde 0x146 _zDrvRpMsg_ReadWithId
+ 0x10003f24 0xe1 _zDrvRpMsg_ReadWithIdLockIrq
+ 0x10004005 0xd8 _zDrvRpMsg_ReadLockIrq
+ 0x100040dd 0x23 _zDrvRpMsg_ChIsEmpty
+ 0x10004100 0x23 _zDrvRpMsg_WriteChIsEmpty
+ 0x10004123 0xd4 _zDrvRpMsg_CreateBlock
+ 0x100041f7 0xe _zDrvRpMsg_GetWriteAddrCnt
+ 0x10004205 0xa2 _zDrvRpMsg_GetWriteAddr
+ 0x100042a7 0xc8 _zDrvRpMsg_WriteUpdate
+ 0x1000436f 0xc4 _zDrvRpMsg_GetReadAddr
+ 0x10004433 0xbf _zDrvRpMsg_ReadUpdate
+ 0x100044f2 0xa4 _zDrvRpMsg_Initiate
+ .text 0x10004596 0x96 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ 0x10004596 0x1 _L1_Comm_SocTopInit
+ 0x10004597 0x1 _delay_1us
+ 0x10004598 0x26 _L1_LpmLatchInit
+ 0x100045be 0x8 _L1_RmHarqRamWcdmaCfg
+ 0x100045c6 0x8 _L1_RmHarqRamTdCfg
+ 0x100045ce 0x9 _L1_RmHarqRam3GRel
+ 0x100045d7 0x9 _L1e_RmHarqRamLteModeClkSelCfg
+ 0x100045e0 0xd _L1_TurboModeSel
+ 0x100045ed 0x1f _L1_WdTdIpSel
+ 0x1000460c 0x1f _L1_WdTdShareRamModeSel
+ 0x1000462b 0x1 _L1_PhyLteModemSel
+ .text 0x1000462c 0x878 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x1000464a 0x6e _L1_AtCmdCtrlLpcFuncs
+ 0x100046b8 0x2c _L1_InitSleepMacro
+ 0x100046e4 0x18 _L1_PhyModeExistInit
+ 0x100046fc 0x46 _L1_SocNoPsmInit
+ 0x10004742 0x14b _L1_SocLpcInit
+ 0x1000488d 0x71 _L1_PcuLpmCalibrationCfg
+ 0x100048fe 0x9 _L1_SocGetApCpuFreq
+ 0x10004907 0x9 _L1_SocGetPsCpuFreq
+ 0x10004910 0x10 _L1_SocGetCurCpuFreq
+ 0x10004920 0x10 _L1_SocGetCurAxiFreq
+ 0x10004930 0x2 _L1_SocGetCurDdrFreq
+ 0x10004932 0x2 _L1_SocDdrDfs
+ 0x10004934 0x17 _L1_SocResCpuExpUpdate
+ 0x1000494b 0x18 _L1_SocResAxiExpUpdate
+ 0x10004963 0x18 _L1_SocResVolExpUpdate
+ 0x1000497b 0x18 _L1_SocResDdrExpUpdate
+ 0x10004993 0x4e _L1_SocResGetExpCurrent
+ 0x100049e1 0xec _L1_SocAdjust
+ 0x10004acd 0x3d7 _L1_LpcTask
+ .text 0x10004ea4 0x20c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x10004ea4 0x10 _L1_LpcDrvChangeCpuPhyFreq
+ 0x10004eb4 0x12 _L1_SetPhyDeepSleepTime2Pcu
+ 0x10004ec6 0x1 _L1_DrvPcu2TpuClkCfg
+ 0x10004ec7 0x1 _L1_DrvPcuCalibrationCfg
+ 0x10004ec8 0x8 _L1_TdlpmClkEn
+ 0x10004ed0 0xa _L1_PhyAxiClkEn
+ 0x10004eda 0x4b _L1_RmModClkEn1
+ 0x10004f25 0x1 _L1_MatrixAxiAutoEn
+ 0x10004f26 0x3d _L1_CpuPhyWakeIntClear
+ 0x10004f63 0x1 _L1_DrvLpcIram1PhyInit
+ 0x10004f64 0x50 _L1_DrvLpcIramFlgInit
+ 0x10004fb4 0x8 _L1_SetPhyDeepSleepFlag
+ 0x10004fbc 0x13 _L1_L2CacheConfigLpMode
+ 0x10004fcf 0x9 _L1_PcuPhyPoweroffIntStart
+ 0x10004fd8 0x9 _L1_CrmSetZspAxiClkEn
+ 0x10004fe1 0x1 _L1_CopyRestartData
+ 0x10004fe2 0x1 _L1_PhyLowPowerInit
+ 0x10004fe3 0x8 _L1_DrvLpcRegLock
+ 0x10004feb 0xa _L1_DrvLpcRegUnLock
+ 0x10004ff5 0x8 _L1_DrvLpcSoftHwLock
+ 0x10004ffd 0xc _L1_DrvLpcSoftHwUnLock
+ 0x10005009 0x4e _L1_DrvLpcSpinSoftLockPsm
+ 0x10005057 0x4a _L1_DrvLpcSpinSoftUnlockPsm
+ 0x100050a1 0xf _L1_DrvLpcSpinSoftlockInit
+ .text 0x100050b0 0x2a4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x100050b2 0x37 _L1_IratSetMode
+ 0x100050e9 0x14 _L1_IratGetMode
+ 0x100050fd 0x13 _L1_IratRfProPcuShareDevInit
+ 0x10005110 0x11 _L1_IratRfProPcuShareDev
+ 0x10005121 0x1f _L1_IratRfIdleToSleep
+ 0x10005140 0x1d _L1_IratRfSleepToIdle
+ 0x1000515d 0x14 _L1_IratRfCfgFlgSet
+ 0x10005171 0x13 _L1_IratIsTdRfCfgNeed
+ 0x10005184 0x13 _L1_IratIsWdRfCfgNeed
+ 0x10005197 0x5b _L1_IratSetSlaveShortGapFlg
+ 0x100051f2 0xd _L1_IratSetGapRptIramFlg
+ 0x100051ff 0xf _L1_IratIsSharePwr
+ 0x1000520e 0x3a _L1_IratPwrCtrl
+ 0x10005248 0x5d _L1_IratLpcInit
+ 0x100052a5 0x2e _L1_IratLpcSleep
+ 0x100052d3 0xc _L1_IratLpcWakeup
+ 0x100052df 0x2b _L1_IratLpcSetCalibrationFlag
+ 0x1000530a 0x1d _L1_IratLpcGetCalibrationFlag
+ 0x10005327 0x18 _L1_IratLpcSetCalibrationTime
+ 0x1000533f 0x15 _L1_IratLpcGetCalibrationTime
+ .text 0x10005354 0x466 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x10005354 0x1 _L1_SysModClkSelInit
+ 0x10005355 0x10 _L1_PhyTimerClkDis
+ 0x10005365 0x11 _L1_Dma1ClkEn
+ 0x10005376 0x65 _L1_MatrixModemClkEn
+ 0x100053db 0xa _L1_DrvPhyCoreAcsCfg
+ 0x100053e5 0x1 _L1_DrvPwrTopRegCtrl
+ 0x100053e6 0x12 _L1_DrvPwrDomainIsOn
+ 0x100053f8 0x61 _L1_DrvPwrCtrl
+ 0x10005459 0x30 _L1_DrvLtePwr1Ctrl
+ 0x10005489 0x4 _L1_Drv3GSyncPwrCtrl
+ 0x1000548d 0x4 _L1_Drv3GDpaPwrCtrl
+ 0x10005491 0x1b _L1_DrvDpll245mClkCtrl
+ 0x100054ac 0x67 _L1_Dpll1Cfg
+ 0x10005513 0x74 _L1_Dpll2Cfg
+ 0x10005587 0x3c _L1_DpllCfg
+ 0x100055c3 0xad _L1_CpuPhyWakeIntInit
+ 0x10005670 0x2e _L1_PcuConfigPhyLpMode
+ 0x1000569e 0x19 _L1_PhyMgClkGating
+ 0x100056b7 0xd _L1_CpuPhyLpSvtAddr
+ 0x100056c4 0x36 _L1_DrvSetSharePwrUsedFlg
+ 0x100056fa 0x19 _L1_DrvGetSharePwrIsUsed
+ 0x10005713 0x18 _L1_DrvPhyComPwrUsedFlgInit
+ 0x1000572b 0x45 _L1_DrvSharePwrCtrl
+ 0x10005770 0x3f _L1_DrvLpcPwrCtrl
+ 0x100057af 0xb _L1_DrvLpcDdrPort1Ctrl
+ .text 0x100057ba 0x34f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ 0x100057ba 0x40 _L1_PhyDmaCfg
+ 0x100057fa 0xa _L1_SaveMgCrm
+ 0x10005804 0xa _L1_RestoreMgCrm
+ 0x1000580e 0xa _L1_SaveL2tcmByDma
+ 0x10005818 0xa _L1_RestoreL2tcmByDma
+ 0x10005822 0x33 _L1_SaveIcu
+ 0x10005855 0x33 _L1_RestoreIcu
+ 0x10005888 0x6 _L1_SaveInt
+ 0x1000588e 0x8 _L1_RestoreInt
+ 0x10005896 0x3 _L1_SaveSmodeReg
+ 0x10005899 0x3 _L1_RestoreSmodeReg
+ 0x1000589c 0x7d _L1_SavePl310
+ 0x10005919 0x87 _L1_RestorePl310
+ 0x100059a0 0x9f _L1_PhyPowerOffSaveContext
+ 0x10005a3f 0xca _L1_PhyPowerOffRestoreContext
+ .text 0x10005b09 0xf5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ 0x10005b09 0x25 _L1_DrvWDTFeedDog
+ 0x10005b2e 0x4c _L1_DrvWDTInit
+ 0x10005b7a 0x50 _L1_DrvM02PhyIcpIsr
+ 0x10005bca 0x34 _L1_WdtTask
+ .text 0x10005bfe 0x66 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ 0x10005bfe 0x1a _serial_puts
+ 0x10005c18 0x4c _printk
+ .text 0x10005c64 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ 0x10005c6a 0x14 _iomemcpy_32
+ .text 0x10005c7e 0x2a1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ 0x10005c7e 0x81 _L1_DrvL1CacheInit
+ 0x10005cff 0x46 _ZSP_DCacheSetExtraNonCacheableRegion_Ext
+ 0x10005d45 0x1b _ZSP_DCacheExtraNonCacheableEnable_Ext
+ 0x10005d60 0x1b _ZSP_DCacheExtraNonCacheableDisable_Ext
+ 0x10005d7b 0x35 _ZSP_DCacheExtraBufferableAndNonCacheableEnable_Ext
+ 0x10005db0 0x35 _ZSP_DCacheExtraBufferableAndNonCacheableDisable_Ext
+ 0x10005de5 0x13 _L1Cache_set_ramclk_gate
+ 0x10005df8 0xd _L1Cache_set_superfetch
+ 0x10005e05 0x15 _L1_DrvL1CacheEnableI
+ 0x10005e1a 0x15 _L1_DrvL1CacheEnableD
+ 0x10005e2f 0x8 _L1_DrvL1CacheEnable
+ 0x10005e37 0xf _L1_DrvL1CacheDisableI
+ 0x10005e46 0x26 _L1_DrvL1CacheDisableD
+ 0x10005e6c 0x8 _L1_DrvL1CacheDisable
+ 0x10005e74 0x21 _L1_DrvL1CacheCleanD
+ 0x10005e95 0x21 _L1_DrvL1CacheFlushD
+ 0x10005eb6 0x21 _L1_DrvL1CacheFlushI
+ 0x10005ed7 0x2d _L1_DrvL1CacheFlush
+ 0x10005f04 0x1b _L1_DrvL1CacheSetWT
+ .text 0x10005f1f 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ 0x10005f1f 0x17 _ZSP_ICacheDisableAllWays
+ .text 0x10005f36 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ 0x10005f36 0x17 _ZSP_ICacheEnable
+ .text 0x10005f4d 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ 0x10005f4d 0x16 _ZSP_ICacheEnableAllWays
+ .text 0x10005f63 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ 0x10005f63 0x25 _ZSP_ICacheFlush
+ .text 0x10005f88 0x36 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ 0x10005f88 0x36 _ZSP_ICacheLoadNCSRAM
+ .text 0x10005fbe 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ 0x10005fbe 0x16 _ZSP_ICacheUseICFGRDescribe
+ .text 0x10005fd4 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ 0x10005fd4 0x12 _ZSP_ICacheNonCacheableDisable
+ .text 0x10005fe6 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ 0x10005fe6 0x17 _ZSP_DCacheDisableAllWays
+ .text 0x10005ffd 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ 0x10005ffd 0x16 _ZSP_DCacheEnableAllWays
+ .text 0x10006013 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ 0x10006013 0x25 _ZSP_DCacheFlush
+ .text 0x10006038 0x22 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ 0x10006038 0x22 _ZSP_DCacheLoadNCSRAM
+ .text 0x1000605a 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ 0x1000605a 0x25 _ZSP_DCacheClean
+ .text 0x1000607f 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ 0x1000607f 0x15 _ZSP_DCacheSetWriteThruRegion
+ .text 0x10006094 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ 0x10006094 0x12 _ZSP_DCacheWriteAllocateEnable
+ .text 0x100060a6 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ 0x100060a6 0x12 _ZSP_DCacheWriteThruEnable
+ .text 0x100060b8 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ 0x100060b8 0x12 _ZSP_DCacheWriteThruDisable
+ .text 0x100060ca 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ 0x100060ca 0x12 _ZSP_DCacheNonCacheableEnable
+ .text 0x100060dc 0x13 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ 0x100060dc 0x13 _ZSP_DCacheExtraNonCacheableEnable
+ .text 0x100060ef 0x142 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x100060ef 0x54 _L1w_TaskPrioEng
+ 0x10006143 0xee _L1w_ModemDrvInit
+ .text 0x10006231 0x8e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x10006231 0x46 _L1w_AtNvInit
+ 0x10006277 0x48 _L1w_NvDataInit
+ .text 0x100062bf 0x13d5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ 0x100062bf 0x2e _L1w_DevBchBchSchedReq
+ 0x100062ed 0x2c _L1w_DevBchAfcSupplyReq
+ 0x10006319 0x26 _L1w_DevBchAfcLockCnf
+ 0x1000633f 0x2e _L1w_DevBchIntInd
+ 0x1000636d 0x3f _L1w_BchTask
+ 0x100063ac 0x45 _L1w_DevBchTimeDecrease
+ 0x100063f1 0xa _L1w_DevBchClearAfcInfo
+ 0x100063fb 0x1d _L1w_DevBchPiSymbol2Float
+ 0x10006418 0x53 _L1w_DevBchPiReset
+ 0x1000646b 0x3e _L1w_DevBchReset
+ 0x100064a9 0x35 _L1w_DevBchInit
+ 0x100064de 0x1f _L1w_DevBchTpuIntHandle
+ 0x100064fd 0x82 _L1w_DevBchPichSched
+ 0x1000657f 0x222 _L1w_DevBchPichRxCfg
+ 0x100067a1 0x97 _L1w_DevBchBchSched
+ 0x10006838 0x1b4 _L1w_DevBchBchRxCfg
+ 0x100069ec 0xa8 _L1w_DevBchAfcSupply
+ 0x10006a94 0xca _L1w_DevBchCpichRxCfg
+ 0x10006b5e 0x23 _L1w_DevBchAfcLockHandle
+ 0x10006b81 0x57 _L1w_DevBchPichIntHandle
+ 0x10006bd8 0xf8 _L1w_DevBchBchIntHandle
+ 0x10006cd0 0x80 _L1w_DevBchCpichIntHandle
+ 0x10006d50 0x24 _L1w_DevBchTimeConflict
+ 0x10006d74 0x56 _L1w_DevBchCalcFingerAdj
+ 0x10006dca 0x32 _L1w_DevBchCalcFingerBound
+ 0x10006dfc 0x6c _L1w_DevBchAddTpuEvent
+ 0x10006e68 0x7e _L1w_DevBchBchAfcProc
+ 0x10006ee6 0x54 _L1w_DevBchPichAfcProc
+ 0x10006f3a 0x14d _L1w_DevBchAdjustFinger
+ 0x10007087 0x2d _L1w_DevBchCpichIntMask
+ 0x100070b4 0x16 _L1w_DevBchClearAfcData
+ 0x100070ca 0xf _L1w_DevBchReadSfnResult
+ 0x100070d9 0x5c _L1w_DevBchFindBchRxCfgBuf
+ 0x10007135 0x5c _L1w_DevBchRtCfgTimeValid
+ 0x10007191 0x49 _L1w_DevBchPichIntPostProc
+ 0x100071da 0x15 _L1w_DevBchCalcFingerDist
+ 0x100071ef 0xc7 _L1w_DevBchSigProc
+ 0x100072b6 0x3a _L1w_DevBchCalcChipDist
+ 0x100072f0 0x25 _L1w_DevBchStopBchDecode
+ 0x10007315 0x7b _L1w_DevBchSetIQRotate
+ 0x10007390 0x26 _L1w_DevBchNCellAfcFeedback
+ 0x100073b6 0x60 _L1w_DevBchCaclRtSfnOffset
+ 0x10007416 0xcf _L1w_DevBchFingerManage
+ 0x100074e5 0x42 _L1w_DevBchFingerUpdate
+ 0x10007527 0x21 _L1w_DevBchStopBchDecodeReq
+ 0x10007548 0xe6 _L1w_DevBchPiaiAfcHandle
+ 0x1000762e 0x66 _L1w_DevBchFilterFinger
+ .text 0x10007694 0x2301 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x10007694 0x41 _L1w_DevMeasInit
+ 0x100076d5 0x41 _L1w_DevMeasReset
+ 0x10007716 0xd _L1w_DevMeasJudgeBufStateFull
+ 0x10007723 0xe _L1w_DevMeasJudgeBufState
+ 0x10007731 0x2cc _L1w_DevMeasConfigHw
+ 0x100079fd 0x40 _L1w_DevMeasCpichMeasCnf
+ 0x10007a3d 0x139 _L1w_DevMeasSideSupres
+ 0x10007b76 0x94 _L1w_DevMeasPathDetct
+ 0x10007c0a 0xd2 _L1w_DevMeasDeleteSttdDetctCell
+ 0x10007cdc 0xc1 _L1w_DevMeasSttdDetct
+ 0x10007d9d 0x4f _L1w_DevMeasCalcFingerPeakSum
+ 0x10007dec 0x5f _L1w_DevMeasCalcSearchWindowSum
+ 0x10007e4b 0x29 _L1w_DevMeasSortFirstFinger
+ 0x10007e74 0xd _L1w_DevMeasIsSearchWindowPath
+ 0x10007e81 0x25 _L1w_DevMeasSelNewWindow
+ 0x10007ea6 0xa8 _L1w_DevMeasSelWinFinInfo
+ 0x10007f4e 0xbe _L1w_DevMeasAdrWindowUpdate
+ 0x1000800c 0x104 _L1w_DevMeasTimeAdjust
+ 0x10008110 0x5f _L1w_DevMeasLOG10Cal
+ 0x1000816f 0x146 _L1w_DevMeasCalRssi
+ 0x100082b5 0x17a _L1w_DevMeasSaveCnfCellInfo
+ 0x1000842f 0x35 _L1w_DevMeasEcIoClaib
+ 0x10008464 0x104 _L1w_DevMeasGetRscpNew
+ 0x10008568 0xc0 _L1w_DevMeasGetRscp
+ 0x10008628 0x249 _L1w_DevMeasCalRscp1New
+ 0x10008871 0x2dd _L1w_DevMeasCalRscp1
+ 0x10008b4e 0xed _L1w_DevMeasPreSyncFingerCmp
+ 0x10008c3b 0xee _L1w_DevMeasAddPreSyncFingernew
+ 0x10008d29 0x14d _L1w_DevMeasAddPreSyncFinger
+ 0x10008e76 0x2f _L1w_DevMeasSetPreSyncInfo
+ 0x10008ea5 0x4 _L1w_DevMeasPreSyncHandler
+ 0x10008ea9 0x134 _L1w_DevMeasRscpHandler
+ 0x10008fdd 0x25 _L1w_DevMeasIntMissHandle
+ 0x10009002 0xb2 _L1w_DevMeasGetTpuEvtTim
+ 0x100090b4 0x50 _L1w_DevMeasSetAbnormalIntInfo
+ 0x10009104 0x1b6 _L1w_DevMeasReqProc
+ 0x100092ba 0x216 _L1w_DevMeasIntProc
+ 0x100094d0 0x62 _L1w_DevMeasTpuHandler
+ 0x10009532 0x48 _L1w_DevMeasIntInd
+ 0x1000957a 0x33 _L1w_DevMeasGetPreSyncInfo
+ 0x100095ad 0xf _L1w_DevMeasCheckWorkSt
+ 0x100095bc 0xe7 _L1w_DevMeasSetAgcStartTime
+ 0x100096a3 0x3e _L1w_DevMeasAgcTrans
+ 0x100096e1 0x2d _L1w_DevMeasSetAgc
+ 0x1000970e 0x18 _L1w_DevMeasOfflinedataStartTime
+ 0x10009726 0xc _L1w_DevMeasGetOfflinedataEndtTime
+ 0x10009732 0x2d _L1w_DevMeasOfflinedataSavedReq
+ 0x1000975f 0xe7 _L1w_DevMeasCfgOfflineData
+ 0x10009846 0x15 _L1w_DevMeasSaveAgcValue
+ 0x1000985b 0x16 _L1w_DevMeasSaveAgcStartTime
+ 0x10009871 0x63 _L1w_DevMeasJugeIsSaveAgcInfo
+ 0x100098d4 0xe _L1w_DevMeasClearOfflineDataInfo
+ 0x100098e2 0xb3 _L1w_MeasTask
+ .text 0x10009995 0x2bc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x10009995 0x8 _L1w_DevHsdpaActiveFlgGet
+ 0x1000999d 0x8 _L1w_DevHsdpaActiveFlgSet
+ 0x100099a5 0x8 _L1w_DevHsdpaHdtrUseTurboFlgGet
+ 0x100099ad 0x8 _L1w_DevHsdpaHdtrUseTurboFlgSet
+ 0x100099b5 0x8 _L1w_DevHsdpaGetAgcDownFlg
+ 0x100099bd 0x7 _L1w_DevHspaFachSetEdchActive
+ 0x100099c4 0x7 _L1w_DevHspaFachGetEdchActive
+ 0x100099cb 0x18 _L1w_DevHspaFachSubFrmInt
+ 0x100099e3 0x47 _L1w_DevHspaReset
+ 0x10009a2a 0x3e _L1w_DevHspaInit
+ 0x10009a68 0x18 _L1w_DevHspaCmnMsgProc
+ 0x10009a80 0x3c _L1w_DevHsupaFachMsgProc
+ 0x10009abc 0x4a _L1w_DevHsdpaFachMsgProc
+ 0x10009b06 0x5e _L1w_DevHsupaMsgProc
+ 0x10009b64 0x83 _L1w_DevHsdpaMsgProc
+ 0x10009be7 0x6a _L1w_HspaTask
+ .text 0x10009c51 0x951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ 0x10009c51 0x15 _L1w_DevRtxReset
+ 0x10009c66 0xf _L1w_DevRtxInit
+ 0x10009c75 0x44 _L1w_DevRtxInitCfgMsgHandle
+ 0x10009cb9 0x1 _L1w_DevRtxTxRfOperate
+ 0x10009cba 0x95 _L1w_DevRtxRxCfgTpuIntHandle
+ 0x10009d4f 0xce _L1w_DevRtxTpuIntUlRfHandle
+ 0x10009e1d 0xfa _L1w_DevRtxTpuIntHandle
+ 0x10009f17 0x24 _L1w_DevRtxResetInd
+ 0x10009f3b 0x24 _L1w_DevRtxInitInd
+ 0x10009f5f 0x21 _L1w_DevRtxTxPrachAbortReq
+ 0x10009f80 0x1 _L1w_DevRtxTxDpcchOfHspaCfgReq
+ 0x10009f81 0x48 _L1w_DevRtxUlRfCtrlSendReq
+ 0x10009fc9 0x2c _L1w_DevRtxRxFingerCfgReq
+ 0x10009ff5 0x32 _L1w_DevRtxRxPchCfgReq
+ 0x1000a027 0x21 _L1w_DevRtxRxAichRelReq
+ 0x1000a048 0x31 _L1w_DevRtxRxFachCfgReq
+ 0x1000a079 0x21 _L1w_DevRtxRxFachRelReq
+ 0x1000a09a 0x2f _L1w_DevRtxRxDlCmCfgReq
+ 0x1000a0c9 0x21 _L1w_DevRtxRxDlCmAbortReq
+ 0x1000a0ea 0x2d _L1w_DevRtxRxHsscchCfgReq
+ 0x1000a117 0x2f _L1w_DevRtxRxEagchCfgReq
+ 0x1000a146 0x21 _L1w_DevRtxRxEagchRelReq
+ 0x1000a167 0x35 _L1w_DevRtxRxDrxUpdateReq
+ 0x1000a19c 0x2a _L1w_DevRtxRxPlusCpichCfgReq
+ 0x1000a1c6 0x26 _L1w_DevRtxRxPlusCpichRelReq
+ 0x1000a1ec 0x2e _L1w_DevRtxRxRgHiCfgReq
+ 0x1000a21a 0x21 _L1w_DevRtxRxRgHiRelReq
+ 0x1000a23b 0x21 _L1w_DevRtxTxTimingAdjustInd
+ 0x1000a25c 0x19 _L1w_DevRtxRxTpcPilotIntInd
+ 0x1000a275 0x18 _L1w_DevRtxRxHwTpcPlIntInd
+ 0x1000a28d 0x2f _L1w_DevRtxRxHwPiAiIntInd
+ 0x1000a2bc 0x9 _L1w_DevRtxRxHwRakeIntInd
+ 0x1000a2c5 0x1a _L1w_DevRtxRxHwDtrIntInd
+ 0x1000a2df 0x22 _L1w_DevRtxRxPichIntInd
+ 0x1000a301 0x22 _L1w_DevRtxRxAichIntInd
+ 0x1000a323 0x102 _L1w_DevRtxRxTpcIntInd
+ 0x1000a425 0x3e _L1w_DevRtxRxTpcIntReq
+ 0x1000a463 0x66 _L1w_DevRtxRxPilotIntInd
+ 0x1000a4c9 0x21 _L1w_DevRtxRxTfciIntInd
+ 0x1000a4ea 0x22 _L1w_DevRtxRxTtiIntInd
+ 0x1000a50c 0x21 _L1w_DevRtxRxAgchFactorIntInd
+ 0x1000a52d 0x1 _L1w_DevRtxErrHandle
+ 0x1000a52e 0x6 _L1w_DevRtxInfoGet
+ 0x1000a534 0x6e _L1w_RtxTask
+ .text 0x1000a5a2 0x152c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x1000a5a2 0x49 _L1w_DevRfcAtSetDebug
+ 0x1000a5eb 0x5 _L1w_DevRfcGetAfcHz
+ 0x1000a5f0 0x1 _L1w_DevRfcRbdpRegCfg
+ 0x1000a5f1 0x6a _L1w_DevRfcReadMrtr
+ 0x1000a65b 0x2a _L1w_DevRfSleepInfo
+ 0x1000a685 0xc7 _L1w_DevRfcReset
+ 0x1000a74c 0x29 _L1w_DevRfcInit
+ 0x1000a775 0x8f _L1w_NvDataCheck
+ 0x1000a804 0x24 _L1w_DevRfcResetCnf
+ 0x1000a828 0x24 _L1w_DevRfcInitCnf
+ 0x1000a84c 0x53 _L1w_DevRfcSchedOpenReq
+ 0x1000a89f 0x23 _L1w_DevRestoreReq
+ 0x1000a8c2 0x2e _L1w_DevRfcIntInd
+ 0x1000a8f0 0x34 _L1w_DevRfcDpaInfoCtrl
+ 0x1000a924 0x30 _L1w_DevRfcAntExchange
+ 0x1000a954 0x2c _L1w_DevRfcAntSel
+ 0x1000a980 0x5e _L1w_DevRfcDiversityCtrl
+ 0x1000a9de 0x35 _L1w_DevRfcChgeInfoCtrlTx
+ 0x1000aa13 0x82 _L1w_DevRfcNotchHandle
+ 0x1000aa95 0xfd _L1w_DevRfcChgeInfoCtrlRx
+ 0x1000ab92 0x21 _L1W_DevRfcWaitForRfClose
+ 0x1000abb3 0xa6 _L1W_DevRfcSoltCtrlRfClose
+ 0x1000ac59 0x71 _L1w_DevRfcSlotCtrl
+ 0x1000acca 0xc6 _L1w_DevRfcFdtTrigCtrl
+ 0x1000ad90 0x56 _L1w_DevRfcFdtGetAgc
+ 0x1000ade6 0xbc _L1w_DevRfcFdtFreqCtrl
+ 0x1000aea2 0x67 _L1w_DevRfcFdtApcCwPaHighCtrl
+ 0x1000af09 0x6e _L1w_DevRfcFdtApcCwPaLowCtrl
+ 0x1000af77 0x67 _L1w_DevRfcFdtStartCtrl
+ 0x1000afde 0x91 _L1w_DevRfcNstTRXOpenCtrl
+ 0x1000b06f 0x42 _L1w_DevRfcNstTRXCloseCtrl
+ 0x1000b0b1 0x6a _L1w_DevRfcNstTRXFreqChge
+ 0x1000b11b 0x52 _L1w_DevRfcAmtCtrl
+ 0x1000b16d 0x46 _L1w_DevRfcAgcRefPowLogUpdate
+ 0x1000b1b3 0x29 _L1w_DevRfcIntTimeLogUpdate
+ 0x1000b1dc 0x19 _L1w_DevRfcMrtrConfLogUpdate
+ 0x1000b1f5 0x91 _L1w_DevRfcAgcRxStateLogUpdate
+ 0x1000b286 0x8 _L1w_DevRfcTempDacToIram
+ 0x1000b28e 0x31 _L1w_DevRfcIntLogUpdate
+ 0x1000b2bf 0x25 _L1w_DevRfcIntAgcDcCalc
+ 0x1000b2e4 0x2f _L1w_DevRfcIntNotchCfg
+ 0x1000b313 0x48 _L1w_DevRfc_RpiCfg
+ 0x1000b35b 0x18 _L1w_DevRfc_RpiSet
+ 0x1000b373 0x56 _L1w_DevRfc_RpiPwrCtrl
+ 0x1000b3c9 0x5e _L1w_DevRfcIntAgcDcSet
+ 0x1000b427 0x25 _L1w_DevRfcIntAfcSet
+ 0x1000b44c 0x63 _L1w_DevRfcRfRegReadCtrl
+ 0x1000b4af 0x2b _L1w_DevRfcSleepStatusSet
+ 0x1000b4da 0x6b _L1w_DevRfcIntProc
+ 0x1000b545 0x45 _L1w_DevRfcSetTxBandMaxPwr
+ 0x1000b58a 0x8f _L1w_DevRfcTxPowerSet
+ 0x1000b619 0x3f _L1w_DevRfcAfcHz2PPM
+ 0x1000b658 0x4d _L1w_DevRfcPpm2Hz
+ 0x1000b6a5 0x50 _L1w_DevRfcAfcUpdate
+ 0x1000b6f5 0x1c _L1w_DevRfcOpenCtrl
+ 0x1000b711 0x33 _L1w_DevRfcReusedReSourceRestore
+ 0x1000b744 0x1 _L1w_DevRfcTxTestMode
+ 0x1000b745 0x389 _L1w_RfcTask
+ .text 0x1000bace 0x1c63 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x1000bace 0x1f _L1w_DevPcDpchReset
+ 0x1000baed 0x1 _L1w_DevPcDpchInit
+ 0x1000baee 0x94 _L1w_DevPcDpcchPowerFilter
+ 0x1000bb82 0x38 _L1w_DevPcDeltaPilotPro
+ 0x1000bbba 0x28 _L1w_DevPcPowerItpPro
+ 0x1000bbe2 0x1c _L1w_DevPcGapTpcJudge
+ 0x1000bbfe 0x4b _L1w_DevPcCmPowerPro
+ 0x1000bc49 0x60 _L1w_DevPcDpcchPowerCalc
+ 0x1000bca9 0x40 _L1w_DevPcDeltaPilotPowerCalc
+ 0x1000bce9 0x3c _L1w_DevPcDeltaResumeCalc
+ 0x1000bd25 0x3c _L1w_DevPcRppPowerCalc
+ 0x1000bd61 0x59 _L1w_DevPcGetDeltaPilotCalcMode
+ 0x1000bdba 0x2a _L1w_DevPcSigmaLastCalc
+ 0x1000bde4 0xe0 _L1w_DevPcAjCalc
+ 0x1000bec4 0x5d _L1w_DevPcFindNearBeltaC
+ 0x1000bf21 0x6b _L1w_DevPcFindNearBeltaD
+ 0x1000bf8c 0x47 _L1w_DevPcAjToBelta
+ 0x1000bfd3 0x11 _L1w_DevPcDpchCurTfciBeltaCD
+ 0x1000bfe4 0x1f5 _L1w_DevPcBeltaCBeltaDCalc
+ 0x1000c1d9 0xf0 _L1w_DevPcBeltaCBeltaDUpdate
+ 0x1000c2c9 0xcc _L1w_DevPcSecCmBetalUpd
+ 0x1000c395 0x18 _L1w_DlIlpc_reset
+ 0x1000c3ad 0x8 _L1w_Olpc_reset
+ 0x1000c3b5 0x10 _L1w_DevPcOlpcCntReset
+ 0x1000c3c5 0xf _L1w_DevPcTpcGenReset
+ 0x1000c3d4 0xc _L1w_DevPcWindupReset
+ 0x1000c3e0 0x42 _L1w_DevPcDlSirCmAdjust
+ 0x1000c422 0x90 _L1w_DevPcDlSirTargetCalc
+ 0x1000c4b2 0xec _L1w_DevPcFdpchSirCal
+ 0x1000c59e 0x111 _L1w_DevPcDpchSirCal
+ 0x1000c6af 0x49 _L1w_DevPcDlWindUpMode
+ 0x1000c6f8 0x3c _L1w_DevPcSirSfAdjust
+ 0x1000c734 0x95 _L1w_DevPcTpcGenDpcMode1
+ 0x1000c7c9 0xd4 _L1w_DevPcDlTpcCmdGen
+ 0x1000c89d 0x26 _L1w_DevFdpchRscpCalc
+ 0x1000c8c3 0x37 _L1w_DevDpchParaECal
+ 0x1000c8fa 0x88 _L1w_DevDpchRscpCalc
+ 0x1000c982 0x9a _L1w_DevPcPilotIntInd
+ 0x1000ca1c 0x75 _L1w_DevPcRlsSetStaticAndSirThJudge
+ 0x1000ca91 0xb2 _L1w_DevPcSetTpcSoftBit
+ 0x1000cb43 0xc5 _L1w_DevPcTpcCombine
+ 0x1000cc08 0x14 _L1w_DevPcTpcSingleRlPca1Calc
+ 0x1000cc1c 0x11 _L1w_DevPcTpcSingleRlPca2Calc
+ 0x1000cc2d 0x89 _L1w_DevPcTpcMultiRlsPca1Calc
+ 0x1000ccb6 0x51 _L1w_DevPcTpcMultiRlsPca2Calc
+ 0x1000cd07 0x46 _L1w_DevPcTpcSingleRlCombine
+ 0x1000cd4d 0x4d _L1w_DevPcTpcMultiRlCombine
+ 0x1000cd9a 0x7e _L1w_DevPcTpcMultiRlsCombine
+ 0x1000ce18 0x18 _L1w_DevPcSirReset
+ 0x1000ce30 0x5 _L1w_DevPcBetalSeqalCal
+ 0x1000ce35 0x58 _L1w_DevPcCurSlotPowCalc
+ 0x1000ce8d 0x1f _L1w_DevPcIsOverPwr
+ 0x1000ceac 0x2a _L1w_DevPcSerachTfci
+ 0x1000ced6 0x31 _L1w_DevPcCurSlotOverPowProc
+ 0x1000cf07 0x40 _L1w_DevPcMaxPowerUpdate
+ 0x1000cf47 0xf _L1w_DevPcUlTfcOverEstCmp
+ 0x1000cf56 0xe9 _L1w_DevPcUlTfcOverEstRlt
+ 0x1000d03f 0x22 _L1w_DevPcUphFrmAvrCalc
+ 0x1000d061 0x5 _L1w_DevPcUphMapRep
+ 0x1000d066 0x32 _L1w_DevPcUphResult
+ 0x1000d098 0x8 _L1w_DevPcGetUphValue
+ 0x1000d0a0 0xab _L1w_DevPcUphProc
+ 0x1000d14b 0x91 _L1w_DevPcCfgInfoUpd
+ 0x1000d1dc 0x83 _L1w_DevPcDchInfoGet
+ 0x1000d25f 0x1e _L1w_DevDchOlpcBlerTargetMapping
+ 0x1000d27d 0x8f _L1w_DevPcDchOlpcThParamGet
+ 0x1000d30c 0x59 _L1w_DevPcEfachBeltacCal
+ 0x1000d365 0x104 _L1w_DevPcDchStartReqHandle
+ 0x1000d469 0x1a _L1w_DevPcUldpchTfciInfoHandle
+ 0x1000d483 0x27 _L1w_DevPcFDpchOutLoopAdj
+ 0x1000d4aa 0x55 _L1w_DevPcDpchOutLoopAdj
+ 0x1000d4ff 0x69 _L1w_DevPcDlRefTrchSel
+ 0x1000d568 0x68 _L1w_DevPcOlpcInit
+ 0x1000d5d0 0x3f _L1w_DevPcDtrBlerInfoHandle
+ 0x1000d60f 0x14 _L1w_DevPcTpcBerCal
+ 0x1000d623 0x27 _L1w_DevPcRlsTpcBerPro
+ 0x1000d64a 0x7e _L1w_DevPcMutlRlsTpcBerCal
+ 0x1000d6c8 0x33 _L1w_DevPcTpcBerCtr
+ 0x1000d6fb 0x36 _L1w_DevPcOlpcCtrl
+ .text 0x1000d731 0x1bca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x1000d731 0x64 _L1w_DevHsdpaStartPc
+ 0x1000d795 0x27 _L1w_DevHspdaHwReset
+ 0x1000d7bc 0x1b _L1w_DevHsdpaHwInit
+ 0x1000d7d7 0xa3 _L1w_DevHsdpaReset
+ 0x1000d87a 0x1 _L1w_DevHsdpaNvInit
+ 0x1000d87b 0x10d _L1w_DevHsdpaParaInit
+ 0x1000d988 0x187 _L1w_DevHsdpaRegTpuEvent
+ 0x1000db0f 0x1ac _L1w_DevHsdpaCfgProc
+ 0x1000dcbb 0x6e _L1w_DevHsdpaRelProc
+ 0x1000dd29 0xc4 _L1w_DevHsdpaIcSymModProc
+ 0x1000dded 0xa1 _L1w_DevHsdpaAdrCirIntProc
+ 0x1000de8e 0xeb _L1w_DevHsdpaAdrCpichIntProc
+ 0x1000df79 0x30 _L1w_DevHsdpaHsscchPart1IntProc
+ 0x1000dfa9 0x4d _L1w_DevHsdpaHsscchPart2IntProc
+ 0x1000dff6 0x30 _L1w_DevHsdpaHdtrIntProc
+ 0x1000e026 0x3a _L1w_DevHsdpaCfn2SfnTime
+ 0x1000e060 0x37 _L1w_DevHsdpaOrderActProc
+ 0x1000e097 0x152 _L1w_DevHsdpaDchTpuProc
+ 0x1000e1e9 0x42f _L1w_DevHsdpaTpuTraceLog
+ 0x1000e618 0xfb _L1w_DevHsdpaIsJudgechangjing3
+ 0x1000e713 0xe0 _L1w_DevHsdpaTpuProc
+ 0x1000e7f3 0xb4 _L1w_DevHsdpaCompareCellInfo
+ 0x1000e8a7 0x173 _L1w_DevHsdpaIsJudgePsrOver512
+ 0x1000ea1a 0x105 _L1w_DevHsdpaPsrOver512
+ 0x1000eb1f 0x2a _L1w_DevHsdpaPsrFingerOldDaNew
+ 0x1000eb49 0x2a _L1w_DevHsdpaPsrFingerNewXiaoOld
+ 0x1000eb73 0xea _L1w_DevHsdpaPsrIschangjing3
+ 0x1000ec5d 0x1d0 _L1w_DevHsdpaTxTpuProc
+ 0x1000ee2d 0x56 _L1w_DevHsdpaPsrUpdateProc
+ 0x1000ee83 0x3f _L1w_DevHsdpaCmUpdateProc
+ 0x1000eec2 0x4a _L1w_DevHsdpaCfgReq
+ 0x1000ef0c 0x29 _L1w_DevHsdpaRelReq
+ 0x1000ef35 0x29 _L1w_DevHsdpaIcSymModIntInd
+ 0x1000ef5e 0x29 _L1w_DevHsdpaAdrCirIntInd
+ 0x1000ef87 0x29 _L1w_DevHsdpaAdrCpichIntInd
+ 0x1000efb0 0x29 _L1w_DevHsdpaHsscchPart1IntInd
+ 0x1000efd9 0x29 _L1w_DevHsdpaHsscchPart2IntInd
+ 0x1000f002 0x29 _L1w_DevHsdpaHdtrIntInd
+ 0x1000f02b 0x3b _L1w_DevDlsHsdpaPsrUpdateReq
+ 0x1000f066 0x35 _L1w_DevHsdpaCmUpdateReq
+ 0x1000f09b 0x3b _L1w_DevHsdpaHsscchOrdInd
+ 0x1000f0d6 0x4c _L1w_DevHsdpaFachCfgReq
+ 0x1000f122 0x26 _L1w_DevHsdpaFachRelReq
+ 0x1000f148 0x29 _L1w_DevHsdpaFachRcvReq
+ 0x1000f171 0x26 _L1w_DevHsdpaFachHrntiUpdateReq
+ 0x1000f197 0x21 _L1w_DevHsdpaFachDataInd
+ 0x1000f1b8 0x4b _L1w_DevHsdpaPchCfgReq
+ 0x1000f203 0x21 _L1w_DevHsdpaPchRelReq
+ 0x1000f224 0x26 _L1w_DevHsdpaRtxPiInd
+ 0x1000f24a 0x28 _L1w_DevHsdpaDmaIntInd
+ 0x1000f272 0x39 _L1w_DevHsdpaDataDmaCpy
+ 0x1000f2ab 0x24 _L1w_DevHsdpaCurTime2SfnTime
+ 0x1000f2cf 0x2c _L1w_DevHsdpaGetCurSfnTime
+ .text 0x1000f2fb 0x16ff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x1000f2fb 0x20 _L1w_DevHsdpaLessIsAct
+ 0x1000f31b 0xa5 _L1w_DevHsdpaLessParaInit
+ 0x1000f3c0 0x2f _L1w_DevHsdpaLessOrdIndProc
+ 0x1000f3ef 0x33 _L1w_DevHsdpaLessTimeRcd
+ 0x1000f422 0x5f _L1w_DevHsdpaLessCfgTraceLog
+ 0x1000f481 0xc _L1w_DevHsdpaLessCfgAllTb
+ 0x1000f48d 0x23 _L1w_DevHsdpaLessFindIdleHarq
+ 0x1000f4b0 0x231 _L1w_DevHsdpaPart2Type2Proc
+ 0x1000f6e1 0xc5 _L1w_DevHsdpaDchLessProc
+ 0x1000f7a6 0x7e _L1w_DevHsdpaPart2LessProc
+ 0x1000f824 0x23 _L1w_DevHsdpaIsLessValid
+ 0x1000f847 0x18 _L1w_DevHsdpaLessFindHsdschTti
+ 0x1000f85f 0x1c9 _L1w_DevHsdpaDchLessHdtrIntProc
+ 0x1000fa28 0x24 _L1w_DevHsdpaLessHdtrIntProc
+ 0x1000fa4c 0x6b _L1w_DevHsdpaPchSaveAdrInitCfg
+ 0x1000fab7 0x51 _L1w_DevHsdpaPchSaveHsscchInitCfg
+ 0x1000fb08 0x7d _L1w_DevHsdpaPchRxInitRcvProc
+ 0x1000fb85 0xae _L1w_DevHsdpaPchSaveLessPara
+ 0x1000fc33 0x8e _L1w_DevHsdpaPchSaveAdrSubFrmCfg
+ 0x1000fcc1 0x42 _L1w_DevHsdpaPchSaveIcPsrCfg
+ 0x1000fd03 0x9a _L1w_DevHsdpaPchRxSubFrmProc
+ 0x1000fd9d 0x5f _L1w_DevHsdpaPchCfgProc
+ 0x1000fdfc 0x2d _L1w_DevHsdpaPchRelProc
+ 0x1000fe29 0x18 _L1w_DevHsdpaPchTpuProc
+ 0x1000fe41 0x62 _L1w_DevHsdpaPchSavePart1IntCfg
+ 0x1000fea3 0x66 _L1w_DevHsdpaPchPart2Type1Proc
+ 0x1000ff09 0x12d _L1w_DevHsdpaPchHdtrIntProc
+ 0x10010036 0x92 _L1w_DevHsdpaPchLessProc
+ 0x100100c8 0x16d _L1w_DevHsdpaPchLessHdtrIntProc
+ 0x10010235 0xa1 _L1w_DevHsdpaRtxPiIndProc
+ 0x100102d6 0x71 _L1w_DevHsdpaFachStartPc
+ 0x10010347 0x4e _L1w_DevHsdpaFachSaveHsdpcchAckCfg
+ 0x10010395 0x5c _L1w_DevHsdpaFachSaveHsdpcchCqiCfg
+ 0x100103f1 0x4d _L1w_DevHsdpaFachCqiSendCtrl
+ 0x1001043e 0x6e _L1w_DevHsdpaFachSaveAdrInitCfg
+ 0x100104ac 0x4a _L1w_DevHsdpaFachSaveHsscchInitCfg
+ 0x100104f6 0x52 _L1w_DevHsdpaFachRxInitRcvProc
+ 0x10010548 0x2e _L1w_DevHsdpaFachTxInitSendProc
+ 0x10010576 0x81 _L1w_DevHsdpaFachSaveAdrSubFrmCfg
+ 0x100105f7 0x83 _L1w_DevHsdpaFachRxSubFrmProc
+ 0x1001067a 0x56 _L1w_DevHsdpaFachTxSubFrmProc
+ 0x100106d0 0x68 _L1w_DevHsdpaFachCfgProc
+ 0x10010738 0x44 _L1w_DevHsdpaFachRelProc
+ 0x1001077c 0x22 _L1w_DevHsdpaFachTpuProc
+ 0x1001079e 0x2e _L1w_DevHsdpaFachSavePart1IntCfg
+ 0x100107cc 0x131 _L1w_DevHsdpaFachHdtrIntProc
+ 0x100108fd 0x3c _L1w_DevHsdpaFachRcvProc
+ 0x10010939 0x28 _L1w_DevHsdpaFachHrntiUpdateProc
+ 0x10010961 0x79 _L1w_DevHsdpaFachEdchIndProc
+ 0x100109da 0x20 _L1w_DevHsdpaFachSetHsdpcchFlg
+ .text 0x100109fa 0x1019 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ 0x100109fa 0x60 _L1w_DevRtxRxFingerCfg
+ 0x10010a5a 0xe2 _L1w_DevRtxRxCpichCfg
+ 0x10010b3c 0x4f _L1w_DevRtxRxPichCfg
+ 0x10010b8b 0x12 _L1w_DevRtxRxPichRel
+ 0x10010b9d 0x50 _L1w_DevRtxRxPchCfg
+ 0x10010bed 0x24 _L1w_DevRtxRxPchRel
+ 0x10010c11 0x2f _L1w_DevRtxRxAichRakeCfg
+ 0x10010c40 0x26 _L1w_DevRtxRxAichCfg
+ 0x10010c66 0x5 _L1w_DevRtxRxAichRel
+ 0x10010c6b 0x2e _L1w_DevRtxRxFachRakeCfg
+ 0x10010c99 0x46 _L1w_DevRtxRxFachCfg
+ 0x10010cdf 0x21 _L1w_DevRtxRxFachRel
+ 0x10010d00 0xa5 _L1w_DevRtxRxDlDpchRakeCfg
+ 0x10010da5 0x40 _L1w_DevRtxRxDlDpchCfg
+ 0x10010de5 0x26 _L1w_DrvDpramRxWriteClearData
+ 0x10010e0b 0x39 _L1w_DevRtxRxDlDpchRel
+ 0x10010e44 0x16d _L1w_DevRtxRxDlCmSlotCfg
+ 0x10010fb1 0xe5 _L1w_DevRtxRxDlCmSlotRel
+ 0x10011096 0x63 _L1w_DevRtxRxDlCmCfgTpuIntHandle
+ 0x100110f9 0x1ff _L1w_DevRtxRxDlCmCfg
+ 0x100112f8 0x6f _L1w_DevRtxRxFdpchRakeCfg
+ 0x10011367 0x3d _L1w_DevRtxRxFdpchCfg
+ 0x100113a4 0x5 _L1w_DevRtxRxFdpchRel
+ 0x100113a9 0x34 _L1w_DevRtxRxHsscchRakeCfg
+ 0x100113dd 0x39 _L1w_DevRtxRxHsscchCfg
+ 0x10011416 0x5 _L1w_DevRtxRxHsscchRel
+ 0x1001141b 0x38 _L1w_DevRtxRxEagchRakeCfg
+ 0x10011453 0x34 _L1w_DevRtxRxEagchCfg
+ 0x10011487 0xf _L1w_DevRtxRxEagchRel
+ 0x10011496 0xbc _L1w_DevRtxRxRgHiRakeCfg
+ 0x10011552 0x4b _L1w_DevRtxRxRgHiCfg
+ 0x1001159d 0x5 _L1w_DevRtxRxRgHiRel
+ 0x100115a2 0x6b _L1w_DevRtxRxCctrchCfgHandle
+ 0x1001160d 0x11b _L1w_DevRtxRxCfgHandle
+ 0x10011728 0x2f _L1w_DevRtxRxDlTpcPlCfg
+ 0x10011757 0x7e _L1w_DevRtxRxIntFingerCfg
+ 0x100117d5 0x69 _L1w_DevRtxRxIntCfg
+ 0x1001183e 0x6e _L1w_DevRtxRxDpchSlotForm
+ 0x100118ac 0x71 _L1w_DevRtxRxSccpchSlotForm
+ 0x1001191d 0x5a _L1w_DevRtxRxComparaSlotForm
+ 0x10011977 0x34 _L1w_DevRtxRxCmASlotForm
+ 0x100119ab 0x34 _L1w_DevRtxRxCmBSlotForm
+ 0x100119df 0x34 _L1w_DevRtxRxNormalSlotForm
+ .text 0x10011a13 0x92c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x10011a13 0x13 _L1w_DevRtxTimeCmp
+ 0x10011a26 0x2d _L1w_DevRtxUlRfcReq
+ 0x10011a53 0x37 _L1w_DevRtxUlRfTblInit
+ 0x10011a8a 0x2f _L1w_DevRtxUlRfGetNodeFromUnusedQ
+ 0x10011ab9 0x17 _L1w_DevRtxUlRfPutNode2UnusedQ
+ 0x10011ad0 0x31 _L1w_DevRtxUlRfQueueInsert
+ 0x10011b01 0x41 _L1w_DevRtxUlRfQueueGet
+ 0x10011b42 0xf _L1w_DevRtxUlRfQueueSearch
+ 0x10011b51 0x67 _L1w_DevRtxUlRfStartSched
+ 0x10011bb8 0x262 _L1w_DevRtxUlRfCtrlReq
+ 0x10011e1a 0x1de _L1w_DevRtxUlRfSchedPick
+ 0x10011ff8 0x81 _L1w_DevRtxUlRfSchedLink
+ 0x10012079 0x12f _L1w_DevRtxUlRfSchedMerge
+ 0x100121a8 0x18a _L1w_DevRtxUlRfSched
+ 0x10012332 0xd _L1w_DevRtxUlRfStopSched
+ .text 0x1001233f 0xf38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x1001233f 0x7 _L1w_DevTxGetDchState
+ 0x10012346 0x11 _L1w_DevTxGetRfCtrlPara
+ 0x10012357 0x15 _L1w_DevTxDchReset
+ 0x1001236c 0x39 _L1w_DevTxOpenRfc
+ 0x100123a5 0x39 _L1w_DevTxCloseRfc
+ 0x100123de 0x68 _L1w_DevTxCmRfcCfg
+ 0x10012446 0x50 _L1w_DevTxNormalSlotForm
+ 0x10012496 0x5e _L1w_DevTxCmSlotForm
+ 0x100124f4 0x1c _L1w_DevTxCalcCmPliot
+ 0x10012510 0x39 _L1w_DevTxGetUlMaxMinTti
+ 0x10012549 0x10e _L1w_DevTxGetDchParam
+ 0x10012657 0x75 _L1w_DevTxUlCmTfciAnalysis
+ 0x100126cc 0x29 _L1w_DevTxHsupaTransInd
+ 0x100126f5 0x16b _L1w_DevTxDchToPcStart
+ 0x10012860 0x26 _L1w_DevTxDchToPcStop
+ 0x10012886 0x64 _L1w_DevTxDchCmParaToPc
+ 0x100128ea 0x27 _L1w_DevTxDpcchPreambleToPc
+ 0x10012911 0x2a _L1w_DevTxDpdchTfciToPc
+ 0x1001293b 0x177 _L1w_DevTxDataUpdate
+ 0x10012ab2 0x55 _L1w_DevTxGetUtrPara
+ 0x10012b07 0x115 _L1w_DevTxDchUtrCfg
+ 0x10012c1c 0x77 _L1w_DevTxDchCmProc
+ 0x10012c93 0x154 _L1w_DevTxDchSendCfg
+ 0x10012de7 0xad _L1w_DevTxDchPreambleSendProc
+ 0x10012e94 0x29 _L1w_DevTxDchPostVerifyFailProc
+ 0x10012ebd 0x94 _L1w_DevTxDchPreambleIntHandle
+ 0x10012f51 0xd9 _L1w_DevTxDpchSendCndCheck
+ 0x1001302a 0x59 _L1w_DevTxDpchIntHandle
+ 0x10013083 0x54 _L1w_DevTxDchTpuIntHandle
+ 0x100130d7 0x65 _L1w_DevTxDchRelMsgHandle
+ 0x1001313c 0x8b _L1w_DevTxCmCfgMsgHandle
+ 0x100131c7 0xb0 _L1w_DevTxDchCfgMsgHandle
+ .text 0x10013277 0x6e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x10013277 0xf _L1W_DevHsupaInitMacro
+ 0x10013286 0xc _L1W_DevHsupaCalCBNum
+ 0x10013292 0x21 _L1W_DevHsupaCalcCBLength
+ 0x100132b3 0xa _L1W_DevHsupaCalInterleavingRow
+ 0x100132bd 0x3a _L1W_DevHsupaCalCodeBlockConf
+ 0x100132f7 0x1c _L1w_DevHsupaCalMaxNej
+ 0x10013313 0x99 _L1W_DevHsupaCalSfOneEtfc
+ 0x100133ac 0xfd _L1W_DevHsupaCalAllSFConf
+ 0x100134a9 0x12a _L1W_DevHsupaCalSFConf
+ 0x100135d3 0x94 _L1W_DevHsupaCalRmRv
+ 0x10013667 0x9b _L1W_DevHsupaCalRmPara
+ 0x10013702 0x41 _L1W_DevHsupaCalChannelCodeConf
+ 0x10013743 0x7a _L1W_DevHsupaCalInterleavingConf
+ 0x100137bd 0x37 _L1W_DevHsupaReTransBitmapTtiTen
+ 0x100137f4 0x6b _L1W_DevHsupaCalEtxBitmap
+ 0x1001385f 0x48 _L1W_DevHsupaCalEUTRConf
+ 0x100138a7 0x6e _L1W_DevHsupaCalETXConf
+ 0x10013915 0x46 _L1W_DevHsupaCalULConf
+ .text 0x1001395b 0x1358 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x1001395b 0xb _L1w_DevRfcCtrlDbChgeInfoSet
+ 0x10013966 0xf _L1w_DevRfcCtrlDbChgeInfoInit
+ 0x10013975 0x2 _L1w_DevRfcCtrlDbSlotEndSet
+ 0x10013977 0x17 _L1w_DevRfcCtrlDbSlotInfoInit
+ 0x1001398e 0x61 _L1w_DevRfcCtrlDbInit
+ 0x100139ef 0x10 _L1w_DevRfcCtrlDbInitAll
+ 0x100139ff 0x37 _L1w_DevRfcCtrlDbTimeContCheck
+ 0x10013a36 0x33 _L1w_DevRfcCtrlDbSlotChgeInfoWr
+ 0x10013a69 0x16 _L1w_DevRfcCtrlDbGetDbInd
+ 0x10013a7f 0x35 _L1w_DevRfcCtrlDbFrameChgeInfoWr
+ 0x10013ab4 0x2d _L1w_DevRfcCtrlDbGetSegLen
+ 0x10013ae1 0x9f _L1w_DevRfcCtrlDbSlotEndUpdate
+ 0x10013b80 0x5c _L1w_DevRfcCtrlDbCtrlInfoUpdate
+ 0x10013bdc 0x117 _L1w_DevRfcCtrlDbSchedUpdate
+ 0x10013cf3 0x9c _L1w_DevRfcCtrlDbStPo2Chge
+ 0x10013d8f 0x6d _L1w_DevRfcCtrlDbStPo1Chge
+ 0x10013dfc 0x93 _L1w_DevRfcCtrlDbStPi2Chge
+ 0x10013e8f 0x27 _L1w_DevRfcCtrlDbStPi1Chge
+ 0x10013eb6 0x63 _L1w_DevRfcCtrlDbStPi0Chge
+ 0x10013f19 0x49 _L1w_DevRfcCtrlDbStartInsert
+ 0x10013f62 0xeb _L1w_DevRfcCtrlDbEndPo2Chge
+ 0x1001404d 0x5d _L1w_DevRfcCtrlDbEndPo1Chge
+ 0x100140aa 0xf _L1w_DevRfcCtrlDbEndPo0Chge
+ 0x100140b9 0x3f _L1w_DevRfcCtrlDbEndInsert
+ 0x100140f8 0xf9 _L1w_DevRfcCtrlDbDrvOpenUpdate
+ 0x100141f1 0xd _L1w_DevRfcCtrlDbGetAdr
+ 0x100141fe 0x4a _L1w_DevRfcCtrlDbChgeInfoHandle
+ 0x10014248 0x10e _L1w_DevRfcCtrlDbGetSlotChgeInfo
+ 0x10014356 0x39 _L1w_DevRfcAgcDbInit
+ 0x1001438f 0x29 _L1w_DevRfcAfcDbInit
+ 0x100143b8 0x14 _L1w_DevRfcAgcDbFreqSearch
+ 0x100143cc 0xe _L1w_DevRfcAgcDbSetFreqChgeFlag
+ 0x100143da 0x21 _L1w_DevRfcAgcDbFindOldestPos
+ 0x100143fb 0x58 _L1w_DevRfcAgcDbFindFreqPos
+ 0x10014453 0x21 _L1w_DevRfcAgcDbGetFreqInd
+ 0x10014474 0x35 _L1w_DevRfcAgcDbFastAgcCond
+ 0x100144a9 0xd0 _L1w_DevRfcAgcDbAgcSet
+ 0x10014579 0x3b _L1w_DevRfcAgcDbLockInfoUpdate
+ 0x100145b4 0x3a _L1w_DevRfcAgcCalcInfoUpdateCmn
+ 0x100145ee 0x2e _L1w_DevRfcAgcCalcInfoUpdateDpa
+ 0x1001461c 0x58 _L1w_DevRfcAgcDbAgcStepCtrl
+ 0x10014674 0x48 _L1w_DevRfcAgcDbAgcUpdate
+ 0x100146bc 0x6e _L1w_DevRfcAgcDbAgcCalcSingleCh
+ 0x1001472a 0x37 _L1w_DevRfcAgcDbAfterFastAgcSet
+ 0x10014761 0x38 _L1w_DevRfcAgcDbFastAgcValUpdate
+ 0x10014799 0x60 _L1w_DevRfcAgcDb2RMainChAdjCond
+ 0x100147f9 0x6b _L1w_DevRfcAgcDb2RAgcHandle
+ 0x10014864 0x124 _L1w_DevRfcAgcDbAgcCalc
+ 0x10014988 0x1c _L1w_DevRfcAgcDbAgcEstEn
+ 0x100149a4 0x3d _L1w_DevRfcAfcDbAfcSet
+ 0x100149e1 0x13 _L1w_DevRfcAfcDbGetAfcDbVal
+ 0x100149f4 0x1e _L1w_DevRfcSetRefFreq
+ 0x10014a12 0x43 _L1w_DevRfcAgcDbGetFreqAgcInfo
+ 0x10014a55 0x62 _L1w_DevRfcAgcDbGetRssi
+ 0x10014ab7 0x9e _L1w_DevRfcAgcDbGetMeanpwr
+ 0x10014b55 0x35 _L1w_DevRfcAgcDbAuxChInitSet
+ 0x10014b8a 0x42 _L1w_DevRfcAgcDbGetTableInd
+ 0x10014bcc 0x7a _L1w_DevRfcAgcDbFdtAgcInit
+ 0x10014c46 0x43 _L1w_DevRfcAgcDbNstAgcInit
+ 0x10014c89 0x15 _L1w_DevRfcAgcDbTxChgeInfoWr
+ 0x10014c9e 0x15 _L1w_DevRfcAgcDbRxChgeInfoWr
+ .text 0x10014cb3 0x2cb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ 0x10014cb3 0x26 _L1w_DevDlsSendIntMsg
+ 0x10014cd9 0x24 _L1w_DevDlsSendCnf
+ 0x10014cfd 0xf _L1w_DevDlsReset
+ 0x10014d0c 0xf _L1w_DevDlsInit
+ 0x10014d1b 0x263 _L1w_DlsTask
+ .text 0x10014f7e 0x12a5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x10014f7e 0x89 _L1w_DevHsdpaSubFrmIsInCm
+ 0x10015007 0x78 _L1w_DevHsdpaCalcTimingInfo
+ 0x1001507f 0x2d _L1w_DevHsdpaCalcAckNackPos
+ 0x100150ac 0x52 _L1w_DevHsdpaCalcTbSizeByTbs
+ 0x100150fe 0x23 _L1w_DevHsdpaCalcTbSizeByTbsIdx
+ 0x10015121 0xd _L1w_DevHsdpaCalcRvB
+ 0x1001512e 0x3a _L1w_DevHsdpaCalcCodeBlockPara
+ 0x10015168 0x25 _L1w_DevHsdpaCalc1stRmPara
+ 0x1001518d 0x37 _L1w_DevHsdpaCalc2ndRmEini
+ 0x100151c4 0xf9 _L1w_DevHsdpaCalcRmPara
+ 0x100152bd 0x9f _L1w_DevHsdpaCalcVelcity
+ 0x1001535c 0xd _L1w_DevHsdpaCalcSymPower
+ 0x10015369 0x79 _L1w_DevHsdpaCalcFingerMaskStep1
+ 0x100153e2 0xba _L1w_DevHsdpaCalcFingerMaskStep2
+ 0x1001549c 0x45 _L1w_DevHsdpaCalcFingerMaskStep3
+ 0x100154e1 0x5d _L1w_DevHsdpaCalcAntFingerMask
+ 0x1001553e 0x11f _L1w_DevHsdpaFingerMaskBufUpdate
+ 0x1001565d 0x8c _L1w_DevHsdpaCalcFingerMask
+ 0x100156e9 0xb8 _L1w_DevHsdpaSnrLowRstJudge
+ 0x100157a1 0x1b0 _L1w_DevHsdpaCalcNoiseSinr
+ 0x10015951 0x47 _L1w_DevHsdpaCalcNoiseFactor
+ 0x10015998 0xc3 _L1w_DevHsdpaCalcCirPower
+ 0x10015a5b 0xba _L1w_DevHsdpaCalcEqNoise
+ 0x10015b15 0x34 _L1w_DevHsdpaCalcNoise
+ 0x10015b49 0x2d _L1w_DevHsdpaIsExceedFinWin
+ 0x10015b76 0x6b _L1w_DevHsdpaPsrFingerFilter
+ 0x10015be1 0x56 _L1w_DevHsdpaCalcFrameHeadPos
+ 0x10015c37 0x87 _L1w_DevHsdpaCalcIntraCellSfnOffset
+ 0x10015cbe 0xfc _L1w_DevHsdpaCalcFingerSort
+ 0x10015dba 0x24 _L1w_DevHsdpaCalcJudgeResetFlg
+ 0x10015dde 0x27c _L1w_DevHsdpaCalcCellFingerSort
+ 0x1001605a 0x1b _L1w_DevHsdpaCalcAntChe4xPos
+ 0x10016075 0xef _L1w_DevHsdpaCalcChe4xPos
+ 0x10016164 0xbf _L1w_DevHsdpaCalcAdrPsrInfo
+ .text 0x10016223 0x3d4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ 0x10016223 0x3f _L1w_DevDrvAllIntClear
+ 0x10016262 0x54 _L1w_DevDrvRestoreAllInt
+ 0x100162b6 0x9e _L1W_TPU_RAKE_ISR
+ 0x10016354 0x70 _L1W_RAKE_DFE_RFC_ISR
+ 0x100163c4 0xac _L1W_TPU_CSR_ADR_HSSCCH_ISR
+ 0x10016470 0x89 _L1W_CSR_DTR_PSR_ISR
+ 0x100164f9 0x27 _L1w_DevCommGetTop19IntStatus
+ 0x10016520 0x26 _L1W_ICP_UPA_DATA_ISR
+ 0x10016546 0x5c _L1W_ICP_SLEEP_WAKEUP_ISR
+ 0x100165a2 0x1c _L1W_EDCP_ISR
+ 0x100165be 0x39 _L1_W_LPM_T3_ISR
+ .text 0x100165f7 0x2265 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x100165f7 0x8 _L1w_DevCsrSetStep1Clk
+ 0x100165ff 0x8 _L1w_DevCsrGetStep1Clk
+ 0x10016607 0x6 _L1w_DevGetPeakThreshold
+ 0x1001660d 0x1 _L1w_DevGetFsThreshold
+ 0x1001660e 0x1e _L1w_DevCsrStep1Cmp
+ 0x1001662c 0xa _L1w_DevCsrF2W
+ 0x10016636 0xf _L1w_DevCsrW2F
+ 0x10016645 0x15 _L1w_DevCsrCompare
+ 0x1001665a 0x87 _L1w_DevCsrComputeWin
+ 0x100166e1 0x2a _L1w_DevCsrInitReq
+ 0x1001670b 0x98 _L1w_DevCsrStep1Req
+ 0x100167a3 0x75 _L1w_DevCsrFsReq
+ 0x10016818 0x27 _L1w_DevCsrResetCnf
+ 0x1001683f 0x27 _L1w_DevCsrInitCnf
+ 0x10016866 0x65 _L1w_DevCsrStep1Cnf
+ 0x100168cb 0x4f _L1w_DevCsrFsCnf
+ 0x1001691a 0x2d _L1w_DevCsrIntInd
+ 0x10016947 0x5d _L1w_DevCsrStep1CalConfigIndex4_1
+ 0x100169a4 0x3d _L1w_DevCsrSaveDateMrtr
+ 0x100169e1 0x138 _L1w_DevCsrIcCfg
+ 0x10016b19 0xe _L1w_DevCsrSetFsAbort
+ 0x10016b27 0x1ac _L1w_DevCsrStep1Abort
+ 0x10016cd3 0x272 _L1w_DevCsrStep1Pro
+ 0x10016f45 0xa _L1w_DevCsrClrFsSt
+ 0x10016f4f 0x7d _L1w_DevCsrFsPro
+ 0x10016fcc 0xbf _L1w_DevCsrPeakFilter
+ 0x1001708b 0xb8 _L1w_DevCsrPeakSearch
+ 0x10017143 0x95 _L1w_DevCsrFsReqCfg
+ 0x100171d8 0x113 _L1w_DevCsrIcFilter
+ 0x100172eb 0x1312 _L1w_DevCsrStep1Int
+ 0x100185fd 0x125 _L1w_DevCsrFsInt
+ 0x10018722 0x1a _L1w_DevCsrStep1IsBusy
+ 0x1001873c 0x13 _L1w_DevCsrReset
+ 0x1001874f 0x10 _L1w_DevCsrStFsSt
+ 0x1001875f 0xfd _L1w_CsrTask
+ .text 0x1001885c 0x220d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x1001885c 0x30 _L1w_DevPcWord64ToFloat
+ 0x1001888c 0x40 _L1w_DevPcFloatToWord
+ 0x100188cc 0x2e _L1w_PcLog2FindTable
+ 0x100188fa 0x80 _L1w_DevPcFloatSirAndBlerToWord32
+ 0x1001897a 0x28 _L1w_DevPcDiv
+ 0x100189a2 0x71 _L1w_DevPcLog10
+ 0x10018a13 0xe6 _L1w_DevPc10xPower10expOld
+ 0x10018af9 0x2c _L1w_DevPc10xPower10exp
+ 0x10018b25 0x65 _L1w_DevSirBlerPcDiv
+ 0x10018b8a 0x38 _L1w_DevPcFloatAdd
+ 0x10018bc2 0x3b _L1w_DevPcUlAlphaDiv
+ 0x10018bfd 0x62 _L1w_DevPcPowerLimit
+ 0x10018c5f 0x86 _L1w_DevPcSumBeltaIQmap
+ 0x10018ce5 0x81 _L1w_DevPcCalcSquareBetaHs
+ 0x10018d66 0x22 _L1w_DevPcP1P2LogCalc
+ 0x10018d88 0x19 _L1w_DevPcP1P2Calc
+ 0x10018da1 0xd _L1w_DevPcBetalRatioProc
+ 0x10018dae 0x9d _L1w_DevPcCodeRatioCalc
+ 0x10018e4b 0x14 _L1w_DevPcGetTxpowerForMeas
+ 0x10018e5f 0x99 _L1w_DevPcConfigTxReg
+ 0x10018ef8 0x92 _L1w_DevPcTtiUpdDpaBeta
+ 0x10018f8a 0xe4 _L1w_DevPcTtiUpdEdchBeta
+ 0x1001906e 0x23 _L1w_DevPcNoDpdchPro
+ 0x10019091 0xb5 _L1w_DevPcTtiUpdDpchBeta
+ 0x10019146 0x35 _L1w_DevPcBetaEdAllSquareCalc
+ 0x1001917b 0xc _L1w_DevPcSumSquareCalc
+ 0x10019187 0x56 _L1w_DevPcSquareCalc
+ 0x100191dd 0x110 _L1w_DevPcIQMap
+ 0x100192ed 0x1b _L1w_DevPcRangeAdjust
+ 0x10019308 0x32 _L1w_DevPcCalcCm
+ 0x1001933a 0x146 _L1w_DevPcMprCalPro
+ 0x10019480 0x2f _L1w_DevPcMprAdjust
+ 0x100194af 0x39 _L1w_DevPcMprCalCtrl
+ 0x100194e8 0x116 _L1w_DevPcCodeRatioAndTotalPowerCalc
+ 0x100195fe 0x33 _L1w_DevPcPwrValadjust
+ 0x10019631 0x94 _L1w_DevPcGainTorAdjust
+ 0x100196c5 0x89 _L1w_DevPcCalPvalue
+ 0x1001974e 0x3f _L1w_DevPcGaintorHalf
+ 0x1001978d 0x4b _L1w_DevPcMaxPwrSetProc
+ 0x100197d8 0x178 _L1w_DevPcTxAndRfSet
+ 0x10019950 0x54 _L1w_DevPcTpuCallBack
+ 0x100199a4 0x1d _L1w_DevPcRegFrmTpu
+ 0x100199c1 0x88 _L1w_DevPcUlRegTpu
+ 0x10019a49 0x1c _L1w_DevPcIsBeltaEdAllEquReduce
+ 0x10019a65 0xff _L1w_DevPcSetLastBelta
+ 0x10019b64 0x25 _L1w_DevPcPmaxReLimt
+ 0x10019b89 0x7d _L1w_DevPcPmaxReCalc
+ 0x10019c06 0x2d _L1w_DevPcBeltaReCalcBeltaEdReducedMin
+ 0x10019c33 0x43 _L1w_DevPcBeltaReCalcEtfciBoost
+ 0x10019c76 0x97 _L1w_DevPcBeltaReCalc
+ 0x10019d0d 0x21 _L1w_DevPcMaxPowerLimit
+ 0x10019d2e 0x14 _L1w_DevPcMinPowerLimit
+ 0x10019d42 0xe0 _L1w_DevPcCMInfoUpdate
+ 0x10019e22 0x46 _L1w_DevPcFrmEventHandle
+ 0x10019e68 0x51 _L1w_DevPcPreCalc
+ 0x10019eb9 0x63 _L1w_DevPcStopHandle
+ 0x10019f1c 0xdd _L1w_DevPc3SymbolIntHandle
+ 0x10019ff9 0x4d _L1w_DevPcGaintorCalc
+ 0x1001a046 0x46 _L1w_DevPcTpuTpcSlotHandle
+ 0x1001a08c 0x1c _L1w_DevPcSlotModeGet
+ 0x1001a0a8 0x15 _L1w_DevPcDlGapPatternJudge
+ 0x1001a0bd 0x9 _L1w_DevPcWriteCmBitMap
+ 0x1001a0c6 0xa _L1w_DevPcIsUlCmFrm
+ 0x1001a0d0 0x15 _L1w_DevPcIsCmFrmOnlyGap
+ 0x1001a0e5 0x2d _L1w_DevPcIsCmFrm
+ 0x1001a112 0x7a _L1w_DevPcSlotModeSet
+ 0x1001a18c 0x2d _L1w_DevPcUlCmInfoHandle
+ 0x1001a1b9 0x24 _L1w_DevPcDlCmInfoHandle
+ 0x1001a1dd 0x48 _L1w_DevPcCmStopHandle
+ 0x1001a225 0x12 _L1w_DevPcCmStopReqHandle
+ 0x1001a237 0x32 _L1w_DevPcStopReqHandle
+ 0x1001a269 0x11c _L1w_DevPcWriteSubFrmIntInfo
+ 0x1001a385 0x74 _L1w_DevPcReset
+ 0x1001a3f9 0xcb _L1w_DevPcInit
+ 0x1001a4c4 0x7b _L1w_DevPcOutSyncEng
+ 0x1001a53f 0xef _L1w_DevPcEngPrintf
+ 0x1001a62e 0x63 _L1w_DevPcWriteDpramMsg
+ 0x1001a691 0x27 _L1w_DevPcResetCnf
+ 0x1001a6b8 0x27 _L1w_DevPcInitCnf
+ 0x1001a6df 0x2c _L1w_DevRtxPcPrachStartReq
+ 0x1001a70b 0x28 _L1w_DevRtxPcPrachPreambleReq
+ 0x1001a733 0x30 _L1w_DevRtxPcPrachMessageReq
+ 0x1001a763 0x39 _L1w_DevRtxPcDchStartReq
+ 0x1001a79c 0x2c _L1w_DevRtxPcUlDpchCmInfoReq
+ 0x1001a7c8 0x2c _L1w_DevRtxPcDlDpchCmInfoReq
+ 0x1001a7f4 0x29 _L1w_DevRtxPcDpchCmStopReq
+ 0x1001a81d 0x2e _L1w_DevRtxPcBlerReq
+ 0x1001a84b 0x2d _L1w_DevHsdpaPcStartReq
+ 0x1001a878 0x28 _L1w_DevHsdpaPcTtiReq
+ 0x1001a8a0 0x21 _L1w_DevHsdpaPcStoptReq
+ 0x1001a8c1 0x11 _L1w_DevDchPcSetPara
+ 0x1001a8d2 0x2a _L1w_DevHsupaPcStartReq
+ 0x1001a8fc 0x2d _L1w_DevHsupaPcTtiReq
+ 0x1001a929 0x21 _L1w_DevHsupaPcStopReq
+ 0x1001a94a 0x11f _L1w_PcTask
+ .text 0x1001aa69 0x29a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x1001aa69 0x1 _L1w_DevEngInitAddr
+ 0x1001aa6a 0x19 _L1w_EngTaskInit
+ 0x1001aa83 0x7 _L1w_DevEngSetFlag
+ 0x1001aa8a 0x12 _L1w_log_track_init
+ 0x1001aa9c 0x8e _L1w_DevEngDisplay
+ 0x1001ab2a 0x46 _L1w_EngTrace
+ 0x1001ab70 0xaa _L1w_DevEngLogHeaderUpdate
+ 0x1001ac1a 0xc6 _L1w_DevEngWriteDataToBuffer
+ 0x1001ace0 0x22 _L1w_DevEngCopyMem2Dpram
+ 0x1001ad02 0x1 _L1w_DevEngUartTransmit
+ .text 0x1001ad03 0xde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ 0x1001ad03 0x9 _L1w_DevTxFirstTpuIntSet
+ 0x1001ad0c 0xc _L1w_DevTxFirstTpuIntDelete
+ 0x1001ad18 0x82 _L1w_DevRtxTxCfgMsgHandle
+ 0x1001ad9a 0x16 _L1w_DevTxTpuIntHandle
+ 0x1001adb0 0x15 _L1w_DevRtxTxReset
+ 0x1001adc5 0x1c _L1w_DevRtxTxInit
+ .text 0x1001ade1 0x1cc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x1001ade1 0x6b _L1w_DevRtxRxBlindAnalyse
+ 0x1001ae4c 0x77 _L1w_DevRtxRxTfcParaCalc
+ 0x1001aec3 0xd5 _L1w_DevRtxRxJudgeCsRam
+ 0x1001af98 0x115 _L1w_DevRtxRxTrchParaCalc
+ 0x1001b0ad 0x33 _L1w_DevRtxRxDtrCtfcSort
+ 0x1001b0e0 0x81 _L1w_DevRtxRxSccpchDtrParam
+ 0x1001b161 0x3b _L1w_DevRtxRxJudgeRrm
+ 0x1001b19c 0x2f _L1w_DevRtxRxV3BlindTbs49Change
+ 0x1001b1cb 0x25 _L1w_DevRtxRxV3BlindTbsChange
+ 0x1001b1f0 0xc4 _L1w_DevRtxRxV3BlindTfcPatch
+ 0x1001b2b4 0xd2 _L1w_DevRtxRxDpchDtrParam
+ 0x1001b386 0x11 _L1w_DevRtxRxTtiModeGet
+ 0x1001b397 0xe _L1w_DevRtxRxCrcModeGet
+ 0x1001b3a5 0x16 _L1w_DevRtxRxCodingGet
+ 0x1001b3bb 0x89 _L1w_DevRtxRxTrchInfoCfg
+ 0x1001b444 0x51 _L1w_DevRtxRxDpchDtrCmCfg
+ 0x1001b495 0x74 _L1w_DevRtxRxDlDpchDtrCfg
+ 0x1001b509 0x6d _L1w_DevRtxRxDlSccpchDtrCfg
+ 0x1001b576 0x36 _L1w_DevRtxRxAgchDtrCfg
+ 0x1001b5ac 0x83 _L1w_DevRtxRxAgchCmDtrCfg
+ 0x1001b62f 0x45 _L1w_DevRtxRxCfgABUpdate
+ 0x1001b674 0x34 _L1w_DevRtxRxDeilBaseSort
+ 0x1001b6a8 0x9f _L1w_DevRtxRxTfciS2Cfg
+ 0x1001b747 0xb1 _L1w_DevRtxRxTfcAnalyse
+ 0x1001b7f8 0x58 _L1w_DevRtxRxBlindGuidCfg
+ 0x1001b850 0x37 _L1w_DevRtxRxPn9BerCheckStart
+ 0x1001b887 0xa1 _L1w_DevRtxRxPn9Get244Bit
+ 0x1001b928 0x42 _L1w_DevRtxRxPn9BerRltReport
+ 0x1001b96a 0xc5 _L1w_DevRtxRxPn9DataCheck
+ 0x1001ba2f 0x81 _L1w_DevRtxRxAllBlindHandle
+ 0x1001bab0 0xda _L1w_DevRtxRxBlindDtrCfg
+ 0x1001bb8a 0x17a _L1w_DevRtxRxBlindCrcHandle
+ 0x1001bd04 0xc3 _L1w_DevRtxRxBlindDataHandle
+ 0x1001bdc7 0x21 _L1w_DevRtxRxBlindStateCheck
+ 0x1001bde8 0xeb _L1w_DevRtxRxBlindTfcAnalyse
+ 0x1001bed3 0x3a _L1w_DevRtxRxTfcDataCmpHandle
+ 0x1001bf0d 0x38 _L1w_DevRtxRxTfciFWHT
+ 0x1001bf45 0x126 _L1w_DevRtxRxTfciCoding
+ 0x1001c06b 0x1f1 _L1w_DevRtxRxTfciIntHandle
+ 0x1001c25c 0x18 _L1w_DevRtxRxGetGsmVal
+ 0x1001c274 0x76 _L1w_DevRtxRxCmpPchUeId
+ 0x1001c2ea 0x55 _L1w_DevRtxRxPchUeIdHandle
+ 0x1001c33f 0x114 _L1w_DevRtxRxTtiBlindHandle
+ 0x1001c453 0xab _L1w_DevRtxRxTrchCrcStatic
+ 0x1001c4fe 0xbd _L1w_DevRtxRxTtiCrcStatic
+ 0x1001c5bb 0xb _L1w_DevRtxRxTtiCrcStatForAfc
+ 0x1001c5c6 0x63 _L1w_DevRtxRxTtiTrchInfoHandle
+ 0x1001c629 0x8d _L1w_DevRtxRxTtiBdTrchInfoHandle
+ 0x1001c6b6 0x64 _L1w_DevRtxRxNoBdTtiHandle
+ 0x1001c71a 0x54 _L1w_DevRtxRxBlindTtiHandle
+ 0x1001c76e 0x49 _L1w_DevRtxRxPchTtiHandle
+ 0x1001c7b7 0x68 _L1w_DevRtxRxTtiIntAfterHandle
+ 0x1001c81f 0x25e _L1w_DevRtxRxTtiIntHandle
+ 0x1001ca7d 0x24 _L1w_DevRtxRxDtrRel
+ .text 0x1001caa1 0x5db T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ 0x1001caa1 0x8b _L1w_DevHsdpaCqiCalcPos
+ 0x1001cb2c 0x1b1 _L1w_DevHsdpaCalcCqiSnr
+ 0x1001ccdd 0x6b _L1w_DevHsdpaSnrLimitAdj
+ 0x1001cd48 0xbf _L1w_DevHsdpaCqiSnrAdj
+ 0x1001ce07 0x68 _L1w_DevHsdpaCalcSnrVal
+ 0x1001ce6f 0x20d _L1w_DevHsdpaSnrMapToCqiVal
+ .text 0x1001d07c 0x2f5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ 0x1001d07c 0x5b _L1w_DevRtxRxPcchBitRead
+ 0x1001d0d7 0x3e _L1w_DevRtxRxImsiGsm
+ 0x1001d115 0x2f _L1w_DevRtxRxTmsiGsm
+ 0x1001d144 0x2f _L1w_DevRtxRxPTmsiGsm
+ 0x1001d173 0xf _L1w_DevRtxRxImsiDs41
+ 0x1001d182 0xf _L1w_DevRtxRxTmsiDs41
+ 0x1001d191 0x3d _L1w_DevRtxRxPagRecCnId
+ 0x1001d1ce 0x44 _L1w_DevRtxRxPagRecUtranId
+ 0x1001d212 0x4e _L1w_DevRtxRxPagRec2UtranSingUeId
+ 0x1001d260 0x28 _L1w_DevRtxRxPagRec2UtranGrpId
+ 0x1001d288 0x28 _L1w_DevRtxRxPagingRecList
+ 0x1001d2b0 0x28 _L1w_DevRtxRxPagingRec2ListR5
+ 0x1001d2d8 0x12 _L1w_DevRtxRxPagingV590ExtIE
+ 0x1001d2ea 0x10 _L1w_DevRtxRxPagingV860ExtIE
+ 0x1001d2fa 0x47 _L1w_DevRtxRxPagingType1
+ 0x1001d341 0x19 _L1w_DevRtxRxPcchMsgType
+ 0x1001d35a 0x17 _L1w_DevRtxRxDecodePcch
+ .text 0x1001d371 0x18da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x1001d371 0x22 _L1w_HspaCalcMod
+ 0x1001d393 0xb _L1w_DevHsupaEdchReadyInit
+ 0x1001d39e 0x11 _L1w_DevHsupaInitUlDataInfo
+ 0x1001d3af 0x18 _L1w_DevHsupaUlReset
+ 0x1001d3c7 0x5c _L1w_DevHsupaParaInit
+ 0x1001d423 0x45 _L1w_DevHsupaInit
+ 0x1001d468 0x15 _L1w_DevHsupaHwRel
+ 0x1001d47d 0x8f _L1w_DevHsupaReset
+ 0x1001d50c 0x5f _L1w_DevHsupaGetDlChanInfo
+ 0x1001d56b 0x34 _L1w_DevHsupaCalcDisEagchEdch
+ 0x1001d59f 0x10 _L1w_DevHsupaCalcDisEhichEdch
+ 0x1001d5af 0x21 _L1w_DevHsupaCalcDisErgchEdch
+ 0x1001d5d0 0x1a _L1w_DevHsupaCalcInitNo
+ 0x1001d5ea 0x3a _L1w_DevHsupaCalcInitSwNo
+ 0x1001d624 0x64 _L1w_DevHsupaCalcIscpSlotId
+ 0x1001d688 0x9a _L1w_DevHsupaCalcDlChanInitNo
+ 0x1001d722 0x5e _L1w_DevHsupaConfigReq
+ 0x1001d780 0x2b _L1w_DevHsupaCpEdpdchInfo
+ 0x1001d7ab 0x3d _L1w_DevHsupaCpErntiInfo
+ 0x1001d7e8 0x65 _L1w_DevHsupaCpRxEagchCfg
+ 0x1001d84d 0x42 _L1w_DevHsupaRtxEagchCfg
+ 0x1001d88f 0x8 _L1w_DevHsupaGetErgchFrameType
+ 0x1001d897 0x7e _L1w_DevHsupaCpRxRgHiCfg
+ 0x1001d915 0x77 _L1w_DevHsupaRtxRgHiCfg
+ 0x1001d98c 0x23 _L1w_DevHsupaRtxCfg
+ 0x1001d9af 0xca _L1w_DevHsupaCpDlRcvInfo
+ 0x1001da79 0x20 _L1w_DevHsupaCfgTxInit
+ 0x1001da99 0x22 _L1w_DevHsupaEagchInt2Ps
+ 0x1001dabb 0x97 _L1w_DevHsupaCalAgRgHiIntNo
+ 0x1001db52 0x4f _L1w_DevHsupaNorm2TpuBase
+ 0x1001dba1 0x79 _L1w_DevHsupaFachNt2CfnTime
+ 0x1001dc1a 0x84 _L1w_DevHsupaSaveTpuTime
+ 0x1001dc9e 0x2d _L1w_DevHsupaCalcSwTtiCntIntOff
+ 0x1001dccb 0x73 _L1w_DevHsupaGetCfnTime
+ 0x1001dd3e 0x25 _L1w_DevHsupaCalcSwTtiCntIntOn
+ 0x1001dd63 0x114 _L1w_DevHsupaEagchIntProc
+ 0x1001de77 0x18 _L1w_DevHsupaEagchIntInd
+ 0x1001de8f 0x4c _L1w_DevHuspaSaveAG
+ 0x1001dedb 0x12 _L1w_DevHuspaUpaTransFlgToMac
+ 0x1001deed 0x1c _L1w_DevHuspaGrantHarqToMac
+ 0x1001df09 0xb9 _L1w_DevHsupaReportPsStatistic
+ 0x1001dfc2 0x65 _L1w_DevHsupaStdlogThroughput
+ 0x1001e027 0x82 _L1w_DevHsupaStdlogPacketInfo
+ 0x1001e0a9 0x40 _L1w_DevHsupaReportToMac
+ 0x1001e0e9 0x71 _L1w_DevHsupaRptHarqFlag
+ 0x1001e15a 0x5b _L1w_DevHsupaDchIsMacTrans
+ 0x1001e1b5 0x14 _L1w_DevHsupaFachIsMacTrans
+ 0x1001e1c9 0x22 _L1w_DevHsupaIsMacTrans
+ 0x1001e1eb 0x37 _L1w_DevHsupaPcCfg
+ 0x1001e222 0x1 _L1w_DevHsupaAgRgHiIndCallBack
+ 0x1001e223 0x3a _L1w_DevHsupaAddTpu
+ 0x1001e25d 0x9 _L1w_DevHsupaGetPhyMinSfMaxChan
+ 0x1001e266 0x9e _L1w_DevHsupaDisplayCfgInfo
+ 0x1001e304 0x6a _L1w_DevHsupaSaveStdlogPacket
+ 0x1001e36e 0x35 _L1w_DevHsupaCfgToPsrInd
+ 0x1001e3a3 0x125 _L1w_DevHsupaConfigProc
+ 0x1001e4c8 0x2c _L1w_DevHsupaIcpIntInd
+ 0x1001e4f4 0x2c _L1w_DevHsupaEdcpIntInd
+ 0x1001e520 0x59 _L1w_DevHsupaIcpIntProc
+ 0x1001e579 0xea _L1w_DevHsupaEdcpIntProc
+ 0x1001e663 0x26 _L1w_DevHsupaCfgPcTti
+ 0x1001e689 0x2c _L1w_DevHsupaEtxIntInd
+ 0x1001e6b5 0x2d _L1w_DevHsupaCalcNtx1Info
+ 0x1001e6e2 0x23 _L1w_DevHsupaCmInfoClr
+ 0x1001e705 0xf1 _L1w_DevHsupaEtxIntProc
+ 0x1001e7f6 0x21 _L1w_DevHsupaRelReq
+ 0x1001e817 0xf _L1w_DevHsupaRtxRelReq
+ 0x1001e826 0x4e _L1w_DevHsupaReleaseProc
+ 0x1001e874 0xc _L1w_DevHsupaIfHarqIdValid
+ 0x1001e880 0x66 _L1w_DevHsupaTestCurFrameNum
+ 0x1001e8e6 0x37 _L1w_DevHsupaCalcEdchCfn
+ 0x1001e91d 0x2a _L1w_DevHsupaGetCurFrameNum
+ 0x1001e947 0x2d _L1w_DevHsupaCalcNextTtiFrameNum
+ 0x1001e974 0x2b _L1w_DevHsupaCmPatternUpdateReq
+ 0x1001e99f 0x5c _L1w_DevHsupaCalcDlCm
+ 0x1001e9fb 0x69 _L1w_DevHsupaCmPatternUpdateProc
+ 0x1001ea64 0x31 _L1w_DevHsupaCalChLen
+ 0x1001ea95 0x7 _L1w_DevHsupaSetHsdschCfg
+ 0x1001ea9c 0x77 _L1w_DevHsupaActive
+ 0x1001eb13 0xf1 _L1w_DevHsupaTpuProc
+ 0x1001ec04 0x3b _L1w_DevHsupaTransIndProc
+ 0x1001ec3f 0xc _L1w_DevHsupaIsDchActive
+ .text 0x1001ec4b 0x18b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ 0x1001ec4b 0xb _L1w_DevRtxRxIntDataInit
+ 0x1001ec56 0x13 _L1w_DevRtxRxIntReset
+ 0x1001ec69 0x12 _L1w_DevRtxRxFix2Sword32
+ 0x1001ec7b 0x13 _L1w_DevRtxRxFix2Sword16
+ 0x1001ec8e 0x6e _L1w_DevRtxRxRcvFingerSlotwt
+ 0x1001ecfc 0x38 _L1w_DevRtxRxRcvFingerAfc
+ 0x1001ed34 0x5b _L1w_DevRtxRxRcvFingerNoise
+ 0x1001ed8f 0x27 _L1w_DevRtxRxCalcFingerIscp
+ 0x1001edb6 0x9c _L1w_DevRtxRxRcvOffLInePiResult
+ 0x1001ee52 0x88 _L1w_DevRtxRxRcvPiData
+ 0x1001eeda 0xcc _L1w_DevRtxRxPichIntHandle
+ 0x1001efa6 0x25 _L1w_DevRtxRxGetBuffIdx
+ 0x1001efcb 0xb2 _L1w_DevRtxRxRcvAiData
+ 0x1001f07d 0xdd _L1w_DevRtxRxCalcAiCpichPower
+ 0x1001f15a 0x51 _L1w_DevRtxRxCalcAiCpichPrIIR
+ 0x1001f1ab 0x10 _L1w_DevRtxRxGetAiDeltaPac
+ 0x1001f1bb 0x31 _L1w_DevRtxRxCalcAiThreshold
+ 0x1001f1ec 0x24 _L1w_DevRtxRxCalcAiSignCorr
+ 0x1001f210 0x26 _L1w_DevRtxRxCalcAiVal
+ 0x1001f236 0x26 _L1w_DevRtxRxAiDataPreHandle
+ 0x1001f25c 0x2e _L1w_DevRtxRxEAiResCfgMap
+ 0x1001f28a 0x4b _L1w_DevRtxRxNewCalcAiVal
+ 0x1001f2d5 0x5e _L1w_DevRtxRxNewEAiCalc
+ 0x1001f333 0x122 _L1w_DevRtxRxNewAichIntHandle
+ 0x1001f455 0x2b _L1w_DevRtxRxCalcFbiFingerPr
+ 0x1001f480 0x34 _L1w_DevRtxRxCalcFbiRlPr
+ 0x1001f4b4 0xed _L1w_DevRtxRxCalcFbiTotalPr
+ 0x1001f5a1 0x23 _L1w_DevRtxRxCalcFbiValue
+ 0x1001f5c4 0xc6 _L1w_DevRtxRxCalcFbi
+ 0x1001f68a 0x4a _L1w_DevRtxRxIntParaUpdate
+ 0x1001f6d4 0x6 _L1w_DevRtxRxGetTpcIData
+ 0x1001f6da 0x5 _L1w_DevRtxRxGetTpcQData
+ 0x1001f6df 0x6 _L1w_DevRtxRxGetTpcIExp
+ 0x1001f6e5 0x5 _L1w_DevRtxRxGetTpcQExp
+ 0x1001f6ea 0x58 _L1w_DevRtxRxDchTpcSirCalc
+ 0x1001f742 0xcf _L1w_DevRtxRxDchTpcIntHandle
+ 0x1001f811 0x9 _L1w_DevRtxRxDchPilotIntHandle
+ 0x1001f81a 0x6f _L1w_DevRtxRxFdpchTpcIntHandle
+ 0x1001f889 0x46 _L1w_DevRtxRxTpcIntHandle
+ 0x1001f8cf 0x4c _L1w_DevRtxRxFactorCheck
+ 0x1001f91b 0x84 _L1w_DevRtxRxFactorDataGet
+ 0x1001f99f 0x44 _L1w_DevRtxRxFactorHandle
+ 0x1001f9e3 0x61 _L1w_DevRtxRxAgchFactorHandle
+ 0x1001fa44 0x50 _L1w_DevRtxRxSccpchFactorCalc
+ 0x1001fa94 0x13b _L1w_DevRtxRxPchFactorHandle
+ 0x1001fbcf 0x109 _L1w_DevRtxRxFachFactorHandle
+ 0x1001fcd8 0x2f _L1w_DevRtxRxCalcIscp
+ 0x1001fd07 0x1dd _L1w_DevRtxRxFingerDataHandle
+ 0x1001fee4 0x8a _L1w_DevRtxRxNoiseDataCheck
+ 0x1001ff6e 0x67 _L1w_DevRtxRxSetAfcInfo
+ 0x1001ffd5 0x119 _L1w_DevRtxRxCpich2ndFingerPrint
+ 0x100200ee 0xf3 _L1w_DevRtxRxCpichTpuIntPrint
+ 0x100201e1 0xea _L1w_DevRtxRxCpichTpuIntAllPrint
+ 0x100202cb 0x5a _L1w_DevRtxRxCpichTpuIntIscpErrPrint
+ 0x10020325 0x45 _L1w_DevRtxRxCpichTpuIntUpaParaUpdate
+ 0x1002036a 0x167 _L1w_DevRtxRxCpichTpuIntHandle
+ 0x100204d1 0x1 _L1w_DevRtxRxPilotIntHandle
+ 0x100204d2 0x2c _L1w_DevRtxRxIntHandle
+ .text 0x100204fe 0x3556 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x100204fe 0x5 _L1w_DevDlsPsrReset
+ 0x10020503 0xb8 _L1w_DevDlsintialGlobalVariable
+ 0x100205bb 0x30 _L1w_DevDlsPsrIntialHardWare
+ 0x100205eb 0x8 _L1w_DevDlsPsrIntial
+ 0x100205f3 0xd _L1w_DevDlsSaveOldUlTiming
+ 0x10020600 0x64 _L1w_DevDlsStop
+ 0x10020664 0x3a _L1w_DevPsrIntEventProc
+ 0x1002069e 0x35 _L1w_DevPsrSendTimingInfoToL1s
+ 0x100206d3 0x3d _L1w_DevPsrAddTpuFixedEvent
+ 0x10020710 0x27 _L1w_DevPsrDchStopReq
+ 0x10020737 0x39 _L1w_DevPsrMeasStartReq
+ 0x10020770 0x12d _L1w_DevPsrDchJudgeNcellSave
+ 0x1002089d 0x177 _L1w_DevPsrSetRlNcellFlag
+ 0x10020a14 0x36 _L1w_DevPsrEfachStartReq
+ 0x10020a4a 0x32 _L1w_DevPsrEfachFdpchOffsetReq
+ 0x10020a7c 0x22 _L1w_DevPsrEfachStopReq
+ 0x10020a9e 0x25 _L1w_DevPsrFmoStopReq
+ 0x10020ac3 0x3b _L1w_DevDlsPsrHsdpaReq
+ 0x10020afe 0x32 _L1w_DevPsrDchUpaExistReq
+ 0x10020b30 0x6c _L1w_DevPsrEfachUlDpcchFBConfig
+ 0x10020b9c 0x54 _L1w_DevPsrUlDpcchFBConfig
+ 0x10020bf0 0x1 _L1w_DevPsrCommParaCfg
+ 0x10020bf1 0x3c _L1w_DevPsrSaveCmInfo
+ 0x10020c2d 0x21 _L1w_DevPsrTransDpchCm2Cpich
+ 0x10020c4e 0xa8 _L1w_DevPsrRtxFirstFingerConfigS
+ 0x10020cf6 0x196 _L1w_DevPsrSelectMasterRl
+ 0x10020e8c 0x6c _L1w_DevPsrSaveLastTimingTrace
+ 0x10020ef8 0x110 _L1w_DevPsrDchSelectUpaCell
+ 0x10021008 0x160 _L1w_DevPsrDchConfigHardware
+ 0x10021168 0xf8 _L1w_DevPsrDchReqConfig
+ 0x10021260 0xfa _L1w_DevPsrHardWorkTimeConfig
+ 0x1002135a 0x53 _L1w_DevPsrRlPosAndCodeConfig
+ 0x100213ad 0xc8 _L1w_DevPsrFachReqConfig
+ 0x10021475 0x29 _L1w_DevDlsCalcHandOverNtAdjPos
+ 0x1002149e 0x2f _L1w_DevDlsCalcAdjPos
+ 0x100214cd 0x1d9 _L1w_DevDlsCalcRegConfigTimingAndReport
+ 0x100216a6 0x15a _L1w_DevDlsCalcRlTimingAndReport
+ 0x10021800 0x58 _L1w_DevDlsPsrUpdateULInfo
+ 0x10021858 0x125 _L1w_DevDlsFachTimingMaintain
+ 0x1002197d 0x1c _L1w_DevDlsTimingMaintain
+ 0x10021999 0x34 _L1w_DevDlsDchJudgeAdustSpeed
+ 0x100219cd 0x42 _L1w_DevDlsDchTimingMaintain
+ 0x10021a0f 0x48 _L1w_DevDlsPsrSelectDpaId
+ 0x10021a57 0x63 _L1w_DevDlsPsrChangeDpaIdCell
+ 0x10021aba 0xc8 _L1w_DevDlsPsrGetAntNumAndJudgeConfig
+ 0x10021b82 0xa _L1w_DevDlsPsrClearCopyFingernfo
+ 0x10021b8c 0x3a _L1w_DevDlsPsrDpaIsChangjing1
+ 0x10021bc6 0x11a _L1w_DevDlsPsrJudgeFingerOver512
+ 0x10021ce0 0x2df _L1w_DevDlsPsrWholeHandleS
+ 0x10021fbf 0x24 _L1w_DevPsrTpuIntHandle
+ 0x10021fe3 0x4a _L1w_DevPsrRlCpichTimingAdujst
+ 0x1002202d 0x5b _L1w_DevPsrSoftHandOverTimingAdj
+ 0x10022088 0x5a _L1w_DevPsrIsCmCfgBug
+ 0x100220e2 0x66 _L1w_DevPsrCmHandle
+ 0x10022148 0x50 _L1w_DevPsrCalcRlsTxRxTimeDiff
+ 0x10022198 0x9a _L1w_DevPsrTimingAdj
+ 0x10022232 0x182 _L1w_DevPsrUpdateRlPos
+ 0x100223b4 0x53 _L1w_DevPsrFmoHandle
+ 0x10022407 0x170 _L1w_DevPsrRdPeakInfoS
+ 0x10022577 0xaf _L1w_DevDlsPsrSidelobeSurp
+ 0x10022626 0x10 _L1w_DevDlsPsrFingerSidelobeSurp
+ 0x10022636 0xb2 _L1w_DevDlsPsrCorasePathDetect
+ 0x100226e8 0x3d _L1w_DevDlsPsrFindStrongFiger
+ 0x10022725 0x46 _L1w_DevDlsPsrUpdateFigerTable
+ 0x1002276b 0x152 _L1w_DevDlsPsrStrongFigerPathDetect
+ 0x100228bd 0x149 _L1w_DevDlsPsrPathDect
+ 0x10022a06 0x3b _L1w_DevPsrRssiNormal
+ 0x10022a41 0x99 _L1w_DevDlsPsrUpdateFingerPos
+ 0x10022ada 0x12 _L1w_DevDlsPsrCalcMrtrDiff
+ 0x10022aec 0x23 _L1w_DevDlsPsrCalcMrtrAver
+ 0x10022b0f 0x31 _L1w_DevDlsPsrSortMinRange
+ 0x10022b40 0x31 _L1w_DevDlsPsrSortMinRange1
+ 0x10022b71 0x70 _L1w_DevDlsPsrSynProtect
+ 0x10022be1 0x24 _L1w_DevPsrBackWardProtect
+ 0x10022c05 0x26 _L1w_DevPsrForwardProtect
+ 0x10022c2b 0x19b _L1w_DevDlsPsrFingerPeakUpdate
+ 0x10022dc6 0x18 _L1w_DevPsrSortMinValue
+ 0x10022dde 0x18 _L1w_DevDlsPsrSortMaxValue
+ 0x10022df6 0x14c _L1w_DevPsrCandidatefingerUpdate
+ 0x10022f42 0xb3 _L1w_DevDlsPsrFingerPeakSelect
+ 0x10022ff5 0x72 _L1w_DevDlsPsrCalcDpchTiming
+ 0x10023067 0x2f _L1w_DevPsrFinPeakNormal
+ 0x10023096 0x38 _L1w_DevPsrAntFinPeakNormal
+ 0x100230ce 0x3b _L1w_DevDlsPsrSelectValidFinger
+ 0x10023109 0x98 _L1w_DevDlsPsrCalcDpchBaseTiming
+ 0x100231a1 0x47 _L1w_DevDlsPsrSortRtxFinger
+ 0x100231e8 0xb _L1w_DevPsrGetDchStartPsrFlag
+ 0x100231f3 0x150 _L1w_DevDlsPsrSelectRtxFinger
+ 0x10023343 0x93 _L1w_DevDlsPsrSelectNcellFinger
+ 0x100233d6 0xc8 _L1w_DevDlsPsrSortDpaFirst
+ 0x1002349e 0xf6 _L1w_DevDlsPsrNewFingerMapping
+ 0x10023594 0xd4 _L1w_DevDlsPsrAdrWindowUpdateS
+ 0x10023668 0xc _L1w_DevDlsPsrSendAdrFingerInfoS
+ 0x10023674 0xd0 _L1w_DevPsrSelSeaWindowFinInfoS
+ 0x10023744 0x47 _L1w_DevPsrSelNewSearchWindowS
+ 0x1002378b 0x21 _L1w_DevPsrIsSearchWindowPath
+ 0x100237ac 0x28 _L1w_DevPsrCalcSearchWindowSum
+ 0x100237d4 0x15 _L1w_DevDlsPsrCalcFingerPeakSum
+ 0x100237e9 0x38 _L1w_DevPsrSortFirstFinger
+ 0x10023821 0x23 _L1w_DevDlscalcPosOff
+ 0x10023844 0x1e3 _L1w_DevDlsChangedMasterRlTiming
+ 0x10023a27 0x13 _L1w_DevDlsPsrFingerCmp
+ 0x10023a3a 0x12 _L1w_DevDlsPsrFingerLessThan
+ 0x10023a4c 0x8 _TestZero
+ .text 0x10023a54 0x5c1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ 0x10023a54 0x8 _L1w_DevHsupaFachFdpchOffset
+ 0x10023a5c 0xb _L1w_DevHsupaIsEfachActive
+ 0x10023a67 0x35 _L1w_DevHsupaRtxEdchResInd
+ 0x10023a9c 0x16 _L1w_DevHsupaFachToPsrInd
+ 0x10023ab2 0x52 _L1w_DevHsupaFachConfigReq
+ 0x10023b04 0x3c _L1w_DevHsupaFachCpErntiInfo
+ 0x10023b40 0xa5 _L1w_DevHsupaFachConfigProc
+ 0x10023be5 0x21 _L1w_DevHsupaFachRelReq
+ 0x10023c06 0x46 _L1w_DevHsupaFachRelProc
+ 0x10023c4c 0x26 _L1w_DevHsupaErntiUpdateReq
+ 0x10023c72 0x24 _L1w_DevHsupaErntiUpdateProc
+ 0x10023c96 0x21 _L1w_DevHsupaFachNoDataReq
+ 0x10023cb7 0x7e _L1w_DevHsupaFachNoDataProc
+ 0x10023d35 0x96 _L1w_DevHsupaFachGetRgHiChanInfo
+ 0x10023dcb 0x4a _L1w_DevHsupaFachCfn2NetTime
+ 0x10023e15 0x9b _L1w_DevHsupaFachAddTpu2ms
+ 0x10023eb0 0x6b _L1w_DevHsupaFachAddTpu10ms
+ 0x10023f1b 0x22 _L1w_DevHsupaFachAddTpu
+ 0x10023f3d 0xe _L1w_DevHsupaFachIsMacInitTrans
+ 0x10023f4b 0x1d _L1w_DevHsupaFachAddTpuSubInt
+ 0x10023f68 0x88 _L1w_DevHsupaFachEdchResProc
+ 0x10023ff0 0x25 _L1w_DevHsupaFachReset
+ .text 0x10024015 0x182d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x10024015 0x21 _L1w_SetWmodeLpcMacroValue
+ 0x10024036 0x8 _L1w_DevSleepSetCfunFlg
+ 0x1002403e 0x13 _L1w_PosCmp
+ 0x10024051 0x1c _L1w_DevLpcDvfs
+ 0x1002406d 0x2b _L1W_DevSleepLpmInspectInit
+ 0x10024098 0x87 _L1w_DevUeTurnOn3sNoLpc
+ 0x1002411f 0xe _l1w_DevLpcSetAdjLpmFrmIntFlg
+ 0x1002412d 0xe _l1w_DevLpcGetAdjLpmFrmIntFlg
+ 0x1002413b 0xf _L1w_DevLpcSetSleepSubSt
+ 0x1002414a 0x10 _L1w_DevLpcGetSleepFlg
+ 0x1002415a 0x85 _L1w_DevLpcDpaRecover
+ 0x100241df 0x1f _L1w_DevLpcDrxRecover
+ 0x100241fe 0x93 _L1w_DevLpcClkDevCtrl
+ 0x10024291 0x3d _l1w_DevLpcClkInit
+ 0x100242ce 0x9e _L1w_DevLpcPwrDevCtrl
+ 0x1002436c 0x2d _l1w_DevLpcPwrInit
+ 0x10024399 0x7d _L1w_DevSleepNoLpc
+ 0x10024416 0xa2 _L1w_DevLpcLpmIntCheck
+ 0x100244b8 0x124 _L1w_DevLpcSendIcp
+ 0x100245dc 0x10 _L1w_DevLpcGetWakeUpType
+ 0x100245ec 0x2f _L1w_LpcRegionJudge
+ 0x1002461b 0x4a _L1w_DevLpcSerIdleLen
+ 0x10024665 0x6 _L1w_LpcGetLpcDbAddress
+ 0x1002466b 0x23 _L1w_LpcCalcLen
+ 0x1002468e 0x46 _L1w_LpcPosMove
+ 0x100246d4 0xb5 _L1w_DevLpcCalPreSyncInfo
+ 0x10024789 0x43 _L1w_DevLpcIsPiPchOffsetLen
+ 0x100247cc 0x1ac _L1w_SchedGapGetSleepEnLen
+ 0x10024978 0x77 _L1w_DevLpcCalSleepInfo
+ 0x100249ef 0x7b _L1W_DevLpcGetWSleepLen
+ 0x10024a6a 0x92 _L1w_DevLpcUpdateWakeFlg
+ 0x10024afc 0x14e _L1w_DevLpcSyncWkUpOpenRf
+ 0x10024c4a 0xa _L1w_DevSleepGetPiEndPos
+ 0x10024c54 0x7d _L1W_LPNoSleepAPeriod
+ 0x10024cd1 0x8f _L1W_DevLpcPwrPrintInfo
+ 0x10024d60 0x18 _L1w_DevSleepCloseIsAbleSleep
+ 0x10024d78 0x2a9 _L1W_DevSleepLpmInspect
+ 0x10025021 0x4f _L1w_DevLpcWakeTimeCheck
+ 0x10025070 0x9 _L1W_LPNoSleepEndSsfnInit
+ 0x10025079 0x5e _L1W_LPDataInit
+ 0x100250d7 0x71 _L1W_LPInit
+ 0x10025148 0x37 _L1W_LpcCfgSocWkupInt
+ 0x1002517f 0x1b _L1W_LpcDisSocWkupInt
+ 0x1002519a 0x16 _L1W_WakeupIsr
+ 0x100251b0 0x8 _L1W_GetNtSsfn
+ 0x100251b8 0x4 _L1w_DevSleepPreSyncPiOffset
+ 0x100251bc 0xd _L1W_DevSleepQueryAllowbit
+ 0x100251c9 0x335 _L1W_ModemLpcSleep
+ 0x100254fe 0x344 _L1W_ModemLpcWakeup
+ .text 0x10025842 0x1519 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x10025842 0x39 _L1w_DevDlsAfcReset
+ 0x1002587b 0x19 _L1w_DevDlsAfcInit
+ 0x10025894 0x56 _L1w_DevAfcBchCorrCalEachSlot
+ 0x100258ea 0x23 _L1w_DevAfcNormalToAfc
+ 0x1002590d 0x20 _L1w_DevAfcToNormal
+ 0x1002592d 0xf _L1w_DevAfcFormatCheck
+ 0x1002593c 0x6 _L1w_DevAfcSubFunc1ForAdd
+ 0x10025942 0x27 _L1w_DevAfcSubFunc2ForAdd
+ 0x10025969 0x75 _L1w_DevAfcAdd
+ 0x100259de 0x60 _L1w_DevAfcDiv
+ 0x10025a3e 0x24 _L1w_DevAfcMultip
+ 0x10025a62 0xf _L1w_DevAfcCompABS
+ 0x10025a71 0xfe _L1w_DevAfcCalcPhaseErr
+ 0x10025b6f 0x36 _L1w_DevAfcCalcFreqcenErr
+ 0x10025ba5 0x1c _L1w_DevAfcLockCheck
+ 0x10025bc1 0xa6 _L1w_DevAfcBchFoePostProc
+ 0x10025c67 0x44 _L1w_DevDlsAfcResultValid
+ 0x10025cab 0x31 _L1w_DevAfcFoeAdjResultLim
+ 0x10025cdc 0x42 _L1w_DevAfcFoeResultLimit
+ 0x10025d1e 0x1c _L1w_DevAfcIQFilterProc
+ 0x10025d3a 0x72 _L1w_DevAfcForBchProc
+ 0x10025dac 0x26 _L1w_DevAfcStateTransfer
+ 0x10025dd2 0x64 _L1w_DevAfcRxFoePostProc
+ 0x10025e36 0x13 _L1w_DevAfcCalcFingerPower
+ 0x10025e49 0xab _L1w_DevAfcFingerFoeAdp
+ 0x10025ef4 0x7b _L1w_DevAfcFingerSortByPeak
+ 0x10025f6f 0x27b _L1w_DevAfcForRxProc
+ 0x100261ea 0x27 _L1w_DevAfcSendFreqMsgToL1s
+ 0x10026211 0x29 _L1w_DevAfcBchReq
+ 0x1002623a 0x2c _L1w_DevAfcRxReq
+ 0x10026266 0x26 _L1w_DevAfcRxCrcFlagReq
+ 0x1002628c 0x28 _L1w_DevAfcStateChangeReq
+ 0x100262b4 0x97 _L1w_DevAfcRxDataAccu
+ 0x1002634b 0xa _L1w_DevAfcVcoTimeSet
+ 0x10026355 0xb5 _L1w_DevAfcCalcParam
+ 0x1002640a 0xd _L1w_DevAfcIsInStableSt
+ 0x10026417 0x11 _L1w_DevAfcRxCrcFlagProc
+ 0x10026428 0x37 _L1w_DevAfcLockHandle
+ 0x1002645f 0x4d _L1w_DevAfcNeedAdj
+ 0x100264ac 0x72 _L1w_DevAfcSaveStableVco
+ 0x1002651e 0x21 _L1w_DevAfcMasteStChange
+ 0x1002653f 0x11 _L1w_DevAfcGetRxCrc
+ 0x10026550 0x31 _L1w_DevAfcGetAfcCellEcIo
+ 0x10026581 0x43 _L1w_DevAfcRxDataReqProc
+ 0x100265c4 0x52 _L1w_DevAfcGetNCellAfcPt
+ 0x10026616 0xa _L1w_DevAfcGetSystemAfc
+ 0x10026620 0xb _L1w_DevAfcGetNCellAbsAfc
+ 0x1002662b 0x1b _L1w_DevAfcGetNCellRelativeAfc
+ 0x10026646 0x58 _L1w_DevAfcUpdateNCellAfc
+ 0x1002669e 0x8 _L1w_DevAfcSetWorkCellInfo
+ 0x100266a6 0xa _L1w_DevAfcGetWorkCellInfo
+ 0x100266b0 0x50 _L1w_DevAfcIsSystemAfc
+ 0x10026700 0xa2 _L1w_DevAfcNcellAfcPostProc
+ 0x100267a2 0x3 _L1w_DevAfcSetNCellAbsAfc
+ 0x100267a5 0xa5 _L1w_DevAfcRlsAloneProc
+ 0x1002684a 0x131 _L1w_DevAfcCalcRlOwnFoe
+ 0x1002697b 0xf _L1w_DevAfcClearNcellAfc
+ 0x1002698a 0x1e _L1w_DevAfcCalcFilterPara
+ 0x100269a8 0x66 _L1w_DevAfcDpaIqRotateProc
+ 0x10026a0e 0x1d _L1w_DevAfcNcellAdjLimit
+ 0x10026a2b 0xc _L1w_DevAfcNormDiffValue
+ 0x10026a37 0x11 _L1w_DevAfcSaveDpaInfo
+ 0x10026a48 0x38 _L1w_DevAfcSetDpaIqRotate
+ 0x10026a80 0x4f _L1w_DevAfcCalcSlotWeight
+ 0x10026acf 0x15 _L1w_DevAfcInitNcellData
+ 0x10026ae4 0x2e _L1w_DevAfcNcellUpByEcIo
+ 0x10026b12 0x1f _L1w_DevAfcRestartReq
+ 0x10026b31 0x22 _L1w_DevAfcRestartLockCheck
+ 0x10026b53 0x29 _L1w_DevAfcWriteBackVco
+ 0x10026b7c 0x4f _L1w_DevAfcSaveWMode
+ 0x10026bcb 0xa7 _L1w_DevAfcSlaveAfcMangement
+ 0x10026c72 0x15 _L1w_DevAfcLimitSlaveVco
+ 0x10026c87 0x15 _L1w_CleanSlaveAfcIRAMBuf
+ 0x10026c9c 0x32 _L1w_WriteMasterAfcInfo
+ 0x10026cce 0x20 _L1w_ReadMasterAfcInfo
+ 0x10026cee 0x6d _L1w_DevChangeAndUpdateAfc
+ .text 0x10026d5b 0xf2e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x10026d5b 0x129 _L1w_DevTpuRt1SampleCompst
+ 0x10026e84 0x77 _L1w_DevTpuReset
+ 0x10026efb 0x10 _L1w_DevTpuTaskIdTransForm
+ 0x10026f0b 0x5e _L1w_DevTpuAddFixedEvent
+ 0x10026f69 0x1a _L1w_DevTpuAddFixedCycleEvent
+ 0x10026f83 0x15 _L1w_DevTpuDelFixedCycleEvent
+ 0x10026f98 0x21 _L1w_DevTpuUpdateVarNtEvent
+ 0x10026fb9 0x20 _L1w_DevTpuUpdateVarRtEvent
+ 0x10026fd9 0xfd _L1w_DevTpuAddVarNtEvent
+ 0x100270d6 0xdf _L1w_DevTpuAddVarRtEvent
+ 0x100271b5 0x46 _L1w_DevTpuDelFixedEvent
+ 0x100271fb 0x62 _L1w_DevTpuDelVarNtEvent
+ 0x1002725d 0x3e _L1w_DevTpuDelVarRtEvent
+ 0x1002729b 0x65 _L1w_DevTpuGetRealTime
+ 0x10027300 0x8e _L1w_DevTpuGetRtForWakeUp
+ 0x1002738e 0x50 _L1w_DevTpuGetNetTime
+ 0x100273de 0xa4 _L1w_DevTpuGetAllTime
+ 0x10027482 0x80 _L1w_DevTpuNtFixedEventProc
+ 0x10027502 0xdd _L1w_DevTpuNtVarEventProc
+ 0x100275df 0xf6 _L1w_DevTpuRtEventProc
+ 0x100276d5 0x59 _L1w_DevTpuMacroAdjust
+ 0x1002772e 0x56 _L1w_DevTpuMicroAdjust
+ 0x10027784 0x1a _L1w_DevTpuMicroAdjustForSleep
+ 0x1002779e 0x56 _L1w_DevTpuMicroAdjSetPreSyncFlag
+ 0x100277f4 0x5 _L1w_DevTpuAdjEventProc
+ 0x100277f9 0xb _L1w_DevTpuSetDoff
+ 0x10027804 0x7 _L1w_DevTpuGetDoff
+ 0x1002780b 0xa _L1w_DevTpuSfn2Cfn
+ 0x10027815 0x25 _L1w_DevTpuCfn2Sfn
+ 0x1002783a 0x1b _L1w_DevTpuGetNtSSFN
+ 0x10027855 0x1c _L1w_DevTpuGetRtSSFN
+ 0x10027871 0x17 _L1w_DevTpuGetSSFN
+ 0x10027888 0xe _L1w_DevTpuGetCurCFN
+ 0x10027896 0x7 _L1w_DevTpuSfn2Ssfn
+ 0x1002789d 0x7 _L1w_DevTpuCfn2Ssfn
+ 0x100278a4 0x27 _L1w_DevTpuRt2Nt
+ 0x100278cb 0x69 _L1w_DevTpuAddCnt
+ 0x10027934 0x34 _L1w_DevTpuCalNt2RtOffset
+ 0x10027968 0x2c _L1w_DevTpuMicroSsfnJumpPatch
+ 0x10027994 0x7a _L1w_DevTpuCheckMicroSsfnJump
+ 0x10027a0e 0x21 _L1w_DevTpuMicroSsfnJumpPro
+ 0x10027a2f 0x77 _L1w_DevTpuCheckMicroSsfnBack
+ 0x10027aa6 0x1f _L1w_DevTpuMicroSsfnBackPro
+ 0x10027ac5 0x32 _L1w_DevTpuNtSSfnCfnUpdate
+ 0x10027af7 0x14 _L1w_DevTpuRtSSfnUpdate
+ 0x10027b0b 0x32 _L1w_DevTpuCalcNtUpdateTime
+ 0x10027b3d 0x31 _L1w_DevTpuCalcRtUpdateTime
+ 0x10027b6e 0x1e _L1w_DevTpuBase2Norm
+ 0x10027b8c 0x43 _L1w_DevTpuNorm2Base
+ 0x10027bcf 0x17 _L1w_DevTpuCalRt2NtOffset
+ 0x10027be6 0x27 _L1w_DevTpuNt2Rt
+ 0x10027c0d 0x7c _L1w_DevTpuSubCnt
+ .text 0x10027c89 0x9a4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x10027c89 0x6 _L1w_DevDbAfcAddrGet
+ 0x10027c8f 0x6 _L1w_DevDbIscpAddrGet
+ 0x10027c95 0x6f _L1w_DevDbRtxUpaRlIscpReport
+ 0x10027d04 0xa _L1w_DevDbRtxPcRlIscpReport
+ 0x10027d0e 0x7 _L1w_DevDbSetHsdpaInd
+ 0x10027d15 0xb _L1w_DevDbReSetHsdpaInd
+ 0x10027d20 0x3d _L1w_DevDbUpdateHsdpaInd
+ 0x10027d5d 0x6 _L1w_DevDbGetHsdpaInd
+ 0x10027d63 0x26 _L1w_DevDbRtxRxSirSet
+ 0x10027d89 0x26 _L1w_DevDbRtxRxSirGet
+ 0x10027daf 0x2d _L1w_DevDbBchWriteAfcData
+ 0x10027ddc 0x34 _L1w_DevAfcReadDataFromBch
+ 0x10027e10 0x3a9 _L1w_DevDlsAfcReadDataFromRx
+ 0x100281b9 0x43 _L1w_DevDbGetInitXValue
+ 0x100281fc 0x42 _L1w_DevDbGetInitYValue
+ 0x1002823e 0x1e _L1w_DevDbGetInitValue
+ 0x1002825c 0x45 _L1w_DevDbCodingPara
+ 0x100282a1 0x43 _L1w_DevDbTrchTtiMap
+ 0x100282e4 0x28 _L1w_DevDbTrchMaxMinTti
+ 0x1002830c 0x7 _L1w_DevDbTrchMaxTtiGet
+ 0x10028313 0x8 _L1w_DevDbTrchMinTtiGet
+ 0x1002831b 0x6 _L1w_DevDbGetPichCfg
+ 0x10028321 0x6 _L1w_DevDbGetPchCfg
+ 0x10028327 0x6 _L1w_DevDbGetFachCfg
+ 0x1002832d 0x6 _L1w_DevDbGetDldpchCfg
+ 0x10028333 0x6 _L1w_DevDbGetFdpchCfg
+ 0x10028339 0x32 _L1w_DevDbGetSchCodeGrp
+ 0x1002836b 0x3a _L1w_DevDbSaveCirData
+ 0x100283a5 0xb _L1w_DevDbClearCirData
+ 0x100283b0 0x6 _L1w_DevDbGetCirDataAddr
+ 0x100283b6 0x6 _L1w_DevDbGetFingerMaskBufAddr
+ 0x100283bc 0x1b _L1w_DevDbRtxReportToMac
+ 0x100283d7 0x21 _L1w_DevDbHspaReportToMac
+ 0x100283f8 0x1d _L1w_DevDbSetHsdpaToMacInfo
+ 0x10028415 0x21 _L1w_DevDbSetHsupaToMacInfo
+ 0x10028436 0xb _L1w_DevDbClrHspaToMacInfo
+ 0x10028441 0x1 _L1w_DevDbPcReportToMac
+ 0x10028442 0x9 _L1w_SchedResIsBand8Freq
+ 0x1002844b 0x15 _L1w_DevDbGetAiSignSeries
+ 0x10028460 0x27 _L1w_DevDbPiValHandle
+ 0x10028487 0x26 _L1w_DevDbCalcPiVal
+ 0x100284ad 0x1c _L1w_DevRtxRxPiAiFloatAdd
+ 0x100284c9 0x6 _L1w_DevDbGetHspaPlusFachPsCmd
+ 0x100284cf 0x12 _L1w_DevDbPsSubFrmInt
+ 0x100284e1 0x24 _L1w_DevDbSubFrmInt
+ 0x10028505 0xe _L1w_DevDbSetHarqFlag
+ 0x10028513 0xc _L1w_DevDbInitHsdpaAntSwitchInfo
+ 0x1002851f 0x7 _L1w_DevDbSetHsdpaAntSwitchFlg
+ 0x10028526 0x7 _L1w_DevDbGetHsdpaAntSwitchFlg
+ 0x1002852d 0x8 _L1w_DevDbSetHsdpaAntNum
+ 0x10028535 0x8 _L1w_DevDbGetHsdpaAntNum
+ 0x1002853d 0x1a _L1w_DevDbHsdpaJudge2Rto1R
+ 0x10028557 0x1c _L1w_DevDbHsdpaJudge1Rto2R
+ 0x10028573 0x9 _L1w_DevDbAddHsscchCnt
+ 0x1002857c 0x17 _L1w_DevDbHsscchSchedCnt
+ 0x10028593 0x9 _L1w_DevDbAddHsscchCorrectCnt
+ 0x1002859c 0xa _L1w_DevDbAddHsscchErrorCnt
+ 0x100285a6 0x9 _L1w_DevDbClearHsscchErrorCnt
+ 0x100285af 0xa _L1w_DevDbAddSnrHighCnt
+ 0x100285b9 0x9 _L1w_DevDbClearSnrHighCnt
+ 0x100285c2 0xa _L1w_DevDbAddSnrLowCnt
+ 0x100285cc 0x9 _L1w_DevDbClearSnrLowCnt
+ 0x100285d5 0xd _L1w_DevDbSet1R2RState
+ 0x100285e2 0xc _L1w_DevDbSetLas1R2RState
+ 0x100285ee 0x11 _L1w_DevDbIs1RTo2R
+ 0x100285ff 0x7 _L1w_DevDbGet1R2RState
+ 0x10028606 0xb _L1w_DevDbGet1R2RAntNum
+ 0x10028611 0x7 _L1w_DevSetSystemAntNum
+ 0x10028618 0x7 _L1w_DevGetSystemAntNum
+ 0x1002861f 0x7 _L1w_DevDbSetTxPower
+ 0x10028626 0x7 _L1w_DevDbGetTxPower
+ .text 0x1002862d 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x1002862d 0xf _L1w_DevRtxRxInit
+ 0x1002863c 0x29 _L1w_DevRtxRxReset
+ 0x10028665 0x87 _L1w_DevRtxRxAddTpuEvent
+ 0x100286ec 0x36 _L1w_DevRtxRxDelTpuEvent
+ 0x10028722 0x1c _L1w_DevRtxRxDelFactorTpuInt
+ 0x1002873e 0x80 _L1w_DevRtxRxSwapFinger
+ 0x100287be 0x10f _L1w_DevRtxRxFingerSort
+ 0x100288cd 0x72 _L1w_DevRtxRxFingerSelect
+ 0x1002893f 0x75 _L1w_DevRtxRxFingerMsgHandle
+ 0x100289b4 0x27 _L1w_DevRtxOfflinePichRelHanlde
+ 0x100289db 0x38 _L1w_DevRtxSetPchCfgState
+ 0x10028a13 0x65 _L1w_DevRtxRxPchCfgReqHandle
+ 0x10028a78 0x5f _L1w_DevRtxRxCompareConfigTime
+ 0x10028ad7 0x1a1 _L1w_DevRtxRxOffLinePichCfg
+ 0x10028c78 0xcd _L1w_DevRtxRxPichCfgMsgHandle
+ 0x10028d45 0x3e _L1w_DevRtxRxPichRelMsgHandle
+ 0x10028d83 0x187 _L1w_DevRtxRxPchCfgMsgHandle
+ 0x10028f0a 0x26 _L1w_DevRtxRxPchRelMsgHandle
+ 0x10028f30 0x157 _L1w_DevRtxRxAichCfgMsgHandle
+ 0x10029087 0x38 _L1w_DevRtxRxAichRelMsgHandle
+ 0x100290bf 0x123 _L1w_DevRtxRxFachCfgMsgHandle
+ 0x100291e2 0x38 _L1w_DevRtxRxFachRelMsgHandle
+ 0x1002921a 0x219 _L1w_DevRtxRxDlDpchCfgMsgHandle
+ 0x10029433 0x36 _L1w_DevRtxRxDlDpchRelMsgHandle
+ 0x10029469 0x119 _L1w_DevRtxRxFdpchCfgMsgHandle
+ 0x10029582 0x87 _L1w_DevRtxRxPlusCpCfgMsgHandle
+ 0x10029609 0x38 _L1w_DevRtxRxFdpchRelMsgHandle
+ 0x10029641 0x3 _L1w_DevRtxRxPlusFachTpuHandle
+ 0x10029644 0x1cc _L1w_DevRtxRxPlusFachCfg
+ 0x10029810 0x15b _L1w_DevRtxRxCmCfgMsgHandle
+ 0x1002996b 0x26 _L1w_DevRtxRxCmAbortMsgHandle
+ 0x10029991 0x5a _L1w_DevRtxRxHsscchCfgMsgHandle
+ 0x100299eb 0x51 _L1w_DevRtxRxEagchCfgMsgHandle
+ 0x10029a3c 0x9 _L1w_DevRtxRxEagchRelMsgHandle
+ 0x10029a45 0x63 _L1w_DevRtxRxRgHiCfgMsgHandle
+ 0x10029aa8 0x9 _L1w_DevRtxRxRgHiRelMsgHandle
+ 0x10029ab1 0x45 _L1w_DevRtxRxDrxMsgHandle
+ 0x10029af6 0x12e _L1w_DevRtxRxMsgHandle
+ 0x10029c24 0x6 _L1w_DevRtxRxTrchInfoGet
+ 0x10029c2a 0x16 _L1w_DevRtxRxTurboUse
+ 0x10029c40 0xed _L1w_DevRtxRxDlStatEng
+ 0x10029d2d 0x6 _L1w_DevRtxRxDpchPhyInfoGet
+ 0x10029d33 0x6 _L1w_DevRtxRxIntCfgParaGet
+ 0x10029d39 0xf _L1w_DevRtxRxDrxSlotCheck
+ 0x10029d48 0x28 _L1w_DevRtxRxCmSlotCheck
+ 0x10029d70 0x8c _L1w_DevRtxRxCpCmSlotCheck
+ 0x10029dfc 0x19 _L1w_DevRtxRxGetSlotId
+ 0x10029e15 0xa _L1w_DevRtxRxDrxSlotClr
+ 0x10029e1f 0x6 _L1w_DevRtxRxTpcInfoGet
+ 0x10029e25 0x6 _L1w_DevRtxRxSccpchPhyInfoGet
+ 0x10029e2b 0x6 _L1w_DevRtxRxAgchPhyInfoGet
+ 0x10029e31 0x6 _L1w_DevRtxRxCfgInfoGet
+ 0x10029e37 0xd _L1w_DevRtxRxCfgRlCntGet
+ 0x10029e44 0x1c _L1w_DevRtxRxRlPrimSrcGet
+ .text 0x10029e60 0x516 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ 0x10029e60 0xd _L1w_DevRtxRxDsReset
+ 0x10029e6d 0x25 _L1w_DevRtxDsMsgHandle
+ 0x10029e92 0x72 _L1w_DevRtxDsStageHandle
+ 0x10029f04 0x84 _L1w_DevRtxDsStart
+ 0x10029f88 0x9 _L1w_DevRtxDsStop
+ 0x10029f91 0x3d _L1w_DevRtxDsCrcCalc
+ 0x10029fce 0x62 _L1w_DevRtxDsStep1Handle
+ 0x1002a030 0x7c _L1w_DevRtxDsQosStep1
+ 0x1002a0ac 0x41 _L1w_DevRtxDsStep2Handle
+ 0x1002a0ed 0xcc _L1w_DevRtxDsQosStep2
+ 0x1002a1b9 0x2a _L1w_DevRtxRxDsPostInd
+ 0x1002a1e3 0x3d _L1w_DevRtxDsInsyncInd
+ 0x1002a220 0x41 _L1w_DevRtxDsOutsyncInd
+ 0x1002a261 0x19 _L1w_DevRtxRxDsIsCrcExist
+ 0x1002a27a 0x1f _L1w_DevRtxRxDsIsCrcOk
+ 0x1002a299 0x16 _L1w_DevRtxRxDsCurTtiParaClr
+ 0x1002a2af 0x16 _L1w_DevRtxRxDsLast20CrcFalse
+ 0x1002a2c5 0xb _L1w_DevRtxRxDsIsPostOk
+ 0x1002a2d0 0x14 _L1w_DevRtxRxDsIsN312Ok
+ 0x1002a2e4 0x31 _L1w_DevRtxRxDsSetTpcData
+ 0x1002a315 0x1d _L1w_DevRtxRxDsGetSyncSt
+ 0x1002a332 0x44 _L1w_DevRtxRxDsUlSendState
+ .text 0x1002a376 0x37c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x1002a376 0xe _L1w_DrvRfcSingedDataMaxLimit
+ 0x1002a384 0xc _L1w_DrvRfcUnSingedDataMaxLimit
+ 0x1002a390 0x26 _L1w_DrvRfcS16ToFastFloat
+ 0x1002a3b6 0x3e _L1w_DrvRfcS16FastFloatDiv
+ 0x1002a3f4 0xd _L1w_DrvRfcFastFloatToS16
+ 0x1002a401 0x3e _L1w_DrvRfcAgcgain2ManExp
+ 0x1002a43f 0x71 _L1w_DrvRfcDcCalcSingleCh
+ 0x1002a4b0 0x29 _L1w_DrvRfcDcCalc
+ 0x1002a4d9 0x37 _L1w_DrvRfcDcSet
+ 0x1002a510 0x1c _L1w_DevRfcDcEstEn
+ 0x1002a52c 0xac _L1w_DrvRfcIQCalcSingleCh
+ 0x1002a5d8 0x2e _L1w_DrvRfcIQSet
+ 0x1002a606 0x11 _L1w_DrvRfcIQCalc
+ 0x1002a617 0x4f _L1w_DrvRfcDagcCalc
+ 0x1002a666 0x8c _L1w_DrvRfcDagcSet
+ .text 0x1002a6f2 0x421 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ 0x1002a6f2 0xa _L1w_DrvPIAIClkGateEnable
+ 0x1002a6fc 0xa _L1w_DrvPIAIClkGateDisable
+ 0x1002a706 0x10 _L1w_DrvPIAISttdCfg
+ 0x1002a716 0xc _L1w_DrvAiOnLineEn
+ 0x1002a722 0xa _L1w_DrvAIonLineDisable
+ 0x1002a72c 0xc _L1w_DrvPIAfcoffLineEnable
+ 0x1002a738 0x12 _L1w_DrvPIAfcoffLineDisable
+ 0x1002a74a 0xf _L1w_DrvPiAfcIntModeCfg
+ 0x1002a759 0xe _L1w_DrvGetPiAiEnPara
+ 0x1002a767 0x9 _L1w_DrvGetPiAiIntMode
+ 0x1002a770 0xe _L1w_DrvGetConfigState
+ 0x1002a77e 0xf _L1w_DrvPiAIFirOrderCfg
+ 0x1002a78d 0x21 _L1w_DrvPiSysmbolLenCfg
+ 0x1002a7ae 0x9 _L1w_DrvAlphaCfg
+ 0x1002a7b7 0xa _L1w_DrvAfcCompensateEnable
+ 0x1002a7c1 0xa _L1w_DrvAfcCompensateDisable
+ 0x1002a7cb 0x14 _L1w_DrvAfcRotateParaCfg
+ 0x1002a7df 0xd _L1w_DrvPiAiFingerParaCfg
+ 0x1002a7ec 0x16 _L1w_DrvPiOffsetCfg
+ 0x1002a802 0x23 _L1w_DrvPiAiOvsfCfg
+ 0x1002a825 0xf _L1w_DrvAfcBestFingerIndexCfg
+ 0x1002a834 0x16 _L1w_DrvAiSeqIndexCfg
+ 0x1002a84a 0xa _L1w_DrvPiAiCfgOver
+ 0x1002a854 0x15 _L1w_DrvReadCpichPower
+ 0x1002a869 0xd _L1w_DrvReadAiResult
+ 0x1002a876 0x3b _L1w_DrvReadConfigTime
+ 0x1002a8b1 0x3e _L1w_DrvSetConfigTime
+ 0x1002a8ef 0x1f _L1w_DrvPiAiReadCpichRam
+ 0x1002a90e 0xa _L1w_DrvPiAiReadAiSymbolRam
+ 0x1002a918 0x1b _L1w_DrvPiAiReadSymbolRam
+ 0x1002a933 0xa _L1w_DrvEAiReadAmRam
+ 0x1002a93d 0x18 _L1w_DrvAiReadAmRam
+ 0x1002a955 0xff _L1w_DrvPiAiAichCfg
+ 0x1002aa54 0x12 _L1w_DrvPiAiAichRel
+ 0x1002aa66 0x82 _L1w_DrvOffPichCfg
+ 0x1002aae8 0x2b _L1w_DrvOffPichRel
+ .text 0x1002ab13 0x2b7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ 0x1002ab13 0x9 _L1w_DrvSleepLpmCtrPwrOn
+ 0x1002ab1c 0x1c _L1w_DrvLpcModemIntCtrl
+ 0x1002ab38 0x3d _L1w_DrvLpcLpmConfPosCal
+ 0x1002ab75 0x38 _L1W_DrvLpcCfgSocWkupInt
+ 0x1002abad 0x15 _L1W_DrvLpcCfgModemWkupInt
+ 0x1002abc2 0xe _L1w_DrvLpcModemWakeUpIntCtrl
+ 0x1002abd0 0xe _L1w_DrvLpcSocWakeUpIntCtrl
+ 0x1002abde 0x17 _L1w_DrvLpcLpmSoftReset
+ 0x1002abf5 0x1a _L1w_DrvLpcClearInt
+ 0x1002ac0f 0xe _L1w_DrvLpcLpmSfIntCtrl
+ 0x1002ac1d 0x9 _L1w_DrvLpcIsLpmSfIntEn
+ 0x1002ac26 0x8c _L1w_DrvLpcSetLpmFrmInt
+ 0x1002acb2 0x2b _L1w_DrvLpcSetLpmAdjustFactor
+ 0x1002acdd 0x87 _L1w_DrvLpcLpmIntPwrCtrl
+ 0x1002ad64 0x1f _L1w_DrvLpcGetWNtTimeFromLpm
+ 0x1002ad83 0x2a _L1w_DrvLpcIcpSendForPsm
+ 0x1002adad 0xe _L1w_DrvLpcSetCampOnFlg
+ 0x1002adbb 0x8 _L1w_DrvLpcSetSleepFlag
+ 0x1002adc3 0x7 _L1w_DrvLpcGetSleepFlag
+ .text 0x1002adca 0x39d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ 0x1002adca 0x1c _L1_DrvCsrInit
+ 0x1002ade6 0x30 _L1_DrvCsrReset
+ 0x1002ae16 0x1c _L1w_DevCsrStep1Reset
+ 0x1002ae32 0x5f _L1w_DrvCsrTopCfg
+ 0x1002ae91 0x82 _L1w_DrvCsrSlotSyncCfg
+ 0x1002af13 0x4b _L1w_DrvCsrIcCfg
+ 0x1002af5e 0x1 _L1w_DrvCsrFrameSyncCfg2A
+ 0x1002af5f 0x1 _L1w_DrvCsrFrameSyncCfg2B
+ 0x1002af60 0x1 _L1w_DrvCsrScrambleSrchCfg
+ 0x1002af61 0x66 _L1w_DrvCsrFullscanKscCfg
+ 0x1002afc7 0x44 _L1w_DrvCsrFullscanUnKscCfg
+ 0x1002b00b 0x83 _L1w_DrvCsrFullscanCfg
+ 0x1002b08e 0x94 _L1w_DrvCsrReadSlotSync
+ 0x1002b122 0x1 _L1w_DrvCsrStep1ReadMaxPos
+ 0x1002b123 0x1 _L1w_DrvCsrReadFrameSync2A
+ 0x1002b124 0x1 _L1w_DrvCsrReadFrameSync2B
+ 0x1002b125 0x1d _L1w_DrvCsrCmpFloat
+ 0x1002b142 0x1 _L1w_DrvCsrReadScrambleCode
+ 0x1002b143 0x24 _L1w_DrvCsrReadFs
+ .text 0x1002b167 0x306 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x1002b167 0x9 _L1w_DrvSetTop01GdtrHdtrBitSet
+ 0x1002b170 0xa _L1w_DrvSetTop01GdtrHdtrBitclr
+ 0x1002b17a 0x9 _L1w_DrvSetTopEDmaIntBypassBitSet
+ 0x1002b183 0xa _L1w_DrvSetTopEDmaIntBypassBitclr
+ 0x1002b18d 0x1c _L1w_DrvResetTopViterbi
+ 0x1002b1a9 0x6 _L1w_DrvGetTop0OSoftResetRegAddr
+ 0x1002b1af 0x9 _L1w_DrvTop00SoftResetBitSet
+ 0x1002b1b8 0xa _L1w_DrvTop00SoftResetBitClr
+ 0x1002b1c2 0x9 _L1w_DrvTop10TpuRakeIntMaskBitSet
+ 0x1002b1cb 0xa _L1w_DrvTop10TpuRakeIntMaskBitClr
+ 0x1002b1d5 0x9 _L1w_DrvTop11RakeDfeRfcIntMaskBitSet
+ 0x1002b1de 0xa _L1w_DrvTop11RakeDfeRfcIntMaskBitClr
+ 0x1002b1e8 0x9 _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitSet
+ 0x1002b1f1 0xa _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitClr
+ 0x1002b1fb 0x9 _L1w_DrvTop13CsrDtrPsrIntMaskBitSet
+ 0x1002b204 0xa _L1w_DrvTop13CsrDtrPsrIntMaskBitClr
+ 0x1002b20e 0x9 _L1w_DrvTop14TpuRakeIntStateMaskBitSet
+ 0x1002b217 0xa _L1w_DrvTop14TpuRakeIntStateMaskBitClr
+ 0x1002b221 0x9 _L1w_DrvTop15RakeDfeRfcIntStateMaskBitSet
+ 0x1002b22a 0xa _L1w_DrvTop15RakeDfeRfcIntStateMaskBitClr
+ 0x1002b234 0x9 _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitSet
+ 0x1002b23d 0xa _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitClr
+ 0x1002b247 0x9 _L1w_DrvTop17CsrDtrPsrIntStateMaskBitSet
+ 0x1002b250 0xa _L1w_DrvTop17CsrDtrPsrIntStateMaskBitClr
+ 0x1002b25a 0xe _L1w_DrvTopCsrDtrPsrIntOpen
+ 0x1002b268 0xe _L1w_DrvTopCsrDtrPsrIntClose
+ 0x1002b276 0x8 _L1w_DrvTopGetTop10High16b
+ 0x1002b27e 0x7 _L1w_DrvTopGetTop10Low16b
+ 0x1002b285 0x8 _L1w_DrvTopGetTop14High16b
+ 0x1002b28d 0x7 _L1w_DrvTopGetTop14Low16b
+ 0x1002b294 0x7 _L1w_DrvTopGetTop11Low16b
+ 0x1002b29b 0x7 _L1w_DrvTopGetTop15Low16b
+ 0x1002b2a2 0x9 _L1w_DrvTopLpcOpenGateClk
+ 0x1002b2ab 0xa _L1w_DrvTopLpcCloseGateClk
+ 0x1002b2b5 0xb _L1w_DrvTopClkIsOpen
+ 0x1002b2c0 0x13 _L1W_DrvTopLpcRegSave
+ 0x1002b2d3 0x23 _L1W_DrvTopLpcRegRestore
+ 0x1002b2f6 0x26 _L1w_DrvMcuIntMask
+ 0x1002b31c 0x26 _L1w_DrvMcuIntUnmask
+ 0x1002b342 0xa _L1w_DrvMcuIntIreqClr
+ 0x1002b34c 0x5f _L1w_DrvTopIntMask
+ 0x1002b3ab 0x4f _L1w_DrvTopIntMaskRestore
+ 0x1002b3fa 0x1a _L1w_DrvTopIntClr
+ 0x1002b414 0x59 _L1w_DrvTopIntEng
+ .text 0x1002b46d 0x20d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x1002b46d 0x25 _L1w_DrvTpuSoftResetCfg
+ 0x1002b492 0x39 _L1w_DrvTpuReset
+ 0x1002b4cb 0x28 _L1w_DrvTpuInit
+ 0x1002b4f3 0x39 _L1w_DrvTpuNTIntEnable
+ 0x1002b52c 0x3a _L1w_DrvTpuNTIntDisable
+ 0x1002b566 0x14 _L1w_DrvTpuRTIntEnable
+ 0x1002b57a 0x15 _L1w_DrvTpuRTIntDisable
+ 0x1002b58f 0x11 _L1w_DrvTpuLatchTimeCfg
+ 0x1002b5a0 0x8 _L1w_DrvTpuRdNTTiming
+ 0x1002b5a8 0x8 _L1w_DrvTpuRdRTTiming
+ 0x1002b5b0 0x11 _L1w_DrvTpuNTIntParaCfg
+ 0x1002b5c1 0x11 _L1w_DrvTpuRTIntParaCfg
+ 0x1002b5d2 0xa _L1w_DrvTpuMacroIntDisble
+ 0x1002b5dc 0x7 _L1w_DrvTpuMicroAdjParaCfg
+ 0x1002b5e3 0x8 _L1w_DrvTpuGetNT2RtOffset
+ 0x1002b5eb 0x8 _L1w_DrvTpuGetNTssfn
+ 0x1002b5f3 0x8 _L1w_DrvTpuGetRTssfn
+ 0x1002b5fb 0x32 _L1w_DrvTpuMacroAdjParaCfg
+ 0x1002b62d 0x28 _L1W_DrvTpuLpcRegRestore
+ 0x1002b655 0x25 _L1W_DrvTpuLpcRegSave
+ .text 0x1002b67a 0x431 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ 0x1002b67a 0x26 _L1w_DrvTxReset
+ 0x1002b6a0 0xb _L1w_DrvTxClear
+ 0x1002b6ab 0x16 _L1w_DrvTxDpxchEnCfg
+ 0x1002b6c1 0x10 _L1w_DrvTxRamLpEnCfg
+ 0x1002b6d1 0x10 _L1w_DrvTxScramFixRotateEnCfg
+ 0x1002b6e1 0x10 _L1w_DrvTxModeTypeCfg
+ 0x1002b6f1 0x10 _L1w_DrvTxGateClkDisableCfg
+ 0x1002b701 0x2b _L1w_DrvTxDpxchOffsetCfg
+ 0x1002b72c 0x31 _L1w_DrvTxPreamblePhchCfg
+ 0x1002b75d 0xa _L1w_DrvTxPreamblePhchDisable
+ 0x1002b767 0x2d _L1w_DrvTxPrachPhchCfg
+ 0x1002b794 0xa _L1w_DrvTxPrachPhchEnable
+ 0x1002b79e 0xa _L1w_DrvTxPrachPhchDisable
+ 0x1002b7a8 0x10 _L1w_DrvTxSampleTxRegTimeCfg
+ 0x1002b7b8 0x10 _L1w_DrvTxDpcchFbiCfg
+ 0x1002b7c8 0x16 _L1w_DrvTxDpcchTpcCfg
+ 0x1002b7de 0x43 _L1w_DrvTxDpxchPhchCfg
+ 0x1002b821 0x30 _L1w_DrvTxPrachSpreaderCfg
+ 0x1002b851 0x22 _L1w_DrvTxScramblerCfg
+ 0x1002b873 0x2a _L1w_DrvTxDpxchOrPrachPwrCfg
+ 0x1002b89d 0x18 _L1w_DrvTxHsDpcchPwrCfg
+ 0x1002b8b5 0x18 _L1w_DrvTxEdpcchPwrCfg
+ 0x1002b8cd 0x49 _L1w_DrvTxEdpdchPwrCfg
+ 0x1002b916 0xc _L1w_DrvTxPreamblePwrCfg
+ 0x1002b922 0x111 _L1_DrvTxRfcTest
+ 0x1002ba33 0x13 _L1w_DrvGetTxDpxchOffset
+ 0x1002ba46 0x39 _L1w_DrvTxCordicAdjustCfg
+ 0x1002ba7f 0x9 _L1w_DrvTxCordicDisable
+ 0x1002ba88 0x23 _L1w_DrvTxCordicEnable
+ .text 0x1002baab 0x381 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x1002baab 0x27 _L1w_DrvMeasReset
+ 0x1002bad2 0x57 _L1w_DrvMeasCfgCellCode
+ 0x1002bb29 0x19 _L1w_DrvMeasParaOverCfg
+ 0x1002bb42 0x6e _L1w_DrvMeasCfgSpsrStartTime
+ 0x1002bbb0 0x8 _L1w_DrvMeasCfgClkGating
+ 0x1002bbb8 0x60 _L1w_DrvMeasReadResult
+ 0x1002bc18 0x1a _L1w_DrvMeasReadAgc
+ 0x1002bc32 0xa _L1w_DrvMeasReadSpsrIntSeqNum
+ 0x1002bc3c 0x5f _L1w_DrvMeasCompareConfigTime
+ 0x1002bc9b 0x14 _L1w_DrvMeasReadSpsrstatus
+ 0x1002bcaf 0x8 _L1w_DrvMeasOffLineRamparaCfg
+ 0x1002bcb7 0x8 _L1w_DrvMeasOffLineRamMrtrCfg
+ 0x1002bcbf 0x9 _L1w_DrvMeasMeasBufUpdateCfg
+ 0x1002bcc8 0x8 _L1w_DrvMeasWorkModeCfg
+ 0x1002bcd0 0x8 _L1w_DrvMeasOnLineStartSpsrCfg
+ 0x1002bcd8 0xe _L1w_DrvMeasOnLineGetSpsrCfg
+ 0x1002bce6 0x10 _L1w_DrvMeasOnLineAgc0paraCfg
+ 0x1002bcf6 0x10 _L1w_DrvMeasOnLineAgc1paraCfg
+ 0x1002bd06 0x35 _L1w_DrvMeasOnLineAgc0StartMrtrCfg
+ 0x1002bd3b 0x35 _L1w_DrvMeasOnLineAgc1StartMrtrCfg
+ 0x1002bd70 0x4f _L1w_DrvMeasFrameBoundaryCfg
+ 0x1002bdbf 0x2d _L1w_DrvMeasSpsrParaCfg
+ 0x1002bdec 0x1c _L1w_DrvMeasCellSttdModeCfg
+ 0x1002be08 0xa _L1w_DrvMeasClkGatingCfg
+ 0x1002be12 0x9 _L1w_DrvMeasSoftPatternCfg
+ 0x1002be1b 0x9 _L1w_DrvMeasPatternModeCfg
+ 0x1002be24 0x8 _L1w_DrvMeasCfgOfflineSpsrStartTime
+ .text 0x1002be2c 0x55d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ 0x1002be2c 0x22 _L1w_DrvHsupaEutrEnable
+ 0x1002be4e 0xa _L1w_DrvHsupaEutrDisable
+ 0x1002be58 0xe _L1w_DrvHsupaEutrSoftRst
+ 0x1002be66 0x13 _L1w_DrvHsupaEutrHarqRamMode
+ 0x1002be79 0x10 _L1w_DrvHsupaEutrHarqId
+ 0x1002be89 0xb _L1w_DrvHsupaEutrTtiTwoFlg
+ 0x1002be94 0xb _L1w_DrvHsupaEutrTbSize
+ 0x1002be9f 0x47 _L1w_DrvHsupaEutrCodeSize
+ 0x1002bee6 0x3e _L1w_DrvHsupaEutrPhchPara
+ 0x1002bf24 0x2d _L1w_DrvHsupaEutrRmSysPara
+ 0x1002bf51 0x2d _L1w_DrvHsupaEutrRmP1Para
+ 0x1002bf7e 0x2d _L1w_DrvHsupaEutrRmP2Para
+ 0x1002bfab 0x55 _L1w_DrvHsupaEutrInterPara
+ 0x1002c000 0x60 _L1w_DrvHsupaEutrConfig
+ 0x1002c060 0xb _L1w_DrvHsupaEutrReadHarqStatus
+ 0x1002c06b 0x23 _L1w_DrvHsupaEtxEnable
+ 0x1002c08e 0x12 _L1w_DrvHsupaEtxDisable
+ 0x1002c0a0 0x19 _L1w_DrvHsupaEtxCfgTti
+ 0x1002c0b9 0x2a _L1w_DrvHsupaCfgEtxInt
+ 0x1002c0e3 0x12 _L1w_DrvHsupaTopEtxIntEnable
+ 0x1002c0f5 0xb _L1w_DrvHsupaEtxDisInt
+ 0x1002c100 0x1b _L1w_DrvHsupaTopMaskEtxInt
+ 0x1002c11b 0x31 _L1w_DrvHsupaRakeReadRgHi
+ 0x1002c14c 0xa _L1w_DrvHsupaCalLogTwo
+ 0x1002c156 0x42 _L1w_DrvHsupaEtxInterPara
+ 0x1002c198 0x34 _L1w_DrvHsupaEtxChCfgReg2
+ 0x1002c1cc 0x54 _L1w_DrvHsupaEtxEdpxchPara
+ 0x1002c220 0x25 _L1w_DrvHsupaEtxSpreadReg
+ 0x1002c245 0x29 _L1w_DrvHsupaEtxConf
+ 0x1002c26e 0xb _L1w_DrvHsupaEtxReadTtiCnt
+ 0x1002c279 0x20 _L1w_DrvHsupaTopGetIntState
+ 0x1002c299 0x1 _L1w_DrvHsupaTopMaskEutrInt
+ 0x1002c29a 0xf _L1w_DrvHsupaTopMaskRgHiState
+ 0x1002c2a9 0xf _L1w_DrvHsupaTopMaskRgHiInt
+ 0x1002c2b8 0x17 _L1w_DevHsupaTopMaskAgInt
+ 0x1002c2cf 0x2 _L1w_DrvHsupaTopMaskRgchHichInt
+ 0x1002c2d1 0x23 _L1w_DrvHsupaMaskInt
+ 0x1002c2f4 0x2d _L1w_DrvHsupaTopEagchRst
+ 0x1002c321 0x7 _L1w_DrvHsupaRdAgIntStateMask
+ 0x1002c328 0x7 _L1w_DrvHsupaWtAgIntStateMask
+ 0x1002c32f 0x7 _L1w_DrvHsupaRdAgIntEnable
+ 0x1002c336 0x7 _L1w_DrvHsupaWtAgIntEnable
+ 0x1002c33d 0x7 _L1w_DrvHsupaRdRgHiIntStateMask
+ 0x1002c344 0x7 _L1w_DrvHsupaWtRgHiIntStateMask
+ 0x1002c34b 0x7 _L1w_DrvHsupaRdRgHiIntEnable
+ 0x1002c352 0x7 _L1w_DrvHsupaWtRgHiIntEnable
+ 0x1002c359 0x17 _L1w_DrvHsupaEnableAgInt
+ 0x1002c370 0x13 _L1w_DrvHsupaPcEtxEdpdchDisable
+ 0x1002c383 0x6 _L1w_DrvEutrGetRamAddr
+ .text 0x1002c389 0x506 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x1002c389 0x1 _L1w_DrvDpramEngDisplay
+ 0x1002c38a 0x4a _L1w_DrvDpramStructInit
+ 0x1002c3d4 0x25 _L1w_DrvDpramIsEmpty
+ 0x1002c3f9 0x42 _L1w_DrvDpramReadMsg
+ 0x1002c43b 0x1 _L1w_DrvDpramUpdateMsgPos
+ 0x1002c43c 0x5 _L1w_DrvDpramQueMemRead
+ 0x1002c441 0x37 _L1w_DrvDpramWriteMsg
+ 0x1002c478 0x23 _L1w_DrvDpramGetRdDataPtr
+ 0x1002c49b 0x1f _L1w_DrvDpramUpdateRdDataPos
+ 0x1002c4ba 0x24 _L1w_DrvDpramTxReadClearData
+ 0x1002c4de 0x31 _L1w_DrvDpramGetWrDataPtr
+ 0x1002c50f 0x8 _L1w_DrvDpramGetWrCnt
+ 0x1002c517 0x2c _L1w_DrvDpramUpdateWrDataPos
+ 0x1002c543 0x1a _L1w_DrvICPSendForPsSched
+ 0x1002c55d 0xa _L1w_DrvDpramIsD2AEmpty
+ 0x1002c567 0xa _L1w_DrvDpramSleepCheck
+ 0x1002c571 0x8 _L1w_DrvDpramWriteSfnDpramFlg
+ 0x1002c579 0x7 _L1w_DrvDpramWriteDoff2Dpram
+ 0x1002c580 0x7 _L1w_DrvDpramReadEdcpIntState
+ 0x1002c587 0xa _L1w_DrvDpramClrEdcpIntState
+ 0x1002c591 0x7 _L1w_DrvDpramClrIcpIntState
+ 0x1002c598 0xa _L1w_DrvDpramMaskIcpInt
+ 0x1002c5a2 0x9 _L1w_DrvDpramDemaskIcpInt
+ 0x1002c5ab 0x49 _L1w_DrvDpramPrintLog
+ 0x1002c5f4 0x104 _L1w_DrvDpramUpdateTpu
+ 0x1002c6f8 0x26 _L1w_DrvDpramWriteGrantHarq
+ 0x1002c71e 0x26 _L1w_DrvDpramWriteUlPower
+ 0x1002c744 0x41 _L1w_DrvDpramGetEutrCtrlInfo
+ 0x1002c785 0xa _L1w_DrvDpramSetRachDchTransFlg
+ 0x1002c78f 0xa _L1w_DrvDpramGetRachDchTransFlg
+ 0x1002c799 0x20 _L1w_DrvDpramSetUpaTransInfo
+ 0x1002c7b9 0x1f _L1w_DrvDpramGetGrantMonitorReq
+ 0x1002c7d8 0xe _L1w_DrvDpramHsupaSetActiveInfos
+ 0x1002c7e6 0xa _L1w_DrvDpramSetCmPattern
+ 0x1002c7f0 0x9 _L1w_DrvDpramSetUph
+ 0x1002c7f9 0x2f _L1w_DrvDpramWriteEtfcRestrictInfo
+ 0x1002c828 0x3e _L1w_DrvDpramWriteCmNtrInfo
+ 0x1002c866 0x29 _L1w_DrvDpramGetEdchHarqId
+ .text 0x1002c88f 0x1984 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x1002c88f 0x81 _L1w_DrvRxTpcPlCombTimeInit
+ 0x1002c910 0x83 _L1w_DrvRxInit
+ 0x1002c993 0x50 _L1w_DrvRxReset
+ 0x1002c9e3 0x2c _L1w_DrvRxSoftReset
+ 0x1002ca0f 0x35 _L1w_DrvRxCalcExp2
+ 0x1002ca44 0xe _L1w_DrvRxFingerCfg
+ 0x1002ca52 0x2c _L1w_DrvRxSetTfciIntTime
+ 0x1002ca7e 0x8 _L1w_DrvRxGetTfciIntTime
+ 0x1002ca86 0x191 _L1w_DrvRxCpichCfg
+ 0x1002cc17 0x16 _L1w_DrvRxCpichRel
+ 0x1002cc2d 0x109 _L1w_DrvRxPichCfg
+ 0x1002cd36 0x3a _L1w_DrvRxPichRel
+ 0x1002cd70 0x123 _L1w_DrvRxAichCfg
+ 0x1002ce93 0x3a _L1w_DrvRxAichRel
+ 0x1002cecd 0x11d _L1w_DrvRxPchCfg
+ 0x1002cfea 0x11 _L1w_DrvRxPchRel
+ 0x1002cffb 0x126 _L1w_DrvRxFachCfg
+ 0x1002d121 0x3b _L1w_DrvRxFachRel
+ 0x1002d15c 0x10e _L1w_DrvRxDlDpchCodeCfg
+ 0x1002d26a 0x33 _L1w_DrvRxDlTpcPilotCfg
+ 0x1002d29d 0x29 _L1w_DrvRxFdpchTpcCfg
+ 0x1002d2c6 0xa4 _L1w_DrvRxDlDpchCfg
+ 0x1002d36a 0x6f _L1w_DrvRxDlDpchRel
+ 0x1002d3d9 0x31 _L1w_DrvRxDlFbiCfg
+ 0x1002d40a 0x15b _L1w_DrvRxFdpchCfg
+ 0x1002d565 0x3b _L1w_DrvRxFdpchRel
+ 0x1002d5a0 0x16a _L1w_DrvRxHsscchCfg
+ 0x1002d70a 0x65 _L1w_DrvRxHsscchRel
+ 0x1002d76f 0x103 _L1w_DrvRxEagchCfg
+ 0x1002d872 0x40 _L1w_DrvRxEagchRel
+ 0x1002d8b2 0x333 _L1w_DrvRxRgHiCfg
+ 0x1002dbe5 0x3c _L1w_DrvRxRgHiRel
+ 0x1002dc21 0x15 _L1w_DrvRxEdchTtiCfg
+ 0x1002dc36 0x5b _L1w_DrvRxRgHichPostCmCfg
+ 0x1002dc91 0x10 _L1w_DrvRxDpchFactorCfg
+ 0x1002dca1 0xf _L1w_DrvRxAgchFactorCfg
+ 0x1002dcb0 0x77 _L1w_DrvRxDlCmCfnCfg
+ 0x1002dd27 0x8c _L1w_DrvRxDlCmSymbCfg
+ 0x1002ddb3 0x64 _L1w_DrvRxDlCmPostCfg
+ 0x1002de17 0x1f _L1w_DrvRxDlCmSymbRel
+ 0x1002de36 0x16 _L1w_DrvRxDlCmPostRel
+ 0x1002de4c 0x24 _L1w_DrvRxRakeCpChangRel
+ 0x1002de70 0x8e _L1w_DrvRxRakeChipCfg
+ 0x1002defe 0x119 _L1w_DrvRxRakeSymbCfg
+ 0x1002e017 0x4a _L1w_DrvRxRakePostCfg
+ 0x1002e061 0x18 _L1w_DrvRxRakeCfg
+ 0x1002e079 0xc _L1w_DrvRxSymbCpichStRead
+ 0x1002e085 0xc _L1w_DrvRxSymbPilotStRead
+ 0x1002e091 0x9 _L1w_DrvRxCombPiAiIntRead
+ 0x1002e09a 0x9 _L1w_DrvRxCombPilotIntRead
+ 0x1002e0a3 0x9 _L1w_DrvRxCombTpcIntRead
+ 0x1002e0ac 0x15 _L1w_DrvRxCombTpcPlStIntRead
+ 0x1002e0c1 0x8 _L1w_DrvRxCombFdpchIntRead
+ 0x1002e0c9 0xa _L1w_DrvRxCombDpchFactorDataRead
+ 0x1002e0d3 0xa _L1w_DrvRxCombAgchFactorDataRead
+ 0x1002e0dd 0x27 _L1w_DrvRxRamPiAiRead
+ 0x1002e104 0xa _L1w_DrvRxRamDpchPilotRead
+ 0x1002e10e 0xa _L1w_DrvRxRamDpchTpcRead
+ 0x1002e118 0x43 _L1w_DrvRxRamFdpchTpcRead
+ 0x1002e15b 0x15 _L1w_DrvRxRamSlotwtRead
+ 0x1002e170 0x15 _L1w_DrvRxRamNoiseRead
+ 0x1002e185 0x1f _L1w_DrvRxRamRawCpichRead
+ 0x1002e1a4 0x15 _L1w_DrvRxRamAfcRead
+ 0x1002e1b9 0x1c _L1w_DrvRxRamRawPilotRead
+ 0x1002e1d5 0x1f _L1w_DrvRxRgchIntInfoRead
+ 0x1002e1f4 0x1f _L1w_DrvRxHichIntInfoRead
+ .text 0x1002e213 0xa62 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ 0x1002e213 0x11 _L1w_DrvDtrBitReverse
+ 0x1002e224 0xa _L1w_DrvDtrTurboInit
+ 0x1002e22e 0x1d _L1w_DrvDtrTurboReset
+ 0x1002e24b 0x11 _L1w_DrvDtrSetCsServiceFlg
+ 0x1002e25c 0x3b _L1w_DrvDtrReset
+ 0x1002e297 0x5e _L1w_DrvDtrInit
+ 0x1002e2f5 0x3e _L1w_DrvDtrTrchCmCfg
+ 0x1002e333 0x4c _L1w_DrvDtrTrchSlotFormCfg
+ 0x1002e37f 0x171 _L1w_DrvDtrTrchTfciS1Cfg
+ 0x1002e4f0 0x24 _L1w_DrvDtrTrchTfciS1Clear
+ 0x1002e514 0xb _L1w_DrvDtrTrchCfnSet
+ 0x1002e51f 0xa _L1w_DrvDtrTrchCfnGet
+ 0x1002e529 0xf _L1w_DrvDtrTrchRegRel
+ 0x1002e538 0xa _L1w_DrvDtrTrchTfciS2Update
+ 0x1002e542 0xa _L1w_DrvDtrTrchDemultiplexUpdate
+ 0x1002e54c 0x9f _L1w_DrvDtrS1CfgPrint
+ 0x1002e5eb 0x1d7 _L1w_DrvDtrS2CfgPrint
+ 0x1002e7c2 0xb0 _L1w_DrvDtrTrchTfciS2Cfg
+ 0x1002e872 0xb _L1w_DrvDtrTrchTfciS2Clear
+ 0x1002e87d 0x42 _L1w_DrvDtrTrchBlindS1Cfg
+ 0x1002e8bf 0xa5 _L1w_DrvDtrTrchBlindGuidCfg
+ 0x1002e964 0xc _L1w_DrvDtrTrchBlindGuidUpdate
+ 0x1002e970 0xa _L1w_DrvDtrTrchTfciRead
+ 0x1002e97a 0x2d _L1w_DrvDtrTrchTfciDataReadV3
+ 0x1002e9a7 0x30 _L1w_DrvDtrTrchBlindRead
+ 0x1002e9d7 0x6 _L1w_DrvDtrTrchBlindDataAddrGet
+ 0x1002e9dd 0x24 _L1w_DrvDtrTrchDecodeInfoRead
+ 0x1002ea01 0x6 _L1w_DrvDtrTrchDecodeAddrGet
+ 0x1002ea07 0x1bb _L1w_DrvDtrTrchDecodeDataRead
+ 0x1002ebc2 0x61 _L1w_DrvDtrEagchCfg
+ 0x1002ec23 0xe _L1w_DrvDtrEagchCmCfg
+ 0x1002ec31 0x9 _L1w_DrvDtrEagchRel
+ 0x1002ec3a 0x3b _L1w_DrvDtrAgchIntDataRead
+ .text 0x1002ec75 0x572 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ 0x1002ec75 0x2d _L1w_DrvBchInit
+ 0x1002eca2 0xe _L1w_DrvBchReset
+ 0x1002ecb0 0x2d _L1w_DrvBchRecover
+ 0x1002ecdd 0xd _L1w_DrvBchSetFingerAdjust
+ 0x1002ecea 0xe _L1w_DrvBchGeViterbiOut
+ 0x1002ecf8 0x56 _L1w_DrvBchGePichSymbol
+ 0x1002ed4e 0xa _L1w_DrvBchGeCrcResult
+ 0x1002ed58 0x2b _L1w_DrvBchGeCpichOut
+ 0x1002ed83 0xf8 _L1w_DrvBchBchRxCfg
+ 0x1002ee7b 0xcd _L1w_DrvBchPichRxCfg
+ 0x1002ef48 0x9b _L1w_DrvBchCpichRxCfg
+ 0x1002efe3 0xc _L1w_DrvBchSetFingerEn
+ 0x1002efef 0xc _L1w_DrvBchSetRuntime
+ 0x1002effb 0xe _L1w_DrvBchGetFingerPos
+ 0x1002f009 0x10 _L1w_DrvBchSetS5TestMode
+ 0x1002f019 0xa _L1w_DrvBchSetTxdMode
+ 0x1002f023 0x7 _L1w_DrvBchSetBchPichSel
+ 0x1002f02a 0x7 _L1w_DrvBchSetTtiSync
+ 0x1002f031 0x7 _L1w_DrvBchSetWindowTh
+ 0x1002f038 0x7 _L1w_DrvBchSetPichOvsfk
+ 0x1002f03f 0xc _L1w_DrvBchSetContexSel
+ 0x1002f04b 0xd _L1w_DrvBchSetFingerPos
+ 0x1002f058 0x19 _L1w_DrvBchSetScramCode
+ 0x1002f071 0x16 _L1w_DrvBchSetStartMode
+ 0x1002f087 0xc _L1w_DrvBchSetPiAfcNum
+ 0x1002f093 0x31 _L1w_DrvBchSetPiPos
+ 0x1002f0c4 0xe _L1w_DrvBchGetFingerSt
+ 0x1002f0d2 0xd _L1w_DrvBchHasInvalidSymbol
+ 0x1002f0df 0xe _L1w_DrvBchGetBufIndex
+ 0x1002f0ed 0xe _L1w_DrvBchGetSlotIndex
+ 0x1002f0fb 0xe _L1w_DrvBchGetBurstPattern
+ 0x1002f109 0xa _L1w_DrvBchGeTotalSt
+ 0x1002f113 0x16 _L1w_DrvBchIsHwBusy
+ 0x1002f129 0x13 _L1w_DrvBchSetIQSel
+ 0x1002f13c 0x12 _L1w_DrvBchSetRotatePara
+ 0x1002f14e 0x21 _L1w_DrvBchSetRotateEn
+ 0x1002f16f 0xf _L1w_DrvBchSetRotateGateCtrl
+ 0x1002f17e 0xb _L1w_DrvBchIsIqRotateEn
+ 0x1002f189 0x36 _L1w_DrvBchStopIqRotate
+ 0x1002f1bf 0x12 _L1w_DrvBchSetFingerAnt
+ 0x1002f1d1 0x16 _L1w_DrvBchSetAdjFingerInfo
+ .text 0x1002f1e7 0x2f1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ 0x1002f1e7 0xc _L1w_DrvUtrLogTwo
+ 0x1002f1f3 0x31 _L1w_DrvUtrReset
+ 0x1002f224 0x1c _L1w_DrvUtrRamSoftReset
+ 0x1002f240 0x3 _L1w_DrvUtrInit
+ 0x1002f243 0xac _L1w_DrvUtrDchConfig
+ 0x1002f2ef 0x32 _L1w_DrvUtrRachConfig
+ 0x1002f321 0xa _L1w_DrvUtrEnable
+ 0x1002f32b 0xe _L1w_DrvUtrClose
+ 0x1002f339 0x8 _L1w_DrvUtrGetRamAddr
+ 0x1002f341 0x5f _L1w_DrvUtrTbAndCbConfig
+ 0x1002f3a0 0xac _L1w_DrvUtrRMConfig
+ 0x1002f44c 0x2d _L1w_DrvUtrGetCrcMode
+ 0x1002f479 0x20 _L1w_DrvUtrGetCodingType
+ 0x1002f499 0x1a _L1w_DrvUtrClearRmPara
+ 0x1002f4b3 0xc _L1w_DrvUtrRegClear
+ 0x1002f4bf 0x11 _L1w_DrvUtrGetRamData
+ 0x1002f4d0 0x8 _L1_DrvUtrGetInterlv1RamState
+ .text 0x1002f4d8 0x1dda T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ 0x1002f4d8 0x5e _L1w_DrvRfcApcTableSel
+ 0x1002f536 0x1d2 _L1w_DrvRfcAbbCsfHpfCfg
+ 0x1002f708 0x5 _L1w_DrvRfcCalcIntFreq
+ 0x1002f70d 0x29 _L1w_DrvRfcCalcFracFreq
+ 0x1002f736 0x51 _L1w_DrvRfcGetFreqData
+ 0x1002f787 0x19 _L1w_DrvRfcGetBandData
+ 0x1002f7a0 0x9d _L1w_DrvRfcFreqSetTx
+ 0x1002f83d 0x12a _L1w_DrvRfcFreqSetRx
+ 0x1002f967 0x84 _L1w_DrvRfcGetBandNvIndex
+ 0x1002f9eb 0x79 _L1w_DrvRfcAuxRxCtrlSet
+ 0x1002fa64 0x1c _L1w_DrvRfcAuxRxIdleSet
+ 0x1002fa80 0x20 _L1w_DrvRfcRegReadBackSet
+ 0x1002faa0 0x1 _L1w_DrvRfcChSel
+ 0x1002faa1 0x1 _L1w_DrvRfcTransceiverInit
+ 0x1002faa2 0x2e _L1w_DrvRfcAgcSet
+ 0x1002fad0 0x2f _L1w_DrvRfcApcTableFreqSel
+ 0x1002faff 0xbc _L1w_DrvRfcApcSet
+ 0x1002fbbb 0x2d _L1w_DrvRfcFreqCompGetNvIdx
+ 0x1002fbe8 0x7c _L1w_DrvRfcApcFreqComp
+ 0x1002fc64 0x38 _L1w_DrvRfcApcTmpComp
+ 0x1002fc9c 0x100 _L1w_DrvRfcApcCalibTableCheck
+ 0x1002fd9c 0x4f _L1w_DrvRfcApcDefaultTableCheck
+ 0x1002fdeb 0x77 _L1w_DrvRfcAgcFreqComp
+ 0x1002fe62 0x71 _L1w_DrvRfcAgcCalibTableCheck
+ 0x1002fed3 0x46 _L1w_DrvRfcAgcDefaultTableCheck
+ 0x1002ff19 0x2a _L1w_DrvRfcRxNotchEn
+ 0x1002ff43 0x2a _L1w_DrvRfcRxNotchDisEn
+ 0x1002ff6d 0x2b _L1w_DrvRfcAntExChangeSelEn
+ 0x1002ff98 0x2b _L1w_DrvRfcAntOriginSelEn
+ 0x1002ffc3 0x2a _L1w_DrvRfcRxStartDivEn
+ 0x1002ffed 0x2b _L1w_DrvRfcRxStopDivEn
+ 0x10030018 0x2a _L1w_DrvRfcAuxRxSwCtrlEn
+ 0x10030042 0x2b _L1w_DrvRfcAuxRxSwIdleEn
+ 0x1003006d 0x38 _L1w_DrvRfcIdleToTxEn
+ 0x100300a5 0x36 _L1w_DrvRfcTxToRxTxEn
+ 0x100300db 0x3a _L1w_DrvRfcTxToIdleEn
+ 0x10030115 0x36 _L1w_DrvRfcRxTxToTxEn
+ 0x1003014b 0x36 _L1w_DrvRfcIdleToRxEn
+ 0x10030181 0x38 _L1w_DrvRfcRxToRxTxEn
+ 0x100301b9 0x2b _L1w_DrvRfcSwAllIdleEn
+ 0x100301e4 0x40 _L1w_DrvRfcRxToIdleEn
+ 0x10030224 0x2d _L1w_DrvRfcRxTxToRxEn
+ 0x10030251 0x37 _L1w_DrvRfcRxFreqChangeEn
+ 0x10030288 0x38 _L1w_DrvRfcTxFreqChangeEn
+ 0x100302c0 0x32 _L1w_DrvRfcIdleToTxHandle
+ 0x100302f2 0x48 _L1w_DrvRfcTxToIdleHandle
+ 0x1003033a 0x45 _L1w_DrvRfcIdleToRxHandle
+ 0x1003037f 0x55 _L1w_DrvRfcRxToIdleHandle
+ 0x100303d4 0x53 _L1w_DrvRfcRxFreqChangeHandle
+ 0x10030427 0xd _L1w_DrvRfcTxFreqChangeHandle
+ 0x10030434 0x41 _L1w_DrvRfcSlotCtrlDiv
+ 0x10030475 0x2a _L1w_DrvRfcSlotCtrlAntSel
+ 0x1003049f 0x29 _L1w_DrvRfcAgcEstEn
+ 0x100304c8 0x29 _L1w_DrvRfcAgcSetEn
+ 0x100304f1 0x35 _L1w_DrvRfcApcEn
+ 0x10030526 0x3c _L1w_DrvRfcAfcSetEn
+ 0x10030562 0x29 _L1w_DrvRfcDcEstEn
+ 0x1003058b 0x29 _L1w_DrvRfcDcSetEn
+ 0x100305b4 0x29 _L1w_DrvRfcRegReadBackEn
+ 0x100305dd 0x29 _L1w_DrvRfcStartAuxAdcEn
+ 0x10030606 0x29 _L1w_DrvRfcStopAuxAdcEn
+ 0x1003062f 0x1c _L1w_DrvRfcDcxoAuxAdcStart
+ 0x1003064b 0x1d _L1w_DrvRfcDcxoAuxAdcStop
+ 0x10030668 0x1f _L1w_DrvRfcAuxAdcCtrlEn
+ 0x10030687 0x41 _L1w_DrvRfcAbbCsfWriteEn
+ 0x100306c8 0x33 _L1w_DrvRfcCtrlRamTxInit
+ 0x100306fb 0x33 _L1w_DrvRfcCtrlRamRx0Init
+ 0x1003072e 0x204 _L1w_DrvRfcCtrlRamSwitchNvInit
+ 0x10030932 0xea _L1w_DrvRfcCtrlRamPaNvInit
+ 0x10030a1c 0x8 _L1w_DrvRfcCtrlRamNvEventInit
+ 0x10030a24 0x38 _L1w_DrvRfcFastAgcCwTableInit
+ 0x10030a5c 0x4c _L1w_DrvRfcFastAgcRamInit
+ 0x10030aa8 0xda _L1w_DrvRfcOpenTx
+ 0x10030b82 0xf7 _L1w_DrvRfcOpenRx
+ 0x10030c79 0xa _L1w_DrvRfcDiversityCtrl
+ 0x10030c83 0x12 _L1w_DrvRfcAfcCw2Hz
+ 0x10030c95 0x6a _L1w_DrvRfcRfRegRead
+ 0x10030cff 0xce _L1w_DrvRfcAllRegReadBack
+ 0x10030dcd 0x54 _L1w_DrvRfcGetDCXOTmp
+ 0x10030e21 0x3b _L1w_DrvRfcReadTmp
+ 0x10030e5c 0x15 _L1w_DrvRfcAptWrite
+ 0x10030e71 0x21 _L1w_DrvRfcDcocWrite
+ 0x10030e92 0x18 _L1w_DrvRfcAgcWrite
+ 0x10030eaa 0x8d _L1w_DrvRfcCloseTx
+ 0x10030f37 0x6d _L1w_DrvRfcCloseRx
+ 0x10030fa4 0x7e _L1w_DrvRfcDirFreqSetTx
+ 0x10031022 0x7c _L1w_DrvRfcDirFreqSetRx
+ 0x1003109e 0x32 _L1w_DrvRfcPowerApcSet
+ 0x100310d0 0x43 _L1w_DrvRfcIndexApcSet
+ 0x10031113 0x177 _L1w_DrvRfcFdtTxApcSet
+ 0x1003128a 0x22 _L1w_DrvRfcHdtGetTxApcTable
+ 0x100312ac 0x6 _L1w_DrvRfcHdtGetRxAgcTable
+ .text 0x100312b2 0xb8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ 0x100312b2 0x8 _L1w_DrvPsrStartPosCfg
+ 0x100312ba 0xb _L1w_DrvPsrRlMrtrPosMrtrConfig
+ 0x100312c5 0xb _L1w_DrvPsrSrcAndChanCodeCfg
+ 0x100312d0 0x8 _L1w_DrvPsrClkGatePassCfg
+ 0x100312d8 0x9 _L1w_DrvPsrPilotPatternCfg
+ 0x100312e1 0x8 _L1w_DrvPsrCmModeCfg
+ 0x100312e9 0x9 _L1w_DrvPsrRlPosStartCfgOver
+ 0x100312f2 0x9 _L1w_DrvPsrSuspendCfg
+ 0x100312fb 0x12 _L1w_DrvPsrTopMaskIntCfg
+ 0x1003130d 0x1c _L1w_DrvPsrResetCfg
+ 0x10031329 0x8 _L1w_DrvPsrPeriodCfg
+ 0x10031331 0x8 _L1w_DrvPsrDoubleAntOpencfg
+ 0x10031339 0x8 _L1w_DrvPsrStartWinPosCfg
+ 0x10031341 0x8 _L1w_DrvPsrRlOpenCloseCfg
+ 0x10031349 0x8 _L1w_DrvPsrMasterRlCfg
+ 0x10031351 0x8 _L1w_DrvPsrSttdCfg
+ 0x10031359 0x8 _L1w_DrvPsrIntInfoCfg
+ 0x10031361 0x9 _L1w_DrvPsrCmOverCfg
+ .text 0x1003136a 0xaff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x1003136a 0x3c _L1w_DrvRfcGetFreqOffset
+ 0x100313a6 0x17 _L1w_DrvRfcNextSlotGet
+ 0x100313bd 0x16 _L1w_DrvRfcPreSlotGet
+ 0x100313d3 0x20 _L1w_DrvRfcFindSlot
+ 0x100313f3 0x8 _L1w_DrvRfcGetTxFirDlyNum
+ 0x100313fb 0x31 _L1w_DrvRfcSpiWrite
+ 0x1003142c 0x31 _L1w_DrvRfcAbbSpiWrite
+ 0x1003145d 0x12 _L1w_DrvRfcGpioWrite
+ 0x1003146f 0x14 _L1w_DrvRfcRffeWrite
+ 0x10031483 0x38 _L1w_DrvRfcFindBandNumFromTable
+ 0x100314bb 0x41 _L1w_DrvRfcGetFreqBand
+ 0x100314fc 0x22 _L1w_DrvRfcRxDfeIntfCfg
+ 0x1003151e 0x2f _L1w_DrvRfcPaModeSel
+ 0x1003154d 0x25 _L1w_DrvRfcGetPaCtrlData
+ 0x10031572 0x1a _L1w_DrvRfcGetPaIdleData
+ 0x1003158c 0x2a _L1w_DrvRfcGetApcCtrlWord
+ 0x100315b6 0xa3 _L1w_DrvRfcGetTxPowerCtrlWord
+ 0x10031659 0x14 _L1w_DrvRfcPaCtrl
+ 0x1003166d 0x25 _L1w_DrvRfcGetAgcCtrlWord
+ 0x10031692 0x27 _L1w_DrvRfcGetAfcDacCtrlWord
+ 0x100316b9 0x2c _L1w_DrvRfcDCXOGetTempDegree
+ 0x100316e5 0xb _L1w_DrvRfcAfcSet
+ 0x100316f0 0x1a _L1w_DrvRfcGetTxSwData
+ 0x1003170a 0x29 _L1w_DrvRfcGetRxSwData
+ 0x10031733 0x1a _L1w_DrvRfcGetTxSwIdleData
+ 0x1003174d 0x29 _L1w_DrvRfcGetRxSwIdleData
+ 0x10031776 0x1a _L1w_DrvRfcGetSwAllIdleData
+ 0x10031790 0x27 _L1w_DrvRfcSwitchPaCwWr
+ 0x100317b7 0x37 _L1w_DrvRfcSwitchCtrl
+ 0x100317ee 0x55 _L1w_DrvRfcSwPaIdleNvGet
+ 0x10031843 0x12 _L1w_DrvRfcGetCfgMrtr
+ 0x10031855 0x54 _L1w_DrvRfcTuEventMrtrWr
+ 0x100318a9 0x21 _L1w_DrvRfcTuEventCtrlDataWr
+ 0x100318ca 0x54 _L1w_DrvRfcTuEventEn
+ 0x1003191e 0x27 _L1w_DrvRfcCtrlRamFmtDataWr
+ 0x10031945 0x28 _L1w_DrvRfcCtrlRamFmtInfoWr
+ 0x1003196d 0x20 _L1w_DrvRfcCtrlRamDataTypeWr
+ 0x1003198d 0x40 _L1w_DrvRfcCtrlRamEn
+ 0x100319cd 0xe _L1w_DrvRfcAgcRamDataWr
+ 0x100319db 0x1c _L1w_DrvRfcFastAgcEn
+ 0x100319f7 0x1a _L1w_DrvRfcFastAgcDisEn
+ 0x10031a11 0x15 _L1w_DrvRfcIntCfg
+ 0x10031a26 0x15 _L1w_DrvRfcSpiFormatCfg
+ 0x10031a3b 0x9 _L1w_DrvRfcRffeFormatCfg
+ 0x10031a44 0x2 _L1w_DrvRfcRbdpCfg
+ 0x10031a46 0x1c _L1w_DrvRfcDagcCfg
+ 0x10031a62 0x13 _L1w_DrvRfcDcCfg
+ 0x10031a75 0xd _L1w_DrvRfcFcCordicCfg
+ 0x10031a82 0x1a _L1w_DrvRfcNotchCordicCfg
+ 0x10031a9c 0x21 _L1w_DrvRfcReadNotchCordicAVal
+ 0x10031abd 0xb8 _L1w_DrvRfcNotchRegCfg
+ 0x10031b75 0x52 _L1w_DrvRfcFastAgcCfg
+ 0x10031bc7 0x4f _L1w_DrvRfcCtrlRamEventInit
+ 0x10031c16 0x84 _L1w_DrvRfcAbbCsfCtrlRamInit
+ 0x10031c9a 0x21 _L1w_DrvRfcEventTableInit
+ 0x10031cbb 0x41 _L1w_DrvRfcReset
+ 0x10031cfc 0x8f _L1w_DrvRfcGsmIntNotchCalc
+ 0x10031d8b 0x73 _L1w_DrvRfcInit
+ 0x10031dfe 0x9 _L1w_DrvRfcDfeTxInit
+ 0x10031e07 0x30 _L1w_DrvRfcTxTone
+ 0x10031e37 0x28 _L1w_DrvRfcAfcCwSet
+ 0x10031e5f 0x1 _L1w_DrvRfcAfcCwGet
+ 0x10031e60 0x9 _L1w_DrvRfcRestore
+ .text 0x10031e69 0x1594 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x10031e69 0x38 _L1w_DrvHsdpaIcReset
+ 0x10031ea1 0x2f _L1w_DrvHsdpaIcTpuCfgOver
+ 0x10031ed0 0x30 _L1w_DrvHsdpaIcTxTpuCfgOver
+ 0x10031f00 0x28 _L1w_DrvHsdpaIcInit
+ 0x10031f28 0x12 _L1w_DrvHsdpaIcIntOpen
+ 0x10031f3a 0x12 _L1w_DrvHsdpaIcIntMask
+ 0x10031f4c 0x17 _L1w_DrvHsdpaIcEnable
+ 0x10031f63 0x18 _L1w_DrvHsdpaIcStaticCfg
+ 0x10031f7b 0x273 _L1w_DrvHsdpaIcTpuAntPsrCfg
+ 0x100321ee 0x1d8 _L1w_DrvHsdpaIcTxTpuAntPsrCfg
+ 0x100323c6 0xa9 _L1w_DrvHsdpaIcTpuSubFrmCfg
+ 0x1003246f 0x97 _L1w_DrvHsdpaIcTxTpuSubFrmCfg
+ 0x10032506 0x69 _L1w_DrvHsdpaIcModeEnableCfg
+ 0x1003256f 0x5b _L1w_DrvHsdpaIcLambdaCfg
+ 0x100325ca 0x5b _L1w_DrvHsdpaIcSymModulusRead
+ 0x10032625 0x34 _L1w_DrvHsdpaAdrReset
+ 0x10032659 0x18 _L1w_DrvHsdpaAdrInit
+ 0x10032671 0x12 _L1w_DrvHsdpaAdrIntOpen
+ 0x10032683 0x12 _L1w_DrvHsdpaAdrIntMask
+ 0x10032695 0xd6 _L1w_DrvHsdpaAdrStaticCfg
+ 0x1003276b 0x83 _L1w_DrvHsdpaAdrInitRcvCfg
+ 0x100327ee 0x4b _L1w_DrvHsdpaAdrFcCfg
+ 0x10032839 0x10 _L1w_DrvHsdpaAdrEnableCfg
+ 0x10032849 0x172 _L1w_DrvHsdpaAdrSubFrmCfg
+ 0x100329bb 0x10 _L1w_DrvHsdpaAdrHsscchCfg
+ 0x100329cb 0x2e _L1w_DrvHsdpaAdrHsdschCfg
+ 0x100329f9 0xa _L1w_DrvHsdpaAdrDisable
+ 0x10032a03 0x2d _L1w_DrvHsdpaAdrCltd1Cfg
+ 0x10032a30 0x74 _L1w_DrvHsdpaAdrCirIntRead
+ 0x10032aa4 0x11 _L1w_DrvHsdpaAdrGetCirDataAddr
+ 0x10032ab5 0x20 _L1w_DrvHsdpaAdrCpichIntRead
+ 0x10032ad5 0x2e _L1w_DrvHsdpaHsscchReset
+ 0x10032b03 0x21 _L1w_DrvHsdpaHsscchInit
+ 0x10032b24 0x12 _L1w_DrvHsdpaHsscchIntOpen
+ 0x10032b36 0x12 _L1w_DrvHsdpaHsscchIntMask
+ 0x10032b48 0x11 _L1w_DrvHsdpaHsscchStaticCfg
+ 0x10032b59 0x65 _L1w_DrvHsdpaHsscchInitRcvCfg
+ 0x10032bbe 0x2d _L1w_DrvHsdpaHsscchPart1Cfg
+ 0x10032beb 0x3b _L1w_DrvHsdpaHsscchPart2Cfg
+ 0x10032c26 0x1b _L1w_DrvHsdpaHsscchDisable
+ 0x10032c41 0xeb _L1w_DrvHsdpaHsscchPart1IntRead
+ 0x10032d2c 0x31 _L1w_DrvHsdpaHsscchPart2IntRead
+ 0x10032d5d 0x30 _L1w_DrvHsdpaHdtrReset
+ 0x10032d8d 0x1a _L1w_DrvHdtrTurboReset
+ 0x10032da7 0x1b _L1w_DrvHdtrLessTurboReset
+ 0x10032dc2 0x2e _L1w_DrvHsdpaHdtrInit
+ 0x10032df0 0x12 _L1w_DrvHsdpaHdtrIntOpen
+ 0x10032e02 0x12 _L1w_DrvHsdpaHdtrIntMask
+ 0x10032e14 0x25 _L1w_DrvHsdpaHdtrStaticCfg
+ 0x10032e39 0xa _L1w_DrvHsdpaHdtrInitRcvCfg
+ 0x10032e43 0x3b _L1w_DrvHsdpaHdtrDemoduleCfg
+ 0x10032e7e 0x183 _L1w_DrvHsdpaHdtrDecodeCfg
+ 0x10033001 0x83 _L1w_DrvHsdpaHdtrHwCfg
+ 0x10033084 0xa _L1w_DrvHsdpaHdtrGetCurCfgSubFrm
+ 0x1003308e 0x76 _L1w_DrvHsdpaHdtrIntRead
+ 0x10033104 0x6 _L1w_DrvHsdpaHdtrGetRamDataAddr
+ 0x1003310a 0x3b _L1w_DrvHsdpaHsdpcchInitSendCfg
+ 0x10033145 0x39 _L1w_DrvHsdpaHsdpcchAckNackCfg
+ 0x1003317e 0x3c _L1w_DrvHsdpaHsdpcchCqiPciCfg
+ 0x100331ba 0x10 _L1w_DrvHsdpaHsdpcchCqiPciCfgEn
+ 0x100331ca 0x10 _L1w_DrvHsdpaHsdpcchDisable
+ 0x100331da 0x19 _L1w_DrvHsdpaLessStaticCfg
+ 0x100331f3 0x20a _L1w_DrvHsdpaLessCfgAllTb
+ .text 0x100333fd 0x2951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x100333fd 0x2f _L1W_SEND_RST_REQ
+ 0x1003342c 0x2f _L1W_SEND_INIT_REQ
+ 0x1003345b 0x1d _L1W_RegTpuTS0IntEvent
+ 0x10033478 0xc _L1W_ResetTpu
+ 0x10033484 0x18d _L1W_Reset
+ 0x10033611 0x125 _L1W_Init
+ 0x10033736 0x35 _L1w_SchedMeasRelease
+ 0x1003376b 0x120 _L1W_W_Release
+ 0x1003388b 0x1c _L1W_SetSecSchedId
+ 0x100338a7 0x8 _L1W_CampOnSetFlag
+ 0x100338af 0x75 _L1W_CampOnOrReconfig
+ 0x10033924 0xad _L1W_DchIn1R2RCtrl
+ 0x100339d1 0x1e _L1W_Only1RCtrl
+ 0x100339ef 0xa9 _L1W_Sch1R2RAntCtrl
+ 0x10033a98 0xd8 _L1w_TpuAdjScByDchCfgScene
+ 0x10033b70 0xa8 _L1W_DlDpchReconfig
+ 0x10033c18 0x1c _L1W_DchRelTpuAdj
+ 0x10033c34 0x6e _L1w_AmtFsmProc
+ 0x10033ca2 0x89 _L1w_AmtNSTSetUlDpchParm
+ 0x10033d2b 0x72 _L1w_AmtNSTSetDlDpchParm
+ 0x10033d9d 0x5b _L1W_WRelDelayHandle
+ 0x10033df8 0x4af _L1W_PSCommonMsgCtrl
+ 0x100342a7 0x5 _L1w_HsupaSubIntCallBack
+ 0x100342ac 0x111 _L1W_ReadPSMsg
+ 0x100343bd 0x1d _L1W_RegTpuSubFrmIntEvent
+ 0x100343da 0x42 _L1W_SubFrmSchedStateCtrl
+ 0x1003441c 0x1b _L1W_InnerCmd
+ 0x10034437 0x55 _L1W_ActiveProcHandler
+ 0x1003448c 0x1f _L1W_ProcSend2PS
+ 0x100344ab 0x34 _L1W_ProcAftSchedHandler
+ 0x100344df 0x26f _L1W_RfDevCtrl
+ 0x1003474e 0xa3 _L1W_DlsDevCtrl
+ 0x100347f1 0x64 _L1W_SlaveSetRFStartEnd
+ 0x10034855 0x9e _L1W_CommonDevCtrl
+ 0x100348f3 0x1ce _L1W_BeforeTpuAdjHandler
+ 0x10034ac1 0x19f _L1W_StateChanging
+ 0x10034c60 0x8d _L1W_NorSubFrmIntHandle
+ 0x10034ced 0x150 _L1W_FrameInt
+ 0x10034e3d 0x29 _L1w_SchedResBaseOffUpdate
+ 0x10034e66 0x1a1 _L1W_PichIntHandle
+ 0x10035007 0xe3 _L1W_PreSyncSleepSched
+ 0x100350ea 0x583 _L1W_DevIntHandle
+ 0x1003566d 0x1bd _L1W_DevMeasResultHnd
+ 0x1003582a 0x18d _L1W_DevResultProc
+ 0x100359b7 0x1c2 _L1w_MainTs0Log
+ 0x10035b79 0x12 _L1w_MainSetCloseLog
+ 0x10035b8b 0x3a _L1w_SchedAntSet
+ 0x10035bc5 0x189 _L1w_SchedMainTask
+ .text 0x10035d4e 0x7c7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ 0x10035d4e 0x36 _L1w_SchedRachProcInit
+ 0x10035d84 0x14 _L1w_SchedRachProcReset
+ 0x10035d98 0x9c _L1w_SchedRachProcRanSelSig
+ 0x10035e34 0x52 _L1w_SchedRachFindAvailableAS
+ 0x10035e86 0xab _L1w_SchedRachNeedDeleteRtFrameEndAichSlot
+ 0x10035f31 0x170 _L1w_SchedRachProcRanSelAS
+ 0x100360a1 0x49 _L1w_SchedRachProcActive
+ 0x100360ea 0x2f _L1w_SchedRachProcDeactive
+ 0x10036119 0xce _L1w_SchedRachConfigRtx
+ 0x100361e7 0xb9 _L1w_SchedRachProcPSCmd
+ 0x100362a0 0x33 _L1w_SchedRachProcL1Cmd
+ 0x100362d3 0x2e _L1w_SchedRachProcPreSched
+ 0x10036301 0x4d _L1w_SchedRachProcCfgHandle
+ 0x1003634e 0x27 _L1w_SchedRachAiResultHandle
+ 0x10036375 0xea _L1w_SchedRachProcSched
+ 0x1003645f 0x28 _L1w_SchedRachProcSend2PS
+ 0x10036487 0x36 _L1w_SchedRachProcL1InnerReq
+ 0x100364bd 0x9 _L1w_SchedRachProcL1InnerAbort
+ 0x100364c6 0x8 _L1w_SchedRachProcDevFachEnable
+ 0x100364ce 0x1b _L1W_SchedRachProcConfigCheck
+ 0x100364e9 0x2c _L1w_SchedRachProcIsNextFmo
+ .text 0x10036515 0x1181 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ 0x10036515 0xd _L1w_SchMeasDbInit
+ 0x10036522 0x30 _L1w_SchMeasU16Filter
+ 0x10036552 0x17 _L1w_SchMeasFingerPosOffset
+ 0x10036569 0x74 _L1w_SchMeasChooseFilterFinger
+ 0x100365dd 0xc8 _L1w_SchMeasDbUpdPreSyncInfo
+ 0x100366a5 0x1d _L1w_SchedMeasReturnCsrSlot
+ 0x100366c2 0x27f _L1w_SchMeasDbSaveSyncCelReslt
+ 0x10036941 0xbb _L1w_SchedMeasSetInnerReq
+ 0x100369fc 0x91 _L1w_SchedMeasSetInnerResult
+ 0x10036a8d 0x17 _L1w_SchedMeasClearInnerDb
+ 0x10036aa4 0x37 _L1w_SchedMeasGetInnerResult
+ 0x10036adb 0x15 _L1w_SchedMeasQueryInnerSt
+ 0x10036af0 0x12 _L1w_SchedMeasGetAfcCel
+ 0x10036b02 0x25 _L1w_SchedMeasGetInnerCelInfo
+ 0x10036b27 0x14f _L1w_SchedMeasGetInnerFreq
+ 0x10036c76 0x13d _L1w_SchedMeasSaveCsResult
+ 0x10036db3 0x9a _L1w_SchedMeasQuerySyncInfo
+ 0x10036e4d 0xc0 _L1w_SchedMeasSyncSetFreq
+ 0x10036f0d 0x48 _L1w_SchedMeasGetScellResult
+ 0x10036f55 0x2db _L1w_SchedMeasGetIntraResult
+ 0x10037230 0x1a _L1w_SchedMeasFilterRscp
+ 0x1003724a 0x2a4 _L1w_SchedMeasGetInterResult
+ 0x100374ee 0xbf _L1w_SchMeasQueryCellInfo
+ 0x100375ad 0x3a _L1w_SchMeasAdjustSfn
+ 0x100375e7 0x4e _L1w_SchMeasSetCellSfnInfo
+ 0x10037635 0x37 _L1w_SchMeasSetCellSttdInfo
+ 0x1003766c 0x2a _L1w_SchMeasGetUeInternalRssi
+ .text 0x10037696 0x8b4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ 0x10037696 0x30 _L1W_RegisterProcedure
+ 0x100376c6 0x49 _L1W_SetIcsStateProcs
+ 0x1003770f 0x68 _L1W_SetIdleStateProcs
+ 0x10037777 0x40 _L1W_SetPageStateProcs
+ 0x100377b7 0x50 _L1W_SetFachStateProcs
+ 0x10037807 0x50 _L1W_SetEFachStateProcs
+ 0x10037857 0x48 _L1W_SetDchStateProcs
+ 0x1003789f 0x14 _L1W_SetAmtHdtStateProcs
+ 0x100378b3 0x14 _L1W_SetAmtFdtStateProcs
+ 0x100378c7 0x40 _L1W_SetAmtThCalibStateProcs
+ 0x10037907 0x40 _L1W_SetAmtNstStateProcs
+ 0x10037947 0x32 _L1W_SetWSlaveModeProcs
+ 0x10037979 0x1 _L1W_SetCloseStateProcs
+ 0x1003797a 0xb _L1W_GetDchActState
+ 0x10037985 0x6f _L1W_NotifyFSM
+ 0x100379f4 0x142 _L1W_WMasteStateCtrl
+ 0x10037b36 0xc0 _L1W_ModeCtrl
+ 0x10037bf6 0x4d _L1W_L1StateCtrl
+ 0x10037c43 0x87 _L1W_SetProc
+ 0x10037cca 0x42 _L1W_GetPriId
+ 0x10037d0c 0x97 _L1w_SetMasterState
+ 0x10037da3 0x30 _L1w_ResetCountForLog
+ 0x10037dd3 0x1b _L1w_AddSlaveStateCntForLog
+ 0x10037dee 0x3a _L1w_AddMasterStateCntForLog
+ 0x10037e28 0xb4 _L1w_CheckMsgToAddProcCntForLog
+ 0x10037edc 0xa _L1w_SetDLULTimingForLog
+ 0x10037ee6 0x64 _L1w_PrintStandLog
+ .text 0x10037f4a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ 0x10037f4a 0x8 _L1w_SchedCs1ProcGetFreq
+ 0x10037f52 0x7 _L1w_SchedCs1ProcGetCsProcState
+ 0x10037f59 0x6 _L1w_Cs1GetInnerInfo
+ 0x10037f5f 0x12 _L1w_SchedCs1ProcInit
+ 0x10037f71 0x21 _L1_SchedCs1ProcReset
+ 0x10037f92 0x22 _L1w_Cs1WriteFullscanResult
+ 0x10037fb4 0x17 _L1w_SchedCs1AbortInnerReq
+ 0x10037fcb 0xf _L1w_Cs1GetInnerReqByActReason
+ 0x10037fda 0x2 _L1w_SchedCs1ProcPSCmd
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+ 0x1004851f 0x2b1 _L1w_SchedHsdpaPSCmd
+ 0x100487d0 0x24d _L1w_SchedHsdpaPreSched
+ 0x10048a1d 0x5a _L1w_SchedHsdpaSched
+ 0x10048a77 0x40 _L1w_SchedHsdpaSend2PS
+ 0x10048ab7 0x1c _L1w_SchedHsdpaReset
+ 0x10048ad3 0xc _L1w_SchedHsdpaInit
+ 0x10048adf 0x3e _L1w_SchedHsdpaDevOrderIndProc
+ 0x10048b1d 0x53 _L1w_SchedHsdpaHsscchOrder
+ 0x10048b70 0x6 _L1w_SchedHsdpaGetSchedDb
+ 0x10048b76 0x32 _L1w_SchedHsdpaInnerRel
+ .text 0x10048ba8 0x2ae T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ 0x10048ba8 0xb _L1w_SchedHspaEraInd
+ 0x10048bb3 0x3a _L1w_SchedHsupaEraStart
+ 0x10048bed 0xb8 _L1w_SchedHsupaFachActive
+ 0x10048ca5 0x11 _L1w_SchedHsupaFachRel
+ 0x10048cb6 0xa _L1w_SchedHsupaErntiUpdateConfig
+ 0x10048cc0 0xee _L1w_SchedHsupaFachPreSched
+ 0x10048dae 0x26 _L1w_SchedHsupaNoDataPSCmd
+ 0x10048dd4 0x2d _L1w_SchedHsupaFachSched
+ 0x10048e01 0x26 _L1w_SchedHsupaEraSend2PS
+ 0x10048e27 0x2f _L1w_SchedHsupaFachSend2PS
+ .text 0x10048e56 0x341 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ 0x10048e56 0x8 _L1w_SchedFmoProcActive
+ 0x10048e5e 0x20 _L1w_SchedFmoProcDeactive
+ 0x10048e7e 0x5e _L1w_SchedFmoCalcInfo
+ 0x10048edc 0x45 _L1w_SchedFmoInfoSend2Psr
+ 0x10048f21 0x46 _L1w_SchedFmoProcForbidFmo
+ 0x10048f67 0x26 _L1w_SchedFmoProcGetFmoInfo
+ 0x10048f8d 0xf _L1w_SchedFmoProcGetFmoPeriod
+ 0x10048f9c 0x2 _L1w_SchedFmoProcReset
+ 0x10048f9e 0x12 _L1w_SchedFmoProcInit
+ 0x10048fb0 0x35 _L1w_SchedFmoProcPSCmd
+ 0x10048fe5 0x1b2 _L1w_SchedFmoProcSched
+ .text 0x10049197 0xce5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ 0x10049197 0x7 _L1w_SchedFsProcGetFsProcState
+ 0x1004919e 0x5 _L1w_SchedFsPscThreshold
+ 0x100491a3 0x23 _l1w_FsRemoveFreq
+ 0x100491c6 0xaf _L1w_FsInit
+ 0x10049275 0x59 _L1w_FsInsertCoarseResult
+ 0x100492ce 0x4a _L1w_FsCalcRssi
+ 0x10049318 0x39 _L1w_FsFilterFineFreq
+ 0x10049351 0xaf _L1w_SchedFsProcBandCrossFilter
+ 0x10049400 0x32 _L1w_FsSetFineFreq
+ 0x10049432 0x64 _L1w_FsGetByRangeIndex
+ 0x10049496 0x63 _L1w_FsGetNextCoarseFreq
+ 0x100494f9 0x2a _L1w_FsGetNextPscFreq
+ 0x10049523 0x27 _L1w_FsGetNextFineFreq
+ 0x1004954a 0x4f _L1w_FsInsertFineResult
+ 0x10049599 0x28 _L1w_SchedFsProcReset
+ 0x100495c1 0x18 _L1w_SchedFsProcInit
+ 0x100495d9 0x30 _L1w_SchedFsProcSchedInit
+ 0x10049609 0xa9 _L1w_SchedfsResQueryGap
+ 0x100496b2 0x88 _L1w_SchedFsProcJudgeEnd
+ 0x1004973a 0x42 _L1w_SchedFsProcSetRes
+ 0x1004977c 0x4f _L1w_SchedFsProcUpdResEnd
+ 0x100497cb 0x4c _L1w_SchedFsProcSetCoarseFreq
+ 0x10049817 0x58 _L1w_SchedFsProcGetRssi
+ 0x1004986f 0x3d _L1w_SchedFsProcCalcCoarseRssi
+ 0x100498ac 0x4d _L1w_SchedFsProcSchedSetFineFreq
+ 0x100498f9 0x60 _L1w_SchedFsProcCalcFineRssi
+ 0x10049959 0xbe _L1w_SchedFsProcSchedSetPscFreq
+ 0x10049a17 0xdd _L1w_SchedFsProcCalcPscRssi
+ 0x10049af4 0x4e _L1w_SchedFsProcSetPscFineInfo
+ 0x10049b42 0x110 _L1w_SchedFsProcSchedCalcPscAndRssi
+ 0x10049c52 0x3c _L1w_SchedFsProcPreSchedHandler
+ 0x10049c8e 0x43 _L1w_SchedFsProcSched
+ 0x10049cd1 0x3c _L1w_SchedFsProcActive
+ 0x10049d0d 0x8 _L1w_SchedFsProcDeactive
+ 0x10049d15 0x64 _L1w_SchedFsProcPSCmd
+ 0x10049d79 0x2c _L1w_FreqScanFineRssiCmp
+ 0x10049da5 0xd7 _L1w_SchedFsProcSend2PS
+ .text 0x10049e7c 0x4eb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
+ 0x10049e7c 0x7e _L1w_MathWord2Float
+ 0x10049efa 0x82 _L1w_MathDword2Float
+ 0x10049f7c 0x2a _L1w_MathFloatDiv
+ 0x10049fa6 0x27 _L1w_MathDivEx
+ 0x10049fcd 0x34 _L1w_MathFloatAdd
+ 0x1004a001 0x5c _L1w_MathFloatSub
+ 0x1004a05d 0x2e _L1w_MathFloatMul
+ 0x1004a08b 0x52 _L1w_MathFloatCmp
+ 0x1004a0dd 0x38 _L1w_MathCalcExp2
+ 0x1004a115 0xb0 _L1w_MathLog
+ 0x1004a1c5 0x187 _L1w_MathQuickSort
+ 0x1004a34c 0x11 _L1w_BitReverse
+ 0x1004a35d 0xa _L1w_GetNonZeroBitNum
+ .text 0x1004a367 0x539 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ 0x1004a367 0x21 _L1w_DevHsupaSetEdpdchReadyTrue
+ 0x1004a388 0x1f _L1w_DevHsupaCalcSubFrmBitmap
+ 0x1004a3a7 0x9 _L1w_DevHsupaIfSubfrmGap
+ 0x1004a3b0 0x105 _L1w_DevHsupaIsEdchReady
+ 0x1004a4b5 0x3e _L1w_DevHsupaCalcHarqId
+ 0x1004a4f3 0x48 _L1w_DevHsupaEdchDataPrint
+ 0x1004a53b 0x3e _L1w_DevHsupaGetTransFlg
+ 0x1004a579 0x24 _L1w_DevHsupaIsNextTtiReady
+ 0x1004a59d 0x13a _L1w_DevHsupaSendDataProc
+ 0x1004a6d7 0x33 _L1w_DevHsupaTxProc
+ 0x1004a70a 0x24 _L1w_DevHsupaSetEhichRcvInf
+ 0x1004a72e 0x20 _L1w_DevHsupaClrEhichRcvInf
+ 0x1004a74e 0xa _L1w_DevHsupaSearchEhichRcvInf
+ 0x1004a758 0xb _L1w_DevHsupaEhichRcvInfReset
+ 0x1004a763 0xc _L1w_DevHsupaEhichRcvInfInit
+ 0x1004a76f 0xe6 _L1w_DevHsupaIcpIntEdchDataProc
+ 0x1004a855 0x4b _L1w_DevHsupaCpPcTtiInfo
+ .text 0x1004a8a0 0x2a8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ 0x1004a8a0 0x25 _L1w_DevPcHspaReset
+ 0x1004a8c5 0x1b _L1w_DevPcHspaInit
+ 0x1004a8e0 0x44 _L1w_DevPcHsdpaBeltaHsCalc
+ 0x1004a924 0x76 _L1w_DevPcHsdpaBeltaHsCmUpdate
+ 0x1004a99a 0x1 _L1w_DevPcHsEdchBeltaObtain
+ 0x1004a99b 0x2b _L1w_DevPcHsdpaStartReqHandle
+ 0x1004a9c6 0x34 _L1w_DevPcGetCurDpaSubFrm
+ 0x1004a9fa 0x83 _L1w_DevPcHsdpaTtiInfoHandle
+ 0x1004aa7d 0x69 _L1w_DevPcHsupaStartReqHandle
+ 0x1004aae6 0x62 _L1w_DevPcHsupaTtiInfoHandle
+ .text 0x1004ab48 0xee3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x1004ab48 0x26 _L1w_DevTxRachIndToL1s
+ 0x1004ab6e 0xc _L1w_DevTxRaInit
+ 0x1004ab7a 0x35 _L1w_DevTxSendPcRaCfgMsg
+ 0x1004abaf 0x13 _L1w_DevTxUtrTrchParamCalc
+ 0x1004abc2 0x19 _L1w_DevTxUtrTbCbParamCalc
+ 0x1004abdb 0x29 _L1w_DevTxUtrRmParamCalc
+ 0x1004ac04 0xf6 _L1w_DevTxRaUtrCfg
+ 0x1004acfa 0x91 _L1w_DevTxRachTpuIntParaCalc
+ 0x1004ad8b 0x118 _L1w_DevTxRachMessageFactor
+ 0x1004aea3 0x11b _L1w_DevTxRachCfg
+ 0x1004afbe 0x42 _L1w_DevTxRachRel
+ 0x1004b000 0x8a _L1w_DevTxRachCfgMsgHandle
+ 0x1004b08a 0x22 _L1w_DevTxRachAbortMsgHandle
+ 0x1004b0ac 0x98 _L1w_DevTxPreamblePowerCtrl
+ 0x1004b144 0x96 _L1w_DevTxAichCfg
+ 0x1004b1da 0x86 _L1w_DevTxPreambleCfg
+ 0x1004b260 0xd8 _L1w_DevTxPrachPowerCtrl
+ 0x1004b338 0xc8 _L1w_DevTxPrachCfg
+ 0x1004b400 0x8f _L1w_DevTxRaIntPreHandle
+ 0x1004b48f 0x95 _L1w_DevTxRaIntAichHandle
+ 0x1004b524 0x64 _L1w_DevTxRaIntSendPrachHandle
+ 0x1004b588 0x5e _L1w_DevTxRaIntHandle
+ 0x1004b5e6 0x1a _L1w_DevTxPrachClose
+ 0x1004b600 0xbc _L1w_DevTxAichIsAck
+ 0x1004b6bc 0x3e _L1w_DevTxAichIsNack
+ 0x1004b6fa 0x106 _L1w_DevTxAichIsNoAck
+ 0x1004b800 0x77 _L1w_DevPrachInfoLogPrintf
+ 0x1004b877 0xb7 _L1w_DevTxEraDpcchCfg
+ 0x1004b92e 0x56 _L1w_DevTxEraDpcchRel
+ 0x1004b984 0xa7 _L1w_DevTxPiAiAichIntHandle
+ .text 0x1004ba2b 0xfa4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ 0x1004ba2b 0xb _L1w_DevRtxRmReset
+ 0x1004ba36 0x9 _L1w_DevRmGetExp
+ 0x1004ba3f 0x37 _L1w_DevRmCeil
+ 0x1004ba76 0x11 _L1w_DevRmCalcGcd
+ 0x1004ba87 0xad _L1w_DevRmGetSf
+ 0x1004bb34 0x37 _L1w_DevRmRachTfciAnalysis
+ 0x1004bb6b 0x5a _L1w_DevRmUlTfciAnalysis
+ 0x1004bbc5 0x78 _L1w_DevRmDlTfciAnalysis
+ 0x1004bc3d 0x59 _L1w_DevRmCalcCbPara
+ 0x1004bc96 0x63 _L1w_DevRmCalcBitsOfTrch
+ 0x1004bcf9 0x79 _L1w_DevRmCalcRmNi
+ 0x1004bd72 0x90 _L1w_DevRmCalcUlDeltaNi
+ 0x1004be02 0x121 _L1w_DevRmCalcDeltaNi
+ 0x1004bf23 0x45 _L1w_DevRmCalcUlNdataj
+ 0x1004bf68 0xa3 _L1w_DevRmCalcUlUncodeRm
+ 0x1004c00b 0x73 _L1w_DevRmCalcTurboS
+ 0x1004c07e 0xa6 _L1w_DevRmCalcUlTurboRm
+ 0x1004c124 0x65 _L1w_DevRmCalcUlTrchRmPara
+ 0x1004c189 0x46 _L1w_DevRmCalcUlRmPara
+ 0x1004c1cf 0x8a _L1w_DevRmCalcDlNimax
+ 0x1004c259 0x1f _L1w_DevRmCalcDlDeltaNimax
+ 0x1004c278 0xbd _L1w_DevRmCalcDlRmTfcNMax
+ 0x1004c335 0x97 _L1w_DevRmCalcDlRmDeltaNiTti
+ 0x1004c3cc 0x67 _L1w_DevRmCalcDlRmNiMax
+ 0x1004c433 0xfb _L1w_DevRmCalcDlTfcDeltaNijTti
+ 0x1004c52e 0x8f _L1w_DevRmCalcDlDeltaNijTti
+ 0x1004c5bd 0x63 _L1w_DevRmCalcDlUncodeRm
+ 0x1004c620 0x99 _L1w_DevRmCalcDlTurboRm
+ 0x1004c6b9 0x3f _L1w_DevRmCalcDlTrchRmPara
+ 0x1004c6f8 0x54 _L1w_DevRmCalcDlRmPara
+ 0x1004c74c 0x4c _L1w_DevRmSaveUlDchPara
+ 0x1004c798 0x4a _L1w_DevRmSaveDlTrchPara
+ 0x1004c7e2 0x34 _L1w_DevRmSaveRachPara
+ 0x1004c816 0xb5 _L1w_DevRmCalcRmPara
+ 0x1004c8cb 0x74 _L1w_DevRmCalcUlRmNi
+ 0x1004c93f 0x25 _L1w_DevRmCalcUlCmRes
+ 0x1004c964 0x6b _L1w_DevRmCalcTfcRes
+ .text 0x1004c9cf 0x3fc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ 0x1004c9cf 0x23 _L1w_DevHsdpaSendPcTtiInfo
+ 0x1004c9f2 0x1f _L1w_DevHsdpaHarqAckBufferShift
+ 0x1004ca11 0x68 _L1w_DevHsdpaSetHarqBufPrePost
+ 0x1004ca79 0x2a _L1w_DevHsdpaSetHarqBufAckNack
+ 0x1004caa3 0x2f _L1w_DevHsdpaInitCqiInfo
+ 0x1004cad2 0xe2 _L1w_DevHsdpaCqiSendProc
+ 0x1004cbb4 0x4b _L1w_DevHsdpaSnrCalcCtrl
+ 0x1004cbff 0x81 _L1w_DevHsdpaCqiSendCtrl
+ 0x1004cc80 0x3c _L1w_DevHsdpaSaveHsdpcchInitCfg
+ 0x1004ccbc 0x4a _L1w_DevHsdpaSaveHsdpcchAckCfg
+ 0x1004cd06 0x49 _L1w_DevHsdpaSaveHsdpcchCqiCfg
+ 0x1004cd4f 0x2a _L1w_DevHsdpaTxInitSendProc
+ 0x1004cd79 0x52 _L1w_DevHsdpaTxSubFrmProc
+ .text 0x1004cdcb 0x1a89 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x1004cdcb 0x9a _L1w_DevHsdpaInitHarqInfo
+ 0x1004ce65 0x45 _L1w_DevHsdpaInitAdrPsrInfo
+ 0x1004ceaa 0x10 _L1w_DevHsdpaGenChMask
+ 0x1004ceba 0x28 _L1w_DevHsdpaIsHdtrValid
+ 0x1004cee2 0x1a _L1w_DevHsdpaSaveDemoduleCfg
+ 0x1004cefc 0x5f _L1w_DevHsdpaSaveDecodeCfg
+ 0x1004cf5b 0x181 _L1w_DevHsdpaTpuSaveIcPsrCfg
+ 0x1004d0dc 0xea _L1w_DevHsdpaTpuCalcCfgPara
+ 0x1004d1c6 0x153 _L1w_DevHsdpaTxTpuSaveIcPsrCfg
+ 0x1004d319 0xdc _L1w_DevHsdpaTxTpuCalcCfgPara
+ 0x1004d3f5 0x92 _L1w_DevHsdpaTpuSaveScrCodePara
+ 0x1004d487 0x93 _L1w_DevHsdpaTxTpuSaveScrCodePara
+ 0x1004d51a 0x151 _L1w_DevHsdpaSaveAdrIcSubFrmPara
+ 0x1004d66b 0x6e _L1w_DevHsdpaSaveAdrInitRcvCfg
+ 0x1004d6d9 0x47 _L1w_DevHsdpaSaveHsscchInitCfg
+ 0x1004d720 0xa5 _L1w_DevHsdpaSaveAdrSubFrmCfg
+ 0x1004d7c5 0x15 _L1w_DevHsdpaIsPart1Valid
+ 0x1004d7da 0x109 _L1w_DevHsdpaPart1Filter
+ 0x1004d8e3 0x96 _L1w_DevHsdpaDchSavePart1IntCfg
+ 0x1004d979 0x2b2 _L1w_DevHsdpaSavePart1IntCfg
+ 0x1004dc2b 0x97 _L1w_DevHsdpaHsscchTypeAnalyse
+ 0x1004dcc2 0x16 _L1w_DevHsdpaIsNeedAckNack
+ 0x1004dcd8 0x149 _L1w_DevHsdpaDchPart2Type1Proc
+ 0x1004de21 0x7e _L1w_DevHsdpaSaveHdtrHwCfg
+ 0x1004de9f 0x4e _L1w_DevHsdpaSaveHdtrCfgPara
+ 0x1004deed 0x2d _L1w_DevHsdpaHdtrCfg
+ 0x1004df1a 0x3e _L1w_DevHsdpaCalcShiftFactor
+ 0x1004df58 0x13e _L1w_DevHsdpaPart2Type1Proc
+ 0x1004e096 0x35 _L1w_DevHsdpaHsscchOrderProc
+ 0x1004e0cb 0x119 _L1w_DevHsdpaPart2IntTraceLog
+ 0x1004e1e4 0x15d _L1w_DevHsdpaDchHdtrIntProc
+ 0x1004e341 0x3c _L1w_DevHsdpaRxParaInit
+ 0x1004e37d 0x5d _L1w_DevHsdpaRxInitRcvProc
+ 0x1004e3da 0x5f _L1w_DevHsdpaRxIcRstFirstCfg
+ 0x1004e439 0xb9 _L1w_DevHsdpaRxSubFrmProc
+ 0x1004e4f2 0xd3 _L1w_DevHsdpaRxPart1IntProc
+ 0x1004e5c5 0x142 _L1w_DevHsdpaRxPart2IntProc
+ 0x1004e707 0x4e _L1w_DevHsdpaRxMacHeadAnalyse
+ 0x1004e755 0xcc _L1w_DevHsdpaRxHdtrIntProc
+ 0x1004e821 0x33 _L1w_DevHsdpaRxThDataUpdate
+ .text 0x1004e854 0x297 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x1004e854 0x1c _L1w_DevPcRachReset
+ 0x1004e870 0x1c _L1w_DevPcRachInit
+ 0x1004e88c 0x9b _L1w_DevPcPrachBeltaCalc
+ 0x1004e927 0x7 _L1w_DevPcPrachPreamblePowerEngGet
+ 0x1004e92e 0x7b _L1w_DevPcPrachPreamblePowerCtrl
+ 0x1004e9a9 0xf6 _L1w_DevPcPrachMessagePowerCtrl
+ 0x1004ea9f 0x34 _L1w_DevPcPrachStartReqHandle
+ 0x1004ead3 0x6 _L1w_DevPcPrachPreambleReqHandle
+ 0x1004ead9 0x12 _L1w_DevPcPrachMessageReqHandle
+ .text 0x1004eaeb 0xeba T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x1004eaeb 0x3a _L1w_HsupaCalcLowLim
+ 0x1004eb25 0x48 _L1w_HsupaFlt2Fix
+ 0x1004eb6d 0x21 _L1w_DevHsupaCalcHiFrameOffset
+ 0x1004eb8e 0xf _L1w_DevHsupaCalcRgFrameOffset
+ 0x1004eb9d 0x46 _L1w_DevHsupaCalcRgHiFrmOffset
+ 0x1004ebe3 0x1f _L1w_DevHsupaIsTtiCntValid
+ 0x1004ec02 0x14 _L1w_DevHsupaCalcTtiCntMod
+ 0x1004ec16 0x26 _L1w_DevHsupaIsDlChanFrontByTx
+ 0x1004ec3c 0x3e _L1w_DevHsupaReadRgHi
+ 0x1004ec7a 0x20 _L1w_DevHsupaLookUpTtiCm
+ 0x1004ec9a 0x15a _L1w_DevHsupaIsRgHiCm
+ 0x1004edf4 0x15c _L1w_DevHsupaReadAllRgHiInfo
+ 0x1004ef50 0x2 _L1w_DevHsupaReadHarqGrant
+ 0x1004ef52 0x91 _L1w_DevHsupaHiCombine
+ 0x1004efe3 0x90 _L1w_DevHsupaRgCombine
+ 0x1004f073 0xaf _L1w_DevHsupaIscpSlotCombine
+ 0x1004f122 0x87 _L1w_DevHsupaHiDecisonParam
+ 0x1004f1a9 0x46 _L1w_DevHsupaNackConfirm
+ 0x1004f1ef 0xa5 _L1w_DevHsupaSingleHiDecision
+ 0x1004f294 0xb2 _L1w_DevHsupaSingleRgDecision
+ 0x1004f346 0x14 _L1w_DevHsupaMulHiNsrlsDecision
+ 0x1004f35a 0x73 _L1w_DevHsupaMulRgNsrlsDecision
+ 0x1004f3cd 0x30 _L1w_DevHsupaTtiCnt2HarqId
+ 0x1004f3fd 0x84 _L1w_DevHsupaNsrlsHiCombDecis
+ 0x1004f481 0x47 _L1w_DevHsupaSrlsHICombDecis
+ 0x1004f4c8 0x4d _L1w_DevHsupaSrlsRGCombDecis
+ 0x1004f515 0x75 _L1w_DevHsupaGetRlIscp
+ 0x1004f58a 0xee _L1w_DevHsupaReadAllIscpInfo
+ 0x1004f678 0x39 _L1w_DevHsupaSingleHiCombDec
+ 0x1004f6b1 0x61 _L1w_DevHsupaHiCombAndDecision
+ 0x1004f712 0x3d _L1w_DevHsupaSingleRgCombDecis
+ 0x1004f74f 0x75 _L1w_DevHsupaNsrlsRGDecision
+ 0x1004f7c4 0x51 _L1w_DevHsupaRgIndProc
+ 0x1004f815 0x91 _L1w_DevHsupaCalcDisDlChanEdch
+ 0x1004f8a6 0xff _L1w_DevHsupaSetHarqInfo
+ .text 0x1004f9a5 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ 0x1004f9a5 0x1 _L1w_DrvDmaReset
+ 0x1004f9a6 0x1 _L1w_DrvDmaInit
+ 0x1004f9a7 0x1 _L1w_DrvDmaSingleMemcpy
+ 0x1004f9a8 0x1 _L1W_DMA_ISR
+ .text 0x1004f9a9 0x165 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ 0x1004f9a9 0xd5 _L1w_SchedHsdpaPchCfgPSCmd
+ 0x1004fa7e 0x43 _L1w_SchedHsdpaPchRelPSCmd
+ 0x1004fac1 0x14 _L1w_SchedHsdpaPchPreSched
+ 0x1004fad5 0x1 _L1w_SchedHsdpaPchSched
+ 0x1004fad6 0x38 _L1w_SchedHsdpaPchSend2PS
+ .text 0x1004fb0e 0x12d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x1004fb0e 0x86 _zPHY_ModemOsProcessInit
+ 0x1004fb94 0x38 _zPHY_HwInit
+ 0x1004fbcc 0x1 _zPHY_FpgaPlatTopInit
+ 0x1004fbcd 0x5 _zPHY_ChipTopRegInit
+ 0x1004fbd2 0x69 _zPHY_LteaInit
+ .text 0x1004fc3b 0x210 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x1004fc3b 0xe _zPHY_NVInit_PreInit
+ 0x1004fc49 0x4b _zPHY_NVLteCopy
+ 0x1004fc94 0xd0 _zPHY_NVInit
+ 0x1004fd64 0x8 _L1e_CmnNvGetUeCategory
+ 0x1004fd6c 0x8 _L1e_CmnNvGetDlMimoCapability
+ 0x1004fd74 0xa _L1e_CmnNvGetRxAntNum
+ 0x1004fd7e 0xf _L1e_CmnNvGetRxRsrpInterval
+ 0x1004fd8d 0xf _L1e_CmnNvGetRxAntThreshold
+ 0x1004fd9c 0xa _L1e_CmnNvGetRxN1Timer
+ 0x1004fda6 0xa _L1e_CmnNvGetRxN2Timer
+ 0x1004fdb0 0x8 _L1e_CmnNvGetLteTempDetectEn
+ 0x1004fdb8 0x8 _L1e_CmnNvGetLteTxPwrBackoffEn
+ 0x1004fdc0 0x8 _L1e_CmnNvGetLteRxRateLimitEn
+ 0x1004fdc8 0x9 _L1e_CmnNvGetLteCqiThdParam
+ 0x1004fdd1 0xa _L1e_CmnNvGetLteRxTiAlgoCtrl
+ 0x1004fddb 0x11 _l1e_CmnZTERfSPIWrite
+ 0x1004fdec 0x20 _l1e_CmnZTERfSPIRead
+ 0x1004fe0c 0x3f _zPHY_erfc_TempReadPa
+ .text 0x1004fe4b 0xd86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x1004fe4b 0x1 _zPHY_ErrorHandle
+ 0x1004fe4c 0x14 _zPHY_GetErrorName
+ 0x1004fe60 0x102 _zPHY_etmtlog_ThreadEntry
+ 0x1004ff62 0x5c _zPHY_VersionInfo
+ 0x1004ffbe 0x41 _L1e_CmnLogUpdateAbsSfn
+ 0x1004ffff 0xc6 _L1e_CmnLogClearVariableVal
+ 0x100500c5 0x1c8 _L1e_CmnLogDlTbCrcAndThroughPut
+ 0x1005028d 0x3b _L1e_CmnLogStatDlFlowByCc
+ 0x100502c8 0x11 _L1e_CmnLogStatDlThroughPut
+ 0x100502d9 0x45 _L1e_CmnLogDlDdtrCfgTimes
+ 0x1005031e 0x45 _L1e_CmnLogDlDdtrIntTimes
+ 0x10050363 0x86 _L1e_CmnLogStatDlRntiApplyCnt
+ 0x100503e9 0x52 _L1e_CmnLogStatPcfichChannel
+ 0x1005043b 0x15c _L1e_CmnLogStatPhichChannel
+ 0x10050597 0x2a9 _L1e_CmnLogStatPdcchChannel
+ 0x10050840 0xa _L1e_CmnLogStatDlCtrlChMonitor
+ 0x1005084a 0x9e _L1e_CmnLogStatDciDecodeInfo
+ 0x100508e8 0x42 _L1e_CmnLogGetRxTxBitmap
+ 0x1005092a 0x94 _L1e_CmnLogGetCalcSinrValByCc
+ 0x100509be 0x3 _L1e_CmnLogGetCalcSinrVal
+ 0x100509c1 0x24 _L1e_CmnLogStatUlFlowByCc
+ 0x100509e5 0x37 _L1e_CmnLogStatUlThroughPut
+ 0x10050a1c 0x1d _zPHY_GetUlQmMcs
+ 0x10050a39 0x2f _zPHY_GetDlQmMcs
+ 0x10050a68 0xa _zPHY_GetDlSinr
+ 0x10050a72 0x1d _zPHY_GetUlHarqNack
+ 0x10050a8f 0x22 _zPHY_GetDlHarqNack
+ 0x10050ab1 0xf _zPHY_GetDlThrougput
+ 0x10050ac0 0xf _zPHY_GetUlThrougput
+ 0x10050acf 0x1a _zPHY_UlResidualBlerCount
+ 0x10050ae9 0xd _zPHY_AtGetPowerHeadroom
+ 0x10050af6 0x9 _zPHY_AtGetPcmax
+ 0x10050aff 0x26 _zPHY_AtGetRsrpDbm
+ 0x10050b25 0x2a _zPHY_AtGetRssiDbm
+ 0x10050b4f 0x42 _zPHY_AtGetResidualBlerByCc
+ 0x10050b91 0x26 _zPHY_AtGetResidualBler
+ 0x10050bb7 0x1a _zPHY_AtClearVariableVal
+ .text 0x10050bd1 0xbb9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x10050bd1 0x117 _zPHY_Tpu_ExtraCheck
+ 0x10050ce8 0x2a _L1L_TpuAdjCnfMsg
+ 0x10050d12 0x293 _L1L_TpuCpModeSwitchProc
+ 0x10050fa5 0x40 _L1L_TpuDevFixedIntRegister
+ 0x10050fe5 0x3d _L1L_TpuDevTimerUnRegister
+ 0x10051022 0x63 _L1L_TpuMicroAdj
+ 0x10051085 0x7 _L1L_TpuDevMsgDelayMsgTimerRegister
+ 0x1005108c 0x6 _L1L_TpuDevMsgDelayCBTimerRegister
+ 0x10051092 0x15 _L1L_TpuDevRelativeMsgTimerRegister
+ 0x100510a7 0x13 _L1L_TpuDevRelativeCBTimerRegister
+ 0x100510ba 0x36 _L1L_TpuDevMrtrTimeTypeMsgTimerRegister
+ 0x100510f0 0x35 _L1L_TpuDevMrtrTimeTypeCBTimerRegister
+ 0x10051125 0x20 _L1L_TpuSuperSlotGet
+ 0x10051145 0x21 _L1L_TpuMrtrFormat
+ 0x10051166 0x1c _L1L_TpuLocalMrtr2FreeMrtr
+ 0x10051182 0x1c _L1L_TpuFreeMrtr2LocalMrtr
+ 0x1005119e 0xb4 _L1L_TpuProUpdateLocalMRTR
+ 0x10051252 0xa _L1L_TpuTimeSub
+ 0x1005125c 0x13 _L1L_TpuTimeAdd
+ 0x1005126f 0x4d _L1L_TpuTs2Time
+ 0x100512bc 0x17 _L1L_TpuTime2Ts
+ 0x100512d3 0x34 _L1L_TpuMrtrAdd
+ 0x10051307 0x40 _L1L_TpuMrtrSub
+ 0x10051347 0x443 _zPHY_LTE_TPU_ThreadEntry
+ .text 0x1005178a 0x677 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x1005178a 0x40 _zPHY_ecsi_HNoDMA
+ 0x100517ca 0x1 _zPHY_ecsi_PCellCSI_En
+ 0x100517cb 0x1 _zPHY_ecsi_SCellCSI_En
+ 0x100517cc 0x49 _zPHY_ecsi_Init
+ 0x10051815 0x2c _zPHY_ecsi_PCellCommParmUpdate
+ 0x10051841 0x9b _zPHY_ecsi_PCellDediParmUpdate
+ 0x100518dc 0xb7 _zPHY_ecsi_PCellHOParmUpdate
+ 0x10051993 0xd3 _zPHY_ecsi_MsgResponse
+ 0x10051a66 0x2d _zPHY_ecsi_ctrl_GetNodeTXAttennaNum
+ 0x10051a93 0x8c _zPHY_ecsi_CbResSetGet
+ 0x10051b1f 0x2c _zPHY_ecsi_PerCqiParaGet
+ 0x10051b4b 0x23 _zPHY_ecsi_CqiRowAParaCalc
+ 0x10051b6e 0x5c _zPHY_ecsi_PcellCsiRepParaDediGet
+ 0x10051bca 0x3f _zPHY_ecsi_ScellCsiRepParaDediGet
+ 0x10051c09 0x12 _zPHY_ecsi_CsiRsParaGet
+ 0x10051c1b 0x28 _zPHY_ecsi_CSITimeUpdate
+ 0x10051c43 0xac _zPHY_ecsi_FlowPrint
+ 0x10051cef 0x1 _zPHY_ecsi2dl_CHECfg
+ 0x10051cf0 0xab _zPHY_ecsi_Start
+ 0x10051d9b 0x66 _zPHY_ecsi_CSIAThreadEntry
+ .text 0x10051e01 0x104d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x10051e01 0x26 _L1e_DevDlsGetTbCrc
+ 0x10051e27 0x16 _L1e_DevDlsGetTbCbCrc
+ 0x10051e3d 0x9c _L1e_DevDlsSetDlHarqFlag
+ 0x10051ed9 0x43 _L1e_DevDlsGetDdtrWorkSf
+ 0x10051f1c 0x89 _zPHY_edls_ProCwCrcGeneration
+ 0x10051fa5 0xfa _zPHY_edls_ProTddCwCrcFeedback
+ 0x1005209f 0x56 _zPHY_edls_ProFddCwCrcFeedback
+ 0x100520f5 0x115 _zPHY_edls_ProHarqFeedbackInfo
+ 0x1005220a 0x11e _zPHY_edls_ProDdtrHbitInt
+ 0x10052328 0xb3 _zPHY_edls_ProDdtrIntDtch
+ 0x100523db 0xa2 _zPHY_edls_ProDdtrIntSibPch
+ 0x1005247d 0x64 _L1e_DbgDlsDecPchInfo
+ 0x100524e1 0x2d _L1e_DevDlsPageMatch
+ 0x1005250e 0x5e _L1e_DevDlsPchMessagePro
+ 0x1005256c 0x5b _L1e_DevDlsPchReportInd
+ 0x100525c7 0x56 _zPHY_edls_ProPchDataProc
+ 0x1005261d 0x48 _zPHY_edls_ProSibDataProc
+ 0x10052665 0x5b _zPHY_edls_ProPchStatAndPrint
+ 0x100526c0 0x53 _zPHY_edls_ProSibStatAndPrint
+ 0x10052713 0x75 _zEumacdl_CrExist
+ 0x10052788 0x285 _L1e_DevDlsCfgMacPduCtrlInfo
+ 0x10052a0d 0x32 _L1e_DevDlsReportMacPdu
+ 0x10052a3f 0x1dc _zPHY_edls_ProDschIntThread
+ 0x10052c1b 0x5c _zPHY_edls_ProMsg2RaRntiMacPdu
+ 0x10052c77 0x36 _zPHY_edls_PDschIsr
+ 0x10052cad 0x7f _L1e_DbgDlsAckNakRptInfo
+ 0x10052d2c 0x122 _L1e_DbgDlsDecStatInfo
+ .text 0x10052e4e 0x6f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x10052e4e 0x51 _zPHY_edls_ProPdcchIntThread
+ 0x10052e9f 0x44 _zPHY_edls_ProMsg4CRntiPdcch
+ 0x10052ee3 0x6a _zPHY_edls_DciIsr
+ 0x10052f4d 0xc _zPHY_edls_ProSetVoLteTime
+ 0x10052f59 0x23 _zLtePsPhy_RemoteMalloc
+ 0x10052f7c 0x35 _zPHY_edls_ProStoreSpsInfo
+ 0x10052fb1 0x17 _L1e_DevDlsRstRxRbBmpReg
+ 0x10052fc8 0x42 _L1e_DevDlsRefSenCntPro
+ 0x1005300a 0x72 _L1e_DevDlsRefSenPro
+ 0x1005307c 0xf _L1e_DevDlsBfInd
+ 0x1005308b 0x39 _zPHY_edls_DdtrHwIdleState
+ 0x100530c4 0x25 _L1x_DevDlsInOutJudge
+ 0x100530e9 0x4e _L1e_DbgDlsCommDecInfo
+ 0x10053137 0xce _L1e_DbgDlsDciInfo
+ 0x10053205 0x51 _L1e_DbgDlsDecErr
+ 0x10053256 0x1 _L1e_DbgDlsValidRptInfo
+ 0x10053257 0x58 _zPHY_edls_ProDbgSpsDciDetInfo
+ 0x100532af 0x291 _zPHY_edls_DbgHarqDdrClose
+ .text 0x10053540 0x2d58 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x10053540 0x3a _zPHY_erfc_ProSetRamSFNumForLargeAdj
+ 0x1005357a 0x46 _zPHY_erfc_ProGetMeas0RamNum
+ 0x100535c0 0x37 _zPHY_erfc_ProGetTxRamNum
+ 0x100535f7 0x34 _zPHY_erfc_ProGetNextSubFrameOffset
+ 0x1005362b 0x96 _zPHY_erfc_SupLteTxEnableCtrl
+ 0x100536c1 0xc _zPHY_erfc_ProSpecSubfrmCheck
+ 0x100536cd 0x23 _zPHY_erfc_ProTxSendCtrl
+ 0x100536f0 0x25 _zPHY_erfc_SupDFESubframeStartCtl
+ 0x10053715 0x311 _zPHY_erfc_ProRamCtrl
+ 0x10053a26 0x1 _zPHY_erfc_ProPrintProcess
+ 0x10053a27 0x27 _zPHY_erfc_ProNotchProCtrl
+ 0x10053a4e 0x10 _zPHY_erfc_ProGetFreqBandNum
+ 0x10053a5e 0x238 _zPHY_erfc_TDDProRFABB_RxToRx
+ 0x10053c96 0xe1 _zPHY_erfc_TDDProRFABB_RxToIdle
+ 0x10053d77 0x4c _zPHY_erfc_TDDProRFABB_RxToTx
+ 0x10053dc3 0x31 _zPHY_erfc_TDDProRFABB_IdleToTx
+ 0x10053df4 0x2ee _zPHY_erfc_TDDProRFABB_IdleToRx
+ 0x100540e2 0x1 _zPHY_erfc_TDDProRFABB_IdleToIdle
+ 0x100540e3 0x30 _zPHY_erfc_TDDProRFABB_TxToIdle
+ 0x10054113 0x108 _zPHY_erfc_TDDProRFABB_TxToRx
+ 0x1005421b 0x1 _zPHY_erfc_TDDProRFABB_TxToTx
+ 0x1005421c 0x58 _zPHY_erfc_ATSetAndReadRfReg
+ 0x10054274 0x534 _zPHY_erfc_ProRFABBCtrl
+ 0x100547a8 0xa07 _zPHY_erfc_ProRFABBCtrl_FDD
+ 0x100551af 0x5b _zPHY_erfc_Pro_IFTempNeedFix
+ 0x1005520a 0x343 _zPHY_erfc_ProRFCWork
+ 0x1005554d 0x58 _zPHY_erfc_ProRxOffsetAutoCtrl
+ 0x100555a5 0x10 _zPHY_erfc_ProTAOffsetAutoCtrl
+ 0x100555b5 0x3b8 _zPHY_erfc_ProTxAndRxOffsetCtrl
+ 0x1005596d 0xe _zPHY_erfc_ProRFSDInit
+ 0x1005597b 0xa _zPHY_erfc_ProRFCSA_CSRConfig
+ 0x10055985 0xe _zPHY_erfc_ProRFCSA_RXConfig
+ 0x10055993 0xa _zPHY_erfc_ProRFCSA_TXConfig
+ 0x1005599d 0x95 _zPHY_erfc_ProRFSDAndRFCSAInit
+ 0x10055a32 0x4b _zPHY_erfc_RpiCfg
+ 0x10055a7d 0x1d _zPHY_erfc_RpiSet
+ 0x10055a9a 0x5d _zPHY_erfc_RpiPwrCtrl
+ 0x10055af7 0x72 _zPHY_erfc_ProRFCSAInit
+ 0x10055b69 0x6f _zPHY_erfc_ProRFCInit
+ 0x10055bd8 0x54 _zPHY_erfc_ProRFCInitPointer
+ 0x10055c2c 0x18d _zPHY_erfc_ProRfsdCheck_FDD
+ 0x10055db9 0x3f _zPHY_erfc_CheckNextSccRfcToIdle
+ 0x10055df8 0x17 _zPHY_erfc_ProGetRFCCurrentState
+ 0x10055e0f 0x1e2 _zPHY_erfc_ThreadEntry
+ 0x10055ff1 0x16 _zPHY_erfc_GetRfcMeasStatus
+ 0x10056007 0x19 _zPHY_erfc_TjpAlgorithm
+ 0x10056020 0x3d _zPHY_erfc_CalcMeasSubfNum
+ 0x1005605d 0x3f _zPHY_erfc_CalcSyncSubfNum
+ 0x1005609c 0x1a _zPHY_erfc_IntraFrameTimeComp
+ 0x100560b6 0x1 _zPHY_erfc_ProCleanHWTable
+ 0x100560b7 0x47 _zPHY_erfc_LTXTxTaConfig
+ 0x100560fe 0x36 _zPHY_erfc_ProCopyTxPccParaToScc
+ 0x10056134 0x1 _zPHY_erfc_RXTX_PathTest
+ 0x10056135 0x27 _zPHY_erfc_MainSlave_InterSwitch
+ 0x1005615c 0x5b _zPHY_erfc_GetTxTabAdjust
+ 0x100561b7 0xa _zPHY_erfc_GetFixDlDelay
+ 0x100561c1 0xd _L1l_DevRfcRxOffsetGet
+ 0x100561ce 0xd _L1l_DevRfcTaTimingGet
+ 0x100561db 0x9 _L1l_DevRfcRatModeSet
+ 0x100561e4 0xc _L1l_DevRfcTmpReadEn
+ 0x100561f0 0x9a _L1l_DevRfcTmpReadCtrl
+ 0x1005628a 0x7 _L1l_DevRfcSetOffsetFlag
+ 0x10056291 0x7 _L1l_DevRfcGetOffsetFlag
+ .text 0x10056298 0x2c1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x10056298 0xf _zPHY_eCSI_Calc_MultiPmiAddr_Init
+ 0x100562a7 0x8 _OSMemCopy16
+ 0x100562af 0x6 _OSMemCopy32
+ 0x100562b5 0x23 _IsTM9_PMIRIEn_CSIRS_2_4
+ 0x100562d8 0x16 _IsTM8_PMIRIEn
+ 0x100562ee 0x1a _zPHY_eCSI_Calc_Sort
+ 0x10056308 0x27 _zPHY_eCSI_Calc_MaxM
+ 0x1005632f 0x16 _zPHY_eCSI_Calc_CapMaxVal
+ 0x10056345 0x20 _zPHY_eCSI_Calc_GetSubbandIdx
+ 0x10056365 0x6c _zPHY_eCSI_Calc_eesm
+ 0x100563d1 0x59 _zPHY_eRLM_Calc_eesm
+ 0x1005642a 0x161 _zPHY_eCSI_Calc_LookupCqiTable
+ 0x1005658b 0x47 _zPHY_eCSI_Calc_WideTotalCapCalc
+ 0x100565d2 0x33 _zPHY_eCSI_Calc_WideTotalCapCalc_PerRI
+ 0x10056605 0x8e _zPHY_eCSI_Calc_WideHigh2UESubCap
+ 0x10056693 0x10c _zPHY_eCSI_Calc_BPMI
+ 0x1005679f 0x3e _zPHY_eCSI_Calc_SPMI
+ 0x100567dd 0x185 _zPHY_eCSI_Calc_RI_TM3
+ 0x10056962 0x127 _zPHY_eCSI_Calc_WPMI_TM4_LastRI
+ 0x10056a89 0x2d0 _zPHY_eCSI_Calc_RI_WPMI_TM4
+ 0x10056d59 0xe5 _zPHY_eCSI_Adjust_RI_PMI
+ 0x10056e3e 0x2e4 _zPHY_eCSI_Calc_RI_PMI
+ 0x10057122 0xd6 _zPHY_eCSI_Calc_WbCQICalc
+ 0x100571f8 0x98 _zPHY_eCSI_Calc_NoPmiGetMsbIdx
+ 0x10057290 0x82 _zPHY_eCSI_Calc_MsbCqiCalc
+ 0x10057312 0xc1 _zPHY_eCSI_Calc_SbCqiCalc
+ 0x100573d3 0x16 _zPHY_eCSI_Calc_Curr_SBSize_Get
+ 0x100573e9 0xcf _zPHY_eCSI_Calc_BpCqiCalc
+ 0x100574b8 0x6d _zPHY_eCSI_Calc_AperSbCqiUpDown
+ 0x10057525 0xb7 _zPHY_eCSI_Calc_AperCQI
+ 0x100575dc 0x9e _zPHY_eCSI_Calc_PerCQI
+ 0x1005767a 0x33 _zPHY_eCSI_Calc_Radio_Monitor
+ 0x100576ad 0x19 _zPHY_eCSI_Calc_BitReversal
+ 0x100576c6 0xf _zPHY_eCSI_Calc_GetPmiBitNum
+ 0x100576d5 0x13 _zPHY_eCSI_Calc_GetMSubbandDifferentCqiValue
+ 0x100576e8 0xf _zPHY_eCSI_Calc_GetSubbandDifferentCqiValue
+ 0x100576f7 0x30 _zPHY_eCSI_CalcMSubbandPosition
+ 0x10057727 0x18 _zPHY_eCSI_FindDiffCQI
+ 0x1005773f 0x297 _zPHY_eCSI_PER_BagPack
+ 0x100579d6 0x5ea _zPHY_eCSI_APER_BagPack
+ 0x10057fc0 0x29 _zPHY_eCSI_PER_PmiBitLen_Estimate
+ 0x10057fe9 0x52 _zPHY_eCSI_APER_PmiBitLen_Estimate
+ 0x1005803b 0x1d _zPHY_ecqi_GetLookTableSNR
+ 0x10058058 0x70 _zPHY_ecsi_Calc_Pow10_inDiv10
+ 0x100580c8 0x3e _zPHY_ecsi_Calc_Get_InvRow_feedA
+ 0x10058106 0x49 _zPHY_ecqi_Calc_Get_InvRowB_lin
+ 0x1005814f 0x243 _zPHY_ecqi_Calc_CSIRltPrint
+ 0x10058392 0x8e _zPHY_eCSI_Calc_ParaInitInDedi
+ 0x10058420 0x211 _zPHY_ecqi_SnrConv
+ 0x10058631 0x1 _zPHY_ecqi_CQISnrPrint
+ 0x10058632 0x1 _zPHY_ecqi_RlmSnrPrint
+ 0x10058633 0x1 _zPHY_ecqi_RiCapPrint
+ 0x10058634 0x60 _zPHY_ecqi_CQIFilter
+ 0x10058694 0x88 _zPHY_ecqi_Sqrt
+ 0x1005871c 0x126 _zPHY_ecsi_Calc_EstiFormatTransform
+ 0x10058842 0x11 _zPHY_ecsi_Calc_LTE_RICapFollowHw0
+ 0x10058853 0x12 _zPHY_ecsi_Calc_LTE_RICapFollowHw1
+ 0x10058865 0x16 _zPHY_ecsi_Calc_LTE_RICapFollowHw2
+ 0x1005887b 0x1c _zPHY_ecsi_Calc_LTE_RICapFollowHw4
+ 0x10058897 0x149 _zPHY_ecsi_Calc_LTE_RICloseLoop
+ 0x100589e0 0x18b _zPHY_ecsi_Calc_LTE_RIOpenLoop
+ 0x10058b6b 0x90 _zPHY_ecsi_Calc_LTE_2Tx2Rx2LWbPMI
+ 0x10058bfb 0xb1 _zPHY_ecsi_Calc_LTE_PeriodWBPmi
+ 0x10058cac 0x79 _zPHY_ecsi_Calc_LTE_GetCQICalcFunc
+ 0x10058d25 0xab _zPHY_ecsi_Calc_LTE_GetCQISNR
+ 0x10058dd0 0x16 _zPHY_ecsi_Calc_LTE_PerCQISNRCalc
+ 0x10058de6 0x94 _zPHY_ecsi_Calc_LTE_AperCQISNRCalc
+ 0x10058e7a 0x3b _zPHY_ecsi_Calc_LTE_RLMSNRCalc
+ .text 0x10058eb5 0x1592 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x10058eb5 0x1b _zPHY_Dl_HwReset
+ 0x10058ed0 0x2a0 _zPHY_epbch_ThreadEntry
+ 0x10059170 0x9a _L1e_Bch_UpdateRxRegs
+ 0x1005920a 0xa _L1e_Bch_ResetProc
+ 0x10059214 0x19 _L1e_Bch_ClkPowerCtrl
+ 0x1005922d 0x2e _L1e_Bch_JudgeSlavePbch
+ 0x1005925b 0x6 _L1e_Bch_GetMaxAntCnt
+ 0x10059261 0x1b _L1e_Bch_BwValid
+ 0x1005927c 0x10 _L1e_Bch_AntValid
+ 0x1005928c 0x7 _L1e_Bch_FrmTyeValid
+ 0x10059293 0x7 _L1e_Bch_SpecPatValid
+ 0x1005929a 0x8e _L1e_Bch_UpdateDb
+ 0x10059328 0x72 _L1e_Bch_CellSync
+ 0x1005939a 0x2b _L1e_Bch_UpRxCtrlOps
+ 0x100593c5 0x8 _L1e_Bch_ClrSyncOps
+ 0x100593cd 0x7 _L1e_Bch_QuerySyncOps
+ 0x100593d4 0x45 _L1e_Bch_PreDecProc
+ 0x10059419 0x3f _L1e_Bch_UpRxState
+ 0x10059458 0x2d _L1e_Bch_InitAllGVar
+ 0x10059485 0x2a _L1e_Bch_AddSpecTpuEvt
+ 0x100594af 0x2d _L1e_Bch_DelAllTpuEvt
+ 0x100594dc 0x1d _L1e_Bch_DelSpecTpuEvt
+ 0x100594f9 0x1a _L1e_Bch_QueryTpuEvt
+ 0x10059513 0x31 _L1e_Bch_CalStartAddr
+ 0x10059544 0x1b _L1e_Bch_GetTpuOffset
+ 0x1005955f 0x43 _L1e_Bch_CalBodryDis
+ 0x100595a2 0x1c _L1e_Bch_RegRxNewFrmEvt
+ 0x100595be 0x1 _L1e_Bch_SaveRfcSyncTable
+ 0x100595bf 0x5e _L1e_Bch_UpRfcCfg
+ 0x1005961d 0x39 _L1e_Bch_RegTpuAdjEvt
+ 0x10059656 0x86 _L1e_Bch_InitBchRegFile
+ 0x100596dc 0x72 _L1e_Bch_GenRxRsScrm
+ 0x1005974e 0xc9 _L1e_Bch_InitRxRegFile
+ 0x10059817 0x6e _L1e_Bch_GetSfnOffset
+ 0x10059885 0x5d _L1e_Bch_StopMibProc
+ 0x100598e2 0x64 _L1e_Bch_Decode
+ 0x10059946 0x89 _L1e_Bch_RltReport
+ 0x100599cf 0x11 _L1e_Bch_StartMib
+ 0x100599e0 0xe _L1e_Bch_GetMibIntCnt
+ 0x100599ee 0x2b _L1e_Bch_ModifyParaForBldDetect
+ 0x10059a19 0x2a _L1e_Bch_StartAnr
+ 0x10059a43 0x45 _L1e_Bch_AnrDecPorc
+ 0x10059a88 0xa7 _L1e_Bch_FrmIntCheck
+ 0x10059b2f 0xc _L1e_Bch_FristBchFrm
+ 0x10059b3b 0xe2 _L1e_Bch_NewFrmDecPorc
+ 0x10059c1d 0x1a _L1e_Bch_EnableSF0RxRcv
+ 0x10059c37 0x9a _L1e_Bch_AdjTpuTime
+ 0x10059cd1 0x18 _L1e_Bch_GetMibResult
+ 0x10059ce9 0x14 _L1e_Bch_CalcInitFrm
+ 0x10059cfd 0x1c _L1e_Bch_MibInfoCheck
+ 0x10059d19 0x3a _L1e_Bch_HandleCrcResult
+ 0x10059d53 0x18 _L1e_Bch_NxtBranchCtrl
+ 0x10059d6b 0xf0 _L1e_Bch_StartNxtDecode
+ 0x10059e5b 0x66 _L1e_Bch_DecideNxtDecode
+ 0x10059ec1 0x5c _L1e_Bch_IntHandle
+ 0x10059f1d 0x49 _L1e_Bch_SaveDlapara
+ 0x10059f66 0x47 _L1e_Bch_ResumeDlapara
+ 0x10059fad 0x53 _L1e_Bch_GetNCellRsNullInd
+ 0x1005a000 0x2e _L1e_Bch_GetNCellRsNullValid
+ 0x1005a02e 0x17 _L1e_Bch_WriteIntraMeasResult
+ 0x1005a045 0x90 _L1e_Bch_GetIntraMeasResult
+ 0x1005a0d5 0x6f _L1e_Bch_SortIntraMeasResult
+ 0x1005a144 0x8 _L1e_Bch_GetMibProc
+ 0x1005a14c 0x6d _L1e_Bch_Performance
+ 0x1005a1b9 0x17 _L1e_Bch_ErrorMoniter
+ 0x1005a1d0 0xc4 _L1e_Bch_RxRsrpMoniter
+ 0x1005a294 0x38 _L1e_Bch_MibReqMonitor
+ 0x1005a2cc 0x59 _L1e_Bch_RfcTpuMonitor
+ 0x1005a325 0x67 _L1e_Bch_IntRptMonitor
+ 0x1005a38c 0x6c _L1e_Bch_CrcRltMonitor
+ 0x1005a3f8 0x32 _L1e_Bch_RxParaMonitor
+ 0x1005a42a 0x1d _L1e_Bch_SerPbchRead
+ .text 0x1005a447 0x9e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x1005a447 0x7b _zPHY_edls_DlHarqReport
+ 0x1005a4c2 0x35 _zPHY_edls_ProDlHarqInit
+ 0x1005a4f7 0x6d _zPHY_edls_ProGvInit
+ 0x1005a564 0x8c _zPHY_edls_ProCommDlschParaInit
+ 0x1005a5f0 0x42 _zPHY_edls_ProSwInit
+ 0x1005a632 0xc _zPHY_edls_ProMcReleaseMsg
+ 0x1005a63e 0x4c _zPHY_edls_ProMsg4AckFeedback
+ 0x1005a68a 0xc _zPHY_edls_ProMcResetMsg
+ 0x1005a696 0x23 _zPHY_edls_ProMcMacResetMsg
+ 0x1005a6b9 0x27 _zPHY_edls_CheckHarqGroupNum
+ 0x1005a6e0 0x116 _zPHY_edls_ThreadEntry
+ 0x1005a7f6 0x4a _zPHY_edls_ProCommDlschParaCal
+ 0x1005a840 0x1 _L1e_DevDlsDdtrAxiReset
+ 0x1005a841 0x1 _L1e_DevDlsProcAxiReset
+ 0x1005a842 0xbe _L1e_DevDlsUeRacpParamInit
+ 0x1005a900 0x4b _L1e_DevDlsDecoderInit
+ 0x1005a94b 0x3e _L1e_DevDlsHarqHwInit
+ 0x1005a989 0x6c _L1e_DevDlsDdtrHwInit
+ 0x1005a9f5 0x17 _L1e_DevDlsRxTMIndCfg
+ 0x1005aa0c 0x1f _L1e_DevDlsSpsParamCfg
+ 0x1005aa2b 0x45 _L1e_DevDlsCsiRsParamCfg
+ 0x1005aa70 0x6d _L1e_DevDlsProcCommonMsg
+ 0x1005aadd 0x5e _L1e_DevDlsProcDedicatedMsg
+ 0x1005ab3b 0xa5 _L1e_DevDlsProcHandoverMsg
+ 0x1005abe0 0x8 _zPHY_edls_ProSetSpsMode
+ 0x1005abe8 0x8 _zPHY_edls_ProGetSpsMode
+ 0x1005abf0 0xe _L1e_DevDlsSetTimeInfo
+ 0x1005abfe 0xd _L1e_DevDlsSetCellParam1
+ 0x1005ac0b 0xd _L1e_DevDlsSetCellparam2
+ 0x1005ac18 0xd _L1e_DevDlsSetRntiInfo
+ 0x1005ac25 0xf _L1e_DevDlsGetTimeInfo
+ 0x1005ac34 0x1a _L1e_DevDlsGetCellParam1
+ 0x1005ac4e 0x1a _L1e_DevDlsGetCellParam2
+ 0x1005ac68 0x1a _L1e_DevDlsGetRntiInfo
+ 0x1005ac82 0x19 _L1e_DevDlsSetDciF1aPld
+ 0x1005ac9b 0x10 _L1e_DevDlsSetDciF1cPld
+ 0x1005acab 0x10 _L1e_DevDlsSetDciFxxPld
+ 0x1005acbb 0xe _L1e_DevDlsSetDciCifSize
+ 0x1005acc9 0xe _L1e_DevDlsSetDciRaHeaderSize
+ 0x1005acd7 0x10 _L1e_DevDlsSetDciRbaSize
+ 0x1005ace7 0xe _L1e_DevDlsSetDciHarqIdSize
+ 0x1005acf5 0xe _L1e_DevDlsSetDciDaiSize
+ 0x1005ad03 0xe _L1e_DevDlsSetDciTpmiSize
+ 0x1005ad11 0xe _L1e_DevDlsSetDciScidSize
+ 0x1005ad1f 0xe _L1e_DevDlsSetDciSrsReqSize
+ 0x1005ad2d 0x1a _L1e_DevDlsGetDciF1aPld
+ 0x1005ad47 0x10 _L1e_DevDlsGetDciF1cPld
+ 0x1005ad57 0x10 _L1e_DevDlsGetDciFxxPld
+ 0x1005ad67 0xd _L1e_DevDlsGetDciCifSize
+ 0x1005ad74 0xd _L1e_DevDlsGetDciRaHeaderSize
+ 0x1005ad81 0x11 _L1e_DevDlsGetDciRbaSize
+ 0x1005ad92 0xd _L1e_DevDlsGetDciHarqIdSize
+ 0x1005ad9f 0xd _L1e_DevDlsGetDciDaiSize
+ 0x1005adac 0xd _L1e_DevDlsGetDciTpmiSize
+ 0x1005adb9 0xd _L1e_DevDlsGetDciScidSize
+ 0x1005adc6 0xd _L1e_DevDlsGetDciSrsReqSize
+ 0x1005add3 0x8 _L1e_DevDlsDdtrUpdateCntCbInit
+ 0x1005addb 0xc _L1e_DevDlsDdtrUpdateCntInc
+ 0x1005ade7 0xc _L1e_DevDlsDdtrUpdateCntClr
+ 0x1005adf3 0x9 _L1e_DevDlsGetDdtrCcUpdateCnt
+ 0x1005adfc 0x7 _L1e_DevDlsGetDdtrUpdateCnt
+ 0x1005ae03 0x7 _L1e_DevDlsSetMsg4RaConflictCnt
+ 0x1005ae0a 0x7 _L1e_DevDlsGetMsg4RaConflictCnt
+ 0x1005ae11 0x9 _L1e_DevDlsMsg4RaConflictCntDec
+ 0x1005ae1a 0x8 _L1e_DevDlsMsg4RaConflictCntClr
+ 0x1005ae22 0x8 _L1e_DevDlsGetTransMode
+ .text 0x1005ae2a 0xbf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x1005ae2a 0x69 _zPHY_ecsi_ctrl_Init
+ 0x1005ae93 0x80 _zPHY_ecsi_StaticBandParaUpdata
+ 0x1005af13 0x28 _zPHY_ecsi_ctrl_PeriodParaUpdate
+ 0x1005af3b 0x7a _zPHY_ecsi_ctrl_AperiodParaUpdate
+ 0x1005afb5 0x7d _zPHY_ecsi_ctrl_AperRepJudge
+ 0x1005b032 0x3f _zPHY_ecsi_ctrl_GetSubbandIdx
+ 0x1005b071 0x51 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcTDD
+ 0x1005b0c2 0x57 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcFDD
+ 0x1005b119 0x32 _zPHY_ecsi_ctrl_RiConfigIndexCalc
+ 0x1005b14b 0x6b _zPHY_ecsi_ctrl_GetPeriodPara
+ 0x1005b1b6 0x14a _zPHY_ecsi_ctrl_GetPeriodRepType
+ 0x1005b300 0xcb _zPHY_ecsi_ctrl_LastRIInit
+ 0x1005b3cb 0x4a _zPHY_ecsi_ctrl_GetMaxLayerNum
+ 0x1005b415 0x71 _zPHY_ecsi_ctrl_SecondCfg
+ 0x1005b486 0x8 _zPHY_ecsi_ctrl_SentCqiRlmProMsg
+ 0x1005b48e 0xc _zPHY_ecsi_ctrl_RlmProEn
+ 0x1005b49a 0x87 _zPHY_ecsi_ctrl_FirIntPrint
+ 0x1005b521 0xa9 _zPHY_ecsi_ctrl_FdBkFirst_IntIsr
+ 0x1005b5ca 0x1e _zPHY_ecsi_ctrl_FdBkSecond_IntIsr
+ 0x1005b5e8 0x1b _zPHY_ecsi_ctrl_FdBk_IntIsr
+ 0x1005b603 0x5c _zPHY_ecsi_ctrl_First_GetEnStep1
+ 0x1005b65f 0x69 _zPHY_ecsi_ctrl_FdBkFirCfgAper
+ 0x1005b6c8 0xbd _zPHY_ecsi_ctrl_FdBkFirCfgPer
+ 0x1005b785 0xcd _zPHY_ecsi_ctrl_First_FdBkCfg
+ 0x1005b852 0x3a _zPHY_ecsi_ctrl_ULGetCSI_Callback
+ 0x1005b88c 0x71 _zPHY_ecsi_Ctrl_CqiRlmCalc
+ 0x1005b8fd 0x2f _zPHY_ecsi_ctrl_PreBagPack
+ 0x1005b92c 0x33 _zPHY_ecsi_ctrl_FindPreDlSfn
+ 0x1005b95f 0xbd _zPHY_ecsi_ctrl_DrxRfZspCtrl
+ .text 0x1005ba1c 0x1ab3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x1005ba1c 0x7 _L1e_DevRxGetAveSinr
+ 0x1005ba23 0x1d _zPHY_erxp_convert_RbNum_to_BWIdx
+ 0x1005ba40 0x7 _L1e_DevRxCirSetIdleAccessReqInd
+ 0x1005ba47 0x7 _L1e_DevRxCirGetIdleAccessReqInd
+ 0x1005ba4e 0x1b2 _zPHY_erxph_ThreadEntry
+ 0x1005bc00 0x173 _L1e_DevRxPowerPrepare
+ 0x1005bd73 0x55 _L1e_DevRxGetSnrFilterFactor
+ 0x1005bdc8 0xa0 _zPHY_erxp_PowerFilterInit
+ 0x1005be68 0x97 _zPHY_erxp_ProPowerFilter
+ 0x1005beff 0x149 _zPHY_erxp_ProSnrMake
+ 0x1005c048 0x64 _zPHY_erxp_ProSnrDB
+ 0x1005c0ac 0x54 _zPHY_erxp_ProLog2
+ 0x1005c100 0x19e _L1e_DevRxProcPwrNbnb
+ 0x1005c29e 0x8a _L1e_DevRxCalcRsrpPwr
+ 0x1005c328 0x36 _L1e_DevRxProcSnrPwrFilter
+ 0x1005c35e 0x50 _L1e_DevRxCalcLinearSnr
+ 0x1005c3ae 0x3e _L1e_DevRxCalcLinearSinr
+ 0x1005c3ec 0x5c _L1e_DevRxConvertSnrDbValue
+ 0x1005c448 0x88 _L1e_DevRxCalcAveSnr
+ 0x1005c4d0 0xa _L1e_DevRxGetAveSnr
+ 0x1005c4da 0xa _L1e_DevRxGetNeiAveSnr
+ 0x1005c4e4 0x14 _L1e_DevRxCalSign
+ 0x1005c4f8 0xa6 _L1e_DevRxCalcMod
+ 0x1005c59e 0x6e _L1e_DevRxDbgMsgRxCrsPwr
+ 0x1005c60c 0x91 _L1e_DevRxDbgMsgRxDrsPwr
+ 0x1005c69d 0x5d _L1e_DevRxDbgMsgRxSnrInfo
+ 0x1005c6fa 0x81 _L1e_DevRxDbgMsgSyncInfo
+ 0x1005c77b 0x48 _L1e_LogDevRxMbsfnCsiInfo
+ 0x1005c7c3 0x54 _L1e_DevRxDbgMsgRxHResult
+ 0x1005c817 0x54 _L1e_DevRxDbgMsgRxPrbN0
+ 0x1005c86b 0x17 _L1e_DevRxExpInfo
+ 0x1005c882 0x1c _L1e_DevRxRssiRead
+ 0x1005c89e 0x2b _L1e_DevRxRspRead
+ 0x1005c8c9 0x25 _L1e_DevRxRsrpRead
+ 0x1005c8ee 0x43 _L1e_DevRxN0Read
+ 0x1005c931 0x15 _L1e_DevRxMrsN0Read
+ 0x1005c946 0x7a _L1e_DevRxGetRxLogInfo
+ 0x1005c9c0 0x20 _L1e_DevRxGetDfeAgcGain
+ 0x1005c9e0 0x14 _L1e_DevRxGetRxAntNum
+ 0x1005c9f4 0x7 _L1e_DevRxSetSingleAntInd
+ 0x1005c9fb 0x7 _L1e_DevRxGetSingleAntInd
+ 0x1005ca02 0x9 _L1e_DevRxSetNbNbSinrCalInd
+ 0x1005ca0b 0x9 _L1e_DevRxGetNbNbSinrCalInd
+ 0x1005ca14 0x9 _L1e_DevRxSetDrsAccNum
+ 0x1005ca1d 0x9 _L1e_DevRxGetDrsAccNum
+ 0x1005ca26 0x9 _L1e_DevRxSetBfDagcFlag
+ 0x1005ca2f 0x9 _L1e_DevRxGetBfDagcFlag
+ 0x1005ca38 0x5f _L1e_DevRxProcBfDagcFlag
+ 0x1005ca97 0x7 _L1e_DevRxPrintCtrlCfg
+ 0x1005ca9e 0x7 _L1e_DevRxPrintCtrlGet
+ 0x1005caa5 0x9 _L1e_DevRxPrintCtrlCnt
+ 0x1005caae 0x22c _L1e_DevRxCalcCsi
+ 0x1005ccda 0x11c _L1e_DevRxCsiLog
+ 0x1005cdf6 0xe _L1e_DevRxSetAntChangeInd
+ 0x1005ce04 0xd _L1e_DevRxGetAntChangeInd
+ 0x1005ce11 0xb4 _zPHY_erxp_RX_DFE_UERS
+ 0x1005cec5 0x10 _zPHY_erxp_RX_SNR
+ 0x1005ced5 0xe _L1e_DevRxSetCfoWorkInd
+ 0x1005cee3 0xd _L1e_DevRxGetCfoWorkInd
+ 0x1005cef0 0x1f _L1e_DevRxSetSinrInd
+ 0x1005cf0f 0x10 _L1e_DevRxGetSinrInd
+ 0x1005cf1f 0x2b _L1e_DevRxGetLowSinrInd
+ 0x1005cf4a 0x11 _L1e_DevReadSnr
+ 0x1005cf5b 0x8 _L1e_DevRxClearFilterInd
+ 0x1005cf63 0x42 _L1e_DevGetNeiBorCellMaxSnr
+ 0x1005cfa5 0x7 _L1e_DevRxGetCellComponState
+ 0x1005cfac 0x7 _L1e_DevRxSetCellComponState
+ 0x1005cfb3 0x7 _L1e_DevRxSetAdaptAntProcInd
+ 0x1005cfba 0x7 _L1e_DevRxGetAdaptAntProcInd
+ 0x1005cfc1 0xaa _L1e_DevRxAdaptAntProc
+ 0x1005d06b 0x44 _L1e_DevRxAdaptAntResult
+ 0x1005d0af 0x3a _L1e_DevRxAdaptAntUpdate
+ 0x1005d0e9 0x36 _L1e_DevRxAdaptSinrAcc
+ 0x1005d11f 0x101 _L1e_DevRxAdaptCalSinr
+ 0x1005d220 0x34 _L1e_DevRxAdaptAgcGainAcc
+ 0x1005d254 0x10 _L1e_DevRxAdaptGetAveResult
+ 0x1005d264 0x8 _L1e_DevRxAdaptGetRsrpRange
+ 0x1005d26c 0x58 _L1e_DevRxAdaptSetRsrpInterval
+ 0x1005d2c4 0x13 _L1e_DevRxClrAdaptAntInfo
+ 0x1005d2d7 0xa _L1e_DevRxAdaptBetaUpdate
+ 0x1005d2e1 0x26 _L1e_DevRxAdaptJudge
+ 0x1005d307 0xa _L1e_DevRxIncN1Timer
+ 0x1005d311 0x8 _L1e_DevRxGetN1Timer
+ 0x1005d319 0x9 _L1e_DevRxClrN1Timer
+ 0x1005d322 0x8 _L1e_DevRxSetN1StartInd
+ 0x1005d32a 0x8 _L1e_DevRxGetN1StartInd
+ 0x1005d332 0xa _L1e_DevRxIncN2Timer
+ 0x1005d33c 0x9 _L1e_DevRxClrN2Timer
+ 0x1005d345 0x8 _L1e_DevRxGetN2Timer
+ 0x1005d34d 0x8 _L1e_DevRxSetN2StartInd
+ 0x1005d355 0x8 _L1e_DevRxGetN2StartInd
+ 0x1005d35d 0x8 _L1e_DevRxSetAdaptStartInd
+ 0x1005d365 0xa _L1e_DevRxGetDLTimer
+ 0x1005d36f 0x8 _L1e_DevRxGetAdaptStartInd
+ 0x1005d377 0x8 _L1e_DevRxGetAdaptResult
+ 0x1005d37f 0x8 _L1e_DevRxSetAdaptResult
+ 0x1005d387 0x8 _L1e_DevRxSetAdaptChangeInd
+ 0x1005d38f 0x8 _L1e_DevRxGetAdaptChangeInd
+ 0x1005d397 0x64 _L1e_DevRxDbgAdptAntInfo
+ 0x1005d3fb 0x6f _L1e_DevRxDbgAdptchangeInfo
+ 0x1005d46a 0x65 _L1e_DevRxAntInfoGetForTool
+ .text 0x1005d4cf 0x1c42 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x1005d4cf 0x69 _zPHY_LteaSysInfoPrint
+ 0x1005d538 0x1d _L1L_elpc_Dvfs
+ 0x1005d555 0x107 _zPHY_elpc_LtePhyTaskStateInfo
+ 0x1005d65c 0x9 _zPHY_elpc_SetCfunFlg
+ 0x1005d665 0x42 _zPHY_elpc_SetLteCamonFlag
+ 0x1005d6a7 0x22 _zPHY_elpc_SetLteConnectFlag
+ 0x1005d6c9 0x28 _zPHY_elpc_SetIratGapReportFlag
+ 0x1005d6f1 0x19 _L11_DrvLpcModemIntCtrl
+ 0x1005d70a 0xe _zPHY_elpc_SetlLtePhySleepFlag
+ 0x1005d718 0x1f _zPHY_elpc_LteIdleTaskStateCtrl
+ 0x1005d737 0x264 _zPHY_elpc_UpdateLteSubFrameNum
+ 0x1005d99b 0x24 _L1L_UpdateAwakeTimer
+ 0x1005d9bf 0x1e _L1L_SetAwakeTimer
+ 0x1005d9dd 0xc _L1L_IsAwakeTimerEnable
+ 0x1005d9e9 0x38 _zPHY_elpc_ProKeepAwakeTimer
+ 0x1005da21 0x87 _zPHY_elpc_ProSleepTimer
+ 0x1005daa8 0x2 _L1_TdSleepInfoPrint
+ 0x1005daaa 0x18 _zPHY_eLpc_GetLpm32KCALIPara
+ 0x1005dac2 0x269 _L1_CpuPhySleepInfo
+ 0x1005dd2b 0x34 _L1L_PrintPwrCtrlInfo
+ 0x1005dd5f 0x29 _L1L_PrintModemClkCtrlInfo
+ 0x1005dd88 0x8e _zPHY_elpc_LpmCalibrationLog
+ 0x1005de16 0x50 _zPHY_elpc_GetLpmCaliIdx
+ 0x1005de66 0x7e _zPHY_elpc_LpmCalibrationProc
+ 0x1005dee4 0x11 _zPHY_elpc_LpmCalibrationParaUpdate
+ 0x1005def5 0x40 _zPHY_eLpc_RecordTpuMrtrForCaliTest
+ 0x1005df35 0xf _zPHY_elpc_IsRfStateIdle
+ 0x1005df44 0x1 _zPHY_elpc_RficSccSleepCtrl
+ 0x1005df45 0x63 _zPHY_eLpc_Lpm32KCALIInfor
+ 0x1005dfa8 0xf1 _zPHY_eLpc_PintCpuAxiFreq
+ 0x1005e099 0x17 _zPHY_eLpc_PrintIcpResult
+ 0x1005e0b0 0x19b _zPHY_eLpc_ChipCfgInfor
+ 0x1005e24b 0x8e _zPHY_eLpc_TimeSysInfo
+ 0x1005e2d9 0x4b4 _zPHY_elpc_CaliTempCompensate
+ 0x1005e78d 0xb _L1L_eLpc_AsynMsgProc
+ 0x1005e798 0x2c1 _L1L_elpc_WakeupMsgFlow
+ 0x1005ea59 0x23a _L1L_elpc_LpmWakeupFlow
+ 0x1005ec93 0x94 _L1L_LPInit
+ 0x1005ed27 0x2 _zPHY_elpc_Init
+ 0x1005ed29 0x6d _L1L_LpcCfgSocWkupInt
+ 0x1005ed96 0x14 _L1L_LpcDisSocWkupInt
+ 0x1005edaa 0x15 _L1L_WakeupIsr
+ 0x1005edbf 0x2b4 _L1L_ModemLpcSleep
+ 0x1005f073 0x9e _L1L_ModemLpcWakeup
+ .text 0x1005f111 0xfa8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x1005f113 0x3d _zPHY_erfc_DrvCheckNVBandWithRFBand
+ 0x1005f150 0x3b _zPHY_erfc_FindNVBandWithRFBand
+ 0x1005f18b 0x3e _zPHY_erfc_DrvCheckTpCompNV
+ 0x1005f1c9 0x2a _zPHY_erfc_SupBinarySearchNv
+ 0x1005f1f3 0xad _zPHY_erfc_SupSampleRateSet
+ 0x1005f2a0 0x82 _zPHY_erfc_SupNVBandIndexInit
+ 0x1005f322 0x1b _zPHY_erfc_SupGlobalVarInit
+ 0x1005f33d 0x18e _zPHY_erfc_InitTableByDma
+ 0x1005f4cb 0x1 _zPHY_erfc_SupIntTxTable
+ 0x1005f4cc 0x129 _zPHY_erfc_SupIntRFC
+ 0x1005f5f5 0x1e _zPHY_erfc_SupBinarySearchAdc
+ 0x1005f613 0x39 _zPHY_erfc_SupCalcDiffpower
+ 0x1005f64c 0x38 _zPHY_erfc_SupCalcDiffpower7510ACP
+ 0x1005f684 0x36 _zPHY_erfc_SupEventRxoffsetEn
+ 0x1005f6ba 0x1c _zPHY_erfc_SupTxSymbSend
+ 0x1005f6d6 0xa _zPHY_erfc_SupTxFclkCtrl
+ 0x1005f6e0 0x2e _zPHY_erfc_SupDFEFrontEsti
+ 0x1005f70e 0x11 _zPHY_erfc_SupDFEpath0RxControl
+ 0x1005f71f 0x1a _zPHY_erfc_SupDFERxDAGC0estiControl
+ 0x1005f739 0x27 _zPHY_erfc_SupDFERxRemovCpControl
+ 0x1005f760 0x11 _zPHY_erfc_SupDFEpath1Meas0Control
+ 0x1005f771 0x1f5 _zPHY_erfc_SupDFEMeas0RemovCpControl
+ 0x1005f966 0x66 _zPHY_erfc_SupDFEMeas0eICICControl
+ 0x1005f9cc 0x21 _zPHY_erfc_SupDFEpath2CellSearchControl
+ 0x1005f9ed 0x2b _zPHY_erfc_SupDFECellSearchDAGC2estiControl
+ 0x1005fa18 0x1 _zPHY_erfc_SupDFEMeas0DAGC1estiControl
+ 0x1005fa19 0x3a _zPHY_erfc_SupDFESubframeStart
+ 0x1005fa53 0x14 _zPHY_erfc_SupDFEFrameStart
+ 0x1005fa67 0x1 _zPHY_erfc_SupSetTDDFDD
+ 0x1005fa68 0x24 _zPHY_erfc_SupEnterLowPower
+ 0x1005fa8c 0x296 _zPHY_erfc_SupLeaveLowPower
+ 0x1005fd22 0x1 _zPHY_erfc_SupRfGPIOOpen
+ 0x1005fd23 0x41 _zPHY_erfc_SupRfRxOpen
+ 0x1005fd64 0x1 _zPHY_erfc_SupRfGPIOClose
+ 0x1005fd65 0x1 _zPHY_erfc_SupRfRxClose
+ 0x1005fd66 0x23 _zPHY_erfc_SupRfEnterLightSleep
+ 0x1005fd89 0x26 _zPHY_erfc_SupRfEnterDeepSleep
+ 0x1005fdaf 0x22 _zPHY_erfc_SupRfLeaveLightSleep
+ 0x1005fdd1 0x23 _zPHY_erfc_SupRfLeaveDeepSleep
+ 0x1005fdf4 0x2c _zPHY_erfc_SupRfLeaveSleep
+ 0x1005fe20 0x24 _zPHY_erfc_SupRfWakeUpRxOpen
+ 0x1005fe44 0x1e _zPHY_erfc_SupRfRxCloseSleep
+ 0x1005fe62 0x4d _zPHY_erfc_SupGetUserNVBandIndex
+ 0x1005feaf 0x3a _zPHY_erfc_SupGetCaliNVBandIndex
+ 0x1005fee9 0x6f _zPHY_erfc_SupNotchEn
+ 0x1005ff58 0xa _zPHY_erfc_SupWriteTempCompDacToIram
+ 0x1005ff62 0x157 _zPHY_erfc_SupGetRBESF
+ .text 0x100600b9 0x5f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x100600b9 0x12 _zPHY_ecsrm_ProReset
+ 0x100600cb 0x17 _zPHY_ecsrm_InitialGlobalVar
+ 0x100600e2 0x55 _zPHY_ecsrm_IsBlackCell
+ 0x10060137 0x88 _zPHY_ecsrm_BuffGetEveryRfcOpenTime
+ 0x100601bf 0xe3 _zPHY_ecsrm_GetRfcOpenTime
+ 0x100602a2 0xba _zPHY_ecsrm_GetRfcOpenTimeFddIdle
+ 0x1006035c 0x8 _zPHY_ecsrm_SetDdMode
+ 0x10060364 0x94 _zPHY_ecsrm_CfgRfcData
+ 0x100603f8 0x2 _zPHY_ecsrm_OnReset
+ 0x100603fa 0x4a _zPHY_ecsrm_OnSearchMeasStart
+ 0x10060444 0x12 _zPHY_ecsrm_OnSearchMeasReset
+ 0x10060456 0x21 _zEcsm_PreEvent
+ 0x10060477 0x38 _L1e_csrm_SfProc
+ 0x100604af 0x1fe _zPHY_ecsrm_WriteRfcEventTabNew
+ .text 0x100606ad 0x1edb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x100606ad 0x3d _zPHY_ecsrm_AveMeasResult
+ 0x100606ea 0x18 _zPHY_ecsrm_AveValLog
+ 0x10060702 0x8 _zPHY_ecsrm_CalSint16ResVal
+ 0x1006070a 0x2 _zPHY_ecsrm_PointToInt
+ 0x1006070c 0x21 _zPHY_ecsrm_CalApproValLog
+ 0x1006072d 0x8 _zPHY_ecsrm_ClearMeasResult
+ 0x10060735 0xd _zPHY_ecsrm_InitialMeasCommPara
+ 0x10060742 0x9 _zPHY_ecsrm_RegistPeriodSfInt
+ 0x1006074b 0xc _L1e_csrm_ClearCurCellInfo
+ 0x10060757 0xfa _zPHY_ecsrm_JudgeMeasState
+ 0x10060851 0x1f _zPHY_escrm_GetFbRelatn
+ 0x10060870 0x2b _zPHY_ecsrm_GetRsNumLogIndex
+ 0x1006089b 0x34 _zPHY_ecsrm_CalModVal
+ 0x100608cf 0x59 _zPHY_ecsrm_Q8log2
+ 0x10060928 0x3c _zPHY_ecsrm_Logarithm
+ 0x10060964 0x3b _zPHY_ecsrm_GetAntAgcCsrm
+ 0x1006099f 0x17 _zPHY_ecsrm_CfgDfeBandCsr
+ 0x100609b6 0x3b _zPHY_ecsrm_GetAntAgcRx
+ 0x100609f1 0x119 _zPHY_ecsrm_ReadRsrpNvInfo
+ 0x10060b0a 0x19 _zPHY_ecsrm_CalLog
+ 0x10060b23 0x25 _zPHY_ecsrm_ReadCaliNvPoint
+ 0x10060b48 0x26 _zPHY_ecsrm_WriteMeasResult
+ 0x10060b6e 0xa4 _zPHY_ecsrm_CalRsrpOffset
+ 0x10060c12 0x1ee _zPHY_ecsrm_CalRsrpRssi
+ 0x10060e00 0xe6 _zPHY_ecsrm_CalRsrpForRx
+ 0x10060ee6 0x18 _zPHY_ecsrm_ReadRealOffet
+ 0x10060efe 0xf1 _zPHY_ecsrm_CalSinr
+ 0x10060fef 0x9 _zPHY_ecrsm_DelAllTpuInt
+ 0x10060ff8 0x2e _zPHY_ecsrm_Buffer_TDDMode
+ 0x10061026 0x36 _zPHY_ecsrm_Idle_Buffer_FddMode
+ 0x1006105c 0x29 _zPHY_ecsrm_Idle_FddMode
+ 0x10061085 0x2c _zPHY_ecsrm_Idle_FddScheInAny
+ 0x100610b1 0x31 _zPHY_ecsrm_Idle_FddReadInAny
+ 0x100610e2 0x26 _zPHY_ecsrm_ClearMeasCellInfo
+ 0x10061108 0x40 _zPHY_ecsrm_ClearBuffInfo
+ 0x10061148 0x34 _zPHY_ecsrm_half_FrameBoundrySub
+ 0x1006117c 0x25 _zPHY_ecsrm_BuffSlaveHFS
+ 0x100611a1 0x44 _zPHY_ecsrm_BuffSlaveMaxBdySub
+ 0x100611e5 0x13 _zPHY_ecsrm_GetCurrCellId
+ 0x100611f8 0x97 _zPHY_ecsrm_UpdateResIntoDbNew
+ 0x1006128f 0x2e _zPHY_ecsrm_ClearMeasResultNew
+ 0x100612bd 0x5d _zPHY_ecsrm_UpdateMeasResultNew
+ 0x1006131a 0x2a _zPHY_ecsrm_Half_Frame_Bdy_Sub
+ 0x10061344 0x25 _zPHY_ecsrm_GetBuffSlaveOpenSfNum
+ 0x10061369 0x3d _zPHY_ecsrm_GetBuffMeasSfNum
+ 0x100613a6 0x2c _zPHY_ecsrm_GetMeasSfNum
+ 0x100613d2 0x10a _zPHY_ecsrm_CalRsrpNew
+ 0x100614dc 0x29 _zPHY_ecsrm_GetNextSchTime
+ 0x10061505 0x1c _zPHY_ecsrm_ClearMeasSch
+ 0x10061521 0x6a _zPHY_ecsrm_DiscardMeas
+ 0x1006158b 0x81 _GetMeasInfo
+ 0x1006160c 0x50 _SetMeasAgeInfo
+ 0x1006165c 0xbf _zPHY_ecsrm_MeasGetCell
+ 0x1006171b 0x10e _zPHY_ecsrm_GetCsrmRegParaNew
+ 0x10061829 0x69 _zPHY_ecsrm_GetDFEBuffFbRelatn
+ 0x10061892 0xc8 _zPHY_ecsrm_GetDFEBuffRegPara
+ 0x1006195a 0xb7 _zPHY_ecsrm_GetDFECellMeasPara_FDD
+ 0x10061a11 0xf7 _zPHY_ecsrm_GetDFECellMeasPara_TDD
+ 0x10061b08 0x97 _zPHY_ecsrm_HandleCsrHWNormalNew
+ 0x10061b9f 0x12 _zPHY_ecsrm_Need_Wait_Cnditon
+ 0x10061bb1 0x9d _zPHY_ecsrm_Wait_MeasPeriodProc
+ 0x10061c4e 0x9a _zPHY_ecsrm_HandleMeasResultNormalNew
+ 0x10061ce8 0x123 _zPHY_ecsrm_MeasSeekToWorkTime
+ 0x10061e0b 0xb _zPHY_ecsrm_OnMeasStart
+ 0x10061e16 0x4a _zPHY_ecsrm_MulmGapCheck
+ 0x10061e60 0x162 _zPHY_ecsrm_MeasConfigHw
+ 0x10061fc2 0xc0 _zPHY_ecsrm_MeasReadResult
+ 0x10062082 0x23 _zPHY_ecsrm_BufferScene
+ 0x100620a5 0x32 _zPHY_ecsrm_CsrFingerSort
+ 0x100620d7 0x4 _zPHY_ecsrc_RemoveMrtrFrame
+ 0x100620db 0x58 _zPHY_ecsrm_half_FrameBoundryCenter
+ 0x10062133 0x4e _zPHY_ecsrm_GetBdyMeasCell
+ 0x10062181 0x215 _zPHY_ecsrm_GetMeasmodeAndCell
+ 0x10062396 0x10 _zPHY_ecsrm_GetMeasCellEarfcn
+ 0x100623a6 0xd3 _eL1_CalCellCfgCont
+ 0x10062479 0x2c _zPHY_ecsrm_GetSF0SF5
+ 0x100624a5 0x2d _zPHY_ecsrm_BeforeBufferMeas
+ 0x100624d2 0x95 _zPHY_ecsrm_MeasNextCell
+ 0x10062567 0x7 _zPHY_ecsrm_SetCaIndex
+ 0x1006256e 0x10 _zPHY_ecsrm_MeasNeedPrimary
+ 0x1006257e 0xa _l1e_csrm_GetMeasFalg
+ .text 0x10062588 0x31e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x10062588 0x1c1 _zPHY_UL_CSI_CombThreadEntry
+ 0x10062749 0x15d _zPHY_DLA_ULSL_CombThreadEntry
+ .text 0x100628a6 0x1861 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x100628a6 0x27 _L1e_DevRxFssSetModIdx
+ 0x100628cd 0xcd _zPHY_eMBMS_CirSearchWinPos_Calc
+ 0x1006299a 0x27 _L1e_DevRxDoubleAntCheckOnlyOneValid
+ 0x100629c1 0x3d _L1e_DevCirPreSyncAcc
+ 0x100629fe 0x5e _L1e_DevCirPreSyncProtect
+ 0x10062a5c 0x43 _zPHY_erxp_CirProc
+ 0x10062a9f 0x25 _zPHY_erxp_CirAdjBorderOfSubframe
+ 0x10062ac4 0x9 _zPHY_eCir_PccPdsch_DmaCallback
+ 0x10062acd 0x9 _zPHY_eCir_SccPdsch_DmaCallback
+ 0x10062ad6 0x9 _zPHY_eCir_PccEicic_DmaCallback
+ 0x10062adf 0x8 _L1e_DevRxSetMbsfnCirIntInt
+ 0x10062ae7 0x1a _L1e_DevRxMbmsCirIntProc
+ 0x10062b01 0x44 _L1e_DevRxFssMainAntFlagSet
+ 0x10062b45 0xd _L1e_DevRxFssMainAntFlagGet
+ 0x10062b52 0xe _L1e_DevRxRefSenDecodeCnt
+ 0x10062b60 0xd _L1e_DevRxRefSenDecodeCntGet
+ 0x10062b6d 0xd _L1e_DevRxRefSenDecodeCntClr
+ 0x10062b7a 0xe _L1e_DevRxRefSenCnt
+ 0x10062b88 0xd _L1e_DevRxRefSenCntGet
+ 0x10062b95 0xd _L1e_DevRxRefSenCntClr
+ 0x10062ba2 0xe _L1e_DevRxRefSenIndCfg
+ 0x10062bb0 0xd _L1e_DevRxRefSenIndGet
+ 0x10062bbd 0x16 _L1e_devRxMrsFIUpdateIndSet
+ 0x10062bd3 0x16 _L1e_devRxMrsBetaUpdateIndSet
+ 0x10062be9 0x18 _L1e_devRxMrsFIUpdateIndGet
+ 0x10062c01 0x18 _L1e_devRxMrsBetaUpdateIndGet
+ 0x10062c19 0x23 _L1e_devRxMrsFIDataAddrGet
+ 0x10062c3c 0x19 _L1e_devRxMrsBetaGet
+ 0x10062c55 0x93e _zPHY_eMBMS_CirInitFftSeq
+ 0x10063593 0xa8 _zPHY_ecir_SW_DynFiRegUdate
+ 0x1006363b 0x135 _zPhy_eMBMS_cir_nomarlize_fir_coeff
+ 0x10063770 0x16a _zPHY_ecir_Apply_Triangle_Window
+ 0x100638da 0xcb _zPhy_ecir_CalcBeta_R01
+ 0x100639a5 0x95 _zPHY_erxp_BchNormalCirCtrl
+ 0x10063a3a 0x23 _zPHY_erxp_CirCfgForBch
+ 0x10063a5d 0x577 _L1e_DevRxCirCtrlCfg
+ 0x10063fd4 0x63 _L1e_DevRxSetRxOffsetAdjTiMode
+ 0x10064037 0x7 _zPHY_ecir_CellChangeSet
+ 0x1006403e 0xc9 _zPHY_ecir_CellChangeGet
+ *fill* 0x10064107 0x80000001 00
+ .text 0x10064108 0x203 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x10064108 0xc4 _zPHY_ecir_Fft256
+ 0x100641cc 0xb _zPhy_ecir_continuous_add
+ 0x100641d7 0x17 _zPhy_ecir_search_max_value
+ 0x100641ee 0xa _zPhy_ecir_acquire_fir_coeff
+ 0x100641f8 0x35 _zPhy_eMBMS_cir_midify_nosieEff
+ 0x1006422d 0x2d _zPhy_ecir_generet_fir_coeff
+ 0x1006425a 0x37 _zPhy_ecir_midify_nosieEff
+ 0x10064291 0x7a _Asm_CIR_FIRCoeffNorm
+ .text 0x1006430b 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x1006430b 0x9 _L1e_DevRxSetRsrpIntInd
+ 0x10064314 0x9 _L1e_DevRxGetRsrpIntInd
+ 0x1006431d 0x1f _L1e_DevRxSetServingCellInd
+ 0x1006433c 0x10b _zPHY_erxp_Cfo_Isr
+ 0x10064447 0x44 _L1e_DevCFOPreSyncAcc
+ 0x1006448b 0x4e _L1e_DevCfoFilterCoeffAdapt
+ 0x100644d9 0x1e _L1e_DevCfoCfgTempRead
+ 0x100644f7 0x59 _L1e_DevSetCfoCoeffK
+ 0x10064550 0xfb _L1e_DevGetCfoCoeffK
+ 0x1006464b 0xa _L1e_DevRxRsrpFilterFlagInit
+ 0x10064655 0x3f _L1e_DevRxGetRsrpFilterCoeff
+ 0x10064694 0x116 _zPHY_erxp_CalRsrpFilter
+ 0x100647aa 0x92 _zPHY_erxp_RsrpFilter
+ 0x1006483c 0xd _L1e_DevRxGetFastCfoConvergenceCnt
+ 0x10064849 0xe _L1e_DevRxSetFastCfoConvergenceCnt
+ 0x10064857 0xe _L1e_DevRxDecreaseFastCfoCnt
+ .text 0x10064865 0x200d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x10064865 0x249 _zPHY_edfe_SupInitDFE
+ 0x10064aae 0x24 _zPHY_edfe_WriteSnrTh
+ 0x10064ad2 0x71 _zPHY_edfe_DCOffsetCal
+ 0x10064b43 0xea _zPHY_edfe_SupNormalHandleDCOffset
+ 0x10064c2d 0xa9 _zPHY_edfe_IQImbaCal
+ 0x10064cd6 0x77 _zPHY_edfe_SupHandleIQImba
+ 0x10064d4d 0x51 _zPHY_edfe_NormalNotSyncAgcIntHandle
+ 0x10064d9e 0x8 _zPHY_edfe_SupInt0Handle
+ 0x10064da6 0x14 _zPHY_edfe_SupInt1Handle
+ 0x10064dba 0x15 _zPHY_edfe_SupInt2Handle
+ 0x10064dcf 0x39 _zPHY_edfe_ProDfeInt
+ 0x10064e08 0x27 _zPHY_edfe_ConfigRXBandwidth
+ 0x10064e2f 0x22 _zPHY_edfe_ConfigCSRMBandwidth
+ 0x10064e51 0x7d _zPHY_edfe_CompesateCFO
+ 0x10064ece 0x72 _zPHY_edfe_CalMeasTotalAGCGain
+ 0x10064f40 0x4c _zPHY_edfe_TotalAGCCsrm
+ 0x10064f8c 0x4c _zPHY_edfe_TotalAGCRx
+ 0x10064fd8 0x2e _zPHY_edfe_SupResetDfeForRelease
+ 0x10065006 0xe _zPHY_edfe_RegsTpuIntForDfe
+ 0x10065014 0x91 _zPHY_edfe_RegsTpuIntForDfeCtrl
+ 0x100650a5 0x1ab _zPHY_edfe_SupDfeIntCheckCtrl
+ 0x10065250 0xb4 _zPHY_edfe_PlmnSaveServCellAgcAndDagc
+ 0x10065304 0x26 _zPHY_edfe_PlmnResumeServCellAgcAndDagc
+ 0x1006532a 0x76 _zPHY_edfe_PlmnBackUpAgcPara
+ 0x100653a0 0x20 _zPHY_edfe_PlmnResumeAgcAndAfc
+ 0x100653c0 0xa _zPHY_edfe_ClearPlmnAgcPara
+ 0x100653ca 0x1ed _zPHY_edfe_SupNotSyncAGCInitCtrl
+ 0x100655b7 0x17e _zPHY_edfe_TMTPrintForFreqScan
+ 0x10065735 0x8d _zPHY_edfe_ConfigAgcWorkState
+ 0x100657c2 0x1b5 _zPHY_edfe_ConfigAgcCalcPara
+ 0x10065977 0xf6 _zPHY_edfe_SupInitAgcDagcGainDB
+ 0x10065a6d 0x5c _zPHY_edfe_SupHandleRxDagcInt
+ 0x10065ac9 0x1b0 _zPHY_edfe_SupHandleAgcInt
+ 0x10065c79 0x43 _zPHY_edfe_StateChangeSetAgcGain
+ 0x10065cbc 0x12a _zPHY_edfe_GetTotalAGCGainOpt
+ 0x10065de6 0x67 _zPHY_edfe_SupCsrcDagcLoseDataCtrl
+ 0x10065e4d 0xbe _zPHY_edfe_PhySlaveDfeIntCtrlOpt
+ 0x10065f0b 0x2c _zPHY_edfe_TotalSubFramePwr
+ 0x10065f37 0x21 _zPHY_edfe_CSRSetFSNewState
+ 0x10065f58 0x48 _zPHY_edfe_CSRSetAGCGain
+ 0x10065fa0 0xfa _zPHY_edfe_SupFSNewSetRF
+ 0x1006609a 0x2d _zPHY_edfe_SupNotSyncAgcIntHandle
+ 0x100660c7 0x72 _zPHY_edfe_FSDCOffsetCal
+ 0x10066139 0x17 _zPHY_edfe_FSDCOffsetClear
+ 0x10066150 0x86 _zPHY_edfe_SupFSHandleDCOffset
+ 0x100661d6 0x12 _zPHY_edfe_SupHandleDCOffset
+ 0x100661e8 0xa9 _zPHY_edfe_SupSingAntNVControl
+ 0x10066291 0x9 _zPHY_edfe_ConfigSingAnt
+ 0x1006629a 0x86 _zPHY_edfe_SupCalAGCGainBalance
+ 0x10066320 0xfa _L1l_DevDfeNotchDbInit
+ 0x1006641a 0x3 _L1l_DevRfcNotchDbReset
+ 0x1006641d 0x14 _L1l_DevDfeNotchAgcGainSave
+ 0x10066431 0x4c _L11_DevDfeNotchBwAndSampRateGet
+ 0x1006647d 0x186 _L1l_DevDfeNotchStartJudge
+ 0x10066603 0xd3 _L1l_DevDfeNotchEvtGet
+ 0x100666d6 0xb7 _L1l_DevDfeNotchRegSet
+ 0x1006678d 0xc7 _L1l_DevDfeNotchProc
+ 0x10066854 0xb _L1l_DevRfcSemiStaticAgcConvCheck
+ 0x1006685f 0x13 _L1l_DevRfcAgcValGet
+ .text 0x10066872 0x1f9a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x10066872 0xfc _zPHY_eula_Entry
+ 0x1006696e 0xf9 _zPHY_eula_TpuInt1MsgPro
+ 0x10066a67 0x9e _zPHY_eula_TpuInt2MsgPro
+ 0x10066b05 0x58e _zPHY_eula_TPU_INT1_process
+ 0x10067093 0x360 _zPHY_eula_TPU_INT2_process
+ 0x100673f3 0x98 _zPHY_eula_ResetDB
+ 0x1006748b 0x17 _zPHY_eula_ResetReqPro
+ 0x100674a2 0x2d4 _zPHY_eula_HandoverReqPro
+ 0x10067776 0x160 _zPHY_eula_Release
+ 0x100678d6 0xd7 _zPHY_eula_MACReset
+ 0x100679ad 0x12d _zPHY_eula_ComCfgReqPro
+ 0x10067ada 0x16d _zPHY_eula_CommRelatedParasCalc
+ 0x10067c47 0x156 _zPHY_eula_DediCfgReqPro
+ 0x10067d9d 0x51 _zPHY_eula_GetScellInfo
+ 0x10067dee 0xca _zPHY_eula_DediRelatedParasCalc
+ 0x10067eb8 0x169 _zPHY_eula_PSGenAllWithCellID
+ 0x10068021 0x5c _zPHY_eula_FuncHopCalculation
+ 0x1006807d 0x5c _zPHY_eula_FuncHopCalculation_Scell
+ 0x100680d9 0x35 _zPHY_eula_UlBandSampleCoeffCfg
+ 0x1006810e 0x46 _zPHY_eula_SetSampleAndFFT
+ 0x10068154 0x15 _zPHY_eula_GetSysTimeInfo
+ 0x10068169 0x13 _zPHY_eula_GetChannelType
+ 0x1006817c 0x29 _zPHY_eula_GetHarqProcessId
+ 0x100681a5 0xe _zPHY_eula_CheckPuschInGap
+ 0x100681b3 0x52 _zPHY_eula_HarqNewTransNoData
+ 0x10068205 0xb0 _zPHY_eula_UL_Conflict_GAP
+ 0x100682b5 0x6b _zPHY_eula_HarqSendDataCopy
+ 0x10068320 0x18 _zPHY_eula_TXInt_Pulse_Isr
+ 0x10068338 0x13 _zPHY_eula_Isr
+ 0x1006834b 0x91 _zPHY_eula_lpcHwRestoreBackupCtrl
+ 0x100683dc 0x2e6 _zPHY_eula_AMTCalcPara
+ 0x100686c2 0x106 _zPHY_amt_Lte_Tx_Create_CommonMsg
+ 0x100687c8 0x44 _zPHY_PrintLocalMrtr
+ .text 0x1006880c 0x121f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x1006880c 0x1a7 _zPHY_edla_Entry
+ 0x100689b3 0x3e _L1e_Dla_UpBchNormalPara
+ 0x100689f1 0x1f7 _zPHY_edla_CdtrCfgProc
+ 0x10068be8 0x1a2 _zPHY_edla_GetSiRnti
+ 0x10068d8a 0x6a _zPHY_edla_QueryDb
+ 0x10068df4 0x1e _zPHY_edla_ProCalYk
+ 0x10068e12 0x1a9 _zPHY_edla_GetRntiInfo
+ 0x10068fbb 0xa8 _zPHY_edla_GetCellInfo
+ 0x10069063 0x20 _zPHY_edla_GetVcInfo
+ 0x10069083 0x1a _zPHY_edla_ErrorTmGuard
+ 0x1006909d 0x2c _zPHY_edla_SetDefaultTM
+ 0x100690c9 0x2e _zPHY_edla_GetTimingInfo
+ 0x100690f7 0x31 _L1e_DevDlaGetPhichMi
+ 0x10069128 0x1b _zPHY_edla_CommRegParaProc
+ 0x10069143 0xbe _zPHY_edla_CdtrCfgCaApply
+ 0x10069201 0x24 _zPHY_edla_CdtrCfgApply
+ 0x10069225 0xf7 _zPHY_edla_InfoCaPrepare
+ 0x1006931c 0x9 _zPHY_edla_InfoPrepare
+ 0x10069325 0x4a _zPHY_edla_IndInfoCaSet
+ 0x1006936f 0x9 _zPHY_edla_IndInfoSet
+ 0x10069378 0x46 _zPHY_edla_ResetDcb
+ 0x100693be 0x3e _zPHY_edla_Init
+ 0x100693fc 0x1e _zPHY_edla_HwInit
+ 0x1006941a 0x1c _zPHY_edla_CacheCtrlReset
+ 0x10069436 0x3b _zPHY_edla_SaveWorkCachePara
+ 0x10069471 0x1a _zPHY_edla_UpdateRBGSize
+ 0x1006948b 0x3d _zPHY_edla_UpdateNGap1
+ 0x100694c8 0x15 _zPHY_edla_UpdateNrbStep
+ 0x100694dd 0x8 _zPHY_edla_ResetCommonInfo
+ 0x100694e5 0xfc _zPHY_edla_UpdateCommonInfo
+ 0x100695e1 0x55 _zPHY_edla_ProCommReqMsg
+ 0x10069636 0x60 _zPHY_edla_ProDediReqMsg
+ 0x10069696 0x56 _zPHY_edla_ProHoReqMsg
+ 0x100696ec 0x24 _zPHY_edla_HoReqEx
+ 0x10069710 0xd _zPHY_edla_LteAmtUpdateEarfcnInfo
+ 0x1006971d 0xb _L1e_DevRxInitLpConvergeCb
+ 0x10069728 0xf _L1e_DevRxSetLpConvergeInd
+ 0x10069737 0x10 _L1e_DevRxGetLpConvergeInd
+ 0x10069747 0x10 _L1e_DevRxSetWorkTimer
+ 0x10069757 0x10 _L1e_DevRxGetWorkTimer
+ 0x10069767 0x13 _L1e_DevRxIncWorkTimer
+ 0x1006977a 0x27 _zPHY_edla_DebugPrint
+ 0x100697a1 0x43 _zPHY_edla_ProDbgMsgRecvCommMsg
+ 0x100697e4 0x43 _zPHY_edla_ProDbgMsgRecvHOMsg
+ 0x10069827 0x43 _zPHY_edla_ProDbgMsgRstRelMacRstMsg
+ 0x1006986a 0x52 _zPHY_edla_ProDbgStateSwitchPrint
+ 0x100698bc 0x3a _zPHY_edla_ProDbgMsgFuncRetErr
+ 0x100698f6 0x77 _zPHY_edla_ProDlCtrlChStatInfoMonitor
+ 0x1006996d 0x25 _zPHY_edla_ProDlCtrlChDecodeMonitor
+ 0x10069992 0x1 _zPHY_edla_ProDlCtrlChConfigMonitor
+ 0x10069993 0x4e _zPHY_edla_PlmnReflashDlaConfig
+ 0x100699e1 0x1a _L1e_DevRxLpcHwRecover
+ 0x100699fb 0x17 _L1e_DevDlaSetDlWorkIndBmp
+ 0x10069a12 0xc _L1e_DevDlaGetDlWorkIndBmp
+ 0x10069a1e 0xd _L1e_DevDlaGetDlBandWidth
+ .text 0x10069a2b 0x2ed3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x10069a2b 0x1cd _zPHY_eula_ProInitial
+ 0x10069bf8 0x68 _zPHY_eula_RegistLutrSymb
+ 0x10069c60 0x130 _zPHY_eula_UlDataSendCtrlInfoProcess
+ 0x10069d90 0x26a _zPHY_eula_LtxParas_ACKMultiplexing
+ 0x10069ffa 0xec _zPHY_eula_LutrLtxParas_RIMultiplexing
+ 0x1006a0e6 0xb _zPHY_eula_CalcInterMatrixColNumber
+ 0x1006a0f1 0x93 _zPHY_eula_CalcRMOutputParas
+ 0x1006a184 0x8 _zPHY_eula_CalcRMOutputParasForPuschWithoutData
+ 0x1006a18c 0xd0 _zPHY_eula_SchdPhichRecInSad
+ 0x1006a25c 0x65 _zPHY_eula_DeterMineHWChanType
+ 0x1006a2c1 0x194 _zPHY_eula_LTXParasCalc
+ 0x1006a455 0x2c _zPHY_eula_LtxParas_wNRsZcDmrs
+ 0x1006a481 0x21 _zPHY_eula_LargestPrimeNumber
+ 0x1006a4a2 0x28 _zPHY_eula_LtxParas_DmrsOCC
+ 0x1006a4ca 0x71 _zPHY_eula_LtxParas_adwQDivNRsZcDmrs
+ 0x1006a53b 0x28 _zPHY_eula_LtxParas_awNcscell
+ 0x1006a563 0x16 _zPHY_eula_LtxParas_acUPucch
+ 0x1006a579 0x113 _zPHY_eula_LtxParas_PucchFormat1Spec
+ 0x1006a68c 0x232 _zPHY_eula_LtxParas_PucchFormat3Spec
+ 0x1006a8be 0x13 _zPHY_eula_LtxParas_dwX2Cinit
+ 0x1006a8d1 0x3e _zPHY_eula_LtxParas_awNcs2
+ 0x1006a90f 0x9e _zPHY_eula_LtxParas_ResMappingPucch
+ 0x1006a9ad 0x14 _zPHY_eula_711712ClosePsmStub
+ 0x1006a9c1 0x46c _zPHY_eula_RfcConfigure
+ 0x1006ae2d 0xe7 _zPHY_eula_LutrRegConfigure
+ 0x1006af14 0x3da _zPHY_eula_LtxConfigure
+ 0x1006b2ee 0x63 _zPHY_eula_LTXTxTaConfig
+ 0x1006b351 0x50 _zPHY_eula_LTXTimingFirstFlag
+ 0x1006b3a1 0x53 _zPHY_eula_LTXTimingLastFlag
+ 0x1006b3f4 0x17 _zPHY_eula_ResetSrInfo
+ 0x1006b40b 0x100 _zPHY_eula_SetPuchFilterCoeff1
+ 0x1006b50b 0x66 _zPHY_eula_SetPrachFilterCoeff2
+ 0x1006b571 0x34 _zPHY_eula_SetPucchScale
+ 0x1006b5a5 0xf _zPHY_eula_GetCsiInfo
+ 0x1006b5b4 0x2 _zPHY_eula_FDDGetHarqAckInfo
+ 0x1006b5b6 0x25 _zPHY_euls_GetPucchHarqAckInfo
+ 0x1006b5db 0x83 _zPHY_eula_GetPucchHarqAckLen
+ 0x1006b65e 0xf7 _zPHY_eula_PucchUciProcess
+ 0x1006b755 0x2bc _zPHY_eula_TDD_PucchAckProcess
+ 0x1006ba11 0x1a _zPHY_eula_FDD_PucchAckProcess
+ 0x1006ba2b 0x70 _zPHY_eula_PucchCSI
+ 0x1006ba9b 0x271 _zPHY_eula_PucchAckParasCalc
+ 0x1006bd0c 0x34 _zPHY_eula_PucchN1pucchCalc
+ 0x1006bd40 0xaa _zPHY_eula_FDD_PucchAckParasCalc
+ 0x1006bdea 0x25 _zPHY_eula_PSGeneration
+ 0x1006be0f 0x7a _zPHY_eula_SrProcess
+ 0x1006be89 0x566 _zPHY_eula_LtxStub
+ 0x1006c3ef 0x213 _zPHY_eula_LutrStub
+ 0x1006c602 0x15a _zPHY_eula_UlTwoAntenHWChanTypeDeterm
+ 0x1006c75c 0xc _zPHY_eula_TATimerStop
+ 0x1006c768 0x25 _zPHY_eula_PucchTwoAntenActivedDetermine
+ 0x1006c78d 0x12f _zPHY_eula_NextAckParasProcess
+ 0x1006c8bc 0x3b _zPHY_eula_GetTQCfgFlg
+ 0x1006c8f7 0x7 _zPHY_eula_PucchAntennaSelect
+ .text 0x1006c8fe 0x38e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x1006c8fe 0x2d _zPHY_eintc_IntDispatchProcess_ICP
+ 0x1006c92b 0x47 _zPHY_eintc_EnableInt
+ 0x1006c972 0x50 _zPHY_eintc_ClearInt
+ 0x1006c9c2 0x1c _L1l_DrvTopIntClr
+ 0x1006c9de 0x46 _zPHY_eintc_InthInit
+ 0x1006ca24 0x1a _L1_LTE_LPM_T1_ISR
+ 0x1006ca3e 0x1 _zPHY_eintc_NullIsr
+ 0x1006ca3f 0xd _zPHY_DMA_CallBack_M
+ 0x1006ca4c 0xd _zPHY_DMA_CallBack_S
+ 0x1006ca59 0xd _zPHY_DMA_CallBack_CSILte
+ 0x1006ca66 0xd _L1e_DevCmnIntPbchIntProc
+ 0x1006ca73 0x36 _L1e_DevCmnIntCfoIntProc
+ 0x1006caa9 0x1c _L1e_DevCmnIntCrsCirIntProc
+ 0x1006cac5 0x31 _L1e_DevCmnIntCdtrIntProc
+ 0x1006caf6 0x24 _L1e_DevCmnIntDdtrIntProc
+ 0x1006cb1a 0x39 _L1e_CmnCheCqiInt
+ 0x1006cb53 0xe _L1e_CmnTpuSubFrameInt
+ 0x1006cb61 0x7 _L1e_CmnTpuAdjInt
+ 0x1006cb68 0xb _L1e_CmnTxPulseInt
+ 0x1006cb73 0x2d _L1e_CmnPdcchIntPcc
+ 0x1006cba0 0x3d _L1e_CmnDfeInt
+ 0x1006cbdd 0x2f _L1e_CmnDfeDcInt
+ 0x1006cc0c 0x2c _L1e_CmnPdcchPccInt
+ 0x1006cc38 0xd _L1e_CmnCsrDebugInt
+ 0x1006cc45 0xd _L1e_CmnPbchInt
+ 0x1006cc52 0xf _L1e_CmnPdschPccCirInt
+ 0x1006cc61 0x1e _L1e_CmnDdtrPccInt
+ 0x1006cc7f 0xd _L1e_CmnPbchIcInt
+ .text 0x1006cc8c 0x1419 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ 0x1006cc8c 0x1e9 _zPHY_eulpc_GetConfigParas
+ 0x1006ce75 0x46 _zPHY_eulpc_InitialProc
+ 0x1006cebb 0x3a _zPHY_eulpc_DeltaTcEUtraBandNoDeterm
+ 0x1006cef5 0x278 _zPHY_eulpc_SingleCarrierMprDeterm
+ 0x1006d16d 0x4e9 _zPHY_eulpc_NoCaAMprDeterm
+ 0x1006d656 0x82 _zPHY_eulpc_PcmaxCalc
+ 0x1006d6d8 0x132 _zPHY_eulpc_PucchTpcProc
+ 0x1006d80a 0x104 _zPHY_eulpc_PuschTpcProc
+ 0x1006d90e 0x44 _zPHY_eulpc_RarTpcProc
+ 0x1006d952 0x6d _zPHY_eulpc_PowCtrlConfigParasCalc
+ 0x1006d9bf 0x96 _zPHY_eulpc_TpcCommandsProc
+ 0x1006da55 0x110 _zPHY_eulpc_CloseLoopPowCtrlProc
+ 0x1006db65 0xb2 _zPHY_eulpc_Type1PhrCalc
+ 0x1006dc17 0x27 _zPHY_eulpc_PhrCalcProc
+ 0x1006dc3e 0xb7 _zPHY_eulpc_Sqrt
+ 0x1006dcf5 0x10d _zPHY_eulpc_PowScaleValCalc
+ 0x1006de02 0x37 _zPHY_eulpc_LinearValToPowDB
+ 0x1006de39 0x142 _zPHY_eulpc_UlaRelativeProc
+ 0x1006df7b 0x29 _zPHY_eulpc_UlPowerStub
+ 0x1006dfa4 0x1c _zPHY_eulpc_ReSetParameters
+ 0x1006dfc0 0xba _zPHY_eulpc_TempMaxPowerBackoff
+ 0x1006e07a 0x2b _zPHY_eulpc_GetLatestPower
+ .text 0x1006e0a5 0x134 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x1006e0a5 0x9 _L1l_DevEngInitAddr
+ 0x1006e0ae 0x12 _L1l_log_track_init
+ 0x1006e0c0 0x46 _L1l_DevEngTrace
+ 0x1006e106 0xd1 _L1l_DevEngWriteDataToBuffer
+ 0x1006e1d7 0x1 _L1l_DevEngUartTransmit
+ 0x1006e1d8 0x1 _L1l_DevEngSwapHook
+ .text 0x1006e1d9 0x35a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ 0x1006e1d9 0x38 _zEasn1p_DcT_zEurrc_OctString
+ 0x1006e211 0x46 _zEasn1p_DcT_zEurrc_S_TMSI
+ 0x1006e257 0x5b _zEasn1p_DcT_zEurrc_IMSI
+ 0x1006e2b2 0x42 _zEasn1p_DcT_zEurrc_PagingUE_Identity
+ 0x1006e2f4 0x56 _zEasn1p_DcT_zEurrc_PagingRecord
+ 0x1006e34a 0x4a _zEasn1p_DcT_zEurrc_PagingRecordList
+ 0x1006e394 0x4e _zEasn1p_DcT_zEurrc_Paging_v920_IEs
+ 0x1006e3e2 0x49 _zEasn1p_DcT_zEurrc_Paging_v890_IEs
+ 0x1006e42b 0x8f _zEasn1p_DcT_zEurrc_Paging
+ 0x1006e4ba 0x36 _zEasn1p_DcT_zEurrc_PCCH_MessageType_c1
+ 0x1006e4f0 0x3a _zEasn1p_DcT_zEurrc_PCCH_MessageType
+ 0x1006e52a 0x9 _zEasn1p_DcT_zEurrc_PCCH_Message
+ .text 0x1006e533 0xe7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ 0x1006e533 0x27 _L1e_DevDlaCalcTotRegNum
+ 0x1006e55a 0x75 _L1e_DevDlaCalcSearchSpace
+ 0x1006e5cf 0xdd _L1e_DevDlaProcPdcchSearchSpace
+ 0x1006e6ac 0x11c _zPHY_edla_PdcchBldRntiEnRegProc
+ 0x1006e7c8 0x6f _zPHY_edla_PdcchBldPayLoadRegProc
+ 0x1006e837 0x82 _zPHY_edla_PdcchBlindDetectCaProc
+ 0x1006e8b9 0xd _zPHY_edla_PdcchBlindDetectProc
+ 0x1006e8c6 0x20 _zPHY_edla_GetBandWidthIdx
+ 0x1006e8e6 0x1c _zPHY_edla_GetAmbitiousBits
+ 0x1006e902 0x8c _zPHY_edla_PreDciInfo
+ 0x1006e98e 0x20d _zPHY_edla_GetDciSize
+ 0x1006eb9b 0x809 _zPHY_edla_PdcchDemappingCaProc
+ 0x1006f3a4 0xd _zPHY_edla_PdcchDemappingProc
+ .text 0x1006f3b1 0xb64 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x1006f3b1 0xa0 _zPHY_erfc_SupACP405ToRx
+ 0x1006f451 0x6f _zPHY_erfc_SupACP405ToIdle
+ 0x1006f4c0 0x7f _zPHY_erfc_SupACP405ToTx
+ 0x1006f53f 0x82 _zPHY_erfc_SupACP405ToRxTx
+ 0x1006f5c1 0x1 _zPHY_erfc_SupACP405McroWriteAGC
+ 0x1006f5c2 0x1c _zPHY_erfc_SupGetRealWorkFreq
+ 0x1006f5de 0x46 _zPHY_erfc_ATAptPointAdjust
+ 0x1006f624 0x22 _zPHY_erfc_TxPowerAdjust
+ 0x1006f646 0xb7 _zPHY_erfc_SupGetPATuRegInfo
+ 0x1006f6fd 0x87 _zPHY_erfc_ProTxTempCompensate
+ 0x1006f784 0x1d3 _zPHY_erfc_SupAPCControl
+ 0x1006f957 0x6f _zPHY_erfc_SupClosePA
+ 0x1006f9c6 0x1 _zPHY_erfc_SupAptReload
+ 0x1006f9c7 0x139 _L1l_DevRfcAfcFreqOffsetSet
+ 0x1006fb00 0xd8 _zPHY_erfc_SupAfcEventSet
+ 0x1006fbd8 0x43 _zPHY_erfc_SupFreqOffseToDacValue
+ 0x1006fc1b 0x55 _zPHY_erfc_SupDacValueToFreqOffset
+ 0x1006fc70 0x36 _zPHY_erfc_SupBandNumToVcxoBitPerHz
+ 0x1006fca6 0x55 _zPHY_erfc_SupAfcVxcoInitWord
+ 0x1006fcfb 0x44 _L1l_DevRfcAfcFreqOffsetGet
+ 0x1006fd3f 0x2e _zPHY_erfc_DCXOCordicCfg
+ 0x1006fd6d 0x35 _zPHY_erfc_DCXOAfcInit
+ 0x1006fda2 0xa _zPHY_erfc_DCXOAfcParaSet
+ 0x1006fdac 0xd7 _zPHY_erfc_DCXOAfcParaGet
+ 0x1006fe83 0x92 _zPHY_erfc_DCXOAfcCtrl
+ .text 0x1006ff15 0x45e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x1006ff15 0x20 _zPHY_edls_AdaJudgePdschTrans
+ 0x1006ff35 0x7a _zPHY_edls_AdaDecodePdcchOrder
+ 0x1006ffaf 0x89 _zPHY_edls_AdaDecodeDciF1C
+ 0x10070038 0x71 _zPHY_edls_AdaCalSiRntiNdiRv
+ 0x100700a9 0x72 _zPHY_edls_AdaCalSibDecodeParas
+ 0x1007011b 0x5e _zPHY_edls_AdaRbDmpType0Bw25Rb
+ 0x10070179 0x56 _zPHY_edls_AdaRbDmpType0Bw15Rb
+ 0x100701cf 0x46 _zPHY_edls_AdaRbDmpType0Bw6Rb
+ 0x10070215 0x26 _L1e_DevDlsGetMLSMTbs
+ 0x1007023b 0x1f _L1e_DevDlsTbsBinarySearch
+ 0x1007025a 0x25 _L1e_DevDlsCalcRmCtrlParam
+ 0x1007027f 0xe9 _zPHY_edls_AdaCalRarDecodeParas
+ 0x10070368 0xb _L1e_DevDlsCalcRmBbClk
+ .text 0x10070373 0xf0b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x10070373 0x7 _L1e_DevRxGetPrevRxStatus
+ 0x1007037a 0x7 _L1e_DevRxGetCurrRxStatus
+ 0x10070381 0xc _L1e_DevRxSwitchPrevStatus
+ 0x1007038d 0x9 _L1e_DevRxSetCurrRxStatus
+ 0x10070396 0xa6 _zPHY_edla_PageSubFrmJudge
+ 0x1007043c 0x17 _zPHY_edla_RxVshiftConfig
+ 0x10070453 0xde _L1e_DevRxSfTypeCfg
+ 0x10070531 0x18 _L1e_DevRxRsN0FactorCtrl
+ 0x10070549 0x17c _L1e_DevRxCRsN0ModeCtrl
+ 0x100706c5 0x7e _L1e_DevRxProcRsCinit
+ 0x10070743 0x5d _zPHY_edla_RxBandTxRxPortConfig
+ 0x100707a0 0x113 _zPHY_edla_RxPhichMatrixConfig
+ 0x100708b3 0xf _zPHY_edla_RxCtrlChannelMimoModeConfig
+ 0x100708c2 0x6 _zPHY_edla_RxCalIndicatorConfig
+ 0x100708c8 0x44 _zPHY_edla_RxCarrierInfoConfig
+ 0x1007090c 0x85 _zPHY_edla_CheProc
+ 0x10070991 0xb _zPHY_edla_RxRbDemappingProc
+ 0x1007099c 0x25c _zPHY_edla_RbDemappingSubProc
+ 0x10070bf8 0x20 _zPHY_edla_WriteRxRbDemapRegFile
+ 0x10070c18 0x2b _L1e_DevRxNormalN0ModCfg
+ 0x10070c43 0x25 _L1e_DevRxNCellRsNullCfg
+ 0x10070c68 0x9 _L1e_DevRxSetCirTiCtlFlg
+ 0x10070c71 0x9 _L1e_DevRxGetCirTiCtlFlg
+ 0x10070c7a 0x70 _L1e_DevRxSinrLowInd
+ 0x10070cea 0x53 _L1e_DevNSIOT_8242_Ind
+ 0x10070d3d 0x41 _L1e_DevRxSinrTiCloseInd
+ 0x10070d7e 0x7 _L1e_DevRxCrsIIRIndSet
+ 0x10070d85 0x7 _L1e_DevRxCrsIIRIndGet
+ 0x10070d8c 0x8f _L1e_DevRxCrsIIRCfg
+ 0x10070e1b 0x5d _L1e_DevRxSnrModeTiAdptProc
+ 0x10070e78 0x1c _L1e_DevRxSetTiAlgoMode
+ 0x10070e94 0x9 _L1e_DevRxGetNCellRsNullEnInd
+ 0x10070e9d 0x9 _L1e_DevRxSetNCellRsNullEnInd
+ 0x10070ea6 0x59 _L1e_DevRxTempPro
+ 0x10070eff 0x25b _zPHY_edla_RxRegCfgApply
+ 0x1007115a 0x30 _L1e_DrvRxAgcCalandConfig
+ 0x1007118a 0xf4 _L1e_DbgRxCtrlInfo
+ .text 0x1007127e 0x25e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ 0x10071280 0x217 _zPHY_eulpc_PucchPowCtrl
+ 0x10071497 0x45 _zPHY_eulpc_HNcqiNharqNsrCalc
+ .text 0x100714dc 0x287 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ 0x100714dc 0x8 _L1e_DrvDdtrResetCfg
+ 0x100714e4 0x8 _L1e_DrvDdtrResetGet
+ 0x100714ec 0x7 _L1e_DrvDtrScaleResetCfg
+ 0x100714f3 0x8 _L1e_DrvDtrScaleEnCfg
+ 0x100714fb 0xb _L1e_DrvDtrScaleDtchEnCfg
+ 0x10071506 0x19 _L1e_DrvDtrScaleReset
+ 0x1007151f 0x8 _L1e_DrvDdtrModeCfg
+ 0x10071527 0x8 _L1e_DrvDdtrTurboLpCtrlRegCfg
+ 0x1007152f 0x8 _L1e_DrvDdtrSubfNumCfg
+ 0x10071537 0x8 _L1e_DrvDdtrHarqCtrlCfg
+ 0x1007153f 0x8 _L1e_DrvDdtrHarqIramCtrlCfg
+ 0x10071547 0xb _L1e_DrvDdtrHarqPriorityCfg
+ 0x10071552 0x8 _L1e_DrvDdtrHarqBurstCtrlCfg
+ 0x1007155a 0x8 _L1e_DrvDdtrIntTimerCfg
+ 0x10071562 0x8 _L1e_DrvDdtrLpCtrlCfg
+ 0x1007156a 0x8 _L1e_DrvDdtrUpdateCfg
+ 0x10071572 0xd _L1e_DrvDdtrTbCrcRead
+ 0x1007157f 0x9 _L1e_DrvDdtrSibPchCrcRead
+ 0x10071588 0x9 _L1e_DrvDdtrSubfNumRead
+ 0x10071591 0x9 _L1e_DrvDdtrIdleStateRead
+ 0x1007159a 0x9 _L1e_DrvDdtrErrorIndRead
+ 0x100715a3 0x1 _L1e_DrvDdtrTurboLpCtrlCfg
+ 0x100715a4 0xb _L1e_DrvDdtrPdschEnCfg
+ 0x100715af 0xb _L1e_DrvDdtrPdschEnRead
+ 0x100715ba 0xb _L1e_DrvDdtrSwapFlagCfg
+ 0x100715c5 0xb _L1e_DrvDdtrSwapFlagGet
+ 0x100715d0 0xe _L1e_DrvDdtrCwCinitCfg
+ 0x100715de 0xb _L1e_DrvDdtrTurboCtrlCfg
+ 0x100715e9 0xb _L1e_DrvDdtrPchBchTurboCtrlCfg
+ 0x100715f4 0x5d _L1e_DrvDdtrTbParamCfg
+ 0x10071651 0x8 _L1e_DrvDdtrPchCinitCfg
+ 0x10071659 0x11 _L1e_DrvDdtrPchParamCfg
+ 0x1007166a 0x8 _L1e_DrvDdtrSibCinitCfg
+ 0x10071672 0x11 _L1e_DrvDdtrSibParamCfg
+ 0x10071683 0x1d _L1e_DrvDdtrTurboReset
+ 0x100716a0 0x9 _L1e_DrvDdtrGetAxiInfo
+ 0x100716a9 0x39 _L1e_DrvDdtrPatchCfg
+ 0x100716e2 0x8 _L1e_DrvDdtrDbgGetDdtrMode
+ 0x100716ea 0x8 _L1e_DrvDdtrDbgGetTopErrInd
+ 0x100716f2 0x8 _L1e_DrvDdtrDbgGetAxiInfo
+ 0x100716fa 0x8 _L1e_DrvDdtrDbgGetIdleState
+ 0x10071702 0x8 _L1e_DrvDdtrDbgGetSubfNum
+ 0x1007170a 0xb _L1e_DrvDdtrDbgGetTurboCtrl
+ 0x10071715 0xb _L1e_DrvDdtrDbgGetTbCbCrc
+ 0x10071720 0xa _L1e_DrvDdtrGetDbgMontor1
+ 0x1007172a 0xa _L1e_DrvDdtrGetDbgMontor2
+ 0x10071734 0xf _L1e_DrvDdtrDbgSelCfg
+ 0x10071743 0x8 _L1e_DrvDdtrDbgSelCfgread
+ 0x1007174b 0x8 _L1e_DrvDdtrDbgSelCfgread0
+ 0x10071753 0x8 _L1e_DrvDdtrDbgSelCfgread1
+ 0x1007175b 0x8 _L1e_DrvDdtrDbgSelCfgread2
+ .text 0x10071763 0x454 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x10071763 0x1c _zPHY_DrvTopIntAbleBitSet
+ 0x1007177f 0x1f _zPHY_DrvTopIntMaskBitSet
+ 0x1007179e 0xc _zPHY_DrvTopIntMaskRegWR
+ 0x100717aa 0xc _zPHY_DrvTopIntMaskRegRD
+ 0x100717b6 0xc _zPHY_DrvGetTopIntStaus
+ 0x100717c2 0xc _zPHY_DrvGetTopIntVec
+ 0x100717ce 0xc _zPHY_DrvTopIntClear
+ 0x100717da 0x1f _zPHY_DrvTopIntEnable
+ 0x100717f9 0x5a _zPHY_eintc_IntRegPrint
+ 0x10071853 0x2c _zPHY_DrvTopIntReg_Print
+ 0x1007187f 0x1 _zPHY_DrvModemTopClkGate
+ 0x10071880 0x1 _zPHY_DrvModemTopClkSel
+ 0x10071881 0x11 _zPHY_LteModemTopClkCfg
+ 0x10071892 0x1b _zPHY_ResetModemHw
+ 0x100718ad 0x33 _zPHY_LteaModemTopCfgBackup
+ 0x100718e0 0x4a _zPHY_LteaModemTopCfgRecover
+ 0x1007192a 0x9 _zPHY_DrvTop_Reg_Set
+ 0x10071933 0x9 _zPHY_DrvTop_IntReg_Set
+ 0x1007193c 0x9 _zPHY_DrvTop_IntReg_Get
+ 0x10071945 0x28 _L1l_DrvMcuIntMask
+ 0x1007196d 0x28 _L1l_DrvMcuIntUnmask
+ 0x10071995 0xa _L1l_DrvMcuIntIreqClr
+ 0x1007199f 0x3a _L1l_DrvTopIntMask
+ 0x100719d9 0x39 _L1l_DrvTopIntRestore
+ 0x10071a12 0x48 _L1l_DrvTopIntEng
+ 0x10071a5a 0x1 _zPHY_DrvTOP_DFE_ClkPrintf
+ 0x10071a5b 0x1 _zPHY_DrvTOP_CSR_ClkPrintf
+ 0x10071a5c 0x7 _zPHY_DrvTOP_GetHarkRamSel
+ 0x10071a63 0x7 _zPHY_DrvTOP_GetTDHarkRamSel
+ 0x10071a6a 0x1 _zPHY_DrvTOP_Ddtr_ClkAndLpramPrintf
+ 0x10071a6b 0x37 _zPHY_DrvLteaPwrClkCtrl
+ 0x10071aa2 0x6 _zPHY_DrvPhyLteModemSel
+ 0x10071aa8 0x7 _zPHY_DrvRmHarqRamLteModeClkSelCfg
+ 0x10071aaf 0x5 _zPHY_DrvTurboModeSel
+ 0x10071ab4 0x58 _zPHY_DrvLteTpuClkSet
+ 0x10071b0c 0xe _zPHY_DrvLteTpuClkInit
+ 0x10071b1a 0x19 _zPHY_DrvChipTopRegInit
+ 0x10071b33 0x8 _zPHY_DrvTopCLKRegPOWGAT
+ 0x10071b3b 0x9 _zPHY_DrvTopCLKReg2m1SCfg
+ 0x10071b44 0x9 _zPHY_DrvTopCLKRegRfcCfg
+ 0x10071b4d 0xb _zPHY_DrvTop_RFInitReg_Set
+ 0x10071b58 0x5f _zPHY_DMA_Cfg
+ .text 0x10071bb7 0x2b6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x10071bb7 0x58 _L1L_TpuDrvReset
+ 0x10071c0f 0x33 _L1L_TpuDrvSuspend
+ 0x10071c42 0x3f _L1L_TpuDrvResume
+ 0x10071c81 0x7 _L1L_TpuDrvCpModeGet
+ 0x10071c88 0x46 _L1L_TpuDrvCpModeSet
+ 0x10071cce 0x1c _L1L_TpuDrvLocalMrtrGet
+ 0x10071cea 0x1c _L1L_TpuDrvMrtrGet
+ 0x10071d06 0xe _L1L_TpuDrvMrtrOffsetGet
+ 0x10071d14 0x47 _L1L_TpuDrvTpuRegister
+ 0x10071d5b 0x1b _L1L_TpuDrvMicroAdj
+ 0x10071d76 0x6 _L1L_TpuDrvMacroAdj
+ 0x10071d7c 0x20 _L1L_TpuDrvHwBackup
+ 0x10071d9c 0xb _L1L_TPUDrvCPModeGet
+ 0x10071da7 0xb _L1L_TPUDrvCPModeSet
+ 0x10071db2 0xa _L1L_TPUDrvMrtrOffGet
+ 0x10071dbc 0x8 _L1L_TPUDrvMrtrOffSet
+ 0x10071dc4 0x8 _L1L_TPUDrvAdjTimeSet
+ 0x10071dcc 0xc _L1L_TPUDrvCPMrtrOffStore
+ 0x10071dd8 0xa _L1L_TPUDrvMRTRTransfer
+ 0x10071de2 0x8 _L1L_TPUDrvLocalMrtrGet
+ 0x10071dea 0x8 _L1L_TPUDrvMrtrGet
+ 0x10071df2 0xb _L1L_TPUDrvHWResetCfg
+ 0x10071dfd 0xf _L1L_TpuDrvRAMCtrl
+ 0x10071e0c 0x8 _L1L_TPUDrvInttoArmIndexGet
+ 0x10071e14 0x9 _L1L_TpuDrvIntECTRamSel
+ 0x10071e1d 0x50 _L1L_TPUDrvIntECTInit
+ .text 0x10071e6d 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x10071e6d 0xea _zPHY_emc_DlDataReport
+ 0x10071f57 0x27 _zPHY_emc_RdUlDataSendCtrlInfo
+ 0x10071f7e 0x20 _zPHY_emc_wrUlReportBlerInfo
+ 0x10071f9e 0x53 _zPHY_emc_WrUlSchedInfo
+ 0x10071ff1 0x25 _zPHY_emc_InitRpMsgCh
+ 0x10072016 0x8 _zPHY_emc_MaskRpMsgCh
+ 0x1007201e 0x8 _zPHY_emc_UnMaskRpMsgCh
+ 0x10072026 0x9 _L1e_DrvGetIramTempCtrlBit
+ 0x1007202f 0x12 _L1e_DrvGetLteTempCtrlLimitInd
+ 0x10072041 0xa _L1e_DrvGetDlSibPduCrcBaseAddr
+ 0x1007204b 0xb _L1e_DrvGetDlSibPduDataBaseAddr
+ 0x10072056 0xa _L1e_DrvGetDlPchPduCrcBaseAddr
+ 0x10072060 0xb _L1e_DrvGetDlPchPduDataBaseAddr
+ 0x1007206b 0xa _L1e_DrvGetDlRarPduCrcBaseAddr
+ 0x10072075 0xb _L1e_DrvGetDlRarPduDataBaseAddr
+ 0x10072080 0x17 _L1e_DrvGetDlMacPduHarqBaseAddr
+ 0x10072097 0xb _L1e_DrvGetDlMacPduCrcBaseAddr
+ 0x100720a2 0xd _L1e_DrvSetIslandAddr
+ .text 0x100720af 0x57c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x100720af 0x7 _zPHY_elpc_DrvDelay
+ 0x100720b6 0x85 _L1l_DrvLpcGetSleepLen
+ 0x1007213b 0x32 _L1l_DrvLpcGetRemainCaliTime
+ 0x1007216d 0x8c _zPHY_elpc_LpmTimerCtrl
+ 0x100721f9 0x26 _L1_LTE_GetLpmTimerIsEn
+ 0x1007221f 0x4 _L1L_DrvLpcSocWakeUpIntCtrl
+ 0x10072223 0x1d _L1L_DrvLpcModemWakeUpIntCtrl
+ 0x10072240 0x1b _L1L_DrvLpcCfgSocWkupInt
+ 0x1007225b 0x23 _L1L_DrvLpcCfgModemWkupInt
+ 0x1007227e 0x16 _L1l_DrvLpcGetLpmNT
+ 0x10072294 0x4b _L1l_DrvLpcWaitLpmMrtrChange
+ 0x100722df 0x19 _zPHY_elpc_DrvLpmCaliCfg
+ 0x100722f8 0x10 _zPHY_elpc_DrvPdLteaCsrBackup
+ 0x10072308 0x6 _zPHY_elpc_DrvPdLteaTxBackup
+ 0x1007230e 0x1e _zPHY_elpc_DrvPdLteaCsrRecover
+ 0x1007232c 0x6 _zPHY_elpc_DrvPdLteaTxRecover
+ 0x10072332 0x11 _zPHY_elpc_DrvPdLteaRfcDfeBackup
+ 0x10072343 0x16 _zPHY_elpc_DrvPdLteaRfcDfeRecover
+ 0x10072359 0x5 _zPHY_elpc_DrvPdLteaRxRecover
+ 0x1007235e 0xf _zPHY_elpc_DrvPdLteaMimoCdtrRecover
+ 0x1007236d 0x5 _zPHY_elpc_DrvPdLteaDdtrHarqRecover
+ 0x10072372 0x19 _zPHY_elpc_DrvPdLteaStdbyCtrl
+ 0x1007238b 0x47 _zPHY_elpc_DrvPdHwIsBusy
+ 0x100723d2 0x1a _zPHY_elpc_DrvLteaPwrScenarioCtrlLog
+ 0x100723ec 0x37 _zPHY_elpc_DrvLteaPwrHwBackup
+ 0x10072423 0x12e _zPHY_elpc_DrvLteaPwrScenarioCtrl
+ 0x10072551 0xc1 _zPHY_elpc_DrvLteaPwrCtrl
+ 0x10072612 0x19 _zPHY_eLpc_DrvClearLteaModemInt
+ .text 0x1007262b 0x802 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ 0x1007262b 0x24 _zPHY_eltx_SoftReset
+ 0x1007264f 0x10 _zPHY_eltx_GetHWVersion
+ 0x1007265f 0x10 _zPHY_eltx_GetStatus
+ 0x1007266f 0x42 _zPHY_eltx_Clk_En
+ 0x100726b1 0xa _zPHY_eltx_SetCPType
+ 0x100726bb 0x12 _zPHY_eltx_SetChannelType
+ 0x100726cd 0x27 _zPHY_eltx_SetSysBandwidth
+ 0x100726f4 0xc _zPHY_eltx_SetTxTa
+ 0x10072700 0x9 _zPHY_eltx_SetPortSel
+ 0x10072709 0x14 _zPHY_eltx_SetFirstSfFlag
+ 0x1007271d 0xf _zPHY_eltx_SetConsecutiveSFLast
+ 0x1007272c 0x1e _zPHY_eltx_SetFirstLastMode
+ 0x1007274a 0xa _zPHY_eltx_SetSendMode
+ 0x10072754 0xe _zPHY_eltx_SetAbbSampleRate
+ 0x10072762 0x14 _zPHY_eltx_SetInterMatrixInfo
+ 0x10072776 0xc _zPHY_eltx_SetPuschScreamblePara
+ 0x10072782 0xe _zPHY_eltx_SetPuschModulationMode
+ 0x10072790 0xc _zPHY_eltx_SetPuschDFTPointNumber
+ 0x1007279c 0x9 _zPHY_eltx_SetPrecodingCodeBook
+ 0x100727a5 0x19 _zPHY_eltx_SetAckRiInfo
+ 0x100727be 0x4c _zPHY_eltx_SetRiMultiplexingInfo
+ 0x1007280a 0x77 _zPHY_eltx_SetAckMultiplexingInfo
+ 0x10072881 0xc _zPHY_eltx_SetPucchScreambleCint
+ 0x1007288d 0x24 _zPHY_eltx_SetPucchHarqAckinfo
+ 0x100728b1 0x1c _zPHY_eltx_SetPucchCqiInfo
+ 0x100728cd 0xe _zPHY_eltx_SetPucchFmt
+ 0x100728db 0x20 _zPHY_eltx_SetPucchCommonReg
+ 0x100728fb 0x20 _zPHY_eltx_SetPucchZCParas
+ 0x1007291b 0x7f _zPHY_eltx_SetPucchNcsParas
+ 0x1007299a 0x72 _zPHY_eltx_SetPuschDmrsParas
+ 0x10072a0c 0x68 _zPHY_eltx_SetSrsParas
+ 0x10072a74 0x3c _zPHY_eltx_SetPrachParas
+ 0x10072ab0 0x3e _zPHY_eltx_SetScale
+ 0x10072aee 0x2b _zPHY_eltx_SetPuschReMappingParas
+ 0x10072b19 0x1c _zPHY_eltx_SetPucchReMappingParas
+ 0x10072b35 0x4b _zPHY_eltx_TxCalibrationPreIQOrDC
+ 0x10072b80 0x4b _zPHY_eltx_SetTxCalibrationParas
+ 0x10072bcb 0x19 _zPHY_eltx_SetFilter1Coeff
+ 0x10072be4 0x19 _zPHY_eltx_SetFilter2Coeff
+ 0x10072bfd 0x19 _zPHY_eltx_SetFilter3Coeff
+ 0x10072c16 0xc _zPHY_eltx_SetByPass
+ 0x10072c22 0x9 _zPHY_eltx_SetFiFO
+ 0x10072c2b 0xb _zPHY_eltx_SetAntPhaseClkDelay
+ 0x10072c36 0xc _zPHY_eltx_SetAntFrameDlyNum
+ 0x10072c42 0x2 _zPHY_eltx_SetPucchFormat3Paras
+ 0x10072c44 0xe _zPHY_eltx_Enable
+ 0x10072c52 0x9 _zPHY_eltx_SetDebugMode
+ 0x10072c5b 0x9 _zPHY_eltx_SetDebugBusSel
+ 0x10072c64 0x9 _zPHY_eula_SetTXIntPulse
+ 0x10072c6d 0xa _zPHY_eltx_SetLTXIntSymbol
+ 0x10072c77 0x30 _zPHY_eltx_SetPRS1Paras
+ 0x10072ca7 0x31 _zPHY_eltx_GetPRS1Result
+ 0x10072cd8 0x30 _zPHY_eltx_SetPRS2Paras
+ 0x10072d08 0x2f _zPHY_eltx_GetPRS2Result
+ 0x10072d37 0x62 _zPHY_eula_TxRFCDBB_Interface
+ 0x10072d99 0x9 _zPHY_eula_SetTxDmaConfig
+ 0x10072da2 0xb _zPHY_eula_SetLtxFreqCompBypass
+ 0x10072dad 0xb _zPHY_eula_SetLtxFreqCompTheta
+ 0x10072db8 0xb _zPHY_eula_SetLtxFreqCompTheta0
+ 0x10072dc3 0x48 _zPHY_eula_TxFreqCompValGet
+ 0x10072e0b 0x11 _zPHY_eula_TxCordicInit
+ 0x10072e1c 0x11 _zPHY_eula_TxCordicCfg
+ .text 0x10072e2d 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ 0x10072e2d 0x19 _zPHY_ecsrm_MeasHwReset
+ 0x10072e46 0x77 _zPHY_ecsrm_MeasHwConfig
+ 0x10072ebd 0x79 _zPHY_ecsrm_MeasResultRead
+ 0x10072f36 0x45 _zPHY_ecsrm_GetMeasDoneFlag
+ 0x10072f7b 0xb _zPHY_ecsrm_GetRspCnt
+ 0x10072f86 0xc _zPHY_ecsrm_ClearMeasDoneFlag
+ .text 0x10072f92 0x8de T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x10072f92 0x1b _L1e_DrvRxResetHW
+ 0x10072fad 0xd1 _L1e_DrvRxCcRegInit
+ 0x1007307e 0x92 _L1e_DrvRxPccRegInit
+ 0x10073110 0x30 _L1e_DrvRxWriteRamCosWinCoeff
+ 0x10073140 0x10 _L1e_DrvRxTransformFirCoeff
+ 0x10073150 0x1c _L1e_DrvRxInitMrsFirCoeff
+ 0x1007316c 0x61 _L1e_DrvRxWriteRamFICoeff
+ 0x100731cd 0x14 _zPHY_Drv_Rx_HwInit
+ 0x100731e1 0x18 _L1e_DrvRxWritePcfichPosRegFile
+ 0x100731f9 0x19 _zPHY_Drv_Rx_WritePhichPosRegFile
+ 0x10073212 0x1 _zPHY_Drv_Rx_ClkPrintf
+ 0x10073213 0x8 _L1e_DrvRxGateCtrlRead
+ 0x1007321b 0x8 _L1e_DrvRxClkSwitch0Cfg
+ 0x10073223 0x8 _L1e_DrvRxClkSwitch0Read
+ 0x1007322b 0x8 _L1e_DrvRxPort5PatchCfg
+ 0x10073233 0x8 _L1e_DrvRxPccCsiCheTimeRead
+ 0x1007323b 0x8 _L1e_DrvRxPbchCtrlCfg
+ 0x10073243 0x8 _L1e_DrvRxPbchCtrlRead
+ 0x1007324b 0x8 _L1e_DrvRxCarrierInfoCfg
+ 0x10073253 0x8 _L1e_DrvRxCarrierInfoRead
+ 0x1007325b 0xb _L1e_DrvRxRxModeCfg
+ 0x10073266 0xb _L1e_DrvRxRxModeRead
+ 0x10073271 0xb _L1e_DrvRxRatModeCfg
+ 0x1007327c 0xb _L1e_DrvRxCpModeCfg
+ 0x10073287 0xb _L1e_DrvRxCpModeRead
+ 0x10073292 0xb _L1e_DrvRxVshiftCfg
+ 0x1007329d 0xb _L1e_DrvRxVshiftRead
+ 0x100732a8 0xe _L1e_DrvRxPcfichRegPosCfg
+ 0x100732b6 0xe _L1e_DrvRxPhichRegPosCfg
+ 0x100732c4 0x18 _L1e_DrvRxCellInfoCfg
+ 0x100732dc 0xb _L1e_DrvRxCellInfoRead
+ 0x100732e7 0xe _L1e_DrvRxSfnTypeCfg
+ 0x100732f5 0xe _L1e_DrvRxSfnTypeRead
+ 0x10073303 0x13 _L1e_DrvRxTmIndCfg
+ 0x10073316 0xb _L1e_DrvRxMbsfnCfiCfg
+ 0x10073321 0xb _L1e_DrvRxMbsfnTm9IndCfg
+ 0x1007332c 0xb _L1e_DrvRxCirAccCtrlCfg
+ 0x10073337 0xb _L1e_DrvRxCirAccCtrlRead
+ 0x10073342 0xb _L1e_DrvRxMrsCirAccCtrlCfg
+ 0x1007334d 0xb _L1e_DrvRxMrsCirAccCtrlRead
+ 0x10073358 0xb _L1e_DrvRxN0FgtFactorlCfg
+ 0x10073363 0x8 _L1e_DrvRxN0FgtFactorRead
+ 0x1007336b 0xb _L1e_DrvRxN0ModeCfg
+ 0x10073376 0xb _L1e_DrvRxN0ModeRead
+ 0x10073381 0xb _L1e_DrvRxSwN0ValCfg
+ 0x1007338c 0xb _L1e_DrvRxSwN0ValRead
+ 0x10073397 0xb _L1e_DrvRxMbsfnN0FgtCfg
+ 0x100733a2 0xb _L1e_DrvRxMbsfnN0FgtRead
+ 0x100733ad 0xb _L1e_DrvRxEicicModeCfg
+ 0x100733b8 0xb _L1e_DrvRxEicicModeRead
+ 0x100733c3 0xb _L1e_DrvRxBniCtrlCfg
+ 0x100733ce 0x1 _L1e_DrvRxNbnbCtrlCfg
+ 0x100733cf 0x2 _L1e_DrvRxNbnbCtrlRead
+ 0x100733d1 0xb _L1e_DrvRxCchModuModeCfg
+ 0x100733dc 0xb _L1e_DrvRxCchModuModeRead
+ 0x100733e7 0xb _L1e_DrvRxCchPcVolCfg
+ 0x100733f2 0xb _L1e_DrvRxCchPcPowCfg
+ 0x100733fd 0xb _L1e_DrvRxCsiRsCfg
+ 0x10073408 0xb _L1e_DrvRxHijRptModeCfg
+ 0x10073413 0xb _L1e_DrvRxTiCrsRptModeCfg
+ 0x1007341e 0xb _L1e_DrvRxTiCrsRptModeRead
+ 0x10073429 0xb _L1e_DrvRxPhichMatrixCfg
+ 0x10073434 0xb _L1e_DrvRxCchWorkModeCfg
+ 0x1007343f 0xb _L1e_DrvRxTiModeCfg
+ 0x1007344a 0xb _L1e_DrvRxTiModeRead
+ 0x10073455 0x10 _L1e_DrvRxAgcBalanceCfg
+ 0x10073465 0xe _L1e_DrvRxAgcBalanceRead
+ 0x10073473 0xb _L1e_DrvRxZpCsiBmpCfg
+ 0x1007347e 0xe _L1e_DrvRxZpCsiPosCfg
+ 0x1007348c 0xe _L1e_DrvRxCrsCinitCfg
+ 0x1007349a 0xe _L1e_DrvRxCrsCinitRead
+ 0x100734a8 0xe _L1e_DrvRxCsiRsCinitCfg
+ 0x100734b6 0xb _L1e_DrvRxRsParamCfg
+ 0x100734c1 0xe _L1e_DrvRxIcCrsCinitCfg
+ 0x100734cf 0xb _L1e_DrvRxIcRsParamCfg
+ 0x100734da 0x26 _L1e_DrvRxN0BetaCfg
+ 0x10073500 0x27 _L1e_DrvRxN0BetaRead
+ 0x10073527 0xb _L1e_DrvRxSwFirUpdateCfg
+ 0x10073532 0x8 _L1e_DrvRxFixFirUpdateCfg
+ 0x1007353a 0xb _L1e_DrvRxDrsGenStateCfg
+ 0x10073545 0xb _L1e_DrvRxDrsCinitCfg
+ 0x10073550 0xb _L1e_DrvRxDrsParamCfg
+ 0x1007355b 0xb _L1e_DrvRxRbBmpValidCfg
+ 0x10073566 0x13 _L1e_DrvRxRbBmpCfg
+ 0x10073579 0xb _L1e_DrvRxPrbBundlingBmpCfg
+ 0x10073584 0xb _L1e_DrvRxCsiRsDelCtrlCfg
+ 0x1007358f 0xb _L1e_DrvRxCsiRsDelCtrlRead
+ 0x1007359a 0xb _L1e_DrvRxPdschModuModeCfg
+ 0x100735a5 0xb _L1e_DrvRxPdschModuModeRead
+ 0x100735b0 0xb _L1e_DrvRxPdschMimoModeCfg
+ 0x100735bb 0xb _L1e_DrvRxPdschMimoModeRead
+ 0x100735c6 0xb _L1e_DrvRxPdschRbMaskCfg
+ 0x100735d1 0xb _L1e_DrvRxPdschTpmiCfg
+ 0x100735dc 0x10 _L1e_DrvRxDchPcVolCfg
+ 0x100735ec 0x10 _L1e_DrvRxDchPcPowCfg
+ 0x100735fc 0xb _L1e_DrvRxPcEnCfg
+ 0x10073607 0xb _L1e_DrvRxPort7IndCfg
+ 0x10073612 0xb _L1e_DrvRxMimoAlgoCfg
+ 0x1007361d 0xb _L1e_DrvRxBfAlgoCfg
+ 0x10073628 0xb _L1e_DrvRxPdschValidCfg
+ 0x10073633 0x13 _L1e_DrvRxCrsRssiRead
+ 0x10073646 0x13 _L1e_DrvRxCrsRspRead
+ 0x10073659 0x16 _L1e_DrvRxCrsRsrpRead
+ 0x1007366f 0xb _L1e_DrvRxCfoPhaseRead
+ 0x1007367a 0x13 _L1e_DrvRxMbsfnRssiRead
+ 0x1007368d 0x13 _L1e_DrvRxMbsfnRspRead
+ 0x100736a0 0x13 _L1e_DrvRxMbsfnRsrpRead
+ 0x100736b3 0x1c _L1e_DrvRxN0Read
+ 0x100736cf 0x1e _L1e_DrvRxCirPeakPosRead
+ 0x100736ed 0x22 _L1e_DrvRxDrsRsrpRead
+ 0x1007370f 0x24 _L1e_DrvRxDrsRspRead
+ 0x10073733 0xb _L1e_DrvRxDrsAccNumRead
+ 0x1007373e 0xc _L1e_DrvRxGetGenStateInd
+ 0x1007374a 0x6 _L1e_DrvRx_CqiHRx0
+ 0x10073750 0x6 _L1e_DrvRx_CqiNo0
+ 0x10073756 0x6 _L1e_DrvRx_R
+ 0x1007375c 0xd _L1e_DrvRxTpmiRamCfg
+ 0x10073769 0xd _L1e_DrvRxFirFixRamCfg
+ 0x10073776 0x6 _L1e_DrvRxFirFixRamRec
+ 0x1007377c 0x16 _L1e_DrvRxFirDynRamCfg
+ 0x10073792 0x1 _L1e_DrvRxFftBitmapRamCfg
+ 0x10073793 0x1 _L1e_DrvRxTiAptRamRead
+ 0x10073794 0x28 _L1e_DrvRxCirRamDataRead
+ 0x100737bc 0xb4 _L1e_DrvRxDbgLogRxCheReg
+ .text 0x10073870 0x209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ 0x10073870 0x1d _zPHY_elutr_SoftReset
+ 0x1007388d 0x12 _zPHY_elutr_GetHWVersion
+ 0x1007389f 0x1f _zPHY_elutr_HarqRam_Harness
+ 0x100738be 0x2b _zPHY_elutr_HarqRam_NoHarness
+ 0x100738e9 0x3a _zPHY_elutr_Clk_En
+ 0x10073923 0xe _zPHY_elutr_Enable
+ 0x10073931 0x9 _zPHY_elutr_GetHWStatus
+ 0x1007393a 0x13 _zPHY_elutr_CommonReg
+ 0x1007394d 0xc _zPHY_elutr_Modulation
+ 0x10073959 0xc _zPHY_elutr_SetTBLength
+ 0x10073965 0x24 _zPHY_elutr_SetTBSegParas
+ 0x10073989 0x1a _zPHY_elutr_SetTurboParas
+ 0x100739a3 0x25 _zPHY_elutr_SetRateMatchParas
+ 0x100739c8 0xc _zPHY_elutr_SetInterMatrixColNumber
+ 0x100739d4 0x24 _zPHY_elutr_SetPuschAckParas
+ 0x100739f8 0xe _zPHY_elutr_SetPuschAckUpdate
+ 0x10073a06 0x15 _zPHY_elutr_SetPuschRiParas
+ 0x10073a1b 0xe _zPHY_elutr_SetPuschRiUpdate
+ 0x10073a29 0x25 _zPHY_elutr_SetPuschCqiParas
+ 0x10073a4e 0xc _zPHY_elutr_SetPuschSubCarrierNumber
+ 0x10073a5a 0x1f _zPHY_elutr_SetRiMultiplexingInfo
+ .text 0x10073a79 0x22a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ 0x10073a79 0x1b _L1e_DrvRxMimoReset
+ 0x10073a94 0x19 _L1e_DrvPbchCdtrViterbiReset
+ 0x10073aad 0x1b _L1e_DrvPbchHWReset
+ 0x10073ac8 0x2 _L1e_DrvPbchInit
+ 0x10073aca 0x6a _L1e_DrvPbchConfigPbchReg
+ 0x10073b34 0xde _L1e_DrvPbchConfigRxReg
+ 0x10073c12 0x22 _L1e_DrvPbchGenRxSubFrmHead
+ 0x10073c34 0x23 _L1e_DrvPbchScGeneration
+ 0x10073c57 0x8 _L1e_DrvPbchCdtrViterbiClkRead
+ 0x10073c5f 0x8 _L1e_DrvPbchResultRead
+ 0x10073c67 0x8 _L1e_DrvPbchAntSfnRead
+ 0x10073c6f 0x8 _L1e_DrvPbchStateRead
+ 0x10073c77 0x9 _L1e_DrvPbchCdtrViterbiCtrl
+ 0x10073c80 0x9 _L1e_DrvPbchCdtrVtbRamLpCtrl
+ 0x10073c89 0x8 _L1e_DrvPbchLpcCfg
+ 0x10073c91 0x9 _L1e_DrvCdtrlkEn
+ 0x10073c9a 0x9 _L1e_DrvPbchClkEn
+ .text 0x10073ca3 0x36f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ 0x10073ca3 0x7 _L1e_DrvMimoCaRstCfg
+ 0x10073caa 0xb _L1e_DrvMimoIrcModeCfg
+ 0x10073cb5 0xb _L1e_DrvMimoIrcModeRead
+ 0x10073cc0 0x8 _L1e_DrvMimoUpdateCfg
+ 0x10073cc8 0x8 _L1e_DrvMimoUpdateRead
+ 0x10073cd0 0x8 _L1e_DrvCdtrResetCfg
+ 0x10073cd8 0x1b _L1e_DrvCdtrHwReset
+ 0x10073cf3 0x19 _L1e_DrvMimoReset
+ 0x10073d0c 0x43 _L1e_DrvCdtrHwInit
+ 0x10073d4f 0x8 _L1e_DrvCdtrTopClkSelCfg
+ 0x10073d57 0x26 _L1e_DrvCdtrTopRegCfg
+ 0x10073d7d 0x9 _L1e_DrvCdtrLpcCtrl
+ 0x10073d86 0x1b _L1e_DrvCdtrPcfichRegCfg
+ 0x10073da1 0x3b _L1e_DrvCdtrPhichRegCfg
+ 0x10073ddc 0x93 _L1e_DrvCdtrPdcchBldRegCfg
+ 0x10073e6f 0x54 _L1e_DrvCdtrPdcchDmpRegCfg
+ 0x10073ec3 0xb _L1e_DrvCdtrPhichNumCfg
+ 0x10073ece 0xb _L1e_DrvCdtrCchEnableCfg
+ 0x10073ed9 0xc _L1e_DrvCdtrRntiEnRead
+ 0x10073ee5 0xc _L1e_DrvCdtrCfiValueRead
+ 0x10073ef1 0xc _L1e_DrvCdtrHiNumRead
+ 0x10073efd 0xf _L1e_DrvCdtrHiValueRead
+ 0x10073f0c 0xc _L1e_DrvCdtrDciPld1Read
+ 0x10073f18 0xc _L1e_DrvCdtrDciPld2Read
+ 0x10073f24 0x1d _L1e_DrvCdtrDciRead
+ 0x10073f41 0x17 _L1e_DrvCdtrDciInfoRead
+ 0x10073f58 0xc _L1e_DrvCdtrDciValidRead
+ 0x10073f64 0xc _L1e_DrvCdtrUePortRead
+ 0x10073f70 0x8 _L1e_DrvCdtrDbgGetIntType
+ 0x10073f78 0xb _L1e_DrvCdtrDbgGetDlDciInfo
+ 0x10073f83 0x11 _L1e_DrvCdtrDbgGetDlDciFlag
+ 0x10073f94 0x11 _L1e_DrvCdtrDbgGetSiDciFlag
+ 0x10073fa5 0x11 _L1e_DrvCdtrDbgGetPmDciFlag
+ 0x10073fb6 0x11 _L1e_DrvCdtrDbgGetRaDciFlag
+ 0x10073fc7 0x4b _L1e_DrvCdtrPdcchBmpRamCfg
+ .text 0x10074012 0x7f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x10074012 0x38 _zPHY_erfc_DrvGetSubFrameAddr
+ 0x1007404a 0xd1 _zPHY_erfc_DrvRealwokEventEn
+ 0x1007411b 0x62 _zPHY_erfc_DrvInitAllEventEnArray
+ 0x1007417d 0x186 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg
+ 0x10074303 0x1 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg_Slave
+ 0x10074304 0x87 _zPHY_erfc_DrvAFCEventEn
+ 0x1007438b 0x10 _zPHY_erfc_DrvSpiWrite
+ 0x1007439b 0x59 _zPHY_erfc_DrvSetAgcSpiReg
+ 0x100743f4 0xa _zPHY_erfc_DrvRbdp_RxIQInvert
+ 0x100743fe 0xa _zPHY_erfc_DrvRbdp_TxIQInvert
+ 0x10074408 0x1 _zPHY_erfc_DrvRbdpModeCfg
+ 0x10074409 0x1 _zPHY_erfc_DrvTopRBDPGPIOConfig
+ 0x1007440a 0x1 _zPHY_erfc_DrvTopSSCConfig
+ 0x1007440b 0xa _zPHY_erfc_DrvMasterModeTopGPIOConfig
+ 0x10074415 0x1 _zPHY_erfc_DrvEventRamLeaveLP
+ 0x10074416 0x50 _zPHY_erfc_DrvRfcRegInit
+ 0x10074466 0x1 _zPHY_erfc_DrvRfcRegInit_Slave
+ 0x10074467 0x91 _zPHY_erfc_DrvRFEventRamInit
+ 0x100744f8 0x1b _zPHY_erfc_DrvSoftwareReset
+ 0x10074513 0x18 _zPHY_erfc_DrvResetHw
+ 0x1007452b 0xe _zPHY_erfc_DrvWriteCmdEvent
+ 0x10074539 0xe _zPHY_erfc_DrvDBBEventSet
+ 0x10074547 0x6 _zPHY_erfc_GetDfeSampleRateAddr
+ 0x1007454d 0x2c _zPHY_erfc_GetRfcShadowEventTableAddr
+ 0x10074579 0x33 _zPHY_erfc_GetRfcEventTableAddr
+ 0x100745ac 0x33 _zPHY_erfc_GetRfcBackupDDREventTableAddr
+ 0x100745df 0x30 _zPHY_erfc_DrvGetRamState
+ 0x1007460f 0x85 _zPHY_erfc_DrvEvtTabStart
+ 0x10074694 0x12 _zPHY_erfc_DrvGPIOEventSet
+ 0x100746a6 0xb _zPHY_erfc_DrvOpenfilter0
+ 0x100746b1 0xb _zPHY_erfc_DrvClosefilter0
+ 0x100746bc 0xb _zPHY_erfc_DrvOpenfilter1
+ 0x100746c7 0xb _zPHY_erfc_DrvClosefilter1
+ 0x100746d2 0xe _zPHY_erfc_DrvOpenfilter2
+ 0x100746e0 0xb _zPHY_erfc_DrvClosefilter2
+ 0x100746eb 0x10 _zPHY_erfc_DrvDfeRXBandWidthEn
+ 0x100746fb 0x10 _zPHY_erfc_DrvDfeMeas0BandWidthEn
+ 0x1007470b 0xb _zPHY_erfc_DrvGetfilter2State
+ 0x10074716 0x7 _zPHY_erfc_DrvGetfilterState
+ 0x1007471d 0x7 _zPHY_erfc_DrvGetSpiReadData
+ 0x10074724 0x7 _zPHY_erfc_DrvGetMipiReadData
+ 0x1007472b 0x9 _zPHY_erfc_DrvSetRxRemovCpOffset
+ 0x10074734 0x54 _zPHY_erfc_DrvEvtSetTableOffset
+ 0x10074788 0x9 _zPHY_erfc_DrvEnTxCalibration
+ 0x10074791 0x1 _zPHY_erfc_DrvSlaveModeTopGPIOConfig
+ 0x10074792 0xb _zPHY_erfc_DrvRfcRXBandWidthEn
+ 0x1007479d 0xb _zPHY_erfc_DrvRfcMeas0BandWidthEn
+ 0x100747a8 0x1a _zPHY_erfc_DrvInitTuRamTxEnReg
+ 0x100747c2 0x25 _zPHY_erfc_DrvInitTuRamTxTable
+ 0x100747e7 0x23 _zPHY_erfc_DrvInitTuRegTxTable
+ .text 0x1007480a 0x1ae0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x1007480a 0xcb _sin_wave_test_dfe
+ 0x100748d5 0x5a _zPHY_erfc_DrvRfcRffeWrite
+ 0x1007492f 0x7a _zPHY_erfc_MIPI_Config
+ 0x100749a9 0x1 _zPHY_erfc_DrvRfcRffeSwitchInit
+ 0x100749aa 0x9f _zPHY_erfc_DrvDFESetAcp405Gain
+ 0x10074a49 0x25 _zPHY_erfc_DrvSpiCtrlWordPreDef
+ 0x10074a6e 0x4b _zPHY_erfc_DrvPaAndAntOpenForRX
+ 0x10074ab9 0x7b _zPHY_erfc_DrvPaAndAntOpenForTX
+ 0x10074b34 0x8e _zPHY_erfc_Idle2TDRX
+ 0x10074bc2 0x82 _zPHY_erfc_Idle2TDTX
+ 0x10074c44 0x2f _zPHY_erfc_TxDbbSingleTone
+ 0x10074c73 0xc _zPHY_erfc_TransToRX
+ 0x10074c7f 0xe _zPHY_erfc_TransToTX
+ 0x10074c8d 0x1 _zPHY_erfc_DrvACP405GpioTest
+ 0x10074c8e 0xc _zPHY_erfc_DrvACP405Spi32BitWrReg
+ 0x10074c9a 0x11 _zPHY_erfc_ZTERfSPIWrite
+ 0x10074cab 0x20 _zPHY_erfc_ZTERfSPIRead
+ 0x10074ccb 0x1f _zPHY_erfc_ZTERfMIPIRead
+ 0x10074cea 0x1f _zPHY_erfc_ZTEAbbSPIRead
+ 0x10074d09 0xa _zPHY_erfc_DrvZTE110RegSet
+ 0x10074d13 0x49 _zPHY_erfc_DrvZTE110RxBandAndWidthConf
+ 0x10074d5c 0x10 _zPHY_erfc_DrvZTE120TxDACEn
+ 0x10074d6c 0x10 _zPHY_erfc_DrvZTE120TxDTXModeEn
+ 0x10074d7c 0xf _zPHY_erfc_DrvZTE120TxDACClk
+ 0x10074d8b 0x33 _zPHY_erfc_DrvCalcFracFreq
+ 0x10074dbe 0x72 _zPHY_erfc_ZTE110_RxRegConfig
+ 0x10074e30 0x65 _zPHY_erfc_ZTE110_TxRegConfig
+ 0x10074e95 0x3a _zPHY_erfc_ZTE120_RxRegConfig
+ 0x10074ecf 0x36 _zPHY_erfc_ZTE120_TxRegConfig
+ 0x10074f05 0x8c _zPHY_erfc_GetOpenRxRamNum
+ 0x10074f91 0x1c5 _zPHY_erfc_EventOpenRx
+ 0x10075156 0x89 _zPHY_erfc_EventOpenRxAntenna
+ 0x100751df 0x18c _zPHY_erfc_EventOpenTx
+ 0x1007536b 0x65 _zPHY_erfc_EventOpenTxAntenna
+ 0x100753d0 0x92 _zPHY_erfc_GetOpenRxAntennaIndex
+ 0x10075462 0xe9 _zPHY_erfc_GetOpenRxIndex
+ 0x1007554b 0x30 _zPHY_erfc_GetOpenTxIndex
+ 0x1007557b 0x35 _zPHY_erfc_GetOpenTxAntennaIndex
+ 0x100755b0 0x26 _zPHY_erfc_GetOpenTxRamNum
+ 0x100755d6 0xdc _zPHY_erfc_GetOpenRxLineIndex
+ 0x100756b2 0x70 _zPHY_erfc_GetOpenRxLineData
+ 0x10075722 0x55 _zPHY_erfc_GetNorTxOpenIndex
+ 0x10075777 0x57 _zPHY_erfc_GetOpenTxLineIndex
+ 0x100757ce 0x6d _zPHY_erfc_GetOpenTxLineData
+ 0x1007583b 0xb6 _zPHY_erfc_EventTableOpenRx
+ 0x100758f1 0xae _zPHY_erfc_TxTableOpenTx
+ 0x1007599f 0xd8 _zPHY_erfc_GetCloseAntennaIndex
+ 0x10075a77 0xdf _zPHY_erfc_GetRfToIdleIndex
+ 0x10075b56 0x75 _zPHY_erfc_GetRfToIdleData
+ 0x10075bcb 0x97 _zPHY_erfc_EventAntennaToIdle
+ 0x10075c62 0xb9 _zPHY_erfc_EventRfToIdle
+ 0x10075d1b 0x2d _zPHY_erfc_GetCloseRfRamNum
+ 0x10075d48 0x54 _zPHY_erfc_EventTableToIdle
+ 0x10075d9c 0x111 _zPHY_erfc_GetPAIndex
+ 0x10075ead 0x7d _zPHY_erfc_AmtRfFrontSet
+ 0x10075f2a 0x2f _zPHY_erfc_RfAntenna_set
+ 0x10075f59 0x6b _zPHY_erfc_RfPAFrontSet
+ 0x10075fc4 0x25 _zPHY_erfc_ATSetAptFixVoltage
+ 0x10075fe9 0xe8 _zPHY_erfc_GetRfVGACtrlWord
+ 0x100760d1 0x14 _zPHY_erfc_LittleTabWritePATrigEna
+ 0x100760e5 0x14 _zPHY_erfc_LittleTabWritePATrigLoad
+ 0x100760f9 0x14 _zPHY_erfc_LittleTabWritePATrigDisa
+ 0x1007610d 0x13e _zPHY_erfc_LittleTabWritePaAndVga
+ 0x1007624b 0x49 _zPHY_erfc_SupCheckPAMode
+ 0x10076294 0x1 _zPHY_erfc_RxSinToneTest
+ 0x10076295 0x1 _zPHY_erfc_TxSinToneTest
+ 0x10076296 0x1 _zPHY_erfc_DrvRfNvInit
+ 0x10076297 0x53 _zPHY_erfc_GetRfDCOC_CalVaue
+ .text 0x100762ea 0x204 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100762ea 0x21 _zPHY_erfc_DrvRfcTxSampleRateSet
+ 0x1007630b 0x34 _zPHY_erfc_DrvRfcDfeSampleRateSet
+ 0x1007633f 0x4c _zPHY_erfc_DrvInitMainSyncTable
+ 0x1007638b 0xa5 _zPHY_erfc_DrvInitMeasTable0
+ 0x10076430 0x45 _zPHY_erfc_DrvInitTxSendTable
+ 0x10076475 0x42 _zPHY_erfc_DrvEventTableBoundaryInit
+ 0x100764b7 0xc _zPHY_erfc_IRAM_Set
+ 0x100764c3 0x1a _zPHY_erfc_IRAM_Get
+ 0x100764dd 0x10 _zPHY_erfc_DrvDBBDely
+ 0x100764ed 0x1 _zPHY_erfc_DrvRfTopIntfInit
+ .text 0x100764ee 0xb70 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x100764ee 0x4a _zPHY_edfe_DrvInitInt
+ 0x10076538 0x53 _zPHY_edfe_DrvResetHw
+ 0x1007658b 0x3b _zPHY_edfe_DrvConfigRXBandwidth
+ 0x100765c6 0x3b _zPHY_edfe_DrvConfigCSRMBandwidth
+ 0x10076601 0x1f _zPHY_edfe_DrvGetDCOffsetEsti
+ 0x10076620 0x2c _zPHY_edfe_DrvConfigDCOffset
+ 0x1007664c 0x1f _zPHY_edfe_DrvGetIQEstiSum
+ 0x1007666b 0x1f _zPHY_edfe_DrvGetIQEstiCPSum
+ 0x1007668a 0x30 _zPHY_edfe_DrvConfigIQImbal
+ 0x100766ba 0x6a _zPHY_edfe_DrvConfigAGCPara
+ 0x10076724 0x14 _zPHY_edfe_DrvGetAGCMeanPower
+ 0x10076738 0x12 _zPHY_edfe_DrvGetAGCLFOutVal
+ 0x1007674a 0xa _zPHY_edfe_DrvGetAGCHWGainValue
+ 0x10076754 0xa _zPHY_edfe_DrvCompesateCFO
+ 0x1007675e 0x27 _zPHY_edfe_DrvDcIqParaInit
+ 0x10076785 0x8a _zPHY_edfe_DrvConfigFIRCoeff
+ 0x1007680f 0x50 _zPHY_edfe_DrvConfigDAGCPara
+ 0x1007685f 0x31 _zPHY_edfe_DrvGetDAGCMeanPower
+ 0x10076890 0x12 _zPHY_edfe_DrvGetMbsfnDAGCMeanPower
+ 0x100768a2 0x52 _zPHY_edfe_DrvConfigDAGCSWGainValue
+ 0x100768f4 0x3b _zPHY_edfe_DrvConfigMbsfnRxDAGCSWGainValue
+ 0x1007692f 0x1 _zPHY_edfe_DrvAGCGainConvertTableInit
+ 0x10076930 0x7e _zPHY_edfe_DrvInitDFE
+ 0x100769ae 0x72 _zPHY_edfe_DrvDcIqCfoDagcApplyEn
+ 0x10076a20 0xd0 _zPHY_edfe_DrvRxCPModeConfig
+ 0x10076af0 0x1 _zPHY_edfe_DrvCsrmCPModeConfig
+ 0x10076af1 0x29 _zPHY_edfe_DrvAgcExtModeConfig
+ 0x10076b1a 0x22 _zPHY_edfe_DrvDfeAbbSamplingRateConfig
+ 0x10076b3c 0x1a _zPHY_edfe_DrvMbsfnTwoAgcDagcEn
+ 0x10076b56 0xb _zPHY_edfe_DrvMbsfnTimingOffset
+ 0x10076b61 0x14 _zPHY_edfe_DrvTxCaliConfig
+ 0x10076b75 0x1e _zPHY_edfe_DrvMeasBufferModeComnParaConfig
+ 0x10076b93 0x15 _zPHY_edfe_DrvMeasBufferModeCellParaConfig
+ 0x10076ba8 0x9 _zPHY_edfe_DrvMeasBufferModeRamReadEn
+ 0x10076bb1 0x29 _zPHY_edfe_DrvMeasMode
+ 0x10076bda 0x15 _zPHY_edfe_DrvMeasClock
+ 0x10076bef 0xe _zPHY_edfe_DrvMeasClockClose
+ 0x10076bfd 0x15 _zPHY_edfe_DrvMeasReset
+ 0x10076c12 0x14 _zPHY_edfe_DrvGetMbsfnAGCMeanPower
+ 0x10076c26 0x29 _zPHY_edfe_DrvConfigMbsfnAGCSWGainValue
+ 0x10076c4f 0x14 _zPHY_edfe_DrvLpcSaveRegForCsr
+ 0x10076c63 0x2a _zPHY_edfe_DrvLpcSaveRegForRxCommon
+ 0x10076c8d 0xe8 _zPHY_edfe_DrvLpcResumeRxCommon
+ 0x10076d75 0x3 _zPHY_edfe_DrvLpcResumePower1Public
+ 0x10076d78 0x68 _zPHY_edfe_DrvLpcResumeCsr
+ 0x10076de0 0x20 _zPHY_edfe_DrvLpcResumePower0Public
+ 0x10076e00 0x12 _zPHY_edfe_DrvAgcLenStepConfig
+ 0x10076e12 0xb _zPHY_edfe_DrvDagc2LenStepConfig
+ 0x10076e1d 0x13 _zPHY_edfe_DrvAntModeConfig
+ 0x10076e30 0x26 _zPHY_edfe_DrvAgcIntStateConfig
+ 0x10076e56 0x8 _zPHY_edfe_DrvConfigAgcCalControl
+ 0x10076e5e 0x18 _zPHY_edfe_DrvGetEverySampMeanPower
+ 0x10076e76 0x1 _zPHY_edfe_DrvRfcDfeInterfaceSet
+ 0x10076e77 0x1 _zPHY_edfe_DrvPrsMeasModeComnParaConfig
+ 0x10076e78 0x1 _zPHY_edfe_DrvCsrInputSelect
+ 0x10076e79 0x2 _zPHY_edfe_DrvGetCsrInputSelState
+ 0x10076e7b 0x54 _zPHY_edfe_DrvResetPwr0
+ 0x10076ecf 0xa _zPHY_edfe_DrvDfeIntfSel
+ 0x10076ed9 0x16 _zPHY_edfe_DrvCPAddLenConfig
+ 0x10076eef 0x30 _zPHY_edfe_DrvCsrDDrCatchDataEn
+ 0x10076f1f 0xd _zPHY_edfe_DrvCsrDDrCatchDataStop
+ 0x10076f2c 0x1f _zPHY_edfe_DrvPwr0RestCsrSyncHw
+ 0x10076f4b 0x3c _L1l_DrvDfeCalcNotchParaA
+ 0x10076f87 0x8 _L1l_DrvDfeNotchSetBypass
+ 0x10076f8f 0xa _L1l_DrvDfeNotchSetA_First
+ 0x10076f99 0xa _L1l_DrvDfeNotchSetA_Second
+ 0x10076fa3 0xa _L1l_DrvDfeNotchSetA_Third
+ 0x10076fad 0xc _L1l_DrvDfeNotchSetT_A
+ 0x10076fb9 0xc _L1l_DrvDfeNotchSetT_B
+ 0x10076fc5 0xe _L1l_DrvDfeNotchSetK_A
+ 0x10076fd3 0xe _L1l_DrvDfeNotchSetK_B
+ 0x10076fe1 0xf _zPHY_edfe_DrvEnableDcInt
+ 0x10076ff0 0x5 _zPHY_edfe_ClkPrintf
+ 0x10076ff5 0x69 _zPHY_edfe_LteBuffRegPrint
+ .text 0x1007705e 0x879 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x1007705e 0x2a _zEcsr_CurrentGapTime
+ 0x10077088 0x1d _zEcsr_CurrentGapSuperTime
+ 0x100770a5 0x3c _zEcsr_GetGapStateEx
+ 0x100770e1 0x13 _zEcsr_GetLteGapState
+ 0x100770f4 0x9 _zEcsr_GetGapState
+ 0x100770fd 0x16 _zEcsr_GetIratGapState
+ 0x10077113 0x23 _zEcsr_GapCnt
+ 0x10077136 0x48 _zEcsr_GetLastGapTime
+ 0x1007717e 0x42 _zEcsr_GetGapStartTime
+ 0x100771c0 0x4b _zEcsr_GetNeartGapTime
+ 0x1007720b 0x76 _zEcsr_GetTimeBeforeIratGap
+ 0x10077281 0x42 _zEcsr_GetTimeBeforeGapEx
+ 0x100772c3 0x8 _zEcsr_GetTimeBeforeGap
+ 0x100772cb 0x12 _zEcsr_GetTimeBeforeLteGap
+ 0x100772dd 0x19 _zEcsr_Compare
+ 0x100772f6 0xb _zEcsr_GapTimeCompare
+ 0x10077301 0x7 _zEcsr_TimeCompare
+ 0x10077308 0x40 _zEcsr_BeforeGapHalfFrame
+ 0x10077348 0x40 _zEcsr_AfterGapHalfFrame
+ 0x10077388 0x33 _zEcsr_GetGapOffsetEx
+ 0x100773bb 0x8 _zEcsr_GetGapOffset
+ 0x100773c3 0x60 _zEcsr_GetGapType
+ 0x10077423 0x32 _zEcsr_IsValidGapTime
+ 0x10077455 0x61 _zEcsr_GetGapDistance
+ 0x100774b6 0x89 _zEcsr_GapType
+ 0x1007753f 0x13 _zEcsr_GetLteGapOffset
+ 0x10077552 0x14 _zEcsr_IsAroundGap
+ 0x10077566 0x14 _zEcsr_IsAroundLteGap
+ 0x1007757a 0x54 _zEcsr_CurrentGapType
+ 0x100775ce 0x3d _zEcsr_CurrentGapStartTime
+ 0x1007760b 0x10 _zEcsr_CurrentGapFrame
+ 0x1007761b 0x18 _zEcsr_NextGapFrame
+ 0x10077633 0xd _zEcsr_GapSubFrame
+ 0x10077640 0xe _zEcsr_LteGapGapAvai
+ 0x1007764e 0xc _zEcsr_CurrentGapStartMrtr
+ 0x1007765a 0x19 _zEcsr_CurrentMrtrUpper
+ 0x10077673 0x2a _zEcsr_NextHalfFrame
+ 0x1007769d 0x2d _zEcsr_TimeToMrtr
+ 0x100776ca 0x12 _zEcsr_MrtrToTime
+ 0x100776dc 0xb _zEcsr_TimeToTs
+ 0x100776e7 0x57 _zEcsr_TimeOnGapConfig
+ 0x1007773e 0x1a _zEcsr_TimeInit
+ 0x10077758 0x7 _zPHY_ecsrc_CtrltTime2Ts
+ 0x1007775f 0x1f _zPHY_ecsrc_TimeAdd
+ 0x1007777e 0x25 _zPHY_ecsrc_TimeSub
+ 0x100777a3 0x16 _zPHY_ecsrc_MrtrAddTs
+ 0x100777b9 0x19 _zPHY_ecsrc_MrtrAddSlot
+ 0x100777d2 0x1c _zPHY_ecsrc_MrtrSubTs
+ 0x100777ee 0x1f _zPHY_ecsrc_MrtrSubSlot
+ 0x1007780d 0x2b _zPHY_ecsrc_MrtrAddSignTs
+ 0x10077838 0x24 _zPHY_ecsrc_GetCurTime
+ 0x1007785c 0x18 _zPHY_ecsrc_Mrtr2LocalMrtr
+ 0x10077874 0x18 _zPHY_ecsrc_LocalMrtr2Mrtr
+ 0x1007788c 0x4 _zPHY_ecsrc_RemoveMrtrTs
+ 0x10077890 0x23 _zPHY_ecsrc_MakeMrtr
+ 0x100778b3 0x24 _zPHY_ecsrc_TsToLocalTs
+ .text 0x100778d7 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ 0x100778d7 0x571 _zPHY_erapc_ThreadEntry
+ .text 0x10077e48 0x131f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x10077e48 0xcf _zPHY_ecsrc_InitMeasOnIdle
+ 0x10077f17 0x31 _zPHY_ecsrc_ConfigRfcOffset
+ 0x10077f48 0x96 _zPHY_ecsrc_CtrlCampOnProcess
+ 0x10077fde 0x9a _zPHY_ecsrc_CtrlMeasConfigProcess
+ 0x10078078 0x141 _zPHY_ecsrc_CtrlMeasSetProcess
+ 0x100781b9 0x37 _zPHY_ecsrc_SetMeasAge
+ 0x100781f0 0x7b _L1e_csrc_IdleSetAgeThrold
+ 0x1007826b 0x147 _L1e_csrc_ConnectSetAgeThrold
+ 0x100783b2 0x46 _zPHY_ecsrc_CtrlSetSearchMeasAgeThrold
+ 0x100783f8 0x73 _zPHY_ecsrc_ReadRxMeas
+ 0x1007846b 0x47 _zPHY_ecsrc_ReadServCellRxMeas
+ 0x100784b2 0x23 _zPHY_ecsrc_GetCellMeasReslut
+ 0x100784d5 0x96 _zPHY_ecsrc_CtrlWriteServingCellResult
+ 0x1007856b 0x3d _zPHY_ecsrc_SetMeasResultValue
+ 0x100785a8 0x3c _zPHY_ecsrc_WriteNeibMeasResult
+ 0x100785e4 0x10 _zPHY_ecsrc_CtrlWritePccMeasResult
+ 0x100785f4 0x14d _zPHY_ecsrc_CtrlMeasFilterReq
+ 0x10078741 0x13 _zPHY_ecsrc_ConnAcquireIntraMeas
+ 0x10078754 0x70 _zPHY_ecsrc_AcquireInterMeas
+ 0x100787c4 0x16 _zPHY_ecsrc_AcquireServMeas
+ 0x100787da 0xd _zPHY_ecsrc_ReportMeasReslutIntra
+ 0x100787e7 0x50 _zPHY_ecsrc_ReportMeasReslutInter
+ 0x10078837 0x2b _zPHY_ecsrc_UpdateRsrpKByFlagCounter
+ 0x10078862 0x38 _zPHY_ecsrc_AdaptFilterFactor
+ 0x1007889a 0xb5 _zPHY_ecsrc_FreqFilter
+ 0x1007894f 0x33 _zPHY_ecsrc_FilterNoResult
+ 0x10078982 0x30 _zPHY_ecsrc_DelInvalidCell
+ 0x100789b2 0x9b _zPHY_ecsrc_InterMeasFilter
+ 0x10078a4d 0x72 _zPHY_ecsrc_IntraMeasFilter
+ 0x10078abf 0x69 _zPHY_ecsrc_FilterMeasRank
+ 0x10078b28 0x42 _zPHY_ecsrc_ReportMeasRank
+ 0x10078b6a 0x34 _zPHY_ecsrc_UpdateFreqReport
+ 0x10078b9e 0x7a _zPHY_ecsrc_UpdateIntraReport
+ 0x10078c18 0x9 _zPHY_ecsrc_GetFilterIntraMeasRsrp
+ 0x10078c21 0x70 _zPHY_ecsrc_UpdateInterReport
+ 0x10078c91 0x12 _zPHY_ecsrc_ClearNeibCellRsrp
+ 0x10078ca3 0x1c _zPHY_ecsrc_ClearIntraFilter
+ 0x10078cbf 0x23 _L1e_csrc_SetIdleFilterFactor
+ 0x10078ce2 0x2e _zPHY_ecsrc_SetFilterFactor
+ 0x10078d10 0x62 _zPHY_ecsrc_FilterMeasCfg
+ 0x10078d72 0x4 _zPHY_ecsrc_FilterComnCfg
+ 0x10078d76 0xc _zPHY_ecsrc_InitInterFilter
+ 0x10078d82 0x36 _zPHY_ecsrc_InitInterFilterFreq
+ 0x10078db8 0x60 _zPHY_ecsrc_InitIntraFilter
+ 0x10078e18 0x47 _zPHY_ecsrc_InterMeasIndPrint
+ 0x10078e5f 0x49 _zPHY_ecsrc_CtrlIntraMeasInfoPrint
+ 0x10078ea8 0x37 _zPHY_ecsrc_IntraFilterDebugInfo
+ 0x10078edf 0x4a _zPHY_ecsrc_InterFilterDebugInfo
+ 0x10078f29 0x12 _zPHY_ecsrc_CaSwitch
+ 0x10078f3b 0x78 _zPHY_ecsrc_ProPhy2PsMsgSINRandRSSI
+ 0x10078fb3 0x54 _zPHY_ecsrc_WriteRssiToSearchCnf
+ 0x10079007 0x25 _zPHY_ecsrc_AcquireIntraMeas
+ 0x1007902c 0x41 _zPHY_ecsrc_SrvCellResltDeal
+ 0x1007906d 0x45 _zPHY_ecsrc_ClearAfcInfo
+ 0x100790b2 0x6a _L1e_DevCsrNCellRsNullInd
+ 0x1007911c 0x10 _L1e_DevCsrGetMeasResult
+ 0x1007912c 0x3b _zPHY_ecsrc_CtrlIdleSetInterFilterFact
+ .text 0x10079167 0x21b2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x10079167 0x8 _L1e_Sir_RxMeasMask
+ 0x1007916f 0x8 _L1e_Sir_QuryRxMeasMask
+ 0x10079177 0x27f _L1e_Sir_MainCtrlFlow
+ 0x100793f6 0x33 _L1e_Sir_DbReset
+ 0x10079429 0x31 _L1e_Sir_LpcAndTurboCtrl
+ 0x1007945a 0x30 _L1e_Sir_AddTpuEvt
+ 0x1007948a 0x28 _L1e_Sir_DelAllTpuEvt
+ 0x100794b2 0x26 _L1e_Sir_QueryTpuEvt
+ 0x100794d8 0x33 _L1e_Sir_DelTpuEvt
+ 0x1007950b 0x4a _L1e_Sir_RegDelayEvt
+ 0x10079555 0x21 _L1e_Sir_PreProc
+ 0x10079576 0x8 _L1e_Sir_MainState
+ 0x1007957e 0x8 _L1e_Sir_StepState
+ 0x10079586 0x8 _L1e_Sir_SyncState
+ 0x1007958e 0x19 _L1e_Sir_CommInSiProc
+ 0x100795a7 0x34 _L1e_Sir_SetState
+ 0x100795db 0x98 _L1e_Sir_UpSib1Para
+ 0x10079673 0x75 _L1e_Sir_UpSiPara
+ 0x100796e8 0x15 _L1e_Sir_UpSerPara
+ 0x100796fd 0x2d _L1e_Sir_UpDecPara
+ 0x1007972a 0x8 _L1e_Sir_UpDecState
+ 0x10079732 0xd _L1e_Sir_QurySerSir
+ 0x1007973f 0xc _L1e_Sir_QurySib1State
+ 0x1007974b 0xd _L1e_Sir_QurySiState
+ 0x10079758 0x1a _L1e_Sir_QueryRptEn
+ 0x10079772 0x14 _L1e_Sir_CtrlDecOps
+ 0x10079786 0x23 _L1e_Sir_UpSibWin
+ 0x100797a9 0x56 _L1e_Sir_StopSibProc
+ 0x100797ff 0x4e _L1e_Sir_UpSchedPara
+ 0x1007984d 0x96 _L1e_Sir_StartSib1
+ 0x100798e3 0x71 _L1e_Sir_BchSync
+ 0x10079954 0x5c _L1e_Sir_RestartBch
+ 0x100799b0 0xcc _L1e_Sir_StartSi
+ 0x10079a7c 0xb7 _L1e_Sir_AbortSi
+ 0x10079b33 0x64 _L1e_Sir_SchedSib1
+ 0x10079b97 0xd4 _L1e_Sir_SchedSi
+ 0x10079c6b 0xcb _L1e_Sir_ProcDecSucc
+ 0x10079d36 0xd0 _L1e_Sir_BackSerCell
+ 0x10079e06 0x2c _L1e_Sir_DataReport
+ 0x10079e32 0x92 _L1e_Sir_SndMibReq
+ 0x10079ec4 0x39 _L1e_Sir_SndMibCnf
+ 0x10079efd 0x19 _L1e_Sir_SndBchFail
+ 0x10079f16 0x7d _L1e_Sir_QueryMib
+ 0x10079f93 0x2e _L1e_Sir_ProBchHandle
+ 0x10079fc1 0x43 _L1e_Sir_QueryCell
+ 0x1007a004 0x15 _L1e_Sir_CtrlAgcState
+ 0x1007a019 0x40 _L1e_Sir_UpRfcCfg
+ 0x1007a059 0x7 _L1e_Sir_CalBoundryTs
+ 0x1007a060 0x81 _L1e_Sir_DelyTpuAdjust
+ 0x1007a0e1 0x60 _L1e_Sir_TpuMacroAdjust
+ 0x1007a141 0x2 _L1e_Sir_SndTpuAdjust
+ 0x1007a143 0x8f _L1e_Sir_StartWinEvtCB
+ 0x1007a1d2 0x60 _L1e_Sir_EndWinEvtCB
+ 0x1007a232 0x32 _L1e_Sir_RegWindowEvt
+ 0x1007a264 0x9e _L1e_Sir_CalNearRxRcv
+ 0x1007a302 0x5a _L1e_Sir_CheckRxRcv
+ 0x1007a35c 0x39 _L1e_Sir_CellSync
+ 0x1007a395 0x3d _L1e_Sir_CheckPaging
+ 0x1007a3d2 0x7d _L1e_Sir_CheckGapPos
+ 0x1007a44f 0x5e _L1e_Sir_SerCellBackProc
+ 0x1007a4ad 0x7 _L1e_Sir_SetAbortSiProcState
+ 0x1007a4b4 0x7 _L1e_Sir_GetAbortSiProcState
+ 0x1007a4bb 0x7 _L1e_Sir_SetSiDelayProcState
+ 0x1007a4c2 0x7 _L1e_Sir_GetSiDelayProcState
+ 0x1007a4c9 0x7 _L1e_Sir_SetTimingNeibState
+ 0x1007a4d0 0x7 _L1e_Sir_GetTimingNeibState
+ 0x1007a4d7 0x10 _L1e_Sir_GetMibReadStateInSib
+ 0x1007a4e7 0x13 _L1e_Sir_GetSibState
+ 0x1007a4fa 0x68 _L1e_Sir_GetNextSiWinTime
+ 0x1007a562 0x1a _L1e_Sir_GetNeiBorSiState
+ 0x1007a57c 0x1e _L1e_Sir_GetNeiBorSibState
+ 0x1007a59a 0x2d _L1e_Sir_GetNeiBorSib1ReportState
+ 0x1007a5c7 0x1c _L1e_Sir_GetSerSibState
+ 0x1007a5e3 0x12 _L1e_Sir_GetNeiBorSiBackState
+ 0x1007a5f5 0xd _L1e_Sir_CleanSiPreSyncState
+ 0x1007a602 0x8 _L1e_Sir_GetSiSubFrmPat
+ 0x1007a60a 0xb9 _L1e_Sir_PreSyncProc
+ 0x1007a6c3 0x80 _L1e_Sir_PreSyncSched
+ 0x1007a743 0x7 _L1e_Sir_SetSiSyncState
+ 0x1007a74a 0x7 _L1e_Sir_GetSiSyncState
+ 0x1007a751 0x7 _L1e_Sir_SetSiSyncSchedState
+ 0x1007a758 0x7 _L1e_Sir_GetSiSyncSchedState
+ 0x1007a75f 0x28 _L1e_Sir_SiWakeUpProc
+ 0x1007a787 0x12 _L1e_Sir_GetBandWidth
+ 0x1007a799 0xc5 _L1e_Sir_StartAnr
+ 0x1007a85e 0x8 _L1e_Anr_QueryEn
+ 0x1007a866 0x8 _L1e_Anr_GetState
+ 0x1007a86e 0x8 _L1e_Anr_ProcIndGet
+ 0x1007a876 0x1f _L1e_Anr_SetState
+ 0x1007a895 0x2fd _L1e_Anr_SubFrmProc
+ 0x1007ab92 0x1c _L1e_Anr_BchProc
+ 0x1007abae 0x6 _L1e_Anr_BchBackSerRx
+ 0x1007abb4 0x19 _L1e_Anr_AbortSi
+ 0x1007abcd 0x2f _L1e_Anr_Reset
+ 0x1007abfc 0x11 _L1e_Anr_ProcDecSucc
+ 0x1007ac0d 0x7e _L1e_Anr_NeibLocalMrtr
+ 0x1007ac8b 0xc1 _L1e_Anr_SwitchRF
+ 0x1007ad4c 0x1a _L1e_Anr_GetAutoGapState
+ 0x1007ad66 0x49 _L1e_Anr_TpuMacroAdjust
+ 0x1007adaf 0xe _L1e_Anr_EnableRxRcv
+ 0x1007adbd 0x6e _L1e_Anr_CalNeibTime
+ 0x1007ae2b 0x2 _L1e_Anr_BchAbortProc
+ 0x1007ae2d 0xd _L1e_Anr_SibAbortProc
+ 0x1007ae3a 0x2c _L1e_Sir_Sib1MsgMonitor
+ 0x1007ae66 0x59 _L1e_Sir_SiMsgMonitor
+ 0x1007aebf 0x29 _L1e_Sir_SibReportMonitor
+ 0x1007aee8 0x2c _L1e_Sir_StateMonitor
+ 0x1007af14 0x2f _L1e_Sir_ErrMonitor
+ 0x1007af43 0x5c _L1e_Sir_RfcMonitor
+ 0x1007af9f 0x93 _L1e_Sir_CellMonitor
+ 0x1007b032 0x38 _L1e_Sir_SibParaMonitor
+ 0x1007b06a 0x43 _L1e_Sir_MibCnfMonitor
+ 0x1007b0ad 0x2c _L1e_Sir_RxRcvCtrlMonitor
+ 0x1007b0d9 0x5b _L1e_Sir_SchedParaMonitor
+ 0x1007b134 0x6e _L1e_Sir_StartWinMonitor
+ 0x1007b1a2 0x6e _L1e_Sir_EndWinMonitor
+ 0x1007b210 0x24 _L1e_Sir_AnrStateMonitor
+ 0x1007b234 0x51 _L1e_Anr_StartMonitor
+ 0x1007b285 0x34 _L1e_Sir_AnrRfcMonitor
+ 0x1007b2b9 0x32 _L1e_Anr_GapPrintf
+ 0x1007b2eb 0x2e _L1e_Anr_ErrProcMonitor
+ .text 0x1007b319 0x3fde T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x1007b319 0x27 _zPHY_emc_DvfsPatch
+ 0x1007b340 0x12 _zPHY_emc_PsMsgIdFindIndex
+ 0x1007b352 0x12 _zPHY_emc_PhyMsgIdFindIndex
+ 0x1007b364 0x12 _zPHY_emc_FindSynMsgIndex
+ 0x1007b376 0x12 _zPHY_emc_FindEmpLoc
+ 0x1007b388 0xf _zPHY_emc_FindAllSyncMsg
+ 0x1007b397 0x26 _zPHY_emc_ClearSyncMsg
+ 0x1007b3bd 0x131 _zPHY_emc_ReadSyncMsg
+ 0x1007b4ee 0x55 _zPHY_emc_StubRecvSyncMsg
+ 0x1007b543 0x1a _zPHY_emc_GetPs2PhyCF
+ 0x1007b55d 0x3a _zPHY_emc_LteAmtUpdateServeCellEarfch
+ 0x1007b597 0x8 _l1e_SchedMcIdlePiCnt
+ 0x1007b59f 0x17b _zPHY_emc_ProInitial
+ 0x1007b71a 0x11 _memcpy_Ps2PhySram
+ 0x1007b72b 0x35 _zPHY_emc_ProPs2PhyMsgLog
+ 0x1007b760 0x5a _zPHY_emc_ProPhy2PsMsgLog
+ 0x1007b7ba 0x6b8 _zPHY_emc_ProSyncMsgSend
+ 0x1007be72 0x27e _zPHY_emc_ProDedicatedMsg
+ 0x1007c0f0 0x1a1 _zPHY_emc_ProPs2PhySyncMsg
+ 0x1007c291 0x41 _zPHY_emc_ProAbortAccessMsg
+ 0x1007c2d2 0x1ad _zPHY_emc_ProAccessMsg
+ 0x1007c47f 0x5 _zPHY_emc_ProTaCmdMsg
+ 0x1007c484 0x12 _zPHY_emc_ProTaTimeStopMsg
+ 0x1007c496 0x24e _zPHY_emc_ProPs2PhyMsgRouter
+ 0x1007c6e4 0x2c _zPHY_emc_WakeUpPS
+ 0x1007c710 0x1c _zPHY_emc_SendIcpToPS
+ 0x1007c72c 0xd5 _zPHY_emc_ProPhy2PsMsgRouter
+ 0x1007c801 0x275 _zPHY_emc_ProReleaseFlow
+ 0x1007ca76 0x1a8 _zPHY_emc_ProTimingCtrlFlow
+ 0x1007cc1e 0x1fd _zPHY_emc_ProTASchedFlow
+ 0x1007ce1b 0x46 _zPHY_emc_ProMacResetFlow
+ 0x1007ce61 0x57 _zPHY_emc_ProSubfrmTypeConfig
+ 0x1007ceb8 0x20d _zPHY_emc_ProResetFlow
+ 0x1007d0c5 0x207 _zPHY_emc_ProSetModeFlow
+ 0x1007d2cc 0x2b _zPHY_emc_ProShowLtePhyStateInfo
+ 0x1007d2f7 0x58 _zPHY_emc_ProShowLtePhySIDInfo
+ 0x1007d34f 0x11b _zPHY_emc_ProAfcConfig
+ 0x1007d46a 0x14 _zPHY_emc_UpdateIniFreq
+ 0x1007d47e 0x12 _zPHY_emc_ReadIniFreq
+ 0x1007d490 0x53 _zPHY_emc_StartGapDelayPro
+ 0x1007d4e3 0x63 _zPHY_emc_GetRfTpuRegTime
+ 0x1007d546 0x25 _zPHY_emc_RegEvent
+ 0x1007d56b 0x13 _zPHY_emc_DelEvent
+ 0x1007d57e 0x40 _zPHY_emc_RfDeal
+ 0x1007d5be 0xb _zPHY_emc_ResetProOn
+ 0x1007d5c9 0xb _zPHY_emc_RelProOn
+ 0x1007d5d4 0x15 _zPHY_emc_InitScellInfo
+ 0x1007d5e9 0x1 _zPHY_emc_ModifyScellExistFlag
+ 0x1007d5ea 0x1 _zPHY_emc_ModifyScellActiveFlag
+ 0x1007d5eb 0x1d _zPHY_emc_InitScellDefaultPara
+ 0x1007d608 0x21 _zPHY_emc_ScellRatModeSet
+ 0x1007d629 0x10 _zPHY_emc_FindFreeSCarrier
+ 0x1007d639 0x10 _zPHY_emc_AddSCarrier
+ 0x1007d649 0x29 _zPHY_emc_ReleaseSCarrier
+ 0x1007d672 0x41 _zPHY_emc_ModifyScellInfo
+ 0x1007d6b3 0x2 _zPHY_emc_ActiveScell
+ 0x1007d6b5 0x2 _zPHY_emc_DeactiveScell
+ 0x1007d6b7 0x2 _zPHY_emc_AutoDeactiveScell
+ 0x1007d6b9 0x2 _zPHY_emc_UpdateDeactInfo
+ 0x1007d6bb 0xa _zPHY_emc_IsAnyScellExist
+ 0x1007d6c5 0xa _zPHY_emc_IsAnyScellActive
+ 0x1007d6cf 0x2 _zPHY_emc_IsScellExist
+ 0x1007d6d1 0x2 _zPHY_emc_IsScellActive
+ 0x1007d6d3 0x2 _zPHY_emc_ReadScellCfgDedi
+ 0x1007d6d5 0x2 _zPHY_emc_ReadScellCfgComn
+ 0x1007d6d7 0x11 _zPHY_emc_ReadScellBasicInfo
+ 0x1007d6e8 0x23 _zPHY_emc_ReadFixDlDelay
+ 0x1007d70b 0x4e _zPHY_emc_SetSysband
+ 0x1007d759 0x52 _zPHY_emc_AlterRateRefreshFB
+ 0x1007d7ab 0x44 _L1e_Anr_AlterRateRefreshFB
+ 0x1007d7ef 0x1e _zPHY_emc_CfgSysband
+ 0x1007d80d 0x1c _zPHY_emc_IsSysbandVarious
+ 0x1007d829 0x19 _zPHY_emc_ReadGapStatue
+ 0x1007d842 0x1f _zPHY_emc_ReadIratGapStatue
+ 0x1007d861 0x15 _zPHY_emc_RfcRbdpCfg
+ 0x1007d876 0x76 _zPHY_emc_ProGapDelayFlow
+ 0x1007d8ec 0x153 _zPHY_emc_ProGapSchedFlow
+ 0x1007da3f 0x2f _zPHY_emc_ScellActiveNoactiveMain
+ 0x1007da6e 0xe _L1e_SchedMcSetSCellDeactivationTimerParam
+ 0x1007da7c 0x7 _L1e_SchedMcGetSCellDeactivationTimerParam
+ 0x1007da83 0x9 _L1e_SchedMcSetSCellDeactivationTimer
+ 0x1007da8c 0xc _L1e_SchedMcIncSCellDeactivationTimer
+ 0x1007da98 0x9 _L1e_SchedMcGetSCellDeactivationTimer
+ 0x1007daa1 0x35 _L1e_SchedMcAutoDeactiveScc
+ 0x1007dad6 0x34 _L1e_SchedMcDeactiveScc
+ 0x1007db0a 0x8f _zPHY_emc_ScellGetRFPara
+ 0x1007db99 0x45 _L1e_SchedMc_CfgUlFreqPoint
+ 0x1007dbde 0x3d _zPHY_emc_ScellRFParaPrint
+ 0x1007dc1b 0x45 _L1e_LogMcSCellInfo
+ 0x1007dc60 0x1d _L1e_SchedMc_ConvertBW
+ 0x1007dc7d 0x86 _L1e_SchedMc_CloseRxRecv
+ 0x1007dd03 0x20 _zPHY_emc_ProClrRfcDBState
+ 0x1007dd23 0x135 _L1e_SchedMc_CfgRfcRxSFData
+ 0x1007de58 0xd _L1e_SchedMc_GetRxRecvState
+ 0x1007de65 0xd _L1e_SchedMc_GetCalcTimeState
+ 0x1007de72 0xd _L1e_SchedMc_GetCfgSrcIdx
+ 0x1007de7f 0x32 _L1e_SchedMc_OpenRxRecv
+ 0x1007deb1 0xc1 _L1e_SchedMc_CalcRxRecvTime
+ 0x1007df72 0x1a _L1e_SchedMc_CalcRxCloseTime
+ 0x1007df8c 0xb9 _L1e_SchedMc_OpenRxRF
+ 0x1007e045 0x147 _L1e_SchedMc_OpenRxRFByCc
+ 0x1007e18c 0x30 _L1e_SchedMc_JudgeRfOpenTime
+ 0x1007e1bc 0x1e _L1e_SchedMc_JudgeRfClose
+ 0x1007e1da 0x16 _L1e_SchedMc_Set4RxRcv
+ 0x1007e1f0 0x8 _L1e_SchedMc_Clr4RxRcv
+ 0x1007e1f8 0x7 _L1e_SchedMc_Get4RxRcv
+ 0x1007e1ff 0x1a _L1e_SchedMc_CfgRfcRxClose
+ 0x1007e219 0x17c _zPHY_emc_SetAndReadPhyPara
+ 0x1007e395 0x8 _zPHY_emc_AsynMsgProcIratGapConfigReq
+ 0x1007e39d 0x9f _zPHY_emc_RdPs2PhyAsyncMsg
+ 0x1007e43c 0x63 _zPHY_emc_CalTpuMrtrAdjType
+ 0x1007e49f 0x48 _zPHY_emc_RefreshPagePara
+ 0x1007e4e7 0x1b _zPHY_SendMsg
+ 0x1007e502 0x1c _zPHY_SendNullMsg
+ 0x1007e51e 0x62 _L1e_SchedMcGetCellInfo
+ 0x1007e580 0xd _L1e_SchedMc_AbortSi
+ 0x1007e58d 0xd _L1e_SchedMc_AbortSearch
+ 0x1007e59a 0xd _L1e_SchedMc_StoreSib
+ 0x1007e5a7 0xd _L1e_SchedMc_StoreSi
+ 0x1007e5b4 0x8 _L1e_SchedMc_SetDelayAnrState
+ 0x1007e5bc 0x8 _L1e_SchedMc_GetDelayAnrState
+ 0x1007e5c4 0xd _L1e_SchedMc_StoreSearch
+ 0x1007e5d1 0xd _L1e_SchedMc_StoreFreqScan
+ 0x1007e5de 0xd _L1e_SchedMc_StoreRapc
+ 0x1007e5eb 0x3b _L1e_SchedMc_SndDelaySearch
+ 0x1007e626 0x3c _L1e_SchedMc_SendDelayFreqScan
+ 0x1007e662 0x1a _L1e_SchedMc_SndDelaySib
+ 0x1007e67c 0x1a _L1e_SchedMc_SndDelaySi
+ 0x1007e696 0x10 _L1e_SchedMc_SndDelayRapc
+ 0x1007e6a6 0x1e _L1e_SchedMc_ReadTpuOffset
+ 0x1007e6c4 0x10 _zPHY_emc_ATSetDrxCtrl
+ 0x1007e6d4 0x83 _zPHY_emc_ATSetAndReadRlm
+ 0x1007e757 0x65 _zPHY_emc_ATSetAndReadCsi
+ 0x1007e7bc 0xc5 _zPHY_emc_ATSetAndReadUlpc
+ 0x1007e881 0x72 _zPHY_emc_ATSetAntenna
+ 0x1007e8f3 0x56 _zPHY_emc_ATSetAndReadUeCategory
+ 0x1007e949 0x21 _zPHY_emc_ATCheckSinr
+ 0x1007e96a 0x20 _zPHY_emc_ATCheckTmMode
+ 0x1007e98a 0x4f _zPHY_emc_ATCheckMcsQmod
+ 0x1007e9d9 0x6e _zPHY_emc_ATCheckHarqNack
+ 0x1007ea47 0x32 _zPHY_emc_ATCheckThrougput
+ 0x1007ea79 0x1f _zPHY_emc_ATCheckRssi
+ 0x1007ea98 0x32 _zPHY_emc_ATCheckSinrRsrp
+ 0x1007eaca 0x2a _zPHY_emc_ATCheckResidualBler
+ 0x1007eaf4 0x8a _zPHY_emc_ATCheckAll
+ 0x1007eb7e 0x1f _zPHY_emc_ATThinkWill
+ 0x1007eb9d 0x2b _zPHY_emc_ATLowPower
+ 0x1007ebc8 0x3d _zPHY_emc_ExtraCheck
+ 0x1007ec05 0x6f2 _zPHY_emc_ThreadEntry
+ .text 0x1007f2f7 0x542f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x1007f2f7 0x16 _zPHY_ecsrc_LteAmtUpdateServeCellEarfch
+ 0x1007f30d 0x35 _zPHY_ecsrc_ReadEarfcnInfo
+ 0x1007f342 0x3a _zPHY_ecsrc_GetDLULEarfchTableInfo
+ 0x1007f37c 0x52 _zPHY_ecsrc_GetEarfchTableInfo
+ 0x1007f3ce 0x11 _zPHY_ecsrc_SchedEarfcn2Freq
+ 0x1007f3df 0x14 _zPHY_ecsrc_SchedFreq2Earfcn
+ 0x1007f3f3 0x2e _zPHY_ecsrc_FindEarfchFromEarfcn
+ 0x1007f421 0x58 _zPHY_ecsrc_GetUlEarfchTableInfo
+ 0x1007f479 0x19 _zPHY_ecsrc_GetTddFddMode
+ 0x1007f492 0x13 _zPHY_ecsrc_CtrlRsrpTrans
+ 0x1007f4a5 0x12 _zPHY_ecsrc_CtrlRsrqTrans
+ 0x1007f4b7 0xc _zPHY_ecsrc_NvReadRsrpFixedOffset
+ 0x1007f4c3 0x36 _zPHY_ecsrc_SendSearchStartReq
+ 0x1007f4f9 0x37 _zPHY_ecsrc_SendCfoStartReq
+ 0x1007f530 0x8f _zPHY_ecsrc_SendMeasStartReq
+ 0x1007f5bf 0x24 _zPHY_ecsrc_SendHandoverCnf
+ 0x1007f5e3 0x51 _zPHY_ecsrc_SendMibReadReq
+ 0x1007f634 0x2c _zPHY_ecsrc_SendTpuMacroAdjReq
+ 0x1007f660 0x2c _zPHY_ecsrc_SendFreqScanReq
+ 0x1007f68c 0xd _zPHY_ecsrc_OnSendFreqScanReq
+ 0x1007f699 0x8 _zPHY_ecsrc_SetAllRxMaskFlag
+ 0x1007f6a1 0x11 _zPHY_ecsrc_SleepCtrlPowerOn
+ 0x1007f6b2 0x13 _L1e_csrc_InitStrInfo
+ 0x1007f6c5 0xec _zPHY_ecsrc_ProInitial
+ 0x1007f7b1 0x11 _zPHY_ecsrc_InitSlaveWorkState
+ 0x1007f7c2 0x13 _zPHY_ecsrc_ProReset
+ 0x1007f7d5 0x15 _zPHY_ecsrc_SetPhyModeByEarfcn
+ 0x1007f7ea 0x10 _zPHY_emc_SetPhyMode
+ 0x1007f7fa 0x14 _zPHY_ecsrc_FindTpuEvent
+ 0x1007f80e 0x40 _zPHY_ecsrc_TpuEventReset
+ 0x1007f84e 0x3a _zPHY_ecsrc_TpuEventMark
+ 0x1007f888 0x1b _zPHY_ecsrc_TpuEventCheck
+ 0x1007f8a3 0x4c _zPHY_ecsrc_DelTpuEvent
+ 0x1007f8ef 0x1c _zPHY_ecsrc_TpuEventClean
+ 0x1007f90b 0x7 _zPHY_ecsrc_FilterEnDelay
+ 0x1007f912 0x22 _zPHY_ecsrc_GetBandIdx
+ 0x1007f934 0x2b _zPHY_ecsrc_MibInfoOutput
+ 0x1007f95f 0x23 _zPHY_ecsrc_FilterOut
+ 0x1007f982 0x62 _zPHY_ecsrc_CtrlReleaseProcess
+ 0x1007f9e4 0x69 _zPHY_ecsrc_CfgRfcFreqBand
+ 0x1007fa4d 0x1c _L1e_csrc_CfgSysband
+ 0x1007fa69 0x2d _zPHY_ecsrc_RecoverToServingFreq
+ 0x1007fa96 0x1c _zPHY_ecsrc_ResetSearchMeas
+ 0x1007fab2 0x71 _zPHY_ecsrc_StopInterSearchMeas
+ 0x1007fb23 0x40 _L1e_csrc_PreWakeUpPS
+ 0x1007fb63 0x18 _zPHY_ecsrc_TsDelayMsgRegister
+ 0x1007fb7b 0x34 _zPHY_ecsrc_DelayMsgRegister
+ 0x1007fbaf 0x4d _zPHY_ecsrc_RegTpuAdjDelay
+ 0x1007fbfc 0x11a _zPHY_ecsrc_CtrlConnectedIntraReportEvent
+ 0x1007fd16 0x4a _zPHY_ecsrc_CtrlConnectedInterReportEvent
+ 0x1007fd60 0x38 _zPHY_ecsrc_CtrlConnectAgingProcess
+ 0x1007fd98 0x17 _zPHY_ecsrc_CfgRfcSynState
+ 0x1007fdaf 0x37 _zPHY_ecsrc_GetInterReportPeriod
+ 0x1007fde6 0x88 _zPHY_ecsrc_CtrlConnectedMeasSchedule
+ 0x1007fe6e 0x31 _zPHY_ecsrc_OpenSubFrameInt
+ 0x1007fe9f 0x15 _zPHY_ecsrc_DelSfInt
+ 0x1007feb4 0x18 _zPHY_ecsrc_InitGapCnt
+ 0x1007fecc 0x19 _zPHY_ecsrc_UpdateGapCnt
+ 0x1007fee5 0x3d _zPHY_ecsrc_DrxRefreshGapCnt
+ 0x1007ff22 0x48 _zPHY_ecsrc_DrxSetIntraWorkPeriod
+ 0x1007ff6a 0x80 _zPHY_ecsrc_DrxSetInterWorkPeriod
+ 0x1007ffea 0x13 _zPHY_ecsrc_DrxSetInterRprtPeriod
+ 0x1007fffd 0x8d _L1e_csrc_RegConEvent
+ 0x1008008a 0x77 _zPHY_ecsrc_CtrlDedicateConfigProcess
+ 0x10080101 0x48 _zPHY_ecsrc_CtrlConncetGapConfigProcess
+ 0x10080149 0x100 _zPHY_ecsrc_CtrlConnectedSetInterFreq
+ 0x10080249 0xa6 _zPHY_ecsrc_CtrlConnectedScheduleInterFreq
+ 0x100802ef 0xc7 _zPHY_ecsrc_CtrlHandoverSearch
+ 0x100803b6 0x25 _zPHY_ecsrc_CtrlHandoverCfoEn
+ 0x100803db 0x1f _zPHY_ecsrc_CtrlHandoverMibInd
+ 0x100803fa 0x112 _zPHY_ecsrc_CtrlHandoverPro
+ 0x1008050c 0x114 _zPHY_ecsrc_CtrlHandoverSearchTimeEvent
+ 0x10080620 0x49 _zPHY_ecsrc_CtrlHandoverPbchTimeEvent
+ 0x10080669 0x38 _zPHY_ecsrc_LteAmtULEarfchTableInfo
+ 0x100806a1 0x38 _zPHY_ecsrc_LteAmtDLEarfchTableInfo
+ 0x100806d9 0x3a _zPHY_ecsrc_LteAmtFDTEarfchTableInfo
+ 0x10080713 0x86 _zPHY_ecsrc_AmtUpdateEarfcnBand
+ 0x10080799 0x2d _zPHY_ecsrc_RegDrxNoUseEvent
+ 0x100807c6 0x24 _zPHY_ecsrc_DelDrxNoUseEvent
+ 0x100807ea 0xc _zPHY_ecsrc_IsDrxUsed
+ 0x100807f6 0x29 _zPHY_ecsrc_IsWorkGap
+ 0x1008081f 0x34 _zPHY_ecsrc_WaitIratGap
+ 0x10080853 0x42 _zPHY_ecsrc_IntraFreqEnable
+ 0x10080895 0x5e _zPHY_ecsrc_InterFreqEnable
+ 0x100808f3 0xb8 _zPHY_ecsrc_CalIntraWorkTime
+ 0x100809ab 0x4d _zPHY_ecsrc_SetSearchPhase
+ 0x100809f8 0x4c _zPHY_ecsrc_GetSearchPhase
+ 0x10080a44 0x1b _zPHY_ecsrc_ClearSearchEnable
+ 0x10080a5f 0x49 _zPHY_ecsrc_FindEnableFreq
+ 0x10080aa8 0x3a _zPHY_ecsrc_UpdateSearchEnable
+ 0x10080ae2 0x2f _zPHY_ecsrc_IsSearchDone
+ 0x10080b11 0x4b _zPHY_ecsrc_RecoverEnableFlag
+ 0x10080b5c 0x90 _zPHY_ecsrc_CalRemainTime
+ 0x10080bec 0x1cf _zPHY_ecsrc_FindUndoneFreq
+ 0x10080dbb 0x1b _L1e_csrc_FindEnableInterFreq
+ 0x10080dd6 0x1d5 _L1e_csrc_FindUndoFreq
+ 0x10080fab 0x6c _L1e_csrc_DrxIntraReport
+ 0x10081017 0x4e _L1e_csrc_DrxInterReport
+ 0x10081065 0xb7 _L1e_csrc_DrxSchdEnd
+ 0x1008111c 0x3b _L1e_csrc_DrxIntraSchd
+ 0x10081157 0x42 _L1e_csrc_DrxInterSchd
+ 0x10081199 0x6e _L1e_csrc_ShortDrxIntraSchd
+ 0x10081207 0x40 _L1e_csrc_ShortDrxInterSchd
+ 0x10081247 0x49 _L1e_csrc_AbortDrxSchd
+ 0x10081290 0x15 _L1e_csrc_CsrIsWork
+ 0x100812a5 0x127 _zPHY_ecsrc_DrxCheckEvent
+ 0x100813cc 0x8 _L1e_csrc_GetStopMeas
+ 0x100813d4 0xe _L1e_csrc_CfgGapCnt
+ 0x100813e2 0xca _L1e_csrc_ShortDrxSchd
+ 0x100814ac 0x30 _L1e_csrc_ShortDrxReSchd
+ 0x100814dc 0x104 _zPHY_ecsrc_CnnDrxStartSchedule
+ 0x100815e0 0x48 _zPHY_ecsrc_CnnDrxSetup
+ 0x10081628 0x1b _zPHY_ecsrc_CnnDrxRelease
+ 0x10081643 0x41 _L1e_csrc_ShortDrxSchdFlag
+ 0x10081684 0x8 _L1e_csrc_GetDfeValidFlag
+ 0x1008168c 0x87 _zPHY_ecsrc_CtrlAbortMeasProcess
+ 0x10081713 0x8 _zPHY_ecsrc_ReadSubframeOffset
+ 0x1008171b 0x15 _zPHY_ecsrc_SubframeOffsetToRfc
+ 0x10081730 0x8 _zPHY_ecsrc_SetFddAdjust
+ 0x10081738 0x30 _zPHY_ecsrc_ClearRfcSFData
+ 0x10081768 0x12 _zPHY_ecsrc_ClearRfTable
+ 0x1008177a 0x12 _L1e_csrc_ClearRfMeasState
+ 0x1008178c 0x2c _zPHY_ecsrc_SetFreq
+ 0x100817b8 0xa _zPHY_ecsrc_SetInterFreq
+ 0x100817c2 0x15 _zPHY_ecsrc_FindEvent
+ 0x100817d7 0x43 _zPHY_ecsrc_RegisterEvent
+ 0x1008181a 0x1d _zPHY_ecsrc_CancelEvent
+ 0x10081837 0x12 _zPHY_ecsrc_CancelAllEvent
+ 0x10081849 0x7b _zPHY_ecsrc_CheckEvent
+ 0x100818c4 0x40 _zPHY_ecsrc_ConnCheckEvent
+ 0x10081904 0x44 _zPHY_ecsrc_ExcuteEvent
+ 0x10081948 0x25 _zPHY_ecsrc_ChangeIntraReportPeriod
+ 0x1008196d 0x33 _zPHY_ecsrc_ChangeIntraReportPeriodDrx
+ 0x100819a0 0x7 _zPHY_ecsrc_OnSetMode
+ 0x100819a7 0x25 _zPHY_ecsrc_OnIratIdlePeriodRepReq
+ 0x100819cc 0x37 _zPHY_ecsrc_OnInactiveTimeReportInt
+ 0x10081a03 0x19 _zPHY_ecsrc_OnFreqListConfigReq
+ 0x10081a1c 0x2e _zPHY_ecsrc_OnIratMeasConfigReq
+ 0x10081a4a 0x32 _zPHY_ecsrc_OnIratMeasReportInt
+ 0x10081a7c 0xf1 _zPHY_ecsrc_OnIratGapConfigReq
+ 0x10081b6d 0x6f _zPHY_ecsrc_OnIratGapConfigDelayInt
+ 0x10081bdc 0x24 _zPHY_ecsrc_OnRfStartDealSfInt
+ 0x10081c00 0x14 _zPHY_ecsrc_OnRfCloseDealSfInt
+ 0x10081c14 0x37 _zPHY_ecsrc_OnReset
+ 0x10081c4b 0x4e _zPHY_ecsrc_OnCellSearchReq
+ 0x10081c99 0x39 _zPHY_ecsrc_InitOnCellSearchReq
+ 0x10081cd2 0xae _zPHY_ecsrc_CtrlAppointSearchPbchTimeEvent
+ 0x10081d80 0x52 _zPHY_ecsrc_CtrlAppointSearchTimeEvent
+ 0x10081dd2 0x2a _zPHY_ecsrc_CtrlAppointSearchPbchEndEvent
+ 0x10081dfc 0xd _zPHY_ecsrc_AppointCellSearchType
+ 0x10081e09 0x17 _zPHY_ecsrc_NeibCellSearchType
+ 0x10081e20 0x99 _zPHY_ecsrc_IdleOnCellSearchReq
+ 0x10081eb9 0x16 _zPHY_ecsrc_SlaveOnCellSearchReq
+ 0x10081ecf 0x1a _zPHY_ecsrc_OnCtrlIniSearchCnf
+ 0x10081ee9 0x19 _zPHY_ecsrc_OnTimeDelayInt
+ 0x10081f02 0x19 _zPHY_ecsrc_OnSssUpdateCounterCnf
+ 0x10081f1b 0xd _zPHY_ecsrc_OnIniMeasTimeEvent
+ 0x10081f28 0x1c _zPHY_ecsrc_OnAbortCellSearchReq
+ 0x10081f44 0x27 _zPHY_ecsrc_OnCommonConfigReq
+ 0x10081f6b 0x4e _zPHY_ecsrc_OnMeasConfigReq
+ 0x10081fb9 0x132 _zPHY_ecsrc_SaveMask
+ 0x100820eb 0x98 _zPHY_ecsrc_OnMeasMaskSetReq
+ 0x10082183 0x30 _zPHY_ecsrc_OnAbortMeasReq
+ 0x100821b3 0x3e _zPHY_ecsrc_OnChangeMeasPeriodReq
+ 0x100821f1 0x11 _zPHY_ecsrc_OnIdleInterRfChangeFinishedEvent
+ 0x10082202 0x39 _zPHY_ecsrc_OnIratMeasGapConfigReq
+ 0x1008223b 0x21 _zPHY_ecsrc_OnFreqScanReq
+ 0x1008225c 0x3b _zPHY_ecsrc_InitOnFreqScanReq
+ 0x10082297 0x53 _zPHY_ecsrc_IdleOnFreqScanReq
+ 0x100822ea 0x27 _zPHY_ecsrc_SlaveOnFreqScanReq
+ 0x10082311 0x21 _zPHY_ecsrc_OnCtrlSearchFreqScanCnf
+ 0x10082332 0x1c _zPHY_ecsrc_OnHandoverReq
+ 0x1008234e 0x10 _zPHY_ecsrc_OnPlmnResumeSrvCellTpu
+ 0x1008235e 0x2c _zPHY_ecsrc_OnPlmnPeriodTpuIntIn
+ 0x1008238a 0x26 _zPHY_ecsrc_FreqScanSubFrameIntDelay
+ 0x100823b0 0x47 _zPHY_ecsrc_RunningCheck
+ 0x100823f7 0x8d _zPHY_ecsrc_OnArfcnListInfo
+ 0x10082484 0x47 _zPHY_amt_Lte_Set_EarfcnInfo
+ 0x100824cb 0xf _L1e_csrc_HandoverSuccPro
+ 0x100824da 0x1b _zPHY_ecsrc_StartProc
+ 0x100824f5 0x15f _zPHY_ecsrc_ComProc
+ 0x10082654 0x15 _zPHY_ecsrc_InitProc
+ 0x10082669 0x6f _zPHY_ecsrc_IdleProc
+ 0x100826d8 0x21 _zPHY_ecsrc_ConnProc
+ 0x100826f9 0x91 _zPHY_ecsrc_SlaveProc
+ 0x1008278a 0x5b _zPHY_ecsrc_Ctrl
+ 0x100827e5 0x48 _zPHY_ecsrc_ThreadEntry
+ 0x1008282d 0xc8 _zEcsrc_PreEvent
+ 0x100828f5 0x38 _zEcsrc_OnEvent
+ 0x1008292d 0x52 _zPHY_ecsrc_ReadSnr
+ 0x1008297f 0xd6 _zPHY_ecsrc_ReadSearctT
+ 0x10082a55 0x1e _zPHY_ecsrc_ReadIntraSearctT
+ 0x10082a73 0x1e _zPHY_ecsrc_ReadSpeedSearctT
+ 0x10082a91 0x1d _zPHY_ecsrc_ReadCfoUpdateT
+ 0x10082aae 0x2a _zPHY_ecsrc_GetDestTime
+ 0x10082ad8 0x1c _zPHY_ecsrc_CalDestTimeOffset
+ 0x10082af4 0x19 _zPHY_ecsrc_GetNonHighPrioFreqNum
+ 0x10082b0d 0x19 _zPHY_ecsrc_GetHighPrioFreqNum
+ 0x10082b26 0x13 _zPHY_ecsrc_GetReportNum
+ 0x10082b39 0x31 _zPHY_ecsrc_NeedIntraSearchStep
+ 0x10082b6a 0x2e _zPHY_ecsrc_NeedIntraSearchStepNormal
+ 0x10082b98 0x45 _zPHY_ecsrc_NeedIntraSearch
+ 0x10082bdd 0x22 _zPHY_ecsrc_IsNonHighPrioWorkDrx
+ 0x10082bff 0xaa _zPHY_ecsrc_NeedWork
+ 0x10082ca9 0x54 _zPHY_ecsrc_CalcInitDrxNum
+ 0x10082cfd 0x7f _zPHY_ecsrc_CalcWorkDrxNum
+ 0x10082d7c 0x22 _zPHY_ecsrc_NeedInterSearch
+ 0x10082d9e 0x9 _zPHY_ecsrc_NeedInterMeas
+ 0x10082da7 0x52 _zPHY_ecsrc_NeedIntraMeas
+ 0x10082df9 0x1c _zPHY_ecsrc_FreqIndexAcc
+ 0x10082e15 0x37 _zPHY_ecsrc_IsLastFreqInDrx
+ 0x10082e4c 0x72 _L1e_csrc_SRCellRank
+ 0x10082ebe 0x9a _L1e_csrc_SaveSRCellInfo
+ 0x10082f58 0x52 _L1e_csrc_SetSRCellInfo
+ 0x10082faa 0x121 _L1e_csrc_GetMobileCxtFlag
+ 0x100830cb 0x49 _zPHY_ecsrc_CtrlIdleIntraMeasEndEventNew
+ 0x10083114 0x37 _zPHY_ecsrc_GetReportDrxNum
+ 0x1008314b 0x2 _zPHY_ecsrc_EverTrue
+ 0x1008314d 0x10 _zPHY_ecsrc_StartDelayTimer
+ 0x1008315d 0x9 _zPHY_ecsrc_WaitEvent
+ 0x10083166 0x1d _zPHY_ecsrc_SchedInit
+ 0x10083183 0x20 _zPHY_ecsrc_SchedStop
+ 0x100831a3 0x8 _zPHY_ecsrc_SchedStart
+ 0x100831ab 0x15 _zPHY_ecsrc_NeedWorkInReportPeriod
+ 0x100831c0 0xbc _zPHY_ecsrc_OnStartPi
+ 0x1008327c 0x63 _zPHY_ecsrc_OnEndPi
+ 0x100832df 0x9b _zPHY_ecsrc_ReportOneFreq
+ 0x1008337a 0x7c _zPHY_ecsrc_ReportPreValue
+ 0x100833f6 0x49 _zPHY_ecsrc_ReportInra
+ 0x1008343f 0x57 _zPHY_ecsrc_DoReportIner
+ 0x10083496 0x11 _zPHY_ecsrc_ReportInter
+ 0x100834a7 0x12 _zPHY_ecsrc_OneFreqModeWork
+ 0x100834b9 0x1a _zPHY_ecsrc_OneFreqIntraWork
+ 0x100834d3 0x27 _zPHY_ecsrc_IntraSearchInLowSnr
+ 0x100834fa 0x36 _zPHY_ecsrc_FixedStrongSearch
+ 0x10083530 0x8 _zPHY_ecsrc_GetFixedStrongSearchFlag
+ 0x10083538 0x30 _zPHY_ecsrc_NeedSearchInLowSnr
+ 0x10083568 0x25 _zPHY_ecsrc_NeedSearchInRA
+ 0x1008358d 0x14 _zPHY_ecsrc_OneFreqInterWork
+ 0x100835a1 0x11 _zPHY_ecsrc_GerFreqNumPerDrx
+ 0x100835b2 0x5c _zPHY_ecsrc_NextInterFreqInDrx
+ 0x1008360e 0x23 _zPHY_ecsrc_IntraWorkInDrx
+ 0x10083631 0x20 _zPHY_ecsrc_InterFinishInDrx
+ 0x10083651 0x35 _zPHY_ecsrc_RecordInterDoneInDrx
+ 0x10083686 0x65 _zPHY_ecsrc_InterSchedInitPerDrx
+ 0x100836eb 0x9b _zPHY_ecsrc_GetIntraSearchTime
+ 0x10083786 0x2e _zPHY_ecsrc_GetInterSearchTime
+ 0x100837b4 0x7f _zPHY_ecsrc_GetIntraMeasTime
+ 0x10083833 0xa1 _zPHY_ecsrc_GetInterMeasTime
+ 0x100838d4 0x4d _zPHY_ecsrc_GetIntraWorkTime
+ 0x10083921 0x15 _zPHY_ecsrc_GetInterWorkTime
+ 0x10083936 0x69 _zEcsr_GetWorkTimeInCurDrx
+ 0x1008399f 0x71 _zPHY_ecsrc_ChangeMeasMode
+ 0x10083a10 0x36 _zPHY_ecsrc_IntraMeasStart
+ 0x10083a46 0x3 _zPHY_ecsrc_InterMeasStart
+ 0x10083a49 0x15 _zPHY_ecsrc_IntraSearchStart
+ 0x10083a5e 0xd _zPHY_ecsrc_SetIntraWorkTime
+ 0x10083a6b 0x1e _zPHY_ecsrc_SetInterWorkTime
+ 0x10083a89 0x12 _zPHY_ecsrc_ServCellStart
+ 0x10083a9b 0x26 _zPHY_ecsrc_SearchInMeasConfig
+ 0x10083ac1 0x21 _zPHY_ecsrc_ReadIndexInSchedContext
+ 0x10083ae2 0x21 _zPHY_ecsrc_IntraFreqStart
+ 0x10083b03 0x12b _zPHY_ecsrc_InterFreqStart
+ 0x10083c2e 0xb4 _zPHY_ecsrc_OneFreqStart
+ 0x10083ce2 0x26 _zPHY_ecsrc_NeedSchedInter
+ 0x10083d08 0x1 _zPHY_ecsrc_BeforeInter
+ 0x10083d09 0x15 _zPHY_ecsrc_BeforeOneFreq
+ 0x10083d1e 0x24 _zPHY_ecsrc_NeedInitial
+ 0x10083d42 0x49 _zPHY_ecsrc_ChangeMeasPeriodIdle
+ 0x10083d8b 0x32 _zPHY_ecsrc_ReportNoInactiveTime
+ 0x10083dbd 0x7 _zPHY_ecsrc_NeedAdjustBndFrmCfo
+ 0x10083dc4 0x5e _zPHY_ecsrc_AdjustBndFrmCfo
+ 0x10083e22 0x15 _zPHY_ecsrc_SetShortDrxState
+ 0x10083e37 0x12 _zPHY_ecsrc_CfgRfcRxOffset
+ 0x10083e49 0x2b _zPHY_ecsrc_AdjustSrvTpu
+ 0x10083e74 0x7 _zPHY_ecsrc_BackupCFOFreqOffset
+ 0x10083e7b 0x8 _l1e_csrc_GetDrxCnt
+ 0x10083e83 0x3b _zPHY_ecsrc_DrxReStartSearchMeas
+ 0x10083ebe 0x2a _zPHY_ecsrc_ReadPrio
+ 0x10083ee8 0x85 _zPHY_ecsrc_WakeupPs
+ 0x10083f6d 0x8 _L1e_csrc_GetCurCtx
+ 0x10083f75 0x8 _L1e_csrc_GetMeasBit
+ 0x10083f7d 0x98 _L1e_csrc_TempRead
+ 0x10084015 0x92 _L1e_ecsrc_UpdateBackBchBnd
+ 0x100840a7 0x9 _L1e_csrc_AtZepcgSetLowPower
+ 0x100840b0 0x9 _L1e_csrc_AtZepcgClrLowPower
+ 0x100840b9 0x40 _L1e_csrc_AtZepcgSetPhyCfg
+ 0x100840f9 0x67 _L1e_csrc_GetFreqOffset
+ 0x10084160 0x90 _L1e_csrc_SetDisableAfcReloadFlag
+ 0x100841f0 0x4a _L1e_csrc_SetScanFailNum
+ 0x1008423a 0x95 _L1e_csrc_C0CaliPeriod
+ 0x100842cf 0x87 _L1e_csrc_C0CaliEvalue
+ 0x10084356 0x10b _L1e_csrc_C0Update
+ 0x10084461 0x80 _L1e_csrc_C0CalRsrp
+ 0x100844e1 0x5f _L1e_csrc_C0CalAfc
+ 0x10084540 0x1c _L1e_csrc_C0CaliRestart
+ 0x1008455c 0x16 _L1e_csrc_C0CaliInit
+ 0x10084572 0x13 _L1e_csrc_C0FactorUtcValid
+ 0x10084585 0x6f _L1e_csrc_UtcTimeExpired
+ 0x100845f4 0x65 _L1e_csrc_BackupCurPpm
+ 0x10084659 0x30 _L1e_csrc_GetCurPpmValid
+ 0x10084689 0x44 _L1e_csrc_TempNoChange
+ 0x100846cd 0x33 _L1e_csrc_FindFreqOffsetIndex
+ 0x10084700 0x26 _L1e_csrc_UpdateFtErrorList
+ .text 0x10084726 0x212 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ 0x10084726 0x212 _zPHY_emc_ProPhyStateCtrl
+ .text 0x10084938 0xb29 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ 0x10084938 0x7 _zPHY_ecsrc_SatAdd
+ 0x1008493f 0x9 _zPHY_ecsrc_SatSub
+ 0x10084948 0x18 _zPHY_ecsrc_CellDatabaseReset
+ 0x10084960 0x2b _zPHY_ecsrc_GetCellInfo
+ 0x1008498b 0x48 _zPHY_ecsrc_GetAddCell
+ 0x100849d3 0x61 _zPHY_ecsrc_DeleteCell
+ 0x10084a34 0x4d _zPHY_ecsrc_DeleteOldCell
+ 0x10084a81 0x69 _zPHY_ecsrc_DeleteAllCell
+ 0x10084aea 0x4d _zPHY_ecsrc_DeleteNoCfgCell
+ 0x10084b37 0x1a _L1e_Csrc_IsServcell
+ 0x10084b51 0x13 _L1e_Csrc_IsServcellEarfcn
+ 0x10084b64 0x42 _zPHY_ecsrc_FindCell
+ 0x10084ba6 0x29 _zPHY_ecsrc_ClearOtherCell
+ 0x10084bcf 0x12 _zPHY_ecsrc_FindServCell
+ 0x10084be1 0x4e _zPHY_ecsrc_CtrlICPWriteMeasPriority
+ 0x10084c2f 0x9e _zPHY_ecsrc_SearchAddCellToDatabase
+ 0x10084ccd 0x8d _zPHY_ecsrc_CtrlRefreshDataBase
+ 0x10084d5a 0x54 _zPHY_ecsrc_CtrlUpdateBoundary
+ 0x10084dae 0x49 _zPHY_ecsrc_AdjustCellAge
+ 0x10084df7 0x3a _zPHY_ecsrc_CtrlGetStrongestCell
+ 0x10084e31 0xc _zPHY_ecsrc_ScellDatabaseReset
+ 0x10084e3d 0x44 _zPHY_ecsrc_CtrlCellDatabaseAging
+ 0x10084e81 0x2a _zPHY_ecsrc_ClearSearchNewCellFlag
+ 0x10084eab 0x2e _zPHY_ecsrc_ClearAppointCellFlag
+ 0x10084ed9 0x23 _zPHY_ecsrc_ClearValidCellFlag
+ 0x10084efc 0x22 _zEcsrc_FindFreq
+ 0x10084f1e 0x13 _zEcsrc_IsIcp
+ 0x10084f31 0x40 _zEcsrc_GetMeasBand
+ 0x10084f71 0x19 _zEcsrc_GetMeasTimes
+ 0x10084f8a 0x2c _zPHY_ecsrc_ClearFreqInfo
+ 0x10084fb6 0x34 _zPHY_ecsrc_ClearNoCfgFreqInfo
+ 0x10084fea 0x1f _zPHY_ecsrc_FindFreqInfo
+ 0x10085009 0x60 _zPHY_ecsrc_ExChangeFreqInfo
+ 0x10085069 0x9e _zPHY_ecsrc_SaveFreqInfo
+ 0x10085107 0x4d _zPHY_ecsrc_ReadRsrpCaliInfo
+ 0x10085154 0x4a _zPHY_ecsrc_UpdateTimeOffset
+ 0x1008519e 0x41 _zPHY_ecsrc_RecoverTimeOffset
+ 0x100851df 0x48 _zPHY_ecsrc_ChangeTimeOffset
+ 0x10085227 0x23 _zPHY_ecsrc_ReadTimeOffset
+ 0x1008524a 0x1e _zPHY_ecsrc_GetCellNum
+ 0x10085268 0xb _L1e_Csrc_UpdateServCell
+ 0x10085273 0x10 _L1e_Csrc_ServCellChange
+ 0x10085283 0xc _L1e_Csrc_ChangeNeiConfigFlag
+ 0x1008528f 0x7e _zPHY_ecsrc_DealSrvBndFrmCfo
+ 0x1008530d 0x25 _L1e_csrc_SetMeasState
+ 0x10085332 0x87 _zPHY_ecsrc_GetMeasCell
+ 0x100853b9 0x4b _zPHY_ecsrc_GetMeasCellNum
+ 0x10085404 0x12 _zPHY_ecsrc_GetFddBufferMode
+ 0x10085416 0x1e _zPHY_ecsrc_GetIndexInFreqMeasMode
+ 0x10085434 0x11 _zPHY_ecsrc_GetMeasAge
+ 0x10085445 0x1c _zPHY_ecsrc_GetFreqOffset
+ .text 0x10085461 0x2c26 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x10085461 0xb _zPHY_ecsrc_CtrlShiftSlaveFunState
+ 0x1008546c 0x14 _zPHY_ecsrc_CtrlShiftSlaveSynState
+ 0x10085480 0xa _zPHY_ecsrc_MulmSetRfWorkSet
+ 0x1008548a 0x65 _zPHY_ecsrc_MulmCfgRFCModem7510
+ 0x100854ef 0x5f _zPHY_ecsrc_MulmRegRFStartClose
+ 0x1008554e 0x121 _zPHY_ecsrc_MulmIratIdlePeriodRepProcess7510
+ 0x1008566f 0x44 _zEcsr_UpdateSiReadState
+ 0x100856b3 0x35 _zPHY_ecsrc_MulmCtrlSetMode
+ 0x100856e8 0xa3 _zPHY_ecsrc_MulmSlaveReset
+ 0x1008578b 0x14 _zPHY_ecsrc_MulmFreqListConfigProcess
+ 0x1008579f 0x60 _L1e_Mulm_ReadSearchT
+ 0x100857ff 0x58 _L1e_Mulm_NeedSearch
+ 0x10085857 0x34 _L1e_Mulm_NeedMeas
+ 0x1008588b 0x47 _zPHY_ecsrc_MulmIratMeasScheduleProcess
+ 0x100858d2 0x3c _zPHY_ecsrc_MulmIratAddMeasReport
+ 0x1008590e 0x77 _zPHY_ecsrc_MulmMeasReset
+ 0x10085985 0xe5 _zPHY_ecsrc_MulmIratMeasConfigProcess
+ 0x10085a6a 0x72 _zPHY_ecsrc_MulmReportFreqMeasResult
+ 0x10085adc 0x5d _zPHY_ecsrc_MulmIratMeasResultHandle
+ 0x10085b39 0x9 _zPHY_ecsrc_MulmIratResetMeasCnt
+ 0x10085b42 0x8d _zPHY_ecsrc_MulmIratMeasReportIntHandle
+ 0x10085bcf 0xaf _zPHY_ecsrc_MulmIratMeasFilter
+ 0x10085c7e 0x88 _zPHY_ecsrc_MulmIratFreqFilter
+ 0x10085d06 0x72 _zPHY_ecsrc_MulmIratUpdateMeasInd
+ 0x10085d78 0x34 _zPHY_ecsrc_MulmIratUpdateFreqReport
+ 0x10085dac 0x40 _zPHY_ecsrc_MulmIratSetFilterFact
+ 0x10085dec 0x2a _zPHY_ecsrc_MulmIratReadPrio
+ 0x10085e16 0x55 _zPHY_ecsrc_MulmIratSearchMeasureStartSchedule
+ 0x10085e6b 0x17 _zPHY_ecsrc_MulmSlaveCfgRfcMeas1Offset7510
+ 0x10085e82 0x37 _zPHY_ecsrc_MulmSlaveGapStartOffsetCfg7510
+ 0x10085eb9 0x43 _zPHY_ecsrc_MulmSlaveGapEndOffsetCfg7510
+ 0x10085efc 0x36 _zPHY_ecsrc_MulmRegTpuSingleEvent
+ 0x10085f32 0x63 _zPHY_ecsrc_MulmGetGapType
+ 0x10085f95 0x28 _zPHY_ecsrc_MulmRegTpuEvent
+ 0x10085fbd 0xed _zPHY_ecsrc_MulmIratGapSchedFlow
+ 0x100860aa 0x62 _zPHY_ecsrc_ReRegistGapConfigDelag
+ 0x1008610c 0x62 _zPHY_ecsrc_MulmIratGapSchedFlowProtect
+ 0x1008616e 0x56 _zPHY_ecsrc_MulmBlackCellFilter
+ 0x100861c4 0x60 _zPHY_ecsrs_MulmRemainTimeInGap
+ 0x10086224 0x2d _zPHY_ecsrs_MulmProtectTimeBeforeGap
+ 0x10086251 0x1a _zPHY_ecsrc_MulmCalMeasTime
+ 0x1008626b 0x5b _zPHY_ecsrc_MulmCalSearchTime
+ 0x100862c6 0x104 _zPHY_ecsrc_MulmTpuCnf
+ 0x100863ca 0x13 _zPHY_ecsrc_MulmCsr2TpuUpdateCounterCnfHandle
+ 0x100863dd 0x4a _zPHY_ecsrc_MulmSlavePlmnSearchStart
+ 0x10086427 0x2a _zPHY_ecsrc_MulmSlavePlmnSearchFinHandle
+ 0x10086451 0x42 _zPHY_ecsrc_MulmSlavePlmnMeasureTimerIntHandle
+ 0x10086493 0x2e _zPHY_ecsrc_MulmSlavePlmnAbortCellSearchHandle
+ 0x100864c1 0x45 _zPHY_ecsrs_MulmPlmnSib1InGap
+ 0x10086506 0x45 _zPHY_ecsrc_MulmRegNotSynSubFrameInt
+ 0x1008654b 0x2c _zPHY_ecsrc_MulmRegCsrmSfInt
+ 0x10086577 0xaa _zPHY_ecsrc_MulmIratGapStartTpuIntHandle
+ 0x10086621 0x20 _zPHY_ecsrc_MulmUnRegistSearchMeasInt
+ 0x10086641 0x42 _zPHY_ecsrc_MulmIratGapEndTpuIntHandle
+ 0x10086683 0x50 _zPHY_ecsrc_MulmSlaveAbortGapProtectTimerEnable
+ 0x100866d3 0x48 _zPHY_ecsrc_MulmIratMeasDoneHandle
+ 0x1008671b 0x6e _zPHY_ecsrc_MulmIratAbortGapHandle
+ 0x10086789 0x68 _zPHY_ecsrc_MulmIratAbortGapProtectTimerHandle
+ 0x100867f1 0x97 _zPHY_ecsrs_MulmIratGapPositionCheck
+ 0x10086888 0x27 _zPHY_ecsrs_MulmGapCoverTime
+ 0x100868af 0x42 _zPHY_ecsrm_MulmPbchStartCheck
+ 0x100868f1 0x27 _zPHY_ecsrs_MulmEnableRfcEventTable
+ 0x10086918 0x26 _zPHY_ecsrs_Mulm6MSRfcMeas1GapOffsetCfg
+ 0x1008693e 0x64 _zPHY_ecsrs_MulmRfOpenNo
+ 0x100869a2 0x49 _zPHY_ecsrs_MulmConfigSynState
+ 0x100869eb 0x56 _zPHY_ecsrs_MulmEnableRF
+ 0x10086a41 0x45 _zPHY_emc_MulmCsrRfStartDeal
+ 0x10086a86 0x62 _zPHY_emc_MulmCsrRfEndDeal
+ 0x10086ae8 0x20 _zPHY_emc_DealRFCloseEvent
+ 0x10086b08 0x2d _zPHY_ecsrc_CtrlMulmDbAging
+ 0x10086b35 0xf _zPHY_ecsrc_CtrlSetMulmSlaveSearchMeasAgeInfor
+ 0x10086b44 0x97 _zPHY_ecsrc_CtrlMulmRefreshDataBase
+ 0x10086bdb 0x50 _zPHY_ecsrs_MulmTpuAdjCheckTime
+ 0x10086c2b 0x2f _zPHY_ecsrs_MulmIcpPssBoundryAdj
+ 0x10086c5a 0x1a _zPHY_ecsrs_MulmPssTpuCnf
+ 0x10086c74 0x46 _zPHY_ecsrs_MulmIsPssWorkTime
+ 0x10086cba 0xa0 _zPHY_ecsrs_MulmGetPssHwStartTime
+ 0x10086d5a 0x53 _zPHY_ecsrs_MulmPssCfg
+ 0x10086dad 0xb _zPHY_ecsrs_MulmPssConfig
+ 0x10086db8 0x16 _zPHY_ecsrs_MulmPssGapCoverTime
+ 0x10086dce 0x68 _zPHY_ecsrc_MulmGetValidCellFrameBoundry7510
+ 0x10086e36 0x3f _zPHY_ecsrc_MulmTpuAdjPro
+ 0x10086e75 0x27 _zPHY_ecsrc_MulmBoundryAdj
+ 0x10086e9c 0x7f _zPHY_ecsrs_MulmCheckTpuAdj
+ 0x10086f1b 0x28 _zPHY_ecsrs_MulmStartTpuAdj
+ 0x10086f43 0xf3 _zPHY_ecsrc_MulmIratSearchStartSchedule7510
+ 0x10087036 0x56 _zPHY_emc_MulmSlaveMeasureReportProtect
+ 0x1008708c 0x190 _zPHY_emc_MulmSlaveMeasureFlow
+ 0x1008721c 0x7 _zPHY_ecsrs_MulmIratFSPssGapPositionCheck
+ 0x10087223 0x17 _zPHY_ecsrs_MulmIratCheckGapTime
+ 0x1008723a 0x3d _zPHY_ecsrs_MulmIratPssTimeCheck
+ 0x10087277 0x4b _zPHY_ecsrs_MulmIratSssGapPositionCheck
+ 0x100872c2 0x39 _zPHY_ecsrs_MulmAgcStable
+ 0x100872fb 0x15 _L1e_mulm_CfoAccNum
+ 0x10087310 0x87 _zPHY_ecsrs_MulmCfoConfig
+ 0x10087397 0x1e _zPHY_ecsrs_MulmSssCfg
+ 0x100873b5 0x8b _zPHY_ecsrs_MulmIsTddSssWorkTime
+ 0x10087440 0x18 _zPHY_ecsrs_MulmStartICSPSubFrameInt
+ 0x10087458 0x13 _zPHY_ecsrs_MulmStartSynSearchSubFrameInt
+ 0x1008746b 0x40 _zPHY_ecsrs_MulmGapCoverTime7510
+ 0x100874ab 0x136 _zPHY_ecsrs_MulmIsFddSssWorkTime
+ 0x100875e1 0x1d _zPHY_ecsrs_MulmGetMeasBaseTime
+ 0x100875fe 0x154 _zPHY_ecsrs_MulmCfoCheckTime
+ 0x10087752 0xa9 _zPHY_ecsrs_MulmIsValidTime
+ 0x100877fb 0xfd _zPHY_ecsrs_MulmCheckOpenTime
+ 0x100878f8 0xb3 _zPHY_ecsrm_MulmBuffCheckOpenTimePeriod
+ 0x100879ab 0x5a _zPHY_ecsrs_MulmGapCoverCheck
+ 0x10087a05 0x47 _zPHY_ecsrs_MulmGapCoverBufferCheck
+ 0x10087a4c 0x14 _zPHY_ecsrs_MulmIsShortGap
+ 0x10087a60 0x16 _zPHY_ecsrs_MulmGetFreqIndex
+ 0x10087a76 0x2e _zPHY_ecsrc_MulmIratClearPreFilter
+ 0x10087aa4 0x26 _zPHY_ecsrs_AbsModSub
+ 0x10087aca 0xc _zPHY_ecsrs_MulmCsBefore
+ 0x10087ad6 0x26 _zPHY_ecsrs_MulmCsNeedCs
+ 0x10087afc 0xc _zPHY_ecsrs_MulmCsNeedAgc
+ 0x10087b08 0x37 _zPHY_ecsrs_MulmCsBeforeAgc
+ 0x10087b3f 0xb _zPHY_ecsrs_MulmCsIsOnAgc
+ 0x10087b4a 0x1c _zPHY_ecsrs_MulmCsAgcProc
+ 0x10087b66 0x8 _zPHY_ecsrs_MulmCsAgcProcEnd
+ 0x10087b6e 0xb _zPHY_ecsrs_MulmCsNeedPss
+ 0x10087b79 0x2d _zPHY_ecsrs_MulmCsBeforePss
+ 0x10087ba6 0x18 _zPHY_ecsrs_MulmCsIsOnPss
+ 0x10087bbe 0x41 _zPHY_ecsrs_MulmCsPssProc
+ 0x10087bff 0x43 _zPHY_ecsrs_MulmCsPssProcEnd
+ 0x10087c42 0x14 _zPHY_ecsrs_MulmCsNeedTpuAdj1
+ 0x10087c56 0xc _zPHY_ecsrs_MulmCsNeedTpuAdj
+ 0x10087c62 0xc _zPHY_ecsrs_MulmCsTpuAdjProc
+ 0x10087c6e 0x1a _zPHY_ecsrs_MulmCsTpuAdjProc2
+ 0x10087c88 0xe _zPHY_ecsrs_MulmCsTpuCheck
+ 0x10087c96 0xc _zPHY_ecsrs_MulmCsNeedCfo
+ 0x10087ca2 0x15 _zPHY_ecsrs_MulmCsBeforeCfo
+ 0x10087cb7 0x25 _zPHY_ecsrs_MulmCsBeforeCfoOnce
+ 0x10087cdc 0x20 _zPHY_ecsrs_MulmCsIsOnCfo
+ 0x10087cfc 0x1d _zPHY_ecsrs_MulmCsNeedMoreCfo
+ 0x10087d19 0x30 _zPHY_ecsrs_MulmCsCfoProc
+ 0x10087d49 0x4a _zPHY_ecsrs_MulmCsCfoOnceProcEnd
+ 0x10087d93 0x8 _zPHY_ecsrs_MulmCsCfoProcEnd
+ 0x10087d9b 0x31 _zPHY_ecsrs_MulmLteCordicConfig
+ 0x10087dcc 0x12 _zPHY_ecsrs_MulmGetLteCordicValue
+ 0x10087dde 0xc _zPHY_ecsr_MulmCordicAdjust
+ 0x10087dea 0x5a _zPHY_ecsr_MulmToLteCfo
+ 0x10087e44 0x8 _zPHY_ecsr_MulmReadCordicValue
+ 0x10087e4c 0x8 _zPHY_ecsr_MulmWriteCordicValue
+ 0x10087e54 0xc _zPHY_ecsrs_MulmCsNeedSss
+ 0x10087e60 0x28 _zPHY_ecsrs_MulmCsBeforeSss
+ 0x10087e88 0x29 _zPHY_ecsrs_MulmCsIsOnSss
+ 0x10087eb1 0x18 _zPHY_ecsrs_MulmIsSssWorkTime
+ 0x10087ec9 0x47 _zPHY_ecsrs_MulmCsSssProc
+ 0x10087f10 0x50 _zPHY_ecsrs_MulmCsSssProcEnd
+ 0x10087f60 0x75 _zPHY_ecsrs_MulmCsProEnd
+ 0x10087fd5 0x8 _zPHY_ecsrc_MulmSetRfState
+ 0x10087fdd 0x25 _zPHY_ecsrc_MulmSchedCheck
+ 0x10088002 0x15 _zPHY_ecsrs_MulmCheckReadTime
+ 0x10088017 0x66 _zPHY_ecsrs_MulmIsSssSchedSubFrm
+ 0x1008807d 0xa _zPHY_ecsrs_Wait
+ .text 0x10088087 0xf36 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x10088087 0x1a _zPHY_ecsrc_InitCellSearchProc
+ 0x100880a1 0x1c _zPHY_ecsrc_IdleCellSearchProc
+ 0x100880bd 0x4d _zPHY_ecsrc_SetCellSearchCnf
+ 0x1008810a 0x7c _zPHY_ecsrc_InitAppointedCS
+ 0x10088186 0x16 _zPHY_ecsrc_InitNotAppointedCS
+ 0x1008819c 0x46 _zPHY_ecsrc_CtrlSssUpdateProcess
+ 0x100881e2 0x42 _zPHY_ecsrc_ReSearchOrReportCell
+ 0x10088224 0x37 _zPHY_ecsrc_SetInitMeasTime
+ 0x1008825b 0x6b _zPHY_ecsrc_CtrlICPTimeEvent
+ 0x100882c6 0x3f _zPHY_ecsrc_CtrlICPTpuAdjust
+ 0x10088305 0xaf _zPHY_ecsrc_CtrlICPMeasTimeEvent
+ 0x100883b4 0x3c _zPHY_ecsrc_SortCellSearchCnf
+ 0x100883f0 0x4a _zPHY_ecsrc_SetReportCellList
+ 0x1008843a 0x99 _zPHY_ecsrc_CtrlICPReportResult
+ 0x100884d3 0xc2 _zPHY_ecsrc_CtrlIcpBchHandle
+ 0x10088595 0x4f _zPHY_ecsrc_CtrlBchDecodeEvent
+ 0x100885e4 0x48 _zPHY_ecsrc_CtrlIcpReportNoCell
+ 0x1008862c 0x62 _zPHY_ecsrc_CtrlIcpTimeEndEvent
+ 0x1008868e 0x29 _zPHY_ecsrc_CfgSynTable
+ 0x100886b7 0x36 _zPHY_ecsrc_ReConstructRxPara
+ 0x100886ed 0x16 _zPHY_ecsrc_ConfirmRxPara
+ 0x10088703 0x35 _zPHY_ecsrc_PlmnBackupSrvCell
+ 0x10088738 0x86 _zPHY_ecsrc_PlmnResumeDlRfcEnableEvent
+ 0x100887be 0xcc _zPHY_ecsrc_PlmnPhyResultReport
+ 0x1008888a 0x54 _zPHY_ecsrc_FreqScanResultReportHandle
+ 0x100888de 0x43 _zPHY_ecsrc_PlmnResumeSrvCellTPU
+ 0x10088921 0x3b _zPHY_ecsrc_PlmnCurTime2PiTimeDistance
+ 0x1008895c 0x10 _zPHY_ecsrc_PlmnHasEnoughTime
+ 0x1008896c 0x30 _zPHY_ecsrc_PlmnProcessPeriodicalTpuIntIn
+ 0x1008899c 0x24 _zPHY_ecsrc_PlmnResumeSrvCellNew
+ 0x100889c0 0x31 _zPHY_ecsrc_PlmnSearchResultHandleNew
+ 0x100889f1 0x37 _zPHY_ecsrc_PlmnFreqScanReqPro
+ 0x10088a28 0x15 _zPHY_ecsrc_PlmnCellSearchReqPro
+ 0x10088a3d 0x72 _zPHY_ecsrc_PlmnPeriodTpuInPro
+ 0x10088aaf 0x33 _L1e_csrc_CalcProTime
+ 0x10088ae2 0x1d _zPHY_ecsrc_PlmnGetPhaseMinTime
+ 0x10088aff 0xa2 _zPHY_ecsrc_PlmnBackupAfc
+ 0x10088ba1 0x1c _zPHY_ecsrc_PlmnResumeAgcAFc
+ 0x10088bbd 0xf _zPHY_ecsrc_PlmnPhasePro
+ 0x10088bcc 0x4a _zPHY_ecsrc_SearchPhaseCheck
+ 0x10088c16 0xa _zPHY_ecsrc_PlmnReadPhase
+ 0x10088c20 0xf _zPHY_ecsrc_PlmnPhaseShift
+ 0x10088c2f 0x3c _zPHY_ecsrc_PlmnPhaseContinue
+ 0x10088c6b 0x28 _zPHY_ecsrc_SearchDone
+ 0x10088c93 0x38 _zPHY_ecsrc_SendCellSearchReq
+ 0x10088ccb 0x9 _zPHY_ecsrc_RestartCellSearch
+ 0x10088cd4 0xd4 _zPHY_ecsrc_CtrlAbortICPProcess
+ 0x10088da8 0x35 _zPHY_ecsrc_BchCellInfoBak
+ 0x10088ddd 0x155 _l1e_SchedCsrcGetOverlapInfo
+ 0x10088f32 0x53 _zPHY_ecsrc_ProWriteBch2CsrDb
+ 0x10088f85 0x38 _zPHY_ecsrc_ProBackBchInfo
+ .text 0x10088fbd 0x379 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ 0x10088fbd 0x35 _CheckThread
+ 0x10088ff2 0x6b _NextStep
+ 0x1008905d 0x33 _RunProc
+ 0x10089090 0x12 _RunFun0
+ 0x100890a2 0x14 _RunFun0P1
+ 0x100890b6 0xc _RunFun1
+ 0x100890c2 0x15 _RunOpt
+ 0x100890d7 0x4c _RunWhile
+ 0x10089123 0x27 _RunEnd
+ 0x1008914a 0x1c _RunDo
+ 0x10089166 0x43 _RunWhile1
+ 0x100891a9 0x15 _RunLoop0
+ 0x100891be 0x15 _RunLoop1
+ 0x100891d3 0x25 _RunReturnIf
+ 0x100891f8 0x8b _DispatchStep
+ 0x10089283 0x26 _RunSync
+ 0x100892a9 0x4c _EventHandlerOnce
+ 0x100892f5 0x16 _EventHandler
+ 0x1008930b 0x2b _StartProc
+ .text 0x10089336 0x1ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ 0x10089336 0xc _L1e_SchedMbmsInit
+ 0x10089342 0x48 _L1e_SchedMbmsProcMsg
+ 0x1008938a 0x20 _L1e_SchedMbmsGenMbsfnSfBmp
+ 0x100893aa 0xe3 _L1e_SchedMbmsGenAllocSfBmp
+ 0x1008948d 0xd _L1e_SchedMbmsGetNextTimeInfo
+ 0x1008949a 0x31 _L1e_SchedMbmsProcMchRecv
+ 0x100894cb 0xb _L1e_SchedMbmsGetMbsfnInd
+ 0x100894d6 0xb _L1e_SchedMbmsSetMbsfnFlag
+ 0x100894e1 0xb _L1e_SchedMbmsSetMbmsFlag
+ 0x100894ec 0xd _L1e_SchedMbmsGetMbsfnFlag
+ 0x100894f9 0xf _L1e_SchedMbmsGetMbmsFlag
+ 0x10089508 0x2 _L1e_SchedMBmsGetMbsfnAllocNum
+ 0x1008950a 0xd _L1e_SchedMbmsGetAreaIndex
+ 0x10089517 0xd _L1e_SchedMbmsGetNonMbsfnLen
+ 0x10089524 0x11 _L1e_SchedMBmsGetConfigNum
+ .text 0x10089535 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x10089535 0x44 _zPHY_DrxPreSyncStartCtrl
+ 0x10089579 0x1f1 _zPHY_emc_ProDrxSchedFlow
+ 0x1008976a 0x97 _zPHY_emc_DrxInactivityTimerCtrl
+ 0x10089801 0x73 _zPHY_emc_DrxOnDurationTimerCtrl
+ 0x10089874 0x128 _zPHY_emc_DrxRttTimerAndDlHarqRetranTimerCtrl
+ 0x1008999c 0xf9 _zPHY_emc_DrxUlHarqCtrl
+ 0x10089a95 0x31 _zPHY_emc_ProDrxTpuEventSchedFlow
+ 0x10089ac6 0x88 _zPHY_emc_DrxCalcOndurationTimerStartTime
+ 0x10089b4e 0x64 _zPHY_emc_ProDrxCallBackFunction
+ 0x10089bb2 0x62 _zPHY_emc_RegOndurStartEvent
+ 0x10089c14 0x9e _zPHY_emc_RegShortDrxCycleEvent
+ 0x10089cb2 0x64 _zPHY_emc_CurSubFrDRXStateCtrl
+ 0x10089d16 0x1f _zPHY_emc_DRXCompare2Time
+ 0x10089d35 0x65 _zPHY_emc_OnDurationPre2SubFrm
+ 0x10089d9a 0x41 _zPHY_emc_InactivityPre2SubFrm
+ 0x10089ddb 0x9b _zPHY_emc_DlHarqPre2SubFrm
+ 0x10089e76 0x89 _zPHY_emc_UlHarqPhichPre2SubFrm
+ 0x10089eff 0x63 _zPHY_emc_Next2SubFrameDrxStateCtrl
+ 0x10089f62 0x93 _zPHY_emc_ProDrxInitial
+ 0x10089ff5 0xb _zPHY_emc_ChePwrCtrlFlg
+ 0x1008a000 0x90 _Ltel1_GetConnNearestGap
+ 0x1008a090 0x28d _zPHY_emc_DrxPresyncCalc
+ 0x1008a31d 0x4e _zPHY_emc_DrxStateCtrl
+ 0x1008a36b 0xaf _zPHY_emc_DrxCsi_OpenRXCtrl
+ 0x1008a41a 0xa1 _zPHY_emc_DRXProcLpCtrl
+ 0x1008a4bb 0x15a _zPHY_emc_DrxSpsLpCtrl
+ 0x1008a615 0x23 _zPHY_emc_GetDrxCloseRfState
+ 0x1008a638 0x162 _zPHY_emc_DRXCalOpenRFTime
+ 0x1008a79a 0x84 _zPHY_emc_DRXSleepJudge
+ 0x1008a81e 0x75 _zPHY_emc_DrxParallelSleepCtrl
+ 0x1008a893 0x9d _zPHY_emc_DrxParallelFlowLog
+ 0x1008a930 0x21 _zPHY_emc_DrxParallelFlowCtrl
+ .text 0x1008a951 0x3f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x1008a951 0x7 _zPHY_emc_ProRadioLink_GetFIUpdateInd
+ 0x1008a958 0x7 _zPHY_emc_ProRadioLink_SetFIUpdateInd
+ 0x1008a95f 0x4e _zPHY_emc_ProRadioLink_ParaGetInDrx
+ 0x1008a9ad 0x1e _zPHY_emc_ProRadioLink_THInit
+ 0x1008a9cb 0x28 _zPHY_emc_ProRadioLink_THFilterInFI
+ 0x1008a9f3 0x60 _zPHY_emc_ProRadioLink_GetFinalTH
+ 0x1008aa53 0x52 _zPHY_emc_ProRadioLink_DrxFilter
+ 0x1008aaa5 0xa2 _zPHY_emc_ProRadioLink_DrxFlow
+ 0x1008ab47 0x60 _zPHY_emc_ProRadioLink_NoDrxFilter
+ 0x1008aba7 0x45 _zPHY_emc_ProRadioLink_StateSwitch
+ 0x1008abec 0xb7 _zPHY_emc_ProRadioLink_MainPro
+ 0x1008aca3 0xa6 _zPHY_emc_ProRadioLinkFlow
+ .text 0x1008ad49 0x2e13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x1008ad49 0x40 _zPHY_amt_Lte_PrintMsgLog
+ 0x1008ad89 0x4c _zPHY_AMT_Rfc_WriteRfFrontReg
+ 0x1008add5 0x66 _zPHY_AMT_erfc_SetCurrentBandAntGPIO
+ 0x1008ae3b 0xc1 _zPHY_AMT_erfc_SetCurrentBandPaModeGPIO
+ 0x1008aefc 0x17 _zPHY_AMT_RFC_110_RxOn
+ 0x1008af13 0x16 _zPHY_AMT_RFC_110_RxOff
+ 0x1008af29 0x17 _zPHY_AMT_RFC_110_TxOn
+ 0x1008af40 0x16 _zPHY_AMT_RFC_110_TxOff
+ 0x1008af56 0x16 _zPHY_AMT_RFC_120_RxOn
+ 0x1008af6c 0x16 _zPHY_AMT_RFC_120_RxOff
+ 0x1008af82 0x16 _zPHY_AMT_RFC_120_TxOn
+ 0x1008af98 0x16 _zPHY_AMT_RFC_120_TxOff
+ 0x1008afae 0x17 _zPHY_AMT_RFC_RXENABLE_On
+ 0x1008afc5 0x16 _zPHY_AMT_RFC_RXENABLE_Off
+ 0x1008afdb 0x17 _zPHY_AMT_RFC_TXENABLE_On
+ 0x1008aff2 0x16 _zPHY_AMT_RFC_TXENABLE_Off
+ 0x1008b008 0xf _zPHY_AMT_RFC_110_AfcSet
+ 0x1008b017 0x1 _zPHY_AMT_RFC_110_Xo_AfcSet
+ 0x1008b018 0x22 _zPHY_AMT_RFC_120_DCIQSet
+ 0x1008b03a 0x42 _zPHY_AMT_RFC_110_TempDacGet
+ 0x1008b07c 0x42 _zPHY_AMT_RFC_110_Xo_TempDacGet
+ 0x1008b0be 0x1d _zPHY_AMT_RFC_110_BandWidthModeGet
+ 0x1008b0db 0xa1 _zPHY_AMT_RFC_110_TxFreqSet
+ 0x1008b17c 0x35 _zPHY_AMT_RFC_110_RegTxCfg
+ 0x1008b1b1 0x24 _zPHY_AMT_RFC_120_RegTxCfg
+ 0x1008b1d5 0x36 _zPHY_AMT_RFC_110_RegRxCfg
+ 0x1008b20b 0x30 _zPHY_AMT_RFC_120_RegRxCfg
+ 0x1008b23b 0x28 _zPHY_AMT_RFC_ZTERF_TxApcSet
+ 0x1008b263 0x33 _zPHY_AMT_RFC_ZTERF_Tx2Idle
+ 0x1008b296 0x33 _zPHY_AMT_RFC_ZTERF_Rx2Idle
+ 0x1008b2c9 0x70 _zPHY_AMT_RFC_ZTERF_ToTx
+ 0x1008b339 0x70 _zPHY_AMT_RFC_ZTERF_ToRx
+ 0x1008b3a9 0x13 _zPHY_AMT_RFC_ZTERF_ToIdle
+ 0x1008b3bc 0xd _zPHY_amt_Lte_GetCarrierMode
+ 0x1008b3c9 0x1f _zPHY_amt_Lte_SetCarrierMode
+ 0x1008b3e8 0xdc _zPHY_amt_Lte_ChangeMode
+ 0x1008b4c4 0x15 _zPHY_amt_Lte_TxParaUpdate
+ 0x1008b4d9 0xc7 _zPHY_amt_Lte_ServCellFreqUpdate
+ 0x1008b5a0 0x135 _zPHY_amt_Lte_CellSyncProc
+ 0x1008b6d5 0xd1 _zPHY_amt_Lte_MprDeterm
+ 0x1008b7a6 0xa8 _zPHY_amt_Lte_RfcTxDataBaseSet
+ 0x1008b84e 0x48 _zPHY_amt_Lte_FDTTransTxVgaCtrl
+ 0x1008b896 0x226 _zPHY_amt_Lte_FDT_PAVGAVOL_Update
+ 0x1008babc 0x1f _zPHY_amt_Lte_FDTTxOffsetSet
+ 0x1008badb 0x12e _zPHY_amt_Lte_FDTRfcDataBaseSet
+ 0x1008bc09 0x1c _zPHY_amt_Lte_FDTRfcDataBaseClear
+ 0x1008bc25 0xe _zPHY_amt_Lte_FDTGetAgcGain
+ 0x1008bc33 0x7c _zPHY_amt_Lte_FDTSaveAgcGain
+ 0x1008bcaf 0xf6 _zPHY_amt_Lte_FDTControl
+ 0x1008bda5 0x2 _zPHY_amt_Lte_FDTGetAGC
+ 0x1008bda7 0xb1 _zPHY_amt_Lte_FDTStart
+ 0x1008be58 0x12 _zPHY_amt_Lte_FDTCellSyncProc
+ 0x1008be6a 0x20 _zPHY_amt_Lte_NSTCellSyncProc
+ 0x1008be8a 0x37 _zPHY_amt_Lte_NSTCellSyncSuccessRsp
+ 0x1008bec1 0x43 _zPHY_amt_Lte_NSTStartBler
+ 0x1008bf04 0xed _zPHY_amt_Lte_NSTGetBler
+ 0x1008bff1 0x32 _zPHY_amt_Lte_NSTStart
+ 0x1008c023 0x22 _zPHY_amt_Lte_NSTCirCfoStop
+ 0x1008c045 0x39 _zPHY_amt_Lte_NSTChangeFreq
+ 0x1008c07e 0x15b _zPHY_amt_Lte_NSTControl
+ 0x1008c1d9 0x13 _zPHY_amt_Lte_FSTCellSyncProc
+ 0x1008c1ec 0x89 _zPHY_amt_Lte_FSTStart
+ 0x1008c275 0xc9 _zPHY_amt_Lte_FSTRfcDataBaseSet
+ 0x1008c33e 0xda _zPHY_amt_Lte_FSTPowerUpdate
+ 0x1008c418 0xc0 _zPHY_amt_Lte_FSTSaveBlerAndRsrp
+ 0x1008c4d8 0xf6 _zPHY_amt_Lte_FSTControl
+ 0x1008c5ce 0x29 _zPHY_amt_Lte_Control
+ 0x1008c5f7 0x294 _zPHY_amt_Lte_Tx_Init_Power
+ 0x1008c88b 0x1a4 _zPHY_amt_Lte_Tx_Init_RFC
+ 0x1008ca2f 0x7a _zPHY_amt_Lte_Tx_Init_MC
+ 0x1008caa9 0x7a _zPHY_amt_Lte_Tx_Init_MC_Power
+ 0x1008cb23 0x6e _zPHY_amt_Lte_Close_Rfc
+ 0x1008cb91 0x51 _zPHY_amt_Lte_Tx_Close_MC
+ 0x1008cbe2 0x3c _zPHY_amt_Lte_TxFreq_RFC
+ 0x1008cc1e 0x1d _zPHY_amt_Lte_TxPaMode_RFC
+ 0x1008cc3b 0x4c _zPHY_amt_Lte_TxAPC_RFC
+ 0x1008cc87 0x3a _zPHY_amt_Lte_AFC_RFC
+ 0x1008ccc1 0x38 _zPHY_amt_Lte_XO_AFC_RFC
+ 0x1008ccf9 0x159 _zPHY_amt_Lte_Rx_Init_RFC
+ 0x1008ce52 0x1a _zPHY_amt_Lte_SetSyncTimer
+ 0x1008ce6c 0x4f _zPHY_amt_Lte_Cell_Search
+ 0x1008cebb 0xa3 _zPHY_amt_Lte_CommMsg_Stub
+ 0x1008cf5e 0x3d _zPHY_amt_Lte_CommMsg_Send
+ 0x1008cf9b 0x19f _zPHY_amt_Lte_DediMsg_Stub
+ 0x1008d13a 0x33 _zPHY_amt_Lte_DediMsg_Send
+ 0x1008d16d 0x26b _zPHY_amt_Lte_Sync_Process
+ 0x1008d3d8 0x74 _zPHY_amt_Lte_Rx_Init_MC
+ 0x1008d44c 0x71 _zPHY_amt_Lte_Rx_Close_MC
+ 0x1008d4bd 0x1b _zPHY_amt_Lte_RxFreq_RFC
+ 0x1008d4d8 0x2 _zPHY_amt_Lte_RxLNAMode_RFC
+ 0x1008d4da 0x2 _zPHY_amt_Lte_RxVGA_RFC
+ 0x1008d4dc 0x3c _zPHY_amt_Lte_Get_Rsrp
+ 0x1008d518 0xe _zPHY_amt_Lte_Get_TempDAC
+ 0x1008d526 0xe _zPHY_amt_Lte_Get_Xo_TempDAC
+ 0x1008d534 0xe _zPHY_amt_Lte_Set_AfcData
+ 0x1008d542 0x25 _zPHY_amt_Lte_Tx_DcOffset
+ 0x1008d567 0xbc _zPHY_amt_Lte_CellSearchResult
+ 0x1008d623 0x9b _zPHY_amt_Lte_CalcServCellAntAMT
+ 0x1008d6be 0x49 _zPHY_amt_Lte_UpCellSearchResult
+ 0x1008d707 0xf5 _zPHY_amt_Lte_RxAlways_Init
+ 0x1008d7fc 0xa _zPHY_amt_Lte_RxAlways_Close
+ 0x1008d806 0xe _zPHY_amt_Lte_RxAlwaysOpen_GetAgc
+ 0x1008d814 0x76 _zPHY_amt_Lte_RxAlwaysOpen
+ 0x1008d88a 0x2 _zPHY_amt_Lte_RxCwControl
+ 0x1008d88c 0x2d0 _zPHY_amtTool_ThreadEntry
+ .text 0x1008db5c 0x1b39 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ 0x1008db5c 0x4a _zPHY_erapc_InitialProc
+ 0x1008dba6 0x33 _zPHY_erapc_RaParamReset
+ 0x1008dbd9 0xa4 _zPHY_erapc_BiProc
+ 0x1008dc7d 0x106 _zPHY_erapc_RaResourceSelect
+ 0x1008dd83 0x164 _zPHY_erapc_RaResourceSelectFDD
+ 0x1008dee7 0x12d _zPHY_erapc_RaResourceSelectTDD
+ 0x1008e014 0x48 _zPHY_erapc_PreambleGroupSelect
+ 0x1008e05c 0x4f _zPHY_erapc_PreambleSelect
+ 0x1008e0ab 0x1d0 _zPHY_erapc_PreamCycShiftCalc
+ 0x1008e27b 0x12b _zPHY_erapc_KValueCalc
+ 0x1008e3a6 0xb8 _zPHY_erapc_PreambleTransPower
+ 0x1008e45e 0x6f _zPHY_erapc_PcmaxCalc
+ 0x1008e4cd 0x12a _zPHY_erapc_RarMacPduDecode
+ 0x1008e5f7 0x9c _zPHY_erapc_TpuEventDelete
+ 0x1008e693 0x42 _zPHY_erapc_RntiDelete
+ 0x1008e6d5 0x4b _zPHY_erapc_SetRapcState
+ 0x1008e720 0x43 _zPHY_erapc_PreamFormatDetermFDD
+ 0x1008e763 0x3e _zPHY_erapc_PreamFormatDetermTDD
+ 0x1008e7a1 0xff _zPHY_erapc_ResrConfigDetermFDD
+ 0x1008e8a0 0x1e1 _zPHY_erapc_ResrConfigDetermTDD
+ 0x1008ea81 0x8f _zPHY_erapc_NextAvailSFDetermTDD
+ 0x1008eb10 0x67 _zPHY_erapc_NPrbRaCalcTDD
+ 0x1008eb77 0x21 _zPHY_erapc_RandomNumGenerate
+ 0x1008eb98 0xdd _zPHY_erapc_RaRntiCalc
+ 0x1008ec75 0x8f _zPHY_erapc_SendRaCnfMsg
+ 0x1008ed04 0x152 _zPHY_erapc_ConfigSAD
+ 0x1008ee56 0x235 _zPHY_erapc_PreamTransPro
+ 0x1008f08b 0x7a _zPHY_erapc_RaRetransProc
+ 0x1008f105 0x150 _zPHY_erapc_RarDetectedProc
+ 0x1008f255 0x7b _zPHY_erapc_CRntiMsg4Proc
+ 0x1008f2d0 0x79 _zPHY_erapc_CcchSduMsg4Proc
+ 0x1008f349 0x55 _zPHY_erapc_AbortRaProc
+ 0x1008f39e 0x63 _zPHY_erapc_ContenStopProc
+ 0x1008f401 0x3d _zPHY_erapc_GetRapcTpuEventFlag
+ 0x1008f43e 0x37 _zPHY_erapc_SetRapcTpuEventFlag
+ 0x1008f475 0xae _zPHY_erapc_Format4PrachNumCalc
+ 0x1008f523 0xda _zPHY_erapc_GapConflictIndicate
+ 0x1008f5fd 0x94 _zPHY_erapc_Format4PrachNumCalc_ForUla
+ 0x1008f691 0x4 _zPHY_erapc_PrachAntennaSelect
+ .text 0x1008f695 0x5eb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x1008f695 0x283 _zPHY_emc_ProHandover2Module
+ 0x1008f918 0x35d _zPHY_emc_ProHandoverFlow
+ 0x1008fc75 0xb _zPHY_emc_InHandoverProc
+ .text 0x1008fc80 0xd01 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x1008fc80 0x1f9 _zPHY_emc_ProPagingFlow
+ 0x1008fe79 0xf8 _zPHY_L1e_DcxoDelayProc
+ 0x1008ff71 0x8 _zPHY_L1e_GetPreSyncValidInd
+ 0x1008ff79 0x8 _zPHY_L1e_SetPreSyncValidInd
+ 0x1008ff81 0x7 _zPHY_L1e_GetPreSyncAccNum
+ 0x1008ff88 0x39 _zPHY_emc_RegPageCallEvent
+ 0x1008ffc1 0x1f2 _zPHY_emc_CalPagingParam
+ 0x100901b3 0x103 _zPHY_emc_ProPagingCallBackFunction
+ 0x100902b6 0x31 _zPHY_emc_NxtSubFrmIsPage
+ 0x100902e7 0x16 _zPHY_emc_DrxPoLpCtrl
+ 0x100902fd 0x53 _L1e_Page_ReUpdatePoEvt
+ 0x10090350 0xd5 _L1e_SchedGetPreSyncSchdInfo
+ 0x10090425 0x4b _L1e_SchedPreSyncGetIdleWorkTimer
+ 0x10090470 0x8 _L1e_SchedReturnPreSyncWorkTime
+ 0x10090478 0x29 _L1e_SchedPreSyncGetAgcWorkTimer
+ 0x100904a1 0x1b _L1e_SchedPreSyncSetState
+ 0x100904bc 0x7 _L1e_SchedPreSyncGetState
+ 0x100904c3 0xc _L1e_SchedPreSyncSetWorkCnt
+ 0x100904cf 0x12 _L1e_SchedPreSyncIsWorkSn
+ 0x100904e1 0x12 _L1e_SchedPreSyncIsWorkInd
+ 0x100904f3 0x17 _L1e_SchedPreSyncGetRfOpenInd
+ 0x1009050a 0x29 _L1e_SchedPreSyncGetAgcWorkInd
+ 0x10090533 0x24 _L1e_SchedPreSyncGetFssWorkInd
+ 0x10090557 0x2d _L1e_SchedPreSyncGetCfoWorkInd
+ 0x10090584 0x8 _L1e_SchedPreSyncGetFssWorkCnt
+ 0x1009058c 0x8 _L1e_SchedPreSyncGetRfcWorkCnt
+ 0x10090594 0x8 _L1e_SchedPreSyncSetCfgSfnInd
+ 0x1009059c 0x8 _L1e_SchedPreSyncGetCfgSfnInd
+ 0x100905a4 0x8 _L1e_SchedPreSyncGetSfnBmp
+ 0x100905ac 0xa _L1e_SchedPreSyncGetPoMarkSn
+ 0x100905b6 0x2e _L1e_SchedPreSyncGetConnWorkTimer
+ 0x100905e4 0x75 _L1e_SchedPreSyncUpdateStep
+ 0x10090659 0x8 _L1e_SchedPreSyncSetStep
+ 0x10090661 0x8 _L1e_SchedPreSyncGetStep
+ 0x10090669 0x66 _L1e_DbgPreSyncCtrlInfo
+ 0x100906cf 0x7f _L1e_SchedPreSyncCtrl
+ 0x1009074e 0x13b _zPHY_emc_tRxCirPreSyncStart
+ 0x10090889 0xa1 _zPHY_emc_RfcRxColseOperationCheck
+ 0x1009092a 0x57 _zPHY_emc_ProLpcSleepSchd
+ .text 0x10090981 0x670 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ 0x10090981 0x71 _zPHY_ecscMeas_LogMeasConfigReq
+ 0x100909f2 0x35 _zPHY_ecscMeas_LogMeasBitMask
+ 0x10090a27 0x71 _zPHY_ecscMeas_LogMeasAgeThrold
+ 0x10090a98 0x5e _zPHY_ecscMeas_LogServCellResult
+ 0x10090af6 0x3f _zPHY_ecscMeas_LogPccMeasResult
+ 0x10090b35 0x78 _zPHY_ecscMeas_LogInterCellInfo
+ 0x10090bad 0x47 _zPHY_ecsrc_LogInterMeasInd
+ 0x10090bf4 0x23 _zPHY_ecscMeas_LogConnInterReport
+ 0x10090c17 0x4f _zPHY_ecscMeas_LogSccIntraMeasFilter
+ 0x10090c66 0x1a _zPHY_ecscMeas_LogSccIntraMeasFilter2
+ 0x10090c80 0x2e _zPHY_ecscMeas_LogIntraFilter2
+ 0x10090cae 0x19 _zPHY_ecscMeas_LogInterMeasFilter
+ 0x10090cc7 0x1f _zPHY_ecscMeas_LogIntraRSSI
+ 0x10090ce6 0x16 _zPHY_ecscMeas_LogUpdateInterReportFail1
+ 0x10090cfc 0x47 _zPHY_ecscMeas_LogFilterInterReport3
+ 0x10090d43 0x33 _zPHY_ecscMeas_LogPCCIntraMeasCell
+ 0x10090d76 0x43 _zPHY_ecscMeas_LogPCCIntraMeasCell4
+ 0x10090db9 0x21 _zPHY_ecscMeas_LogSCCIntraMeasCell
+ 0x10090dda 0x85 _zPHY_ecscMeas_LogSCCIntraMeasCell2
+ 0x10090e5f 0x76 _zPHY_ecscMeas_LogSCCIntraMeasCell4
+ 0x10090ed5 0x41 _zPHY_ecscMeas_LogFilterIntraDebug
+ 0x10090f16 0x53 _zPHY_ecscMeas_LogFilterIntraDebug2
+ 0x10090f69 0x4f _zPHY_ecscMeas_LogFilterInterDebug
+ 0x10090fb8 0x39 _zPHY_ecscMeas_LogCsrSnr
+ .text 0x10090ff1 0x6f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ 0x10090ff1 0x6f _L1e_LogDlDlsDciDetInfo
+ .text 0x10091060 0x9e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ 0x10091060 0x31 _zPHY_ecsc_LogMibReqCellInfo
+ 0x10091091 0x17 _zPHY_ecsc_LogEarfchTable
+ 0x100910a8 0x2f _zPHY_ecsc_LogTpuEventMark
+ 0x100910d7 0x59 _zPHY_ecsc_LogTimeOffsetPerfreq
+ 0x10091130 0x25 _L1e_csrc_LogDrxRefreshGapCnt
+ 0x10091155 0xa0 _L1e_csrc_LogCnnDrxSchedule
+ 0x100911f5 0x15 _zPHY_ecsc_LogRecv_REL_REQ
+ 0x1009120a 0x29 _zPHY_ecsc_LogRecv_StopInterSearchMeas
+ 0x10091233 0x15 _zPHY_ecsc_LogReportMEASErr
+ 0x10091248 0x48 _zPHY_ecsc_LogGAPTime
+ 0x10091290 0x2e _zPHY_ecsc_LogInterFreq
+ 0x100912be 0x2e _zPHY_ecsc_LogHandover
+ 0x100912ec 0x24 _zPHY_ecsc_LogRecv_MULM_IRAT_IDLE_PERIOD_REP_REQ
+ 0x10091310 0x20 _zPHY_ecsc_LogRecv_FREQ_LIST_CONFIG_REQ
+ 0x10091330 0x1d _zPHY_ecsc_LogRecv_IRAT_MEAS_CONFIG_REQ
+ 0x1009134d 0x1d _zPHY_ecsc_LogRecv_IRAT_MEASURE_REPORT_INT
+ 0x1009136a 0x15 _zPHY_ecsc_LogAbortGap
+ 0x1009137f 0x3f _zPHY_ecsc_LogREG_IRAT_GAP_CONFIG_DELAY_INT
+ 0x100913be 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_REQ
+ 0x100913ec 0x15 _zPHY_ecsc_LogTPUAdjusting
+ 0x10091401 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_DELAY_INT
+ 0x1009142f 0x15 _zPHY_ecsc_LogRecv_RF_START_DEAL_PRE2SFINT
+ 0x10091444 0x15 _zPHY_ecsc_LogRecv_RF_CLOSE_DEAL_PRE2SFINT
+ 0x10091459 0x15 _zPHY_ecsc_LogRecv_RESET_REQ
+ 0x1009146e 0x2a _zPHY_ecsc_LogRecv_CELL_SEARCH_REQ
+ 0x10091498 0x15 _zPHY_ecsc_LogRecv_ABORT_CELL_SEARCH_REQ
+ 0x100914ad 0x21 _zPHY_ecsc_LogRecv_COMMON_CONFIG_REQ
+ 0x100914ce 0x15 _zPHY_ecsc_LogRecv_ABORT_MEAS_REQ
+ 0x100914e3 0x73 _zPHY_ecsc_LogRecv_PI_START_REQ
+ 0x10091556 0x15 _zPHY_ecsc_LogRecv_ONE_FREQ_END_REQ
+ 0x1009156b 0x2e _zPHY_ecsc_LogRecv_IRAT_MEAS_GAP_CONFIG_REQ
+ 0x10091599 0x1d _zPHY_ecsc_LogRecv_FREQ_SCAN_REQ
+ 0x100915b6 0x2b _zPHY_ecsc_LogPhyModeConfig
+ 0x100915e1 0x27 _zPHY_ecsc_LogReportGap
+ 0x10091608 0x3c _L1e_CsrcDb_LogDelCell
+ 0x10091644 0x18 _L1e_csrc_LogReTimeOffset
+ 0x1009165c 0x66 _zPHY_ecscDb_LogCellToDB
+ 0x100916c2 0x3d _zPHY_ecscDb_LogRefreshDB
+ 0x100916ff 0x16 _zPHY_ecscDb_LogUpdateBoundary
+ 0x10091715 0x1e _zPHY_ecsc_LogChangeMeasPeriodIdle
+ 0x10091733 0x39 _zPHY_ecsc_Log_Earfcn_BandInfo
+ 0x1009176c 0x22 _zPHY_ecscMeas_LogSrvCellReslt
+ 0x1009178e 0x1f _zPHY_ecsc_LogStandardOutput
+ 0x100917ad 0x15 _zPHY_ecsc_LogMeasPeriodChgDelay
+ 0x100917c2 0x1d _zPHY_ecsc_LogSibOrRapcConflict
+ 0x100917df 0x1d _zPHY_ecsc_LogSubFreqOffset
+ 0x100917fc 0x16 _zPHY_ecsc_LogEarfcnError
+ 0x10091812 0x76 _L1e_csrc_LogShortDrxInfo
+ 0x10091888 0x15 _L1e_csrc_LogTempComp
+ 0x1009189d 0x15 _L1e_csrc_LogTempRead
+ 0x100918b2 0x1f _L1e_csrc_LogGetFreqOffset
+ 0x100918d1 0x1d _L1e_csrc_LogSetDisableAfcReloadFlag
+ 0x100918ee 0x25 _L1e_csrc_LogC0CaliUpDate
+ 0x10091913 0x21 _L1e_csrc_LogC0CaliPeriod
+ 0x10091934 0x22 _L1e_csrc_LogC0CaliEvalue
+ 0x10091956 0x2f _L1e_csrc_LogC0Update
+ 0x10091985 0x1e _L1e_csrc_LogC0Debug
+ 0x100919a3 0x27 _L1e_csrc_LogC0CalRsrp
+ 0x100919ca 0x1f _L1e_csrc_LogC0CalAfc
+ 0x100919e9 0x21 _L1e_csrc_LogC0UtcTimeExp
+ 0x10091a0a 0x15 _L1e_csrc_LogC0CaliRestart
+ 0x10091a1f 0x21 _L1e_csrc_LogNewUtcError
+ .text 0x10091a40 0x276 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ 0x10091a40 0x4c _zPHY_ecsm_LogMeasHwInfo
+ 0x10091a8c 0x79 _zPHY_ecsmNormal_LogUpdateRes
+ 0x10091b05 0x16 _zPHY_ecsrm_BuffLogSlaveMaxBdySub
+ 0x10091b1b 0x22 _zPHY_ecsrm_LogSetMeasAge
+ 0x10091b3d 0x19 _zPHY_ecsrm_LogBuffFbRelatn
+ 0x10091b56 0x17 _zPHY_ecsrm_LogMeasStartSubFrame
+ 0x10091b6d 0x2b _zPHY_ecsrm_LogBuffCellPara
+ 0x10091b98 0x3f _zPHY_ecsrm_LogBuffCommPara
+ 0x10091bd7 0x2d _zPHY_ecsrm_LogMeasResultRead
+ 0x10091c04 0x18 _zPHY_ecsrm_LogBuffMulmsubf
+ 0x10091c1c 0x29 _zPHY_ecsrm_LogBuffSortCell
+ 0x10091c45 0x27 _zPHY_ecsrm_LogBuffBdyCell
+ 0x10091c6c 0x27 _zPHY_ecsrm_LogBuffwait
+ 0x10091c93 0x23 _zPHY_ecsrm_LogBuffMeasConfig
+ .text 0x10091cb6 0x378 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ 0x10091cb6 0x15 _zPHY_ecsccs_LogRSStart
+ 0x10091ccb 0x27 _zPHY_ecsccs_LogSearchReq
+ 0x10091cf2 0x41 _zPHY_ecsccs_LogCellInfo
+ 0x10091d33 0x1a _zPHY_ecsc_LogRecv_PBCH
+ 0x10091d4d 0x24 _zPHY_ecsccs_LogMeasStart
+ 0x10091d71 0x26 _zPHY_ecsccs_LogSendTPUAdjust
+ 0x10091d97 0x30 _zPHY_ecsccs_LogCellRank
+ 0x10091dc7 0x1d _zPHY_ecsccs_LogNoAppointedCell
+ 0x10091de4 0x42 _zPHY_ecsccs_LogICPReportResultRIGHT
+ 0x10091e26 0x18 _zPHY_ecsccs_LogIcpBchCell
+ 0x10091e3e 0x15 _zPHY_ecsccs_LogNoCell
+ 0x10091e53 0x44 _zPHY_ecsccs_LogStartResumeSrv
+ 0x10091e97 0x4b _zPHY_ecsccs_LogNewPlmnRS_ReportStatus
+ 0x10091ee2 0x29 _zPHY_ecsccs_LogNewPlmnRS_SearchFinished
+ 0x10091f0b 0x1f _zPHY_ecsccs_LogNewPlmnRS_MeasFinished
+ 0x10091f2a 0x3c _zPHY_ecsccs_LogResumeServBCHBoundry
+ 0x10091f66 0x26 _zPHY_ecsccs_LogCurTime2PiTime
+ 0x10091f8c 0x30 _zPHY_ecsccs_LogReg_PLMN_PERIODICAL_TPU_INT
+ 0x10091fbc 0x21 _zPHY_ecsccs_LogRecv_PLMN_SEARCH_TIME_EVENT
+ 0x10091fdd 0x51 _zPHY_ecsccs_LogWriteBch2CsrDb
+ .text 0x1009202e 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ 0x1009202e 0x29 _L1e_LogDlRxMbsfnCirInfo
+ 0x10092057 0x52 _L1e_LogRxMbmsCirAreaInfo
+ 0x100920a9 0x9f _L1e_LogRxCirDataInfo
+ 0x10092148 0x42 _L1e_LogRxMbmsCirSearchInfo
+ 0x1009218a 0x22 _L1e_LogRxBetaInfo
+ 0x100921ac 0x1a _L1e_LogRxCfoCfgInfo
+ .text 0x100921c6 0xb03 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ 0x100921c6 0x17 _zPHY_emulm_LogCsrSlaveStateChange
+ 0x100921dd 0x17 _zPHY_emulm_LogCsrSlaveSYNStateChange
+ 0x100921f4 0x20 _zPHY_emulm_LogCsrcGapStartOffset
+ 0x10092214 0x2c _zPHY_emulm_LogCsrcFreeTimeRep
+ 0x10092240 0x17 _zPHY_emulm_LogCsrcSetModeReq
+ 0x10092257 0x17 _zPHY_emulm_LogCsrcMeasSche
+ 0x1009226e 0x26 _zPHY_emulm_LogCsrcMeasReportProct
+ 0x10092294 0x2f _zPHY_emulm_LogCsrcMeasReportInt
+ 0x100922c3 0x16 _zPHY_emulm_LogMeasNoCell
+ 0x100922d9 0x18 _zPHY_emulm_LogMeasCell
+ 0x100922f1 0x19 _zPHY_emulm_LogMeasNoCellReport
+ 0x1009230a 0x73 _zPHY_emulm_LogMeasRight
+ 0x1009237d 0x16 _zPHY_emulm_LogASynSearch
+ 0x10092393 0x2a _zPHY_emulm_LogGapStartOffset
+ 0x100923bd 0x17 _zPHY_emulm_LogSubFrameOnOff
+ 0x100923d4 0x2a _zPHY_emulm_LogGapEndOffset
+ 0x100923fe 0x56 _zPHY_emulm_LogRegCsrIratGapStart
+ 0x10092454 0x94 _zPHY_emulm_LogRegCsrGapEnd
+ 0x100924e8 0x56 _zPHY_emulm_LogRegCsrRfClose
+ 0x1009253e 0x17 _zPHY_emulm_LogBlackList
+ 0x10092555 0x1c _zPHY_emulm_LogRemainTime
+ 0x10092571 0x20 _zPHY_emulm_LogSynInterSearchMeas
+ 0x10092591 0x22 _zPHY_emulm_LogRegIratPlmnMeas
+ 0x100925b3 0x22 _zPHY_emulm_LogRegSlaveAbortGap
+ 0x100925d5 0x1d _zPHY_emulm_LogIratAbortGap
+ 0x100925f2 0x1d _zPHY_emulm_LogIratMeasDone
+ 0x1009260f 0x1e _zPHY_emulm_LogGapPosition
+ 0x1009262d 0x4d _zPHY_emulm_LogGapTime
+ 0x1009267a 0x4d _zPHY_emulm_LogGapTime1
+ 0x100926c7 0x4d _zPHY_emulm_LogGapTime2
+ 0x10092714 0x17 _zPHY_emulm_LogPbchInGap
+ 0x1009272b 0x28 _zPHY_emulm_LogEnRfcEventTable
+ 0x10092753 0x54 _zPHY_emulm_Log6MSRfcEventTableInGap
+ 0x100927a7 0x39 _zPHY_emulm_LogrRfStartDeal
+ 0x100927e0 0x39 _zPHY_emulm_LogrRfEndDeal
+ 0x10092819 0x36 _zPHY_emulm_LogRefreshDataBase1
+ 0x1009284f 0x18 _zPHY_emulm_LogtpuAdjust
+ 0x10092867 0x18 _zPHY_emulm_LogtpuCantAdjust
+ 0x1009287f 0x29 _zPHY_emulm_LogPssAdjust
+ 0x100928a8 0x15 _zPHY_emulm_LogRecvSlaveAbortGap
+ 0x100928bd 0x15 _zPHY_emulm_LogRecvCsrAbortGap
+ 0x100928d2 0x15 _zPHY_emulm_LogRecvCsrTpuIratGap
+ 0x100928e7 0x15 _zPHY_emulm_LogRecvCsrTpuIratGapStart
+ 0x100928fc 0x65 _zPHY_emulm_LogSlaveMeasureFlow
+ 0x10092961 0x15 _zPHY_emulm_LogRecvCsrTpuIratPlmnMeas
+ 0x10092976 0x15 _zPHY_emulm_LogRecvCsrTpuUpdateCounter
+ 0x1009298b 0x15 _zPHY_emulm_LogCsrcRecvGapEndOffsetCfg
+ 0x100929a0 0x38 _zPHY_emulm_LogCsrcGatValidCellFbInfo
+ 0x100929d8 0x21 _zPHY_emulm_LogCsrcTimeDelayIntEvent
+ 0x100929f9 0x2c _zPHY_emulm_LogCsrcAfterAdjTpu
+ 0x10092a25 0x31 _L1e_Mulm_LogNeedSearchAndMeas
+ 0x10092a56 0x19 _zPHY_emulm_LogCsrcStartEarfcnInfo
+ 0x10092a6f 0x2f _zPHY_emulm_LogCsrcEndEarfcnInfo
+ 0x10092a9e 0x67 _zPHY_emulm_LogCsrcGapAndSssInfo
+ 0x10092b05 0x6a _zPHY_emulm_LogCsrcHbTimeInfo
+ 0x10092b6f 0x2c _zPHY_emulm_LogCsrcSssBufferAndGap
+ 0x10092b9b 0x21 _zPHY_emulm_LogCsrcAgcStart
+ 0x10092bbc 0x39 _zPHY_emulm_LogCsrcSlaveSssProcessInfo
+ 0x10092bf5 0x43 _zPHY_emulm_LogBuffCheckOpenTimePeriod
+ 0x10092c38 0x21 _zPHY_emulm_LogGapCoverBuffCheck
+ 0x10092c59 0x1a _zPHY_emulm_LogMeasFilter
+ 0x10092c73 0x16 _zPHY_emulm_LogUpdateReportFail
+ 0x10092c89 0x26 _zPHY_emulm_LogSetFilterFact
+ 0x10092caf 0x1a _zPHY_emulm_LogGetFilterFact
+ .text 0x10092cc9 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ 0x10092cc9 0x91 _L1e_logCmnMbmsMbsfnSubfListInfo
+ 0x10092d5a 0x8f _L1e_LogCmnMbmsMbsfnAllocInfo
+ .text 0x10092de9 0x10f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ 0x10092de9 0x35 _zPHY_ecsrc_LogSlaveSearchMode
+ 0x10092e1e 0x34 _zPHY_ecsrc_LogRecvUpdateCounterCnf
+ 0x10092e52 0x64 _zPHY_ecsrc_LogPssTpuAdjust3
+ 0x10092eb6 0x26 _zPHY_ecsrc_LogModifyRfCfgInfo
+ 0x10092edc 0x85 _zPHY_ecsrc_LogIsRfOpen
+ 0x10092f61 0x4f _zPHY_ecsrs_LogCommonInfor
+ 0x10092fb0 0x36 _zPHY_ecsrs_LogInterFreqChange
+ 0x10092fe6 0x2e _zPHY_ecsrs_LogGetHwConfigMode
+ 0x10093014 0x34 _zPHY_ecsrs_LogGetReadAndConfigIndex
+ 0x10093048 0x18 _zPHY_ecsrs_LogTFConfirmSearchMode
+ 0x10093060 0x19 _zPHY_ecsrs_LogGetSubTime
+ 0x10093079 0x16 _zPHY_ecsrs_LogSubFrameOnOff
+ 0x1009308f 0xba _zPHY_ecsrs_LogCsPssPro
+ 0x10093149 0x48 _zPHY_ecsrs_LogGetPssStartTime
+ 0x10093191 0x14 _zPHY_ecsrs_LogCsCfoProcEnd
+ 0x100931a5 0x9a _zPHY_ecsrs_LogCsSssPro
+ 0x1009323f 0x3e _zPHY_ecsrpss_LogAdjustPssStartTime
+ 0x1009327d 0x1c _zPHY_ecsrpss_LogUrfcnFreqIdx
+ 0x10093299 0x57 _zPHY_ecsrpss_LogSearchResult
+ 0x100932f0 0x5f _zPHY_ecsrpss_LogPssDb
+ 0x1009334f 0x1b _zPHY_ecsrpss_LogSendRfcOffset
+ 0x1009336a 0x2a _zPHY_ecsrpss_LogCalRedoCfoBoundary
+ 0x10093394 0x2a _zPHY_ecsrpss_LogFilterFinger
+ 0x100933be 0x4d _zPHY_ecsrSss_LogStartFinger
+ 0x1009340b 0x3c _zPHY_ecsrSss_LogStartTime
+ 0x10093447 0x4f _zPHY_ecsrSss_LogStartFingerAll
+ 0x10093496 0x4a _zPHY_ecsrSss_LogSLAVE_HWStart
+ 0x100934e0 0x22 _zPHY_ecsrSss_LogGetRfcEnableInfo
+ 0x10093502 0x27 _zPHY_ecsrSss_LogReadFlagInfor
+ 0x10093529 0xc5 _zPHY_ecsrSss_LogThreshold
+ 0x100935ee 0x5d _zPHY_ecsrSss_LogResultInfo
+ 0x1009364b 0x65 _zPHY_ecsrSss_LogSssFingerReorder
+ 0x100936b0 0x18 _zPHY_ecsrSss_LogAdjustSssFddProc
+ 0x100936c8 0x2e _zPHY_ecsrSss_LogSssState
+ 0x100936f6 0x62 _zPHY_ecsrSss_LogStartFingerAfterSort
+ 0x10093758 0x14 _zPHY_ecsrSss_LogGetSssStartInfo
+ 0x1009376c 0x27 _zPHY_ecsrCfo_LogFreqOffset
+ 0x10093793 0x6a _zPHY_ecsrCfo_LogSLAVE_HWStart
+ 0x100937fd 0x28 _zPHY_ecsrCfo_LogCfoResultMerge
+ 0x10093825 0x41 _zPHY_ecsrIc_LogCellFlag
+ 0x10093866 0x7e _zPHY_ecsrIc_LogCoverInfo
+ 0x100938e4 0x60 _zPHY_ecsrIc_LogCellInfo
+ 0x10093944 0xa9 _zPHY_ecsrs_LogCfgIcFifo
+ 0x100939ed 0x191 _zPHY_ecsrs_LogCfgIc
+ 0x10093b7e 0x136 _zPHY_ecsrs_LogCfgPssHw
+ 0x10093cb4 0x5f _zPHY_ecsrs_LogCfgCfoHw
+ 0x10093d13 0x138 _zPHY_ecsrs_LogCfgSssHw
+ 0x10093e4b 0x20 _zPHY_ecsrSss_LogCheckCfoValid
+ 0x10093e6b 0x2d _L1e_csrs_LogSetFtErrorList
+ 0x10093e98 0x25 _L1e_csrs_LogSetFreqOffsetAge
+ 0x10093ebd 0x1e _L1e_csrs_LogGetFreqOffset
+ .text 0x10093edb 0x239 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ 0x10093edb 0x30 _zPHY_ecsm_LogBlackCell
+ 0x10093f0b 0xba _zPHY_ecsm_LogRfcOpenTime
+ 0x10093fc5 0x4d _zPHY_ecsm_LogRfcOpenTimeFddIdle
+ 0x10094012 0x54 _zPHY_ecsm_LogTDDRfcEventTab
+ 0x10094066 0x14 _zPHY_ecsm_LogRecv_RESET_REQ
+ 0x1009407a 0x32 _zPHY_ecsm_LogMeasStart
+ 0x100940ac 0x14 _zPHY_ecsm_Logrec_MEASRESET
+ 0x100940c0 0x16 _zPHY_ecsm_LogRecv_UnknownMsg
+ 0x100940d6 0x1e _zPHY_ecsm_Buff_LogRfcOpenTime
+ 0x100940f4 0x20 _zPHY_ecsm_LogRfcEventTablength
+ .text 0x10094114 0x3c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ 0x10094114 0xc _zPHY_GetUINT32BitsField
+ 0x10094120 0x27 _zPHY_GetUINT64BitsField
+ 0x10094147 0x1f _zPHY_GetUINT16DivCeilValue
+ 0x10094166 0x22 _zPHY_GetUINT32DivCeilValue
+ 0x10094188 0x28 _zPHY_GetSINT16DivFloorValue
+ 0x100941b0 0x2e _zPHY_GetSINT32DivFloorValue
+ 0x100941de 0x16 _zPHY_BinarySearch
+ 0x100941f4 0x132 _zPHY_Pow2
+ 0x10094326 0x5b _zPHY_Fixpoint2Float
+ 0x10094381 0x88 _zPHY_Float2Fixpoint
+ 0x10094409 0x6c _zPHY_DivRet2Fixpoint7510
+ 0x10094475 0x57 _zPHY_DivRet2Fixpoint
+ 0x100944cc 0x10 _zPHY_LteaDelay
+ .text 0x100944dc 0x60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x100944dc 0x57 _zPHY_setRxMaskFlag
+ 0x10094533 0x9 _zPHY_getRxMaskFlag
+ .text 0x1009453c 0x95 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x1009453c 0x37 _L1l_CmnAssert
+ 0x10094573 0x5a _zPHY_RecvUnknownMsg
+ 0x100945cd 0x4 _zPHY_create_handler
+ .text 0x100945d1 0x28c6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ 0x100945d1 0x2f _zPHY_eula_PucchSrsRelease
+ 0x10094600 0x6d _zPHY_eula_SetSrsScale
+ 0x1009466d 0x58 _zPHY_eula_LtxParas_QDivNRsZcSrs
+ 0x100946c5 0x31f _zPHY_eula_UpdataSrsBGParas_Cell
+ 0x100949e4 0xd0 _zPHY_eula_UpdataSrsBGParas_APSfOffset
+ 0x10094ab4 0x19d _zPHY_eula_UpdataSrsBGParas_APTiming
+ 0x10094c51 0x159 _zPHY_eula_UpdataSrsBGParas_APParaCalc_PTS
+ 0x10094daa 0x29b _zPHY_eula_UpdataSrsBGParas_APParaCalc
+ 0x10095045 0x3d _zPHY_eula_UpdataSrsBGParas_APParaAssign
+ 0x10095082 0x62 _zPHY_eula_UpdataSrsBGParas_AP
+ 0x100950e4 0x2f6 _zPHY_eula_UpdataSrsBGParas_PTiming
+ 0x100953da 0x15a _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc_PTS
+ 0x10095534 0x219 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc
+ 0x1009574d 0x118 _zPHY_eula_UpdataSrsBGParas_PHopParaCalc_PTS
+ 0x10095865 0x27d _zPHY_eula_UpdataSrsBGParas_PHopParaCalc
+ 0x10095ae2 0x6d _zPHY_eula_UpdataSrsBGParas_P
+ 0x10095b4f 0xb2 _zPHY_eula_UpdataSrsBGParas
+ 0x10095c01 0xe4 _zPHY_eula_CommSrsProc
+ 0x10095ce5 0x22e _zPHY_eula_ScheApSrs
+ 0x10095f13 0x27 _zPHY_eula_WipeSrsInRarBasedPusch
+ 0x10095f3a 0x80 _zPHY_eula_DetermineSrsCellSpecStateInPusch
+ 0x10095fba 0xbe _zPHY_eula_ProcConflictOfSrsAndPucchPusch_OneCell
+ 0x10096078 0x50 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell
+ 0x100960c8 0x4d _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschScell
+ 0x10096115 0x86 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_PuschScell
+ 0x1009619b 0x120 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch
+ 0x100962bb 0x136 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_Pucch_PuschScell
+ 0x100963f1 0x12e _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch_PuschScell
+ 0x1009651f 0x2 _zPHY_eula_ProcConflictOfSrsAndPucchPusch
+ 0x10096521 0x5e _zPHY_eula_ScheSrsInPusch_AntMapping
+ 0x1009657f 0x7d _zPHY_eula_ScheSrsInPusch
+ 0x100965fc 0xb1 _zPHY_eula_ProcConflictOfSrsAndPucch_OneCell
+ 0x100966ad 0x2 _zPHY_eula_ProcConflictOfSrsAndPucch
+ 0x100966af 0x1d _zPHY_eula_ProcConflictOfSrsAndDrx
+ 0x100966cc 0x4b _zPHY_eula_ScheSrsInNonPusch
+ 0x10096717 0x4e _zPHY_eula_ProcSrsInDurationMode0
+ 0x10096765 0x4c _zPHY_eula_GetPtsState
+ 0x100967b1 0xbe _zPHY_eula_CalcApSrsParas
+ 0x1009686f 0xbe _zPHY_eula_CalcPNonHopSrsParas
+ 0x1009692d 0x389 _zPHY_eula_CalcPHopSrsParas
+ 0x10096cb6 0x46 _zPHY_eula_CalcSrsParas
+ 0x10096cfc 0x70 _zPHY_eula_InitSrsDB
+ 0x10096d6c 0x4e _zPHY_eula_SrsSrcRelease
+ 0x10096dba 0x18 _zPHY_eula_ClearApSrsSche
+ 0x10096dd2 0xbc _zPHY_eula_CalcnSrs
+ 0x10096e8e 0x9 _zPHY_eula_SrsAntennaSelect
+ .text 0x10096e97 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x10096e97 0x53 _zPHY_edla_GetPhichGrpNum
+ 0x10096eea 0xb _zPHY_edla_GetPhichRegNum
+ 0x10096ef5 0x10b _zPHY_edla_GetNextSubFrmPhichInfo
+ 0x10097000 0x100 _zPHY_edla_UpdateIphichInfo
+ 0x10097100 0x10 _zPHY_edla_GetPhichInfo
+ 0x10097110 0xc9 _zPHY_edla_GetPerPhichSeq
+ 0x100971d9 0x95 _zPHY_edla_GetPerTBPhichSeq
+ 0x1009726e 0x11 _zPHY_edla_GetPhichSeq
+ 0x1009727f 0x23 _zPHY_edla_GetHichSubFreq
+ 0x100972a2 0xbb _zPHY_edla_PhichProc
+ 0x1009735d 0x45 _zPHY_edla_UpdatePhichInfo
+ 0x100973a2 0xb _zPHY_edla_HiValidJudgment
+ .text 0x100973ad 0x1540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x100973ad 0x5d _zPHY_edfe_SupCommonCalAGC
+ 0x1009740a 0x72 _zPHY_edfe_SupFastAGC
+ 0x1009747c 0xd9 _zPHY_edfe_SupNotSyncAGC
+ 0x10097555 0x295 _zPHY_edfe_SupNotSyncAGCAnt0And1
+ 0x100977ea 0x18 _zPHY_edfe_GetAgcReloadVal
+ 0x10097802 0x11 _zPHY_edfe_ConfigAgcReloadVal
+ 0x10097813 0x16 _zPHY_edfe_ACP405AgcGainConfig
+ 0x10097829 0xac _zPHY_edfe_SupAGCLostLockMethod
+ 0x100978d5 0x3f _zPHY_edfe_InitAgcPara
+ 0x10097914 0x1a _zPHY_edfe_ResetAgcCoverJudgePara
+ 0x1009792e 0x24 _zPHY_edfe_InitAgcDagcGain
+ 0x10097952 0x155 _zPHY_edfe_JudgeAgcCoverOpt
+ 0x10097aa7 0x67 _zPHY_edfe_CalcAGCForBandChange
+ 0x10097b0e 0xb8 _zPHY_edfe_GetNextAGCInitGain
+ 0x10097bc6 0x9b _zPHY_edfe_CalcAGCNewMethodAnt
+ 0x10097c61 0x9d _zPHY_edfe_CalcAGCGainNewMethod
+ 0x10097cfe 0x139 _zPHY_edfe_SupHandleAGCOpt
+ 0x10097e37 0x51 _zPHY_edfe_FindOldestPosInAgcGainDB
+ 0x10097e88 0x9 _zPHY_edfe_SupResetAGCLoopOpt
+ 0x10097e91 0xb7 _zPHY_edfe_NotSyncToSyncSetAgc
+ 0x10097f48 0x3d _zPHY_edfe_SyncToNotSyncSetAgc
+ 0x10097f85 0x10b _zPHY_edfe_UpdateSCCAGC
+ 0x10098090 0x12 _zPHY_edfe_CompAgcDBTimeInfo
+ 0x100980a2 0xc7 _zPHY_edfe_IratHandoverAfcManage
+ 0x10098169 0x71 _zPHY_edfe_SupSaveSlaveAfcCtrl
+ 0x100981da 0xfd _zPHY_edfe_IratHandoverCordicManage
+ 0x100982d7 0x8e _zPHY_edfe_IratCordicManage
+ 0x10098365 0x6e _zPHY_edfe_SupSaveSlaveCordicCtrl
+ 0x100983d3 0x77 _zPHY_edfe_FSNewAgcIntHandle
+ 0x1009844a 0x72 _zPHY_edfe_InitSubFramePwrDB
+ 0x100984bc 0x263 _zPHY_edfe_SupSemiStaticAgcNew
+ 0x1009871f 0x26 _zPHY_edfe_MbsfnAgcDbInit
+ 0x10098745 0xc _zPHY_edfe_MbsfnAgcParaConfig
+ 0x10098751 0x9f _zPHY_edfe_SupCalMbsfnRegionAgc
+ 0x100987f0 0xb6 _zPHY_edfe_SupHandleMbsfnAGC
+ 0x100988a6 0x2f _zPHY_edfe_NewMbsfnAGCGainInit
+ 0x100988d5 0x1 _zPHY_edfe_MbsfnAgcCoverJudge
+ 0x100988d6 0x17 _zPHY_edfe_MbsfnAgcGainConfig
+ .text 0x100988ed 0x251 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ 0x100988ed 0x1ae _zPHY_eulpc_SrsPowCalc
+ 0x10098a9b 0xa3 _zPHY_eulpc_SrsPowCtrl
+ .text 0x10098b3e 0x1173 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ 0x10098b3e 0x1 _zPHY_euls_L_Entry
+ 0x10098b3f 0x34c _zPHY_euls_Entry
+ 0x10098e8b 0x2cc _zPHY_euls_TPU_INT1_RARGrantProcess
+ 0x10099157 0x2f8 _zPHY_euls_TPU_INT1_DCIProcess
+ 0x1009944f 0x435 _zPHY_euls_TPU_INT1_Step1_process
+ 0x10099884 0x191 _zPHY_euls_TPU_INT1_Step2_process
+ 0x10099a15 0x8b _zPHY_euls_GetDediCfgParas
+ 0x10099aa0 0x7f _zPHY_euls_GetSCellCfgParas
+ 0x10099b1f 0x80 _zPHY_euls_GetCommCfgParas
+ 0x10099b9f 0x10e _zPHY_euls_GetHandoverCfgParas
+ 0x10099cad 0x4 _zPHY_euls_PuschAntennaSelect
+ .text 0x10099cb1 0x2362 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x10099cb1 0x2c _L1e_FS_SwReset
+ 0x10099cdd 0x16 _L1e_FS_Init
+ 0x10099cf3 0x32 _L1e_FS_FreqScanEnRfcNotSyncTable
+ 0x10099d25 0xb3 _L1e_FS_HandleFreqscanAddSearchResult
+ 0x10099dd8 0x9c _L1e_FS_CalcSssAgcGainCompen
+ 0x10099e74 0xec _L1e_FS_FreqScanAddSearchResultSort
+ 0x10099f60 0x30 _L1e_FS_SetFSResult
+ 0x10099f90 0x110 _L1e_FS_FindFSEarfcnToReport
+ 0x1009a0a0 0x34 _L1e_FS_FindEarfcnForSearch
+ 0x1009a0d4 0x36 _L1e_FS_SendFsCnf
+ 0x1009a10a 0x8f _L1e_FS_BufForSearch
+ 0x1009a199 0x86 _L1e_Fs_CreateList_Band38_Bak
+ 0x1009a21f 0x6c _L1e_Fs_CreateListBak
+ 0x1009a28b 0x6a _L1e_Fs_IsFreqPointValid
+ 0x1009a2f5 0x36 _L1e_Fs_MaxPeakSetZero
+ 0x1009a32b 0x2a _L1e_Fs_GetMaxValue
+ 0x1009a355 0x28 _L1e_Fs_GetMinValue
+ 0x1009a37d 0x1c _L1e_FS_LogNumPrint
+ 0x1009a399 0x33 _L1e_Fs_SetProfileInfo
+ 0x1009a3cc 0x34 _L1e_Fs_DelList
+ 0x1009a400 0x6 _L1e_FS_ClearPssResultList
+ 0x1009a406 0x6 _L1e_FS_ClearMeanPowerResultList
+ 0x1009a40c 0xe _L1e_FS_SetRedoInfo
+ 0x1009a41a 0xf4 _L1e_FS_GetAllGainProfileInfo
+ 0x1009a50e 0x63 _L1e_FS_GetAllProfileInfo
+ 0x1009a571 0xcf _L1e_Fs_GetAllValidFreqPoint
+ 0x1009a640 0x33 _L1e_FS_SetBandInfo
+ 0x1009a673 0xf _L1e_FS_SetSpecialBandInfo
+ 0x1009a682 0x5c _L1e_FS_SetOverLapFreqBand
+ 0x1009a6de 0x1bc _L1e_FS_GenFreqBand
+ 0x1009a89a 0x1e _L1e_FS_CfgRfcNotSyncTable
+ 0x1009a8b8 0x51 _L1e_FS_ReqMsgHandle
+ 0x1009a909 0x13 _L1e_FS_SetFreqPoint
+ 0x1009a91c 0x74 _L1e_FS_InsertPssResult
+ 0x1009a990 0xe3 _L1e_FS_SetIniCsrInfo
+ 0x1009aa73 0xdf _L1e_FS_SetFsRslt
+ 0x1009ab52 0x8b _L1e_FS_ResultSort
+ 0x1009abdd 0x1b _L1e_FS_PlmnPeriodTpuInPro
+ 0x1009abf8 0xd2 _L1e_FS_SetDisctRslt
+ 0x1009acca 0x21 _L1e_FS_SeekToHalfFram
+ 0x1009aceb 0xce _L1e_FS_DoPss
+ 0x1009adb9 0x109 _L1e_FS_PssNext100KFreqPointNoPreCFO
+ 0x1009aec2 0x61 _L1e_FS_PssNext100KFreqPointPreCFO
+ 0x1009af23 0x35 _L1e_FS_PssNext100KFreqPoint
+ 0x1009af58 0x35 _L1e_FS_PssNextAgcGain
+ 0x1009af8d 0x1b _L1e_FS_PssNextProfile
+ 0x1009afa8 0x6c _L1e_FS_InitFreqOffset
+ 0x1009b014 0x49 _L1e_FS_PssNextFreqOffset
+ 0x1009b05d 0x3d _L1e_FS_PreFreqOffset
+ 0x1009b09a 0x136 _L1e_FS_Pss100KResult
+ 0x1009b1d0 0x3d _L1e_FS_DiscreteFreqOffsetLoop
+ 0x1009b20d 0x7f _L1e_FS_PssDisctResult
+ 0x1009b28c 0x1b _L1e_FS_PssProfileLoopStart
+ 0x1009b2a7 0x54 _L1e_FS_NextBand
+ 0x1009b2fb 0x1b _L1e_FS_Pss500KFreqPointLoopStart
+ 0x1009b316 0x31 _L1e_FS_PssNext500KFreqPoint
+ 0x1009b347 0x11 _L1e_FS_GetFsMode
+ 0x1009b358 0x56 _L1e_FS_SetFsTempResult
+ 0x1009b3ae 0xa4 _L1e_FS_FreqScanCellSearch
+ 0x1009b452 0x4a _L1e_FS_PssOneFreqPointStart
+ 0x1009b49c 0x2b _L1e_FS_PssAgcGainLoopStart
+ 0x1009b4c7 0x6a _L1e_FS_Pss100KFreqPointLoopStart
+ 0x1009b531 0xc _L1e_FS_PssNeedOffset
+ 0x1009b53d 0xd _L1e_FS_PssNeedDo100K
+ 0x1009b54a 0xe _L1e_FS_BandLoopStart
+ 0x1009b558 0x2b _L1e_FS_PssSkipPiTime
+ 0x1009b583 0x1e _L1e_FS_PssSeekToSlaveGap
+ 0x1009b5a1 0x23 _L1e_FS_SeekToWorkTime
+ 0x1009b5c4 0x24 _L1e_FS_MpFreqPointLoopStart
+ 0x1009b5e8 0x7b _L1e_FS_SegmentInfoSort
+ 0x1009b663 0x93 _L1e_FS_SetSegmentInfo
+ 0x1009b6f6 0xd3 _L1e_FS_SetSegmentInfoEnd
+ 0x1009b7c9 0xb4 _L1e_FS_FreqSegmentAlorigthm
+ 0x1009b87d 0x61 _L1e_FS_SetBackupFreqOffset
+ 0x1009b8de 0x62 _L1e_FS_FreqSegment
+ 0x1009b940 0x2f _L1e_FS_MpNextFreqPoint
+ 0x1009b96f 0x24 _L1e_FS_MpOneFreqPointStart
+ 0x1009b993 0x40 _L1e_FS_MeanPowerCal
+ 0x1009b9d3 0xc _L1e_FS_MpMethod
+ 0x1009b9df 0x11 _L1e_FS_PssMethod
+ 0x1009b9f0 0x14 _L1e_FS_PLMN
+ 0x1009ba04 0xb _L1e_FS_SetState
+ 0x1009ba0f 0x8 _L1e_FS_GetState
+ 0x1009ba17 0x34 _L1e_FS_MpStart
+ 0x1009ba4b 0x15 _L1e_FS_SetCnfInfo
+ 0x1009ba60 0x68 _L1e_FS_OverlapSegment
+ 0x1009bac8 0x89 _L1e_FS_Report2PsResult
+ 0x1009bb51 0x1b _l1e_FS_MPEnvelopeSort
+ 0x1009bb6c 0x22 _L1e_FS_MpEnvelope
+ 0x1009bb8e 0xa _L1e_FS_PssNeedReDo500K
+ 0x1009bb98 0xc _L1e_FS_Redo500KStart
+ 0x1009bba4 0xf _L1e_FS_PssReDo500KNextProfile
+ 0x1009bbb3 0x1c _L1e_FS_PssReDo500KFpLoopStart
+ 0x1009bbcf 0x43 _L1e_Fs_ReDoGetAllValidFreqPoint
+ 0x1009bc12 0x24 _L1e_FS_PssReDoNext500KFreqPoint
+ 0x1009bc36 0xa _L1e_FS_PssNeedAgc
+ 0x1009bc40 0x9 _L1e_FS_AgcLoopStart
+ 0x1009bc49 0x45 _L1e_FS_AgcNextFreqPoint
+ 0x1009bc8e 0x21 _L1e_FS_BeforeAgc
+ 0x1009bcaf 0x16 _L1e_FS_AddAgcWaitTime
+ 0x1009bcc5 0xc5 _L1e_FS_AgcProc
+ 0x1009bd8a 0x17 _L1e_FS_PssNeedReDo100K
+ 0x1009bda1 0x17 _L1e_FS_IsSerialMode
+ 0x1009bdb8 0x35 _L1e_FS_IsDiscreteMode
+ 0x1009bded 0x2b _L1e_FS_DiscretePssStart
+ 0x1009be18 0x12 _L1e_FS_DiscretePssSnrBackup
+ 0x1009be2a 0xc _L1e_FS_DiscretePssSnrClear
+ 0x1009be36 0x31 _L1e_FS_CheckSearchMode
+ 0x1009be67 0x192 _L1e_FS_CfgRfAndGetMp
+ 0x1009bff9 0x1a _L1e_FS_MpSeekWorkTime
+ .text 0x1009c013 0x345b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x1009c013 0x119 _zPHY_euls_UlGrantReception
+ 0x1009c12c 0x13d _zPHY_euls_HARQEntity
+ 0x1009c269 0x332 _zPHY_euls_HARQProcess
+ 0x1009c59b 0x57 _zPHY_euls_ProInitial
+ 0x1009c5f2 0x31 _zPHY_euls_InitUlHarqIDInHarqDB
+ 0x1009c623 0x141 _zPHY_euls_UlHarqProcessCtrl
+ 0x1009c764 0x364 _zPHY_euls_DecodeDci4
+ 0x1009cac8 0x3bf _zPHY_euls_DecodeDci0
+ 0x1009ce87 0x104 _zPHY_euls_DecodeDci
+ 0x1009cf8b 0x4f _zPHY_euls_DecodePucchTPC
+ 0x1009cfda 0x8f _zPHY_euls_GetMsg3SendSubFrmNo
+ 0x1009d069 0x99 _zPHY_euls_DecodeRARGrant
+ 0x1009d102 0xaf _zPHY_euls_ReportUlGrantParas
+ 0x1009d1b1 0xa8 _zPHY_euls_ReportUlGrantToPS
+ 0x1009d259 0xab _zPHY_euls_CalcLUtrPara
+ 0x1009d304 0x9c _zPHY_euls_CalcLTxPara
+ 0x1009d3a0 0x129 _zPHY_euls_PuschPrmFHType1
+ 0x1009d4c9 0x1df _zPHY_euls_PuschPrmFHType2
+ 0x1009d6a8 0x10 _zPHY_euls_CalcX2Cinit
+ 0x1009d6b8 0x62 _zPHY_euls_CalcNPuschSymb
+ 0x1009d71a 0x148 _zPHY_euls_DecodeModuleCodeSchem
+ 0x1009d862 0x25 _zPHY_euls_Nchoosek
+ 0x1009d887 0x1b5 _zPHY_euls_DecodeRIV_Ratype1
+ 0x1009da3c 0x75 _zPHY_euls_DecodeRIV
+ 0x1009dab1 0x44 _zPHY_euls_GetRbAssignBitWidInDci4
+ 0x1009daf5 0x43 _zPHY_euls_GetRbAssignBitWidInDci0
+ 0x1009db38 0xc9 _zPHY_euls_GetPuschPosByPdcchOrPhichPos
+ 0x1009dc01 0x59 _zPHY_euls_AddMsg4DetectStartEvent
+ 0x1009dc5a 0x5a _zPHY_euls_AddMsg4DetectStopEvent
+ 0x1009dcb4 0x1f _zPHY_euls_AddMsg4DetectWinEvents
+ 0x1009dcd3 0x2d _zPHY_euls_ModifyMsg4DetectWinEvents
+ 0x1009dd00 0xde _zPHY_euls_AddMsg3LtxDealEvent
+ 0x1009ddde 0x49 _zPHY_euls_AddCqiRarSchdEvents
+ 0x1009de27 0x32 _zPHY_euls_InitSPSMode
+ 0x1009de59 0x2b _zPHY_euls_SetupSPSMode
+ 0x1009de84 0x7a _zPHY_euls_SetupSPSMode_DealComnPara
+ 0x1009defe 0x37 _zPHY_euls_SetupSPSMode_CalNextRecurPara
+ 0x1009df35 0x41 _zPHY_euls_JudgeAndDealUlSpsInterval_TDD
+ 0x1009df76 0x2e _zPHY_euls_JudgeAndDealUlSpsInterval_FDD
+ 0x1009dfa4 0x53 _zPHY_euls_ProSPSMode
+ 0x1009dff7 0x53 _zPHY_euls_ProSPSMode_GetUlSfUponCfgGrantSf
+ 0x1009e04a 0x44 _zPHY_euls_ProSPSMode_CalNextRecurPara
+ 0x1009e08e 0x32 _zPHY_euls_ReleaseSPSMode
+ 0x1009e0c0 0x37 _zPHY_euls_ProcessSPSImplicitRelease
+ 0x1009e0f7 0x11 _zPHY_euls_GetDCI0InfoFromConfiguredGrant
+ 0x1009e108 0x11 _zPHY_euls_LastSubframe_SFN
+ 0x1009e119 0xd _zPHY_euls_LastSubframe_Subframe
+ 0x1009e126 0xc _zPHY_euls_JudgeIfBitsIsAll1s_ForSPSRelease
+ 0x1009e132 0x4b _zPHY_euls_TATimerStop
+ 0x1009e17d 0xe _zPHY_euls_MACReset
+ 0x1009e18b 0xa1 _zPHY_euls_Release
+ 0x1009e22c 0x1e _zPHY_euls_ProcDci0PhichSelec
+ 0x1009e24a 0xcd _zPHY_euls_ProcDci0PhichSelec_Assign
+ 0x1009e317 0x46 _zPHY_euls_ProcDci0PhichSelec_Selec
+ 0x1009e35d 0x34 _zPHY_euls_DecodeUlIndexDci0
+ 0x1009e391 0x33 _zPHY_euls_DecodeUlIndexDci4
+ 0x1009e3c4 0x152 _zPHY_euls_AssignDCI0PHICH
+ 0x1009e516 0x5e _zPHY_euls_AssignDCI0_Schedule
+ 0x1009e574 0x26 _zPHY_euls_AssignPHICH_Schedule
+ 0x1009e59a 0x5a _zPHY_euls_SelecDCI0PHICH
+ 0x1009e5f4 0x21 _zPHY_euls_ReleaseDCI0PHICHSelecDB
+ 0x1009e615 0x67 _zPHY_euls_UpdataTTIBundlingHarqID
+ 0x1009e67c 0xa1 _zPHY_euls_DealBundlingGrant
+ 0x1009e71d 0x5a _zPHY_euls_ProcRealPHICH
+ 0x1009e777 0x59 _zPHY_euls_ProcVirtualPHICH
+ 0x1009e7d0 0x7b _zPHY_euls_InitTTIBundlingHarqID
+ 0x1009e84b 0x16 _zPHY_euls_InitTTIBundlingMode
+ 0x1009e861 0xc _zPHY_euls_ReleaseTTIBundlingMode
+ 0x1009e86d 0x6c _zPHY_euls_GetBundlingIDAndHarqID_InULA
+ 0x1009e8d9 0x75 _zPHY_euls_UpdataHarqID
+ 0x1009e94e 0x8 _zPHY_euls_AddAbsSubframe
+ 0x1009e956 0x66 _zPHY_euls_SetDrxFlag
+ 0x1009e9bc 0xcd _zPHY_euls_Dci0SelecAndCsiReport_Proc
+ 0x1009ea89 0x3d3 _zPHY_euls_CalcDciCsiReqFlag
+ 0x1009ee5c 0xf7 _zPHY_euls_CalLutrAndLtx
+ 0x1009ef53 0x16 _zPHY_euls_ScheduleTxChannelType
+ 0x1009ef69 0x7d _zPHY_euls_SchedulePuschAndPucch
+ 0x1009efe6 0x16f _zPHY_euls_DeterminePuschTransType
+ 0x1009f155 0x37 _zPHY_euls_GetPuschHarqAckInfo
+ 0x1009f18c 0x12d _zPHY_euls_DeterminePucchFmt
+ 0x1009f2b9 0x26 _zPHY_euls_GetSysTimeInfo
+ 0x1009f2df 0x75 _zPHY_euls_TM2_ChanExchange
+ 0x1009f354 0x66 _zPHY_euls_PuschPowerControl_Process
+ 0x1009f3ba 0x50 _zPHY_euls_NoPuschPowerControl_Process
+ 0x1009f40a 0x2a _zPHY_euls_GaoTong_Statistics_Process
+ 0x1009f434 0x1 _zPHY_euls_AmtTest_DciStubProcess
+ 0x1009f435 0x39 _zPHY_euls_GetPhichSubFrmNo
+ .text 0x1009f46e 0xa6d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x1009f46e 0x5 _zPHY_ecsrs_GetIdleDrxInterPssWorkTime
+ 0x1009f473 0x165 _zPHY_ecsrs_GetPssStartTime
+ 0x1009f5d8 0x63 _zPHY_ecsrs_AdjustPssStartTime
+ 0x1009f63b 0x14e _zPHY_ecsrs_SetPssFirstStartInfo
+ 0x1009f789 0xca _zPHY_ecsrs_SetPssNotFirstStartInfo
+ 0x1009f853 0x9a _zPHY_ecsrs_GetPssStartInfo
+ 0x1009f8ed 0x4f _zPHY_ecsrs_GetPssReadFlag
+ 0x1009f93c 0x23 _zPHY_ecsrs_ClearPeakList
+ 0x1009f95f 0x1a _zPHY_ecsrs_GetPssData
+ 0x1009f979 0x1c _zPHY_ecsrs_BackupPssFinger
+ 0x1009f995 0xb _zPHY_ecsrs_ClearPssFinger
+ 0x1009f9a0 0xd _zPHY_ecsrs_ClearInnerPeakList
+ 0x1009f9ad 0x5e _zPHY_ecsrs_AdjustPeakTime
+ 0x1009fa0b 0x19 _zPHY_ecsrs_FindFreq
+ 0x1009fa24 0x3d _zPHY_ecsrs_BackupPeakList
+ 0x1009fa61 0xa8 _zPHY_ecsrs_RecoverPeakList
+ 0x1009fb09 0x215 _zPHY_ecsrs_PssResultReadNew
+ 0x1009fd1e 0x63 _zPHY_ecsrs_CalBoundary
+ 0x1009fd81 0x2b _zPHY_ecsrs_CalRedoCfoBoundary
+ 0x1009fdac 0x46 _zPHY_ecsrs_PssAdjustPro
+ 0x1009fdf2 0x28 _zPHY_ecsrs_PssTpuAdjust
+ 0x1009fe1a 0x13 _zPHY_ecsrs_SearchMaxFinger
+ 0x1009fe2d 0xa0 _zPHY_ecsrs_FilterFinger
+ 0x1009fecd 0xe _zPHY_ecsrs_FingerIsValid
+ .text 0x1009fedb 0xc54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ 0x1009fedb 0x69 _zPHY_eula_PuschAckProcess
+ 0x1009ff44 0x177 _zPHY_eula_PuschCsiProcess
+ 0x100a00bb 0xc2 _zPHY_eula_SetPuschScale
+ 0x100a017d 0x1ed _zPHY_eula_PuschAckEncodedLenCalc
+ 0x100a036a 0x2b9 _zPHY_eula_TDD_PuschAckParasCalc
+ 0x100a0623 0x57 _zPHY_eula_TDD_PuschAckParasCalc_UlDl0
+ 0x100a067a 0x86 _zPHY_eula_LtxParas_acNcsPuschDmrs
+ 0x100a0700 0xc7 _zPHY_eula_LtxParas_acUVPuschDmrs
+ 0x100a07c7 0x290 _zPHY_eula_PuschCqiRiEncodedLenCalc
+ 0x100a0a57 0x24 _zPHY_eula_FDD_PuschAckParasCalc
+ 0x100a0a7b 0x8e _zPHY_eula_LtxParas_adwNcsDiv6PuschDmrs
+ 0x100a0b09 0x26 _zPHY_eula_HarqPuschMsg3Stub
+ .text 0x100a0b2f 0x547 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ 0x100a0b2f 0x80 _zPHY_eulpc_PuschPowParasCalc
+ 0x100a0baf 0x119 _zPHY_eulpc_UlsRelativePuscchPowCtrlProc
+ 0x100a0cc8 0x190 _zPHY_eulpc_PuschPowCalcProc
+ 0x100a0e58 0xa9 _zPHY_eulpc_NoPuschPowCalc
+ 0x100a0f01 0xb3 _zPHY_eulpc_DeltaTFCalc
+ 0x100a0fb4 0x89 _zPHY_eulpc_Log10yLinear
+ 0x100a103d 0x39 _zPHY_eulpc_PuschGetCsiInfo
+ .text 0x100a1076 0x540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x100a1076 0x6d _zPHY_edfe_Q8log2
+ 0x100a10e3 0x21 _zPHY_edfe_Logarithm
+ 0x100a1104 0x34 _zPHY_edfe_SupCalLog
+ 0x100a1138 0x8 _zPHY_edfe_SetCsrmDAGCGain
+ 0x100a1140 0x76 _zPHY_edfe_CalcRxDAGCGain
+ 0x100a11b6 0xa2 _zPHY_edfe_HandleRxDAGCGain
+ 0x100a1258 0x57 _zPHY_edfe_FixedRXDagcGain
+ 0x100a12af 0x105 _zPHY_edfe_CalcCsrsDAGCGain
+ 0x100a13b4 0x26 _zPHY_edfe_JudgeRxDagcCover
+ 0x100a13da 0x6d _zPHY_edfe_JudgeCsrsDagcCover
+ 0x100a1447 0xa8 _zPHY_edfe_HandleCsrsDagcInt
+ 0x100a14ef 0x39 _zPHY_edfe_ConfigDagcCalcPara
+ 0x100a1528 0x8e _zPHY_edfe_SetInterCsrsDAGCGain
+ .text 0x100a15b6 0x777 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ 0x100a15b6 0x26 _zAsn1_GetU16Bits
+ 0x100a15dc 0x39 _zAsn1_SetU16Bits
+ 0x100a1615 0x18 _zEasn1p_perGetConVal
+ 0x100a162d 0xc _zEasn1p_perGetDivbVal
+ 0x100a1639 0xa _zEasn1p_perGetIntVal
+ 0x100a1643 0x13 _zEasn1p_perGetBitNum
+ 0x100a1656 0x1a _zEasn1p_perGetRange
+ 0x100a1670 0x67 _zEasn1p_DcGetBitsVal32_Dec
+ 0x100a16d7 0x2 _zEasn1p_DcGetBitsVal32
+ 0x100a16d9 0x13 _zEasn1p_MovePtr_Dec
+ 0x100a16ec 0x1d _zEasn1p_EcSetBitStr_Dec
+ 0x100a1709 0xa2 _zEasn1p_DcGetBitsStr_Dec
+ 0x100a17ab 0x2 _zEasn1p_DcGetBitsStr
+ 0x100a17ad 0x1a _zEasn1p_ChkCodeLen_Dec
+ 0x100a17c7 0x91 _zEasn1p_per_dcOctStr
+ 0x100a1858 0xe5 _zEasn1p_per_dcLen
+ 0x100a193d 0x2f _zEasn1p_per_DcExt
+ 0x100a196c 0x2f _zEasn1p_per_dcIndefiniteLenWholeNum
+ 0x100a199b 0x2e _zEasn1p_per_dcConWholeNum
+ 0x100a19c9 0x8f _zEasn1p_per_dcSequenceOf
+ 0x100a1a58 0x2 _zEasn1p_MovePtr
+ 0x100a1a5a 0x24 _zEasn1p_per_dcPreamble
+ 0x100a1a7e 0x29 _zEasn1p_per_dcPreamble_Sequence
+ 0x100a1aa7 0x47 _zEasn1p_per_dcSmallWholeNum
+ 0x100a1aee 0x46 _zEasn1p_per_dcSkipAllExtData
+ 0x100a1b34 0xb7 _zEasn1p_per_dcInt
+ 0x100a1beb 0x66 _zEasn1p_per_dcChoiceOf
+ 0x100a1c51 0x4a _zEasn1p_per_dcSkipOneExtData
+ 0x100a1c9b 0x92 _zEasn1p_per_dcBitStr
+ .text 0x100a1d2d 0x391 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ 0x100a1d2d 0x55 _zPHY_ecsrs_GetCfoStartTime
+ 0x100a1d82 0x54 _zPHY_ecsrs_SetCfoStartInfoSymMap
+ 0x100a1dd6 0xa1 _zPHY_ecsrs_GetCfoStartInfo
+ 0x100a1e77 0x1e _zPHY_ecsrs_CalPowerNcpEcp
+ 0x100a1e95 0x46 _zPHY_ecsrs_CfoCalcPower
+ 0x100a1edb 0x5e _zPHY_ecsrs_CfoCalcPowerNcpEcp
+ 0x100a1f39 0x5e _zPHY_ecsrs_Codic_atan_FixPoint
+ 0x100a1f97 0x76 _zPHY_ecsrs_CsCfoResultMerge
+ 0x100a200d 0xb1 _zPHY_ecsrs_CfoResultRead
+ .text 0x100a20be 0x189 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ 0x100a20be 0x186 _zPHY_edla_CalcPcfichRegFilePara
+ 0x100a2244 0x3 _zPHY_edla_PcfichProc
+ .text 0x100a2247 0x1107 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ 0x100a2247 0xb7 _zPHY_ecsrs_SssStartFingerSort
+ 0x100a22fe 0xff _zPHY_ecsrs_SssFingerReorder
+ 0x100a23fd 0x49 _zPHY_ecsrs_AdjustSssFddProc
+ 0x100a2446 0x7c _zPHY_ecsrs_GetSssStartFinger
+ 0x100a24c2 0x37 _zPHY_ecsrs_GetNearValidTime
+ 0x100a24f9 0x33 _zPHY_ecsrs_CalSssBufferTime
+ 0x100a252c 0x170 _zPHY_ecsrs_GetSssStartTime
+ 0x100a269c 0x92 _zPHY_ecsrs_GetRfcEnableInfo
+ 0x100a272e 0x3e _zPHY_ecsrs_GetSssStartFg
+ 0x100a276c 0x50 _zPHY_ecsrs_InitSssStartInfo
+ 0x100a27bc 0x8f _zPHY_ecsrs_SetSssFddStartInfoAllProc
+ 0x100a284b 0xb7 _zPHY_ecsrs_SetSssTddStartInfoAllProc
+ 0x100a2902 0x251 _zPHY_ecsrs_SetSssFirstStartInfo
+ 0x100a2b53 0xd9 _zPHY_ecsrs_SetSssComStartInfo
+ 0x100a2c2c 0x4d _zPHY_ecsrs_GetSssStartInfo
+ 0x100a2c79 0x9b _zPHY_ecsrs_GetSssReadFlag
+ 0x100a2d14 0xe2 _zPHY_ecsrs_GetThresholdAndFilterCell
+ 0x100a2df6 0x2ae _zPHY_ecsrs_SssResultReadNew
+ 0x100a30a4 0x1a7 _zPHY_ecsrs_SssResultReadAppointCell
+ 0x100a324b 0x28 _zPHY_ecsrs_RecodCfoInfo
+ 0x100a3273 0x3e _zPHY_ecsrs_CheckCfoValid
+ 0x100a32b1 0x77 _zPHY_ecsrs_SearchForSssHwReset
+ 0x100a3328 0x26 _zPHY_ecsrs_SetSssHwCfgTime
+ .text 0x100a334e 0x1722 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x100a334e 0x5 _zPHY_ecsrs_Init
+ 0x100a3353 0x17 _zPHY_ecsrs_Reset
+ 0x100a336a 0x1 _zPHY_ecsrs_DebugModeInitPara
+ 0x100a336b 0x24 _zPHY_ecsrs_InitCommonInfor
+ 0x100a338f 0x1b _zPHY_ecsrs_DeleteAllSubFrameInt
+ 0x100a33aa 0x8 _zPHY_ecsrs_ResetSynInforTable
+ 0x100a33b2 0x30 _zPHY_ecsrs_GetIntraEarfcnInfo
+ 0x100a33e2 0x1e _zPHY_ecsrs_GetInterEarfcnInfo
+ 0x100a3400 0x1c4 _zPHY_ecsrs_GetCommonInfor
+ 0x100a35c4 0x34 _zPHY_ecsrs_CsRfcConfig
+ 0x100a35f8 0x1a _zPHY_ecsrs_BeforeInitSearch
+ 0x100a3612 0x15 _zPHY_ecsrs_TimeRelation
+ 0x100a3627 0x88 _zPHY_ecsrs_InterFreqChange
+ 0x100a36af 0x62 _zPHY_ecsrs_GetHwConfigMode
+ 0x100a3711 0x112 _zPHY_ecsrs_GetReadAndConfigIndex
+ 0x100a3823 0x1e _zPHY_ecsrs_SetSyncRelation
+ 0x100a3841 0x25 _zPHY_ecsrs_TFConfirmSearchMode
+ 0x100a3866 0x31 _zPHY_ecsrs_SetFilterRange
+ 0x100a3897 0xd _zPHY_ecsrs_OpenSubFrameInt
+ 0x100a38a4 0xd _zPHY_ecsrs_DelSubFrameInt
+ 0x100a38b1 0x8 _zPHY_ecsrs_UpdateInnOffset
+ 0x100a38b9 0x2b _zPHY_ecsrs_ReadSearchResult
+ 0x100a38e4 0x3d _zPHY_ecsrs_GetSubTime
+ 0x100a3921 0x31 _L1e_csrs_InitGloPara
+ 0x100a3952 0x8 _zPHY_ecsrs_OnReset
+ 0x100a395a 0x3 _zPHY_ecsrs_OnSearchMeasReset
+ 0x100a395d 0x48 _zPHY_ecsrs_OnSearchFreqScan
+ 0x100a39a5 0x81 _zPHY_ecsrs_OnSearchMeasStart
+ 0x100a3a26 0x1f _zPHY_ecsrs_OnPssUpdateCounterCnf
+ 0x100a3a45 0x70 _zPHY_ecsrs_OnTimeDelayInt
+ 0x100a3ab5 0xd _zPHY_ecsrs_OnNotSynSubFrameInt
+ 0x100a3ac2 0x57 _zPHY_ecsrs_InitFreqOffset
+ 0x100a3b19 0x9b _L1e_csrs_GetFreqOffset
+ 0x100a3bb4 0x6e _L1e_csrs_SetFtErrorList
+ 0x100a3c22 0x65 _L1e_csrs_SetFreqOffsetAge
+ 0x100a3c87 0x11 _L1e_csrs_GetMaxAgeIndex
+ 0x100a3c98 0x30 _L1e_csrs_NormalTemp
+ 0x100a3cc8 0x89 _zPHY_ecsrs_ModifyRfCfgInfo
+ 0x100a3d51 0x7 _zPHY_ecsrs_setMode
+ 0x100a3d58 0xa _zPHY_ecsrs_IsIntraMode
+ 0x100a3d62 0x86 _zEcsrs_PreEvent
+ 0x100a3de8 0x9e _L1e_csrs_SfProc
+ 0x100a3e86 0x2c _L1e_FS_SfProc
+ 0x100a3eb2 0x2e _zEcsrs_OnEvent
+ 0x100a3ee0 0xb _zPHY_ecsrs_IsInitCs
+ 0x100a3eeb 0x3c _zPHY_ecsrs_CsNeedReCfo
+ 0x100a3f27 0x16 _zPHY_ecsrs_CsNeedReSss
+ 0x100a3f3d 0x67 _zPHY_ecsrs_IsRfOpen
+ 0x100a3fa4 0x14c _zPHY_csr_RfcConfig
+ 0x100a40f0 0x1e _zPHY_ecsrs_IsOptSearch
+ 0x100a410e 0x1a _zPHY_ecsrs_CfoAccNum
+ 0x100a4128 0x1a _zPHY_ecsrs_GetConfigRfFlag
+ 0x100a4142 0x3d _zPHY_ecsrs_GetScheduleFlag
+ 0x100a417f 0x9 _zPHY_ecsrs_CsBeforeAgc
+ 0x100a4188 0x17 _zPHY_ecsrs_CsNeedAgc
+ 0x100a419f 0x6b _zPHY_ecsrs_CsNeedPss
+ 0x100a420a 0x2 _zPHY_ecsrs_CsNeedCfo
+ 0x100a420c 0x82 _zPHY_ecsrs_CsNeedSss
+ 0x100a428e 0x16 _zPHY_ecsrs_CsNeedTempComp
+ 0x100a42a4 0x26 _zPHY_ecsrs_CsIsOnAgc
+ 0x100a42ca 0x37 _zPHY_ecsrs_CsAgcProc
+ 0x100a4301 0x1 _zPHY_ecsrs_CsAgcProcEnd
+ 0x100a4302 0xd _zPHY_ecsrs_CsNeedPssAgain
+ 0x100a430f 0x17 _zPHY_ecsrs_CsBeforePss
+ 0x100a4326 0x1a _zPHY_ecsrs_CsIsOnPss
+ 0x100a4340 0x91 _zPHY_ecsrs_CsGetPssRfCfgInfo
+ 0x100a43d1 0x50 _zPHY_ecsrs_SniffInterFreqChange
+ 0x100a4421 0x13b _zPHY_ecsrs_CsPssProc
+ 0x100a455c 0xda _zPHY_ecsrs_CsPssProcEnd
+ 0x100a4636 0x2a _zPHY_ecsrs_CsNeedMoreCfo
+ 0x100a4660 0x23 _zPHY_ecsrs_CsBeforeCfo
+ 0x100a4683 0x12 _zPHY_ecsrs_CsCfoTpuAdjPro
+ 0x100a4695 0x14 _zPHY_ecsrs_CsIsOnCfo
+ 0x100a46a9 0x6f _zPHY_ecsrs_CsCfoProc
+ 0x100a4718 0x60 _zPHY_ecsrs_CsCfoProcEnd
+ 0x100a4778 0x13 _zPHY_ecsrs_CsBeforeSss
+ 0x100a478b 0x1a _zPHY_ecsrs_CsIsOnSss
+ 0x100a47a5 0x8d _zPHY_ecsrs_CsGetSssRfCfgInfo
+ 0x100a4832 0x12d _zPHY_ecsrs_CsSssProc
+ 0x100a495f 0x1d _zPHY_ecsrs_InitSearchCnf
+ 0x100a497c 0x56 _zPHY_ecsrs_CsSssProcEnd
+ 0x100a49d2 0x18 _zPHY_ecsrs_CsNeedCs
+ 0x100a49ea 0x1a _zPHY_ecsrs_CsBeforeCs
+ 0x100a4a04 0xb _zPHY_ecsrs_WaitSubFrameInt
+ 0x100a4a0f 0x1c _zPHY_ecsrs_SSSearctT
+ 0x100a4a2b 0x3d _zPHY_ecsrs_CheckSssCount
+ 0x100a4a68 0x8 _zPHY_ecsrs_SetSssHwRestartCnt
+ .text 0x100a4a70 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ .text 0x100a4aac 0x458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x100a4aac 0x13 _zPHY_ecsrs_HwIntHandle
+ 0x100a4abf 0x49 _zPHY_ecsrs_HwReset
+ 0x100a4b08 0x33 _zPHY_ecsrs_AllHwReset
+ 0x100a4b3b 0x15 _zPHY_ecsr_HwSssTdCommonReset
+ 0x100a4b50 0xa3 _zPHY_ecsrs_ConfigIcFiFoHw
+ 0x100a4bf3 0x8a _zPHY_ecsrs_ConfigIcHw
+ 0x100a4c7d 0x4f _zPHY_ecsrs_ConfigPssHw
+ 0x100a4ccc 0x36 _zPHY_ecsrs_ConfigCfoHw
+ 0x100a4d02 0x47 _zPHY_ecsrs_ConfigSssHw
+ 0x100a4d49 0xc _zPHY_ecsrs_CfgTopClkGating
+ 0x100a4d55 0x14 _zPHY_ecsrs_CfgTopReg
+ 0x100a4d69 0x27 _zPHY_ecsrs_SssCfgPschLocalSeq
+ 0x100a4d90 0x31 _zPHY_ecsrs_AgcBalanceCfgRegs
+ 0x100a4dc1 0xc _zPHY_ecsrs_AgcBalanceDisable
+ 0x100a4dcd 0x23 _zPHY_ecsrc_SwClkGateCtrl
+ 0x100a4df0 0x49 _zPHY_ecsr_ConvertFinger
+ 0x100a4e39 0x1f _zPHY_ecsr_GetHwPssFinger
+ 0x100a4e58 0x8 _zPHY_ecsr_GetHwPssFreqInd
+ 0x100a4e60 0xd _zPHY_ecsr_GetHwPssDoneMark
+ 0x100a4e6d 0xd _zPHY_ecsr_GetHwPssNumHalfFrame
+ 0x100a4e7a 0x3 _zPHY_ecsr_GetHwPssPeakValid
+ 0x100a4e7d 0x8 _zPHY_ecsr_GetHwPssMaxPower
+ 0x100a4e85 0xa _zPHY_ecsr_GetHwCfoOutput
+ 0x100a4e8f 0x10 _zPHY_ecsr_GetHwSssPeakList
+ 0x100a4e9f 0xa _zPHY_ecsr_GetHwSssComResult
+ 0x100a4ea9 0xb _zPHY_ecsr_GetHwSssProcCount
+ 0x100a4eb4 0xb _zPHY_ecsr_GetHwSssProcStatus
+ 0x100a4ebf 0xd _zPHY_ecsr_GetHwSssProcEnable
+ 0x100a4ecc 0x8 _zPHY_ecsr_GetHwSssProcRdWrState
+ 0x100a4ed4 0x8 _zPHY_ecsr_GetHwIcWorkState
+ 0x100a4edc 0x8 _zPHY_ecsr_GetHwTopClkGating
+ 0x100a4ee4 0x8 _zPHY_ecsr_GetHwPssClkGatingBypass
+ 0x100a4eec 0x8 _zPHY_ecsr_GetHwIcClkGatingBypass
+ 0x100a4ef4 0x8 _zPHY_ecsr_GetHwSssClkGatingEn
+ 0x100a4efc 0x8 _zPHY_ecsr_GetHwSssWorkStatus
+ .text 0x100a4f04 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ 0x100a4f04 0x2f _L1e_FS_LogAddSearchResult
+ 0x100a4f33 0x25 _L1e_FS_LogAddSearchResultFail
+ 0x100a4f58 0x14 _L1e_FS_LogGainCompenError
+ 0x100a4f6c 0x17 _L1e_FS_LogMinAgcGainError
+ 0x100a4f83 0x17 _L1e_FS_LogDeleteEarfcn
+ 0x100a4f9a 0x2d _L1e_FS_LogSssResult
+ 0x100a4fc7 0x17 _L1e_FS_LogFsResultNum
+ 0x100a4fde 0x1e _L1e_FS_LogDeleteFreqPoint
+ 0x100a4ffc 0x5c _L1e_FS_LogBandInfo
+ 0x100a5058 0x40 _L1e_FS_LogProfileInfo
+ 0x100a5098 0x38 _L1e_FS_LogInsertPSSResult
+ 0x100a50d0 0x54 _L1e_FS_LogAddSearchwEarfcn
+ 0x100a5124 0x21 _L1e_FS_LogPlmnReturnSrvCell
+ 0x100a5145 0x95 _L1e_FS_LogPSSFinger
+ 0x100a51da 0x14 _L1e_FS_LogPSSNoValidEarfcn
+ 0x100a51ee 0x22 _L1e_FS_LogResultNULL
+ 0x100a5210 0x1d _L1e_FS_LogChangeAgc
+ 0x100a522d 0x1a _L1e_FS_LogAllAgcFail
+ 0x100a5247 0x14 _L1e_FS_LogReqMsgError
+ 0x100a525b 0x41 _L1e_FS_LogSegmeantInfo
+ 0x100a529c 0x31 _L1e_FS_LogSssAgcGain
+ 0x100a52cd 0x26 _L1e_FS_LogMpInfo
+ 0x100a52f3 0x5b _L1e_FS_LogProGainInfo
+ 0x100a534e 0x1d _L1e_FS_LogAGCInfo
+ 0x100a536b 0x4a _L1e_FS_LogProRedo100KInfo
+ 0x100a53b5 0x1d _L1e_FS_StartAGC
+ 0x100a53d2 0x2a _L1e_FS_AGCInfo
+ 0x100a53fc 0x27 _L1e_FS_TestInfo
+ 0x100a5423 0x1e _L1e_FS_LogBackup100KResult
+ 0x100a5441 0x17 _L1e_FS_LogFreqOffsetIndex
+ 0x100a5458 0x1d _zPHY_ecsc_LogPss100KResult
+ .text 0x100a5475 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ 0x100a5475 0x1c _zPHY_ecsrs_ListInsert
+ 0x100a5491 0x5 _zPHY_ecsrs_ListAdd
+ 0x100a5496 0x1a _zPHY_ecsrs_ListDelete
+ 0x100a54b0 0x3 _zPHY_ecsrs_ListFirst
+ 0x100a54b3 0x3 _zPHY_ecsrs_ListLast
+ 0x100a54b6 0x2 _zPHY_ecsrs_ListNext
+ 0x100a54b8 0x3 _zPHY_ecsrs_ListPrev
+ 0x100a54bb 0x8 _zPHY_ecsrs_IsListEmpty
+ .text 0x100a54c3 0x9c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ 0x100a54c3 0x9c _s_create_pool
+ .text 0x100a555f 0x20 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ 0x100a555f 0x20 _create_sem
+ .text 0x100a557f 0x9 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ 0x100a557f 0x9 _current_process
+ .text 0x100a5588 0x50 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ 0x100a5588 0x50 _delay
+ .text 0x100a55d8 0x63 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ 0x100a55d8 0x63 _free_buf
+ .text 0x100a563b 0x49 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ 0x100a563b 0x49 _get_pri
+ .text 0x100a5684 0x8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ 0x100a5684 0x8 _get_ticks
+ .text 0x100a568c 0x4c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ 0x100a568c 0x4c _kill_sem
+ .text 0x100a56d8 0x7c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ 0x100a56da 0x7a _receive
+ .text 0x100a5754 0xc7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ 0x100a5756 0xc5 _s_alloc_nil
+ .text 0x100a581b 0x16 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ 0x100a581b 0x16 _sender
+ .text 0x100a5831 0x116 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ 0x100a5831 0x77 _set_pri
+ 0x100a58a8 0x9f _set_ot_pri
+ .text 0x100a5947 0x31 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ 0x100a5947 0x31 _signal_sem
+ .text 0x100a5978 0x65 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ 0x100a5978 0x65 _start
+ .text 0x100a59dd 0x1c5 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ 0x100a59dd 0xa _zcos_sysd_init
+ 0x100a59e7 0x5b _odo_kill_proc
+ 0x100a5a42 0x39 _odo_hunt_kill_proc
+ 0x100a5a7b 0x7b _odo_new_process
+ 0x100a5af6 0x34 _odo_hunt_request_local
+ 0x100a5b2a 0x55 _ose_sysd_handle_signal
+ 0x100a5b7f 0x23 _zcos_sysd
+ .text 0x100a5ba2 0x83 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ 0x100a5ba2 0x83 _tick
+ .text 0x100a5c25 0x4c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ 0x100a5c25 0x4c _wait_sem
+ .text 0x100a5c71 0xfa T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ 0x100a5c71 0x36 _odo_hunt_find_name
+ 0x100a5ca7 0xc4 _hunt
+ .text 0x100a5d6b 0x43 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ 0x100a5d6b 0x43 _restore
+ .text 0x100a5dae 0x98 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ 0x100a5dae 0x98 _send_w_s
+ .text 0x100a5e46 0x5b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ 0x100a5e46 0x5b _zDrvEfuse_IsSpe
+ .text 0x100a5ea1 0x4f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(32.o)
+ 0x100a5ea1 0xf ___modhi3
+ 0x100a5eb0 0x19 ___umodhi3
+ 0x100a5ec9 0x11 ___divhi3
+ 0x100a5eda 0x16 ___udivhi3
+ .text 0x100a5ef0 0x19e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o)
+ 0x100a5ef0 0x19e ___addsf3
+ .text 0x100a608e 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(compare_IEEE.o)
+ 0x100a608e 0x0 ___gehf2
+ 0x100a608e 0x0 ___nehf2
+ 0x100a608e 0x0 ___eqhf2
+ 0x100a608e 0x0 ___lthf2
+ 0x100a608e 0x0 ___gthf2
+ 0x100a608e 0x2a ___lehf2
+ .text 0x100a60b8 0x2d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convert.o)
+ 0x100a60b8 0x21 ___floatunshihf2
+ 0x100a60d9 0xc ___floathihf2
+ .text 0x100a60e5 0x18 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convertqi.o)
+ 0x100a60e5 0xb ___floatqihf2
+ 0x100a60f0 0xd ___floatunsqihf2
+ .text 0x100a60fd 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(div.o)
+ 0x100a6105 0x21 ___divqi3
+ .text 0x100a6126 0x112 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Div.o)
+ 0x100a6126 0x112 ___divsf3
+ .text 0x100a6238 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(divzi3_v2.o)
+ 0x100a6238 0x29 ___divzi3_v2
+ *fill* 0x100a6261 0x80000001 00
+ .text 0x100a6262 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ftou.o)
+ 0x100a6262 0x17 ___ieee754_ftou
+ .text 0x100a6279 0xf C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
+ 0x100a6279 0xf _memcmp
+ .text 0x100a6288 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy16.o)
+ 0x100a6289 0x11 ___memcpy16
+ .text 0x100a629a 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy.o)
+ 0x100a629f 0x10 _memcpy
+ .text 0x100a62af 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memset.o)
+ 0x100a62b0 0x14 _memset
+ .text 0x100a62c4 0x21 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mod.o)
+ 0x100a62c4 0x21 ___modqi3
+ .text 0x100a62e5 0x27 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(modzi3_v2.o)
+ 0x100a62e5 0x27 ___modzi3_v2
+ .text 0x100a630c 0xe1 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Mul.o)
+ 0x100a630c 0x0 ___ieee754_mul
+ 0x100a630c 0xe1 ___mulsf3
+ .text 0x100a63ed 0x6b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pnan.o)
+ 0x100a63ed 0x6b ___ieee754_propagate_nan
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+ 0x100db49b 0xc _L1W_TAB_HSUPA_RG_THRESH
+ 0x100db4a7 0x8 _L1W_TAB_HSUPA_HI_THRESH
+ 0x100db4af 0x1 _g_eL1wServHiNckDtx
+ 0x100db4b0 0x1 _g_hiNackCnt
+ .data 0x100db4b1 0x269 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x100db719 0x1 _g_L1LteaInitFlag
+ .data 0x100db71a 0x61a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ .data 0x100dbd34 0x34 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x100dbd34 0x1f _swTpuSym2Ts
+ 0x100dbd53 0x15 _s_awNextXSubFrm
+ .data 0x100dbd68 0x13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x100dbd68 0x8 _g_tCsi
+ 0x100dbd70 0x1 _g_wCsiSCellActive
+ 0x100dbd71 0xa _g_awCsiNoUpFlg
+ .data 0x100dbd7b 0x87 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x100dbd7b 0x10 _g_aswDdrPro
+ 0x100dbd8b 0x4 _g_aswDdrStartPro
+ 0x100dbd8f 0x40 _g_awDdrBmpConv
+ 0x100dbdcf 0x32 _g_awStartBlockIdx
+ 0x100dbe01 0x1 _wPchUseSibFlag
+ .data 0x100dbe02 0x235 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x100dbe02 0x39 _T_ZPHY_RFSD_CONFIG
+ 0x100dbe3b 0x1c _T_ZPHY_RFCSA_CSRC_CONFIG
+ 0x100dbe57 0x15 _T_ZPHY_RFCSA_RX_CONFIG
+ 0x100dbe6c 0x18 _T_ZPHY_RFCSA_TX_CONFIG
+ 0x100dbe84 0x16 _T_ZPHY_TA_MAX
+ 0x100dbe9a 0x31 _T_ZPHY_ACP405_TRANS_TABLE
+ 0x100dbecb 0x6 _T_ZPHY_ACP405_FASTAGC_APPLY
+ 0x100dbed1 0x6 _T_ZPHY_RFC_FASTAGC_ESTI
+ 0x100dbed7 0x28 _g_at_zPHY_erfc_VgaTempDiffList
+ 0x100dbeff 0xc _g_adwFixDlDelay
+ 0x100dbf0b 0xc _g_dwFixUlDelay
+ 0x100dbf17 0xc _g_dwULDBBRFDelay
+ 0x100dbf23 0x1 _g_wTddOrFddbuff
+ 0x100dbf24 0x14 _g_asdzPHY_erfc_Rxoffset0SFConfig
+ 0x100dbf38 0x14 _g_asdzPHY_erfc_Rxoffset1SFConfig
+ 0x100dbf4c 0x1 _g_zPHY_erfc_wMeas0TabJumpToNum
+ 0x100dbf4d 0x1 _g_zPHY_erfc_cTxTabJumpToSubNum
+ 0x100dbf4e 0x14 _g_asdzPHY_erfc_TAoffsetSFConfig
+ 0x100dbf62 0x2 _g_ptzPHY_etpu_LocalMrtrOffset
+ 0x100dbf64 0x98 _g_zPHY_erfc_Temp_Dac_Data
+ 0x100dbffc 0x2 _g_swATCtrlFixTa
+ 0x100dbffe 0x2 _g_ePhyRatMode
+ 0x100dc000 0x12 _g_zPHY_RfcDataPointer
+ 0x100dc012 0x1 _g_zPHY_erfc_bRfcProfileInd
+ 0x100dc013 0x1 _g_zPHY_edfe_bRfcProfileInd
+ 0x100dc014 0x1 _g_zPHY_erfc_NextSfnSccIdleFlag
+ 0x100dc015 0x6 _g_atL1lRfcNextSfOffset
+ 0x100dc01b 0x6 _g_tXoAtDebugC0
+ 0x100dc021 0x16 _g_zPHY_erfc_tDcxoPara
+ .data 0x100dc037 0x4e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x100dc037 0x9 _g_wCddRiFirCalc
+ 0x100dc040 0x297 _g_awLog2TableDot16
+ 0x100dc2d7 0x80 _g_awLog2Table
+ 0x100dc357 0x10 _g_atCDDL2CB
+ 0x100dc367 0x18 _g_atCBTX2NL1
+ 0x100dc37f 0x20 _g_atCBTX2NL2
+ 0x100dc39f 0x100 _g_atCBTX4NL2
+ 0x100dc49f 0x48 _g_atCBCDDTx4
+ 0x100dc4e7 0x2a _g_awCqiEfficiency
+ 0x100dc511 0x1 _g_RiVal2Dl
+ 0x100dc512 0x4 _g_adCddRiCurSnr
+ 0x100dc516 0x4 _g_adCddRiFilterSnr
+ .data 0x100dc51a 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x100dc51a 0x2 _ptrBch
+ 0x100dc51c 0x2 _g_dwCsrsMulmPbchWorkFlag
+ .data 0x100dc51e 0x52 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x100dc53c 0x12 _g_ptL1eDevDlsDlaIx
+ 0x100dc54e 0x20 _g_dwHarqAddr
+ 0x100dc56e 0x2 _gDLHarqPduMutex
+ .data 0x100dc570 0x97 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x100dc5d4 0x6 _s_aWBHiCfgSBSize
+ 0x100dc5da 0x6 _s_aWBHiCfgLastSBSize
+ 0x100dc5e0 0x24 _s_aWBHiCfgSBNum
+ 0x100dc604 0x2 _g_PatCsiEnFinal
+ 0x100dc606 0x1 _g_awFeedBack_ConfigTimes
+ .data 0x100dc607 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x100dc607 0x2 _g_sdwTxOffset
+ *fill* 0x100dc609 0x80000001 00
+ .data 0x100dc60a 0xf4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x100dc629 0x2 _g_ptRxp_Ops
+ 0x100dc62b 0x1a _g_lsdwL1eRxSnrRefValue
+ 0x100dc645 0x28 _g_tLtel1RxAdaptAntCb
+ 0x100dc66d 0x16 _g_tLtel1DlaRfcDfeInfo
+ 0x100dc683 0x20 _g_lsdwNbnbRsrp
+ 0x100dc6a3 0x8 _g_lsdwNbnbN0
+ 0x100dc6ab 0x10 _g_lsdwNbnbRsrpPwr
+ 0x100dc6bb 0x40 _g_asdwL1eRxDrsRsrp
+ 0x100dc6fb 0x1 _g_wSingleAnt
+ 0x100dc6fc 0x2 _g_dwDrxState_For712Cir
+ *fill* 0x100dc6fe 0x80000002 00
+ .data 0x100dc700 0x1eee T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x100dc700 0x2 _g_dwSf_BeforeTAAdjust
+ 0x100dc702 0x20 _G_AW_SRS_M_NB_0640
+ 0x100dc722 0x20 _G_AW_SRS_M_NB_4060
+ 0x100dc742 0x20 _G_AW_SRS_M_NB_6080
+ 0x100dc762 0x20 _G_AW_SRS_M_NB_80110
+ 0x100dc782 0x50 _G_AC_SRS_SUBFRM_CONFIG_TDD
+ 0x100dc7d2 0xa0 _G_CELL_SRS_POS_SUBFRM_CONFIG_TDD
+ 0x100dc872 0x1e _G_AC_SRS_UE_SPEC_CONFIG_TDD
+ 0x100dc890 0x64 _G_UE_SRS_POS_CONFIG_TDD
+ 0x100dc8f4 0xc _G_AC_K_SRS1
+ 0x100dc900 0xc _G_AC_K_SRS2
+ 0x100dc90c 0x14 _G_AC_MULTI_ACKNACK_B0B1
+ 0x100dc920 0x9 _G_NEXT_ACK_ORDER
+ 0x100dc929 0x46 _G_AC_DL_SET_K_INFO
+ 0x100dc96f 0x46 _G_AC_DL_SET_K_FDD_TDD_INFO
+ 0x100dc9b5 0x9 _G_AC_M2_ACK_MULTIPLEXING
+ 0x100dc9be 0x1b _G_AC_M3_ACK_MULTIPLEXING
+ 0x100dc9d9 0x51 _G_AC_M4_ACK_MULTIPLEXING
+ 0x100dca2a 0x9 _G_AC_M2_ACK_MULTIPLEXING_R10
+ 0x100dca33 0x1b _G_AC_M3_ACK_MULTIPLEXING_R10
+ 0x100dca4e 0x51 _G_AC_M4_ACK_MULTIPLEXING_R10
+ 0x100dca9f 0x8 _G_AC_CA_A2_ACK_MULTIPLEXING
+ 0x100dcaa7 0x10 _G_AC_CA_A3_ACK_MULTIPLEXING
+ 0x100dcab7 0x20 _G_AC_CA_A4_ACK_MULTIPLEXING
+ 0x100dcad7 0x20 _G_FDD_CA_A4_ACK_FORMAT1B
+ 0x100dcaf7 0x12 _G_FDD_CA_A3_ACK_FORMAT1B
+ 0x100dcb09 0x8 _G_FDD_CA_A2_ACK_FORMAT1B
+ 0x100dcb11 0x20 _G_AC_CA_M3_ACK_MULTIPLEXING
+ 0x100dcb31 0x4c _G_AC_CA_M4_ACK_MULTIPLEXING
+ 0x100dcb7d 0x20 _G_AC_CA_M3_ACK_RESOURCE_VALUE
+ 0x100dcb9d 0x4c _G_AC_CA_M4_ACK_RESOURCE_VALUE
+ 0x100dcbe9 0x9 _G_AC_ULDL5_ACK_ORDER
+ 0x100dcbf2 0x46 _G_AC_SPECIAL_SUBFRAME_FLAG
+ 0x100dcc38 0x90 _G_AC_SRS_SUBFRM_CONFIG_FDD
+ 0x100dccc8 0xa0 _G_CELL_SRS_POS_SUBFRM_CONFIG_FDD
+ 0x100dcd68 0x10 _G_AW_HARQ_ACK_OFFSET
+ 0x100dcd78 0x10 _G_AW_RI_OFFSET
+ 0x100dcd88 0x10 _G_AW_CQI_OFFSET
+ 0x100dcd98 0xc5 _G_AW_PRIME_NUMBER
+ 0x100dce5d 0x8 _G_AW_CYCLIC_SHIFT_NDMRS1
+ 0x100dce65 0x18 _G_AW_CYCLIC_SHIFT_INDCI_NDMRS2_OCC
+ 0x100dce7d 0x5 _G_AW_FORMAT3_NOC_NPNS_NSF1_5
+ 0x100dce82 0x4 _G_AW_FORMAT3_NOC_NPNS_NSF1_4
+ 0x100dce86 0x7 _G_W_PRACH0_3_SCALE1
+ 0x100dce8d 0x1 _G_W_PRACH0_3_SCALE3
+ 0x100dce8e 0x7 _G_W_PRACH4_SCALE1
+ 0x100dce95 0x1 _G_W_PRACH4_SCALE3
+ 0x100dce96 0x7 _G_W_PUCCH_SCALE1_1_92M_SAMPLE
+ 0x100dce9d 0x7 _G_W_PUCCH_SCALE1_3_84M_SAMPLE
+ 0x100dcea4 0x7 _G_W_PUCCH_SCALE1_7_68M_SAMPLE
+ 0x100dceab 0x7 _G_W_PUCCH_SCALE1_15_36M_SAMPLE
+ 0x100dceb2 0x7 _G_W_PUCCH_SCALE1_30_72M_SAMPLE
+ 0x100dceb9 0x1 _G_W_PUCCH_SCALE3
+ 0x100dceba 0x1 _G_W_SRS_SCALE3
+ 0x100dcebb 0x7 _G_W_SRS_SCALE1_1_92M_SAMPLE
+ 0x100dcec2 0x1c _G_W_SRS_SCALE1_3_84M_SAMPLE
+ 0x100dcede 0x31 _G_W_SRS_SCALE1_7_68M_SAMPLE
+ 0x100dcf0f 0x62 _G_W_SRS_SCALE1_15_36M_SAMPLE
+ 0x100dcf71 0xaf _G_W_SRS_SCALE1_30_72M_SAMPLE
+ 0x100dd020 0x7 _G_W_PUSCH_SCALE1_1_92M_SAMPLE
+ 0x100dd027 0x7 _G_W_PUSCH_SCALE3_1_92M_SAMPLE
+ 0x100dd02e 0x7 _G_W_PUSCH_SCALE1_3_84M_SAMPLE
+ 0x100dd035 0x10 _G_W_PUSCH_SCALE3_3_84M_SAMPLE
+ 0x100dd045 0x7 _G_W_PUSCH_SCALE1_7_68M_SAMPLE
+ 0x100dd04c 0x1a _G_W_PUSCH_SCALE3_7_68M_SAMPLE
+ 0x100dd066 0x7 _G_W_PUSCH_SCALE1_15_36M_SAMPLE
+ 0x100dd06d 0x33 _G_W_PUSCH_SCALE3_15_36M_SAMPLE
+ 0x100dd0a0 0xe _G_W_PUSCH_SCALE1_30_72M_SAMPLE
+ 0x100dd0ae 0x65 _G_W_PUSCH_SCALE3_30_72M_SAMPLE
+ 0x100dd113 0x42 _G_W_FIRST_FILTER_1_4M_SAMPLE
+ 0x100dd155 0x42 _G_W_FIRST_FILTER_1_4M_SAMPLE_FIX3072
+ 0x100dd197 0x42 _G_W_FIRST_FILTER_3M_SAMPLE
+ 0x100dd1d9 0x42 _G_W_FIRST_FILTER_3M_SAMPLE_FIX3072
+ 0x100dd21b 0x42 _G_W_FIRST_FILTER_5M_SAMPLE
+ 0x100dd25d 0x42 _G_W_FIRST_FILTER_5M_SAMPLE_FIX3072
+ 0x100dd29f 0x42 _G_W_FIRST_FILTER_10M_SAMPLE
+ 0x100dd2e1 0x42 _G_W_FIRST_FILTER_10M_SAMPLE_FIX3072
+ 0x100dd323 0x42 _G_W_FIRST_FILTER_15M_SAMPLE
+ 0x100dd365 0x42 _G_W_FIRST_FILTER_20M_SAMPLE
+ 0x100dd3a7 0x42 _G_W_FIRST_FILTER_BYPASS_STUB_SAMPLE
+ 0x100dd3e9 0x42 _G_W_PRACH_FILTER_20M_15M_SAMPLE
+ 0x100dd42b 0x42 _G_W_PRACH_FILTER_3M_SAMPLE
+ 0x100dd46d 0x42 _G_W_PRACH_FILTER_5M_SAMPLE
+ 0x100dd4af 0x42 _G_W_PRACH_FILTER_10M_SAMPLE
+ 0x100dd4f1 0x18 _G_ADW_NCS_DIV_6
+ 0x100dd509 0x10 _G_ADW_NCS_DIV_4
+ 0x100dd519 0x6 _G_AW_C_NRBSC_DELTAPUCCHSHIFT
+ 0x100dd51f 0x208 _G_AW_MOD_30
+ 0x100dd727 0x12c _G_AW_MOD_12
+ 0x100dd853 0x24 _G_A_ZPHY_EULA_CHANNELTIMINGSEQTAB
+ 0x100dd877 0x25 _G_A_ZPHY_EULA_TQADJSUBFRAME
+ 0x100dd89c 0xc8 _g_adw_zPHY_eula_PuschMsg3Data
+ 0x100dd964 0xc76 _g_adw_zPHY_eula_TestCase12_2Data
+ 0x100de5da 0x14 _g_aeUlChannelType
+ .data 0x100de5ee 0x104 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x100de5ee 0x1 _g_zPHY_eWakeUpMode
+ 0x100de5ef 0x2 _g_zPHY_SleepFlag
+ 0x100de5f1 0x55 _G_ZPHY_ELPC_DVFS
+ 0x100de646 0x14 _g_zPHY_LPMCALIPARA
+ 0x100de65a 0x4 _G_ZPHY_ELPC_ZSPCLK
+ 0x100de65e 0x8f _G_ZPHY_ELPC_AXICLK
+ 0x100de6ed 0x1 _g_wWakeUpFlag
+ 0x100de6ee 0x1 _g_zPHY_bSccRficSleepFlag
+ 0x100de6ef 0x1 _g_zPHY_bUlGrantIntState
+ 0x100de6f0 0x1 _g_wLteCfunReset
+ 0x100de6f1 0x1 _g_wLtePrint1
+ .data 0x100de6f2 0x27 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x100de6f2 0x2 _g_dwInitalBandwidth
+ 0x100de6f4 0x24 _T_ZPHY_RELOAD_CONFIG
+ 0x100de718 0x1 _g_zPHY_tRfSleepState
+ .data 0x100de719 0x110 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x100de719 0x1 _g_zPHY_ecsrm_tConnectedMeasMode
+ 0x100de71a 0x10f _g_ThreadMeas
+ .data 0x100de829 0x17a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x100de829 0xa _g_awCsrmRsNumLog2
+ 0x100de833 0xa _g_awCsrmRsNumLog2_Single_Symbol
+ 0x100de83d 0x6 _g_awCsrmNumFftLogVal
+ 0x100de843 0x8 _MeasOnceSteps
+ 0x100de84b 0x67 _MeasOnce
+ 0x100de8b2 0x8 _MeasPrimarySteps
+ 0x100de8ba 0x67 _MeasPrimary
+ 0x100de921 0x18 _MeasProcSteps
+ 0x100de939 0x67 _MeasProc
+ 0x100de9a0 0x1 _g_zPHY_ecsrm_bHalfFrame
+ 0x100de9a1 0x2 _g_awMeasSingleSymModeFlag
+ .data 0x100de9a3 0x37 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x100de9a3 0x35 _g_awTriangleCoefft
+ 0x100de9d8 0x1 _gwCellchangeFlag
+ 0x100de9d9 0x1 _g_wMaxTxIndex
+ *fill* 0x100de9da 0x80000026 00
+ .data 0x100dea00 0x200 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x100dea00 0x200 _g_aswOutdata
+ .data 0x100dec00 0x64 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x100dec00 0x50 _g_awL1eRxRsrpIdleFilterCoeff
+ 0x100dec50 0x14 _g_awL1eRxRsrpFilterCoeff
+ .data 0x100dec64 0x9b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x100dec64 0x2 _g_zPHY_edfe_dwAgcHwModeVari
+ 0x100dec66 0x1 _g_wFirstFlagDC0
+ 0x100dec67 0x1 _g_wFirstFlagDC1
+ 0x100dec68 0x84 _WDFE_GAINDBTOLINEVALUE
+ 0x100decec 0x1 _g_Csrs_Csrm_Start_Flag
+ 0x100deced 0x1 _g_bDfeIntCheckEventFlag
+ 0x100decee 0x1 _g_bCsrsDagcEstiEnableFlag
+ 0x100decef 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd
+ 0x100decf0 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd0
+ 0x100decf1 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd1
+ 0x100decf2 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCoverFlag
+ 0x100decf3 0x2 _g_dwRspRx0Tx0
+ 0x100decf5 0x2 _g_dwRspRx1Tx0
+ 0x100decf7 0x2 _g_dwRspRx0Tx1
+ 0x100decf9 0x2 _g_dwRspRx1Tx1
+ 0x100decfb 0x1 _g_Idle_Inter_Freq_Flag
+ 0x100decfc 0x1 _g_wRxDagcIntCounter
+ 0x100decfd 0x1 _g_zPHY_edfe_RxDagcDoneFlag
+ 0x100decfe 0x1 _g_wFreqScanWorkOnFlag
+ .data 0x100decff 0xb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x100decff 0x1 _g_wPreSubFrame
+ 0x100ded00 0x1 _g_wCurSubFrame
+ 0x100ded01 0x1 _g_wPreFrame
+ 0x100ded02 0x1 _g_wCurFrame
+ 0x100ded03 0x1 _g_wSrsUpdataFlg
+ 0x100ded04 0x1 _g_wSrsUpdataFlg_Scell
+ 0x100ded05 0x2 _g_b_zPHY_eula_SrsSendFlag
+ 0x100ded07 0x1 _g_wMSG4AckINTLOCKCnt
+ 0x100ded08 0x1 _g_b711712Test1Test2Flg
+ 0x100ded09 0x1 _g_b711Test3Flg
+ .data 0x100ded0a 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x100ded0a 0x1 _wTddFddCaEnFlg
+ .data 0x100ded0b 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x100ded4f 0x1 _g_zPHY_RFQuickAdjTxoffsetFlag
+ .data 0x100ded50 0x58 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x100ded50 0x28 _g_zPHY_Int0HandleCfg
+ 0x100ded78 0x18 _g_zPHY_Int1HandleCfg
+ 0x100ded90 0x18 _g_zPHY_Int2HandleCfg
+ .data 0x100deda8 0x12 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ .data 0x100dedba 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x100dedba 0x1 _G_ZPHY_WORD32_BYTENUM
+ 0x100dedbb 0x1 _G_ZPHY_T_EngPrintMsg_BYTENUM
+ 0x100dedbc 0x1 _G_ZPHY_SIZEOF_WORD32
+ 0x100dedbd 0x1 _G_ZPHY_SIZEOF_WORD16
+ 0x100dedbe 0x1 _G_ZPHY_SIZEOF_T_EngPrintMsg
+ 0x100dedbf 0x1 _G_ZPHY_SIZEOF_T_EngLogHeader
+ 0x100dedc0 0x1 _g_bL1lLogOutUsing
+ .data 0x100dedc1 0x14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ .data 0x100dedd5 0x5d3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x100dedd5 0x60 _G_AC_UL_MODULE_CODE_SCHEME
+ 0x100dee35 0x4 _G_AC_ULS_RV_VALUE
+ 0x100dee39 0x234 _G_AW_ULS_TURBO_INTERLEAVER
+ 0x100df06d 0x46 _G_AC_UL_TDD_HARQ_ID_DATABASE
+ 0x100df0b3 0xa _G_AC_UL_FDD_HARQ_ID_DATABASE
+ 0x100df0bd 0x46 _G_AC_UL_NORM_HARQ_PUSCH_KVALUE
+ 0x100df103 0x46 _G_AC_UL_NORM_HARQ_PHICH_KVALUE
+ 0x100df149 0x46 _G_AC_UL_SPS_SUBFRAMOFFSET
+ 0x100df18f 0x46 _G_AC_UL_PRE_UL_SUBFRAME
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+ 0x100df225 0xa _G_AC_UL_NEXT_UL_SUBFRAME_FDD
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+ 0x100df3a6 0x1 _g_bIsRarNewTrans
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+ 0x100df407 0x1 _g_ReadTpFlagCnt
+ 0x100df408 0x1 _g_sdAtCtl_TxPowerValue
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+ .data 0x100df41d 0x2e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x100df445 0x1 _g_wL1eRxCrsIIRInd
+ 0x100df446 0x1 _g_wBchUseSoftNoFlag
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+ 0x100df449 0x2 _g_sdwRxTemp2
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+ .data 0x100df45b 0x24c0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
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+ 0x100df4a1 0x1e _g_ac_zPHY_edls_NcpSpeSubfrmCfg
+ 0x100df4bf 0x1b _g_ac_zPHY_edls_EcpSpeSubfrmCfg
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+ 0x100df4de 0x4 _g_ac_zPHY_edls_DeltaShiftBw4
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+ 0x100df5df 0x1a _g_ac_zPHY_edls_PrbIndexTabBw2
+ 0x100df5f9 0x10 _g_ac_zPHY_edls_PrbIndexTabBw1
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+ 0x100df6d1 0xc8 _g_ac_zPHY_edls_VrbTabBw5Gap2
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+ 0x100df82f 0x96 _g_ac_zPHY_edls_VrbTabBw4Gap2
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+ 0x100df929 0x64 _g_ac_zPHY_edls_VrbTabBw3Gap2
+ 0x100df98d 0x32 _g_ac_zPHY_edls_VrbTabBw2Gap1
+ 0x100df9bf 0x1e _g_ac_zPHY_edls_VrbTabBw1Gap1
+ 0x100df9dd 0xc _g_ac_zPHY_edls_VrbTabBw0Gap1
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+ 0x100e133d 0xbc _g_aw_zPHY_edls_TurboParaK
+ 0x100e13f9 0x20 _g_aw_zPHY_edls_PcInfoAnt2Dci2
+ 0x100e1419 0x100 _g_aw_zPHY_edls_PcInfoAnt4Dci2
+ 0x100e1519 0x8 _g_ac_zPHY_edls_PcInfoAnt4Dci2A
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+ 0x100e1528 0x7 _g_ac_zPHY_edls_DlHarqProNumMin
+ 0x100e152f 0x46 _g_ac_zPHY_edls_TddDlHarqCapM
+ 0x100e1575 0x46 _g_ac_zPHY_edls_TddDlHarqCapM_TddFddCA
+ 0x100e15bb 0x46 _g_ac_zPHY_edls_TddDlHarqTiming
+ 0x100e1601 0x46 _g_ac_zPHY_edls_TddDlHarqTiming_TddFddCA
+ 0x100e1647 0x46 _g_ac_zPHY_edls_TddDlHarqOrder
+ 0x100e168d 0x46 _g_ac_zPHY_edls_TddDlHarqOrder_TddFddCA
+ 0x100e16d3 0x46 _g_ac_zPHY_edls_TddDlHarqSetK
+ 0x100e1719 0xa _g_ac_zPHY_edls_FddDlHarqTiming
+ 0x100e1723 0x8 _awRohAPowerTable1ForSinglePort
+ 0x100e172b 0xa _awRohAPowerTable1
+ 0x100e1735 0x8 _awRohAVoltageTable1SinglePort
+ 0x100e173d 0xa _awRohAVoltageTable1
+ 0x100e1747 0x20 _awRohBPowerTable1ForSinglePort
+ 0x100e1767 0x20 _awRohBVoltageTable1SinglePort
+ 0x100e1787 0x28 _awRohBPowerTable2
+ 0x100e17af 0x28 _awRohBVoltageTable2
+ 0x100e17d7 0xa _awRohAPowerTable2
+ 0x100e17e1 0xa _awRohAVoltageTable2
+ 0x100e17eb 0x28 _awRohBPowerTable4
+ 0x100e1813 0x28 _awRohBVoltageTable4
+ 0x100e183b 0x8 _g_wLteL1MultiPortPA3dBRouAPow
+ 0x100e1843 0x20 _g_wLteL1MultiPortPA3dBRouBPow
+ 0x100e1863 0x8 _g_wLteL1MultiPortPA3dBRouAVol
+ 0x100e186b 0x20 _g_wLteL1MultiPortPA3dBRouBVol
+ 0x100e188b 0x8 _g_wLteL1MultiPortPA6dBRouAPow
+ 0x100e1893 0x20 _g_wLteL1MultiPortPA6dBRouBPow
+ 0x100e18b3 0x8 _g_wLteL1MultiPortPA6dBRouAVol
+ 0x100e18bb 0x20 _g_wLteL1MultiPortPA6dBRouBVol
+ 0x100e18db 0x20 _g_wLteL1MultiPortPA6dBRouBVolTable
+ 0x100e18fb 0x20 _g_wLteL1MultiPortPA6dBRouBPowTable
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+ .data 0x100e191f 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ .data 0x100e1929 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .data 0x100e192b 0x27c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x100e192b 0x13 _g_tzPHY_eulpc_At2UlPc
+ 0x100e193e 0x2 _g_zPHY_emc_dwIcpArm1CtrlInfoRegAddr
+ 0x100e1940 0x266 _g_ateMcMsgTable
+ 0x100e1ba6 0x1 _g_bPchReportFlag
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+ 0x100e1bc3 0x4 _g_zPHY_tLpcPwrDomainState
+ .data 0x100e1bc7 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ .data 0x100e1bd5 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ *fill* 0x100e1bd7 0x80000001 00
+ .data 0x100e1bd8 0xa82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x100e1bd8 0x800 _g_adw_Drv_Rx_CosineCoeff
+ 0x100e23d8 0x31 _g_aw_Drv_Rx_FiTriangleCoeff
+ 0x100e2409 0x62 _g_adw_Drv_Rx_FixedFirCoeff
+ 0x100e246b 0x62 _g_adw_Drv_Rx_Eicic_FixedFirCoeff
+ 0x100e24cd 0x62 _g_adw_Drv_Rx_FixFirCoeff_16QAM
+ 0x100e252f 0x62 _g_adw_Drv_Rx_FixFirCoeff_64QAM
+ 0x100e2591 0x62 _g_aw_Drv_FiCoeffPrbBundling
+ 0x100e25f3 0x66 _g_adwL1eDrvRxMbsfnFirCoeff
+ 0x100e2659 0x1 _g_wL1eDrvRxFirCoeffFormatInd
+ .data 0x100e265a 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ .data 0x100e265c 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ .data 0x100e2660 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ *fill* 0x100e2666 0x80000002 00
+ .data 0x100e2668 0x229 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x100e2668 0x80 _g_zPHY_erfc_atDBBMainSyncEvent
+ 0x100e26e8 0x80 _g_zPHY_erfc_atDBBMeas0Event
+ 0x100e2768 0x20 _g_zPHY_erfc_atDBBTxSendEvent
+ 0x100e2788 0x24 _g_zPHY_erfc_SubframeStartAddr
+ 0x100e27ac 0x24 _g_zPHY_erfc_SubframeDDRBackUpStartAddr
+ 0x100e27d0 0x8 _g_atzPHY_erfc_TuRegTxEvent
+ 0x100e27d8 0xb9 _g_atzPHY_erfc_TuRamTxEvent
+ *fill* 0x100e2891 0x80000003 00
+ .data 0x100e2894 0xb54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x100e2894 0x400 _g_atzPHY_erfc_atRFABBMainSyncEvent
+ 0x100e2c94 0x200 _g_atzPHY_erfc_atRFABBMeas0Event
+ 0x100e2e94 0x554 _g_atzPHY_erfc_atRFABBTxSendEvent
+ .data 0x100e33e8 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100e33e8 0x1 _g_zPHY_erfc_cTddOrFddTemp
+ 0x100e33e9 0x1 _g_zPHY_erfc_cTddOrFddSel
+ 0x100e33ea 0x1 _g_zPHY_erfc_cTddOrFddlast
+ .data 0x100e33eb 0x3a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x100e33ef 0x14 _AWNCPSUBFRMPATREGVALUE
+ 0x100e3403 0x22 _AWDFEECPSUBFRMPATREGVALUE
+ .data 0x100e3425 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x100e3425 0x2 _xlb_g_zPHY_SID
+ .data 0x100e3427 0x2e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x100e3427 0x2e _g_azPHY_ecsrc_abFilterFactor
+ .data 0x100e3455 0xf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x100e3455 0x2 _ptrSib1Req
+ 0x100e3457 0x2 _ptrSiReq
+ 0x100e3459 0x2 _gSirMrtr
+ 0x100e345b 0x2 _g_zPHY_emc_TpuUpdateSemId4SI
+ 0x100e345d 0x1 _g_wSibPrintCtrlCnt
+ 0x100e345e 0x1 _g_wSiPreSyncFlag
+ 0x100e345f 0x1 _g_wSiPreSchedFlag
+ 0x100e3460 0x1 _g_L1e_wAbortSiMsgProc
+ 0x100e3461 0x1 _g_L1e_wSiDelayProc
+ 0x100e3462 0x1 _g_wAnrBchFailInd
+ 0x100e3463 0x1 _g_wAnrBchSuccInd
+ .data 0x100e3464 0x16f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x100e3464 0x1 _g_bDrxLowCtrlFg
+ 0x100e3465 0xa _g_wRegTpuMsgId
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+ 0x100e34bf 0x103 _G_ZPS_LTE_ASYNMSG_NUM
+ 0x100e35c2 0x1 _g_zPHY_emc_tCpMode
+ 0x100e35c3 0x1 _g_zPHY_emc_bPagingPoAndGapConflictFlag
+ 0x100e35c4 0x1 _g_zPHY_emc_bPagingPoCallBackFlag
+ 0x100e35c5 0x1 _gwUe4RxRcvFalg
+ 0x100e35c6 0x1 _g_zPHY_emc_bRfcETCSuspendFlag
+ 0x100e35c7 0x2 _g_zPHY_emc_TpuUpdateSemId4Com
+ 0x100e35c9 0x2 _g_zPHY_emc_TpuUpdateSemId4HO
+ 0x100e35cb 0x2 _g_zPHY_emc_TpuUpdateSemId4PreSync
+ 0x100e35cd 0x1 _g_bMaxTimeAdvance
+ 0x100e35ce 0x1 _g_wFreqAbortcellsearchConflictTimer
+ 0x100e35cf 0x1 _wCommInSiProc
+ 0x100e35d0 0x2 _dwLastRxoffset
+ 0x100e35d2 0x1 _g_wDelayAnrCnt
+ .data 0x100e35d3 0x1081 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x100e35d3 0x8 _g_zPHY_SearchPeriod
+ 0x100e35db 0x39c _g_zPHY_ecsrc_tEarfcnTable
+ 0x100e3977 0x42 _s_awzPHY_CsrcEarfcnMInBandTable
+ 0x100e39b9 0xa5 _g_adwCsrcTpuEventTable
+ 0x100e3a5e 0x4 _g_awPiSearchPeriod
+ 0x100e3a62 0x4 _g_awPiSearchPeriodAT
+ 0x100e3a66 0x4 _g_awPiSearchPeriodPerDrx
+ 0x100e3a6a 0x4 _g_awPiSearchPeriodSpeed
+ 0x100e3a6e 0x4 _g_awPiSearchPeriodFixStrong
+ 0x100e3a72 0x4 _g_awMovCtxSchPeriod
+ 0x100e3a76 0x4 _g_awCfoUpdatePeriod
+ 0x100e3a7a 0x60 _g_atCsrEventManage
+ 0x100e3ada 0x5a _g_L1e_C0_UtcInfo
+ 0x100e3b34 0x8 _DelaySteps
+ 0x100e3b3c 0x67 _Delay
+ 0x100e3ba3 0x20 _SchedServCellSteps
+ 0x100e3bc3 0x67 _SchedServCell
+ 0x100e3c2a 0x8 _AdjustBndFrmCfoSteps
+ 0x100e3c32 0x67 _AdjustBndFrmCfo
+ 0x100e3c99 0x14 _SchedOneFreqSteps
+ 0x100e3cad 0x67 _SchedOneFreq
+ 0x100e3d14 0xc _SchedIntraSteps
+ 0x100e3d20 0x67 _SchedIntra
+ 0x100e3d87 0x18 _SchedInterSteps
+ 0x100e3d9f 0x67 _SchedInter
+ 0x100e3e06 0x4 _SchedInitSteps
+ 0x100e3e0a 0x67 _SchedInit
+ 0x100e3e71 0x28 _SchedIdleSteps
+ 0x100e3e99 0x67 _SchedIdle
+ 0x100e3f00 0x1 _g_bCsrPlmnStatusFlagNew
+ 0x100e3f01 0x1 _g_csrc_wSearchInFreqscanState
+ 0x100e3f02 0x1 _g_zPHY_ecsrc_bNeedAdjustBndFrmCfo
+ 0x100e3f03 0x1 _g_zPHY_Csrc_bConnSetInterFg
+ 0x100e3f04 0x2 _g_AtZepcgSetLowPower
+ 0x100e3f06 0x63f _g_SchedContext
+ 0x100e4545 0x10f _g_ThreadCsrc
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+ 0x100e4654 0x180 _G_AC_RA_RESR_CFG_FDD
+ 0x100e47d4 0x80 _G_AC_RA_RESR_CFG_TDD1
+ 0x100e4854 0x43d _G_AC_RA_RESR_CFG_TDD2
+ 0x100e4c91 0x20 _G_AW_NCS_VAL_FORMAT0TO3
+ 0x100e4cb1 0x10 _G_AW_NCS_VAL_FORMAT4
+ 0x100e4cc1 0x346 _G_AW_P_VAL_FORMAT0TO3
+ 0x100e5007 0x8a _G_AW_P_VAL_FORMAT4
+ 0x100e5091 0x5 _G_ASC_DELTA_PREAMBLE_VAL
+ 0x100e5096 0x8 _G_ASC_MSG_POWOFFSET_GROUPB
+ 0x100e509e 0x6 _G_AW_RA_BASEBAND_PARAS_1_4
+ 0x100e50a4 0x6 _G_AW_RA_BASEBAND_PARAS_3
+ 0x100e50aa 0x6 _G_AW_RA_BASEBAND_PARAS_5
+ 0x100e50b0 0x6 _G_AW_RA_BASEBAND_PARAS_10
+ 0x100e50b6 0x6 _G_AW_RA_BASEBAND_PARAS_15_20
+ 0x100e50bc 0x6 _G_AW_RA_BASEBAND_PARAS
+ 0x100e50c2 0x5 _G_AC_PREAMBLE_LENGTH
+ 0x100e50c7 0x10 _G_AW_BI_VALUE
+ 0x100e50d7 0x24 _G_AC_FID_VALUE_FORMAT0TO3
+ 0x100e50fb 0x39 _g_zPHY_erapc_tCtrlBlock
+ .data 0x100e5134 0x46e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x100e5134 0x1 _g_zPHY_emulm_PlmnSearchMeasFlag
+ 0x100e5135 0x2 _g_azPHY_emulm_UsedGapCount
+ 0x100e5137 0x18 _MulmCsAgcSteps
+ 0x100e514f 0x67 _MulmCsAgc
+ 0x100e51b6 0x18 _MulmCsPssSteps
+ 0x100e51ce 0x67 _MulmCsPss
+ 0x100e5235 0xc _MulmCsTpuAdjType1Steps
+ 0x100e5241 0x67 _MulmCsTpuAdjType1
+ 0x100e52a8 0xc _MulmCsTpuAdjType2Steps
+ 0x100e52b4 0x67 _MulmCsTpuAdjType2
+ 0x100e531b 0x14 _MulmCsCfoOnceSteps
+ 0x100e532f 0x67 _MulmCsCfoOnce
+ 0x100e5396 0x14 _MulmCsCfoSteps
+ 0x100e53aa 0x67 _MulmCsCfo
+ 0x100e5411 0x18 _MulmCsSssSteps
+ 0x100e5429 0x67 _MulmCsSss
+ 0x100e5490 0x34 _MulmCellSearchOnceSteps
+ 0x100e54c4 0x67 _MulmCellSearchOnce
+ 0x100e552b 0xc _MulmCellSearchProcSteps
+ 0x100e5537 0x67 _MulmCellSearchProc
+ 0x100e559e 0x1 _g_eCsrsTpuAdjStep
+ 0x100e559f 0x1 _g_L1e_mulm_SatisfyFlag
+ 0x100e55a0 0x1 _g_L1e_mulm_SlaveLpcFlagCnt
+ 0x100e55a1 0x1 _g_bMulmConnectedAbortGapFlag
+ .data 0x100e55a2 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ .data 0x100e55b0 0x1e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ .data 0x100e55ce 0xc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ 0x100e55ce 0x6 _g_awL1eFddMbsfnSubfNumTab
+ 0x100e55d4 0x6 _g_awL1eTddMbsfnSubfNumTab
+ .data 0x100e55da 0x5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x100e55da 0x1 _g_wDrxUnActiveFlag
+ 0x100e55db 0x1 _g_wDrxActiveFlag
+ 0x100e55dc 0x1 _g_zPHY_emc_bDediHoReveFlag
+ 0x100e55dd 0x1 _g_zPHY_emc_bDrxActvieFlag
+ 0x100e55de 0x1 _g_wLastPreSyncAbsSubf
+ .data 0x100e55df 0x194 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x100e55df 0x2 _g_zPHY_AMT_Tool_Agc_Open
+ 0x100e55e1 0x4 _g_tLteAmtAfc
+ 0x100e55e5 0x186 _g_zPHY_tCurrentBandCtrlInfo
+ 0x100e576b 0x2 _ptLteAmtFdtParameter
+ 0x100e576d 0x2 _g_tLteAmtFdtParameter
+ 0x100e576f 0x2 _ptLteAmtFstParameter
+ 0x100e5771 0x2 _g_tLteAmtFstParameter
+ .data 0x100e5773 0x40 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ 0x100e57ac 0x1 _g_sbFixTaAutoAdjFlg
+ 0x100e57ad 0x2 _g_dwRaPIDNotMatchCnt
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+ 0x100e67ff 0x6 _g_aw_zPHY_FDD_DCI01APadding_COM
+ 0x100e6805 0x6 _g_aw_zPHY_DCI_1C_COM
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+ 0x100e72b4 0x2 _g_ptTi_Ctl
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+ 0x100e7450 0xbe _GainValueConfig_TDD
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+ 0x100e75cc 0x7 _g_pcZcosVersion
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+ 0x100e75d3 0x4 _gtHuntList
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+ 0x100e75d7 0x2 _efuseMutex
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+ 0x100e77b0 0x2 LONG 0xa (SIZEOF (.d2tcm_s) / 0x2)
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+
+.display
+ *(.display_data_buffer)
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+
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+ .bss 0x100f0b70 0x392 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ .bss 0x100f0f02 0x43a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ .bss 0x100f133c 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ .bss 0x100f133f 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ .bss 0x100f1340 0x259c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ .bss 0x100f38dc 0x1d2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ .bss 0x100f3aae 0x564 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ .bss 0x100f4012 0x1e1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ .bss 0x100f41f3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ .bss 0x100f41f4 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ .bss 0x100f41f7 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ .bss 0x100f41fd 0x981 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ .bss 0x100f4b7e 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ .bss 0x100f4ba2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ .bss 0x100f4ba3 0x82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ .bss 0x100f4c25 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ *fill* 0x100f4c27 0x80000001 00
+ .bss 0x100f4c28 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ .bss 0x100f4c6d 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ .bss 0x100f4c70 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ .bss 0x100f4c72 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ .bss 0x100f4c76 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ .bss 0x100f4c77 0x234 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .bss 0x100f4eab 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ .bss 0x100f4eb3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ .bss 0x100f4eb4 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ .bss 0x100f4eb6 0x72 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ .bss 0x100f4f28 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ .bss 0x100f4f2a 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ .bss 0x100f4f7a 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ .bss 0x100f4f7d 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ .bss 0x100f4f7e 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ .bss 0x100f4f80 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ *(COMMON)
+ COMMON 0x100f4fb4 0x6 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x0 (size before relaxing)
+ 0x100f4fb4 0x6 _err_msg
+ COMMON 0x100f4fba 0x18f T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x0 (size before relaxing)
+ 0x100f4fba 0x18f _odo_sys
+ COMMON 0x100f5149 0x44 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x0 (size before relaxing)
+ 0x100f5149 0x1 _zsp_cmm_len
+ 0x100f514a 0x5 _g_L1ErrInfo
+ 0x100f514f 0x3e _zsp_ramdump_regs
+ COMMON 0x100f518d 0x364 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x0 (size before relaxing)
+ 0x100f518d 0x1 _g_erfc_cnt
+ 0x100f518e 0x302 _g_atHookInfo
+ 0x100f5490 0x60 _g_erfc_tpu
+ 0x100f54f0 0x1 _gIramHookCnt
+ COMMON 0x100f54f1 0x1c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x0 (size before relaxing)
+ 0x100f54f1 0x1 _g_wRficRev
+ 0x100f54f2 0x1b _g_awTempDAC
+ COMMON 0x100f550d 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x0 (size before relaxing)
+ 0x100f550d 0x1a _g_tL1wCallStackInfo
+ COMMON 0x100f5527 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x0 (size before relaxing)
+ 0x100f5527 0x1 _g_uComPhyFunc
+ COMMON 0x100f5528 0xd00 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x0 (size before relaxing)
+ 0x100f5528 0x100 _gReadBlockCnt
+ 0x100f5628 0x100 _RpMsgRead_Exit
+ 0x100f5728 0x100 _gWriteBlockCnt
+ 0x100f5828 0x100 _gRpMsgWriteMutex
+ 0x100f5928 0x100 _s_RpMsgCallbackList
+ 0x100f5a28 0x300 _phy2ps_chinfo
+ 0x100f5d28 0x100 _rpMsgSem
+ 0x100f5e28 0x300 _ps2phy_chinfo
+ 0x100f6128 0x100 _gRpMsgReadMutex
+ COMMON 0x100f6228 0x9 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x0 (size before relaxing)
+ 0x100f6228 0x2 _g_L1_tModeState
+ 0x100f622a 0x6 _g_L1_tLpmCaliTime
+ 0x100f6230 0x1 _g_L1_tLpCalibrationFlag
+ COMMON 0x100f6231 0xd T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x0 (size before relaxing)
+ 0x100f6231 0x9 _g_L1wPriTaskPid
+ 0x100f623a 0x4 _g_L1wIsrTaskPid
+ COMMON 0x100f623e 0xc9e6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x0 (size before relaxing)
+ 0x100f623e 0xbec _g_tWcdmaUserNv
+ 0x100f6e2a 0x22c _g_tL1wNvBb
+ 0x100f7056 0xbbca _g_tWcdmaCalibNv
+ 0x10102c20 0x4 _g_tL1wAtNv
+ COMMON 0x10102c24 0x427 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x0 (size before relaxing)
+ 0x10102c24 0x3eb _g_tL1wDevMeasInfo
+ 0x1010300f 0x3c _g_atMeasSpsrInfo
+ COMMON 0x1010304b 0x5b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x0 (size before relaxing)
+ 0x1010304b 0x4e4 _s_tL1wDevHsupaInfo
+ 0x1010352f 0xcf _g_PsrUpdateReq
+ COMMON 0x101035fe 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x0 (size before relaxing)
+ 0x101035fe 0x1 _g_SSC_CFLT_chip
+ 0x101035ff 0x14 _g_tRfcNotchInfo
+ 0x10103613 0x24 _g_tWRfcRpiPwrCtl
+ 0x10103637 0x1 _g_wRfcResetState
+ 0x10103638 0x1 _g_SSC_CFLT_ssfn
+ 0x10103639 0x2 _g_zPHYRfcSSCDebugCnt
+ COMMON 0x1010363b 0x13e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x0 (size before relaxing)
+ 0x1010363b 0x48 _tPcDataDb
+ 0x10103683 0x62 _tPcCnt
+ 0x101036e5 0x94 _g_tPcDpchSirCalInfo
+ COMMON 0x10103779 0x113 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x0 (size before relaxing)
+ 0x10103779 0x2 _g_Rt
+ 0x1010377b 0x11 _g_tL1wHsdpaSnrAdjInfo
+ 0x1010378c 0x36 _g_tHsdpaAdrIcRstInfo
+ 0x101037c2 0x6 _g_tL1wHsdpaDbgInfo
+ 0x101037c8 0x78 _g_tL1wHsdpaPacketInfo
+ 0x10103840 0x19 _g_tHsdpaIcFingerDiffInfo
+ 0x10103859 0x1 _g_wAdrIcEn
+ 0x1010385a 0x26 _g_tL1wHsdpaCodingInfo
+ 0x10103880 0x1 _g_wL1wHsdpaRxDivMode
+ 0x10103881 0xb _g_tHsdpaResetInfo
+ COMMON 0x1010388c 0x191 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x0 (size before relaxing)
+ 0x1010388c 0x168 _g_atLessDecodeCfg
+ 0x101039f4 0x28 _g_atLessDemoluleCfg
+ 0x10103a1c 0x1 _g_wL1wLessCfgIdx
+ COMMON 0x10103a1d 0x1b6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x0 (size before relaxing)
+ 0x10103a1d 0x1b6 _g_tUlRfTbl
+ COMMON 0x10103bd3 0x26c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x0 (size before relaxing)
+ 0x10103bd3 0x26c _g_tWuldataBuf
+ COMMON 0x10103e3f 0x624 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x0 (size before relaxing)
+ 0x10103e3f 0x604 _g_uLSfInfo
+ 0x10104443 0x20 _g_atL1wHsupaFirstTranPara
+ COMMON 0x10104463 0xd06 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x0 (size before relaxing)
+ 0x10104463 0x12 _g_tRfcPowerAdcReadInfo
+ 0x10104475 0x5a _g_atRfcAgcDbLog
+ 0x101044cf 0x1 _g_eAntSel
+ 0x101044d0 0x1 _g_bNvCheck
+ 0x101044d1 0x1 _g_wRfcTxRxState
+ 0x101044d2 0x318 _g_tRfcCtrlDbRx
+ 0x101047ea 0x26 _g_tRfcGapMixLog
+ 0x10104810 0x5df _g_tRfcAgcDb
+ 0x10104def 0x1e _g_atRfcStateLog
+ 0x10104e0d 0x1 _g_eDivState
+ 0x10104e0e 0xb _g_tRfcAfcDb
+ 0x10104e19 0x1 _g_eAntState
+ 0x10104e1a 0x318 _g_tRfcCtrlDbTx
+ 0x10105132 0x23 _g_tRfcCmnInfoLOG
+ 0x10105155 0xe _g_tRfcTxPowLog
+ 0x10105163 0x5 _g_tRfcTmpReadInfo
+ 0x10105168 0x1 _g_eRfcRamState
+ COMMON 0x10105169 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x0 (size before relaxing)
+ 0x10105169 0x4 _g_wAdrIcCellState
+ 0x1010516d 0x1 _g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1010516e 0x5 _g_awL1wHsdpaMvalue
+ 0x10105173 0x4 _g_wSubFrmOffset
+ 0x10105177 0x1 _g_wL1wHsdpaHsdpcchUldpcchOffset
+ 0x10105178 0xf _g_awL1wHsdpaCfnSlot2SfnSubFrm
+ 0x10105187 0x1 _g_wL1wHsdpaSfnCfnOffset
+ COMMON 0x10105188 0x2824 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x0 (size before relaxing)
+ 0x10105188 0x24 _s_tCsStatisticInfo
+ 0x101051ac 0x2800 _dwPeakInfoInSlot
+ COMMON 0x101079ac 0xc5d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x0 (size before relaxing)
+ 0x101079ac 0x26 _g_tPcUphDb
+ 0x101079d2 0x3e _tDevEngStardardParam
+ 0x10107a10 0x559 _g_tPcOverEstDb
+ 0x10107f69 0x3e3 _tPcBetaDb
+ 0x1010834c 0xa _swPcTimeOff
+ 0x10108356 0x1 _wTimeOff
+ 0x10108357 0xa _swPcTimeOff2
+ 0x10108361 0x95 _tPcCalcDb
+ 0x101083f6 0x2 _g_tIqMappingCon
+ 0x101083f8 0x146 _tPcInfoDb
+ 0x1010853e 0xcb _tMprTest
+ COMMON 0x10108609 0x286 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x0 (size before relaxing)
+ 0x10108609 0x4 _g_awL1wStandardMsgRpt
+ 0x1010860d 0x80 _g_awL1wPrintMsgProcRpt
+ 0x1010868d 0x2 _gL1w_MissLogInfo
+ 0x1010868f 0x200 _g_awL1wEngTempBuffer
+ COMMON 0x1010888f 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x0 (size before relaxing)
+ 0x1010888f 0x5 _g_RxDataPn9Check
+ 0x10108894 0x2 _g_dwCfgSsfn
+ 0x10108896 0x1 _g_RxTtiNum
+ 0x10108897 0x1 _g_RxTfciNum
+ 0x10108898 0x2 _g_dwTtiSsfn
+ COMMON 0x1010889a 0x11c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x0 (size before relaxing)
+ 0x1010889a 0xe _g_tWUpaStdlogStatisitcInfo
+ 0x101088a8 0x2 _g_EdchNewTbTotal
+ 0x101088aa 0x20 _g_atWHsupaEhichInfTab
+ 0x101088ca 0x1 _g_EagchCnt500Ms
+ 0x101088cb 0x38 _g_tWUpaStdlogPacketInfo
+ 0x10108903 0x2 _g_EdchTbTotal
+ 0x10108905 0x10 _g_atWHsupaEdchReadyFlag
+ 0x10108915 0x36 _g_tWUpaUlDebugInfo
+ 0x1010894b 0x6b _g_tWUpaDlDebugInfo
+ COMMON 0x101089b6 0x11b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x0 (size before relaxing)
+ 0x101089b6 0xc _g_atL1wCellType
+ 0x101089c2 0x2f _g_tL1wMeasCellReq
+ 0x101089f1 0x24 _g_atL1wRlsTrace
+ 0x10108a15 0x8 _g_tL1wFmoDlsPsrParaConfig
+ 0x10108a1d 0x2 _g_tL1wPsrAntNumPara
+ 0x10108a1f 0x2 _g_dIntIndex
+ 0x10108a21 0xe _g_tL1wCmPsrPatternInfo
+ 0x10108a2f 0x1 _g_wL1wDpchOffset
+ 0x10108a30 0x2f _g_tL1wDchDlsLastReq
+ 0x10108a5f 0x2f _g_tL1wDchDlsPsrReq
+ 0x10108a8e 0x6 _g_asL1wAdujstFlag
+ 0x10108a94 0x4 _g_tL1wHsupaRlToPsr
+ 0x10108a98 0x7 _g_tL1wFachDlsPsrReq
+ 0x10108a9f 0x1 _g_sL1wUlAdujstFlag
+ 0x10108aa0 0x2 _g_dOldUlTiming
+ 0x10108aa2 0x2f _g_tL1wDpaRlReqInfo
+ COMMON 0x10108ad1 0xec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x0 (size before relaxing)
+ 0x10108ad1 0xe8 _g_tResInfo
+ 0x10108bb9 0x4 _g_tSendIcpTpuTime
+ COMMON 0x10108bbd 0x163 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x0 (size before relaxing)
+ 0x10108bbd 0x106 _g_tL1wAfcFreqOffsetValue
+ 0x10108cc3 0x30 _g_atL1wRxHistoryIQBuffer
+ 0x10108cf3 0x3 _g_tAfcErrorPrint
+ 0x10108cf6 0x20 _g_tL1wAfcWorkPara
+ 0x10108d16 0x6 _g_tL1wSlaveAfcWorkPara
+ 0x10108d1c 0x4 _g_tL1wBchDataHistoryIQValue
+ COMMON 0x10108d20 0xe47 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x0 (size before relaxing)
+ 0x10108d20 0x1a _g_adL1wTpuTaskID
+ 0x10108d3a 0x235 _g_atL1wTpuRegRtVarEventInfo
+ 0x10108f6f 0x4db _g_atL1wTpuRegNtVarEventInfo
+ 0x1010944a 0x4 _g_tL1wTpuLastMicroAdjustInfo
+ 0x1010944e 0x1 _g_wL1wTpuDoffVal
+ 0x1010944f 0x8 _g_tL1wTpuFrmInfo
+ 0x10109457 0x710 _g_atL1wTpuRegNtFixedEventInfo
+ *fill* 0x10109b67 0x80000001 00
+ COMMON 0x10109b68 0x427f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x0 (size before relaxing)
+ 0x10109b68 0x7c _g_tL1wDevDbHsdpaCfgReqB
+ 0x10109be4 0x7a _g_atDevBchAfcdb
+ 0x10109c5e 0x3d6 _g_tL1wDevDbUlDpchCfgReqA
+ 0x1010a034 0x7c _g_tL1wDevDbHsdpaCfgReqA
+ 0x1010a0b0 0x41c _g_tL1wDevDbRtxIscpInfo
+ 0x1010a4cc 0x4 _g_tL1wDevDbRaMacProcReq
+ 0x1010a4d0 0x7e _g_tL1wDevDbDlFdpchCfgReqA
+ 0x1010a54e 0xf8 _g_tDevDbHsupaCfgReqB
+ 0x1010a646 0x382 _g_tL1wDevDbPageFachCfgReq
+ 0x1010a9c8 0x2 _g_tL1wDevDbTrchTtiInfo
+ 0x1010a9ca 0xf8 _g_tDevDbHsupaCfgReqA
+ 0x1010aac2 0x39a _g_tL1wDevDbRaEraRrcReq
+ 0x1010ae5c 0x5 _g_tL1wDevDbHsdpaInd
+ 0x1010ae61 0x880 _g_tDevDbHsdpaFingMaskBuffer
+ 0x1010b6e1 0x27 _g_tDevDbHspaToMacInfo
+ 0x1010b708 0x200 _g_tDevDbHsdpaAdrCirData
+ 0x1010b908 0x1a70 _g_tL1wDevDbRtxAfcInfo
+ 0x1010d378 0xb _g_tDevDbHsdpaAntSwitch
+ 0x1010d383 0x62 _g_tL1wDevDbHsdpaPlusPchCfgReq
+ 0x1010d3e5 0x4be _g_tL1wDevDbDlDpchCfgReqA
+ 0x1010d8a3 0x544 _g_tWDevDbHspaPlusFachCfgReq
+ COMMON 0x1010dde7 0x85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010dde7 0x3b _g_tRxEng
+ 0x1010de22 0x4a _g_tDlCpchEng
+ COMMON 0x1010de6c 0x86 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x0 (size before relaxing)
+ 0x1010de6c 0x4 _g_tRfcIQInfo
+ 0x1010de70 0x2 _g_sdAnt0CarrierPhase
+ 0x1010de72 0x78 _g_atRfcDcLog
+ 0x1010deea 0x2 _g_sdAnt1CarrierPhase
+ 0x1010deec 0x4 _g_tRfcDcInfo
+ 0x1010def0 0x2 _g_tRfcDagcGain
+ COMMON 0x1010def2 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x0 (size before relaxing)
+ 0x1010def2 0x38 _g_TopRegLpcSave
+ COMMON 0x1010df2a 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x0 (size before relaxing)
+ 0x1010df2a 0xa _g_wTpuRtRegLpcSave
+ 0x1010df34 0x36 _g_wTpuNtRegLpcSave
+ COMMON 0x1010df6a 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x0 (size before relaxing)
+ 0x1010df6a 0xd0 _g_atL1wDrvMeasResultInfo
+ COMMON 0x1010e03a 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x0 (size before relaxing)
+ 0x1010e03a 0x2 _g_dL1wDprICPSSFN
+ 0x1010e03c 0x1 _g_wLastSubframe
+ 0x1010e03d 0x1 _g_wL1wDprModState
+ 0x1010e03e 0x26 _g_tL1wDrvDpramStruct
+ 0x1010e064 0x2 _g_dL1wDprResetCnfSSFN
+ 0x1010e066 0x2 _g_wL1wDprSubFrmCnt
+ 0x1010e068 0xa _g_awReportCFN
+ COMMON 0x1010e072 0x808 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010e072 0x808 _s_tDrvRxCfg
+ COMMON 0x1010e87a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010e87a 0x7b8 _g_tRegRxRakeReg
+ COMMON 0x1010f032 0x7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x0 (size before relaxing)
+ 0x1010f032 0x1 _wLastBand
+ 0x1010f033 0x2 _g_l1wATSetAPCTmpCmpVal
+ 0x1010f035 0x2 _g_l1wATOriAPCTmpCmpVal
+ 0x1010f037 0x2 _g_l1wATSetAPCFlag
+ COMMON 0x1010f039 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x0 (size before relaxing)
+ 0x1010f039 0x1 _g_TxCfgOver
+ 0x1010f03a 0x1 _g_TpuCfgOver
+ COMMON 0x1010f03b 0x415 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x0 (size before relaxing)
+ 0x1010f03b 0x3a _g_tRfcDrvOpen
+ 0x1010f075 0x1 _g_wRfOpCnt
+ 0x1010f076 0x3a _g_atLastRfcOpen
+ 0x1010f0b0 0x3a0 _g_atRfcOpen
+ COMMON 0x1010f450 0xa3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ 0x0 (size before relaxing)
+ 0x1010f450 0xa3 _g_tL1wInnerCellDb
+ COMMON 0x1010f4f3 0x8f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ 0x0 (size before relaxing)
+ 0x1010f4f3 0x19 _g_tL1wCtrlDb
+ 0x1010f50c 0x1c _g_tL1MainMixInfo
+ 0x1010f528 0x1 _g_eL1wAmtL1sStateInfo
+ 0x1010f529 0x1a _g_tL1wStateCnt
+ 0x1010f543 0x3f _g_tL1wProcSetDb
+ COMMON 0x1010f582 0xf4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ 0x0 (size before relaxing)
+ 0x1010f582 0x1 _g_wBackupCellMainIdx
+ 0x1010f583 0x79 _g_tServCellDb
+ 0x1010f5fc 0x60 _g_atBackupCellInfo
+ 0x1010f65c 0x1a _g_tL1wAddionCtrl
+ COMMON 0x1010f676 0xa1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ 0x0 (size before relaxing)
+ 0x1010f676 0xa1 _g_tWL1sHsupaProcInfo
+ COMMON 0x1010f717 0x350 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ 0x0 (size before relaxing)
+ 0x1010f717 0x5a _g_tL1wCmCfnN0123Bitmap
+ 0x1010f771 0x78 _g_atL1wCmWaitCfgPatternDB
+ 0x1010f7e9 0x5a _g_tL1wCmCfnN0123BitmapTemp
+ 0x1010f843 0xdc _g_tL1wCmInnerInfo
+ 0x1010f91f 0xca _g_tL1wCmInfoForN4N9
+ 0x1010f9e9 0x7e _g_tL1wPsCmConfigBuffer
+ COMMON 0x1010fa67 0x339 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ 0x0 (size before relaxing)
+ 0x1010fa67 0xa0 _g_atL1RfSegInfo
+ 0x1010fb07 0x4 _g_tTimerCnt
+ 0x1010fb0b 0x2 _g_tL1wResCtrl
+ 0x1010fb0d 0x28f _g_tL1wRfTbl
+ 0x1010fd9c 0x3 _g_tL1wResAgcCtrl
+ 0x1010fd9f 0x1 _g_wRfSegNum
+ COMMON 0x1010fda0 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ 0x0 (size before relaxing)
+ 0x1010fda0 0x33 _g_tDchAscPara
+ COMMON 0x1010fdd3 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd3 0x1 _g_RxRachAiNum
+ 0x1010fdd4 0x1 _g_RxAichIntCnt
+ COMMON 0x1010fdd5 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd5 0x1 _g_wMissHdtrInt
+ COMMON 0x1010fdd6 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd6 0x5 _g_tPcPrachConfigInfo
+ 0x1010fddb 0x1 _g_swPrachSlotPower
+ 0x1010fddc 0x13 _g_tRtxPcPrachMessageInfo
+ COMMON 0x1010fdef 0x18 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010fdef 0x18 _g_atL1wHsupaDlCmPattern
+ COMMON 0x1010fe07 0x1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x0 (size before relaxing)
+ 0x1010fe07 0x4 _g_L1LteAIsrTaskPid
+ 0x1010fe0b 0x2 _g_pSemId_INTH1
+ 0x1010fe0d 0x11 _g_L1LteAPriTaskPid
+ 0x1010fe1e 0x2 _g_pSemId_ICP
+ 0x1010fe20 0x2 _g_pSemId_TXIntPulse
+ 0x1010fe22 0x2 _g_pSemId_INTH2
+ COMMON 0x1010fe24 0x2bf08 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x0 (size before relaxing)
+ 0x1010fe24 0x8 _g_tUEIdInfo
+ 0x1010fe2c 0x28000 _g_zPHY_AMT_tNVInfo
+ 0x10137e2c 0x2540 _g_zPHY_tNVInfo
+ 0x1013a36c 0x198c _g_zPHY_tNV_user
+ 0x1013bcf8 0x2e _g_zPsPhyATNvLte
+ 0x1013bd26 0x6 _g_zPsPhyATNvcom
+ COMMON 0x1013bd2c 0xe5b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x0 (size before relaxing)
+ 0x1013bd2c 0x158 _g_EUL_SrsStatisticsInfo
+ 0x1013be84 0x136 _g_EDL_PDSCH_INFO
+ 0x1013bfba 0x2 _g_dwUlResidualBlerCount
+ 0x1013bfbc 0xb8 _g_EUL_CqiHarqSimulStatisticsInfo
+ 0x1013c074 0x2 _g_EDL_PA_INFO
+ 0x1013c076 0xc _g_UL_SrHarqSimulStatisticsInfo
+ 0x1013c082 0x2a _g_UE_BASE_INFO
+ 0x1013c0ac 0x4 _g_dwTxThroughPutBps
+ 0x1013c0b0 0x72 _g_EDL_PCFICH_INFO
+ 0x1013c122 0x82 _g_EUL_Dci0Info
+ 0x1013c1a4 0x10e _g_EDL_PHICH_INFO
+ 0x1013c2b2 0x4 _g_dwUlNewTransCount
+ 0x1013c2b6 0x8 _g_EUL_DCI3Or3AInfo
+ 0x1013c2be 0x230 _g_EDL_DCI_INFO
+ 0x1013c4ee 0x4 _g_dwRxThroughPutBps
+ 0x1013c4f2 0x40 _g_EDL_CALC_For_SINR
+ 0x1013c532 0x12 _g_EDLUL_FLOW_INFO
+ 0x1013c544 0x20 _g_EUL_PucchFmtStatisticsInfo
+ 0x1013c564 0x44 _g_UL_MutiplexingANStatisticsInfo
+ 0x1013c5a8 0x9a _g_EDL_HARQ_INFO
+ 0x1013c642 0x52 _g_EUL_HarqTransStatisticsInfo
+ 0x1013c694 0x3c _g_EDL_WORK_INFO
+ 0x1013c6d0 0x22 _g_EUL_AT_INFO
+ 0x1013c6f2 0x3c _g_EUL_BunldingANStatisticsInfo
+ 0x1013c72e 0x52 _g_EUL_PowerCtrlInfo
+ 0x1013c780 0x2d0 _g_EDL_PDCCH_INFO
+ 0x1013ca50 0x2 _gdwUlTmtFlowCount
+ 0x1013ca52 0x54 _g_EDL_AT_INFO
+ 0x1013caa6 0x2 _g_TmtLogCnt
+ 0x1013caa8 0x2 _gdwTmtFlowCount
+ 0x1013caaa 0xd9 _g_EUL_PrachStatisticsInfo
+ 0x1013cb83 0x4 _g_dwUlHarqFailCount
+ COMMON 0x1013cb87 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x0 (size before relaxing)
+ 0x1013cb87 0x4 _gt_CsiPrintCtrl
+ 0x1013cb8b 0x1 _g_wLastAbsSfn
+ 0x1013cb8c 0x1 _g_wCsiWorkFlg
+ COMMON 0x1013cb8d 0x16 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x0 (size before relaxing)
+ 0x1013cb8d 0x4 _g_adwTbCbCrc
+ 0x1013cb91 0x10 _g_adwDebugDLS
+ 0x1013cba1 0x2 _g_awTbCrc
+ COMMON 0x1013cba3 0x51 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x0 (size before relaxing)
+ 0x1013cba3 0x1 _g_zPHY_bDdtrWorkFlag
+ 0x1013cba4 0x1 _wTest
+ 0x1013cba5 0x2 _g_zPHY_dwDdtrCfgTimer
+ 0x1013cba7 0x2 _g_awHarqPrintFlg
+ 0x1013cba9 0x32 _g_tdbCqi2DlsPmiInfo
+ 0x1013cbdb 0x2 _dwCrcRlt
+ 0x1013cbdd 0x14 _awCfgHarqErr
+ 0x1013cbf1 0x2 _g_awHarqPreTime
+ 0x1013cbf3 0x1 _g_wLayerNum
+ COMMON 0x1013cbf4 0x89 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x0 (size before relaxing)
+ 0x1013cbf4 0x2 _g_dwOffsetDelta
+ 0x1013cbf6 0x2 _g_zPHY_erfc_tempDac
+ 0x1013cbf8 0x1 _g_zPHY_erfc_TempStartRecordFlag
+ 0x1013cbf9 0x1 _g_dwOffsetFlag
+ 0x1013cbfa 0x1 _g_zPHY_erfc_wMID2RXFlag
+ 0x1013cbfb 0x1 _g_slot1_nRBNum
+ 0x1013cbfc 0x14 _g_asdzPHY_erfc_CirServOrNeibor
+ 0x1013cc10 0x1 _g_zPHY_erfc_Meas0SubfNum
+ 0x1013cc11 0x2 _g_dwSubframeNumForTest
+ 0x1013cc13 0x2 _g_zPHY_erfc_CleanTxoffset
+ 0x1013cc15 0x2 _g_zPHY_erfc_Meas0Offset
+ 0x1013cc17 0x1 _g_zPHY_erfc_wSyncState
+ 0x1013cc18 0x1 _g_slot0_RBStart
+ 0x1013cc19 0x2 _g_zPHY_erfc_Meas1Offset
+ 0x1013cc1b 0x2 _g_zPHY_erfc_InitialTempDac
+ 0x1013cc1d 0x2 _g_zPHY_erfc_TxMulmOffset
+ 0x1013cc1f 0x2 _g_zPHY_erfc_RxoffsetAcumulator
+ 0x1013cc21 0x2 _g_AgcHwModeOnFalg
+ 0x1013cc23 0x1 _g_zPHY_erfc_eAcp405NextState
+ 0x1013cc24 0x1 _g_slot1_RBStart
+ 0x1013cc25 0x1 _g_zPHY_erfc_eAcp405CurrState
+ 0x1013cc26 0x1 _g_wReadState
+ 0x1013cc27 0x4 _g_tLteRfcTmpReadInfo
+ 0x1013cc2b 0x14 _g_adzPHY_erfc_MainAntInd
+ 0x1013cc3f 0x1 _g_zPHY_erfc_TaTimer
+ 0x1013cc40 0x2 _g_adzPHY_erfc_CurMainAntInd
+ 0x1013cc42 0x2 _g_dwTxoffset
+ 0x1013cc44 0x2 _g_dwDbgSubfCount
+ 0x1013cc46 0x1 _g_slot0_nRBNum
+ 0x1013cc47 0x33 _gtLteRfcRpiPwrCtl
+ 0x1013cc7a 0x2 _g_zPHY_erfc_RfStateMap
+ 0x1013cc7c 0x1 _g_zPHY_erfc_Meas0SubfDef
+ COMMON 0x1013cc7d 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x0 (size before relaxing)
+ 0x1013cc7d 0x1 _g_wRi1LstCqi
+ 0x1013cc7e 0x1 _g_wStartCNTFlg
+ 0x1013cc7f 0x61 _gt_CsiFilter
+ 0x1013cce0 0x1 _g_wLstTm
+ 0x1013cce1 0xaa _g_atCsiPmiRiCalcResult
+ 0x1013cd8b 0x1 _g_wCNT
+ COMMON 0x1013cd8c 0xbb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x0 (size before relaxing)
+ 0x1013cd8c 0x28 _g_L1e_dwPbchEvtList
+ 0x1013cdb4 0x1e _g_L1e_tPbchCB
+ 0x1013cdd2 0x22 _g_L1e_tMibRxReg
+ 0x1013cdf4 0x9 _g_L1e_tDlaparaSave
+ 0x1013cdfd 0x14 _g_L1e_tMibPbchReg
+ 0x1013ce11 0x15 _g_L1e_tMibInfo
+ 0x1013ce26 0xc _g_L1e_tBchOps
+ 0x1013ce32 0xa _g_DbgMibPerStat
+ 0x1013ce3c 0xb _g_L1e_tMibRfcBackUp
+ COMMON 0x1013ce47 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x0 (size before relaxing)
+ 0x1013ce47 0x1 _g_wMsg4AckRaConflictCnt
+ 0x1013ce48 0x1 _g_wHarqGroupNum
+ COMMON 0x1013ce49 0x9c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x0 (size before relaxing)
+ 0x1013ce49 0x9 _g_atCqiCommonInfo
+ 0x1013ce52 0x1 _g_awCqiPmiRiIndex
+ 0x1013ce53 0xd _g_atBandWidthInfo
+ 0x1013ce60 0xa _g_adAperLastCqiPmiDataBuffer
+ 0x1013ce6a 0x1 _g_awAPERLastRI
+ 0x1013ce6b 0x32 _g_atCsiEnFinal
+ 0x1013ce9d 0x8 _g_atPeriodRepPara
+ 0x1013cea5 0x1 _g_awLastReportIndex
+ 0x1013cea6 0x2 _g_awLastWBPMI
+ 0x1013cea8 0x4 _g_tCsiTime
+ 0x1013ceac 0x1 _g_awLastWBCQICW0
+ 0x1013cead 0x1 _g_awRiBitLen
+ 0x1013ceae 0x1 _g_awAPERLastWBCQICW0
+ 0x1013ceaf 0x2 _g_awLastRI
+ 0x1013ceb1 0x32 _g_atCqiDedicateInfo
+ 0x1013cee3 0x1 _g_awLastWBCQICW1
+ 0x1013cee4 0x1 _g_awMaxLayerNum
+ COMMON 0x1013cee5 0x233b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x0 (size before relaxing)
+ 0x1013cee5 0x50 _g_awFHopSeq4SubBands
+ 0x1013cf35 0x2 _g_dwTpcPrintCnt
+ 0x1013cf37 0x50 _g_awFHopSeq3SubBands
+ 0x1013cf87 0x2 _g_dwSrsPrintCnt
+ 0x1013cf89 0x2 _g_dwPucchPrintCnt
+ 0x1013cf8b 0x2 _g_dwPrachPrintCnt
+ 0x1013cf8d 0x50 _g_awFHopSeq2SubBands
+ 0x1013cfdd 0x4 _g_awSpecPrachNum
+ 0x1013cfe1 0x50 _g_awFmSeq
+ 0x1013d031 0xe98 _g_zPHY_etx_HarqProDbPort0
+ 0x1013dec9 0x50 _g_awFmSeq_Scell
+ 0x1013df19 0x8 _g_t_zPHY_etx_Uls_H2L_HarqProcessIDInfo
+ 0x1013df21 0x8 _g_t_zPHY_etx_HarqProcessIDInfo
+ 0x1013df29 0x25f _g_awUlTestMacPduBuf
+ 0x1013e188 0x50 _g_awFHopSeq2SubBands_Scell
+ 0x1013e1d8 0xe98 _g_zPHY_etx_HarqProDbPort1
+ 0x1013f070 0x104 _g_t_zPHY_Dls2UlsDciValue
+ 0x1013f174 0x50 _g_awFHopSeq4SubBands_Scell
+ 0x1013f1c4 0x2 _g_dwCloseLoopPowerPrintCnt
+ 0x1013f1c6 0x2 _g_dwPuschPrintCnt
+ 0x1013f1c8 0x50 _g_awFHopSeq3SubBands_Scell
+ 0x1013f218 0x8 _g_t_zPHY_etx_RarUlGrant
+ COMMON 0x1013f220 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x0 (size before relaxing)
+ 0x1013f220 0x1 _g_swPrintProNoInt
+ 0x1013f221 0x10 _g_asdwL1eRxCrsRsrp
+ 0x1013f231 0x4 _g_adwL1eRxCrsRssi
+ 0x1013f235 0x4 _g_lsdwNsIot_8242_SINR
+ 0x1013f239 0x18 _g_adwL1eRxDrsRsp
+ 0x1013f251 0x1 _g_zPHY_emc_wCellComponFlag
+ 0x1013f252 0xc _g_adwL1eRxCrsRsp
+ 0x1013f25e 0x1 _g_wLtel1IdleAccessReqInd
+ 0x1013f25f 0x1 _g_awL1eRxBfDagcFlag
+ 0x1013f260 0x1 _g_awL1eRxBfTransFlag
+ 0x1013f261 0x1 _g_wL1eRxNbNbSinrCalInd
+ 0x1013f262 0xb _g_zPHY_emc_tSinrInfo
+ 0x1013f26d 0x1 _g_awL1eRxDrsAccNum
+ COMMON 0x1013f26e 0x118e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x0 (size before relaxing)
+ 0x1013f26e 0xa _g_awPSeqCellIDDiv30
+ 0x1013f278 0x12b _g_tUlaLtxParas
+ 0x1013f3a3 0x46 _g_awPSeqCellIDDiv30SS
+ 0x1013f3e9 0x1 _g_EUL_wPuschPowerIdx
+ 0x1013f3ea 0x1 _g_EUL_wPucchPowerIdx
+ 0x1013f3eb 0xe7 _g_tUlaCommRelatedParasScell
+ 0x1013f4d2 0x46 _g_awPSeqCellIDDiv30SS_Scell
+ 0x1013f518 0x1 _g_EUL_wSrsPowerIdx
+ 0x1013f519 0x6 _g_tUlaDediRelatedParas
+ 0x1013f51f 0x4 _g_tUlaCID
+ 0x1013f523 0xa6d _g_t_zPHY_eula_CtrlBlock
+ 0x1013ff90 0x50 _g_awPSeqCellID
+ 0x1013ffe0 0x1c _g_tUlaCommConfig
+ 0x1013fffc 0xac _g_tUlaDediConfig
+ 0x101400a8 0xa _g_awPSeqPuschSeqShift
+ 0x101400b2 0xc8 _g_tUlaScellInfo
+ 0x1014017a 0xe7 _g_tUlaCommRelatedParas
+ 0x10140261 0xa _g_awPSeqCellIDDiv30_Scell
+ 0x1014026b 0x1f _g_tUlaPucchInfo
+ 0x1014028a 0x120 _g_tSrsInfo
+ 0x101403aa 0x50 _g_awPSeqCellID_Scell
+ 0x101403fa 0x1 _g_w_FirstFlgSet
+ 0x101403fb 0x1 _g_EUL_wPrachPowerIdx
+ COMMON 0x101403fc 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x0 (size before relaxing)
+ 0x101403fc 0x1 _g_L1l_LpmCaliIdx
+ 0x101403fd 0x8 _g_L1l_MrtrBeforeWakup
+ 0x10140405 0xa _g_wTpuIntTypeforlpm
+ 0x1014040f 0x2 _g_L1l_LpmCaliCnt
+ 0x10140411 0x6 _g_zPHY_tSuperFrameCtrlInfo
+ 0x10140417 0x22 _g_zPHY_tWakeupTimerInfo
+ 0x10140439 0x1 _g_zPHY_dwTpuSleepTimeLenByFrame
+ 0x1014043a 0x1 _g_L1lLpAwakeTimerCtrl
+ 0x1014043b 0x2 _g_zPHY_tWakeupReq
+ 0x1014043d 0x1 _g_L1lLpTaskStateCtrl
+ 0x1014043e 0x2 _g_L1l_LpmModemWakeupTime
+ 0x10140440 0x2 _g_L1l_LpmCaliAbortTime
+ 0x10140442 0x2 _g_tL1lLpCtrl
+ 0x10140444 0x2 _g_L1l_LpmSocWakeupTime
+ 0x10140446 0x2 _g_zPHY_LtePhySleepCnt
+ 0x10140448 0x8 _g_L1l_MrtrAfterSleep
+ COMMON 0x10140450 0x14e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x0 (size before relaxing)
+ 0x10140450 0x10 _g_adw_zPHY_erfc_profile_DB
+ 0x10140460 0x2 _g_dwLPTxoffset
+ 0x10140462 0x1 _g_zPHY_erfc_AfcWord
+ 0x10140463 0xc0 _g_zPHY_erfc_aNVBandIndex
+ 0x10140523 0x39 _g_zPHY_erfc_atLPCSFConfig
+ 0x1014055c 0x2 _g_zPHY_erfc_ACP405Version
+ 0x1014055e 0x40 _g_at_zPHY_erfc_atReloadData
+ COMMON 0x1014059e 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x0 (size before relaxing)
+ 0x1014059e 0x1 _g_zPHY_ecsrm_wNextIntFlag
+ 0x1014059f 0x1 _g_ZPHY_ecsrm_tMeasState
+ 0x101405a0 0xf _g_zPHY_ecsrm_tCommInfo
+ COMMON 0x101405af 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x0 (size before relaxing)
+ 0x101405af 0x120 _g_MeasContext
+ COMMON 0x101406cf 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x0 (size before relaxing)
+ 0x101406cf 0x7 _g_tUlBlerInfo
+ *fill* 0x101406d6 0x80000002 00
+ COMMON 0x101406d8 0x3ec T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x0 (size before relaxing)
+ 0x101406d8 0x2 _g_awMbmsClusterNum
+ 0x101406da 0x1 _g_ePreRapcState
+ 0x101406db 0x30 _g_aswMBMS_MaxDelay
+ 0x1014070b 0x31 _g_aswMBMS_FftWinStart
+ 0x1014073c 0xc4 _g_aswFreq_Inter_Coeff
+ 0x10140800 0xc4 _g_aswFreq_NormalCoeff
+ 0x101408c4 0x200 _g_aiInitSequence
+ COMMON 0x10140ac4 0x1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x0 (size before relaxing)
+ 0x10140ac4 0x14 _g_tLteA1DlaRxCb
+ 0x10140ad8 0x4 _g_awL1eRxRsrpFilter
+ 0x10140adc 0x4 _g_awL1eRxRsrpFilterFlag
+ COMMON 0x10140ae0 0x3cf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x0 (size before relaxing)
+ 0x10140ae0 0x1 _g_zPHY_edfe_wAgcEnEventFlag
+ 0x10140ae1 0x8 _g_tTempDCOffsetComp
+ 0x10140ae9 0xd _g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0x10140af6 0x1 _g_zPHY_edfe_wRxLinDagc1
+ 0x10140af7 0x1 _g_zPHY_edfe_swAgcMeanPwr1
+ 0x10140af8 0x2 _g_zPHY_edfe_dwScanFreqAgcCalFlag
+ 0x10140afa 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp0
+ 0x10140afc 0x1 _g_zPHY_edfe_wNotSyncAGCDone
+ 0x10140afd 0x1 _g_zPHY_edfe_wRfcSingleAnt
+ 0x10140afe 0x8 _g_tIQComp
+ 0x10140b06 0x1 _g_wAgcCntForFirstDC
+ 0x10140b07 0x6 _g_awAgcGain0
+ 0x10140b0d 0x1 _g_zPHY_edfe_wAgcLog2Gain0
+ 0x10140b0e 0x1 _g_zPHY_edfe_wCsrsLinDagc0
+ 0x10140b0f 0x1 _g_zPHY_edfe_wCsrmLinDagc1
+ 0x10140b10 0x78 _g_zPHY_edfe_MeasAgcPara
+ 0x10140b88 0x1 _g_wCount
+ 0x10140b89 0x120 _g_a_zPHY_edfe_tReloadAgcData
+ 0x10140ca9 0x1 _g_zPHY_edfe_cRxAntennaMode
+ 0x10140caa 0x18 _g_zPHY_edfe_tPlmnAgcPara
+ 0x10140cc2 0x8 _g_tDCOffsetCompRecord
+ 0x10140cca 0x2 _g_dwCsrmRssiRx0
+ 0x10140ccc 0x1 _g_zPHY_edfe_wAgcExtendModeEn
+ 0x10140ccd 0x6 _g_awAgcGain1
+ 0x10140cd3 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp7
+ 0x10140cd5 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt1
+ 0x10140cd6 0x1 _g_zPHY_edfe_wRxLinDagc0
+ 0x10140cd7 0x28 _g_a_zPHY_edfe_wCsrmTotalAgcGainLog2
+ 0x10140cff 0x78 _g_tDfeNotchInfo
+ 0x10140d77 0x1 _g_zPHY_edfe_wAgcIntReportFlag
+ 0x10140d78 0x6 _g_awTempMeanPower1
+ 0x10140d7e 0x1 _g_zPHY_edfe_wAgcMeaPwSavReg
+ 0x10140d7f 0x1 _g_zPHY_edfe_wAgcLog2Gain1
+ 0x10140d80 0x1 _g_zPHY_edfe_wSaveRxBand
+ 0x10140d81 0x1 _g_wAgcWorkState
+ 0x10140d82 0x1 _g_zPHY_edfe_wCsrmLinDagc0
+ 0x10140d83 0x1 _g_zPHY_edfe_wRfcSyncState
+ 0x10140d84 0xd7 _g_EDFE_SYSTEM_INFO
+ 0x10140e5b 0x1 _g_zPHY_edfe_swAgcMeanPwr0
+ 0x10140e5c 0x1 _g_zPHY_edfe_wAgcdBGain0
+ 0x10140e5d 0x2 _g_DcCounter
+ 0x10140e5f 0x8 _g_tDCOffsetEsti
+ 0x10140e67 0x2 _g_dwCsrmRssiRx1
+ 0x10140e69 0x8 _g_tDCOffsetComp
+ 0x10140e71 0x1 _g_wIqCount
+ 0x10140e72 0x2 _g_zPHY_edfe_dwSearchAgcCalFlag
+ 0x10140e74 0x1 _g_zPHY_edfe_wCsrsLinDagc1
+ 0x10140e75 0x28 _g_a_zPHY_edfe_wRxTotalAgcGainLog2
+ 0x10140e9d 0x1 _g_zPHY_erfc_SlaveOutGapAGC
+ 0x10140e9e 0x1 _g_wCsrs_RX_Sib1_Read_Flag
+ 0x10140e9f 0x8 _g_zPHY_edfe_tRxAgcBalance
+ 0x10140ea7 0x6 _g_awTempMeanPower0
+ 0x10140ead 0x1 _g_zPHY_edfe_wAgcdBGain1
+ 0x10140eae 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ COMMON 0x10140eaf 0x1e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x0 (size before relaxing)
+ 0x10140eaf 0x1 _g_eTxCalibrationStep
+ 0x10140eb0 0x1 _g_wTxSendScaleDC
+ 0x10140eb1 0x4 _g_awDfeFftOutputDC
+ 0x10140eb5 0x4 _g_awDfeFftOutputIQ
+ 0x10140eb9 0x2 _g_dwCalibration_angle
+ 0x10140ebb 0x1d3 _g_atzPHY_UlAMTHarqProcessDB
+ 0x1014108e 0x1 _g_wTxSendScaleIQ
+ 0x1014108f 0x1 _Configdelay
+ 0x10141090 0x2 _g_dwCalibration_amp
+ COMMON 0x10141092 0x269d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x0 (size before relaxing)
+ 0x10141092 0x1 _g_wAutoDeactiveTimer
+ 0x10141093 0x6 _g_t_zPHY_DlaDciInfo
+ 0x10141099 0xa _g_tL1eDevRxLpConvergeCb
+ 0x101410a3 0x268c _g_t_zPHY_DlaCb
+ COMMON 0x1014372f 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x0 (size before relaxing)
+ 0x1014372f 0x2 _g_Scc_Rsrp_Cfo_IntCnt
+ 0x10143731 0x1 _g_wULA_Process_SubFrame
+ 0x10143732 0x2 _gTimer1Int_RcvNum
+ 0x10143734 0x6 _g_zPHY_Int_dwDFEIntType
+ 0x1014373a 0x2 _g_zPHY_Int_dwDFEIntType_agc
+ COMMON 0x1014373c 0xc0a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x0 (size before relaxing)
+ 0x1014373c 0x2 _g_dwL1lPreHookEntry
+ 0x1014373e 0x2 _gL1l_MissLogInfo
+ 0x10143740 0xc00 _g_awL1lEngTempBuffer
+ 0x10144340 0x2 _L1L_STANDARD_LOG_ID_BASE
+ 0x10144342 0x2 _g_dwL1lCurrentHookEntry
+ 0x10144344 0x2 _g_wL1lRemainLen
+ COMMON 0x10144346 0x138d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x0 (size before relaxing)
+ 0x10144346 0xd _g_tTTIBundlingDB
+ 0x10144353 0xe _g_zPHY_euls_tTpcCommands
+ 0x10144361 0x1 _g_EUL_wRachIdx
+ 0x10144362 0x14 _g_tRarCtrlDB
+ 0x10144376 0x2 _g_EUL_wDci0InfoIdx
+ 0x10144378 0x2d _g_tUlSPSDB
+ 0x101443a5 0x2a _g_zPHY_euls_ComConfig
+ 0x101443cf 0x123e _g_tShadowHarqDB
+ 0x1014560d 0x8 _g_tUlsDB
+ 0x10145615 0x72 _g_atDCI0PhichSelecDB
+ 0x10145687 0x4c _g_zPHY_euls_DedConfig
+ COMMON 0x101456d3 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x0 (size before relaxing)
+ 0x101456d3 0x4 _g_zPHY_erfc_tCordicAdjustPara
+ 0x101456d7 0x2 _g_ACP405_AFC_DIFF
+ 0x101456d9 0x5 _g_zPHY_erfc_tAfcPara
+ 0x101456de 0x28 _g_sdAtCtl_ApcOffsetTime
+ COMMON 0x10145706 0x2c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x0 (size before relaxing)
+ 0x10145706 0x2 _gadwZeroCsiRsCollideInd
+ 0x10145708 0x2 _gau_zPHY_Rx_CsiRsIdicator
+ 0x1014570a 0x1 _g_PchBlerInfo_0
+ 0x1014570b 0x8 _gau_zPHY_Rx_ZeroPowerCisPos
+ 0x10145713 0x1 _g_PchBlerInfo_3
+ 0x10145714 0x2 _g_dwRxPreN0Value
+ 0x10145716 0x1 _g_wPrbNoPrintFlg
+ 0x10145717 0x2 _gauZeroPowerCsiBitMap
+ 0x10145719 0x2 _gadwCsiRsCollideInd
+ 0x1014571b 0x1 _g_PchBlerInfo_1
+ 0x1014571c 0x1 _g_PchTiCfgInd_1
+ 0x1014571d 0x2 _gadwZeroPowerCsiRsPosCalculated
+ 0x1014571f 0x1 _g_tRxPreState
+ 0x10145720 0x1 _g_wPchFlag
+ 0x10145721 0x1 _g_tRxCurrState
+ 0x10145722 0x1 _g_PchBlerInfo_4
+ 0x10145723 0x2 _g_dwTempN0
+ 0x10145725 0x1 _gwNS_IOT_8242_Ind
+ 0x10145726 0x1 _g_awL1eRxNCellRsNullEnInd
+ 0x10145727 0x2 _gadwCsiRsPosCalculated
+ 0x10145729 0x1 _g_awRxCirTiCfgInd
+ 0x1014572a 0x2 _gt_zPHY_Rx_ZeroCsiRsExistInd
+ 0x1014572c 0x2 _g_awCsiRsCheCfgVal
+ 0x1014572e 0x1 _g_PchBlerInfo_2
+ 0x1014572f 0x1 _g_PchTiCfgInd_2
+ 0x10145730 0x2 _gt_zPHY_Rx_CsiRsExistInd
+ COMMON 0x10145732 0xa04 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ 0x0 (size before relaxing)
+ 0x10145732 0x510 _g_adwCommDlschPara1A
+ 0x10145c42 0x300 _g_adwCommDlschPara1C
+ 0x10145f42 0x1f4 _g_adwPhyNirDivC
+ COMMON 0x10146136 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x0 (size before relaxing)
+ 0x10146136 0x24c _g_TopReg
+ 0x10146382 0xc _g_LteaTopIntRegBitMap
+ COMMON 0x1014638e 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x0 (size before relaxing)
+ 0x1014638e 0xa _g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0x10146398 0x1 _g_wRLMATQInFlg
+ 0x10146399 0x2 _g_sdRLMATQIn
+ 0x1014639b 0x1 _g_zPHY_emc_wSIDataBufSel
+ 0x1014639c 0x2 _g_sdRLMATQOut
+ 0x1014639e 0x1 _g_wRLMATQOutFlg
+ 0x1014639f 0x1e _g_zPHY_emc_tScheduleSiReq
+ 0x101463bd 0x8 _g_zPHY_emc_tPchDataRecvCtrlInfo
+ 0x101463c5 0x6 _g_zPHY_emc_tReadSib1Req
+ COMMON 0x101463cb 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x0 (size before relaxing)
+ 0x101463cb 0x8 _g_zPHY_tLpcPwrCtrlScenExpect
+ COMMON 0x101463d3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x0 (size before relaxing)
+ 0x101463d3 0x1 _g_VrbFlag
+ COMMON 0x101463d4 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x0 (size before relaxing)
+ 0x101463d4 0x2 _g_zPHY_erfc_dwConFr40AuxAdcClkBase
+ 0x101463d6 0x2 _g_dwAptFixVoltageNvSet
+ 0x101463d8 0x2 _g_zPHY_erfc_dwConFr11_19Xtal
+ 0x101463da 0x2 _g_zPHY_erfc_dwConFr24LowRefMode
+ 0x101463dc 0x2 _g_ACP405_RxPGC1_Word
+ 0x101463de 0x2 _g_ACP405_RxPGC0_Word
+ 0x101463e0 0x2 _g_zPHY_erfc_dwConFr33RefClk
+ COMMON 0x101463e2 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x0 (size before relaxing)
+ 0x101463e2 0x28 _g_a_zPHY_edfe_dwLpcSaveReg
+ COMMON 0x1014640a 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x0 (size before relaxing)
+ 0x1014640a 0xa _g_CsrGapInfo
+ COMMON 0x10146414 0x63b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x0 (size before relaxing)
+ 0x10146414 0x1 _g_dwCsrIntraRsrpFilterPrintCnt
+ 0x10146415 0x2 _g_swCsr_Rssi_SearCnf
+ 0x10146417 0x55d _g_zPHY_ecsrc_tFilterInterMeas
+ 0x10146974 0x2 _g_swCsr_Rssi_Report
+ 0x10146976 0xc4 _g_zPHY_ecsrc_tFilterIntraMeas
+ 0x10146a3a 0x1 _g_awAgcNoBalance
+ 0x10146a3b 0x12 _g_zPHY_ecsrc_tFilterFactor
+ 0x10146a4d 0x1 _g_dwCsrInterRsrpFilterPrintCnt
+ 0x10146a4e 0x1 _g_dwCsrInterRsrpFilterRepPrintCnt
+ COMMON 0x10146a4f 0x11b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x0 (size before relaxing)
+ 0x10146a4f 0x78 _g_L1e_dwSirEvtList
+ 0x10146ac7 0x5 _g_l1e_tSirRxRcv
+ 0x10146acc 0x95 _g_L1e_tSirDb
+ 0x10146b61 0x1 _g_zPHY_wSibStartPbchTimes
+ 0x10146b62 0x1 _g_L1e_wSibRptDelay
+ 0x10146b63 0x6 _g_L1e_tSibCrc
+ 0x10146b69 0x1 _g_L1e_wSiTimingNeibState
+ COMMON 0x10146b6a 0x352b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x0 (size before relaxing)
+ 0x10146b6a 0x2ee0 _g_awSyncMsgBuff
+ 0x10149a4a 0x5 _g_zPHY_tRfRxOffsetCfgInfo
+ 0x10149a4f 0x1 _g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x10149a50 0x96 _g_zPHY_emc_tCommonConfigReq
+ 0x10149ae6 0x2 _g_zPHY_emc_tMcCtrlParam
+ 0x10149ae8 0x1 _g_zPHY_emc_wSoftResetOkFlag
+ 0x10149ae9 0x2 _g_dwNextX
+ 0x10149aeb 0x1 _g_zPHY_emc_bGapConfigState
+ 0x10149aec 0x1 _g_wSCellDeactivationTimerParam
+ 0x10149aed 0x1 _g_zPHY_emc_wReleaseDlDelayCnt
+ 0x10149aee 0x50 _g_atzPhy_emc_SyncMsgInfo
+ 0x10149b3e 0x1 _g_wPlmnRapcConflictTimer
+ 0x10149b3f 0x1 _g_zPHY_emc_wIsCampOn
+ 0x10149b40 0x4 _g_zPHY_emc_tTimingCtrlParam
+ 0x10149b44 0x4 _g_zPHY_emc_ScellCtrlReq
+ 0x10149b48 0x2 _g_dwGapStatue
+ 0x10149b4a 0x1 _g_zPHY_emc_wUseServeInfoFlag
+ 0x10149b4b 0x1 _g_zPHY_emc_wReleaseRfcIdleModeOkCnt
+ 0x10149b4c 0x4 _g_zPHY_emc_tTACtrlParam
+ 0x10149b50 0x2 _g_dwSubFrm
+ 0x10149b52 0x2 _g_dwErrorNum
+ 0x10149b54 0x13 _g_zPHY_emc_tDrxSPSCtrlInfo
+ 0x10149b67 0x1 _g_ePrePhyState
+ 0x10149b68 0x4 _g_awSCellDeactivationTimer
+ 0x10149b6c 0x412 _g_zPHY_emc_tDedicatedConfigReq
+ 0x10149f7e 0x8 _g_zPHY_emc_tAccessReq
+ 0x10149f86 0x1 _g_zPHY_emc_wCommonMsgDisPathFlag
+ 0x10149f87 0x1 _g_wThinkWill_Flg
+ 0x10149f88 0x50 _g_CellSearchData
+ 0x10149fd8 0xd _g_zPHY_emc_tRec_Tpu
+ 0x10149fe5 0x1 _g_zPHY_emc_wSetModeOkFlag
+ 0x10149fe6 0x86 _g_FreqScanData
+ 0x1014a06c 0x2 _g_zPHY_emc_tReleaseCtrlParam
+ 0x1014a06e 0x3 _g_zPHY_emc_tRaMsgHoldFlag
+ 0x1014a071 0x24 _g_L1e_tDlRfcCfgInfo
+ COMMON 0x1014a095 0x1513 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x0 (size before relaxing)
+ 0x1014a095 0x1 _g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1014a096 0x1 _g_zPHY_ecsrc_wPiPeriod
+ 0x1014a097 0x8 _g_zPHY_ecsrc_tSearchMeasAgeThrold
+ 0x1014a09f 0x2 _g_zPHY_ecsrs_dwTpuAdjTime
+ 0x1014a0a1 0x86 _g_zPHY_ecsrc_tFreqScanReq
+ 0x1014a127 0x28 _g_zPHY_ecsrc_tCommInfo
+ 0x1014a14f 0x4 _g_L1e_Csrc_PreCfo
+ 0x1014a153 0x10 _g_zPHY_ecsrc_tEarfcnTable_B28
+ 0x1014a163 0x39e _g_zPHY_ecsrc_tCsrPsInterMeasInd
+ 0x1014a501 0x55 _g_L1e_Csrc_C0Update
+ 0x1014a556 0x6 _g_zPHY_ecsrc_tMeasMaskSetBack
+ 0x1014a55c 0x50 _g_zPHY_ecsrc_tCellSearchReq
+ 0x1014a5ac 0x1f _g_zPHY_ecsrc_tCnnDrxMeasSchedule
+ 0x1014a5cb 0x6 _g_zPHY_ecsrc_tMeasMaskSetReq
+ 0x1014a5d1 0x82 _g_zPHY_ecsrc_tFreqScanCnf
+ 0x1014a653 0x4 _g_atAgeTimer
+ 0x1014a657 0x1 _g_L1e_Csrc_DisFreqScan
+ 0x1014a658 0x1 _g_zPHY_ecsrc_wScheduleInfoCnt
+ 0x1014a659 0x1 _g_L1e_C0ConIntraRptCnt
+ 0x1014a65a 0x1 _g_L1e_C0ConDrxCnt
+ 0x1014a65b 0x6 _g_L1e_Csrc_CurPpm
+ 0x1014a661 0x1 _g_wcsrc_HoOnflag
+ 0x1014a662 0x2ae _g_zPHY_ecsrc_tCsrPsIntraMeasInd
+ 0x1014a910 0x1 _g_zPHY_ecsrc_wWorkInterFreqIndex
+ 0x1014a911 0x6a7 _g_zPHY_ecsrc_tCsrCellDatabase
+ 0x1014afb8 0x9 _g_zPHY_ecsrc_tFliterSchduInd
+ 0x1014afc1 0x1 _g_zPHY_wHoStartPbchTimes
+ 0x1014afc2 0x2 _g_zPHY_ecsrc_dwCsrcFlag
+ 0x1014afc4 0x2 _g_L1e_csrc_tMeasPeriodChgReq
+ 0x1014afc6 0x1 _g_zPHY_ecsrc_AferGapFlag
+ 0x1014afc7 0x12 _g_zPHY_ecsrc_wDoneInterPerDrx
+ 0x1014afd9 0x5c8 _g_zPHY_ecsrc_tMeasConfigReq
+ 0x1014b5a1 0x2 _g_zPHY_ecsrc_swBackupCFOFreqOffset
+ 0x1014b5a3 0x1 _g_L1e_ConnIntraRptCnt
+ 0x1014b5a4 0x1 _g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1014b5a5 0x2 _g_L1eTempAdc
+ 0x1014b5a7 0x1 _g_L1e_Csrc_bCellSearchPbch
+ COMMON 0x1014b5a8 0x1c2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ 0x0 (size before relaxing)
+ 0x1014b5a8 0x1c1 _g_aw_RarMacPdu
+ 0x1014b769 0x1 _g_zPHY_swRsrpFilter
+ COMMON 0x1014b76a 0x919 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x0 (size before relaxing)
+ 0x1014b76a 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x1014b772 0x134 _g_zPHY_ecsrc_tMulmFreqListConfig
+ 0x1014b8a6 0x8 _g_zPHY_ecsrc_tIratGapConfig
+ 0x1014b8ae 0x3 _g_tSlaveSearchMeasAgeThrold
+ 0x1014b8b1 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReqBackUp
+ 0x1014b8b9 0x1 _g_zPHY_emulm_PlmnSearchMeasCnt
+ 0x1014b8ba 0x6 _g_zPHY_emulm_tFilterFactor
+ 0x1014b8c0 0x1 _g_L1e_mulm_NoSatisfyCfoCnt
+ 0x1014b8c1 0x2 _g_zPHY_SetModeReq
+ 0x1014b8c3 0x6 _g_zPHY_ecsrc_tMulmInactiveTimeInd
+ 0x1014b8c9 0x1a _g_zPHY_emulm_SlaveHwEnable
+ 0x1014b8e3 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfigBackUp
+ 0x1014b8e9 0x8 _g_zPHY_ecsrc_tIratGapConfig1
+ 0x1014b8f1 0x1 _g_L1e_mulm_40msGapCnt
+ 0x1014b8f2 0x2 _g_zPHY_emulm_tMulmIdlePeriodReqFlag
+ 0x1014b8f4 0x3 _g_zPHY_emulm_tMulmAfcPara
+ 0x1014b8f7 0x165 _g_zPHY_ecsrc_atSlaveMeasInfo
+ 0x1014ba5c 0x621 _g_zPHY_emulm_tFilterMeas
+ 0x1014c07d 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfig
+ COMMON 0x1014c083 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x0 (size before relaxing)
+ 0x1014c083 0x11 _g_RxOpenPara
+ COMMON 0x1014c094 0x88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x0 (size before relaxing)
+ 0x1014c094 0x6c _g_zPHY_emc_tDrxCtrlInfo
+ 0x1014c100 0xa _g_wIntTypeforDrx
+ 0x1014c10a 0x10 _g_awDrxUlRetranCnt
+ 0x1014c11a 0x2 _g_Next2SubFrameDrxActiveSidFlag
+ COMMON 0x1014c11c 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x0 (size before relaxing)
+ 0x1014c11c 0x1 _g_wFIUpdate2RLM
+ 0x1014c11d 0xf _g_zPHY_emc_tRadioLinkCtrlInfo
+ COMMON 0x1014c12c 0x19c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x0 (size before relaxing)
+ 0x1014c12c 0x10 _g_tLteAmtCellSyncPara
+ 0x1014c13c 0x157 _g_tLteAmtInfo
+ 0x1014c293 0x2 _g_zPHY_AMT_SearchCellCnt
+ 0x1014c295 0x2 _g_zPHY_AMT_Strongest_CellId
+ 0x1014c297 0x1f _gtAmtCellSyncProc
+ 0x1014c2b6 0x2 _g_zPHY_AMT_Strongest_Rsrp
+ 0x1014c2b8 0x2 _g_zPHY_AMT_Earfcn
+ 0x1014c2ba 0xa _g_zPHY_AMT_SrvCellRsrp
+ 0x1014c2c4 0x2 _g_dwFdt10MsCnt
+ 0x1014c2c6 0x2 _g_zPHY_AMT_Frequency
+ COMMON 0x1014c2c8 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x0 (size before relaxing)
+ 0x1014c2c8 0x2 _g_tHandoverCnf
+ 0x1014c2ca 0x488 _g_tHandoverReq
+ COMMON 0x1014c752 0x5a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x0 (size before relaxing)
+ 0x1014c752 0xa _g_wIntTypeforPaging
+ 0x1014c75c 0x12 _g_tL1eSchedPreSyncCb
+ 0x1014c76e 0x3a _g_tL1eDcxoProcCb
+ 0x1014c7a8 0x2 _g_zPHY_sdwRxAnt0OffsetValue
+ 0x1014c7aa 0x2 _g_zPHY_sdwRxAnt1OffsetValue
+ COMMON 0x1014c7ac 0x248 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x0 (size before relaxing)
+ 0x1014c7ac 0x23a _g_atzPHY_RFSD
+ 0x1014c9e6 0xa _g_atCsiATCMDInfo
+ 0x1014c9f0 0x4 _g_zPHY_LteRfWorkSet
+ COMMON 0x1014c9f4 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x0 (size before relaxing)
+ 0x1014c9f4 0x18 _g_tL1lCallStackInfo
+ COMMON 0x1014ca0c 0x90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x0 (size before relaxing)
+ 0x1014ca0c 0x48 _g_at_zPHY_NxtHiQuadPosTab
+ 0x1014ca54 0x48 _g_at_zPHY_CurHiQuadPosTab
+ COMMON 0x1014ca9c 0x2e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x0 (size before relaxing)
+ 0x1014ca9c 0x1 _g_zPHY_edfe_wNotSyncAGCBegin
+ 0x1014ca9d 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr1
+ 0x1014ca9e 0x1 _g_Connect_State_Inter_Freq_Flag
+ 0x1014ca9f 0x1 _g_wConnectAgcIntCounter
+ 0x1014caa0 0x1 _g_zPHY_edfe_LostLock_MAX
+ 0x1014caa1 0x1 _g_zPHY_edfe_wFirstInInterFreq
+ 0x1014caa2 0x2 _g_wContinGreaterCount
+ 0x1014caa4 0x1 _g_zPHY_edfe_LostLock_MIN
+ 0x1014caa5 0x1 _g_zPHY_edfe_ScellActiveState
+ 0x1014caa6 0x61 _g_zPHY_edfe_FSNewPara
+ 0x1014cb07 0x1e _g_zPHY_edfe_tAgcDagcPara
+ 0x1014cb25 0x1 _g_dwAgcTargetSync
+ 0x1014cb26 0x1 _g_zPHY_edfe_ScellActiveCounter
+ 0x1014cb27 0x2 _g_wContinLessCount
+ 0x1014cb29 0x1 _g_zPHY_edfe_wPrePhyState
+ 0x1014cb2a 0x1 _g_wAgcFactLf
+ 0x1014cb2b 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr0
+ 0x1014cb2c 0x1 _g_zPHY_edfe_wNotSyncAgcIntCnt
+ 0x1014cb2d 0xa _g_zPHY_edfe_AgcDagcIntCount
+ 0x1014cb37 0x1 _g_dwAgcAvePowLenSync
+ 0x1014cb38 0x1f0 _g_zPHY_edfe_wAgcDagcGain
+ 0x1014cd28 0x4 _g_zPHY_edfe_tMbsfnAgcInfo
+ 0x1014cd2c 0x50 _g_zPHY_edfe_tMbsfnAgcGain
+ COMMON 0x1014cd7c 0xdac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x0 (size before relaxing)
+ 0x1014cd7c 0xd91 _g_tzPHY_ecsrs_FSPara
+ 0x1014db0d 0x4 _g_FS_swMeanPower
+ 0x1014db11 0x1 _g_tzPHY_ecsrs_FS_RepNum
+ 0x1014db12 0x4 _g_PssContext
+ 0x1014db16 0x12 _g_tFS_BackUpPssResult
+ COMMON 0x1014db28 0xd6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x0 (size before relaxing)
+ 0x1014db28 0x2 _TotalPuschNackTB0
+ 0x1014db2a 0x2 _TotalPuschNackTB1
+ 0x1014db2c 0x2 _TotalPuschNumTB1
+ 0x1014db2e 0x6 _g_tUlReportBlerInfo
+ 0x1014db34 0x2 _TotalPuschNumTB0
+ 0x1014db36 0xc8 _g_adwDebug
+ COMMON 0x1014dbfe 0x418 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x0 (size before relaxing)
+ 0x1014dbfe 0x3c8 _g_atEcsrPeakList
+ 0x1014dfc6 0x50 _g_tPssHwResult
+ COMMON 0x1014e016 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x0 (size before relaxing)
+ 0x1014e016 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x1014e01a 0x1 _g_swCsrsDagcMeanPower0
+ 0x1014e01b 0x1 _g_zPHY_edfe_wRxLog2Dagc1
+ 0x1014e01c 0x1 _g_zPHY_edfe_wCsrsLog2Dagc1
+ 0x1014e01d 0x1 _g_swCsrsDagcMeanPower1
+ 0x1014e01e 0x1 _g_zPHY_edfe_wCsrsLog2Dagc0
+ 0x1014e01f 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
+ 0x1014e023 0x1 _g_zPHY_edfe_wRxLog2Dagc0
+ COMMON 0x1014e024 0x8d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ 0x0 (size before relaxing)
+ 0x1014e024 0x5f _g_tzPHY_eulpc_PowerCtrlBlock
+ 0x1014e083 0x1 _g_EUL_wPuschPowerHeadroomIdx
+ 0x1014e084 0x1 _g_tzPHY_eulpc_Ulpc2DlParas
+ 0x1014e085 0x13 _g_tzPHY_eulpc_PcmaxInputInfo
+ 0x1014e098 0x6 _g_tzPHY_eulpc_TempPowerBackoffInfo
+ 0x1014e09e 0x13 _g_tzPHY_eulpc_PowerCtrlParas
+ COMMON 0x1014e0b1 0x9a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x0 (size before relaxing)
+ 0x1014e0b1 0x10f _g_ThreadIntraCs
+ 0x1014e1c0 0xf2 _g_atEcsrSearchPeakdatabase
+ 0x1014e2b2 0x1 _g_CsContext
+ 0x1014e2b3 0x10f _g_ThreadFreqScan
+ 0x1014e3c2 0x60 _g_l1e_tDcxoFtErrorList
+ 0x1014e422 0x2e6 _g_tEcsrSearchCommonInfor
+ 0x1014e708 0xa _g_tTddAndFddCommInfo
+ 0x1014e712 0x2 _g_zPHY_ecsrs_dwPssFrameBnd_dbg
+ 0x1014e714 0x1 _g_eCsrsSynStatus
+ 0x1014e715 0x4 _g_tEmulmSubFrameIntTable
+ 0x1014e719 0xe _g_atEcsrReCfoInfo
+ 0x1014e727 0x1 _g_wSssHwRestartCnt
+ 0x1014e728 0x10f _g_ThreadCfoCs
+ 0x1014e837 0x10f _g_ThreadInterCs
+ 0x1014e946 0x10f _g_ThreadMulmCs
+ COMMON 0x1014ea55 0x11e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x0 (size before relaxing)
+ 0x1014ea55 0x11e _g_CsrDrvCfgInfor
+ 0x1014eb73 ___bss_end = .
+
+.itcm 0x00000000 0x6e38 load address 0x100e8000
+ 0x00000000 _itcm_start = .
+ *(.vectors)
+ .vectors 0x00000000 0xb8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ 0x00000000 0x20 _zsp_int_vector
+ 0x00000020 0x8 _odo_stub_Int12
+ 0x00000028 0x8 _odo_stub_Int11
+ 0x00000030 0x8 _odo_stub_Int10
+ 0x00000038 0x8 _odo_stub_Int9
+ 0x00000040 0x8 _odo_stub_Int8
+ 0x00000048 0x8 _odo_stub_Int7
+ 0x00000050 0x8 _odo_stub_Int6
+ 0x00000058 0x8 _odo_stub_Int5
+ 0x00000060 0x8 _odo_stub_Int4
+ 0x00000068 0x8 _odo_stub_Int3
+ 0x00000070 0x8 _odo_stub_Int2
+ 0x00000078 0x8 _odo_stub_Int1
+ 0x00000080 0x38 _odo_stub_Int0
+ *(.dmc)
+ .dmc 0x000000b8 0x17e T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+ 0x000000b8 0x17e _dei_handler
+ *(.zcos_vector_code)
+ *fill* 0x00000236 0x2 00
+ .zcos_vector_code
+ 0x00000238 0x1a0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ 0x00000238 0x20 _odo_wakeup_osint
+ 0x00000258 0x38 _jump_int
+ 0x00000290 0xf1 _odo_zsp_do_int
+ 0x00000381 0x27 _odo_swap_context
+ 0x000003a8 0x6 _odo_zsp_restore_flags
+ 0x000003ae 0xb _odo_restart
+ 0x000003b9 0x1f _odo_setup_context
+ .zcos_vector_code
+ 0x000003d8 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x000003d8 0x4d _L1_SwapHookUseTimer
+ *(.TcmLtePhyCode)
+ .TcmLtePhyCode
+ 0x00000425 0x290 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x0000055d 0x108 _L1Comm_DevEngCopyMem2Dpram
+ 0x00000665 0x50 _L1Comm_EmtpyLogUnit
+ .TcmLtePhyCode
+ 0x000006b5 0x193 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x000006b5 0xfb _L1L_TpuSubFrmUpdate
+ 0x000007b0 0x55 _L1L_TpuIntISRProc
+ 0x00000805 0x1b _L1L_TpuSysTimeUpdate
+ 0x00000820 0x28 _L1L_TpuHwIntGen
+ .TcmLtePhyCode
+ 0x00000848 0x2b1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x00000848 0x31a _L1e_DevDlsCdtrIntProc
+ 0x00000b62 0x37 _L1e_DevDlsGetDlCcInfo
+ 0x00000b99 0x26 _L1e_DevDlsGetDciDetInfo
+ 0x00000bbf 0x26 _L1e_DevDlsGetDciInfo
+ 0x00000be5 0x10 _L1e_DevDlsGetDciNum
+ 0x00000bf5 0x18 _L1e_DevDlsSwapDciInfo
+ 0x00000c0d 0x89 _L1e_DevDlsDciSelection
+ 0x00000c96 0x13 _L1e_DevDlsGetDestDci
+ 0x00000ca9 0x16 _L1e_DevDlsGetDestDciInfo
+ 0x00000cbf 0x369 _L1e_DevDlsGetUlCcInfo
+ 0x00001028 0x16 _L1e_DevDlsJudgeSccAssignment
+ 0x0000103e 0x10 _L1e_DevDlsRxUeRsAlgoCfg
+ 0x0000104e 0x15f _L1e_DevDlsRxCtrlRegCfg
+ 0x000011ad 0xe _L1e_DevDlsCalcTurboDelay
+ 0x000011bb 0x62 _L1e_DevDlsCalcTurboITs
+ 0x0000121d 0x67 _L1e_DevDlsTurboCtrlRegCfg
+ 0x00001284 0x22 _L1e_DevDlsGetDdtrWorkStatusInd
+ 0x000012a6 0x1d _L1e_DevDlsResetTurbo
+ 0x000012c3 0xf _L1e_DevDlsSubfNumRegCfg
+ 0x000012d2 0x8 _L1e_DevDlsPdschEnRegCfg
+ 0x000012da 0x1 _L1e_DevDlsDdtrClkSelCfg
+ 0x000012db 0x33 _L1e_DevDlsDdtrModeRegCfg
+ 0x0000130e 0x52 _L1e_DevDlsUpdateDdtr
+ 0x00001360 0x17 _L1e_DevDlsGetKmimoParam
+ 0x00001377 0x98 _L1e_DevDlsGetCcParam
+ 0x0000140f 0x40 _L1e_DevDlsGetCcCommParam
+ 0x0000144f 0x36c _zPHY_edls_ProRxBFCfg
+ 0x000017bb 0x48 _zPHY_edls_ProHarqInfoUpdate
+ 0x00001803 0x2c _zPHY_edls_HarqDdrRel
+ 0x0000182f 0x6b _zPHY_edls_HarqDdrTimeOut
+ 0x0000189a 0x13b _zPHY_edls_HarqDdr_DtchDone
+ 0x000019d5 0x2e _zPHY_edls_HarqDdr_DbgMonitorRst
+ 0x00001a03 0x14 _zPHY_edls_HarqDdr_BlockNumIdx
+ 0x00001a17 0x106 _zPHY_edls_HarqDdrReq
+ 0x00001b1d 0x2b7 _zPHY_edls_ProHarqDdrAddrCfg
+ 0x00001dd4 0x1ab _zPHY_edls_ProHarqInfoCfg
+ 0x00001f7f 0x68 _zPHY_edls_ProDciF1BTpmiValueCfg
+ 0x00001fe7 0x1f _zPHY_edls_ProDciF1DTpmiValueCfg
+ 0x00002006 0x1ce _zPHY_edls_ProDciF2TpmiValueCfg
+ 0x000021d4 0xa0 _zPHY_edls_ProDciF2LayerCfg
+ 0x00002274 0x451 _zPHY_edls_ProCommDlSchDecCfg
+ 0x000026c5 0x36 _zPHY_edls_ProPdcchOrder
+ 0x000026fb 0x3d5 _zPHY_edls_ProDediDlSchDecCfg
+ 0x00002ad0 0x79 _zPHY_edls_ProDLHarqValidInfo
+ 0x00002b49 0x30 _zPHY_edls_ProCwCrcValidGen
+ 0x00002b79 0xda _zPHY_edls_ProTddCwValidFeedback
+ 0x00002c53 0x1e _zPHY_edls_ProFddCwValidFeedback
+ 0x00002c71 0x170 _zPHY_edla_PdschPowCompensate
+ 0x00002de1 0x97 _zPHY_edla_PdschDefaultPCCfg
+ 0x00002e78 0x13 _zPHY_edls_DrvArmDspRamRead
+ 0x00002e8b 0x51 _zPHY_edls_GetUeFeedbackPmiIndex
+ 0x00002edc 0x10 _zPHY_edls_ProValidateSpsRecurs
+ 0x00002eec 0x3b _zPHY_edls_ProCalSpsRecurs
+ 0x00002f27 0x27 _zPHY_edls_ProCalSpsHarqId
+ 0x00002f4e 0xf0 _zPHY_edls_ProLTESpsDecCfg
+ 0x0000303e 0x31 _zPHY_edls_ProSpsValidation
+ 0x0000306f 0x94 _zPHY_edls_ProSpsActive
+ 0x00003103 0x84 _zPHY_edls_ProSpsRelease
+ 0x00003187 0x1dd _L1e_DevDlsDlMacPduBufCfg
+ .TcmLtePhyCode
+ 0x00003364 0x6bd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x00003364 0xb6 _zPHY_erfc_ProEventRamNumSet
+ 0x0000341a 0x7a _zPHY_erfc_ProRxReceiveCtrl
+ 0x00003494 0x8f _zPHY_erfc_ProCellSearchCtrl
+ 0x00003523 0x148 _zPHY_erfc_ProPowerCtrl
+ 0x0000366b 0x17 _zPHY_erfc_ProTDDCalcNextACP405State
+ 0x00003682 0x33 _zPHY_erfc_ProFDDCalcNextACP405State
+ 0x000036b5 0x20b _zPHY_erfc_ProRfsdCheck
+ 0x000038c0 0xd4 _zPHY_erfc_ProRFSDMerge
+ 0x00003994 0x8d _zPHY_erfc_ProMeas0Ctrl
+ .TcmLtePhyCode
+ 0x00003a21 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x00003a21 0xf0 _zPHY_erfc_SupMainSyncTableControl
+ 0x00003b11 0x9d _zPHY_erfc_SupTxSendSyncTableControl
+ 0x00003bae 0xb3 _zPHY_erfc_SupMeas0SyncTableControl
+ 0x00003c61 0x31a _zPHY_erfc_SupDFEAGCEsti
+ .TcmLtePhyCode
+ 0x00003f7b 0xdb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x00003f7b 0xdb _zPHY_edfe_SupHandleDFESyncInt
+ .TcmLtePhyCode
+ 0x00004056 0xfb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x00004056 0x60 _zPHY_eintc_InthHandler
+ 0x000040b6 0x22 _zPHY_eintc_Inth0Handler
+ 0x000040d8 0x22 _zPHY_eintc_Inth1Handler
+ 0x000040fa 0x22 _zPHY_eintc_Inth2Handler
+ 0x0000411c 0xa _zPHY_eintc_IntTimer1Handler
+ 0x00004126 0x2b _zPHY_eintc_ICPHandler
+ .TcmLtePhyCode
+ 0x00004151 0x1e6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x00004151 0x67 _L1l_DevEng_DbgExceptLog
+ 0x000041b8 0x24 _L1l_DevEng_DbgInfo
+ 0x000041dc 0xc0 _L1l_DevEngDisplay
+ 0x0000429c 0x58 _L1l_DevEngLogHeaderUpdate
+ 0x000042f4 0x43 _L1l_DevEngCopyMem2Dpram
+ .TcmLtePhyCode
+ 0x00004337 0x92 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x00004337 0x92 _zPHY_erfc_SupAGCControl
+ .TcmLtePhyCode
+ 0x000043c9 0x1894 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x000043c9 0x31 _L1e_DevDlsGetDciField
+ 0x000043fa 0x1bf _L1e_DevDlsDecodeDciF1A
+ 0x000045b9 0x1d _L1e_DevDlsGetTpmiFieldSize
+ 0x000045d6 0x6b _L1e_DevDlsGetRaType1Info
+ 0x00004641 0x26b _L1e_DevDlsDecodeDualCwDci
+ 0x000048ac 0x17f _L1e_DevDlsDecodeSLSMDci
+ 0x00004a2b 0x176 _zPHY_edls_AdaDecodeDciF1
+ 0x00004ba1 0x8e _zPHY_edls_ProDciF2ALayerCfg
+ 0x00004c2f 0x59 _zPHY_edls_AdaCalRbStartRbLength
+ 0x00004c88 0x8a _zPHY_edls_AdaRbDmpType1
+ 0x00004d12 0x1c2 _zPHY_edls_AdaRbDmpType2Dvrb
+ 0x00004ed4 0x8e _zPHY_edls_AdaRbDmpType2Lvrb
+ 0x00004f62 0x72 _zPHY_edls_AdaRbDmpType01Ctrl
+ 0x00004fd4 0x36 _zPHY_edls_AdaRbDmpType0Bw100Rb
+ 0x0000500a 0x62 _zPHY_edls_AdaRbDmpType0Bw75Rb
+ 0x0000506c 0xb5 _zPHY_edls_AdaRbDmpType0Bw50Rb
+ 0x00005121 0xf9 _zPHY_edls_AdaCalTotalREs
+ 0x0000521a 0x5d _zPHY_edls_CsiRsSfnCal
+ 0x00005277 0xde _zPHY_edls_AdaCalOverlapRbNum
+ 0x00005355 0x2b8 _zPHY_edls_AdaCalTddFddNcpTbREs
+ 0x0000560d 0x10e _zPHY_edls_AdaCalTddFddEcpTbREs
+ 0x0000571b 0xc3 _zPHY_edls_AdaCalTddNcpSpeTbREs
+ 0x000057de 0x92 _zPHY_edls_AdaCalTddEcpSpeTbREs
+ 0x00005870 0x79 _zPHY_edls_AdaGetTbTbs
+ 0x000058e9 0x61 _zPHY_edls_AdaCalTbDecodeParas
+ 0x0000594a 0x3c _zPHY_edls_AdaCalTbCbNum
+ 0x00005986 0x1c _zPHY_edls_AdaCalTbParaKParaC
+ 0x000059a2 0xf0 _zPHY_edls_AdaCalTbParaCEParaE
+ 0x00005a92 0x92 _zPHY_edls_AdaCalTbParaNcbParaK0
+ 0x00005b24 0x45 _zPHY_edls_AdaCalTbK0Start
+ 0x00005b69 0x85 _zPHY_edls_AdaCalTbK1Start
+ 0x00005bee 0x6f _zPHY_edls_AdaCalTbNcbStart
+ .TcmLtePhyCode
+ 0x00005c5d 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x00005c5d 0x1 _zPHY_DrvTop_IntReg_Clear
+ .TcmLtePhyCode
+ 0x00005c5e 0x15 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x00005c5e 0x15 _L1L_TpuDrvTpuUnregister
+ .TcmLtePhyCode
+ 0x00005c73 0x3f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00005c73 0x69 _zPHY_erfc_DrvSubframeEventEn
+ 0x00005cdc 0xbb _zPHY_erfc_DrvEventEn
+ 0x00005d97 0x174 _zPHY_erfc_DrvWriteEventEnArrayToABBRamHwReg
+ 0x00005f0b 0x92 _zPHY_erfc_DrvWriteEventEnArrayToDBBNextRamHwReg
+ 0x00005f9d 0x24 _zPHY_erfc_DrvWriteMainEventEnArrayToDBBRamHwReg
+ 0x00005fc1 0x1c _zPHY_erfc_DrvWriteTuReg
+ 0x00005fdd 0x6 _zPHY_erfc_DrvDisableTuReg
+ 0x00005fe3 0x2c _zPHY_erfc_DrvWriteTuRegMrtr
+ 0x0000600f 0x17 _zPHY_erfc_DrvTuRamDisable
+ 0x00006026 0x16 _zPHY_erfc_DrvTuRamEnable
+ 0x0000603c 0x2b _zPHY_erfc_DrvWriteTuRamData
+ .TcmLtePhyCode
+ 0x00006067 0xdc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x00006067 0x7b _zPHY_erfc_DrvWriteOtherCmdDataToEventTable
+ 0x000060e2 0x61 _zPHY_erfc_DrvWriteCmdDataToEventTable
+ .TcmLtePhyCode
+ 0x00006143 0xa9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x00006143 0xa9 _zPHY_Phy_TdlThreadPriprintf
+ *(.fasttext)
+ .fasttext 0x000061ec 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ 0x000061ec 0xe7 _Asm_Tx2Rx2_NL2_PMICalc
+ 0x000062d3 0x85 _Asm_NL1_PMICalc
+ 0x00006358 0xd6 _Asm_Tx4Rx2_NL2_PMICalc
+ .fasttext 0x0000642e 0x4b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ 0x0000642e 0x42 _Asm_SumLOGNoSqrt_RICalc
+ 0x00006470 0x85 _Asm_Tx2Rx2_CL_NL1_RICalc
+ 0x000064f5 0x105 _Asm_Tx2Rx2_CDD_RICalc
+ 0x000065fa 0x122 _Asm_Tx4Rx2_CL_NL2_RICalc
+ 0x0000671c 0x41 _Asm_Tx4Rx2_CL_NL1_RICalc
+ 0x0000675d 0x65 _Asm_Rx2_DIV_RICalc
+ 0x000067c2 0x120 _Asm_Tx4Rx2_CDD_RICalc
+ .fasttext 0x000068e2 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ 0x000068e2 0x36 _Asm_CqiSinglePort_TX1_RX1_NL1
+ 0x00006918 0x6d _Asm_CqiTransDiver_Common_NL1
+ 0x00006985 0x8d _Asm_CqiSpatiMulti_RX2_NL1
+ 0x00006a12 0xf3 _Asm_CqiSpatiMulti_RX2_NL2
+ 0x00006b05 0xb0 _Asm_CqiCDD_TX2_RX2_NL2
+ 0x00006bb5 0xff _Asm_CqiCDD_TX4_RX2_NL2
+ 0x00006cb4 0x41 _ASM_Log2
+ 0x00006cf5 0x77 _Asm_RLMSNR_Calc
+ *(.LpcCodeTcm)
+ .LpcCodeTcm 0x00006d6c 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x00006d6c 0x2e _L1_SocLpModeControlCfg
+ 0x00006d9a 0x1f _L1_SocCpuIdle
+ .LpcCodeTcm 0x00006db9 0x2f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00006db9 0x2f _L1_CpuEnterIdleMode
+ *(.save_zsp_reg)
+ .save_zsp_reg 0x00006de8 0x50 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ 0x00006de8 0x50 _save_zsp880_reg
+ *Cqi_control.o(.text)
+ *Cqi.o(.text)
+ *CQI_Period.o(.text)
+ allnil*(.text)
+ send*(.text)
+ swap*(.text)
+ timer*(.text)
+ alloc*(.text)
+ arch*(.text)
+ free*(.text)
+ receive*(.text)
+ set_pri*(.text)
+ error*(.text)
+ 0x00006e38 _itcm_end = .
+
+.dtcm 0x00010000 0x63fa load address 0x100f0000
+ 0x00010000 _dtcm_start = .
+ *(.LteDataTcm)
+ .LteDataTcm 0x00010000 0xb T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x00010000 0x2 _g_lte_log_buf
+ 0x00010002 0x2 _g_w_log_buf
+ 0x00010004 0x2 _g_td_log_buf
+ 0x00010006 0x2 _g_sig_log_buf
+ 0x00010008 0x1 _g_bL1CommLogOutUsing
+ 0x00010009 0x2 _g_bL1CommIcpFailCnt
+ .LteDataTcm 0x0001000b 0x1bf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x0001000b 0x4 _g_tLocalSSFrm
+ 0x0001000f 0x4 _g_tNativeSSFrm
+ 0x00010013 0x2 _g_zPHY_SuperFrameNumber
+ 0x00010015 0x2 _g_pFreeItemsNum
+ 0x00010017 0x1a0 _g_pBusyItemsNum
+ 0x000101b7 0x13 _stTpuInfo
+ *fill* 0x000101ca 0x80000006 00
+ .LteDataTcm 0x000101d0 0x1480 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x000101d0 0x190 _g_awNo
+ 0x00010360 0x320 _g_adHRx0
+ 0x00010680 0x320 _g_adHRx1
+ 0x000109a0 0x400 _s_awSNR_P1
+ 0x00010da0 0x400 _s_awSNR_P2
+ 0x000111a0 0xc8 _g_awSNR_RLM
+ 0x00011268 0x320 _g_aCqiRamChe
+ 0x00011588 0xc8 _g_aCqiRamNo
+ .LteDataTcm 0x00011650 0x53b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x00011650 0x53b _g_zPHY_edls_tDlsCb
+ .LteDataTcm 0x00011b8b 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x00011b8b 0x2 _g_zPHY_InthTpuCnt
+ 0x00011b8d 0x4 _g_zPHY_InthTpuCntDebug
+ *fill* 0x00011b91 0x80000003 00
+ .LteDataTcm 0x00011b94 0x3344 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x00011b94 0x2b44 _g_tRxpCirCb
+ 0x000146d8 0x800 _g_awL1eRxCirRam
+ .LteDataTcm 0x00014ed8 0x20 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x00014ed8 0x20 _g_tL1lEngDgbInfo
+ .LteDataTcm 0x00014ef8 0xea T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00014ef8 0x39 _g_zPHY_erfc_atCurrentSFConfig
+ 0x00014f31 0x39 _g_zPHY_erfc_atNextSFConfig
+ 0x00014f6a 0x20 _g_adwzPHY_erfc_RFABBMainSyncEventEnArray
+ 0x00014f8a 0x18 _g_adwzPHY_erfc_RFABBMeas0SyncEventEnArray
+ 0x00014fa2 0x20 _g_adwzPHY_erfc_RFABBTxSyncEventEnArray
+ 0x00014fc2 0x8 _g_adwzPHY_erfc_DBBMainSyncEventEnArray
+ 0x00014fca 0xc _g_adwzPHY_erfc_DBBMeas0SyncEventEnArray
+ 0x00014fd6 0x2 _g_zPHY_erfc_DBBTxSyncEventEn
+ 0x00014fd8 0xa _g_zPHY_erfc_wRamNum
+ .LteDataTcm 0x00014fe2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x00014fe2 0x1 _g_zPHY_edfe_cAGCCalMode
+ .LteDataTcm 0x00014fe3 0x1209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x00014fe3 0x4ad _g_zPHY_SID
+ 0x00015490 0xa82 _g_atzPHY_SAD
+ 0x00015f12 0x118 _g_atzPHY_erfc_CsrcSFData
+ 0x0001602a 0xd2 _g_atzPHY_erfc_RxSFData
+ 0x000160fc 0xf0 _g_atzPHY_erfc_TxSFData
+ *(.LpcDataTcm)
+ .LpcDataTcm 0x000161ec 0x48 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x000161ec 0x2 _g_tAtCommM0PsmCtr
+ 0x000161ee 0x2 _g_tAtCommZspPsmCtr
+ 0x000161f0 0x3 _g_tAtCommPsApPsmCtr
+ 0x000161f3 0x10 _g_L1SoCResExpStat
+ 0x00016203 0x2 _g_dSleepLenMs
+ 0x00016205 0x1 _g_wImaskReg
+ 0x00016206 0x2b _g_tLpDebugInfo
+ 0x00016231 0x2 _g_dwPHY_USE_PSM
+ 0x00016233 0x1 _g_bPhyCanSendIcp
+ .LpcDataTcm 0x00016234 0x5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00016234 0x5 _g_wSharePwrUseBit
+ .LpcDataTcm 0x00016239 0x5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x00016239 0x1 _g_tL1IratLpCtrl
+ 0x0001623a 0x2 _g_L1Lpc_tSlaveShortGapFlg
+ 0x0001623c 0x1 _g_eWdRfCfgFlg
+ 0x0001623d 0x1 _g_eTdRfCfgFlg
+ .LpcDataTcm 0x0001623e 0x3 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x0001623e 0x1 _g_L1Lpc_wHarqTurboUsedFlg
+ 0x0001623f 0x1 _g_L1Lpc_w3gSyncUsedFlg
+ 0x00016240 0x1 _g_L1Lpc_w3gDpaUsedFlg
+ .LpcDataTcm 0x00016241 0x6b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x00016241 0x1 _g_bIsWUsePsm
+ 0x00016242 0x2 _g_tL1wLpCtrl
+ 0x00016244 0x49 _g_tL1wLpcInfo
+ 0x0001628d 0x2 _g_wLpmFactorBefSleep
+ 0x0001628f 0x2 _g_wLpmFactorAftWakeup
+ 0x00016291 0x1 _g_wLpmFactorErrCnt
+ 0x00016292 0x1 _g_bL1wLpcCfunReset
+ 0x00016293 0x2 _g_dwPrintSsfn1
+ 0x00016295 0x2 _g_dwPrintSsfn2
+ 0x00016297 0x2 _g_dwPrintSsfn3
+ 0x00016299 0x2 _g_dwPrintSsfn4
+ 0x0001629b 0x2 _g_dwSleepSchedSsfn
+ 0x0001629d 0x7 _g_tWLpmFactorLast
+ 0x000162a4 0x7 _g_tWLpmFactorCurent
+ 0x000162ab 0x1 _g_wLpmChangeOneDir
+ *(.dncsram)
+ .dncsram 0x000162ac 0x14c T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x000162ac 0x4 _odo_pool_list
+ 0x000162b0 0x100 _odo_pcb_list
+ 0x000163b0 0x1 _odo_max_valid_pid
+ 0x000163b1 0x26 _odo_config
+ 0x000163d7 0x21 _config_int_mask_list
+ .dncsram 0x000163f8 0x2 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x000163f8 0x2 _g_wHookCnt
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(.data)
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(.bss)
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(COMMON)
+ init*(COMMON)
+
+.reg_icp1
+ *(.icp_reg)
+
+.reg_icp2
+ *(.icp_reg_m0)
+
+.reg_dma 0x00980000 0x41a
+ *(.dma_reg)
+ .dma_reg 0x00980000 0x41a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ 0x00980000 0x400 _g_atDmaRegCh
+ 0x00980400 0x2 _g_dDmaIntTcStatus
+ 0x00980402 0x2 _g_dDmaSerrorStatus
+ 0x00980404 0x2 _g_dDmaDerrorStatus
+ 0x00980406 0x2 _g_dDmaCfgError
+ 0x00980408 0x2 _g_dDmaRawIntTcStatus
+ 0x0098040a 0x2 _g_dDmaRawIntSerrorStatus
+ 0x0098040c 0x2 _g_dDmaRawIntDerrorStatus
+ 0x0098040e 0x2 _g_dDmaRawIntCfgErrorStatus
+ 0x00980410 0x2 _g_dDmaWorkingStatus
+ 0x00980412 0x2 _g_dDmaGroupOrder
+ 0x00980414 0x2 _g_dDmaArbitMode
+ 0x00980416 0x2 _g_dDmaIrqType
+ 0x00980418 0x2 _g_dDmaVersion
+
+.reg_icu 0x00400800 0x238
+ *(.icu_reg)
+ .icu_reg 0x00400800 0x238 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+ 0x00400800 0x2 _g_dRegIcuVersion
+ 0x00400802 0x2 _g_dRegIcuReserved1
+ 0x00400804 0x2 _g_dRegIcuReserved2
+ 0x00400806 0x2 _g_dRegIcuReserved3
+ 0x00400808 0x2 _g_dRegIcuIntIrqNum
+ 0x0040080a 0x2 _g_dRegIcuIntFiqNum
+ 0x0040080c 0x2 _g_dRegIcuIrqCur
+ 0x0040080e 0x2 _g_dRegIcuFiqCur
+ 0x00400810 0x2 _g_dRegIcuReserved4
+ 0x00400812 0x2 _g_dRegIcuIntStatus
+ 0x00400814 0x8 _g_dRegIcuReserved5
+ 0x0040081c 0x2 _g_dRegIcuTest
+ 0x0040081e 0x8 _g_dRegIcuIntSigBitSet
+ 0x00400826 0x8 _g_dRegIcuIntClr
+ 0x0040082e 0x8 _g_dRegIcuIntEn
+ 0x00400836 0x8 _g_dRegIcuIntDisEn
+ 0x0040083e 0x2 _g_dRegIcuReserved6
+ 0x00400840 0x100 _g_dRegIcuIntMode
+ 0x00400940 0x2 _g_dRegIcuReserved7
+ 0x00400942 0x2 _g_dRegIcuFiqNum
+ 0x00400944 0x2 _g_dRegIcuClkGateEn
+ 0x00400946 0x2 _g_dRegIcuReserved8
+ 0x00400948 0x8 _g_dRegIcuIntMask
+ 0x00400950 0x30 _g_dRegIcuReserved9
+ 0x00400980 0x8 _g_dRegIcuIntReq
+ 0x00400988 0xa8 _g_dRegIcuReserved10
+ 0x00400a30 0x8 _g_dRegIcuIntSetReq
+
+.reg4 0x7e080000 0x40
+ *(.top_reg)
+ .top_reg 0x7e080000 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_top.o)
+ 0x7e080000 0x2 _g_wL1wTop00SoftReset
+ 0x7e080002 0x2 _g_wL1wTop01GdtrHdtrChoose
+ 0x7e080004 0x2 _g_wL1wTop02Version1
+ 0x7e080006 0x2 _g_wL1wTop03BmiClkGate
+ 0x7e080008 0x2 _g_wL1wTop04ModeCtrl
+ 0x7e08000a 0x2 _g_wL1wTop05FixIqValue
+ 0x7e08000c 0x6 _g_wL1wTopReserved
+ 0x7e080012 0x2 _g_wL1wTop09GateClkCtrl
+ 0x7e080014 0x2 _g_wL1wTopAWdTimingRtVal0
+ 0x7e080016 0x2 _g_wL1wTopBWdTimingRtVal1
+ 0x7e080018 0x2 _g_wL1wTopCWdTimingNtVal0
+ 0x7e08001a 0x2 _g_wL1wTopDWdTimingNtVal1
+ 0x7e08001c 0x2 _g_wL1wTopEDmaIntBypass
+ 0x7e08001e 0x2 _g_wL1wTopReserved1
+ 0x7e080020 0x2 _g_wL1wTop10TpuRakeIntMask
+ 0x7e080022 0x2 _g_wL1wTop11RakeDfeRfcIntMask
+ 0x7e080024 0x2 _g_wL1wTop12TpuCsrAdrHsscchIntMask
+ 0x7e080026 0x2 _g_wL1wTop13CsrDtrPsrIntMask
+ 0x7e080028 0x2 _g_wL1wTop14TpuRakeIntStateMask
+ 0x7e08002a 0x2 _g_wL1wTop15RakeDfeRfcIntStateMask
+ 0x7e08002c 0x2 _g_wL1wTop16TpuCsrAdrHsscchIntStateMask
+ 0x7e08002e 0x2 _g_wL1wTop17CsrDtrPsrIntStateMask
+ 0x7e080030 0x2 _g_wL1wTop18TpuRakeIntStat
+ 0x7e080032 0x2 _g_wL1wTop19RakeDfeRfcIntStat
+ 0x7e080034 0x2 _g_wL1wTop1ATpuCsrAdrHsscchIntState
+ 0x7e080036 0x2 _g_wL1wTop1BCsrDtrPsrIntState
+ 0x7e080038 0x2 _g_wL1wTop1CReserved
+ 0x7e08003a 0x2 _g_wL1wTop1DReserved
+ 0x7e08003c 0x2 _g_wL1wTop1EReserved
+ 0x7e08003e 0x2 _g_wL1wTop1FReserved
+
+.reg5 0x7e080800 0xe0
+ *(.tpu_reg)
+ .tpu_reg 0x7e080800 0xe0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ 0x7e080800 0x2 _g_tRegTpuReset
+ 0x7e080802 0x2 _g_tRegTpuMrtrAdjConfig
+ 0x7e080804 0x2 _g_tRegTpuMrtrOffset
+ 0x7e080806 0x2 _g_tRegTpuMrtrCnt
+ 0x7e080808 0x2 _g_tRegTpuMrtrLatch
+ 0x7e08080a 0x2 _g_tRegTpuLocalMrtrCnt
+ 0x7e08080c 0x2 _g_tRegTpuLocalMrtrLatch
+ 0x7e08080e 0x2 _g_tRegTpuMacroCtrl
+ 0x7e080810 0x2 _g_tRegTpuMrtrGoal
+ 0x7e080812 0x2 _g_tRegTpuMrtrAdjustCtrl
+ 0x7e080814 0x2 _g_tRegTpuReserve0
+ 0x7e080816 0x2 _g_tRegTpuNt2RtOffset
+ 0x7e080818 0x2 _g_tRegTpuMrtrSSFN
+ 0x7e08081a 0x2 _g_tRegTpuLocalMrtrSSFN
+ 0x7e08081c 0x2 _g_tRegTpuMrtrSuperfrGoal
+ 0x7e08081e 0x2 _g_tRegTpuTip
+ 0x7e080820 0x4 _g_tRegTpuReserve1
+ 0x7e080824 0x2 _g_tRegTpuRestore
+ 0x7e080826 0x2 _g_tRegTpuSsfnOffRestore
+ 0x7e080828 0x2 _g_tRegTpuSsfnOff
+ 0x7e08082a 0x2 _g_tRegTpuMrtrLatchSSFN
+ 0x7e08082c 0x2 _g_tRegTpuLocalMrtrLatchSSFN
+ 0x7e08082e 0x52 _g_tRegTpuReserve2
+ 0x7e080880 0x36 _g_atRegTpuNtInt
+ 0x7e0808b6 0xa _g_atRegTpuRtInt
+ 0x7e0808c0 0x20 _g_tRegTpuReserve4
+
+.reg6 0x7e082000 0x2420
+ *(.rfc_reg)
+ .rfc_reg 0x7e082000 0x2420 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ 0x7e082000 0x2 _g_dRegRfcReset
+ 0x7e082002 0x2 _g_dRegRfcGpioVal
+ 0x7e082004 0x2 _g_dRegRfcFilterEn
+ 0x7e082006 0x2 _g_dRfcSpiReadData
+ 0x7e082008 0x2 _g_dRfcFAgcEventEn
+ 0x7e08200a 0x2 _g_dRegRfcFAgcRldVal
+ 0x7e08200c 0x4 _g_tRegRfcAnt0FAgcCtrlData
+ 0x7e082010 0x4 _g_tRegRfcAnt1FAgcCtrlData
+ 0x7e082014 0x2 _g_dRegRfcFAgcSpiBitSel
+ 0x7e082016 0x2 _g_dRegRfcFAgcTimeOffst
+ 0x7e082018 0x2 _g_dRegRfcFAgcEn
+ 0x7e08201a 0x2 _g_dRegRfcDebugSel
+ 0x7e08201c 0x2 _g_dRegRfcG1GpioSyncSel
+ 0x7e08201e 0x2 _g_dRegRfcMrtrTpuSel
+ 0x7e082020 0x2 _g_dRegRfcIntSel
+ 0x7e082022 0x2 _g_dRegRfcIntTimeCfg
+ 0x7e082024 0x4 _g_adRegRfcCtrlRamRegEn
+ 0x7e082028 0x8 _g_adRegRfcCtrlRamRx0En0
+ 0x7e082030 0x8 _g_adRegRfcCtrlRamRx0En1
+ 0x7e082038 0x8 _g_adRegRfcCtrlRamRx1En0
+ 0x7e082040 0x8 _g_adRegRfcCtrlRamRx1En1
+ 0x7e082048 0x8 _g_adRegRfcCtrlRamTxEn0
+ 0x7e082050 0x2 _g_dRegRfcUnsualIntClr
+ 0x7e082052 0xe _g_adRegRfcSpiFormatMap
+ 0x7e082060 0x2 _g_dRegRfcRffeDataMap
+ 0x7e082062 0x2 _g_dRegRfcWRfcEn
+ 0x7e082064 0x2 _g_dRegRfcMrtrConCrrnt
+ 0x7e082066 0x8 _g_adRegRfcCtrlRamTxEn1
+ 0x7e08206e 0x2 _g_dRegRfcFAgcCtrlWordAnt01Lsb
+ 0x7e082070 0x2 _g_dRegRfcFAgcCtrlWordAnt11Lsb
+ 0x7e082072 0x2 _g_dRegRfcFAgcCtrlWordAntSecMsb
+ 0x7e082074 0x2 _g_dRegRfcFAgcTimeInterval
+ 0x7e082076 0x18a _g_adReserved5
+ 0x7e082200 0x5a _g_atRegRfcCtrlReg
+ 0x7e08225a 0x6 _g_tRegRfcCtrlReg15
+ 0x7e082260 0x1a0 _g_adReserved6
+ 0x7e082400 0x20 _g_atRegRfcRxTu
+ 0x7e082420 0x1e0 _g_adReserved1
+ 0x7e082600 0x20 _g_atRegRfcTxTu
+ 0x7e082620 0x1e0 _g_adReserved2
+ 0x7e082800 0x40 _g_adRegRfcFastAgcRam
+ 0x7e082840 0x7c0 _g_adReserved3
+ 0x7e083000 0x100 _g_atRegRfcCtrlRamReg
+ 0x7e083100 0x300 _g_adReserved4
+ 0x7e083400 0x400 _g_atRegRfcCtrlRamRx0
+ 0x7e083800 0x400 _g_atRegRfcCtrlRamRx1
+ 0x7e083c00 0x400 _g_atRegRfcCtrlRamTx
+ 0x7e084000 0x2 _g_dRegDfeRxVersion
+ 0x7e084002 0x2 _g_dRegDfeRxReset
+ 0x7e084004 0x2 _g_dRegDfeRxAntEn
+ 0x7e084006 0x2 _g_dRegDfeRxAnt0ClkCtrl
+ 0x7e084008 0x2 _g_dRegDfeRxAnt1ClkCtrl
+ 0x7e08400a 0x2 _g_dRegDfeRxFilterEnDelay
+ 0x7e08400c 0x2 _g_dRegDfeRxDagcDelay
+ 0x7e08400e 0x2 _g_dRegDfeRxCompEn
+ 0x7e084010 0x2 _g_dRegDfeRxEstLen
+ 0x7e084012 0x2 _g_dRegDfeRxAnt0DcEst
+ 0x7e084014 0x2 _g_dRegDfeRxAnt1DcEst
+ 0x7e084016 0x2 _g_dRegDfeRxAnt0DcComp
+ 0x7e084018 0x2 _g_dRegDfeRxAnt1DcComp
+ 0x7e08401a 0x2 _g_dRegDfeRxAnt0IqEstSum
+ 0x7e08401c 0x2 _g_dRegDfeRxAnt1IqEstSum
+ 0x7e08401e 0x2 _g_dRegDfeRxRxAnt0IqCorr
+ 0x7e084020 0x2 _g_dRegDfeRxRxAnt1IqCorr
+ 0x7e084022 0x2 _g_dRegDfeRxIqAmpComp
+ 0x7e084024 0x2 _g_dRegDfeRxIqPhaComp
+ 0x7e084026 0x2 _g_dRegDfeRxHwAgcGainInit
+ 0x7e084028 0x2 _g_dRegDfeRxAgcLfCoff
+ 0x7e08402a 0x2 _g_dRegDfeRxAgcTarget
+ 0x7e08402c 0x2 _g_dRegDfeRxAgcMaxGain
+ 0x7e08402e 0x2 _g_dReserved11
+ 0x7e084030 0x2 _g_dRegDfeRxAgcLfIntEn
+ 0x7e084032 0x2 _g_dRegDfeRxAgcMeanPwr
+ 0x7e084034 0x2 _g_dRegDfeRxAgcLoopOut
+ 0x7e084036 0x2 _g_dReserved12
+ 0x7e084038 0x2 _g_dReserved13
+ 0x7e08403a 0x2 _g_dRegDfeRxAnt0HwAgcGain
+ 0x7e08403c 0x2 _g_dRegDfeRxAnt1HwAgcGain
+ 0x7e08403e 0x2 _g_dRegDfeRxFreqCorrPhaVal
+ 0x7e084040 0x2 _g_dReserved10
+ 0x7e084042 0x2 _g_dRegDfeRxAnt0DagcMeanPwr
+ 0x7e084044 0x2 _g_dRegDfeRxAnt1DagcMeanPwr
+ 0x7e084046 0x2 _g_dRegDfeRxDagcCtrl
+ 0x7e084048 0x2 _g_dRegDfeRxDagcBitSel
+ 0x7e08404a 0x2 _g_dRegDfeRxFifoReset
+ 0x7e08404c 0x2 _g_dRegDfeRxIntfSel
+ 0x7e08404e 0x2 _g_dRegDfeRxDLIntf1Cfg
+ 0x7e084050 0x2 _g_dRegDfeRxDLIntf2Cfg
+ 0x7e084052 0x2 _g_dRegDfeRxDLIntf3Cfg
+ 0x7e084054 0x2 _g_dRegDfeRxDLIntfDebugSel
+ 0x7e084056 0x2 _g_dRegDfeRxDLIntfDebugData
+ 0x7e084058 0x2 _g_dRegDfeRxDLIntfFifoDebug
+ 0x7e08405a 0x2 _g_dRegDfeRxBypass
+ 0x7e08405c 0x2 _g_dRegDfeRxTestCtrl
+ 0x7e08405e 0x2 _g_adReserved9
+ 0x7e084060 0x2 _g_dRegDfeNotchFreq
+ 0x7e084062 0x2 _g_dRegDfeNotchFs
+ 0x7e084064 0x2 _g_dRegDfeNotchStart
+ 0x7e084066 0x2 _g_dRegDfeNotchTimeA
+ 0x7e084068 0x2 _g_dRegDfeNotchTimeBAnt0
+ 0x7e08406a 0x2 _g_dRegDfeNotchParKA
+ 0x7e08406c 0x2 _g_dRegDfeNotchParKBAnt0
+ 0x7e08406e 0x2 _g_dRegDfeNotchParARe
+ 0x7e084070 0x2 _g_dRegDfeNotchParAIm
+ 0x7e084072 0x2 _g_dRegDfeNotchParAOutRe
+ 0x7e084074 0x2 _g_dRegDfeNotchParAOutIm
+ 0x7e084076 0x2 _g_dRegDfeNotchCordicSt
+ 0x7e084078 0x2 _g_dRegDfeNotchTimeBAnt1
+ 0x7e08407a 0x2 _g_dRegDfeNotchParKBAnt1
+ 0x7e08407c 0x2 _g_dRegDfeRxDLIntf4Cfg
+ 0x7e08407e 0x2 _g_dRegDfeRxDLIntf5Cfg
+ 0x7e084080 0x2 _g_dRegDfeRxAgcRamClkSel
+ 0x7e084082 0x2 _g_dRegDfeNotch1TimeA
+ 0x7e084084 0x2 _g_dRegDfeNotch1ParKA
+ 0x7e084086 0x2 _g_dRegDfeNotch2TimeA
+ 0x7e084088 0x2 _g_dRegDfeNotch2ParKA
+ 0x7e08408a 0x2 _g_dRegDfeNotch1TimeBAnt0
+ 0x7e08408c 0x2 _g_dRegDfeNotch1ParKBAnt0
+ 0x7e08408e 0x2 _g_dRegDfeNotch2TimeBAnt0
+ 0x7e084090 0x2 _g_dRegDfeNotch2ParKBAnt0
+ 0x7e084092 0x2 _g_dRegDfeNotch1TimeBAnt1
+ 0x7e084094 0x2 _g_dRegDfeNotch1ParKBAnt1
+ 0x7e084096 0x2 _g_dRegDfeNotch2TimeBAnt1
+ 0x7e084098 0x2 _g_dRegDfeNotch2ParKBAnt1
+ 0x7e08409a 0x2 _g_dRegDfeNotch1ParARe
+ 0x7e08409c 0x2 _g_dRegDfeNotch1ParAIm
+ 0x7e08409e 0x2 _g_dRegDfeNotch2ParARe
+ 0x7e0840a0 0x2 _g_dRegDfeNotch2ParAIm
+ 0x7e0840a2 0x2 _g_dRegDfeNotchbyPass
+ 0x7e0840a4 0x2 _g_dRegDfeFcInitPhase
+ 0x7e0840a6 0x2 _g_dRegDfeFcRotValSum
+ 0x7e0840a8 0x158 _g_adReserved19
+ 0x7e084200 0xc8 _g_adAgcCwTable
+ 0x7e0842c8 0x138 _g_adReserved14
+ 0x7e084400 0x2 _g_dRegDfeTxReset
+ 0x7e084402 0x2 _g_dRegDfeTxAmpCorr
+ 0x7e084404 0x2 _g_dRegDfeTxPhaCorr
+ 0x7e084406 0x2 _g_dRegDfeTxDcComp
+ 0x7e084408 0x2 _g_dRegDfeTxFirBitSel
+ 0x7e08440a 0x2 _g_dRegDfeTxBypassCtrl
+ 0x7e08440c 0x2 _g_dRegDfeTxEnExtnd
+ 0x7e08440e 0x2 _g_dRegDfeTxEnCtrl
+ 0x7e084410 0x2 _g_dRegDfeTxChainEn
+ 0x7e084412 0x2 _g_dRegDfeTxIntfSel
+ 0x7e084414 0x2 _g_dRegDfeTxIntf1Cfg
+ 0x7e084416 0x2 _g_dRegDfeTxIntf2Cfg
+ 0x7e084418 0x2 _g_dRegDfeTxIntf3Cfg
+ 0x7e08441a 0x2 _g_dRegDfeTxClkGate
+ 0x7e08441c 0x2 _g_dRegDfeTxOutEnSel
+ 0x7e08441e 0x2 _g_dRegDfeTxFirDlyNum
+
+.reg7 0x7e084800 0xa00
+ *(.csr_reg)
+ .csr_reg 0x7e084800 0xa00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7e084800 0x2 _g_adCsrReserved2400
+ 0x7e084802 0x2 _g_tRegCsrFpgaVersion
+ 0x7e084804 0x2 _g_tRegCsrTestMode
+ 0x7e084806 0x2 _g_tRegCsrStepIqSel
+ 0x7e084808 0x2 _g_tRegCsrRotate0
+ 0x7e08480a 0x2 _g_tRegCsrRotateParaEn0
+ 0x7e08480c 0x2 _g_tRegCsrRotate1
+ 0x7e08480e 0x2 _g_tRegCsrRotateParaEn1
+ 0x7e084810 0x2 _g_tRegCsrOfflineSPSRRotate
+ 0x7e084812 0x2 _g_tRegCsrReadMrtrReq
+ 0x7e084814 0x2 _g_tRegCsrSetWdtReq
+ 0x7e084816 0x2 _g_tRegCsrIntMrtrValue
+ 0x7e084818 0x2 _g_tRegCsrFreqInd
+ 0x7e08481a 0x2 _g_tRegCsrFxEndBoundary
+ 0x7e08481c 0x2 _g_tRegCsrFxStartBoundary
+ 0x7e08481e 0x2 _g_tRegCsrDataValidEn
+ 0x7e084820 0x2 _g_tRegCsrPatternSoft
+ 0x7e084822 0x2 _g_tRegCsrPatternMode
+ 0x7e084824 0x2 _g_tRegCsrPatternIntEn
+ 0x7e084826 0x2 _g_tRegCsrTopClkGating
+ 0x7e084828 0x2 _g_tRegCsrTestpinSel
+ 0x7e08482a 0x2 _g_tRegCsrSaveDataEn
+ 0x7e08482c 0x2 _g_tRegCsrSaveDataSymNum
+ 0x7e08482e 0x2 _g_tRegCsrFsBuffMrtr
+ 0x7e084830 0x2 _g_tRegCsrFsBuffEndClear
+ 0x7e084832 0x6e _g_adCsrReserved1
+ 0x7e0848a0 0x2 _g_tRegCsrRdMrtrValue
+ 0x7e0848a2 0x2 _g_tRegCsrFsBuffState
+ 0x7e0848a4 0x2 _g_tRegCsrFsBuffEndMrtr
+ 0x7e0848a6 0x15a _g_adCsrReserved2
+ 0x7e084a00 0x2 _g_tRegCsrStep1Reset
+ 0x7e084a02 0x2 _g_tRegCsrNSlot1
+ 0x7e084a04 0x2 _g_tRegCsrStartEn1
+ 0x7e084a06 0x2 _g_tRegCsrMrtrS1
+ 0x7e084a08 0x2 _g_tRegCsrPeakWidth
+ 0x7e084a0a 0x2 _g_tRegCsrPeakMask
+ 0x7e084a0c 0x2 _g_tRegCsrGapModeIndex
+ 0x7e084a0e 0x2 _g_tRegCsrSatCtrlbits
+ 0x7e084a10 0x2 _g_tRegCsrS1ClkGating
+ 0x7e084a12 0x2 _g_tRegCsrStep1Start
+ 0x7e084a14 0x8c _g_adCsrReserved3
+ 0x7e084aa0 0x2 _g_tRegCsrOutMrtrS1
+ 0x7e084aa2 0x2 _g_tRegCsrSlotNo1
+ 0x7e084aa4 0x2 _g_tRegCsrStep1Status
+ 0x7e084aa6 0x2 _g_tRegCsrPowerAvg1
+ 0x7e084aa8 0x158 _g_adCsrReserved4
+ 0x7e084c00 0x2 _g_tRegCsrIcVersion
+ 0x7e084c02 0x2 _g_tRegCsrIcEnable
+ 0x7e084c04 0x2 _g_tRegCsrIcStartPos
+ 0x7e084c06 0x2 _g_tRegCsrIcCpichSlotHead
+ 0x7e084c08 0x2 _g_tRegCsrIcPrar
+ 0x7e084c0a 0x2 _g_tRegCsrIcScramblePra
+ 0x7e084c0c 0x2 _g_tRegCsrIcClkGatingBypas
+ 0x7e084c0e 0x2 _g_tRegCsrIcUpdate
+ 0x7e084c10 0x10 _g_adCsrReserved5
+ 0x7e084c20 0x2 _g_tRegCsrIcScchValue
+ 0x7e084c22 0x2 _g_tRegCsrIcCpichValue
+ 0x7e084c24 0x1dc _g_adCsrReserved6
+ 0x7e084e00 0x2 _g_tRegCsrStep2BReset
+ 0x7e084e02 0x2 _g_tRegCsrNSlot2B
+ 0x7e084e04 0x2 _g_tRegCsrMrtrS2B
+ 0x7e084e06 0x2 _g_tRegCsrTimeAdjMode2B
+ 0x7e084e08 0x2 _g_tRegCsrResyncWinWidth2B
+ 0x7e084e0a 0x8 _g_adCodeGroupListSet
+ 0x7e084e12 0x2 _g_tRegCsrBurstContextS2B
+ 0x7e084e14 0x2 _g_tRegCsrTimingAdjustS2B
+ 0x7e084e16 0x2 _g_tRegCsrMrtrS2BStart
+ 0x7e084e18 0x2 _g_tRegCsrStartEn2B
+ 0x7e084e1a 0x2 _g_tRegCsrS2bClkGateBypass
+ 0x7e084e1c 0x2 _g_tRegCsrStep2BStart
+ 0x7e084e1e 0x82 _g_adCsrReserved7
+ 0x7e084ea0 0x2 _g_tRegCsrMrtrS2BSlot
+ 0x7e084ea2 0x2 _g_tRegCsrSlotNo2B
+ 0x7e084ea4 0x2 _g_tRegCsrSlotNum2B
+ 0x7e084ea6 0x2 _g_tRegCsrGroupNum2B
+ 0x7e084ea8 0x2 _g_tRegCsrCorNormMax2B
+ 0x7e084eaa 0xe _g_atRegCsrAccCorTmPos2B
+ 0x7e084eb8 0x2 _g_tRegCsrMaxTmPosSel2B
+ 0x7e084eba 0x2 _g_tRegCsrSelfResyncS2B
+ 0x7e084ebc 0x2 _g_tRegCsrStep2BStatus
+ 0x7e084ebe 0x2 _g_tRegCsrBurstPatternS2B
+ 0x7e084ec0 0x10 _g_atRegCsrSlotNum2B
+ 0x7e084ed0 0x10 _g_atRegCsrGroupNum2B
+ 0x7e084ee0 0x10 _g_atRegCsrCorNormMax2B
+ 0x7e084ef0 0x10 _g_atRegCsrMaxTmPosSel2B
+ 0x7e084f00 0x2 _g_tRegCsrGrpSumMaxVal2B
+ 0x7e084f02 0xfe _g_adCsrReserved8
+ 0x7e085000 0x2 _g_tRegCsrStep3Reset
+ 0x7e085002 0x2 _g_tRegCsrNSlot3
+ 0x7e085004 0x2 _g_tRegCsrMrtrS3
+ 0x7e085006 0x2 _g_tRegCsrMrtrS3Slot
+ 0x7e085008 0x2 _g_tRegCsrScramblingCodeS3
+ 0x7e08500a 0x2 _g_tRegCsrResyncWinWidthS3
+ 0x7e08500c 0x2 _g_tRegCsrBurstContextS3
+ 0x7e08500e 0x2 _g_tRegCsrMrtrS3Start
+ 0x7e085010 0x2 _g_tRegCsrStartEn3
+ 0x7e085012 0x2 _g_tRegCsrStep3Start
+ 0x7e085014 0x2 _g_tRegCsrStep3ClkBypass
+ 0x7e085016 0x8a _g_adCsrReserved9
+ 0x7e0850a0 0x2 _g_tRegCsrSlotNo3
+ 0x7e0850a2 0x2 _g_tRegCsrCorNormAvg
+ 0x7e0850a4 0x10 _g_atRegCsrCorNormMax3
+ 0x7e0850b4 0x10 _g_atRegCsrTimeAdj3
+ 0x7e0850c4 0x2 _g_tRegCsrStep3Status
+ 0x7e0850c6 0x2 _g_tRegCsrBurstPatternS3
+ 0x7e0850c8 0x138 _g_adCsrReserved10
+
+.reg8 0x7e085200 0xb6
+ *(.meas_reg)
+ .meas_reg 0x7e085200 0xb6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ 0x7e085200 0x2 _g_tL1wRegMeasSoftReset
+ 0x7e085202 0x2 _g_tRegMeasBufOffline
+ 0x7e085204 0x2 _g_tRegMeasBufOffMrtr
+ 0x7e085206 0x2 _g_tRegMeasBufUpdate
+ 0x7e085208 0x2 _g_tRegMeasWorkMode
+ 0x7e08520a 0x2 _g_tRegMeasOnLineMrtr
+ 0x7e08520c 0x2 _g_tRegMeasOnLineAgc0Para
+ 0x7e08520e 0x2 _g_tRegMeasOnLineAgc1Para
+ 0x7e085210 0x2 _g_tRegMeasOnLineAgc0Mrtr
+ 0x7e085212 0x2 _g_tRegMeasOnLineAgc1Mrtr
+ 0x7e085214 0x2 _g_tRegMeasContxtSel
+ 0x7e085216 0x2 _g_tRegMeasSpsrParaCfg
+ 0x7e085218 0x2 _g_tL1wRegMeasSttdMode
+ 0x7e08521a 0x2 _g_tL1wRegMeasCell012
+ 0x7e08521c 0x2 _g_tL1wRegMeasCell345
+ 0x7e08521e 0x2 _g_tL1wRegMeasCell67
+ 0x7e085220 0x10 _g_atL1wMeasCellMrtr
+ 0x7e085230 0x2 _g_tRegMeasClkInfo
+ 0x7e085232 0x2 _g_tRegMeasParaUpdate
+ 0x7e085234 0x6e _g_adReserved
+ 0x7e0852a2 0x2 _g_tRegMeasSpsrStatus
+ 0x7e0852a4 0x2 _g_tRegMeasBurstPattern
+ 0x7e0852a6 0x10 _g_atL1wRegMeasCellAgc
+
+.reg9 0x7e086000 0x200
+ *(.csr_fullscan_reg)
+ .csr_fullscan_reg
+ 0x7e086000 0x200 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7e086000 0x2 _g_tRegCsrFsSoftReset
+ 0x7e086002 0x2 _g_tRegCsrFsAccLen
+ 0x7e086004 0x14 _g_atRegCsrFsDataOffset
+ 0x7e086018 0x28 _g_atRegCsrFsScrambleGroup
+ 0x7e086040 0x2 _g_tRegCsrFsScrambleGroup
+ 0x7e086042 0x2 _g_tRegCsrFsClkGating
+ 0x7e086044 0x2 _g_tRegCsrFsStart
+ 0x7e086046 0x5a _g_adCsrReserved11
+ 0x7e0860a0 0x2 _g_tRegCsrFsFirstDataMrtr
+ 0x7e0860a2 0x14 _g_atRegCsrFsPeakPowerPos
+ 0x7e0860b6 0x14 _g_atRegCsrFsPeakScrambleOffset
+ 0x7e0860ca 0x2 _g_tRegCsrFsInt
+ 0x7e0860cc 0x2 _g_dCsrFsNoise
+ 0x7e0860ce 0x132 _g_adCsrReserved12
+
+.reg10 0x7e086200 0x26e
+ *(.bch_reg)
+ .bch_reg 0x7e086200 0x26e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ 0x7e086200 0x2 _g_uRegBchSoftReset
+ 0x7e086202 0x2 _g_uRegBchTxdMode
+ 0x7e086204 0x2 _g_uRegBchBchPichSel
+ 0x7e086206 0x2 _g_uRegBchTtiSync
+ 0x7e086208 0x2 _g_uRegBchWindowTh
+ 0x7e08620a 0x2 _g_uRegBchPichOvsfK
+ 0x7e08620c 0x6c _g_atRegBchFingerConfig
+ 0x7e086278 0x2 _g_uRegBchClkGate
+ 0x7e08627a 0x186 _g_adRegBchReserved1
+ 0x7e086400 0x48 _g_atRegBchFingerStatus
+ 0x7e086448 0x12 _g_adRegBchViterbiOut
+ 0x7e08645a 0x10 _g_asdRegBchPichData
+ 0x7e08646a 0x2 _g_uRegBchTotalStatus
+ 0x7e08646c 0x2 _g_uRegBchCrcResult
+
+.reg11 0x7e086800 0xb6
+ *(.psr_reg)
+ .psr_reg 0x7e086800 0xb6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ 0x7e086800 0x2 _g_tRegPsrReset
+ 0x7e086802 0x2 _g_tRegPsrSuspendEn
+ 0x7e086804 0x2 _g_tRegPsrPilotPatternConfig
+ 0x7e086806 0x2 _g_tRegPsrClkGatePassConfig
+ 0x7e086808 0x2 _g_tRegPsrAntSelectCfg
+ 0x7e08680a 0x2 _g_tRegPsrWinPosCfg
+ 0x7e08680c 0x2 _g_tRegPsrRlInfoCfg
+ 0x7e08680e 0x2 _g_tRegPsrMasterRlEn
+ 0x7e086810 0x2 _g_tRegPsrRlSttdCfg
+ 0x7e086812 0x2 _g_tRegPsrPeriodCfg
+ 0x7e086814 0x2 _g_tRegPsrIntInfo
+ 0x7e086816 0xc _g_atRegPsrSrcAndChanCfg
+ 0x7e086822 0xc _g_atRegPsrRlMrtrCfg
+ 0x7e08682e 0x2 _g_tRegPsrStartPosCfg
+ 0x7e086830 0x2 _g_tRegPsrPosEnCfg
+ 0x7e086832 0x2 _g_tRegPsrCmModeConfig
+ 0x7e086834 0x2 _g_tRegPsrCmEnCfg
+ 0x7e086836 0x6a _g_wRegPsrCfg
+ 0x7e0868a0 0x2 _g_tRegPsrIntStatus
+ 0x7e0868a2 0x2 _g_tRegPsrProFileNum
+ 0x7e0868a4 0x2 _g_tRegPsrFrameNum
+ 0x7e0868a6 0x2 _g_tRegPsrWorkStatus
+ 0x7e0868a8 0x2 _g_tRegPsrCfgError
+ 0x7e0868aa 0xc _g_atRegPsrRlPosReports
+
+.reg12 0x7e087000 0x4c
+ *(.tx_reg)
+ .tx_reg 0x7e087000 0x4c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7e087000 0x4c _g_tRegTxReg
+
+.reg13 0x7e087600 0xf2
+ *(.utr_reg)
+ .utr_reg 0x7e087600 0xf2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ 0x7e087600 0xf2 _g_tL1wRegRtxUtrReg
+
+.reg14 0x7e087c00 0x40
+ *(.eutr_reg)
+ .eutr_reg 0x7e087c00 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ 0x7e087c00 0x40 _g_tL1wEutrParaConf
+
+//.reg15
+ *(.rake_reg)
+
+.reg16 0x7e088000 0x480
+ *(.rx_cfg_chip)
+ .rx_cfg_chip 0x7e088000 0x480 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e088000 0x480 _g_tRegRxRakeChipLvl
+
+.reg17 0x7e088800 0x240
+ *(.rx_cfg_symb)
+ .rx_cfg_symb 0x7e088800 0x240 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e088800 0x240 _g_tRegRxRakeSymbLvl
+
+.reg18 0x7e089000 0x38
+ *(.rx_cfg_comb)
+ .rx_cfg_comb 0x7e089000 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e089000 0x38 _g_tRegRxRakeCombLvl
+
+.reg19 0x7e089800 0xc0
+ *(.rx_cfg_post)
+ .rx_cfg_post 0x7e089800 0xc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e089800 0xc0 _g_tRegRxRakePostLvl
+
+.reg20 0x7e08a000 0xc00
+ *(.gdtr_reg)
+ .gdtr_reg 0x7e08a000 0xc00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7e08a000 0x200 _g_tRegRtxDtrReg
+ 0x7e08a200 0x600 _g_adReserve
+ 0x7e08a800 0x400 _g_tRegRtxDtrNewReg
+
+.reg21 0x7e08c000 0x1e
+ *(.eagch_reg)
+ .eagch_reg 0x7e08c000 0x1e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7e08c000 0x1e _g_tRegRtxAgchReg
+
+.adr_reg 0x7e08c400 0x164
+ *(.adr_reg)
+ .adr_reg 0x7e08c400 0x164 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08c400 0x2 _g_dL1wRegAdrVer
+ 0x7e08c402 0x2 _g_tL1wRegAdrCtrl
+ 0x7e08c404 0x4 _g_adL1wRegAdrReserved1
+ 0x7e08c408 0x2 _g_tL1wRegAdrAnt1Slot0Fc
+ 0x7e08c40a 0x2 _g_tL1wRegAdrAnt1Slot1Fc
+ 0x7e08c40c 0x2 _g_tL1wRegAdrAnt1Slot2Fc
+ 0x7e08c40e 0x2 _g_tL1wRegAdrAnt2Slot0Fc
+ 0x7e08c410 0x2 _g_tL1wRegAdrAnt2Slot1Fc
+ 0x7e08c412 0x2 _g_tL1wRegAdrAnt2Slot2Fc
+ 0x7e08c414 0x2 _g_adL1wRegAdrReserved2
+ 0x7e08c416 0x2 _g_tL1wRegAdrRxTxMode
+ 0x7e08c418 0x2 _g_tL1wRegAdrCir
+ 0x7e08c41a 0x2 _g_tL1wRegAdrCirAlpha
+ 0x7e08c41c 0x2 _g_dL1wRegAdrFingerMaskR1T1L
+ 0x7e08c41e 0x2 _g_dL1wRegAdrFingerMaskR1T1H
+ 0x7e08c420 0x2 _g_dL1wRegAdrFingerMaskR1T2L
+ 0x7e08c422 0x2 _g_dL1wRegAdrFingerMaskR1T2H
+ 0x7e08c424 0x2 _g_dL1wRegAdrFingerMaskR2T1L
+ 0x7e08c426 0x2 _g_dL1wRegAdrFingerMaskR2T1H
+ 0x7e08c428 0x2 _g_dL1wRegAdrFingerMaskR2T2L
+ 0x7e08c42a 0x2 _g_dL1wRegAdrFingerMaskR2T2H
+ 0x7e08c42c 0x2 _g_tL1wRegAdrNoiseThresh
+ 0x7e08c42e 0x4 _g_adL1wRegAdrReserved3
+ 0x7e08c432 0x2 _g_tL1wRegAdrDataPscCoeQ
+ 0x7e08c434 0x2 _g_tL1wRegAdrAntLambda
+ 0x7e08c436 0x2 _g_tL1wRegAdrDataPscCoeP
+ 0x7e08c438 0x2 _g_tL1wRegAdrCirFft
+ 0x7e08c43a 0x2 _g_tL1wRegAdrDataFft
+ 0x7e08c43c 0x2 _g_tL1wRegAdrRyyCoeff
+ 0x7e08c43e 0x2 _g_tL1wRegAdrSchCancelCoeff
+ 0x7e08c440 0x2 _g_tL1wRegAdrSchCancel
+ 0x7e08c442 0x2 _g_tL1wRegAdrCpichCodeX
+ 0x7e08c444 0x2 _g_tL1wRegAdrCpichCodeY
+ 0x7e08c446 0x2 _g_tL1wRegAdrHsscchHsdschCodeX
+ 0x7e08c448 0x2 _g_tL1wRegAdrHsscchHsdschCodeY
+ 0x7e08c44a 0x2 _g_tL1wRegAdrCpichHsscchChEn
+ 0x7e08c44c 0x2 _g_tL1wRegAdrHsdsch
+ 0x7e08c44e 0x2 _g_tL1wRegAdrHsscch
+ 0x7e08c450 0x2 _g_tL1wRegAdrChCompsEn
+ 0x7e08c452 0x2 _g_tL1wRegAdrSymCpichAlpha
+ 0x7e08c454 0x2 _g_tL1wRegAdrCltd1
+ 0x7e08c456 0x2 _g_tL1wRegAdrTimeCfg
+ 0x7e08c458 0x2 _g_tL1wRegAdrHsdschParaA
+ 0x7e08c45a 0x2 _g_tL1wRegAdrMemClkBypass
+ 0x7e08c45c 0x2 _g_tL1wRegAdrModuleClkBypass
+ 0x7e08c45e 0x2 _g_tL1wRegAdrAmMean
+ 0x7e08c460 0x2 _g_tL1wRegAdrAnt1EqNoise
+ 0x7e08c462 0x2 _g_tL1wRegAdrAnt2EqNoise
+ 0x7e08c464 0x9c _g_adL1wRegAdrReserved4
+ 0x7e08c500 0x3c _g_atL1wRegAdrCpichData
+ 0x7e08c53c 0x2 _g_dL1wRegAdrReserved5
+ 0x7e08c53e 0x2 _g_tL1wRegAdrCirSlotNum
+ 0x7e08c540 0x2 _g_dL1wRegAdrMaxPowerR1T1
+ 0x7e08c542 0x2 _g_dL1wRegAdrMaxPowerR2T1
+ 0x7e08c544 0x2 _g_dL1wRegAdrMaxPowerR1T2
+ 0x7e08c546 0x2 _g_dL1wRegAdrMaxPowerR2T2
+ 0x7e08c548 0x2 _g_dL1wRegAdrNoisePowerR1
+ 0x7e08c54a 0x2 _g_dL1wRegAdrNoisePowerR2
+ 0x7e08c54c 0x2 _g_dL1wRegAdrMaxPowerR1T1Bak
+ 0x7e08c54e 0x2 _g_dL1wRegAdrMaxPowerR2T1Bak
+ 0x7e08c550 0x2 _g_dL1wRegAdrMaxPowerR1T2Bak
+ 0x7e08c552 0x2 _g_dL1wRegAdrMaxPowerR2T2Bak
+ 0x7e08c554 0x2 _g_dL1wRegAdrNoisePowerR1Bak
+ 0x7e08c556 0x2 _g_dL1wRegAdrNoisePowerR2Bak
+ 0x7e08c558 0x6 _g_adL1wRegAdrCpichT1SlotAbs
+ 0x7e08c55e 0x6 _g_adL1wRegAdrCpichT2SlotAbs
+
+.ic_reg 0x7e08c600 0xd2
+ *(.ic_reg)
+ .ic_reg 0x7e08c600 0xd2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08c600 0x2 _g_tL1wRegIcVer
+ 0x7e08c602 0x2 _g_tL1wRegIcEnable
+ 0x7e08c604 0x2 _g_tL1wRegIcMode
+ 0x7e08c606 0x2 _g_uL1wRegIcSubFrameHead
+ 0x7e08c608 0x40 _g_tL1wRegIcCellFinger
+ 0x7e08c648 0x10 _g_atL1wRegIcScrcodeXY
+ 0x7e08c658 0x8 _g_atL1wRegIcSchCodeNum
+ 0x7e08c660 0x2 _g_tL1wRegIcBchLambda
+ 0x7e08c662 0x2 _g_tL1wRegIcSchLambda
+ 0x7e08c664 0x2 _g_tL1wRegIcAlpha
+ 0x7e08c666 0x2 _g_tL1wRegIcCpichLambda
+ 0x7e08c668 0x2 _g_tL1wRegIcAnt0Che4xPos
+ 0x7e08c66a 0x2 _g_tL1wRegIcAnt1Che4xPos
+ 0x7e08c66c 0x6 _g_uL1wRegIcAnt0CellSubFrmHead
+ 0x7e08c672 0xc _g_adL1wRegIcReserved1
+ 0x7e08c67e 0x2 _g_tL1wRegIcConfigOver
+ 0x7e08c680 0x18 _g_adL1wRegIcReserved2
+ 0x7e08c698 0x6 _g_uL1wRegAdjIcConfigTime
+ 0x7e08c69e 0x2 _g_tRegIcSubFrmHeadTime
+ 0x7e08c6a0 0x2 _g_uL1wRegIcConfigTime
+ 0x7e08c6a2 0x6 _g_tL1wRegIcCell0CpichSymModulus
+ 0x7e08c6a8 0x6 _g_tL1wRegIcCell1CpichSymModulus
+ 0x7e08c6ae 0x6 _g_tL1wRegIcCell2CpichSymModulus
+ 0x7e08c6b4 0x6 _g_tL1wRegIcCell3CpichSymModulus
+ 0x7e08c6ba 0x6 _g_tL1wRegIcCell0BchSymModulus
+ 0x7e08c6c0 0x6 _g_tL1wRegIcCell1BchSymModulus
+ 0x7e08c6c6 0x6 _g_tL1wRegIcCell2BchSymModulus
+ 0x7e08c6cc 0x6 _g_tL1wRegIcCell3BchSymModulus
+
+.hdtr_reg 0x7e08e000 0xce
+ *(.hdtr_reg)
+ .hdtr_reg 0x7e08e000 0xce T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08e000 0x2 _g_tL1wRegHdtrDemodule
+ 0x7e08e002 0x2 _g_tL1wRegHdtrHsdsch
+ 0x7e08e004 0xa _g_adL1wRegHdtrReserved1
+ 0x7e08e00e 0x2 _g_tL1wRegHdtr2ndRmNtp1
+ 0x7e08e010 0x2 _g_tL1wRegHdtr2ndRmNtp2
+ 0x7e08e012 0x2 _g_tL1wRegHdtr2ndRmNdi
+ 0x7e08e014 0x2 _g_dL1wRegHdtrReserved1
+ 0x7e08e016 0x2 _g_tL1wRegHdtrHarqId
+ 0x7e08e018 0x6 _g_adL1wRegHdtrReserved2
+ 0x7e08e01e 0x2 _g_tL1wRegHdtrTurboCfg
+ 0x7e08e020 0x14 _g_adL1wRegHdtrReserved3
+ 0x7e08e034 0x2 _g_tL1wRegHdtr2ndRmType
+ 0x7e08e036 0x2 _g_tL1wRegHdtr2ndRmEiniSys
+ 0x7e08e038 0x2 _g_tL1wRegHdtr2ndRmEplusSys
+ 0x7e08e03a 0x2 _g_tL1wRegHdtr2ndRmEminusSys
+ 0x7e08e03c 0x2 _g_tL1wRegHdtr2ndRmEiniP1
+ 0x7e08e03e 0x2 _g_tL1wRegHdtr2ndRmEplusP1
+ 0x7e08e040 0x2 _g_tL1wRegHdtr2ndRmEminusP1
+ 0x7e08e042 0x2 _g_tL1wRegHdtr2ndRmEiniP2
+ 0x7e08e044 0x2 _g_tL1wRegHdtr2ndRmEplusP2
+ 0x7e08e046 0x2 _g_tL1wRegHdtr2ndRmEminusP2
+ 0x7e08e048 0x2 _g_tL1wRegHdtr1stRmFlg
+ 0x7e08e04a 0x2 _g_tL1wRegHdtr2ndRmNp1
+ 0x7e08e04c 0x2 _g_tL1wRegHdtr2ndRmNp2
+ 0x7e08e04e 0x2 _g_tL1wRegHdtr1stRmEiniP1
+ 0x7e08e050 0x2 _g_tL1wRegHdtr1stRmEplusP1
+ 0x7e08e052 0x2 _g_tL1wRegHdtr1stRmEminusP1
+ 0x7e08e054 0x2 _g_tL1wRegHdtr1stRmEiniP2
+ 0x7e08e056 0x2 _g_tL1wRegHdtr1stRmEplusP2
+ 0x7e08e058 0x2 _g_tL1wRegHdtr1stRmEminusP2
+ 0x7e08e05a 0x2 _g_dL1wRegHdtrReserved2
+ 0x7e08e05c 0x2 _g_tL1wRegHdtrCodeBlk
+ 0x7e08e05e 0x2 _g_tL1wRegHdtrCrcRslt
+ 0x7e08e060 0x2 _g_tL1wRegHdtrTbSize
+ 0x7e08e062 0x14 _g_adL1wRegHdtrReserved4
+ 0x7e08e076 0x2 _g_tL1wRegHdtrEn
+ 0x7e08e078 0x2 _g_dL1wRegHdtrReserved3
+ 0x7e08e07a 0x2 _g_tL1wRegHdtrHarqAddr
+ 0x7e08e07c 0x2 _g_tL1wRegHdtr2ndRmNtsys
+ 0x7e08e07e 0x2 _g_tL1wRegHdtr2ndRmNsys
+ 0x7e08e080 0x2 _g_tL1wRegHdtrNdataCodeBlkNum
+ 0x7e08e082 0x2 _g_tL1wRegHdtrTbWithCrc
+ 0x7e08e084 0x2 _g_tL1wRegHdtrCtrl
+ 0x7e08e086 0x2 _g_tL1wRegHdtrLlrBitWidth
+ 0x7e08e088 0x4 _g_adL1wRegHdtrReserved5
+ 0x7e08e08c 0x2 _g_tL1wRegHdtrTargetBitWidth
+ 0x7e08e08e 0x2 _g_dL1wRegHdtrReserved8
+ 0x7e08e090 0x2 _g_tL1wRegHdtrHarqBitWidth
+ 0x7e08e092 0x2 _g_tL1wRegHdtrTurboModuleClkMsk
+ 0x7e08e094 0x6 _g_dL1wRegHdtrReserved9
+ 0x7e08e09a 0x2 _g_tL1wRegHdtrDeintlvClkCtrl
+ 0x7e08e09c 0x2 _g_tL1wRegHdtrSoftBitsClkCtrl
+ 0x7e08e09e 0x2 _g_dL1wRegHdtrReserved10
+ 0x7e08e0a0 0x2 _g_tL1wRegHdtrDrmClkCtrl
+ 0x7e08e0a2 0x2 _g_tL1wRegHdtrCrcClkCtrl
+ 0x7e08e0a4 0x2 _g_tL1wRegHdtrTrchRamClkCtrl
+ 0x7e08e0a6 0x2 _g_tL1wRegHdtrTurboSoftReset
+ 0x7e08e0a8 0x2 _g_tL1wRegHdtrStartCfg
+ 0x7e08e0aa 0x2 _g_tL1wRegHdtrDemoduleCfg
+ 0x7e08e0ac 0x14 _g_adL1wRegHdtrReserved6
+ 0x7e08e0c0 0x2 _g_tL1wRegHdtrSubFrm
+ 0x7e08e0c2 0x2 _g_tL1wRegHdtrModuleVer
+ 0x7e08e0c4 0x2 _g_tL1wRegHdtrChipName
+ 0x7e08e0c6 0x2 _g_adL1wRegHdtrReserved7
+ 0x7e08e0c8 0x2 _g_tL1wRegHdtrCrcRedundancy
+ 0x7e08e0ca 0x2 _g_tL1wRegHdtrHrnti
+ 0x7e08e0cc 0x2 _g_tL1wRegHdtrChStart
+
+.reg_hsscch 0x7e08e400 0x4c
+ *(.hsscch_reg)
+ .hsscch_reg 0x7e08e400 0x4c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08e400 0x2 _g_tL1wRegHsscchCtrl
+ 0x7e08e402 0x2 _g_tL1wRegHsscchMode
+ 0x7e08e404 0x2 _g_tL1wRegHsscchHrnti
+ 0x7e08e406 0x2 _g_tL1wRegHsscchViterbiThresh
+ 0x7e08e408 0x2 _g_tL1wRegHsscchPart1Rcv
+ 0x7e08e40a 0x2 _g_tL1wRegHsscchPart1Flg
+ 0x7e08e40c 0x2 _g_tL1wRegHsscchPart2Rcv
+ 0x7e08e40e 0x2 _g_tL1wRegHsscchHmRslt
+ 0x7e08e410 0x8 _g_atL1wRegHsscchSmRslt
+ 0x7e08e418 0x2 _g_tL1wRegHsscchSmPart1ChMsk
+ 0x7e08e41a 0x8 _g_atL1wRegHsscchS0Dist
+ 0x7e08e422 0x8 _g_atL1wRegHsscchMaxDist
+ 0x7e08e42a 0x8 _g_atL1wRegHsscchMinDist
+ 0x7e08e432 0x8 _g_atL1wRegHsscchPart1Sum
+ 0x7e08e43a 0x2 _g_tL1wRegHsscchPart2Rslt
+ 0x7e08e43c 0x2 _g_tL1wRegHsscchModuleVer
+ 0x7e08e43e 0x2 _g_tL1wRegHsscchChipName
+ 0x7e08e440 0x2 _g_tL1wRegHsscchBcchHrntiEn
+ 0x7e08e442 0x2 _g_tL1wRegHsscchBcchHrntiSmRslt
+ 0x7e08e444 0x2 _g_tL1wRegHsscchBcchHrntiS0Dist
+ 0x7e08e446 0x2 _g_tL1wRegHsscchBcchHrntiMaxDist
+ 0x7e08e448 0x2 _g_tL1wRegHsscchBcchHrntiMinDist
+ 0x7e08e44a 0x2 _g_tL1wRegHsscchBcchHrntiPart1Sum
+
+.reg22 0x7e08e800 0x30
+ *(.pich_reg)
+ .pich_reg 0x7e08e800 0x30 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ 0x7e08e800 0x2 _g_wRegPiAiVersion
+ 0x7e08e802 0x2 _g_tRegPiAiEnble
+ 0x7e08e804 0x2 _g_tRegPichMode
+ 0x7e08e806 0x2 _g_tRegAlpha
+ 0x7e08e808 0x2 _g_tRegRotatePara
+ 0x7e08e80a 0x10 _g_tRegFingerPara
+ 0x7e08e81a 0x2 _g_tRegPiAIOffsetPara
+ 0x7e08e81c 0x2 _g_tRegPiAIOvsfPara
+ 0x7e08e81e 0x2 _g_tRegAfcFingerNum
+ 0x7e08e820 0x2 _g_tRegAichSeqIndex
+ 0x7e08e822 0x2 _g_tRegSetUpdateTime
+ 0x7e08e824 0x2 _g_tRegConfigOver
+ 0x7e08e826 0x4 _g_tRegCpichPower
+ 0x7e08e82a 0x2 _g_tRegAichAmplitude
+ 0x7e08e82c 0x2 _g_tRegConfigState
+ 0x7e08e82e 0x2 _g_tRegConfigTime
+
+.reg23
+ *(.slotbuf_reg)
+
+.less_reg 0x7e08f400 0x280
+ *(.less_reg)
+ .less_reg 0x7e08f400 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08f400 0x200 _g_atL1wRegLessTbCfg
+ 0x7e08f600 0x2 _g_tL1wRegLessReset
+ 0x7e08f602 0x2 _g_tL1wRegLessDataOrder
+ 0x7e08f604 0x2 _g_tL1wRegLessHrnti
+ 0x7e08f606 0x2 _g_tL1wRegLessSubFrm
+ 0x7e08f608 0x2 _g_tL1wRegLessTurboCtrl
+ 0x7e08f60a 0x2 _g_tL1wRegLessClkCtrl
+ 0x7e08f60c 0x2 _g_tL1wRegLessLlrRepBitWidth
+ 0x7e08f60e 0x2 _g_tL1wRegLessTranPara
+ 0x7e08f610 0x2 _g_tL1wRegLessUpdate
+ 0x7e08f612 0x6e _g_adL1wRegLessReserved1
+
+.reg24 0x7c080000 0x280
+ *(.csr_reg_ram)
+ .csr_reg_ram 0x7c080000 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7c080000 0x78 _g_atRegCsrStep1Peek
+ 0x7c080078 0x8 _g_adCsrReserved13
+ 0x7c080080 0x78 _g_atRegCsrStep1PeekVal
+ 0x7c0800f8 0x108 _g_adCsrReserved14
+ 0x7c080200 0x80 _g_dwCodeListSet
+
+.reg25 0x7c080400 0xd0
+ *(.meas_ram)
+ .meas_ram 0x7c080400 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ 0x7c080400 0xd0 _g_atL1wRegMeasResultInfo
+
+.reg26 0x7c080600 0x300
+ *(.bch_ram)
+ .bch_ram 0x7c080600 0x300 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ 0x7c080600 0x300 _g_atRegBchBmiSymbol
+
+.reg27 0x7c088000 0x398
+ *(.psr_data_ram)
+ .psr_data_ram 0x7c088000 0x398 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ 0x7c088000 0x180 _g_atRegPsrAnt0RLFingerInfo
+ 0x7c088180 0xc _g_atRegPsrAnt0NoiseMantisse
+ 0x7c08818c 0xc _g_atRegPsrAnt0NoiseFingerCommExp
+ 0x7c088198 0x68 _g_wRegPsrRamCfg
+ 0x7c088200 0x180 _g_atRegPsrAnt1RLsFingerInfo
+ 0x7c088380 0xc _g_atRegPsrAnt1NoiseMantisse
+ 0x7c08838c 0xc _g_atRegPsrAnt1NoiseFingerCommExp
+
+.reg28 0x7c08e000 0xf00
+ *(.tx_ram0)
+ .tx_ram0 0x7c08e000 0xf00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7c08e000 0xf00 _g_atTxRam0
+
+.reg29 0x7c090000 0xf00
+ *(.tx_ram1)
+ .tx_ram1 0x7c090000 0xf00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7c090000 0xf00 _g_atTxRam1
+
+.reg30 0x7c092000 0x490
+ *(.utr_ram)
+ .utr_ram 0x7c092000 0x490 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ 0x7c092000 0x490 _g_awL1wRamUtrData
+
+.reg31 0x7c096000 0x500
+ *(.eutr_ram)
+ .eutr_ram 0x7c096000 0x500 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ 0x7c096000 0x500 _g_awL1wRamEutrData
+
+.reg32 0x7c09a000 0x140
+ *(.rx_raw_cpich)
+ .rx_raw_cpich 0x7c09a000 0x140 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a000 0x140 _g_atRegRxRawCpich
+
+.reg33 0x7c09a140 0x40
+ *(.rx_slotwt)
+ .rx_slotwt 0x7c09a140 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a140 0x40 _g_atRegRxSlotwt
+
+.reg34 0x7c09a180 0x40
+ *(.rx_afc)
+ .rx_afc 0x7c09a180 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a180 0x40 _g_atRegRxAfcRam
+
+.reg35 0x7c09a1c0 0x40
+ *(.rx_raw_noise)
+ .rx_raw_noise 0x7c09a1c0 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a1c0 0x40 _g_atRegRxRawNoise
+
+.reg36 0x7c09a240 0x30
+ *(.rx_comb_tpcpl)
+ .rx_comb_tpcpl
+ 0x7c09a240 0x30 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a240 0x30 _g_tRegRxCombTpcPilot
+
+.reg37 0x7c09a800 0x100
+ *(.rx_pilot)
+ .rx_pilot 0x7c09a800 0x100 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a800 0x100 _g_atRegRxRawPilot
+
+.reg38 0x7c09ac00 0x14
+ *(.rx_piaipage0)
+ .rx_piaipage0 0x7c09ac00 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ac00 0x14 _g_tRegRxCombPiAiPage0
+
+.reg39 0x7c09ac20 0x14
+ *(.rx_piaipage1)
+ .rx_piaipage1 0x7c09ac20 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ac20 0x14 _g_tRegRxCombPiAiPage1
+
+.reg40 0x7c09c000 0x280
+ *(.rx_dpch0)
+ .rx_dpch0 0x7c09c000 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09c000 0x280 _g_tRegRxCombDpch0
+
+.reg41 0x7c09c800 0x280
+ *(.rx_dpch1)
+ .rx_dpch1 0x7c09c800 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09c800 0x280 _g_tRegRxCombDpch1
+
+.reg42 0x7c09d800 0xa0
+ *(.rx_scch0)
+ .rx_scch0 0x7c09d800 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09d800 0xa0 _g_tRegRxCombScchPage0
+
+.reg43 0x7c09d900 0xa0
+ *(.rx_scch1)
+ .rx_scch1 0x7c09d900 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09d900 0xa0 _g_tRegRxCombScchPage1
+
+.reg44 0x7c09dc00 0x28
+ *(.rx_rghi00)
+ .rx_rghi00 0x7c09dc00 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc00 0x28 _g_tRegRxCombRgHiRl0Page0
+
+.reg45 0x7c09dc40 0x28
+ *(.rx_rghi01)
+ .rx_rghi01 0x7c09dc40 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc40 0x28 _g_tRegRxCombRgHiRl0Page1
+
+.reg46 0x7c09dc80 0x28
+ *(.rx_rghi10)
+ .rx_rghi10 0x7c09dc80 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc80 0x28 _g_tRegRxCombRgHiRl1Page0
+
+.reg47 0x7c09dcc0 0x28
+ *(.rx_rghi11)
+ .rx_rghi11 0x7c09dcc0 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dcc0 0x28 _g_tRegRxCombRgHiRl1Page1
+
+.reg48 0x7c09dd00 0x28
+ *(.rx_rghi20)
+ .rx_rghi20 0x7c09dd00 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd00 0x28 _g_tRegRxCombRgHiRl2Page0
+
+.reg49 0x7c09dd40 0x28
+ *(.rx_rghi21)
+ .rx_rghi21 0x7c09dd40 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd40 0x28 _g_tRegRxCombRgHiRl2Page1
+
+.reg50 0x7c09dd80 0x28
+ *(.rx_rghi30)
+ .rx_rghi30 0x7c09dd80 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd80 0x28 _g_tRegRxCombRgHiRl3Page0
+
+.reg51 0x7c09ddc0 0x28
+ *(.rx_rghi31)
+ .rx_rghi31 0x7c09ddc0 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ddc0 0x28 _g_tRegRxCombRgHiRl3Page1
+
+.reg52 0x7c09df00 0x14
+ *(.rx_agch0)
+ .rx_agch0 0x7c09df00 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09df00 0x14 _g_tRegRxCombAgchPage0
+
+.reg53 0x7c09df20 0x14
+ *(.rx_agch1)
+ .rx_agch1 0x7c09df20 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09df20 0x14 _g_tRegRxCombAgchPage1
+
+.reg54 0x7c0a0000 0x400
+ *(.gdtr_ram)
+ .gdtr_ram 0x7c0a0000 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7c0a0000 0x400 _g_uRegDtrTtiResultReg
+
+.reg55
+ *(.slotbuf_ram)
+
+.reg56 0x0009a300 0x36
+ *(.sleep_reg)
+ .sleep_reg 0x0009a300 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ 0x0009a300 0x2 _g_URegLpmTime1CtrlCmd
+ 0x0009a302 0x2 _g_uRegLpmTime1Cfg
+ 0x0009a304 0x2 _g_uRegLpmTime2Cfg
+ 0x0009a306 0x2 _g_uRegLpmTime3Cfg
+ 0x0009a308 0x2 _g_uRegLpmTime4Cfg
+ 0x0009a30a 0x2 _g_uRegLpmTime5PosedgeCfg
+ 0x0009a30c 0x2 _g_uRegLpmTime5EngedgeCfg
+ 0x0009a30e 0x2 _g_uRegLpmMrtrTrace
+ 0x0009a310 0x2 _g_uRegLpmLocalMrtrTrace
+ 0x0009a312 0x2 _g_uRegLpm32KCailSelCfg
+ 0x0009a314 0x2 _g_dRegLpmCount32K
+ 0x0009a316 0x2 _g_dRegLpm15MCountOffset
+ 0x0009a318 0x2 _g_dRegLpmReserve2
+ 0x0009a31a 0x2 _g_dRegLpm32KFactorInteg
+ 0x0009a31c 0x2 _g_dRegLpm32KFactorDecimal
+ 0x0009a31e 0x2 _g_dRegLpm32KSoftFactorInteg
+ 0x0009a320 0x2 _g_dRegLpm32KSoftFactorDecimal
+ 0x0009a322 0x2 _g_dRegLpmSoftReset
+ 0x0009a324 0x2 _g_dRegLpmMrtrOffset
+ 0x0009a326 0x2 _g_uRegLowPowerCtrl
+ 0x0009a328 0x2 _g_dRegLpmSuperframeOff
+ 0x0009a32a 0x2 _g_dRegLpmReserve3
+ 0x0009a32c 0x2 _g_URegLpmTime2CtrlCmd
+ 0x0009a32e 0x2 _g_URegLpmTime3CtrlCmd
+ 0x0009a330 0x2 _g_URegLpmTime4CtrlCmd
+ 0x0009a332 0x2 _g_URegLpmTime5CtrlCmd
+ 0x0009a334 0x2 _g_tRegLpmClkEnDisable
+
+.reg57 0x7c250000 0x34
+ *(.rffe_reg)
+ .rffe_reg 0x7c250000 0x34 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ 0x7c250000 0x2 _g_dRegRffeReset
+ 0x7c250002 0x2 _g_dRegRffeRdSpeedSet
+ 0x7c250004 0xe _g_adReserved16
+ 0x7c250012 0x2 _g_dRegRffeWcdmaRdData
+ 0x7c250014 0x4 _g_adReserved17
+ 0x7c250018 0x2 _g_dRegRffeCh0Packet
+ 0x7c25001a 0x16 _g_adReserved18
+ 0x7c250030 0x2 _g_dRegRffeConCrrnt
+ 0x7c250032 0x2 _g_dRegRffeFreqDiv
+
+.reg58
+ *(.spi_reg)
+
+.adr_ram 0x7c0b0000 0x400
+ *(.adr_ram)
+ .adr_ram 0x7c0b0000 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7c0b0000 0x80 _g_atL1wRamAdrCirR1T1
+ 0x7c0b0080 0x80 _g_atL1wRamAdrCirR2T1
+ 0x7c0b0100 0x80 _g_atL1wRamAdrCirR1T2
+ 0x7c0b0180 0x80 _g_atL1wRamAdrCirR2T2
+ 0x7c0b0200 0x80 _g_atL1wRamAdrCirR1T1Bak
+ 0x7c0b0280 0x80 _g_atL1wRamAdrCirR2T1Bak
+ 0x7c0b0300 0x80 _g_atL1wRamAdrCirR1T2Bak
+ 0x7c0b0380 0x80 _g_atL1wRamAdrCirR2T2Bak
+
+.hdtr_ram 0x7c0c0000 0xa4e
+ *(.hdtr_ram)
+ .hdtr_ram 0x7c0c0000 0xa4e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7c0c0000 0xa4e _g_adL1wRamHdtr
+
+.piai_ram 0x7c0c8000 0xd0
+ *(.piai_ram)
+ .piai_ram 0x7c0c8000 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ 0x7c0c8000 0x20 _g_tRegEAISymbolRam
+ 0x7c0c8020 0x20 _g_tRegRservedRam
+ 0x7c0c8040 0x40 _g_tRegPIAISymbolRam
+ 0x7c0c8080 0x50 _g_tRegCpichSymbolRam
+
+.slotbuf_ram
+ *(.slotbuf_ram)
+
+.slotbuf_lte_reg
+ *(.slotbuf_lte_reg)
+
+.td_tpu_reg
+ *(.td_tpu_reg)
+
+.td_top_reg
+ *(.td_top_reg)
+
+.td_csr_reg
+ *(.td_csr_reg)
+
+.td_csr_dpram
+ *(.td_csr_dpram)
+
+.td_rfc_reg
+ *(.td_rfc_reg)
+
+.td_dst_reg
+ *(.td_dst_reg)
+
+.td_dst_dpram
+ *(.td_dst_dpram)
+
+.td_dst_interf_dpram
+ *(.td_dst_interf_dpram)
+
+.td_jd_reg
+ *(.td_jd_reg)
+
+.td_jd_dpram2
+ *(.td_jd_dpram2)
+
+.td_utr_dpram
+ *(.td_utr_dpram)
+
+.td_utr_reg
+ *(.td_utr_reg)
+
+.td_ulc_reg
+ *(.td_ulc_reg)
+
+.td_afc_reg
+ *(.td_afc_reg)
+
+.td_gdtr_reg
+ *(.td_gdtr_reg)
+
+.td_gdtr_dpram
+ *(.td_gdtr_dpram)
+
+.td_ul_hsupa_reg
+ *(.td_ul_hsupa_reg)
+
+.td_ul_hsupa_dpram
+ *(.td_ul_hsupa_dpram)
+
+.td_dm_rdb_reg
+ *(.td_dm_rdb_reg)
+
+.td_hdtr_reg
+ *(.td_hdtr_reg)
+
+.td_hdtr_dpram
+ *(.td_hdtr_dpram)
+
+.td_sleep_reg
+ *(.td_sleep_reg)
+
+.td_pslpm_reg
+ *(.td_pslpm_reg)
+
+.td_uart_reg
+ *(.td_uart_reg)
+
+.td_tfci_reg
+ *(.td_tfci_reg)
+
+.td_viterbi_reg
+ *(.td_viterbi_reg)
+
+.dst_slot_buf
+ *(.dst_slot_buf)
+ 0x00017000 __heap_start = 0x17000
+ 0x00017010 __heap_limit = 0x17010
+ 0x00017fff __stack_start = 0x17fff
+ 0x00017010 __stack_end = __heap_limit
+ 0x00000001 ___ZSP_G3___ = 0x1
+OUTPUT(T:/cp/phy/project/7520_phy_plat_zsp/bin/debug/proj_lte_w_td.out elf32-sdsp)
+
+.comment 0x00000000 0x4875
+ .comment 0x00000000 0x15 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ .comment 0x00000015 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ .comment 0x00000051 0x31 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+ .comment 0x00000082 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ .comment 0x000000be 0x3e T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+ .comment 0x000000fc 0x15 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ .comment 0x00000112 0x15 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ .comment 0x00000127 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ .comment 0x0000015b 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ .comment 0x0000018e 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ .comment 0x000001c0 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ .comment 0x000001f2 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ .comment 0x00000225 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ .comment 0x00000257 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ .comment 0x0000028c 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ .comment 0x000002be 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ .comment 0x000002f0 0x36 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ .comment 0x00000327 0x35 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ .comment 0x0000035c 0x31 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ .comment 0x0000038e 0x41 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ .comment 0x000003cf 0x3e T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ .comment 0x0000040d 0x41 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ .comment 0x0000044f 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ .comment 0x0000048d 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ .comment 0x000004cd 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ .comment 0x00000509 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ .comment 0x00000546 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ .comment 0x00000582 0x3b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ .comment 0x000005be 0x3b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ .comment 0x000005f9 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ .comment 0x0000063a 0x15 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ .comment 0x0000064f 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ .comment 0x0000068d 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ .comment 0x000006ca 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ .comment 0x00000706 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ .comment 0x00000743 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ .comment 0x00000781 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
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+.stab 0x00000000 0x1685d0
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diff --git a/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
new file mode 100755
index 0000000..86ac87e
--- /dev/null
+++ b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
Binary files differ
diff --git a/Uboot/cp/ps/driver/src/chipsets/src/audio_base/volte/hal_volte.c b/Uboot/cp/ps/driver/src/chipsets/src/audio_base/volte/hal_volte.c
new file mode 100755
index 0000000..ebdb296
--- /dev/null
+++ b/Uboot/cp/ps/driver/src/chipsets/src/audio_base/volte/hal_volte.c
Binary files differ
diff --git a/do_package_tool/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/evb_cpuphy.bin b/do_package_tool/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/evb_cpuphy.bin
new file mode 100755
index 0000000..c3de9f3
--- /dev/null
+++ b/do_package_tool/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/evb_cpuphy.bin
Binary files differ
diff --git a/do_package_tool/allbins/zx297520v3/prj_vehicle/elf_dc_ref/evb_cpuphy.map b/do_package_tool/allbins/zx297520v3/prj_vehicle/elf_dc_ref/evb_cpuphy.map
new file mode 100755
index 0000000..4a7e274
--- /dev/null
+++ b/do_package_tool/allbins/zx297520v3/prj_vehicle/elf_dc_ref/evb_cpuphy.map
@@ -0,0 +1,14691 @@
+Mapfile generated by: ZView-4.1.0-Windows
+Archive member included because of file (symbol)
+
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o (_odo_zsp_do_int)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o (_create_process)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o (_odo_panic)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_sys)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_main)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_process_entry)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o) (_send)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_start_zcos)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_go_search)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o) (_alloc)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o) (_odo_arch_init_interrupts)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_ZSP_DCacheUseDCFGRDescribe)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_ZSP_DCacheEnableNCSRAM)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o) (___zsp_dc_mba)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor_addr.o)
+ T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o) (___zsp_dc_mba_value)
+T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o) (_odo_pool_list)
+T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_TIMER0_ISR)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_BspTimerInit1)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_DrvPhyTimer1Init)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_L1_SysErrHnd)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_LoadStaticIDNCSRAM)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_SysEntry)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_g_atHookInfo)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_dwMacroSupport_ZX7520_PHY_SP_PS)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_w_assert)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_InitComAtNv)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_save_zsp880_reg)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_L1_DrvL2CacheTcmEnable)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_L1_DrvCacheDisable)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_DrvDmaInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_zDrvRpMsg_CreateChannel)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_LpmLatchInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o) (_g_dwPHY_USE_PSM)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_LpcDrvChangeCpuPhyFreq)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_tL1IratLpCtrl)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_aeClkSelToCpuFreq)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_PhyPowerOffSaveContext)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_PhyPowerOff)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_DrvWDTFeedDog)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_printk)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_iomemcpy_32)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o) (_L1_DrvL1CacheInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o) (_g_atDmaRegCh)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(dmc_zsp_0x140_lp.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_dei_handler_lp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheDsc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheDisableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheEnableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_ZSP_ICacheFlush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheLoadNCSRAM)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheUseICFGRDescribe)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheNonCacheableDisable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheDisableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheEnableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_ZSP_DCacheFlush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_DCacheLoadNCSRAM)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheClean)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheSetWriteThruRegion)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteAllocateEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteThruEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteThruDisable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheNonCacheableEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheExtraNonCacheableEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor_addr.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o) (___zsp_ic_mba_value)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_g_L1wPriTaskPid)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_g_tL1wNvBb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_BchTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DevMeasGetPreSyncInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_HspaTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DevRtxRxPchCfgReq)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_L1w_DevRfSleepInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevPcPilotIntInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o) (_g_tL1wHsdpaDbgInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_wL1wLessCfgIdx)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DrvDpramRxWriteClearData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_g_tUlRfTbl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevTxGetDchState)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1W_DevHsupaInitMacro)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_eDivState)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_DlsTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o) (_TAB_L1W_HSDPA_HSDPCCH_ACK_CODING)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_wPiAiAfcIntCnt)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o) (_L1w_DevCsrIntInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (_tPcCalcDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (_g_awL1wEngTempBuffer)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_g_tTxTrchInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRxSccpchDtrParam)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o) (_L1w_DevHsdpaCqiCalcPos)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o) (_L1w_DevRtxRxDecodePcch)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o) (_g_eL1wHsupaTaskType)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_L1w_DevRtxRxIntDataInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o) (_g_tL1wDchDlsPsrReq)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_L1w_DevHsupaIsEfachActive)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_bIsWUsePsm)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_tAfcErrorPrint)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o) (_g_atL1wTpuRegNtFixedEventInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_atDevBchAfcdb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRxInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o) (_L1w_DevRtxRxDsReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_atRfcDcLog)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DrvGetPiAiEnPara)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvLpcModemIntCtrl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_URegLpmTime1CtrlCmd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_g_awL1wRamUtrData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o) (_L1_DrvCsrInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_L1w_DrvSetTop01GdtrHdtrBitSet)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o) (_g_atL1wTpuIntStaticNtPara)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_dRfcSpiReadData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o) (_g_tRegTpuReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_L1w_DrvTxReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o) (_g_atL1wDrvMeasResultInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o) (_g_tRegPsrWinPosCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_g_bL1wHsdschConfigFlg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o) (_g_tL1wEutrParaConf)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvDpramIsEmpty)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o) (_g_tRegTxReg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvRxInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_top.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_wL1wTop00SoftReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_L1w_DrvDtrSetCsServiceFlg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DrvBchReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o) (_g_tRegCsrFpgaVersion)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_L1w_DrvUtrReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_uL1wRegIcSubFrameHead)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_L1w_DrvRfcAbbCsfHpfCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_g_tRegRxRakeChipLvl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o) (_L1w_DrvPsrStartPosCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o) (_g_atBandInfoTX)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o) (_g_tRegMeasBufOffline)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o) (_g_tRegPiAiEnble)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_TxCfgOver)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_SchedMainTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_g_tL1wRachProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_L1w_SchMeasQueryCellInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_tL1wCtrlDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCs1ProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_g_tServCellDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o) (_g_tL1wMeasProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_L1w_SchedHsupaGetUpaSchedDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCmProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_sc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o) (_L1w_SchedCs1SetStrategy)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_g_tL1wResCtrl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wBchProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_amt.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_g_tL1wAmtProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCs0ProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wHspaProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFachProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wPageProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_dch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wDchProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o) (_L1w_SchedHsdpaFachActive)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wGapProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o) (_g_tL1wHsdpaProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o) (_L1w_SchedHspaEraInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFmoProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFSProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o) (_L1w_MathFloatAdd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o) (_L1w_DevHsupaCalcSubFrmBitmap)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o) (_L1w_DevPcHspaReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o) (_L1w_DevTxRaInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRmReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_L1w_DevHsdpaSendPcTtiInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_bL1wHsdpaDmaBusy)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o) (_L1w_DevPcRachReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_g_atL1wHsupaDlCmPattern)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o) (_g_tRegRtxDtrReg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o) (_g_uRegBchTxdMode)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_L1w_DrvDmaReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o) (_L1w_SchedHsdpaPchCfgPSCmd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_g_L1LteAPriTaskPid)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_NVInit)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_etmtlog_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_LTE_TPU_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_ecsi_CSIAThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_edls_PDschIsr)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o) (_wPchUseSibFlag)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_erfc_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_wCNT)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_epbch_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_zPHY_edls_tDlsCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_atCqiCommonInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_t_zPHY_Dls2UlsDciValue)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_ptRxp_Ops)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_t_zPHY_eula_CtrlBlock)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_tL1lLpCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_zPHY_erfc_SupSampleRateSet)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_ZPHY_ecsrm_tMeasState)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o) (_g_zPHY_ecsrm_bHalfFrame)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_UL_CSI_CombThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_Tx2Rx2_NL2_PMICalc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o) (_g_tRxpCirCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_aswOutdata)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_SumLOGNoSqrt_RICalc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o) (_g_tLteA1DlaRxCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_EDFE_SYSTEM_INFO)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eula_Entry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_t_zPHY_DlaCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eula_ProInitial)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_Int_dwDFEIntType_agc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eulpc_GetConfigParas)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (_g_awL1lEngTempBuffer)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o) (_zEasn1p_DcT_zEurrc_PCCH_Message)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_zPHY_edla_PdcchBlindDetectProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_CqiSinglePort_TX1_RX1_NL1)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_g_bIsRarNewTrans)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_ACP405_AFC_DIFF)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_DevDlsDecodeDciF1A)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_gadwCsiRsPosCalculated)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_zPHY_eulpc_PucchPowCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_ac_zPHY_edls_TddSubframeType)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_DrvDdtrResetCfg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o) (_zPHY_DrvTopIntAbleBitSet)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_L1L_TpuDrvReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_g_tzPHY_eulpc_At2UlPc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o) (_g_zPHY_tLpcPwrDomainState)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_eltx_SoftReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_zPHY_ecsrm_MeasHwReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_adw_Drv_Rx_FixFirCoeff_16QAM)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_elutr_SoftReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o) (_L1e_DrvRxMimoReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_L1e_DrvMimoCaRstCfg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_zPHY_erfc_atCurrentSFConfig)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o) (_g_atzPHY_erfc_atRFABBMainSyncEvent)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_zPHY_erfc_cTddOrFddSel)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_cAGCCalMode)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o) (_g_CsrGapInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_erapc_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_g_awAgcNoBalance)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_g_wSibPrintCtrlCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o) (_g_L1e_tDlRfcCfgInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_g_L1e_ConnIntraRptCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_zPHY_emc_ProPhyStateCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_g_zPHY_erapc_tCtrlBlock)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_zPHY_ecsrc_SatAdd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_g_zPHY_ecsrc_tMulmInactiveTimeInd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_g_RxOpenPara)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o) (_EventHandler)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_L1e_SchedMbmsInit)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_g_zPHY_emc_bDrxActvieFlag)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_zPHY_emc_ProRadioLink_SetFIUpdateInd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_gtAmtCellSyncProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_g_sbFixTaAutoAdjFlg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_tHandoverReq)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_g_wPreSyncInterval)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_zPHY_ecscMeas_LogMeasConfigReq)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_LogDlDlsDciDetInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_zPHY_ecsc_LogMibReqCellInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_zPHY_ecsm_LogMeasHwInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o) (_zPHY_ecsccs_LogRSStart)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_L1e_LogDlRxMbsfnCirInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_emulm_LogCsrSlaveStateChange)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o) (_L1e_logCmnMbmsMbsfnSubfListInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_L1e_csrs_LogSetFtErrorList)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o) (_zPHY_ecsm_LogBlackCell)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_zPHY_Float2Fixpoint)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_zPHY_SID)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_L1l_CmnAssert)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_zPHY_eula_PucchSrsRelease)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_adw_zPHY_Rx_NormalSfnTypeValue)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_at_zPHY_NxtHiQuadPosTab)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_wNotSyncAgcIntCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_zPHY_eulpc_SrsPowCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_euls_Entry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_aswTwf)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_g_tzPHY_ecsrs_FSPara)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o) (_zPHY_euls_ReleaseSPSMode)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetPssStartInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_g_ai_zPHY_Tdd_MiTab)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_eula_PuschAckProcess)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o) (_zPHY_eulpc_UlsRelativePuscchPowCtrlProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_wRxLog2Dagc0)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o) (_zEasn1p_per_dcOctStr)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_G_EULPC_RARTPCVAL)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetCfoStartInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_zPHY_edla_PcfichProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetNearValidTime)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o) (_g_atEcsrSearchPeakdatabase)
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+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fflush.o) (__zsim_fwrite)
+
+Allocating common symbols
+Common symbol size file
+
+_g_awSyncMsgBuff 0x2ee0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_tL1wDevDbHsdpaCfgReqB
+ 0x7c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_zPHY_edfe_wAgcEnEventFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_L1l_LpmCaliIdx 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_ThreadIntraCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_dwOffsetDelta 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_atDevBchAfcdb 0x7a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_dwL1lPreHookEntry
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_g_tTempDCOffsetComp
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_atL1wCellType 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_wLastBand 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+_g_tL1wDevDbUlDpchCfgReqA
+ 0x3d6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_atEcsrSearchPeakdatabase
+ 0xf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_tL1lCallStackInfo
+ 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+_g_eTxCalibrationStep
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+_g_tL1wCmCfnN0123Bitmap
+ 0x5a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_tL1wDevDbHsdpaCfgReqA
+ 0x7c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_awPSeqCellIDDiv30
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_zPHY_erfc_tempDac
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_dL1wDprICPSSFN 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+_g_zPHY_bDdtrWorkFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+_g_wAdrIcCellState 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+_g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+_g_awFHopSeq4SubBands
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_tRfRxOffsetCfgInfo
+ 0x5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_tTTIBundlingDB 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_adL1wTpuTaskID 0x1a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+_g_tLteAmtCellSyncPara
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_edfe_wRxLinDagc1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_tWUpaStdlogStatisitcInfo
+ 0xe T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+_g_tWcdmaUserNv 0xbec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+_g_dwTpcPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_tUEIdInfo 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+_g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_atL1RfSegInfo 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_EUL_SrsStatisticsInfo
+ 0x158 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_awL1wStandardMsgRpt
+ 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+_g_atL1wTpuRegRtVarEventInfo
+ 0x235 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+_g_zPHY_edfe_swAgcMeanPwr1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_swPrintProNoInt 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+_g_tL1wDevMeasInfo 0x3eb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+_g_tTimerCnt 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_zPHY_euls_tTpcCommands
+ 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_zPHY_emc_tCommonConfigReq
+ 0x96 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_CsContext 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_g_tzPHY_ecsrs_FSPara
+ 0xd91 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+_g_wRLMATQInFlg 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_erfc_TempStartRecordFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_awMbmsClusterNum
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+_gL1l_MissLogInfo 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_g_zPHY_ecsrm_wNextIntFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+_g_adw_zPHY_erfc_profile_DB
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+_g_sdRLMATQIn 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_emc_wSIDataBufSel
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_ecsrc_wPiPeriod
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_dwOffsetFlag 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_ThreadFreqScan 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_zPHY_edfe_dwScanFreqAgcCalFlag
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_tzPHY_eulpc_PowerCtrlBlock
+ 0x5f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+_g_zPHY_edfe_aswAgcMeanPwr_Samp0
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_SSC_CFLT_chip 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+_g_zPHY_ecsrc_tMulmFreqListConfig
+ 0x134 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_awFHopSeq3SubBands
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_tPcPrachConfigInfo
+ 0x5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+_g_tL1wMeasCellReq 0x2f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_dwSrsPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_wTest 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+_g_zPHY_ecsrc_tSearchMeasAgeThrold
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_atCqiCommonInfo 0x9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+_g_l1e_tDcxoFtErrorList
+ 0x60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_zsp_cmm_len 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+_g_zPHY_edfe_wNotSyncAGCDone
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_aw_RarMacPdu 0x1c1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+_g_EDL_PDSCH_INFO 0x136 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_edfe_wRfcSingleAnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_zPHY_edfe_wNotSyncAGCBegin
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_g_tL1wCtrlDb 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+_g_atEcsrPeakList 0x3c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+_tPcDataDb 0x48 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+_g_EUL_wRachIdx 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_L1l_MrtrBeforeWakup
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_at_zPHY_NxtHiQuadPosTab
+ 0x48 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+_g_tIQComp 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_atL1wRlsTrace 0x24 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_RxDataPn9Check 0x5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+_g_zPHY_ecsrc_tIratGapConfig
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_wIntTypeforPaging
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+_g_L1e_dwPbchEvtList
+ 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_dwCfgSsfn 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+_g_wTpuIntTypeforlpm
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_tUlaLtxParas 0x12b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_awL1wPrintMsgProcRpt
+ 0x80 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+_g_tSlaveSearchMeasAgeThrold
+ 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_gadwZeroCsiRsCollideInd
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_wAgcCntForFirstDC
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_zPHY_erfc_wMID2RXFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_awAgcGain0 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_s_tL1wDevHsupaInfo
+ 0x4e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+_g_sdRLMATQOut 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_L1LteAIsrTaskPid
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+_g_dwPucchPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_dwUlResidualBlerCount
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_L1e_dwSirEvtList
+ 0x78 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+_g_zPHY_emc_tMcCtrlParam
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_EUL_CqiHarqSimulStatisticsInfo
+ 0xb8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_gau_zPHY_Rx_CsiRsIdicator
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_zPHY_edfe_swMaxAGCMeanPwr1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_gReadBlockCnt 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_tL1wResCtrl 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_Connect_State_Inter_Freq_Flag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_g_awCqiPmiRiIndex 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+_g_slot1_nRBNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_zPHY_edfe_wAgcLog2Gain0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_PchBlerInfo_0 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_wAutoDeactiveTimer
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+_g_atBandWidthInfo 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+_g_adAperLastCqiPmiDataBuffer
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+_g_tHandoverCnf 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+_g_zPHY_ecsrs_dwTpuAdjTime
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_dwPrachPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
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+_g_zPHY_sdwRxAnt1OffsetValue
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+_gdwTmtFlowCount 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_emc_tReadSib1Req
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_ps2phy_chinfo 0x300 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_tzPHY_eulpc_PowerCtrlParas
+ 0x13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+_g_adwDebug 0xc8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_EUL_PrachStatisticsInfo
+ 0xd9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_dwCalibration_amp
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+_g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_emc_tRaMsgHoldFlag
+ 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_zPHY_edfe_wRxLog2Dagc0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_g_L1l_MrtrAfterSleep
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_gIramHookCnt 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+_g_DbgMibPerStat 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_zPHY_AMT_Frequency
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_Int_dwDFEIntType_agc
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+_g_tRtxPcPrachMessageInfo
+ 0x13 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+_gt_zPHY_Rx_CsiRsExistInd
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_L1e_wSiTimingNeibState
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+_g_atL1wDrvMeasResultInfo
+ 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+_g_tL1wPsCmConfigBuffer
+ 0x7e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_sdAtCtl_ApcOffsetTime
+ 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+_g_wL1lRemainLen 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_gRpMsgReadMutex 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_awL1eRxDrsAccNum
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+_g_zPHY_edfe_wAgcdBGain1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_L1e_tDlRfcCfgInfo
+ 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_L1eTempAdc 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_ecsrc_tMulmIratMeasConfig
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_wCsiWorkFlg 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+_g_L1e_tMibRfcBackUp
+ 0xb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_TpuCfgOver 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+_g_L1e_Csrc_bCellSearchPbch
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_tMprTest 0xcb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_dwUlHarqFailCount
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+INCSRAM 0x00000000 0x00008000
+//OLINCSRAM 0x00000000 0x00000000
+DNCSRAM 0x00010000 0x00007000
+OLDNSCRAM 0x00015400 0x00001c00
+HEAP_STACK 0x00017000 0x00001000
+IRAM 0x41000000 0x00008000
+IRAM1 0x00080800 0x00000600
+DDR 0x10000000 0x00180000
+L2_CODE_TCM_STA 0x30060000 0x00004000
+L2_CODE_TCM_DYN 0x30064000 0x00004000
+L2_DATA_TCM_STA 0x30068000 0x00004000
+L2_DATA_TCM_DYN 0x3006c000 0x00004000
+DMA_REG 0x00980000 0x00001000
+ICP_REG 0x0098101c 0x00000030
+ICP_REG_M0 0x009810f4 0x00000030
+ICU_REG 0x00400800 0x00001000
+UART_REG 0x00a00800 0x00001000
+SLOTBUF_LTE_REG 0x7e010140 0x00000008
+TOP_REG 0x7e080000 0x00000800
+TPU_REG 0x7e080800 0x00001800
+RFC_REG 0x7e082000 0x00002800
+//DFE_RX_REG 0x7e084000 0x00000400
+//DFE_TX_REG 0x7e084400 0x00000400
+CSR_REG 0x7e084800 0x00000a00
+MEAS_REG 0x7e085200 0x00000e00
+CSR_FULLSCAN_REG 0x7e086000 0x00000200
+BCH_REG 0x7e086200 0x00000600
+PSR_REG 0x7e086800 0x00000100
+TX_REG 0x7e087000 0x00000200
+UTR_REG 0x7e087600 0x00000200
+EUTR_REG 0x7e087c00 0x00000400
+//RAKE_REG 0x7e088000 0x00000000
+RX_REG1 0x7e088000 0x00000800
+RX_REG2 0x7e088800 0x00000800
+RX_REG3 0x7e089000 0x00000800
+RX_REG4 0x7e089800 0x00000800
+GDTR_REG 0x7e08a000 0x00002000
+EAGCH_REG 0x7e08c000 0x00000400
+ADR_REG 0x7e08c400 0x00000200
+IC_REG 0x7e08c600 0x00001a00
+HDTR_REG 0x7e08e000 0x00000400
+HSSCCH_REG 0x7e08e400 0x00000400
+PICH_REG 0x7e08e800 0x00000200
+SLOTBUF_REG 0x7e08f000 0x00000200
+HDTR_LESS_REG 0x7e08f400 0x00000c00
+CSR_RAM 0x7c080000 0x00000400
+MEAS_RAM 0x7c080400 0x00000200
+BCH_RAM 0x7c080600 0x00007a00
+PSR_DATA_RAM 0x7c088000 0x00000400
+TX_RAM0 0x7c08e000 0x00002000
+TX_RAM1 0x7c090000 0x00002000
+UTR_RAM 0x7c092000 0x00004000
+EUTR_RAM 0x7c096000 0x00002000
+RX_RAM1 0x7c09a000 0x00000140
+RX_RAM2 0x7c09a140 0x00000040
+RX_RAM3 0x7c09a180 0x00000040
+RX_RAM4 0x7c09a1c0 0x00000100
+RX_RAM5 0x7c09a240 0x000005c0
+RX_RAM6 0x7c09a800 0x00000400
+RX_RAM7 0x7c09ac00 0x00000020
+RX_RAM8 0x7c09ac20 0x000013e0
+RX_RAM9 0x7c09c000 0x00000800
+RX_RAM10 0x7c09c800 0x00001000
+RX_RAM15 0x7c09d800 0x00000100
+RX_RAM16 0x7c09d900 0x00000300
+RX_RAM17 0x7c09dc00 0x00000040
+RX_RAM18 0x7c09dc40 0x00000040
+RX_RAM19 0x7c09dc80 0x00000040
+RX_RAM20 0x7c09dcc0 0x00000040
+RX_RAM21 0x7c09dd00 0x00000040
+RX_RAM22 0x7c09dd40 0x00000040
+RX_RAM23 0x7c09dd80 0x00000040
+RX_RAM24 0x7c09ddc0 0x00000140
+RX_RAM25 0x7c09df00 0x00000020
+RX_RAM26 0x7c09df20 0x000020e0
+GDTR_RAM 0x7c0a0000 0x00000400
+ADR_RAM 0x7c0b0000 0x00010000
+HDTR_RAM 0x7c0c0000 0x00008000
+PIAI_RAM 0x7c0c8000 0x00000100
+SLOTBUF_RAM 0x7c0e0000 0x00008000
+SLEEP_REG 0x0009a300 0x00000040
+RFFE_REG 0x7c250000 0x00000208
+SPI_REG 0x7c250208 0x00000010
+TD_TOP_REG 0x7e100000 0x00000080
+TD_TPU_REG 0x7e100400 0x00000040
+TD_AFC_REG 0x7e100800 0x00000400
+TD_CSR_REG 0x7e100c00 0x00000400
+TD_DST_REG 0x7e101000 0x00000080
+TD_RX_REG 0x7e101400 0x00000200
+TD_GDTR_REG 0x7e101800 0x00000100
+TD_HDTR_REG 0x7e101c00 0x00000040
+TD_UTR_REG 0x7e102000 0x00000079
+TD_ULC_REG 0x7e102079 0x00000187
+TD_HSUPA_REG 0x7e102200 0x00000080
+TD_DM_RDB_REG 0x7e103000 0x00000010
+TD_RFC_REG 0x7e104000 0x00005000
+TD_TFCI_REG 0x7e103400 0x00000020
+TD_SLEEP_REG 0x0009a200 0x00000080
+TD_PSLPM_REG 0x0009a280 0x00000080
+TD_VITERBI_REG 0x7e103400 0x00000020
+TD_CSR_DPRAM_MEM 0x7c100400 0x00000800
+TD_DST_DPRAM_MEM 0x7c104000 0x00000400
+TD_DST_DPRAM_INTERF_MEM 0x7c104800 0x00000400
+TD_UL_DPRAM_MEM 0x7c108000 0x00000400
+TD_HSUPA_MEM 0x7c10a000 0x00002000
+TD_RX_DPRAM_MEM2 0x7c10c000 0x00001000
+TD_GDTR_DPRAM_MEM 0x7c114000 0x00004000
+//TD_GDTR_DPRAM_TEST_MEM 0x7c118000 0x00004000
+TD_HDTR_DPRAM_MEM 0x7c11c000 0x00004400
+DST_SLOT_BUF 0x7c122000 0x00008000
+*default* 0x00000000 0xffffffff
+RAKE_REG 0x00000000 0xffffffff
+
+Linker script and memory map
+
+START GROUP
+LOAD T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a
+LOAD T:/cp/phy/rtos/zcos/os_krn/libczspfft.a
+LOAD T:/cp/phy/rtos/zcos/os_krn/libzspcache.a
+LOAD T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a
+LOAD T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libm.a
+LOAD T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a
+LOAD T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a
+LOAD /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+END GROUP
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a
+ 0x10000000 . = 0x10000000
+
+.text 0x10000000 0xa7b05
+ 0x10000000 _stext = .
+ *(.ddr_vectors)
+ .ddr_vectors 0x10000000 0x8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ *(.text)
+ .text 0x10000008 0x83 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ 0x10000008 0x80 __start
+ 0x10000088 0x3 __finished
+ .text 0x1000008b 0xe3 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ 0x1000008b 0x2e _L1_DrvIcuIntStart
+ 0x100000b9 0x1b _L1_DrvIcuIntMask
+ 0x100000d4 0x1a _L1_DrvIcuIntUnMask
+ 0x100000ee 0x27 _ICU_ISR
+ 0x10000115 0x2 _L1_DrvIcuError
+ 0x10000117 0x57 _L1_DrvIcuInit
+ .text 0x1000016e 0xbe T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ 0x1000016e 0x5 _L1_DrvIntInit
+ 0x10000173 0x5 _L1_DrvIntMaskAll
+ 0x10000178 0x27 _L1_DrvIntMask
+ 0x1000019f 0x26 _L1_DrvIntUnMask
+ 0x100001c5 0x67 _L1_DrvInstallIsr
+ .text 0x1000022c 0x19a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ 0x1000022c 0xc8 _odo_create_process
+ 0x100002f4 0x72 _s_create_process
+ 0x10000366 0x60 _create_process
+ .text 0x100003c6 0x8d T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x100003c6 0x54 _odo_error
+ 0x1000041a 0x5 _error
+ 0x1000041f 0x5 _error2
+ 0x10000424 0x20 _odo_panic
+ 0x10000444 0x3 _odo_panic2
+ 0x10000447 0x9 _odo_panic_nonfatal
+ 0x10000450 0x3 _odo_panic_nonfatal2
+ .text 0x10000453 0x179 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x10000453 0x31 _creat_pcb
+ 0x10000484 0x8e _odo_init_os_stage2
+ 0x10000512 0x4d _creat_idlepcb
+ 0x1000055f 0x6d _odo_init_os
+ .text 0x100005cc 0xc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ 0x100005cc 0xc _main
+ .text 0x100005d8 0xf7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ 0x100005d8 0x21 _odo_process_entry
+ 0x100005f9 0x3f _odo_alloc_pcb
+ 0x10000638 0x20 _odo_init_process
+ 0x10000658 0x77 _odo_init_pcb
+ .text 0x100006cf 0xa4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ 0x100006cf 0xa4 _send
+ .text 0x10000773 0x26 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ 0x10000773 0x26 _start_zcos
+ .text 0x10000799 0xee T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ 0x10000799 0x1e _odo_go_search
+ 0x100007b7 0x6b _odo_do_swap
+ 0x10000822 0x2d _odo_wait
+ 0x1000084f 0x38 _odo_swap_if_necessary
+ .text 0x10000887 0x90 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ 0x10000887 0x90 _alloc
+ .text 0x10000917 0x94 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ 0x10000917 0x1b _update_mask_list
+ 0x10000932 0x8 _odo_arch_init_interrupts
+ 0x1000093a 0x5c _odo_arch_create_osint
+ 0x10000996 0x15 _odo_arch_init
+ .text 0x100009ab 0x16 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ 0x100009ab 0x16 _ZSP_DCacheUseDCFGRDescribe
+ .text 0x100009c1 0xa T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o)
+ 0x100009c1 0xa _ZSP_DCacheEnableNCSRAM
+ .text 0x100009cb 0x104 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x100009cb 0x5b _odo_config_init_pools
+ 0x10000a26 0x44 _odo_config_start_handler1
+ 0x10000a6a 0x65 _odo_config_start_handler2
+ .text 0x10000acf 0x23 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ 0x10000acf 0x5 _L1_TIMER0_ISR
+ 0x10000ad4 0x1e _L1_SysIdleTask
+ .text 0x10000af2 0x6e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ 0x10000af2 0x1b _BspTimerInit1
+ 0x10000b0d 0xd _BspTimerInit2
+ 0x10000b1a 0x1b _BspTimerGet
+ 0x10000b35 0x1c _BspTimerCallbackReg
+ 0x10000b51 0xf _Timer0_ISR
+ .text 0x10000b60 0xf5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ 0x10000b60 0x4d _L1_DrvTimer
+ 0x10000bad 0x6 _L1_DrvTimerStop
+ 0x10000bb3 0x42 _L1_DrvPhyTimer1Init
+ 0x10000bf5 0x1e _L1_DrvSwDelay
+ 0x10000c13 0x6 _L1_DrvGetTimeCnt
+ 0x10000c19 0x10 _L1_DrvCalcTimeElapse
+ 0x10000c29 0x10 _L1_DrvTimer0Init
+ 0x10000c39 0xf _L1_DrvTimer1Init
+ 0x10000c48 0x6 _TIMER0_INT
+ 0x10000c4e 0x7 _TIMER1_INT
+ .text 0x10000c55 0x2cc T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x10000c55 0x1a _L1_SysSendRamDumpIcp
+ 0x10000c6f 0x1e9 _ramdump_client_cmm_create_sde
+ 0x10000e58 0x36 _L1_SysErrHnd
+ 0x10000e8e 0x42 _RAMDUMP_ICP_ISR
+ 0x10000ed0 0x33 _L1_AllocHookDebug
+ 0x10000f03 0x1e _L1_FreeHookDebug
+ .text 0x10000f21 0x1ed T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x10000f21 0x90 _LoadStaticIDNCSRAM
+ 0x10000fb1 0xd _CpyDdrBetweenL2Tcm
+ 0x10000fbe 0x6c _FirstLoadL2Tcm
+ 0x1000102a 0x1 _DynamicLoadL2CodeTcm
+ 0x1000102b 0x4f _CopyBackL2TcmData
+ 0x1000107a 0x94 _UpdateL2TcmDynamic
+ .text 0x1000110e 0x215 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ 0x1000110e 0x105 _L1_InitMacro
+ 0x10001213 0x110 _L1_SysEntry
+ .text 0x10001323 0x63 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x10001323 0x1a __ASSERT
+ 0x1000133d 0x35 __AllocMsg
+ 0x10001372 0xb _ZSP_DelayChip
+ 0x1000137d 0x7 _ZSP_delay_clock
+ 0x10001384 0x2 _erfc_tpu_state
+ .text 0x10001386 0x132f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x10001386 0x11 _phy_memcpy
+ 0x10001397 0x1 _TD_WD_L1_Init
+ 0x10001398 0x22 _L1_RfcSscConfig
+ 0x100013ba 0xa _L1_RfcSscClkEnDisable
+ 0x100013c4 0x59 _L1_RfcSpiWriteSleep
+ 0x1000141d 0x59 _L1_RfcAbbSpiWriteSleep
+ 0x10001476 0x8 _L1_RfcGetSpiRdDataSleep
+ 0x1000147e 0x10 _L1_RfcMipiRffeWrite
+ 0x1000148e 0x44 _L1_RfcMipiInit
+ 0x100014d2 0x16 _L1_RfcDcxoTempDacInit
+ 0x100014e8 0x1b _L1_RfcDcxoTempDacBSearch
+ 0x10001503 0x36 _L1_RfcDcxoGetTempFromDac
+ 0x10001539 0x30 _L1_RfcDcxoGetTempDegree
+ 0x10001569 0x1a _L1_Rf220TxOff
+ 0x10001583 0x1a _L1_Rf220TxOn
+ 0x1000159d 0x12 _L1_Rf220A1IsoOn
+ 0x100015af 0x12 _L1_Rf220A1IsoOff
+ 0x100015c1 0x17 _L1_Abb128TxOff
+ 0x100015d8 0x18 _L1_Abb128TxOn
+ 0x100015f0 0x1 _L1_Rf220GsmWakeUpOn
+ 0x100015f1 0x1 _L1_Rf220GsmWakeUpOff
+ 0x100015f2 0x8 _L1_Abb128WakeUpOff
+ 0x100015fa 0x9 _L1_Abb128WakeUpOn
+ 0x10001603 0x12 _L1_Abb128ResetOff
+ 0x10001615 0x30 _L1_Abb128ResetOn
+ 0x10001645 0x8 _L1_AbbIsoEnOff
+ 0x1000164d 0x9 _L1_AbbIsoEnOn
+ 0x10001656 0x1b9 _L1_Abb128DRXFilterCnfLTE20
+ 0x1000180f 0x1b4 _L1_Abb128DRXFilterCnfLTE15
+ 0x100019c3 0x1b4 _L1_Abb128DRXFilterCnfLTE10
+ 0x10001b77 0x1b4 _L1_Abb128DRXFilterCnfLTE5
+ 0x10001d2b 0x1c2 _L1_Abb128DRXFilterCnfLTE3
+ 0x10001eed 0x1a2 _L1_Abb128DRXFilterCnfLTE1_4
+ 0x1000208f 0x197 _L1_Abb128DRXFilterCnfWcdma
+ 0x10002226 0x1ad _L1_Abb128DRXFilterCnfTdscdma
+ 0x100023d3 0xac _L1_Abb128DRXFilterCnfHpf
+ 0x1000247f 0x20 _L1_RfGpioPinMuxReCfg
+ 0x1000249f 0x8 _L1_Rfc_IratShare_Lock
+ 0x100024a7 0xa _L1_Rfc_IratShare_UnLock
+ 0x100024b1 0x13 _L1_AbbClkEnCtrl
+ 0x100024c4 0xbc _L1_RfcIdleToSleepForLp
+ 0x10002580 0x135 _L1_RfcSleepToIdleForLp
+ .text 0x100026b5 0xa0 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x100026b5 0x75 _w_assert
+ 0x1000272a 0x15 _delay_ms
+ 0x1000273f 0x16 _delay_10us
+ .text 0x10002755 0x9cb T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x10002755 0x25 _L1_InitComAtNv
+ 0x1000277a 0x79 _L1_MmcPrioLteReset
+ 0x100027f3 0x74 _L1_MmcPrioLteMaster
+ 0x10002867 0x79 _L1_MmcPrioLteSlave
+ 0x100028e0 0x5 _L1_MmcPrioLteSlaveInFsPostPro
+ 0x100028e5 0x5 _L1_MmcPrioLteSlaveOutFsPostPro
+ 0x100028ea 0x17 _L1_MmcPrioLteEIcp
+ 0x10002901 0x17 _L1_MmcPrioLteEIcpRestore
+ 0x10002918 0x5 _L1_MmcPrioLteSleep
+ 0x1000291d 0x5 _L1_MmcPrioLteWakeup
+ 0x10002922 0x49 _L1_MmcPrioWReset
+ 0x1000296b 0x49 _L1_MmcPrioWMaster
+ 0x100029b4 0x49 _L1_MmcPrioWSlave
+ 0x100029fd 0x5 _L1_MmcPrioWSleep
+ 0x10002a02 0x5 _L1_MmcPrioWWakeup
+ 0x10002a07 0x7 _L1_MmcSetResetPrio
+ 0x10002a0e 0x2f _L1_MmcGetLteStamp
+ 0x10002a3d 0x34 _L1_MmcGetWStamp
+ 0x10002a71 0x34 _L1_MmcGetTdsStamp
+ 0x10002aa5 0x39 _L1_MmcGetGsmStamp
+ 0x10002ade 0x20 _L1_MmcTimeTransLte2Ms
+ 0x10002afe 0x2b _L1_MmcTimeTransW2Ms
+ 0x10002b29 0x2a _L1_MmcTimeTransTds2Ms
+ 0x10002b53 0x28 _L1_MmcTimeTransGsm2Ms
+ 0x10002b7b 0x1d _L1_MmcTimeTransMs2Lte
+ 0x10002b98 0x20 _L1_MmcTimeTransMs2W
+ 0x10002bb8 0x1f _L1_MmcTimeTransMs2Tds
+ 0x10002bd7 0x32 _L1_MmcTimeTransMs2Gsm
+ 0x10002c09 0x17 _L1_MmcTimeTransLte2W
+ 0x10002c20 0x17 _L1_MmcTimeTransLte2Tds
+ 0x10002c37 0x17 _L1_MmcTimeTransLte2Gsm
+ 0x10002c4e 0x17 _L1_MmcTimeTransW2Lte
+ 0x10002c65 0x17 _L1_MmcTimeTransW2Gsm
+ 0x10002c7c 0x17 _L1_MmcTimeTransTds2Lte
+ 0x10002c93 0x17 _L1_MmcTimeTransTds2Gsm
+ 0x10002caa 0x17 _L1_MmcTimeTransGsm2Lte
+ 0x10002cc1 0x17 _L1_MmcTimeTransGsm2W
+ 0x10002cd8 0x17 _L1_MmcTimeTransGsm2Tds
+ 0x10002cef 0x4e _L1_MmcPosTransLte2Gsm
+ 0x10002d3d 0x49 _L1_MmcPosTransGsm2Lte
+ 0x10002d86 0x47 _L1_MmcPosTransW2Gsm
+ 0x10002dcd 0x38 _L1_MmcPosTransGsm2W
+ 0x10002e05 0x47 _L1_MmcPosTransTds2Gsm
+ 0x10002e4c 0x31 _L1_MmcPosTransGsm2Tds
+ 0x10002e7d 0x34 _L1_MmcLteTimePlus
+ 0x10002eb1 0x27 _L1_MmcWTimePlus
+ 0x10002ed8 0x27 _L1_MmcTdsTimePlus
+ 0x10002eff 0x33 _L1_MmcGsmTimePlus
+ 0x10002f32 0x6e _L1_MmcLteTimeMinus
+ 0x10002fa0 0x5c _L1_MmcWTimeMinus
+ 0x10002ffc 0x53 _L1_MmcTdsTimeMinus
+ 0x1000304f 0xa3 _L1_MmcGsmTimeMinus
+ 0x100030f2 0x2e _L1_MMcGsmPosMove
+ .text 0x10003120 0x24b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ 0x10003120 0x25 _L1_DrvL2CachePrefetchCfg
+ 0x10003145 0xa _L1_DrvL2CachePowerModeCfg
+ 0x1000314f 0x41 _L1_DrvL2CacheGetInfo
+ 0x10003190 0x4d _L1_DrvL2CacheEnable
+ 0x100031dd 0x18 _L1_DrvL2CacheDisable
+ 0x100031f5 0x11 _L1_DrvL2CacheSync
+ 0x10003206 0x27 _L1_DrvL2CacheClean
+ 0x1000322d 0x27 _L1_DrvL2CacheInv
+ 0x10003254 0x27 _L1_DrvL2CacheCleanInv
+ 0x1000327b 0x1d _L1_DrvL2CacheCleanByWay
+ 0x10003298 0x1d _L1_DrvL2CacheInvByWay
+ 0x100032b5 0x1d _L1_DrvL2CacheCleanInvByWay
+ 0x100032d2 0xd _L1_DrvL2CacheIntEnable
+ 0x100032df 0xe _L1_DrvL2CacheIntDisable
+ 0x100032ed 0xa _L1_DrvL2CacheGetMaskIntStatus
+ 0x100032f7 0xa _L1_DrvL2CacheClearIntStatus
+ 0x10003301 0x1e _L1_DrvL2CacheCfgEventCounter
+ 0x1000331f 0xa _L1_DrvL2CacheEventCounterEnable
+ 0x10003329 0x9 _L1_DrvL2CacheEventCounterDisable
+ 0x10003332 0x13 _L1_DrvL2CacheGetEventCounterVal
+ 0x10003345 0x1a _L1_DrvL2CacheTcmEnable
+ 0x1000335f 0xc _L1_DrvL2CacheTcmDisable
+ .text 0x1000336b 0x98 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ 0x1000336b 0x1b _L1_DrvCacheDisable
+ 0x10003386 0x3b _L1_DrvCacheEnable
+ 0x100033c1 0x24 _L1_DrvCacheWb
+ 0x100033e5 0x1e _L1_DrvCacheWbAll
+ .text 0x10003403 0x179 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ 0x10003403 0xb _L1_DrvDmaReset
+ 0x1000340e 0x15 _L1_DrvDmaCfg
+ 0x10003423 0x41 _L1_DrvDmaClear
+ 0x10003464 0x2 _L1_DrvDmaError
+ 0x10003466 0x41 _L1_DrvDmaInit
+ 0x100034a7 0x21 _L1_DrvDmaStart
+ 0x100034c8 0x26 _L1_DrvDmaIsr
+ 0x100034ee 0x4e _L1_DrvDmaCfgChParam
+ 0x1000353c 0x33 _L1_DrvDmaCfgLLI
+ 0x1000356f 0xd _L1_DrvDmaTcEnd
+ .text 0x1000357c 0x101a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x1000357c 0x1 _RPMSG_ERR
+ 0x1000357d 0x3e _rpMsg_MaskInt
+ 0x100035bb 0x40 _rpMsg_UnmaskInt
+ 0x100035fb 0x39 _rpMsg_GetIntState
+ 0x10003634 0x38 _rpMsg_ClearState
+ 0x1000366c 0xd2 _rpMsg_SetInt
+ 0x1000373e 0x184 _rpMsg_DispatchMsg
+ 0x100038c2 0xcc _zDrvRpMsg_CreateChannel
+ 0x1000398e 0x32 _zDrvRpMsg_RegCallBack
+ 0x100039c0 0xfa _zDrvRpMsg_Write
+ 0x10003aba 0x107 _zDrvRpMsg_WriteWithId
+ 0x10003bc1 0xd7 _zDrvRpMsg_WriteLockIrq
+ 0x10003c98 0x146 _zDrvRpMsg_Read
+ 0x10003dde 0x146 _zDrvRpMsg_ReadWithId
+ 0x10003f24 0xe1 _zDrvRpMsg_ReadWithIdLockIrq
+ 0x10004005 0xd8 _zDrvRpMsg_ReadLockIrq
+ 0x100040dd 0x23 _zDrvRpMsg_ChIsEmpty
+ 0x10004100 0x23 _zDrvRpMsg_WriteChIsEmpty
+ 0x10004123 0xd4 _zDrvRpMsg_CreateBlock
+ 0x100041f7 0xe _zDrvRpMsg_GetWriteAddrCnt
+ 0x10004205 0xa2 _zDrvRpMsg_GetWriteAddr
+ 0x100042a7 0xc8 _zDrvRpMsg_WriteUpdate
+ 0x1000436f 0xc4 _zDrvRpMsg_GetReadAddr
+ 0x10004433 0xbf _zDrvRpMsg_ReadUpdate
+ 0x100044f2 0xa4 _zDrvRpMsg_Initiate
+ .text 0x10004596 0x96 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ 0x10004596 0x1 _L1_Comm_SocTopInit
+ 0x10004597 0x1 _delay_1us
+ 0x10004598 0x26 _L1_LpmLatchInit
+ 0x100045be 0x8 _L1_RmHarqRamWcdmaCfg
+ 0x100045c6 0x8 _L1_RmHarqRamTdCfg
+ 0x100045ce 0x9 _L1_RmHarqRam3GRel
+ 0x100045d7 0x9 _L1e_RmHarqRamLteModeClkSelCfg
+ 0x100045e0 0xd _L1_TurboModeSel
+ 0x100045ed 0x1f _L1_WdTdIpSel
+ 0x1000460c 0x1f _L1_WdTdShareRamModeSel
+ 0x1000462b 0x1 _L1_PhyLteModemSel
+ .text 0x1000462c 0x878 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x1000464a 0x6e _L1_AtCmdCtrlLpcFuncs
+ 0x100046b8 0x2c _L1_InitSleepMacro
+ 0x100046e4 0x18 _L1_PhyModeExistInit
+ 0x100046fc 0x46 _L1_SocNoPsmInit
+ 0x10004742 0x14b _L1_SocLpcInit
+ 0x1000488d 0x71 _L1_PcuLpmCalibrationCfg
+ 0x100048fe 0x9 _L1_SocGetApCpuFreq
+ 0x10004907 0x9 _L1_SocGetPsCpuFreq
+ 0x10004910 0x10 _L1_SocGetCurCpuFreq
+ 0x10004920 0x10 _L1_SocGetCurAxiFreq
+ 0x10004930 0x2 _L1_SocGetCurDdrFreq
+ 0x10004932 0x2 _L1_SocDdrDfs
+ 0x10004934 0x17 _L1_SocResCpuExpUpdate
+ 0x1000494b 0x18 _L1_SocResAxiExpUpdate
+ 0x10004963 0x18 _L1_SocResVolExpUpdate
+ 0x1000497b 0x18 _L1_SocResDdrExpUpdate
+ 0x10004993 0x4e _L1_SocResGetExpCurrent
+ 0x100049e1 0xec _L1_SocAdjust
+ 0x10004acd 0x3d7 _L1_LpcTask
+ .text 0x10004ea4 0x20c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x10004ea4 0x10 _L1_LpcDrvChangeCpuPhyFreq
+ 0x10004eb4 0x12 _L1_SetPhyDeepSleepTime2Pcu
+ 0x10004ec6 0x1 _L1_DrvPcu2TpuClkCfg
+ 0x10004ec7 0x1 _L1_DrvPcuCalibrationCfg
+ 0x10004ec8 0x8 _L1_TdlpmClkEn
+ 0x10004ed0 0xa _L1_PhyAxiClkEn
+ 0x10004eda 0x4b _L1_RmModClkEn1
+ 0x10004f25 0x1 _L1_MatrixAxiAutoEn
+ 0x10004f26 0x3d _L1_CpuPhyWakeIntClear
+ 0x10004f63 0x1 _L1_DrvLpcIram1PhyInit
+ 0x10004f64 0x50 _L1_DrvLpcIramFlgInit
+ 0x10004fb4 0x8 _L1_SetPhyDeepSleepFlag
+ 0x10004fbc 0x13 _L1_L2CacheConfigLpMode
+ 0x10004fcf 0x9 _L1_PcuPhyPoweroffIntStart
+ 0x10004fd8 0x9 _L1_CrmSetZspAxiClkEn
+ 0x10004fe1 0x1 _L1_CopyRestartData
+ 0x10004fe2 0x1 _L1_PhyLowPowerInit
+ 0x10004fe3 0x8 _L1_DrvLpcRegLock
+ 0x10004feb 0xa _L1_DrvLpcRegUnLock
+ 0x10004ff5 0x8 _L1_DrvLpcSoftHwLock
+ 0x10004ffd 0xc _L1_DrvLpcSoftHwUnLock
+ 0x10005009 0x4e _L1_DrvLpcSpinSoftLockPsm
+ 0x10005057 0x4a _L1_DrvLpcSpinSoftUnlockPsm
+ 0x100050a1 0xf _L1_DrvLpcSpinSoftlockInit
+ .text 0x100050b0 0x2a4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x100050b2 0x37 _L1_IratSetMode
+ 0x100050e9 0x14 _L1_IratGetMode
+ 0x100050fd 0x13 _L1_IratRfProPcuShareDevInit
+ 0x10005110 0x11 _L1_IratRfProPcuShareDev
+ 0x10005121 0x1f _L1_IratRfIdleToSleep
+ 0x10005140 0x1d _L1_IratRfSleepToIdle
+ 0x1000515d 0x14 _L1_IratRfCfgFlgSet
+ 0x10005171 0x13 _L1_IratIsTdRfCfgNeed
+ 0x10005184 0x13 _L1_IratIsWdRfCfgNeed
+ 0x10005197 0x5b _L1_IratSetSlaveShortGapFlg
+ 0x100051f2 0xd _L1_IratSetGapRptIramFlg
+ 0x100051ff 0xf _L1_IratIsSharePwr
+ 0x1000520e 0x3a _L1_IratPwrCtrl
+ 0x10005248 0x5d _L1_IratLpcInit
+ 0x100052a5 0x2e _L1_IratLpcSleep
+ 0x100052d3 0xc _L1_IratLpcWakeup
+ 0x100052df 0x2b _L1_IratLpcSetCalibrationFlag
+ 0x1000530a 0x1d _L1_IratLpcGetCalibrationFlag
+ 0x10005327 0x18 _L1_IratLpcSetCalibrationTime
+ 0x1000533f 0x15 _L1_IratLpcGetCalibrationTime
+ .text 0x10005354 0x466 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x10005354 0x1 _L1_SysModClkSelInit
+ 0x10005355 0x10 _L1_PhyTimerClkDis
+ 0x10005365 0x11 _L1_Dma1ClkEn
+ 0x10005376 0x65 _L1_MatrixModemClkEn
+ 0x100053db 0xa _L1_DrvPhyCoreAcsCfg
+ 0x100053e5 0x1 _L1_DrvPwrTopRegCtrl
+ 0x100053e6 0x12 _L1_DrvPwrDomainIsOn
+ 0x100053f8 0x61 _L1_DrvPwrCtrl
+ 0x10005459 0x30 _L1_DrvLtePwr1Ctrl
+ 0x10005489 0x4 _L1_Drv3GSyncPwrCtrl
+ 0x1000548d 0x4 _L1_Drv3GDpaPwrCtrl
+ 0x10005491 0x1b _L1_DrvDpll245mClkCtrl
+ 0x100054ac 0x67 _L1_Dpll1Cfg
+ 0x10005513 0x74 _L1_Dpll2Cfg
+ 0x10005587 0x3c _L1_DpllCfg
+ 0x100055c3 0xad _L1_CpuPhyWakeIntInit
+ 0x10005670 0x2e _L1_PcuConfigPhyLpMode
+ 0x1000569e 0x19 _L1_PhyMgClkGating
+ 0x100056b7 0xd _L1_CpuPhyLpSvtAddr
+ 0x100056c4 0x36 _L1_DrvSetSharePwrUsedFlg
+ 0x100056fa 0x19 _L1_DrvGetSharePwrIsUsed
+ 0x10005713 0x18 _L1_DrvPhyComPwrUsedFlgInit
+ 0x1000572b 0x45 _L1_DrvSharePwrCtrl
+ 0x10005770 0x3f _L1_DrvLpcPwrCtrl
+ 0x100057af 0xb _L1_DrvLpcDdrPort1Ctrl
+ .text 0x100057ba 0x34f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ 0x100057ba 0x40 _L1_PhyDmaCfg
+ 0x100057fa 0xa _L1_SaveMgCrm
+ 0x10005804 0xa _L1_RestoreMgCrm
+ 0x1000580e 0xa _L1_SaveL2tcmByDma
+ 0x10005818 0xa _L1_RestoreL2tcmByDma
+ 0x10005822 0x33 _L1_SaveIcu
+ 0x10005855 0x33 _L1_RestoreIcu
+ 0x10005888 0x6 _L1_SaveInt
+ 0x1000588e 0x8 _L1_RestoreInt
+ 0x10005896 0x3 _L1_SaveSmodeReg
+ 0x10005899 0x3 _L1_RestoreSmodeReg
+ 0x1000589c 0x7d _L1_SavePl310
+ 0x10005919 0x87 _L1_RestorePl310
+ 0x100059a0 0x9f _L1_PhyPowerOffSaveContext
+ 0x10005a3f 0xca _L1_PhyPowerOffRestoreContext
+ .text 0x10005b09 0xf5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ 0x10005b09 0x25 _L1_DrvWDTFeedDog
+ 0x10005b2e 0x4c _L1_DrvWDTInit
+ 0x10005b7a 0x50 _L1_DrvM02PhyIcpIsr
+ 0x10005bca 0x34 _L1_WdtTask
+ .text 0x10005bfe 0x66 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ 0x10005bfe 0x1a _serial_puts
+ 0x10005c18 0x4c _printk
+ .text 0x10005c64 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ 0x10005c6a 0x14 _iomemcpy_32
+ .text 0x10005c7e 0x2a1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ 0x10005c7e 0x81 _L1_DrvL1CacheInit
+ 0x10005cff 0x46 _ZSP_DCacheSetExtraNonCacheableRegion_Ext
+ 0x10005d45 0x1b _ZSP_DCacheExtraNonCacheableEnable_Ext
+ 0x10005d60 0x1b _ZSP_DCacheExtraNonCacheableDisable_Ext
+ 0x10005d7b 0x35 _ZSP_DCacheExtraBufferableAndNonCacheableEnable_Ext
+ 0x10005db0 0x35 _ZSP_DCacheExtraBufferableAndNonCacheableDisable_Ext
+ 0x10005de5 0x13 _L1Cache_set_ramclk_gate
+ 0x10005df8 0xd _L1Cache_set_superfetch
+ 0x10005e05 0x15 _L1_DrvL1CacheEnableI
+ 0x10005e1a 0x15 _L1_DrvL1CacheEnableD
+ 0x10005e2f 0x8 _L1_DrvL1CacheEnable
+ 0x10005e37 0xf _L1_DrvL1CacheDisableI
+ 0x10005e46 0x26 _L1_DrvL1CacheDisableD
+ 0x10005e6c 0x8 _L1_DrvL1CacheDisable
+ 0x10005e74 0x21 _L1_DrvL1CacheCleanD
+ 0x10005e95 0x21 _L1_DrvL1CacheFlushD
+ 0x10005eb6 0x21 _L1_DrvL1CacheFlushI
+ 0x10005ed7 0x2d _L1_DrvL1CacheFlush
+ 0x10005f04 0x1b _L1_DrvL1CacheSetWT
+ .text 0x10005f1f 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ 0x10005f1f 0x17 _ZSP_ICacheDisableAllWays
+ .text 0x10005f36 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ 0x10005f36 0x17 _ZSP_ICacheEnable
+ .text 0x10005f4d 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ 0x10005f4d 0x16 _ZSP_ICacheEnableAllWays
+ .text 0x10005f63 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ 0x10005f63 0x25 _ZSP_ICacheFlush
+ .text 0x10005f88 0x36 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ 0x10005f88 0x36 _ZSP_ICacheLoadNCSRAM
+ .text 0x10005fbe 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ 0x10005fbe 0x16 _ZSP_ICacheUseICFGRDescribe
+ .text 0x10005fd4 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ 0x10005fd4 0x12 _ZSP_ICacheNonCacheableDisable
+ .text 0x10005fe6 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ 0x10005fe6 0x17 _ZSP_DCacheDisableAllWays
+ .text 0x10005ffd 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ 0x10005ffd 0x16 _ZSP_DCacheEnableAllWays
+ .text 0x10006013 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ 0x10006013 0x25 _ZSP_DCacheFlush
+ .text 0x10006038 0x22 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ 0x10006038 0x22 _ZSP_DCacheLoadNCSRAM
+ .text 0x1000605a 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ 0x1000605a 0x25 _ZSP_DCacheClean
+ .text 0x1000607f 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ 0x1000607f 0x15 _ZSP_DCacheSetWriteThruRegion
+ .text 0x10006094 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ 0x10006094 0x12 _ZSP_DCacheWriteAllocateEnable
+ .text 0x100060a6 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ 0x100060a6 0x12 _ZSP_DCacheWriteThruEnable
+ .text 0x100060b8 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ 0x100060b8 0x12 _ZSP_DCacheWriteThruDisable
+ .text 0x100060ca 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ 0x100060ca 0x12 _ZSP_DCacheNonCacheableEnable
+ .text 0x100060dc 0x13 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ 0x100060dc 0x13 _ZSP_DCacheExtraNonCacheableEnable
+ .text 0x100060ef 0x142 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x100060ef 0x54 _L1w_TaskPrioEng
+ 0x10006143 0xee _L1w_ModemDrvInit
+ .text 0x10006231 0x8e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x10006231 0x46 _L1w_AtNvInit
+ 0x10006277 0x48 _L1w_NvDataInit
+ .text 0x100062bf 0x13d5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ 0x100062bf 0x2e _L1w_DevBchBchSchedReq
+ 0x100062ed 0x2c _L1w_DevBchAfcSupplyReq
+ 0x10006319 0x26 _L1w_DevBchAfcLockCnf
+ 0x1000633f 0x2e _L1w_DevBchIntInd
+ 0x1000636d 0x3f _L1w_BchTask
+ 0x100063ac 0x45 _L1w_DevBchTimeDecrease
+ 0x100063f1 0xa _L1w_DevBchClearAfcInfo
+ 0x100063fb 0x1d _L1w_DevBchPiSymbol2Float
+ 0x10006418 0x53 _L1w_DevBchPiReset
+ 0x1000646b 0x3e _L1w_DevBchReset
+ 0x100064a9 0x35 _L1w_DevBchInit
+ 0x100064de 0x1f _L1w_DevBchTpuIntHandle
+ 0x100064fd 0x82 _L1w_DevBchPichSched
+ 0x1000657f 0x222 _L1w_DevBchPichRxCfg
+ 0x100067a1 0x97 _L1w_DevBchBchSched
+ 0x10006838 0x1b4 _L1w_DevBchBchRxCfg
+ 0x100069ec 0xa8 _L1w_DevBchAfcSupply
+ 0x10006a94 0xca _L1w_DevBchCpichRxCfg
+ 0x10006b5e 0x23 _L1w_DevBchAfcLockHandle
+ 0x10006b81 0x57 _L1w_DevBchPichIntHandle
+ 0x10006bd8 0xf8 _L1w_DevBchBchIntHandle
+ 0x10006cd0 0x80 _L1w_DevBchCpichIntHandle
+ 0x10006d50 0x24 _L1w_DevBchTimeConflict
+ 0x10006d74 0x56 _L1w_DevBchCalcFingerAdj
+ 0x10006dca 0x32 _L1w_DevBchCalcFingerBound
+ 0x10006dfc 0x6c _L1w_DevBchAddTpuEvent
+ 0x10006e68 0x7e _L1w_DevBchBchAfcProc
+ 0x10006ee6 0x54 _L1w_DevBchPichAfcProc
+ 0x10006f3a 0x14d _L1w_DevBchAdjustFinger
+ 0x10007087 0x2d _L1w_DevBchCpichIntMask
+ 0x100070b4 0x16 _L1w_DevBchClearAfcData
+ 0x100070ca 0xf _L1w_DevBchReadSfnResult
+ 0x100070d9 0x5c _L1w_DevBchFindBchRxCfgBuf
+ 0x10007135 0x5c _L1w_DevBchRtCfgTimeValid
+ 0x10007191 0x49 _L1w_DevBchPichIntPostProc
+ 0x100071da 0x15 _L1w_DevBchCalcFingerDist
+ 0x100071ef 0xc7 _L1w_DevBchSigProc
+ 0x100072b6 0x3a _L1w_DevBchCalcChipDist
+ 0x100072f0 0x25 _L1w_DevBchStopBchDecode
+ 0x10007315 0x7b _L1w_DevBchSetIQRotate
+ 0x10007390 0x26 _L1w_DevBchNCellAfcFeedback
+ 0x100073b6 0x60 _L1w_DevBchCaclRtSfnOffset
+ 0x10007416 0xcf _L1w_DevBchFingerManage
+ 0x100074e5 0x42 _L1w_DevBchFingerUpdate
+ 0x10007527 0x21 _L1w_DevBchStopBchDecodeReq
+ 0x10007548 0xe6 _L1w_DevBchPiaiAfcHandle
+ 0x1000762e 0x66 _L1w_DevBchFilterFinger
+ .text 0x10007694 0x2301 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x10007694 0x41 _L1w_DevMeasInit
+ 0x100076d5 0x41 _L1w_DevMeasReset
+ 0x10007716 0xd _L1w_DevMeasJudgeBufStateFull
+ 0x10007723 0xe _L1w_DevMeasJudgeBufState
+ 0x10007731 0x2cc _L1w_DevMeasConfigHw
+ 0x100079fd 0x40 _L1w_DevMeasCpichMeasCnf
+ 0x10007a3d 0x139 _L1w_DevMeasSideSupres
+ 0x10007b76 0x94 _L1w_DevMeasPathDetct
+ 0x10007c0a 0xd2 _L1w_DevMeasDeleteSttdDetctCell
+ 0x10007cdc 0xc1 _L1w_DevMeasSttdDetct
+ 0x10007d9d 0x4f _L1w_DevMeasCalcFingerPeakSum
+ 0x10007dec 0x5f _L1w_DevMeasCalcSearchWindowSum
+ 0x10007e4b 0x29 _L1w_DevMeasSortFirstFinger
+ 0x10007e74 0xd _L1w_DevMeasIsSearchWindowPath
+ 0x10007e81 0x25 _L1w_DevMeasSelNewWindow
+ 0x10007ea6 0xa8 _L1w_DevMeasSelWinFinInfo
+ 0x10007f4e 0xbe _L1w_DevMeasAdrWindowUpdate
+ 0x1000800c 0x104 _L1w_DevMeasTimeAdjust
+ 0x10008110 0x5f _L1w_DevMeasLOG10Cal
+ 0x1000816f 0x146 _L1w_DevMeasCalRssi
+ 0x100082b5 0x17a _L1w_DevMeasSaveCnfCellInfo
+ 0x1000842f 0x35 _L1w_DevMeasEcIoClaib
+ 0x10008464 0x104 _L1w_DevMeasGetRscpNew
+ 0x10008568 0xc0 _L1w_DevMeasGetRscp
+ 0x10008628 0x249 _L1w_DevMeasCalRscp1New
+ 0x10008871 0x2dd _L1w_DevMeasCalRscp1
+ 0x10008b4e 0xed _L1w_DevMeasPreSyncFingerCmp
+ 0x10008c3b 0xee _L1w_DevMeasAddPreSyncFingernew
+ 0x10008d29 0x14d _L1w_DevMeasAddPreSyncFinger
+ 0x10008e76 0x2f _L1w_DevMeasSetPreSyncInfo
+ 0x10008ea5 0x4 _L1w_DevMeasPreSyncHandler
+ 0x10008ea9 0x134 _L1w_DevMeasRscpHandler
+ 0x10008fdd 0x25 _L1w_DevMeasIntMissHandle
+ 0x10009002 0xb2 _L1w_DevMeasGetTpuEvtTim
+ 0x100090b4 0x50 _L1w_DevMeasSetAbnormalIntInfo
+ 0x10009104 0x1b6 _L1w_DevMeasReqProc
+ 0x100092ba 0x216 _L1w_DevMeasIntProc
+ 0x100094d0 0x62 _L1w_DevMeasTpuHandler
+ 0x10009532 0x48 _L1w_DevMeasIntInd
+ 0x1000957a 0x33 _L1w_DevMeasGetPreSyncInfo
+ 0x100095ad 0xf _L1w_DevMeasCheckWorkSt
+ 0x100095bc 0xe7 _L1w_DevMeasSetAgcStartTime
+ 0x100096a3 0x3e _L1w_DevMeasAgcTrans
+ 0x100096e1 0x2d _L1w_DevMeasSetAgc
+ 0x1000970e 0x18 _L1w_DevMeasOfflinedataStartTime
+ 0x10009726 0xc _L1w_DevMeasGetOfflinedataEndtTime
+ 0x10009732 0x2d _L1w_DevMeasOfflinedataSavedReq
+ 0x1000975f 0xe7 _L1w_DevMeasCfgOfflineData
+ 0x10009846 0x15 _L1w_DevMeasSaveAgcValue
+ 0x1000985b 0x16 _L1w_DevMeasSaveAgcStartTime
+ 0x10009871 0x63 _L1w_DevMeasJugeIsSaveAgcInfo
+ 0x100098d4 0xe _L1w_DevMeasClearOfflineDataInfo
+ 0x100098e2 0xb3 _L1w_MeasTask
+ .text 0x10009995 0x2bc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x10009995 0x8 _L1w_DevHsdpaActiveFlgGet
+ 0x1000999d 0x8 _L1w_DevHsdpaActiveFlgSet
+ 0x100099a5 0x8 _L1w_DevHsdpaHdtrUseTurboFlgGet
+ 0x100099ad 0x8 _L1w_DevHsdpaHdtrUseTurboFlgSet
+ 0x100099b5 0x8 _L1w_DevHsdpaGetAgcDownFlg
+ 0x100099bd 0x7 _L1w_DevHspaFachSetEdchActive
+ 0x100099c4 0x7 _L1w_DevHspaFachGetEdchActive
+ 0x100099cb 0x18 _L1w_DevHspaFachSubFrmInt
+ 0x100099e3 0x47 _L1w_DevHspaReset
+ 0x10009a2a 0x3e _L1w_DevHspaInit
+ 0x10009a68 0x18 _L1w_DevHspaCmnMsgProc
+ 0x10009a80 0x3c _L1w_DevHsupaFachMsgProc
+ 0x10009abc 0x4a _L1w_DevHsdpaFachMsgProc
+ 0x10009b06 0x5e _L1w_DevHsupaMsgProc
+ 0x10009b64 0x83 _L1w_DevHsdpaMsgProc
+ 0x10009be7 0x6a _L1w_HspaTask
+ .text 0x10009c51 0x951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ 0x10009c51 0x15 _L1w_DevRtxReset
+ 0x10009c66 0xf _L1w_DevRtxInit
+ 0x10009c75 0x44 _L1w_DevRtxInitCfgMsgHandle
+ 0x10009cb9 0x1 _L1w_DevRtxTxRfOperate
+ 0x10009cba 0x95 _L1w_DevRtxRxCfgTpuIntHandle
+ 0x10009d4f 0xce _L1w_DevRtxTpuIntUlRfHandle
+ 0x10009e1d 0xfa _L1w_DevRtxTpuIntHandle
+ 0x10009f17 0x24 _L1w_DevRtxResetInd
+ 0x10009f3b 0x24 _L1w_DevRtxInitInd
+ 0x10009f5f 0x21 _L1w_DevRtxTxPrachAbortReq
+ 0x10009f80 0x1 _L1w_DevRtxTxDpcchOfHspaCfgReq
+ 0x10009f81 0x48 _L1w_DevRtxUlRfCtrlSendReq
+ 0x10009fc9 0x2c _L1w_DevRtxRxFingerCfgReq
+ 0x10009ff5 0x32 _L1w_DevRtxRxPchCfgReq
+ 0x1000a027 0x21 _L1w_DevRtxRxAichRelReq
+ 0x1000a048 0x31 _L1w_DevRtxRxFachCfgReq
+ 0x1000a079 0x21 _L1w_DevRtxRxFachRelReq
+ 0x1000a09a 0x2f _L1w_DevRtxRxDlCmCfgReq
+ 0x1000a0c9 0x21 _L1w_DevRtxRxDlCmAbortReq
+ 0x1000a0ea 0x2d _L1w_DevRtxRxHsscchCfgReq
+ 0x1000a117 0x2f _L1w_DevRtxRxEagchCfgReq
+ 0x1000a146 0x21 _L1w_DevRtxRxEagchRelReq
+ 0x1000a167 0x35 _L1w_DevRtxRxDrxUpdateReq
+ 0x1000a19c 0x2a _L1w_DevRtxRxPlusCpichCfgReq
+ 0x1000a1c6 0x26 _L1w_DevRtxRxPlusCpichRelReq
+ 0x1000a1ec 0x2e _L1w_DevRtxRxRgHiCfgReq
+ 0x1000a21a 0x21 _L1w_DevRtxRxRgHiRelReq
+ 0x1000a23b 0x21 _L1w_DevRtxTxTimingAdjustInd
+ 0x1000a25c 0x19 _L1w_DevRtxRxTpcPilotIntInd
+ 0x1000a275 0x18 _L1w_DevRtxRxHwTpcPlIntInd
+ 0x1000a28d 0x2f _L1w_DevRtxRxHwPiAiIntInd
+ 0x1000a2bc 0x9 _L1w_DevRtxRxHwRakeIntInd
+ 0x1000a2c5 0x1a _L1w_DevRtxRxHwDtrIntInd
+ 0x1000a2df 0x22 _L1w_DevRtxRxPichIntInd
+ 0x1000a301 0x22 _L1w_DevRtxRxAichIntInd
+ 0x1000a323 0x102 _L1w_DevRtxRxTpcIntInd
+ 0x1000a425 0x3e _L1w_DevRtxRxTpcIntReq
+ 0x1000a463 0x66 _L1w_DevRtxRxPilotIntInd
+ 0x1000a4c9 0x21 _L1w_DevRtxRxTfciIntInd
+ 0x1000a4ea 0x22 _L1w_DevRtxRxTtiIntInd
+ 0x1000a50c 0x21 _L1w_DevRtxRxAgchFactorIntInd
+ 0x1000a52d 0x1 _L1w_DevRtxErrHandle
+ 0x1000a52e 0x6 _L1w_DevRtxInfoGet
+ 0x1000a534 0x6e _L1w_RtxTask
+ .text 0x1000a5a2 0x152c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x1000a5a2 0x49 _L1w_DevRfcAtSetDebug
+ 0x1000a5eb 0x5 _L1w_DevRfcGetAfcHz
+ 0x1000a5f0 0x1 _L1w_DevRfcRbdpRegCfg
+ 0x1000a5f1 0x6a _L1w_DevRfcReadMrtr
+ 0x1000a65b 0x2a _L1w_DevRfSleepInfo
+ 0x1000a685 0xc7 _L1w_DevRfcReset
+ 0x1000a74c 0x29 _L1w_DevRfcInit
+ 0x1000a775 0x8f _L1w_NvDataCheck
+ 0x1000a804 0x24 _L1w_DevRfcResetCnf
+ 0x1000a828 0x24 _L1w_DevRfcInitCnf
+ 0x1000a84c 0x53 _L1w_DevRfcSchedOpenReq
+ 0x1000a89f 0x23 _L1w_DevRestoreReq
+ 0x1000a8c2 0x2e _L1w_DevRfcIntInd
+ 0x1000a8f0 0x34 _L1w_DevRfcDpaInfoCtrl
+ 0x1000a924 0x30 _L1w_DevRfcAntExchange
+ 0x1000a954 0x2c _L1w_DevRfcAntSel
+ 0x1000a980 0x5e _L1w_DevRfcDiversityCtrl
+ 0x1000a9de 0x35 _L1w_DevRfcChgeInfoCtrlTx
+ 0x1000aa13 0x82 _L1w_DevRfcNotchHandle
+ 0x1000aa95 0xfd _L1w_DevRfcChgeInfoCtrlRx
+ 0x1000ab92 0x21 _L1W_DevRfcWaitForRfClose
+ 0x1000abb3 0xa6 _L1W_DevRfcSoltCtrlRfClose
+ 0x1000ac59 0x71 _L1w_DevRfcSlotCtrl
+ 0x1000acca 0xc6 _L1w_DevRfcFdtTrigCtrl
+ 0x1000ad90 0x56 _L1w_DevRfcFdtGetAgc
+ 0x1000ade6 0xbc _L1w_DevRfcFdtFreqCtrl
+ 0x1000aea2 0x67 _L1w_DevRfcFdtApcCwPaHighCtrl
+ 0x1000af09 0x6e _L1w_DevRfcFdtApcCwPaLowCtrl
+ 0x1000af77 0x67 _L1w_DevRfcFdtStartCtrl
+ 0x1000afde 0x91 _L1w_DevRfcNstTRXOpenCtrl
+ 0x1000b06f 0x42 _L1w_DevRfcNstTRXCloseCtrl
+ 0x1000b0b1 0x6a _L1w_DevRfcNstTRXFreqChge
+ 0x1000b11b 0x52 _L1w_DevRfcAmtCtrl
+ 0x1000b16d 0x46 _L1w_DevRfcAgcRefPowLogUpdate
+ 0x1000b1b3 0x29 _L1w_DevRfcIntTimeLogUpdate
+ 0x1000b1dc 0x19 _L1w_DevRfcMrtrConfLogUpdate
+ 0x1000b1f5 0x91 _L1w_DevRfcAgcRxStateLogUpdate
+ 0x1000b286 0x8 _L1w_DevRfcTempDacToIram
+ 0x1000b28e 0x31 _L1w_DevRfcIntLogUpdate
+ 0x1000b2bf 0x25 _L1w_DevRfcIntAgcDcCalc
+ 0x1000b2e4 0x2f _L1w_DevRfcIntNotchCfg
+ 0x1000b313 0x48 _L1w_DevRfc_RpiCfg
+ 0x1000b35b 0x18 _L1w_DevRfc_RpiSet
+ 0x1000b373 0x56 _L1w_DevRfc_RpiPwrCtrl
+ 0x1000b3c9 0x5e _L1w_DevRfcIntAgcDcSet
+ 0x1000b427 0x25 _L1w_DevRfcIntAfcSet
+ 0x1000b44c 0x63 _L1w_DevRfcRfRegReadCtrl
+ 0x1000b4af 0x2b _L1w_DevRfcSleepStatusSet
+ 0x1000b4da 0x6b _L1w_DevRfcIntProc
+ 0x1000b545 0x45 _L1w_DevRfcSetTxBandMaxPwr
+ 0x1000b58a 0x8f _L1w_DevRfcTxPowerSet
+ 0x1000b619 0x3f _L1w_DevRfcAfcHz2PPM
+ 0x1000b658 0x4d _L1w_DevRfcPpm2Hz
+ 0x1000b6a5 0x50 _L1w_DevRfcAfcUpdate
+ 0x1000b6f5 0x1c _L1w_DevRfcOpenCtrl
+ 0x1000b711 0x33 _L1w_DevRfcReusedReSourceRestore
+ 0x1000b744 0x1 _L1w_DevRfcTxTestMode
+ 0x1000b745 0x389 _L1w_RfcTask
+ .text 0x1000bace 0x1c63 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x1000bace 0x1f _L1w_DevPcDpchReset
+ 0x1000baed 0x1 _L1w_DevPcDpchInit
+ 0x1000baee 0x94 _L1w_DevPcDpcchPowerFilter
+ 0x1000bb82 0x38 _L1w_DevPcDeltaPilotPro
+ 0x1000bbba 0x28 _L1w_DevPcPowerItpPro
+ 0x1000bbe2 0x1c _L1w_DevPcGapTpcJudge
+ 0x1000bbfe 0x4b _L1w_DevPcCmPowerPro
+ 0x1000bc49 0x60 _L1w_DevPcDpcchPowerCalc
+ 0x1000bca9 0x40 _L1w_DevPcDeltaPilotPowerCalc
+ 0x1000bce9 0x3c _L1w_DevPcDeltaResumeCalc
+ 0x1000bd25 0x3c _L1w_DevPcRppPowerCalc
+ 0x1000bd61 0x59 _L1w_DevPcGetDeltaPilotCalcMode
+ 0x1000bdba 0x2a _L1w_DevPcSigmaLastCalc
+ 0x1000bde4 0xe0 _L1w_DevPcAjCalc
+ 0x1000bec4 0x5d _L1w_DevPcFindNearBeltaC
+ 0x1000bf21 0x6b _L1w_DevPcFindNearBeltaD
+ 0x1000bf8c 0x47 _L1w_DevPcAjToBelta
+ 0x1000bfd3 0x11 _L1w_DevPcDpchCurTfciBeltaCD
+ 0x1000bfe4 0x1f5 _L1w_DevPcBeltaCBeltaDCalc
+ 0x1000c1d9 0xf0 _L1w_DevPcBeltaCBeltaDUpdate
+ 0x1000c2c9 0xcc _L1w_DevPcSecCmBetalUpd
+ 0x1000c395 0x18 _L1w_DlIlpc_reset
+ 0x1000c3ad 0x8 _L1w_Olpc_reset
+ 0x1000c3b5 0x10 _L1w_DevPcOlpcCntReset
+ 0x1000c3c5 0xf _L1w_DevPcTpcGenReset
+ 0x1000c3d4 0xc _L1w_DevPcWindupReset
+ 0x1000c3e0 0x42 _L1w_DevPcDlSirCmAdjust
+ 0x1000c422 0x90 _L1w_DevPcDlSirTargetCalc
+ 0x1000c4b2 0xec _L1w_DevPcFdpchSirCal
+ 0x1000c59e 0x111 _L1w_DevPcDpchSirCal
+ 0x1000c6af 0x49 _L1w_DevPcDlWindUpMode
+ 0x1000c6f8 0x3c _L1w_DevPcSirSfAdjust
+ 0x1000c734 0x95 _L1w_DevPcTpcGenDpcMode1
+ 0x1000c7c9 0xd4 _L1w_DevPcDlTpcCmdGen
+ 0x1000c89d 0x26 _L1w_DevFdpchRscpCalc
+ 0x1000c8c3 0x37 _L1w_DevDpchParaECal
+ 0x1000c8fa 0x88 _L1w_DevDpchRscpCalc
+ 0x1000c982 0x9a _L1w_DevPcPilotIntInd
+ 0x1000ca1c 0x75 _L1w_DevPcRlsSetStaticAndSirThJudge
+ 0x1000ca91 0xb2 _L1w_DevPcSetTpcSoftBit
+ 0x1000cb43 0xc5 _L1w_DevPcTpcCombine
+ 0x1000cc08 0x14 _L1w_DevPcTpcSingleRlPca1Calc
+ 0x1000cc1c 0x11 _L1w_DevPcTpcSingleRlPca2Calc
+ 0x1000cc2d 0x89 _L1w_DevPcTpcMultiRlsPca1Calc
+ 0x1000ccb6 0x51 _L1w_DevPcTpcMultiRlsPca2Calc
+ 0x1000cd07 0x46 _L1w_DevPcTpcSingleRlCombine
+ 0x1000cd4d 0x4d _L1w_DevPcTpcMultiRlCombine
+ 0x1000cd9a 0x7e _L1w_DevPcTpcMultiRlsCombine
+ 0x1000ce18 0x18 _L1w_DevPcSirReset
+ 0x1000ce30 0x5 _L1w_DevPcBetalSeqalCal
+ 0x1000ce35 0x58 _L1w_DevPcCurSlotPowCalc
+ 0x1000ce8d 0x1f _L1w_DevPcIsOverPwr
+ 0x1000ceac 0x2a _L1w_DevPcSerachTfci
+ 0x1000ced6 0x31 _L1w_DevPcCurSlotOverPowProc
+ 0x1000cf07 0x40 _L1w_DevPcMaxPowerUpdate
+ 0x1000cf47 0xf _L1w_DevPcUlTfcOverEstCmp
+ 0x1000cf56 0xe9 _L1w_DevPcUlTfcOverEstRlt
+ 0x1000d03f 0x22 _L1w_DevPcUphFrmAvrCalc
+ 0x1000d061 0x5 _L1w_DevPcUphMapRep
+ 0x1000d066 0x32 _L1w_DevPcUphResult
+ 0x1000d098 0x8 _L1w_DevPcGetUphValue
+ 0x1000d0a0 0xab _L1w_DevPcUphProc
+ 0x1000d14b 0x91 _L1w_DevPcCfgInfoUpd
+ 0x1000d1dc 0x83 _L1w_DevPcDchInfoGet
+ 0x1000d25f 0x1e _L1w_DevDchOlpcBlerTargetMapping
+ 0x1000d27d 0x8f _L1w_DevPcDchOlpcThParamGet
+ 0x1000d30c 0x59 _L1w_DevPcEfachBeltacCal
+ 0x1000d365 0x104 _L1w_DevPcDchStartReqHandle
+ 0x1000d469 0x1a _L1w_DevPcUldpchTfciInfoHandle
+ 0x1000d483 0x27 _L1w_DevPcFDpchOutLoopAdj
+ 0x1000d4aa 0x55 _L1w_DevPcDpchOutLoopAdj
+ 0x1000d4ff 0x69 _L1w_DevPcDlRefTrchSel
+ 0x1000d568 0x68 _L1w_DevPcOlpcInit
+ 0x1000d5d0 0x3f _L1w_DevPcDtrBlerInfoHandle
+ 0x1000d60f 0x14 _L1w_DevPcTpcBerCal
+ 0x1000d623 0x27 _L1w_DevPcRlsTpcBerPro
+ 0x1000d64a 0x7e _L1w_DevPcMutlRlsTpcBerCal
+ 0x1000d6c8 0x33 _L1w_DevPcTpcBerCtr
+ 0x1000d6fb 0x36 _L1w_DevPcOlpcCtrl
+ .text 0x1000d731 0x1bca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x1000d731 0x64 _L1w_DevHsdpaStartPc
+ 0x1000d795 0x27 _L1w_DevHspdaHwReset
+ 0x1000d7bc 0x1b _L1w_DevHsdpaHwInit
+ 0x1000d7d7 0xa3 _L1w_DevHsdpaReset
+ 0x1000d87a 0x1 _L1w_DevHsdpaNvInit
+ 0x1000d87b 0x10d _L1w_DevHsdpaParaInit
+ 0x1000d988 0x187 _L1w_DevHsdpaRegTpuEvent
+ 0x1000db0f 0x1ac _L1w_DevHsdpaCfgProc
+ 0x1000dcbb 0x6e _L1w_DevHsdpaRelProc
+ 0x1000dd29 0xc4 _L1w_DevHsdpaIcSymModProc
+ 0x1000dded 0xa1 _L1w_DevHsdpaAdrCirIntProc
+ 0x1000de8e 0xeb _L1w_DevHsdpaAdrCpichIntProc
+ 0x1000df79 0x30 _L1w_DevHsdpaHsscchPart1IntProc
+ 0x1000dfa9 0x4d _L1w_DevHsdpaHsscchPart2IntProc
+ 0x1000dff6 0x30 _L1w_DevHsdpaHdtrIntProc
+ 0x1000e026 0x3a _L1w_DevHsdpaCfn2SfnTime
+ 0x1000e060 0x37 _L1w_DevHsdpaOrderActProc
+ 0x1000e097 0x152 _L1w_DevHsdpaDchTpuProc
+ 0x1000e1e9 0x42f _L1w_DevHsdpaTpuTraceLog
+ 0x1000e618 0xfb _L1w_DevHsdpaIsJudgechangjing3
+ 0x1000e713 0xe0 _L1w_DevHsdpaTpuProc
+ 0x1000e7f3 0xb4 _L1w_DevHsdpaCompareCellInfo
+ 0x1000e8a7 0x173 _L1w_DevHsdpaIsJudgePsrOver512
+ 0x1000ea1a 0x105 _L1w_DevHsdpaPsrOver512
+ 0x1000eb1f 0x2a _L1w_DevHsdpaPsrFingerOldDaNew
+ 0x1000eb49 0x2a _L1w_DevHsdpaPsrFingerNewXiaoOld
+ 0x1000eb73 0xea _L1w_DevHsdpaPsrIschangjing3
+ 0x1000ec5d 0x1d0 _L1w_DevHsdpaTxTpuProc
+ 0x1000ee2d 0x56 _L1w_DevHsdpaPsrUpdateProc
+ 0x1000ee83 0x3f _L1w_DevHsdpaCmUpdateProc
+ 0x1000eec2 0x4a _L1w_DevHsdpaCfgReq
+ 0x1000ef0c 0x29 _L1w_DevHsdpaRelReq
+ 0x1000ef35 0x29 _L1w_DevHsdpaIcSymModIntInd
+ 0x1000ef5e 0x29 _L1w_DevHsdpaAdrCirIntInd
+ 0x1000ef87 0x29 _L1w_DevHsdpaAdrCpichIntInd
+ 0x1000efb0 0x29 _L1w_DevHsdpaHsscchPart1IntInd
+ 0x1000efd9 0x29 _L1w_DevHsdpaHsscchPart2IntInd
+ 0x1000f002 0x29 _L1w_DevHsdpaHdtrIntInd
+ 0x1000f02b 0x3b _L1w_DevDlsHsdpaPsrUpdateReq
+ 0x1000f066 0x35 _L1w_DevHsdpaCmUpdateReq
+ 0x1000f09b 0x3b _L1w_DevHsdpaHsscchOrdInd
+ 0x1000f0d6 0x4c _L1w_DevHsdpaFachCfgReq
+ 0x1000f122 0x26 _L1w_DevHsdpaFachRelReq
+ 0x1000f148 0x29 _L1w_DevHsdpaFachRcvReq
+ 0x1000f171 0x26 _L1w_DevHsdpaFachHrntiUpdateReq
+ 0x1000f197 0x21 _L1w_DevHsdpaFachDataInd
+ 0x1000f1b8 0x4b _L1w_DevHsdpaPchCfgReq
+ 0x1000f203 0x21 _L1w_DevHsdpaPchRelReq
+ 0x1000f224 0x26 _L1w_DevHsdpaRtxPiInd
+ 0x1000f24a 0x28 _L1w_DevHsdpaDmaIntInd
+ 0x1000f272 0x39 _L1w_DevHsdpaDataDmaCpy
+ 0x1000f2ab 0x24 _L1w_DevHsdpaCurTime2SfnTime
+ 0x1000f2cf 0x2c _L1w_DevHsdpaGetCurSfnTime
+ .text 0x1000f2fb 0x16ff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x1000f2fb 0x20 _L1w_DevHsdpaLessIsAct
+ 0x1000f31b 0xa5 _L1w_DevHsdpaLessParaInit
+ 0x1000f3c0 0x2f _L1w_DevHsdpaLessOrdIndProc
+ 0x1000f3ef 0x33 _L1w_DevHsdpaLessTimeRcd
+ 0x1000f422 0x5f _L1w_DevHsdpaLessCfgTraceLog
+ 0x1000f481 0xc _L1w_DevHsdpaLessCfgAllTb
+ 0x1000f48d 0x23 _L1w_DevHsdpaLessFindIdleHarq
+ 0x1000f4b0 0x231 _L1w_DevHsdpaPart2Type2Proc
+ 0x1000f6e1 0xc5 _L1w_DevHsdpaDchLessProc
+ 0x1000f7a6 0x7e _L1w_DevHsdpaPart2LessProc
+ 0x1000f824 0x23 _L1w_DevHsdpaIsLessValid
+ 0x1000f847 0x18 _L1w_DevHsdpaLessFindHsdschTti
+ 0x1000f85f 0x1c9 _L1w_DevHsdpaDchLessHdtrIntProc
+ 0x1000fa28 0x24 _L1w_DevHsdpaLessHdtrIntProc
+ 0x1000fa4c 0x6b _L1w_DevHsdpaPchSaveAdrInitCfg
+ 0x1000fab7 0x51 _L1w_DevHsdpaPchSaveHsscchInitCfg
+ 0x1000fb08 0x7d _L1w_DevHsdpaPchRxInitRcvProc
+ 0x1000fb85 0xae _L1w_DevHsdpaPchSaveLessPara
+ 0x1000fc33 0x8e _L1w_DevHsdpaPchSaveAdrSubFrmCfg
+ 0x1000fcc1 0x42 _L1w_DevHsdpaPchSaveIcPsrCfg
+ 0x1000fd03 0x9a _L1w_DevHsdpaPchRxSubFrmProc
+ 0x1000fd9d 0x5f _L1w_DevHsdpaPchCfgProc
+ 0x1000fdfc 0x2d _L1w_DevHsdpaPchRelProc
+ 0x1000fe29 0x18 _L1w_DevHsdpaPchTpuProc
+ 0x1000fe41 0x62 _L1w_DevHsdpaPchSavePart1IntCfg
+ 0x1000fea3 0x66 _L1w_DevHsdpaPchPart2Type1Proc
+ 0x1000ff09 0x12d _L1w_DevHsdpaPchHdtrIntProc
+ 0x10010036 0x92 _L1w_DevHsdpaPchLessProc
+ 0x100100c8 0x16d _L1w_DevHsdpaPchLessHdtrIntProc
+ 0x10010235 0xa1 _L1w_DevHsdpaRtxPiIndProc
+ 0x100102d6 0x71 _L1w_DevHsdpaFachStartPc
+ 0x10010347 0x4e _L1w_DevHsdpaFachSaveHsdpcchAckCfg
+ 0x10010395 0x5c _L1w_DevHsdpaFachSaveHsdpcchCqiCfg
+ 0x100103f1 0x4d _L1w_DevHsdpaFachCqiSendCtrl
+ 0x1001043e 0x6e _L1w_DevHsdpaFachSaveAdrInitCfg
+ 0x100104ac 0x4a _L1w_DevHsdpaFachSaveHsscchInitCfg
+ 0x100104f6 0x52 _L1w_DevHsdpaFachRxInitRcvProc
+ 0x10010548 0x2e _L1w_DevHsdpaFachTxInitSendProc
+ 0x10010576 0x81 _L1w_DevHsdpaFachSaveAdrSubFrmCfg
+ 0x100105f7 0x83 _L1w_DevHsdpaFachRxSubFrmProc
+ 0x1001067a 0x56 _L1w_DevHsdpaFachTxSubFrmProc
+ 0x100106d0 0x68 _L1w_DevHsdpaFachCfgProc
+ 0x10010738 0x44 _L1w_DevHsdpaFachRelProc
+ 0x1001077c 0x22 _L1w_DevHsdpaFachTpuProc
+ 0x1001079e 0x2e _L1w_DevHsdpaFachSavePart1IntCfg
+ 0x100107cc 0x131 _L1w_DevHsdpaFachHdtrIntProc
+ 0x100108fd 0x3c _L1w_DevHsdpaFachRcvProc
+ 0x10010939 0x28 _L1w_DevHsdpaFachHrntiUpdateProc
+ 0x10010961 0x79 _L1w_DevHsdpaFachEdchIndProc
+ 0x100109da 0x20 _L1w_DevHsdpaFachSetHsdpcchFlg
+ .text 0x100109fa 0x1019 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ 0x100109fa 0x60 _L1w_DevRtxRxFingerCfg
+ 0x10010a5a 0xe2 _L1w_DevRtxRxCpichCfg
+ 0x10010b3c 0x4f _L1w_DevRtxRxPichCfg
+ 0x10010b8b 0x12 _L1w_DevRtxRxPichRel
+ 0x10010b9d 0x50 _L1w_DevRtxRxPchCfg
+ 0x10010bed 0x24 _L1w_DevRtxRxPchRel
+ 0x10010c11 0x2f _L1w_DevRtxRxAichRakeCfg
+ 0x10010c40 0x26 _L1w_DevRtxRxAichCfg
+ 0x10010c66 0x5 _L1w_DevRtxRxAichRel
+ 0x10010c6b 0x2e _L1w_DevRtxRxFachRakeCfg
+ 0x10010c99 0x46 _L1w_DevRtxRxFachCfg
+ 0x10010cdf 0x21 _L1w_DevRtxRxFachRel
+ 0x10010d00 0xa5 _L1w_DevRtxRxDlDpchRakeCfg
+ 0x10010da5 0x40 _L1w_DevRtxRxDlDpchCfg
+ 0x10010de5 0x26 _L1w_DrvDpramRxWriteClearData
+ 0x10010e0b 0x39 _L1w_DevRtxRxDlDpchRel
+ 0x10010e44 0x16d _L1w_DevRtxRxDlCmSlotCfg
+ 0x10010fb1 0xe5 _L1w_DevRtxRxDlCmSlotRel
+ 0x10011096 0x63 _L1w_DevRtxRxDlCmCfgTpuIntHandle
+ 0x100110f9 0x1ff _L1w_DevRtxRxDlCmCfg
+ 0x100112f8 0x6f _L1w_DevRtxRxFdpchRakeCfg
+ 0x10011367 0x3d _L1w_DevRtxRxFdpchCfg
+ 0x100113a4 0x5 _L1w_DevRtxRxFdpchRel
+ 0x100113a9 0x34 _L1w_DevRtxRxHsscchRakeCfg
+ 0x100113dd 0x39 _L1w_DevRtxRxHsscchCfg
+ 0x10011416 0x5 _L1w_DevRtxRxHsscchRel
+ 0x1001141b 0x38 _L1w_DevRtxRxEagchRakeCfg
+ 0x10011453 0x34 _L1w_DevRtxRxEagchCfg
+ 0x10011487 0xf _L1w_DevRtxRxEagchRel
+ 0x10011496 0xbc _L1w_DevRtxRxRgHiRakeCfg
+ 0x10011552 0x4b _L1w_DevRtxRxRgHiCfg
+ 0x1001159d 0x5 _L1w_DevRtxRxRgHiRel
+ 0x100115a2 0x6b _L1w_DevRtxRxCctrchCfgHandle
+ 0x1001160d 0x11b _L1w_DevRtxRxCfgHandle
+ 0x10011728 0x2f _L1w_DevRtxRxDlTpcPlCfg
+ 0x10011757 0x7e _L1w_DevRtxRxIntFingerCfg
+ 0x100117d5 0x69 _L1w_DevRtxRxIntCfg
+ 0x1001183e 0x6e _L1w_DevRtxRxDpchSlotForm
+ 0x100118ac 0x71 _L1w_DevRtxRxSccpchSlotForm
+ 0x1001191d 0x5a _L1w_DevRtxRxComparaSlotForm
+ 0x10011977 0x34 _L1w_DevRtxRxCmASlotForm
+ 0x100119ab 0x34 _L1w_DevRtxRxCmBSlotForm
+ 0x100119df 0x34 _L1w_DevRtxRxNormalSlotForm
+ .text 0x10011a13 0x92c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x10011a13 0x13 _L1w_DevRtxTimeCmp
+ 0x10011a26 0x2d _L1w_DevRtxUlRfcReq
+ 0x10011a53 0x37 _L1w_DevRtxUlRfTblInit
+ 0x10011a8a 0x2f _L1w_DevRtxUlRfGetNodeFromUnusedQ
+ 0x10011ab9 0x17 _L1w_DevRtxUlRfPutNode2UnusedQ
+ 0x10011ad0 0x31 _L1w_DevRtxUlRfQueueInsert
+ 0x10011b01 0x41 _L1w_DevRtxUlRfQueueGet
+ 0x10011b42 0xf _L1w_DevRtxUlRfQueueSearch
+ 0x10011b51 0x67 _L1w_DevRtxUlRfStartSched
+ 0x10011bb8 0x262 _L1w_DevRtxUlRfCtrlReq
+ 0x10011e1a 0x1de _L1w_DevRtxUlRfSchedPick
+ 0x10011ff8 0x81 _L1w_DevRtxUlRfSchedLink
+ 0x10012079 0x12f _L1w_DevRtxUlRfSchedMerge
+ 0x100121a8 0x18a _L1w_DevRtxUlRfSched
+ 0x10012332 0xd _L1w_DevRtxUlRfStopSched
+ .text 0x1001233f 0xf38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x1001233f 0x7 _L1w_DevTxGetDchState
+ 0x10012346 0x11 _L1w_DevTxGetRfCtrlPara
+ 0x10012357 0x15 _L1w_DevTxDchReset
+ 0x1001236c 0x39 _L1w_DevTxOpenRfc
+ 0x100123a5 0x39 _L1w_DevTxCloseRfc
+ 0x100123de 0x68 _L1w_DevTxCmRfcCfg
+ 0x10012446 0x50 _L1w_DevTxNormalSlotForm
+ 0x10012496 0x5e _L1w_DevTxCmSlotForm
+ 0x100124f4 0x1c _L1w_DevTxCalcCmPliot
+ 0x10012510 0x39 _L1w_DevTxGetUlMaxMinTti
+ 0x10012549 0x10e _L1w_DevTxGetDchParam
+ 0x10012657 0x75 _L1w_DevTxUlCmTfciAnalysis
+ 0x100126cc 0x29 _L1w_DevTxHsupaTransInd
+ 0x100126f5 0x16b _L1w_DevTxDchToPcStart
+ 0x10012860 0x26 _L1w_DevTxDchToPcStop
+ 0x10012886 0x64 _L1w_DevTxDchCmParaToPc
+ 0x100128ea 0x27 _L1w_DevTxDpcchPreambleToPc
+ 0x10012911 0x2a _L1w_DevTxDpdchTfciToPc
+ 0x1001293b 0x177 _L1w_DevTxDataUpdate
+ 0x10012ab2 0x55 _L1w_DevTxGetUtrPara
+ 0x10012b07 0x115 _L1w_DevTxDchUtrCfg
+ 0x10012c1c 0x77 _L1w_DevTxDchCmProc
+ 0x10012c93 0x154 _L1w_DevTxDchSendCfg
+ 0x10012de7 0xad _L1w_DevTxDchPreambleSendProc
+ 0x10012e94 0x29 _L1w_DevTxDchPostVerifyFailProc
+ 0x10012ebd 0x94 _L1w_DevTxDchPreambleIntHandle
+ 0x10012f51 0xd9 _L1w_DevTxDpchSendCndCheck
+ 0x1001302a 0x59 _L1w_DevTxDpchIntHandle
+ 0x10013083 0x54 _L1w_DevTxDchTpuIntHandle
+ 0x100130d7 0x65 _L1w_DevTxDchRelMsgHandle
+ 0x1001313c 0x8b _L1w_DevTxCmCfgMsgHandle
+ 0x100131c7 0xb0 _L1w_DevTxDchCfgMsgHandle
+ .text 0x10013277 0x6e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x10013277 0xf _L1W_DevHsupaInitMacro
+ 0x10013286 0xc _L1W_DevHsupaCalCBNum
+ 0x10013292 0x21 _L1W_DevHsupaCalcCBLength
+ 0x100132b3 0xa _L1W_DevHsupaCalInterleavingRow
+ 0x100132bd 0x3a _L1W_DevHsupaCalCodeBlockConf
+ 0x100132f7 0x1c _L1w_DevHsupaCalMaxNej
+ 0x10013313 0x99 _L1W_DevHsupaCalSfOneEtfc
+ 0x100133ac 0xfd _L1W_DevHsupaCalAllSFConf
+ 0x100134a9 0x12a _L1W_DevHsupaCalSFConf
+ 0x100135d3 0x94 _L1W_DevHsupaCalRmRv
+ 0x10013667 0x9b _L1W_DevHsupaCalRmPara
+ 0x10013702 0x41 _L1W_DevHsupaCalChannelCodeConf
+ 0x10013743 0x7a _L1W_DevHsupaCalInterleavingConf
+ 0x100137bd 0x37 _L1W_DevHsupaReTransBitmapTtiTen
+ 0x100137f4 0x6b _L1W_DevHsupaCalEtxBitmap
+ 0x1001385f 0x48 _L1W_DevHsupaCalEUTRConf
+ 0x100138a7 0x6e _L1W_DevHsupaCalETXConf
+ 0x10013915 0x46 _L1W_DevHsupaCalULConf
+ .text 0x1001395b 0x1358 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x1001395b 0xb _L1w_DevRfcCtrlDbChgeInfoSet
+ 0x10013966 0xf _L1w_DevRfcCtrlDbChgeInfoInit
+ 0x10013975 0x2 _L1w_DevRfcCtrlDbSlotEndSet
+ 0x10013977 0x17 _L1w_DevRfcCtrlDbSlotInfoInit
+ 0x1001398e 0x61 _L1w_DevRfcCtrlDbInit
+ 0x100139ef 0x10 _L1w_DevRfcCtrlDbInitAll
+ 0x100139ff 0x37 _L1w_DevRfcCtrlDbTimeContCheck
+ 0x10013a36 0x33 _L1w_DevRfcCtrlDbSlotChgeInfoWr
+ 0x10013a69 0x16 _L1w_DevRfcCtrlDbGetDbInd
+ 0x10013a7f 0x35 _L1w_DevRfcCtrlDbFrameChgeInfoWr
+ 0x10013ab4 0x2d _L1w_DevRfcCtrlDbGetSegLen
+ 0x10013ae1 0x9f _L1w_DevRfcCtrlDbSlotEndUpdate
+ 0x10013b80 0x5c _L1w_DevRfcCtrlDbCtrlInfoUpdate
+ 0x10013bdc 0x117 _L1w_DevRfcCtrlDbSchedUpdate
+ 0x10013cf3 0x9c _L1w_DevRfcCtrlDbStPo2Chge
+ 0x10013d8f 0x6d _L1w_DevRfcCtrlDbStPo1Chge
+ 0x10013dfc 0x93 _L1w_DevRfcCtrlDbStPi2Chge
+ 0x10013e8f 0x27 _L1w_DevRfcCtrlDbStPi1Chge
+ 0x10013eb6 0x63 _L1w_DevRfcCtrlDbStPi0Chge
+ 0x10013f19 0x49 _L1w_DevRfcCtrlDbStartInsert
+ 0x10013f62 0xeb _L1w_DevRfcCtrlDbEndPo2Chge
+ 0x1001404d 0x5d _L1w_DevRfcCtrlDbEndPo1Chge
+ 0x100140aa 0xf _L1w_DevRfcCtrlDbEndPo0Chge
+ 0x100140b9 0x3f _L1w_DevRfcCtrlDbEndInsert
+ 0x100140f8 0xf9 _L1w_DevRfcCtrlDbDrvOpenUpdate
+ 0x100141f1 0xd _L1w_DevRfcCtrlDbGetAdr
+ 0x100141fe 0x4a _L1w_DevRfcCtrlDbChgeInfoHandle
+ 0x10014248 0x10e _L1w_DevRfcCtrlDbGetSlotChgeInfo
+ 0x10014356 0x39 _L1w_DevRfcAgcDbInit
+ 0x1001438f 0x29 _L1w_DevRfcAfcDbInit
+ 0x100143b8 0x14 _L1w_DevRfcAgcDbFreqSearch
+ 0x100143cc 0xe _L1w_DevRfcAgcDbSetFreqChgeFlag
+ 0x100143da 0x21 _L1w_DevRfcAgcDbFindOldestPos
+ 0x100143fb 0x58 _L1w_DevRfcAgcDbFindFreqPos
+ 0x10014453 0x21 _L1w_DevRfcAgcDbGetFreqInd
+ 0x10014474 0x35 _L1w_DevRfcAgcDbFastAgcCond
+ 0x100144a9 0xd0 _L1w_DevRfcAgcDbAgcSet
+ 0x10014579 0x3b _L1w_DevRfcAgcDbLockInfoUpdate
+ 0x100145b4 0x3a _L1w_DevRfcAgcCalcInfoUpdateCmn
+ 0x100145ee 0x2e _L1w_DevRfcAgcCalcInfoUpdateDpa
+ 0x1001461c 0x58 _L1w_DevRfcAgcDbAgcStepCtrl
+ 0x10014674 0x48 _L1w_DevRfcAgcDbAgcUpdate
+ 0x100146bc 0x6e _L1w_DevRfcAgcDbAgcCalcSingleCh
+ 0x1001472a 0x37 _L1w_DevRfcAgcDbAfterFastAgcSet
+ 0x10014761 0x38 _L1w_DevRfcAgcDbFastAgcValUpdate
+ 0x10014799 0x60 _L1w_DevRfcAgcDb2RMainChAdjCond
+ 0x100147f9 0x6b _L1w_DevRfcAgcDb2RAgcHandle
+ 0x10014864 0x124 _L1w_DevRfcAgcDbAgcCalc
+ 0x10014988 0x1c _L1w_DevRfcAgcDbAgcEstEn
+ 0x100149a4 0x3d _L1w_DevRfcAfcDbAfcSet
+ 0x100149e1 0x13 _L1w_DevRfcAfcDbGetAfcDbVal
+ 0x100149f4 0x1e _L1w_DevRfcSetRefFreq
+ 0x10014a12 0x43 _L1w_DevRfcAgcDbGetFreqAgcInfo
+ 0x10014a55 0x62 _L1w_DevRfcAgcDbGetRssi
+ 0x10014ab7 0x9e _L1w_DevRfcAgcDbGetMeanpwr
+ 0x10014b55 0x35 _L1w_DevRfcAgcDbAuxChInitSet
+ 0x10014b8a 0x42 _L1w_DevRfcAgcDbGetTableInd
+ 0x10014bcc 0x7a _L1w_DevRfcAgcDbFdtAgcInit
+ 0x10014c46 0x43 _L1w_DevRfcAgcDbNstAgcInit
+ 0x10014c89 0x15 _L1w_DevRfcAgcDbTxChgeInfoWr
+ 0x10014c9e 0x15 _L1w_DevRfcAgcDbRxChgeInfoWr
+ .text 0x10014cb3 0x2cb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ 0x10014cb3 0x26 _L1w_DevDlsSendIntMsg
+ 0x10014cd9 0x24 _L1w_DevDlsSendCnf
+ 0x10014cfd 0xf _L1w_DevDlsReset
+ 0x10014d0c 0xf _L1w_DevDlsInit
+ 0x10014d1b 0x263 _L1w_DlsTask
+ .text 0x10014f7e 0x12a5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x10014f7e 0x89 _L1w_DevHsdpaSubFrmIsInCm
+ 0x10015007 0x78 _L1w_DevHsdpaCalcTimingInfo
+ 0x1001507f 0x2d _L1w_DevHsdpaCalcAckNackPos
+ 0x100150ac 0x52 _L1w_DevHsdpaCalcTbSizeByTbs
+ 0x100150fe 0x23 _L1w_DevHsdpaCalcTbSizeByTbsIdx
+ 0x10015121 0xd _L1w_DevHsdpaCalcRvB
+ 0x1001512e 0x3a _L1w_DevHsdpaCalcCodeBlockPara
+ 0x10015168 0x25 _L1w_DevHsdpaCalc1stRmPara
+ 0x1001518d 0x37 _L1w_DevHsdpaCalc2ndRmEini
+ 0x100151c4 0xf9 _L1w_DevHsdpaCalcRmPara
+ 0x100152bd 0x9f _L1w_DevHsdpaCalcVelcity
+ 0x1001535c 0xd _L1w_DevHsdpaCalcSymPower
+ 0x10015369 0x79 _L1w_DevHsdpaCalcFingerMaskStep1
+ 0x100153e2 0xba _L1w_DevHsdpaCalcFingerMaskStep2
+ 0x1001549c 0x45 _L1w_DevHsdpaCalcFingerMaskStep3
+ 0x100154e1 0x5d _L1w_DevHsdpaCalcAntFingerMask
+ 0x1001553e 0x11f _L1w_DevHsdpaFingerMaskBufUpdate
+ 0x1001565d 0x8c _L1w_DevHsdpaCalcFingerMask
+ 0x100156e9 0xb8 _L1w_DevHsdpaSnrLowRstJudge
+ 0x100157a1 0x1b0 _L1w_DevHsdpaCalcNoiseSinr
+ 0x10015951 0x47 _L1w_DevHsdpaCalcNoiseFactor
+ 0x10015998 0xc3 _L1w_DevHsdpaCalcCirPower
+ 0x10015a5b 0xba _L1w_DevHsdpaCalcEqNoise
+ 0x10015b15 0x34 _L1w_DevHsdpaCalcNoise
+ 0x10015b49 0x2d _L1w_DevHsdpaIsExceedFinWin
+ 0x10015b76 0x6b _L1w_DevHsdpaPsrFingerFilter
+ 0x10015be1 0x56 _L1w_DevHsdpaCalcFrameHeadPos
+ 0x10015c37 0x87 _L1w_DevHsdpaCalcIntraCellSfnOffset
+ 0x10015cbe 0xfc _L1w_DevHsdpaCalcFingerSort
+ 0x10015dba 0x24 _L1w_DevHsdpaCalcJudgeResetFlg
+ 0x10015dde 0x27c _L1w_DevHsdpaCalcCellFingerSort
+ 0x1001605a 0x1b _L1w_DevHsdpaCalcAntChe4xPos
+ 0x10016075 0xef _L1w_DevHsdpaCalcChe4xPos
+ 0x10016164 0xbf _L1w_DevHsdpaCalcAdrPsrInfo
+ .text 0x10016223 0x3d4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ 0x10016223 0x3f _L1w_DevDrvAllIntClear
+ 0x10016262 0x54 _L1w_DevDrvRestoreAllInt
+ 0x100162b6 0x9e _L1W_TPU_RAKE_ISR
+ 0x10016354 0x70 _L1W_RAKE_DFE_RFC_ISR
+ 0x100163c4 0xac _L1W_TPU_CSR_ADR_HSSCCH_ISR
+ 0x10016470 0x89 _L1W_CSR_DTR_PSR_ISR
+ 0x100164f9 0x27 _L1w_DevCommGetTop19IntStatus
+ 0x10016520 0x26 _L1W_ICP_UPA_DATA_ISR
+ 0x10016546 0x5c _L1W_ICP_SLEEP_WAKEUP_ISR
+ 0x100165a2 0x1c _L1W_EDCP_ISR
+ 0x100165be 0x39 _L1_W_LPM_T3_ISR
+ .text 0x100165f7 0x2265 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x100165f7 0x8 _L1w_DevCsrSetStep1Clk
+ 0x100165ff 0x8 _L1w_DevCsrGetStep1Clk
+ 0x10016607 0x6 _L1w_DevGetPeakThreshold
+ 0x1001660d 0x1 _L1w_DevGetFsThreshold
+ 0x1001660e 0x1e _L1w_DevCsrStep1Cmp
+ 0x1001662c 0xa _L1w_DevCsrF2W
+ 0x10016636 0xf _L1w_DevCsrW2F
+ 0x10016645 0x15 _L1w_DevCsrCompare
+ 0x1001665a 0x87 _L1w_DevCsrComputeWin
+ 0x100166e1 0x2a _L1w_DevCsrInitReq
+ 0x1001670b 0x98 _L1w_DevCsrStep1Req
+ 0x100167a3 0x75 _L1w_DevCsrFsReq
+ 0x10016818 0x27 _L1w_DevCsrResetCnf
+ 0x1001683f 0x27 _L1w_DevCsrInitCnf
+ 0x10016866 0x65 _L1w_DevCsrStep1Cnf
+ 0x100168cb 0x4f _L1w_DevCsrFsCnf
+ 0x1001691a 0x2d _L1w_DevCsrIntInd
+ 0x10016947 0x5d _L1w_DevCsrStep1CalConfigIndex4_1
+ 0x100169a4 0x3d _L1w_DevCsrSaveDateMrtr
+ 0x100169e1 0x138 _L1w_DevCsrIcCfg
+ 0x10016b19 0xe _L1w_DevCsrSetFsAbort
+ 0x10016b27 0x1ac _L1w_DevCsrStep1Abort
+ 0x10016cd3 0x272 _L1w_DevCsrStep1Pro
+ 0x10016f45 0xa _L1w_DevCsrClrFsSt
+ 0x10016f4f 0x7d _L1w_DevCsrFsPro
+ 0x10016fcc 0xbf _L1w_DevCsrPeakFilter
+ 0x1001708b 0xb8 _L1w_DevCsrPeakSearch
+ 0x10017143 0x95 _L1w_DevCsrFsReqCfg
+ 0x100171d8 0x113 _L1w_DevCsrIcFilter
+ 0x100172eb 0x1312 _L1w_DevCsrStep1Int
+ 0x100185fd 0x125 _L1w_DevCsrFsInt
+ 0x10018722 0x1a _L1w_DevCsrStep1IsBusy
+ 0x1001873c 0x13 _L1w_DevCsrReset
+ 0x1001874f 0x10 _L1w_DevCsrStFsSt
+ 0x1001875f 0xfd _L1w_CsrTask
+ .text 0x1001885c 0x220d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x1001885c 0x30 _L1w_DevPcWord64ToFloat
+ 0x1001888c 0x40 _L1w_DevPcFloatToWord
+ 0x100188cc 0x2e _L1w_PcLog2FindTable
+ 0x100188fa 0x80 _L1w_DevPcFloatSirAndBlerToWord32
+ 0x1001897a 0x28 _L1w_DevPcDiv
+ 0x100189a2 0x71 _L1w_DevPcLog10
+ 0x10018a13 0xe6 _L1w_DevPc10xPower10expOld
+ 0x10018af9 0x2c _L1w_DevPc10xPower10exp
+ 0x10018b25 0x65 _L1w_DevSirBlerPcDiv
+ 0x10018b8a 0x38 _L1w_DevPcFloatAdd
+ 0x10018bc2 0x3b _L1w_DevPcUlAlphaDiv
+ 0x10018bfd 0x62 _L1w_DevPcPowerLimit
+ 0x10018c5f 0x86 _L1w_DevPcSumBeltaIQmap
+ 0x10018ce5 0x81 _L1w_DevPcCalcSquareBetaHs
+ 0x10018d66 0x22 _L1w_DevPcP1P2LogCalc
+ 0x10018d88 0x19 _L1w_DevPcP1P2Calc
+ 0x10018da1 0xd _L1w_DevPcBetalRatioProc
+ 0x10018dae 0x9d _L1w_DevPcCodeRatioCalc
+ 0x10018e4b 0x14 _L1w_DevPcGetTxpowerForMeas
+ 0x10018e5f 0x99 _L1w_DevPcConfigTxReg
+ 0x10018ef8 0x92 _L1w_DevPcTtiUpdDpaBeta
+ 0x10018f8a 0xe4 _L1w_DevPcTtiUpdEdchBeta
+ 0x1001906e 0x23 _L1w_DevPcNoDpdchPro
+ 0x10019091 0xb5 _L1w_DevPcTtiUpdDpchBeta
+ 0x10019146 0x35 _L1w_DevPcBetaEdAllSquareCalc
+ 0x1001917b 0xc _L1w_DevPcSumSquareCalc
+ 0x10019187 0x56 _L1w_DevPcSquareCalc
+ 0x100191dd 0x110 _L1w_DevPcIQMap
+ 0x100192ed 0x1b _L1w_DevPcRangeAdjust
+ 0x10019308 0x32 _L1w_DevPcCalcCm
+ 0x1001933a 0x146 _L1w_DevPcMprCalPro
+ 0x10019480 0x2f _L1w_DevPcMprAdjust
+ 0x100194af 0x39 _L1w_DevPcMprCalCtrl
+ 0x100194e8 0x116 _L1w_DevPcCodeRatioAndTotalPowerCalc
+ 0x100195fe 0x33 _L1w_DevPcPwrValadjust
+ 0x10019631 0x94 _L1w_DevPcGainTorAdjust
+ 0x100196c5 0x89 _L1w_DevPcCalPvalue
+ 0x1001974e 0x3f _L1w_DevPcGaintorHalf
+ 0x1001978d 0x4b _L1w_DevPcMaxPwrSetProc
+ 0x100197d8 0x178 _L1w_DevPcTxAndRfSet
+ 0x10019950 0x54 _L1w_DevPcTpuCallBack
+ 0x100199a4 0x1d _L1w_DevPcRegFrmTpu
+ 0x100199c1 0x88 _L1w_DevPcUlRegTpu
+ 0x10019a49 0x1c _L1w_DevPcIsBeltaEdAllEquReduce
+ 0x10019a65 0xff _L1w_DevPcSetLastBelta
+ 0x10019b64 0x25 _L1w_DevPcPmaxReLimt
+ 0x10019b89 0x7d _L1w_DevPcPmaxReCalc
+ 0x10019c06 0x2d _L1w_DevPcBeltaReCalcBeltaEdReducedMin
+ 0x10019c33 0x43 _L1w_DevPcBeltaReCalcEtfciBoost
+ 0x10019c76 0x97 _L1w_DevPcBeltaReCalc
+ 0x10019d0d 0x21 _L1w_DevPcMaxPowerLimit
+ 0x10019d2e 0x14 _L1w_DevPcMinPowerLimit
+ 0x10019d42 0xe0 _L1w_DevPcCMInfoUpdate
+ 0x10019e22 0x46 _L1w_DevPcFrmEventHandle
+ 0x10019e68 0x51 _L1w_DevPcPreCalc
+ 0x10019eb9 0x63 _L1w_DevPcStopHandle
+ 0x10019f1c 0xdd _L1w_DevPc3SymbolIntHandle
+ 0x10019ff9 0x4d _L1w_DevPcGaintorCalc
+ 0x1001a046 0x46 _L1w_DevPcTpuTpcSlotHandle
+ 0x1001a08c 0x1c _L1w_DevPcSlotModeGet
+ 0x1001a0a8 0x15 _L1w_DevPcDlGapPatternJudge
+ 0x1001a0bd 0x9 _L1w_DevPcWriteCmBitMap
+ 0x1001a0c6 0xa _L1w_DevPcIsUlCmFrm
+ 0x1001a0d0 0x15 _L1w_DevPcIsCmFrmOnlyGap
+ 0x1001a0e5 0x2d _L1w_DevPcIsCmFrm
+ 0x1001a112 0x7a _L1w_DevPcSlotModeSet
+ 0x1001a18c 0x2d _L1w_DevPcUlCmInfoHandle
+ 0x1001a1b9 0x24 _L1w_DevPcDlCmInfoHandle
+ 0x1001a1dd 0x48 _L1w_DevPcCmStopHandle
+ 0x1001a225 0x12 _L1w_DevPcCmStopReqHandle
+ 0x1001a237 0x32 _L1w_DevPcStopReqHandle
+ 0x1001a269 0x11c _L1w_DevPcWriteSubFrmIntInfo
+ 0x1001a385 0x74 _L1w_DevPcReset
+ 0x1001a3f9 0xcb _L1w_DevPcInit
+ 0x1001a4c4 0x7b _L1w_DevPcOutSyncEng
+ 0x1001a53f 0xef _L1w_DevPcEngPrintf
+ 0x1001a62e 0x63 _L1w_DevPcWriteDpramMsg
+ 0x1001a691 0x27 _L1w_DevPcResetCnf
+ 0x1001a6b8 0x27 _L1w_DevPcInitCnf
+ 0x1001a6df 0x2c _L1w_DevRtxPcPrachStartReq
+ 0x1001a70b 0x28 _L1w_DevRtxPcPrachPreambleReq
+ 0x1001a733 0x30 _L1w_DevRtxPcPrachMessageReq
+ 0x1001a763 0x39 _L1w_DevRtxPcDchStartReq
+ 0x1001a79c 0x2c _L1w_DevRtxPcUlDpchCmInfoReq
+ 0x1001a7c8 0x2c _L1w_DevRtxPcDlDpchCmInfoReq
+ 0x1001a7f4 0x29 _L1w_DevRtxPcDpchCmStopReq
+ 0x1001a81d 0x2e _L1w_DevRtxPcBlerReq
+ 0x1001a84b 0x2d _L1w_DevHsdpaPcStartReq
+ 0x1001a878 0x28 _L1w_DevHsdpaPcTtiReq
+ 0x1001a8a0 0x21 _L1w_DevHsdpaPcStoptReq
+ 0x1001a8c1 0x11 _L1w_DevDchPcSetPara
+ 0x1001a8d2 0x2a _L1w_DevHsupaPcStartReq
+ 0x1001a8fc 0x2d _L1w_DevHsupaPcTtiReq
+ 0x1001a929 0x21 _L1w_DevHsupaPcStopReq
+ 0x1001a94a 0x11f _L1w_PcTask
+ .text 0x1001aa69 0x29a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x1001aa69 0x1 _L1w_DevEngInitAddr
+ 0x1001aa6a 0x19 _L1w_EngTaskInit
+ 0x1001aa83 0x7 _L1w_DevEngSetFlag
+ 0x1001aa8a 0x12 _L1w_log_track_init
+ 0x1001aa9c 0x8e _L1w_DevEngDisplay
+ 0x1001ab2a 0x46 _L1w_EngTrace
+ 0x1001ab70 0xaa _L1w_DevEngLogHeaderUpdate
+ 0x1001ac1a 0xc6 _L1w_DevEngWriteDataToBuffer
+ 0x1001ace0 0x22 _L1w_DevEngCopyMem2Dpram
+ 0x1001ad02 0x1 _L1w_DevEngUartTransmit
+ .text 0x1001ad03 0xde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ 0x1001ad03 0x9 _L1w_DevTxFirstTpuIntSet
+ 0x1001ad0c 0xc _L1w_DevTxFirstTpuIntDelete
+ 0x1001ad18 0x82 _L1w_DevRtxTxCfgMsgHandle
+ 0x1001ad9a 0x16 _L1w_DevTxTpuIntHandle
+ 0x1001adb0 0x15 _L1w_DevRtxTxReset
+ 0x1001adc5 0x1c _L1w_DevRtxTxInit
+ .text 0x1001ade1 0x1cc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x1001ade1 0x6b _L1w_DevRtxRxBlindAnalyse
+ 0x1001ae4c 0x77 _L1w_DevRtxRxTfcParaCalc
+ 0x1001aec3 0xd5 _L1w_DevRtxRxJudgeCsRam
+ 0x1001af98 0x115 _L1w_DevRtxRxTrchParaCalc
+ 0x1001b0ad 0x33 _L1w_DevRtxRxDtrCtfcSort
+ 0x1001b0e0 0x81 _L1w_DevRtxRxSccpchDtrParam
+ 0x1001b161 0x3b _L1w_DevRtxRxJudgeRrm
+ 0x1001b19c 0x2f _L1w_DevRtxRxV3BlindTbs49Change
+ 0x1001b1cb 0x25 _L1w_DevRtxRxV3BlindTbsChange
+ 0x1001b1f0 0xc4 _L1w_DevRtxRxV3BlindTfcPatch
+ 0x1001b2b4 0xd2 _L1w_DevRtxRxDpchDtrParam
+ 0x1001b386 0x11 _L1w_DevRtxRxTtiModeGet
+ 0x1001b397 0xe _L1w_DevRtxRxCrcModeGet
+ 0x1001b3a5 0x16 _L1w_DevRtxRxCodingGet
+ 0x1001b3bb 0x89 _L1w_DevRtxRxTrchInfoCfg
+ 0x1001b444 0x51 _L1w_DevRtxRxDpchDtrCmCfg
+ 0x1001b495 0x74 _L1w_DevRtxRxDlDpchDtrCfg
+ 0x1001b509 0x6d _L1w_DevRtxRxDlSccpchDtrCfg
+ 0x1001b576 0x36 _L1w_DevRtxRxAgchDtrCfg
+ 0x1001b5ac 0x83 _L1w_DevRtxRxAgchCmDtrCfg
+ 0x1001b62f 0x45 _L1w_DevRtxRxCfgABUpdate
+ 0x1001b674 0x34 _L1w_DevRtxRxDeilBaseSort
+ 0x1001b6a8 0x9f _L1w_DevRtxRxTfciS2Cfg
+ 0x1001b747 0xb1 _L1w_DevRtxRxTfcAnalyse
+ 0x1001b7f8 0x58 _L1w_DevRtxRxBlindGuidCfg
+ 0x1001b850 0x37 _L1w_DevRtxRxPn9BerCheckStart
+ 0x1001b887 0xa1 _L1w_DevRtxRxPn9Get244Bit
+ 0x1001b928 0x42 _L1w_DevRtxRxPn9BerRltReport
+ 0x1001b96a 0xc5 _L1w_DevRtxRxPn9DataCheck
+ 0x1001ba2f 0x81 _L1w_DevRtxRxAllBlindHandle
+ 0x1001bab0 0xda _L1w_DevRtxRxBlindDtrCfg
+ 0x1001bb8a 0x17a _L1w_DevRtxRxBlindCrcHandle
+ 0x1001bd04 0xc3 _L1w_DevRtxRxBlindDataHandle
+ 0x1001bdc7 0x21 _L1w_DevRtxRxBlindStateCheck
+ 0x1001bde8 0xeb _L1w_DevRtxRxBlindTfcAnalyse
+ 0x1001bed3 0x3a _L1w_DevRtxRxTfcDataCmpHandle
+ 0x1001bf0d 0x38 _L1w_DevRtxRxTfciFWHT
+ 0x1001bf45 0x126 _L1w_DevRtxRxTfciCoding
+ 0x1001c06b 0x1f1 _L1w_DevRtxRxTfciIntHandle
+ 0x1001c25c 0x18 _L1w_DevRtxRxGetGsmVal
+ 0x1001c274 0x76 _L1w_DevRtxRxCmpPchUeId
+ 0x1001c2ea 0x55 _L1w_DevRtxRxPchUeIdHandle
+ 0x1001c33f 0x114 _L1w_DevRtxRxTtiBlindHandle
+ 0x1001c453 0xab _L1w_DevRtxRxTrchCrcStatic
+ 0x1001c4fe 0xbd _L1w_DevRtxRxTtiCrcStatic
+ 0x1001c5bb 0xb _L1w_DevRtxRxTtiCrcStatForAfc
+ 0x1001c5c6 0x63 _L1w_DevRtxRxTtiTrchInfoHandle
+ 0x1001c629 0x8d _L1w_DevRtxRxTtiBdTrchInfoHandle
+ 0x1001c6b6 0x64 _L1w_DevRtxRxNoBdTtiHandle
+ 0x1001c71a 0x54 _L1w_DevRtxRxBlindTtiHandle
+ 0x1001c76e 0x49 _L1w_DevRtxRxPchTtiHandle
+ 0x1001c7b7 0x68 _L1w_DevRtxRxTtiIntAfterHandle
+ 0x1001c81f 0x25e _L1w_DevRtxRxTtiIntHandle
+ 0x1001ca7d 0x24 _L1w_DevRtxRxDtrRel
+ .text 0x1001caa1 0x5db T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ 0x1001caa1 0x8b _L1w_DevHsdpaCqiCalcPos
+ 0x1001cb2c 0x1b1 _L1w_DevHsdpaCalcCqiSnr
+ 0x1001ccdd 0x6b _L1w_DevHsdpaSnrLimitAdj
+ 0x1001cd48 0xbf _L1w_DevHsdpaCqiSnrAdj
+ 0x1001ce07 0x68 _L1w_DevHsdpaCalcSnrVal
+ 0x1001ce6f 0x20d _L1w_DevHsdpaSnrMapToCqiVal
+ .text 0x1001d07c 0x2f5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ 0x1001d07c 0x5b _L1w_DevRtxRxPcchBitRead
+ 0x1001d0d7 0x3e _L1w_DevRtxRxImsiGsm
+ 0x1001d115 0x2f _L1w_DevRtxRxTmsiGsm
+ 0x1001d144 0x2f _L1w_DevRtxRxPTmsiGsm
+ 0x1001d173 0xf _L1w_DevRtxRxImsiDs41
+ 0x1001d182 0xf _L1w_DevRtxRxTmsiDs41
+ 0x1001d191 0x3d _L1w_DevRtxRxPagRecCnId
+ 0x1001d1ce 0x44 _L1w_DevRtxRxPagRecUtranId
+ 0x1001d212 0x4e _L1w_DevRtxRxPagRec2UtranSingUeId
+ 0x1001d260 0x28 _L1w_DevRtxRxPagRec2UtranGrpId
+ 0x1001d288 0x28 _L1w_DevRtxRxPagingRecList
+ 0x1001d2b0 0x28 _L1w_DevRtxRxPagingRec2ListR5
+ 0x1001d2d8 0x12 _L1w_DevRtxRxPagingV590ExtIE
+ 0x1001d2ea 0x10 _L1w_DevRtxRxPagingV860ExtIE
+ 0x1001d2fa 0x47 _L1w_DevRtxRxPagingType1
+ 0x1001d341 0x19 _L1w_DevRtxRxPcchMsgType
+ 0x1001d35a 0x17 _L1w_DevRtxRxDecodePcch
+ .text 0x1001d371 0x18da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x1001d371 0x22 _L1w_HspaCalcMod
+ 0x1001d393 0xb _L1w_DevHsupaEdchReadyInit
+ 0x1001d39e 0x11 _L1w_DevHsupaInitUlDataInfo
+ 0x1001d3af 0x18 _L1w_DevHsupaUlReset
+ 0x1001d3c7 0x5c _L1w_DevHsupaParaInit
+ 0x1001d423 0x45 _L1w_DevHsupaInit
+ 0x1001d468 0x15 _L1w_DevHsupaHwRel
+ 0x1001d47d 0x8f _L1w_DevHsupaReset
+ 0x1001d50c 0x5f _L1w_DevHsupaGetDlChanInfo
+ 0x1001d56b 0x34 _L1w_DevHsupaCalcDisEagchEdch
+ 0x1001d59f 0x10 _L1w_DevHsupaCalcDisEhichEdch
+ 0x1001d5af 0x21 _L1w_DevHsupaCalcDisErgchEdch
+ 0x1001d5d0 0x1a _L1w_DevHsupaCalcInitNo
+ 0x1001d5ea 0x3a _L1w_DevHsupaCalcInitSwNo
+ 0x1001d624 0x64 _L1w_DevHsupaCalcIscpSlotId
+ 0x1001d688 0x9a _L1w_DevHsupaCalcDlChanInitNo
+ 0x1001d722 0x5e _L1w_DevHsupaConfigReq
+ 0x1001d780 0x2b _L1w_DevHsupaCpEdpdchInfo
+ 0x1001d7ab 0x3d _L1w_DevHsupaCpErntiInfo
+ 0x1001d7e8 0x65 _L1w_DevHsupaCpRxEagchCfg
+ 0x1001d84d 0x42 _L1w_DevHsupaRtxEagchCfg
+ 0x1001d88f 0x8 _L1w_DevHsupaGetErgchFrameType
+ 0x1001d897 0x7e _L1w_DevHsupaCpRxRgHiCfg
+ 0x1001d915 0x77 _L1w_DevHsupaRtxRgHiCfg
+ 0x1001d98c 0x23 _L1w_DevHsupaRtxCfg
+ 0x1001d9af 0xca _L1w_DevHsupaCpDlRcvInfo
+ 0x1001da79 0x20 _L1w_DevHsupaCfgTxInit
+ 0x1001da99 0x22 _L1w_DevHsupaEagchInt2Ps
+ 0x1001dabb 0x97 _L1w_DevHsupaCalAgRgHiIntNo
+ 0x1001db52 0x4f _L1w_DevHsupaNorm2TpuBase
+ 0x1001dba1 0x79 _L1w_DevHsupaFachNt2CfnTime
+ 0x1001dc1a 0x84 _L1w_DevHsupaSaveTpuTime
+ 0x1001dc9e 0x2d _L1w_DevHsupaCalcSwTtiCntIntOff
+ 0x1001dccb 0x73 _L1w_DevHsupaGetCfnTime
+ 0x1001dd3e 0x25 _L1w_DevHsupaCalcSwTtiCntIntOn
+ 0x1001dd63 0x114 _L1w_DevHsupaEagchIntProc
+ 0x1001de77 0x18 _L1w_DevHsupaEagchIntInd
+ 0x1001de8f 0x4c _L1w_DevHuspaSaveAG
+ 0x1001dedb 0x12 _L1w_DevHuspaUpaTransFlgToMac
+ 0x1001deed 0x1c _L1w_DevHuspaGrantHarqToMac
+ 0x1001df09 0xb9 _L1w_DevHsupaReportPsStatistic
+ 0x1001dfc2 0x65 _L1w_DevHsupaStdlogThroughput
+ 0x1001e027 0x82 _L1w_DevHsupaStdlogPacketInfo
+ 0x1001e0a9 0x40 _L1w_DevHsupaReportToMac
+ 0x1001e0e9 0x71 _L1w_DevHsupaRptHarqFlag
+ 0x1001e15a 0x5b _L1w_DevHsupaDchIsMacTrans
+ 0x1001e1b5 0x14 _L1w_DevHsupaFachIsMacTrans
+ 0x1001e1c9 0x22 _L1w_DevHsupaIsMacTrans
+ 0x1001e1eb 0x37 _L1w_DevHsupaPcCfg
+ 0x1001e222 0x1 _L1w_DevHsupaAgRgHiIndCallBack
+ 0x1001e223 0x3a _L1w_DevHsupaAddTpu
+ 0x1001e25d 0x9 _L1w_DevHsupaGetPhyMinSfMaxChan
+ 0x1001e266 0x9e _L1w_DevHsupaDisplayCfgInfo
+ 0x1001e304 0x6a _L1w_DevHsupaSaveStdlogPacket
+ 0x1001e36e 0x35 _L1w_DevHsupaCfgToPsrInd
+ 0x1001e3a3 0x125 _L1w_DevHsupaConfigProc
+ 0x1001e4c8 0x2c _L1w_DevHsupaIcpIntInd
+ 0x1001e4f4 0x2c _L1w_DevHsupaEdcpIntInd
+ 0x1001e520 0x59 _L1w_DevHsupaIcpIntProc
+ 0x1001e579 0xea _L1w_DevHsupaEdcpIntProc
+ 0x1001e663 0x26 _L1w_DevHsupaCfgPcTti
+ 0x1001e689 0x2c _L1w_DevHsupaEtxIntInd
+ 0x1001e6b5 0x2d _L1w_DevHsupaCalcNtx1Info
+ 0x1001e6e2 0x23 _L1w_DevHsupaCmInfoClr
+ 0x1001e705 0xf1 _L1w_DevHsupaEtxIntProc
+ 0x1001e7f6 0x21 _L1w_DevHsupaRelReq
+ 0x1001e817 0xf _L1w_DevHsupaRtxRelReq
+ 0x1001e826 0x4e _L1w_DevHsupaReleaseProc
+ 0x1001e874 0xc _L1w_DevHsupaIfHarqIdValid
+ 0x1001e880 0x66 _L1w_DevHsupaTestCurFrameNum
+ 0x1001e8e6 0x37 _L1w_DevHsupaCalcEdchCfn
+ 0x1001e91d 0x2a _L1w_DevHsupaGetCurFrameNum
+ 0x1001e947 0x2d _L1w_DevHsupaCalcNextTtiFrameNum
+ 0x1001e974 0x2b _L1w_DevHsupaCmPatternUpdateReq
+ 0x1001e99f 0x5c _L1w_DevHsupaCalcDlCm
+ 0x1001e9fb 0x69 _L1w_DevHsupaCmPatternUpdateProc
+ 0x1001ea64 0x31 _L1w_DevHsupaCalChLen
+ 0x1001ea95 0x7 _L1w_DevHsupaSetHsdschCfg
+ 0x1001ea9c 0x77 _L1w_DevHsupaActive
+ 0x1001eb13 0xf1 _L1w_DevHsupaTpuProc
+ 0x1001ec04 0x3b _L1w_DevHsupaTransIndProc
+ 0x1001ec3f 0xc _L1w_DevHsupaIsDchActive
+ .text 0x1001ec4b 0x18b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ 0x1001ec4b 0xb _L1w_DevRtxRxIntDataInit
+ 0x1001ec56 0x13 _L1w_DevRtxRxIntReset
+ 0x1001ec69 0x12 _L1w_DevRtxRxFix2Sword32
+ 0x1001ec7b 0x13 _L1w_DevRtxRxFix2Sword16
+ 0x1001ec8e 0x6e _L1w_DevRtxRxRcvFingerSlotwt
+ 0x1001ecfc 0x38 _L1w_DevRtxRxRcvFingerAfc
+ 0x1001ed34 0x5b _L1w_DevRtxRxRcvFingerNoise
+ 0x1001ed8f 0x27 _L1w_DevRtxRxCalcFingerIscp
+ 0x1001edb6 0x9c _L1w_DevRtxRxRcvOffLInePiResult
+ 0x1001ee52 0x88 _L1w_DevRtxRxRcvPiData
+ 0x1001eeda 0xcc _L1w_DevRtxRxPichIntHandle
+ 0x1001efa6 0x25 _L1w_DevRtxRxGetBuffIdx
+ 0x1001efcb 0xb2 _L1w_DevRtxRxRcvAiData
+ 0x1001f07d 0xdd _L1w_DevRtxRxCalcAiCpichPower
+ 0x1001f15a 0x51 _L1w_DevRtxRxCalcAiCpichPrIIR
+ 0x1001f1ab 0x10 _L1w_DevRtxRxGetAiDeltaPac
+ 0x1001f1bb 0x31 _L1w_DevRtxRxCalcAiThreshold
+ 0x1001f1ec 0x24 _L1w_DevRtxRxCalcAiSignCorr
+ 0x1001f210 0x26 _L1w_DevRtxRxCalcAiVal
+ 0x1001f236 0x26 _L1w_DevRtxRxAiDataPreHandle
+ 0x1001f25c 0x2e _L1w_DevRtxRxEAiResCfgMap
+ 0x1001f28a 0x4b _L1w_DevRtxRxNewCalcAiVal
+ 0x1001f2d5 0x5e _L1w_DevRtxRxNewEAiCalc
+ 0x1001f333 0x122 _L1w_DevRtxRxNewAichIntHandle
+ 0x1001f455 0x2b _L1w_DevRtxRxCalcFbiFingerPr
+ 0x1001f480 0x34 _L1w_DevRtxRxCalcFbiRlPr
+ 0x1001f4b4 0xed _L1w_DevRtxRxCalcFbiTotalPr
+ 0x1001f5a1 0x23 _L1w_DevRtxRxCalcFbiValue
+ 0x1001f5c4 0xc6 _L1w_DevRtxRxCalcFbi
+ 0x1001f68a 0x4a _L1w_DevRtxRxIntParaUpdate
+ 0x1001f6d4 0x6 _L1w_DevRtxRxGetTpcIData
+ 0x1001f6da 0x5 _L1w_DevRtxRxGetTpcQData
+ 0x1001f6df 0x6 _L1w_DevRtxRxGetTpcIExp
+ 0x1001f6e5 0x5 _L1w_DevRtxRxGetTpcQExp
+ 0x1001f6ea 0x58 _L1w_DevRtxRxDchTpcSirCalc
+ 0x1001f742 0xcf _L1w_DevRtxRxDchTpcIntHandle
+ 0x1001f811 0x9 _L1w_DevRtxRxDchPilotIntHandle
+ 0x1001f81a 0x6f _L1w_DevRtxRxFdpchTpcIntHandle
+ 0x1001f889 0x46 _L1w_DevRtxRxTpcIntHandle
+ 0x1001f8cf 0x4c _L1w_DevRtxRxFactorCheck
+ 0x1001f91b 0x84 _L1w_DevRtxRxFactorDataGet
+ 0x1001f99f 0x44 _L1w_DevRtxRxFactorHandle
+ 0x1001f9e3 0x61 _L1w_DevRtxRxAgchFactorHandle
+ 0x1001fa44 0x50 _L1w_DevRtxRxSccpchFactorCalc
+ 0x1001fa94 0x13b _L1w_DevRtxRxPchFactorHandle
+ 0x1001fbcf 0x109 _L1w_DevRtxRxFachFactorHandle
+ 0x1001fcd8 0x2f _L1w_DevRtxRxCalcIscp
+ 0x1001fd07 0x1dd _L1w_DevRtxRxFingerDataHandle
+ 0x1001fee4 0x8a _L1w_DevRtxRxNoiseDataCheck
+ 0x1001ff6e 0x67 _L1w_DevRtxRxSetAfcInfo
+ 0x1001ffd5 0x119 _L1w_DevRtxRxCpich2ndFingerPrint
+ 0x100200ee 0xf3 _L1w_DevRtxRxCpichTpuIntPrint
+ 0x100201e1 0xea _L1w_DevRtxRxCpichTpuIntAllPrint
+ 0x100202cb 0x5a _L1w_DevRtxRxCpichTpuIntIscpErrPrint
+ 0x10020325 0x45 _L1w_DevRtxRxCpichTpuIntUpaParaUpdate
+ 0x1002036a 0x167 _L1w_DevRtxRxCpichTpuIntHandle
+ 0x100204d1 0x1 _L1w_DevRtxRxPilotIntHandle
+ 0x100204d2 0x2c _L1w_DevRtxRxIntHandle
+ .text 0x100204fe 0x3556 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x100204fe 0x5 _L1w_DevDlsPsrReset
+ 0x10020503 0xb8 _L1w_DevDlsintialGlobalVariable
+ 0x100205bb 0x30 _L1w_DevDlsPsrIntialHardWare
+ 0x100205eb 0x8 _L1w_DevDlsPsrIntial
+ 0x100205f3 0xd _L1w_DevDlsSaveOldUlTiming
+ 0x10020600 0x64 _L1w_DevDlsStop
+ 0x10020664 0x3a _L1w_DevPsrIntEventProc
+ 0x1002069e 0x35 _L1w_DevPsrSendTimingInfoToL1s
+ 0x100206d3 0x3d _L1w_DevPsrAddTpuFixedEvent
+ 0x10020710 0x27 _L1w_DevPsrDchStopReq
+ 0x10020737 0x39 _L1w_DevPsrMeasStartReq
+ 0x10020770 0x12d _L1w_DevPsrDchJudgeNcellSave
+ 0x1002089d 0x177 _L1w_DevPsrSetRlNcellFlag
+ 0x10020a14 0x36 _L1w_DevPsrEfachStartReq
+ 0x10020a4a 0x32 _L1w_DevPsrEfachFdpchOffsetReq
+ 0x10020a7c 0x22 _L1w_DevPsrEfachStopReq
+ 0x10020a9e 0x25 _L1w_DevPsrFmoStopReq
+ 0x10020ac3 0x3b _L1w_DevDlsPsrHsdpaReq
+ 0x10020afe 0x32 _L1w_DevPsrDchUpaExistReq
+ 0x10020b30 0x6c _L1w_DevPsrEfachUlDpcchFBConfig
+ 0x10020b9c 0x54 _L1w_DevPsrUlDpcchFBConfig
+ 0x10020bf0 0x1 _L1w_DevPsrCommParaCfg
+ 0x10020bf1 0x3c _L1w_DevPsrSaveCmInfo
+ 0x10020c2d 0x21 _L1w_DevPsrTransDpchCm2Cpich
+ 0x10020c4e 0xa8 _L1w_DevPsrRtxFirstFingerConfigS
+ 0x10020cf6 0x196 _L1w_DevPsrSelectMasterRl
+ 0x10020e8c 0x6c _L1w_DevPsrSaveLastTimingTrace
+ 0x10020ef8 0x110 _L1w_DevPsrDchSelectUpaCell
+ 0x10021008 0x160 _L1w_DevPsrDchConfigHardware
+ 0x10021168 0xf8 _L1w_DevPsrDchReqConfig
+ 0x10021260 0xfa _L1w_DevPsrHardWorkTimeConfig
+ 0x1002135a 0x53 _L1w_DevPsrRlPosAndCodeConfig
+ 0x100213ad 0xc8 _L1w_DevPsrFachReqConfig
+ 0x10021475 0x29 _L1w_DevDlsCalcHandOverNtAdjPos
+ 0x1002149e 0x2f _L1w_DevDlsCalcAdjPos
+ 0x100214cd 0x1d9 _L1w_DevDlsCalcRegConfigTimingAndReport
+ 0x100216a6 0x15a _L1w_DevDlsCalcRlTimingAndReport
+ 0x10021800 0x58 _L1w_DevDlsPsrUpdateULInfo
+ 0x10021858 0x125 _L1w_DevDlsFachTimingMaintain
+ 0x1002197d 0x1c _L1w_DevDlsTimingMaintain
+ 0x10021999 0x34 _L1w_DevDlsDchJudgeAdustSpeed
+ 0x100219cd 0x42 _L1w_DevDlsDchTimingMaintain
+ 0x10021a0f 0x48 _L1w_DevDlsPsrSelectDpaId
+ 0x10021a57 0x63 _L1w_DevDlsPsrChangeDpaIdCell
+ 0x10021aba 0xc8 _L1w_DevDlsPsrGetAntNumAndJudgeConfig
+ 0x10021b82 0xa _L1w_DevDlsPsrClearCopyFingernfo
+ 0x10021b8c 0x3a _L1w_DevDlsPsrDpaIsChangjing1
+ 0x10021bc6 0x11a _L1w_DevDlsPsrJudgeFingerOver512
+ 0x10021ce0 0x2df _L1w_DevDlsPsrWholeHandleS
+ 0x10021fbf 0x24 _L1w_DevPsrTpuIntHandle
+ 0x10021fe3 0x4a _L1w_DevPsrRlCpichTimingAdujst
+ 0x1002202d 0x5b _L1w_DevPsrSoftHandOverTimingAdj
+ 0x10022088 0x5a _L1w_DevPsrIsCmCfgBug
+ 0x100220e2 0x66 _L1w_DevPsrCmHandle
+ 0x10022148 0x50 _L1w_DevPsrCalcRlsTxRxTimeDiff
+ 0x10022198 0x9a _L1w_DevPsrTimingAdj
+ 0x10022232 0x182 _L1w_DevPsrUpdateRlPos
+ 0x100223b4 0x53 _L1w_DevPsrFmoHandle
+ 0x10022407 0x170 _L1w_DevPsrRdPeakInfoS
+ 0x10022577 0xaf _L1w_DevDlsPsrSidelobeSurp
+ 0x10022626 0x10 _L1w_DevDlsPsrFingerSidelobeSurp
+ 0x10022636 0xb2 _L1w_DevDlsPsrCorasePathDetect
+ 0x100226e8 0x3d _L1w_DevDlsPsrFindStrongFiger
+ 0x10022725 0x46 _L1w_DevDlsPsrUpdateFigerTable
+ 0x1002276b 0x152 _L1w_DevDlsPsrStrongFigerPathDetect
+ 0x100228bd 0x149 _L1w_DevDlsPsrPathDect
+ 0x10022a06 0x3b _L1w_DevPsrRssiNormal
+ 0x10022a41 0x99 _L1w_DevDlsPsrUpdateFingerPos
+ 0x10022ada 0x12 _L1w_DevDlsPsrCalcMrtrDiff
+ 0x10022aec 0x23 _L1w_DevDlsPsrCalcMrtrAver
+ 0x10022b0f 0x31 _L1w_DevDlsPsrSortMinRange
+ 0x10022b40 0x31 _L1w_DevDlsPsrSortMinRange1
+ 0x10022b71 0x70 _L1w_DevDlsPsrSynProtect
+ 0x10022be1 0x24 _L1w_DevPsrBackWardProtect
+ 0x10022c05 0x26 _L1w_DevPsrForwardProtect
+ 0x10022c2b 0x19b _L1w_DevDlsPsrFingerPeakUpdate
+ 0x10022dc6 0x18 _L1w_DevPsrSortMinValue
+ 0x10022dde 0x18 _L1w_DevDlsPsrSortMaxValue
+ 0x10022df6 0x14c _L1w_DevPsrCandidatefingerUpdate
+ 0x10022f42 0xb3 _L1w_DevDlsPsrFingerPeakSelect
+ 0x10022ff5 0x72 _L1w_DevDlsPsrCalcDpchTiming
+ 0x10023067 0x2f _L1w_DevPsrFinPeakNormal
+ 0x10023096 0x38 _L1w_DevPsrAntFinPeakNormal
+ 0x100230ce 0x3b _L1w_DevDlsPsrSelectValidFinger
+ 0x10023109 0x98 _L1w_DevDlsPsrCalcDpchBaseTiming
+ 0x100231a1 0x47 _L1w_DevDlsPsrSortRtxFinger
+ 0x100231e8 0xb _L1w_DevPsrGetDchStartPsrFlag
+ 0x100231f3 0x150 _L1w_DevDlsPsrSelectRtxFinger
+ 0x10023343 0x93 _L1w_DevDlsPsrSelectNcellFinger
+ 0x100233d6 0xc8 _L1w_DevDlsPsrSortDpaFirst
+ 0x1002349e 0xf6 _L1w_DevDlsPsrNewFingerMapping
+ 0x10023594 0xd4 _L1w_DevDlsPsrAdrWindowUpdateS
+ 0x10023668 0xc _L1w_DevDlsPsrSendAdrFingerInfoS
+ 0x10023674 0xd0 _L1w_DevPsrSelSeaWindowFinInfoS
+ 0x10023744 0x47 _L1w_DevPsrSelNewSearchWindowS
+ 0x1002378b 0x21 _L1w_DevPsrIsSearchWindowPath
+ 0x100237ac 0x28 _L1w_DevPsrCalcSearchWindowSum
+ 0x100237d4 0x15 _L1w_DevDlsPsrCalcFingerPeakSum
+ 0x100237e9 0x38 _L1w_DevPsrSortFirstFinger
+ 0x10023821 0x23 _L1w_DevDlscalcPosOff
+ 0x10023844 0x1e3 _L1w_DevDlsChangedMasterRlTiming
+ 0x10023a27 0x13 _L1w_DevDlsPsrFingerCmp
+ 0x10023a3a 0x12 _L1w_DevDlsPsrFingerLessThan
+ 0x10023a4c 0x8 _TestZero
+ .text 0x10023a54 0x5c1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ 0x10023a54 0x8 _L1w_DevHsupaFachFdpchOffset
+ 0x10023a5c 0xb _L1w_DevHsupaIsEfachActive
+ 0x10023a67 0x35 _L1w_DevHsupaRtxEdchResInd
+ 0x10023a9c 0x16 _L1w_DevHsupaFachToPsrInd
+ 0x10023ab2 0x52 _L1w_DevHsupaFachConfigReq
+ 0x10023b04 0x3c _L1w_DevHsupaFachCpErntiInfo
+ 0x10023b40 0xa5 _L1w_DevHsupaFachConfigProc
+ 0x10023be5 0x21 _L1w_DevHsupaFachRelReq
+ 0x10023c06 0x46 _L1w_DevHsupaFachRelProc
+ 0x10023c4c 0x26 _L1w_DevHsupaErntiUpdateReq
+ 0x10023c72 0x24 _L1w_DevHsupaErntiUpdateProc
+ 0x10023c96 0x21 _L1w_DevHsupaFachNoDataReq
+ 0x10023cb7 0x7e _L1w_DevHsupaFachNoDataProc
+ 0x10023d35 0x96 _L1w_DevHsupaFachGetRgHiChanInfo
+ 0x10023dcb 0x4a _L1w_DevHsupaFachCfn2NetTime
+ 0x10023e15 0x9b _L1w_DevHsupaFachAddTpu2ms
+ 0x10023eb0 0x6b _L1w_DevHsupaFachAddTpu10ms
+ 0x10023f1b 0x22 _L1w_DevHsupaFachAddTpu
+ 0x10023f3d 0xe _L1w_DevHsupaFachIsMacInitTrans
+ 0x10023f4b 0x1d _L1w_DevHsupaFachAddTpuSubInt
+ 0x10023f68 0x88 _L1w_DevHsupaFachEdchResProc
+ 0x10023ff0 0x25 _L1w_DevHsupaFachReset
+ .text 0x10024015 0x182d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x10024015 0x21 _L1w_SetWmodeLpcMacroValue
+ 0x10024036 0x8 _L1w_DevSleepSetCfunFlg
+ 0x1002403e 0x13 _L1w_PosCmp
+ 0x10024051 0x1c _L1w_DevLpcDvfs
+ 0x1002406d 0x2b _L1W_DevSleepLpmInspectInit
+ 0x10024098 0x87 _L1w_DevUeTurnOn3sNoLpc
+ 0x1002411f 0xe _l1w_DevLpcSetAdjLpmFrmIntFlg
+ 0x1002412d 0xe _l1w_DevLpcGetAdjLpmFrmIntFlg
+ 0x1002413b 0xf _L1w_DevLpcSetSleepSubSt
+ 0x1002414a 0x10 _L1w_DevLpcGetSleepFlg
+ 0x1002415a 0x85 _L1w_DevLpcDpaRecover
+ 0x100241df 0x1f _L1w_DevLpcDrxRecover
+ 0x100241fe 0x93 _L1w_DevLpcClkDevCtrl
+ 0x10024291 0x3d _l1w_DevLpcClkInit
+ 0x100242ce 0x9e _L1w_DevLpcPwrDevCtrl
+ 0x1002436c 0x2d _l1w_DevLpcPwrInit
+ 0x10024399 0x7d _L1w_DevSleepNoLpc
+ 0x10024416 0xa2 _L1w_DevLpcLpmIntCheck
+ 0x100244b8 0x124 _L1w_DevLpcSendIcp
+ 0x100245dc 0x10 _L1w_DevLpcGetWakeUpType
+ 0x100245ec 0x2f _L1w_LpcRegionJudge
+ 0x1002461b 0x4a _L1w_DevLpcSerIdleLen
+ 0x10024665 0x6 _L1w_LpcGetLpcDbAddress
+ 0x1002466b 0x23 _L1w_LpcCalcLen
+ 0x1002468e 0x46 _L1w_LpcPosMove
+ 0x100246d4 0xb5 _L1w_DevLpcCalPreSyncInfo
+ 0x10024789 0x43 _L1w_DevLpcIsPiPchOffsetLen
+ 0x100247cc 0x1ac _L1w_SchedGapGetSleepEnLen
+ 0x10024978 0x77 _L1w_DevLpcCalSleepInfo
+ 0x100249ef 0x7b _L1W_DevLpcGetWSleepLen
+ 0x10024a6a 0x92 _L1w_DevLpcUpdateWakeFlg
+ 0x10024afc 0x14e _L1w_DevLpcSyncWkUpOpenRf
+ 0x10024c4a 0xa _L1w_DevSleepGetPiEndPos
+ 0x10024c54 0x7d _L1W_LPNoSleepAPeriod
+ 0x10024cd1 0x8f _L1W_DevLpcPwrPrintInfo
+ 0x10024d60 0x18 _L1w_DevSleepCloseIsAbleSleep
+ 0x10024d78 0x2a9 _L1W_DevSleepLpmInspect
+ 0x10025021 0x4f _L1w_DevLpcWakeTimeCheck
+ 0x10025070 0x9 _L1W_LPNoSleepEndSsfnInit
+ 0x10025079 0x5e _L1W_LPDataInit
+ 0x100250d7 0x71 _L1W_LPInit
+ 0x10025148 0x37 _L1W_LpcCfgSocWkupInt
+ 0x1002517f 0x1b _L1W_LpcDisSocWkupInt
+ 0x1002519a 0x16 _L1W_WakeupIsr
+ 0x100251b0 0x8 _L1W_GetNtSsfn
+ 0x100251b8 0x4 _L1w_DevSleepPreSyncPiOffset
+ 0x100251bc 0xd _L1W_DevSleepQueryAllowbit
+ 0x100251c9 0x335 _L1W_ModemLpcSleep
+ 0x100254fe 0x344 _L1W_ModemLpcWakeup
+ .text 0x10025842 0x1519 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x10025842 0x39 _L1w_DevDlsAfcReset
+ 0x1002587b 0x19 _L1w_DevDlsAfcInit
+ 0x10025894 0x56 _L1w_DevAfcBchCorrCalEachSlot
+ 0x100258ea 0x23 _L1w_DevAfcNormalToAfc
+ 0x1002590d 0x20 _L1w_DevAfcToNormal
+ 0x1002592d 0xf _L1w_DevAfcFormatCheck
+ 0x1002593c 0x6 _L1w_DevAfcSubFunc1ForAdd
+ 0x10025942 0x27 _L1w_DevAfcSubFunc2ForAdd
+ 0x10025969 0x75 _L1w_DevAfcAdd
+ 0x100259de 0x60 _L1w_DevAfcDiv
+ 0x10025a3e 0x24 _L1w_DevAfcMultip
+ 0x10025a62 0xf _L1w_DevAfcCompABS
+ 0x10025a71 0xfe _L1w_DevAfcCalcPhaseErr
+ 0x10025b6f 0x36 _L1w_DevAfcCalcFreqcenErr
+ 0x10025ba5 0x1c _L1w_DevAfcLockCheck
+ 0x10025bc1 0xa6 _L1w_DevAfcBchFoePostProc
+ 0x10025c67 0x44 _L1w_DevDlsAfcResultValid
+ 0x10025cab 0x31 _L1w_DevAfcFoeAdjResultLim
+ 0x10025cdc 0x42 _L1w_DevAfcFoeResultLimit
+ 0x10025d1e 0x1c _L1w_DevAfcIQFilterProc
+ 0x10025d3a 0x72 _L1w_DevAfcForBchProc
+ 0x10025dac 0x26 _L1w_DevAfcStateTransfer
+ 0x10025dd2 0x64 _L1w_DevAfcRxFoePostProc
+ 0x10025e36 0x13 _L1w_DevAfcCalcFingerPower
+ 0x10025e49 0xab _L1w_DevAfcFingerFoeAdp
+ 0x10025ef4 0x7b _L1w_DevAfcFingerSortByPeak
+ 0x10025f6f 0x27b _L1w_DevAfcForRxProc
+ 0x100261ea 0x27 _L1w_DevAfcSendFreqMsgToL1s
+ 0x10026211 0x29 _L1w_DevAfcBchReq
+ 0x1002623a 0x2c _L1w_DevAfcRxReq
+ 0x10026266 0x26 _L1w_DevAfcRxCrcFlagReq
+ 0x1002628c 0x28 _L1w_DevAfcStateChangeReq
+ 0x100262b4 0x97 _L1w_DevAfcRxDataAccu
+ 0x1002634b 0xa _L1w_DevAfcVcoTimeSet
+ 0x10026355 0xb5 _L1w_DevAfcCalcParam
+ 0x1002640a 0xd _L1w_DevAfcIsInStableSt
+ 0x10026417 0x11 _L1w_DevAfcRxCrcFlagProc
+ 0x10026428 0x37 _L1w_DevAfcLockHandle
+ 0x1002645f 0x4d _L1w_DevAfcNeedAdj
+ 0x100264ac 0x72 _L1w_DevAfcSaveStableVco
+ 0x1002651e 0x21 _L1w_DevAfcMasteStChange
+ 0x1002653f 0x11 _L1w_DevAfcGetRxCrc
+ 0x10026550 0x31 _L1w_DevAfcGetAfcCellEcIo
+ 0x10026581 0x43 _L1w_DevAfcRxDataReqProc
+ 0x100265c4 0x52 _L1w_DevAfcGetNCellAfcPt
+ 0x10026616 0xa _L1w_DevAfcGetSystemAfc
+ 0x10026620 0xb _L1w_DevAfcGetNCellAbsAfc
+ 0x1002662b 0x1b _L1w_DevAfcGetNCellRelativeAfc
+ 0x10026646 0x58 _L1w_DevAfcUpdateNCellAfc
+ 0x1002669e 0x8 _L1w_DevAfcSetWorkCellInfo
+ 0x100266a6 0xa _L1w_DevAfcGetWorkCellInfo
+ 0x100266b0 0x50 _L1w_DevAfcIsSystemAfc
+ 0x10026700 0xa2 _L1w_DevAfcNcellAfcPostProc
+ 0x100267a2 0x3 _L1w_DevAfcSetNCellAbsAfc
+ 0x100267a5 0xa5 _L1w_DevAfcRlsAloneProc
+ 0x1002684a 0x131 _L1w_DevAfcCalcRlOwnFoe
+ 0x1002697b 0xf _L1w_DevAfcClearNcellAfc
+ 0x1002698a 0x1e _L1w_DevAfcCalcFilterPara
+ 0x100269a8 0x66 _L1w_DevAfcDpaIqRotateProc
+ 0x10026a0e 0x1d _L1w_DevAfcNcellAdjLimit
+ 0x10026a2b 0xc _L1w_DevAfcNormDiffValue
+ 0x10026a37 0x11 _L1w_DevAfcSaveDpaInfo
+ 0x10026a48 0x38 _L1w_DevAfcSetDpaIqRotate
+ 0x10026a80 0x4f _L1w_DevAfcCalcSlotWeight
+ 0x10026acf 0x15 _L1w_DevAfcInitNcellData
+ 0x10026ae4 0x2e _L1w_DevAfcNcellUpByEcIo
+ 0x10026b12 0x1f _L1w_DevAfcRestartReq
+ 0x10026b31 0x22 _L1w_DevAfcRestartLockCheck
+ 0x10026b53 0x29 _L1w_DevAfcWriteBackVco
+ 0x10026b7c 0x4f _L1w_DevAfcSaveWMode
+ 0x10026bcb 0xa7 _L1w_DevAfcSlaveAfcMangement
+ 0x10026c72 0x15 _L1w_DevAfcLimitSlaveVco
+ 0x10026c87 0x15 _L1w_CleanSlaveAfcIRAMBuf
+ 0x10026c9c 0x32 _L1w_WriteMasterAfcInfo
+ 0x10026cce 0x20 _L1w_ReadMasterAfcInfo
+ 0x10026cee 0x6d _L1w_DevChangeAndUpdateAfc
+ .text 0x10026d5b 0xf2e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x10026d5b 0x129 _L1w_DevTpuRt1SampleCompst
+ 0x10026e84 0x77 _L1w_DevTpuReset
+ 0x10026efb 0x10 _L1w_DevTpuTaskIdTransForm
+ 0x10026f0b 0x5e _L1w_DevTpuAddFixedEvent
+ 0x10026f69 0x1a _L1w_DevTpuAddFixedCycleEvent
+ 0x10026f83 0x15 _L1w_DevTpuDelFixedCycleEvent
+ 0x10026f98 0x21 _L1w_DevTpuUpdateVarNtEvent
+ 0x10026fb9 0x20 _L1w_DevTpuUpdateVarRtEvent
+ 0x10026fd9 0xfd _L1w_DevTpuAddVarNtEvent
+ 0x100270d6 0xdf _L1w_DevTpuAddVarRtEvent
+ 0x100271b5 0x46 _L1w_DevTpuDelFixedEvent
+ 0x100271fb 0x62 _L1w_DevTpuDelVarNtEvent
+ 0x1002725d 0x3e _L1w_DevTpuDelVarRtEvent
+ 0x1002729b 0x65 _L1w_DevTpuGetRealTime
+ 0x10027300 0x8e _L1w_DevTpuGetRtForWakeUp
+ 0x1002738e 0x50 _L1w_DevTpuGetNetTime
+ 0x100273de 0xa4 _L1w_DevTpuGetAllTime
+ 0x10027482 0x80 _L1w_DevTpuNtFixedEventProc
+ 0x10027502 0xdd _L1w_DevTpuNtVarEventProc
+ 0x100275df 0xf6 _L1w_DevTpuRtEventProc
+ 0x100276d5 0x59 _L1w_DevTpuMacroAdjust
+ 0x1002772e 0x56 _L1w_DevTpuMicroAdjust
+ 0x10027784 0x1a _L1w_DevTpuMicroAdjustForSleep
+ 0x1002779e 0x56 _L1w_DevTpuMicroAdjSetPreSyncFlag
+ 0x100277f4 0x5 _L1w_DevTpuAdjEventProc
+ 0x100277f9 0xb _L1w_DevTpuSetDoff
+ 0x10027804 0x7 _L1w_DevTpuGetDoff
+ 0x1002780b 0xa _L1w_DevTpuSfn2Cfn
+ 0x10027815 0x25 _L1w_DevTpuCfn2Sfn
+ 0x1002783a 0x1b _L1w_DevTpuGetNtSSFN
+ 0x10027855 0x1c _L1w_DevTpuGetRtSSFN
+ 0x10027871 0x17 _L1w_DevTpuGetSSFN
+ 0x10027888 0xe _L1w_DevTpuGetCurCFN
+ 0x10027896 0x7 _L1w_DevTpuSfn2Ssfn
+ 0x1002789d 0x7 _L1w_DevTpuCfn2Ssfn
+ 0x100278a4 0x27 _L1w_DevTpuRt2Nt
+ 0x100278cb 0x69 _L1w_DevTpuAddCnt
+ 0x10027934 0x34 _L1w_DevTpuCalNt2RtOffset
+ 0x10027968 0x2c _L1w_DevTpuMicroSsfnJumpPatch
+ 0x10027994 0x7a _L1w_DevTpuCheckMicroSsfnJump
+ 0x10027a0e 0x21 _L1w_DevTpuMicroSsfnJumpPro
+ 0x10027a2f 0x77 _L1w_DevTpuCheckMicroSsfnBack
+ 0x10027aa6 0x1f _L1w_DevTpuMicroSsfnBackPro
+ 0x10027ac5 0x32 _L1w_DevTpuNtSSfnCfnUpdate
+ 0x10027af7 0x14 _L1w_DevTpuRtSSfnUpdate
+ 0x10027b0b 0x32 _L1w_DevTpuCalcNtUpdateTime
+ 0x10027b3d 0x31 _L1w_DevTpuCalcRtUpdateTime
+ 0x10027b6e 0x1e _L1w_DevTpuBase2Norm
+ 0x10027b8c 0x43 _L1w_DevTpuNorm2Base
+ 0x10027bcf 0x17 _L1w_DevTpuCalRt2NtOffset
+ 0x10027be6 0x27 _L1w_DevTpuNt2Rt
+ 0x10027c0d 0x7c _L1w_DevTpuSubCnt
+ .text 0x10027c89 0x9a4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x10027c89 0x6 _L1w_DevDbAfcAddrGet
+ 0x10027c8f 0x6 _L1w_DevDbIscpAddrGet
+ 0x10027c95 0x6f _L1w_DevDbRtxUpaRlIscpReport
+ 0x10027d04 0xa _L1w_DevDbRtxPcRlIscpReport
+ 0x10027d0e 0x7 _L1w_DevDbSetHsdpaInd
+ 0x10027d15 0xb _L1w_DevDbReSetHsdpaInd
+ 0x10027d20 0x3d _L1w_DevDbUpdateHsdpaInd
+ 0x10027d5d 0x6 _L1w_DevDbGetHsdpaInd
+ 0x10027d63 0x26 _L1w_DevDbRtxRxSirSet
+ 0x10027d89 0x26 _L1w_DevDbRtxRxSirGet
+ 0x10027daf 0x2d _L1w_DevDbBchWriteAfcData
+ 0x10027ddc 0x34 _L1w_DevAfcReadDataFromBch
+ 0x10027e10 0x3a9 _L1w_DevDlsAfcReadDataFromRx
+ 0x100281b9 0x43 _L1w_DevDbGetInitXValue
+ 0x100281fc 0x42 _L1w_DevDbGetInitYValue
+ 0x1002823e 0x1e _L1w_DevDbGetInitValue
+ 0x1002825c 0x45 _L1w_DevDbCodingPara
+ 0x100282a1 0x43 _L1w_DevDbTrchTtiMap
+ 0x100282e4 0x28 _L1w_DevDbTrchMaxMinTti
+ 0x1002830c 0x7 _L1w_DevDbTrchMaxTtiGet
+ 0x10028313 0x8 _L1w_DevDbTrchMinTtiGet
+ 0x1002831b 0x6 _L1w_DevDbGetPichCfg
+ 0x10028321 0x6 _L1w_DevDbGetPchCfg
+ 0x10028327 0x6 _L1w_DevDbGetFachCfg
+ 0x1002832d 0x6 _L1w_DevDbGetDldpchCfg
+ 0x10028333 0x6 _L1w_DevDbGetFdpchCfg
+ 0x10028339 0x32 _L1w_DevDbGetSchCodeGrp
+ 0x1002836b 0x3a _L1w_DevDbSaveCirData
+ 0x100283a5 0xb _L1w_DevDbClearCirData
+ 0x100283b0 0x6 _L1w_DevDbGetCirDataAddr
+ 0x100283b6 0x6 _L1w_DevDbGetFingerMaskBufAddr
+ 0x100283bc 0x1b _L1w_DevDbRtxReportToMac
+ 0x100283d7 0x21 _L1w_DevDbHspaReportToMac
+ 0x100283f8 0x1d _L1w_DevDbSetHsdpaToMacInfo
+ 0x10028415 0x21 _L1w_DevDbSetHsupaToMacInfo
+ 0x10028436 0xb _L1w_DevDbClrHspaToMacInfo
+ 0x10028441 0x1 _L1w_DevDbPcReportToMac
+ 0x10028442 0x9 _L1w_SchedResIsBand8Freq
+ 0x1002844b 0x15 _L1w_DevDbGetAiSignSeries
+ 0x10028460 0x27 _L1w_DevDbPiValHandle
+ 0x10028487 0x26 _L1w_DevDbCalcPiVal
+ 0x100284ad 0x1c _L1w_DevRtxRxPiAiFloatAdd
+ 0x100284c9 0x6 _L1w_DevDbGetHspaPlusFachPsCmd
+ 0x100284cf 0x12 _L1w_DevDbPsSubFrmInt
+ 0x100284e1 0x24 _L1w_DevDbSubFrmInt
+ 0x10028505 0xe _L1w_DevDbSetHarqFlag
+ 0x10028513 0xc _L1w_DevDbInitHsdpaAntSwitchInfo
+ 0x1002851f 0x7 _L1w_DevDbSetHsdpaAntSwitchFlg
+ 0x10028526 0x7 _L1w_DevDbGetHsdpaAntSwitchFlg
+ 0x1002852d 0x8 _L1w_DevDbSetHsdpaAntNum
+ 0x10028535 0x8 _L1w_DevDbGetHsdpaAntNum
+ 0x1002853d 0x1a _L1w_DevDbHsdpaJudge2Rto1R
+ 0x10028557 0x1c _L1w_DevDbHsdpaJudge1Rto2R
+ 0x10028573 0x9 _L1w_DevDbAddHsscchCnt
+ 0x1002857c 0x17 _L1w_DevDbHsscchSchedCnt
+ 0x10028593 0x9 _L1w_DevDbAddHsscchCorrectCnt
+ 0x1002859c 0xa _L1w_DevDbAddHsscchErrorCnt
+ 0x100285a6 0x9 _L1w_DevDbClearHsscchErrorCnt
+ 0x100285af 0xa _L1w_DevDbAddSnrHighCnt
+ 0x100285b9 0x9 _L1w_DevDbClearSnrHighCnt
+ 0x100285c2 0xa _L1w_DevDbAddSnrLowCnt
+ 0x100285cc 0x9 _L1w_DevDbClearSnrLowCnt
+ 0x100285d5 0xd _L1w_DevDbSet1R2RState
+ 0x100285e2 0xc _L1w_DevDbSetLas1R2RState
+ 0x100285ee 0x11 _L1w_DevDbIs1RTo2R
+ 0x100285ff 0x7 _L1w_DevDbGet1R2RState
+ 0x10028606 0xb _L1w_DevDbGet1R2RAntNum
+ 0x10028611 0x7 _L1w_DevSetSystemAntNum
+ 0x10028618 0x7 _L1w_DevGetSystemAntNum
+ 0x1002861f 0x7 _L1w_DevDbSetTxPower
+ 0x10028626 0x7 _L1w_DevDbGetTxPower
+ .text 0x1002862d 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x1002862d 0xf _L1w_DevRtxRxInit
+ 0x1002863c 0x29 _L1w_DevRtxRxReset
+ 0x10028665 0x87 _L1w_DevRtxRxAddTpuEvent
+ 0x100286ec 0x36 _L1w_DevRtxRxDelTpuEvent
+ 0x10028722 0x1c _L1w_DevRtxRxDelFactorTpuInt
+ 0x1002873e 0x80 _L1w_DevRtxRxSwapFinger
+ 0x100287be 0x10f _L1w_DevRtxRxFingerSort
+ 0x100288cd 0x72 _L1w_DevRtxRxFingerSelect
+ 0x1002893f 0x75 _L1w_DevRtxRxFingerMsgHandle
+ 0x100289b4 0x27 _L1w_DevRtxOfflinePichRelHanlde
+ 0x100289db 0x38 _L1w_DevRtxSetPchCfgState
+ 0x10028a13 0x65 _L1w_DevRtxRxPchCfgReqHandle
+ 0x10028a78 0x5f _L1w_DevRtxRxCompareConfigTime
+ 0x10028ad7 0x1a1 _L1w_DevRtxRxOffLinePichCfg
+ 0x10028c78 0xcd _L1w_DevRtxRxPichCfgMsgHandle
+ 0x10028d45 0x3e _L1w_DevRtxRxPichRelMsgHandle
+ 0x10028d83 0x187 _L1w_DevRtxRxPchCfgMsgHandle
+ 0x10028f0a 0x26 _L1w_DevRtxRxPchRelMsgHandle
+ 0x10028f30 0x157 _L1w_DevRtxRxAichCfgMsgHandle
+ 0x10029087 0x38 _L1w_DevRtxRxAichRelMsgHandle
+ 0x100290bf 0x123 _L1w_DevRtxRxFachCfgMsgHandle
+ 0x100291e2 0x38 _L1w_DevRtxRxFachRelMsgHandle
+ 0x1002921a 0x219 _L1w_DevRtxRxDlDpchCfgMsgHandle
+ 0x10029433 0x36 _L1w_DevRtxRxDlDpchRelMsgHandle
+ 0x10029469 0x119 _L1w_DevRtxRxFdpchCfgMsgHandle
+ 0x10029582 0x87 _L1w_DevRtxRxPlusCpCfgMsgHandle
+ 0x10029609 0x38 _L1w_DevRtxRxFdpchRelMsgHandle
+ 0x10029641 0x3 _L1w_DevRtxRxPlusFachTpuHandle
+ 0x10029644 0x1cc _L1w_DevRtxRxPlusFachCfg
+ 0x10029810 0x15b _L1w_DevRtxRxCmCfgMsgHandle
+ 0x1002996b 0x26 _L1w_DevRtxRxCmAbortMsgHandle
+ 0x10029991 0x5a _L1w_DevRtxRxHsscchCfgMsgHandle
+ 0x100299eb 0x51 _L1w_DevRtxRxEagchCfgMsgHandle
+ 0x10029a3c 0x9 _L1w_DevRtxRxEagchRelMsgHandle
+ 0x10029a45 0x63 _L1w_DevRtxRxRgHiCfgMsgHandle
+ 0x10029aa8 0x9 _L1w_DevRtxRxRgHiRelMsgHandle
+ 0x10029ab1 0x45 _L1w_DevRtxRxDrxMsgHandle
+ 0x10029af6 0x12e _L1w_DevRtxRxMsgHandle
+ 0x10029c24 0x6 _L1w_DevRtxRxTrchInfoGet
+ 0x10029c2a 0x16 _L1w_DevRtxRxTurboUse
+ 0x10029c40 0xed _L1w_DevRtxRxDlStatEng
+ 0x10029d2d 0x6 _L1w_DevRtxRxDpchPhyInfoGet
+ 0x10029d33 0x6 _L1w_DevRtxRxIntCfgParaGet
+ 0x10029d39 0xf _L1w_DevRtxRxDrxSlotCheck
+ 0x10029d48 0x28 _L1w_DevRtxRxCmSlotCheck
+ 0x10029d70 0x8c _L1w_DevRtxRxCpCmSlotCheck
+ 0x10029dfc 0x19 _L1w_DevRtxRxGetSlotId
+ 0x10029e15 0xa _L1w_DevRtxRxDrxSlotClr
+ 0x10029e1f 0x6 _L1w_DevRtxRxTpcInfoGet
+ 0x10029e25 0x6 _L1w_DevRtxRxSccpchPhyInfoGet
+ 0x10029e2b 0x6 _L1w_DevRtxRxAgchPhyInfoGet
+ 0x10029e31 0x6 _L1w_DevRtxRxCfgInfoGet
+ 0x10029e37 0xd _L1w_DevRtxRxCfgRlCntGet
+ 0x10029e44 0x1c _L1w_DevRtxRxRlPrimSrcGet
+ .text 0x10029e60 0x516 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ 0x10029e60 0xd _L1w_DevRtxRxDsReset
+ 0x10029e6d 0x25 _L1w_DevRtxDsMsgHandle
+ 0x10029e92 0x72 _L1w_DevRtxDsStageHandle
+ 0x10029f04 0x84 _L1w_DevRtxDsStart
+ 0x10029f88 0x9 _L1w_DevRtxDsStop
+ 0x10029f91 0x3d _L1w_DevRtxDsCrcCalc
+ 0x10029fce 0x62 _L1w_DevRtxDsStep1Handle
+ 0x1002a030 0x7c _L1w_DevRtxDsQosStep1
+ 0x1002a0ac 0x41 _L1w_DevRtxDsStep2Handle
+ 0x1002a0ed 0xcc _L1w_DevRtxDsQosStep2
+ 0x1002a1b9 0x2a _L1w_DevRtxRxDsPostInd
+ 0x1002a1e3 0x3d _L1w_DevRtxDsInsyncInd
+ 0x1002a220 0x41 _L1w_DevRtxDsOutsyncInd
+ 0x1002a261 0x19 _L1w_DevRtxRxDsIsCrcExist
+ 0x1002a27a 0x1f _L1w_DevRtxRxDsIsCrcOk
+ 0x1002a299 0x16 _L1w_DevRtxRxDsCurTtiParaClr
+ 0x1002a2af 0x16 _L1w_DevRtxRxDsLast20CrcFalse
+ 0x1002a2c5 0xb _L1w_DevRtxRxDsIsPostOk
+ 0x1002a2d0 0x14 _L1w_DevRtxRxDsIsN312Ok
+ 0x1002a2e4 0x31 _L1w_DevRtxRxDsSetTpcData
+ 0x1002a315 0x1d _L1w_DevRtxRxDsGetSyncSt
+ 0x1002a332 0x44 _L1w_DevRtxRxDsUlSendState
+ .text 0x1002a376 0x37c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x1002a376 0xe _L1w_DrvRfcSingedDataMaxLimit
+ 0x1002a384 0xc _L1w_DrvRfcUnSingedDataMaxLimit
+ 0x1002a390 0x26 _L1w_DrvRfcS16ToFastFloat
+ 0x1002a3b6 0x3e _L1w_DrvRfcS16FastFloatDiv
+ 0x1002a3f4 0xd _L1w_DrvRfcFastFloatToS16
+ 0x1002a401 0x3e _L1w_DrvRfcAgcgain2ManExp
+ 0x1002a43f 0x71 _L1w_DrvRfcDcCalcSingleCh
+ 0x1002a4b0 0x29 _L1w_DrvRfcDcCalc
+ 0x1002a4d9 0x37 _L1w_DrvRfcDcSet
+ 0x1002a510 0x1c _L1w_DevRfcDcEstEn
+ 0x1002a52c 0xac _L1w_DrvRfcIQCalcSingleCh
+ 0x1002a5d8 0x2e _L1w_DrvRfcIQSet
+ 0x1002a606 0x11 _L1w_DrvRfcIQCalc
+ 0x1002a617 0x4f _L1w_DrvRfcDagcCalc
+ 0x1002a666 0x8c _L1w_DrvRfcDagcSet
+ .text 0x1002a6f2 0x421 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ 0x1002a6f2 0xa _L1w_DrvPIAIClkGateEnable
+ 0x1002a6fc 0xa _L1w_DrvPIAIClkGateDisable
+ 0x1002a706 0x10 _L1w_DrvPIAISttdCfg
+ 0x1002a716 0xc _L1w_DrvAiOnLineEn
+ 0x1002a722 0xa _L1w_DrvAIonLineDisable
+ 0x1002a72c 0xc _L1w_DrvPIAfcoffLineEnable
+ 0x1002a738 0x12 _L1w_DrvPIAfcoffLineDisable
+ 0x1002a74a 0xf _L1w_DrvPiAfcIntModeCfg
+ 0x1002a759 0xe _L1w_DrvGetPiAiEnPara
+ 0x1002a767 0x9 _L1w_DrvGetPiAiIntMode
+ 0x1002a770 0xe _L1w_DrvGetConfigState
+ 0x1002a77e 0xf _L1w_DrvPiAIFirOrderCfg
+ 0x1002a78d 0x21 _L1w_DrvPiSysmbolLenCfg
+ 0x1002a7ae 0x9 _L1w_DrvAlphaCfg
+ 0x1002a7b7 0xa _L1w_DrvAfcCompensateEnable
+ 0x1002a7c1 0xa _L1w_DrvAfcCompensateDisable
+ 0x1002a7cb 0x14 _L1w_DrvAfcRotateParaCfg
+ 0x1002a7df 0xd _L1w_DrvPiAiFingerParaCfg
+ 0x1002a7ec 0x16 _L1w_DrvPiOffsetCfg
+ 0x1002a802 0x23 _L1w_DrvPiAiOvsfCfg
+ 0x1002a825 0xf _L1w_DrvAfcBestFingerIndexCfg
+ 0x1002a834 0x16 _L1w_DrvAiSeqIndexCfg
+ 0x1002a84a 0xa _L1w_DrvPiAiCfgOver
+ 0x1002a854 0x15 _L1w_DrvReadCpichPower
+ 0x1002a869 0xd _L1w_DrvReadAiResult
+ 0x1002a876 0x3b _L1w_DrvReadConfigTime
+ 0x1002a8b1 0x3e _L1w_DrvSetConfigTime
+ 0x1002a8ef 0x1f _L1w_DrvPiAiReadCpichRam
+ 0x1002a90e 0xa _L1w_DrvPiAiReadAiSymbolRam
+ 0x1002a918 0x1b _L1w_DrvPiAiReadSymbolRam
+ 0x1002a933 0xa _L1w_DrvEAiReadAmRam
+ 0x1002a93d 0x18 _L1w_DrvAiReadAmRam
+ 0x1002a955 0xff _L1w_DrvPiAiAichCfg
+ 0x1002aa54 0x12 _L1w_DrvPiAiAichRel
+ 0x1002aa66 0x82 _L1w_DrvOffPichCfg
+ 0x1002aae8 0x2b _L1w_DrvOffPichRel
+ .text 0x1002ab13 0x2b7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ 0x1002ab13 0x9 _L1w_DrvSleepLpmCtrPwrOn
+ 0x1002ab1c 0x1c _L1w_DrvLpcModemIntCtrl
+ 0x1002ab38 0x3d _L1w_DrvLpcLpmConfPosCal
+ 0x1002ab75 0x38 _L1W_DrvLpcCfgSocWkupInt
+ 0x1002abad 0x15 _L1W_DrvLpcCfgModemWkupInt
+ 0x1002abc2 0xe _L1w_DrvLpcModemWakeUpIntCtrl
+ 0x1002abd0 0xe _L1w_DrvLpcSocWakeUpIntCtrl
+ 0x1002abde 0x17 _L1w_DrvLpcLpmSoftReset
+ 0x1002abf5 0x1a _L1w_DrvLpcClearInt
+ 0x1002ac0f 0xe _L1w_DrvLpcLpmSfIntCtrl
+ 0x1002ac1d 0x9 _L1w_DrvLpcIsLpmSfIntEn
+ 0x1002ac26 0x8c _L1w_DrvLpcSetLpmFrmInt
+ 0x1002acb2 0x2b _L1w_DrvLpcSetLpmAdjustFactor
+ 0x1002acdd 0x87 _L1w_DrvLpcLpmIntPwrCtrl
+ 0x1002ad64 0x1f _L1w_DrvLpcGetWNtTimeFromLpm
+ 0x1002ad83 0x2a _L1w_DrvLpcIcpSendForPsm
+ 0x1002adad 0xe _L1w_DrvLpcSetCampOnFlg
+ 0x1002adbb 0x8 _L1w_DrvLpcSetSleepFlag
+ 0x1002adc3 0x7 _L1w_DrvLpcGetSleepFlag
+ .text 0x1002adca 0x39d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ 0x1002adca 0x1c _L1_DrvCsrInit
+ 0x1002ade6 0x30 _L1_DrvCsrReset
+ 0x1002ae16 0x1c _L1w_DevCsrStep1Reset
+ 0x1002ae32 0x5f _L1w_DrvCsrTopCfg
+ 0x1002ae91 0x82 _L1w_DrvCsrSlotSyncCfg
+ 0x1002af13 0x4b _L1w_DrvCsrIcCfg
+ 0x1002af5e 0x1 _L1w_DrvCsrFrameSyncCfg2A
+ 0x1002af5f 0x1 _L1w_DrvCsrFrameSyncCfg2B
+ 0x1002af60 0x1 _L1w_DrvCsrScrambleSrchCfg
+ 0x1002af61 0x66 _L1w_DrvCsrFullscanKscCfg
+ 0x1002afc7 0x44 _L1w_DrvCsrFullscanUnKscCfg
+ 0x1002b00b 0x83 _L1w_DrvCsrFullscanCfg
+ 0x1002b08e 0x94 _L1w_DrvCsrReadSlotSync
+ 0x1002b122 0x1 _L1w_DrvCsrStep1ReadMaxPos
+ 0x1002b123 0x1 _L1w_DrvCsrReadFrameSync2A
+ 0x1002b124 0x1 _L1w_DrvCsrReadFrameSync2B
+ 0x1002b125 0x1d _L1w_DrvCsrCmpFloat
+ 0x1002b142 0x1 _L1w_DrvCsrReadScrambleCode
+ 0x1002b143 0x24 _L1w_DrvCsrReadFs
+ .text 0x1002b167 0x306 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x1002b167 0x9 _L1w_DrvSetTop01GdtrHdtrBitSet
+ 0x1002b170 0xa _L1w_DrvSetTop01GdtrHdtrBitclr
+ 0x1002b17a 0x9 _L1w_DrvSetTopEDmaIntBypassBitSet
+ 0x1002b183 0xa _L1w_DrvSetTopEDmaIntBypassBitclr
+ 0x1002b18d 0x1c _L1w_DrvResetTopViterbi
+ 0x1002b1a9 0x6 _L1w_DrvGetTop0OSoftResetRegAddr
+ 0x1002b1af 0x9 _L1w_DrvTop00SoftResetBitSet
+ 0x1002b1b8 0xa _L1w_DrvTop00SoftResetBitClr
+ 0x1002b1c2 0x9 _L1w_DrvTop10TpuRakeIntMaskBitSet
+ 0x1002b1cb 0xa _L1w_DrvTop10TpuRakeIntMaskBitClr
+ 0x1002b1d5 0x9 _L1w_DrvTop11RakeDfeRfcIntMaskBitSet
+ 0x1002b1de 0xa _L1w_DrvTop11RakeDfeRfcIntMaskBitClr
+ 0x1002b1e8 0x9 _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitSet
+ 0x1002b1f1 0xa _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitClr
+ 0x1002b1fb 0x9 _L1w_DrvTop13CsrDtrPsrIntMaskBitSet
+ 0x1002b204 0xa _L1w_DrvTop13CsrDtrPsrIntMaskBitClr
+ 0x1002b20e 0x9 _L1w_DrvTop14TpuRakeIntStateMaskBitSet
+ 0x1002b217 0xa _L1w_DrvTop14TpuRakeIntStateMaskBitClr
+ 0x1002b221 0x9 _L1w_DrvTop15RakeDfeRfcIntStateMaskBitSet
+ 0x1002b22a 0xa _L1w_DrvTop15RakeDfeRfcIntStateMaskBitClr
+ 0x1002b234 0x9 _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitSet
+ 0x1002b23d 0xa _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitClr
+ 0x1002b247 0x9 _L1w_DrvTop17CsrDtrPsrIntStateMaskBitSet
+ 0x1002b250 0xa _L1w_DrvTop17CsrDtrPsrIntStateMaskBitClr
+ 0x1002b25a 0xe _L1w_DrvTopCsrDtrPsrIntOpen
+ 0x1002b268 0xe _L1w_DrvTopCsrDtrPsrIntClose
+ 0x1002b276 0x8 _L1w_DrvTopGetTop10High16b
+ 0x1002b27e 0x7 _L1w_DrvTopGetTop10Low16b
+ 0x1002b285 0x8 _L1w_DrvTopGetTop14High16b
+ 0x1002b28d 0x7 _L1w_DrvTopGetTop14Low16b
+ 0x1002b294 0x7 _L1w_DrvTopGetTop11Low16b
+ 0x1002b29b 0x7 _L1w_DrvTopGetTop15Low16b
+ 0x1002b2a2 0x9 _L1w_DrvTopLpcOpenGateClk
+ 0x1002b2ab 0xa _L1w_DrvTopLpcCloseGateClk
+ 0x1002b2b5 0xb _L1w_DrvTopClkIsOpen
+ 0x1002b2c0 0x13 _L1W_DrvTopLpcRegSave
+ 0x1002b2d3 0x23 _L1W_DrvTopLpcRegRestore
+ 0x1002b2f6 0x26 _L1w_DrvMcuIntMask
+ 0x1002b31c 0x26 _L1w_DrvMcuIntUnmask
+ 0x1002b342 0xa _L1w_DrvMcuIntIreqClr
+ 0x1002b34c 0x5f _L1w_DrvTopIntMask
+ 0x1002b3ab 0x4f _L1w_DrvTopIntMaskRestore
+ 0x1002b3fa 0x1a _L1w_DrvTopIntClr
+ 0x1002b414 0x59 _L1w_DrvTopIntEng
+ .text 0x1002b46d 0x20d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x1002b46d 0x25 _L1w_DrvTpuSoftResetCfg
+ 0x1002b492 0x39 _L1w_DrvTpuReset
+ 0x1002b4cb 0x28 _L1w_DrvTpuInit
+ 0x1002b4f3 0x39 _L1w_DrvTpuNTIntEnable
+ 0x1002b52c 0x3a _L1w_DrvTpuNTIntDisable
+ 0x1002b566 0x14 _L1w_DrvTpuRTIntEnable
+ 0x1002b57a 0x15 _L1w_DrvTpuRTIntDisable
+ 0x1002b58f 0x11 _L1w_DrvTpuLatchTimeCfg
+ 0x1002b5a0 0x8 _L1w_DrvTpuRdNTTiming
+ 0x1002b5a8 0x8 _L1w_DrvTpuRdRTTiming
+ 0x1002b5b0 0x11 _L1w_DrvTpuNTIntParaCfg
+ 0x1002b5c1 0x11 _L1w_DrvTpuRTIntParaCfg
+ 0x1002b5d2 0xa _L1w_DrvTpuMacroIntDisble
+ 0x1002b5dc 0x7 _L1w_DrvTpuMicroAdjParaCfg
+ 0x1002b5e3 0x8 _L1w_DrvTpuGetNT2RtOffset
+ 0x1002b5eb 0x8 _L1w_DrvTpuGetNTssfn
+ 0x1002b5f3 0x8 _L1w_DrvTpuGetRTssfn
+ 0x1002b5fb 0x32 _L1w_DrvTpuMacroAdjParaCfg
+ 0x1002b62d 0x28 _L1W_DrvTpuLpcRegRestore
+ 0x1002b655 0x25 _L1W_DrvTpuLpcRegSave
+ .text 0x1002b67a 0x431 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ 0x1002b67a 0x26 _L1w_DrvTxReset
+ 0x1002b6a0 0xb _L1w_DrvTxClear
+ 0x1002b6ab 0x16 _L1w_DrvTxDpxchEnCfg
+ 0x1002b6c1 0x10 _L1w_DrvTxRamLpEnCfg
+ 0x1002b6d1 0x10 _L1w_DrvTxScramFixRotateEnCfg
+ 0x1002b6e1 0x10 _L1w_DrvTxModeTypeCfg
+ 0x1002b6f1 0x10 _L1w_DrvTxGateClkDisableCfg
+ 0x1002b701 0x2b _L1w_DrvTxDpxchOffsetCfg
+ 0x1002b72c 0x31 _L1w_DrvTxPreamblePhchCfg
+ 0x1002b75d 0xa _L1w_DrvTxPreamblePhchDisable
+ 0x1002b767 0x2d _L1w_DrvTxPrachPhchCfg
+ 0x1002b794 0xa _L1w_DrvTxPrachPhchEnable
+ 0x1002b79e 0xa _L1w_DrvTxPrachPhchDisable
+ 0x1002b7a8 0x10 _L1w_DrvTxSampleTxRegTimeCfg
+ 0x1002b7b8 0x10 _L1w_DrvTxDpcchFbiCfg
+ 0x1002b7c8 0x16 _L1w_DrvTxDpcchTpcCfg
+ 0x1002b7de 0x43 _L1w_DrvTxDpxchPhchCfg
+ 0x1002b821 0x30 _L1w_DrvTxPrachSpreaderCfg
+ 0x1002b851 0x22 _L1w_DrvTxScramblerCfg
+ 0x1002b873 0x2a _L1w_DrvTxDpxchOrPrachPwrCfg
+ 0x1002b89d 0x18 _L1w_DrvTxHsDpcchPwrCfg
+ 0x1002b8b5 0x18 _L1w_DrvTxEdpcchPwrCfg
+ 0x1002b8cd 0x49 _L1w_DrvTxEdpdchPwrCfg
+ 0x1002b916 0xc _L1w_DrvTxPreamblePwrCfg
+ 0x1002b922 0x111 _L1_DrvTxRfcTest
+ 0x1002ba33 0x13 _L1w_DrvGetTxDpxchOffset
+ 0x1002ba46 0x39 _L1w_DrvTxCordicAdjustCfg
+ 0x1002ba7f 0x9 _L1w_DrvTxCordicDisable
+ 0x1002ba88 0x23 _L1w_DrvTxCordicEnable
+ .text 0x1002baab 0x381 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x1002baab 0x27 _L1w_DrvMeasReset
+ 0x1002bad2 0x57 _L1w_DrvMeasCfgCellCode
+ 0x1002bb29 0x19 _L1w_DrvMeasParaOverCfg
+ 0x1002bb42 0x6e _L1w_DrvMeasCfgSpsrStartTime
+ 0x1002bbb0 0x8 _L1w_DrvMeasCfgClkGating
+ 0x1002bbb8 0x60 _L1w_DrvMeasReadResult
+ 0x1002bc18 0x1a _L1w_DrvMeasReadAgc
+ 0x1002bc32 0xa _L1w_DrvMeasReadSpsrIntSeqNum
+ 0x1002bc3c 0x5f _L1w_DrvMeasCompareConfigTime
+ 0x1002bc9b 0x14 _L1w_DrvMeasReadSpsrstatus
+ 0x1002bcaf 0x8 _L1w_DrvMeasOffLineRamparaCfg
+ 0x1002bcb7 0x8 _L1w_DrvMeasOffLineRamMrtrCfg
+ 0x1002bcbf 0x9 _L1w_DrvMeasMeasBufUpdateCfg
+ 0x1002bcc8 0x8 _L1w_DrvMeasWorkModeCfg
+ 0x1002bcd0 0x8 _L1w_DrvMeasOnLineStartSpsrCfg
+ 0x1002bcd8 0xe _L1w_DrvMeasOnLineGetSpsrCfg
+ 0x1002bce6 0x10 _L1w_DrvMeasOnLineAgc0paraCfg
+ 0x1002bcf6 0x10 _L1w_DrvMeasOnLineAgc1paraCfg
+ 0x1002bd06 0x35 _L1w_DrvMeasOnLineAgc0StartMrtrCfg
+ 0x1002bd3b 0x35 _L1w_DrvMeasOnLineAgc1StartMrtrCfg
+ 0x1002bd70 0x4f _L1w_DrvMeasFrameBoundaryCfg
+ 0x1002bdbf 0x2d _L1w_DrvMeasSpsrParaCfg
+ 0x1002bdec 0x1c _L1w_DrvMeasCellSttdModeCfg
+ 0x1002be08 0xa _L1w_DrvMeasClkGatingCfg
+ 0x1002be12 0x9 _L1w_DrvMeasSoftPatternCfg
+ 0x1002be1b 0x9 _L1w_DrvMeasPatternModeCfg
+ 0x1002be24 0x8 _L1w_DrvMeasCfgOfflineSpsrStartTime
+ .text 0x1002be2c 0x55d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ 0x1002be2c 0x22 _L1w_DrvHsupaEutrEnable
+ 0x1002be4e 0xa _L1w_DrvHsupaEutrDisable
+ 0x1002be58 0xe _L1w_DrvHsupaEutrSoftRst
+ 0x1002be66 0x13 _L1w_DrvHsupaEutrHarqRamMode
+ 0x1002be79 0x10 _L1w_DrvHsupaEutrHarqId
+ 0x1002be89 0xb _L1w_DrvHsupaEutrTtiTwoFlg
+ 0x1002be94 0xb _L1w_DrvHsupaEutrTbSize
+ 0x1002be9f 0x47 _L1w_DrvHsupaEutrCodeSize
+ 0x1002bee6 0x3e _L1w_DrvHsupaEutrPhchPara
+ 0x1002bf24 0x2d _L1w_DrvHsupaEutrRmSysPara
+ 0x1002bf51 0x2d _L1w_DrvHsupaEutrRmP1Para
+ 0x1002bf7e 0x2d _L1w_DrvHsupaEutrRmP2Para
+ 0x1002bfab 0x55 _L1w_DrvHsupaEutrInterPara
+ 0x1002c000 0x60 _L1w_DrvHsupaEutrConfig
+ 0x1002c060 0xb _L1w_DrvHsupaEutrReadHarqStatus
+ 0x1002c06b 0x23 _L1w_DrvHsupaEtxEnable
+ 0x1002c08e 0x12 _L1w_DrvHsupaEtxDisable
+ 0x1002c0a0 0x19 _L1w_DrvHsupaEtxCfgTti
+ 0x1002c0b9 0x2a _L1w_DrvHsupaCfgEtxInt
+ 0x1002c0e3 0x12 _L1w_DrvHsupaTopEtxIntEnable
+ 0x1002c0f5 0xb _L1w_DrvHsupaEtxDisInt
+ 0x1002c100 0x1b _L1w_DrvHsupaTopMaskEtxInt
+ 0x1002c11b 0x31 _L1w_DrvHsupaRakeReadRgHi
+ 0x1002c14c 0xa _L1w_DrvHsupaCalLogTwo
+ 0x1002c156 0x42 _L1w_DrvHsupaEtxInterPara
+ 0x1002c198 0x34 _L1w_DrvHsupaEtxChCfgReg2
+ 0x1002c1cc 0x54 _L1w_DrvHsupaEtxEdpxchPara
+ 0x1002c220 0x25 _L1w_DrvHsupaEtxSpreadReg
+ 0x1002c245 0x29 _L1w_DrvHsupaEtxConf
+ 0x1002c26e 0xb _L1w_DrvHsupaEtxReadTtiCnt
+ 0x1002c279 0x20 _L1w_DrvHsupaTopGetIntState
+ 0x1002c299 0x1 _L1w_DrvHsupaTopMaskEutrInt
+ 0x1002c29a 0xf _L1w_DrvHsupaTopMaskRgHiState
+ 0x1002c2a9 0xf _L1w_DrvHsupaTopMaskRgHiInt
+ 0x1002c2b8 0x17 _L1w_DevHsupaTopMaskAgInt
+ 0x1002c2cf 0x2 _L1w_DrvHsupaTopMaskRgchHichInt
+ 0x1002c2d1 0x23 _L1w_DrvHsupaMaskInt
+ 0x1002c2f4 0x2d _L1w_DrvHsupaTopEagchRst
+ 0x1002c321 0x7 _L1w_DrvHsupaRdAgIntStateMask
+ 0x1002c328 0x7 _L1w_DrvHsupaWtAgIntStateMask
+ 0x1002c32f 0x7 _L1w_DrvHsupaRdAgIntEnable
+ 0x1002c336 0x7 _L1w_DrvHsupaWtAgIntEnable
+ 0x1002c33d 0x7 _L1w_DrvHsupaRdRgHiIntStateMask
+ 0x1002c344 0x7 _L1w_DrvHsupaWtRgHiIntStateMask
+ 0x1002c34b 0x7 _L1w_DrvHsupaRdRgHiIntEnable
+ 0x1002c352 0x7 _L1w_DrvHsupaWtRgHiIntEnable
+ 0x1002c359 0x17 _L1w_DrvHsupaEnableAgInt
+ 0x1002c370 0x13 _L1w_DrvHsupaPcEtxEdpdchDisable
+ 0x1002c383 0x6 _L1w_DrvEutrGetRamAddr
+ .text 0x1002c389 0x506 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x1002c389 0x1 _L1w_DrvDpramEngDisplay
+ 0x1002c38a 0x4a _L1w_DrvDpramStructInit
+ 0x1002c3d4 0x25 _L1w_DrvDpramIsEmpty
+ 0x1002c3f9 0x42 _L1w_DrvDpramReadMsg
+ 0x1002c43b 0x1 _L1w_DrvDpramUpdateMsgPos
+ 0x1002c43c 0x5 _L1w_DrvDpramQueMemRead
+ 0x1002c441 0x37 _L1w_DrvDpramWriteMsg
+ 0x1002c478 0x23 _L1w_DrvDpramGetRdDataPtr
+ 0x1002c49b 0x1f _L1w_DrvDpramUpdateRdDataPos
+ 0x1002c4ba 0x24 _L1w_DrvDpramTxReadClearData
+ 0x1002c4de 0x31 _L1w_DrvDpramGetWrDataPtr
+ 0x1002c50f 0x8 _L1w_DrvDpramGetWrCnt
+ 0x1002c517 0x2c _L1w_DrvDpramUpdateWrDataPos
+ 0x1002c543 0x1a _L1w_DrvICPSendForPsSched
+ 0x1002c55d 0xa _L1w_DrvDpramIsD2AEmpty
+ 0x1002c567 0xa _L1w_DrvDpramSleepCheck
+ 0x1002c571 0x8 _L1w_DrvDpramWriteSfnDpramFlg
+ 0x1002c579 0x7 _L1w_DrvDpramWriteDoff2Dpram
+ 0x1002c580 0x7 _L1w_DrvDpramReadEdcpIntState
+ 0x1002c587 0xa _L1w_DrvDpramClrEdcpIntState
+ 0x1002c591 0x7 _L1w_DrvDpramClrIcpIntState
+ 0x1002c598 0xa _L1w_DrvDpramMaskIcpInt
+ 0x1002c5a2 0x9 _L1w_DrvDpramDemaskIcpInt
+ 0x1002c5ab 0x49 _L1w_DrvDpramPrintLog
+ 0x1002c5f4 0x104 _L1w_DrvDpramUpdateTpu
+ 0x1002c6f8 0x26 _L1w_DrvDpramWriteGrantHarq
+ 0x1002c71e 0x26 _L1w_DrvDpramWriteUlPower
+ 0x1002c744 0x41 _L1w_DrvDpramGetEutrCtrlInfo
+ 0x1002c785 0xa _L1w_DrvDpramSetRachDchTransFlg
+ 0x1002c78f 0xa _L1w_DrvDpramGetRachDchTransFlg
+ 0x1002c799 0x20 _L1w_DrvDpramSetUpaTransInfo
+ 0x1002c7b9 0x1f _L1w_DrvDpramGetGrantMonitorReq
+ 0x1002c7d8 0xe _L1w_DrvDpramHsupaSetActiveInfos
+ 0x1002c7e6 0xa _L1w_DrvDpramSetCmPattern
+ 0x1002c7f0 0x9 _L1w_DrvDpramSetUph
+ 0x1002c7f9 0x2f _L1w_DrvDpramWriteEtfcRestrictInfo
+ 0x1002c828 0x3e _L1w_DrvDpramWriteCmNtrInfo
+ 0x1002c866 0x29 _L1w_DrvDpramGetEdchHarqId
+ .text 0x1002c88f 0x1984 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x1002c88f 0x81 _L1w_DrvRxTpcPlCombTimeInit
+ 0x1002c910 0x83 _L1w_DrvRxInit
+ 0x1002c993 0x50 _L1w_DrvRxReset
+ 0x1002c9e3 0x2c _L1w_DrvRxSoftReset
+ 0x1002ca0f 0x35 _L1w_DrvRxCalcExp2
+ 0x1002ca44 0xe _L1w_DrvRxFingerCfg
+ 0x1002ca52 0x2c _L1w_DrvRxSetTfciIntTime
+ 0x1002ca7e 0x8 _L1w_DrvRxGetTfciIntTime
+ 0x1002ca86 0x191 _L1w_DrvRxCpichCfg
+ 0x1002cc17 0x16 _L1w_DrvRxCpichRel
+ 0x1002cc2d 0x109 _L1w_DrvRxPichCfg
+ 0x1002cd36 0x3a _L1w_DrvRxPichRel
+ 0x1002cd70 0x123 _L1w_DrvRxAichCfg
+ 0x1002ce93 0x3a _L1w_DrvRxAichRel
+ 0x1002cecd 0x11d _L1w_DrvRxPchCfg
+ 0x1002cfea 0x11 _L1w_DrvRxPchRel
+ 0x1002cffb 0x126 _L1w_DrvRxFachCfg
+ 0x1002d121 0x3b _L1w_DrvRxFachRel
+ 0x1002d15c 0x10e _L1w_DrvRxDlDpchCodeCfg
+ 0x1002d26a 0x33 _L1w_DrvRxDlTpcPilotCfg
+ 0x1002d29d 0x29 _L1w_DrvRxFdpchTpcCfg
+ 0x1002d2c6 0xa4 _L1w_DrvRxDlDpchCfg
+ 0x1002d36a 0x6f _L1w_DrvRxDlDpchRel
+ 0x1002d3d9 0x31 _L1w_DrvRxDlFbiCfg
+ 0x1002d40a 0x15b _L1w_DrvRxFdpchCfg
+ 0x1002d565 0x3b _L1w_DrvRxFdpchRel
+ 0x1002d5a0 0x16a _L1w_DrvRxHsscchCfg
+ 0x1002d70a 0x65 _L1w_DrvRxHsscchRel
+ 0x1002d76f 0x103 _L1w_DrvRxEagchCfg
+ 0x1002d872 0x40 _L1w_DrvRxEagchRel
+ 0x1002d8b2 0x333 _L1w_DrvRxRgHiCfg
+ 0x1002dbe5 0x3c _L1w_DrvRxRgHiRel
+ 0x1002dc21 0x15 _L1w_DrvRxEdchTtiCfg
+ 0x1002dc36 0x5b _L1w_DrvRxRgHichPostCmCfg
+ 0x1002dc91 0x10 _L1w_DrvRxDpchFactorCfg
+ 0x1002dca1 0xf _L1w_DrvRxAgchFactorCfg
+ 0x1002dcb0 0x77 _L1w_DrvRxDlCmCfnCfg
+ 0x1002dd27 0x8c _L1w_DrvRxDlCmSymbCfg
+ 0x1002ddb3 0x64 _L1w_DrvRxDlCmPostCfg
+ 0x1002de17 0x1f _L1w_DrvRxDlCmSymbRel
+ 0x1002de36 0x16 _L1w_DrvRxDlCmPostRel
+ 0x1002de4c 0x24 _L1w_DrvRxRakeCpChangRel
+ 0x1002de70 0x8e _L1w_DrvRxRakeChipCfg
+ 0x1002defe 0x119 _L1w_DrvRxRakeSymbCfg
+ 0x1002e017 0x4a _L1w_DrvRxRakePostCfg
+ 0x1002e061 0x18 _L1w_DrvRxRakeCfg
+ 0x1002e079 0xc _L1w_DrvRxSymbCpichStRead
+ 0x1002e085 0xc _L1w_DrvRxSymbPilotStRead
+ 0x1002e091 0x9 _L1w_DrvRxCombPiAiIntRead
+ 0x1002e09a 0x9 _L1w_DrvRxCombPilotIntRead
+ 0x1002e0a3 0x9 _L1w_DrvRxCombTpcIntRead
+ 0x1002e0ac 0x15 _L1w_DrvRxCombTpcPlStIntRead
+ 0x1002e0c1 0x8 _L1w_DrvRxCombFdpchIntRead
+ 0x1002e0c9 0xa _L1w_DrvRxCombDpchFactorDataRead
+ 0x1002e0d3 0xa _L1w_DrvRxCombAgchFactorDataRead
+ 0x1002e0dd 0x27 _L1w_DrvRxRamPiAiRead
+ 0x1002e104 0xa _L1w_DrvRxRamDpchPilotRead
+ 0x1002e10e 0xa _L1w_DrvRxRamDpchTpcRead
+ 0x1002e118 0x43 _L1w_DrvRxRamFdpchTpcRead
+ 0x1002e15b 0x15 _L1w_DrvRxRamSlotwtRead
+ 0x1002e170 0x15 _L1w_DrvRxRamNoiseRead
+ 0x1002e185 0x1f _L1w_DrvRxRamRawCpichRead
+ 0x1002e1a4 0x15 _L1w_DrvRxRamAfcRead
+ 0x1002e1b9 0x1c _L1w_DrvRxRamRawPilotRead
+ 0x1002e1d5 0x1f _L1w_DrvRxRgchIntInfoRead
+ 0x1002e1f4 0x1f _L1w_DrvRxHichIntInfoRead
+ .text 0x1002e213 0xa62 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ 0x1002e213 0x11 _L1w_DrvDtrBitReverse
+ 0x1002e224 0xa _L1w_DrvDtrTurboInit
+ 0x1002e22e 0x1d _L1w_DrvDtrTurboReset
+ 0x1002e24b 0x11 _L1w_DrvDtrSetCsServiceFlg
+ 0x1002e25c 0x3b _L1w_DrvDtrReset
+ 0x1002e297 0x5e _L1w_DrvDtrInit
+ 0x1002e2f5 0x3e _L1w_DrvDtrTrchCmCfg
+ 0x1002e333 0x4c _L1w_DrvDtrTrchSlotFormCfg
+ 0x1002e37f 0x171 _L1w_DrvDtrTrchTfciS1Cfg
+ 0x1002e4f0 0x24 _L1w_DrvDtrTrchTfciS1Clear
+ 0x1002e514 0xb _L1w_DrvDtrTrchCfnSet
+ 0x1002e51f 0xa _L1w_DrvDtrTrchCfnGet
+ 0x1002e529 0xf _L1w_DrvDtrTrchRegRel
+ 0x1002e538 0xa _L1w_DrvDtrTrchTfciS2Update
+ 0x1002e542 0xa _L1w_DrvDtrTrchDemultiplexUpdate
+ 0x1002e54c 0x9f _L1w_DrvDtrS1CfgPrint
+ 0x1002e5eb 0x1d7 _L1w_DrvDtrS2CfgPrint
+ 0x1002e7c2 0xb0 _L1w_DrvDtrTrchTfciS2Cfg
+ 0x1002e872 0xb _L1w_DrvDtrTrchTfciS2Clear
+ 0x1002e87d 0x42 _L1w_DrvDtrTrchBlindS1Cfg
+ 0x1002e8bf 0xa5 _L1w_DrvDtrTrchBlindGuidCfg
+ 0x1002e964 0xc _L1w_DrvDtrTrchBlindGuidUpdate
+ 0x1002e970 0xa _L1w_DrvDtrTrchTfciRead
+ 0x1002e97a 0x2d _L1w_DrvDtrTrchTfciDataReadV3
+ 0x1002e9a7 0x30 _L1w_DrvDtrTrchBlindRead
+ 0x1002e9d7 0x6 _L1w_DrvDtrTrchBlindDataAddrGet
+ 0x1002e9dd 0x24 _L1w_DrvDtrTrchDecodeInfoRead
+ 0x1002ea01 0x6 _L1w_DrvDtrTrchDecodeAddrGet
+ 0x1002ea07 0x1bb _L1w_DrvDtrTrchDecodeDataRead
+ 0x1002ebc2 0x61 _L1w_DrvDtrEagchCfg
+ 0x1002ec23 0xe _L1w_DrvDtrEagchCmCfg
+ 0x1002ec31 0x9 _L1w_DrvDtrEagchRel
+ 0x1002ec3a 0x3b _L1w_DrvDtrAgchIntDataRead
+ .text 0x1002ec75 0x572 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ 0x1002ec75 0x2d _L1w_DrvBchInit
+ 0x1002eca2 0xe _L1w_DrvBchReset
+ 0x1002ecb0 0x2d _L1w_DrvBchRecover
+ 0x1002ecdd 0xd _L1w_DrvBchSetFingerAdjust
+ 0x1002ecea 0xe _L1w_DrvBchGeViterbiOut
+ 0x1002ecf8 0x56 _L1w_DrvBchGePichSymbol
+ 0x1002ed4e 0xa _L1w_DrvBchGeCrcResult
+ 0x1002ed58 0x2b _L1w_DrvBchGeCpichOut
+ 0x1002ed83 0xf8 _L1w_DrvBchBchRxCfg
+ 0x1002ee7b 0xcd _L1w_DrvBchPichRxCfg
+ 0x1002ef48 0x9b _L1w_DrvBchCpichRxCfg
+ 0x1002efe3 0xc _L1w_DrvBchSetFingerEn
+ 0x1002efef 0xc _L1w_DrvBchSetRuntime
+ 0x1002effb 0xe _L1w_DrvBchGetFingerPos
+ 0x1002f009 0x10 _L1w_DrvBchSetS5TestMode
+ 0x1002f019 0xa _L1w_DrvBchSetTxdMode
+ 0x1002f023 0x7 _L1w_DrvBchSetBchPichSel
+ 0x1002f02a 0x7 _L1w_DrvBchSetTtiSync
+ 0x1002f031 0x7 _L1w_DrvBchSetWindowTh
+ 0x1002f038 0x7 _L1w_DrvBchSetPichOvsfk
+ 0x1002f03f 0xc _L1w_DrvBchSetContexSel
+ 0x1002f04b 0xd _L1w_DrvBchSetFingerPos
+ 0x1002f058 0x19 _L1w_DrvBchSetScramCode
+ 0x1002f071 0x16 _L1w_DrvBchSetStartMode
+ 0x1002f087 0xc _L1w_DrvBchSetPiAfcNum
+ 0x1002f093 0x31 _L1w_DrvBchSetPiPos
+ 0x1002f0c4 0xe _L1w_DrvBchGetFingerSt
+ 0x1002f0d2 0xd _L1w_DrvBchHasInvalidSymbol
+ 0x1002f0df 0xe _L1w_DrvBchGetBufIndex
+ 0x1002f0ed 0xe _L1w_DrvBchGetSlotIndex
+ 0x1002f0fb 0xe _L1w_DrvBchGetBurstPattern
+ 0x1002f109 0xa _L1w_DrvBchGeTotalSt
+ 0x1002f113 0x16 _L1w_DrvBchIsHwBusy
+ 0x1002f129 0x13 _L1w_DrvBchSetIQSel
+ 0x1002f13c 0x12 _L1w_DrvBchSetRotatePara
+ 0x1002f14e 0x21 _L1w_DrvBchSetRotateEn
+ 0x1002f16f 0xf _L1w_DrvBchSetRotateGateCtrl
+ 0x1002f17e 0xb _L1w_DrvBchIsIqRotateEn
+ 0x1002f189 0x36 _L1w_DrvBchStopIqRotate
+ 0x1002f1bf 0x12 _L1w_DrvBchSetFingerAnt
+ 0x1002f1d1 0x16 _L1w_DrvBchSetAdjFingerInfo
+ .text 0x1002f1e7 0x2f1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ 0x1002f1e7 0xc _L1w_DrvUtrLogTwo
+ 0x1002f1f3 0x31 _L1w_DrvUtrReset
+ 0x1002f224 0x1c _L1w_DrvUtrRamSoftReset
+ 0x1002f240 0x3 _L1w_DrvUtrInit
+ 0x1002f243 0xac _L1w_DrvUtrDchConfig
+ 0x1002f2ef 0x32 _L1w_DrvUtrRachConfig
+ 0x1002f321 0xa _L1w_DrvUtrEnable
+ 0x1002f32b 0xe _L1w_DrvUtrClose
+ 0x1002f339 0x8 _L1w_DrvUtrGetRamAddr
+ 0x1002f341 0x5f _L1w_DrvUtrTbAndCbConfig
+ 0x1002f3a0 0xac _L1w_DrvUtrRMConfig
+ 0x1002f44c 0x2d _L1w_DrvUtrGetCrcMode
+ 0x1002f479 0x20 _L1w_DrvUtrGetCodingType
+ 0x1002f499 0x1a _L1w_DrvUtrClearRmPara
+ 0x1002f4b3 0xc _L1w_DrvUtrRegClear
+ 0x1002f4bf 0x11 _L1w_DrvUtrGetRamData
+ 0x1002f4d0 0x8 _L1_DrvUtrGetInterlv1RamState
+ .text 0x1002f4d8 0x1dda T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ 0x1002f4d8 0x5e _L1w_DrvRfcApcTableSel
+ 0x1002f536 0x1d2 _L1w_DrvRfcAbbCsfHpfCfg
+ 0x1002f708 0x5 _L1w_DrvRfcCalcIntFreq
+ 0x1002f70d 0x29 _L1w_DrvRfcCalcFracFreq
+ 0x1002f736 0x51 _L1w_DrvRfcGetFreqData
+ 0x1002f787 0x19 _L1w_DrvRfcGetBandData
+ 0x1002f7a0 0x9d _L1w_DrvRfcFreqSetTx
+ 0x1002f83d 0x12a _L1w_DrvRfcFreqSetRx
+ 0x1002f967 0x84 _L1w_DrvRfcGetBandNvIndex
+ 0x1002f9eb 0x79 _L1w_DrvRfcAuxRxCtrlSet
+ 0x1002fa64 0x1c _L1w_DrvRfcAuxRxIdleSet
+ 0x1002fa80 0x20 _L1w_DrvRfcRegReadBackSet
+ 0x1002faa0 0x1 _L1w_DrvRfcChSel
+ 0x1002faa1 0x1 _L1w_DrvRfcTransceiverInit
+ 0x1002faa2 0x2e _L1w_DrvRfcAgcSet
+ 0x1002fad0 0x2f _L1w_DrvRfcApcTableFreqSel
+ 0x1002faff 0xbc _L1w_DrvRfcApcSet
+ 0x1002fbbb 0x2d _L1w_DrvRfcFreqCompGetNvIdx
+ 0x1002fbe8 0x7c _L1w_DrvRfcApcFreqComp
+ 0x1002fc64 0x38 _L1w_DrvRfcApcTmpComp
+ 0x1002fc9c 0x100 _L1w_DrvRfcApcCalibTableCheck
+ 0x1002fd9c 0x4f _L1w_DrvRfcApcDefaultTableCheck
+ 0x1002fdeb 0x77 _L1w_DrvRfcAgcFreqComp
+ 0x1002fe62 0x71 _L1w_DrvRfcAgcCalibTableCheck
+ 0x1002fed3 0x46 _L1w_DrvRfcAgcDefaultTableCheck
+ 0x1002ff19 0x2a _L1w_DrvRfcRxNotchEn
+ 0x1002ff43 0x2a _L1w_DrvRfcRxNotchDisEn
+ 0x1002ff6d 0x2b _L1w_DrvRfcAntExChangeSelEn
+ 0x1002ff98 0x2b _L1w_DrvRfcAntOriginSelEn
+ 0x1002ffc3 0x2a _L1w_DrvRfcRxStartDivEn
+ 0x1002ffed 0x2b _L1w_DrvRfcRxStopDivEn
+ 0x10030018 0x2a _L1w_DrvRfcAuxRxSwCtrlEn
+ 0x10030042 0x2b _L1w_DrvRfcAuxRxSwIdleEn
+ 0x1003006d 0x38 _L1w_DrvRfcIdleToTxEn
+ 0x100300a5 0x36 _L1w_DrvRfcTxToRxTxEn
+ 0x100300db 0x3a _L1w_DrvRfcTxToIdleEn
+ 0x10030115 0x36 _L1w_DrvRfcRxTxToTxEn
+ 0x1003014b 0x36 _L1w_DrvRfcIdleToRxEn
+ 0x10030181 0x38 _L1w_DrvRfcRxToRxTxEn
+ 0x100301b9 0x2b _L1w_DrvRfcSwAllIdleEn
+ 0x100301e4 0x40 _L1w_DrvRfcRxToIdleEn
+ 0x10030224 0x2d _L1w_DrvRfcRxTxToRxEn
+ 0x10030251 0x37 _L1w_DrvRfcRxFreqChangeEn
+ 0x10030288 0x38 _L1w_DrvRfcTxFreqChangeEn
+ 0x100302c0 0x32 _L1w_DrvRfcIdleToTxHandle
+ 0x100302f2 0x48 _L1w_DrvRfcTxToIdleHandle
+ 0x1003033a 0x45 _L1w_DrvRfcIdleToRxHandle
+ 0x1003037f 0x55 _L1w_DrvRfcRxToIdleHandle
+ 0x100303d4 0x53 _L1w_DrvRfcRxFreqChangeHandle
+ 0x10030427 0xd _L1w_DrvRfcTxFreqChangeHandle
+ 0x10030434 0x41 _L1w_DrvRfcSlotCtrlDiv
+ 0x10030475 0x2a _L1w_DrvRfcSlotCtrlAntSel
+ 0x1003049f 0x29 _L1w_DrvRfcAgcEstEn
+ 0x100304c8 0x29 _L1w_DrvRfcAgcSetEn
+ 0x100304f1 0x35 _L1w_DrvRfcApcEn
+ 0x10030526 0x3c _L1w_DrvRfcAfcSetEn
+ 0x10030562 0x29 _L1w_DrvRfcDcEstEn
+ 0x1003058b 0x29 _L1w_DrvRfcDcSetEn
+ 0x100305b4 0x29 _L1w_DrvRfcRegReadBackEn
+ 0x100305dd 0x29 _L1w_DrvRfcStartAuxAdcEn
+ 0x10030606 0x29 _L1w_DrvRfcStopAuxAdcEn
+ 0x1003062f 0x1c _L1w_DrvRfcDcxoAuxAdcStart
+ 0x1003064b 0x1d _L1w_DrvRfcDcxoAuxAdcStop
+ 0x10030668 0x1f _L1w_DrvRfcAuxAdcCtrlEn
+ 0x10030687 0x41 _L1w_DrvRfcAbbCsfWriteEn
+ 0x100306c8 0x33 _L1w_DrvRfcCtrlRamTxInit
+ 0x100306fb 0x33 _L1w_DrvRfcCtrlRamRx0Init
+ 0x1003072e 0x204 _L1w_DrvRfcCtrlRamSwitchNvInit
+ 0x10030932 0xea _L1w_DrvRfcCtrlRamPaNvInit
+ 0x10030a1c 0x8 _L1w_DrvRfcCtrlRamNvEventInit
+ 0x10030a24 0x38 _L1w_DrvRfcFastAgcCwTableInit
+ 0x10030a5c 0x4c _L1w_DrvRfcFastAgcRamInit
+ 0x10030aa8 0xda _L1w_DrvRfcOpenTx
+ 0x10030b82 0xf7 _L1w_DrvRfcOpenRx
+ 0x10030c79 0xa _L1w_DrvRfcDiversityCtrl
+ 0x10030c83 0x12 _L1w_DrvRfcAfcCw2Hz
+ 0x10030c95 0x6a _L1w_DrvRfcRfRegRead
+ 0x10030cff 0xce _L1w_DrvRfcAllRegReadBack
+ 0x10030dcd 0x54 _L1w_DrvRfcGetDCXOTmp
+ 0x10030e21 0x3b _L1w_DrvRfcReadTmp
+ 0x10030e5c 0x15 _L1w_DrvRfcAptWrite
+ 0x10030e71 0x21 _L1w_DrvRfcDcocWrite
+ 0x10030e92 0x18 _L1w_DrvRfcAgcWrite
+ 0x10030eaa 0x8d _L1w_DrvRfcCloseTx
+ 0x10030f37 0x6d _L1w_DrvRfcCloseRx
+ 0x10030fa4 0x7e _L1w_DrvRfcDirFreqSetTx
+ 0x10031022 0x7c _L1w_DrvRfcDirFreqSetRx
+ 0x1003109e 0x32 _L1w_DrvRfcPowerApcSet
+ 0x100310d0 0x43 _L1w_DrvRfcIndexApcSet
+ 0x10031113 0x177 _L1w_DrvRfcFdtTxApcSet
+ 0x1003128a 0x22 _L1w_DrvRfcHdtGetTxApcTable
+ 0x100312ac 0x6 _L1w_DrvRfcHdtGetRxAgcTable
+ .text 0x100312b2 0xb8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ 0x100312b2 0x8 _L1w_DrvPsrStartPosCfg
+ 0x100312ba 0xb _L1w_DrvPsrRlMrtrPosMrtrConfig
+ 0x100312c5 0xb _L1w_DrvPsrSrcAndChanCodeCfg
+ 0x100312d0 0x8 _L1w_DrvPsrClkGatePassCfg
+ 0x100312d8 0x9 _L1w_DrvPsrPilotPatternCfg
+ 0x100312e1 0x8 _L1w_DrvPsrCmModeCfg
+ 0x100312e9 0x9 _L1w_DrvPsrRlPosStartCfgOver
+ 0x100312f2 0x9 _L1w_DrvPsrSuspendCfg
+ 0x100312fb 0x12 _L1w_DrvPsrTopMaskIntCfg
+ 0x1003130d 0x1c _L1w_DrvPsrResetCfg
+ 0x10031329 0x8 _L1w_DrvPsrPeriodCfg
+ 0x10031331 0x8 _L1w_DrvPsrDoubleAntOpencfg
+ 0x10031339 0x8 _L1w_DrvPsrStartWinPosCfg
+ 0x10031341 0x8 _L1w_DrvPsrRlOpenCloseCfg
+ 0x10031349 0x8 _L1w_DrvPsrMasterRlCfg
+ 0x10031351 0x8 _L1w_DrvPsrSttdCfg
+ 0x10031359 0x8 _L1w_DrvPsrIntInfoCfg
+ 0x10031361 0x9 _L1w_DrvPsrCmOverCfg
+ .text 0x1003136a 0xaff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x1003136a 0x3c _L1w_DrvRfcGetFreqOffset
+ 0x100313a6 0x17 _L1w_DrvRfcNextSlotGet
+ 0x100313bd 0x16 _L1w_DrvRfcPreSlotGet
+ 0x100313d3 0x20 _L1w_DrvRfcFindSlot
+ 0x100313f3 0x8 _L1w_DrvRfcGetTxFirDlyNum
+ 0x100313fb 0x31 _L1w_DrvRfcSpiWrite
+ 0x1003142c 0x31 _L1w_DrvRfcAbbSpiWrite
+ 0x1003145d 0x12 _L1w_DrvRfcGpioWrite
+ 0x1003146f 0x14 _L1w_DrvRfcRffeWrite
+ 0x10031483 0x38 _L1w_DrvRfcFindBandNumFromTable
+ 0x100314bb 0x41 _L1w_DrvRfcGetFreqBand
+ 0x100314fc 0x22 _L1w_DrvRfcRxDfeIntfCfg
+ 0x1003151e 0x2f _L1w_DrvRfcPaModeSel
+ 0x1003154d 0x25 _L1w_DrvRfcGetPaCtrlData
+ 0x10031572 0x1a _L1w_DrvRfcGetPaIdleData
+ 0x1003158c 0x2a _L1w_DrvRfcGetApcCtrlWord
+ 0x100315b6 0xa3 _L1w_DrvRfcGetTxPowerCtrlWord
+ 0x10031659 0x14 _L1w_DrvRfcPaCtrl
+ 0x1003166d 0x25 _L1w_DrvRfcGetAgcCtrlWord
+ 0x10031692 0x27 _L1w_DrvRfcGetAfcDacCtrlWord
+ 0x100316b9 0x2c _L1w_DrvRfcDCXOGetTempDegree
+ 0x100316e5 0xb _L1w_DrvRfcAfcSet
+ 0x100316f0 0x1a _L1w_DrvRfcGetTxSwData
+ 0x1003170a 0x29 _L1w_DrvRfcGetRxSwData
+ 0x10031733 0x1a _L1w_DrvRfcGetTxSwIdleData
+ 0x1003174d 0x29 _L1w_DrvRfcGetRxSwIdleData
+ 0x10031776 0x1a _L1w_DrvRfcGetSwAllIdleData
+ 0x10031790 0x27 _L1w_DrvRfcSwitchPaCwWr
+ 0x100317b7 0x37 _L1w_DrvRfcSwitchCtrl
+ 0x100317ee 0x55 _L1w_DrvRfcSwPaIdleNvGet
+ 0x10031843 0x12 _L1w_DrvRfcGetCfgMrtr
+ 0x10031855 0x54 _L1w_DrvRfcTuEventMrtrWr
+ 0x100318a9 0x21 _L1w_DrvRfcTuEventCtrlDataWr
+ 0x100318ca 0x54 _L1w_DrvRfcTuEventEn
+ 0x1003191e 0x27 _L1w_DrvRfcCtrlRamFmtDataWr
+ 0x10031945 0x28 _L1w_DrvRfcCtrlRamFmtInfoWr
+ 0x1003196d 0x20 _L1w_DrvRfcCtrlRamDataTypeWr
+ 0x1003198d 0x40 _L1w_DrvRfcCtrlRamEn
+ 0x100319cd 0xe _L1w_DrvRfcAgcRamDataWr
+ 0x100319db 0x1c _L1w_DrvRfcFastAgcEn
+ 0x100319f7 0x1a _L1w_DrvRfcFastAgcDisEn
+ 0x10031a11 0x15 _L1w_DrvRfcIntCfg
+ 0x10031a26 0x15 _L1w_DrvRfcSpiFormatCfg
+ 0x10031a3b 0x9 _L1w_DrvRfcRffeFormatCfg
+ 0x10031a44 0x2 _L1w_DrvRfcRbdpCfg
+ 0x10031a46 0x1c _L1w_DrvRfcDagcCfg
+ 0x10031a62 0x13 _L1w_DrvRfcDcCfg
+ 0x10031a75 0xd _L1w_DrvRfcFcCordicCfg
+ 0x10031a82 0x1a _L1w_DrvRfcNotchCordicCfg
+ 0x10031a9c 0x21 _L1w_DrvRfcReadNotchCordicAVal
+ 0x10031abd 0xb8 _L1w_DrvRfcNotchRegCfg
+ 0x10031b75 0x52 _L1w_DrvRfcFastAgcCfg
+ 0x10031bc7 0x4f _L1w_DrvRfcCtrlRamEventInit
+ 0x10031c16 0x84 _L1w_DrvRfcAbbCsfCtrlRamInit
+ 0x10031c9a 0x21 _L1w_DrvRfcEventTableInit
+ 0x10031cbb 0x41 _L1w_DrvRfcReset
+ 0x10031cfc 0x8f _L1w_DrvRfcGsmIntNotchCalc
+ 0x10031d8b 0x73 _L1w_DrvRfcInit
+ 0x10031dfe 0x9 _L1w_DrvRfcDfeTxInit
+ 0x10031e07 0x30 _L1w_DrvRfcTxTone
+ 0x10031e37 0x28 _L1w_DrvRfcAfcCwSet
+ 0x10031e5f 0x1 _L1w_DrvRfcAfcCwGet
+ 0x10031e60 0x9 _L1w_DrvRfcRestore
+ .text 0x10031e69 0x1594 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x10031e69 0x38 _L1w_DrvHsdpaIcReset
+ 0x10031ea1 0x2f _L1w_DrvHsdpaIcTpuCfgOver
+ 0x10031ed0 0x30 _L1w_DrvHsdpaIcTxTpuCfgOver
+ 0x10031f00 0x28 _L1w_DrvHsdpaIcInit
+ 0x10031f28 0x12 _L1w_DrvHsdpaIcIntOpen
+ 0x10031f3a 0x12 _L1w_DrvHsdpaIcIntMask
+ 0x10031f4c 0x17 _L1w_DrvHsdpaIcEnable
+ 0x10031f63 0x18 _L1w_DrvHsdpaIcStaticCfg
+ 0x10031f7b 0x273 _L1w_DrvHsdpaIcTpuAntPsrCfg
+ 0x100321ee 0x1d8 _L1w_DrvHsdpaIcTxTpuAntPsrCfg
+ 0x100323c6 0xa9 _L1w_DrvHsdpaIcTpuSubFrmCfg
+ 0x1003246f 0x97 _L1w_DrvHsdpaIcTxTpuSubFrmCfg
+ 0x10032506 0x69 _L1w_DrvHsdpaIcModeEnableCfg
+ 0x1003256f 0x5b _L1w_DrvHsdpaIcLambdaCfg
+ 0x100325ca 0x5b _L1w_DrvHsdpaIcSymModulusRead
+ 0x10032625 0x34 _L1w_DrvHsdpaAdrReset
+ 0x10032659 0x18 _L1w_DrvHsdpaAdrInit
+ 0x10032671 0x12 _L1w_DrvHsdpaAdrIntOpen
+ 0x10032683 0x12 _L1w_DrvHsdpaAdrIntMask
+ 0x10032695 0xd6 _L1w_DrvHsdpaAdrStaticCfg
+ 0x1003276b 0x83 _L1w_DrvHsdpaAdrInitRcvCfg
+ 0x100327ee 0x4b _L1w_DrvHsdpaAdrFcCfg
+ 0x10032839 0x10 _L1w_DrvHsdpaAdrEnableCfg
+ 0x10032849 0x172 _L1w_DrvHsdpaAdrSubFrmCfg
+ 0x100329bb 0x10 _L1w_DrvHsdpaAdrHsscchCfg
+ 0x100329cb 0x2e _L1w_DrvHsdpaAdrHsdschCfg
+ 0x100329f9 0xa _L1w_DrvHsdpaAdrDisable
+ 0x10032a03 0x2d _L1w_DrvHsdpaAdrCltd1Cfg
+ 0x10032a30 0x74 _L1w_DrvHsdpaAdrCirIntRead
+ 0x10032aa4 0x11 _L1w_DrvHsdpaAdrGetCirDataAddr
+ 0x10032ab5 0x20 _L1w_DrvHsdpaAdrCpichIntRead
+ 0x10032ad5 0x2e _L1w_DrvHsdpaHsscchReset
+ 0x10032b03 0x21 _L1w_DrvHsdpaHsscchInit
+ 0x10032b24 0x12 _L1w_DrvHsdpaHsscchIntOpen
+ 0x10032b36 0x12 _L1w_DrvHsdpaHsscchIntMask
+ 0x10032b48 0x11 _L1w_DrvHsdpaHsscchStaticCfg
+ 0x10032b59 0x65 _L1w_DrvHsdpaHsscchInitRcvCfg
+ 0x10032bbe 0x2d _L1w_DrvHsdpaHsscchPart1Cfg
+ 0x10032beb 0x3b _L1w_DrvHsdpaHsscchPart2Cfg
+ 0x10032c26 0x1b _L1w_DrvHsdpaHsscchDisable
+ 0x10032c41 0xeb _L1w_DrvHsdpaHsscchPart1IntRead
+ 0x10032d2c 0x31 _L1w_DrvHsdpaHsscchPart2IntRead
+ 0x10032d5d 0x30 _L1w_DrvHsdpaHdtrReset
+ 0x10032d8d 0x1a _L1w_DrvHdtrTurboReset
+ 0x10032da7 0x1b _L1w_DrvHdtrLessTurboReset
+ 0x10032dc2 0x2e _L1w_DrvHsdpaHdtrInit
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+ .text 0x1004561f 0x9d5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
+ 0x1004561f 0x2b _L1w_SchedPageCalcImsi
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+ .text 0x1004727f 0x11c2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
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+ .text 0x10048441 0x767 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ 0x1004851f 0x2b1 _L1w_SchedHsdpaPSCmd
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+ .text 0x10048ba8 0x2ae T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ 0x10048ba8 0xb _L1w_SchedHspaEraInd
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+ .text 0x10048e56 0x341 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
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+ .text 0x10049197 0xce5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
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+ .text 0x1004a367 0x539 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
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+ 0x1004a74e 0xa _L1w_DevHsupaSearchEhichRcvInf
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+ 0x1004a76f 0xe6 _L1w_DevHsupaIcpIntEdchDataProc
+ 0x1004a855 0x4b _L1w_DevHsupaCpPcTtiInfo
+ .text 0x1004a8a0 0x2a8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ 0x1004a8a0 0x25 _L1w_DevPcHspaReset
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+ 0x1004a8e0 0x44 _L1w_DevPcHsdpaBeltaHsCalc
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+ 0x1004aa7d 0x69 _L1w_DevPcHsupaStartReqHandle
+ 0x1004aae6 0x62 _L1w_DevPcHsupaTtiInfoHandle
+ .text 0x1004ab48 0xee3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x1004ab48 0x26 _L1w_DevTxRachIndToL1s
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+ 0x1004b338 0xc8 _L1w_DevTxPrachCfg
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+ 0x1004b92e 0x56 _L1w_DevTxEraDpcchRel
+ 0x1004b984 0xa7 _L1w_DevTxPiAiAichIntHandle
+ .text 0x1004ba2b 0xfa4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ 0x1004ba2b 0xb _L1w_DevRtxRmReset
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+ 0x1004bb6b 0x5a _L1w_DevRmUlTfciAnalysis
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+ 0x1004bf68 0xa3 _L1w_DevRmCalcUlUncodeRm
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+ 0x1004c07e 0xa6 _L1w_DevRmCalcUlTurboRm
+ 0x1004c124 0x65 _L1w_DevRmCalcUlTrchRmPara
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+ 0x1004c1cf 0x8a _L1w_DevRmCalcDlNimax
+ 0x1004c259 0x1f _L1w_DevRmCalcDlDeltaNimax
+ 0x1004c278 0xbd _L1w_DevRmCalcDlRmTfcNMax
+ 0x1004c335 0x97 _L1w_DevRmCalcDlRmDeltaNiTti
+ 0x1004c3cc 0x67 _L1w_DevRmCalcDlRmNiMax
+ 0x1004c433 0xfb _L1w_DevRmCalcDlTfcDeltaNijTti
+ 0x1004c52e 0x8f _L1w_DevRmCalcDlDeltaNijTti
+ 0x1004c5bd 0x63 _L1w_DevRmCalcDlUncodeRm
+ 0x1004c620 0x99 _L1w_DevRmCalcDlTurboRm
+ 0x1004c6b9 0x3f _L1w_DevRmCalcDlTrchRmPara
+ 0x1004c6f8 0x54 _L1w_DevRmCalcDlRmPara
+ 0x1004c74c 0x4c _L1w_DevRmSaveUlDchPara
+ 0x1004c798 0x4a _L1w_DevRmSaveDlTrchPara
+ 0x1004c7e2 0x34 _L1w_DevRmSaveRachPara
+ 0x1004c816 0xb5 _L1w_DevRmCalcRmPara
+ 0x1004c8cb 0x74 _L1w_DevRmCalcUlRmNi
+ 0x1004c93f 0x25 _L1w_DevRmCalcUlCmRes
+ 0x1004c964 0x6b _L1w_DevRmCalcTfcRes
+ .text 0x1004c9cf 0x3fc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ 0x1004c9cf 0x23 _L1w_DevHsdpaSendPcTtiInfo
+ 0x1004c9f2 0x1f _L1w_DevHsdpaHarqAckBufferShift
+ 0x1004ca11 0x68 _L1w_DevHsdpaSetHarqBufPrePost
+ 0x1004ca79 0x2a _L1w_DevHsdpaSetHarqBufAckNack
+ 0x1004caa3 0x2f _L1w_DevHsdpaInitCqiInfo
+ 0x1004cad2 0xe2 _L1w_DevHsdpaCqiSendProc
+ 0x1004cbb4 0x4b _L1w_DevHsdpaSnrCalcCtrl
+ 0x1004cbff 0x81 _L1w_DevHsdpaCqiSendCtrl
+ 0x1004cc80 0x3c _L1w_DevHsdpaSaveHsdpcchInitCfg
+ 0x1004ccbc 0x4a _L1w_DevHsdpaSaveHsdpcchAckCfg
+ 0x1004cd06 0x49 _L1w_DevHsdpaSaveHsdpcchCqiCfg
+ 0x1004cd4f 0x2a _L1w_DevHsdpaTxInitSendProc
+ 0x1004cd79 0x52 _L1w_DevHsdpaTxSubFrmProc
+ .text 0x1004cdcb 0x1a89 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x1004cdcb 0x9a _L1w_DevHsdpaInitHarqInfo
+ 0x1004ce65 0x45 _L1w_DevHsdpaInitAdrPsrInfo
+ 0x1004ceaa 0x10 _L1w_DevHsdpaGenChMask
+ 0x1004ceba 0x28 _L1w_DevHsdpaIsHdtrValid
+ 0x1004cee2 0x1a _L1w_DevHsdpaSaveDemoduleCfg
+ 0x1004cefc 0x5f _L1w_DevHsdpaSaveDecodeCfg
+ 0x1004cf5b 0x181 _L1w_DevHsdpaTpuSaveIcPsrCfg
+ 0x1004d0dc 0xea _L1w_DevHsdpaTpuCalcCfgPara
+ 0x1004d1c6 0x153 _L1w_DevHsdpaTxTpuSaveIcPsrCfg
+ 0x1004d319 0xdc _L1w_DevHsdpaTxTpuCalcCfgPara
+ 0x1004d3f5 0x92 _L1w_DevHsdpaTpuSaveScrCodePara
+ 0x1004d487 0x93 _L1w_DevHsdpaTxTpuSaveScrCodePara
+ 0x1004d51a 0x151 _L1w_DevHsdpaSaveAdrIcSubFrmPara
+ 0x1004d66b 0x6e _L1w_DevHsdpaSaveAdrInitRcvCfg
+ 0x1004d6d9 0x47 _L1w_DevHsdpaSaveHsscchInitCfg
+ 0x1004d720 0xa5 _L1w_DevHsdpaSaveAdrSubFrmCfg
+ 0x1004d7c5 0x15 _L1w_DevHsdpaIsPart1Valid
+ 0x1004d7da 0x109 _L1w_DevHsdpaPart1Filter
+ 0x1004d8e3 0x96 _L1w_DevHsdpaDchSavePart1IntCfg
+ 0x1004d979 0x2b2 _L1w_DevHsdpaSavePart1IntCfg
+ 0x1004dc2b 0x97 _L1w_DevHsdpaHsscchTypeAnalyse
+ 0x1004dcc2 0x16 _L1w_DevHsdpaIsNeedAckNack
+ 0x1004dcd8 0x149 _L1w_DevHsdpaDchPart2Type1Proc
+ 0x1004de21 0x7e _L1w_DevHsdpaSaveHdtrHwCfg
+ 0x1004de9f 0x4e _L1w_DevHsdpaSaveHdtrCfgPara
+ 0x1004deed 0x2d _L1w_DevHsdpaHdtrCfg
+ 0x1004df1a 0x3e _L1w_DevHsdpaCalcShiftFactor
+ 0x1004df58 0x13e _L1w_DevHsdpaPart2Type1Proc
+ 0x1004e096 0x35 _L1w_DevHsdpaHsscchOrderProc
+ 0x1004e0cb 0x119 _L1w_DevHsdpaPart2IntTraceLog
+ 0x1004e1e4 0x15d _L1w_DevHsdpaDchHdtrIntProc
+ 0x1004e341 0x3c _L1w_DevHsdpaRxParaInit
+ 0x1004e37d 0x5d _L1w_DevHsdpaRxInitRcvProc
+ 0x1004e3da 0x5f _L1w_DevHsdpaRxIcRstFirstCfg
+ 0x1004e439 0xb9 _L1w_DevHsdpaRxSubFrmProc
+ 0x1004e4f2 0xd3 _L1w_DevHsdpaRxPart1IntProc
+ 0x1004e5c5 0x142 _L1w_DevHsdpaRxPart2IntProc
+ 0x1004e707 0x4e _L1w_DevHsdpaRxMacHeadAnalyse
+ 0x1004e755 0xcc _L1w_DevHsdpaRxHdtrIntProc
+ 0x1004e821 0x33 _L1w_DevHsdpaRxThDataUpdate
+ .text 0x1004e854 0x297 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x1004e854 0x1c _L1w_DevPcRachReset
+ 0x1004e870 0x1c _L1w_DevPcRachInit
+ 0x1004e88c 0x9b _L1w_DevPcPrachBeltaCalc
+ 0x1004e927 0x7 _L1w_DevPcPrachPreamblePowerEngGet
+ 0x1004e92e 0x7b _L1w_DevPcPrachPreamblePowerCtrl
+ 0x1004e9a9 0xf6 _L1w_DevPcPrachMessagePowerCtrl
+ 0x1004ea9f 0x34 _L1w_DevPcPrachStartReqHandle
+ 0x1004ead3 0x6 _L1w_DevPcPrachPreambleReqHandle
+ 0x1004ead9 0x12 _L1w_DevPcPrachMessageReqHandle
+ .text 0x1004eaeb 0xeba T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x1004eaeb 0x3a _L1w_HsupaCalcLowLim
+ 0x1004eb25 0x48 _L1w_HsupaFlt2Fix
+ 0x1004eb6d 0x21 _L1w_DevHsupaCalcHiFrameOffset
+ 0x1004eb8e 0xf _L1w_DevHsupaCalcRgFrameOffset
+ 0x1004eb9d 0x46 _L1w_DevHsupaCalcRgHiFrmOffset
+ 0x1004ebe3 0x1f _L1w_DevHsupaIsTtiCntValid
+ 0x1004ec02 0x14 _L1w_DevHsupaCalcTtiCntMod
+ 0x1004ec16 0x26 _L1w_DevHsupaIsDlChanFrontByTx
+ 0x1004ec3c 0x3e _L1w_DevHsupaReadRgHi
+ 0x1004ec7a 0x20 _L1w_DevHsupaLookUpTtiCm
+ 0x1004ec9a 0x15a _L1w_DevHsupaIsRgHiCm
+ 0x1004edf4 0x15c _L1w_DevHsupaReadAllRgHiInfo
+ 0x1004ef50 0x2 _L1w_DevHsupaReadHarqGrant
+ 0x1004ef52 0x91 _L1w_DevHsupaHiCombine
+ 0x1004efe3 0x90 _L1w_DevHsupaRgCombine
+ 0x1004f073 0xaf _L1w_DevHsupaIscpSlotCombine
+ 0x1004f122 0x87 _L1w_DevHsupaHiDecisonParam
+ 0x1004f1a9 0x46 _L1w_DevHsupaNackConfirm
+ 0x1004f1ef 0xa5 _L1w_DevHsupaSingleHiDecision
+ 0x1004f294 0xb2 _L1w_DevHsupaSingleRgDecision
+ 0x1004f346 0x14 _L1w_DevHsupaMulHiNsrlsDecision
+ 0x1004f35a 0x73 _L1w_DevHsupaMulRgNsrlsDecision
+ 0x1004f3cd 0x30 _L1w_DevHsupaTtiCnt2HarqId
+ 0x1004f3fd 0x84 _L1w_DevHsupaNsrlsHiCombDecis
+ 0x1004f481 0x47 _L1w_DevHsupaSrlsHICombDecis
+ 0x1004f4c8 0x4d _L1w_DevHsupaSrlsRGCombDecis
+ 0x1004f515 0x75 _L1w_DevHsupaGetRlIscp
+ 0x1004f58a 0xee _L1w_DevHsupaReadAllIscpInfo
+ 0x1004f678 0x39 _L1w_DevHsupaSingleHiCombDec
+ 0x1004f6b1 0x61 _L1w_DevHsupaHiCombAndDecision
+ 0x1004f712 0x3d _L1w_DevHsupaSingleRgCombDecis
+ 0x1004f74f 0x75 _L1w_DevHsupaNsrlsRGDecision
+ 0x1004f7c4 0x51 _L1w_DevHsupaRgIndProc
+ 0x1004f815 0x91 _L1w_DevHsupaCalcDisDlChanEdch
+ 0x1004f8a6 0xff _L1w_DevHsupaSetHarqInfo
+ .text 0x1004f9a5 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ 0x1004f9a5 0x1 _L1w_DrvDmaReset
+ 0x1004f9a6 0x1 _L1w_DrvDmaInit
+ 0x1004f9a7 0x1 _L1w_DrvDmaSingleMemcpy
+ 0x1004f9a8 0x1 _L1W_DMA_ISR
+ .text 0x1004f9a9 0x165 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ 0x1004f9a9 0xd5 _L1w_SchedHsdpaPchCfgPSCmd
+ 0x1004fa7e 0x43 _L1w_SchedHsdpaPchRelPSCmd
+ 0x1004fac1 0x14 _L1w_SchedHsdpaPchPreSched
+ 0x1004fad5 0x1 _L1w_SchedHsdpaPchSched
+ 0x1004fad6 0x38 _L1w_SchedHsdpaPchSend2PS
+ .text 0x1004fb0e 0x12d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x1004fb0e 0x86 _zPHY_ModemOsProcessInit
+ 0x1004fb94 0x38 _zPHY_HwInit
+ 0x1004fbcc 0x1 _zPHY_FpgaPlatTopInit
+ 0x1004fbcd 0x5 _zPHY_ChipTopRegInit
+ 0x1004fbd2 0x69 _zPHY_LteaInit
+ .text 0x1004fc3b 0x210 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x1004fc3b 0xe _zPHY_NVInit_PreInit
+ 0x1004fc49 0x4b _zPHY_NVLteCopy
+ 0x1004fc94 0xd0 _zPHY_NVInit
+ 0x1004fd64 0x8 _L1e_CmnNvGetUeCategory
+ 0x1004fd6c 0x8 _L1e_CmnNvGetDlMimoCapability
+ 0x1004fd74 0xa _L1e_CmnNvGetRxAntNum
+ 0x1004fd7e 0xf _L1e_CmnNvGetRxRsrpInterval
+ 0x1004fd8d 0xf _L1e_CmnNvGetRxAntThreshold
+ 0x1004fd9c 0xa _L1e_CmnNvGetRxN1Timer
+ 0x1004fda6 0xa _L1e_CmnNvGetRxN2Timer
+ 0x1004fdb0 0x8 _L1e_CmnNvGetLteTempDetectEn
+ 0x1004fdb8 0x8 _L1e_CmnNvGetLteTxPwrBackoffEn
+ 0x1004fdc0 0x8 _L1e_CmnNvGetLteRxRateLimitEn
+ 0x1004fdc8 0x9 _L1e_CmnNvGetLteCqiThdParam
+ 0x1004fdd1 0xa _L1e_CmnNvGetLteRxTiAlgoCtrl
+ 0x1004fddb 0x11 _l1e_CmnZTERfSPIWrite
+ 0x1004fdec 0x20 _l1e_CmnZTERfSPIRead
+ 0x1004fe0c 0x3f _zPHY_erfc_TempReadPa
+ .text 0x1004fe4b 0xd86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x1004fe4b 0x1 _zPHY_ErrorHandle
+ 0x1004fe4c 0x14 _zPHY_GetErrorName
+ 0x1004fe60 0x102 _zPHY_etmtlog_ThreadEntry
+ 0x1004ff62 0x5c _zPHY_VersionInfo
+ 0x1004ffbe 0x41 _L1e_CmnLogUpdateAbsSfn
+ 0x1004ffff 0xc6 _L1e_CmnLogClearVariableVal
+ 0x100500c5 0x1c8 _L1e_CmnLogDlTbCrcAndThroughPut
+ 0x1005028d 0x3b _L1e_CmnLogStatDlFlowByCc
+ 0x100502c8 0x11 _L1e_CmnLogStatDlThroughPut
+ 0x100502d9 0x45 _L1e_CmnLogDlDdtrCfgTimes
+ 0x1005031e 0x45 _L1e_CmnLogDlDdtrIntTimes
+ 0x10050363 0x86 _L1e_CmnLogStatDlRntiApplyCnt
+ 0x100503e9 0x52 _L1e_CmnLogStatPcfichChannel
+ 0x1005043b 0x15c _L1e_CmnLogStatPhichChannel
+ 0x10050597 0x2a9 _L1e_CmnLogStatPdcchChannel
+ 0x10050840 0xa _L1e_CmnLogStatDlCtrlChMonitor
+ 0x1005084a 0x9e _L1e_CmnLogStatDciDecodeInfo
+ 0x100508e8 0x42 _L1e_CmnLogGetRxTxBitmap
+ 0x1005092a 0x94 _L1e_CmnLogGetCalcSinrValByCc
+ 0x100509be 0x3 _L1e_CmnLogGetCalcSinrVal
+ 0x100509c1 0x24 _L1e_CmnLogStatUlFlowByCc
+ 0x100509e5 0x37 _L1e_CmnLogStatUlThroughPut
+ 0x10050a1c 0x1d _zPHY_GetUlQmMcs
+ 0x10050a39 0x2f _zPHY_GetDlQmMcs
+ 0x10050a68 0xa _zPHY_GetDlSinr
+ 0x10050a72 0x1d _zPHY_GetUlHarqNack
+ 0x10050a8f 0x22 _zPHY_GetDlHarqNack
+ 0x10050ab1 0xf _zPHY_GetDlThrougput
+ 0x10050ac0 0xf _zPHY_GetUlThrougput
+ 0x10050acf 0x1a _zPHY_UlResidualBlerCount
+ 0x10050ae9 0xd _zPHY_AtGetPowerHeadroom
+ 0x10050af6 0x9 _zPHY_AtGetPcmax
+ 0x10050aff 0x26 _zPHY_AtGetRsrpDbm
+ 0x10050b25 0x2a _zPHY_AtGetRssiDbm
+ 0x10050b4f 0x42 _zPHY_AtGetResidualBlerByCc
+ 0x10050b91 0x26 _zPHY_AtGetResidualBler
+ 0x10050bb7 0x1a _zPHY_AtClearVariableVal
+ .text 0x10050bd1 0xbb9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x10050bd1 0x117 _zPHY_Tpu_ExtraCheck
+ 0x10050ce8 0x2a _L1L_TpuAdjCnfMsg
+ 0x10050d12 0x293 _L1L_TpuCpModeSwitchProc
+ 0x10050fa5 0x40 _L1L_TpuDevFixedIntRegister
+ 0x10050fe5 0x3d _L1L_TpuDevTimerUnRegister
+ 0x10051022 0x63 _L1L_TpuMicroAdj
+ 0x10051085 0x7 _L1L_TpuDevMsgDelayMsgTimerRegister
+ 0x1005108c 0x6 _L1L_TpuDevMsgDelayCBTimerRegister
+ 0x10051092 0x15 _L1L_TpuDevRelativeMsgTimerRegister
+ 0x100510a7 0x13 _L1L_TpuDevRelativeCBTimerRegister
+ 0x100510ba 0x36 _L1L_TpuDevMrtrTimeTypeMsgTimerRegister
+ 0x100510f0 0x35 _L1L_TpuDevMrtrTimeTypeCBTimerRegister
+ 0x10051125 0x20 _L1L_TpuSuperSlotGet
+ 0x10051145 0x21 _L1L_TpuMrtrFormat
+ 0x10051166 0x1c _L1L_TpuLocalMrtr2FreeMrtr
+ 0x10051182 0x1c _L1L_TpuFreeMrtr2LocalMrtr
+ 0x1005119e 0xb4 _L1L_TpuProUpdateLocalMRTR
+ 0x10051252 0xa _L1L_TpuTimeSub
+ 0x1005125c 0x13 _L1L_TpuTimeAdd
+ 0x1005126f 0x4d _L1L_TpuTs2Time
+ 0x100512bc 0x17 _L1L_TpuTime2Ts
+ 0x100512d3 0x34 _L1L_TpuMrtrAdd
+ 0x10051307 0x40 _L1L_TpuMrtrSub
+ 0x10051347 0x443 _zPHY_LTE_TPU_ThreadEntry
+ .text 0x1005178a 0x677 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x1005178a 0x40 _zPHY_ecsi_HNoDMA
+ 0x100517ca 0x1 _zPHY_ecsi_PCellCSI_En
+ 0x100517cb 0x1 _zPHY_ecsi_SCellCSI_En
+ 0x100517cc 0x49 _zPHY_ecsi_Init
+ 0x10051815 0x2c _zPHY_ecsi_PCellCommParmUpdate
+ 0x10051841 0x9b _zPHY_ecsi_PCellDediParmUpdate
+ 0x100518dc 0xb7 _zPHY_ecsi_PCellHOParmUpdate
+ 0x10051993 0xd3 _zPHY_ecsi_MsgResponse
+ 0x10051a66 0x2d _zPHY_ecsi_ctrl_GetNodeTXAttennaNum
+ 0x10051a93 0x8c _zPHY_ecsi_CbResSetGet
+ 0x10051b1f 0x2c _zPHY_ecsi_PerCqiParaGet
+ 0x10051b4b 0x23 _zPHY_ecsi_CqiRowAParaCalc
+ 0x10051b6e 0x5c _zPHY_ecsi_PcellCsiRepParaDediGet
+ 0x10051bca 0x3f _zPHY_ecsi_ScellCsiRepParaDediGet
+ 0x10051c09 0x12 _zPHY_ecsi_CsiRsParaGet
+ 0x10051c1b 0x28 _zPHY_ecsi_CSITimeUpdate
+ 0x10051c43 0xac _zPHY_ecsi_FlowPrint
+ 0x10051cef 0x1 _zPHY_ecsi2dl_CHECfg
+ 0x10051cf0 0xab _zPHY_ecsi_Start
+ 0x10051d9b 0x66 _zPHY_ecsi_CSIAThreadEntry
+ .text 0x10051e01 0x104d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x10051e01 0x26 _L1e_DevDlsGetTbCrc
+ 0x10051e27 0x16 _L1e_DevDlsGetTbCbCrc
+ 0x10051e3d 0x9c _L1e_DevDlsSetDlHarqFlag
+ 0x10051ed9 0x43 _L1e_DevDlsGetDdtrWorkSf
+ 0x10051f1c 0x89 _zPHY_edls_ProCwCrcGeneration
+ 0x10051fa5 0xfa _zPHY_edls_ProTddCwCrcFeedback
+ 0x1005209f 0x56 _zPHY_edls_ProFddCwCrcFeedback
+ 0x100520f5 0x115 _zPHY_edls_ProHarqFeedbackInfo
+ 0x1005220a 0x11e _zPHY_edls_ProDdtrHbitInt
+ 0x10052328 0xb3 _zPHY_edls_ProDdtrIntDtch
+ 0x100523db 0xa2 _zPHY_edls_ProDdtrIntSibPch
+ 0x1005247d 0x64 _L1e_DbgDlsDecPchInfo
+ 0x100524e1 0x2d _L1e_DevDlsPageMatch
+ 0x1005250e 0x5e _L1e_DevDlsPchMessagePro
+ 0x1005256c 0x5b _L1e_DevDlsPchReportInd
+ 0x100525c7 0x56 _zPHY_edls_ProPchDataProc
+ 0x1005261d 0x48 _zPHY_edls_ProSibDataProc
+ 0x10052665 0x5b _zPHY_edls_ProPchStatAndPrint
+ 0x100526c0 0x53 _zPHY_edls_ProSibStatAndPrint
+ 0x10052713 0x75 _zEumacdl_CrExist
+ 0x10052788 0x285 _L1e_DevDlsCfgMacPduCtrlInfo
+ 0x10052a0d 0x32 _L1e_DevDlsReportMacPdu
+ 0x10052a3f 0x1dc _zPHY_edls_ProDschIntThread
+ 0x10052c1b 0x5c _zPHY_edls_ProMsg2RaRntiMacPdu
+ 0x10052c77 0x36 _zPHY_edls_PDschIsr
+ 0x10052cad 0x7f _L1e_DbgDlsAckNakRptInfo
+ 0x10052d2c 0x122 _L1e_DbgDlsDecStatInfo
+ .text 0x10052e4e 0x6f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x10052e4e 0x51 _zPHY_edls_ProPdcchIntThread
+ 0x10052e9f 0x44 _zPHY_edls_ProMsg4CRntiPdcch
+ 0x10052ee3 0x6a _zPHY_edls_DciIsr
+ 0x10052f4d 0xc _zPHY_edls_ProSetVoLteTime
+ 0x10052f59 0x23 _zLtePsPhy_RemoteMalloc
+ 0x10052f7c 0x35 _zPHY_edls_ProStoreSpsInfo
+ 0x10052fb1 0x17 _L1e_DevDlsRstRxRbBmpReg
+ 0x10052fc8 0x42 _L1e_DevDlsRefSenCntPro
+ 0x1005300a 0x72 _L1e_DevDlsRefSenPro
+ 0x1005307c 0xf _L1e_DevDlsBfInd
+ 0x1005308b 0x39 _zPHY_edls_DdtrHwIdleState
+ 0x100530c4 0x25 _L1x_DevDlsInOutJudge
+ 0x100530e9 0x4e _L1e_DbgDlsCommDecInfo
+ 0x10053137 0xce _L1e_DbgDlsDciInfo
+ 0x10053205 0x51 _L1e_DbgDlsDecErr
+ 0x10053256 0x1 _L1e_DbgDlsValidRptInfo
+ 0x10053257 0x58 _zPHY_edls_ProDbgSpsDciDetInfo
+ 0x100532af 0x291 _zPHY_edls_DbgHarqDdrClose
+ .text 0x10053540 0x2d58 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x10053540 0x3a _zPHY_erfc_ProSetRamSFNumForLargeAdj
+ 0x1005357a 0x46 _zPHY_erfc_ProGetMeas0RamNum
+ 0x100535c0 0x37 _zPHY_erfc_ProGetTxRamNum
+ 0x100535f7 0x34 _zPHY_erfc_ProGetNextSubFrameOffset
+ 0x1005362b 0x96 _zPHY_erfc_SupLteTxEnableCtrl
+ 0x100536c1 0xc _zPHY_erfc_ProSpecSubfrmCheck
+ 0x100536cd 0x23 _zPHY_erfc_ProTxSendCtrl
+ 0x100536f0 0x25 _zPHY_erfc_SupDFESubframeStartCtl
+ 0x10053715 0x311 _zPHY_erfc_ProRamCtrl
+ 0x10053a26 0x1 _zPHY_erfc_ProPrintProcess
+ 0x10053a27 0x27 _zPHY_erfc_ProNotchProCtrl
+ 0x10053a4e 0x10 _zPHY_erfc_ProGetFreqBandNum
+ 0x10053a5e 0x238 _zPHY_erfc_TDDProRFABB_RxToRx
+ 0x10053c96 0xe1 _zPHY_erfc_TDDProRFABB_RxToIdle
+ 0x10053d77 0x4c _zPHY_erfc_TDDProRFABB_RxToTx
+ 0x10053dc3 0x31 _zPHY_erfc_TDDProRFABB_IdleToTx
+ 0x10053df4 0x2ee _zPHY_erfc_TDDProRFABB_IdleToRx
+ 0x100540e2 0x1 _zPHY_erfc_TDDProRFABB_IdleToIdle
+ 0x100540e3 0x30 _zPHY_erfc_TDDProRFABB_TxToIdle
+ 0x10054113 0x108 _zPHY_erfc_TDDProRFABB_TxToRx
+ 0x1005421b 0x1 _zPHY_erfc_TDDProRFABB_TxToTx
+ 0x1005421c 0x58 _zPHY_erfc_ATSetAndReadRfReg
+ 0x10054274 0x534 _zPHY_erfc_ProRFABBCtrl
+ 0x100547a8 0xa07 _zPHY_erfc_ProRFABBCtrl_FDD
+ 0x100551af 0x5b _zPHY_erfc_Pro_IFTempNeedFix
+ 0x1005520a 0x343 _zPHY_erfc_ProRFCWork
+ 0x1005554d 0x58 _zPHY_erfc_ProRxOffsetAutoCtrl
+ 0x100555a5 0x10 _zPHY_erfc_ProTAOffsetAutoCtrl
+ 0x100555b5 0x3b8 _zPHY_erfc_ProTxAndRxOffsetCtrl
+ 0x1005596d 0xe _zPHY_erfc_ProRFSDInit
+ 0x1005597b 0xa _zPHY_erfc_ProRFCSA_CSRConfig
+ 0x10055985 0xe _zPHY_erfc_ProRFCSA_RXConfig
+ 0x10055993 0xa _zPHY_erfc_ProRFCSA_TXConfig
+ 0x1005599d 0x95 _zPHY_erfc_ProRFSDAndRFCSAInit
+ 0x10055a32 0x4b _zPHY_erfc_RpiCfg
+ 0x10055a7d 0x1d _zPHY_erfc_RpiSet
+ 0x10055a9a 0x5d _zPHY_erfc_RpiPwrCtrl
+ 0x10055af7 0x72 _zPHY_erfc_ProRFCSAInit
+ 0x10055b69 0x6f _zPHY_erfc_ProRFCInit
+ 0x10055bd8 0x54 _zPHY_erfc_ProRFCInitPointer
+ 0x10055c2c 0x18d _zPHY_erfc_ProRfsdCheck_FDD
+ 0x10055db9 0x3f _zPHY_erfc_CheckNextSccRfcToIdle
+ 0x10055df8 0x17 _zPHY_erfc_ProGetRFCCurrentState
+ 0x10055e0f 0x1e2 _zPHY_erfc_ThreadEntry
+ 0x10055ff1 0x16 _zPHY_erfc_GetRfcMeasStatus
+ 0x10056007 0x19 _zPHY_erfc_TjpAlgorithm
+ 0x10056020 0x3d _zPHY_erfc_CalcMeasSubfNum
+ 0x1005605d 0x3f _zPHY_erfc_CalcSyncSubfNum
+ 0x1005609c 0x1a _zPHY_erfc_IntraFrameTimeComp
+ 0x100560b6 0x1 _zPHY_erfc_ProCleanHWTable
+ 0x100560b7 0x47 _zPHY_erfc_LTXTxTaConfig
+ 0x100560fe 0x36 _zPHY_erfc_ProCopyTxPccParaToScc
+ 0x10056134 0x1 _zPHY_erfc_RXTX_PathTest
+ 0x10056135 0x27 _zPHY_erfc_MainSlave_InterSwitch
+ 0x1005615c 0x5b _zPHY_erfc_GetTxTabAdjust
+ 0x100561b7 0xa _zPHY_erfc_GetFixDlDelay
+ 0x100561c1 0xd _L1l_DevRfcRxOffsetGet
+ 0x100561ce 0xd _L1l_DevRfcTaTimingGet
+ 0x100561db 0x9 _L1l_DevRfcRatModeSet
+ 0x100561e4 0xc _L1l_DevRfcTmpReadEn
+ 0x100561f0 0x9a _L1l_DevRfcTmpReadCtrl
+ 0x1005628a 0x7 _L1l_DevRfcSetOffsetFlag
+ 0x10056291 0x7 _L1l_DevRfcGetOffsetFlag
+ .text 0x10056298 0x2c1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x10056298 0xf _zPHY_eCSI_Calc_MultiPmiAddr_Init
+ 0x100562a7 0x8 _OSMemCopy16
+ 0x100562af 0x6 _OSMemCopy32
+ 0x100562b5 0x23 _IsTM9_PMIRIEn_CSIRS_2_4
+ 0x100562d8 0x16 _IsTM8_PMIRIEn
+ 0x100562ee 0x1a _zPHY_eCSI_Calc_Sort
+ 0x10056308 0x27 _zPHY_eCSI_Calc_MaxM
+ 0x1005632f 0x16 _zPHY_eCSI_Calc_CapMaxVal
+ 0x10056345 0x20 _zPHY_eCSI_Calc_GetSubbandIdx
+ 0x10056365 0x6c _zPHY_eCSI_Calc_eesm
+ 0x100563d1 0x59 _zPHY_eRLM_Calc_eesm
+ 0x1005642a 0x161 _zPHY_eCSI_Calc_LookupCqiTable
+ 0x1005658b 0x47 _zPHY_eCSI_Calc_WideTotalCapCalc
+ 0x100565d2 0x33 _zPHY_eCSI_Calc_WideTotalCapCalc_PerRI
+ 0x10056605 0x8e _zPHY_eCSI_Calc_WideHigh2UESubCap
+ 0x10056693 0x10c _zPHY_eCSI_Calc_BPMI
+ 0x1005679f 0x3e _zPHY_eCSI_Calc_SPMI
+ 0x100567dd 0x185 _zPHY_eCSI_Calc_RI_TM3
+ 0x10056962 0x127 _zPHY_eCSI_Calc_WPMI_TM4_LastRI
+ 0x10056a89 0x2d0 _zPHY_eCSI_Calc_RI_WPMI_TM4
+ 0x10056d59 0xe5 _zPHY_eCSI_Adjust_RI_PMI
+ 0x10056e3e 0x2e4 _zPHY_eCSI_Calc_RI_PMI
+ 0x10057122 0xd6 _zPHY_eCSI_Calc_WbCQICalc
+ 0x100571f8 0x98 _zPHY_eCSI_Calc_NoPmiGetMsbIdx
+ 0x10057290 0x82 _zPHY_eCSI_Calc_MsbCqiCalc
+ 0x10057312 0xc1 _zPHY_eCSI_Calc_SbCqiCalc
+ 0x100573d3 0x16 _zPHY_eCSI_Calc_Curr_SBSize_Get
+ 0x100573e9 0xcf _zPHY_eCSI_Calc_BpCqiCalc
+ 0x100574b8 0x6d _zPHY_eCSI_Calc_AperSbCqiUpDown
+ 0x10057525 0xb7 _zPHY_eCSI_Calc_AperCQI
+ 0x100575dc 0x9e _zPHY_eCSI_Calc_PerCQI
+ 0x1005767a 0x33 _zPHY_eCSI_Calc_Radio_Monitor
+ 0x100576ad 0x19 _zPHY_eCSI_Calc_BitReversal
+ 0x100576c6 0xf _zPHY_eCSI_Calc_GetPmiBitNum
+ 0x100576d5 0x13 _zPHY_eCSI_Calc_GetMSubbandDifferentCqiValue
+ 0x100576e8 0xf _zPHY_eCSI_Calc_GetSubbandDifferentCqiValue
+ 0x100576f7 0x30 _zPHY_eCSI_CalcMSubbandPosition
+ 0x10057727 0x18 _zPHY_eCSI_FindDiffCQI
+ 0x1005773f 0x297 _zPHY_eCSI_PER_BagPack
+ 0x100579d6 0x5ea _zPHY_eCSI_APER_BagPack
+ 0x10057fc0 0x29 _zPHY_eCSI_PER_PmiBitLen_Estimate
+ 0x10057fe9 0x52 _zPHY_eCSI_APER_PmiBitLen_Estimate
+ 0x1005803b 0x1d _zPHY_ecqi_GetLookTableSNR
+ 0x10058058 0x70 _zPHY_ecsi_Calc_Pow10_inDiv10
+ 0x100580c8 0x3e _zPHY_ecsi_Calc_Get_InvRow_feedA
+ 0x10058106 0x49 _zPHY_ecqi_Calc_Get_InvRowB_lin
+ 0x1005814f 0x243 _zPHY_ecqi_Calc_CSIRltPrint
+ 0x10058392 0x8e _zPHY_eCSI_Calc_ParaInitInDedi
+ 0x10058420 0x211 _zPHY_ecqi_SnrConv
+ 0x10058631 0x1 _zPHY_ecqi_CQISnrPrint
+ 0x10058632 0x1 _zPHY_ecqi_RlmSnrPrint
+ 0x10058633 0x1 _zPHY_ecqi_RiCapPrint
+ 0x10058634 0x60 _zPHY_ecqi_CQIFilter
+ 0x10058694 0x88 _zPHY_ecqi_Sqrt
+ 0x1005871c 0x126 _zPHY_ecsi_Calc_EstiFormatTransform
+ 0x10058842 0x11 _zPHY_ecsi_Calc_LTE_RICapFollowHw0
+ 0x10058853 0x12 _zPHY_ecsi_Calc_LTE_RICapFollowHw1
+ 0x10058865 0x16 _zPHY_ecsi_Calc_LTE_RICapFollowHw2
+ 0x1005887b 0x1c _zPHY_ecsi_Calc_LTE_RICapFollowHw4
+ 0x10058897 0x149 _zPHY_ecsi_Calc_LTE_RICloseLoop
+ 0x100589e0 0x18b _zPHY_ecsi_Calc_LTE_RIOpenLoop
+ 0x10058b6b 0x90 _zPHY_ecsi_Calc_LTE_2Tx2Rx2LWbPMI
+ 0x10058bfb 0xb1 _zPHY_ecsi_Calc_LTE_PeriodWBPmi
+ 0x10058cac 0x79 _zPHY_ecsi_Calc_LTE_GetCQICalcFunc
+ 0x10058d25 0xab _zPHY_ecsi_Calc_LTE_GetCQISNR
+ 0x10058dd0 0x16 _zPHY_ecsi_Calc_LTE_PerCQISNRCalc
+ 0x10058de6 0x94 _zPHY_ecsi_Calc_LTE_AperCQISNRCalc
+ 0x10058e7a 0x3b _zPHY_ecsi_Calc_LTE_RLMSNRCalc
+ .text 0x10058eb5 0x1592 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x10058eb5 0x1b _zPHY_Dl_HwReset
+ 0x10058ed0 0x2a0 _zPHY_epbch_ThreadEntry
+ 0x10059170 0x9a _L1e_Bch_UpdateRxRegs
+ 0x1005920a 0xa _L1e_Bch_ResetProc
+ 0x10059214 0x19 _L1e_Bch_ClkPowerCtrl
+ 0x1005922d 0x2e _L1e_Bch_JudgeSlavePbch
+ 0x1005925b 0x6 _L1e_Bch_GetMaxAntCnt
+ 0x10059261 0x1b _L1e_Bch_BwValid
+ 0x1005927c 0x10 _L1e_Bch_AntValid
+ 0x1005928c 0x7 _L1e_Bch_FrmTyeValid
+ 0x10059293 0x7 _L1e_Bch_SpecPatValid
+ 0x1005929a 0x8e _L1e_Bch_UpdateDb
+ 0x10059328 0x72 _L1e_Bch_CellSync
+ 0x1005939a 0x2b _L1e_Bch_UpRxCtrlOps
+ 0x100593c5 0x8 _L1e_Bch_ClrSyncOps
+ 0x100593cd 0x7 _L1e_Bch_QuerySyncOps
+ 0x100593d4 0x45 _L1e_Bch_PreDecProc
+ 0x10059419 0x3f _L1e_Bch_UpRxState
+ 0x10059458 0x2d _L1e_Bch_InitAllGVar
+ 0x10059485 0x2a _L1e_Bch_AddSpecTpuEvt
+ 0x100594af 0x2d _L1e_Bch_DelAllTpuEvt
+ 0x100594dc 0x1d _L1e_Bch_DelSpecTpuEvt
+ 0x100594f9 0x1a _L1e_Bch_QueryTpuEvt
+ 0x10059513 0x31 _L1e_Bch_CalStartAddr
+ 0x10059544 0x1b _L1e_Bch_GetTpuOffset
+ 0x1005955f 0x43 _L1e_Bch_CalBodryDis
+ 0x100595a2 0x1c _L1e_Bch_RegRxNewFrmEvt
+ 0x100595be 0x1 _L1e_Bch_SaveRfcSyncTable
+ 0x100595bf 0x5e _L1e_Bch_UpRfcCfg
+ 0x1005961d 0x39 _L1e_Bch_RegTpuAdjEvt
+ 0x10059656 0x86 _L1e_Bch_InitBchRegFile
+ 0x100596dc 0x72 _L1e_Bch_GenRxRsScrm
+ 0x1005974e 0xc9 _L1e_Bch_InitRxRegFile
+ 0x10059817 0x6e _L1e_Bch_GetSfnOffset
+ 0x10059885 0x5d _L1e_Bch_StopMibProc
+ 0x100598e2 0x64 _L1e_Bch_Decode
+ 0x10059946 0x89 _L1e_Bch_RltReport
+ 0x100599cf 0x11 _L1e_Bch_StartMib
+ 0x100599e0 0xe _L1e_Bch_GetMibIntCnt
+ 0x100599ee 0x2b _L1e_Bch_ModifyParaForBldDetect
+ 0x10059a19 0x2a _L1e_Bch_StartAnr
+ 0x10059a43 0x45 _L1e_Bch_AnrDecPorc
+ 0x10059a88 0xa7 _L1e_Bch_FrmIntCheck
+ 0x10059b2f 0xc _L1e_Bch_FristBchFrm
+ 0x10059b3b 0xe2 _L1e_Bch_NewFrmDecPorc
+ 0x10059c1d 0x1a _L1e_Bch_EnableSF0RxRcv
+ 0x10059c37 0x9a _L1e_Bch_AdjTpuTime
+ 0x10059cd1 0x18 _L1e_Bch_GetMibResult
+ 0x10059ce9 0x14 _L1e_Bch_CalcInitFrm
+ 0x10059cfd 0x1c _L1e_Bch_MibInfoCheck
+ 0x10059d19 0x3a _L1e_Bch_HandleCrcResult
+ 0x10059d53 0x18 _L1e_Bch_NxtBranchCtrl
+ 0x10059d6b 0xf0 _L1e_Bch_StartNxtDecode
+ 0x10059e5b 0x66 _L1e_Bch_DecideNxtDecode
+ 0x10059ec1 0x5c _L1e_Bch_IntHandle
+ 0x10059f1d 0x49 _L1e_Bch_SaveDlapara
+ 0x10059f66 0x47 _L1e_Bch_ResumeDlapara
+ 0x10059fad 0x53 _L1e_Bch_GetNCellRsNullInd
+ 0x1005a000 0x2e _L1e_Bch_GetNCellRsNullValid
+ 0x1005a02e 0x17 _L1e_Bch_WriteIntraMeasResult
+ 0x1005a045 0x90 _L1e_Bch_GetIntraMeasResult
+ 0x1005a0d5 0x6f _L1e_Bch_SortIntraMeasResult
+ 0x1005a144 0x8 _L1e_Bch_GetMibProc
+ 0x1005a14c 0x6d _L1e_Bch_Performance
+ 0x1005a1b9 0x17 _L1e_Bch_ErrorMoniter
+ 0x1005a1d0 0xc4 _L1e_Bch_RxRsrpMoniter
+ 0x1005a294 0x38 _L1e_Bch_MibReqMonitor
+ 0x1005a2cc 0x59 _L1e_Bch_RfcTpuMonitor
+ 0x1005a325 0x67 _L1e_Bch_IntRptMonitor
+ 0x1005a38c 0x6c _L1e_Bch_CrcRltMonitor
+ 0x1005a3f8 0x32 _L1e_Bch_RxParaMonitor
+ 0x1005a42a 0x1d _L1e_Bch_SerPbchRead
+ .text 0x1005a447 0x9e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x1005a447 0x7b _zPHY_edls_DlHarqReport
+ 0x1005a4c2 0x35 _zPHY_edls_ProDlHarqInit
+ 0x1005a4f7 0x6d _zPHY_edls_ProGvInit
+ 0x1005a564 0x8c _zPHY_edls_ProCommDlschParaInit
+ 0x1005a5f0 0x42 _zPHY_edls_ProSwInit
+ 0x1005a632 0xc _zPHY_edls_ProMcReleaseMsg
+ 0x1005a63e 0x4c _zPHY_edls_ProMsg4AckFeedback
+ 0x1005a68a 0xc _zPHY_edls_ProMcResetMsg
+ 0x1005a696 0x23 _zPHY_edls_ProMcMacResetMsg
+ 0x1005a6b9 0x27 _zPHY_edls_CheckHarqGroupNum
+ 0x1005a6e0 0x116 _zPHY_edls_ThreadEntry
+ 0x1005a7f6 0x4a _zPHY_edls_ProCommDlschParaCal
+ 0x1005a840 0x1 _L1e_DevDlsDdtrAxiReset
+ 0x1005a841 0x1 _L1e_DevDlsProcAxiReset
+ 0x1005a842 0xbe _L1e_DevDlsUeRacpParamInit
+ 0x1005a900 0x4b _L1e_DevDlsDecoderInit
+ 0x1005a94b 0x3e _L1e_DevDlsHarqHwInit
+ 0x1005a989 0x6c _L1e_DevDlsDdtrHwInit
+ 0x1005a9f5 0x17 _L1e_DevDlsRxTMIndCfg
+ 0x1005aa0c 0x1f _L1e_DevDlsSpsParamCfg
+ 0x1005aa2b 0x45 _L1e_DevDlsCsiRsParamCfg
+ 0x1005aa70 0x6d _L1e_DevDlsProcCommonMsg
+ 0x1005aadd 0x5e _L1e_DevDlsProcDedicatedMsg
+ 0x1005ab3b 0xa5 _L1e_DevDlsProcHandoverMsg
+ 0x1005abe0 0x8 _zPHY_edls_ProSetSpsMode
+ 0x1005abe8 0x8 _zPHY_edls_ProGetSpsMode
+ 0x1005abf0 0xe _L1e_DevDlsSetTimeInfo
+ 0x1005abfe 0xd _L1e_DevDlsSetCellParam1
+ 0x1005ac0b 0xd _L1e_DevDlsSetCellparam2
+ 0x1005ac18 0xd _L1e_DevDlsSetRntiInfo
+ 0x1005ac25 0xf _L1e_DevDlsGetTimeInfo
+ 0x1005ac34 0x1a _L1e_DevDlsGetCellParam1
+ 0x1005ac4e 0x1a _L1e_DevDlsGetCellParam2
+ 0x1005ac68 0x1a _L1e_DevDlsGetRntiInfo
+ 0x1005ac82 0x19 _L1e_DevDlsSetDciF1aPld
+ 0x1005ac9b 0x10 _L1e_DevDlsSetDciF1cPld
+ 0x1005acab 0x10 _L1e_DevDlsSetDciFxxPld
+ 0x1005acbb 0xe _L1e_DevDlsSetDciCifSize
+ 0x1005acc9 0xe _L1e_DevDlsSetDciRaHeaderSize
+ 0x1005acd7 0x10 _L1e_DevDlsSetDciRbaSize
+ 0x1005ace7 0xe _L1e_DevDlsSetDciHarqIdSize
+ 0x1005acf5 0xe _L1e_DevDlsSetDciDaiSize
+ 0x1005ad03 0xe _L1e_DevDlsSetDciTpmiSize
+ 0x1005ad11 0xe _L1e_DevDlsSetDciScidSize
+ 0x1005ad1f 0xe _L1e_DevDlsSetDciSrsReqSize
+ 0x1005ad2d 0x1a _L1e_DevDlsGetDciF1aPld
+ 0x1005ad47 0x10 _L1e_DevDlsGetDciF1cPld
+ 0x1005ad57 0x10 _L1e_DevDlsGetDciFxxPld
+ 0x1005ad67 0xd _L1e_DevDlsGetDciCifSize
+ 0x1005ad74 0xd _L1e_DevDlsGetDciRaHeaderSize
+ 0x1005ad81 0x11 _L1e_DevDlsGetDciRbaSize
+ 0x1005ad92 0xd _L1e_DevDlsGetDciHarqIdSize
+ 0x1005ad9f 0xd _L1e_DevDlsGetDciDaiSize
+ 0x1005adac 0xd _L1e_DevDlsGetDciTpmiSize
+ 0x1005adb9 0xd _L1e_DevDlsGetDciScidSize
+ 0x1005adc6 0xd _L1e_DevDlsGetDciSrsReqSize
+ 0x1005add3 0x8 _L1e_DevDlsDdtrUpdateCntCbInit
+ 0x1005addb 0xc _L1e_DevDlsDdtrUpdateCntInc
+ 0x1005ade7 0xc _L1e_DevDlsDdtrUpdateCntClr
+ 0x1005adf3 0x9 _L1e_DevDlsGetDdtrCcUpdateCnt
+ 0x1005adfc 0x7 _L1e_DevDlsGetDdtrUpdateCnt
+ 0x1005ae03 0x7 _L1e_DevDlsSetMsg4RaConflictCnt
+ 0x1005ae0a 0x7 _L1e_DevDlsGetMsg4RaConflictCnt
+ 0x1005ae11 0x9 _L1e_DevDlsMsg4RaConflictCntDec
+ 0x1005ae1a 0x8 _L1e_DevDlsMsg4RaConflictCntClr
+ 0x1005ae22 0x8 _L1e_DevDlsGetTransMode
+ .text 0x1005ae2a 0xbf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x1005ae2a 0x69 _zPHY_ecsi_ctrl_Init
+ 0x1005ae93 0x80 _zPHY_ecsi_StaticBandParaUpdata
+ 0x1005af13 0x28 _zPHY_ecsi_ctrl_PeriodParaUpdate
+ 0x1005af3b 0x7a _zPHY_ecsi_ctrl_AperiodParaUpdate
+ 0x1005afb5 0x7d _zPHY_ecsi_ctrl_AperRepJudge
+ 0x1005b032 0x3f _zPHY_ecsi_ctrl_GetSubbandIdx
+ 0x1005b071 0x51 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcTDD
+ 0x1005b0c2 0x57 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcFDD
+ 0x1005b119 0x32 _zPHY_ecsi_ctrl_RiConfigIndexCalc
+ 0x1005b14b 0x6b _zPHY_ecsi_ctrl_GetPeriodPara
+ 0x1005b1b6 0x14a _zPHY_ecsi_ctrl_GetPeriodRepType
+ 0x1005b300 0xcb _zPHY_ecsi_ctrl_LastRIInit
+ 0x1005b3cb 0x4a _zPHY_ecsi_ctrl_GetMaxLayerNum
+ 0x1005b415 0x71 _zPHY_ecsi_ctrl_SecondCfg
+ 0x1005b486 0x8 _zPHY_ecsi_ctrl_SentCqiRlmProMsg
+ 0x1005b48e 0xc _zPHY_ecsi_ctrl_RlmProEn
+ 0x1005b49a 0x87 _zPHY_ecsi_ctrl_FirIntPrint
+ 0x1005b521 0xa9 _zPHY_ecsi_ctrl_FdBkFirst_IntIsr
+ 0x1005b5ca 0x1e _zPHY_ecsi_ctrl_FdBkSecond_IntIsr
+ 0x1005b5e8 0x1b _zPHY_ecsi_ctrl_FdBk_IntIsr
+ 0x1005b603 0x5c _zPHY_ecsi_ctrl_First_GetEnStep1
+ 0x1005b65f 0x69 _zPHY_ecsi_ctrl_FdBkFirCfgAper
+ 0x1005b6c8 0xbd _zPHY_ecsi_ctrl_FdBkFirCfgPer
+ 0x1005b785 0xcd _zPHY_ecsi_ctrl_First_FdBkCfg
+ 0x1005b852 0x3a _zPHY_ecsi_ctrl_ULGetCSI_Callback
+ 0x1005b88c 0x71 _zPHY_ecsi_Ctrl_CqiRlmCalc
+ 0x1005b8fd 0x2f _zPHY_ecsi_ctrl_PreBagPack
+ 0x1005b92c 0x33 _zPHY_ecsi_ctrl_FindPreDlSfn
+ 0x1005b95f 0xbd _zPHY_ecsi_ctrl_DrxRfZspCtrl
+ .text 0x1005ba1c 0x1ab3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x1005ba1c 0x7 _L1e_DevRxGetAveSinr
+ 0x1005ba23 0x1d _zPHY_erxp_convert_RbNum_to_BWIdx
+ 0x1005ba40 0x7 _L1e_DevRxCirSetIdleAccessReqInd
+ 0x1005ba47 0x7 _L1e_DevRxCirGetIdleAccessReqInd
+ 0x1005ba4e 0x1b2 _zPHY_erxph_ThreadEntry
+ 0x1005bc00 0x173 _L1e_DevRxPowerPrepare
+ 0x1005bd73 0x55 _L1e_DevRxGetSnrFilterFactor
+ 0x1005bdc8 0xa0 _zPHY_erxp_PowerFilterInit
+ 0x1005be68 0x97 _zPHY_erxp_ProPowerFilter
+ 0x1005beff 0x149 _zPHY_erxp_ProSnrMake
+ 0x1005c048 0x64 _zPHY_erxp_ProSnrDB
+ 0x1005c0ac 0x54 _zPHY_erxp_ProLog2
+ 0x1005c100 0x19e _L1e_DevRxProcPwrNbnb
+ 0x1005c29e 0x8a _L1e_DevRxCalcRsrpPwr
+ 0x1005c328 0x36 _L1e_DevRxProcSnrPwrFilter
+ 0x1005c35e 0x50 _L1e_DevRxCalcLinearSnr
+ 0x1005c3ae 0x3e _L1e_DevRxCalcLinearSinr
+ 0x1005c3ec 0x5c _L1e_DevRxConvertSnrDbValue
+ 0x1005c448 0x88 _L1e_DevRxCalcAveSnr
+ 0x1005c4d0 0xa _L1e_DevRxGetAveSnr
+ 0x1005c4da 0xa _L1e_DevRxGetNeiAveSnr
+ 0x1005c4e4 0x14 _L1e_DevRxCalSign
+ 0x1005c4f8 0xa6 _L1e_DevRxCalcMod
+ 0x1005c59e 0x6e _L1e_DevRxDbgMsgRxCrsPwr
+ 0x1005c60c 0x91 _L1e_DevRxDbgMsgRxDrsPwr
+ 0x1005c69d 0x5d _L1e_DevRxDbgMsgRxSnrInfo
+ 0x1005c6fa 0x81 _L1e_DevRxDbgMsgSyncInfo
+ 0x1005c77b 0x48 _L1e_LogDevRxMbsfnCsiInfo
+ 0x1005c7c3 0x54 _L1e_DevRxDbgMsgRxHResult
+ 0x1005c817 0x54 _L1e_DevRxDbgMsgRxPrbN0
+ 0x1005c86b 0x17 _L1e_DevRxExpInfo
+ 0x1005c882 0x1c _L1e_DevRxRssiRead
+ 0x1005c89e 0x2b _L1e_DevRxRspRead
+ 0x1005c8c9 0x25 _L1e_DevRxRsrpRead
+ 0x1005c8ee 0x43 _L1e_DevRxN0Read
+ 0x1005c931 0x15 _L1e_DevRxMrsN0Read
+ 0x1005c946 0x7a _L1e_DevRxGetRxLogInfo
+ 0x1005c9c0 0x20 _L1e_DevRxGetDfeAgcGain
+ 0x1005c9e0 0x14 _L1e_DevRxGetRxAntNum
+ 0x1005c9f4 0x7 _L1e_DevRxSetSingleAntInd
+ 0x1005c9fb 0x7 _L1e_DevRxGetSingleAntInd
+ 0x1005ca02 0x9 _L1e_DevRxSetNbNbSinrCalInd
+ 0x1005ca0b 0x9 _L1e_DevRxGetNbNbSinrCalInd
+ 0x1005ca14 0x9 _L1e_DevRxSetDrsAccNum
+ 0x1005ca1d 0x9 _L1e_DevRxGetDrsAccNum
+ 0x1005ca26 0x9 _L1e_DevRxSetBfDagcFlag
+ 0x1005ca2f 0x9 _L1e_DevRxGetBfDagcFlag
+ 0x1005ca38 0x5f _L1e_DevRxProcBfDagcFlag
+ 0x1005ca97 0x7 _L1e_DevRxPrintCtrlCfg
+ 0x1005ca9e 0x7 _L1e_DevRxPrintCtrlGet
+ 0x1005caa5 0x9 _L1e_DevRxPrintCtrlCnt
+ 0x1005caae 0x22c _L1e_DevRxCalcCsi
+ 0x1005ccda 0x11c _L1e_DevRxCsiLog
+ 0x1005cdf6 0xe _L1e_DevRxSetAntChangeInd
+ 0x1005ce04 0xd _L1e_DevRxGetAntChangeInd
+ 0x1005ce11 0xb4 _zPHY_erxp_RX_DFE_UERS
+ 0x1005cec5 0x10 _zPHY_erxp_RX_SNR
+ 0x1005ced5 0xe _L1e_DevRxSetCfoWorkInd
+ 0x1005cee3 0xd _L1e_DevRxGetCfoWorkInd
+ 0x1005cef0 0x1f _L1e_DevRxSetSinrInd
+ 0x1005cf0f 0x10 _L1e_DevRxGetSinrInd
+ 0x1005cf1f 0x2b _L1e_DevRxGetLowSinrInd
+ 0x1005cf4a 0x11 _L1e_DevReadSnr
+ 0x1005cf5b 0x8 _L1e_DevRxClearFilterInd
+ 0x1005cf63 0x42 _L1e_DevGetNeiBorCellMaxSnr
+ 0x1005cfa5 0x7 _L1e_DevRxGetCellComponState
+ 0x1005cfac 0x7 _L1e_DevRxSetCellComponState
+ 0x1005cfb3 0x7 _L1e_DevRxSetAdaptAntProcInd
+ 0x1005cfba 0x7 _L1e_DevRxGetAdaptAntProcInd
+ 0x1005cfc1 0xaa _L1e_DevRxAdaptAntProc
+ 0x1005d06b 0x44 _L1e_DevRxAdaptAntResult
+ 0x1005d0af 0x3a _L1e_DevRxAdaptAntUpdate
+ 0x1005d0e9 0x36 _L1e_DevRxAdaptSinrAcc
+ 0x1005d11f 0x101 _L1e_DevRxAdaptCalSinr
+ 0x1005d220 0x34 _L1e_DevRxAdaptAgcGainAcc
+ 0x1005d254 0x10 _L1e_DevRxAdaptGetAveResult
+ 0x1005d264 0x8 _L1e_DevRxAdaptGetRsrpRange
+ 0x1005d26c 0x58 _L1e_DevRxAdaptSetRsrpInterval
+ 0x1005d2c4 0x13 _L1e_DevRxClrAdaptAntInfo
+ 0x1005d2d7 0xa _L1e_DevRxAdaptBetaUpdate
+ 0x1005d2e1 0x26 _L1e_DevRxAdaptJudge
+ 0x1005d307 0xa _L1e_DevRxIncN1Timer
+ 0x1005d311 0x8 _L1e_DevRxGetN1Timer
+ 0x1005d319 0x9 _L1e_DevRxClrN1Timer
+ 0x1005d322 0x8 _L1e_DevRxSetN1StartInd
+ 0x1005d32a 0x8 _L1e_DevRxGetN1StartInd
+ 0x1005d332 0xa _L1e_DevRxIncN2Timer
+ 0x1005d33c 0x9 _L1e_DevRxClrN2Timer
+ 0x1005d345 0x8 _L1e_DevRxGetN2Timer
+ 0x1005d34d 0x8 _L1e_DevRxSetN2StartInd
+ 0x1005d355 0x8 _L1e_DevRxGetN2StartInd
+ 0x1005d35d 0x8 _L1e_DevRxSetAdaptStartInd
+ 0x1005d365 0xa _L1e_DevRxGetDLTimer
+ 0x1005d36f 0x8 _L1e_DevRxGetAdaptStartInd
+ 0x1005d377 0x8 _L1e_DevRxGetAdaptResult
+ 0x1005d37f 0x8 _L1e_DevRxSetAdaptResult
+ 0x1005d387 0x8 _L1e_DevRxSetAdaptChangeInd
+ 0x1005d38f 0x8 _L1e_DevRxGetAdaptChangeInd
+ 0x1005d397 0x64 _L1e_DevRxDbgAdptAntInfo
+ 0x1005d3fb 0x6f _L1e_DevRxDbgAdptchangeInfo
+ 0x1005d46a 0x65 _L1e_DevRxAntInfoGetForTool
+ .text 0x1005d4cf 0x1c42 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x1005d4cf 0x69 _zPHY_LteaSysInfoPrint
+ 0x1005d538 0x1d _L1L_elpc_Dvfs
+ 0x1005d555 0x107 _zPHY_elpc_LtePhyTaskStateInfo
+ 0x1005d65c 0x9 _zPHY_elpc_SetCfunFlg
+ 0x1005d665 0x42 _zPHY_elpc_SetLteCamonFlag
+ 0x1005d6a7 0x22 _zPHY_elpc_SetLteConnectFlag
+ 0x1005d6c9 0x28 _zPHY_elpc_SetIratGapReportFlag
+ 0x1005d6f1 0x19 _L11_DrvLpcModemIntCtrl
+ 0x1005d70a 0xe _zPHY_elpc_SetlLtePhySleepFlag
+ 0x1005d718 0x1f _zPHY_elpc_LteIdleTaskStateCtrl
+ 0x1005d737 0x264 _zPHY_elpc_UpdateLteSubFrameNum
+ 0x1005d99b 0x24 _L1L_UpdateAwakeTimer
+ 0x1005d9bf 0x1e _L1L_SetAwakeTimer
+ 0x1005d9dd 0xc _L1L_IsAwakeTimerEnable
+ 0x1005d9e9 0x38 _zPHY_elpc_ProKeepAwakeTimer
+ 0x1005da21 0x87 _zPHY_elpc_ProSleepTimer
+ 0x1005daa8 0x2 _L1_TdSleepInfoPrint
+ 0x1005daaa 0x18 _zPHY_eLpc_GetLpm32KCALIPara
+ 0x1005dac2 0x269 _L1_CpuPhySleepInfo
+ 0x1005dd2b 0x34 _L1L_PrintPwrCtrlInfo
+ 0x1005dd5f 0x29 _L1L_PrintModemClkCtrlInfo
+ 0x1005dd88 0x8e _zPHY_elpc_LpmCalibrationLog
+ 0x1005de16 0x50 _zPHY_elpc_GetLpmCaliIdx
+ 0x1005de66 0x7e _zPHY_elpc_LpmCalibrationProc
+ 0x1005dee4 0x11 _zPHY_elpc_LpmCalibrationParaUpdate
+ 0x1005def5 0x40 _zPHY_eLpc_RecordTpuMrtrForCaliTest
+ 0x1005df35 0xf _zPHY_elpc_IsRfStateIdle
+ 0x1005df44 0x1 _zPHY_elpc_RficSccSleepCtrl
+ 0x1005df45 0x63 _zPHY_eLpc_Lpm32KCALIInfor
+ 0x1005dfa8 0xf1 _zPHY_eLpc_PintCpuAxiFreq
+ 0x1005e099 0x17 _zPHY_eLpc_PrintIcpResult
+ 0x1005e0b0 0x19b _zPHY_eLpc_ChipCfgInfor
+ 0x1005e24b 0x8e _zPHY_eLpc_TimeSysInfo
+ 0x1005e2d9 0x4b4 _zPHY_elpc_CaliTempCompensate
+ 0x1005e78d 0xb _L1L_eLpc_AsynMsgProc
+ 0x1005e798 0x2c1 _L1L_elpc_WakeupMsgFlow
+ 0x1005ea59 0x23a _L1L_elpc_LpmWakeupFlow
+ 0x1005ec93 0x94 _L1L_LPInit
+ 0x1005ed27 0x2 _zPHY_elpc_Init
+ 0x1005ed29 0x6d _L1L_LpcCfgSocWkupInt
+ 0x1005ed96 0x14 _L1L_LpcDisSocWkupInt
+ 0x1005edaa 0x15 _L1L_WakeupIsr
+ 0x1005edbf 0x2b4 _L1L_ModemLpcSleep
+ 0x1005f073 0x9e _L1L_ModemLpcWakeup
+ .text 0x1005f111 0xfa8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x1005f113 0x3d _zPHY_erfc_DrvCheckNVBandWithRFBand
+ 0x1005f150 0x3b _zPHY_erfc_FindNVBandWithRFBand
+ 0x1005f18b 0x3e _zPHY_erfc_DrvCheckTpCompNV
+ 0x1005f1c9 0x2a _zPHY_erfc_SupBinarySearchNv
+ 0x1005f1f3 0xad _zPHY_erfc_SupSampleRateSet
+ 0x1005f2a0 0x82 _zPHY_erfc_SupNVBandIndexInit
+ 0x1005f322 0x1b _zPHY_erfc_SupGlobalVarInit
+ 0x1005f33d 0x18e _zPHY_erfc_InitTableByDma
+ 0x1005f4cb 0x1 _zPHY_erfc_SupIntTxTable
+ 0x1005f4cc 0x129 _zPHY_erfc_SupIntRFC
+ 0x1005f5f5 0x1e _zPHY_erfc_SupBinarySearchAdc
+ 0x1005f613 0x39 _zPHY_erfc_SupCalcDiffpower
+ 0x1005f64c 0x38 _zPHY_erfc_SupCalcDiffpower7510ACP
+ 0x1005f684 0x36 _zPHY_erfc_SupEventRxoffsetEn
+ 0x1005f6ba 0x1c _zPHY_erfc_SupTxSymbSend
+ 0x1005f6d6 0xa _zPHY_erfc_SupTxFclkCtrl
+ 0x1005f6e0 0x2e _zPHY_erfc_SupDFEFrontEsti
+ 0x1005f70e 0x11 _zPHY_erfc_SupDFEpath0RxControl
+ 0x1005f71f 0x1a _zPHY_erfc_SupDFERxDAGC0estiControl
+ 0x1005f739 0x27 _zPHY_erfc_SupDFERxRemovCpControl
+ 0x1005f760 0x11 _zPHY_erfc_SupDFEpath1Meas0Control
+ 0x1005f771 0x1f5 _zPHY_erfc_SupDFEMeas0RemovCpControl
+ 0x1005f966 0x66 _zPHY_erfc_SupDFEMeas0eICICControl
+ 0x1005f9cc 0x21 _zPHY_erfc_SupDFEpath2CellSearchControl
+ 0x1005f9ed 0x2b _zPHY_erfc_SupDFECellSearchDAGC2estiControl
+ 0x1005fa18 0x1 _zPHY_erfc_SupDFEMeas0DAGC1estiControl
+ 0x1005fa19 0x3a _zPHY_erfc_SupDFESubframeStart
+ 0x1005fa53 0x14 _zPHY_erfc_SupDFEFrameStart
+ 0x1005fa67 0x1 _zPHY_erfc_SupSetTDDFDD
+ 0x1005fa68 0x24 _zPHY_erfc_SupEnterLowPower
+ 0x1005fa8c 0x296 _zPHY_erfc_SupLeaveLowPower
+ 0x1005fd22 0x1 _zPHY_erfc_SupRfGPIOOpen
+ 0x1005fd23 0x41 _zPHY_erfc_SupRfRxOpen
+ 0x1005fd64 0x1 _zPHY_erfc_SupRfGPIOClose
+ 0x1005fd65 0x1 _zPHY_erfc_SupRfRxClose
+ 0x1005fd66 0x23 _zPHY_erfc_SupRfEnterLightSleep
+ 0x1005fd89 0x26 _zPHY_erfc_SupRfEnterDeepSleep
+ 0x1005fdaf 0x22 _zPHY_erfc_SupRfLeaveLightSleep
+ 0x1005fdd1 0x23 _zPHY_erfc_SupRfLeaveDeepSleep
+ 0x1005fdf4 0x2c _zPHY_erfc_SupRfLeaveSleep
+ 0x1005fe20 0x24 _zPHY_erfc_SupRfWakeUpRxOpen
+ 0x1005fe44 0x1e _zPHY_erfc_SupRfRxCloseSleep
+ 0x1005fe62 0x4d _zPHY_erfc_SupGetUserNVBandIndex
+ 0x1005feaf 0x3a _zPHY_erfc_SupGetCaliNVBandIndex
+ 0x1005fee9 0x6f _zPHY_erfc_SupNotchEn
+ 0x1005ff58 0xa _zPHY_erfc_SupWriteTempCompDacToIram
+ 0x1005ff62 0x157 _zPHY_erfc_SupGetRBESF
+ .text 0x100600b9 0x5f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x100600b9 0x12 _zPHY_ecsrm_ProReset
+ 0x100600cb 0x17 _zPHY_ecsrm_InitialGlobalVar
+ 0x100600e2 0x55 _zPHY_ecsrm_IsBlackCell
+ 0x10060137 0x88 _zPHY_ecsrm_BuffGetEveryRfcOpenTime
+ 0x100601bf 0xe3 _zPHY_ecsrm_GetRfcOpenTime
+ 0x100602a2 0xba _zPHY_ecsrm_GetRfcOpenTimeFddIdle
+ 0x1006035c 0x8 _zPHY_ecsrm_SetDdMode
+ 0x10060364 0x94 _zPHY_ecsrm_CfgRfcData
+ 0x100603f8 0x2 _zPHY_ecsrm_OnReset
+ 0x100603fa 0x4a _zPHY_ecsrm_OnSearchMeasStart
+ 0x10060444 0x12 _zPHY_ecsrm_OnSearchMeasReset
+ 0x10060456 0x21 _zEcsm_PreEvent
+ 0x10060477 0x38 _L1e_csrm_SfProc
+ 0x100604af 0x1fe _zPHY_ecsrm_WriteRfcEventTabNew
+ .text 0x100606ad 0x1edb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x100606ad 0x3d _zPHY_ecsrm_AveMeasResult
+ 0x100606ea 0x18 _zPHY_ecsrm_AveValLog
+ 0x10060702 0x8 _zPHY_ecsrm_CalSint16ResVal
+ 0x1006070a 0x2 _zPHY_ecsrm_PointToInt
+ 0x1006070c 0x21 _zPHY_ecsrm_CalApproValLog
+ 0x1006072d 0x8 _zPHY_ecsrm_ClearMeasResult
+ 0x10060735 0xd _zPHY_ecsrm_InitialMeasCommPara
+ 0x10060742 0x9 _zPHY_ecsrm_RegistPeriodSfInt
+ 0x1006074b 0xc _L1e_csrm_ClearCurCellInfo
+ 0x10060757 0xfa _zPHY_ecsrm_JudgeMeasState
+ 0x10060851 0x1f _zPHY_escrm_GetFbRelatn
+ 0x10060870 0x2b _zPHY_ecsrm_GetRsNumLogIndex
+ 0x1006089b 0x34 _zPHY_ecsrm_CalModVal
+ 0x100608cf 0x59 _zPHY_ecsrm_Q8log2
+ 0x10060928 0x3c _zPHY_ecsrm_Logarithm
+ 0x10060964 0x3b _zPHY_ecsrm_GetAntAgcCsrm
+ 0x1006099f 0x17 _zPHY_ecsrm_CfgDfeBandCsr
+ 0x100609b6 0x3b _zPHY_ecsrm_GetAntAgcRx
+ 0x100609f1 0x119 _zPHY_ecsrm_ReadRsrpNvInfo
+ 0x10060b0a 0x19 _zPHY_ecsrm_CalLog
+ 0x10060b23 0x25 _zPHY_ecsrm_ReadCaliNvPoint
+ 0x10060b48 0x26 _zPHY_ecsrm_WriteMeasResult
+ 0x10060b6e 0xa4 _zPHY_ecsrm_CalRsrpOffset
+ 0x10060c12 0x1ee _zPHY_ecsrm_CalRsrpRssi
+ 0x10060e00 0xe6 _zPHY_ecsrm_CalRsrpForRx
+ 0x10060ee6 0x18 _zPHY_ecsrm_ReadRealOffet
+ 0x10060efe 0xf1 _zPHY_ecsrm_CalSinr
+ 0x10060fef 0x9 _zPHY_ecrsm_DelAllTpuInt
+ 0x10060ff8 0x2e _zPHY_ecsrm_Buffer_TDDMode
+ 0x10061026 0x36 _zPHY_ecsrm_Idle_Buffer_FddMode
+ 0x1006105c 0x29 _zPHY_ecsrm_Idle_FddMode
+ 0x10061085 0x2c _zPHY_ecsrm_Idle_FddScheInAny
+ 0x100610b1 0x31 _zPHY_ecsrm_Idle_FddReadInAny
+ 0x100610e2 0x26 _zPHY_ecsrm_ClearMeasCellInfo
+ 0x10061108 0x40 _zPHY_ecsrm_ClearBuffInfo
+ 0x10061148 0x34 _zPHY_ecsrm_half_FrameBoundrySub
+ 0x1006117c 0x25 _zPHY_ecsrm_BuffSlaveHFS
+ 0x100611a1 0x44 _zPHY_ecsrm_BuffSlaveMaxBdySub
+ 0x100611e5 0x13 _zPHY_ecsrm_GetCurrCellId
+ 0x100611f8 0x97 _zPHY_ecsrm_UpdateResIntoDbNew
+ 0x1006128f 0x2e _zPHY_ecsrm_ClearMeasResultNew
+ 0x100612bd 0x5d _zPHY_ecsrm_UpdateMeasResultNew
+ 0x1006131a 0x2a _zPHY_ecsrm_Half_Frame_Bdy_Sub
+ 0x10061344 0x25 _zPHY_ecsrm_GetBuffSlaveOpenSfNum
+ 0x10061369 0x3d _zPHY_ecsrm_GetBuffMeasSfNum
+ 0x100613a6 0x2c _zPHY_ecsrm_GetMeasSfNum
+ 0x100613d2 0x10a _zPHY_ecsrm_CalRsrpNew
+ 0x100614dc 0x29 _zPHY_ecsrm_GetNextSchTime
+ 0x10061505 0x1c _zPHY_ecsrm_ClearMeasSch
+ 0x10061521 0x6a _zPHY_ecsrm_DiscardMeas
+ 0x1006158b 0x81 _GetMeasInfo
+ 0x1006160c 0x50 _SetMeasAgeInfo
+ 0x1006165c 0xbf _zPHY_ecsrm_MeasGetCell
+ 0x1006171b 0x10e _zPHY_ecsrm_GetCsrmRegParaNew
+ 0x10061829 0x69 _zPHY_ecsrm_GetDFEBuffFbRelatn
+ 0x10061892 0xc8 _zPHY_ecsrm_GetDFEBuffRegPara
+ 0x1006195a 0xb7 _zPHY_ecsrm_GetDFECellMeasPara_FDD
+ 0x10061a11 0xf7 _zPHY_ecsrm_GetDFECellMeasPara_TDD
+ 0x10061b08 0x97 _zPHY_ecsrm_HandleCsrHWNormalNew
+ 0x10061b9f 0x12 _zPHY_ecsrm_Need_Wait_Cnditon
+ 0x10061bb1 0x9d _zPHY_ecsrm_Wait_MeasPeriodProc
+ 0x10061c4e 0x9a _zPHY_ecsrm_HandleMeasResultNormalNew
+ 0x10061ce8 0x123 _zPHY_ecsrm_MeasSeekToWorkTime
+ 0x10061e0b 0xb _zPHY_ecsrm_OnMeasStart
+ 0x10061e16 0x4a _zPHY_ecsrm_MulmGapCheck
+ 0x10061e60 0x162 _zPHY_ecsrm_MeasConfigHw
+ 0x10061fc2 0xc0 _zPHY_ecsrm_MeasReadResult
+ 0x10062082 0x23 _zPHY_ecsrm_BufferScene
+ 0x100620a5 0x32 _zPHY_ecsrm_CsrFingerSort
+ 0x100620d7 0x4 _zPHY_ecsrc_RemoveMrtrFrame
+ 0x100620db 0x58 _zPHY_ecsrm_half_FrameBoundryCenter
+ 0x10062133 0x4e _zPHY_ecsrm_GetBdyMeasCell
+ 0x10062181 0x215 _zPHY_ecsrm_GetMeasmodeAndCell
+ 0x10062396 0x10 _zPHY_ecsrm_GetMeasCellEarfcn
+ 0x100623a6 0xd3 _eL1_CalCellCfgCont
+ 0x10062479 0x2c _zPHY_ecsrm_GetSF0SF5
+ 0x100624a5 0x2d _zPHY_ecsrm_BeforeBufferMeas
+ 0x100624d2 0x95 _zPHY_ecsrm_MeasNextCell
+ 0x10062567 0x7 _zPHY_ecsrm_SetCaIndex
+ 0x1006256e 0x10 _zPHY_ecsrm_MeasNeedPrimary
+ 0x1006257e 0xa _l1e_csrm_GetMeasFalg
+ .text 0x10062588 0x31e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x10062588 0x1c1 _zPHY_UL_CSI_CombThreadEntry
+ 0x10062749 0x15d _zPHY_DLA_ULSL_CombThreadEntry
+ .text 0x100628a6 0x1861 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x100628a6 0x27 _L1e_DevRxFssSetModIdx
+ 0x100628cd 0xcd _zPHY_eMBMS_CirSearchWinPos_Calc
+ 0x1006299a 0x27 _L1e_DevRxDoubleAntCheckOnlyOneValid
+ 0x100629c1 0x3d _L1e_DevCirPreSyncAcc
+ 0x100629fe 0x5e _L1e_DevCirPreSyncProtect
+ 0x10062a5c 0x43 _zPHY_erxp_CirProc
+ 0x10062a9f 0x25 _zPHY_erxp_CirAdjBorderOfSubframe
+ 0x10062ac4 0x9 _zPHY_eCir_PccPdsch_DmaCallback
+ 0x10062acd 0x9 _zPHY_eCir_SccPdsch_DmaCallback
+ 0x10062ad6 0x9 _zPHY_eCir_PccEicic_DmaCallback
+ 0x10062adf 0x8 _L1e_DevRxSetMbsfnCirIntInt
+ 0x10062ae7 0x1a _L1e_DevRxMbmsCirIntProc
+ 0x10062b01 0x44 _L1e_DevRxFssMainAntFlagSet
+ 0x10062b45 0xd _L1e_DevRxFssMainAntFlagGet
+ 0x10062b52 0xe _L1e_DevRxRefSenDecodeCnt
+ 0x10062b60 0xd _L1e_DevRxRefSenDecodeCntGet
+ 0x10062b6d 0xd _L1e_DevRxRefSenDecodeCntClr
+ 0x10062b7a 0xe _L1e_DevRxRefSenCnt
+ 0x10062b88 0xd _L1e_DevRxRefSenCntGet
+ 0x10062b95 0xd _L1e_DevRxRefSenCntClr
+ 0x10062ba2 0xe _L1e_DevRxRefSenIndCfg
+ 0x10062bb0 0xd _L1e_DevRxRefSenIndGet
+ 0x10062bbd 0x16 _L1e_devRxMrsFIUpdateIndSet
+ 0x10062bd3 0x16 _L1e_devRxMrsBetaUpdateIndSet
+ 0x10062be9 0x18 _L1e_devRxMrsFIUpdateIndGet
+ 0x10062c01 0x18 _L1e_devRxMrsBetaUpdateIndGet
+ 0x10062c19 0x23 _L1e_devRxMrsFIDataAddrGet
+ 0x10062c3c 0x19 _L1e_devRxMrsBetaGet
+ 0x10062c55 0x93e _zPHY_eMBMS_CirInitFftSeq
+ 0x10063593 0xa8 _zPHY_ecir_SW_DynFiRegUdate
+ 0x1006363b 0x135 _zPhy_eMBMS_cir_nomarlize_fir_coeff
+ 0x10063770 0x16a _zPHY_ecir_Apply_Triangle_Window
+ 0x100638da 0xcb _zPhy_ecir_CalcBeta_R01
+ 0x100639a5 0x95 _zPHY_erxp_BchNormalCirCtrl
+ 0x10063a3a 0x23 _zPHY_erxp_CirCfgForBch
+ 0x10063a5d 0x577 _L1e_DevRxCirCtrlCfg
+ 0x10063fd4 0x63 _L1e_DevRxSetRxOffsetAdjTiMode
+ 0x10064037 0x7 _zPHY_ecir_CellChangeSet
+ 0x1006403e 0xc9 _zPHY_ecir_CellChangeGet
+ *fill* 0x10064107 0x80000001 00
+ .text 0x10064108 0x203 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x10064108 0xc4 _zPHY_ecir_Fft256
+ 0x100641cc 0xb _zPhy_ecir_continuous_add
+ 0x100641d7 0x17 _zPhy_ecir_search_max_value
+ 0x100641ee 0xa _zPhy_ecir_acquire_fir_coeff
+ 0x100641f8 0x35 _zPhy_eMBMS_cir_midify_nosieEff
+ 0x1006422d 0x2d _zPhy_ecir_generet_fir_coeff
+ 0x1006425a 0x37 _zPhy_ecir_midify_nosieEff
+ 0x10064291 0x7a _Asm_CIR_FIRCoeffNorm
+ .text 0x1006430b 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x1006430b 0x9 _L1e_DevRxSetRsrpIntInd
+ 0x10064314 0x9 _L1e_DevRxGetRsrpIntInd
+ 0x1006431d 0x1f _L1e_DevRxSetServingCellInd
+ 0x1006433c 0x10b _zPHY_erxp_Cfo_Isr
+ 0x10064447 0x44 _L1e_DevCFOPreSyncAcc
+ 0x1006448b 0x4e _L1e_DevCfoFilterCoeffAdapt
+ 0x100644d9 0x1e _L1e_DevCfoCfgTempRead
+ 0x100644f7 0x59 _L1e_DevSetCfoCoeffK
+ 0x10064550 0xfb _L1e_DevGetCfoCoeffK
+ 0x1006464b 0xa _L1e_DevRxRsrpFilterFlagInit
+ 0x10064655 0x3f _L1e_DevRxGetRsrpFilterCoeff
+ 0x10064694 0x116 _zPHY_erxp_CalRsrpFilter
+ 0x100647aa 0x92 _zPHY_erxp_RsrpFilter
+ 0x1006483c 0xd _L1e_DevRxGetFastCfoConvergenceCnt
+ 0x10064849 0xe _L1e_DevRxSetFastCfoConvergenceCnt
+ 0x10064857 0xe _L1e_DevRxDecreaseFastCfoCnt
+ .text 0x10064865 0x200d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x10064865 0x249 _zPHY_edfe_SupInitDFE
+ 0x10064aae 0x24 _zPHY_edfe_WriteSnrTh
+ 0x10064ad2 0x71 _zPHY_edfe_DCOffsetCal
+ 0x10064b43 0xea _zPHY_edfe_SupNormalHandleDCOffset
+ 0x10064c2d 0xa9 _zPHY_edfe_IQImbaCal
+ 0x10064cd6 0x77 _zPHY_edfe_SupHandleIQImba
+ 0x10064d4d 0x51 _zPHY_edfe_NormalNotSyncAgcIntHandle
+ 0x10064d9e 0x8 _zPHY_edfe_SupInt0Handle
+ 0x10064da6 0x14 _zPHY_edfe_SupInt1Handle
+ 0x10064dba 0x15 _zPHY_edfe_SupInt2Handle
+ 0x10064dcf 0x39 _zPHY_edfe_ProDfeInt
+ 0x10064e08 0x27 _zPHY_edfe_ConfigRXBandwidth
+ 0x10064e2f 0x22 _zPHY_edfe_ConfigCSRMBandwidth
+ 0x10064e51 0x7d _zPHY_edfe_CompesateCFO
+ 0x10064ece 0x72 _zPHY_edfe_CalMeasTotalAGCGain
+ 0x10064f40 0x4c _zPHY_edfe_TotalAGCCsrm
+ 0x10064f8c 0x4c _zPHY_edfe_TotalAGCRx
+ 0x10064fd8 0x2e _zPHY_edfe_SupResetDfeForRelease
+ 0x10065006 0xe _zPHY_edfe_RegsTpuIntForDfe
+ 0x10065014 0x91 _zPHY_edfe_RegsTpuIntForDfeCtrl
+ 0x100650a5 0x1ab _zPHY_edfe_SupDfeIntCheckCtrl
+ 0x10065250 0xb4 _zPHY_edfe_PlmnSaveServCellAgcAndDagc
+ 0x10065304 0x26 _zPHY_edfe_PlmnResumeServCellAgcAndDagc
+ 0x1006532a 0x76 _zPHY_edfe_PlmnBackUpAgcPara
+ 0x100653a0 0x20 _zPHY_edfe_PlmnResumeAgcAndAfc
+ 0x100653c0 0xa _zPHY_edfe_ClearPlmnAgcPara
+ 0x100653ca 0x1ed _zPHY_edfe_SupNotSyncAGCInitCtrl
+ 0x100655b7 0x17e _zPHY_edfe_TMTPrintForFreqScan
+ 0x10065735 0x8d _zPHY_edfe_ConfigAgcWorkState
+ 0x100657c2 0x1b5 _zPHY_edfe_ConfigAgcCalcPara
+ 0x10065977 0xf6 _zPHY_edfe_SupInitAgcDagcGainDB
+ 0x10065a6d 0x5c _zPHY_edfe_SupHandleRxDagcInt
+ 0x10065ac9 0x1b0 _zPHY_edfe_SupHandleAgcInt
+ 0x10065c79 0x43 _zPHY_edfe_StateChangeSetAgcGain
+ 0x10065cbc 0x12a _zPHY_edfe_GetTotalAGCGainOpt
+ 0x10065de6 0x67 _zPHY_edfe_SupCsrcDagcLoseDataCtrl
+ 0x10065e4d 0xbe _zPHY_edfe_PhySlaveDfeIntCtrlOpt
+ 0x10065f0b 0x2c _zPHY_edfe_TotalSubFramePwr
+ 0x10065f37 0x21 _zPHY_edfe_CSRSetFSNewState
+ 0x10065f58 0x48 _zPHY_edfe_CSRSetAGCGain
+ 0x10065fa0 0xfa _zPHY_edfe_SupFSNewSetRF
+ 0x1006609a 0x2d _zPHY_edfe_SupNotSyncAgcIntHandle
+ 0x100660c7 0x72 _zPHY_edfe_FSDCOffsetCal
+ 0x10066139 0x17 _zPHY_edfe_FSDCOffsetClear
+ 0x10066150 0x86 _zPHY_edfe_SupFSHandleDCOffset
+ 0x100661d6 0x12 _zPHY_edfe_SupHandleDCOffset
+ 0x100661e8 0xa9 _zPHY_edfe_SupSingAntNVControl
+ 0x10066291 0x9 _zPHY_edfe_ConfigSingAnt
+ 0x1006629a 0x86 _zPHY_edfe_SupCalAGCGainBalance
+ 0x10066320 0xfa _L1l_DevDfeNotchDbInit
+ 0x1006641a 0x3 _L1l_DevRfcNotchDbReset
+ 0x1006641d 0x14 _L1l_DevDfeNotchAgcGainSave
+ 0x10066431 0x4c _L11_DevDfeNotchBwAndSampRateGet
+ 0x1006647d 0x186 _L1l_DevDfeNotchStartJudge
+ 0x10066603 0xd3 _L1l_DevDfeNotchEvtGet
+ 0x100666d6 0xb7 _L1l_DevDfeNotchRegSet
+ 0x1006678d 0xc7 _L1l_DevDfeNotchProc
+ 0x10066854 0xb _L1l_DevRfcSemiStaticAgcConvCheck
+ 0x1006685f 0x13 _L1l_DevRfcAgcValGet
+ .text 0x10066872 0x1f9a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x10066872 0xfc _zPHY_eula_Entry
+ 0x1006696e 0xf9 _zPHY_eula_TpuInt1MsgPro
+ 0x10066a67 0x9e _zPHY_eula_TpuInt2MsgPro
+ 0x10066b05 0x58e _zPHY_eula_TPU_INT1_process
+ 0x10067093 0x360 _zPHY_eula_TPU_INT2_process
+ 0x100673f3 0x98 _zPHY_eula_ResetDB
+ 0x1006748b 0x17 _zPHY_eula_ResetReqPro
+ 0x100674a2 0x2d4 _zPHY_eula_HandoverReqPro
+ 0x10067776 0x160 _zPHY_eula_Release
+ 0x100678d6 0xd7 _zPHY_eula_MACReset
+ 0x100679ad 0x12d _zPHY_eula_ComCfgReqPro
+ 0x10067ada 0x16d _zPHY_eula_CommRelatedParasCalc
+ 0x10067c47 0x156 _zPHY_eula_DediCfgReqPro
+ 0x10067d9d 0x51 _zPHY_eula_GetScellInfo
+ 0x10067dee 0xca _zPHY_eula_DediRelatedParasCalc
+ 0x10067eb8 0x169 _zPHY_eula_PSGenAllWithCellID
+ 0x10068021 0x5c _zPHY_eula_FuncHopCalculation
+ 0x1006807d 0x5c _zPHY_eula_FuncHopCalculation_Scell
+ 0x100680d9 0x35 _zPHY_eula_UlBandSampleCoeffCfg
+ 0x1006810e 0x46 _zPHY_eula_SetSampleAndFFT
+ 0x10068154 0x15 _zPHY_eula_GetSysTimeInfo
+ 0x10068169 0x13 _zPHY_eula_GetChannelType
+ 0x1006817c 0x29 _zPHY_eula_GetHarqProcessId
+ 0x100681a5 0xe _zPHY_eula_CheckPuschInGap
+ 0x100681b3 0x52 _zPHY_eula_HarqNewTransNoData
+ 0x10068205 0xb0 _zPHY_eula_UL_Conflict_GAP
+ 0x100682b5 0x6b _zPHY_eula_HarqSendDataCopy
+ 0x10068320 0x18 _zPHY_eula_TXInt_Pulse_Isr
+ 0x10068338 0x13 _zPHY_eula_Isr
+ 0x1006834b 0x91 _zPHY_eula_lpcHwRestoreBackupCtrl
+ 0x100683dc 0x2e6 _zPHY_eula_AMTCalcPara
+ 0x100686c2 0x106 _zPHY_amt_Lte_Tx_Create_CommonMsg
+ 0x100687c8 0x44 _zPHY_PrintLocalMrtr
+ .text 0x1006880c 0x121f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x1006880c 0x1a7 _zPHY_edla_Entry
+ 0x100689b3 0x3e _L1e_Dla_UpBchNormalPara
+ 0x100689f1 0x1f7 _zPHY_edla_CdtrCfgProc
+ 0x10068be8 0x1a2 _zPHY_edla_GetSiRnti
+ 0x10068d8a 0x6a _zPHY_edla_QueryDb
+ 0x10068df4 0x1e _zPHY_edla_ProCalYk
+ 0x10068e12 0x1a9 _zPHY_edla_GetRntiInfo
+ 0x10068fbb 0xa8 _zPHY_edla_GetCellInfo
+ 0x10069063 0x20 _zPHY_edla_GetVcInfo
+ 0x10069083 0x1a _zPHY_edla_ErrorTmGuard
+ 0x1006909d 0x2c _zPHY_edla_SetDefaultTM
+ 0x100690c9 0x2e _zPHY_edla_GetTimingInfo
+ 0x100690f7 0x31 _L1e_DevDlaGetPhichMi
+ 0x10069128 0x1b _zPHY_edla_CommRegParaProc
+ 0x10069143 0xbe _zPHY_edla_CdtrCfgCaApply
+ 0x10069201 0x24 _zPHY_edla_CdtrCfgApply
+ 0x10069225 0xf7 _zPHY_edla_InfoCaPrepare
+ 0x1006931c 0x9 _zPHY_edla_InfoPrepare
+ 0x10069325 0x4a _zPHY_edla_IndInfoCaSet
+ 0x1006936f 0x9 _zPHY_edla_IndInfoSet
+ 0x10069378 0x46 _zPHY_edla_ResetDcb
+ 0x100693be 0x3e _zPHY_edla_Init
+ 0x100693fc 0x1e _zPHY_edla_HwInit
+ 0x1006941a 0x1c _zPHY_edla_CacheCtrlReset
+ 0x10069436 0x3b _zPHY_edla_SaveWorkCachePara
+ 0x10069471 0x1a _zPHY_edla_UpdateRBGSize
+ 0x1006948b 0x3d _zPHY_edla_UpdateNGap1
+ 0x100694c8 0x15 _zPHY_edla_UpdateNrbStep
+ 0x100694dd 0x8 _zPHY_edla_ResetCommonInfo
+ 0x100694e5 0xfc _zPHY_edla_UpdateCommonInfo
+ 0x100695e1 0x55 _zPHY_edla_ProCommReqMsg
+ 0x10069636 0x60 _zPHY_edla_ProDediReqMsg
+ 0x10069696 0x56 _zPHY_edla_ProHoReqMsg
+ 0x100696ec 0x24 _zPHY_edla_HoReqEx
+ 0x10069710 0xd _zPHY_edla_LteAmtUpdateEarfcnInfo
+ 0x1006971d 0xb _L1e_DevRxInitLpConvergeCb
+ 0x10069728 0xf _L1e_DevRxSetLpConvergeInd
+ 0x10069737 0x10 _L1e_DevRxGetLpConvergeInd
+ 0x10069747 0x10 _L1e_DevRxSetWorkTimer
+ 0x10069757 0x10 _L1e_DevRxGetWorkTimer
+ 0x10069767 0x13 _L1e_DevRxIncWorkTimer
+ 0x1006977a 0x27 _zPHY_edla_DebugPrint
+ 0x100697a1 0x43 _zPHY_edla_ProDbgMsgRecvCommMsg
+ 0x100697e4 0x43 _zPHY_edla_ProDbgMsgRecvHOMsg
+ 0x10069827 0x43 _zPHY_edla_ProDbgMsgRstRelMacRstMsg
+ 0x1006986a 0x52 _zPHY_edla_ProDbgStateSwitchPrint
+ 0x100698bc 0x3a _zPHY_edla_ProDbgMsgFuncRetErr
+ 0x100698f6 0x77 _zPHY_edla_ProDlCtrlChStatInfoMonitor
+ 0x1006996d 0x25 _zPHY_edla_ProDlCtrlChDecodeMonitor
+ 0x10069992 0x1 _zPHY_edla_ProDlCtrlChConfigMonitor
+ 0x10069993 0x4e _zPHY_edla_PlmnReflashDlaConfig
+ 0x100699e1 0x1a _L1e_DevRxLpcHwRecover
+ 0x100699fb 0x17 _L1e_DevDlaSetDlWorkIndBmp
+ 0x10069a12 0xc _L1e_DevDlaGetDlWorkIndBmp
+ 0x10069a1e 0xd _L1e_DevDlaGetDlBandWidth
+ .text 0x10069a2b 0x2ed3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x10069a2b 0x1cd _zPHY_eula_ProInitial
+ 0x10069bf8 0x68 _zPHY_eula_RegistLutrSymb
+ 0x10069c60 0x130 _zPHY_eula_UlDataSendCtrlInfoProcess
+ 0x10069d90 0x26a _zPHY_eula_LtxParas_ACKMultiplexing
+ 0x10069ffa 0xec _zPHY_eula_LutrLtxParas_RIMultiplexing
+ 0x1006a0e6 0xb _zPHY_eula_CalcInterMatrixColNumber
+ 0x1006a0f1 0x93 _zPHY_eula_CalcRMOutputParas
+ 0x1006a184 0x8 _zPHY_eula_CalcRMOutputParasForPuschWithoutData
+ 0x1006a18c 0xd0 _zPHY_eula_SchdPhichRecInSad
+ 0x1006a25c 0x65 _zPHY_eula_DeterMineHWChanType
+ 0x1006a2c1 0x194 _zPHY_eula_LTXParasCalc
+ 0x1006a455 0x2c _zPHY_eula_LtxParas_wNRsZcDmrs
+ 0x1006a481 0x21 _zPHY_eula_LargestPrimeNumber
+ 0x1006a4a2 0x28 _zPHY_eula_LtxParas_DmrsOCC
+ 0x1006a4ca 0x71 _zPHY_eula_LtxParas_adwQDivNRsZcDmrs
+ 0x1006a53b 0x28 _zPHY_eula_LtxParas_awNcscell
+ 0x1006a563 0x16 _zPHY_eula_LtxParas_acUPucch
+ 0x1006a579 0x113 _zPHY_eula_LtxParas_PucchFormat1Spec
+ 0x1006a68c 0x232 _zPHY_eula_LtxParas_PucchFormat3Spec
+ 0x1006a8be 0x13 _zPHY_eula_LtxParas_dwX2Cinit
+ 0x1006a8d1 0x3e _zPHY_eula_LtxParas_awNcs2
+ 0x1006a90f 0x9e _zPHY_eula_LtxParas_ResMappingPucch
+ 0x1006a9ad 0x14 _zPHY_eula_711712ClosePsmStub
+ 0x1006a9c1 0x46c _zPHY_eula_RfcConfigure
+ 0x1006ae2d 0xe7 _zPHY_eula_LutrRegConfigure
+ 0x1006af14 0x3da _zPHY_eula_LtxConfigure
+ 0x1006b2ee 0x63 _zPHY_eula_LTXTxTaConfig
+ 0x1006b351 0x50 _zPHY_eula_LTXTimingFirstFlag
+ 0x1006b3a1 0x53 _zPHY_eula_LTXTimingLastFlag
+ 0x1006b3f4 0x17 _zPHY_eula_ResetSrInfo
+ 0x1006b40b 0x100 _zPHY_eula_SetPuchFilterCoeff1
+ 0x1006b50b 0x66 _zPHY_eula_SetPrachFilterCoeff2
+ 0x1006b571 0x34 _zPHY_eula_SetPucchScale
+ 0x1006b5a5 0xf _zPHY_eula_GetCsiInfo
+ 0x1006b5b4 0x2 _zPHY_eula_FDDGetHarqAckInfo
+ 0x1006b5b6 0x25 _zPHY_euls_GetPucchHarqAckInfo
+ 0x1006b5db 0x83 _zPHY_eula_GetPucchHarqAckLen
+ 0x1006b65e 0xf7 _zPHY_eula_PucchUciProcess
+ 0x1006b755 0x2bc _zPHY_eula_TDD_PucchAckProcess
+ 0x1006ba11 0x1a _zPHY_eula_FDD_PucchAckProcess
+ 0x1006ba2b 0x70 _zPHY_eula_PucchCSI
+ 0x1006ba9b 0x271 _zPHY_eula_PucchAckParasCalc
+ 0x1006bd0c 0x34 _zPHY_eula_PucchN1pucchCalc
+ 0x1006bd40 0xaa _zPHY_eula_FDD_PucchAckParasCalc
+ 0x1006bdea 0x25 _zPHY_eula_PSGeneration
+ 0x1006be0f 0x7a _zPHY_eula_SrProcess
+ 0x1006be89 0x566 _zPHY_eula_LtxStub
+ 0x1006c3ef 0x213 _zPHY_eula_LutrStub
+ 0x1006c602 0x15a _zPHY_eula_UlTwoAntenHWChanTypeDeterm
+ 0x1006c75c 0xc _zPHY_eula_TATimerStop
+ 0x1006c768 0x25 _zPHY_eula_PucchTwoAntenActivedDetermine
+ 0x1006c78d 0x12f _zPHY_eula_NextAckParasProcess
+ 0x1006c8bc 0x3b _zPHY_eula_GetTQCfgFlg
+ 0x1006c8f7 0x7 _zPHY_eula_PucchAntennaSelect
+ .text 0x1006c8fe 0x38e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x1006c8fe 0x2d _zPHY_eintc_IntDispatchProcess_ICP
+ 0x1006c92b 0x47 _zPHY_eintc_EnableInt
+ 0x1006c972 0x50 _zPHY_eintc_ClearInt
+ 0x1006c9c2 0x1c _L1l_DrvTopIntClr
+ 0x1006c9de 0x46 _zPHY_eintc_InthInit
+ 0x1006ca24 0x1a _L1_LTE_LPM_T1_ISR
+ 0x1006ca3e 0x1 _zPHY_eintc_NullIsr
+ 0x1006ca3f 0xd _zPHY_DMA_CallBack_M
+ 0x1006ca4c 0xd _zPHY_DMA_CallBack_S
+ 0x1006ca59 0xd _zPHY_DMA_CallBack_CSILte
+ 0x1006ca66 0xd _L1e_DevCmnIntPbchIntProc
+ 0x1006ca73 0x36 _L1e_DevCmnIntCfoIntProc
+ 0x1006caa9 0x1c _L1e_DevCmnIntCrsCirIntProc
+ 0x1006cac5 0x31 _L1e_DevCmnIntCdtrIntProc
+ 0x1006caf6 0x24 _L1e_DevCmnIntDdtrIntProc
+ 0x1006cb1a 0x39 _L1e_CmnCheCqiInt
+ 0x1006cb53 0xe _L1e_CmnTpuSubFrameInt
+ 0x1006cb61 0x7 _L1e_CmnTpuAdjInt
+ 0x1006cb68 0xb _L1e_CmnTxPulseInt
+ 0x1006cb73 0x2d _L1e_CmnPdcchIntPcc
+ 0x1006cba0 0x3d _L1e_CmnDfeInt
+ 0x1006cbdd 0x2f _L1e_CmnDfeDcInt
+ 0x1006cc0c 0x2c _L1e_CmnPdcchPccInt
+ 0x1006cc38 0xd _L1e_CmnCsrDebugInt
+ 0x1006cc45 0xd _L1e_CmnPbchInt
+ 0x1006cc52 0xf _L1e_CmnPdschPccCirInt
+ 0x1006cc61 0x1e _L1e_CmnDdtrPccInt
+ 0x1006cc7f 0xd _L1e_CmnPbchIcInt
+ .text 0x1006cc8c 0x1419 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ 0x1006cc8c 0x1e9 _zPHY_eulpc_GetConfigParas
+ 0x1006ce75 0x46 _zPHY_eulpc_InitialProc
+ 0x1006cebb 0x3a _zPHY_eulpc_DeltaTcEUtraBandNoDeterm
+ 0x1006cef5 0x278 _zPHY_eulpc_SingleCarrierMprDeterm
+ 0x1006d16d 0x4e9 _zPHY_eulpc_NoCaAMprDeterm
+ 0x1006d656 0x82 _zPHY_eulpc_PcmaxCalc
+ 0x1006d6d8 0x132 _zPHY_eulpc_PucchTpcProc
+ 0x1006d80a 0x104 _zPHY_eulpc_PuschTpcProc
+ 0x1006d90e 0x44 _zPHY_eulpc_RarTpcProc
+ 0x1006d952 0x6d _zPHY_eulpc_PowCtrlConfigParasCalc
+ 0x1006d9bf 0x96 _zPHY_eulpc_TpcCommandsProc
+ 0x1006da55 0x110 _zPHY_eulpc_CloseLoopPowCtrlProc
+ 0x1006db65 0xb2 _zPHY_eulpc_Type1PhrCalc
+ 0x1006dc17 0x27 _zPHY_eulpc_PhrCalcProc
+ 0x1006dc3e 0xb7 _zPHY_eulpc_Sqrt
+ 0x1006dcf5 0x10d _zPHY_eulpc_PowScaleValCalc
+ 0x1006de02 0x37 _zPHY_eulpc_LinearValToPowDB
+ 0x1006de39 0x142 _zPHY_eulpc_UlaRelativeProc
+ 0x1006df7b 0x29 _zPHY_eulpc_UlPowerStub
+ 0x1006dfa4 0x1c _zPHY_eulpc_ReSetParameters
+ 0x1006dfc0 0xba _zPHY_eulpc_TempMaxPowerBackoff
+ 0x1006e07a 0x2b _zPHY_eulpc_GetLatestPower
+ .text 0x1006e0a5 0x134 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x1006e0a5 0x9 _L1l_DevEngInitAddr
+ 0x1006e0ae 0x12 _L1l_log_track_init
+ 0x1006e0c0 0x46 _L1l_DevEngTrace
+ 0x1006e106 0xd1 _L1l_DevEngWriteDataToBuffer
+ 0x1006e1d7 0x1 _L1l_DevEngUartTransmit
+ 0x1006e1d8 0x1 _L1l_DevEngSwapHook
+ .text 0x1006e1d9 0x35a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ 0x1006e1d9 0x38 _zEasn1p_DcT_zEurrc_OctString
+ 0x1006e211 0x46 _zEasn1p_DcT_zEurrc_S_TMSI
+ 0x1006e257 0x5b _zEasn1p_DcT_zEurrc_IMSI
+ 0x1006e2b2 0x42 _zEasn1p_DcT_zEurrc_PagingUE_Identity
+ 0x1006e2f4 0x56 _zEasn1p_DcT_zEurrc_PagingRecord
+ 0x1006e34a 0x4a _zEasn1p_DcT_zEurrc_PagingRecordList
+ 0x1006e394 0x4e _zEasn1p_DcT_zEurrc_Paging_v920_IEs
+ 0x1006e3e2 0x49 _zEasn1p_DcT_zEurrc_Paging_v890_IEs
+ 0x1006e42b 0x8f _zEasn1p_DcT_zEurrc_Paging
+ 0x1006e4ba 0x36 _zEasn1p_DcT_zEurrc_PCCH_MessageType_c1
+ 0x1006e4f0 0x3a _zEasn1p_DcT_zEurrc_PCCH_MessageType
+ 0x1006e52a 0x9 _zEasn1p_DcT_zEurrc_PCCH_Message
+ .text 0x1006e533 0xe7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ 0x1006e533 0x27 _L1e_DevDlaCalcTotRegNum
+ 0x1006e55a 0x75 _L1e_DevDlaCalcSearchSpace
+ 0x1006e5cf 0xdd _L1e_DevDlaProcPdcchSearchSpace
+ 0x1006e6ac 0x11c _zPHY_edla_PdcchBldRntiEnRegProc
+ 0x1006e7c8 0x6f _zPHY_edla_PdcchBldPayLoadRegProc
+ 0x1006e837 0x82 _zPHY_edla_PdcchBlindDetectCaProc
+ 0x1006e8b9 0xd _zPHY_edla_PdcchBlindDetectProc
+ 0x1006e8c6 0x20 _zPHY_edla_GetBandWidthIdx
+ 0x1006e8e6 0x1c _zPHY_edla_GetAmbitiousBits
+ 0x1006e902 0x8c _zPHY_edla_PreDciInfo
+ 0x1006e98e 0x20d _zPHY_edla_GetDciSize
+ 0x1006eb9b 0x809 _zPHY_edla_PdcchDemappingCaProc
+ 0x1006f3a4 0xd _zPHY_edla_PdcchDemappingProc
+ .text 0x1006f3b1 0xb64 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x1006f3b1 0xa0 _zPHY_erfc_SupACP405ToRx
+ 0x1006f451 0x6f _zPHY_erfc_SupACP405ToIdle
+ 0x1006f4c0 0x7f _zPHY_erfc_SupACP405ToTx
+ 0x1006f53f 0x82 _zPHY_erfc_SupACP405ToRxTx
+ 0x1006f5c1 0x1 _zPHY_erfc_SupACP405McroWriteAGC
+ 0x1006f5c2 0x1c _zPHY_erfc_SupGetRealWorkFreq
+ 0x1006f5de 0x46 _zPHY_erfc_ATAptPointAdjust
+ 0x1006f624 0x22 _zPHY_erfc_TxPowerAdjust
+ 0x1006f646 0xb7 _zPHY_erfc_SupGetPATuRegInfo
+ 0x1006f6fd 0x87 _zPHY_erfc_ProTxTempCompensate
+ 0x1006f784 0x1d3 _zPHY_erfc_SupAPCControl
+ 0x1006f957 0x6f _zPHY_erfc_SupClosePA
+ 0x1006f9c6 0x1 _zPHY_erfc_SupAptReload
+ 0x1006f9c7 0x139 _L1l_DevRfcAfcFreqOffsetSet
+ 0x1006fb00 0xd8 _zPHY_erfc_SupAfcEventSet
+ 0x1006fbd8 0x43 _zPHY_erfc_SupFreqOffseToDacValue
+ 0x1006fc1b 0x55 _zPHY_erfc_SupDacValueToFreqOffset
+ 0x1006fc70 0x36 _zPHY_erfc_SupBandNumToVcxoBitPerHz
+ 0x1006fca6 0x55 _zPHY_erfc_SupAfcVxcoInitWord
+ 0x1006fcfb 0x44 _L1l_DevRfcAfcFreqOffsetGet
+ 0x1006fd3f 0x2e _zPHY_erfc_DCXOCordicCfg
+ 0x1006fd6d 0x35 _zPHY_erfc_DCXOAfcInit
+ 0x1006fda2 0xa _zPHY_erfc_DCXOAfcParaSet
+ 0x1006fdac 0xd7 _zPHY_erfc_DCXOAfcParaGet
+ 0x1006fe83 0x92 _zPHY_erfc_DCXOAfcCtrl
+ .text 0x1006ff15 0x45e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x1006ff15 0x20 _zPHY_edls_AdaJudgePdschTrans
+ 0x1006ff35 0x7a _zPHY_edls_AdaDecodePdcchOrder
+ 0x1006ffaf 0x89 _zPHY_edls_AdaDecodeDciF1C
+ 0x10070038 0x71 _zPHY_edls_AdaCalSiRntiNdiRv
+ 0x100700a9 0x72 _zPHY_edls_AdaCalSibDecodeParas
+ 0x1007011b 0x5e _zPHY_edls_AdaRbDmpType0Bw25Rb
+ 0x10070179 0x56 _zPHY_edls_AdaRbDmpType0Bw15Rb
+ 0x100701cf 0x46 _zPHY_edls_AdaRbDmpType0Bw6Rb
+ 0x10070215 0x26 _L1e_DevDlsGetMLSMTbs
+ 0x1007023b 0x1f _L1e_DevDlsTbsBinarySearch
+ 0x1007025a 0x25 _L1e_DevDlsCalcRmCtrlParam
+ 0x1007027f 0xe9 _zPHY_edls_AdaCalRarDecodeParas
+ 0x10070368 0xb _L1e_DevDlsCalcRmBbClk
+ .text 0x10070373 0xf0b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x10070373 0x7 _L1e_DevRxGetPrevRxStatus
+ 0x1007037a 0x7 _L1e_DevRxGetCurrRxStatus
+ 0x10070381 0xc _L1e_DevRxSwitchPrevStatus
+ 0x1007038d 0x9 _L1e_DevRxSetCurrRxStatus
+ 0x10070396 0xa6 _zPHY_edla_PageSubFrmJudge
+ 0x1007043c 0x17 _zPHY_edla_RxVshiftConfig
+ 0x10070453 0xde _L1e_DevRxSfTypeCfg
+ 0x10070531 0x18 _L1e_DevRxRsN0FactorCtrl
+ 0x10070549 0x17c _L1e_DevRxCRsN0ModeCtrl
+ 0x100706c5 0x7e _L1e_DevRxProcRsCinit
+ 0x10070743 0x5d _zPHY_edla_RxBandTxRxPortConfig
+ 0x100707a0 0x113 _zPHY_edla_RxPhichMatrixConfig
+ 0x100708b3 0xf _zPHY_edla_RxCtrlChannelMimoModeConfig
+ 0x100708c2 0x6 _zPHY_edla_RxCalIndicatorConfig
+ 0x100708c8 0x44 _zPHY_edla_RxCarrierInfoConfig
+ 0x1007090c 0x85 _zPHY_edla_CheProc
+ 0x10070991 0xb _zPHY_edla_RxRbDemappingProc
+ 0x1007099c 0x25c _zPHY_edla_RbDemappingSubProc
+ 0x10070bf8 0x20 _zPHY_edla_WriteRxRbDemapRegFile
+ 0x10070c18 0x2b _L1e_DevRxNormalN0ModCfg
+ 0x10070c43 0x25 _L1e_DevRxNCellRsNullCfg
+ 0x10070c68 0x9 _L1e_DevRxSetCirTiCtlFlg
+ 0x10070c71 0x9 _L1e_DevRxGetCirTiCtlFlg
+ 0x10070c7a 0x70 _L1e_DevRxSinrLowInd
+ 0x10070cea 0x53 _L1e_DevNSIOT_8242_Ind
+ 0x10070d3d 0x41 _L1e_DevRxSinrTiCloseInd
+ 0x10070d7e 0x7 _L1e_DevRxCrsIIRIndSet
+ 0x10070d85 0x7 _L1e_DevRxCrsIIRIndGet
+ 0x10070d8c 0x8f _L1e_DevRxCrsIIRCfg
+ 0x10070e1b 0x5d _L1e_DevRxSnrModeTiAdptProc
+ 0x10070e78 0x1c _L1e_DevRxSetTiAlgoMode
+ 0x10070e94 0x9 _L1e_DevRxGetNCellRsNullEnInd
+ 0x10070e9d 0x9 _L1e_DevRxSetNCellRsNullEnInd
+ 0x10070ea6 0x59 _L1e_DevRxTempPro
+ 0x10070eff 0x25b _zPHY_edla_RxRegCfgApply
+ 0x1007115a 0x30 _L1e_DrvRxAgcCalandConfig
+ 0x1007118a 0xf4 _L1e_DbgRxCtrlInfo
+ .text 0x1007127e 0x25e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ 0x10071280 0x217 _zPHY_eulpc_PucchPowCtrl
+ 0x10071497 0x45 _zPHY_eulpc_HNcqiNharqNsrCalc
+ .text 0x100714dc 0x287 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ 0x100714dc 0x8 _L1e_DrvDdtrResetCfg
+ 0x100714e4 0x8 _L1e_DrvDdtrResetGet
+ 0x100714ec 0x7 _L1e_DrvDtrScaleResetCfg
+ 0x100714f3 0x8 _L1e_DrvDtrScaleEnCfg
+ 0x100714fb 0xb _L1e_DrvDtrScaleDtchEnCfg
+ 0x10071506 0x19 _L1e_DrvDtrScaleReset
+ 0x1007151f 0x8 _L1e_DrvDdtrModeCfg
+ 0x10071527 0x8 _L1e_DrvDdtrTurboLpCtrlRegCfg
+ 0x1007152f 0x8 _L1e_DrvDdtrSubfNumCfg
+ 0x10071537 0x8 _L1e_DrvDdtrHarqCtrlCfg
+ 0x1007153f 0x8 _L1e_DrvDdtrHarqIramCtrlCfg
+ 0x10071547 0xb _L1e_DrvDdtrHarqPriorityCfg
+ 0x10071552 0x8 _L1e_DrvDdtrHarqBurstCtrlCfg
+ 0x1007155a 0x8 _L1e_DrvDdtrIntTimerCfg
+ 0x10071562 0x8 _L1e_DrvDdtrLpCtrlCfg
+ 0x1007156a 0x8 _L1e_DrvDdtrUpdateCfg
+ 0x10071572 0xd _L1e_DrvDdtrTbCrcRead
+ 0x1007157f 0x9 _L1e_DrvDdtrSibPchCrcRead
+ 0x10071588 0x9 _L1e_DrvDdtrSubfNumRead
+ 0x10071591 0x9 _L1e_DrvDdtrIdleStateRead
+ 0x1007159a 0x9 _L1e_DrvDdtrErrorIndRead
+ 0x100715a3 0x1 _L1e_DrvDdtrTurboLpCtrlCfg
+ 0x100715a4 0xb _L1e_DrvDdtrPdschEnCfg
+ 0x100715af 0xb _L1e_DrvDdtrPdschEnRead
+ 0x100715ba 0xb _L1e_DrvDdtrSwapFlagCfg
+ 0x100715c5 0xb _L1e_DrvDdtrSwapFlagGet
+ 0x100715d0 0xe _L1e_DrvDdtrCwCinitCfg
+ 0x100715de 0xb _L1e_DrvDdtrTurboCtrlCfg
+ 0x100715e9 0xb _L1e_DrvDdtrPchBchTurboCtrlCfg
+ 0x100715f4 0x5d _L1e_DrvDdtrTbParamCfg
+ 0x10071651 0x8 _L1e_DrvDdtrPchCinitCfg
+ 0x10071659 0x11 _L1e_DrvDdtrPchParamCfg
+ 0x1007166a 0x8 _L1e_DrvDdtrSibCinitCfg
+ 0x10071672 0x11 _L1e_DrvDdtrSibParamCfg
+ 0x10071683 0x1d _L1e_DrvDdtrTurboReset
+ 0x100716a0 0x9 _L1e_DrvDdtrGetAxiInfo
+ 0x100716a9 0x39 _L1e_DrvDdtrPatchCfg
+ 0x100716e2 0x8 _L1e_DrvDdtrDbgGetDdtrMode
+ 0x100716ea 0x8 _L1e_DrvDdtrDbgGetTopErrInd
+ 0x100716f2 0x8 _L1e_DrvDdtrDbgGetAxiInfo
+ 0x100716fa 0x8 _L1e_DrvDdtrDbgGetIdleState
+ 0x10071702 0x8 _L1e_DrvDdtrDbgGetSubfNum
+ 0x1007170a 0xb _L1e_DrvDdtrDbgGetTurboCtrl
+ 0x10071715 0xb _L1e_DrvDdtrDbgGetTbCbCrc
+ 0x10071720 0xa _L1e_DrvDdtrGetDbgMontor1
+ 0x1007172a 0xa _L1e_DrvDdtrGetDbgMontor2
+ 0x10071734 0xf _L1e_DrvDdtrDbgSelCfg
+ 0x10071743 0x8 _L1e_DrvDdtrDbgSelCfgread
+ 0x1007174b 0x8 _L1e_DrvDdtrDbgSelCfgread0
+ 0x10071753 0x8 _L1e_DrvDdtrDbgSelCfgread1
+ 0x1007175b 0x8 _L1e_DrvDdtrDbgSelCfgread2
+ .text 0x10071763 0x454 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x10071763 0x1c _zPHY_DrvTopIntAbleBitSet
+ 0x1007177f 0x1f _zPHY_DrvTopIntMaskBitSet
+ 0x1007179e 0xc _zPHY_DrvTopIntMaskRegWR
+ 0x100717aa 0xc _zPHY_DrvTopIntMaskRegRD
+ 0x100717b6 0xc _zPHY_DrvGetTopIntStaus
+ 0x100717c2 0xc _zPHY_DrvGetTopIntVec
+ 0x100717ce 0xc _zPHY_DrvTopIntClear
+ 0x100717da 0x1f _zPHY_DrvTopIntEnable
+ 0x100717f9 0x5a _zPHY_eintc_IntRegPrint
+ 0x10071853 0x2c _zPHY_DrvTopIntReg_Print
+ 0x1007187f 0x1 _zPHY_DrvModemTopClkGate
+ 0x10071880 0x1 _zPHY_DrvModemTopClkSel
+ 0x10071881 0x11 _zPHY_LteModemTopClkCfg
+ 0x10071892 0x1b _zPHY_ResetModemHw
+ 0x100718ad 0x33 _zPHY_LteaModemTopCfgBackup
+ 0x100718e0 0x4a _zPHY_LteaModemTopCfgRecover
+ 0x1007192a 0x9 _zPHY_DrvTop_Reg_Set
+ 0x10071933 0x9 _zPHY_DrvTop_IntReg_Set
+ 0x1007193c 0x9 _zPHY_DrvTop_IntReg_Get
+ 0x10071945 0x28 _L1l_DrvMcuIntMask
+ 0x1007196d 0x28 _L1l_DrvMcuIntUnmask
+ 0x10071995 0xa _L1l_DrvMcuIntIreqClr
+ 0x1007199f 0x3a _L1l_DrvTopIntMask
+ 0x100719d9 0x39 _L1l_DrvTopIntRestore
+ 0x10071a12 0x48 _L1l_DrvTopIntEng
+ 0x10071a5a 0x1 _zPHY_DrvTOP_DFE_ClkPrintf
+ 0x10071a5b 0x1 _zPHY_DrvTOP_CSR_ClkPrintf
+ 0x10071a5c 0x7 _zPHY_DrvTOP_GetHarkRamSel
+ 0x10071a63 0x7 _zPHY_DrvTOP_GetTDHarkRamSel
+ 0x10071a6a 0x1 _zPHY_DrvTOP_Ddtr_ClkAndLpramPrintf
+ 0x10071a6b 0x37 _zPHY_DrvLteaPwrClkCtrl
+ 0x10071aa2 0x6 _zPHY_DrvPhyLteModemSel
+ 0x10071aa8 0x7 _zPHY_DrvRmHarqRamLteModeClkSelCfg
+ 0x10071aaf 0x5 _zPHY_DrvTurboModeSel
+ 0x10071ab4 0x58 _zPHY_DrvLteTpuClkSet
+ 0x10071b0c 0xe _zPHY_DrvLteTpuClkInit
+ 0x10071b1a 0x19 _zPHY_DrvChipTopRegInit
+ 0x10071b33 0x8 _zPHY_DrvTopCLKRegPOWGAT
+ 0x10071b3b 0x9 _zPHY_DrvTopCLKReg2m1SCfg
+ 0x10071b44 0x9 _zPHY_DrvTopCLKRegRfcCfg
+ 0x10071b4d 0xb _zPHY_DrvTop_RFInitReg_Set
+ 0x10071b58 0x5f _zPHY_DMA_Cfg
+ .text 0x10071bb7 0x2b6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x10071bb7 0x58 _L1L_TpuDrvReset
+ 0x10071c0f 0x33 _L1L_TpuDrvSuspend
+ 0x10071c42 0x3f _L1L_TpuDrvResume
+ 0x10071c81 0x7 _L1L_TpuDrvCpModeGet
+ 0x10071c88 0x46 _L1L_TpuDrvCpModeSet
+ 0x10071cce 0x1c _L1L_TpuDrvLocalMrtrGet
+ 0x10071cea 0x1c _L1L_TpuDrvMrtrGet
+ 0x10071d06 0xe _L1L_TpuDrvMrtrOffsetGet
+ 0x10071d14 0x47 _L1L_TpuDrvTpuRegister
+ 0x10071d5b 0x1b _L1L_TpuDrvMicroAdj
+ 0x10071d76 0x6 _L1L_TpuDrvMacroAdj
+ 0x10071d7c 0x20 _L1L_TpuDrvHwBackup
+ 0x10071d9c 0xb _L1L_TPUDrvCPModeGet
+ 0x10071da7 0xb _L1L_TPUDrvCPModeSet
+ 0x10071db2 0xa _L1L_TPUDrvMrtrOffGet
+ 0x10071dbc 0x8 _L1L_TPUDrvMrtrOffSet
+ 0x10071dc4 0x8 _L1L_TPUDrvAdjTimeSet
+ 0x10071dcc 0xc _L1L_TPUDrvCPMrtrOffStore
+ 0x10071dd8 0xa _L1L_TPUDrvMRTRTransfer
+ 0x10071de2 0x8 _L1L_TPUDrvLocalMrtrGet
+ 0x10071dea 0x8 _L1L_TPUDrvMrtrGet
+ 0x10071df2 0xb _L1L_TPUDrvHWResetCfg
+ 0x10071dfd 0xf _L1L_TpuDrvRAMCtrl
+ 0x10071e0c 0x8 _L1L_TPUDrvInttoArmIndexGet
+ 0x10071e14 0x9 _L1L_TpuDrvIntECTRamSel
+ 0x10071e1d 0x50 _L1L_TPUDrvIntECTInit
+ .text 0x10071e6d 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x10071e6d 0xea _zPHY_emc_DlDataReport
+ 0x10071f57 0x27 _zPHY_emc_RdUlDataSendCtrlInfo
+ 0x10071f7e 0x20 _zPHY_emc_wrUlReportBlerInfo
+ 0x10071f9e 0x53 _zPHY_emc_WrUlSchedInfo
+ 0x10071ff1 0x25 _zPHY_emc_InitRpMsgCh
+ 0x10072016 0x8 _zPHY_emc_MaskRpMsgCh
+ 0x1007201e 0x8 _zPHY_emc_UnMaskRpMsgCh
+ 0x10072026 0x9 _L1e_DrvGetIramTempCtrlBit
+ 0x1007202f 0x12 _L1e_DrvGetLteTempCtrlLimitInd
+ 0x10072041 0xa _L1e_DrvGetDlSibPduCrcBaseAddr
+ 0x1007204b 0xb _L1e_DrvGetDlSibPduDataBaseAddr
+ 0x10072056 0xa _L1e_DrvGetDlPchPduCrcBaseAddr
+ 0x10072060 0xb _L1e_DrvGetDlPchPduDataBaseAddr
+ 0x1007206b 0xa _L1e_DrvGetDlRarPduCrcBaseAddr
+ 0x10072075 0xb _L1e_DrvGetDlRarPduDataBaseAddr
+ 0x10072080 0x17 _L1e_DrvGetDlMacPduHarqBaseAddr
+ 0x10072097 0xb _L1e_DrvGetDlMacPduCrcBaseAddr
+ 0x100720a2 0xd _L1e_DrvSetIslandAddr
+ .text 0x100720af 0x57c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x100720af 0x7 _zPHY_elpc_DrvDelay
+ 0x100720b6 0x85 _L1l_DrvLpcGetSleepLen
+ 0x1007213b 0x32 _L1l_DrvLpcGetRemainCaliTime
+ 0x1007216d 0x8c _zPHY_elpc_LpmTimerCtrl
+ 0x100721f9 0x26 _L1_LTE_GetLpmTimerIsEn
+ 0x1007221f 0x4 _L1L_DrvLpcSocWakeUpIntCtrl
+ 0x10072223 0x1d _L1L_DrvLpcModemWakeUpIntCtrl
+ 0x10072240 0x1b _L1L_DrvLpcCfgSocWkupInt
+ 0x1007225b 0x23 _L1L_DrvLpcCfgModemWkupInt
+ 0x1007227e 0x16 _L1l_DrvLpcGetLpmNT
+ 0x10072294 0x4b _L1l_DrvLpcWaitLpmMrtrChange
+ 0x100722df 0x19 _zPHY_elpc_DrvLpmCaliCfg
+ 0x100722f8 0x10 _zPHY_elpc_DrvPdLteaCsrBackup
+ 0x10072308 0x6 _zPHY_elpc_DrvPdLteaTxBackup
+ 0x1007230e 0x1e _zPHY_elpc_DrvPdLteaCsrRecover
+ 0x1007232c 0x6 _zPHY_elpc_DrvPdLteaTxRecover
+ 0x10072332 0x11 _zPHY_elpc_DrvPdLteaRfcDfeBackup
+ 0x10072343 0x16 _zPHY_elpc_DrvPdLteaRfcDfeRecover
+ 0x10072359 0x5 _zPHY_elpc_DrvPdLteaRxRecover
+ 0x1007235e 0xf _zPHY_elpc_DrvPdLteaMimoCdtrRecover
+ 0x1007236d 0x5 _zPHY_elpc_DrvPdLteaDdtrHarqRecover
+ 0x10072372 0x19 _zPHY_elpc_DrvPdLteaStdbyCtrl
+ 0x1007238b 0x47 _zPHY_elpc_DrvPdHwIsBusy
+ 0x100723d2 0x1a _zPHY_elpc_DrvLteaPwrScenarioCtrlLog
+ 0x100723ec 0x37 _zPHY_elpc_DrvLteaPwrHwBackup
+ 0x10072423 0x12e _zPHY_elpc_DrvLteaPwrScenarioCtrl
+ 0x10072551 0xc1 _zPHY_elpc_DrvLteaPwrCtrl
+ 0x10072612 0x19 _zPHY_eLpc_DrvClearLteaModemInt
+ .text 0x1007262b 0x802 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ 0x1007262b 0x24 _zPHY_eltx_SoftReset
+ 0x1007264f 0x10 _zPHY_eltx_GetHWVersion
+ 0x1007265f 0x10 _zPHY_eltx_GetStatus
+ 0x1007266f 0x42 _zPHY_eltx_Clk_En
+ 0x100726b1 0xa _zPHY_eltx_SetCPType
+ 0x100726bb 0x12 _zPHY_eltx_SetChannelType
+ 0x100726cd 0x27 _zPHY_eltx_SetSysBandwidth
+ 0x100726f4 0xc _zPHY_eltx_SetTxTa
+ 0x10072700 0x9 _zPHY_eltx_SetPortSel
+ 0x10072709 0x14 _zPHY_eltx_SetFirstSfFlag
+ 0x1007271d 0xf _zPHY_eltx_SetConsecutiveSFLast
+ 0x1007272c 0x1e _zPHY_eltx_SetFirstLastMode
+ 0x1007274a 0xa _zPHY_eltx_SetSendMode
+ 0x10072754 0xe _zPHY_eltx_SetAbbSampleRate
+ 0x10072762 0x14 _zPHY_eltx_SetInterMatrixInfo
+ 0x10072776 0xc _zPHY_eltx_SetPuschScreamblePara
+ 0x10072782 0xe _zPHY_eltx_SetPuschModulationMode
+ 0x10072790 0xc _zPHY_eltx_SetPuschDFTPointNumber
+ 0x1007279c 0x9 _zPHY_eltx_SetPrecodingCodeBook
+ 0x100727a5 0x19 _zPHY_eltx_SetAckRiInfo
+ 0x100727be 0x4c _zPHY_eltx_SetRiMultiplexingInfo
+ 0x1007280a 0x77 _zPHY_eltx_SetAckMultiplexingInfo
+ 0x10072881 0xc _zPHY_eltx_SetPucchScreambleCint
+ 0x1007288d 0x24 _zPHY_eltx_SetPucchHarqAckinfo
+ 0x100728b1 0x1c _zPHY_eltx_SetPucchCqiInfo
+ 0x100728cd 0xe _zPHY_eltx_SetPucchFmt
+ 0x100728db 0x20 _zPHY_eltx_SetPucchCommonReg
+ 0x100728fb 0x20 _zPHY_eltx_SetPucchZCParas
+ 0x1007291b 0x7f _zPHY_eltx_SetPucchNcsParas
+ 0x1007299a 0x72 _zPHY_eltx_SetPuschDmrsParas
+ 0x10072a0c 0x68 _zPHY_eltx_SetSrsParas
+ 0x10072a74 0x3c _zPHY_eltx_SetPrachParas
+ 0x10072ab0 0x3e _zPHY_eltx_SetScale
+ 0x10072aee 0x2b _zPHY_eltx_SetPuschReMappingParas
+ 0x10072b19 0x1c _zPHY_eltx_SetPucchReMappingParas
+ 0x10072b35 0x4b _zPHY_eltx_TxCalibrationPreIQOrDC
+ 0x10072b80 0x4b _zPHY_eltx_SetTxCalibrationParas
+ 0x10072bcb 0x19 _zPHY_eltx_SetFilter1Coeff
+ 0x10072be4 0x19 _zPHY_eltx_SetFilter2Coeff
+ 0x10072bfd 0x19 _zPHY_eltx_SetFilter3Coeff
+ 0x10072c16 0xc _zPHY_eltx_SetByPass
+ 0x10072c22 0x9 _zPHY_eltx_SetFiFO
+ 0x10072c2b 0xb _zPHY_eltx_SetAntPhaseClkDelay
+ 0x10072c36 0xc _zPHY_eltx_SetAntFrameDlyNum
+ 0x10072c42 0x2 _zPHY_eltx_SetPucchFormat3Paras
+ 0x10072c44 0xe _zPHY_eltx_Enable
+ 0x10072c52 0x9 _zPHY_eltx_SetDebugMode
+ 0x10072c5b 0x9 _zPHY_eltx_SetDebugBusSel
+ 0x10072c64 0x9 _zPHY_eula_SetTXIntPulse
+ 0x10072c6d 0xa _zPHY_eltx_SetLTXIntSymbol
+ 0x10072c77 0x30 _zPHY_eltx_SetPRS1Paras
+ 0x10072ca7 0x31 _zPHY_eltx_GetPRS1Result
+ 0x10072cd8 0x30 _zPHY_eltx_SetPRS2Paras
+ 0x10072d08 0x2f _zPHY_eltx_GetPRS2Result
+ 0x10072d37 0x62 _zPHY_eula_TxRFCDBB_Interface
+ 0x10072d99 0x9 _zPHY_eula_SetTxDmaConfig
+ 0x10072da2 0xb _zPHY_eula_SetLtxFreqCompBypass
+ 0x10072dad 0xb _zPHY_eula_SetLtxFreqCompTheta
+ 0x10072db8 0xb _zPHY_eula_SetLtxFreqCompTheta0
+ 0x10072dc3 0x48 _zPHY_eula_TxFreqCompValGet
+ 0x10072e0b 0x11 _zPHY_eula_TxCordicInit
+ 0x10072e1c 0x11 _zPHY_eula_TxCordicCfg
+ .text 0x10072e2d 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ 0x10072e2d 0x19 _zPHY_ecsrm_MeasHwReset
+ 0x10072e46 0x77 _zPHY_ecsrm_MeasHwConfig
+ 0x10072ebd 0x79 _zPHY_ecsrm_MeasResultRead
+ 0x10072f36 0x45 _zPHY_ecsrm_GetMeasDoneFlag
+ 0x10072f7b 0xb _zPHY_ecsrm_GetRspCnt
+ 0x10072f86 0xc _zPHY_ecsrm_ClearMeasDoneFlag
+ .text 0x10072f92 0x8de T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x10072f92 0x1b _L1e_DrvRxResetHW
+ 0x10072fad 0xd1 _L1e_DrvRxCcRegInit
+ 0x1007307e 0x92 _L1e_DrvRxPccRegInit
+ 0x10073110 0x30 _L1e_DrvRxWriteRamCosWinCoeff
+ 0x10073140 0x10 _L1e_DrvRxTransformFirCoeff
+ 0x10073150 0x1c _L1e_DrvRxInitMrsFirCoeff
+ 0x1007316c 0x61 _L1e_DrvRxWriteRamFICoeff
+ 0x100731cd 0x14 _zPHY_Drv_Rx_HwInit
+ 0x100731e1 0x18 _L1e_DrvRxWritePcfichPosRegFile
+ 0x100731f9 0x19 _zPHY_Drv_Rx_WritePhichPosRegFile
+ 0x10073212 0x1 _zPHY_Drv_Rx_ClkPrintf
+ 0x10073213 0x8 _L1e_DrvRxGateCtrlRead
+ 0x1007321b 0x8 _L1e_DrvRxClkSwitch0Cfg
+ 0x10073223 0x8 _L1e_DrvRxClkSwitch0Read
+ 0x1007322b 0x8 _L1e_DrvRxPort5PatchCfg
+ 0x10073233 0x8 _L1e_DrvRxPccCsiCheTimeRead
+ 0x1007323b 0x8 _L1e_DrvRxPbchCtrlCfg
+ 0x10073243 0x8 _L1e_DrvRxPbchCtrlRead
+ 0x1007324b 0x8 _L1e_DrvRxCarrierInfoCfg
+ 0x10073253 0x8 _L1e_DrvRxCarrierInfoRead
+ 0x1007325b 0xb _L1e_DrvRxRxModeCfg
+ 0x10073266 0xb _L1e_DrvRxRxModeRead
+ 0x10073271 0xb _L1e_DrvRxRatModeCfg
+ 0x1007327c 0xb _L1e_DrvRxCpModeCfg
+ 0x10073287 0xb _L1e_DrvRxCpModeRead
+ 0x10073292 0xb _L1e_DrvRxVshiftCfg
+ 0x1007329d 0xb _L1e_DrvRxVshiftRead
+ 0x100732a8 0xe _L1e_DrvRxPcfichRegPosCfg
+ 0x100732b6 0xe _L1e_DrvRxPhichRegPosCfg
+ 0x100732c4 0x18 _L1e_DrvRxCellInfoCfg
+ 0x100732dc 0xb _L1e_DrvRxCellInfoRead
+ 0x100732e7 0xe _L1e_DrvRxSfnTypeCfg
+ 0x100732f5 0xe _L1e_DrvRxSfnTypeRead
+ 0x10073303 0x13 _L1e_DrvRxTmIndCfg
+ 0x10073316 0xb _L1e_DrvRxMbsfnCfiCfg
+ 0x10073321 0xb _L1e_DrvRxMbsfnTm9IndCfg
+ 0x1007332c 0xb _L1e_DrvRxCirAccCtrlCfg
+ 0x10073337 0xb _L1e_DrvRxCirAccCtrlRead
+ 0x10073342 0xb _L1e_DrvRxMrsCirAccCtrlCfg
+ 0x1007334d 0xb _L1e_DrvRxMrsCirAccCtrlRead
+ 0x10073358 0xb _L1e_DrvRxN0FgtFactorlCfg
+ 0x10073363 0x8 _L1e_DrvRxN0FgtFactorRead
+ 0x1007336b 0xb _L1e_DrvRxN0ModeCfg
+ 0x10073376 0xb _L1e_DrvRxN0ModeRead
+ 0x10073381 0xb _L1e_DrvRxSwN0ValCfg
+ 0x1007338c 0xb _L1e_DrvRxSwN0ValRead
+ 0x10073397 0xb _L1e_DrvRxMbsfnN0FgtCfg
+ 0x100733a2 0xb _L1e_DrvRxMbsfnN0FgtRead
+ 0x100733ad 0xb _L1e_DrvRxEicicModeCfg
+ 0x100733b8 0xb _L1e_DrvRxEicicModeRead
+ 0x100733c3 0xb _L1e_DrvRxBniCtrlCfg
+ 0x100733ce 0x1 _L1e_DrvRxNbnbCtrlCfg
+ 0x100733cf 0x2 _L1e_DrvRxNbnbCtrlRead
+ 0x100733d1 0xb _L1e_DrvRxCchModuModeCfg
+ 0x100733dc 0xb _L1e_DrvRxCchModuModeRead
+ 0x100733e7 0xb _L1e_DrvRxCchPcVolCfg
+ 0x100733f2 0xb _L1e_DrvRxCchPcPowCfg
+ 0x100733fd 0xb _L1e_DrvRxCsiRsCfg
+ 0x10073408 0xb _L1e_DrvRxHijRptModeCfg
+ 0x10073413 0xb _L1e_DrvRxTiCrsRptModeCfg
+ 0x1007341e 0xb _L1e_DrvRxTiCrsRptModeRead
+ 0x10073429 0xb _L1e_DrvRxPhichMatrixCfg
+ 0x10073434 0xb _L1e_DrvRxCchWorkModeCfg
+ 0x1007343f 0xb _L1e_DrvRxTiModeCfg
+ 0x1007344a 0xb _L1e_DrvRxTiModeRead
+ 0x10073455 0x10 _L1e_DrvRxAgcBalanceCfg
+ 0x10073465 0xe _L1e_DrvRxAgcBalanceRead
+ 0x10073473 0xb _L1e_DrvRxZpCsiBmpCfg
+ 0x1007347e 0xe _L1e_DrvRxZpCsiPosCfg
+ 0x1007348c 0xe _L1e_DrvRxCrsCinitCfg
+ 0x1007349a 0xe _L1e_DrvRxCrsCinitRead
+ 0x100734a8 0xe _L1e_DrvRxCsiRsCinitCfg
+ 0x100734b6 0xb _L1e_DrvRxRsParamCfg
+ 0x100734c1 0xe _L1e_DrvRxIcCrsCinitCfg
+ 0x100734cf 0xb _L1e_DrvRxIcRsParamCfg
+ 0x100734da 0x26 _L1e_DrvRxN0BetaCfg
+ 0x10073500 0x27 _L1e_DrvRxN0BetaRead
+ 0x10073527 0xb _L1e_DrvRxSwFirUpdateCfg
+ 0x10073532 0x8 _L1e_DrvRxFixFirUpdateCfg
+ 0x1007353a 0xb _L1e_DrvRxDrsGenStateCfg
+ 0x10073545 0xb _L1e_DrvRxDrsCinitCfg
+ 0x10073550 0xb _L1e_DrvRxDrsParamCfg
+ 0x1007355b 0xb _L1e_DrvRxRbBmpValidCfg
+ 0x10073566 0x13 _L1e_DrvRxRbBmpCfg
+ 0x10073579 0xb _L1e_DrvRxPrbBundlingBmpCfg
+ 0x10073584 0xb _L1e_DrvRxCsiRsDelCtrlCfg
+ 0x1007358f 0xb _L1e_DrvRxCsiRsDelCtrlRead
+ 0x1007359a 0xb _L1e_DrvRxPdschModuModeCfg
+ 0x100735a5 0xb _L1e_DrvRxPdschModuModeRead
+ 0x100735b0 0xb _L1e_DrvRxPdschMimoModeCfg
+ 0x100735bb 0xb _L1e_DrvRxPdschMimoModeRead
+ 0x100735c6 0xb _L1e_DrvRxPdschRbMaskCfg
+ 0x100735d1 0xb _L1e_DrvRxPdschTpmiCfg
+ 0x100735dc 0x10 _L1e_DrvRxDchPcVolCfg
+ 0x100735ec 0x10 _L1e_DrvRxDchPcPowCfg
+ 0x100735fc 0xb _L1e_DrvRxPcEnCfg
+ 0x10073607 0xb _L1e_DrvRxPort7IndCfg
+ 0x10073612 0xb _L1e_DrvRxMimoAlgoCfg
+ 0x1007361d 0xb _L1e_DrvRxBfAlgoCfg
+ 0x10073628 0xb _L1e_DrvRxPdschValidCfg
+ 0x10073633 0x13 _L1e_DrvRxCrsRssiRead
+ 0x10073646 0x13 _L1e_DrvRxCrsRspRead
+ 0x10073659 0x16 _L1e_DrvRxCrsRsrpRead
+ 0x1007366f 0xb _L1e_DrvRxCfoPhaseRead
+ 0x1007367a 0x13 _L1e_DrvRxMbsfnRssiRead
+ 0x1007368d 0x13 _L1e_DrvRxMbsfnRspRead
+ 0x100736a0 0x13 _L1e_DrvRxMbsfnRsrpRead
+ 0x100736b3 0x1c _L1e_DrvRxN0Read
+ 0x100736cf 0x1e _L1e_DrvRxCirPeakPosRead
+ 0x100736ed 0x22 _L1e_DrvRxDrsRsrpRead
+ 0x1007370f 0x24 _L1e_DrvRxDrsRspRead
+ 0x10073733 0xb _L1e_DrvRxDrsAccNumRead
+ 0x1007373e 0xc _L1e_DrvRxGetGenStateInd
+ 0x1007374a 0x6 _L1e_DrvRx_CqiHRx0
+ 0x10073750 0x6 _L1e_DrvRx_CqiNo0
+ 0x10073756 0x6 _L1e_DrvRx_R
+ 0x1007375c 0xd _L1e_DrvRxTpmiRamCfg
+ 0x10073769 0xd _L1e_DrvRxFirFixRamCfg
+ 0x10073776 0x6 _L1e_DrvRxFirFixRamRec
+ 0x1007377c 0x16 _L1e_DrvRxFirDynRamCfg
+ 0x10073792 0x1 _L1e_DrvRxFftBitmapRamCfg
+ 0x10073793 0x1 _L1e_DrvRxTiAptRamRead
+ 0x10073794 0x28 _L1e_DrvRxCirRamDataRead
+ 0x100737bc 0xb4 _L1e_DrvRxDbgLogRxCheReg
+ .text 0x10073870 0x209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ 0x10073870 0x1d _zPHY_elutr_SoftReset
+ 0x1007388d 0x12 _zPHY_elutr_GetHWVersion
+ 0x1007389f 0x1f _zPHY_elutr_HarqRam_Harness
+ 0x100738be 0x2b _zPHY_elutr_HarqRam_NoHarness
+ 0x100738e9 0x3a _zPHY_elutr_Clk_En
+ 0x10073923 0xe _zPHY_elutr_Enable
+ 0x10073931 0x9 _zPHY_elutr_GetHWStatus
+ 0x1007393a 0x13 _zPHY_elutr_CommonReg
+ 0x1007394d 0xc _zPHY_elutr_Modulation
+ 0x10073959 0xc _zPHY_elutr_SetTBLength
+ 0x10073965 0x24 _zPHY_elutr_SetTBSegParas
+ 0x10073989 0x1a _zPHY_elutr_SetTurboParas
+ 0x100739a3 0x25 _zPHY_elutr_SetRateMatchParas
+ 0x100739c8 0xc _zPHY_elutr_SetInterMatrixColNumber
+ 0x100739d4 0x24 _zPHY_elutr_SetPuschAckParas
+ 0x100739f8 0xe _zPHY_elutr_SetPuschAckUpdate
+ 0x10073a06 0x15 _zPHY_elutr_SetPuschRiParas
+ 0x10073a1b 0xe _zPHY_elutr_SetPuschRiUpdate
+ 0x10073a29 0x25 _zPHY_elutr_SetPuschCqiParas
+ 0x10073a4e 0xc _zPHY_elutr_SetPuschSubCarrierNumber
+ 0x10073a5a 0x1f _zPHY_elutr_SetRiMultiplexingInfo
+ .text 0x10073a79 0x22a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ 0x10073a79 0x1b _L1e_DrvRxMimoReset
+ 0x10073a94 0x19 _L1e_DrvPbchCdtrViterbiReset
+ 0x10073aad 0x1b _L1e_DrvPbchHWReset
+ 0x10073ac8 0x2 _L1e_DrvPbchInit
+ 0x10073aca 0x6a _L1e_DrvPbchConfigPbchReg
+ 0x10073b34 0xde _L1e_DrvPbchConfigRxReg
+ 0x10073c12 0x22 _L1e_DrvPbchGenRxSubFrmHead
+ 0x10073c34 0x23 _L1e_DrvPbchScGeneration
+ 0x10073c57 0x8 _L1e_DrvPbchCdtrViterbiClkRead
+ 0x10073c5f 0x8 _L1e_DrvPbchResultRead
+ 0x10073c67 0x8 _L1e_DrvPbchAntSfnRead
+ 0x10073c6f 0x8 _L1e_DrvPbchStateRead
+ 0x10073c77 0x9 _L1e_DrvPbchCdtrViterbiCtrl
+ 0x10073c80 0x9 _L1e_DrvPbchCdtrVtbRamLpCtrl
+ 0x10073c89 0x8 _L1e_DrvPbchLpcCfg
+ 0x10073c91 0x9 _L1e_DrvCdtrlkEn
+ 0x10073c9a 0x9 _L1e_DrvPbchClkEn
+ .text 0x10073ca3 0x36f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ 0x10073ca3 0x7 _L1e_DrvMimoCaRstCfg
+ 0x10073caa 0xb _L1e_DrvMimoIrcModeCfg
+ 0x10073cb5 0xb _L1e_DrvMimoIrcModeRead
+ 0x10073cc0 0x8 _L1e_DrvMimoUpdateCfg
+ 0x10073cc8 0x8 _L1e_DrvMimoUpdateRead
+ 0x10073cd0 0x8 _L1e_DrvCdtrResetCfg
+ 0x10073cd8 0x1b _L1e_DrvCdtrHwReset
+ 0x10073cf3 0x19 _L1e_DrvMimoReset
+ 0x10073d0c 0x43 _L1e_DrvCdtrHwInit
+ 0x10073d4f 0x8 _L1e_DrvCdtrTopClkSelCfg
+ 0x10073d57 0x26 _L1e_DrvCdtrTopRegCfg
+ 0x10073d7d 0x9 _L1e_DrvCdtrLpcCtrl
+ 0x10073d86 0x1b _L1e_DrvCdtrPcfichRegCfg
+ 0x10073da1 0x3b _L1e_DrvCdtrPhichRegCfg
+ 0x10073ddc 0x93 _L1e_DrvCdtrPdcchBldRegCfg
+ 0x10073e6f 0x54 _L1e_DrvCdtrPdcchDmpRegCfg
+ 0x10073ec3 0xb _L1e_DrvCdtrPhichNumCfg
+ 0x10073ece 0xb _L1e_DrvCdtrCchEnableCfg
+ 0x10073ed9 0xc _L1e_DrvCdtrRntiEnRead
+ 0x10073ee5 0xc _L1e_DrvCdtrCfiValueRead
+ 0x10073ef1 0xc _L1e_DrvCdtrHiNumRead
+ 0x10073efd 0xf _L1e_DrvCdtrHiValueRead
+ 0x10073f0c 0xc _L1e_DrvCdtrDciPld1Read
+ 0x10073f18 0xc _L1e_DrvCdtrDciPld2Read
+ 0x10073f24 0x1d _L1e_DrvCdtrDciRead
+ 0x10073f41 0x17 _L1e_DrvCdtrDciInfoRead
+ 0x10073f58 0xc _L1e_DrvCdtrDciValidRead
+ 0x10073f64 0xc _L1e_DrvCdtrUePortRead
+ 0x10073f70 0x8 _L1e_DrvCdtrDbgGetIntType
+ 0x10073f78 0xb _L1e_DrvCdtrDbgGetDlDciInfo
+ 0x10073f83 0x11 _L1e_DrvCdtrDbgGetDlDciFlag
+ 0x10073f94 0x11 _L1e_DrvCdtrDbgGetSiDciFlag
+ 0x10073fa5 0x11 _L1e_DrvCdtrDbgGetPmDciFlag
+ 0x10073fb6 0x11 _L1e_DrvCdtrDbgGetRaDciFlag
+ 0x10073fc7 0x4b _L1e_DrvCdtrPdcchBmpRamCfg
+ .text 0x10074012 0x7f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x10074012 0x38 _zPHY_erfc_DrvGetSubFrameAddr
+ 0x1007404a 0xd1 _zPHY_erfc_DrvRealwokEventEn
+ 0x1007411b 0x62 _zPHY_erfc_DrvInitAllEventEnArray
+ 0x1007417d 0x186 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg
+ 0x10074303 0x1 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg_Slave
+ 0x10074304 0x87 _zPHY_erfc_DrvAFCEventEn
+ 0x1007438b 0x10 _zPHY_erfc_DrvSpiWrite
+ 0x1007439b 0x59 _zPHY_erfc_DrvSetAgcSpiReg
+ 0x100743f4 0xa _zPHY_erfc_DrvRbdp_RxIQInvert
+ 0x100743fe 0xa _zPHY_erfc_DrvRbdp_TxIQInvert
+ 0x10074408 0x1 _zPHY_erfc_DrvRbdpModeCfg
+ 0x10074409 0x1 _zPHY_erfc_DrvTopRBDPGPIOConfig
+ 0x1007440a 0x1 _zPHY_erfc_DrvTopSSCConfig
+ 0x1007440b 0xa _zPHY_erfc_DrvMasterModeTopGPIOConfig
+ 0x10074415 0x1 _zPHY_erfc_DrvEventRamLeaveLP
+ 0x10074416 0x50 _zPHY_erfc_DrvRfcRegInit
+ 0x10074466 0x1 _zPHY_erfc_DrvRfcRegInit_Slave
+ 0x10074467 0x91 _zPHY_erfc_DrvRFEventRamInit
+ 0x100744f8 0x1b _zPHY_erfc_DrvSoftwareReset
+ 0x10074513 0x18 _zPHY_erfc_DrvResetHw
+ 0x1007452b 0xe _zPHY_erfc_DrvWriteCmdEvent
+ 0x10074539 0xe _zPHY_erfc_DrvDBBEventSet
+ 0x10074547 0x6 _zPHY_erfc_GetDfeSampleRateAddr
+ 0x1007454d 0x2c _zPHY_erfc_GetRfcShadowEventTableAddr
+ 0x10074579 0x33 _zPHY_erfc_GetRfcEventTableAddr
+ 0x100745ac 0x33 _zPHY_erfc_GetRfcBackupDDREventTableAddr
+ 0x100745df 0x30 _zPHY_erfc_DrvGetRamState
+ 0x1007460f 0x85 _zPHY_erfc_DrvEvtTabStart
+ 0x10074694 0x12 _zPHY_erfc_DrvGPIOEventSet
+ 0x100746a6 0xb _zPHY_erfc_DrvOpenfilter0
+ 0x100746b1 0xb _zPHY_erfc_DrvClosefilter0
+ 0x100746bc 0xb _zPHY_erfc_DrvOpenfilter1
+ 0x100746c7 0xb _zPHY_erfc_DrvClosefilter1
+ 0x100746d2 0xe _zPHY_erfc_DrvOpenfilter2
+ 0x100746e0 0xb _zPHY_erfc_DrvClosefilter2
+ 0x100746eb 0x10 _zPHY_erfc_DrvDfeRXBandWidthEn
+ 0x100746fb 0x10 _zPHY_erfc_DrvDfeMeas0BandWidthEn
+ 0x1007470b 0xb _zPHY_erfc_DrvGetfilter2State
+ 0x10074716 0x7 _zPHY_erfc_DrvGetfilterState
+ 0x1007471d 0x7 _zPHY_erfc_DrvGetSpiReadData
+ 0x10074724 0x7 _zPHY_erfc_DrvGetMipiReadData
+ 0x1007472b 0x9 _zPHY_erfc_DrvSetRxRemovCpOffset
+ 0x10074734 0x54 _zPHY_erfc_DrvEvtSetTableOffset
+ 0x10074788 0x9 _zPHY_erfc_DrvEnTxCalibration
+ 0x10074791 0x1 _zPHY_erfc_DrvSlaveModeTopGPIOConfig
+ 0x10074792 0xb _zPHY_erfc_DrvRfcRXBandWidthEn
+ 0x1007479d 0xb _zPHY_erfc_DrvRfcMeas0BandWidthEn
+ 0x100747a8 0x1a _zPHY_erfc_DrvInitTuRamTxEnReg
+ 0x100747c2 0x25 _zPHY_erfc_DrvInitTuRamTxTable
+ 0x100747e7 0x23 _zPHY_erfc_DrvInitTuRegTxTable
+ .text 0x1007480a 0x1ae0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x1007480a 0xcb _sin_wave_test_dfe
+ 0x100748d5 0x5a _zPHY_erfc_DrvRfcRffeWrite
+ 0x1007492f 0x7a _zPHY_erfc_MIPI_Config
+ 0x100749a9 0x1 _zPHY_erfc_DrvRfcRffeSwitchInit
+ 0x100749aa 0x9f _zPHY_erfc_DrvDFESetAcp405Gain
+ 0x10074a49 0x25 _zPHY_erfc_DrvSpiCtrlWordPreDef
+ 0x10074a6e 0x4b _zPHY_erfc_DrvPaAndAntOpenForRX
+ 0x10074ab9 0x7b _zPHY_erfc_DrvPaAndAntOpenForTX
+ 0x10074b34 0x8e _zPHY_erfc_Idle2TDRX
+ 0x10074bc2 0x82 _zPHY_erfc_Idle2TDTX
+ 0x10074c44 0x2f _zPHY_erfc_TxDbbSingleTone
+ 0x10074c73 0xc _zPHY_erfc_TransToRX
+ 0x10074c7f 0xe _zPHY_erfc_TransToTX
+ 0x10074c8d 0x1 _zPHY_erfc_DrvACP405GpioTest
+ 0x10074c8e 0xc _zPHY_erfc_DrvACP405Spi32BitWrReg
+ 0x10074c9a 0x11 _zPHY_erfc_ZTERfSPIWrite
+ 0x10074cab 0x20 _zPHY_erfc_ZTERfSPIRead
+ 0x10074ccb 0x1f _zPHY_erfc_ZTERfMIPIRead
+ 0x10074cea 0x1f _zPHY_erfc_ZTEAbbSPIRead
+ 0x10074d09 0xa _zPHY_erfc_DrvZTE110RegSet
+ 0x10074d13 0x49 _zPHY_erfc_DrvZTE110RxBandAndWidthConf
+ 0x10074d5c 0x10 _zPHY_erfc_DrvZTE120TxDACEn
+ 0x10074d6c 0x10 _zPHY_erfc_DrvZTE120TxDTXModeEn
+ 0x10074d7c 0xf _zPHY_erfc_DrvZTE120TxDACClk
+ 0x10074d8b 0x33 _zPHY_erfc_DrvCalcFracFreq
+ 0x10074dbe 0x72 _zPHY_erfc_ZTE110_RxRegConfig
+ 0x10074e30 0x65 _zPHY_erfc_ZTE110_TxRegConfig
+ 0x10074e95 0x3a _zPHY_erfc_ZTE120_RxRegConfig
+ 0x10074ecf 0x36 _zPHY_erfc_ZTE120_TxRegConfig
+ 0x10074f05 0x8c _zPHY_erfc_GetOpenRxRamNum
+ 0x10074f91 0x1c5 _zPHY_erfc_EventOpenRx
+ 0x10075156 0x89 _zPHY_erfc_EventOpenRxAntenna
+ 0x100751df 0x18c _zPHY_erfc_EventOpenTx
+ 0x1007536b 0x65 _zPHY_erfc_EventOpenTxAntenna
+ 0x100753d0 0x92 _zPHY_erfc_GetOpenRxAntennaIndex
+ 0x10075462 0xe9 _zPHY_erfc_GetOpenRxIndex
+ 0x1007554b 0x30 _zPHY_erfc_GetOpenTxIndex
+ 0x1007557b 0x35 _zPHY_erfc_GetOpenTxAntennaIndex
+ 0x100755b0 0x26 _zPHY_erfc_GetOpenTxRamNum
+ 0x100755d6 0xdc _zPHY_erfc_GetOpenRxLineIndex
+ 0x100756b2 0x70 _zPHY_erfc_GetOpenRxLineData
+ 0x10075722 0x55 _zPHY_erfc_GetNorTxOpenIndex
+ 0x10075777 0x57 _zPHY_erfc_GetOpenTxLineIndex
+ 0x100757ce 0x6d _zPHY_erfc_GetOpenTxLineData
+ 0x1007583b 0xb6 _zPHY_erfc_EventTableOpenRx
+ 0x100758f1 0xae _zPHY_erfc_TxTableOpenTx
+ 0x1007599f 0xd8 _zPHY_erfc_GetCloseAntennaIndex
+ 0x10075a77 0xdf _zPHY_erfc_GetRfToIdleIndex
+ 0x10075b56 0x75 _zPHY_erfc_GetRfToIdleData
+ 0x10075bcb 0x97 _zPHY_erfc_EventAntennaToIdle
+ 0x10075c62 0xb9 _zPHY_erfc_EventRfToIdle
+ 0x10075d1b 0x2d _zPHY_erfc_GetCloseRfRamNum
+ 0x10075d48 0x54 _zPHY_erfc_EventTableToIdle
+ 0x10075d9c 0x111 _zPHY_erfc_GetPAIndex
+ 0x10075ead 0x7d _zPHY_erfc_AmtRfFrontSet
+ 0x10075f2a 0x2f _zPHY_erfc_RfAntenna_set
+ 0x10075f59 0x6b _zPHY_erfc_RfPAFrontSet
+ 0x10075fc4 0x25 _zPHY_erfc_ATSetAptFixVoltage
+ 0x10075fe9 0xe8 _zPHY_erfc_GetRfVGACtrlWord
+ 0x100760d1 0x14 _zPHY_erfc_LittleTabWritePATrigEna
+ 0x100760e5 0x14 _zPHY_erfc_LittleTabWritePATrigLoad
+ 0x100760f9 0x14 _zPHY_erfc_LittleTabWritePATrigDisa
+ 0x1007610d 0x13e _zPHY_erfc_LittleTabWritePaAndVga
+ 0x1007624b 0x49 _zPHY_erfc_SupCheckPAMode
+ 0x10076294 0x1 _zPHY_erfc_RxSinToneTest
+ 0x10076295 0x1 _zPHY_erfc_TxSinToneTest
+ 0x10076296 0x1 _zPHY_erfc_DrvRfNvInit
+ 0x10076297 0x53 _zPHY_erfc_GetRfDCOC_CalVaue
+ .text 0x100762ea 0x204 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100762ea 0x21 _zPHY_erfc_DrvRfcTxSampleRateSet
+ 0x1007630b 0x34 _zPHY_erfc_DrvRfcDfeSampleRateSet
+ 0x1007633f 0x4c _zPHY_erfc_DrvInitMainSyncTable
+ 0x1007638b 0xa5 _zPHY_erfc_DrvInitMeasTable0
+ 0x10076430 0x45 _zPHY_erfc_DrvInitTxSendTable
+ 0x10076475 0x42 _zPHY_erfc_DrvEventTableBoundaryInit
+ 0x100764b7 0xc _zPHY_erfc_IRAM_Set
+ 0x100764c3 0x1a _zPHY_erfc_IRAM_Get
+ 0x100764dd 0x10 _zPHY_erfc_DrvDBBDely
+ 0x100764ed 0x1 _zPHY_erfc_DrvRfTopIntfInit
+ .text 0x100764ee 0xb70 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x100764ee 0x4a _zPHY_edfe_DrvInitInt
+ 0x10076538 0x53 _zPHY_edfe_DrvResetHw
+ 0x1007658b 0x3b _zPHY_edfe_DrvConfigRXBandwidth
+ 0x100765c6 0x3b _zPHY_edfe_DrvConfigCSRMBandwidth
+ 0x10076601 0x1f _zPHY_edfe_DrvGetDCOffsetEsti
+ 0x10076620 0x2c _zPHY_edfe_DrvConfigDCOffset
+ 0x1007664c 0x1f _zPHY_edfe_DrvGetIQEstiSum
+ 0x1007666b 0x1f _zPHY_edfe_DrvGetIQEstiCPSum
+ 0x1007668a 0x30 _zPHY_edfe_DrvConfigIQImbal
+ 0x100766ba 0x6a _zPHY_edfe_DrvConfigAGCPara
+ 0x10076724 0x14 _zPHY_edfe_DrvGetAGCMeanPower
+ 0x10076738 0x12 _zPHY_edfe_DrvGetAGCLFOutVal
+ 0x1007674a 0xa _zPHY_edfe_DrvGetAGCHWGainValue
+ 0x10076754 0xa _zPHY_edfe_DrvCompesateCFO
+ 0x1007675e 0x27 _zPHY_edfe_DrvDcIqParaInit
+ 0x10076785 0x8a _zPHY_edfe_DrvConfigFIRCoeff
+ 0x1007680f 0x50 _zPHY_edfe_DrvConfigDAGCPara
+ 0x1007685f 0x31 _zPHY_edfe_DrvGetDAGCMeanPower
+ 0x10076890 0x12 _zPHY_edfe_DrvGetMbsfnDAGCMeanPower
+ 0x100768a2 0x52 _zPHY_edfe_DrvConfigDAGCSWGainValue
+ 0x100768f4 0x3b _zPHY_edfe_DrvConfigMbsfnRxDAGCSWGainValue
+ 0x1007692f 0x1 _zPHY_edfe_DrvAGCGainConvertTableInit
+ 0x10076930 0x7e _zPHY_edfe_DrvInitDFE
+ 0x100769ae 0x72 _zPHY_edfe_DrvDcIqCfoDagcApplyEn
+ 0x10076a20 0xd0 _zPHY_edfe_DrvRxCPModeConfig
+ 0x10076af0 0x1 _zPHY_edfe_DrvCsrmCPModeConfig
+ 0x10076af1 0x29 _zPHY_edfe_DrvAgcExtModeConfig
+ 0x10076b1a 0x22 _zPHY_edfe_DrvDfeAbbSamplingRateConfig
+ 0x10076b3c 0x1a _zPHY_edfe_DrvMbsfnTwoAgcDagcEn
+ 0x10076b56 0xb _zPHY_edfe_DrvMbsfnTimingOffset
+ 0x10076b61 0x14 _zPHY_edfe_DrvTxCaliConfig
+ 0x10076b75 0x1e _zPHY_edfe_DrvMeasBufferModeComnParaConfig
+ 0x10076b93 0x15 _zPHY_edfe_DrvMeasBufferModeCellParaConfig
+ 0x10076ba8 0x9 _zPHY_edfe_DrvMeasBufferModeRamReadEn
+ 0x10076bb1 0x29 _zPHY_edfe_DrvMeasMode
+ 0x10076bda 0x15 _zPHY_edfe_DrvMeasClock
+ 0x10076bef 0xe _zPHY_edfe_DrvMeasClockClose
+ 0x10076bfd 0x15 _zPHY_edfe_DrvMeasReset
+ 0x10076c12 0x14 _zPHY_edfe_DrvGetMbsfnAGCMeanPower
+ 0x10076c26 0x29 _zPHY_edfe_DrvConfigMbsfnAGCSWGainValue
+ 0x10076c4f 0x14 _zPHY_edfe_DrvLpcSaveRegForCsr
+ 0x10076c63 0x2a _zPHY_edfe_DrvLpcSaveRegForRxCommon
+ 0x10076c8d 0xe8 _zPHY_edfe_DrvLpcResumeRxCommon
+ 0x10076d75 0x3 _zPHY_edfe_DrvLpcResumePower1Public
+ 0x10076d78 0x68 _zPHY_edfe_DrvLpcResumeCsr
+ 0x10076de0 0x20 _zPHY_edfe_DrvLpcResumePower0Public
+ 0x10076e00 0x12 _zPHY_edfe_DrvAgcLenStepConfig
+ 0x10076e12 0xb _zPHY_edfe_DrvDagc2LenStepConfig
+ 0x10076e1d 0x13 _zPHY_edfe_DrvAntModeConfig
+ 0x10076e30 0x26 _zPHY_edfe_DrvAgcIntStateConfig
+ 0x10076e56 0x8 _zPHY_edfe_DrvConfigAgcCalControl
+ 0x10076e5e 0x18 _zPHY_edfe_DrvGetEverySampMeanPower
+ 0x10076e76 0x1 _zPHY_edfe_DrvRfcDfeInterfaceSet
+ 0x10076e77 0x1 _zPHY_edfe_DrvPrsMeasModeComnParaConfig
+ 0x10076e78 0x1 _zPHY_edfe_DrvCsrInputSelect
+ 0x10076e79 0x2 _zPHY_edfe_DrvGetCsrInputSelState
+ 0x10076e7b 0x54 _zPHY_edfe_DrvResetPwr0
+ 0x10076ecf 0xa _zPHY_edfe_DrvDfeIntfSel
+ 0x10076ed9 0x16 _zPHY_edfe_DrvCPAddLenConfig
+ 0x10076eef 0x30 _zPHY_edfe_DrvCsrDDrCatchDataEn
+ 0x10076f1f 0xd _zPHY_edfe_DrvCsrDDrCatchDataStop
+ 0x10076f2c 0x1f _zPHY_edfe_DrvPwr0RestCsrSyncHw
+ 0x10076f4b 0x3c _L1l_DrvDfeCalcNotchParaA
+ 0x10076f87 0x8 _L1l_DrvDfeNotchSetBypass
+ 0x10076f8f 0xa _L1l_DrvDfeNotchSetA_First
+ 0x10076f99 0xa _L1l_DrvDfeNotchSetA_Second
+ 0x10076fa3 0xa _L1l_DrvDfeNotchSetA_Third
+ 0x10076fad 0xc _L1l_DrvDfeNotchSetT_A
+ 0x10076fb9 0xc _L1l_DrvDfeNotchSetT_B
+ 0x10076fc5 0xe _L1l_DrvDfeNotchSetK_A
+ 0x10076fd3 0xe _L1l_DrvDfeNotchSetK_B
+ 0x10076fe1 0xf _zPHY_edfe_DrvEnableDcInt
+ 0x10076ff0 0x5 _zPHY_edfe_ClkPrintf
+ 0x10076ff5 0x69 _zPHY_edfe_LteBuffRegPrint
+ .text 0x1007705e 0x879 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x1007705e 0x2a _zEcsr_CurrentGapTime
+ 0x10077088 0x1d _zEcsr_CurrentGapSuperTime
+ 0x100770a5 0x3c _zEcsr_GetGapStateEx
+ 0x100770e1 0x13 _zEcsr_GetLteGapState
+ 0x100770f4 0x9 _zEcsr_GetGapState
+ 0x100770fd 0x16 _zEcsr_GetIratGapState
+ 0x10077113 0x23 _zEcsr_GapCnt
+ 0x10077136 0x48 _zEcsr_GetLastGapTime
+ 0x1007717e 0x42 _zEcsr_GetGapStartTime
+ 0x100771c0 0x4b _zEcsr_GetNeartGapTime
+ 0x1007720b 0x76 _zEcsr_GetTimeBeforeIratGap
+ 0x10077281 0x42 _zEcsr_GetTimeBeforeGapEx
+ 0x100772c3 0x8 _zEcsr_GetTimeBeforeGap
+ 0x100772cb 0x12 _zEcsr_GetTimeBeforeLteGap
+ 0x100772dd 0x19 _zEcsr_Compare
+ 0x100772f6 0xb _zEcsr_GapTimeCompare
+ 0x10077301 0x7 _zEcsr_TimeCompare
+ 0x10077308 0x40 _zEcsr_BeforeGapHalfFrame
+ 0x10077348 0x40 _zEcsr_AfterGapHalfFrame
+ 0x10077388 0x33 _zEcsr_GetGapOffsetEx
+ 0x100773bb 0x8 _zEcsr_GetGapOffset
+ 0x100773c3 0x60 _zEcsr_GetGapType
+ 0x10077423 0x32 _zEcsr_IsValidGapTime
+ 0x10077455 0x61 _zEcsr_GetGapDistance
+ 0x100774b6 0x89 _zEcsr_GapType
+ 0x1007753f 0x13 _zEcsr_GetLteGapOffset
+ 0x10077552 0x14 _zEcsr_IsAroundGap
+ 0x10077566 0x14 _zEcsr_IsAroundLteGap
+ 0x1007757a 0x54 _zEcsr_CurrentGapType
+ 0x100775ce 0x3d _zEcsr_CurrentGapStartTime
+ 0x1007760b 0x10 _zEcsr_CurrentGapFrame
+ 0x1007761b 0x18 _zEcsr_NextGapFrame
+ 0x10077633 0xd _zEcsr_GapSubFrame
+ 0x10077640 0xe _zEcsr_LteGapGapAvai
+ 0x1007764e 0xc _zEcsr_CurrentGapStartMrtr
+ 0x1007765a 0x19 _zEcsr_CurrentMrtrUpper
+ 0x10077673 0x2a _zEcsr_NextHalfFrame
+ 0x1007769d 0x2d _zEcsr_TimeToMrtr
+ 0x100776ca 0x12 _zEcsr_MrtrToTime
+ 0x100776dc 0xb _zEcsr_TimeToTs
+ 0x100776e7 0x57 _zEcsr_TimeOnGapConfig
+ 0x1007773e 0x1a _zEcsr_TimeInit
+ 0x10077758 0x7 _zPHY_ecsrc_CtrltTime2Ts
+ 0x1007775f 0x1f _zPHY_ecsrc_TimeAdd
+ 0x1007777e 0x25 _zPHY_ecsrc_TimeSub
+ 0x100777a3 0x16 _zPHY_ecsrc_MrtrAddTs
+ 0x100777b9 0x19 _zPHY_ecsrc_MrtrAddSlot
+ 0x100777d2 0x1c _zPHY_ecsrc_MrtrSubTs
+ 0x100777ee 0x1f _zPHY_ecsrc_MrtrSubSlot
+ 0x1007780d 0x2b _zPHY_ecsrc_MrtrAddSignTs
+ 0x10077838 0x24 _zPHY_ecsrc_GetCurTime
+ 0x1007785c 0x18 _zPHY_ecsrc_Mrtr2LocalMrtr
+ 0x10077874 0x18 _zPHY_ecsrc_LocalMrtr2Mrtr
+ 0x1007788c 0x4 _zPHY_ecsrc_RemoveMrtrTs
+ 0x10077890 0x23 _zPHY_ecsrc_MakeMrtr
+ 0x100778b3 0x24 _zPHY_ecsrc_TsToLocalTs
+ .text 0x100778d7 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ 0x100778d7 0x571 _zPHY_erapc_ThreadEntry
+ .text 0x10077e48 0x131f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x10077e48 0xcf _zPHY_ecsrc_InitMeasOnIdle
+ 0x10077f17 0x31 _zPHY_ecsrc_ConfigRfcOffset
+ 0x10077f48 0x96 _zPHY_ecsrc_CtrlCampOnProcess
+ 0x10077fde 0x9a _zPHY_ecsrc_CtrlMeasConfigProcess
+ 0x10078078 0x141 _zPHY_ecsrc_CtrlMeasSetProcess
+ 0x100781b9 0x37 _zPHY_ecsrc_SetMeasAge
+ 0x100781f0 0x7b _L1e_csrc_IdleSetAgeThrold
+ 0x1007826b 0x147 _L1e_csrc_ConnectSetAgeThrold
+ 0x100783b2 0x46 _zPHY_ecsrc_CtrlSetSearchMeasAgeThrold
+ 0x100783f8 0x73 _zPHY_ecsrc_ReadRxMeas
+ 0x1007846b 0x47 _zPHY_ecsrc_ReadServCellRxMeas
+ 0x100784b2 0x23 _zPHY_ecsrc_GetCellMeasReslut
+ 0x100784d5 0x96 _zPHY_ecsrc_CtrlWriteServingCellResult
+ 0x1007856b 0x3d _zPHY_ecsrc_SetMeasResultValue
+ 0x100785a8 0x3c _zPHY_ecsrc_WriteNeibMeasResult
+ 0x100785e4 0x10 _zPHY_ecsrc_CtrlWritePccMeasResult
+ 0x100785f4 0x14d _zPHY_ecsrc_CtrlMeasFilterReq
+ 0x10078741 0x13 _zPHY_ecsrc_ConnAcquireIntraMeas
+ 0x10078754 0x70 _zPHY_ecsrc_AcquireInterMeas
+ 0x100787c4 0x16 _zPHY_ecsrc_AcquireServMeas
+ 0x100787da 0xd _zPHY_ecsrc_ReportMeasReslutIntra
+ 0x100787e7 0x50 _zPHY_ecsrc_ReportMeasReslutInter
+ 0x10078837 0x2b _zPHY_ecsrc_UpdateRsrpKByFlagCounter
+ 0x10078862 0x38 _zPHY_ecsrc_AdaptFilterFactor
+ 0x1007889a 0xb5 _zPHY_ecsrc_FreqFilter
+ 0x1007894f 0x33 _zPHY_ecsrc_FilterNoResult
+ 0x10078982 0x30 _zPHY_ecsrc_DelInvalidCell
+ 0x100789b2 0x9b _zPHY_ecsrc_InterMeasFilter
+ 0x10078a4d 0x72 _zPHY_ecsrc_IntraMeasFilter
+ 0x10078abf 0x69 _zPHY_ecsrc_FilterMeasRank
+ 0x10078b28 0x42 _zPHY_ecsrc_ReportMeasRank
+ 0x10078b6a 0x34 _zPHY_ecsrc_UpdateFreqReport
+ 0x10078b9e 0x7a _zPHY_ecsrc_UpdateIntraReport
+ 0x10078c18 0x9 _zPHY_ecsrc_GetFilterIntraMeasRsrp
+ 0x10078c21 0x70 _zPHY_ecsrc_UpdateInterReport
+ 0x10078c91 0x12 _zPHY_ecsrc_ClearNeibCellRsrp
+ 0x10078ca3 0x1c _zPHY_ecsrc_ClearIntraFilter
+ 0x10078cbf 0x23 _L1e_csrc_SetIdleFilterFactor
+ 0x10078ce2 0x2e _zPHY_ecsrc_SetFilterFactor
+ 0x10078d10 0x62 _zPHY_ecsrc_FilterMeasCfg
+ 0x10078d72 0x4 _zPHY_ecsrc_FilterComnCfg
+ 0x10078d76 0xc _zPHY_ecsrc_InitInterFilter
+ 0x10078d82 0x36 _zPHY_ecsrc_InitInterFilterFreq
+ 0x10078db8 0x60 _zPHY_ecsrc_InitIntraFilter
+ 0x10078e18 0x47 _zPHY_ecsrc_InterMeasIndPrint
+ 0x10078e5f 0x49 _zPHY_ecsrc_CtrlIntraMeasInfoPrint
+ 0x10078ea8 0x37 _zPHY_ecsrc_IntraFilterDebugInfo
+ 0x10078edf 0x4a _zPHY_ecsrc_InterFilterDebugInfo
+ 0x10078f29 0x12 _zPHY_ecsrc_CaSwitch
+ 0x10078f3b 0x78 _zPHY_ecsrc_ProPhy2PsMsgSINRandRSSI
+ 0x10078fb3 0x54 _zPHY_ecsrc_WriteRssiToSearchCnf
+ 0x10079007 0x25 _zPHY_ecsrc_AcquireIntraMeas
+ 0x1007902c 0x41 _zPHY_ecsrc_SrvCellResltDeal
+ 0x1007906d 0x45 _zPHY_ecsrc_ClearAfcInfo
+ 0x100790b2 0x6a _L1e_DevCsrNCellRsNullInd
+ 0x1007911c 0x10 _L1e_DevCsrGetMeasResult
+ 0x1007912c 0x3b _zPHY_ecsrc_CtrlIdleSetInterFilterFact
+ .text 0x10079167 0x21b2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x10079167 0x8 _L1e_Sir_RxMeasMask
+ 0x1007916f 0x8 _L1e_Sir_QuryRxMeasMask
+ 0x10079177 0x27f _L1e_Sir_MainCtrlFlow
+ 0x100793f6 0x33 _L1e_Sir_DbReset
+ 0x10079429 0x31 _L1e_Sir_LpcAndTurboCtrl
+ 0x1007945a 0x30 _L1e_Sir_AddTpuEvt
+ 0x1007948a 0x28 _L1e_Sir_DelAllTpuEvt
+ 0x100794b2 0x26 _L1e_Sir_QueryTpuEvt
+ 0x100794d8 0x33 _L1e_Sir_DelTpuEvt
+ 0x1007950b 0x4a _L1e_Sir_RegDelayEvt
+ 0x10079555 0x21 _L1e_Sir_PreProc
+ 0x10079576 0x8 _L1e_Sir_MainState
+ 0x1007957e 0x8 _L1e_Sir_StepState
+ 0x10079586 0x8 _L1e_Sir_SyncState
+ 0x1007958e 0x19 _L1e_Sir_CommInSiProc
+ 0x100795a7 0x34 _L1e_Sir_SetState
+ 0x100795db 0x98 _L1e_Sir_UpSib1Para
+ 0x10079673 0x75 _L1e_Sir_UpSiPara
+ 0x100796e8 0x15 _L1e_Sir_UpSerPara
+ 0x100796fd 0x2d _L1e_Sir_UpDecPara
+ 0x1007972a 0x8 _L1e_Sir_UpDecState
+ 0x10079732 0xd _L1e_Sir_QurySerSir
+ 0x1007973f 0xc _L1e_Sir_QurySib1State
+ 0x1007974b 0xd _L1e_Sir_QurySiState
+ 0x10079758 0x1a _L1e_Sir_QueryRptEn
+ 0x10079772 0x14 _L1e_Sir_CtrlDecOps
+ 0x10079786 0x23 _L1e_Sir_UpSibWin
+ 0x100797a9 0x56 _L1e_Sir_StopSibProc
+ 0x100797ff 0x4e _L1e_Sir_UpSchedPara
+ 0x1007984d 0x96 _L1e_Sir_StartSib1
+ 0x100798e3 0x71 _L1e_Sir_BchSync
+ 0x10079954 0x5c _L1e_Sir_RestartBch
+ 0x100799b0 0xcc _L1e_Sir_StartSi
+ 0x10079a7c 0xb7 _L1e_Sir_AbortSi
+ 0x10079b33 0x64 _L1e_Sir_SchedSib1
+ 0x10079b97 0xd4 _L1e_Sir_SchedSi
+ 0x10079c6b 0xcb _L1e_Sir_ProcDecSucc
+ 0x10079d36 0xd0 _L1e_Sir_BackSerCell
+ 0x10079e06 0x2c _L1e_Sir_DataReport
+ 0x10079e32 0x92 _L1e_Sir_SndMibReq
+ 0x10079ec4 0x39 _L1e_Sir_SndMibCnf
+ 0x10079efd 0x19 _L1e_Sir_SndBchFail
+ 0x10079f16 0x7d _L1e_Sir_QueryMib
+ 0x10079f93 0x2e _L1e_Sir_ProBchHandle
+ 0x10079fc1 0x43 _L1e_Sir_QueryCell
+ 0x1007a004 0x15 _L1e_Sir_CtrlAgcState
+ 0x1007a019 0x40 _L1e_Sir_UpRfcCfg
+ 0x1007a059 0x7 _L1e_Sir_CalBoundryTs
+ 0x1007a060 0x81 _L1e_Sir_DelyTpuAdjust
+ 0x1007a0e1 0x60 _L1e_Sir_TpuMacroAdjust
+ 0x1007a141 0x2 _L1e_Sir_SndTpuAdjust
+ 0x1007a143 0x8f _L1e_Sir_StartWinEvtCB
+ 0x1007a1d2 0x60 _L1e_Sir_EndWinEvtCB
+ 0x1007a232 0x32 _L1e_Sir_RegWindowEvt
+ 0x1007a264 0x9e _L1e_Sir_CalNearRxRcv
+ 0x1007a302 0x5a _L1e_Sir_CheckRxRcv
+ 0x1007a35c 0x39 _L1e_Sir_CellSync
+ 0x1007a395 0x3d _L1e_Sir_CheckPaging
+ 0x1007a3d2 0x7d _L1e_Sir_CheckGapPos
+ 0x1007a44f 0x5e _L1e_Sir_SerCellBackProc
+ 0x1007a4ad 0x7 _L1e_Sir_SetAbortSiProcState
+ 0x1007a4b4 0x7 _L1e_Sir_GetAbortSiProcState
+ 0x1007a4bb 0x7 _L1e_Sir_SetSiDelayProcState
+ 0x1007a4c2 0x7 _L1e_Sir_GetSiDelayProcState
+ 0x1007a4c9 0x7 _L1e_Sir_SetTimingNeibState
+ 0x1007a4d0 0x7 _L1e_Sir_GetTimingNeibState
+ 0x1007a4d7 0x10 _L1e_Sir_GetMibReadStateInSib
+ 0x1007a4e7 0x13 _L1e_Sir_GetSibState
+ 0x1007a4fa 0x68 _L1e_Sir_GetNextSiWinTime
+ 0x1007a562 0x1a _L1e_Sir_GetNeiBorSiState
+ 0x1007a57c 0x1e _L1e_Sir_GetNeiBorSibState
+ 0x1007a59a 0x2d _L1e_Sir_GetNeiBorSib1ReportState
+ 0x1007a5c7 0x1c _L1e_Sir_GetSerSibState
+ 0x1007a5e3 0x12 _L1e_Sir_GetNeiBorSiBackState
+ 0x1007a5f5 0xd _L1e_Sir_CleanSiPreSyncState
+ 0x1007a602 0x8 _L1e_Sir_GetSiSubFrmPat
+ 0x1007a60a 0xb9 _L1e_Sir_PreSyncProc
+ 0x1007a6c3 0x80 _L1e_Sir_PreSyncSched
+ 0x1007a743 0x7 _L1e_Sir_SetSiSyncState
+ 0x1007a74a 0x7 _L1e_Sir_GetSiSyncState
+ 0x1007a751 0x7 _L1e_Sir_SetSiSyncSchedState
+ 0x1007a758 0x7 _L1e_Sir_GetSiSyncSchedState
+ 0x1007a75f 0x28 _L1e_Sir_SiWakeUpProc
+ 0x1007a787 0x12 _L1e_Sir_GetBandWidth
+ 0x1007a799 0xc5 _L1e_Sir_StartAnr
+ 0x1007a85e 0x8 _L1e_Anr_QueryEn
+ 0x1007a866 0x8 _L1e_Anr_GetState
+ 0x1007a86e 0x8 _L1e_Anr_ProcIndGet
+ 0x1007a876 0x1f _L1e_Anr_SetState
+ 0x1007a895 0x2fd _L1e_Anr_SubFrmProc
+ 0x1007ab92 0x1c _L1e_Anr_BchProc
+ 0x1007abae 0x6 _L1e_Anr_BchBackSerRx
+ 0x1007abb4 0x19 _L1e_Anr_AbortSi
+ 0x1007abcd 0x2f _L1e_Anr_Reset
+ 0x1007abfc 0x11 _L1e_Anr_ProcDecSucc
+ 0x1007ac0d 0x7e _L1e_Anr_NeibLocalMrtr
+ 0x1007ac8b 0xc1 _L1e_Anr_SwitchRF
+ 0x1007ad4c 0x1a _L1e_Anr_GetAutoGapState
+ 0x1007ad66 0x49 _L1e_Anr_TpuMacroAdjust
+ 0x1007adaf 0xe _L1e_Anr_EnableRxRcv
+ 0x1007adbd 0x6e _L1e_Anr_CalNeibTime
+ 0x1007ae2b 0x2 _L1e_Anr_BchAbortProc
+ 0x1007ae2d 0xd _L1e_Anr_SibAbortProc
+ 0x1007ae3a 0x2c _L1e_Sir_Sib1MsgMonitor
+ 0x1007ae66 0x59 _L1e_Sir_SiMsgMonitor
+ 0x1007aebf 0x29 _L1e_Sir_SibReportMonitor
+ 0x1007aee8 0x2c _L1e_Sir_StateMonitor
+ 0x1007af14 0x2f _L1e_Sir_ErrMonitor
+ 0x1007af43 0x5c _L1e_Sir_RfcMonitor
+ 0x1007af9f 0x93 _L1e_Sir_CellMonitor
+ 0x1007b032 0x38 _L1e_Sir_SibParaMonitor
+ 0x1007b06a 0x43 _L1e_Sir_MibCnfMonitor
+ 0x1007b0ad 0x2c _L1e_Sir_RxRcvCtrlMonitor
+ 0x1007b0d9 0x5b _L1e_Sir_SchedParaMonitor
+ 0x1007b134 0x6e _L1e_Sir_StartWinMonitor
+ 0x1007b1a2 0x6e _L1e_Sir_EndWinMonitor
+ 0x1007b210 0x24 _L1e_Sir_AnrStateMonitor
+ 0x1007b234 0x51 _L1e_Anr_StartMonitor
+ 0x1007b285 0x34 _L1e_Sir_AnrRfcMonitor
+ 0x1007b2b9 0x32 _L1e_Anr_GapPrintf
+ 0x1007b2eb 0x2e _L1e_Anr_ErrProcMonitor
+ .text 0x1007b319 0x3fde T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x1007b319 0x27 _zPHY_emc_DvfsPatch
+ 0x1007b340 0x12 _zPHY_emc_PsMsgIdFindIndex
+ 0x1007b352 0x12 _zPHY_emc_PhyMsgIdFindIndex
+ 0x1007b364 0x12 _zPHY_emc_FindSynMsgIndex
+ 0x1007b376 0x12 _zPHY_emc_FindEmpLoc
+ 0x1007b388 0xf _zPHY_emc_FindAllSyncMsg
+ 0x1007b397 0x26 _zPHY_emc_ClearSyncMsg
+ 0x1007b3bd 0x131 _zPHY_emc_ReadSyncMsg
+ 0x1007b4ee 0x55 _zPHY_emc_StubRecvSyncMsg
+ 0x1007b543 0x1a _zPHY_emc_GetPs2PhyCF
+ 0x1007b55d 0x3a _zPHY_emc_LteAmtUpdateServeCellEarfch
+ 0x1007b597 0x8 _l1e_SchedMcIdlePiCnt
+ 0x1007b59f 0x17b _zPHY_emc_ProInitial
+ 0x1007b71a 0x11 _memcpy_Ps2PhySram
+ 0x1007b72b 0x35 _zPHY_emc_ProPs2PhyMsgLog
+ 0x1007b760 0x5a _zPHY_emc_ProPhy2PsMsgLog
+ 0x1007b7ba 0x6b8 _zPHY_emc_ProSyncMsgSend
+ 0x1007be72 0x27e _zPHY_emc_ProDedicatedMsg
+ 0x1007c0f0 0x1a1 _zPHY_emc_ProPs2PhySyncMsg
+ 0x1007c291 0x41 _zPHY_emc_ProAbortAccessMsg
+ 0x1007c2d2 0x1ad _zPHY_emc_ProAccessMsg
+ 0x1007c47f 0x5 _zPHY_emc_ProTaCmdMsg
+ 0x1007c484 0x12 _zPHY_emc_ProTaTimeStopMsg
+ 0x1007c496 0x24e _zPHY_emc_ProPs2PhyMsgRouter
+ 0x1007c6e4 0x2c _zPHY_emc_WakeUpPS
+ 0x1007c710 0x1c _zPHY_emc_SendIcpToPS
+ 0x1007c72c 0xd5 _zPHY_emc_ProPhy2PsMsgRouter
+ 0x1007c801 0x275 _zPHY_emc_ProReleaseFlow
+ 0x1007ca76 0x1a8 _zPHY_emc_ProTimingCtrlFlow
+ 0x1007cc1e 0x1fd _zPHY_emc_ProTASchedFlow
+ 0x1007ce1b 0x46 _zPHY_emc_ProMacResetFlow
+ 0x1007ce61 0x57 _zPHY_emc_ProSubfrmTypeConfig
+ 0x1007ceb8 0x20d _zPHY_emc_ProResetFlow
+ 0x1007d0c5 0x207 _zPHY_emc_ProSetModeFlow
+ 0x1007d2cc 0x2b _zPHY_emc_ProShowLtePhyStateInfo
+ 0x1007d2f7 0x58 _zPHY_emc_ProShowLtePhySIDInfo
+ 0x1007d34f 0x11b _zPHY_emc_ProAfcConfig
+ 0x1007d46a 0x14 _zPHY_emc_UpdateIniFreq
+ 0x1007d47e 0x12 _zPHY_emc_ReadIniFreq
+ 0x1007d490 0x53 _zPHY_emc_StartGapDelayPro
+ 0x1007d4e3 0x63 _zPHY_emc_GetRfTpuRegTime
+ 0x1007d546 0x25 _zPHY_emc_RegEvent
+ 0x1007d56b 0x13 _zPHY_emc_DelEvent
+ 0x1007d57e 0x40 _zPHY_emc_RfDeal
+ 0x1007d5be 0xb _zPHY_emc_ResetProOn
+ 0x1007d5c9 0xb _zPHY_emc_RelProOn
+ 0x1007d5d4 0x15 _zPHY_emc_InitScellInfo
+ 0x1007d5e9 0x1 _zPHY_emc_ModifyScellExistFlag
+ 0x1007d5ea 0x1 _zPHY_emc_ModifyScellActiveFlag
+ 0x1007d5eb 0x1d _zPHY_emc_InitScellDefaultPara
+ 0x1007d608 0x21 _zPHY_emc_ScellRatModeSet
+ 0x1007d629 0x10 _zPHY_emc_FindFreeSCarrier
+ 0x1007d639 0x10 _zPHY_emc_AddSCarrier
+ 0x1007d649 0x29 _zPHY_emc_ReleaseSCarrier
+ 0x1007d672 0x41 _zPHY_emc_ModifyScellInfo
+ 0x1007d6b3 0x2 _zPHY_emc_ActiveScell
+ 0x1007d6b5 0x2 _zPHY_emc_DeactiveScell
+ 0x1007d6b7 0x2 _zPHY_emc_AutoDeactiveScell
+ 0x1007d6b9 0x2 _zPHY_emc_UpdateDeactInfo
+ 0x1007d6bb 0xa _zPHY_emc_IsAnyScellExist
+ 0x1007d6c5 0xa _zPHY_emc_IsAnyScellActive
+ 0x1007d6cf 0x2 _zPHY_emc_IsScellExist
+ 0x1007d6d1 0x2 _zPHY_emc_IsScellActive
+ 0x1007d6d3 0x2 _zPHY_emc_ReadScellCfgDedi
+ 0x1007d6d5 0x2 _zPHY_emc_ReadScellCfgComn
+ 0x1007d6d7 0x11 _zPHY_emc_ReadScellBasicInfo
+ 0x1007d6e8 0x23 _zPHY_emc_ReadFixDlDelay
+ 0x1007d70b 0x4e _zPHY_emc_SetSysband
+ 0x1007d759 0x52 _zPHY_emc_AlterRateRefreshFB
+ 0x1007d7ab 0x44 _L1e_Anr_AlterRateRefreshFB
+ 0x1007d7ef 0x1e _zPHY_emc_CfgSysband
+ 0x1007d80d 0x1c _zPHY_emc_IsSysbandVarious
+ 0x1007d829 0x19 _zPHY_emc_ReadGapStatue
+ 0x1007d842 0x1f _zPHY_emc_ReadIratGapStatue
+ 0x1007d861 0x15 _zPHY_emc_RfcRbdpCfg
+ 0x1007d876 0x76 _zPHY_emc_ProGapDelayFlow
+ 0x1007d8ec 0x153 _zPHY_emc_ProGapSchedFlow
+ 0x1007da3f 0x2f _zPHY_emc_ScellActiveNoactiveMain
+ 0x1007da6e 0xe _L1e_SchedMcSetSCellDeactivationTimerParam
+ 0x1007da7c 0x7 _L1e_SchedMcGetSCellDeactivationTimerParam
+ 0x1007da83 0x9 _L1e_SchedMcSetSCellDeactivationTimer
+ 0x1007da8c 0xc _L1e_SchedMcIncSCellDeactivationTimer
+ 0x1007da98 0x9 _L1e_SchedMcGetSCellDeactivationTimer
+ 0x1007daa1 0x35 _L1e_SchedMcAutoDeactiveScc
+ 0x1007dad6 0x34 _L1e_SchedMcDeactiveScc
+ 0x1007db0a 0x8f _zPHY_emc_ScellGetRFPara
+ 0x1007db99 0x45 _L1e_SchedMc_CfgUlFreqPoint
+ 0x1007dbde 0x3d _zPHY_emc_ScellRFParaPrint
+ 0x1007dc1b 0x45 _L1e_LogMcSCellInfo
+ 0x1007dc60 0x1d _L1e_SchedMc_ConvertBW
+ 0x1007dc7d 0x86 _L1e_SchedMc_CloseRxRecv
+ 0x1007dd03 0x20 _zPHY_emc_ProClrRfcDBState
+ 0x1007dd23 0x135 _L1e_SchedMc_CfgRfcRxSFData
+ 0x1007de58 0xd _L1e_SchedMc_GetRxRecvState
+ 0x1007de65 0xd _L1e_SchedMc_GetCalcTimeState
+ 0x1007de72 0xd _L1e_SchedMc_GetCfgSrcIdx
+ 0x1007de7f 0x32 _L1e_SchedMc_OpenRxRecv
+ 0x1007deb1 0xc1 _L1e_SchedMc_CalcRxRecvTime
+ 0x1007df72 0x1a _L1e_SchedMc_CalcRxCloseTime
+ 0x1007df8c 0xb9 _L1e_SchedMc_OpenRxRF
+ 0x1007e045 0x147 _L1e_SchedMc_OpenRxRFByCc
+ 0x1007e18c 0x30 _L1e_SchedMc_JudgeRfOpenTime
+ 0x1007e1bc 0x1e _L1e_SchedMc_JudgeRfClose
+ 0x1007e1da 0x16 _L1e_SchedMc_Set4RxRcv
+ 0x1007e1f0 0x8 _L1e_SchedMc_Clr4RxRcv
+ 0x1007e1f8 0x7 _L1e_SchedMc_Get4RxRcv
+ 0x1007e1ff 0x1a _L1e_SchedMc_CfgRfcRxClose
+ 0x1007e219 0x17c _zPHY_emc_SetAndReadPhyPara
+ 0x1007e395 0x8 _zPHY_emc_AsynMsgProcIratGapConfigReq
+ 0x1007e39d 0x9f _zPHY_emc_RdPs2PhyAsyncMsg
+ 0x1007e43c 0x63 _zPHY_emc_CalTpuMrtrAdjType
+ 0x1007e49f 0x48 _zPHY_emc_RefreshPagePara
+ 0x1007e4e7 0x1b _zPHY_SendMsg
+ 0x1007e502 0x1c _zPHY_SendNullMsg
+ 0x1007e51e 0x62 _L1e_SchedMcGetCellInfo
+ 0x1007e580 0xd _L1e_SchedMc_AbortSi
+ 0x1007e58d 0xd _L1e_SchedMc_AbortSearch
+ 0x1007e59a 0xd _L1e_SchedMc_StoreSib
+ 0x1007e5a7 0xd _L1e_SchedMc_StoreSi
+ 0x1007e5b4 0x8 _L1e_SchedMc_SetDelayAnrState
+ 0x1007e5bc 0x8 _L1e_SchedMc_GetDelayAnrState
+ 0x1007e5c4 0xd _L1e_SchedMc_StoreSearch
+ 0x1007e5d1 0xd _L1e_SchedMc_StoreFreqScan
+ 0x1007e5de 0xd _L1e_SchedMc_StoreRapc
+ 0x1007e5eb 0x3b _L1e_SchedMc_SndDelaySearch
+ 0x1007e626 0x3c _L1e_SchedMc_SendDelayFreqScan
+ 0x1007e662 0x1a _L1e_SchedMc_SndDelaySib
+ 0x1007e67c 0x1a _L1e_SchedMc_SndDelaySi
+ 0x1007e696 0x10 _L1e_SchedMc_SndDelayRapc
+ 0x1007e6a6 0x1e _L1e_SchedMc_ReadTpuOffset
+ 0x1007e6c4 0x10 _zPHY_emc_ATSetDrxCtrl
+ 0x1007e6d4 0x83 _zPHY_emc_ATSetAndReadRlm
+ 0x1007e757 0x65 _zPHY_emc_ATSetAndReadCsi
+ 0x1007e7bc 0xc5 _zPHY_emc_ATSetAndReadUlpc
+ 0x1007e881 0x72 _zPHY_emc_ATSetAntenna
+ 0x1007e8f3 0x56 _zPHY_emc_ATSetAndReadUeCategory
+ 0x1007e949 0x21 _zPHY_emc_ATCheckSinr
+ 0x1007e96a 0x20 _zPHY_emc_ATCheckTmMode
+ 0x1007e98a 0x4f _zPHY_emc_ATCheckMcsQmod
+ 0x1007e9d9 0x6e _zPHY_emc_ATCheckHarqNack
+ 0x1007ea47 0x32 _zPHY_emc_ATCheckThrougput
+ 0x1007ea79 0x1f _zPHY_emc_ATCheckRssi
+ 0x1007ea98 0x32 _zPHY_emc_ATCheckSinrRsrp
+ 0x1007eaca 0x2a _zPHY_emc_ATCheckResidualBler
+ 0x1007eaf4 0x8a _zPHY_emc_ATCheckAll
+ 0x1007eb7e 0x1f _zPHY_emc_ATThinkWill
+ 0x1007eb9d 0x2b _zPHY_emc_ATLowPower
+ 0x1007ebc8 0x3d _zPHY_emc_ExtraCheck
+ 0x1007ec05 0x6f2 _zPHY_emc_ThreadEntry
+ .text 0x1007f2f7 0x542f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x1007f2f7 0x16 _zPHY_ecsrc_LteAmtUpdateServeCellEarfch
+ 0x1007f30d 0x35 _zPHY_ecsrc_ReadEarfcnInfo
+ 0x1007f342 0x3a _zPHY_ecsrc_GetDLULEarfchTableInfo
+ 0x1007f37c 0x52 _zPHY_ecsrc_GetEarfchTableInfo
+ 0x1007f3ce 0x11 _zPHY_ecsrc_SchedEarfcn2Freq
+ 0x1007f3df 0x14 _zPHY_ecsrc_SchedFreq2Earfcn
+ 0x1007f3f3 0x2e _zPHY_ecsrc_FindEarfchFromEarfcn
+ 0x1007f421 0x58 _zPHY_ecsrc_GetUlEarfchTableInfo
+ 0x1007f479 0x19 _zPHY_ecsrc_GetTddFddMode
+ 0x1007f492 0x13 _zPHY_ecsrc_CtrlRsrpTrans
+ 0x1007f4a5 0x12 _zPHY_ecsrc_CtrlRsrqTrans
+ 0x1007f4b7 0xc _zPHY_ecsrc_NvReadRsrpFixedOffset
+ 0x1007f4c3 0x36 _zPHY_ecsrc_SendSearchStartReq
+ 0x1007f4f9 0x37 _zPHY_ecsrc_SendCfoStartReq
+ 0x1007f530 0x8f _zPHY_ecsrc_SendMeasStartReq
+ 0x1007f5bf 0x24 _zPHY_ecsrc_SendHandoverCnf
+ 0x1007f5e3 0x51 _zPHY_ecsrc_SendMibReadReq
+ 0x1007f634 0x2c _zPHY_ecsrc_SendTpuMacroAdjReq
+ 0x1007f660 0x2c _zPHY_ecsrc_SendFreqScanReq
+ 0x1007f68c 0xd _zPHY_ecsrc_OnSendFreqScanReq
+ 0x1007f699 0x8 _zPHY_ecsrc_SetAllRxMaskFlag
+ 0x1007f6a1 0x11 _zPHY_ecsrc_SleepCtrlPowerOn
+ 0x1007f6b2 0x13 _L1e_csrc_InitStrInfo
+ 0x1007f6c5 0xec _zPHY_ecsrc_ProInitial
+ 0x1007f7b1 0x11 _zPHY_ecsrc_InitSlaveWorkState
+ 0x1007f7c2 0x13 _zPHY_ecsrc_ProReset
+ 0x1007f7d5 0x15 _zPHY_ecsrc_SetPhyModeByEarfcn
+ 0x1007f7ea 0x10 _zPHY_emc_SetPhyMode
+ 0x1007f7fa 0x14 _zPHY_ecsrc_FindTpuEvent
+ 0x1007f80e 0x40 _zPHY_ecsrc_TpuEventReset
+ 0x1007f84e 0x3a _zPHY_ecsrc_TpuEventMark
+ 0x1007f888 0x1b _zPHY_ecsrc_TpuEventCheck
+ 0x1007f8a3 0x4c _zPHY_ecsrc_DelTpuEvent
+ 0x1007f8ef 0x1c _zPHY_ecsrc_TpuEventClean
+ 0x1007f90b 0x7 _zPHY_ecsrc_FilterEnDelay
+ 0x1007f912 0x22 _zPHY_ecsrc_GetBandIdx
+ 0x1007f934 0x2b _zPHY_ecsrc_MibInfoOutput
+ 0x1007f95f 0x23 _zPHY_ecsrc_FilterOut
+ 0x1007f982 0x62 _zPHY_ecsrc_CtrlReleaseProcess
+ 0x1007f9e4 0x69 _zPHY_ecsrc_CfgRfcFreqBand
+ 0x1007fa4d 0x1c _L1e_csrc_CfgSysband
+ 0x1007fa69 0x2d _zPHY_ecsrc_RecoverToServingFreq
+ 0x1007fa96 0x1c _zPHY_ecsrc_ResetSearchMeas
+ 0x1007fab2 0x71 _zPHY_ecsrc_StopInterSearchMeas
+ 0x1007fb23 0x40 _L1e_csrc_PreWakeUpPS
+ 0x1007fb63 0x18 _zPHY_ecsrc_TsDelayMsgRegister
+ 0x1007fb7b 0x34 _zPHY_ecsrc_DelayMsgRegister
+ 0x1007fbaf 0x4d _zPHY_ecsrc_RegTpuAdjDelay
+ 0x1007fbfc 0x11a _zPHY_ecsrc_CtrlConnectedIntraReportEvent
+ 0x1007fd16 0x4a _zPHY_ecsrc_CtrlConnectedInterReportEvent
+ 0x1007fd60 0x38 _zPHY_ecsrc_CtrlConnectAgingProcess
+ 0x1007fd98 0x17 _zPHY_ecsrc_CfgRfcSynState
+ 0x1007fdaf 0x37 _zPHY_ecsrc_GetInterReportPeriod
+ 0x1007fde6 0x88 _zPHY_ecsrc_CtrlConnectedMeasSchedule
+ 0x1007fe6e 0x31 _zPHY_ecsrc_OpenSubFrameInt
+ 0x1007fe9f 0x15 _zPHY_ecsrc_DelSfInt
+ 0x1007feb4 0x18 _zPHY_ecsrc_InitGapCnt
+ 0x1007fecc 0x19 _zPHY_ecsrc_UpdateGapCnt
+ 0x1007fee5 0x3d _zPHY_ecsrc_DrxRefreshGapCnt
+ 0x1007ff22 0x48 _zPHY_ecsrc_DrxSetIntraWorkPeriod
+ 0x1007ff6a 0x80 _zPHY_ecsrc_DrxSetInterWorkPeriod
+ 0x1007ffea 0x13 _zPHY_ecsrc_DrxSetInterRprtPeriod
+ 0x1007fffd 0x8d _L1e_csrc_RegConEvent
+ 0x1008008a 0x77 _zPHY_ecsrc_CtrlDedicateConfigProcess
+ 0x10080101 0x48 _zPHY_ecsrc_CtrlConncetGapConfigProcess
+ 0x10080149 0x100 _zPHY_ecsrc_CtrlConnectedSetInterFreq
+ 0x10080249 0xa6 _zPHY_ecsrc_CtrlConnectedScheduleInterFreq
+ 0x100802ef 0xc7 _zPHY_ecsrc_CtrlHandoverSearch
+ 0x100803b6 0x25 _zPHY_ecsrc_CtrlHandoverCfoEn
+ 0x100803db 0x1f _zPHY_ecsrc_CtrlHandoverMibInd
+ 0x100803fa 0x112 _zPHY_ecsrc_CtrlHandoverPro
+ 0x1008050c 0x114 _zPHY_ecsrc_CtrlHandoverSearchTimeEvent
+ 0x10080620 0x49 _zPHY_ecsrc_CtrlHandoverPbchTimeEvent
+ 0x10080669 0x38 _zPHY_ecsrc_LteAmtULEarfchTableInfo
+ 0x100806a1 0x38 _zPHY_ecsrc_LteAmtDLEarfchTableInfo
+ 0x100806d9 0x3a _zPHY_ecsrc_LteAmtFDTEarfchTableInfo
+ 0x10080713 0x86 _zPHY_ecsrc_AmtUpdateEarfcnBand
+ 0x10080799 0x2d _zPHY_ecsrc_RegDrxNoUseEvent
+ 0x100807c6 0x24 _zPHY_ecsrc_DelDrxNoUseEvent
+ 0x100807ea 0xc _zPHY_ecsrc_IsDrxUsed
+ 0x100807f6 0x29 _zPHY_ecsrc_IsWorkGap
+ 0x1008081f 0x34 _zPHY_ecsrc_WaitIratGap
+ 0x10080853 0x42 _zPHY_ecsrc_IntraFreqEnable
+ 0x10080895 0x5e _zPHY_ecsrc_InterFreqEnable
+ 0x100808f3 0xb8 _zPHY_ecsrc_CalIntraWorkTime
+ 0x100809ab 0x4d _zPHY_ecsrc_SetSearchPhase
+ 0x100809f8 0x4c _zPHY_ecsrc_GetSearchPhase
+ 0x10080a44 0x1b _zPHY_ecsrc_ClearSearchEnable
+ 0x10080a5f 0x49 _zPHY_ecsrc_FindEnableFreq
+ 0x10080aa8 0x3a _zPHY_ecsrc_UpdateSearchEnable
+ 0x10080ae2 0x2f _zPHY_ecsrc_IsSearchDone
+ 0x10080b11 0x4b _zPHY_ecsrc_RecoverEnableFlag
+ 0x10080b5c 0x90 _zPHY_ecsrc_CalRemainTime
+ 0x10080bec 0x1cf _zPHY_ecsrc_FindUndoneFreq
+ 0x10080dbb 0x1b _L1e_csrc_FindEnableInterFreq
+ 0x10080dd6 0x1d5 _L1e_csrc_FindUndoFreq
+ 0x10080fab 0x6c _L1e_csrc_DrxIntraReport
+ 0x10081017 0x4e _L1e_csrc_DrxInterReport
+ 0x10081065 0xb7 _L1e_csrc_DrxSchdEnd
+ 0x1008111c 0x3b _L1e_csrc_DrxIntraSchd
+ 0x10081157 0x42 _L1e_csrc_DrxInterSchd
+ 0x10081199 0x6e _L1e_csrc_ShortDrxIntraSchd
+ 0x10081207 0x40 _L1e_csrc_ShortDrxInterSchd
+ 0x10081247 0x49 _L1e_csrc_AbortDrxSchd
+ 0x10081290 0x15 _L1e_csrc_CsrIsWork
+ 0x100812a5 0x127 _zPHY_ecsrc_DrxCheckEvent
+ 0x100813cc 0x8 _L1e_csrc_GetStopMeas
+ 0x100813d4 0xe _L1e_csrc_CfgGapCnt
+ 0x100813e2 0xca _L1e_csrc_ShortDrxSchd
+ 0x100814ac 0x30 _L1e_csrc_ShortDrxReSchd
+ 0x100814dc 0x104 _zPHY_ecsrc_CnnDrxStartSchedule
+ 0x100815e0 0x48 _zPHY_ecsrc_CnnDrxSetup
+ 0x10081628 0x1b _zPHY_ecsrc_CnnDrxRelease
+ 0x10081643 0x41 _L1e_csrc_ShortDrxSchdFlag
+ 0x10081684 0x8 _L1e_csrc_GetDfeValidFlag
+ 0x1008168c 0x87 _zPHY_ecsrc_CtrlAbortMeasProcess
+ 0x10081713 0x8 _zPHY_ecsrc_ReadSubframeOffset
+ 0x1008171b 0x15 _zPHY_ecsrc_SubframeOffsetToRfc
+ 0x10081730 0x8 _zPHY_ecsrc_SetFddAdjust
+ 0x10081738 0x30 _zPHY_ecsrc_ClearRfcSFData
+ 0x10081768 0x12 _zPHY_ecsrc_ClearRfTable
+ 0x1008177a 0x12 _L1e_csrc_ClearRfMeasState
+ 0x1008178c 0x2c _zPHY_ecsrc_SetFreq
+ 0x100817b8 0xa _zPHY_ecsrc_SetInterFreq
+ 0x100817c2 0x15 _zPHY_ecsrc_FindEvent
+ 0x100817d7 0x43 _zPHY_ecsrc_RegisterEvent
+ 0x1008181a 0x1d _zPHY_ecsrc_CancelEvent
+ 0x10081837 0x12 _zPHY_ecsrc_CancelAllEvent
+ 0x10081849 0x7b _zPHY_ecsrc_CheckEvent
+ 0x100818c4 0x40 _zPHY_ecsrc_ConnCheckEvent
+ 0x10081904 0x44 _zPHY_ecsrc_ExcuteEvent
+ 0x10081948 0x25 _zPHY_ecsrc_ChangeIntraReportPeriod
+ 0x1008196d 0x33 _zPHY_ecsrc_ChangeIntraReportPeriodDrx
+ 0x100819a0 0x7 _zPHY_ecsrc_OnSetMode
+ 0x100819a7 0x25 _zPHY_ecsrc_OnIratIdlePeriodRepReq
+ 0x100819cc 0x37 _zPHY_ecsrc_OnInactiveTimeReportInt
+ 0x10081a03 0x19 _zPHY_ecsrc_OnFreqListConfigReq
+ 0x10081a1c 0x2e _zPHY_ecsrc_OnIratMeasConfigReq
+ 0x10081a4a 0x32 _zPHY_ecsrc_OnIratMeasReportInt
+ 0x10081a7c 0xf1 _zPHY_ecsrc_OnIratGapConfigReq
+ 0x10081b6d 0x6f _zPHY_ecsrc_OnIratGapConfigDelayInt
+ 0x10081bdc 0x24 _zPHY_ecsrc_OnRfStartDealSfInt
+ 0x10081c00 0x14 _zPHY_ecsrc_OnRfCloseDealSfInt
+ 0x10081c14 0x37 _zPHY_ecsrc_OnReset
+ 0x10081c4b 0x4e _zPHY_ecsrc_OnCellSearchReq
+ 0x10081c99 0x39 _zPHY_ecsrc_InitOnCellSearchReq
+ 0x10081cd2 0xae _zPHY_ecsrc_CtrlAppointSearchPbchTimeEvent
+ 0x10081d80 0x52 _zPHY_ecsrc_CtrlAppointSearchTimeEvent
+ 0x10081dd2 0x2a _zPHY_ecsrc_CtrlAppointSearchPbchEndEvent
+ 0x10081dfc 0xd _zPHY_ecsrc_AppointCellSearchType
+ 0x10081e09 0x17 _zPHY_ecsrc_NeibCellSearchType
+ 0x10081e20 0x99 _zPHY_ecsrc_IdleOnCellSearchReq
+ 0x10081eb9 0x16 _zPHY_ecsrc_SlaveOnCellSearchReq
+ 0x10081ecf 0x1a _zPHY_ecsrc_OnCtrlIniSearchCnf
+ 0x10081ee9 0x19 _zPHY_ecsrc_OnTimeDelayInt
+ 0x10081f02 0x19 _zPHY_ecsrc_OnSssUpdateCounterCnf
+ 0x10081f1b 0xd _zPHY_ecsrc_OnIniMeasTimeEvent
+ 0x10081f28 0x1c _zPHY_ecsrc_OnAbortCellSearchReq
+ 0x10081f44 0x27 _zPHY_ecsrc_OnCommonConfigReq
+ 0x10081f6b 0x4e _zPHY_ecsrc_OnMeasConfigReq
+ 0x10081fb9 0x132 _zPHY_ecsrc_SaveMask
+ 0x100820eb 0x98 _zPHY_ecsrc_OnMeasMaskSetReq
+ 0x10082183 0x30 _zPHY_ecsrc_OnAbortMeasReq
+ 0x100821b3 0x3e _zPHY_ecsrc_OnChangeMeasPeriodReq
+ 0x100821f1 0x11 _zPHY_ecsrc_OnIdleInterRfChangeFinishedEvent
+ 0x10082202 0x39 _zPHY_ecsrc_OnIratMeasGapConfigReq
+ 0x1008223b 0x21 _zPHY_ecsrc_OnFreqScanReq
+ 0x1008225c 0x3b _zPHY_ecsrc_InitOnFreqScanReq
+ 0x10082297 0x53 _zPHY_ecsrc_IdleOnFreqScanReq
+ 0x100822ea 0x27 _zPHY_ecsrc_SlaveOnFreqScanReq
+ 0x10082311 0x21 _zPHY_ecsrc_OnCtrlSearchFreqScanCnf
+ 0x10082332 0x1c _zPHY_ecsrc_OnHandoverReq
+ 0x1008234e 0x10 _zPHY_ecsrc_OnPlmnResumeSrvCellTpu
+ 0x1008235e 0x2c _zPHY_ecsrc_OnPlmnPeriodTpuIntIn
+ 0x1008238a 0x26 _zPHY_ecsrc_FreqScanSubFrameIntDelay
+ 0x100823b0 0x47 _zPHY_ecsrc_RunningCheck
+ 0x100823f7 0x8d _zPHY_ecsrc_OnArfcnListInfo
+ 0x10082484 0x47 _zPHY_amt_Lte_Set_EarfcnInfo
+ 0x100824cb 0xf _L1e_csrc_HandoverSuccPro
+ 0x100824da 0x1b _zPHY_ecsrc_StartProc
+ 0x100824f5 0x15f _zPHY_ecsrc_ComProc
+ 0x10082654 0x15 _zPHY_ecsrc_InitProc
+ 0x10082669 0x6f _zPHY_ecsrc_IdleProc
+ 0x100826d8 0x21 _zPHY_ecsrc_ConnProc
+ 0x100826f9 0x91 _zPHY_ecsrc_SlaveProc
+ 0x1008278a 0x5b _zPHY_ecsrc_Ctrl
+ 0x100827e5 0x48 _zPHY_ecsrc_ThreadEntry
+ 0x1008282d 0xc8 _zEcsrc_PreEvent
+ 0x100828f5 0x38 _zEcsrc_OnEvent
+ 0x1008292d 0x52 _zPHY_ecsrc_ReadSnr
+ 0x1008297f 0xd6 _zPHY_ecsrc_ReadSearctT
+ 0x10082a55 0x1e _zPHY_ecsrc_ReadIntraSearctT
+ 0x10082a73 0x1e _zPHY_ecsrc_ReadSpeedSearctT
+ 0x10082a91 0x1d _zPHY_ecsrc_ReadCfoUpdateT
+ 0x10082aae 0x2a _zPHY_ecsrc_GetDestTime
+ 0x10082ad8 0x1c _zPHY_ecsrc_CalDestTimeOffset
+ 0x10082af4 0x19 _zPHY_ecsrc_GetNonHighPrioFreqNum
+ 0x10082b0d 0x19 _zPHY_ecsrc_GetHighPrioFreqNum
+ 0x10082b26 0x13 _zPHY_ecsrc_GetReportNum
+ 0x10082b39 0x31 _zPHY_ecsrc_NeedIntraSearchStep
+ 0x10082b6a 0x2e _zPHY_ecsrc_NeedIntraSearchStepNormal
+ 0x10082b98 0x45 _zPHY_ecsrc_NeedIntraSearch
+ 0x10082bdd 0x22 _zPHY_ecsrc_IsNonHighPrioWorkDrx
+ 0x10082bff 0xaa _zPHY_ecsrc_NeedWork
+ 0x10082ca9 0x54 _zPHY_ecsrc_CalcInitDrxNum
+ 0x10082cfd 0x7f _zPHY_ecsrc_CalcWorkDrxNum
+ 0x10082d7c 0x22 _zPHY_ecsrc_NeedInterSearch
+ 0x10082d9e 0x9 _zPHY_ecsrc_NeedInterMeas
+ 0x10082da7 0x52 _zPHY_ecsrc_NeedIntraMeas
+ 0x10082df9 0x1c _zPHY_ecsrc_FreqIndexAcc
+ 0x10082e15 0x37 _zPHY_ecsrc_IsLastFreqInDrx
+ 0x10082e4c 0x72 _L1e_csrc_SRCellRank
+ 0x10082ebe 0x9a _L1e_csrc_SaveSRCellInfo
+ 0x10082f58 0x52 _L1e_csrc_SetSRCellInfo
+ 0x10082faa 0x121 _L1e_csrc_GetMobileCxtFlag
+ 0x100830cb 0x49 _zPHY_ecsrc_CtrlIdleIntraMeasEndEventNew
+ 0x10083114 0x37 _zPHY_ecsrc_GetReportDrxNum
+ 0x1008314b 0x2 _zPHY_ecsrc_EverTrue
+ 0x1008314d 0x10 _zPHY_ecsrc_StartDelayTimer
+ 0x1008315d 0x9 _zPHY_ecsrc_WaitEvent
+ 0x10083166 0x1d _zPHY_ecsrc_SchedInit
+ 0x10083183 0x20 _zPHY_ecsrc_SchedStop
+ 0x100831a3 0x8 _zPHY_ecsrc_SchedStart
+ 0x100831ab 0x15 _zPHY_ecsrc_NeedWorkInReportPeriod
+ 0x100831c0 0xbc _zPHY_ecsrc_OnStartPi
+ 0x1008327c 0x63 _zPHY_ecsrc_OnEndPi
+ 0x100832df 0x9b _zPHY_ecsrc_ReportOneFreq
+ 0x1008337a 0x7c _zPHY_ecsrc_ReportPreValue
+ 0x100833f6 0x49 _zPHY_ecsrc_ReportInra
+ 0x1008343f 0x57 _zPHY_ecsrc_DoReportIner
+ 0x10083496 0x11 _zPHY_ecsrc_ReportInter
+ 0x100834a7 0x12 _zPHY_ecsrc_OneFreqModeWork
+ 0x100834b9 0x1a _zPHY_ecsrc_OneFreqIntraWork
+ 0x100834d3 0x27 _zPHY_ecsrc_IntraSearchInLowSnr
+ 0x100834fa 0x36 _zPHY_ecsrc_FixedStrongSearch
+ 0x10083530 0x8 _zPHY_ecsrc_GetFixedStrongSearchFlag
+ 0x10083538 0x30 _zPHY_ecsrc_NeedSearchInLowSnr
+ 0x10083568 0x25 _zPHY_ecsrc_NeedSearchInRA
+ 0x1008358d 0x14 _zPHY_ecsrc_OneFreqInterWork
+ 0x100835a1 0x11 _zPHY_ecsrc_GerFreqNumPerDrx
+ 0x100835b2 0x5c _zPHY_ecsrc_NextInterFreqInDrx
+ 0x1008360e 0x23 _zPHY_ecsrc_IntraWorkInDrx
+ 0x10083631 0x20 _zPHY_ecsrc_InterFinishInDrx
+ 0x10083651 0x35 _zPHY_ecsrc_RecordInterDoneInDrx
+ 0x10083686 0x65 _zPHY_ecsrc_InterSchedInitPerDrx
+ 0x100836eb 0x9b _zPHY_ecsrc_GetIntraSearchTime
+ 0x10083786 0x2e _zPHY_ecsrc_GetInterSearchTime
+ 0x100837b4 0x7f _zPHY_ecsrc_GetIntraMeasTime
+ 0x10083833 0xa1 _zPHY_ecsrc_GetInterMeasTime
+ 0x100838d4 0x4d _zPHY_ecsrc_GetIntraWorkTime
+ 0x10083921 0x15 _zPHY_ecsrc_GetInterWorkTime
+ 0x10083936 0x69 _zEcsr_GetWorkTimeInCurDrx
+ 0x1008399f 0x71 _zPHY_ecsrc_ChangeMeasMode
+ 0x10083a10 0x36 _zPHY_ecsrc_IntraMeasStart
+ 0x10083a46 0x3 _zPHY_ecsrc_InterMeasStart
+ 0x10083a49 0x15 _zPHY_ecsrc_IntraSearchStart
+ 0x10083a5e 0xd _zPHY_ecsrc_SetIntraWorkTime
+ 0x10083a6b 0x1e _zPHY_ecsrc_SetInterWorkTime
+ 0x10083a89 0x12 _zPHY_ecsrc_ServCellStart
+ 0x10083a9b 0x26 _zPHY_ecsrc_SearchInMeasConfig
+ 0x10083ac1 0x21 _zPHY_ecsrc_ReadIndexInSchedContext
+ 0x10083ae2 0x21 _zPHY_ecsrc_IntraFreqStart
+ 0x10083b03 0x12b _zPHY_ecsrc_InterFreqStart
+ 0x10083c2e 0xb4 _zPHY_ecsrc_OneFreqStart
+ 0x10083ce2 0x26 _zPHY_ecsrc_NeedSchedInter
+ 0x10083d08 0x1 _zPHY_ecsrc_BeforeInter
+ 0x10083d09 0x15 _zPHY_ecsrc_BeforeOneFreq
+ 0x10083d1e 0x24 _zPHY_ecsrc_NeedInitial
+ 0x10083d42 0x49 _zPHY_ecsrc_ChangeMeasPeriodIdle
+ 0x10083d8b 0x32 _zPHY_ecsrc_ReportNoInactiveTime
+ 0x10083dbd 0x7 _zPHY_ecsrc_NeedAdjustBndFrmCfo
+ 0x10083dc4 0x5e _zPHY_ecsrc_AdjustBndFrmCfo
+ 0x10083e22 0x15 _zPHY_ecsrc_SetShortDrxState
+ 0x10083e37 0x12 _zPHY_ecsrc_CfgRfcRxOffset
+ 0x10083e49 0x2b _zPHY_ecsrc_AdjustSrvTpu
+ 0x10083e74 0x7 _zPHY_ecsrc_BackupCFOFreqOffset
+ 0x10083e7b 0x8 _l1e_csrc_GetDrxCnt
+ 0x10083e83 0x3b _zPHY_ecsrc_DrxReStartSearchMeas
+ 0x10083ebe 0x2a _zPHY_ecsrc_ReadPrio
+ 0x10083ee8 0x85 _zPHY_ecsrc_WakeupPs
+ 0x10083f6d 0x8 _L1e_csrc_GetCurCtx
+ 0x10083f75 0x8 _L1e_csrc_GetMeasBit
+ 0x10083f7d 0x98 _L1e_csrc_TempRead
+ 0x10084015 0x92 _L1e_ecsrc_UpdateBackBchBnd
+ 0x100840a7 0x9 _L1e_csrc_AtZepcgSetLowPower
+ 0x100840b0 0x9 _L1e_csrc_AtZepcgClrLowPower
+ 0x100840b9 0x40 _L1e_csrc_AtZepcgSetPhyCfg
+ 0x100840f9 0x67 _L1e_csrc_GetFreqOffset
+ 0x10084160 0x90 _L1e_csrc_SetDisableAfcReloadFlag
+ 0x100841f0 0x4a _L1e_csrc_SetScanFailNum
+ 0x1008423a 0x95 _L1e_csrc_C0CaliPeriod
+ 0x100842cf 0x87 _L1e_csrc_C0CaliEvalue
+ 0x10084356 0x10b _L1e_csrc_C0Update
+ 0x10084461 0x80 _L1e_csrc_C0CalRsrp
+ 0x100844e1 0x5f _L1e_csrc_C0CalAfc
+ 0x10084540 0x1c _L1e_csrc_C0CaliRestart
+ 0x1008455c 0x16 _L1e_csrc_C0CaliInit
+ 0x10084572 0x13 _L1e_csrc_C0FactorUtcValid
+ 0x10084585 0x6f _L1e_csrc_UtcTimeExpired
+ 0x100845f4 0x65 _L1e_csrc_BackupCurPpm
+ 0x10084659 0x30 _L1e_csrc_GetCurPpmValid
+ 0x10084689 0x44 _L1e_csrc_TempNoChange
+ 0x100846cd 0x33 _L1e_csrc_FindFreqOffsetIndex
+ 0x10084700 0x26 _L1e_csrc_UpdateFtErrorList
+ .text 0x10084726 0x212 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ 0x10084726 0x212 _zPHY_emc_ProPhyStateCtrl
+ .text 0x10084938 0xb29 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ 0x10084938 0x7 _zPHY_ecsrc_SatAdd
+ 0x1008493f 0x9 _zPHY_ecsrc_SatSub
+ 0x10084948 0x18 _zPHY_ecsrc_CellDatabaseReset
+ 0x10084960 0x2b _zPHY_ecsrc_GetCellInfo
+ 0x1008498b 0x48 _zPHY_ecsrc_GetAddCell
+ 0x100849d3 0x61 _zPHY_ecsrc_DeleteCell
+ 0x10084a34 0x4d _zPHY_ecsrc_DeleteOldCell
+ 0x10084a81 0x69 _zPHY_ecsrc_DeleteAllCell
+ 0x10084aea 0x4d _zPHY_ecsrc_DeleteNoCfgCell
+ 0x10084b37 0x1a _L1e_Csrc_IsServcell
+ 0x10084b51 0x13 _L1e_Csrc_IsServcellEarfcn
+ 0x10084b64 0x42 _zPHY_ecsrc_FindCell
+ 0x10084ba6 0x29 _zPHY_ecsrc_ClearOtherCell
+ 0x10084bcf 0x12 _zPHY_ecsrc_FindServCell
+ 0x10084be1 0x4e _zPHY_ecsrc_CtrlICPWriteMeasPriority
+ 0x10084c2f 0x9e _zPHY_ecsrc_SearchAddCellToDatabase
+ 0x10084ccd 0x8d _zPHY_ecsrc_CtrlRefreshDataBase
+ 0x10084d5a 0x54 _zPHY_ecsrc_CtrlUpdateBoundary
+ 0x10084dae 0x49 _zPHY_ecsrc_AdjustCellAge
+ 0x10084df7 0x3a _zPHY_ecsrc_CtrlGetStrongestCell
+ 0x10084e31 0xc _zPHY_ecsrc_ScellDatabaseReset
+ 0x10084e3d 0x44 _zPHY_ecsrc_CtrlCellDatabaseAging
+ 0x10084e81 0x2a _zPHY_ecsrc_ClearSearchNewCellFlag
+ 0x10084eab 0x2e _zPHY_ecsrc_ClearAppointCellFlag
+ 0x10084ed9 0x23 _zPHY_ecsrc_ClearValidCellFlag
+ 0x10084efc 0x22 _zEcsrc_FindFreq
+ 0x10084f1e 0x13 _zEcsrc_IsIcp
+ 0x10084f31 0x40 _zEcsrc_GetMeasBand
+ 0x10084f71 0x19 _zEcsrc_GetMeasTimes
+ 0x10084f8a 0x2c _zPHY_ecsrc_ClearFreqInfo
+ 0x10084fb6 0x34 _zPHY_ecsrc_ClearNoCfgFreqInfo
+ 0x10084fea 0x1f _zPHY_ecsrc_FindFreqInfo
+ 0x10085009 0x60 _zPHY_ecsrc_ExChangeFreqInfo
+ 0x10085069 0x9e _zPHY_ecsrc_SaveFreqInfo
+ 0x10085107 0x4d _zPHY_ecsrc_ReadRsrpCaliInfo
+ 0x10085154 0x4a _zPHY_ecsrc_UpdateTimeOffset
+ 0x1008519e 0x41 _zPHY_ecsrc_RecoverTimeOffset
+ 0x100851df 0x48 _zPHY_ecsrc_ChangeTimeOffset
+ 0x10085227 0x23 _zPHY_ecsrc_ReadTimeOffset
+ 0x1008524a 0x1e _zPHY_ecsrc_GetCellNum
+ 0x10085268 0xb _L1e_Csrc_UpdateServCell
+ 0x10085273 0x10 _L1e_Csrc_ServCellChange
+ 0x10085283 0xc _L1e_Csrc_ChangeNeiConfigFlag
+ 0x1008528f 0x7e _zPHY_ecsrc_DealSrvBndFrmCfo
+ 0x1008530d 0x25 _L1e_csrc_SetMeasState
+ 0x10085332 0x87 _zPHY_ecsrc_GetMeasCell
+ 0x100853b9 0x4b _zPHY_ecsrc_GetMeasCellNum
+ 0x10085404 0x12 _zPHY_ecsrc_GetFddBufferMode
+ 0x10085416 0x1e _zPHY_ecsrc_GetIndexInFreqMeasMode
+ 0x10085434 0x11 _zPHY_ecsrc_GetMeasAge
+ 0x10085445 0x1c _zPHY_ecsrc_GetFreqOffset
+ .text 0x10085461 0x2c26 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x10085461 0xb _zPHY_ecsrc_CtrlShiftSlaveFunState
+ 0x1008546c 0x14 _zPHY_ecsrc_CtrlShiftSlaveSynState
+ 0x10085480 0xa _zPHY_ecsrc_MulmSetRfWorkSet
+ 0x1008548a 0x65 _zPHY_ecsrc_MulmCfgRFCModem7510
+ 0x100854ef 0x5f _zPHY_ecsrc_MulmRegRFStartClose
+ 0x1008554e 0x121 _zPHY_ecsrc_MulmIratIdlePeriodRepProcess7510
+ 0x1008566f 0x44 _zEcsr_UpdateSiReadState
+ 0x100856b3 0x35 _zPHY_ecsrc_MulmCtrlSetMode
+ 0x100856e8 0xa3 _zPHY_ecsrc_MulmSlaveReset
+ 0x1008578b 0x14 _zPHY_ecsrc_MulmFreqListConfigProcess
+ 0x1008579f 0x60 _L1e_Mulm_ReadSearchT
+ 0x100857ff 0x58 _L1e_Mulm_NeedSearch
+ 0x10085857 0x34 _L1e_Mulm_NeedMeas
+ 0x1008588b 0x47 _zPHY_ecsrc_MulmIratMeasScheduleProcess
+ 0x100858d2 0x3c _zPHY_ecsrc_MulmIratAddMeasReport
+ 0x1008590e 0x77 _zPHY_ecsrc_MulmMeasReset
+ 0x10085985 0xe5 _zPHY_ecsrc_MulmIratMeasConfigProcess
+ 0x10085a6a 0x72 _zPHY_ecsrc_MulmReportFreqMeasResult
+ 0x10085adc 0x5d _zPHY_ecsrc_MulmIratMeasResultHandle
+ 0x10085b39 0x9 _zPHY_ecsrc_MulmIratResetMeasCnt
+ 0x10085b42 0x8d _zPHY_ecsrc_MulmIratMeasReportIntHandle
+ 0x10085bcf 0xaf _zPHY_ecsrc_MulmIratMeasFilter
+ 0x10085c7e 0x88 _zPHY_ecsrc_MulmIratFreqFilter
+ 0x10085d06 0x72 _zPHY_ecsrc_MulmIratUpdateMeasInd
+ 0x10085d78 0x34 _zPHY_ecsrc_MulmIratUpdateFreqReport
+ 0x10085dac 0x40 _zPHY_ecsrc_MulmIratSetFilterFact
+ 0x10085dec 0x2a _zPHY_ecsrc_MulmIratReadPrio
+ 0x10085e16 0x55 _zPHY_ecsrc_MulmIratSearchMeasureStartSchedule
+ 0x10085e6b 0x17 _zPHY_ecsrc_MulmSlaveCfgRfcMeas1Offset7510
+ 0x10085e82 0x37 _zPHY_ecsrc_MulmSlaveGapStartOffsetCfg7510
+ 0x10085eb9 0x43 _zPHY_ecsrc_MulmSlaveGapEndOffsetCfg7510
+ 0x10085efc 0x36 _zPHY_ecsrc_MulmRegTpuSingleEvent
+ 0x10085f32 0x63 _zPHY_ecsrc_MulmGetGapType
+ 0x10085f95 0x28 _zPHY_ecsrc_MulmRegTpuEvent
+ 0x10085fbd 0xed _zPHY_ecsrc_MulmIratGapSchedFlow
+ 0x100860aa 0x62 _zPHY_ecsrc_ReRegistGapConfigDelag
+ 0x1008610c 0x62 _zPHY_ecsrc_MulmIratGapSchedFlowProtect
+ 0x1008616e 0x56 _zPHY_ecsrc_MulmBlackCellFilter
+ 0x100861c4 0x60 _zPHY_ecsrs_MulmRemainTimeInGap
+ 0x10086224 0x2d _zPHY_ecsrs_MulmProtectTimeBeforeGap
+ 0x10086251 0x1a _zPHY_ecsrc_MulmCalMeasTime
+ 0x1008626b 0x5b _zPHY_ecsrc_MulmCalSearchTime
+ 0x100862c6 0x104 _zPHY_ecsrc_MulmTpuCnf
+ 0x100863ca 0x13 _zPHY_ecsrc_MulmCsr2TpuUpdateCounterCnfHandle
+ 0x100863dd 0x4a _zPHY_ecsrc_MulmSlavePlmnSearchStart
+ 0x10086427 0x2a _zPHY_ecsrc_MulmSlavePlmnSearchFinHandle
+ 0x10086451 0x42 _zPHY_ecsrc_MulmSlavePlmnMeasureTimerIntHandle
+ 0x10086493 0x2e _zPHY_ecsrc_MulmSlavePlmnAbortCellSearchHandle
+ 0x100864c1 0x45 _zPHY_ecsrs_MulmPlmnSib1InGap
+ 0x10086506 0x45 _zPHY_ecsrc_MulmRegNotSynSubFrameInt
+ 0x1008654b 0x2c _zPHY_ecsrc_MulmRegCsrmSfInt
+ 0x10086577 0xaa _zPHY_ecsrc_MulmIratGapStartTpuIntHandle
+ 0x10086621 0x20 _zPHY_ecsrc_MulmUnRegistSearchMeasInt
+ 0x10086641 0x42 _zPHY_ecsrc_MulmIratGapEndTpuIntHandle
+ 0x10086683 0x50 _zPHY_ecsrc_MulmSlaveAbortGapProtectTimerEnable
+ 0x100866d3 0x48 _zPHY_ecsrc_MulmIratMeasDoneHandle
+ 0x1008671b 0x6e _zPHY_ecsrc_MulmIratAbortGapHandle
+ 0x10086789 0x68 _zPHY_ecsrc_MulmIratAbortGapProtectTimerHandle
+ 0x100867f1 0x97 _zPHY_ecsrs_MulmIratGapPositionCheck
+ 0x10086888 0x27 _zPHY_ecsrs_MulmGapCoverTime
+ 0x100868af 0x42 _zPHY_ecsrm_MulmPbchStartCheck
+ 0x100868f1 0x27 _zPHY_ecsrs_MulmEnableRfcEventTable
+ 0x10086918 0x26 _zPHY_ecsrs_Mulm6MSRfcMeas1GapOffsetCfg
+ 0x1008693e 0x64 _zPHY_ecsrs_MulmRfOpenNo
+ 0x100869a2 0x49 _zPHY_ecsrs_MulmConfigSynState
+ 0x100869eb 0x56 _zPHY_ecsrs_MulmEnableRF
+ 0x10086a41 0x45 _zPHY_emc_MulmCsrRfStartDeal
+ 0x10086a86 0x62 _zPHY_emc_MulmCsrRfEndDeal
+ 0x10086ae8 0x20 _zPHY_emc_DealRFCloseEvent
+ 0x10086b08 0x2d _zPHY_ecsrc_CtrlMulmDbAging
+ 0x10086b35 0xf _zPHY_ecsrc_CtrlSetMulmSlaveSearchMeasAgeInfor
+ 0x10086b44 0x97 _zPHY_ecsrc_CtrlMulmRefreshDataBase
+ 0x10086bdb 0x50 _zPHY_ecsrs_MulmTpuAdjCheckTime
+ 0x10086c2b 0x2f _zPHY_ecsrs_MulmIcpPssBoundryAdj
+ 0x10086c5a 0x1a _zPHY_ecsrs_MulmPssTpuCnf
+ 0x10086c74 0x46 _zPHY_ecsrs_MulmIsPssWorkTime
+ 0x10086cba 0xa0 _zPHY_ecsrs_MulmGetPssHwStartTime
+ 0x10086d5a 0x53 _zPHY_ecsrs_MulmPssCfg
+ 0x10086dad 0xb _zPHY_ecsrs_MulmPssConfig
+ 0x10086db8 0x16 _zPHY_ecsrs_MulmPssGapCoverTime
+ 0x10086dce 0x68 _zPHY_ecsrc_MulmGetValidCellFrameBoundry7510
+ 0x10086e36 0x3f _zPHY_ecsrc_MulmTpuAdjPro
+ 0x10086e75 0x27 _zPHY_ecsrc_MulmBoundryAdj
+ 0x10086e9c 0x7f _zPHY_ecsrs_MulmCheckTpuAdj
+ 0x10086f1b 0x28 _zPHY_ecsrs_MulmStartTpuAdj
+ 0x10086f43 0xf3 _zPHY_ecsrc_MulmIratSearchStartSchedule7510
+ 0x10087036 0x56 _zPHY_emc_MulmSlaveMeasureReportProtect
+ 0x1008708c 0x190 _zPHY_emc_MulmSlaveMeasureFlow
+ 0x1008721c 0x7 _zPHY_ecsrs_MulmIratFSPssGapPositionCheck
+ 0x10087223 0x17 _zPHY_ecsrs_MulmIratCheckGapTime
+ 0x1008723a 0x3d _zPHY_ecsrs_MulmIratPssTimeCheck
+ 0x10087277 0x4b _zPHY_ecsrs_MulmIratSssGapPositionCheck
+ 0x100872c2 0x39 _zPHY_ecsrs_MulmAgcStable
+ 0x100872fb 0x15 _L1e_mulm_CfoAccNum
+ 0x10087310 0x87 _zPHY_ecsrs_MulmCfoConfig
+ 0x10087397 0x1e _zPHY_ecsrs_MulmSssCfg
+ 0x100873b5 0x8b _zPHY_ecsrs_MulmIsTddSssWorkTime
+ 0x10087440 0x18 _zPHY_ecsrs_MulmStartICSPSubFrameInt
+ 0x10087458 0x13 _zPHY_ecsrs_MulmStartSynSearchSubFrameInt
+ 0x1008746b 0x40 _zPHY_ecsrs_MulmGapCoverTime7510
+ 0x100874ab 0x136 _zPHY_ecsrs_MulmIsFddSssWorkTime
+ 0x100875e1 0x1d _zPHY_ecsrs_MulmGetMeasBaseTime
+ 0x100875fe 0x154 _zPHY_ecsrs_MulmCfoCheckTime
+ 0x10087752 0xa9 _zPHY_ecsrs_MulmIsValidTime
+ 0x100877fb 0xfd _zPHY_ecsrs_MulmCheckOpenTime
+ 0x100878f8 0xb3 _zPHY_ecsrm_MulmBuffCheckOpenTimePeriod
+ 0x100879ab 0x5a _zPHY_ecsrs_MulmGapCoverCheck
+ 0x10087a05 0x47 _zPHY_ecsrs_MulmGapCoverBufferCheck
+ 0x10087a4c 0x14 _zPHY_ecsrs_MulmIsShortGap
+ 0x10087a60 0x16 _zPHY_ecsrs_MulmGetFreqIndex
+ 0x10087a76 0x2e _zPHY_ecsrc_MulmIratClearPreFilter
+ 0x10087aa4 0x26 _zPHY_ecsrs_AbsModSub
+ 0x10087aca 0xc _zPHY_ecsrs_MulmCsBefore
+ 0x10087ad6 0x26 _zPHY_ecsrs_MulmCsNeedCs
+ 0x10087afc 0xc _zPHY_ecsrs_MulmCsNeedAgc
+ 0x10087b08 0x37 _zPHY_ecsrs_MulmCsBeforeAgc
+ 0x10087b3f 0xb _zPHY_ecsrs_MulmCsIsOnAgc
+ 0x10087b4a 0x1c _zPHY_ecsrs_MulmCsAgcProc
+ 0x10087b66 0x8 _zPHY_ecsrs_MulmCsAgcProcEnd
+ 0x10087b6e 0xb _zPHY_ecsrs_MulmCsNeedPss
+ 0x10087b79 0x2d _zPHY_ecsrs_MulmCsBeforePss
+ 0x10087ba6 0x18 _zPHY_ecsrs_MulmCsIsOnPss
+ 0x10087bbe 0x41 _zPHY_ecsrs_MulmCsPssProc
+ 0x10087bff 0x43 _zPHY_ecsrs_MulmCsPssProcEnd
+ 0x10087c42 0x14 _zPHY_ecsrs_MulmCsNeedTpuAdj1
+ 0x10087c56 0xc _zPHY_ecsrs_MulmCsNeedTpuAdj
+ 0x10087c62 0xc _zPHY_ecsrs_MulmCsTpuAdjProc
+ 0x10087c6e 0x1a _zPHY_ecsrs_MulmCsTpuAdjProc2
+ 0x10087c88 0xe _zPHY_ecsrs_MulmCsTpuCheck
+ 0x10087c96 0xc _zPHY_ecsrs_MulmCsNeedCfo
+ 0x10087ca2 0x15 _zPHY_ecsrs_MulmCsBeforeCfo
+ 0x10087cb7 0x25 _zPHY_ecsrs_MulmCsBeforeCfoOnce
+ 0x10087cdc 0x20 _zPHY_ecsrs_MulmCsIsOnCfo
+ 0x10087cfc 0x1d _zPHY_ecsrs_MulmCsNeedMoreCfo
+ 0x10087d19 0x30 _zPHY_ecsrs_MulmCsCfoProc
+ 0x10087d49 0x4a _zPHY_ecsrs_MulmCsCfoOnceProcEnd
+ 0x10087d93 0x8 _zPHY_ecsrs_MulmCsCfoProcEnd
+ 0x10087d9b 0x31 _zPHY_ecsrs_MulmLteCordicConfig
+ 0x10087dcc 0x12 _zPHY_ecsrs_MulmGetLteCordicValue
+ 0x10087dde 0xc _zPHY_ecsr_MulmCordicAdjust
+ 0x10087dea 0x5a _zPHY_ecsr_MulmToLteCfo
+ 0x10087e44 0x8 _zPHY_ecsr_MulmReadCordicValue
+ 0x10087e4c 0x8 _zPHY_ecsr_MulmWriteCordicValue
+ 0x10087e54 0xc _zPHY_ecsrs_MulmCsNeedSss
+ 0x10087e60 0x28 _zPHY_ecsrs_MulmCsBeforeSss
+ 0x10087e88 0x29 _zPHY_ecsrs_MulmCsIsOnSss
+ 0x10087eb1 0x18 _zPHY_ecsrs_MulmIsSssWorkTime
+ 0x10087ec9 0x47 _zPHY_ecsrs_MulmCsSssProc
+ 0x10087f10 0x50 _zPHY_ecsrs_MulmCsSssProcEnd
+ 0x10087f60 0x75 _zPHY_ecsrs_MulmCsProEnd
+ 0x10087fd5 0x8 _zPHY_ecsrc_MulmSetRfState
+ 0x10087fdd 0x25 _zPHY_ecsrc_MulmSchedCheck
+ 0x10088002 0x15 _zPHY_ecsrs_MulmCheckReadTime
+ 0x10088017 0x66 _zPHY_ecsrs_MulmIsSssSchedSubFrm
+ 0x1008807d 0xa _zPHY_ecsrs_Wait
+ .text 0x10088087 0xf36 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x10088087 0x1a _zPHY_ecsrc_InitCellSearchProc
+ 0x100880a1 0x1c _zPHY_ecsrc_IdleCellSearchProc
+ 0x100880bd 0x4d _zPHY_ecsrc_SetCellSearchCnf
+ 0x1008810a 0x7c _zPHY_ecsrc_InitAppointedCS
+ 0x10088186 0x16 _zPHY_ecsrc_InitNotAppointedCS
+ 0x1008819c 0x46 _zPHY_ecsrc_CtrlSssUpdateProcess
+ 0x100881e2 0x42 _zPHY_ecsrc_ReSearchOrReportCell
+ 0x10088224 0x37 _zPHY_ecsrc_SetInitMeasTime
+ 0x1008825b 0x6b _zPHY_ecsrc_CtrlICPTimeEvent
+ 0x100882c6 0x3f _zPHY_ecsrc_CtrlICPTpuAdjust
+ 0x10088305 0xaf _zPHY_ecsrc_CtrlICPMeasTimeEvent
+ 0x100883b4 0x3c _zPHY_ecsrc_SortCellSearchCnf
+ 0x100883f0 0x4a _zPHY_ecsrc_SetReportCellList
+ 0x1008843a 0x99 _zPHY_ecsrc_CtrlICPReportResult
+ 0x100884d3 0xc2 _zPHY_ecsrc_CtrlIcpBchHandle
+ 0x10088595 0x4f _zPHY_ecsrc_CtrlBchDecodeEvent
+ 0x100885e4 0x48 _zPHY_ecsrc_CtrlIcpReportNoCell
+ 0x1008862c 0x62 _zPHY_ecsrc_CtrlIcpTimeEndEvent
+ 0x1008868e 0x29 _zPHY_ecsrc_CfgSynTable
+ 0x100886b7 0x36 _zPHY_ecsrc_ReConstructRxPara
+ 0x100886ed 0x16 _zPHY_ecsrc_ConfirmRxPara
+ 0x10088703 0x35 _zPHY_ecsrc_PlmnBackupSrvCell
+ 0x10088738 0x86 _zPHY_ecsrc_PlmnResumeDlRfcEnableEvent
+ 0x100887be 0xcc _zPHY_ecsrc_PlmnPhyResultReport
+ 0x1008888a 0x54 _zPHY_ecsrc_FreqScanResultReportHandle
+ 0x100888de 0x43 _zPHY_ecsrc_PlmnResumeSrvCellTPU
+ 0x10088921 0x3b _zPHY_ecsrc_PlmnCurTime2PiTimeDistance
+ 0x1008895c 0x10 _zPHY_ecsrc_PlmnHasEnoughTime
+ 0x1008896c 0x30 _zPHY_ecsrc_PlmnProcessPeriodicalTpuIntIn
+ 0x1008899c 0x24 _zPHY_ecsrc_PlmnResumeSrvCellNew
+ 0x100889c0 0x31 _zPHY_ecsrc_PlmnSearchResultHandleNew
+ 0x100889f1 0x37 _zPHY_ecsrc_PlmnFreqScanReqPro
+ 0x10088a28 0x15 _zPHY_ecsrc_PlmnCellSearchReqPro
+ 0x10088a3d 0x72 _zPHY_ecsrc_PlmnPeriodTpuInPro
+ 0x10088aaf 0x33 _L1e_csrc_CalcProTime
+ 0x10088ae2 0x1d _zPHY_ecsrc_PlmnGetPhaseMinTime
+ 0x10088aff 0xa2 _zPHY_ecsrc_PlmnBackupAfc
+ 0x10088ba1 0x1c _zPHY_ecsrc_PlmnResumeAgcAFc
+ 0x10088bbd 0xf _zPHY_ecsrc_PlmnPhasePro
+ 0x10088bcc 0x4a _zPHY_ecsrc_SearchPhaseCheck
+ 0x10088c16 0xa _zPHY_ecsrc_PlmnReadPhase
+ 0x10088c20 0xf _zPHY_ecsrc_PlmnPhaseShift
+ 0x10088c2f 0x3c _zPHY_ecsrc_PlmnPhaseContinue
+ 0x10088c6b 0x28 _zPHY_ecsrc_SearchDone
+ 0x10088c93 0x38 _zPHY_ecsrc_SendCellSearchReq
+ 0x10088ccb 0x9 _zPHY_ecsrc_RestartCellSearch
+ 0x10088cd4 0xd4 _zPHY_ecsrc_CtrlAbortICPProcess
+ 0x10088da8 0x35 _zPHY_ecsrc_BchCellInfoBak
+ 0x10088ddd 0x155 _l1e_SchedCsrcGetOverlapInfo
+ 0x10088f32 0x53 _zPHY_ecsrc_ProWriteBch2CsrDb
+ 0x10088f85 0x38 _zPHY_ecsrc_ProBackBchInfo
+ .text 0x10088fbd 0x379 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ 0x10088fbd 0x35 _CheckThread
+ 0x10088ff2 0x6b _NextStep
+ 0x1008905d 0x33 _RunProc
+ 0x10089090 0x12 _RunFun0
+ 0x100890a2 0x14 _RunFun0P1
+ 0x100890b6 0xc _RunFun1
+ 0x100890c2 0x15 _RunOpt
+ 0x100890d7 0x4c _RunWhile
+ 0x10089123 0x27 _RunEnd
+ 0x1008914a 0x1c _RunDo
+ 0x10089166 0x43 _RunWhile1
+ 0x100891a9 0x15 _RunLoop0
+ 0x100891be 0x15 _RunLoop1
+ 0x100891d3 0x25 _RunReturnIf
+ 0x100891f8 0x8b _DispatchStep
+ 0x10089283 0x26 _RunSync
+ 0x100892a9 0x4c _EventHandlerOnce
+ 0x100892f5 0x16 _EventHandler
+ 0x1008930b 0x2b _StartProc
+ .text 0x10089336 0x1ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ 0x10089336 0xc _L1e_SchedMbmsInit
+ 0x10089342 0x48 _L1e_SchedMbmsProcMsg
+ 0x1008938a 0x20 _L1e_SchedMbmsGenMbsfnSfBmp
+ 0x100893aa 0xe3 _L1e_SchedMbmsGenAllocSfBmp
+ 0x1008948d 0xd _L1e_SchedMbmsGetNextTimeInfo
+ 0x1008949a 0x31 _L1e_SchedMbmsProcMchRecv
+ 0x100894cb 0xb _L1e_SchedMbmsGetMbsfnInd
+ 0x100894d6 0xb _L1e_SchedMbmsSetMbsfnFlag
+ 0x100894e1 0xb _L1e_SchedMbmsSetMbmsFlag
+ 0x100894ec 0xd _L1e_SchedMbmsGetMbsfnFlag
+ 0x100894f9 0xf _L1e_SchedMbmsGetMbmsFlag
+ 0x10089508 0x2 _L1e_SchedMBmsGetMbsfnAllocNum
+ 0x1008950a 0xd _L1e_SchedMbmsGetAreaIndex
+ 0x10089517 0xd _L1e_SchedMbmsGetNonMbsfnLen
+ 0x10089524 0x11 _L1e_SchedMBmsGetConfigNum
+ .text 0x10089535 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x10089535 0x44 _zPHY_DrxPreSyncStartCtrl
+ 0x10089579 0x1f1 _zPHY_emc_ProDrxSchedFlow
+ 0x1008976a 0x97 _zPHY_emc_DrxInactivityTimerCtrl
+ 0x10089801 0x73 _zPHY_emc_DrxOnDurationTimerCtrl
+ 0x10089874 0x128 _zPHY_emc_DrxRttTimerAndDlHarqRetranTimerCtrl
+ 0x1008999c 0xf9 _zPHY_emc_DrxUlHarqCtrl
+ 0x10089a95 0x31 _zPHY_emc_ProDrxTpuEventSchedFlow
+ 0x10089ac6 0x88 _zPHY_emc_DrxCalcOndurationTimerStartTime
+ 0x10089b4e 0x64 _zPHY_emc_ProDrxCallBackFunction
+ 0x10089bb2 0x62 _zPHY_emc_RegOndurStartEvent
+ 0x10089c14 0x9e _zPHY_emc_RegShortDrxCycleEvent
+ 0x10089cb2 0x64 _zPHY_emc_CurSubFrDRXStateCtrl
+ 0x10089d16 0x1f _zPHY_emc_DRXCompare2Time
+ 0x10089d35 0x65 _zPHY_emc_OnDurationPre2SubFrm
+ 0x10089d9a 0x41 _zPHY_emc_InactivityPre2SubFrm
+ 0x10089ddb 0x9b _zPHY_emc_DlHarqPre2SubFrm
+ 0x10089e76 0x89 _zPHY_emc_UlHarqPhichPre2SubFrm
+ 0x10089eff 0x63 _zPHY_emc_Next2SubFrameDrxStateCtrl
+ 0x10089f62 0x93 _zPHY_emc_ProDrxInitial
+ 0x10089ff5 0xb _zPHY_emc_ChePwrCtrlFlg
+ 0x1008a000 0x90 _Ltel1_GetConnNearestGap
+ 0x1008a090 0x28d _zPHY_emc_DrxPresyncCalc
+ 0x1008a31d 0x4e _zPHY_emc_DrxStateCtrl
+ 0x1008a36b 0xaf _zPHY_emc_DrxCsi_OpenRXCtrl
+ 0x1008a41a 0xa1 _zPHY_emc_DRXProcLpCtrl
+ 0x1008a4bb 0x15a _zPHY_emc_DrxSpsLpCtrl
+ 0x1008a615 0x23 _zPHY_emc_GetDrxCloseRfState
+ 0x1008a638 0x162 _zPHY_emc_DRXCalOpenRFTime
+ 0x1008a79a 0x84 _zPHY_emc_DRXSleepJudge
+ 0x1008a81e 0x75 _zPHY_emc_DrxParallelSleepCtrl
+ 0x1008a893 0x9d _zPHY_emc_DrxParallelFlowLog
+ 0x1008a930 0x21 _zPHY_emc_DrxParallelFlowCtrl
+ .text 0x1008a951 0x3f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x1008a951 0x7 _zPHY_emc_ProRadioLink_GetFIUpdateInd
+ 0x1008a958 0x7 _zPHY_emc_ProRadioLink_SetFIUpdateInd
+ 0x1008a95f 0x4e _zPHY_emc_ProRadioLink_ParaGetInDrx
+ 0x1008a9ad 0x1e _zPHY_emc_ProRadioLink_THInit
+ 0x1008a9cb 0x28 _zPHY_emc_ProRadioLink_THFilterInFI
+ 0x1008a9f3 0x60 _zPHY_emc_ProRadioLink_GetFinalTH
+ 0x1008aa53 0x52 _zPHY_emc_ProRadioLink_DrxFilter
+ 0x1008aaa5 0xa2 _zPHY_emc_ProRadioLink_DrxFlow
+ 0x1008ab47 0x60 _zPHY_emc_ProRadioLink_NoDrxFilter
+ 0x1008aba7 0x45 _zPHY_emc_ProRadioLink_StateSwitch
+ 0x1008abec 0xb7 _zPHY_emc_ProRadioLink_MainPro
+ 0x1008aca3 0xa6 _zPHY_emc_ProRadioLinkFlow
+ .text 0x1008ad49 0x2e13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x1008ad49 0x40 _zPHY_amt_Lte_PrintMsgLog
+ 0x1008ad89 0x4c _zPHY_AMT_Rfc_WriteRfFrontReg
+ 0x1008add5 0x66 _zPHY_AMT_erfc_SetCurrentBandAntGPIO
+ 0x1008ae3b 0xc1 _zPHY_AMT_erfc_SetCurrentBandPaModeGPIO
+ 0x1008aefc 0x17 _zPHY_AMT_RFC_110_RxOn
+ 0x1008af13 0x16 _zPHY_AMT_RFC_110_RxOff
+ 0x1008af29 0x17 _zPHY_AMT_RFC_110_TxOn
+ 0x1008af40 0x16 _zPHY_AMT_RFC_110_TxOff
+ 0x1008af56 0x16 _zPHY_AMT_RFC_120_RxOn
+ 0x1008af6c 0x16 _zPHY_AMT_RFC_120_RxOff
+ 0x1008af82 0x16 _zPHY_AMT_RFC_120_TxOn
+ 0x1008af98 0x16 _zPHY_AMT_RFC_120_TxOff
+ 0x1008afae 0x17 _zPHY_AMT_RFC_RXENABLE_On
+ 0x1008afc5 0x16 _zPHY_AMT_RFC_RXENABLE_Off
+ 0x1008afdb 0x17 _zPHY_AMT_RFC_TXENABLE_On
+ 0x1008aff2 0x16 _zPHY_AMT_RFC_TXENABLE_Off
+ 0x1008b008 0xf _zPHY_AMT_RFC_110_AfcSet
+ 0x1008b017 0x1 _zPHY_AMT_RFC_110_Xo_AfcSet
+ 0x1008b018 0x22 _zPHY_AMT_RFC_120_DCIQSet
+ 0x1008b03a 0x42 _zPHY_AMT_RFC_110_TempDacGet
+ 0x1008b07c 0x42 _zPHY_AMT_RFC_110_Xo_TempDacGet
+ 0x1008b0be 0x1d _zPHY_AMT_RFC_110_BandWidthModeGet
+ 0x1008b0db 0xa1 _zPHY_AMT_RFC_110_TxFreqSet
+ 0x1008b17c 0x35 _zPHY_AMT_RFC_110_RegTxCfg
+ 0x1008b1b1 0x24 _zPHY_AMT_RFC_120_RegTxCfg
+ 0x1008b1d5 0x36 _zPHY_AMT_RFC_110_RegRxCfg
+ 0x1008b20b 0x30 _zPHY_AMT_RFC_120_RegRxCfg
+ 0x1008b23b 0x28 _zPHY_AMT_RFC_ZTERF_TxApcSet
+ 0x1008b263 0x33 _zPHY_AMT_RFC_ZTERF_Tx2Idle
+ 0x1008b296 0x33 _zPHY_AMT_RFC_ZTERF_Rx2Idle
+ 0x1008b2c9 0x70 _zPHY_AMT_RFC_ZTERF_ToTx
+ 0x1008b339 0x70 _zPHY_AMT_RFC_ZTERF_ToRx
+ 0x1008b3a9 0x13 _zPHY_AMT_RFC_ZTERF_ToIdle
+ 0x1008b3bc 0xd _zPHY_amt_Lte_GetCarrierMode
+ 0x1008b3c9 0x1f _zPHY_amt_Lte_SetCarrierMode
+ 0x1008b3e8 0xdc _zPHY_amt_Lte_ChangeMode
+ 0x1008b4c4 0x15 _zPHY_amt_Lte_TxParaUpdate
+ 0x1008b4d9 0xc7 _zPHY_amt_Lte_ServCellFreqUpdate
+ 0x1008b5a0 0x135 _zPHY_amt_Lte_CellSyncProc
+ 0x1008b6d5 0xd1 _zPHY_amt_Lte_MprDeterm
+ 0x1008b7a6 0xa8 _zPHY_amt_Lte_RfcTxDataBaseSet
+ 0x1008b84e 0x48 _zPHY_amt_Lte_FDTTransTxVgaCtrl
+ 0x1008b896 0x226 _zPHY_amt_Lte_FDT_PAVGAVOL_Update
+ 0x1008babc 0x1f _zPHY_amt_Lte_FDTTxOffsetSet
+ 0x1008badb 0x12e _zPHY_amt_Lte_FDTRfcDataBaseSet
+ 0x1008bc09 0x1c _zPHY_amt_Lte_FDTRfcDataBaseClear
+ 0x1008bc25 0xe _zPHY_amt_Lte_FDTGetAgcGain
+ 0x1008bc33 0x7c _zPHY_amt_Lte_FDTSaveAgcGain
+ 0x1008bcaf 0xf6 _zPHY_amt_Lte_FDTControl
+ 0x1008bda5 0x2 _zPHY_amt_Lte_FDTGetAGC
+ 0x1008bda7 0xb1 _zPHY_amt_Lte_FDTStart
+ 0x1008be58 0x12 _zPHY_amt_Lte_FDTCellSyncProc
+ 0x1008be6a 0x20 _zPHY_amt_Lte_NSTCellSyncProc
+ 0x1008be8a 0x37 _zPHY_amt_Lte_NSTCellSyncSuccessRsp
+ 0x1008bec1 0x43 _zPHY_amt_Lte_NSTStartBler
+ 0x1008bf04 0xed _zPHY_amt_Lte_NSTGetBler
+ 0x1008bff1 0x32 _zPHY_amt_Lte_NSTStart
+ 0x1008c023 0x22 _zPHY_amt_Lte_NSTCirCfoStop
+ 0x1008c045 0x39 _zPHY_amt_Lte_NSTChangeFreq
+ 0x1008c07e 0x15b _zPHY_amt_Lte_NSTControl
+ 0x1008c1d9 0x13 _zPHY_amt_Lte_FSTCellSyncProc
+ 0x1008c1ec 0x89 _zPHY_amt_Lte_FSTStart
+ 0x1008c275 0xc9 _zPHY_amt_Lte_FSTRfcDataBaseSet
+ 0x1008c33e 0xda _zPHY_amt_Lte_FSTPowerUpdate
+ 0x1008c418 0xc0 _zPHY_amt_Lte_FSTSaveBlerAndRsrp
+ 0x1008c4d8 0xf6 _zPHY_amt_Lte_FSTControl
+ 0x1008c5ce 0x29 _zPHY_amt_Lte_Control
+ 0x1008c5f7 0x294 _zPHY_amt_Lte_Tx_Init_Power
+ 0x1008c88b 0x1a4 _zPHY_amt_Lte_Tx_Init_RFC
+ 0x1008ca2f 0x7a _zPHY_amt_Lte_Tx_Init_MC
+ 0x1008caa9 0x7a _zPHY_amt_Lte_Tx_Init_MC_Power
+ 0x1008cb23 0x6e _zPHY_amt_Lte_Close_Rfc
+ 0x1008cb91 0x51 _zPHY_amt_Lte_Tx_Close_MC
+ 0x1008cbe2 0x3c _zPHY_amt_Lte_TxFreq_RFC
+ 0x1008cc1e 0x1d _zPHY_amt_Lte_TxPaMode_RFC
+ 0x1008cc3b 0x4c _zPHY_amt_Lte_TxAPC_RFC
+ 0x1008cc87 0x3a _zPHY_amt_Lte_AFC_RFC
+ 0x1008ccc1 0x38 _zPHY_amt_Lte_XO_AFC_RFC
+ 0x1008ccf9 0x159 _zPHY_amt_Lte_Rx_Init_RFC
+ 0x1008ce52 0x1a _zPHY_amt_Lte_SetSyncTimer
+ 0x1008ce6c 0x4f _zPHY_amt_Lte_Cell_Search
+ 0x1008cebb 0xa3 _zPHY_amt_Lte_CommMsg_Stub
+ 0x1008cf5e 0x3d _zPHY_amt_Lte_CommMsg_Send
+ 0x1008cf9b 0x19f _zPHY_amt_Lte_DediMsg_Stub
+ 0x1008d13a 0x33 _zPHY_amt_Lte_DediMsg_Send
+ 0x1008d16d 0x26b _zPHY_amt_Lte_Sync_Process
+ 0x1008d3d8 0x74 _zPHY_amt_Lte_Rx_Init_MC
+ 0x1008d44c 0x71 _zPHY_amt_Lte_Rx_Close_MC
+ 0x1008d4bd 0x1b _zPHY_amt_Lte_RxFreq_RFC
+ 0x1008d4d8 0x2 _zPHY_amt_Lte_RxLNAMode_RFC
+ 0x1008d4da 0x2 _zPHY_amt_Lte_RxVGA_RFC
+ 0x1008d4dc 0x3c _zPHY_amt_Lte_Get_Rsrp
+ 0x1008d518 0xe _zPHY_amt_Lte_Get_TempDAC
+ 0x1008d526 0xe _zPHY_amt_Lte_Get_Xo_TempDAC
+ 0x1008d534 0xe _zPHY_amt_Lte_Set_AfcData
+ 0x1008d542 0x25 _zPHY_amt_Lte_Tx_DcOffset
+ 0x1008d567 0xbc _zPHY_amt_Lte_CellSearchResult
+ 0x1008d623 0x9b _zPHY_amt_Lte_CalcServCellAntAMT
+ 0x1008d6be 0x49 _zPHY_amt_Lte_UpCellSearchResult
+ 0x1008d707 0xf5 _zPHY_amt_Lte_RxAlways_Init
+ 0x1008d7fc 0xa _zPHY_amt_Lte_RxAlways_Close
+ 0x1008d806 0xe _zPHY_amt_Lte_RxAlwaysOpen_GetAgc
+ 0x1008d814 0x76 _zPHY_amt_Lte_RxAlwaysOpen
+ 0x1008d88a 0x2 _zPHY_amt_Lte_RxCwControl
+ 0x1008d88c 0x2d0 _zPHY_amtTool_ThreadEntry
+ .text 0x1008db5c 0x1b39 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ 0x1008db5c 0x4a _zPHY_erapc_InitialProc
+ 0x1008dba6 0x33 _zPHY_erapc_RaParamReset
+ 0x1008dbd9 0xa4 _zPHY_erapc_BiProc
+ 0x1008dc7d 0x106 _zPHY_erapc_RaResourceSelect
+ 0x1008dd83 0x164 _zPHY_erapc_RaResourceSelectFDD
+ 0x1008dee7 0x12d _zPHY_erapc_RaResourceSelectTDD
+ 0x1008e014 0x48 _zPHY_erapc_PreambleGroupSelect
+ 0x1008e05c 0x4f _zPHY_erapc_PreambleSelect
+ 0x1008e0ab 0x1d0 _zPHY_erapc_PreamCycShiftCalc
+ 0x1008e27b 0x12b _zPHY_erapc_KValueCalc
+ 0x1008e3a6 0xb8 _zPHY_erapc_PreambleTransPower
+ 0x1008e45e 0x6f _zPHY_erapc_PcmaxCalc
+ 0x1008e4cd 0x12a _zPHY_erapc_RarMacPduDecode
+ 0x1008e5f7 0x9c _zPHY_erapc_TpuEventDelete
+ 0x1008e693 0x42 _zPHY_erapc_RntiDelete
+ 0x1008e6d5 0x4b _zPHY_erapc_SetRapcState
+ 0x1008e720 0x43 _zPHY_erapc_PreamFormatDetermFDD
+ 0x1008e763 0x3e _zPHY_erapc_PreamFormatDetermTDD
+ 0x1008e7a1 0xff _zPHY_erapc_ResrConfigDetermFDD
+ 0x1008e8a0 0x1e1 _zPHY_erapc_ResrConfigDetermTDD
+ 0x1008ea81 0x8f _zPHY_erapc_NextAvailSFDetermTDD
+ 0x1008eb10 0x67 _zPHY_erapc_NPrbRaCalcTDD
+ 0x1008eb77 0x21 _zPHY_erapc_RandomNumGenerate
+ 0x1008eb98 0xdd _zPHY_erapc_RaRntiCalc
+ 0x1008ec75 0x8f _zPHY_erapc_SendRaCnfMsg
+ 0x1008ed04 0x152 _zPHY_erapc_ConfigSAD
+ 0x1008ee56 0x235 _zPHY_erapc_PreamTransPro
+ 0x1008f08b 0x7a _zPHY_erapc_RaRetransProc
+ 0x1008f105 0x150 _zPHY_erapc_RarDetectedProc
+ 0x1008f255 0x7b _zPHY_erapc_CRntiMsg4Proc
+ 0x1008f2d0 0x79 _zPHY_erapc_CcchSduMsg4Proc
+ 0x1008f349 0x55 _zPHY_erapc_AbortRaProc
+ 0x1008f39e 0x63 _zPHY_erapc_ContenStopProc
+ 0x1008f401 0x3d _zPHY_erapc_GetRapcTpuEventFlag
+ 0x1008f43e 0x37 _zPHY_erapc_SetRapcTpuEventFlag
+ 0x1008f475 0xae _zPHY_erapc_Format4PrachNumCalc
+ 0x1008f523 0xda _zPHY_erapc_GapConflictIndicate
+ 0x1008f5fd 0x94 _zPHY_erapc_Format4PrachNumCalc_ForUla
+ 0x1008f691 0x4 _zPHY_erapc_PrachAntennaSelect
+ .text 0x1008f695 0x5eb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x1008f695 0x283 _zPHY_emc_ProHandover2Module
+ 0x1008f918 0x35d _zPHY_emc_ProHandoverFlow
+ 0x1008fc75 0xb _zPHY_emc_InHandoverProc
+ .text 0x1008fc80 0xd01 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x1008fc80 0x1f9 _zPHY_emc_ProPagingFlow
+ 0x1008fe79 0xf8 _zPHY_L1e_DcxoDelayProc
+ 0x1008ff71 0x8 _zPHY_L1e_GetPreSyncValidInd
+ 0x1008ff79 0x8 _zPHY_L1e_SetPreSyncValidInd
+ 0x1008ff81 0x7 _zPHY_L1e_GetPreSyncAccNum
+ 0x1008ff88 0x39 _zPHY_emc_RegPageCallEvent
+ 0x1008ffc1 0x1f2 _zPHY_emc_CalPagingParam
+ 0x100901b3 0x103 _zPHY_emc_ProPagingCallBackFunction
+ 0x100902b6 0x31 _zPHY_emc_NxtSubFrmIsPage
+ 0x100902e7 0x16 _zPHY_emc_DrxPoLpCtrl
+ 0x100902fd 0x53 _L1e_Page_ReUpdatePoEvt
+ 0x10090350 0xd5 _L1e_SchedGetPreSyncSchdInfo
+ 0x10090425 0x4b _L1e_SchedPreSyncGetIdleWorkTimer
+ 0x10090470 0x8 _L1e_SchedReturnPreSyncWorkTime
+ 0x10090478 0x29 _L1e_SchedPreSyncGetAgcWorkTimer
+ 0x100904a1 0x1b _L1e_SchedPreSyncSetState
+ 0x100904bc 0x7 _L1e_SchedPreSyncGetState
+ 0x100904c3 0xc _L1e_SchedPreSyncSetWorkCnt
+ 0x100904cf 0x12 _L1e_SchedPreSyncIsWorkSn
+ 0x100904e1 0x12 _L1e_SchedPreSyncIsWorkInd
+ 0x100904f3 0x17 _L1e_SchedPreSyncGetRfOpenInd
+ 0x1009050a 0x29 _L1e_SchedPreSyncGetAgcWorkInd
+ 0x10090533 0x24 _L1e_SchedPreSyncGetFssWorkInd
+ 0x10090557 0x2d _L1e_SchedPreSyncGetCfoWorkInd
+ 0x10090584 0x8 _L1e_SchedPreSyncGetFssWorkCnt
+ 0x1009058c 0x8 _L1e_SchedPreSyncGetRfcWorkCnt
+ 0x10090594 0x8 _L1e_SchedPreSyncSetCfgSfnInd
+ 0x1009059c 0x8 _L1e_SchedPreSyncGetCfgSfnInd
+ 0x100905a4 0x8 _L1e_SchedPreSyncGetSfnBmp
+ 0x100905ac 0xa _L1e_SchedPreSyncGetPoMarkSn
+ 0x100905b6 0x2e _L1e_SchedPreSyncGetConnWorkTimer
+ 0x100905e4 0x75 _L1e_SchedPreSyncUpdateStep
+ 0x10090659 0x8 _L1e_SchedPreSyncSetStep
+ 0x10090661 0x8 _L1e_SchedPreSyncGetStep
+ 0x10090669 0x66 _L1e_DbgPreSyncCtrlInfo
+ 0x100906cf 0x7f _L1e_SchedPreSyncCtrl
+ 0x1009074e 0x13b _zPHY_emc_tRxCirPreSyncStart
+ 0x10090889 0xa1 _zPHY_emc_RfcRxColseOperationCheck
+ 0x1009092a 0x57 _zPHY_emc_ProLpcSleepSchd
+ .text 0x10090981 0x670 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ 0x10090981 0x71 _zPHY_ecscMeas_LogMeasConfigReq
+ 0x100909f2 0x35 _zPHY_ecscMeas_LogMeasBitMask
+ 0x10090a27 0x71 _zPHY_ecscMeas_LogMeasAgeThrold
+ 0x10090a98 0x5e _zPHY_ecscMeas_LogServCellResult
+ 0x10090af6 0x3f _zPHY_ecscMeas_LogPccMeasResult
+ 0x10090b35 0x78 _zPHY_ecscMeas_LogInterCellInfo
+ 0x10090bad 0x47 _zPHY_ecsrc_LogInterMeasInd
+ 0x10090bf4 0x23 _zPHY_ecscMeas_LogConnInterReport
+ 0x10090c17 0x4f _zPHY_ecscMeas_LogSccIntraMeasFilter
+ 0x10090c66 0x1a _zPHY_ecscMeas_LogSccIntraMeasFilter2
+ 0x10090c80 0x2e _zPHY_ecscMeas_LogIntraFilter2
+ 0x10090cae 0x19 _zPHY_ecscMeas_LogInterMeasFilter
+ 0x10090cc7 0x1f _zPHY_ecscMeas_LogIntraRSSI
+ 0x10090ce6 0x16 _zPHY_ecscMeas_LogUpdateInterReportFail1
+ 0x10090cfc 0x47 _zPHY_ecscMeas_LogFilterInterReport3
+ 0x10090d43 0x33 _zPHY_ecscMeas_LogPCCIntraMeasCell
+ 0x10090d76 0x43 _zPHY_ecscMeas_LogPCCIntraMeasCell4
+ 0x10090db9 0x21 _zPHY_ecscMeas_LogSCCIntraMeasCell
+ 0x10090dda 0x85 _zPHY_ecscMeas_LogSCCIntraMeasCell2
+ 0x10090e5f 0x76 _zPHY_ecscMeas_LogSCCIntraMeasCell4
+ 0x10090ed5 0x41 _zPHY_ecscMeas_LogFilterIntraDebug
+ 0x10090f16 0x53 _zPHY_ecscMeas_LogFilterIntraDebug2
+ 0x10090f69 0x4f _zPHY_ecscMeas_LogFilterInterDebug
+ 0x10090fb8 0x39 _zPHY_ecscMeas_LogCsrSnr
+ .text 0x10090ff1 0x6f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ 0x10090ff1 0x6f _L1e_LogDlDlsDciDetInfo
+ .text 0x10091060 0x9e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ 0x10091060 0x31 _zPHY_ecsc_LogMibReqCellInfo
+ 0x10091091 0x17 _zPHY_ecsc_LogEarfchTable
+ 0x100910a8 0x2f _zPHY_ecsc_LogTpuEventMark
+ 0x100910d7 0x59 _zPHY_ecsc_LogTimeOffsetPerfreq
+ 0x10091130 0x25 _L1e_csrc_LogDrxRefreshGapCnt
+ 0x10091155 0xa0 _L1e_csrc_LogCnnDrxSchedule
+ 0x100911f5 0x15 _zPHY_ecsc_LogRecv_REL_REQ
+ 0x1009120a 0x29 _zPHY_ecsc_LogRecv_StopInterSearchMeas
+ 0x10091233 0x15 _zPHY_ecsc_LogReportMEASErr
+ 0x10091248 0x48 _zPHY_ecsc_LogGAPTime
+ 0x10091290 0x2e _zPHY_ecsc_LogInterFreq
+ 0x100912be 0x2e _zPHY_ecsc_LogHandover
+ 0x100912ec 0x24 _zPHY_ecsc_LogRecv_MULM_IRAT_IDLE_PERIOD_REP_REQ
+ 0x10091310 0x20 _zPHY_ecsc_LogRecv_FREQ_LIST_CONFIG_REQ
+ 0x10091330 0x1d _zPHY_ecsc_LogRecv_IRAT_MEAS_CONFIG_REQ
+ 0x1009134d 0x1d _zPHY_ecsc_LogRecv_IRAT_MEASURE_REPORT_INT
+ 0x1009136a 0x15 _zPHY_ecsc_LogAbortGap
+ 0x1009137f 0x3f _zPHY_ecsc_LogREG_IRAT_GAP_CONFIG_DELAY_INT
+ 0x100913be 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_REQ
+ 0x100913ec 0x15 _zPHY_ecsc_LogTPUAdjusting
+ 0x10091401 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_DELAY_INT
+ 0x1009142f 0x15 _zPHY_ecsc_LogRecv_RF_START_DEAL_PRE2SFINT
+ 0x10091444 0x15 _zPHY_ecsc_LogRecv_RF_CLOSE_DEAL_PRE2SFINT
+ 0x10091459 0x15 _zPHY_ecsc_LogRecv_RESET_REQ
+ 0x1009146e 0x2a _zPHY_ecsc_LogRecv_CELL_SEARCH_REQ
+ 0x10091498 0x15 _zPHY_ecsc_LogRecv_ABORT_CELL_SEARCH_REQ
+ 0x100914ad 0x21 _zPHY_ecsc_LogRecv_COMMON_CONFIG_REQ
+ 0x100914ce 0x15 _zPHY_ecsc_LogRecv_ABORT_MEAS_REQ
+ 0x100914e3 0x73 _zPHY_ecsc_LogRecv_PI_START_REQ
+ 0x10091556 0x15 _zPHY_ecsc_LogRecv_ONE_FREQ_END_REQ
+ 0x1009156b 0x2e _zPHY_ecsc_LogRecv_IRAT_MEAS_GAP_CONFIG_REQ
+ 0x10091599 0x1d _zPHY_ecsc_LogRecv_FREQ_SCAN_REQ
+ 0x100915b6 0x2b _zPHY_ecsc_LogPhyModeConfig
+ 0x100915e1 0x27 _zPHY_ecsc_LogReportGap
+ 0x10091608 0x3c _L1e_CsrcDb_LogDelCell
+ 0x10091644 0x18 _L1e_csrc_LogReTimeOffset
+ 0x1009165c 0x66 _zPHY_ecscDb_LogCellToDB
+ 0x100916c2 0x3d _zPHY_ecscDb_LogRefreshDB
+ 0x100916ff 0x16 _zPHY_ecscDb_LogUpdateBoundary
+ 0x10091715 0x1e _zPHY_ecsc_LogChangeMeasPeriodIdle
+ 0x10091733 0x39 _zPHY_ecsc_Log_Earfcn_BandInfo
+ 0x1009176c 0x22 _zPHY_ecscMeas_LogSrvCellReslt
+ 0x1009178e 0x1f _zPHY_ecsc_LogStandardOutput
+ 0x100917ad 0x15 _zPHY_ecsc_LogMeasPeriodChgDelay
+ 0x100917c2 0x1d _zPHY_ecsc_LogSibOrRapcConflict
+ 0x100917df 0x1d _zPHY_ecsc_LogSubFreqOffset
+ 0x100917fc 0x16 _zPHY_ecsc_LogEarfcnError
+ 0x10091812 0x76 _L1e_csrc_LogShortDrxInfo
+ 0x10091888 0x15 _L1e_csrc_LogTempComp
+ 0x1009189d 0x15 _L1e_csrc_LogTempRead
+ 0x100918b2 0x1f _L1e_csrc_LogGetFreqOffset
+ 0x100918d1 0x1d _L1e_csrc_LogSetDisableAfcReloadFlag
+ 0x100918ee 0x25 _L1e_csrc_LogC0CaliUpDate
+ 0x10091913 0x21 _L1e_csrc_LogC0CaliPeriod
+ 0x10091934 0x22 _L1e_csrc_LogC0CaliEvalue
+ 0x10091956 0x2f _L1e_csrc_LogC0Update
+ 0x10091985 0x1e _L1e_csrc_LogC0Debug
+ 0x100919a3 0x27 _L1e_csrc_LogC0CalRsrp
+ 0x100919ca 0x1f _L1e_csrc_LogC0CalAfc
+ 0x100919e9 0x21 _L1e_csrc_LogC0UtcTimeExp
+ 0x10091a0a 0x15 _L1e_csrc_LogC0CaliRestart
+ 0x10091a1f 0x21 _L1e_csrc_LogNewUtcError
+ .text 0x10091a40 0x276 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ 0x10091a40 0x4c _zPHY_ecsm_LogMeasHwInfo
+ 0x10091a8c 0x79 _zPHY_ecsmNormal_LogUpdateRes
+ 0x10091b05 0x16 _zPHY_ecsrm_BuffLogSlaveMaxBdySub
+ 0x10091b1b 0x22 _zPHY_ecsrm_LogSetMeasAge
+ 0x10091b3d 0x19 _zPHY_ecsrm_LogBuffFbRelatn
+ 0x10091b56 0x17 _zPHY_ecsrm_LogMeasStartSubFrame
+ 0x10091b6d 0x2b _zPHY_ecsrm_LogBuffCellPara
+ 0x10091b98 0x3f _zPHY_ecsrm_LogBuffCommPara
+ 0x10091bd7 0x2d _zPHY_ecsrm_LogMeasResultRead
+ 0x10091c04 0x18 _zPHY_ecsrm_LogBuffMulmsubf
+ 0x10091c1c 0x29 _zPHY_ecsrm_LogBuffSortCell
+ 0x10091c45 0x27 _zPHY_ecsrm_LogBuffBdyCell
+ 0x10091c6c 0x27 _zPHY_ecsrm_LogBuffwait
+ 0x10091c93 0x23 _zPHY_ecsrm_LogBuffMeasConfig
+ .text 0x10091cb6 0x378 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ 0x10091cb6 0x15 _zPHY_ecsccs_LogRSStart
+ 0x10091ccb 0x27 _zPHY_ecsccs_LogSearchReq
+ 0x10091cf2 0x41 _zPHY_ecsccs_LogCellInfo
+ 0x10091d33 0x1a _zPHY_ecsc_LogRecv_PBCH
+ 0x10091d4d 0x24 _zPHY_ecsccs_LogMeasStart
+ 0x10091d71 0x26 _zPHY_ecsccs_LogSendTPUAdjust
+ 0x10091d97 0x30 _zPHY_ecsccs_LogCellRank
+ 0x10091dc7 0x1d _zPHY_ecsccs_LogNoAppointedCell
+ 0x10091de4 0x42 _zPHY_ecsccs_LogICPReportResultRIGHT
+ 0x10091e26 0x18 _zPHY_ecsccs_LogIcpBchCell
+ 0x10091e3e 0x15 _zPHY_ecsccs_LogNoCell
+ 0x10091e53 0x44 _zPHY_ecsccs_LogStartResumeSrv
+ 0x10091e97 0x4b _zPHY_ecsccs_LogNewPlmnRS_ReportStatus
+ 0x10091ee2 0x29 _zPHY_ecsccs_LogNewPlmnRS_SearchFinished
+ 0x10091f0b 0x1f _zPHY_ecsccs_LogNewPlmnRS_MeasFinished
+ 0x10091f2a 0x3c _zPHY_ecsccs_LogResumeServBCHBoundry
+ 0x10091f66 0x26 _zPHY_ecsccs_LogCurTime2PiTime
+ 0x10091f8c 0x30 _zPHY_ecsccs_LogReg_PLMN_PERIODICAL_TPU_INT
+ 0x10091fbc 0x21 _zPHY_ecsccs_LogRecv_PLMN_SEARCH_TIME_EVENT
+ 0x10091fdd 0x51 _zPHY_ecsccs_LogWriteBch2CsrDb
+ .text 0x1009202e 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ 0x1009202e 0x29 _L1e_LogDlRxMbsfnCirInfo
+ 0x10092057 0x52 _L1e_LogRxMbmsCirAreaInfo
+ 0x100920a9 0x9f _L1e_LogRxCirDataInfo
+ 0x10092148 0x42 _L1e_LogRxMbmsCirSearchInfo
+ 0x1009218a 0x22 _L1e_LogRxBetaInfo
+ 0x100921ac 0x1a _L1e_LogRxCfoCfgInfo
+ .text 0x100921c6 0xb03 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ 0x100921c6 0x17 _zPHY_emulm_LogCsrSlaveStateChange
+ 0x100921dd 0x17 _zPHY_emulm_LogCsrSlaveSYNStateChange
+ 0x100921f4 0x20 _zPHY_emulm_LogCsrcGapStartOffset
+ 0x10092214 0x2c _zPHY_emulm_LogCsrcFreeTimeRep
+ 0x10092240 0x17 _zPHY_emulm_LogCsrcSetModeReq
+ 0x10092257 0x17 _zPHY_emulm_LogCsrcMeasSche
+ 0x1009226e 0x26 _zPHY_emulm_LogCsrcMeasReportProct
+ 0x10092294 0x2f _zPHY_emulm_LogCsrcMeasReportInt
+ 0x100922c3 0x16 _zPHY_emulm_LogMeasNoCell
+ 0x100922d9 0x18 _zPHY_emulm_LogMeasCell
+ 0x100922f1 0x19 _zPHY_emulm_LogMeasNoCellReport
+ 0x1009230a 0x73 _zPHY_emulm_LogMeasRight
+ 0x1009237d 0x16 _zPHY_emulm_LogASynSearch
+ 0x10092393 0x2a _zPHY_emulm_LogGapStartOffset
+ 0x100923bd 0x17 _zPHY_emulm_LogSubFrameOnOff
+ 0x100923d4 0x2a _zPHY_emulm_LogGapEndOffset
+ 0x100923fe 0x56 _zPHY_emulm_LogRegCsrIratGapStart
+ 0x10092454 0x94 _zPHY_emulm_LogRegCsrGapEnd
+ 0x100924e8 0x56 _zPHY_emulm_LogRegCsrRfClose
+ 0x1009253e 0x17 _zPHY_emulm_LogBlackList
+ 0x10092555 0x1c _zPHY_emulm_LogRemainTime
+ 0x10092571 0x20 _zPHY_emulm_LogSynInterSearchMeas
+ 0x10092591 0x22 _zPHY_emulm_LogRegIratPlmnMeas
+ 0x100925b3 0x22 _zPHY_emulm_LogRegSlaveAbortGap
+ 0x100925d5 0x1d _zPHY_emulm_LogIratAbortGap
+ 0x100925f2 0x1d _zPHY_emulm_LogIratMeasDone
+ 0x1009260f 0x1e _zPHY_emulm_LogGapPosition
+ 0x1009262d 0x4d _zPHY_emulm_LogGapTime
+ 0x1009267a 0x4d _zPHY_emulm_LogGapTime1
+ 0x100926c7 0x4d _zPHY_emulm_LogGapTime2
+ 0x10092714 0x17 _zPHY_emulm_LogPbchInGap
+ 0x1009272b 0x28 _zPHY_emulm_LogEnRfcEventTable
+ 0x10092753 0x54 _zPHY_emulm_Log6MSRfcEventTableInGap
+ 0x100927a7 0x39 _zPHY_emulm_LogrRfStartDeal
+ 0x100927e0 0x39 _zPHY_emulm_LogrRfEndDeal
+ 0x10092819 0x36 _zPHY_emulm_LogRefreshDataBase1
+ 0x1009284f 0x18 _zPHY_emulm_LogtpuAdjust
+ 0x10092867 0x18 _zPHY_emulm_LogtpuCantAdjust
+ 0x1009287f 0x29 _zPHY_emulm_LogPssAdjust
+ 0x100928a8 0x15 _zPHY_emulm_LogRecvSlaveAbortGap
+ 0x100928bd 0x15 _zPHY_emulm_LogRecvCsrAbortGap
+ 0x100928d2 0x15 _zPHY_emulm_LogRecvCsrTpuIratGap
+ 0x100928e7 0x15 _zPHY_emulm_LogRecvCsrTpuIratGapStart
+ 0x100928fc 0x65 _zPHY_emulm_LogSlaveMeasureFlow
+ 0x10092961 0x15 _zPHY_emulm_LogRecvCsrTpuIratPlmnMeas
+ 0x10092976 0x15 _zPHY_emulm_LogRecvCsrTpuUpdateCounter
+ 0x1009298b 0x15 _zPHY_emulm_LogCsrcRecvGapEndOffsetCfg
+ 0x100929a0 0x38 _zPHY_emulm_LogCsrcGatValidCellFbInfo
+ 0x100929d8 0x21 _zPHY_emulm_LogCsrcTimeDelayIntEvent
+ 0x100929f9 0x2c _zPHY_emulm_LogCsrcAfterAdjTpu
+ 0x10092a25 0x31 _L1e_Mulm_LogNeedSearchAndMeas
+ 0x10092a56 0x19 _zPHY_emulm_LogCsrcStartEarfcnInfo
+ 0x10092a6f 0x2f _zPHY_emulm_LogCsrcEndEarfcnInfo
+ 0x10092a9e 0x67 _zPHY_emulm_LogCsrcGapAndSssInfo
+ 0x10092b05 0x6a _zPHY_emulm_LogCsrcHbTimeInfo
+ 0x10092b6f 0x2c _zPHY_emulm_LogCsrcSssBufferAndGap
+ 0x10092b9b 0x21 _zPHY_emulm_LogCsrcAgcStart
+ 0x10092bbc 0x39 _zPHY_emulm_LogCsrcSlaveSssProcessInfo
+ 0x10092bf5 0x43 _zPHY_emulm_LogBuffCheckOpenTimePeriod
+ 0x10092c38 0x21 _zPHY_emulm_LogGapCoverBuffCheck
+ 0x10092c59 0x1a _zPHY_emulm_LogMeasFilter
+ 0x10092c73 0x16 _zPHY_emulm_LogUpdateReportFail
+ 0x10092c89 0x26 _zPHY_emulm_LogSetFilterFact
+ 0x10092caf 0x1a _zPHY_emulm_LogGetFilterFact
+ .text 0x10092cc9 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ 0x10092cc9 0x91 _L1e_logCmnMbmsMbsfnSubfListInfo
+ 0x10092d5a 0x8f _L1e_LogCmnMbmsMbsfnAllocInfo
+ .text 0x10092de9 0x10f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ 0x10092de9 0x35 _zPHY_ecsrc_LogSlaveSearchMode
+ 0x10092e1e 0x34 _zPHY_ecsrc_LogRecvUpdateCounterCnf
+ 0x10092e52 0x64 _zPHY_ecsrc_LogPssTpuAdjust3
+ 0x10092eb6 0x26 _zPHY_ecsrc_LogModifyRfCfgInfo
+ 0x10092edc 0x85 _zPHY_ecsrc_LogIsRfOpen
+ 0x10092f61 0x4f _zPHY_ecsrs_LogCommonInfor
+ 0x10092fb0 0x36 _zPHY_ecsrs_LogInterFreqChange
+ 0x10092fe6 0x2e _zPHY_ecsrs_LogGetHwConfigMode
+ 0x10093014 0x34 _zPHY_ecsrs_LogGetReadAndConfigIndex
+ 0x10093048 0x18 _zPHY_ecsrs_LogTFConfirmSearchMode
+ 0x10093060 0x19 _zPHY_ecsrs_LogGetSubTime
+ 0x10093079 0x16 _zPHY_ecsrs_LogSubFrameOnOff
+ 0x1009308f 0xba _zPHY_ecsrs_LogCsPssPro
+ 0x10093149 0x48 _zPHY_ecsrs_LogGetPssStartTime
+ 0x10093191 0x14 _zPHY_ecsrs_LogCsCfoProcEnd
+ 0x100931a5 0x9a _zPHY_ecsrs_LogCsSssPro
+ 0x1009323f 0x3e _zPHY_ecsrpss_LogAdjustPssStartTime
+ 0x1009327d 0x1c _zPHY_ecsrpss_LogUrfcnFreqIdx
+ 0x10093299 0x57 _zPHY_ecsrpss_LogSearchResult
+ 0x100932f0 0x5f _zPHY_ecsrpss_LogPssDb
+ 0x1009334f 0x1b _zPHY_ecsrpss_LogSendRfcOffset
+ 0x1009336a 0x2a _zPHY_ecsrpss_LogCalRedoCfoBoundary
+ 0x10093394 0x2a _zPHY_ecsrpss_LogFilterFinger
+ 0x100933be 0x4d _zPHY_ecsrSss_LogStartFinger
+ 0x1009340b 0x3c _zPHY_ecsrSss_LogStartTime
+ 0x10093447 0x4f _zPHY_ecsrSss_LogStartFingerAll
+ 0x10093496 0x4a _zPHY_ecsrSss_LogSLAVE_HWStart
+ 0x100934e0 0x22 _zPHY_ecsrSss_LogGetRfcEnableInfo
+ 0x10093502 0x27 _zPHY_ecsrSss_LogReadFlagInfor
+ 0x10093529 0xc5 _zPHY_ecsrSss_LogThreshold
+ 0x100935ee 0x5d _zPHY_ecsrSss_LogResultInfo
+ 0x1009364b 0x65 _zPHY_ecsrSss_LogSssFingerReorder
+ 0x100936b0 0x18 _zPHY_ecsrSss_LogAdjustSssFddProc
+ 0x100936c8 0x2e _zPHY_ecsrSss_LogSssState
+ 0x100936f6 0x62 _zPHY_ecsrSss_LogStartFingerAfterSort
+ 0x10093758 0x14 _zPHY_ecsrSss_LogGetSssStartInfo
+ 0x1009376c 0x27 _zPHY_ecsrCfo_LogFreqOffset
+ 0x10093793 0x6a _zPHY_ecsrCfo_LogSLAVE_HWStart
+ 0x100937fd 0x28 _zPHY_ecsrCfo_LogCfoResultMerge
+ 0x10093825 0x41 _zPHY_ecsrIc_LogCellFlag
+ 0x10093866 0x7e _zPHY_ecsrIc_LogCoverInfo
+ 0x100938e4 0x60 _zPHY_ecsrIc_LogCellInfo
+ 0x10093944 0xa9 _zPHY_ecsrs_LogCfgIcFifo
+ 0x100939ed 0x191 _zPHY_ecsrs_LogCfgIc
+ 0x10093b7e 0x136 _zPHY_ecsrs_LogCfgPssHw
+ 0x10093cb4 0x5f _zPHY_ecsrs_LogCfgCfoHw
+ 0x10093d13 0x138 _zPHY_ecsrs_LogCfgSssHw
+ 0x10093e4b 0x20 _zPHY_ecsrSss_LogCheckCfoValid
+ 0x10093e6b 0x2d _L1e_csrs_LogSetFtErrorList
+ 0x10093e98 0x25 _L1e_csrs_LogSetFreqOffsetAge
+ 0x10093ebd 0x1e _L1e_csrs_LogGetFreqOffset
+ .text 0x10093edb 0x239 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ 0x10093edb 0x30 _zPHY_ecsm_LogBlackCell
+ 0x10093f0b 0xba _zPHY_ecsm_LogRfcOpenTime
+ 0x10093fc5 0x4d _zPHY_ecsm_LogRfcOpenTimeFddIdle
+ 0x10094012 0x54 _zPHY_ecsm_LogTDDRfcEventTab
+ 0x10094066 0x14 _zPHY_ecsm_LogRecv_RESET_REQ
+ 0x1009407a 0x32 _zPHY_ecsm_LogMeasStart
+ 0x100940ac 0x14 _zPHY_ecsm_Logrec_MEASRESET
+ 0x100940c0 0x16 _zPHY_ecsm_LogRecv_UnknownMsg
+ 0x100940d6 0x1e _zPHY_ecsm_Buff_LogRfcOpenTime
+ 0x100940f4 0x20 _zPHY_ecsm_LogRfcEventTablength
+ .text 0x10094114 0x3c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ 0x10094114 0xc _zPHY_GetUINT32BitsField
+ 0x10094120 0x27 _zPHY_GetUINT64BitsField
+ 0x10094147 0x1f _zPHY_GetUINT16DivCeilValue
+ 0x10094166 0x22 _zPHY_GetUINT32DivCeilValue
+ 0x10094188 0x28 _zPHY_GetSINT16DivFloorValue
+ 0x100941b0 0x2e _zPHY_GetSINT32DivFloorValue
+ 0x100941de 0x16 _zPHY_BinarySearch
+ 0x100941f4 0x132 _zPHY_Pow2
+ 0x10094326 0x5b _zPHY_Fixpoint2Float
+ 0x10094381 0x88 _zPHY_Float2Fixpoint
+ 0x10094409 0x6c _zPHY_DivRet2Fixpoint7510
+ 0x10094475 0x57 _zPHY_DivRet2Fixpoint
+ 0x100944cc 0x10 _zPHY_LteaDelay
+ .text 0x100944dc 0x60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x100944dc 0x57 _zPHY_setRxMaskFlag
+ 0x10094533 0x9 _zPHY_getRxMaskFlag
+ .text 0x1009453c 0x95 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x1009453c 0x37 _L1l_CmnAssert
+ 0x10094573 0x5a _zPHY_RecvUnknownMsg
+ 0x100945cd 0x4 _zPHY_create_handler
+ .text 0x100945d1 0x28c6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ 0x100945d1 0x2f _zPHY_eula_PucchSrsRelease
+ 0x10094600 0x6d _zPHY_eula_SetSrsScale
+ 0x1009466d 0x58 _zPHY_eula_LtxParas_QDivNRsZcSrs
+ 0x100946c5 0x31f _zPHY_eula_UpdataSrsBGParas_Cell
+ 0x100949e4 0xd0 _zPHY_eula_UpdataSrsBGParas_APSfOffset
+ 0x10094ab4 0x19d _zPHY_eula_UpdataSrsBGParas_APTiming
+ 0x10094c51 0x159 _zPHY_eula_UpdataSrsBGParas_APParaCalc_PTS
+ 0x10094daa 0x29b _zPHY_eula_UpdataSrsBGParas_APParaCalc
+ 0x10095045 0x3d _zPHY_eula_UpdataSrsBGParas_APParaAssign
+ 0x10095082 0x62 _zPHY_eula_UpdataSrsBGParas_AP
+ 0x100950e4 0x2f6 _zPHY_eula_UpdataSrsBGParas_PTiming
+ 0x100953da 0x15a _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc_PTS
+ 0x10095534 0x219 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc
+ 0x1009574d 0x118 _zPHY_eula_UpdataSrsBGParas_PHopParaCalc_PTS
+ 0x10095865 0x27d _zPHY_eula_UpdataSrsBGParas_PHopParaCalc
+ 0x10095ae2 0x6d _zPHY_eula_UpdataSrsBGParas_P
+ 0x10095b4f 0xb2 _zPHY_eula_UpdataSrsBGParas
+ 0x10095c01 0xe4 _zPHY_eula_CommSrsProc
+ 0x10095ce5 0x22e _zPHY_eula_ScheApSrs
+ 0x10095f13 0x27 _zPHY_eula_WipeSrsInRarBasedPusch
+ 0x10095f3a 0x80 _zPHY_eula_DetermineSrsCellSpecStateInPusch
+ 0x10095fba 0xbe _zPHY_eula_ProcConflictOfSrsAndPucchPusch_OneCell
+ 0x10096078 0x50 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell
+ 0x100960c8 0x4d _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschScell
+ 0x10096115 0x86 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_PuschScell
+ 0x1009619b 0x120 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch
+ 0x100962bb 0x136 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_Pucch_PuschScell
+ 0x100963f1 0x12e _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch_PuschScell
+ 0x1009651f 0x2 _zPHY_eula_ProcConflictOfSrsAndPucchPusch
+ 0x10096521 0x5e _zPHY_eula_ScheSrsInPusch_AntMapping
+ 0x1009657f 0x7d _zPHY_eula_ScheSrsInPusch
+ 0x100965fc 0xb1 _zPHY_eula_ProcConflictOfSrsAndPucch_OneCell
+ 0x100966ad 0x2 _zPHY_eula_ProcConflictOfSrsAndPucch
+ 0x100966af 0x1d _zPHY_eula_ProcConflictOfSrsAndDrx
+ 0x100966cc 0x4b _zPHY_eula_ScheSrsInNonPusch
+ 0x10096717 0x4e _zPHY_eula_ProcSrsInDurationMode0
+ 0x10096765 0x4c _zPHY_eula_GetPtsState
+ 0x100967b1 0xbe _zPHY_eula_CalcApSrsParas
+ 0x1009686f 0xbe _zPHY_eula_CalcPNonHopSrsParas
+ 0x1009692d 0x389 _zPHY_eula_CalcPHopSrsParas
+ 0x10096cb6 0x46 _zPHY_eula_CalcSrsParas
+ 0x10096cfc 0x70 _zPHY_eula_InitSrsDB
+ 0x10096d6c 0x4e _zPHY_eula_SrsSrcRelease
+ 0x10096dba 0x18 _zPHY_eula_ClearApSrsSche
+ 0x10096dd2 0xbc _zPHY_eula_CalcnSrs
+ 0x10096e8e 0x9 _zPHY_eula_SrsAntennaSelect
+ .text 0x10096e97 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x10096e97 0x53 _zPHY_edla_GetPhichGrpNum
+ 0x10096eea 0xb _zPHY_edla_GetPhichRegNum
+ 0x10096ef5 0x10b _zPHY_edla_GetNextSubFrmPhichInfo
+ 0x10097000 0x100 _zPHY_edla_UpdateIphichInfo
+ 0x10097100 0x10 _zPHY_edla_GetPhichInfo
+ 0x10097110 0xc9 _zPHY_edla_GetPerPhichSeq
+ 0x100971d9 0x95 _zPHY_edla_GetPerTBPhichSeq
+ 0x1009726e 0x11 _zPHY_edla_GetPhichSeq
+ 0x1009727f 0x23 _zPHY_edla_GetHichSubFreq
+ 0x100972a2 0xbb _zPHY_edla_PhichProc
+ 0x1009735d 0x45 _zPHY_edla_UpdatePhichInfo
+ 0x100973a2 0xb _zPHY_edla_HiValidJudgment
+ .text 0x100973ad 0x1540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x100973ad 0x5d _zPHY_edfe_SupCommonCalAGC
+ 0x1009740a 0x72 _zPHY_edfe_SupFastAGC
+ 0x1009747c 0xd9 _zPHY_edfe_SupNotSyncAGC
+ 0x10097555 0x295 _zPHY_edfe_SupNotSyncAGCAnt0And1
+ 0x100977ea 0x18 _zPHY_edfe_GetAgcReloadVal
+ 0x10097802 0x11 _zPHY_edfe_ConfigAgcReloadVal
+ 0x10097813 0x16 _zPHY_edfe_ACP405AgcGainConfig
+ 0x10097829 0xac _zPHY_edfe_SupAGCLostLockMethod
+ 0x100978d5 0x3f _zPHY_edfe_InitAgcPara
+ 0x10097914 0x1a _zPHY_edfe_ResetAgcCoverJudgePara
+ 0x1009792e 0x24 _zPHY_edfe_InitAgcDagcGain
+ 0x10097952 0x155 _zPHY_edfe_JudgeAgcCoverOpt
+ 0x10097aa7 0x67 _zPHY_edfe_CalcAGCForBandChange
+ 0x10097b0e 0xb8 _zPHY_edfe_GetNextAGCInitGain
+ 0x10097bc6 0x9b _zPHY_edfe_CalcAGCNewMethodAnt
+ 0x10097c61 0x9d _zPHY_edfe_CalcAGCGainNewMethod
+ 0x10097cfe 0x139 _zPHY_edfe_SupHandleAGCOpt
+ 0x10097e37 0x51 _zPHY_edfe_FindOldestPosInAgcGainDB
+ 0x10097e88 0x9 _zPHY_edfe_SupResetAGCLoopOpt
+ 0x10097e91 0xb7 _zPHY_edfe_NotSyncToSyncSetAgc
+ 0x10097f48 0x3d _zPHY_edfe_SyncToNotSyncSetAgc
+ 0x10097f85 0x10b _zPHY_edfe_UpdateSCCAGC
+ 0x10098090 0x12 _zPHY_edfe_CompAgcDBTimeInfo
+ 0x100980a2 0xc7 _zPHY_edfe_IratHandoverAfcManage
+ 0x10098169 0x71 _zPHY_edfe_SupSaveSlaveAfcCtrl
+ 0x100981da 0xfd _zPHY_edfe_IratHandoverCordicManage
+ 0x100982d7 0x8e _zPHY_edfe_IratCordicManage
+ 0x10098365 0x6e _zPHY_edfe_SupSaveSlaveCordicCtrl
+ 0x100983d3 0x77 _zPHY_edfe_FSNewAgcIntHandle
+ 0x1009844a 0x72 _zPHY_edfe_InitSubFramePwrDB
+ 0x100984bc 0x263 _zPHY_edfe_SupSemiStaticAgcNew
+ 0x1009871f 0x26 _zPHY_edfe_MbsfnAgcDbInit
+ 0x10098745 0xc _zPHY_edfe_MbsfnAgcParaConfig
+ 0x10098751 0x9f _zPHY_edfe_SupCalMbsfnRegionAgc
+ 0x100987f0 0xb6 _zPHY_edfe_SupHandleMbsfnAGC
+ 0x100988a6 0x2f _zPHY_edfe_NewMbsfnAGCGainInit
+ 0x100988d5 0x1 _zPHY_edfe_MbsfnAgcCoverJudge
+ 0x100988d6 0x17 _zPHY_edfe_MbsfnAgcGainConfig
+ .text 0x100988ed 0x251 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ 0x100988ed 0x1ae _zPHY_eulpc_SrsPowCalc
+ 0x10098a9b 0xa3 _zPHY_eulpc_SrsPowCtrl
+ .text 0x10098b3e 0x1173 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ 0x10098b3e 0x1 _zPHY_euls_L_Entry
+ 0x10098b3f 0x34c _zPHY_euls_Entry
+ 0x10098e8b 0x2cc _zPHY_euls_TPU_INT1_RARGrantProcess
+ 0x10099157 0x2f8 _zPHY_euls_TPU_INT1_DCIProcess
+ 0x1009944f 0x435 _zPHY_euls_TPU_INT1_Step1_process
+ 0x10099884 0x191 _zPHY_euls_TPU_INT1_Step2_process
+ 0x10099a15 0x8b _zPHY_euls_GetDediCfgParas
+ 0x10099aa0 0x7f _zPHY_euls_GetSCellCfgParas
+ 0x10099b1f 0x80 _zPHY_euls_GetCommCfgParas
+ 0x10099b9f 0x10e _zPHY_euls_GetHandoverCfgParas
+ 0x10099cad 0x4 _zPHY_euls_PuschAntennaSelect
+ .text 0x10099cb1 0x2362 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x10099cb1 0x2c _L1e_FS_SwReset
+ 0x10099cdd 0x16 _L1e_FS_Init
+ 0x10099cf3 0x32 _L1e_FS_FreqScanEnRfcNotSyncTable
+ 0x10099d25 0xb3 _L1e_FS_HandleFreqscanAddSearchResult
+ 0x10099dd8 0x9c _L1e_FS_CalcSssAgcGainCompen
+ 0x10099e74 0xec _L1e_FS_FreqScanAddSearchResultSort
+ 0x10099f60 0x30 _L1e_FS_SetFSResult
+ 0x10099f90 0x110 _L1e_FS_FindFSEarfcnToReport
+ 0x1009a0a0 0x34 _L1e_FS_FindEarfcnForSearch
+ 0x1009a0d4 0x36 _L1e_FS_SendFsCnf
+ 0x1009a10a 0x8f _L1e_FS_BufForSearch
+ 0x1009a199 0x86 _L1e_Fs_CreateList_Band38_Bak
+ 0x1009a21f 0x6c _L1e_Fs_CreateListBak
+ 0x1009a28b 0x6a _L1e_Fs_IsFreqPointValid
+ 0x1009a2f5 0x36 _L1e_Fs_MaxPeakSetZero
+ 0x1009a32b 0x2a _L1e_Fs_GetMaxValue
+ 0x1009a355 0x28 _L1e_Fs_GetMinValue
+ 0x1009a37d 0x1c _L1e_FS_LogNumPrint
+ 0x1009a399 0x33 _L1e_Fs_SetProfileInfo
+ 0x1009a3cc 0x34 _L1e_Fs_DelList
+ 0x1009a400 0x6 _L1e_FS_ClearPssResultList
+ 0x1009a406 0x6 _L1e_FS_ClearMeanPowerResultList
+ 0x1009a40c 0xe _L1e_FS_SetRedoInfo
+ 0x1009a41a 0xf4 _L1e_FS_GetAllGainProfileInfo
+ 0x1009a50e 0x63 _L1e_FS_GetAllProfileInfo
+ 0x1009a571 0xcf _L1e_Fs_GetAllValidFreqPoint
+ 0x1009a640 0x33 _L1e_FS_SetBandInfo
+ 0x1009a673 0xf _L1e_FS_SetSpecialBandInfo
+ 0x1009a682 0x5c _L1e_FS_SetOverLapFreqBand
+ 0x1009a6de 0x1bc _L1e_FS_GenFreqBand
+ 0x1009a89a 0x1e _L1e_FS_CfgRfcNotSyncTable
+ 0x1009a8b8 0x51 _L1e_FS_ReqMsgHandle
+ 0x1009a909 0x13 _L1e_FS_SetFreqPoint
+ 0x1009a91c 0x74 _L1e_FS_InsertPssResult
+ 0x1009a990 0xe3 _L1e_FS_SetIniCsrInfo
+ 0x1009aa73 0xdf _L1e_FS_SetFsRslt
+ 0x1009ab52 0x8b _L1e_FS_ResultSort
+ 0x1009abdd 0x1b _L1e_FS_PlmnPeriodTpuInPro
+ 0x1009abf8 0xd2 _L1e_FS_SetDisctRslt
+ 0x1009acca 0x21 _L1e_FS_SeekToHalfFram
+ 0x1009aceb 0xce _L1e_FS_DoPss
+ 0x1009adb9 0x109 _L1e_FS_PssNext100KFreqPointNoPreCFO
+ 0x1009aec2 0x61 _L1e_FS_PssNext100KFreqPointPreCFO
+ 0x1009af23 0x35 _L1e_FS_PssNext100KFreqPoint
+ 0x1009af58 0x35 _L1e_FS_PssNextAgcGain
+ 0x1009af8d 0x1b _L1e_FS_PssNextProfile
+ 0x1009afa8 0x6c _L1e_FS_InitFreqOffset
+ 0x1009b014 0x49 _L1e_FS_PssNextFreqOffset
+ 0x1009b05d 0x3d _L1e_FS_PreFreqOffset
+ 0x1009b09a 0x136 _L1e_FS_Pss100KResult
+ 0x1009b1d0 0x3d _L1e_FS_DiscreteFreqOffsetLoop
+ 0x1009b20d 0x7f _L1e_FS_PssDisctResult
+ 0x1009b28c 0x1b _L1e_FS_PssProfileLoopStart
+ 0x1009b2a7 0x54 _L1e_FS_NextBand
+ 0x1009b2fb 0x1b _L1e_FS_Pss500KFreqPointLoopStart
+ 0x1009b316 0x31 _L1e_FS_PssNext500KFreqPoint
+ 0x1009b347 0x11 _L1e_FS_GetFsMode
+ 0x1009b358 0x56 _L1e_FS_SetFsTempResult
+ 0x1009b3ae 0xa4 _L1e_FS_FreqScanCellSearch
+ 0x1009b452 0x4a _L1e_FS_PssOneFreqPointStart
+ 0x1009b49c 0x2b _L1e_FS_PssAgcGainLoopStart
+ 0x1009b4c7 0x6a _L1e_FS_Pss100KFreqPointLoopStart
+ 0x1009b531 0xc _L1e_FS_PssNeedOffset
+ 0x1009b53d 0xd _L1e_FS_PssNeedDo100K
+ 0x1009b54a 0xe _L1e_FS_BandLoopStart
+ 0x1009b558 0x2b _L1e_FS_PssSkipPiTime
+ 0x1009b583 0x1e _L1e_FS_PssSeekToSlaveGap
+ 0x1009b5a1 0x23 _L1e_FS_SeekToWorkTime
+ 0x1009b5c4 0x24 _L1e_FS_MpFreqPointLoopStart
+ 0x1009b5e8 0x7b _L1e_FS_SegmentInfoSort
+ 0x1009b663 0x93 _L1e_FS_SetSegmentInfo
+ 0x1009b6f6 0xd3 _L1e_FS_SetSegmentInfoEnd
+ 0x1009b7c9 0xb4 _L1e_FS_FreqSegmentAlorigthm
+ 0x1009b87d 0x61 _L1e_FS_SetBackupFreqOffset
+ 0x1009b8de 0x62 _L1e_FS_FreqSegment
+ 0x1009b940 0x2f _L1e_FS_MpNextFreqPoint
+ 0x1009b96f 0x24 _L1e_FS_MpOneFreqPointStart
+ 0x1009b993 0x40 _L1e_FS_MeanPowerCal
+ 0x1009b9d3 0xc _L1e_FS_MpMethod
+ 0x1009b9df 0x11 _L1e_FS_PssMethod
+ 0x1009b9f0 0x14 _L1e_FS_PLMN
+ 0x1009ba04 0xb _L1e_FS_SetState
+ 0x1009ba0f 0x8 _L1e_FS_GetState
+ 0x1009ba17 0x34 _L1e_FS_MpStart
+ 0x1009ba4b 0x15 _L1e_FS_SetCnfInfo
+ 0x1009ba60 0x68 _L1e_FS_OverlapSegment
+ 0x1009bac8 0x89 _L1e_FS_Report2PsResult
+ 0x1009bb51 0x1b _l1e_FS_MPEnvelopeSort
+ 0x1009bb6c 0x22 _L1e_FS_MpEnvelope
+ 0x1009bb8e 0xa _L1e_FS_PssNeedReDo500K
+ 0x1009bb98 0xc _L1e_FS_Redo500KStart
+ 0x1009bba4 0xf _L1e_FS_PssReDo500KNextProfile
+ 0x1009bbb3 0x1c _L1e_FS_PssReDo500KFpLoopStart
+ 0x1009bbcf 0x43 _L1e_Fs_ReDoGetAllValidFreqPoint
+ 0x1009bc12 0x24 _L1e_FS_PssReDoNext500KFreqPoint
+ 0x1009bc36 0xa _L1e_FS_PssNeedAgc
+ 0x1009bc40 0x9 _L1e_FS_AgcLoopStart
+ 0x1009bc49 0x45 _L1e_FS_AgcNextFreqPoint
+ 0x1009bc8e 0x21 _L1e_FS_BeforeAgc
+ 0x1009bcaf 0x16 _L1e_FS_AddAgcWaitTime
+ 0x1009bcc5 0xc5 _L1e_FS_AgcProc
+ 0x1009bd8a 0x17 _L1e_FS_PssNeedReDo100K
+ 0x1009bda1 0x17 _L1e_FS_IsSerialMode
+ 0x1009bdb8 0x35 _L1e_FS_IsDiscreteMode
+ 0x1009bded 0x2b _L1e_FS_DiscretePssStart
+ 0x1009be18 0x12 _L1e_FS_DiscretePssSnrBackup
+ 0x1009be2a 0xc _L1e_FS_DiscretePssSnrClear
+ 0x1009be36 0x31 _L1e_FS_CheckSearchMode
+ 0x1009be67 0x192 _L1e_FS_CfgRfAndGetMp
+ 0x1009bff9 0x1a _L1e_FS_MpSeekWorkTime
+ .text 0x1009c013 0x345b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x1009c013 0x119 _zPHY_euls_UlGrantReception
+ 0x1009c12c 0x13d _zPHY_euls_HARQEntity
+ 0x1009c269 0x332 _zPHY_euls_HARQProcess
+ 0x1009c59b 0x57 _zPHY_euls_ProInitial
+ 0x1009c5f2 0x31 _zPHY_euls_InitUlHarqIDInHarqDB
+ 0x1009c623 0x141 _zPHY_euls_UlHarqProcessCtrl
+ 0x1009c764 0x364 _zPHY_euls_DecodeDci4
+ 0x1009cac8 0x3bf _zPHY_euls_DecodeDci0
+ 0x1009ce87 0x104 _zPHY_euls_DecodeDci
+ 0x1009cf8b 0x4f _zPHY_euls_DecodePucchTPC
+ 0x1009cfda 0x8f _zPHY_euls_GetMsg3SendSubFrmNo
+ 0x1009d069 0x99 _zPHY_euls_DecodeRARGrant
+ 0x1009d102 0xaf _zPHY_euls_ReportUlGrantParas
+ 0x1009d1b1 0xa8 _zPHY_euls_ReportUlGrantToPS
+ 0x1009d259 0xab _zPHY_euls_CalcLUtrPara
+ 0x1009d304 0x9c _zPHY_euls_CalcLTxPara
+ 0x1009d3a0 0x129 _zPHY_euls_PuschPrmFHType1
+ 0x1009d4c9 0x1df _zPHY_euls_PuschPrmFHType2
+ 0x1009d6a8 0x10 _zPHY_euls_CalcX2Cinit
+ 0x1009d6b8 0x62 _zPHY_euls_CalcNPuschSymb
+ 0x1009d71a 0x148 _zPHY_euls_DecodeModuleCodeSchem
+ 0x1009d862 0x25 _zPHY_euls_Nchoosek
+ 0x1009d887 0x1b5 _zPHY_euls_DecodeRIV_Ratype1
+ 0x1009da3c 0x75 _zPHY_euls_DecodeRIV
+ 0x1009dab1 0x44 _zPHY_euls_GetRbAssignBitWidInDci4
+ 0x1009daf5 0x43 _zPHY_euls_GetRbAssignBitWidInDci0
+ 0x1009db38 0xc9 _zPHY_euls_GetPuschPosByPdcchOrPhichPos
+ 0x1009dc01 0x59 _zPHY_euls_AddMsg4DetectStartEvent
+ 0x1009dc5a 0x5a _zPHY_euls_AddMsg4DetectStopEvent
+ 0x1009dcb4 0x1f _zPHY_euls_AddMsg4DetectWinEvents
+ 0x1009dcd3 0x2d _zPHY_euls_ModifyMsg4DetectWinEvents
+ 0x1009dd00 0xde _zPHY_euls_AddMsg3LtxDealEvent
+ 0x1009ddde 0x49 _zPHY_euls_AddCqiRarSchdEvents
+ 0x1009de27 0x32 _zPHY_euls_InitSPSMode
+ 0x1009de59 0x2b _zPHY_euls_SetupSPSMode
+ 0x1009de84 0x7a _zPHY_euls_SetupSPSMode_DealComnPara
+ 0x1009defe 0x37 _zPHY_euls_SetupSPSMode_CalNextRecurPara
+ 0x1009df35 0x41 _zPHY_euls_JudgeAndDealUlSpsInterval_TDD
+ 0x1009df76 0x2e _zPHY_euls_JudgeAndDealUlSpsInterval_FDD
+ 0x1009dfa4 0x53 _zPHY_euls_ProSPSMode
+ 0x1009dff7 0x53 _zPHY_euls_ProSPSMode_GetUlSfUponCfgGrantSf
+ 0x1009e04a 0x44 _zPHY_euls_ProSPSMode_CalNextRecurPara
+ 0x1009e08e 0x32 _zPHY_euls_ReleaseSPSMode
+ 0x1009e0c0 0x37 _zPHY_euls_ProcessSPSImplicitRelease
+ 0x1009e0f7 0x11 _zPHY_euls_GetDCI0InfoFromConfiguredGrant
+ 0x1009e108 0x11 _zPHY_euls_LastSubframe_SFN
+ 0x1009e119 0xd _zPHY_euls_LastSubframe_Subframe
+ 0x1009e126 0xc _zPHY_euls_JudgeIfBitsIsAll1s_ForSPSRelease
+ 0x1009e132 0x4b _zPHY_euls_TATimerStop
+ 0x1009e17d 0xe _zPHY_euls_MACReset
+ 0x1009e18b 0xa1 _zPHY_euls_Release
+ 0x1009e22c 0x1e _zPHY_euls_ProcDci0PhichSelec
+ 0x1009e24a 0xcd _zPHY_euls_ProcDci0PhichSelec_Assign
+ 0x1009e317 0x46 _zPHY_euls_ProcDci0PhichSelec_Selec
+ 0x1009e35d 0x34 _zPHY_euls_DecodeUlIndexDci0
+ 0x1009e391 0x33 _zPHY_euls_DecodeUlIndexDci4
+ 0x1009e3c4 0x152 _zPHY_euls_AssignDCI0PHICH
+ 0x1009e516 0x5e _zPHY_euls_AssignDCI0_Schedule
+ 0x1009e574 0x26 _zPHY_euls_AssignPHICH_Schedule
+ 0x1009e59a 0x5a _zPHY_euls_SelecDCI0PHICH
+ 0x1009e5f4 0x21 _zPHY_euls_ReleaseDCI0PHICHSelecDB
+ 0x1009e615 0x67 _zPHY_euls_UpdataTTIBundlingHarqID
+ 0x1009e67c 0xa1 _zPHY_euls_DealBundlingGrant
+ 0x1009e71d 0x5a _zPHY_euls_ProcRealPHICH
+ 0x1009e777 0x59 _zPHY_euls_ProcVirtualPHICH
+ 0x1009e7d0 0x7b _zPHY_euls_InitTTIBundlingHarqID
+ 0x1009e84b 0x16 _zPHY_euls_InitTTIBundlingMode
+ 0x1009e861 0xc _zPHY_euls_ReleaseTTIBundlingMode
+ 0x1009e86d 0x6c _zPHY_euls_GetBundlingIDAndHarqID_InULA
+ 0x1009e8d9 0x75 _zPHY_euls_UpdataHarqID
+ 0x1009e94e 0x8 _zPHY_euls_AddAbsSubframe
+ 0x1009e956 0x66 _zPHY_euls_SetDrxFlag
+ 0x1009e9bc 0xcd _zPHY_euls_Dci0SelecAndCsiReport_Proc
+ 0x1009ea89 0x3d3 _zPHY_euls_CalcDciCsiReqFlag
+ 0x1009ee5c 0xf7 _zPHY_euls_CalLutrAndLtx
+ 0x1009ef53 0x16 _zPHY_euls_ScheduleTxChannelType
+ 0x1009ef69 0x7d _zPHY_euls_SchedulePuschAndPucch
+ 0x1009efe6 0x16f _zPHY_euls_DeterminePuschTransType
+ 0x1009f155 0x37 _zPHY_euls_GetPuschHarqAckInfo
+ 0x1009f18c 0x12d _zPHY_euls_DeterminePucchFmt
+ 0x1009f2b9 0x26 _zPHY_euls_GetSysTimeInfo
+ 0x1009f2df 0x75 _zPHY_euls_TM2_ChanExchange
+ 0x1009f354 0x66 _zPHY_euls_PuschPowerControl_Process
+ 0x1009f3ba 0x50 _zPHY_euls_NoPuschPowerControl_Process
+ 0x1009f40a 0x2a _zPHY_euls_GaoTong_Statistics_Process
+ 0x1009f434 0x1 _zPHY_euls_AmtTest_DciStubProcess
+ 0x1009f435 0x39 _zPHY_euls_GetPhichSubFrmNo
+ .text 0x1009f46e 0xa6d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x1009f46e 0x5 _zPHY_ecsrs_GetIdleDrxInterPssWorkTime
+ 0x1009f473 0x165 _zPHY_ecsrs_GetPssStartTime
+ 0x1009f5d8 0x63 _zPHY_ecsrs_AdjustPssStartTime
+ 0x1009f63b 0x14e _zPHY_ecsrs_SetPssFirstStartInfo
+ 0x1009f789 0xca _zPHY_ecsrs_SetPssNotFirstStartInfo
+ 0x1009f853 0x9a _zPHY_ecsrs_GetPssStartInfo
+ 0x1009f8ed 0x4f _zPHY_ecsrs_GetPssReadFlag
+ 0x1009f93c 0x23 _zPHY_ecsrs_ClearPeakList
+ 0x1009f95f 0x1a _zPHY_ecsrs_GetPssData
+ 0x1009f979 0x1c _zPHY_ecsrs_BackupPssFinger
+ 0x1009f995 0xb _zPHY_ecsrs_ClearPssFinger
+ 0x1009f9a0 0xd _zPHY_ecsrs_ClearInnerPeakList
+ 0x1009f9ad 0x5e _zPHY_ecsrs_AdjustPeakTime
+ 0x1009fa0b 0x19 _zPHY_ecsrs_FindFreq
+ 0x1009fa24 0x3d _zPHY_ecsrs_BackupPeakList
+ 0x1009fa61 0xa8 _zPHY_ecsrs_RecoverPeakList
+ 0x1009fb09 0x215 _zPHY_ecsrs_PssResultReadNew
+ 0x1009fd1e 0x63 _zPHY_ecsrs_CalBoundary
+ 0x1009fd81 0x2b _zPHY_ecsrs_CalRedoCfoBoundary
+ 0x1009fdac 0x46 _zPHY_ecsrs_PssAdjustPro
+ 0x1009fdf2 0x28 _zPHY_ecsrs_PssTpuAdjust
+ 0x1009fe1a 0x13 _zPHY_ecsrs_SearchMaxFinger
+ 0x1009fe2d 0xa0 _zPHY_ecsrs_FilterFinger
+ 0x1009fecd 0xe _zPHY_ecsrs_FingerIsValid
+ .text 0x1009fedb 0xc54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ 0x1009fedb 0x69 _zPHY_eula_PuschAckProcess
+ 0x1009ff44 0x177 _zPHY_eula_PuschCsiProcess
+ 0x100a00bb 0xc2 _zPHY_eula_SetPuschScale
+ 0x100a017d 0x1ed _zPHY_eula_PuschAckEncodedLenCalc
+ 0x100a036a 0x2b9 _zPHY_eula_TDD_PuschAckParasCalc
+ 0x100a0623 0x57 _zPHY_eula_TDD_PuschAckParasCalc_UlDl0
+ 0x100a067a 0x86 _zPHY_eula_LtxParas_acNcsPuschDmrs
+ 0x100a0700 0xc7 _zPHY_eula_LtxParas_acUVPuschDmrs
+ 0x100a07c7 0x290 _zPHY_eula_PuschCqiRiEncodedLenCalc
+ 0x100a0a57 0x24 _zPHY_eula_FDD_PuschAckParasCalc
+ 0x100a0a7b 0x8e _zPHY_eula_LtxParas_adwNcsDiv6PuschDmrs
+ 0x100a0b09 0x26 _zPHY_eula_HarqPuschMsg3Stub
+ .text 0x100a0b2f 0x547 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ 0x100a0b2f 0x80 _zPHY_eulpc_PuschPowParasCalc
+ 0x100a0baf 0x119 _zPHY_eulpc_UlsRelativePuscchPowCtrlProc
+ 0x100a0cc8 0x190 _zPHY_eulpc_PuschPowCalcProc
+ 0x100a0e58 0xa9 _zPHY_eulpc_NoPuschPowCalc
+ 0x100a0f01 0xb3 _zPHY_eulpc_DeltaTFCalc
+ 0x100a0fb4 0x89 _zPHY_eulpc_Log10yLinear
+ 0x100a103d 0x39 _zPHY_eulpc_PuschGetCsiInfo
+ .text 0x100a1076 0x540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x100a1076 0x6d _zPHY_edfe_Q8log2
+ 0x100a10e3 0x21 _zPHY_edfe_Logarithm
+ 0x100a1104 0x34 _zPHY_edfe_SupCalLog
+ 0x100a1138 0x8 _zPHY_edfe_SetCsrmDAGCGain
+ 0x100a1140 0x76 _zPHY_edfe_CalcRxDAGCGain
+ 0x100a11b6 0xa2 _zPHY_edfe_HandleRxDAGCGain
+ 0x100a1258 0x57 _zPHY_edfe_FixedRXDagcGain
+ 0x100a12af 0x105 _zPHY_edfe_CalcCsrsDAGCGain
+ 0x100a13b4 0x26 _zPHY_edfe_JudgeRxDagcCover
+ 0x100a13da 0x6d _zPHY_edfe_JudgeCsrsDagcCover
+ 0x100a1447 0xa8 _zPHY_edfe_HandleCsrsDagcInt
+ 0x100a14ef 0x39 _zPHY_edfe_ConfigDagcCalcPara
+ 0x100a1528 0x8e _zPHY_edfe_SetInterCsrsDAGCGain
+ .text 0x100a15b6 0x777 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ 0x100a15b6 0x26 _zAsn1_GetU16Bits
+ 0x100a15dc 0x39 _zAsn1_SetU16Bits
+ 0x100a1615 0x18 _zEasn1p_perGetConVal
+ 0x100a162d 0xc _zEasn1p_perGetDivbVal
+ 0x100a1639 0xa _zEasn1p_perGetIntVal
+ 0x100a1643 0x13 _zEasn1p_perGetBitNum
+ 0x100a1656 0x1a _zEasn1p_perGetRange
+ 0x100a1670 0x67 _zEasn1p_DcGetBitsVal32_Dec
+ 0x100a16d7 0x2 _zEasn1p_DcGetBitsVal32
+ 0x100a16d9 0x13 _zEasn1p_MovePtr_Dec
+ 0x100a16ec 0x1d _zEasn1p_EcSetBitStr_Dec
+ 0x100a1709 0xa2 _zEasn1p_DcGetBitsStr_Dec
+ 0x100a17ab 0x2 _zEasn1p_DcGetBitsStr
+ 0x100a17ad 0x1a _zEasn1p_ChkCodeLen_Dec
+ 0x100a17c7 0x91 _zEasn1p_per_dcOctStr
+ 0x100a1858 0xe5 _zEasn1p_per_dcLen
+ 0x100a193d 0x2f _zEasn1p_per_DcExt
+ 0x100a196c 0x2f _zEasn1p_per_dcIndefiniteLenWholeNum
+ 0x100a199b 0x2e _zEasn1p_per_dcConWholeNum
+ 0x100a19c9 0x8f _zEasn1p_per_dcSequenceOf
+ 0x100a1a58 0x2 _zEasn1p_MovePtr
+ 0x100a1a5a 0x24 _zEasn1p_per_dcPreamble
+ 0x100a1a7e 0x29 _zEasn1p_per_dcPreamble_Sequence
+ 0x100a1aa7 0x47 _zEasn1p_per_dcSmallWholeNum
+ 0x100a1aee 0x46 _zEasn1p_per_dcSkipAllExtData
+ 0x100a1b34 0xb7 _zEasn1p_per_dcInt
+ 0x100a1beb 0x66 _zEasn1p_per_dcChoiceOf
+ 0x100a1c51 0x4a _zEasn1p_per_dcSkipOneExtData
+ 0x100a1c9b 0x92 _zEasn1p_per_dcBitStr
+ .text 0x100a1d2d 0x391 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ 0x100a1d2d 0x55 _zPHY_ecsrs_GetCfoStartTime
+ 0x100a1d82 0x54 _zPHY_ecsrs_SetCfoStartInfoSymMap
+ 0x100a1dd6 0xa1 _zPHY_ecsrs_GetCfoStartInfo
+ 0x100a1e77 0x1e _zPHY_ecsrs_CalPowerNcpEcp
+ 0x100a1e95 0x46 _zPHY_ecsrs_CfoCalcPower
+ 0x100a1edb 0x5e _zPHY_ecsrs_CfoCalcPowerNcpEcp
+ 0x100a1f39 0x5e _zPHY_ecsrs_Codic_atan_FixPoint
+ 0x100a1f97 0x76 _zPHY_ecsrs_CsCfoResultMerge
+ 0x100a200d 0xb1 _zPHY_ecsrs_CfoResultRead
+ .text 0x100a20be 0x189 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ 0x100a20be 0x186 _zPHY_edla_CalcPcfichRegFilePara
+ 0x100a2244 0x3 _zPHY_edla_PcfichProc
+ .text 0x100a2247 0x1107 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ 0x100a2247 0xb7 _zPHY_ecsrs_SssStartFingerSort
+ 0x100a22fe 0xff _zPHY_ecsrs_SssFingerReorder
+ 0x100a23fd 0x49 _zPHY_ecsrs_AdjustSssFddProc
+ 0x100a2446 0x7c _zPHY_ecsrs_GetSssStartFinger
+ 0x100a24c2 0x37 _zPHY_ecsrs_GetNearValidTime
+ 0x100a24f9 0x33 _zPHY_ecsrs_CalSssBufferTime
+ 0x100a252c 0x170 _zPHY_ecsrs_GetSssStartTime
+ 0x100a269c 0x92 _zPHY_ecsrs_GetRfcEnableInfo
+ 0x100a272e 0x3e _zPHY_ecsrs_GetSssStartFg
+ 0x100a276c 0x50 _zPHY_ecsrs_InitSssStartInfo
+ 0x100a27bc 0x8f _zPHY_ecsrs_SetSssFddStartInfoAllProc
+ 0x100a284b 0xb7 _zPHY_ecsrs_SetSssTddStartInfoAllProc
+ 0x100a2902 0x251 _zPHY_ecsrs_SetSssFirstStartInfo
+ 0x100a2b53 0xd9 _zPHY_ecsrs_SetSssComStartInfo
+ 0x100a2c2c 0x4d _zPHY_ecsrs_GetSssStartInfo
+ 0x100a2c79 0x9b _zPHY_ecsrs_GetSssReadFlag
+ 0x100a2d14 0xe2 _zPHY_ecsrs_GetThresholdAndFilterCell
+ 0x100a2df6 0x2ae _zPHY_ecsrs_SssResultReadNew
+ 0x100a30a4 0x1a7 _zPHY_ecsrs_SssResultReadAppointCell
+ 0x100a324b 0x28 _zPHY_ecsrs_RecodCfoInfo
+ 0x100a3273 0x3e _zPHY_ecsrs_CheckCfoValid
+ 0x100a32b1 0x77 _zPHY_ecsrs_SearchForSssHwReset
+ 0x100a3328 0x26 _zPHY_ecsrs_SetSssHwCfgTime
+ .text 0x100a334e 0x1722 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x100a334e 0x5 _zPHY_ecsrs_Init
+ 0x100a3353 0x17 _zPHY_ecsrs_Reset
+ 0x100a336a 0x1 _zPHY_ecsrs_DebugModeInitPara
+ 0x100a336b 0x24 _zPHY_ecsrs_InitCommonInfor
+ 0x100a338f 0x1b _zPHY_ecsrs_DeleteAllSubFrameInt
+ 0x100a33aa 0x8 _zPHY_ecsrs_ResetSynInforTable
+ 0x100a33b2 0x30 _zPHY_ecsrs_GetIntraEarfcnInfo
+ 0x100a33e2 0x1e _zPHY_ecsrs_GetInterEarfcnInfo
+ 0x100a3400 0x1c4 _zPHY_ecsrs_GetCommonInfor
+ 0x100a35c4 0x34 _zPHY_ecsrs_CsRfcConfig
+ 0x100a35f8 0x1a _zPHY_ecsrs_BeforeInitSearch
+ 0x100a3612 0x15 _zPHY_ecsrs_TimeRelation
+ 0x100a3627 0x88 _zPHY_ecsrs_InterFreqChange
+ 0x100a36af 0x62 _zPHY_ecsrs_GetHwConfigMode
+ 0x100a3711 0x112 _zPHY_ecsrs_GetReadAndConfigIndex
+ 0x100a3823 0x1e _zPHY_ecsrs_SetSyncRelation
+ 0x100a3841 0x25 _zPHY_ecsrs_TFConfirmSearchMode
+ 0x100a3866 0x31 _zPHY_ecsrs_SetFilterRange
+ 0x100a3897 0xd _zPHY_ecsrs_OpenSubFrameInt
+ 0x100a38a4 0xd _zPHY_ecsrs_DelSubFrameInt
+ 0x100a38b1 0x8 _zPHY_ecsrs_UpdateInnOffset
+ 0x100a38b9 0x2b _zPHY_ecsrs_ReadSearchResult
+ 0x100a38e4 0x3d _zPHY_ecsrs_GetSubTime
+ 0x100a3921 0x31 _L1e_csrs_InitGloPara
+ 0x100a3952 0x8 _zPHY_ecsrs_OnReset
+ 0x100a395a 0x3 _zPHY_ecsrs_OnSearchMeasReset
+ 0x100a395d 0x48 _zPHY_ecsrs_OnSearchFreqScan
+ 0x100a39a5 0x81 _zPHY_ecsrs_OnSearchMeasStart
+ 0x100a3a26 0x1f _zPHY_ecsrs_OnPssUpdateCounterCnf
+ 0x100a3a45 0x70 _zPHY_ecsrs_OnTimeDelayInt
+ 0x100a3ab5 0xd _zPHY_ecsrs_OnNotSynSubFrameInt
+ 0x100a3ac2 0x57 _zPHY_ecsrs_InitFreqOffset
+ 0x100a3b19 0x9b _L1e_csrs_GetFreqOffset
+ 0x100a3bb4 0x6e _L1e_csrs_SetFtErrorList
+ 0x100a3c22 0x65 _L1e_csrs_SetFreqOffsetAge
+ 0x100a3c87 0x11 _L1e_csrs_GetMaxAgeIndex
+ 0x100a3c98 0x30 _L1e_csrs_NormalTemp
+ 0x100a3cc8 0x89 _zPHY_ecsrs_ModifyRfCfgInfo
+ 0x100a3d51 0x7 _zPHY_ecsrs_setMode
+ 0x100a3d58 0xa _zPHY_ecsrs_IsIntraMode
+ 0x100a3d62 0x86 _zEcsrs_PreEvent
+ 0x100a3de8 0x9e _L1e_csrs_SfProc
+ 0x100a3e86 0x2c _L1e_FS_SfProc
+ 0x100a3eb2 0x2e _zEcsrs_OnEvent
+ 0x100a3ee0 0xb _zPHY_ecsrs_IsInitCs
+ 0x100a3eeb 0x3c _zPHY_ecsrs_CsNeedReCfo
+ 0x100a3f27 0x16 _zPHY_ecsrs_CsNeedReSss
+ 0x100a3f3d 0x67 _zPHY_ecsrs_IsRfOpen
+ 0x100a3fa4 0x14c _zPHY_csr_RfcConfig
+ 0x100a40f0 0x1e _zPHY_ecsrs_IsOptSearch
+ 0x100a410e 0x1a _zPHY_ecsrs_CfoAccNum
+ 0x100a4128 0x1a _zPHY_ecsrs_GetConfigRfFlag
+ 0x100a4142 0x3d _zPHY_ecsrs_GetScheduleFlag
+ 0x100a417f 0x9 _zPHY_ecsrs_CsBeforeAgc
+ 0x100a4188 0x17 _zPHY_ecsrs_CsNeedAgc
+ 0x100a419f 0x6b _zPHY_ecsrs_CsNeedPss
+ 0x100a420a 0x2 _zPHY_ecsrs_CsNeedCfo
+ 0x100a420c 0x82 _zPHY_ecsrs_CsNeedSss
+ 0x100a428e 0x16 _zPHY_ecsrs_CsNeedTempComp
+ 0x100a42a4 0x26 _zPHY_ecsrs_CsIsOnAgc
+ 0x100a42ca 0x37 _zPHY_ecsrs_CsAgcProc
+ 0x100a4301 0x1 _zPHY_ecsrs_CsAgcProcEnd
+ 0x100a4302 0xd _zPHY_ecsrs_CsNeedPssAgain
+ 0x100a430f 0x17 _zPHY_ecsrs_CsBeforePss
+ 0x100a4326 0x1a _zPHY_ecsrs_CsIsOnPss
+ 0x100a4340 0x91 _zPHY_ecsrs_CsGetPssRfCfgInfo
+ 0x100a43d1 0x50 _zPHY_ecsrs_SniffInterFreqChange
+ 0x100a4421 0x13b _zPHY_ecsrs_CsPssProc
+ 0x100a455c 0xda _zPHY_ecsrs_CsPssProcEnd
+ 0x100a4636 0x2a _zPHY_ecsrs_CsNeedMoreCfo
+ 0x100a4660 0x23 _zPHY_ecsrs_CsBeforeCfo
+ 0x100a4683 0x12 _zPHY_ecsrs_CsCfoTpuAdjPro
+ 0x100a4695 0x14 _zPHY_ecsrs_CsIsOnCfo
+ 0x100a46a9 0x6f _zPHY_ecsrs_CsCfoProc
+ 0x100a4718 0x60 _zPHY_ecsrs_CsCfoProcEnd
+ 0x100a4778 0x13 _zPHY_ecsrs_CsBeforeSss
+ 0x100a478b 0x1a _zPHY_ecsrs_CsIsOnSss
+ 0x100a47a5 0x8d _zPHY_ecsrs_CsGetSssRfCfgInfo
+ 0x100a4832 0x12d _zPHY_ecsrs_CsSssProc
+ 0x100a495f 0x1d _zPHY_ecsrs_InitSearchCnf
+ 0x100a497c 0x56 _zPHY_ecsrs_CsSssProcEnd
+ 0x100a49d2 0x18 _zPHY_ecsrs_CsNeedCs
+ 0x100a49ea 0x1a _zPHY_ecsrs_CsBeforeCs
+ 0x100a4a04 0xb _zPHY_ecsrs_WaitSubFrameInt
+ 0x100a4a0f 0x1c _zPHY_ecsrs_SSSearctT
+ 0x100a4a2b 0x3d _zPHY_ecsrs_CheckSssCount
+ 0x100a4a68 0x8 _zPHY_ecsrs_SetSssHwRestartCnt
+ .text 0x100a4a70 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ .text 0x100a4aac 0x458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x100a4aac 0x13 _zPHY_ecsrs_HwIntHandle
+ 0x100a4abf 0x49 _zPHY_ecsrs_HwReset
+ 0x100a4b08 0x33 _zPHY_ecsrs_AllHwReset
+ 0x100a4b3b 0x15 _zPHY_ecsr_HwSssTdCommonReset
+ 0x100a4b50 0xa3 _zPHY_ecsrs_ConfigIcFiFoHw
+ 0x100a4bf3 0x8a _zPHY_ecsrs_ConfigIcHw
+ 0x100a4c7d 0x4f _zPHY_ecsrs_ConfigPssHw
+ 0x100a4ccc 0x36 _zPHY_ecsrs_ConfigCfoHw
+ 0x100a4d02 0x47 _zPHY_ecsrs_ConfigSssHw
+ 0x100a4d49 0xc _zPHY_ecsrs_CfgTopClkGating
+ 0x100a4d55 0x14 _zPHY_ecsrs_CfgTopReg
+ 0x100a4d69 0x27 _zPHY_ecsrs_SssCfgPschLocalSeq
+ 0x100a4d90 0x31 _zPHY_ecsrs_AgcBalanceCfgRegs
+ 0x100a4dc1 0xc _zPHY_ecsrs_AgcBalanceDisable
+ 0x100a4dcd 0x23 _zPHY_ecsrc_SwClkGateCtrl
+ 0x100a4df0 0x49 _zPHY_ecsr_ConvertFinger
+ 0x100a4e39 0x1f _zPHY_ecsr_GetHwPssFinger
+ 0x100a4e58 0x8 _zPHY_ecsr_GetHwPssFreqInd
+ 0x100a4e60 0xd _zPHY_ecsr_GetHwPssDoneMark
+ 0x100a4e6d 0xd _zPHY_ecsr_GetHwPssNumHalfFrame
+ 0x100a4e7a 0x3 _zPHY_ecsr_GetHwPssPeakValid
+ 0x100a4e7d 0x8 _zPHY_ecsr_GetHwPssMaxPower
+ 0x100a4e85 0xa _zPHY_ecsr_GetHwCfoOutput
+ 0x100a4e8f 0x10 _zPHY_ecsr_GetHwSssPeakList
+ 0x100a4e9f 0xa _zPHY_ecsr_GetHwSssComResult
+ 0x100a4ea9 0xb _zPHY_ecsr_GetHwSssProcCount
+ 0x100a4eb4 0xb _zPHY_ecsr_GetHwSssProcStatus
+ 0x100a4ebf 0xd _zPHY_ecsr_GetHwSssProcEnable
+ 0x100a4ecc 0x8 _zPHY_ecsr_GetHwSssProcRdWrState
+ 0x100a4ed4 0x8 _zPHY_ecsr_GetHwIcWorkState
+ 0x100a4edc 0x8 _zPHY_ecsr_GetHwTopClkGating
+ 0x100a4ee4 0x8 _zPHY_ecsr_GetHwPssClkGatingBypass
+ 0x100a4eec 0x8 _zPHY_ecsr_GetHwIcClkGatingBypass
+ 0x100a4ef4 0x8 _zPHY_ecsr_GetHwSssClkGatingEn
+ 0x100a4efc 0x8 _zPHY_ecsr_GetHwSssWorkStatus
+ .text 0x100a4f04 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ 0x100a4f04 0x2f _L1e_FS_LogAddSearchResult
+ 0x100a4f33 0x25 _L1e_FS_LogAddSearchResultFail
+ 0x100a4f58 0x14 _L1e_FS_LogGainCompenError
+ 0x100a4f6c 0x17 _L1e_FS_LogMinAgcGainError
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+ .code_L2d_update2
+ 0x30064000 0x9 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x30064000 0x9 _TestTcm2_update2
+
+.d2tcm_s 0x30068000 0x14 load address 0x100a7e70
+ 0x30068000 _d2tcm_s_start = .
+ *(.data_L2s)
+ .data_L2s 0x30068000 0x14 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x30068000 0x14 _tcm_primes
+
+.d2tcm_d 0x3006c000 0x1 load address 0x100a7e90
+ 0x3006c000 _d2tcm_d_start = .
+ *(.data_L2d)
+ .data_L2d 0x3006c000 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x3006c000 0x1 _tcm_test_result
+
+.d2tcm_d_update1
+ 0x3006c000 0x1 load address 0x100a7ea0
+ 0x3006c000 _d2tcm_d_update1_start = .
+ *(.data_L2d_update1)
+ .data_L2d_update1
+ 0x3006c000 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x3006c000 0x1 _tcm_test_result_update1
+
+.d2tcm_d_update2
+ 0x3006c000 0x1 load address 0x100a7eb0
+ 0x3006c000 _d2tcm_d_update2_start = .
+ *(.data_L2d_update2)
+ .data_L2d_update2
+ 0x3006c000 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x3006c000 0x1 _tcm_test_result_update2
+ 0x100a7ec0 . = ((((LOADADDR (.d2tcm_d_update2) + SIZEOF (.d2tcm_d_update2)) + 0x10) - 0x1) & 0xfffffff0)
+
+.pool 0x100a7ec0 0x22ab0
+ *(.pool)
+ .pool 0x100a7ec0 0x22ab0 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x100a7ec0 0x18e70 _odo_signalpool0
+ 0x100c0d30 0x9c40 _odo_signalpool1
+
+.data 0x100caa00 0x1cdc4
+ *(.data)
+ .data 0x100caa00 0x7 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ 0x100caa00 0x2 ___flushRoutinePtr
+ 0x100caa02 0x5 _ZSP_target_type
+ .data 0x100caa07 0x56 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ 0x100caa0b 0x52 _g_fpIcuCallBack
+ .data 0x100caa5d 0x108 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ 0x100caa5d 0x38 _g_aIntTable
+ 0x100caa95 0xa4 _g_aIntIcuTable
+ 0x100cab39 0x2 _g_dNmiIntErrCnt
+ 0x100cab3b 0x1c _g_fpIntCallBack
+ 0x100cab57 0xe _g_aIntProcId
+ .data 0x100cab65 0x8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ 0x100cab65 0x8 _g_awProcName
+ .data 0x100cab6d 0x9 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x100cab6d 0x9 _odo_panic_info
+ .data 0x100cab76 0x20 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ 0x100cab76 0x20 _odo_arch_vect2pcb
+ .data 0x100cab96 0xe T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ 0x100cab96 0x2 ___zsp_dc_mba
+ 0x100cab98 0xc _ZSP_DCacheDsc
+ .data 0x100caba4 0x57 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x100caba4 0x44 _g_ppZcosVersion
+ 0x100cabe8 0xd _odo_debug_info
+ 0x100cabf5 0x1 _g_SysResetCheck
+ 0x100cabf6 0x2 _sysinfo_state
+ 0x100cabf8 0x1 _g_SysResetCnt1
+ 0x100cabf9 0x1 _g_SysResetCnt2
+ 0x100cabfa 0x1 _g_SysResetCnt3
+ .data 0x100cabfb 0x12 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ 0x100cac09 0x4 _g_fpTimerCallBack
+ .data 0x100cac0d 0x210 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x100cac0d 0x2 _zsp_cmm_buf
+ 0x100cac0f 0x200 _ramdump_cyc
+ 0x100cae0f 0x2 _Test1
+ 0x100cae11 0x2 _ZCAT_PHY_2_PS_BUFFER_BASE
+ 0x100cae13 0x2 _ZCAT_PS_2_PHY_BUFFER_BASE
+ 0x100cae15 0x4 _g_alloc_size
+ 0x100cae19 0x4 _g_max_alloc_size
+ .data 0x100cae1d 0x2 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x100cae1d 0x2 _gIramHookPtr
+ .data 0x100cae1f 0x2b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x100cae1f 0x2 _dwMacroSupport_ZX7520_PHY_SP_PS
+ 0x100cae21 0x2 _dwMacroSupportPS_NODEB_SWITCH
+ 0x100cae23 0x2 _dwMacroSupportPC_SB_ULPWR
+ 0x100cae25 0x2 _dwMacroSupportPCH_DEC_FUNC
+ 0x100cae27 0x2 _dwMacroSupport_ZX7520_PHY_SP_TH
+ 0x100cae29 0x2 _dwMacroSupportTH_ESG_SWITCH
+ 0x100cae2b 0x2 _dwMacroSupportTH_NODEB_SWITCH
+ 0x100cae2d 0x2 _dwMacroSupportTH_ESG_SFN_ADJUST
+ 0x100cae2f 0x2 _dwMacroSupportRX_JD_PICH_DETECT_MODE
+ 0x100cae31 0x2 _dwMacroSupportW_TH_ESG_SWITCH
+ 0x100cae33 0x2 _dwMacroSupportCACL_L_AT_ARM1
+ 0x100cae35 0x2 _dwMacroSupport_TEST_HARNESS_MACRO
+ 0x100cae37 0x2 _dwMacroSupportZPHY_EULA_PRACH_TRANS_INFO
+ 0x100cae39 0x2 _dwMacroSupport_TESTHARNESS_TEST
+ 0x100cae3b 0x2 _dwMacroSupport_DEBUG_ULPC
+ 0x100cae3d 0x2 _dwMacroSupport_DEBUG_C_RNTI_MSG3_STUB
+ 0x100cae3f 0x2 _dwMacroSupportLTE_SPS_MODE_STUB
+ 0x100cae41 0x2 _dwMacroSupport_DEBUG_CCCH_SDU_MSG3_STUB
+ 0x100cae43 0x2 _dwMacroSupport_DEBUG_WITHOUT_PS
+ 0x100cae45 0x2 _dwMacroSupport_TEST_HARNESS_REPORT_MIB_INFO
+ 0x100cae47 0x2 _dwMacroSupport_TH_DEBUG_FOR_CONN_PARALLEL_CRNTI
+ 0x100cae49 0x1 _g_bSleep
+ .data 0x100cae4a 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x100cae4a 0x1 _g_eNvComModelType
+ .data 0x100cae4b 0x2c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ 0x100cae4b 0xe _g_tL2CachePrefetchCfg
+ 0x100cae59 0x1e _g_tL2CacheStaticCfg
+ .data 0x100cae77 0x4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ .data 0x100cae7b 0x10d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x100cae7b 0x106 _g_RpMsgChConfig
+ 0x100caf81 0x2 _rpMsgHisrSem
+ 0x100caf83 0x1 _rpMsgHisrTaskId
+ 0x100caf84 0x2 _pRpMsgRecord
+ 0x100caf86 0x2 _pRpMsgPosRecord
+ .data 0x100caf88 0x37 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x100caf88 0x36 _g_tNvPhyExistInfo
+ 0x100cafbe 0x1 _g_wL1_CpuPhyLpc_ThreadId
+ .data 0x100cafbf 0x2 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x100cafbf 0x2 _g_L1SysPsmInterface
+ .data 0x100cafc1 0x10 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ .data 0x100cafd1 0x1c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x100cafd1 0x4 _g_awPwrBit
+ 0x100cafd5 0x4 _g_aeClkSelToCpuFreq
+ 0x100cafd9 0x4 _g_aeCpuFreqToClkSel
+ 0x100cafdd 0x8 _g_aeClkSelToAxiFreq
+ 0x100cafe5 0x8 _g_aeAxiFreqToClkSel
+ .data 0x100cafed 0x6 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ 0x100cafed 0x2 _g_ptZspSaveBase
+ 0x100cafef 0x2 _g_save_rpc
+ 0x100caff1 0x2 _g_restore_rpc
+ .data 0x100caff3 0x14 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ 0x100caffe 0x1 _g_wL1WdtTaskId
+ 0x100cafff 0x2 _g_dwM0IcpCnt
+ 0x100cb001 0x2 _g_dwM0IcpCnt1
+ 0x100cb003 0x4 _g_tWatchdogLpmTime
+ .data 0x100cb007 0x4c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ 0x100cb007 0x2c _g_atNonICacheCfgInfo
+ 0x100cb033 0x20 _g_atNonDCacheCfgInfo
+ 0x100cb053 0x0 _g_atCacheWTCfgInfo
+ .data 0x100cb053 0xe C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o)
+ 0x100cb053 0x2 ___zsp_ic_mba
+ 0x100cb055 0xc _ZSP_ICacheDsc
+ .data 0x100cb061 0x135 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ .data 0x100cb196 0xf T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x100cb1a4 0x1 _g_bL1wMeasSetAgcStartTime
+ .data 0x100cb1a5 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x100cb1a5 0x1 _g_bDevHspaFachEdchActive
+ 0x100cb1a6 0x1 _g_bPsrUpdate
+ .data 0x100cb1a7 0xf T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ .data 0x100cb1b6 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ .data 0x100cb1b7 0x80 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ .data 0x100cb237 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x100cb237 0x1 _g_wL1wHsdpaTpuIntId
+ 0x100cb238 0x1 _g_wL1wHsdpaTxTpuIntId
+ 0x100cb239 0x1 _g_bFlg
+ .data 0x100cb23a 0xb4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x100cb23a 0x19 _g_abL1wHsdpaP2IntDecodeEnFlg
+ 0x100cb253 0x99 _g_atLessHwCfg
+ 0x100cb2ec 0x2 _g_ptL1wLessSubfrmLogInfo
+ .data 0x100cb2ee 0x162 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ .data 0x100cb450 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x100cb450 0x1 _g_tRtxTxRfcInfo
+ .data 0x100cb451 0x21c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x100cb451 0x8 _RV_R_S_TABLE
+ 0x100cb459 0x80 _TB_L1W_TABLE_NEJ_TWO_A
+ 0x100cb4d9 0x7e _TB_L1W_TABLE_NEJ_TWO_B
+ 0x100cb557 0x80 _TB_L1W_TABLE_NEJ_TEN_A
+ 0x100cb5d7 0x79 _TB_L1W_TABLE_NEJ_TEN_B
+ 0x100cb650 0xa _L1W_SET_FOR_TTI_TEN
+ 0x100cb65a 0xa _L1W_SET_FOR_TTI_TWO
+ 0x100cb664 0x8 _g_atL1wHsupaCmPattern
+ 0x100cb66c 0x1 _dwMacroSupportW_HSUPA_TH_WITHOUT_L
+ .data 0x100cb66d 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ .data 0x100cb671 0x2c8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x100cb671 0x8 _TAB_L1W_HSDPA_RV_B
+ 0x100cb679 0x18 _TAB_L1W_HSDPA_RV_S
+ 0x100cb691 0x18 _TAB_L1W_HSDPA_RV_R
+ 0x100cb6a9 0x3 _TAB_L1W_HSDPA_RV_RMAX
+ 0x100cb6ac 0x3 _TAB_L1W_HSDPA_NDATA_1
+ 0x100cb6af 0x1e _TAB_L1W_HSDPA_K_BIT_ALIGN
+ 0x100cb6cd 0x2d _TAB_L1W_HSDPA_K_OCTET_ALIGN
+ 0x100cb6fa 0xfe _TAB_L1W_HSDPA_TB_SIZE_BIT_ALIGN
+ 0x100cb7f8 0x127 _TAB_L1W_HSDPA_TB_SIZE_OCTET_ALIGN
+ 0x100cb91f 0x7 _TAB_L1W_HSDPA_HSDPCCH_CH_CODE
+ 0x100cb926 0x4 _TAB_L1W_HSDPA_HSDPCCH_ACK_CODING
+ 0x100cb92a 0xf _TAB_HSDPA_NEXT_SUBFRAME_ID
+ .data 0x100cb939 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ 0x100cb939 0x1 _g_wPiAiAfcIntCnt
+ .data 0x100cb93a 0x10a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x100cb93a 0x10a _g_bSymbol3EventEn
+ .data 0x100cba44 0x8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x100cba44 0x1 _g_wHeaderOffset
+ 0x100cba45 0x6 _g_abL1wMsgTypeRpt
+ 0x100cba4b 0x1 _g_bL1wLogOutUsing
+ .data 0x100cba4c 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ 0x100cba60 0x3ec _g_tTxTrchInfo
+ .data 0x100cbe4c 0x1fb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x100cc045 0x2 _g_pvBlindData
+ .data 0x100cc047 0x61a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ 0x100cc047 0x1e _TAB_L1W_HSDPA_T1R1_TAU1
+ 0x100cc065 0x1e _TAB_L1W_HSDPA_T1R1_TAU3
+ 0x100cc083 0x1e _TAB_L1W_HSDPA_T1R1_TAU6
+ 0x100cc0a1 0x1e _TAB_L1W_HSDPA_T1R1_TAU10
+ 0x100cc0bf 0x1e _TAB_L1W_HSDPA_T1R1_TAU13
+ 0x100cc0dd 0x1e _TAB_L1W_HSDPA_T1R1_TAU15
+ 0x100cc0fb 0x1e _TAB_L1W_HSDPA_T1R1_TAUX
+ 0x100cc119 0x1e _TAB_L1W_HSDPA_T1R2_TAU2
+ 0x100cc137 0x1e _TAB_L1W_HSDPA_T1R2_TAU6
+ 0x100cc155 0x1e _TAB_L1W_HSDPA_T1R2_TAU10
+ 0x100cc173 0x1e _TAB_L1W_HSDPA_T1R2_TAU13
+ 0x100cc191 0x1e _TAB_L1W_HSDPA_T1R2_TAU15
+ 0x100cc1af 0x1e _TAB_L1W_HSDPA_T1R2_TAUX
+ 0x100cc1cd 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAU1
+ 0x100cc1eb 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAU3
+ 0x100cc209 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAU6
+ 0x100cc227 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAU10
+ 0x100cc245 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAU13
+ 0x100cc263 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAU15
+ 0x100cc281 0x1e _TAB_L1W_HSDPA_PLUS_T1R1_TAUX
+ 0x100cc29f 0x1e _TAB_L1W_HSDPA_PLUS_T1R2_TAU2
+ 0x100cc2bd 0x1e _TAB_L1W_HSDPA_PLUS_T1R2_TAU6
+ 0x100cc2db 0x1e _TAB_L1W_HSDPA_PLUS_T1R2_TAU10
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+ 0x100cc317 0x1e _TAB_L1W_HSDPA_PLUS_T1R2_TAU15
+ 0x100cc335 0x1e _TAB_L1W_HSDPA_PLUS_T1R2_TAUX
+ 0x100cc353 0x1e _TAB_L1W_HSDPA_STTD_T2R1_TAU2
+ 0x100cc371 0x1e _TAB_L1W_HSDPA_STTD_T2R1_TAU6
+ 0x100cc38f 0x1e _TAB_L1W_HSDPA_STTD_T2R1_TAU10
+ 0x100cc3ad 0x1e _TAB_L1W_HSDPA_STTD_T2R1_TAU13
+ 0x100cc3cb 0x1e _TAB_L1W_HSDPA_STTD_T2R1_TAU15
+ 0x100cc3e9 0x1e _TAB_L1W_HSDPA_STTD_T2R1_TAUX
+ 0x100cc407 0x1e _TAB_L1W_HSDPA_STTD_T2R2_TAU6
+ 0x100cc425 0x1e _TAB_L1W_HSDPA_STTD_T2R2_TAU10
+ 0x100cc443 0x1e _TAB_L1W_HSDPA_STTD_T2R2_TAU13
+ 0x100cc461 0x1e _TAB_L1W_HSDPA_STTD_T2R2_TAU15
+ 0x100cc47f 0x1e _TAB_L1W_HSDPA_STTD_T2R2_TAUX
+ 0x100cc49d 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R1_TAU2
+ 0x100cc4bb 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R1_TAU6
+ 0x100cc4d9 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R1_TAU10
+ 0x100cc4f7 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R1_TAU13
+ 0x100cc515 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R1_TAU15
+ 0x100cc533 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R1_TAUX
+ 0x100cc551 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R2_TAU6
+ 0x100cc56f 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R2_TAU10
+ 0x100cc58d 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R2_TAU13
+ 0x100cc5ab 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R2_TAU15
+ 0x100cc5c9 0x1e _TAB_L1W_HSDPA_PLUS_STTD_T2R2_TAUX
+ 0x100cc5e7 0x1e _TAB_L1W_HSDPA_CLTD_T2R1_TAUX
+ 0x100cc605 0x1e _TAB_L1W_HSDPA_PLUS_CLTD_T2R1_TAUX
+ 0x100cc623 0x1e _TAB_L1W_HSDPA_CLTD_T2R2_TAUX
+ 0x100cc641 0x1e _TAB_L1W_HSDPA_PLUS_CLTD_T2R2_TAUX
+ 0x100cc65f 0x2 _g_pswCqiTab
+ .data 0x100cc661 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x100cc661 0x2 _g_tWEdchTtin
+ 0x100cc663 0x1 _g_wL1wHsupaIntId
+ 0x100cc664 0x1 _g_wL1wHsupaSubFrmIntId
+ 0x100cc665 0x1 _g_wHsupaEagchIntTti
+ 0x100cc666 0x2 _g_ptWHsupaDlRcvInfo
+ 0x100cc668 0x2 _g_pwFdpchFrmOffset
+ 0x100cc66a 0x1 _g_eL1wHsupaTaskType
+ 0x100cc66b 0x1 _g_wHsupaEagchCountInt
+ 0x100cc66c 0x1 _g_eutrRstCnt
+ .data 0x100cc66d 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ .data 0x100cc6a5 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x100cc6a5 0x1 _g_bL1wDchStartPsrFlag
+ 0x100cc6a6 0x1 _g_bL1wFachStartPsrFlag
+ 0x100cc6a7 0x1 _g_bL1wEFachStartPsrFlag
+ 0x100cc6a8 0x1 _g_bL1wUpaExistFlag
+ 0x100cc6a9 0x6 _g_bL1wTrueFingerExistFlag
+ 0x100cc6af 0x1 _g_bUpaStateChangeFlag
+ 0x100cc6b0 0x1 _g_bSelectMasterFlag
+ .data 0x100cc6b1 0x73 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x100cc6b1 0x73 _g_aL1wDvfs
+ .data 0x100cc724 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x100cc724 0x1 _g_bL1wTpuWorkFlag
+ 0x100cc725 0x1 _g_bL1wTpuMicroSsfnBackPatch
+ 0x100cc726 0x1 _g_bL1wTpuMicroSsfnJumpPatch
+ .data 0x100cc727 0x1c96 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x100cc727 0x1 _g_eRxChannelState
+ 0x100cc728 0x1 _g_eRxChannelCtrlInfo
+ 0x100cc729 0x1 _g_swL1wCurTxPower
+ 0x100cc72a 0xb62 _TAB_DB_INIT_X_VALUE
+ 0x100cd28c 0x962 _TAB_DB_INIT_Y_VALUE
+ 0x100cdbee 0x3c0 _TAB_DB_SCH_CODE_GRP
+ 0x100cdfae 0x200 _TAB_DB_AI_SIGNATURE_SERIES
+ 0x100ce1ae 0x20c _TAB_DB_EAI_SIGNATURE_SERIES
+ 0x100ce3ba 0x1 _g_eDevLast1R2RState
+ 0x100ce3bb 0x1 _g_eDevCur1R2RState
+ 0x100ce3bc 0x1 _g_eSystemAntNumDetect
+ .data 0x100ce3bd 0x2c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ .data 0x100ce3e9 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x100ce3e9 0x6 _g_awDagcFracStepTable
+ 0x100ce3ef 0x7 _g_awDagcFracTable
+ 0x100ce3f6 0x7 _g_awDagcTempTable
+ .data 0x100ce3fd 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x100ce3fd 0x36 _g_atL1wTpuIntStaticNtPara
+ 0x100ce433 0xa _g_atL1wTpuIntStaticRtPara
+ .data 0x100ce43d 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ 0x100ce43d 0x1 _g_bL1wHsdschConfigFlg
+ .data 0x100ce43e 0x5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x100ce43e 0x1 _g_bLastSubFrmIs0
+ 0x100ce43f 0x4 _g_tLpmTimeReportPs
+ .data 0x100ce443 0x7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ .data 0x100ce44a 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ .data 0x100ce480 0x17fd T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ 0x100ce480 0x16 _TX_TU_EVENT
+ 0x100ce496 0xa8 _CTRL_RAM_TX_EVENT
+ 0x100ce53e 0x16 _RX_TU_EVENT
+ 0x100ce554 0xcf _CTRL_RAM_RX_EVENT
+ 0x100ce623 0x280 _g_awRF_W_APC_HI_TABLE_ZXPA
+ 0x100ce8a3 0x280 _g_awRF_W_APC_HI_TABLE
+ 0x100ceb23 0x280 _g_awABB_W_APC_HI_TABLE_ZXPA
+ 0x100ceda3 0x280 _g_awABB_W_APC_HI_TABLE
+ 0x100cf023 0x280 _g_awRF_W_APC_LOW_TABLE_ZXPA
+ 0x100cf2a3 0x280 _g_awRF_W_APC_LOW_TABLE
+ 0x100cf523 0x280 _g_awABB_W_APC_LOW_TABLE_ZXPA
+ 0x100cf7a3 0x280 _g_awABB_W_APC_LOW_TABLE
+ 0x100cfa23 0x5f _g_awRF_W_AGC_TABLE
+ 0x100cfa82 0x5f _g_awABB_W_AGC_TABLE
+ 0x100cfae1 0xbe _g_aFAST_AGC_TABLE
+ 0x100cfb9f 0xc0 _g_ZX220120_BandData
+ 0x100cfc5f 0x1e _g_adRfcReadBackTable
+ .data 0x100cfc7d 0x21ec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x100cfc7d 0x30 _g_atBandRangeTX
+ 0x100cfcad 0x82 _g_atBandAddTX
+ 0x100cfd2f 0x30 _g_atBandRangeRX
+ 0x100cfd5f 0x82 _g_atBandAddRX
+ 0x100cfde1 0xdc _g_atBandInfoTX
+ 0x100cfebd 0xdc _g_atBandInfoRX
+ 0x100cff99 0x68 _adCsf3_8M
+ 0x100d0001 0x1e68 _adCsf5M
+ .data 0x100d1e69 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x100d1e69 0xc _TAB_L1W_LESS_DCH_CW
+ 0x100d1e75 0x8 _TAB_L1W_LESS_PCH_CW
+ 0x100d1e7d 0x3 _TAB_L1W_LESS_HARQ_ADDR
+ 0x100d1e80 0x2 _g_peHsdpaState
+ .data 0x100d1e82 0x6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ .data 0x100d1e88 0x1af T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ 0x100d1e88 0x147 _g_tL1wRachProcInfo
+ 0x100d1fcf 0x8 _g_awL1wAsHeader
+ 0x100d1fd7 0x60 _g_awL1wAsStartSlot
+ .data 0x100d2037 0x206 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ .data 0x100d223d 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ 0x100d223d 0x28 _g_tL1wCs1ProcInfo
+ .data 0x100d2265 0x6ef9 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
+ 0x100d2265 0x6ef6 _g_tL1wMeasProcInfo
+ 0x100d915b 0x2 _g_curTemp
+ 0x100d915d 0x1 _g_bNotify
+ .data 0x100d915e 0x15 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ 0x100d915e 0x14 _g_tL1wCmProcInfo
+ 0x100d9172 0x1 _g_bL1wCmHiSched
+ .data 0x100d9173 0x1a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_sc.o)
+ .data 0x100d918d 0x2e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ .data 0x100d91bb 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ 0x100d91bb 0x14 _g_tL1wBchProcInfo
+ .data 0x100d91cf 0x1ee9 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_amt.o)
+ 0x100d91cf 0x1 _g_bAmtCnfEn
+ 0x100d91d0 0x1ee8 _g_tL1wAmtProcInfo
+ .data 0x100db0b8 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ 0x100db0b8 0x28 _g_tL1wCs0ProcInfo
+ .data 0x100db0e0 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ 0x100db0e0 0x14 _g_tL1wHspaProcInfo
+ .data 0x100db0f4 0x73 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fach.o)
+ 0x100db0f4 0x73 _g_tL1wFachProcInfo
+ .data 0x100db167 0x86 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
+ 0x100db167 0x86 _g_tL1wPageProcInfo
+ .data 0x100db1ed 0xb7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_dch.o)
+ 0x100db1ed 0xb7 _g_tL1wDchProcInfo
+ .data 0x100db2a4 0x146 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ 0x100db2a4 0x145 _g_tL1wGapProcInfo
+ 0x100db3e9 0x1 _g_bAbortGapCnfImmediately
+ .data 0x100db3ea 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ 0x100db3ea 0x36 _g_tL1wHsdpaProcInfo
+ .data 0x100db420 0x21 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ 0x100db420 0x21 _g_tL1wFmoProcInfo
+ .data 0x100db441 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ 0x100db441 0x14 _g_tL1wFSProcInfo
+ .data 0x100db455 0xe T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ .data 0x100db463 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ .data 0x100db467 0x31 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ .data 0x100db498 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x100db498 0x1 _g_bL1wHsdpaDmaBusy
+ 0x100db499 0x2 _g_ptL1wHsdpaDmaDataAddr
+ .data 0x100db49b 0x16 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x100db49b 0xc _L1W_TAB_HSUPA_RG_THRESH
+ 0x100db4a7 0x8 _L1W_TAB_HSUPA_HI_THRESH
+ 0x100db4af 0x1 _g_eL1wServHiNckDtx
+ 0x100db4b0 0x1 _g_hiNackCnt
+ .data 0x100db4b1 0x269 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x100db719 0x1 _g_L1LteaInitFlag
+ .data 0x100db71a 0x61a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ .data 0x100dbd34 0x34 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x100dbd34 0x1f _swTpuSym2Ts
+ 0x100dbd53 0x15 _s_awNextXSubFrm
+ .data 0x100dbd68 0x13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x100dbd68 0x8 _g_tCsi
+ 0x100dbd70 0x1 _g_wCsiSCellActive
+ 0x100dbd71 0xa _g_awCsiNoUpFlg
+ .data 0x100dbd7b 0x87 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x100dbd7b 0x10 _g_aswDdrPro
+ 0x100dbd8b 0x4 _g_aswDdrStartPro
+ 0x100dbd8f 0x40 _g_awDdrBmpConv
+ 0x100dbdcf 0x32 _g_awStartBlockIdx
+ 0x100dbe01 0x1 _wPchUseSibFlag
+ .data 0x100dbe02 0x235 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x100dbe02 0x39 _T_ZPHY_RFSD_CONFIG
+ 0x100dbe3b 0x1c _T_ZPHY_RFCSA_CSRC_CONFIG
+ 0x100dbe57 0x15 _T_ZPHY_RFCSA_RX_CONFIG
+ 0x100dbe6c 0x18 _T_ZPHY_RFCSA_TX_CONFIG
+ 0x100dbe84 0x16 _T_ZPHY_TA_MAX
+ 0x100dbe9a 0x31 _T_ZPHY_ACP405_TRANS_TABLE
+ 0x100dbecb 0x6 _T_ZPHY_ACP405_FASTAGC_APPLY
+ 0x100dbed1 0x6 _T_ZPHY_RFC_FASTAGC_ESTI
+ 0x100dbed7 0x28 _g_at_zPHY_erfc_VgaTempDiffList
+ 0x100dbeff 0xc _g_adwFixDlDelay
+ 0x100dbf0b 0xc _g_dwFixUlDelay
+ 0x100dbf17 0xc _g_dwULDBBRFDelay
+ 0x100dbf23 0x1 _g_wTddOrFddbuff
+ 0x100dbf24 0x14 _g_asdzPHY_erfc_Rxoffset0SFConfig
+ 0x100dbf38 0x14 _g_asdzPHY_erfc_Rxoffset1SFConfig
+ 0x100dbf4c 0x1 _g_zPHY_erfc_wMeas0TabJumpToNum
+ 0x100dbf4d 0x1 _g_zPHY_erfc_cTxTabJumpToSubNum
+ 0x100dbf4e 0x14 _g_asdzPHY_erfc_TAoffsetSFConfig
+ 0x100dbf62 0x2 _g_ptzPHY_etpu_LocalMrtrOffset
+ 0x100dbf64 0x98 _g_zPHY_erfc_Temp_Dac_Data
+ 0x100dbffc 0x2 _g_swATCtrlFixTa
+ 0x100dbffe 0x2 _g_ePhyRatMode
+ 0x100dc000 0x12 _g_zPHY_RfcDataPointer
+ 0x100dc012 0x1 _g_zPHY_erfc_bRfcProfileInd
+ 0x100dc013 0x1 _g_zPHY_edfe_bRfcProfileInd
+ 0x100dc014 0x1 _g_zPHY_erfc_NextSfnSccIdleFlag
+ 0x100dc015 0x6 _g_atL1lRfcNextSfOffset
+ 0x100dc01b 0x6 _g_tXoAtDebugC0
+ 0x100dc021 0x16 _g_zPHY_erfc_tDcxoPara
+ .data 0x100dc037 0x4e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x100dc037 0x9 _g_wCddRiFirCalc
+ 0x100dc040 0x297 _g_awLog2TableDot16
+ 0x100dc2d7 0x80 _g_awLog2Table
+ 0x100dc357 0x10 _g_atCDDL2CB
+ 0x100dc367 0x18 _g_atCBTX2NL1
+ 0x100dc37f 0x20 _g_atCBTX2NL2
+ 0x100dc39f 0x100 _g_atCBTX4NL2
+ 0x100dc49f 0x48 _g_atCBCDDTx4
+ 0x100dc4e7 0x2a _g_awCqiEfficiency
+ 0x100dc511 0x1 _g_RiVal2Dl
+ 0x100dc512 0x4 _g_adCddRiCurSnr
+ 0x100dc516 0x4 _g_adCddRiFilterSnr
+ .data 0x100dc51a 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x100dc51a 0x2 _ptrBch
+ 0x100dc51c 0x2 _g_dwCsrsMulmPbchWorkFlag
+ .data 0x100dc51e 0x52 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x100dc53c 0x12 _g_ptL1eDevDlsDlaIx
+ 0x100dc54e 0x20 _g_dwHarqAddr
+ 0x100dc56e 0x2 _gDLHarqPduMutex
+ .data 0x100dc570 0x97 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x100dc5d4 0x6 _s_aWBHiCfgSBSize
+ 0x100dc5da 0x6 _s_aWBHiCfgLastSBSize
+ 0x100dc5e0 0x24 _s_aWBHiCfgSBNum
+ 0x100dc604 0x2 _g_PatCsiEnFinal
+ 0x100dc606 0x1 _g_awFeedBack_ConfigTimes
+ .data 0x100dc607 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x100dc607 0x2 _g_sdwTxOffset
+ *fill* 0x100dc609 0x80000001 00
+ .data 0x100dc60a 0xf4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x100dc629 0x2 _g_ptRxp_Ops
+ 0x100dc62b 0x1a _g_lsdwL1eRxSnrRefValue
+ 0x100dc645 0x28 _g_tLtel1RxAdaptAntCb
+ 0x100dc66d 0x16 _g_tLtel1DlaRfcDfeInfo
+ 0x100dc683 0x20 _g_lsdwNbnbRsrp
+ 0x100dc6a3 0x8 _g_lsdwNbnbN0
+ 0x100dc6ab 0x10 _g_lsdwNbnbRsrpPwr
+ 0x100dc6bb 0x40 _g_asdwL1eRxDrsRsrp
+ 0x100dc6fb 0x1 _g_wSingleAnt
+ 0x100dc6fc 0x2 _g_dwDrxState_For712Cir
+ *fill* 0x100dc6fe 0x80000002 00
+ .data 0x100dc700 0x1eee T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x100dc700 0x2 _g_dwSf_BeforeTAAdjust
+ 0x100dc702 0x20 _G_AW_SRS_M_NB_0640
+ 0x100dc722 0x20 _G_AW_SRS_M_NB_4060
+ 0x100dc742 0x20 _G_AW_SRS_M_NB_6080
+ 0x100dc762 0x20 _G_AW_SRS_M_NB_80110
+ 0x100dc782 0x50 _G_AC_SRS_SUBFRM_CONFIG_TDD
+ 0x100dc7d2 0xa0 _G_CELL_SRS_POS_SUBFRM_CONFIG_TDD
+ 0x100dc872 0x1e _G_AC_SRS_UE_SPEC_CONFIG_TDD
+ 0x100dc890 0x64 _G_UE_SRS_POS_CONFIG_TDD
+ 0x100dc8f4 0xc _G_AC_K_SRS1
+ 0x100dc900 0xc _G_AC_K_SRS2
+ 0x100dc90c 0x14 _G_AC_MULTI_ACKNACK_B0B1
+ 0x100dc920 0x9 _G_NEXT_ACK_ORDER
+ 0x100dc929 0x46 _G_AC_DL_SET_K_INFO
+ 0x100dc96f 0x46 _G_AC_DL_SET_K_FDD_TDD_INFO
+ 0x100dc9b5 0x9 _G_AC_M2_ACK_MULTIPLEXING
+ 0x100dc9be 0x1b _G_AC_M3_ACK_MULTIPLEXING
+ 0x100dc9d9 0x51 _G_AC_M4_ACK_MULTIPLEXING
+ 0x100dca2a 0x9 _G_AC_M2_ACK_MULTIPLEXING_R10
+ 0x100dca33 0x1b _G_AC_M3_ACK_MULTIPLEXING_R10
+ 0x100dca4e 0x51 _G_AC_M4_ACK_MULTIPLEXING_R10
+ 0x100dca9f 0x8 _G_AC_CA_A2_ACK_MULTIPLEXING
+ 0x100dcaa7 0x10 _G_AC_CA_A3_ACK_MULTIPLEXING
+ 0x100dcab7 0x20 _G_AC_CA_A4_ACK_MULTIPLEXING
+ 0x100dcad7 0x20 _G_FDD_CA_A4_ACK_FORMAT1B
+ 0x100dcaf7 0x12 _G_FDD_CA_A3_ACK_FORMAT1B
+ 0x100dcb09 0x8 _G_FDD_CA_A2_ACK_FORMAT1B
+ 0x100dcb11 0x20 _G_AC_CA_M3_ACK_MULTIPLEXING
+ 0x100dcb31 0x4c _G_AC_CA_M4_ACK_MULTIPLEXING
+ 0x100dcb7d 0x20 _G_AC_CA_M3_ACK_RESOURCE_VALUE
+ 0x100dcb9d 0x4c _G_AC_CA_M4_ACK_RESOURCE_VALUE
+ 0x100dcbe9 0x9 _G_AC_ULDL5_ACK_ORDER
+ 0x100dcbf2 0x46 _G_AC_SPECIAL_SUBFRAME_FLAG
+ 0x100dcc38 0x90 _G_AC_SRS_SUBFRM_CONFIG_FDD
+ 0x100dccc8 0xa0 _G_CELL_SRS_POS_SUBFRM_CONFIG_FDD
+ 0x100dcd68 0x10 _G_AW_HARQ_ACK_OFFSET
+ 0x100dcd78 0x10 _G_AW_RI_OFFSET
+ 0x100dcd88 0x10 _G_AW_CQI_OFFSET
+ 0x100dcd98 0xc5 _G_AW_PRIME_NUMBER
+ 0x100dce5d 0x8 _G_AW_CYCLIC_SHIFT_NDMRS1
+ 0x100dce65 0x18 _G_AW_CYCLIC_SHIFT_INDCI_NDMRS2_OCC
+ 0x100dce7d 0x5 _G_AW_FORMAT3_NOC_NPNS_NSF1_5
+ 0x100dce82 0x4 _G_AW_FORMAT3_NOC_NPNS_NSF1_4
+ 0x100dce86 0x7 _G_W_PRACH0_3_SCALE1
+ 0x100dce8d 0x1 _G_W_PRACH0_3_SCALE3
+ 0x100dce8e 0x7 _G_W_PRACH4_SCALE1
+ 0x100dce95 0x1 _G_W_PRACH4_SCALE3
+ 0x100dce96 0x7 _G_W_PUCCH_SCALE1_1_92M_SAMPLE
+ 0x100dce9d 0x7 _G_W_PUCCH_SCALE1_3_84M_SAMPLE
+ 0x100dcea4 0x7 _G_W_PUCCH_SCALE1_7_68M_SAMPLE
+ 0x100dceab 0x7 _G_W_PUCCH_SCALE1_15_36M_SAMPLE
+ 0x100dceb2 0x7 _G_W_PUCCH_SCALE1_30_72M_SAMPLE
+ 0x100dceb9 0x1 _G_W_PUCCH_SCALE3
+ 0x100dceba 0x1 _G_W_SRS_SCALE3
+ 0x100dcebb 0x7 _G_W_SRS_SCALE1_1_92M_SAMPLE
+ 0x100dcec2 0x1c _G_W_SRS_SCALE1_3_84M_SAMPLE
+ 0x100dcede 0x31 _G_W_SRS_SCALE1_7_68M_SAMPLE
+ 0x100dcf0f 0x62 _G_W_SRS_SCALE1_15_36M_SAMPLE
+ 0x100dcf71 0xaf _G_W_SRS_SCALE1_30_72M_SAMPLE
+ 0x100dd020 0x7 _G_W_PUSCH_SCALE1_1_92M_SAMPLE
+ 0x100dd027 0x7 _G_W_PUSCH_SCALE3_1_92M_SAMPLE
+ 0x100dd02e 0x7 _G_W_PUSCH_SCALE1_3_84M_SAMPLE
+ 0x100dd035 0x10 _G_W_PUSCH_SCALE3_3_84M_SAMPLE
+ 0x100dd045 0x7 _G_W_PUSCH_SCALE1_7_68M_SAMPLE
+ 0x100dd04c 0x1a _G_W_PUSCH_SCALE3_7_68M_SAMPLE
+ 0x100dd066 0x7 _G_W_PUSCH_SCALE1_15_36M_SAMPLE
+ 0x100dd06d 0x33 _G_W_PUSCH_SCALE3_15_36M_SAMPLE
+ 0x100dd0a0 0xe _G_W_PUSCH_SCALE1_30_72M_SAMPLE
+ 0x100dd0ae 0x65 _G_W_PUSCH_SCALE3_30_72M_SAMPLE
+ 0x100dd113 0x42 _G_W_FIRST_FILTER_1_4M_SAMPLE
+ 0x100dd155 0x42 _G_W_FIRST_FILTER_1_4M_SAMPLE_FIX3072
+ 0x100dd197 0x42 _G_W_FIRST_FILTER_3M_SAMPLE
+ 0x100dd1d9 0x42 _G_W_FIRST_FILTER_3M_SAMPLE_FIX3072
+ 0x100dd21b 0x42 _G_W_FIRST_FILTER_5M_SAMPLE
+ 0x100dd25d 0x42 _G_W_FIRST_FILTER_5M_SAMPLE_FIX3072
+ 0x100dd29f 0x42 _G_W_FIRST_FILTER_10M_SAMPLE
+ 0x100dd2e1 0x42 _G_W_FIRST_FILTER_10M_SAMPLE_FIX3072
+ 0x100dd323 0x42 _G_W_FIRST_FILTER_15M_SAMPLE
+ 0x100dd365 0x42 _G_W_FIRST_FILTER_20M_SAMPLE
+ 0x100dd3a7 0x42 _G_W_FIRST_FILTER_BYPASS_STUB_SAMPLE
+ 0x100dd3e9 0x42 _G_W_PRACH_FILTER_20M_15M_SAMPLE
+ 0x100dd42b 0x42 _G_W_PRACH_FILTER_3M_SAMPLE
+ 0x100dd46d 0x42 _G_W_PRACH_FILTER_5M_SAMPLE
+ 0x100dd4af 0x42 _G_W_PRACH_FILTER_10M_SAMPLE
+ 0x100dd4f1 0x18 _G_ADW_NCS_DIV_6
+ 0x100dd509 0x10 _G_ADW_NCS_DIV_4
+ 0x100dd519 0x6 _G_AW_C_NRBSC_DELTAPUCCHSHIFT
+ 0x100dd51f 0x208 _G_AW_MOD_30
+ 0x100dd727 0x12c _G_AW_MOD_12
+ 0x100dd853 0x24 _G_A_ZPHY_EULA_CHANNELTIMINGSEQTAB
+ 0x100dd877 0x25 _G_A_ZPHY_EULA_TQADJSUBFRAME
+ 0x100dd89c 0xc8 _g_adw_zPHY_eula_PuschMsg3Data
+ 0x100dd964 0xc76 _g_adw_zPHY_eula_TestCase12_2Data
+ 0x100de5da 0x14 _g_aeUlChannelType
+ .data 0x100de5ee 0x104 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x100de5ee 0x1 _g_zPHY_eWakeUpMode
+ 0x100de5ef 0x2 _g_zPHY_SleepFlag
+ 0x100de5f1 0x55 _G_ZPHY_ELPC_DVFS
+ 0x100de646 0x14 _g_zPHY_LPMCALIPARA
+ 0x100de65a 0x4 _G_ZPHY_ELPC_ZSPCLK
+ 0x100de65e 0x8f _G_ZPHY_ELPC_AXICLK
+ 0x100de6ed 0x1 _g_wWakeUpFlag
+ 0x100de6ee 0x1 _g_zPHY_bSccRficSleepFlag
+ 0x100de6ef 0x1 _g_zPHY_bUlGrantIntState
+ 0x100de6f0 0x1 _g_wLteCfunReset
+ 0x100de6f1 0x1 _g_wLtePrint1
+ .data 0x100de6f2 0x27 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x100de6f2 0x2 _g_dwInitalBandwidth
+ 0x100de6f4 0x24 _T_ZPHY_RELOAD_CONFIG
+ 0x100de718 0x1 _g_zPHY_tRfSleepState
+ .data 0x100de719 0x110 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x100de719 0x1 _g_zPHY_ecsrm_tConnectedMeasMode
+ 0x100de71a 0x10f _g_ThreadMeas
+ .data 0x100de829 0x17a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x100de829 0xa _g_awCsrmRsNumLog2
+ 0x100de833 0xa _g_awCsrmRsNumLog2_Single_Symbol
+ 0x100de83d 0x6 _g_awCsrmNumFftLogVal
+ 0x100de843 0x8 _MeasOnceSteps
+ 0x100de84b 0x67 _MeasOnce
+ 0x100de8b2 0x8 _MeasPrimarySteps
+ 0x100de8ba 0x67 _MeasPrimary
+ 0x100de921 0x18 _MeasProcSteps
+ 0x100de939 0x67 _MeasProc
+ 0x100de9a0 0x1 _g_zPHY_ecsrm_bHalfFrame
+ 0x100de9a1 0x2 _g_awMeasSingleSymModeFlag
+ .data 0x100de9a3 0x37 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x100de9a3 0x35 _g_awTriangleCoefft
+ 0x100de9d8 0x1 _gwCellchangeFlag
+ 0x100de9d9 0x1 _g_wMaxTxIndex
+ *fill* 0x100de9da 0x80000026 00
+ .data 0x100dea00 0x200 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x100dea00 0x200 _g_aswOutdata
+ .data 0x100dec00 0x64 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x100dec00 0x50 _g_awL1eRxRsrpIdleFilterCoeff
+ 0x100dec50 0x14 _g_awL1eRxRsrpFilterCoeff
+ .data 0x100dec64 0x9b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x100dec64 0x2 _g_zPHY_edfe_dwAgcHwModeVari
+ 0x100dec66 0x1 _g_wFirstFlagDC0
+ 0x100dec67 0x1 _g_wFirstFlagDC1
+ 0x100dec68 0x84 _WDFE_GAINDBTOLINEVALUE
+ 0x100decec 0x1 _g_Csrs_Csrm_Start_Flag
+ 0x100deced 0x1 _g_bDfeIntCheckEventFlag
+ 0x100decee 0x1 _g_bCsrsDagcEstiEnableFlag
+ 0x100decef 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd
+ 0x100decf0 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd0
+ 0x100decf1 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd1
+ 0x100decf2 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCoverFlag
+ 0x100decf3 0x2 _g_dwRspRx0Tx0
+ 0x100decf5 0x2 _g_dwRspRx1Tx0
+ 0x100decf7 0x2 _g_dwRspRx0Tx1
+ 0x100decf9 0x2 _g_dwRspRx1Tx1
+ 0x100decfb 0x1 _g_Idle_Inter_Freq_Flag
+ 0x100decfc 0x1 _g_wRxDagcIntCounter
+ 0x100decfd 0x1 _g_zPHY_edfe_RxDagcDoneFlag
+ 0x100decfe 0x1 _g_wFreqScanWorkOnFlag
+ .data 0x100decff 0xb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x100decff 0x1 _g_wPreSubFrame
+ 0x100ded00 0x1 _g_wCurSubFrame
+ 0x100ded01 0x1 _g_wPreFrame
+ 0x100ded02 0x1 _g_wCurFrame
+ 0x100ded03 0x1 _g_wSrsUpdataFlg
+ 0x100ded04 0x1 _g_wSrsUpdataFlg_Scell
+ 0x100ded05 0x2 _g_b_zPHY_eula_SrsSendFlag
+ 0x100ded07 0x1 _g_wMSG4AckINTLOCKCnt
+ 0x100ded08 0x1 _g_b711712Test1Test2Flg
+ 0x100ded09 0x1 _g_b711Test3Flg
+ .data 0x100ded0a 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x100ded0a 0x1 _wTddFddCaEnFlg
+ .data 0x100ded0b 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x100ded4f 0x1 _g_zPHY_RFQuickAdjTxoffsetFlag
+ .data 0x100ded50 0x58 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x100ded50 0x28 _g_zPHY_Int0HandleCfg
+ 0x100ded78 0x18 _g_zPHY_Int1HandleCfg
+ 0x100ded90 0x18 _g_zPHY_Int2HandleCfg
+ .data 0x100deda8 0x12 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ .data 0x100dedba 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x100dedba 0x1 _G_ZPHY_WORD32_BYTENUM
+ 0x100dedbb 0x1 _G_ZPHY_T_EngPrintMsg_BYTENUM
+ 0x100dedbc 0x1 _G_ZPHY_SIZEOF_WORD32
+ 0x100dedbd 0x1 _G_ZPHY_SIZEOF_WORD16
+ 0x100dedbe 0x1 _G_ZPHY_SIZEOF_T_EngPrintMsg
+ 0x100dedbf 0x1 _G_ZPHY_SIZEOF_T_EngLogHeader
+ 0x100dedc0 0x1 _g_bL1lLogOutUsing
+ .data 0x100dedc1 0x14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ .data 0x100dedd5 0x5d3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x100dedd5 0x60 _G_AC_UL_MODULE_CODE_SCHEME
+ 0x100dee35 0x4 _G_AC_ULS_RV_VALUE
+ 0x100dee39 0x234 _G_AW_ULS_TURBO_INTERLEAVER
+ 0x100df06d 0x46 _G_AC_UL_TDD_HARQ_ID_DATABASE
+ 0x100df0b3 0xa _G_AC_UL_FDD_HARQ_ID_DATABASE
+ 0x100df0bd 0x46 _G_AC_UL_NORM_HARQ_PUSCH_KVALUE
+ 0x100df103 0x46 _G_AC_UL_NORM_HARQ_PHICH_KVALUE
+ 0x100df149 0x46 _G_AC_UL_SPS_SUBFRAMOFFSET
+ 0x100df18f 0x46 _G_AC_UL_PRE_UL_SUBFRAME
+ 0x100df1d5 0xa _G_AC_UL_PRE_UL_SUBFRAME_FDD
+ 0x100df1df 0x46 _G_AC_UL_NEXT_UL_SUBFRAME
+ 0x100df225 0xa _G_AC_UL_NEXT_UL_SUBFRAME_FDD
+ 0x100df22f 0xe _G_AC_MAX_NUM_HARQPROC
+ 0x100df23d 0x2 _G_AC_MAX_NUM_HARQPROC_FDD
+ 0x100df23f 0x46 _G_AC_INTERVAL_BETWEEN_GRANT_SUBFRAME
+ 0x100df285 0xa _G_AC_KPHICH_PROSF_And_RECSF_ULDL0
+ 0x100df28f 0x46 _G_AC_K_MSG3_SENDSF
+ 0x100df2d5 0x46 _G_AC_K_MSG3_SENDSF_ULDLAY
+ 0x100df31b 0x87 _G_AC_ULS_PERMUTATION_COMBINATION
+ 0x100df3a2 0x1 _g_bIsNewTransmit
+ 0x100df3a3 0x1 _g_bUlDlPaternFirst
+ 0x100df3a4 0x1 _g_wSCellActive
+ 0x100df3a5 0x1 _g_bHandOverFlag
+ 0x100df3a6 0x1 _g_bIsRarNewTrans
+ 0x100df3a7 0x1 _g_eHarqIDUpdataState
+ .data 0x100df3a8 0x61 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x100df3a8 0x2 _g_Dcxo_UTC_CO_Info
+ 0x100df3aa 0x5d _g_sdL1lRfcAPCSchedTime
+ 0x100df407 0x1 _g_ReadTpFlagCnt
+ 0x100df408 0x1 _g_sdAtCtl_TxPowerValue
+ .data 0x100df409 0x14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ .data 0x100df41d 0x2e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x100df445 0x1 _g_wL1eRxCrsIIRInd
+ 0x100df446 0x1 _g_wBchUseSoftNoFlag
+ 0x100df447 0x2 _g_sdwRxTemp1
+ 0x100df449 0x2 _g_sdwRxTemp2
+ .data 0x100df44b 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ .data 0x100df45b 0x24c0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ 0x100df45b 0x46 _g_ac_zPHY_edls_TddSubframeType
+ 0x100df4a1 0x1e _g_ac_zPHY_edls_NcpSpeSubfrmCfg
+ 0x100df4bf 0x1b _g_ac_zPHY_edls_EcpSpeSubfrmCfg
+ 0x100df4da 0x4 _g_ac_zPHY_edls_DeltaShiftBw5
+ 0x100df4de 0x4 _g_ac_zPHY_edls_DeltaShiftBw4
+ 0x100df4e2 0x3 _g_ac_zPHY_edls_DeltaShiftBw3
+ 0x100df4e5 0x2 _g_ac_zPHY_edls_DeltaShiftBw2
+ 0x100df4e7 0x2 _g_ac_zPHY_edls_DeltaShiftBw1
+ 0x100df4e9 0x70 _g_ac_zPHY_edls_PrbIndexTabBw5
+ 0x100df559 0x50 _g_ac_zPHY_edls_PrbIndexTabBw4
+ 0x100df5a9 0x36 _g_ac_zPHY_edls_PrbIndexTabBw3
+ 0x100df5df 0x1a _g_ac_zPHY_edls_PrbIndexTabBw2
+ 0x100df5f9 0x10 _g_ac_zPHY_edls_PrbIndexTabBw1
+ 0x100df609 0xc8 _g_ac_zPHY_edls_VrbTabBw5Gap1
+ 0x100df6d1 0xc8 _g_ac_zPHY_edls_VrbTabBw5Gap2
+ 0x100df799 0x96 _g_ac_zPHY_edls_VrbTabBw4Gap1
+ 0x100df82f 0x96 _g_ac_zPHY_edls_VrbTabBw4Gap2
+ 0x100df8c5 0x64 _g_ac_zPHY_edls_VrbTabBw3Gap1
+ 0x100df929 0x64 _g_ac_zPHY_edls_VrbTabBw3Gap2
+ 0x100df98d 0x32 _g_ac_zPHY_edls_VrbTabBw2Gap1
+ 0x100df9bf 0x1e _g_ac_zPHY_edls_VrbTabBw1Gap1
+ 0x100df9dd 0xc _g_ac_zPHY_edls_VrbTabBw0Gap1
+ 0x100df9e9 0x40 _g_ac_zPHY_edls_ModTbsTab
+ 0x100dfa29 0x1734 _g_adw_zPHY_edls_TbsTab
+ 0x100e115d 0x1c0 _g_adw_zPHY_edls_TbsTabDualLayer
+ 0x100e131d 0x20 _g_aw_zPHY_edls_TbsTableDci1C
+ 0x100e133d 0xbc _g_aw_zPHY_edls_TurboParaK
+ 0x100e13f9 0x20 _g_aw_zPHY_edls_PcInfoAnt2Dci2
+ 0x100e1419 0x100 _g_aw_zPHY_edls_PcInfoAnt4Dci2
+ 0x100e1519 0x8 _g_ac_zPHY_edls_PcInfoAnt4Dci2A
+ 0x100e1521 0x7 _g_ac_zPHY_edls_MaxDlHarqProNum
+ 0x100e1528 0x7 _g_ac_zPHY_edls_DlHarqProNumMin
+ 0x100e152f 0x46 _g_ac_zPHY_edls_TddDlHarqCapM
+ 0x100e1575 0x46 _g_ac_zPHY_edls_TddDlHarqCapM_TddFddCA
+ 0x100e15bb 0x46 _g_ac_zPHY_edls_TddDlHarqTiming
+ 0x100e1601 0x46 _g_ac_zPHY_edls_TddDlHarqTiming_TddFddCA
+ 0x100e1647 0x46 _g_ac_zPHY_edls_TddDlHarqOrder
+ 0x100e168d 0x46 _g_ac_zPHY_edls_TddDlHarqOrder_TddFddCA
+ 0x100e16d3 0x46 _g_ac_zPHY_edls_TddDlHarqSetK
+ 0x100e1719 0xa _g_ac_zPHY_edls_FddDlHarqTiming
+ 0x100e1723 0x8 _awRohAPowerTable1ForSinglePort
+ 0x100e172b 0xa _awRohAPowerTable1
+ 0x100e1735 0x8 _awRohAVoltageTable1SinglePort
+ 0x100e173d 0xa _awRohAVoltageTable1
+ 0x100e1747 0x20 _awRohBPowerTable1ForSinglePort
+ 0x100e1767 0x20 _awRohBVoltageTable1SinglePort
+ 0x100e1787 0x28 _awRohBPowerTable2
+ 0x100e17af 0x28 _awRohBVoltageTable2
+ 0x100e17d7 0xa _awRohAPowerTable2
+ 0x100e17e1 0xa _awRohAVoltageTable2
+ 0x100e17eb 0x28 _awRohBPowerTable4
+ 0x100e1813 0x28 _awRohBVoltageTable4
+ 0x100e183b 0x8 _g_wLteL1MultiPortPA3dBRouAPow
+ 0x100e1843 0x20 _g_wLteL1MultiPortPA3dBRouBPow
+ 0x100e1863 0x8 _g_wLteL1MultiPortPA3dBRouAVol
+ 0x100e186b 0x20 _g_wLteL1MultiPortPA3dBRouBVol
+ 0x100e188b 0x8 _g_wLteL1MultiPortPA6dBRouAPow
+ 0x100e1893 0x20 _g_wLteL1MultiPortPA6dBRouBPow
+ 0x100e18b3 0x8 _g_wLteL1MultiPortPA6dBRouAVol
+ 0x100e18bb 0x20 _g_wLteL1MultiPortPA6dBRouBVol
+ 0x100e18db 0x20 _g_wLteL1MultiPortPA6dBRouBVolTable
+ 0x100e18fb 0x20 _g_wLteL1MultiPortPA6dBRouBPowTable
+ .data 0x100e191b 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ .data 0x100e191f 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ .data 0x100e1929 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .data 0x100e192b 0x27c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x100e192b 0x13 _g_tzPHY_eulpc_At2UlPc
+ 0x100e193e 0x2 _g_zPHY_emc_dwIcpArm1CtrlInfoRegAddr
+ 0x100e1940 0x266 _g_ateMcMsgTable
+ 0x100e1ba6 0x1 _g_bPchReportFlag
+ .data 0x100e1ba7 0x20 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x100e1bc3 0x4 _g_zPHY_tLpcPwrDomainState
+ .data 0x100e1bc7 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ .data 0x100e1bd5 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ *fill* 0x100e1bd7 0x80000001 00
+ .data 0x100e1bd8 0xa82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x100e1bd8 0x800 _g_adw_Drv_Rx_CosineCoeff
+ 0x100e23d8 0x31 _g_aw_Drv_Rx_FiTriangleCoeff
+ 0x100e2409 0x62 _g_adw_Drv_Rx_FixedFirCoeff
+ 0x100e246b 0x62 _g_adw_Drv_Rx_Eicic_FixedFirCoeff
+ 0x100e24cd 0x62 _g_adw_Drv_Rx_FixFirCoeff_16QAM
+ 0x100e252f 0x62 _g_adw_Drv_Rx_FixFirCoeff_64QAM
+ 0x100e2591 0x62 _g_aw_Drv_FiCoeffPrbBundling
+ 0x100e25f3 0x66 _g_adwL1eDrvRxMbsfnFirCoeff
+ 0x100e2659 0x1 _g_wL1eDrvRxFirCoeffFormatInd
+ .data 0x100e265a 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ .data 0x100e265c 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ .data 0x100e2660 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ *fill* 0x100e2666 0x80000002 00
+ .data 0x100e2668 0x229 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x100e2668 0x80 _g_zPHY_erfc_atDBBMainSyncEvent
+ 0x100e26e8 0x80 _g_zPHY_erfc_atDBBMeas0Event
+ 0x100e2768 0x20 _g_zPHY_erfc_atDBBTxSendEvent
+ 0x100e2788 0x24 _g_zPHY_erfc_SubframeStartAddr
+ 0x100e27ac 0x24 _g_zPHY_erfc_SubframeDDRBackUpStartAddr
+ 0x100e27d0 0x8 _g_atzPHY_erfc_TuRegTxEvent
+ 0x100e27d8 0xb9 _g_atzPHY_erfc_TuRamTxEvent
+ *fill* 0x100e2891 0x80000003 00
+ .data 0x100e2894 0xb54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x100e2894 0x400 _g_atzPHY_erfc_atRFABBMainSyncEvent
+ 0x100e2c94 0x200 _g_atzPHY_erfc_atRFABBMeas0Event
+ 0x100e2e94 0x554 _g_atzPHY_erfc_atRFABBTxSendEvent
+ .data 0x100e33e8 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100e33e8 0x1 _g_zPHY_erfc_cTddOrFddTemp
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+ 0x100e7450 0xbe _GainValueConfig_TDD
+ 0x100e750e 0xbe _GainValueConfig_FDD
+ .data 0x100e75cc 0x7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ 0x100e75cc 0x7 _g_pcZcosVersion
+ .data 0x100e75d3 0x4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ 0x100e75d3 0x4 _gtHuntList
+ .data 0x100e75d7 0x2 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ 0x100e75d7 0x2 _efuseMutex
+ .data 0x100e75d9 0x2 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(errno.o)
+ 0x100e75d9 0x1 _errno
+ 0x100e75da 0x1 _ierrno
+ .data 0x100e75db 0xb3 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o)
+ .data 0x100e768e 0x3 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_data.o)
+ 0x100e768e 0x1 _floatx80_rounding_precision
+ 0x100e768f 0x1 _float_detect_tininess
+ 0x100e7690 0x1 _float_rounding_mode
+ .data 0x100e7691 0x101 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ctype.o)
+ 0x100e7691 0x101 ___ctype
+ .data 0x100e7792 0x4 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pr_routines.o)
+ 0x100e7792 0x2 _ZSP_get_cycle_ZSP_overridePtr
+ 0x100e7794 0x2 _ZSP_get_insn_ZSP_overridePtr
+ 0x100e7796 __incsram_loadaddr = .
+ 0x100e7796 0x2 LONG 0x8074000 (<code 338> (LOADADDR (.itcm)) / 0x2)
+ 0x100e7798 __incsram_size = .
+ 0x100e7798 0x2 LONG 0x371c (SIZEOF (.itcm) / 0x2)
+ 0x100e779a __dncsram_loadaddr = .
+ 0x100e779a 0x2 LONG 0x8078000 (<code 338> (LOADADDR (.dtcm)) / 0x2)
+ 0x100e779c __dncsram_size = .
+ 0x100e779c 0x2 LONG 0x31fd (SIZEOF (.dtcm) / 0x2)
+ 0x100e779e __L2_code_s_loadaddr = .
+ 0x100e779e 0x2 LONG 0x8053f18 (<code 338> (LOADADDR (.c2tcm_s)) / 0x2)
+ 0x100e77a0 __L2_code_s_size = .
+ 0x100e77a0 0x2 LONG 0x4 (SIZEOF (.c2tcm_s) / 0x2)
+ 0x100e77a2 __L2_code_d_loadaddr = .
+ 0x100e77a2 0x2 LONG 0x8053f20 (<code 338> (LOADADDR (.c2tcm_d)) / 0x2)
+ 0x100e77a4 __L2_code_d_size = .
+ 0x100e77a4 0x2 LONG 0x4 (SIZEOF (.c2tcm_d) / 0x2)
+ 0x100e77a6 __L2_code_d_loadaddr_update1 = .
+ 0x100e77a6 0x2 LONG 0x8053f28 (<code 338> (LOADADDR (.c2tcm_d_update1)) / 0x2)
+ 0x100e77a8 __L2_code_d_size_update1 = .
+ 0x100e77a8 0x2 LONG 0x4 (SIZEOF (.c2tcm_d_update1) / 0x2)
+ 0x100e77aa __L2_code_d_loadaddr_update2 = .
+ 0x100e77aa 0x2 LONG 0x8053f30 (<code 338> (LOADADDR (.c2tcm_d_update2)) / 0x2)
+ 0x100e77ac __L2_code_d_size_update2 = .
+ 0x100e77ac 0x2 LONG 0x4 (SIZEOF (.c2tcm_d_update2) / 0x2)
+ 0x100e77ae __L2_data_s_loadaddr = .
+ 0x100e77ae 0x2 LONG 0x8053f38 (<code 338> (LOADADDR (.d2tcm_s)) / 0x2)
+ 0x100e77b0 __L2_data_s_size = .
+ 0x100e77b0 0x2 LONG 0xa (SIZEOF (.d2tcm_s) / 0x2)
+ 0x100e77b2 __L2_data_d_loadaddr = .
+ 0x100e77b2 0x2 LONG 0x8053f48 (<code 338> (LOADADDR (.d2tcm_d)) / 0x2)
+ 0x100e77b4 __L2_data_d_size = .
+ 0x100e77b4 0x2 LONG 0x0 (SIZEOF (.d2tcm_d) / 0x2)
+ 0x100e77b6 __L2_data_d_loadaddr_update1 = .
+ 0x100e77b6 0x2 LONG 0x8053f50 (<code 338> (LOADADDR (.d2tcm_d_update1)) / 0x2)
+ 0x100e77b8 __L2_data_d_size_update1 = .
+ 0x100e77b8 0x2 LONG 0x0 (SIZEOF (.d2tcm_d_update1) / 0x2)
+ 0x100e77ba __L2_data_d_loadaddr_update2 = .
+ 0x100e77ba 0x2 LONG 0x8053f58 (<code 338> (LOADADDR (.d2tcm_d_update2)) / 0x2)
+ 0x100e77bc __L2_data_d_size_update2 = .
+ 0x100e77bc 0x2 LONG 0x0 (SIZEOF (.d2tcm_d_update2) / 0x2)
+ 0x100e77be __lp_text_addr = .
+ 0x100e77be 0x2 LONG 0x8053e00 (<code 338> (ADDR (.lp_text)) / 0x2)
+ 0x100e77c0 __lp_text_loadaddr = .
+ 0x100e77c0 0x2 LONG 0x8053e00 (<code 338> (LOADADDR (.lp_text)) / 0x2)
+ 0x100e77c2 __lp_text_size = .
+ 0x100e77c2 0x2 LONG 0x112 (SIZEOF (.lp_text) / 0x2)
+
+.display
+ *(.display_data_buffer)
+
+.save_zsp 0x100e77d0 0x100
+ *(.save_zsp_data)
+ .save_zsp_data
+ 0x100e77d0 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+
+.bss 0x100e78d0 0x672a3 load address 0x100e78d0
+ 0x100e78d0 ___bss_start = .
+ *(.bss)
+ .bss 0x100e78d0 0x19 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ .bss 0x100e78e9 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ .bss 0x100e7929 0x22c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ .bss 0x100e7b55 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ .bss 0x100e7b95 0x8d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ .bss 0x100e7c22 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ .bss 0x100e7c23 0x77d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ .bss 0x100e83a0 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ .bss 0x100e83bf 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ .bss 0x100e83c0 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ .bss 0x100e83c3 0x6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ .bss 0x100e83c9 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ .bss 0x100e83ca 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ .bss 0x100e840a 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ .bss 0x100e840b 0x22dd T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ .bss 0x100ea6e8 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ .bss 0x100ea6ec 0x29c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ .bss 0x100ea988 0x14d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ .bss 0x100eaad5 0x2c3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ .bss 0x100ed711 0xbd2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ *fill* 0x100ee2e3 0x80000001 00
+ .bss 0x100ee2e4 0xec7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ .bss 0x100ef1ab 0x2ef T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ .bss 0x100ef49a 0x8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ .bss 0x100ef4a2 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ .bss 0x100ef4a3 0x1b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ .bss 0x100ef4be 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ .bss 0x100ef4c1 0x439 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ .bss 0x100ef8fa 0xf85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ .bss 0x100f087f 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
+ .bss 0x100f0881 0x2ef T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ .bss 0x100f0b70 0x392 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ .bss 0x100f0f02 0x43a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ .bss 0x100f133c 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ .bss 0x100f133f 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ .bss 0x100f1340 0x259c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ .bss 0x100f38dc 0x1d2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ .bss 0x100f3aae 0x564 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ .bss 0x100f4012 0x1e1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ .bss 0x100f41f3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ .bss 0x100f41f4 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ .bss 0x100f41f7 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ .bss 0x100f41fd 0x981 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ .bss 0x100f4b7e 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ .bss 0x100f4ba2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ .bss 0x100f4ba3 0x82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ .bss 0x100f4c25 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ *fill* 0x100f4c27 0x80000001 00
+ .bss 0x100f4c28 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ .bss 0x100f4c6d 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ .bss 0x100f4c70 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ .bss 0x100f4c72 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ .bss 0x100f4c76 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ .bss 0x100f4c77 0x234 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .bss 0x100f4eab 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ .bss 0x100f4eb3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ .bss 0x100f4eb4 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ .bss 0x100f4eb6 0x72 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ .bss 0x100f4f28 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ .bss 0x100f4f2a 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ .bss 0x100f4f7a 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ .bss 0x100f4f7d 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ .bss 0x100f4f7e 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ .bss 0x100f4f80 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ *(COMMON)
+ COMMON 0x100f4fb4 0x6 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x0 (size before relaxing)
+ 0x100f4fb4 0x6 _err_msg
+ COMMON 0x100f4fba 0x18f T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x0 (size before relaxing)
+ 0x100f4fba 0x18f _odo_sys
+ COMMON 0x100f5149 0x44 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x0 (size before relaxing)
+ 0x100f5149 0x1 _zsp_cmm_len
+ 0x100f514a 0x5 _g_L1ErrInfo
+ 0x100f514f 0x3e _zsp_ramdump_regs
+ COMMON 0x100f518d 0x364 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x0 (size before relaxing)
+ 0x100f518d 0x1 _g_erfc_cnt
+ 0x100f518e 0x302 _g_atHookInfo
+ 0x100f5490 0x60 _g_erfc_tpu
+ 0x100f54f0 0x1 _gIramHookCnt
+ COMMON 0x100f54f1 0x1c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x0 (size before relaxing)
+ 0x100f54f1 0x1 _g_wRficRev
+ 0x100f54f2 0x1b _g_awTempDAC
+ COMMON 0x100f550d 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x0 (size before relaxing)
+ 0x100f550d 0x1a _g_tL1wCallStackInfo
+ COMMON 0x100f5527 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x0 (size before relaxing)
+ 0x100f5527 0x1 _g_uComPhyFunc
+ COMMON 0x100f5528 0xd00 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x0 (size before relaxing)
+ 0x100f5528 0x100 _gReadBlockCnt
+ 0x100f5628 0x100 _RpMsgRead_Exit
+ 0x100f5728 0x100 _gWriteBlockCnt
+ 0x100f5828 0x100 _gRpMsgWriteMutex
+ 0x100f5928 0x100 _s_RpMsgCallbackList
+ 0x100f5a28 0x300 _phy2ps_chinfo
+ 0x100f5d28 0x100 _rpMsgSem
+ 0x100f5e28 0x300 _ps2phy_chinfo
+ 0x100f6128 0x100 _gRpMsgReadMutex
+ COMMON 0x100f6228 0x9 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x0 (size before relaxing)
+ 0x100f6228 0x2 _g_L1_tModeState
+ 0x100f622a 0x6 _g_L1_tLpmCaliTime
+ 0x100f6230 0x1 _g_L1_tLpCalibrationFlag
+ COMMON 0x100f6231 0xd T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x0 (size before relaxing)
+ 0x100f6231 0x9 _g_L1wPriTaskPid
+ 0x100f623a 0x4 _g_L1wIsrTaskPid
+ COMMON 0x100f623e 0xc9e6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x0 (size before relaxing)
+ 0x100f623e 0xbec _g_tWcdmaUserNv
+ 0x100f6e2a 0x22c _g_tL1wNvBb
+ 0x100f7056 0xbbca _g_tWcdmaCalibNv
+ 0x10102c20 0x4 _g_tL1wAtNv
+ COMMON 0x10102c24 0x427 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x0 (size before relaxing)
+ 0x10102c24 0x3eb _g_tL1wDevMeasInfo
+ 0x1010300f 0x3c _g_atMeasSpsrInfo
+ COMMON 0x1010304b 0x5b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x0 (size before relaxing)
+ 0x1010304b 0x4e4 _s_tL1wDevHsupaInfo
+ 0x1010352f 0xcf _g_PsrUpdateReq
+ COMMON 0x101035fe 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x0 (size before relaxing)
+ 0x101035fe 0x1 _g_SSC_CFLT_chip
+ 0x101035ff 0x14 _g_tRfcNotchInfo
+ 0x10103613 0x24 _g_tWRfcRpiPwrCtl
+ 0x10103637 0x1 _g_wRfcResetState
+ 0x10103638 0x1 _g_SSC_CFLT_ssfn
+ 0x10103639 0x2 _g_zPHYRfcSSCDebugCnt
+ COMMON 0x1010363b 0x13e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x0 (size before relaxing)
+ 0x1010363b 0x48 _tPcDataDb
+ 0x10103683 0x62 _tPcCnt
+ 0x101036e5 0x94 _g_tPcDpchSirCalInfo
+ COMMON 0x10103779 0x113 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x0 (size before relaxing)
+ 0x10103779 0x2 _g_Rt
+ 0x1010377b 0x11 _g_tL1wHsdpaSnrAdjInfo
+ 0x1010378c 0x36 _g_tHsdpaAdrIcRstInfo
+ 0x101037c2 0x6 _g_tL1wHsdpaDbgInfo
+ 0x101037c8 0x78 _g_tL1wHsdpaPacketInfo
+ 0x10103840 0x19 _g_tHsdpaIcFingerDiffInfo
+ 0x10103859 0x1 _g_wAdrIcEn
+ 0x1010385a 0x26 _g_tL1wHsdpaCodingInfo
+ 0x10103880 0x1 _g_wL1wHsdpaRxDivMode
+ 0x10103881 0xb _g_tHsdpaResetInfo
+ COMMON 0x1010388c 0x191 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x0 (size before relaxing)
+ 0x1010388c 0x168 _g_atLessDecodeCfg
+ 0x101039f4 0x28 _g_atLessDemoluleCfg
+ 0x10103a1c 0x1 _g_wL1wLessCfgIdx
+ COMMON 0x10103a1d 0x1b6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x0 (size before relaxing)
+ 0x10103a1d 0x1b6 _g_tUlRfTbl
+ COMMON 0x10103bd3 0x26c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x0 (size before relaxing)
+ 0x10103bd3 0x26c _g_tWuldataBuf
+ COMMON 0x10103e3f 0x624 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x0 (size before relaxing)
+ 0x10103e3f 0x604 _g_uLSfInfo
+ 0x10104443 0x20 _g_atL1wHsupaFirstTranPara
+ COMMON 0x10104463 0xd06 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x0 (size before relaxing)
+ 0x10104463 0x12 _g_tRfcPowerAdcReadInfo
+ 0x10104475 0x5a _g_atRfcAgcDbLog
+ 0x101044cf 0x1 _g_eAntSel
+ 0x101044d0 0x1 _g_bNvCheck
+ 0x101044d1 0x1 _g_wRfcTxRxState
+ 0x101044d2 0x318 _g_tRfcCtrlDbRx
+ 0x101047ea 0x26 _g_tRfcGapMixLog
+ 0x10104810 0x5df _g_tRfcAgcDb
+ 0x10104def 0x1e _g_atRfcStateLog
+ 0x10104e0d 0x1 _g_eDivState
+ 0x10104e0e 0xb _g_tRfcAfcDb
+ 0x10104e19 0x1 _g_eAntState
+ 0x10104e1a 0x318 _g_tRfcCtrlDbTx
+ 0x10105132 0x23 _g_tRfcCmnInfoLOG
+ 0x10105155 0xe _g_tRfcTxPowLog
+ 0x10105163 0x5 _g_tRfcTmpReadInfo
+ 0x10105168 0x1 _g_eRfcRamState
+ COMMON 0x10105169 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x0 (size before relaxing)
+ 0x10105169 0x4 _g_wAdrIcCellState
+ 0x1010516d 0x1 _g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1010516e 0x5 _g_awL1wHsdpaMvalue
+ 0x10105173 0x4 _g_wSubFrmOffset
+ 0x10105177 0x1 _g_wL1wHsdpaHsdpcchUldpcchOffset
+ 0x10105178 0xf _g_awL1wHsdpaCfnSlot2SfnSubFrm
+ 0x10105187 0x1 _g_wL1wHsdpaSfnCfnOffset
+ COMMON 0x10105188 0x2824 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x0 (size before relaxing)
+ 0x10105188 0x24 _s_tCsStatisticInfo
+ 0x101051ac 0x2800 _dwPeakInfoInSlot
+ COMMON 0x101079ac 0xc5d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x0 (size before relaxing)
+ 0x101079ac 0x26 _g_tPcUphDb
+ 0x101079d2 0x3e _tDevEngStardardParam
+ 0x10107a10 0x559 _g_tPcOverEstDb
+ 0x10107f69 0x3e3 _tPcBetaDb
+ 0x1010834c 0xa _swPcTimeOff
+ 0x10108356 0x1 _wTimeOff
+ 0x10108357 0xa _swPcTimeOff2
+ 0x10108361 0x95 _tPcCalcDb
+ 0x101083f6 0x2 _g_tIqMappingCon
+ 0x101083f8 0x146 _tPcInfoDb
+ 0x1010853e 0xcb _tMprTest
+ COMMON 0x10108609 0x286 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x0 (size before relaxing)
+ 0x10108609 0x4 _g_awL1wStandardMsgRpt
+ 0x1010860d 0x80 _g_awL1wPrintMsgProcRpt
+ 0x1010868d 0x2 _gL1w_MissLogInfo
+ 0x1010868f 0x200 _g_awL1wEngTempBuffer
+ COMMON 0x1010888f 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x0 (size before relaxing)
+ 0x1010888f 0x5 _g_RxDataPn9Check
+ 0x10108894 0x2 _g_dwCfgSsfn
+ 0x10108896 0x1 _g_RxTtiNum
+ 0x10108897 0x1 _g_RxTfciNum
+ 0x10108898 0x2 _g_dwTtiSsfn
+ COMMON 0x1010889a 0x11c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x0 (size before relaxing)
+ 0x1010889a 0xe _g_tWUpaStdlogStatisitcInfo
+ 0x101088a8 0x2 _g_EdchNewTbTotal
+ 0x101088aa 0x20 _g_atWHsupaEhichInfTab
+ 0x101088ca 0x1 _g_EagchCnt500Ms
+ 0x101088cb 0x38 _g_tWUpaStdlogPacketInfo
+ 0x10108903 0x2 _g_EdchTbTotal
+ 0x10108905 0x10 _g_atWHsupaEdchReadyFlag
+ 0x10108915 0x36 _g_tWUpaUlDebugInfo
+ 0x1010894b 0x6b _g_tWUpaDlDebugInfo
+ COMMON 0x101089b6 0x11b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x0 (size before relaxing)
+ 0x101089b6 0xc _g_atL1wCellType
+ 0x101089c2 0x2f _g_tL1wMeasCellReq
+ 0x101089f1 0x24 _g_atL1wRlsTrace
+ 0x10108a15 0x8 _g_tL1wFmoDlsPsrParaConfig
+ 0x10108a1d 0x2 _g_tL1wPsrAntNumPara
+ 0x10108a1f 0x2 _g_dIntIndex
+ 0x10108a21 0xe _g_tL1wCmPsrPatternInfo
+ 0x10108a2f 0x1 _g_wL1wDpchOffset
+ 0x10108a30 0x2f _g_tL1wDchDlsLastReq
+ 0x10108a5f 0x2f _g_tL1wDchDlsPsrReq
+ 0x10108a8e 0x6 _g_asL1wAdujstFlag
+ 0x10108a94 0x4 _g_tL1wHsupaRlToPsr
+ 0x10108a98 0x7 _g_tL1wFachDlsPsrReq
+ 0x10108a9f 0x1 _g_sL1wUlAdujstFlag
+ 0x10108aa0 0x2 _g_dOldUlTiming
+ 0x10108aa2 0x2f _g_tL1wDpaRlReqInfo
+ COMMON 0x10108ad1 0xec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x0 (size before relaxing)
+ 0x10108ad1 0xe8 _g_tResInfo
+ 0x10108bb9 0x4 _g_tSendIcpTpuTime
+ COMMON 0x10108bbd 0x163 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x0 (size before relaxing)
+ 0x10108bbd 0x106 _g_tL1wAfcFreqOffsetValue
+ 0x10108cc3 0x30 _g_atL1wRxHistoryIQBuffer
+ 0x10108cf3 0x3 _g_tAfcErrorPrint
+ 0x10108cf6 0x20 _g_tL1wAfcWorkPara
+ 0x10108d16 0x6 _g_tL1wSlaveAfcWorkPara
+ 0x10108d1c 0x4 _g_tL1wBchDataHistoryIQValue
+ COMMON 0x10108d20 0xe47 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x0 (size before relaxing)
+ 0x10108d20 0x1a _g_adL1wTpuTaskID
+ 0x10108d3a 0x235 _g_atL1wTpuRegRtVarEventInfo
+ 0x10108f6f 0x4db _g_atL1wTpuRegNtVarEventInfo
+ 0x1010944a 0x4 _g_tL1wTpuLastMicroAdjustInfo
+ 0x1010944e 0x1 _g_wL1wTpuDoffVal
+ 0x1010944f 0x8 _g_tL1wTpuFrmInfo
+ 0x10109457 0x710 _g_atL1wTpuRegNtFixedEventInfo
+ *fill* 0x10109b67 0x80000001 00
+ COMMON 0x10109b68 0x427f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x0 (size before relaxing)
+ 0x10109b68 0x7c _g_tL1wDevDbHsdpaCfgReqB
+ 0x10109be4 0x7a _g_atDevBchAfcdb
+ 0x10109c5e 0x3d6 _g_tL1wDevDbUlDpchCfgReqA
+ 0x1010a034 0x7c _g_tL1wDevDbHsdpaCfgReqA
+ 0x1010a0b0 0x41c _g_tL1wDevDbRtxIscpInfo
+ 0x1010a4cc 0x4 _g_tL1wDevDbRaMacProcReq
+ 0x1010a4d0 0x7e _g_tL1wDevDbDlFdpchCfgReqA
+ 0x1010a54e 0xf8 _g_tDevDbHsupaCfgReqB
+ 0x1010a646 0x382 _g_tL1wDevDbPageFachCfgReq
+ 0x1010a9c8 0x2 _g_tL1wDevDbTrchTtiInfo
+ 0x1010a9ca 0xf8 _g_tDevDbHsupaCfgReqA
+ 0x1010aac2 0x39a _g_tL1wDevDbRaEraRrcReq
+ 0x1010ae5c 0x5 _g_tL1wDevDbHsdpaInd
+ 0x1010ae61 0x880 _g_tDevDbHsdpaFingMaskBuffer
+ 0x1010b6e1 0x27 _g_tDevDbHspaToMacInfo
+ 0x1010b708 0x200 _g_tDevDbHsdpaAdrCirData
+ 0x1010b908 0x1a70 _g_tL1wDevDbRtxAfcInfo
+ 0x1010d378 0xb _g_tDevDbHsdpaAntSwitch
+ 0x1010d383 0x62 _g_tL1wDevDbHsdpaPlusPchCfgReq
+ 0x1010d3e5 0x4be _g_tL1wDevDbDlDpchCfgReqA
+ 0x1010d8a3 0x544 _g_tWDevDbHspaPlusFachCfgReq
+ COMMON 0x1010dde7 0x85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010dde7 0x3b _g_tRxEng
+ 0x1010de22 0x4a _g_tDlCpchEng
+ COMMON 0x1010de6c 0x86 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x0 (size before relaxing)
+ 0x1010de6c 0x4 _g_tRfcIQInfo
+ 0x1010de70 0x2 _g_sdAnt0CarrierPhase
+ 0x1010de72 0x78 _g_atRfcDcLog
+ 0x1010deea 0x2 _g_sdAnt1CarrierPhase
+ 0x1010deec 0x4 _g_tRfcDcInfo
+ 0x1010def0 0x2 _g_tRfcDagcGain
+ COMMON 0x1010def2 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x0 (size before relaxing)
+ 0x1010def2 0x38 _g_TopRegLpcSave
+ COMMON 0x1010df2a 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x0 (size before relaxing)
+ 0x1010df2a 0xa _g_wTpuRtRegLpcSave
+ 0x1010df34 0x36 _g_wTpuNtRegLpcSave
+ COMMON 0x1010df6a 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x0 (size before relaxing)
+ 0x1010df6a 0xd0 _g_atL1wDrvMeasResultInfo
+ COMMON 0x1010e03a 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x0 (size before relaxing)
+ 0x1010e03a 0x2 _g_dL1wDprICPSSFN
+ 0x1010e03c 0x1 _g_wLastSubframe
+ 0x1010e03d 0x1 _g_wL1wDprModState
+ 0x1010e03e 0x26 _g_tL1wDrvDpramStruct
+ 0x1010e064 0x2 _g_dL1wDprResetCnfSSFN
+ 0x1010e066 0x2 _g_wL1wDprSubFrmCnt
+ 0x1010e068 0xa _g_awReportCFN
+ COMMON 0x1010e072 0x808 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010e072 0x808 _s_tDrvRxCfg
+ COMMON 0x1010e87a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010e87a 0x7b8 _g_tRegRxRakeReg
+ COMMON 0x1010f032 0x7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x0 (size before relaxing)
+ 0x1010f032 0x1 _wLastBand
+ 0x1010f033 0x2 _g_l1wATSetAPCTmpCmpVal
+ 0x1010f035 0x2 _g_l1wATOriAPCTmpCmpVal
+ 0x1010f037 0x2 _g_l1wATSetAPCFlag
+ COMMON 0x1010f039 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x0 (size before relaxing)
+ 0x1010f039 0x1 _g_TxCfgOver
+ 0x1010f03a 0x1 _g_TpuCfgOver
+ COMMON 0x1010f03b 0x415 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x0 (size before relaxing)
+ 0x1010f03b 0x3a _g_tRfcDrvOpen
+ 0x1010f075 0x1 _g_wRfOpCnt
+ 0x1010f076 0x3a _g_atLastRfcOpen
+ 0x1010f0b0 0x3a0 _g_atRfcOpen
+ COMMON 0x1010f450 0xa3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ 0x0 (size before relaxing)
+ 0x1010f450 0xa3 _g_tL1wInnerCellDb
+ COMMON 0x1010f4f3 0x8f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ 0x0 (size before relaxing)
+ 0x1010f4f3 0x19 _g_tL1wCtrlDb
+ 0x1010f50c 0x1c _g_tL1MainMixInfo
+ 0x1010f528 0x1 _g_eL1wAmtL1sStateInfo
+ 0x1010f529 0x1a _g_tL1wStateCnt
+ 0x1010f543 0x3f _g_tL1wProcSetDb
+ COMMON 0x1010f582 0xf4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ 0x0 (size before relaxing)
+ 0x1010f582 0x1 _g_wBackupCellMainIdx
+ 0x1010f583 0x79 _g_tServCellDb
+ 0x1010f5fc 0x60 _g_atBackupCellInfo
+ 0x1010f65c 0x1a _g_tL1wAddionCtrl
+ COMMON 0x1010f676 0xa1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ 0x0 (size before relaxing)
+ 0x1010f676 0xa1 _g_tWL1sHsupaProcInfo
+ COMMON 0x1010f717 0x350 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ 0x0 (size before relaxing)
+ 0x1010f717 0x5a _g_tL1wCmCfnN0123Bitmap
+ 0x1010f771 0x78 _g_atL1wCmWaitCfgPatternDB
+ 0x1010f7e9 0x5a _g_tL1wCmCfnN0123BitmapTemp
+ 0x1010f843 0xdc _g_tL1wCmInnerInfo
+ 0x1010f91f 0xca _g_tL1wCmInfoForN4N9
+ 0x1010f9e9 0x7e _g_tL1wPsCmConfigBuffer
+ COMMON 0x1010fa67 0x339 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ 0x0 (size before relaxing)
+ 0x1010fa67 0xa0 _g_atL1RfSegInfo
+ 0x1010fb07 0x4 _g_tTimerCnt
+ 0x1010fb0b 0x2 _g_tL1wResCtrl
+ 0x1010fb0d 0x28f _g_tL1wRfTbl
+ 0x1010fd9c 0x3 _g_tL1wResAgcCtrl
+ 0x1010fd9f 0x1 _g_wRfSegNum
+ COMMON 0x1010fda0 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ 0x0 (size before relaxing)
+ 0x1010fda0 0x33 _g_tDchAscPara
+ COMMON 0x1010fdd3 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd3 0x1 _g_RxRachAiNum
+ 0x1010fdd4 0x1 _g_RxAichIntCnt
+ COMMON 0x1010fdd5 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd5 0x1 _g_wMissHdtrInt
+ COMMON 0x1010fdd6 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd6 0x5 _g_tPcPrachConfigInfo
+ 0x1010fddb 0x1 _g_swPrachSlotPower
+ 0x1010fddc 0x13 _g_tRtxPcPrachMessageInfo
+ COMMON 0x1010fdef 0x18 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010fdef 0x18 _g_atL1wHsupaDlCmPattern
+ COMMON 0x1010fe07 0x1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x0 (size before relaxing)
+ 0x1010fe07 0x4 _g_L1LteAIsrTaskPid
+ 0x1010fe0b 0x2 _g_pSemId_INTH1
+ 0x1010fe0d 0x11 _g_L1LteAPriTaskPid
+ 0x1010fe1e 0x2 _g_pSemId_ICP
+ 0x1010fe20 0x2 _g_pSemId_TXIntPulse
+ 0x1010fe22 0x2 _g_pSemId_INTH2
+ COMMON 0x1010fe24 0x2bf08 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x0 (size before relaxing)
+ 0x1010fe24 0x8 _g_tUEIdInfo
+ 0x1010fe2c 0x28000 _g_zPHY_AMT_tNVInfo
+ 0x10137e2c 0x2540 _g_zPHY_tNVInfo
+ 0x1013a36c 0x198c _g_zPHY_tNV_user
+ 0x1013bcf8 0x2e _g_zPsPhyATNvLte
+ 0x1013bd26 0x6 _g_zPsPhyATNvcom
+ COMMON 0x1013bd2c 0xe5b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x0 (size before relaxing)
+ 0x1013bd2c 0x158 _g_EUL_SrsStatisticsInfo
+ 0x1013be84 0x136 _g_EDL_PDSCH_INFO
+ 0x1013bfba 0x2 _g_dwUlResidualBlerCount
+ 0x1013bfbc 0xb8 _g_EUL_CqiHarqSimulStatisticsInfo
+ 0x1013c074 0x2 _g_EDL_PA_INFO
+ 0x1013c076 0xc _g_UL_SrHarqSimulStatisticsInfo
+ 0x1013c082 0x2a _g_UE_BASE_INFO
+ 0x1013c0ac 0x4 _g_dwTxThroughPutBps
+ 0x1013c0b0 0x72 _g_EDL_PCFICH_INFO
+ 0x1013c122 0x82 _g_EUL_Dci0Info
+ 0x1013c1a4 0x10e _g_EDL_PHICH_INFO
+ 0x1013c2b2 0x4 _g_dwUlNewTransCount
+ 0x1013c2b6 0x8 _g_EUL_DCI3Or3AInfo
+ 0x1013c2be 0x230 _g_EDL_DCI_INFO
+ 0x1013c4ee 0x4 _g_dwRxThroughPutBps
+ 0x1013c4f2 0x40 _g_EDL_CALC_For_SINR
+ 0x1013c532 0x12 _g_EDLUL_FLOW_INFO
+ 0x1013c544 0x20 _g_EUL_PucchFmtStatisticsInfo
+ 0x1013c564 0x44 _g_UL_MutiplexingANStatisticsInfo
+ 0x1013c5a8 0x9a _g_EDL_HARQ_INFO
+ 0x1013c642 0x52 _g_EUL_HarqTransStatisticsInfo
+ 0x1013c694 0x3c _g_EDL_WORK_INFO
+ 0x1013c6d0 0x22 _g_EUL_AT_INFO
+ 0x1013c6f2 0x3c _g_EUL_BunldingANStatisticsInfo
+ 0x1013c72e 0x52 _g_EUL_PowerCtrlInfo
+ 0x1013c780 0x2d0 _g_EDL_PDCCH_INFO
+ 0x1013ca50 0x2 _gdwUlTmtFlowCount
+ 0x1013ca52 0x54 _g_EDL_AT_INFO
+ 0x1013caa6 0x2 _g_TmtLogCnt
+ 0x1013caa8 0x2 _gdwTmtFlowCount
+ 0x1013caaa 0xd9 _g_EUL_PrachStatisticsInfo
+ 0x1013cb83 0x4 _g_dwUlHarqFailCount
+ COMMON 0x1013cb87 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x0 (size before relaxing)
+ 0x1013cb87 0x4 _gt_CsiPrintCtrl
+ 0x1013cb8b 0x1 _g_wLastAbsSfn
+ 0x1013cb8c 0x1 _g_wCsiWorkFlg
+ COMMON 0x1013cb8d 0x16 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x0 (size before relaxing)
+ 0x1013cb8d 0x4 _g_adwTbCbCrc
+ 0x1013cb91 0x10 _g_adwDebugDLS
+ 0x1013cba1 0x2 _g_awTbCrc
+ COMMON 0x1013cba3 0x51 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x0 (size before relaxing)
+ 0x1013cba3 0x1 _g_zPHY_bDdtrWorkFlag
+ 0x1013cba4 0x1 _wTest
+ 0x1013cba5 0x2 _g_zPHY_dwDdtrCfgTimer
+ 0x1013cba7 0x2 _g_awHarqPrintFlg
+ 0x1013cba9 0x32 _g_tdbCqi2DlsPmiInfo
+ 0x1013cbdb 0x2 _dwCrcRlt
+ 0x1013cbdd 0x14 _awCfgHarqErr
+ 0x1013cbf1 0x2 _g_awHarqPreTime
+ 0x1013cbf3 0x1 _g_wLayerNum
+ COMMON 0x1013cbf4 0x89 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x0 (size before relaxing)
+ 0x1013cbf4 0x2 _g_dwOffsetDelta
+ 0x1013cbf6 0x2 _g_zPHY_erfc_tempDac
+ 0x1013cbf8 0x1 _g_zPHY_erfc_TempStartRecordFlag
+ 0x1013cbf9 0x1 _g_dwOffsetFlag
+ 0x1013cbfa 0x1 _g_zPHY_erfc_wMID2RXFlag
+ 0x1013cbfb 0x1 _g_slot1_nRBNum
+ 0x1013cbfc 0x14 _g_asdzPHY_erfc_CirServOrNeibor
+ 0x1013cc10 0x1 _g_zPHY_erfc_Meas0SubfNum
+ 0x1013cc11 0x2 _g_dwSubframeNumForTest
+ 0x1013cc13 0x2 _g_zPHY_erfc_CleanTxoffset
+ 0x1013cc15 0x2 _g_zPHY_erfc_Meas0Offset
+ 0x1013cc17 0x1 _g_zPHY_erfc_wSyncState
+ 0x1013cc18 0x1 _g_slot0_RBStart
+ 0x1013cc19 0x2 _g_zPHY_erfc_Meas1Offset
+ 0x1013cc1b 0x2 _g_zPHY_erfc_InitialTempDac
+ 0x1013cc1d 0x2 _g_zPHY_erfc_TxMulmOffset
+ 0x1013cc1f 0x2 _g_zPHY_erfc_RxoffsetAcumulator
+ 0x1013cc21 0x2 _g_AgcHwModeOnFalg
+ 0x1013cc23 0x1 _g_zPHY_erfc_eAcp405NextState
+ 0x1013cc24 0x1 _g_slot1_RBStart
+ 0x1013cc25 0x1 _g_zPHY_erfc_eAcp405CurrState
+ 0x1013cc26 0x1 _g_wReadState
+ 0x1013cc27 0x4 _g_tLteRfcTmpReadInfo
+ 0x1013cc2b 0x14 _g_adzPHY_erfc_MainAntInd
+ 0x1013cc3f 0x1 _g_zPHY_erfc_TaTimer
+ 0x1013cc40 0x2 _g_adzPHY_erfc_CurMainAntInd
+ 0x1013cc42 0x2 _g_dwTxoffset
+ 0x1013cc44 0x2 _g_dwDbgSubfCount
+ 0x1013cc46 0x1 _g_slot0_nRBNum
+ 0x1013cc47 0x33 _gtLteRfcRpiPwrCtl
+ 0x1013cc7a 0x2 _g_zPHY_erfc_RfStateMap
+ 0x1013cc7c 0x1 _g_zPHY_erfc_Meas0SubfDef
+ COMMON 0x1013cc7d 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x0 (size before relaxing)
+ 0x1013cc7d 0x1 _g_wRi1LstCqi
+ 0x1013cc7e 0x1 _g_wStartCNTFlg
+ 0x1013cc7f 0x61 _gt_CsiFilter
+ 0x1013cce0 0x1 _g_wLstTm
+ 0x1013cce1 0xaa _g_atCsiPmiRiCalcResult
+ 0x1013cd8b 0x1 _g_wCNT
+ COMMON 0x1013cd8c 0xbb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x0 (size before relaxing)
+ 0x1013cd8c 0x28 _g_L1e_dwPbchEvtList
+ 0x1013cdb4 0x1e _g_L1e_tPbchCB
+ 0x1013cdd2 0x22 _g_L1e_tMibRxReg
+ 0x1013cdf4 0x9 _g_L1e_tDlaparaSave
+ 0x1013cdfd 0x14 _g_L1e_tMibPbchReg
+ 0x1013ce11 0x15 _g_L1e_tMibInfo
+ 0x1013ce26 0xc _g_L1e_tBchOps
+ 0x1013ce32 0xa _g_DbgMibPerStat
+ 0x1013ce3c 0xb _g_L1e_tMibRfcBackUp
+ COMMON 0x1013ce47 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x0 (size before relaxing)
+ 0x1013ce47 0x1 _g_wMsg4AckRaConflictCnt
+ 0x1013ce48 0x1 _g_wHarqGroupNum
+ COMMON 0x1013ce49 0x9c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x0 (size before relaxing)
+ 0x1013ce49 0x9 _g_atCqiCommonInfo
+ 0x1013ce52 0x1 _g_awCqiPmiRiIndex
+ 0x1013ce53 0xd _g_atBandWidthInfo
+ 0x1013ce60 0xa _g_adAperLastCqiPmiDataBuffer
+ 0x1013ce6a 0x1 _g_awAPERLastRI
+ 0x1013ce6b 0x32 _g_atCsiEnFinal
+ 0x1013ce9d 0x8 _g_atPeriodRepPara
+ 0x1013cea5 0x1 _g_awLastReportIndex
+ 0x1013cea6 0x2 _g_awLastWBPMI
+ 0x1013cea8 0x4 _g_tCsiTime
+ 0x1013ceac 0x1 _g_awLastWBCQICW0
+ 0x1013cead 0x1 _g_awRiBitLen
+ 0x1013ceae 0x1 _g_awAPERLastWBCQICW0
+ 0x1013ceaf 0x2 _g_awLastRI
+ 0x1013ceb1 0x32 _g_atCqiDedicateInfo
+ 0x1013cee3 0x1 _g_awLastWBCQICW1
+ 0x1013cee4 0x1 _g_awMaxLayerNum
+ COMMON 0x1013cee5 0x233b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x0 (size before relaxing)
+ 0x1013cee5 0x50 _g_awFHopSeq4SubBands
+ 0x1013cf35 0x2 _g_dwTpcPrintCnt
+ 0x1013cf37 0x50 _g_awFHopSeq3SubBands
+ 0x1013cf87 0x2 _g_dwSrsPrintCnt
+ 0x1013cf89 0x2 _g_dwPucchPrintCnt
+ 0x1013cf8b 0x2 _g_dwPrachPrintCnt
+ 0x1013cf8d 0x50 _g_awFHopSeq2SubBands
+ 0x1013cfdd 0x4 _g_awSpecPrachNum
+ 0x1013cfe1 0x50 _g_awFmSeq
+ 0x1013d031 0xe98 _g_zPHY_etx_HarqProDbPort0
+ 0x1013dec9 0x50 _g_awFmSeq_Scell
+ 0x1013df19 0x8 _g_t_zPHY_etx_Uls_H2L_HarqProcessIDInfo
+ 0x1013df21 0x8 _g_t_zPHY_etx_HarqProcessIDInfo
+ 0x1013df29 0x25f _g_awUlTestMacPduBuf
+ 0x1013e188 0x50 _g_awFHopSeq2SubBands_Scell
+ 0x1013e1d8 0xe98 _g_zPHY_etx_HarqProDbPort1
+ 0x1013f070 0x104 _g_t_zPHY_Dls2UlsDciValue
+ 0x1013f174 0x50 _g_awFHopSeq4SubBands_Scell
+ 0x1013f1c4 0x2 _g_dwCloseLoopPowerPrintCnt
+ 0x1013f1c6 0x2 _g_dwPuschPrintCnt
+ 0x1013f1c8 0x50 _g_awFHopSeq3SubBands_Scell
+ 0x1013f218 0x8 _g_t_zPHY_etx_RarUlGrant
+ COMMON 0x1013f220 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x0 (size before relaxing)
+ 0x1013f220 0x1 _g_swPrintProNoInt
+ 0x1013f221 0x10 _g_asdwL1eRxCrsRsrp
+ 0x1013f231 0x4 _g_adwL1eRxCrsRssi
+ 0x1013f235 0x4 _g_lsdwNsIot_8242_SINR
+ 0x1013f239 0x18 _g_adwL1eRxDrsRsp
+ 0x1013f251 0x1 _g_zPHY_emc_wCellComponFlag
+ 0x1013f252 0xc _g_adwL1eRxCrsRsp
+ 0x1013f25e 0x1 _g_wLtel1IdleAccessReqInd
+ 0x1013f25f 0x1 _g_awL1eRxBfDagcFlag
+ 0x1013f260 0x1 _g_awL1eRxBfTransFlag
+ 0x1013f261 0x1 _g_wL1eRxNbNbSinrCalInd
+ 0x1013f262 0xb _g_zPHY_emc_tSinrInfo
+ 0x1013f26d 0x1 _g_awL1eRxDrsAccNum
+ COMMON 0x1013f26e 0x118e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x0 (size before relaxing)
+ 0x1013f26e 0xa _g_awPSeqCellIDDiv30
+ 0x1013f278 0x12b _g_tUlaLtxParas
+ 0x1013f3a3 0x46 _g_awPSeqCellIDDiv30SS
+ 0x1013f3e9 0x1 _g_EUL_wPuschPowerIdx
+ 0x1013f3ea 0x1 _g_EUL_wPucchPowerIdx
+ 0x1013f3eb 0xe7 _g_tUlaCommRelatedParasScell
+ 0x1013f4d2 0x46 _g_awPSeqCellIDDiv30SS_Scell
+ 0x1013f518 0x1 _g_EUL_wSrsPowerIdx
+ 0x1013f519 0x6 _g_tUlaDediRelatedParas
+ 0x1013f51f 0x4 _g_tUlaCID
+ 0x1013f523 0xa6d _g_t_zPHY_eula_CtrlBlock
+ 0x1013ff90 0x50 _g_awPSeqCellID
+ 0x1013ffe0 0x1c _g_tUlaCommConfig
+ 0x1013fffc 0xac _g_tUlaDediConfig
+ 0x101400a8 0xa _g_awPSeqPuschSeqShift
+ 0x101400b2 0xc8 _g_tUlaScellInfo
+ 0x1014017a 0xe7 _g_tUlaCommRelatedParas
+ 0x10140261 0xa _g_awPSeqCellIDDiv30_Scell
+ 0x1014026b 0x1f _g_tUlaPucchInfo
+ 0x1014028a 0x120 _g_tSrsInfo
+ 0x101403aa 0x50 _g_awPSeqCellID_Scell
+ 0x101403fa 0x1 _g_w_FirstFlgSet
+ 0x101403fb 0x1 _g_EUL_wPrachPowerIdx
+ COMMON 0x101403fc 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x0 (size before relaxing)
+ 0x101403fc 0x1 _g_L1l_LpmCaliIdx
+ 0x101403fd 0x8 _g_L1l_MrtrBeforeWakup
+ 0x10140405 0xa _g_wTpuIntTypeforlpm
+ 0x1014040f 0x2 _g_L1l_LpmCaliCnt
+ 0x10140411 0x6 _g_zPHY_tSuperFrameCtrlInfo
+ 0x10140417 0x22 _g_zPHY_tWakeupTimerInfo
+ 0x10140439 0x1 _g_zPHY_dwTpuSleepTimeLenByFrame
+ 0x1014043a 0x1 _g_L1lLpAwakeTimerCtrl
+ 0x1014043b 0x2 _g_zPHY_tWakeupReq
+ 0x1014043d 0x1 _g_L1lLpTaskStateCtrl
+ 0x1014043e 0x2 _g_L1l_LpmModemWakeupTime
+ 0x10140440 0x2 _g_L1l_LpmCaliAbortTime
+ 0x10140442 0x2 _g_tL1lLpCtrl
+ 0x10140444 0x2 _g_L1l_LpmSocWakeupTime
+ 0x10140446 0x2 _g_zPHY_LtePhySleepCnt
+ 0x10140448 0x8 _g_L1l_MrtrAfterSleep
+ COMMON 0x10140450 0x14e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x0 (size before relaxing)
+ 0x10140450 0x10 _g_adw_zPHY_erfc_profile_DB
+ 0x10140460 0x2 _g_dwLPTxoffset
+ 0x10140462 0x1 _g_zPHY_erfc_AfcWord
+ 0x10140463 0xc0 _g_zPHY_erfc_aNVBandIndex
+ 0x10140523 0x39 _g_zPHY_erfc_atLPCSFConfig
+ 0x1014055c 0x2 _g_zPHY_erfc_ACP405Version
+ 0x1014055e 0x40 _g_at_zPHY_erfc_atReloadData
+ COMMON 0x1014059e 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x0 (size before relaxing)
+ 0x1014059e 0x1 _g_zPHY_ecsrm_wNextIntFlag
+ 0x1014059f 0x1 _g_ZPHY_ecsrm_tMeasState
+ 0x101405a0 0xf _g_zPHY_ecsrm_tCommInfo
+ COMMON 0x101405af 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x0 (size before relaxing)
+ 0x101405af 0x120 _g_MeasContext
+ COMMON 0x101406cf 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x0 (size before relaxing)
+ 0x101406cf 0x7 _g_tUlBlerInfo
+ *fill* 0x101406d6 0x80000002 00
+ COMMON 0x101406d8 0x3ec T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x0 (size before relaxing)
+ 0x101406d8 0x2 _g_awMbmsClusterNum
+ 0x101406da 0x1 _g_ePreRapcState
+ 0x101406db 0x30 _g_aswMBMS_MaxDelay
+ 0x1014070b 0x31 _g_aswMBMS_FftWinStart
+ 0x1014073c 0xc4 _g_aswFreq_Inter_Coeff
+ 0x10140800 0xc4 _g_aswFreq_NormalCoeff
+ 0x101408c4 0x200 _g_aiInitSequence
+ COMMON 0x10140ac4 0x1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x0 (size before relaxing)
+ 0x10140ac4 0x14 _g_tLteA1DlaRxCb
+ 0x10140ad8 0x4 _g_awL1eRxRsrpFilter
+ 0x10140adc 0x4 _g_awL1eRxRsrpFilterFlag
+ COMMON 0x10140ae0 0x3cf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x0 (size before relaxing)
+ 0x10140ae0 0x1 _g_zPHY_edfe_wAgcEnEventFlag
+ 0x10140ae1 0x8 _g_tTempDCOffsetComp
+ 0x10140ae9 0xd _g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0x10140af6 0x1 _g_zPHY_edfe_wRxLinDagc1
+ 0x10140af7 0x1 _g_zPHY_edfe_swAgcMeanPwr1
+ 0x10140af8 0x2 _g_zPHY_edfe_dwScanFreqAgcCalFlag
+ 0x10140afa 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp0
+ 0x10140afc 0x1 _g_zPHY_edfe_wNotSyncAGCDone
+ 0x10140afd 0x1 _g_zPHY_edfe_wRfcSingleAnt
+ 0x10140afe 0x8 _g_tIQComp
+ 0x10140b06 0x1 _g_wAgcCntForFirstDC
+ 0x10140b07 0x6 _g_awAgcGain0
+ 0x10140b0d 0x1 _g_zPHY_edfe_wAgcLog2Gain0
+ 0x10140b0e 0x1 _g_zPHY_edfe_wCsrsLinDagc0
+ 0x10140b0f 0x1 _g_zPHY_edfe_wCsrmLinDagc1
+ 0x10140b10 0x78 _g_zPHY_edfe_MeasAgcPara
+ 0x10140b88 0x1 _g_wCount
+ 0x10140b89 0x120 _g_a_zPHY_edfe_tReloadAgcData
+ 0x10140ca9 0x1 _g_zPHY_edfe_cRxAntennaMode
+ 0x10140caa 0x18 _g_zPHY_edfe_tPlmnAgcPara
+ 0x10140cc2 0x8 _g_tDCOffsetCompRecord
+ 0x10140cca 0x2 _g_dwCsrmRssiRx0
+ 0x10140ccc 0x1 _g_zPHY_edfe_wAgcExtendModeEn
+ 0x10140ccd 0x6 _g_awAgcGain1
+ 0x10140cd3 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp7
+ 0x10140cd5 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt1
+ 0x10140cd6 0x1 _g_zPHY_edfe_wRxLinDagc0
+ 0x10140cd7 0x28 _g_a_zPHY_edfe_wCsrmTotalAgcGainLog2
+ 0x10140cff 0x78 _g_tDfeNotchInfo
+ 0x10140d77 0x1 _g_zPHY_edfe_wAgcIntReportFlag
+ 0x10140d78 0x6 _g_awTempMeanPower1
+ 0x10140d7e 0x1 _g_zPHY_edfe_wAgcMeaPwSavReg
+ 0x10140d7f 0x1 _g_zPHY_edfe_wAgcLog2Gain1
+ 0x10140d80 0x1 _g_zPHY_edfe_wSaveRxBand
+ 0x10140d81 0x1 _g_wAgcWorkState
+ 0x10140d82 0x1 _g_zPHY_edfe_wCsrmLinDagc0
+ 0x10140d83 0x1 _g_zPHY_edfe_wRfcSyncState
+ 0x10140d84 0xd7 _g_EDFE_SYSTEM_INFO
+ 0x10140e5b 0x1 _g_zPHY_edfe_swAgcMeanPwr0
+ 0x10140e5c 0x1 _g_zPHY_edfe_wAgcdBGain0
+ 0x10140e5d 0x2 _g_DcCounter
+ 0x10140e5f 0x8 _g_tDCOffsetEsti
+ 0x10140e67 0x2 _g_dwCsrmRssiRx1
+ 0x10140e69 0x8 _g_tDCOffsetComp
+ 0x10140e71 0x1 _g_wIqCount
+ 0x10140e72 0x2 _g_zPHY_edfe_dwSearchAgcCalFlag
+ 0x10140e74 0x1 _g_zPHY_edfe_wCsrsLinDagc1
+ 0x10140e75 0x28 _g_a_zPHY_edfe_wRxTotalAgcGainLog2
+ 0x10140e9d 0x1 _g_zPHY_erfc_SlaveOutGapAGC
+ 0x10140e9e 0x1 _g_wCsrs_RX_Sib1_Read_Flag
+ 0x10140e9f 0x8 _g_zPHY_edfe_tRxAgcBalance
+ 0x10140ea7 0x6 _g_awTempMeanPower0
+ 0x10140ead 0x1 _g_zPHY_edfe_wAgcdBGain1
+ 0x10140eae 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ COMMON 0x10140eaf 0x1e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x0 (size before relaxing)
+ 0x10140eaf 0x1 _g_eTxCalibrationStep
+ 0x10140eb0 0x1 _g_wTxSendScaleDC
+ 0x10140eb1 0x4 _g_awDfeFftOutputDC
+ 0x10140eb5 0x4 _g_awDfeFftOutputIQ
+ 0x10140eb9 0x2 _g_dwCalibration_angle
+ 0x10140ebb 0x1d3 _g_atzPHY_UlAMTHarqProcessDB
+ 0x1014108e 0x1 _g_wTxSendScaleIQ
+ 0x1014108f 0x1 _Configdelay
+ 0x10141090 0x2 _g_dwCalibration_amp
+ COMMON 0x10141092 0x269d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x0 (size before relaxing)
+ 0x10141092 0x1 _g_wAutoDeactiveTimer
+ 0x10141093 0x6 _g_t_zPHY_DlaDciInfo
+ 0x10141099 0xa _g_tL1eDevRxLpConvergeCb
+ 0x101410a3 0x268c _g_t_zPHY_DlaCb
+ COMMON 0x1014372f 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x0 (size before relaxing)
+ 0x1014372f 0x2 _g_Scc_Rsrp_Cfo_IntCnt
+ 0x10143731 0x1 _g_wULA_Process_SubFrame
+ 0x10143732 0x2 _gTimer1Int_RcvNum
+ 0x10143734 0x6 _g_zPHY_Int_dwDFEIntType
+ 0x1014373a 0x2 _g_zPHY_Int_dwDFEIntType_agc
+ COMMON 0x1014373c 0xc0a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x0 (size before relaxing)
+ 0x1014373c 0x2 _g_dwL1lPreHookEntry
+ 0x1014373e 0x2 _gL1l_MissLogInfo
+ 0x10143740 0xc00 _g_awL1lEngTempBuffer
+ 0x10144340 0x2 _L1L_STANDARD_LOG_ID_BASE
+ 0x10144342 0x2 _g_dwL1lCurrentHookEntry
+ 0x10144344 0x2 _g_wL1lRemainLen
+ COMMON 0x10144346 0x138d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x0 (size before relaxing)
+ 0x10144346 0xd _g_tTTIBundlingDB
+ 0x10144353 0xe _g_zPHY_euls_tTpcCommands
+ 0x10144361 0x1 _g_EUL_wRachIdx
+ 0x10144362 0x14 _g_tRarCtrlDB
+ 0x10144376 0x2 _g_EUL_wDci0InfoIdx
+ 0x10144378 0x2d _g_tUlSPSDB
+ 0x101443a5 0x2a _g_zPHY_euls_ComConfig
+ 0x101443cf 0x123e _g_tShadowHarqDB
+ 0x1014560d 0x8 _g_tUlsDB
+ 0x10145615 0x72 _g_atDCI0PhichSelecDB
+ 0x10145687 0x4c _g_zPHY_euls_DedConfig
+ COMMON 0x101456d3 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x0 (size before relaxing)
+ 0x101456d3 0x4 _g_zPHY_erfc_tCordicAdjustPara
+ 0x101456d7 0x2 _g_ACP405_AFC_DIFF
+ 0x101456d9 0x5 _g_zPHY_erfc_tAfcPara
+ 0x101456de 0x28 _g_sdAtCtl_ApcOffsetTime
+ COMMON 0x10145706 0x2c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x0 (size before relaxing)
+ 0x10145706 0x2 _gadwZeroCsiRsCollideInd
+ 0x10145708 0x2 _gau_zPHY_Rx_CsiRsIdicator
+ 0x1014570a 0x1 _g_PchBlerInfo_0
+ 0x1014570b 0x8 _gau_zPHY_Rx_ZeroPowerCisPos
+ 0x10145713 0x1 _g_PchBlerInfo_3
+ 0x10145714 0x2 _g_dwRxPreN0Value
+ 0x10145716 0x1 _g_wPrbNoPrintFlg
+ 0x10145717 0x2 _gauZeroPowerCsiBitMap
+ 0x10145719 0x2 _gadwCsiRsCollideInd
+ 0x1014571b 0x1 _g_PchBlerInfo_1
+ 0x1014571c 0x1 _g_PchTiCfgInd_1
+ 0x1014571d 0x2 _gadwZeroPowerCsiRsPosCalculated
+ 0x1014571f 0x1 _g_tRxPreState
+ 0x10145720 0x1 _g_wPchFlag
+ 0x10145721 0x1 _g_tRxCurrState
+ 0x10145722 0x1 _g_PchBlerInfo_4
+ 0x10145723 0x2 _g_dwTempN0
+ 0x10145725 0x1 _gwNS_IOT_8242_Ind
+ 0x10145726 0x1 _g_awL1eRxNCellRsNullEnInd
+ 0x10145727 0x2 _gadwCsiRsPosCalculated
+ 0x10145729 0x1 _g_awRxCirTiCfgInd
+ 0x1014572a 0x2 _gt_zPHY_Rx_ZeroCsiRsExistInd
+ 0x1014572c 0x2 _g_awCsiRsCheCfgVal
+ 0x1014572e 0x1 _g_PchBlerInfo_2
+ 0x1014572f 0x1 _g_PchTiCfgInd_2
+ 0x10145730 0x2 _gt_zPHY_Rx_CsiRsExistInd
+ COMMON 0x10145732 0xa04 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ 0x0 (size before relaxing)
+ 0x10145732 0x510 _g_adwCommDlschPara1A
+ 0x10145c42 0x300 _g_adwCommDlschPara1C
+ 0x10145f42 0x1f4 _g_adwPhyNirDivC
+ COMMON 0x10146136 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x0 (size before relaxing)
+ 0x10146136 0x24c _g_TopReg
+ 0x10146382 0xc _g_LteaTopIntRegBitMap
+ COMMON 0x1014638e 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x0 (size before relaxing)
+ 0x1014638e 0xa _g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0x10146398 0x1 _g_wRLMATQInFlg
+ 0x10146399 0x2 _g_sdRLMATQIn
+ 0x1014639b 0x1 _g_zPHY_emc_wSIDataBufSel
+ 0x1014639c 0x2 _g_sdRLMATQOut
+ 0x1014639e 0x1 _g_wRLMATQOutFlg
+ 0x1014639f 0x1e _g_zPHY_emc_tScheduleSiReq
+ 0x101463bd 0x8 _g_zPHY_emc_tPchDataRecvCtrlInfo
+ 0x101463c5 0x6 _g_zPHY_emc_tReadSib1Req
+ COMMON 0x101463cb 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x0 (size before relaxing)
+ 0x101463cb 0x8 _g_zPHY_tLpcPwrCtrlScenExpect
+ COMMON 0x101463d3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x0 (size before relaxing)
+ 0x101463d3 0x1 _g_VrbFlag
+ COMMON 0x101463d4 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x0 (size before relaxing)
+ 0x101463d4 0x2 _g_zPHY_erfc_dwConFr40AuxAdcClkBase
+ 0x101463d6 0x2 _g_dwAptFixVoltageNvSet
+ 0x101463d8 0x2 _g_zPHY_erfc_dwConFr11_19Xtal
+ 0x101463da 0x2 _g_zPHY_erfc_dwConFr24LowRefMode
+ 0x101463dc 0x2 _g_ACP405_RxPGC1_Word
+ 0x101463de 0x2 _g_ACP405_RxPGC0_Word
+ 0x101463e0 0x2 _g_zPHY_erfc_dwConFr33RefClk
+ COMMON 0x101463e2 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x0 (size before relaxing)
+ 0x101463e2 0x28 _g_a_zPHY_edfe_dwLpcSaveReg
+ COMMON 0x1014640a 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x0 (size before relaxing)
+ 0x1014640a 0xa _g_CsrGapInfo
+ COMMON 0x10146414 0x63b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x0 (size before relaxing)
+ 0x10146414 0x1 _g_dwCsrIntraRsrpFilterPrintCnt
+ 0x10146415 0x2 _g_swCsr_Rssi_SearCnf
+ 0x10146417 0x55d _g_zPHY_ecsrc_tFilterInterMeas
+ 0x10146974 0x2 _g_swCsr_Rssi_Report
+ 0x10146976 0xc4 _g_zPHY_ecsrc_tFilterIntraMeas
+ 0x10146a3a 0x1 _g_awAgcNoBalance
+ 0x10146a3b 0x12 _g_zPHY_ecsrc_tFilterFactor
+ 0x10146a4d 0x1 _g_dwCsrInterRsrpFilterPrintCnt
+ 0x10146a4e 0x1 _g_dwCsrInterRsrpFilterRepPrintCnt
+ COMMON 0x10146a4f 0x11b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x0 (size before relaxing)
+ 0x10146a4f 0x78 _g_L1e_dwSirEvtList
+ 0x10146ac7 0x5 _g_l1e_tSirRxRcv
+ 0x10146acc 0x95 _g_L1e_tSirDb
+ 0x10146b61 0x1 _g_zPHY_wSibStartPbchTimes
+ 0x10146b62 0x1 _g_L1e_wSibRptDelay
+ 0x10146b63 0x6 _g_L1e_tSibCrc
+ 0x10146b69 0x1 _g_L1e_wSiTimingNeibState
+ COMMON 0x10146b6a 0x352b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x0 (size before relaxing)
+ 0x10146b6a 0x2ee0 _g_awSyncMsgBuff
+ 0x10149a4a 0x5 _g_zPHY_tRfRxOffsetCfgInfo
+ 0x10149a4f 0x1 _g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x10149a50 0x96 _g_zPHY_emc_tCommonConfigReq
+ 0x10149ae6 0x2 _g_zPHY_emc_tMcCtrlParam
+ 0x10149ae8 0x1 _g_zPHY_emc_wSoftResetOkFlag
+ 0x10149ae9 0x2 _g_dwNextX
+ 0x10149aeb 0x1 _g_zPHY_emc_bGapConfigState
+ 0x10149aec 0x1 _g_wSCellDeactivationTimerParam
+ 0x10149aed 0x1 _g_zPHY_emc_wReleaseDlDelayCnt
+ 0x10149aee 0x50 _g_atzPhy_emc_SyncMsgInfo
+ 0x10149b3e 0x1 _g_wPlmnRapcConflictTimer
+ 0x10149b3f 0x1 _g_zPHY_emc_wIsCampOn
+ 0x10149b40 0x4 _g_zPHY_emc_tTimingCtrlParam
+ 0x10149b44 0x4 _g_zPHY_emc_ScellCtrlReq
+ 0x10149b48 0x2 _g_dwGapStatue
+ 0x10149b4a 0x1 _g_zPHY_emc_wUseServeInfoFlag
+ 0x10149b4b 0x1 _g_zPHY_emc_wReleaseRfcIdleModeOkCnt
+ 0x10149b4c 0x4 _g_zPHY_emc_tTACtrlParam
+ 0x10149b50 0x2 _g_dwSubFrm
+ 0x10149b52 0x2 _g_dwErrorNum
+ 0x10149b54 0x13 _g_zPHY_emc_tDrxSPSCtrlInfo
+ 0x10149b67 0x1 _g_ePrePhyState
+ 0x10149b68 0x4 _g_awSCellDeactivationTimer
+ 0x10149b6c 0x412 _g_zPHY_emc_tDedicatedConfigReq
+ 0x10149f7e 0x8 _g_zPHY_emc_tAccessReq
+ 0x10149f86 0x1 _g_zPHY_emc_wCommonMsgDisPathFlag
+ 0x10149f87 0x1 _g_wThinkWill_Flg
+ 0x10149f88 0x50 _g_CellSearchData
+ 0x10149fd8 0xd _g_zPHY_emc_tRec_Tpu
+ 0x10149fe5 0x1 _g_zPHY_emc_wSetModeOkFlag
+ 0x10149fe6 0x86 _g_FreqScanData
+ 0x1014a06c 0x2 _g_zPHY_emc_tReleaseCtrlParam
+ 0x1014a06e 0x3 _g_zPHY_emc_tRaMsgHoldFlag
+ 0x1014a071 0x24 _g_L1e_tDlRfcCfgInfo
+ COMMON 0x1014a095 0x1513 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x0 (size before relaxing)
+ 0x1014a095 0x1 _g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1014a096 0x1 _g_zPHY_ecsrc_wPiPeriod
+ 0x1014a097 0x8 _g_zPHY_ecsrc_tSearchMeasAgeThrold
+ 0x1014a09f 0x2 _g_zPHY_ecsrs_dwTpuAdjTime
+ 0x1014a0a1 0x86 _g_zPHY_ecsrc_tFreqScanReq
+ 0x1014a127 0x28 _g_zPHY_ecsrc_tCommInfo
+ 0x1014a14f 0x4 _g_L1e_Csrc_PreCfo
+ 0x1014a153 0x10 _g_zPHY_ecsrc_tEarfcnTable_B28
+ 0x1014a163 0x39e _g_zPHY_ecsrc_tCsrPsInterMeasInd
+ 0x1014a501 0x55 _g_L1e_Csrc_C0Update
+ 0x1014a556 0x6 _g_zPHY_ecsrc_tMeasMaskSetBack
+ 0x1014a55c 0x50 _g_zPHY_ecsrc_tCellSearchReq
+ 0x1014a5ac 0x1f _g_zPHY_ecsrc_tCnnDrxMeasSchedule
+ 0x1014a5cb 0x6 _g_zPHY_ecsrc_tMeasMaskSetReq
+ 0x1014a5d1 0x82 _g_zPHY_ecsrc_tFreqScanCnf
+ 0x1014a653 0x4 _g_atAgeTimer
+ 0x1014a657 0x1 _g_L1e_Csrc_DisFreqScan
+ 0x1014a658 0x1 _g_zPHY_ecsrc_wScheduleInfoCnt
+ 0x1014a659 0x1 _g_L1e_C0ConIntraRptCnt
+ 0x1014a65a 0x1 _g_L1e_C0ConDrxCnt
+ 0x1014a65b 0x6 _g_L1e_Csrc_CurPpm
+ 0x1014a661 0x1 _g_wcsrc_HoOnflag
+ 0x1014a662 0x2ae _g_zPHY_ecsrc_tCsrPsIntraMeasInd
+ 0x1014a910 0x1 _g_zPHY_ecsrc_wWorkInterFreqIndex
+ 0x1014a911 0x6a7 _g_zPHY_ecsrc_tCsrCellDatabase
+ 0x1014afb8 0x9 _g_zPHY_ecsrc_tFliterSchduInd
+ 0x1014afc1 0x1 _g_zPHY_wHoStartPbchTimes
+ 0x1014afc2 0x2 _g_zPHY_ecsrc_dwCsrcFlag
+ 0x1014afc4 0x2 _g_L1e_csrc_tMeasPeriodChgReq
+ 0x1014afc6 0x1 _g_zPHY_ecsrc_AferGapFlag
+ 0x1014afc7 0x12 _g_zPHY_ecsrc_wDoneInterPerDrx
+ 0x1014afd9 0x5c8 _g_zPHY_ecsrc_tMeasConfigReq
+ 0x1014b5a1 0x2 _g_zPHY_ecsrc_swBackupCFOFreqOffset
+ 0x1014b5a3 0x1 _g_L1e_ConnIntraRptCnt
+ 0x1014b5a4 0x1 _g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1014b5a5 0x2 _g_L1eTempAdc
+ 0x1014b5a7 0x1 _g_L1e_Csrc_bCellSearchPbch
+ COMMON 0x1014b5a8 0x1c2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ 0x0 (size before relaxing)
+ 0x1014b5a8 0x1c1 _g_aw_RarMacPdu
+ 0x1014b769 0x1 _g_zPHY_swRsrpFilter
+ COMMON 0x1014b76a 0x919 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x0 (size before relaxing)
+ 0x1014b76a 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x1014b772 0x134 _g_zPHY_ecsrc_tMulmFreqListConfig
+ 0x1014b8a6 0x8 _g_zPHY_ecsrc_tIratGapConfig
+ 0x1014b8ae 0x3 _g_tSlaveSearchMeasAgeThrold
+ 0x1014b8b1 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReqBackUp
+ 0x1014b8b9 0x1 _g_zPHY_emulm_PlmnSearchMeasCnt
+ 0x1014b8ba 0x6 _g_zPHY_emulm_tFilterFactor
+ 0x1014b8c0 0x1 _g_L1e_mulm_NoSatisfyCfoCnt
+ 0x1014b8c1 0x2 _g_zPHY_SetModeReq
+ 0x1014b8c3 0x6 _g_zPHY_ecsrc_tMulmInactiveTimeInd
+ 0x1014b8c9 0x1a _g_zPHY_emulm_SlaveHwEnable
+ 0x1014b8e3 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfigBackUp
+ 0x1014b8e9 0x8 _g_zPHY_ecsrc_tIratGapConfig1
+ 0x1014b8f1 0x1 _g_L1e_mulm_40msGapCnt
+ 0x1014b8f2 0x2 _g_zPHY_emulm_tMulmIdlePeriodReqFlag
+ 0x1014b8f4 0x3 _g_zPHY_emulm_tMulmAfcPara
+ 0x1014b8f7 0x165 _g_zPHY_ecsrc_atSlaveMeasInfo
+ 0x1014ba5c 0x621 _g_zPHY_emulm_tFilterMeas
+ 0x1014c07d 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfig
+ COMMON 0x1014c083 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x0 (size before relaxing)
+ 0x1014c083 0x11 _g_RxOpenPara
+ COMMON 0x1014c094 0x88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x0 (size before relaxing)
+ 0x1014c094 0x6c _g_zPHY_emc_tDrxCtrlInfo
+ 0x1014c100 0xa _g_wIntTypeforDrx
+ 0x1014c10a 0x10 _g_awDrxUlRetranCnt
+ 0x1014c11a 0x2 _g_Next2SubFrameDrxActiveSidFlag
+ COMMON 0x1014c11c 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x0 (size before relaxing)
+ 0x1014c11c 0x1 _g_wFIUpdate2RLM
+ 0x1014c11d 0xf _g_zPHY_emc_tRadioLinkCtrlInfo
+ COMMON 0x1014c12c 0x19c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x0 (size before relaxing)
+ 0x1014c12c 0x10 _g_tLteAmtCellSyncPara
+ 0x1014c13c 0x157 _g_tLteAmtInfo
+ 0x1014c293 0x2 _g_zPHY_AMT_SearchCellCnt
+ 0x1014c295 0x2 _g_zPHY_AMT_Strongest_CellId
+ 0x1014c297 0x1f _gtAmtCellSyncProc
+ 0x1014c2b6 0x2 _g_zPHY_AMT_Strongest_Rsrp
+ 0x1014c2b8 0x2 _g_zPHY_AMT_Earfcn
+ 0x1014c2ba 0xa _g_zPHY_AMT_SrvCellRsrp
+ 0x1014c2c4 0x2 _g_dwFdt10MsCnt
+ 0x1014c2c6 0x2 _g_zPHY_AMT_Frequency
+ COMMON 0x1014c2c8 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x0 (size before relaxing)
+ 0x1014c2c8 0x2 _g_tHandoverCnf
+ 0x1014c2ca 0x488 _g_tHandoverReq
+ COMMON 0x1014c752 0x5a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x0 (size before relaxing)
+ 0x1014c752 0xa _g_wIntTypeforPaging
+ 0x1014c75c 0x12 _g_tL1eSchedPreSyncCb
+ 0x1014c76e 0x3a _g_tL1eDcxoProcCb
+ 0x1014c7a8 0x2 _g_zPHY_sdwRxAnt0OffsetValue
+ 0x1014c7aa 0x2 _g_zPHY_sdwRxAnt1OffsetValue
+ COMMON 0x1014c7ac 0x248 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x0 (size before relaxing)
+ 0x1014c7ac 0x23a _g_atzPHY_RFSD
+ 0x1014c9e6 0xa _g_atCsiATCMDInfo
+ 0x1014c9f0 0x4 _g_zPHY_LteRfWorkSet
+ COMMON 0x1014c9f4 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x0 (size before relaxing)
+ 0x1014c9f4 0x18 _g_tL1lCallStackInfo
+ COMMON 0x1014ca0c 0x90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x0 (size before relaxing)
+ 0x1014ca0c 0x48 _g_at_zPHY_NxtHiQuadPosTab
+ 0x1014ca54 0x48 _g_at_zPHY_CurHiQuadPosTab
+ COMMON 0x1014ca9c 0x2e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x0 (size before relaxing)
+ 0x1014ca9c 0x1 _g_zPHY_edfe_wNotSyncAGCBegin
+ 0x1014ca9d 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr1
+ 0x1014ca9e 0x1 _g_Connect_State_Inter_Freq_Flag
+ 0x1014ca9f 0x1 _g_wConnectAgcIntCounter
+ 0x1014caa0 0x1 _g_zPHY_edfe_LostLock_MAX
+ 0x1014caa1 0x1 _g_zPHY_edfe_wFirstInInterFreq
+ 0x1014caa2 0x2 _g_wContinGreaterCount
+ 0x1014caa4 0x1 _g_zPHY_edfe_LostLock_MIN
+ 0x1014caa5 0x1 _g_zPHY_edfe_ScellActiveState
+ 0x1014caa6 0x61 _g_zPHY_edfe_FSNewPara
+ 0x1014cb07 0x1e _g_zPHY_edfe_tAgcDagcPara
+ 0x1014cb25 0x1 _g_dwAgcTargetSync
+ 0x1014cb26 0x1 _g_zPHY_edfe_ScellActiveCounter
+ 0x1014cb27 0x2 _g_wContinLessCount
+ 0x1014cb29 0x1 _g_zPHY_edfe_wPrePhyState
+ 0x1014cb2a 0x1 _g_wAgcFactLf
+ 0x1014cb2b 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr0
+ 0x1014cb2c 0x1 _g_zPHY_edfe_wNotSyncAgcIntCnt
+ 0x1014cb2d 0xa _g_zPHY_edfe_AgcDagcIntCount
+ 0x1014cb37 0x1 _g_dwAgcAvePowLenSync
+ 0x1014cb38 0x1f0 _g_zPHY_edfe_wAgcDagcGain
+ 0x1014cd28 0x4 _g_zPHY_edfe_tMbsfnAgcInfo
+ 0x1014cd2c 0x50 _g_zPHY_edfe_tMbsfnAgcGain
+ COMMON 0x1014cd7c 0xdac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x0 (size before relaxing)
+ 0x1014cd7c 0xd91 _g_tzPHY_ecsrs_FSPara
+ 0x1014db0d 0x4 _g_FS_swMeanPower
+ 0x1014db11 0x1 _g_tzPHY_ecsrs_FS_RepNum
+ 0x1014db12 0x4 _g_PssContext
+ 0x1014db16 0x12 _g_tFS_BackUpPssResult
+ COMMON 0x1014db28 0xd6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x0 (size before relaxing)
+ 0x1014db28 0x2 _TotalPuschNackTB0
+ 0x1014db2a 0x2 _TotalPuschNackTB1
+ 0x1014db2c 0x2 _TotalPuschNumTB1
+ 0x1014db2e 0x6 _g_tUlReportBlerInfo
+ 0x1014db34 0x2 _TotalPuschNumTB0
+ 0x1014db36 0xc8 _g_adwDebug
+ COMMON 0x1014dbfe 0x418 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x0 (size before relaxing)
+ 0x1014dbfe 0x3c8 _g_atEcsrPeakList
+ 0x1014dfc6 0x50 _g_tPssHwResult
+ COMMON 0x1014e016 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x0 (size before relaxing)
+ 0x1014e016 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x1014e01a 0x1 _g_swCsrsDagcMeanPower0
+ 0x1014e01b 0x1 _g_zPHY_edfe_wRxLog2Dagc1
+ 0x1014e01c 0x1 _g_zPHY_edfe_wCsrsLog2Dagc1
+ 0x1014e01d 0x1 _g_swCsrsDagcMeanPower1
+ 0x1014e01e 0x1 _g_zPHY_edfe_wCsrsLog2Dagc0
+ 0x1014e01f 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
+ 0x1014e023 0x1 _g_zPHY_edfe_wRxLog2Dagc0
+ COMMON 0x1014e024 0x8d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ 0x0 (size before relaxing)
+ 0x1014e024 0x5f _g_tzPHY_eulpc_PowerCtrlBlock
+ 0x1014e083 0x1 _g_EUL_wPuschPowerHeadroomIdx
+ 0x1014e084 0x1 _g_tzPHY_eulpc_Ulpc2DlParas
+ 0x1014e085 0x13 _g_tzPHY_eulpc_PcmaxInputInfo
+ 0x1014e098 0x6 _g_tzPHY_eulpc_TempPowerBackoffInfo
+ 0x1014e09e 0x13 _g_tzPHY_eulpc_PowerCtrlParas
+ COMMON 0x1014e0b1 0x9a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x0 (size before relaxing)
+ 0x1014e0b1 0x10f _g_ThreadIntraCs
+ 0x1014e1c0 0xf2 _g_atEcsrSearchPeakdatabase
+ 0x1014e2b2 0x1 _g_CsContext
+ 0x1014e2b3 0x10f _g_ThreadFreqScan
+ 0x1014e3c2 0x60 _g_l1e_tDcxoFtErrorList
+ 0x1014e422 0x2e6 _g_tEcsrSearchCommonInfor
+ 0x1014e708 0xa _g_tTddAndFddCommInfo
+ 0x1014e712 0x2 _g_zPHY_ecsrs_dwPssFrameBnd_dbg
+ 0x1014e714 0x1 _g_eCsrsSynStatus
+ 0x1014e715 0x4 _g_tEmulmSubFrameIntTable
+ 0x1014e719 0xe _g_atEcsrReCfoInfo
+ 0x1014e727 0x1 _g_wSssHwRestartCnt
+ 0x1014e728 0x10f _g_ThreadCfoCs
+ 0x1014e837 0x10f _g_ThreadInterCs
+ 0x1014e946 0x10f _g_ThreadMulmCs
+ COMMON 0x1014ea55 0x11e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x0 (size before relaxing)
+ 0x1014ea55 0x11e _g_CsrDrvCfgInfor
+ 0x1014eb73 ___bss_end = .
+
+.itcm 0x00000000 0x6e38 load address 0x100e8000
+ 0x00000000 _itcm_start = .
+ *(.vectors)
+ .vectors 0x00000000 0xb8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ 0x00000000 0x20 _zsp_int_vector
+ 0x00000020 0x8 _odo_stub_Int12
+ 0x00000028 0x8 _odo_stub_Int11
+ 0x00000030 0x8 _odo_stub_Int10
+ 0x00000038 0x8 _odo_stub_Int9
+ 0x00000040 0x8 _odo_stub_Int8
+ 0x00000048 0x8 _odo_stub_Int7
+ 0x00000050 0x8 _odo_stub_Int6
+ 0x00000058 0x8 _odo_stub_Int5
+ 0x00000060 0x8 _odo_stub_Int4
+ 0x00000068 0x8 _odo_stub_Int3
+ 0x00000070 0x8 _odo_stub_Int2
+ 0x00000078 0x8 _odo_stub_Int1
+ 0x00000080 0x38 _odo_stub_Int0
+ *(.dmc)
+ .dmc 0x000000b8 0x17e T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+ 0x000000b8 0x17e _dei_handler
+ *(.zcos_vector_code)
+ *fill* 0x00000236 0x2 00
+ .zcos_vector_code
+ 0x00000238 0x1a0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ 0x00000238 0x20 _odo_wakeup_osint
+ 0x00000258 0x38 _jump_int
+ 0x00000290 0xf1 _odo_zsp_do_int
+ 0x00000381 0x27 _odo_swap_context
+ 0x000003a8 0x6 _odo_zsp_restore_flags
+ 0x000003ae 0xb _odo_restart
+ 0x000003b9 0x1f _odo_setup_context
+ .zcos_vector_code
+ 0x000003d8 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x000003d8 0x4d _L1_SwapHookUseTimer
+ *(.TcmLtePhyCode)
+ .TcmLtePhyCode
+ 0x00000425 0x290 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x0000055d 0x108 _L1Comm_DevEngCopyMem2Dpram
+ 0x00000665 0x50 _L1Comm_EmtpyLogUnit
+ .TcmLtePhyCode
+ 0x000006b5 0x193 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x000006b5 0xfb _L1L_TpuSubFrmUpdate
+ 0x000007b0 0x55 _L1L_TpuIntISRProc
+ 0x00000805 0x1b _L1L_TpuSysTimeUpdate
+ 0x00000820 0x28 _L1L_TpuHwIntGen
+ .TcmLtePhyCode
+ 0x00000848 0x2b1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x00000848 0x31a _L1e_DevDlsCdtrIntProc
+ 0x00000b62 0x37 _L1e_DevDlsGetDlCcInfo
+ 0x00000b99 0x26 _L1e_DevDlsGetDciDetInfo
+ 0x00000bbf 0x26 _L1e_DevDlsGetDciInfo
+ 0x00000be5 0x10 _L1e_DevDlsGetDciNum
+ 0x00000bf5 0x18 _L1e_DevDlsSwapDciInfo
+ 0x00000c0d 0x89 _L1e_DevDlsDciSelection
+ 0x00000c96 0x13 _L1e_DevDlsGetDestDci
+ 0x00000ca9 0x16 _L1e_DevDlsGetDestDciInfo
+ 0x00000cbf 0x369 _L1e_DevDlsGetUlCcInfo
+ 0x00001028 0x16 _L1e_DevDlsJudgeSccAssignment
+ 0x0000103e 0x10 _L1e_DevDlsRxUeRsAlgoCfg
+ 0x0000104e 0x15f _L1e_DevDlsRxCtrlRegCfg
+ 0x000011ad 0xe _L1e_DevDlsCalcTurboDelay
+ 0x000011bb 0x62 _L1e_DevDlsCalcTurboITs
+ 0x0000121d 0x67 _L1e_DevDlsTurboCtrlRegCfg
+ 0x00001284 0x22 _L1e_DevDlsGetDdtrWorkStatusInd
+ 0x000012a6 0x1d _L1e_DevDlsResetTurbo
+ 0x000012c3 0xf _L1e_DevDlsSubfNumRegCfg
+ 0x000012d2 0x8 _L1e_DevDlsPdschEnRegCfg
+ 0x000012da 0x1 _L1e_DevDlsDdtrClkSelCfg
+ 0x000012db 0x33 _L1e_DevDlsDdtrModeRegCfg
+ 0x0000130e 0x52 _L1e_DevDlsUpdateDdtr
+ 0x00001360 0x17 _L1e_DevDlsGetKmimoParam
+ 0x00001377 0x98 _L1e_DevDlsGetCcParam
+ 0x0000140f 0x40 _L1e_DevDlsGetCcCommParam
+ 0x0000144f 0x36c _zPHY_edls_ProRxBFCfg
+ 0x000017bb 0x48 _zPHY_edls_ProHarqInfoUpdate
+ 0x00001803 0x2c _zPHY_edls_HarqDdrRel
+ 0x0000182f 0x6b _zPHY_edls_HarqDdrTimeOut
+ 0x0000189a 0x13b _zPHY_edls_HarqDdr_DtchDone
+ 0x000019d5 0x2e _zPHY_edls_HarqDdr_DbgMonitorRst
+ 0x00001a03 0x14 _zPHY_edls_HarqDdr_BlockNumIdx
+ 0x00001a17 0x106 _zPHY_edls_HarqDdrReq
+ 0x00001b1d 0x2b7 _zPHY_edls_ProHarqDdrAddrCfg
+ 0x00001dd4 0x1ab _zPHY_edls_ProHarqInfoCfg
+ 0x00001f7f 0x68 _zPHY_edls_ProDciF1BTpmiValueCfg
+ 0x00001fe7 0x1f _zPHY_edls_ProDciF1DTpmiValueCfg
+ 0x00002006 0x1ce _zPHY_edls_ProDciF2TpmiValueCfg
+ 0x000021d4 0xa0 _zPHY_edls_ProDciF2LayerCfg
+ 0x00002274 0x451 _zPHY_edls_ProCommDlSchDecCfg
+ 0x000026c5 0x36 _zPHY_edls_ProPdcchOrder
+ 0x000026fb 0x3d5 _zPHY_edls_ProDediDlSchDecCfg
+ 0x00002ad0 0x79 _zPHY_edls_ProDLHarqValidInfo
+ 0x00002b49 0x30 _zPHY_edls_ProCwCrcValidGen
+ 0x00002b79 0xda _zPHY_edls_ProTddCwValidFeedback
+ 0x00002c53 0x1e _zPHY_edls_ProFddCwValidFeedback
+ 0x00002c71 0x170 _zPHY_edla_PdschPowCompensate
+ 0x00002de1 0x97 _zPHY_edla_PdschDefaultPCCfg
+ 0x00002e78 0x13 _zPHY_edls_DrvArmDspRamRead
+ 0x00002e8b 0x51 _zPHY_edls_GetUeFeedbackPmiIndex
+ 0x00002edc 0x10 _zPHY_edls_ProValidateSpsRecurs
+ 0x00002eec 0x3b _zPHY_edls_ProCalSpsRecurs
+ 0x00002f27 0x27 _zPHY_edls_ProCalSpsHarqId
+ 0x00002f4e 0xf0 _zPHY_edls_ProLTESpsDecCfg
+ 0x0000303e 0x31 _zPHY_edls_ProSpsValidation
+ 0x0000306f 0x94 _zPHY_edls_ProSpsActive
+ 0x00003103 0x84 _zPHY_edls_ProSpsRelease
+ 0x00003187 0x1dd _L1e_DevDlsDlMacPduBufCfg
+ .TcmLtePhyCode
+ 0x00003364 0x6bd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x00003364 0xb6 _zPHY_erfc_ProEventRamNumSet
+ 0x0000341a 0x7a _zPHY_erfc_ProRxReceiveCtrl
+ 0x00003494 0x8f _zPHY_erfc_ProCellSearchCtrl
+ 0x00003523 0x148 _zPHY_erfc_ProPowerCtrl
+ 0x0000366b 0x17 _zPHY_erfc_ProTDDCalcNextACP405State
+ 0x00003682 0x33 _zPHY_erfc_ProFDDCalcNextACP405State
+ 0x000036b5 0x20b _zPHY_erfc_ProRfsdCheck
+ 0x000038c0 0xd4 _zPHY_erfc_ProRFSDMerge
+ 0x00003994 0x8d _zPHY_erfc_ProMeas0Ctrl
+ .TcmLtePhyCode
+ 0x00003a21 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x00003a21 0xf0 _zPHY_erfc_SupMainSyncTableControl
+ 0x00003b11 0x9d _zPHY_erfc_SupTxSendSyncTableControl
+ 0x00003bae 0xb3 _zPHY_erfc_SupMeas0SyncTableControl
+ 0x00003c61 0x31a _zPHY_erfc_SupDFEAGCEsti
+ .TcmLtePhyCode
+ 0x00003f7b 0xdb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x00003f7b 0xdb _zPHY_edfe_SupHandleDFESyncInt
+ .TcmLtePhyCode
+ 0x00004056 0xfb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x00004056 0x60 _zPHY_eintc_InthHandler
+ 0x000040b6 0x22 _zPHY_eintc_Inth0Handler
+ 0x000040d8 0x22 _zPHY_eintc_Inth1Handler
+ 0x000040fa 0x22 _zPHY_eintc_Inth2Handler
+ 0x0000411c 0xa _zPHY_eintc_IntTimer1Handler
+ 0x00004126 0x2b _zPHY_eintc_ICPHandler
+ .TcmLtePhyCode
+ 0x00004151 0x1e6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x00004151 0x67 _L1l_DevEng_DbgExceptLog
+ 0x000041b8 0x24 _L1l_DevEng_DbgInfo
+ 0x000041dc 0xc0 _L1l_DevEngDisplay
+ 0x0000429c 0x58 _L1l_DevEngLogHeaderUpdate
+ 0x000042f4 0x43 _L1l_DevEngCopyMem2Dpram
+ .TcmLtePhyCode
+ 0x00004337 0x92 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x00004337 0x92 _zPHY_erfc_SupAGCControl
+ .TcmLtePhyCode
+ 0x000043c9 0x1894 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x000043c9 0x31 _L1e_DevDlsGetDciField
+ 0x000043fa 0x1bf _L1e_DevDlsDecodeDciF1A
+ 0x000045b9 0x1d _L1e_DevDlsGetTpmiFieldSize
+ 0x000045d6 0x6b _L1e_DevDlsGetRaType1Info
+ 0x00004641 0x26b _L1e_DevDlsDecodeDualCwDci
+ 0x000048ac 0x17f _L1e_DevDlsDecodeSLSMDci
+ 0x00004a2b 0x176 _zPHY_edls_AdaDecodeDciF1
+ 0x00004ba1 0x8e _zPHY_edls_ProDciF2ALayerCfg
+ 0x00004c2f 0x59 _zPHY_edls_AdaCalRbStartRbLength
+ 0x00004c88 0x8a _zPHY_edls_AdaRbDmpType1
+ 0x00004d12 0x1c2 _zPHY_edls_AdaRbDmpType2Dvrb
+ 0x00004ed4 0x8e _zPHY_edls_AdaRbDmpType2Lvrb
+ 0x00004f62 0x72 _zPHY_edls_AdaRbDmpType01Ctrl
+ 0x00004fd4 0x36 _zPHY_edls_AdaRbDmpType0Bw100Rb
+ 0x0000500a 0x62 _zPHY_edls_AdaRbDmpType0Bw75Rb
+ 0x0000506c 0xb5 _zPHY_edls_AdaRbDmpType0Bw50Rb
+ 0x00005121 0xf9 _zPHY_edls_AdaCalTotalREs
+ 0x0000521a 0x5d _zPHY_edls_CsiRsSfnCal
+ 0x00005277 0xde _zPHY_edls_AdaCalOverlapRbNum
+ 0x00005355 0x2b8 _zPHY_edls_AdaCalTddFddNcpTbREs
+ 0x0000560d 0x10e _zPHY_edls_AdaCalTddFddEcpTbREs
+ 0x0000571b 0xc3 _zPHY_edls_AdaCalTddNcpSpeTbREs
+ 0x000057de 0x92 _zPHY_edls_AdaCalTddEcpSpeTbREs
+ 0x00005870 0x79 _zPHY_edls_AdaGetTbTbs
+ 0x000058e9 0x61 _zPHY_edls_AdaCalTbDecodeParas
+ 0x0000594a 0x3c _zPHY_edls_AdaCalTbCbNum
+ 0x00005986 0x1c _zPHY_edls_AdaCalTbParaKParaC
+ 0x000059a2 0xf0 _zPHY_edls_AdaCalTbParaCEParaE
+ 0x00005a92 0x92 _zPHY_edls_AdaCalTbParaNcbParaK0
+ 0x00005b24 0x45 _zPHY_edls_AdaCalTbK0Start
+ 0x00005b69 0x85 _zPHY_edls_AdaCalTbK1Start
+ 0x00005bee 0x6f _zPHY_edls_AdaCalTbNcbStart
+ .TcmLtePhyCode
+ 0x00005c5d 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x00005c5d 0x1 _zPHY_DrvTop_IntReg_Clear
+ .TcmLtePhyCode
+ 0x00005c5e 0x15 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x00005c5e 0x15 _L1L_TpuDrvTpuUnregister
+ .TcmLtePhyCode
+ 0x00005c73 0x3f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00005c73 0x69 _zPHY_erfc_DrvSubframeEventEn
+ 0x00005cdc 0xbb _zPHY_erfc_DrvEventEn
+ 0x00005d97 0x174 _zPHY_erfc_DrvWriteEventEnArrayToABBRamHwReg
+ 0x00005f0b 0x92 _zPHY_erfc_DrvWriteEventEnArrayToDBBNextRamHwReg
+ 0x00005f9d 0x24 _zPHY_erfc_DrvWriteMainEventEnArrayToDBBRamHwReg
+ 0x00005fc1 0x1c _zPHY_erfc_DrvWriteTuReg
+ 0x00005fdd 0x6 _zPHY_erfc_DrvDisableTuReg
+ 0x00005fe3 0x2c _zPHY_erfc_DrvWriteTuRegMrtr
+ 0x0000600f 0x17 _zPHY_erfc_DrvTuRamDisable
+ 0x00006026 0x16 _zPHY_erfc_DrvTuRamEnable
+ 0x0000603c 0x2b _zPHY_erfc_DrvWriteTuRamData
+ .TcmLtePhyCode
+ 0x00006067 0xdc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x00006067 0x7b _zPHY_erfc_DrvWriteOtherCmdDataToEventTable
+ 0x000060e2 0x61 _zPHY_erfc_DrvWriteCmdDataToEventTable
+ .TcmLtePhyCode
+ 0x00006143 0xa9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x00006143 0xa9 _zPHY_Phy_TdlThreadPriprintf
+ *(.fasttext)
+ .fasttext 0x000061ec 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ 0x000061ec 0xe7 _Asm_Tx2Rx2_NL2_PMICalc
+ 0x000062d3 0x85 _Asm_NL1_PMICalc
+ 0x00006358 0xd6 _Asm_Tx4Rx2_NL2_PMICalc
+ .fasttext 0x0000642e 0x4b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ 0x0000642e 0x42 _Asm_SumLOGNoSqrt_RICalc
+ 0x00006470 0x85 _Asm_Tx2Rx2_CL_NL1_RICalc
+ 0x000064f5 0x105 _Asm_Tx2Rx2_CDD_RICalc
+ 0x000065fa 0x122 _Asm_Tx4Rx2_CL_NL2_RICalc
+ 0x0000671c 0x41 _Asm_Tx4Rx2_CL_NL1_RICalc
+ 0x0000675d 0x65 _Asm_Rx2_DIV_RICalc
+ 0x000067c2 0x120 _Asm_Tx4Rx2_CDD_RICalc
+ .fasttext 0x000068e2 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ 0x000068e2 0x36 _Asm_CqiSinglePort_TX1_RX1_NL1
+ 0x00006918 0x6d _Asm_CqiTransDiver_Common_NL1
+ 0x00006985 0x8d _Asm_CqiSpatiMulti_RX2_NL1
+ 0x00006a12 0xf3 _Asm_CqiSpatiMulti_RX2_NL2
+ 0x00006b05 0xb0 _Asm_CqiCDD_TX2_RX2_NL2
+ 0x00006bb5 0xff _Asm_CqiCDD_TX4_RX2_NL2
+ 0x00006cb4 0x41 _ASM_Log2
+ 0x00006cf5 0x77 _Asm_RLMSNR_Calc
+ *(.LpcCodeTcm)
+ .LpcCodeTcm 0x00006d6c 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x00006d6c 0x2e _L1_SocLpModeControlCfg
+ 0x00006d9a 0x1f _L1_SocCpuIdle
+ .LpcCodeTcm 0x00006db9 0x2f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00006db9 0x2f _L1_CpuEnterIdleMode
+ *(.save_zsp_reg)
+ .save_zsp_reg 0x00006de8 0x50 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ 0x00006de8 0x50 _save_zsp880_reg
+ *Cqi_control.o(.text)
+ *Cqi.o(.text)
+ *CQI_Period.o(.text)
+ allnil*(.text)
+ send*(.text)
+ swap*(.text)
+ timer*(.text)
+ alloc*(.text)
+ arch*(.text)
+ free*(.text)
+ receive*(.text)
+ set_pri*(.text)
+ error*(.text)
+ 0x00006e38 _itcm_end = .
+
+.dtcm 0x00010000 0x63fa load address 0x100f0000
+ 0x00010000 _dtcm_start = .
+ *(.LteDataTcm)
+ .LteDataTcm 0x00010000 0xb T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x00010000 0x2 _g_lte_log_buf
+ 0x00010002 0x2 _g_w_log_buf
+ 0x00010004 0x2 _g_td_log_buf
+ 0x00010006 0x2 _g_sig_log_buf
+ 0x00010008 0x1 _g_bL1CommLogOutUsing
+ 0x00010009 0x2 _g_bL1CommIcpFailCnt
+ .LteDataTcm 0x0001000b 0x1bf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x0001000b 0x4 _g_tLocalSSFrm
+ 0x0001000f 0x4 _g_tNativeSSFrm
+ 0x00010013 0x2 _g_zPHY_SuperFrameNumber
+ 0x00010015 0x2 _g_pFreeItemsNum
+ 0x00010017 0x1a0 _g_pBusyItemsNum
+ 0x000101b7 0x13 _stTpuInfo
+ *fill* 0x000101ca 0x80000006 00
+ .LteDataTcm 0x000101d0 0x1480 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x000101d0 0x190 _g_awNo
+ 0x00010360 0x320 _g_adHRx0
+ 0x00010680 0x320 _g_adHRx1
+ 0x000109a0 0x400 _s_awSNR_P1
+ 0x00010da0 0x400 _s_awSNR_P2
+ 0x000111a0 0xc8 _g_awSNR_RLM
+ 0x00011268 0x320 _g_aCqiRamChe
+ 0x00011588 0xc8 _g_aCqiRamNo
+ .LteDataTcm 0x00011650 0x53b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x00011650 0x53b _g_zPHY_edls_tDlsCb
+ .LteDataTcm 0x00011b8b 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x00011b8b 0x2 _g_zPHY_InthTpuCnt
+ 0x00011b8d 0x4 _g_zPHY_InthTpuCntDebug
+ *fill* 0x00011b91 0x80000003 00
+ .LteDataTcm 0x00011b94 0x3344 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x00011b94 0x2b44 _g_tRxpCirCb
+ 0x000146d8 0x800 _g_awL1eRxCirRam
+ .LteDataTcm 0x00014ed8 0x20 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x00014ed8 0x20 _g_tL1lEngDgbInfo
+ .LteDataTcm 0x00014ef8 0xea T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00014ef8 0x39 _g_zPHY_erfc_atCurrentSFConfig
+ 0x00014f31 0x39 _g_zPHY_erfc_atNextSFConfig
+ 0x00014f6a 0x20 _g_adwzPHY_erfc_RFABBMainSyncEventEnArray
+ 0x00014f8a 0x18 _g_adwzPHY_erfc_RFABBMeas0SyncEventEnArray
+ 0x00014fa2 0x20 _g_adwzPHY_erfc_RFABBTxSyncEventEnArray
+ 0x00014fc2 0x8 _g_adwzPHY_erfc_DBBMainSyncEventEnArray
+ 0x00014fca 0xc _g_adwzPHY_erfc_DBBMeas0SyncEventEnArray
+ 0x00014fd6 0x2 _g_zPHY_erfc_DBBTxSyncEventEn
+ 0x00014fd8 0xa _g_zPHY_erfc_wRamNum
+ .LteDataTcm 0x00014fe2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x00014fe2 0x1 _g_zPHY_edfe_cAGCCalMode
+ .LteDataTcm 0x00014fe3 0x1209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x00014fe3 0x4ad _g_zPHY_SID
+ 0x00015490 0xa82 _g_atzPHY_SAD
+ 0x00015f12 0x118 _g_atzPHY_erfc_CsrcSFData
+ 0x0001602a 0xd2 _g_atzPHY_erfc_RxSFData
+ 0x000160fc 0xf0 _g_atzPHY_erfc_TxSFData
+ *(.LpcDataTcm)
+ .LpcDataTcm 0x000161ec 0x48 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x000161ec 0x2 _g_tAtCommM0PsmCtr
+ 0x000161ee 0x2 _g_tAtCommZspPsmCtr
+ 0x000161f0 0x3 _g_tAtCommPsApPsmCtr
+ 0x000161f3 0x10 _g_L1SoCResExpStat
+ 0x00016203 0x2 _g_dSleepLenMs
+ 0x00016205 0x1 _g_wImaskReg
+ 0x00016206 0x2b _g_tLpDebugInfo
+ 0x00016231 0x2 _g_dwPHY_USE_PSM
+ 0x00016233 0x1 _g_bPhyCanSendIcp
+ .LpcDataTcm 0x00016234 0x5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00016234 0x5 _g_wSharePwrUseBit
+ .LpcDataTcm 0x00016239 0x5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x00016239 0x1 _g_tL1IratLpCtrl
+ 0x0001623a 0x2 _g_L1Lpc_tSlaveShortGapFlg
+ 0x0001623c 0x1 _g_eWdRfCfgFlg
+ 0x0001623d 0x1 _g_eTdRfCfgFlg
+ .LpcDataTcm 0x0001623e 0x3 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x0001623e 0x1 _g_L1Lpc_wHarqTurboUsedFlg
+ 0x0001623f 0x1 _g_L1Lpc_w3gSyncUsedFlg
+ 0x00016240 0x1 _g_L1Lpc_w3gDpaUsedFlg
+ .LpcDataTcm 0x00016241 0x6b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x00016241 0x1 _g_bIsWUsePsm
+ 0x00016242 0x2 _g_tL1wLpCtrl
+ 0x00016244 0x49 _g_tL1wLpcInfo
+ 0x0001628d 0x2 _g_wLpmFactorBefSleep
+ 0x0001628f 0x2 _g_wLpmFactorAftWakeup
+ 0x00016291 0x1 _g_wLpmFactorErrCnt
+ 0x00016292 0x1 _g_bL1wLpcCfunReset
+ 0x00016293 0x2 _g_dwPrintSsfn1
+ 0x00016295 0x2 _g_dwPrintSsfn2
+ 0x00016297 0x2 _g_dwPrintSsfn3
+ 0x00016299 0x2 _g_dwPrintSsfn4
+ 0x0001629b 0x2 _g_dwSleepSchedSsfn
+ 0x0001629d 0x7 _g_tWLpmFactorLast
+ 0x000162a4 0x7 _g_tWLpmFactorCurent
+ 0x000162ab 0x1 _g_wLpmChangeOneDir
+ *(.dncsram)
+ .dncsram 0x000162ac 0x14c T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x000162ac 0x4 _odo_pool_list
+ 0x000162b0 0x100 _odo_pcb_list
+ 0x000163b0 0x1 _odo_max_valid_pid
+ 0x000163b1 0x26 _odo_config
+ 0x000163d7 0x21 _config_int_mask_list
+ .dncsram 0x000163f8 0x2 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x000163f8 0x2 _g_wHookCnt
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(.data)
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(.bss)
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(COMMON)
+ init*(COMMON)
+
+.reg_icp1
+ *(.icp_reg)
+
+.reg_icp2
+ *(.icp_reg_m0)
+
+.reg_dma 0x00980000 0x41a
+ *(.dma_reg)
+ .dma_reg 0x00980000 0x41a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ 0x00980000 0x400 _g_atDmaRegCh
+ 0x00980400 0x2 _g_dDmaIntTcStatus
+ 0x00980402 0x2 _g_dDmaSerrorStatus
+ 0x00980404 0x2 _g_dDmaDerrorStatus
+ 0x00980406 0x2 _g_dDmaCfgError
+ 0x00980408 0x2 _g_dDmaRawIntTcStatus
+ 0x0098040a 0x2 _g_dDmaRawIntSerrorStatus
+ 0x0098040c 0x2 _g_dDmaRawIntDerrorStatus
+ 0x0098040e 0x2 _g_dDmaRawIntCfgErrorStatus
+ 0x00980410 0x2 _g_dDmaWorkingStatus
+ 0x00980412 0x2 _g_dDmaGroupOrder
+ 0x00980414 0x2 _g_dDmaArbitMode
+ 0x00980416 0x2 _g_dDmaIrqType
+ 0x00980418 0x2 _g_dDmaVersion
+
+.reg_icu 0x00400800 0x238
+ *(.icu_reg)
+ .icu_reg 0x00400800 0x238 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+ 0x00400800 0x2 _g_dRegIcuVersion
+ 0x00400802 0x2 _g_dRegIcuReserved1
+ 0x00400804 0x2 _g_dRegIcuReserved2
+ 0x00400806 0x2 _g_dRegIcuReserved3
+ 0x00400808 0x2 _g_dRegIcuIntIrqNum
+ 0x0040080a 0x2 _g_dRegIcuIntFiqNum
+ 0x0040080c 0x2 _g_dRegIcuIrqCur
+ 0x0040080e 0x2 _g_dRegIcuFiqCur
+ 0x00400810 0x2 _g_dRegIcuReserved4
+ 0x00400812 0x2 _g_dRegIcuIntStatus
+ 0x00400814 0x8 _g_dRegIcuReserved5
+ 0x0040081c 0x2 _g_dRegIcuTest
+ 0x0040081e 0x8 _g_dRegIcuIntSigBitSet
+ 0x00400826 0x8 _g_dRegIcuIntClr
+ 0x0040082e 0x8 _g_dRegIcuIntEn
+ 0x00400836 0x8 _g_dRegIcuIntDisEn
+ 0x0040083e 0x2 _g_dRegIcuReserved6
+ 0x00400840 0x100 _g_dRegIcuIntMode
+ 0x00400940 0x2 _g_dRegIcuReserved7
+ 0x00400942 0x2 _g_dRegIcuFiqNum
+ 0x00400944 0x2 _g_dRegIcuClkGateEn
+ 0x00400946 0x2 _g_dRegIcuReserved8
+ 0x00400948 0x8 _g_dRegIcuIntMask
+ 0x00400950 0x30 _g_dRegIcuReserved9
+ 0x00400980 0x8 _g_dRegIcuIntReq
+ 0x00400988 0xa8 _g_dRegIcuReserved10
+ 0x00400a30 0x8 _g_dRegIcuIntSetReq
+
+.reg4 0x7e080000 0x40
+ *(.top_reg)
+ .top_reg 0x7e080000 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_top.o)
+ 0x7e080000 0x2 _g_wL1wTop00SoftReset
+ 0x7e080002 0x2 _g_wL1wTop01GdtrHdtrChoose
+ 0x7e080004 0x2 _g_wL1wTop02Version1
+ 0x7e080006 0x2 _g_wL1wTop03BmiClkGate
+ 0x7e080008 0x2 _g_wL1wTop04ModeCtrl
+ 0x7e08000a 0x2 _g_wL1wTop05FixIqValue
+ 0x7e08000c 0x6 _g_wL1wTopReserved
+ 0x7e080012 0x2 _g_wL1wTop09GateClkCtrl
+ 0x7e080014 0x2 _g_wL1wTopAWdTimingRtVal0
+ 0x7e080016 0x2 _g_wL1wTopBWdTimingRtVal1
+ 0x7e080018 0x2 _g_wL1wTopCWdTimingNtVal0
+ 0x7e08001a 0x2 _g_wL1wTopDWdTimingNtVal1
+ 0x7e08001c 0x2 _g_wL1wTopEDmaIntBypass
+ 0x7e08001e 0x2 _g_wL1wTopReserved1
+ 0x7e080020 0x2 _g_wL1wTop10TpuRakeIntMask
+ 0x7e080022 0x2 _g_wL1wTop11RakeDfeRfcIntMask
+ 0x7e080024 0x2 _g_wL1wTop12TpuCsrAdrHsscchIntMask
+ 0x7e080026 0x2 _g_wL1wTop13CsrDtrPsrIntMask
+ 0x7e080028 0x2 _g_wL1wTop14TpuRakeIntStateMask
+ 0x7e08002a 0x2 _g_wL1wTop15RakeDfeRfcIntStateMask
+ 0x7e08002c 0x2 _g_wL1wTop16TpuCsrAdrHsscchIntStateMask
+ 0x7e08002e 0x2 _g_wL1wTop17CsrDtrPsrIntStateMask
+ 0x7e080030 0x2 _g_wL1wTop18TpuRakeIntStat
+ 0x7e080032 0x2 _g_wL1wTop19RakeDfeRfcIntStat
+ 0x7e080034 0x2 _g_wL1wTop1ATpuCsrAdrHsscchIntState
+ 0x7e080036 0x2 _g_wL1wTop1BCsrDtrPsrIntState
+ 0x7e080038 0x2 _g_wL1wTop1CReserved
+ 0x7e08003a 0x2 _g_wL1wTop1DReserved
+ 0x7e08003c 0x2 _g_wL1wTop1EReserved
+ 0x7e08003e 0x2 _g_wL1wTop1FReserved
+
+.reg5 0x7e080800 0xe0
+ *(.tpu_reg)
+ .tpu_reg 0x7e080800 0xe0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ 0x7e080800 0x2 _g_tRegTpuReset
+ 0x7e080802 0x2 _g_tRegTpuMrtrAdjConfig
+ 0x7e080804 0x2 _g_tRegTpuMrtrOffset
+ 0x7e080806 0x2 _g_tRegTpuMrtrCnt
+ 0x7e080808 0x2 _g_tRegTpuMrtrLatch
+ 0x7e08080a 0x2 _g_tRegTpuLocalMrtrCnt
+ 0x7e08080c 0x2 _g_tRegTpuLocalMrtrLatch
+ 0x7e08080e 0x2 _g_tRegTpuMacroCtrl
+ 0x7e080810 0x2 _g_tRegTpuMrtrGoal
+ 0x7e080812 0x2 _g_tRegTpuMrtrAdjustCtrl
+ 0x7e080814 0x2 _g_tRegTpuReserve0
+ 0x7e080816 0x2 _g_tRegTpuNt2RtOffset
+ 0x7e080818 0x2 _g_tRegTpuMrtrSSFN
+ 0x7e08081a 0x2 _g_tRegTpuLocalMrtrSSFN
+ 0x7e08081c 0x2 _g_tRegTpuMrtrSuperfrGoal
+ 0x7e08081e 0x2 _g_tRegTpuTip
+ 0x7e080820 0x4 _g_tRegTpuReserve1
+ 0x7e080824 0x2 _g_tRegTpuRestore
+ 0x7e080826 0x2 _g_tRegTpuSsfnOffRestore
+ 0x7e080828 0x2 _g_tRegTpuSsfnOff
+ 0x7e08082a 0x2 _g_tRegTpuMrtrLatchSSFN
+ 0x7e08082c 0x2 _g_tRegTpuLocalMrtrLatchSSFN
+ 0x7e08082e 0x52 _g_tRegTpuReserve2
+ 0x7e080880 0x36 _g_atRegTpuNtInt
+ 0x7e0808b6 0xa _g_atRegTpuRtInt
+ 0x7e0808c0 0x20 _g_tRegTpuReserve4
+
+.reg6 0x7e082000 0x2420
+ *(.rfc_reg)
+ .rfc_reg 0x7e082000 0x2420 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ 0x7e082000 0x2 _g_dRegRfcReset
+ 0x7e082002 0x2 _g_dRegRfcGpioVal
+ 0x7e082004 0x2 _g_dRegRfcFilterEn
+ 0x7e082006 0x2 _g_dRfcSpiReadData
+ 0x7e082008 0x2 _g_dRfcFAgcEventEn
+ 0x7e08200a 0x2 _g_dRegRfcFAgcRldVal
+ 0x7e08200c 0x4 _g_tRegRfcAnt0FAgcCtrlData
+ 0x7e082010 0x4 _g_tRegRfcAnt1FAgcCtrlData
+ 0x7e082014 0x2 _g_dRegRfcFAgcSpiBitSel
+ 0x7e082016 0x2 _g_dRegRfcFAgcTimeOffst
+ 0x7e082018 0x2 _g_dRegRfcFAgcEn
+ 0x7e08201a 0x2 _g_dRegRfcDebugSel
+ 0x7e08201c 0x2 _g_dRegRfcG1GpioSyncSel
+ 0x7e08201e 0x2 _g_dRegRfcMrtrTpuSel
+ 0x7e082020 0x2 _g_dRegRfcIntSel
+ 0x7e082022 0x2 _g_dRegRfcIntTimeCfg
+ 0x7e082024 0x4 _g_adRegRfcCtrlRamRegEn
+ 0x7e082028 0x8 _g_adRegRfcCtrlRamRx0En0
+ 0x7e082030 0x8 _g_adRegRfcCtrlRamRx0En1
+ 0x7e082038 0x8 _g_adRegRfcCtrlRamRx1En0
+ 0x7e082040 0x8 _g_adRegRfcCtrlRamRx1En1
+ 0x7e082048 0x8 _g_adRegRfcCtrlRamTxEn0
+ 0x7e082050 0x2 _g_dRegRfcUnsualIntClr
+ 0x7e082052 0xe _g_adRegRfcSpiFormatMap
+ 0x7e082060 0x2 _g_dRegRfcRffeDataMap
+ 0x7e082062 0x2 _g_dRegRfcWRfcEn
+ 0x7e082064 0x2 _g_dRegRfcMrtrConCrrnt
+ 0x7e082066 0x8 _g_adRegRfcCtrlRamTxEn1
+ 0x7e08206e 0x2 _g_dRegRfcFAgcCtrlWordAnt01Lsb
+ 0x7e082070 0x2 _g_dRegRfcFAgcCtrlWordAnt11Lsb
+ 0x7e082072 0x2 _g_dRegRfcFAgcCtrlWordAntSecMsb
+ 0x7e082074 0x2 _g_dRegRfcFAgcTimeInterval
+ 0x7e082076 0x18a _g_adReserved5
+ 0x7e082200 0x5a _g_atRegRfcCtrlReg
+ 0x7e08225a 0x6 _g_tRegRfcCtrlReg15
+ 0x7e082260 0x1a0 _g_adReserved6
+ 0x7e082400 0x20 _g_atRegRfcRxTu
+ 0x7e082420 0x1e0 _g_adReserved1
+ 0x7e082600 0x20 _g_atRegRfcTxTu
+ 0x7e082620 0x1e0 _g_adReserved2
+ 0x7e082800 0x40 _g_adRegRfcFastAgcRam
+ 0x7e082840 0x7c0 _g_adReserved3
+ 0x7e083000 0x100 _g_atRegRfcCtrlRamReg
+ 0x7e083100 0x300 _g_adReserved4
+ 0x7e083400 0x400 _g_atRegRfcCtrlRamRx0
+ 0x7e083800 0x400 _g_atRegRfcCtrlRamRx1
+ 0x7e083c00 0x400 _g_atRegRfcCtrlRamTx
+ 0x7e084000 0x2 _g_dRegDfeRxVersion
+ 0x7e084002 0x2 _g_dRegDfeRxReset
+ 0x7e084004 0x2 _g_dRegDfeRxAntEn
+ 0x7e084006 0x2 _g_dRegDfeRxAnt0ClkCtrl
+ 0x7e084008 0x2 _g_dRegDfeRxAnt1ClkCtrl
+ 0x7e08400a 0x2 _g_dRegDfeRxFilterEnDelay
+ 0x7e08400c 0x2 _g_dRegDfeRxDagcDelay
+ 0x7e08400e 0x2 _g_dRegDfeRxCompEn
+ 0x7e084010 0x2 _g_dRegDfeRxEstLen
+ 0x7e084012 0x2 _g_dRegDfeRxAnt0DcEst
+ 0x7e084014 0x2 _g_dRegDfeRxAnt1DcEst
+ 0x7e084016 0x2 _g_dRegDfeRxAnt0DcComp
+ 0x7e084018 0x2 _g_dRegDfeRxAnt1DcComp
+ 0x7e08401a 0x2 _g_dRegDfeRxAnt0IqEstSum
+ 0x7e08401c 0x2 _g_dRegDfeRxAnt1IqEstSum
+ 0x7e08401e 0x2 _g_dRegDfeRxRxAnt0IqCorr
+ 0x7e084020 0x2 _g_dRegDfeRxRxAnt1IqCorr
+ 0x7e084022 0x2 _g_dRegDfeRxIqAmpComp
+ 0x7e084024 0x2 _g_dRegDfeRxIqPhaComp
+ 0x7e084026 0x2 _g_dRegDfeRxHwAgcGainInit
+ 0x7e084028 0x2 _g_dRegDfeRxAgcLfCoff
+ 0x7e08402a 0x2 _g_dRegDfeRxAgcTarget
+ 0x7e08402c 0x2 _g_dRegDfeRxAgcMaxGain
+ 0x7e08402e 0x2 _g_dReserved11
+ 0x7e084030 0x2 _g_dRegDfeRxAgcLfIntEn
+ 0x7e084032 0x2 _g_dRegDfeRxAgcMeanPwr
+ 0x7e084034 0x2 _g_dRegDfeRxAgcLoopOut
+ 0x7e084036 0x2 _g_dReserved12
+ 0x7e084038 0x2 _g_dReserved13
+ 0x7e08403a 0x2 _g_dRegDfeRxAnt0HwAgcGain
+ 0x7e08403c 0x2 _g_dRegDfeRxAnt1HwAgcGain
+ 0x7e08403e 0x2 _g_dRegDfeRxFreqCorrPhaVal
+ 0x7e084040 0x2 _g_dReserved10
+ 0x7e084042 0x2 _g_dRegDfeRxAnt0DagcMeanPwr
+ 0x7e084044 0x2 _g_dRegDfeRxAnt1DagcMeanPwr
+ 0x7e084046 0x2 _g_dRegDfeRxDagcCtrl
+ 0x7e084048 0x2 _g_dRegDfeRxDagcBitSel
+ 0x7e08404a 0x2 _g_dRegDfeRxFifoReset
+ 0x7e08404c 0x2 _g_dRegDfeRxIntfSel
+ 0x7e08404e 0x2 _g_dRegDfeRxDLIntf1Cfg
+ 0x7e084050 0x2 _g_dRegDfeRxDLIntf2Cfg
+ 0x7e084052 0x2 _g_dRegDfeRxDLIntf3Cfg
+ 0x7e084054 0x2 _g_dRegDfeRxDLIntfDebugSel
+ 0x7e084056 0x2 _g_dRegDfeRxDLIntfDebugData
+ 0x7e084058 0x2 _g_dRegDfeRxDLIntfFifoDebug
+ 0x7e08405a 0x2 _g_dRegDfeRxBypass
+ 0x7e08405c 0x2 _g_dRegDfeRxTestCtrl
+ 0x7e08405e 0x2 _g_adReserved9
+ 0x7e084060 0x2 _g_dRegDfeNotchFreq
+ 0x7e084062 0x2 _g_dRegDfeNotchFs
+ 0x7e084064 0x2 _g_dRegDfeNotchStart
+ 0x7e084066 0x2 _g_dRegDfeNotchTimeA
+ 0x7e084068 0x2 _g_dRegDfeNotchTimeBAnt0
+ 0x7e08406a 0x2 _g_dRegDfeNotchParKA
+ 0x7e08406c 0x2 _g_dRegDfeNotchParKBAnt0
+ 0x7e08406e 0x2 _g_dRegDfeNotchParARe
+ 0x7e084070 0x2 _g_dRegDfeNotchParAIm
+ 0x7e084072 0x2 _g_dRegDfeNotchParAOutRe
+ 0x7e084074 0x2 _g_dRegDfeNotchParAOutIm
+ 0x7e084076 0x2 _g_dRegDfeNotchCordicSt
+ 0x7e084078 0x2 _g_dRegDfeNotchTimeBAnt1
+ 0x7e08407a 0x2 _g_dRegDfeNotchParKBAnt1
+ 0x7e08407c 0x2 _g_dRegDfeRxDLIntf4Cfg
+ 0x7e08407e 0x2 _g_dRegDfeRxDLIntf5Cfg
+ 0x7e084080 0x2 _g_dRegDfeRxAgcRamClkSel
+ 0x7e084082 0x2 _g_dRegDfeNotch1TimeA
+ 0x7e084084 0x2 _g_dRegDfeNotch1ParKA
+ 0x7e084086 0x2 _g_dRegDfeNotch2TimeA
+ 0x7e084088 0x2 _g_dRegDfeNotch2ParKA
+ 0x7e08408a 0x2 _g_dRegDfeNotch1TimeBAnt0
+ 0x7e08408c 0x2 _g_dRegDfeNotch1ParKBAnt0
+ 0x7e08408e 0x2 _g_dRegDfeNotch2TimeBAnt0
+ 0x7e084090 0x2 _g_dRegDfeNotch2ParKBAnt0
+ 0x7e084092 0x2 _g_dRegDfeNotch1TimeBAnt1
+ 0x7e084094 0x2 _g_dRegDfeNotch1ParKBAnt1
+ 0x7e084096 0x2 _g_dRegDfeNotch2TimeBAnt1
+ 0x7e084098 0x2 _g_dRegDfeNotch2ParKBAnt1
+ 0x7e08409a 0x2 _g_dRegDfeNotch1ParARe
+ 0x7e08409c 0x2 _g_dRegDfeNotch1ParAIm
+ 0x7e08409e 0x2 _g_dRegDfeNotch2ParARe
+ 0x7e0840a0 0x2 _g_dRegDfeNotch2ParAIm
+ 0x7e0840a2 0x2 _g_dRegDfeNotchbyPass
+ 0x7e0840a4 0x2 _g_dRegDfeFcInitPhase
+ 0x7e0840a6 0x2 _g_dRegDfeFcRotValSum
+ 0x7e0840a8 0x158 _g_adReserved19
+ 0x7e084200 0xc8 _g_adAgcCwTable
+ 0x7e0842c8 0x138 _g_adReserved14
+ 0x7e084400 0x2 _g_dRegDfeTxReset
+ 0x7e084402 0x2 _g_dRegDfeTxAmpCorr
+ 0x7e084404 0x2 _g_dRegDfeTxPhaCorr
+ 0x7e084406 0x2 _g_dRegDfeTxDcComp
+ 0x7e084408 0x2 _g_dRegDfeTxFirBitSel
+ 0x7e08440a 0x2 _g_dRegDfeTxBypassCtrl
+ 0x7e08440c 0x2 _g_dRegDfeTxEnExtnd
+ 0x7e08440e 0x2 _g_dRegDfeTxEnCtrl
+ 0x7e084410 0x2 _g_dRegDfeTxChainEn
+ 0x7e084412 0x2 _g_dRegDfeTxIntfSel
+ 0x7e084414 0x2 _g_dRegDfeTxIntf1Cfg
+ 0x7e084416 0x2 _g_dRegDfeTxIntf2Cfg
+ 0x7e084418 0x2 _g_dRegDfeTxIntf3Cfg
+ 0x7e08441a 0x2 _g_dRegDfeTxClkGate
+ 0x7e08441c 0x2 _g_dRegDfeTxOutEnSel
+ 0x7e08441e 0x2 _g_dRegDfeTxFirDlyNum
+
+.reg7 0x7e084800 0xa00
+ *(.csr_reg)
+ .csr_reg 0x7e084800 0xa00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7e084800 0x2 _g_adCsrReserved2400
+ 0x7e084802 0x2 _g_tRegCsrFpgaVersion
+ 0x7e084804 0x2 _g_tRegCsrTestMode
+ 0x7e084806 0x2 _g_tRegCsrStepIqSel
+ 0x7e084808 0x2 _g_tRegCsrRotate0
+ 0x7e08480a 0x2 _g_tRegCsrRotateParaEn0
+ 0x7e08480c 0x2 _g_tRegCsrRotate1
+ 0x7e08480e 0x2 _g_tRegCsrRotateParaEn1
+ 0x7e084810 0x2 _g_tRegCsrOfflineSPSRRotate
+ 0x7e084812 0x2 _g_tRegCsrReadMrtrReq
+ 0x7e084814 0x2 _g_tRegCsrSetWdtReq
+ 0x7e084816 0x2 _g_tRegCsrIntMrtrValue
+ 0x7e084818 0x2 _g_tRegCsrFreqInd
+ 0x7e08481a 0x2 _g_tRegCsrFxEndBoundary
+ 0x7e08481c 0x2 _g_tRegCsrFxStartBoundary
+ 0x7e08481e 0x2 _g_tRegCsrDataValidEn
+ 0x7e084820 0x2 _g_tRegCsrPatternSoft
+ 0x7e084822 0x2 _g_tRegCsrPatternMode
+ 0x7e084824 0x2 _g_tRegCsrPatternIntEn
+ 0x7e084826 0x2 _g_tRegCsrTopClkGating
+ 0x7e084828 0x2 _g_tRegCsrTestpinSel
+ 0x7e08482a 0x2 _g_tRegCsrSaveDataEn
+ 0x7e08482c 0x2 _g_tRegCsrSaveDataSymNum
+ 0x7e08482e 0x2 _g_tRegCsrFsBuffMrtr
+ 0x7e084830 0x2 _g_tRegCsrFsBuffEndClear
+ 0x7e084832 0x6e _g_adCsrReserved1
+ 0x7e0848a0 0x2 _g_tRegCsrRdMrtrValue
+ 0x7e0848a2 0x2 _g_tRegCsrFsBuffState
+ 0x7e0848a4 0x2 _g_tRegCsrFsBuffEndMrtr
+ 0x7e0848a6 0x15a _g_adCsrReserved2
+ 0x7e084a00 0x2 _g_tRegCsrStep1Reset
+ 0x7e084a02 0x2 _g_tRegCsrNSlot1
+ 0x7e084a04 0x2 _g_tRegCsrStartEn1
+ 0x7e084a06 0x2 _g_tRegCsrMrtrS1
+ 0x7e084a08 0x2 _g_tRegCsrPeakWidth
+ 0x7e084a0a 0x2 _g_tRegCsrPeakMask
+ 0x7e084a0c 0x2 _g_tRegCsrGapModeIndex
+ 0x7e084a0e 0x2 _g_tRegCsrSatCtrlbits
+ 0x7e084a10 0x2 _g_tRegCsrS1ClkGating
+ 0x7e084a12 0x2 _g_tRegCsrStep1Start
+ 0x7e084a14 0x8c _g_adCsrReserved3
+ 0x7e084aa0 0x2 _g_tRegCsrOutMrtrS1
+ 0x7e084aa2 0x2 _g_tRegCsrSlotNo1
+ 0x7e084aa4 0x2 _g_tRegCsrStep1Status
+ 0x7e084aa6 0x2 _g_tRegCsrPowerAvg1
+ 0x7e084aa8 0x158 _g_adCsrReserved4
+ 0x7e084c00 0x2 _g_tRegCsrIcVersion
+ 0x7e084c02 0x2 _g_tRegCsrIcEnable
+ 0x7e084c04 0x2 _g_tRegCsrIcStartPos
+ 0x7e084c06 0x2 _g_tRegCsrIcCpichSlotHead
+ 0x7e084c08 0x2 _g_tRegCsrIcPrar
+ 0x7e084c0a 0x2 _g_tRegCsrIcScramblePra
+ 0x7e084c0c 0x2 _g_tRegCsrIcClkGatingBypas
+ 0x7e084c0e 0x2 _g_tRegCsrIcUpdate
+ 0x7e084c10 0x10 _g_adCsrReserved5
+ 0x7e084c20 0x2 _g_tRegCsrIcScchValue
+ 0x7e084c22 0x2 _g_tRegCsrIcCpichValue
+ 0x7e084c24 0x1dc _g_adCsrReserved6
+ 0x7e084e00 0x2 _g_tRegCsrStep2BReset
+ 0x7e084e02 0x2 _g_tRegCsrNSlot2B
+ 0x7e084e04 0x2 _g_tRegCsrMrtrS2B
+ 0x7e084e06 0x2 _g_tRegCsrTimeAdjMode2B
+ 0x7e084e08 0x2 _g_tRegCsrResyncWinWidth2B
+ 0x7e084e0a 0x8 _g_adCodeGroupListSet
+ 0x7e084e12 0x2 _g_tRegCsrBurstContextS2B
+ 0x7e084e14 0x2 _g_tRegCsrTimingAdjustS2B
+ 0x7e084e16 0x2 _g_tRegCsrMrtrS2BStart
+ 0x7e084e18 0x2 _g_tRegCsrStartEn2B
+ 0x7e084e1a 0x2 _g_tRegCsrS2bClkGateBypass
+ 0x7e084e1c 0x2 _g_tRegCsrStep2BStart
+ 0x7e084e1e 0x82 _g_adCsrReserved7
+ 0x7e084ea0 0x2 _g_tRegCsrMrtrS2BSlot
+ 0x7e084ea2 0x2 _g_tRegCsrSlotNo2B
+ 0x7e084ea4 0x2 _g_tRegCsrSlotNum2B
+ 0x7e084ea6 0x2 _g_tRegCsrGroupNum2B
+ 0x7e084ea8 0x2 _g_tRegCsrCorNormMax2B
+ 0x7e084eaa 0xe _g_atRegCsrAccCorTmPos2B
+ 0x7e084eb8 0x2 _g_tRegCsrMaxTmPosSel2B
+ 0x7e084eba 0x2 _g_tRegCsrSelfResyncS2B
+ 0x7e084ebc 0x2 _g_tRegCsrStep2BStatus
+ 0x7e084ebe 0x2 _g_tRegCsrBurstPatternS2B
+ 0x7e084ec0 0x10 _g_atRegCsrSlotNum2B
+ 0x7e084ed0 0x10 _g_atRegCsrGroupNum2B
+ 0x7e084ee0 0x10 _g_atRegCsrCorNormMax2B
+ 0x7e084ef0 0x10 _g_atRegCsrMaxTmPosSel2B
+ 0x7e084f00 0x2 _g_tRegCsrGrpSumMaxVal2B
+ 0x7e084f02 0xfe _g_adCsrReserved8
+ 0x7e085000 0x2 _g_tRegCsrStep3Reset
+ 0x7e085002 0x2 _g_tRegCsrNSlot3
+ 0x7e085004 0x2 _g_tRegCsrMrtrS3
+ 0x7e085006 0x2 _g_tRegCsrMrtrS3Slot
+ 0x7e085008 0x2 _g_tRegCsrScramblingCodeS3
+ 0x7e08500a 0x2 _g_tRegCsrResyncWinWidthS3
+ 0x7e08500c 0x2 _g_tRegCsrBurstContextS3
+ 0x7e08500e 0x2 _g_tRegCsrMrtrS3Start
+ 0x7e085010 0x2 _g_tRegCsrStartEn3
+ 0x7e085012 0x2 _g_tRegCsrStep3Start
+ 0x7e085014 0x2 _g_tRegCsrStep3ClkBypass
+ 0x7e085016 0x8a _g_adCsrReserved9
+ 0x7e0850a0 0x2 _g_tRegCsrSlotNo3
+ 0x7e0850a2 0x2 _g_tRegCsrCorNormAvg
+ 0x7e0850a4 0x10 _g_atRegCsrCorNormMax3
+ 0x7e0850b4 0x10 _g_atRegCsrTimeAdj3
+ 0x7e0850c4 0x2 _g_tRegCsrStep3Status
+ 0x7e0850c6 0x2 _g_tRegCsrBurstPatternS3
+ 0x7e0850c8 0x138 _g_adCsrReserved10
+
+.reg8 0x7e085200 0xb6
+ *(.meas_reg)
+ .meas_reg 0x7e085200 0xb6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ 0x7e085200 0x2 _g_tL1wRegMeasSoftReset
+ 0x7e085202 0x2 _g_tRegMeasBufOffline
+ 0x7e085204 0x2 _g_tRegMeasBufOffMrtr
+ 0x7e085206 0x2 _g_tRegMeasBufUpdate
+ 0x7e085208 0x2 _g_tRegMeasWorkMode
+ 0x7e08520a 0x2 _g_tRegMeasOnLineMrtr
+ 0x7e08520c 0x2 _g_tRegMeasOnLineAgc0Para
+ 0x7e08520e 0x2 _g_tRegMeasOnLineAgc1Para
+ 0x7e085210 0x2 _g_tRegMeasOnLineAgc0Mrtr
+ 0x7e085212 0x2 _g_tRegMeasOnLineAgc1Mrtr
+ 0x7e085214 0x2 _g_tRegMeasContxtSel
+ 0x7e085216 0x2 _g_tRegMeasSpsrParaCfg
+ 0x7e085218 0x2 _g_tL1wRegMeasSttdMode
+ 0x7e08521a 0x2 _g_tL1wRegMeasCell012
+ 0x7e08521c 0x2 _g_tL1wRegMeasCell345
+ 0x7e08521e 0x2 _g_tL1wRegMeasCell67
+ 0x7e085220 0x10 _g_atL1wMeasCellMrtr
+ 0x7e085230 0x2 _g_tRegMeasClkInfo
+ 0x7e085232 0x2 _g_tRegMeasParaUpdate
+ 0x7e085234 0x6e _g_adReserved
+ 0x7e0852a2 0x2 _g_tRegMeasSpsrStatus
+ 0x7e0852a4 0x2 _g_tRegMeasBurstPattern
+ 0x7e0852a6 0x10 _g_atL1wRegMeasCellAgc
+
+.reg9 0x7e086000 0x200
+ *(.csr_fullscan_reg)
+ .csr_fullscan_reg
+ 0x7e086000 0x200 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7e086000 0x2 _g_tRegCsrFsSoftReset
+ 0x7e086002 0x2 _g_tRegCsrFsAccLen
+ 0x7e086004 0x14 _g_atRegCsrFsDataOffset
+ 0x7e086018 0x28 _g_atRegCsrFsScrambleGroup
+ 0x7e086040 0x2 _g_tRegCsrFsScrambleGroup
+ 0x7e086042 0x2 _g_tRegCsrFsClkGating
+ 0x7e086044 0x2 _g_tRegCsrFsStart
+ 0x7e086046 0x5a _g_adCsrReserved11
+ 0x7e0860a0 0x2 _g_tRegCsrFsFirstDataMrtr
+ 0x7e0860a2 0x14 _g_atRegCsrFsPeakPowerPos
+ 0x7e0860b6 0x14 _g_atRegCsrFsPeakScrambleOffset
+ 0x7e0860ca 0x2 _g_tRegCsrFsInt
+ 0x7e0860cc 0x2 _g_dCsrFsNoise
+ 0x7e0860ce 0x132 _g_adCsrReserved12
+
+.reg10 0x7e086200 0x26e
+ *(.bch_reg)
+ .bch_reg 0x7e086200 0x26e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ 0x7e086200 0x2 _g_uRegBchSoftReset
+ 0x7e086202 0x2 _g_uRegBchTxdMode
+ 0x7e086204 0x2 _g_uRegBchBchPichSel
+ 0x7e086206 0x2 _g_uRegBchTtiSync
+ 0x7e086208 0x2 _g_uRegBchWindowTh
+ 0x7e08620a 0x2 _g_uRegBchPichOvsfK
+ 0x7e08620c 0x6c _g_atRegBchFingerConfig
+ 0x7e086278 0x2 _g_uRegBchClkGate
+ 0x7e08627a 0x186 _g_adRegBchReserved1
+ 0x7e086400 0x48 _g_atRegBchFingerStatus
+ 0x7e086448 0x12 _g_adRegBchViterbiOut
+ 0x7e08645a 0x10 _g_asdRegBchPichData
+ 0x7e08646a 0x2 _g_uRegBchTotalStatus
+ 0x7e08646c 0x2 _g_uRegBchCrcResult
+
+.reg11 0x7e086800 0xb6
+ *(.psr_reg)
+ .psr_reg 0x7e086800 0xb6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ 0x7e086800 0x2 _g_tRegPsrReset
+ 0x7e086802 0x2 _g_tRegPsrSuspendEn
+ 0x7e086804 0x2 _g_tRegPsrPilotPatternConfig
+ 0x7e086806 0x2 _g_tRegPsrClkGatePassConfig
+ 0x7e086808 0x2 _g_tRegPsrAntSelectCfg
+ 0x7e08680a 0x2 _g_tRegPsrWinPosCfg
+ 0x7e08680c 0x2 _g_tRegPsrRlInfoCfg
+ 0x7e08680e 0x2 _g_tRegPsrMasterRlEn
+ 0x7e086810 0x2 _g_tRegPsrRlSttdCfg
+ 0x7e086812 0x2 _g_tRegPsrPeriodCfg
+ 0x7e086814 0x2 _g_tRegPsrIntInfo
+ 0x7e086816 0xc _g_atRegPsrSrcAndChanCfg
+ 0x7e086822 0xc _g_atRegPsrRlMrtrCfg
+ 0x7e08682e 0x2 _g_tRegPsrStartPosCfg
+ 0x7e086830 0x2 _g_tRegPsrPosEnCfg
+ 0x7e086832 0x2 _g_tRegPsrCmModeConfig
+ 0x7e086834 0x2 _g_tRegPsrCmEnCfg
+ 0x7e086836 0x6a _g_wRegPsrCfg
+ 0x7e0868a0 0x2 _g_tRegPsrIntStatus
+ 0x7e0868a2 0x2 _g_tRegPsrProFileNum
+ 0x7e0868a4 0x2 _g_tRegPsrFrameNum
+ 0x7e0868a6 0x2 _g_tRegPsrWorkStatus
+ 0x7e0868a8 0x2 _g_tRegPsrCfgError
+ 0x7e0868aa 0xc _g_atRegPsrRlPosReports
+
+.reg12 0x7e087000 0x4c
+ *(.tx_reg)
+ .tx_reg 0x7e087000 0x4c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7e087000 0x4c _g_tRegTxReg
+
+.reg13 0x7e087600 0xf2
+ *(.utr_reg)
+ .utr_reg 0x7e087600 0xf2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ 0x7e087600 0xf2 _g_tL1wRegRtxUtrReg
+
+.reg14 0x7e087c00 0x40
+ *(.eutr_reg)
+ .eutr_reg 0x7e087c00 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ 0x7e087c00 0x40 _g_tL1wEutrParaConf
+
+//.reg15
+ *(.rake_reg)
+
+.reg16 0x7e088000 0x480
+ *(.rx_cfg_chip)
+ .rx_cfg_chip 0x7e088000 0x480 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e088000 0x480 _g_tRegRxRakeChipLvl
+
+.reg17 0x7e088800 0x240
+ *(.rx_cfg_symb)
+ .rx_cfg_symb 0x7e088800 0x240 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e088800 0x240 _g_tRegRxRakeSymbLvl
+
+.reg18 0x7e089000 0x38
+ *(.rx_cfg_comb)
+ .rx_cfg_comb 0x7e089000 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e089000 0x38 _g_tRegRxRakeCombLvl
+
+.reg19 0x7e089800 0xc0
+ *(.rx_cfg_post)
+ .rx_cfg_post 0x7e089800 0xc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e089800 0xc0 _g_tRegRxRakePostLvl
+
+.reg20 0x7e08a000 0xc00
+ *(.gdtr_reg)
+ .gdtr_reg 0x7e08a000 0xc00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7e08a000 0x200 _g_tRegRtxDtrReg
+ 0x7e08a200 0x600 _g_adReserve
+ 0x7e08a800 0x400 _g_tRegRtxDtrNewReg
+
+.reg21 0x7e08c000 0x1e
+ *(.eagch_reg)
+ .eagch_reg 0x7e08c000 0x1e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7e08c000 0x1e _g_tRegRtxAgchReg
+
+.adr_reg 0x7e08c400 0x164
+ *(.adr_reg)
+ .adr_reg 0x7e08c400 0x164 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08c400 0x2 _g_dL1wRegAdrVer
+ 0x7e08c402 0x2 _g_tL1wRegAdrCtrl
+ 0x7e08c404 0x4 _g_adL1wRegAdrReserved1
+ 0x7e08c408 0x2 _g_tL1wRegAdrAnt1Slot0Fc
+ 0x7e08c40a 0x2 _g_tL1wRegAdrAnt1Slot1Fc
+ 0x7e08c40c 0x2 _g_tL1wRegAdrAnt1Slot2Fc
+ 0x7e08c40e 0x2 _g_tL1wRegAdrAnt2Slot0Fc
+ 0x7e08c410 0x2 _g_tL1wRegAdrAnt2Slot1Fc
+ 0x7e08c412 0x2 _g_tL1wRegAdrAnt2Slot2Fc
+ 0x7e08c414 0x2 _g_adL1wRegAdrReserved2
+ 0x7e08c416 0x2 _g_tL1wRegAdrRxTxMode
+ 0x7e08c418 0x2 _g_tL1wRegAdrCir
+ 0x7e08c41a 0x2 _g_tL1wRegAdrCirAlpha
+ 0x7e08c41c 0x2 _g_dL1wRegAdrFingerMaskR1T1L
+ 0x7e08c41e 0x2 _g_dL1wRegAdrFingerMaskR1T1H
+ 0x7e08c420 0x2 _g_dL1wRegAdrFingerMaskR1T2L
+ 0x7e08c422 0x2 _g_dL1wRegAdrFingerMaskR1T2H
+ 0x7e08c424 0x2 _g_dL1wRegAdrFingerMaskR2T1L
+ 0x7e08c426 0x2 _g_dL1wRegAdrFingerMaskR2T1H
+ 0x7e08c428 0x2 _g_dL1wRegAdrFingerMaskR2T2L
+ 0x7e08c42a 0x2 _g_dL1wRegAdrFingerMaskR2T2H
+ 0x7e08c42c 0x2 _g_tL1wRegAdrNoiseThresh
+ 0x7e08c42e 0x4 _g_adL1wRegAdrReserved3
+ 0x7e08c432 0x2 _g_tL1wRegAdrDataPscCoeQ
+ 0x7e08c434 0x2 _g_tL1wRegAdrAntLambda
+ 0x7e08c436 0x2 _g_tL1wRegAdrDataPscCoeP
+ 0x7e08c438 0x2 _g_tL1wRegAdrCirFft
+ 0x7e08c43a 0x2 _g_tL1wRegAdrDataFft
+ 0x7e08c43c 0x2 _g_tL1wRegAdrRyyCoeff
+ 0x7e08c43e 0x2 _g_tL1wRegAdrSchCancelCoeff
+ 0x7e08c440 0x2 _g_tL1wRegAdrSchCancel
+ 0x7e08c442 0x2 _g_tL1wRegAdrCpichCodeX
+ 0x7e08c444 0x2 _g_tL1wRegAdrCpichCodeY
+ 0x7e08c446 0x2 _g_tL1wRegAdrHsscchHsdschCodeX
+ 0x7e08c448 0x2 _g_tL1wRegAdrHsscchHsdschCodeY
+ 0x7e08c44a 0x2 _g_tL1wRegAdrCpichHsscchChEn
+ 0x7e08c44c 0x2 _g_tL1wRegAdrHsdsch
+ 0x7e08c44e 0x2 _g_tL1wRegAdrHsscch
+ 0x7e08c450 0x2 _g_tL1wRegAdrChCompsEn
+ 0x7e08c452 0x2 _g_tL1wRegAdrSymCpichAlpha
+ 0x7e08c454 0x2 _g_tL1wRegAdrCltd1
+ 0x7e08c456 0x2 _g_tL1wRegAdrTimeCfg
+ 0x7e08c458 0x2 _g_tL1wRegAdrHsdschParaA
+ 0x7e08c45a 0x2 _g_tL1wRegAdrMemClkBypass
+ 0x7e08c45c 0x2 _g_tL1wRegAdrModuleClkBypass
+ 0x7e08c45e 0x2 _g_tL1wRegAdrAmMean
+ 0x7e08c460 0x2 _g_tL1wRegAdrAnt1EqNoise
+ 0x7e08c462 0x2 _g_tL1wRegAdrAnt2EqNoise
+ 0x7e08c464 0x9c _g_adL1wRegAdrReserved4
+ 0x7e08c500 0x3c _g_atL1wRegAdrCpichData
+ 0x7e08c53c 0x2 _g_dL1wRegAdrReserved5
+ 0x7e08c53e 0x2 _g_tL1wRegAdrCirSlotNum
+ 0x7e08c540 0x2 _g_dL1wRegAdrMaxPowerR1T1
+ 0x7e08c542 0x2 _g_dL1wRegAdrMaxPowerR2T1
+ 0x7e08c544 0x2 _g_dL1wRegAdrMaxPowerR1T2
+ 0x7e08c546 0x2 _g_dL1wRegAdrMaxPowerR2T2
+ 0x7e08c548 0x2 _g_dL1wRegAdrNoisePowerR1
+ 0x7e08c54a 0x2 _g_dL1wRegAdrNoisePowerR2
+ 0x7e08c54c 0x2 _g_dL1wRegAdrMaxPowerR1T1Bak
+ 0x7e08c54e 0x2 _g_dL1wRegAdrMaxPowerR2T1Bak
+ 0x7e08c550 0x2 _g_dL1wRegAdrMaxPowerR1T2Bak
+ 0x7e08c552 0x2 _g_dL1wRegAdrMaxPowerR2T2Bak
+ 0x7e08c554 0x2 _g_dL1wRegAdrNoisePowerR1Bak
+ 0x7e08c556 0x2 _g_dL1wRegAdrNoisePowerR2Bak
+ 0x7e08c558 0x6 _g_adL1wRegAdrCpichT1SlotAbs
+ 0x7e08c55e 0x6 _g_adL1wRegAdrCpichT2SlotAbs
+
+.ic_reg 0x7e08c600 0xd2
+ *(.ic_reg)
+ .ic_reg 0x7e08c600 0xd2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08c600 0x2 _g_tL1wRegIcVer
+ 0x7e08c602 0x2 _g_tL1wRegIcEnable
+ 0x7e08c604 0x2 _g_tL1wRegIcMode
+ 0x7e08c606 0x2 _g_uL1wRegIcSubFrameHead
+ 0x7e08c608 0x40 _g_tL1wRegIcCellFinger
+ 0x7e08c648 0x10 _g_atL1wRegIcScrcodeXY
+ 0x7e08c658 0x8 _g_atL1wRegIcSchCodeNum
+ 0x7e08c660 0x2 _g_tL1wRegIcBchLambda
+ 0x7e08c662 0x2 _g_tL1wRegIcSchLambda
+ 0x7e08c664 0x2 _g_tL1wRegIcAlpha
+ 0x7e08c666 0x2 _g_tL1wRegIcCpichLambda
+ 0x7e08c668 0x2 _g_tL1wRegIcAnt0Che4xPos
+ 0x7e08c66a 0x2 _g_tL1wRegIcAnt1Che4xPos
+ 0x7e08c66c 0x6 _g_uL1wRegIcAnt0CellSubFrmHead
+ 0x7e08c672 0xc _g_adL1wRegIcReserved1
+ 0x7e08c67e 0x2 _g_tL1wRegIcConfigOver
+ 0x7e08c680 0x18 _g_adL1wRegIcReserved2
+ 0x7e08c698 0x6 _g_uL1wRegAdjIcConfigTime
+ 0x7e08c69e 0x2 _g_tRegIcSubFrmHeadTime
+ 0x7e08c6a0 0x2 _g_uL1wRegIcConfigTime
+ 0x7e08c6a2 0x6 _g_tL1wRegIcCell0CpichSymModulus
+ 0x7e08c6a8 0x6 _g_tL1wRegIcCell1CpichSymModulus
+ 0x7e08c6ae 0x6 _g_tL1wRegIcCell2CpichSymModulus
+ 0x7e08c6b4 0x6 _g_tL1wRegIcCell3CpichSymModulus
+ 0x7e08c6ba 0x6 _g_tL1wRegIcCell0BchSymModulus
+ 0x7e08c6c0 0x6 _g_tL1wRegIcCell1BchSymModulus
+ 0x7e08c6c6 0x6 _g_tL1wRegIcCell2BchSymModulus
+ 0x7e08c6cc 0x6 _g_tL1wRegIcCell3BchSymModulus
+
+.hdtr_reg 0x7e08e000 0xce
+ *(.hdtr_reg)
+ .hdtr_reg 0x7e08e000 0xce T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08e000 0x2 _g_tL1wRegHdtrDemodule
+ 0x7e08e002 0x2 _g_tL1wRegHdtrHsdsch
+ 0x7e08e004 0xa _g_adL1wRegHdtrReserved1
+ 0x7e08e00e 0x2 _g_tL1wRegHdtr2ndRmNtp1
+ 0x7e08e010 0x2 _g_tL1wRegHdtr2ndRmNtp2
+ 0x7e08e012 0x2 _g_tL1wRegHdtr2ndRmNdi
+ 0x7e08e014 0x2 _g_dL1wRegHdtrReserved1
+ 0x7e08e016 0x2 _g_tL1wRegHdtrHarqId
+ 0x7e08e018 0x6 _g_adL1wRegHdtrReserved2
+ 0x7e08e01e 0x2 _g_tL1wRegHdtrTurboCfg
+ 0x7e08e020 0x14 _g_adL1wRegHdtrReserved3
+ 0x7e08e034 0x2 _g_tL1wRegHdtr2ndRmType
+ 0x7e08e036 0x2 _g_tL1wRegHdtr2ndRmEiniSys
+ 0x7e08e038 0x2 _g_tL1wRegHdtr2ndRmEplusSys
+ 0x7e08e03a 0x2 _g_tL1wRegHdtr2ndRmEminusSys
+ 0x7e08e03c 0x2 _g_tL1wRegHdtr2ndRmEiniP1
+ 0x7e08e03e 0x2 _g_tL1wRegHdtr2ndRmEplusP1
+ 0x7e08e040 0x2 _g_tL1wRegHdtr2ndRmEminusP1
+ 0x7e08e042 0x2 _g_tL1wRegHdtr2ndRmEiniP2
+ 0x7e08e044 0x2 _g_tL1wRegHdtr2ndRmEplusP2
+ 0x7e08e046 0x2 _g_tL1wRegHdtr2ndRmEminusP2
+ 0x7e08e048 0x2 _g_tL1wRegHdtr1stRmFlg
+ 0x7e08e04a 0x2 _g_tL1wRegHdtr2ndRmNp1
+ 0x7e08e04c 0x2 _g_tL1wRegHdtr2ndRmNp2
+ 0x7e08e04e 0x2 _g_tL1wRegHdtr1stRmEiniP1
+ 0x7e08e050 0x2 _g_tL1wRegHdtr1stRmEplusP1
+ 0x7e08e052 0x2 _g_tL1wRegHdtr1stRmEminusP1
+ 0x7e08e054 0x2 _g_tL1wRegHdtr1stRmEiniP2
+ 0x7e08e056 0x2 _g_tL1wRegHdtr1stRmEplusP2
+ 0x7e08e058 0x2 _g_tL1wRegHdtr1stRmEminusP2
+ 0x7e08e05a 0x2 _g_dL1wRegHdtrReserved2
+ 0x7e08e05c 0x2 _g_tL1wRegHdtrCodeBlk
+ 0x7e08e05e 0x2 _g_tL1wRegHdtrCrcRslt
+ 0x7e08e060 0x2 _g_tL1wRegHdtrTbSize
+ 0x7e08e062 0x14 _g_adL1wRegHdtrReserved4
+ 0x7e08e076 0x2 _g_tL1wRegHdtrEn
+ 0x7e08e078 0x2 _g_dL1wRegHdtrReserved3
+ 0x7e08e07a 0x2 _g_tL1wRegHdtrHarqAddr
+ 0x7e08e07c 0x2 _g_tL1wRegHdtr2ndRmNtsys
+ 0x7e08e07e 0x2 _g_tL1wRegHdtr2ndRmNsys
+ 0x7e08e080 0x2 _g_tL1wRegHdtrNdataCodeBlkNum
+ 0x7e08e082 0x2 _g_tL1wRegHdtrTbWithCrc
+ 0x7e08e084 0x2 _g_tL1wRegHdtrCtrl
+ 0x7e08e086 0x2 _g_tL1wRegHdtrLlrBitWidth
+ 0x7e08e088 0x4 _g_adL1wRegHdtrReserved5
+ 0x7e08e08c 0x2 _g_tL1wRegHdtrTargetBitWidth
+ 0x7e08e08e 0x2 _g_dL1wRegHdtrReserved8
+ 0x7e08e090 0x2 _g_tL1wRegHdtrHarqBitWidth
+ 0x7e08e092 0x2 _g_tL1wRegHdtrTurboModuleClkMsk
+ 0x7e08e094 0x6 _g_dL1wRegHdtrReserved9
+ 0x7e08e09a 0x2 _g_tL1wRegHdtrDeintlvClkCtrl
+ 0x7e08e09c 0x2 _g_tL1wRegHdtrSoftBitsClkCtrl
+ 0x7e08e09e 0x2 _g_dL1wRegHdtrReserved10
+ 0x7e08e0a0 0x2 _g_tL1wRegHdtrDrmClkCtrl
+ 0x7e08e0a2 0x2 _g_tL1wRegHdtrCrcClkCtrl
+ 0x7e08e0a4 0x2 _g_tL1wRegHdtrTrchRamClkCtrl
+ 0x7e08e0a6 0x2 _g_tL1wRegHdtrTurboSoftReset
+ 0x7e08e0a8 0x2 _g_tL1wRegHdtrStartCfg
+ 0x7e08e0aa 0x2 _g_tL1wRegHdtrDemoduleCfg
+ 0x7e08e0ac 0x14 _g_adL1wRegHdtrReserved6
+ 0x7e08e0c0 0x2 _g_tL1wRegHdtrSubFrm
+ 0x7e08e0c2 0x2 _g_tL1wRegHdtrModuleVer
+ 0x7e08e0c4 0x2 _g_tL1wRegHdtrChipName
+ 0x7e08e0c6 0x2 _g_adL1wRegHdtrReserved7
+ 0x7e08e0c8 0x2 _g_tL1wRegHdtrCrcRedundancy
+ 0x7e08e0ca 0x2 _g_tL1wRegHdtrHrnti
+ 0x7e08e0cc 0x2 _g_tL1wRegHdtrChStart
+
+.reg_hsscch 0x7e08e400 0x4c
+ *(.hsscch_reg)
+ .hsscch_reg 0x7e08e400 0x4c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08e400 0x2 _g_tL1wRegHsscchCtrl
+ 0x7e08e402 0x2 _g_tL1wRegHsscchMode
+ 0x7e08e404 0x2 _g_tL1wRegHsscchHrnti
+ 0x7e08e406 0x2 _g_tL1wRegHsscchViterbiThresh
+ 0x7e08e408 0x2 _g_tL1wRegHsscchPart1Rcv
+ 0x7e08e40a 0x2 _g_tL1wRegHsscchPart1Flg
+ 0x7e08e40c 0x2 _g_tL1wRegHsscchPart2Rcv
+ 0x7e08e40e 0x2 _g_tL1wRegHsscchHmRslt
+ 0x7e08e410 0x8 _g_atL1wRegHsscchSmRslt
+ 0x7e08e418 0x2 _g_tL1wRegHsscchSmPart1ChMsk
+ 0x7e08e41a 0x8 _g_atL1wRegHsscchS0Dist
+ 0x7e08e422 0x8 _g_atL1wRegHsscchMaxDist
+ 0x7e08e42a 0x8 _g_atL1wRegHsscchMinDist
+ 0x7e08e432 0x8 _g_atL1wRegHsscchPart1Sum
+ 0x7e08e43a 0x2 _g_tL1wRegHsscchPart2Rslt
+ 0x7e08e43c 0x2 _g_tL1wRegHsscchModuleVer
+ 0x7e08e43e 0x2 _g_tL1wRegHsscchChipName
+ 0x7e08e440 0x2 _g_tL1wRegHsscchBcchHrntiEn
+ 0x7e08e442 0x2 _g_tL1wRegHsscchBcchHrntiSmRslt
+ 0x7e08e444 0x2 _g_tL1wRegHsscchBcchHrntiS0Dist
+ 0x7e08e446 0x2 _g_tL1wRegHsscchBcchHrntiMaxDist
+ 0x7e08e448 0x2 _g_tL1wRegHsscchBcchHrntiMinDist
+ 0x7e08e44a 0x2 _g_tL1wRegHsscchBcchHrntiPart1Sum
+
+.reg22 0x7e08e800 0x30
+ *(.pich_reg)
+ .pich_reg 0x7e08e800 0x30 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ 0x7e08e800 0x2 _g_wRegPiAiVersion
+ 0x7e08e802 0x2 _g_tRegPiAiEnble
+ 0x7e08e804 0x2 _g_tRegPichMode
+ 0x7e08e806 0x2 _g_tRegAlpha
+ 0x7e08e808 0x2 _g_tRegRotatePara
+ 0x7e08e80a 0x10 _g_tRegFingerPara
+ 0x7e08e81a 0x2 _g_tRegPiAIOffsetPara
+ 0x7e08e81c 0x2 _g_tRegPiAIOvsfPara
+ 0x7e08e81e 0x2 _g_tRegAfcFingerNum
+ 0x7e08e820 0x2 _g_tRegAichSeqIndex
+ 0x7e08e822 0x2 _g_tRegSetUpdateTime
+ 0x7e08e824 0x2 _g_tRegConfigOver
+ 0x7e08e826 0x4 _g_tRegCpichPower
+ 0x7e08e82a 0x2 _g_tRegAichAmplitude
+ 0x7e08e82c 0x2 _g_tRegConfigState
+ 0x7e08e82e 0x2 _g_tRegConfigTime
+
+.reg23
+ *(.slotbuf_reg)
+
+.less_reg 0x7e08f400 0x280
+ *(.less_reg)
+ .less_reg 0x7e08f400 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08f400 0x200 _g_atL1wRegLessTbCfg
+ 0x7e08f600 0x2 _g_tL1wRegLessReset
+ 0x7e08f602 0x2 _g_tL1wRegLessDataOrder
+ 0x7e08f604 0x2 _g_tL1wRegLessHrnti
+ 0x7e08f606 0x2 _g_tL1wRegLessSubFrm
+ 0x7e08f608 0x2 _g_tL1wRegLessTurboCtrl
+ 0x7e08f60a 0x2 _g_tL1wRegLessClkCtrl
+ 0x7e08f60c 0x2 _g_tL1wRegLessLlrRepBitWidth
+ 0x7e08f60e 0x2 _g_tL1wRegLessTranPara
+ 0x7e08f610 0x2 _g_tL1wRegLessUpdate
+ 0x7e08f612 0x6e _g_adL1wRegLessReserved1
+
+.reg24 0x7c080000 0x280
+ *(.csr_reg_ram)
+ .csr_reg_ram 0x7c080000 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7c080000 0x78 _g_atRegCsrStep1Peek
+ 0x7c080078 0x8 _g_adCsrReserved13
+ 0x7c080080 0x78 _g_atRegCsrStep1PeekVal
+ 0x7c0800f8 0x108 _g_adCsrReserved14
+ 0x7c080200 0x80 _g_dwCodeListSet
+
+.reg25 0x7c080400 0xd0
+ *(.meas_ram)
+ .meas_ram 0x7c080400 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ 0x7c080400 0xd0 _g_atL1wRegMeasResultInfo
+
+.reg26 0x7c080600 0x300
+ *(.bch_ram)
+ .bch_ram 0x7c080600 0x300 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ 0x7c080600 0x300 _g_atRegBchBmiSymbol
+
+.reg27 0x7c088000 0x398
+ *(.psr_data_ram)
+ .psr_data_ram 0x7c088000 0x398 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ 0x7c088000 0x180 _g_atRegPsrAnt0RLFingerInfo
+ 0x7c088180 0xc _g_atRegPsrAnt0NoiseMantisse
+ 0x7c08818c 0xc _g_atRegPsrAnt0NoiseFingerCommExp
+ 0x7c088198 0x68 _g_wRegPsrRamCfg
+ 0x7c088200 0x180 _g_atRegPsrAnt1RLsFingerInfo
+ 0x7c088380 0xc _g_atRegPsrAnt1NoiseMantisse
+ 0x7c08838c 0xc _g_atRegPsrAnt1NoiseFingerCommExp
+
+.reg28 0x7c08e000 0xf00
+ *(.tx_ram0)
+ .tx_ram0 0x7c08e000 0xf00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7c08e000 0xf00 _g_atTxRam0
+
+.reg29 0x7c090000 0xf00
+ *(.tx_ram1)
+ .tx_ram1 0x7c090000 0xf00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7c090000 0xf00 _g_atTxRam1
+
+.reg30 0x7c092000 0x490
+ *(.utr_ram)
+ .utr_ram 0x7c092000 0x490 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ 0x7c092000 0x490 _g_awL1wRamUtrData
+
+.reg31 0x7c096000 0x500
+ *(.eutr_ram)
+ .eutr_ram 0x7c096000 0x500 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ 0x7c096000 0x500 _g_awL1wRamEutrData
+
+.reg32 0x7c09a000 0x140
+ *(.rx_raw_cpich)
+ .rx_raw_cpich 0x7c09a000 0x140 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a000 0x140 _g_atRegRxRawCpich
+
+.reg33 0x7c09a140 0x40
+ *(.rx_slotwt)
+ .rx_slotwt 0x7c09a140 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a140 0x40 _g_atRegRxSlotwt
+
+.reg34 0x7c09a180 0x40
+ *(.rx_afc)
+ .rx_afc 0x7c09a180 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a180 0x40 _g_atRegRxAfcRam
+
+.reg35 0x7c09a1c0 0x40
+ *(.rx_raw_noise)
+ .rx_raw_noise 0x7c09a1c0 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a1c0 0x40 _g_atRegRxRawNoise
+
+.reg36 0x7c09a240 0x30
+ *(.rx_comb_tpcpl)
+ .rx_comb_tpcpl
+ 0x7c09a240 0x30 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a240 0x30 _g_tRegRxCombTpcPilot
+
+.reg37 0x7c09a800 0x100
+ *(.rx_pilot)
+ .rx_pilot 0x7c09a800 0x100 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a800 0x100 _g_atRegRxRawPilot
+
+.reg38 0x7c09ac00 0x14
+ *(.rx_piaipage0)
+ .rx_piaipage0 0x7c09ac00 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ac00 0x14 _g_tRegRxCombPiAiPage0
+
+.reg39 0x7c09ac20 0x14
+ *(.rx_piaipage1)
+ .rx_piaipage1 0x7c09ac20 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ac20 0x14 _g_tRegRxCombPiAiPage1
+
+.reg40 0x7c09c000 0x280
+ *(.rx_dpch0)
+ .rx_dpch0 0x7c09c000 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09c000 0x280 _g_tRegRxCombDpch0
+
+.reg41 0x7c09c800 0x280
+ *(.rx_dpch1)
+ .rx_dpch1 0x7c09c800 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09c800 0x280 _g_tRegRxCombDpch1
+
+.reg42 0x7c09d800 0xa0
+ *(.rx_scch0)
+ .rx_scch0 0x7c09d800 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09d800 0xa0 _g_tRegRxCombScchPage0
+
+.reg43 0x7c09d900 0xa0
+ *(.rx_scch1)
+ .rx_scch1 0x7c09d900 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09d900 0xa0 _g_tRegRxCombScchPage1
+
+.reg44 0x7c09dc00 0x28
+ *(.rx_rghi00)
+ .rx_rghi00 0x7c09dc00 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc00 0x28 _g_tRegRxCombRgHiRl0Page0
+
+.reg45 0x7c09dc40 0x28
+ *(.rx_rghi01)
+ .rx_rghi01 0x7c09dc40 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc40 0x28 _g_tRegRxCombRgHiRl0Page1
+
+.reg46 0x7c09dc80 0x28
+ *(.rx_rghi10)
+ .rx_rghi10 0x7c09dc80 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc80 0x28 _g_tRegRxCombRgHiRl1Page0
+
+.reg47 0x7c09dcc0 0x28
+ *(.rx_rghi11)
+ .rx_rghi11 0x7c09dcc0 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dcc0 0x28 _g_tRegRxCombRgHiRl1Page1
+
+.reg48 0x7c09dd00 0x28
+ *(.rx_rghi20)
+ .rx_rghi20 0x7c09dd00 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd00 0x28 _g_tRegRxCombRgHiRl2Page0
+
+.reg49 0x7c09dd40 0x28
+ *(.rx_rghi21)
+ .rx_rghi21 0x7c09dd40 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd40 0x28 _g_tRegRxCombRgHiRl2Page1
+
+.reg50 0x7c09dd80 0x28
+ *(.rx_rghi30)
+ .rx_rghi30 0x7c09dd80 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd80 0x28 _g_tRegRxCombRgHiRl3Page0
+
+.reg51 0x7c09ddc0 0x28
+ *(.rx_rghi31)
+ .rx_rghi31 0x7c09ddc0 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ddc0 0x28 _g_tRegRxCombRgHiRl3Page1
+
+.reg52 0x7c09df00 0x14
+ *(.rx_agch0)
+ .rx_agch0 0x7c09df00 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09df00 0x14 _g_tRegRxCombAgchPage0
+
+.reg53 0x7c09df20 0x14
+ *(.rx_agch1)
+ .rx_agch1 0x7c09df20 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09df20 0x14 _g_tRegRxCombAgchPage1
+
+.reg54 0x7c0a0000 0x400
+ *(.gdtr_ram)
+ .gdtr_ram 0x7c0a0000 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7c0a0000 0x400 _g_uRegDtrTtiResultReg
+
+.reg55
+ *(.slotbuf_ram)
+
+.reg56 0x0009a300 0x36
+ *(.sleep_reg)
+ .sleep_reg 0x0009a300 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ 0x0009a300 0x2 _g_URegLpmTime1CtrlCmd
+ 0x0009a302 0x2 _g_uRegLpmTime1Cfg
+ 0x0009a304 0x2 _g_uRegLpmTime2Cfg
+ 0x0009a306 0x2 _g_uRegLpmTime3Cfg
+ 0x0009a308 0x2 _g_uRegLpmTime4Cfg
+ 0x0009a30a 0x2 _g_uRegLpmTime5PosedgeCfg
+ 0x0009a30c 0x2 _g_uRegLpmTime5EngedgeCfg
+ 0x0009a30e 0x2 _g_uRegLpmMrtrTrace
+ 0x0009a310 0x2 _g_uRegLpmLocalMrtrTrace
+ 0x0009a312 0x2 _g_uRegLpm32KCailSelCfg
+ 0x0009a314 0x2 _g_dRegLpmCount32K
+ 0x0009a316 0x2 _g_dRegLpm15MCountOffset
+ 0x0009a318 0x2 _g_dRegLpmReserve2
+ 0x0009a31a 0x2 _g_dRegLpm32KFactorInteg
+ 0x0009a31c 0x2 _g_dRegLpm32KFactorDecimal
+ 0x0009a31e 0x2 _g_dRegLpm32KSoftFactorInteg
+ 0x0009a320 0x2 _g_dRegLpm32KSoftFactorDecimal
+ 0x0009a322 0x2 _g_dRegLpmSoftReset
+ 0x0009a324 0x2 _g_dRegLpmMrtrOffset
+ 0x0009a326 0x2 _g_uRegLowPowerCtrl
+ 0x0009a328 0x2 _g_dRegLpmSuperframeOff
+ 0x0009a32a 0x2 _g_dRegLpmReserve3
+ 0x0009a32c 0x2 _g_URegLpmTime2CtrlCmd
+ 0x0009a32e 0x2 _g_URegLpmTime3CtrlCmd
+ 0x0009a330 0x2 _g_URegLpmTime4CtrlCmd
+ 0x0009a332 0x2 _g_URegLpmTime5CtrlCmd
+ 0x0009a334 0x2 _g_tRegLpmClkEnDisable
+
+.reg57 0x7c250000 0x34
+ *(.rffe_reg)
+ .rffe_reg 0x7c250000 0x34 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ 0x7c250000 0x2 _g_dRegRffeReset
+ 0x7c250002 0x2 _g_dRegRffeRdSpeedSet
+ 0x7c250004 0xe _g_adReserved16
+ 0x7c250012 0x2 _g_dRegRffeWcdmaRdData
+ 0x7c250014 0x4 _g_adReserved17
+ 0x7c250018 0x2 _g_dRegRffeCh0Packet
+ 0x7c25001a 0x16 _g_adReserved18
+ 0x7c250030 0x2 _g_dRegRffeConCrrnt
+ 0x7c250032 0x2 _g_dRegRffeFreqDiv
+
+.reg58
+ *(.spi_reg)
+
+.adr_ram 0x7c0b0000 0x400
+ *(.adr_ram)
+ .adr_ram 0x7c0b0000 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7c0b0000 0x80 _g_atL1wRamAdrCirR1T1
+ 0x7c0b0080 0x80 _g_atL1wRamAdrCirR2T1
+ 0x7c0b0100 0x80 _g_atL1wRamAdrCirR1T2
+ 0x7c0b0180 0x80 _g_atL1wRamAdrCirR2T2
+ 0x7c0b0200 0x80 _g_atL1wRamAdrCirR1T1Bak
+ 0x7c0b0280 0x80 _g_atL1wRamAdrCirR2T1Bak
+ 0x7c0b0300 0x80 _g_atL1wRamAdrCirR1T2Bak
+ 0x7c0b0380 0x80 _g_atL1wRamAdrCirR2T2Bak
+
+.hdtr_ram 0x7c0c0000 0xa4e
+ *(.hdtr_ram)
+ .hdtr_ram 0x7c0c0000 0xa4e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7c0c0000 0xa4e _g_adL1wRamHdtr
+
+.piai_ram 0x7c0c8000 0xd0
+ *(.piai_ram)
+ .piai_ram 0x7c0c8000 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ 0x7c0c8000 0x20 _g_tRegEAISymbolRam
+ 0x7c0c8020 0x20 _g_tRegRservedRam
+ 0x7c0c8040 0x40 _g_tRegPIAISymbolRam
+ 0x7c0c8080 0x50 _g_tRegCpichSymbolRam
+
+.slotbuf_ram
+ *(.slotbuf_ram)
+
+.slotbuf_lte_reg
+ *(.slotbuf_lte_reg)
+
+.td_tpu_reg
+ *(.td_tpu_reg)
+
+.td_top_reg
+ *(.td_top_reg)
+
+.td_csr_reg
+ *(.td_csr_reg)
+
+.td_csr_dpram
+ *(.td_csr_dpram)
+
+.td_rfc_reg
+ *(.td_rfc_reg)
+
+.td_dst_reg
+ *(.td_dst_reg)
+
+.td_dst_dpram
+ *(.td_dst_dpram)
+
+.td_dst_interf_dpram
+ *(.td_dst_interf_dpram)
+
+.td_jd_reg
+ *(.td_jd_reg)
+
+.td_jd_dpram2
+ *(.td_jd_dpram2)
+
+.td_utr_dpram
+ *(.td_utr_dpram)
+
+.td_utr_reg
+ *(.td_utr_reg)
+
+.td_ulc_reg
+ *(.td_ulc_reg)
+
+.td_afc_reg
+ *(.td_afc_reg)
+
+.td_gdtr_reg
+ *(.td_gdtr_reg)
+
+.td_gdtr_dpram
+ *(.td_gdtr_dpram)
+
+.td_ul_hsupa_reg
+ *(.td_ul_hsupa_reg)
+
+.td_ul_hsupa_dpram
+ *(.td_ul_hsupa_dpram)
+
+.td_dm_rdb_reg
+ *(.td_dm_rdb_reg)
+
+.td_hdtr_reg
+ *(.td_hdtr_reg)
+
+.td_hdtr_dpram
+ *(.td_hdtr_dpram)
+
+.td_sleep_reg
+ *(.td_sleep_reg)
+
+.td_pslpm_reg
+ *(.td_pslpm_reg)
+
+.td_uart_reg
+ *(.td_uart_reg)
+
+.td_tfci_reg
+ *(.td_tfci_reg)
+
+.td_viterbi_reg
+ *(.td_viterbi_reg)
+
+.dst_slot_buf
+ *(.dst_slot_buf)
+ 0x00017000 __heap_start = 0x17000
+ 0x00017010 __heap_limit = 0x17010
+ 0x00017fff __stack_start = 0x17fff
+ 0x00017010 __stack_end = __heap_limit
+ 0x00000001 ___ZSP_G3___ = 0x1
+OUTPUT(T:/cp/phy/project/7520_phy_plat_zsp/bin/debug/proj_lte_w_td.out elf32-sdsp)
+
+.comment 0x00000000 0x4875
+ .comment 0x00000000 0x15 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ .comment 0x00000015 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ .comment 0x00000051 0x31 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+ .comment 0x00000082 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ .comment 0x000000be 0x3e T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+ .comment 0x000000fc 0x15 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ .comment 0x00000112 0x15 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ .comment 0x00000127 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ .comment 0x0000015b 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ .comment 0x0000018e 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ .comment 0x000001c0 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ .comment 0x000001f2 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ .comment 0x00000225 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ .comment 0x00000257 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ .comment 0x0000028c 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ .comment 0x000002be 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ .comment 0x000002f0 0x36 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ .comment 0x00000327 0x35 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ .comment 0x0000035c 0x31 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ .comment 0x0000038e 0x41 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ .comment 0x000003cf 0x3e T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ .comment 0x0000040d 0x41 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ .comment 0x0000044f 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ .comment 0x0000048d 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ .comment 0x000004cd 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ .comment 0x00000509 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ .comment 0x00000546 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ .comment 0x00000582 0x3b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ .comment 0x000005be 0x3b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ .comment 0x000005f9 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ .comment 0x0000063a 0x15 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ .comment 0x0000064f 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ .comment 0x0000068d 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ .comment 0x000006ca 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ .comment 0x00000706 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ .comment 0x00000743 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ .comment 0x00000781 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ .comment 0x000007bf 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ .comment 0x000007fc 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ .comment 0x0000083a 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ .comment 0x0000087a 0x44 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ .comment 0x000008be 0x15 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o)
+ .comment 0x000008d4 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ .comment 0x00000910 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ .comment 0x0000094d 0x15 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ .comment 0x00000962 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ .comment 0x000009a0 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ .comment 0x000009de 0x31 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(dmc_zsp_0x140_lp.o)
+ .comment 0x00000a0f 0x31 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o)
+ .comment 0x00000a41 0x31 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ .comment 0x00000a72 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ .comment 0x00000aa2 0x31 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ .comment 0x00000ad3 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ .comment 0x00000b02 0x30 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ .comment 0x00000b32 0x35 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ .comment 0x00000b67 0x36 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ .comment 0x00000b9e 0x31 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ .comment 0x00000bcf 0x31 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ .comment 0x00000c00 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ .comment 0x00000c2f 0x30 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ .comment 0x00000c5f 0x2f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ .comment 0x00000c8e 0x35 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ .comment 0x00000cc4 0x36 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ .comment 0x00000cfa 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ .comment 0x00000d2f 0x35 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ .comment 0x00000d64 0x36 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ .comment 0x00000d9a 0x38 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ .comment 0x00000dd2 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ .comment 0x00000e0d 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ .comment 0x00000e47 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ .comment 0x00000e83 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ .comment 0x00000ec0 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ .comment 0x00000efd 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ .comment 0x00000f39 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ .comment 0x00000f75 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ .comment 0x00000fb2 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ .comment 0x00000ff0 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ .comment 0x00001030 0x3f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ .comment 0x0000106f 0x3f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ .comment 0x000010ae 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ .comment 0x000010ee 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ .comment 0x0000112e 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ .comment 0x0000116c 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ .comment 0x000011a8 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ .comment 0x000011e8 0x3e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ .comment 0x00001226 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ .comment 0x00001262 0x3b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ .comment 0x0000129d 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ .comment 0x000012d9 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ .comment 0x00001317 0x3f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ .comment 0x00001356 0x3f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ .comment 0x00001396 0x3e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ .comment 0x000013d4 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ .comment 0x00001412 0x3f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ .comment 0x00001451 0x3e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ .comment 0x0000148f 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ .comment 0x000014cf 0x3e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ .comment 0x0000150d 0x3e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ .comment 0x0000154b 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ .comment 0x00001587 0x3b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ .comment 0x000015c3 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ .comment 0x00001600 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ .comment 0x0000163e 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ .comment 0x0000167a 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ .comment 0x000016b4 0x3b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ .comment 0x000016ef 0x3b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ .comment 0x0000172a 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ .comment 0x00001764 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ .comment 0x0000179e 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ .comment 0x000017d8 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ .comment 0x00001812 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ .comment 0x0000184c 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ .comment 0x00001886 0x39 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ .comment 0x000018c0 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ .comment 0x000018fa 0x3a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ .comment 0x00001934 0x3b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ .comment 0x0000196f 0x3b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
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+ 0x259e (size before relaxing)
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+ 0x4b6 (size before relaxing)
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+ 0x492 (size before relaxing)
+ .stab 0x001661c4 0x1b0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
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+ 0x22e (size before relaxing)
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+ 0x2d0 (size before relaxing)
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+ 0x22e (size before relaxing)
+ .stab 0x00166a76 0xc0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ 0xc6 (size before relaxing)
+ .stab 0x00166b36 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ 0x288 (size before relaxing)
+ .stab 0x00166c74 0x1e0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ 0x32a (size before relaxing)
+ .stab 0x00166e54 0x216 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
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+ .stab 0x0016706a 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
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+ .stab 0x00167178 0x294 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
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+ .stab 0x0016740c 0x14a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ 0x294 (size before relaxing)
+ .stab 0x00167556 0x15c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ 0x2a6 (size before relaxing)
+ .stab 0x001676b2 0x480 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ 0x5f4 (size before relaxing)
+ .stab 0x00167b32 0x1c8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ 0x312 (size before relaxing)
+ .stab 0x00167cfa 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ 0x2ca (size before relaxing)
+ .stab 0x00167e7a 0x288 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ 0x3fc (size before relaxing)
+ .stab 0x00168102 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ 0x288 (size before relaxing)
+ .stab 0x00168240 0x1bc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ 0x306 (size before relaxing)
+ .stab 0x001683fc 0x1d4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ 0x660 (size before relaxing)
+
+.stabstr 0x00000000 0x364cca
+ .stabstr 0x00000000 0x364cca /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ 0x0 (size before relaxing)
+
+.dmc_data 0x00000000 0x0
+
+.dmc_lp_data 0x00000000 0x0
+ 0x00017010 __stack_end.linker_defined = 0x17010
+ 0x00000ff0 __stack_size.linker_defined = 0xff0
diff --git a/do_package_tool/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh b/do_package_tool/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh
new file mode 100755
index 0000000..697130b
--- /dev/null
+++ b/do_package_tool/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_a_to_b.sh
@@ -0,0 +1,38 @@
+#!/bin/bash
+
+CURR_DIR=`pwd`
+TOP_DIR=$CURR_DIR/../../..
+
+
+#ap_imagefs
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_imagefs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_imagefs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_imagefs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_imagefs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_imagefs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_imagefs2.img
+
+#ap_rootfs.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_rootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_rootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_rootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_rootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_rootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_rootfs2.img
+
+#ap_caprootfs
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/ap_caprootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/ap_caprootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/ap_caprootfs2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_caprootfs.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/ap_caprootfs2.img
+
+#uboot
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins/uboot2.bin
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc/uboot2.bin
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/uboot2.bin
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/uboot2.bin
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/uboot.bin $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/uboot2.bin
+
+#oem
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins/ap_oem2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_4Gb/cap_oem2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_ref/cap_oem2.img
+cp -rvf $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/cap_oem.img $TOP_DIR/zx297520v3/prj_vehicle/allbins_dc_systemd/cap_oem2.img
\ No newline at end of file
diff --git a/do_package_tool/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_vehicle_dc_ref.sh b/do_package_tool/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_vehicle_dc_ref.sh
new file mode 100755
index 0000000..364ab03
--- /dev/null
+++ b/do_package_tool/allbins/zx297520v3/prj_vehicle/scripts_linux/copybin_vehicle_dc_ref.sh
@@ -0,0 +1,60 @@
+#!/bin/bash
+
+CURR_DIR=`pwd`
+TOP_DIR=$CURR_DIR/../../../..
+
+#partition
+cp -rvf $TOP_DIR/allbins/zx297520v3/prj_vehicle/config_dc_4Gb/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+
+#rpm
+cp -rvf $TOP_DIR/rpm/project/zx297520v3/bin/tos/modem_7520v3/evb_cpurpm.img $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/evb_cpurpm.img
+cp -rvf $TOP_DIR/rpm/project/zx297520v3/bin/tos/modem_7520v3/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/evb_cpurpm.img
+
+#phy
+cp -rvf $TOP_DIR/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/evb_cpuphy.bin
+cp -rvf $TOP_DIR/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/evb_cpuphy.bin
+
+
+
+#nv
+mkdir -p $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/config
+cp -rvf $TOP_DIR/allbins/zx297520v3/prj_evb/nv/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+cp -rvf $TOP_DIR/allbins/zx297520v3/prj_evb/nv/merge_lte/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+cp -rvf $TOP_DIR/allbins/zx297520v3/prj_vehicle/nv/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+cp -rvf $TOP_DIR/allbins/zx297520v3/prj_vehicle/nv_dc_ref/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+rm -rf $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/merge_lte
+rm -rf $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/ps_nopsm
+rm -rf $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/th_psm
+rm -rf $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/单天线
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/amtComm_nvro_0x00000000.bin
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/phyGgeAmtCali_nvro_0x00050000.bin
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/phyLteAmtCali_nvro_0x00008000.bin
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/phyTdsAmtCali_nvro_0x00048000.bin
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/phyWcdmaAmtCali_nvro_0x00058000.bin
+rm $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/phyLteaAmtCali_nvro_0x00078000.bin
+
+#uboot
+mkdir -p $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/dl_off
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/tboot.bin $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/tboot.bin
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/tloader.bin $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/tloader.bin
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/uboot.bin $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/uboot.bin
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/dl_off/zloader.bin $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/zloader.bin
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/u-boot $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/u-boot
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/u-boot.map $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/u-boot.map
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/z-load $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/z-load
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/z-load.map $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/z-load.map
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/dl_off/z-load $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/dl_off/z-load
+cp -rvf $TOP_DIR/boot/prj/zx297520v3/vehicle_dc_ref/bin/dl_off/z-load.map $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/boot/dl_off/z-load.map
+
+#ap
+cp -rvf $TOP_DIR/ap/project/zx297520v3/prj_vehicle_dc_ref/bin/220A1/allbins/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+cp -rvf $TOP_DIR/ap/project/zx297520v3/prj_vehicle_dc_ref/bin/220A1/elfs/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/
+
+#cap
+mkdir -p $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/cap
+cp -rvf $TOP_DIR/cap/allbins/zx297520v3/vehicle_dc_ref/bins/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/allbins_dc_ref/
+cp -rvf $TOP_DIR/cap/allbins/zx297520v3/vehicle_dc_ref/elf/* $TOP_DIR/allbins/zx297520v3/prj_vehicle/elf_dc_ref/cap/
+
+
diff --git a/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc b/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
new file mode 100755
index 0000000..439b293
--- /dev/null
+++ b/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
@@ -0,0 +1,10 @@
+PAGESIZE = "0x1000"
+ERASEBLOCK = "0x40000"
+UBI_LEB_SIZE = "253952"
+UBI_IMAGE_SEQ = "1024"
+
+#rootfs ubi参数配置
+#MKUBIFS_ARGS = "-m ${PAGESIZE} -e ${UBI_LEB_SIZE} -c 122 -x zlib -F"
+UBINIZE_ARGS = "-m ${PAGESIZE} -p ${ERASEBLOCK} -s ${PAGESIZE} -Q ${UBI_IMAGE_SEQ}"
+#userdata ubi参数配置
+USERDATA_UBINIZE_ARGS = "${UBINIZE_ARGS}"
diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
new file mode 100755
index 0000000..2b48930
--- /dev/null
+++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
new file mode 100755
index 0000000..2b48930
--- /dev/null
+++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
new file mode 100755
index 0000000..2b48930
--- /dev/null
+++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
new file mode 100755
index 0000000..5d7d82f
--- /dev/null
+++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
@@ -0,0 +1,1137 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+# CONFIG_INIT is not set
+# CONFIG_LINUXRC is not set
+# CONFIG_FEATURE_USE_INITTAB is not set
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+# CONFIG_FEATURE_INIT_SCTTY is not set
+# CONFIG_FEATURE_INIT_SYSLOG is not set
+# CONFIG_FEATURE_INIT_QUIET is not set
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE=""
+# CONFIG_FEATURE_INIT_MODIFY_CMDLINE is not set
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+# CONFIG_MDEV is not set
+# CONFIG_FEATURE_MDEV_CONF is not set
+# CONFIG_FEATURE_MDEV_RENAME is not set
+# CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set
+# CONFIG_FEATURE_MDEV_EXEC is not set
+# CONFIG_FEATURE_MDEV_LOAD_FIRMWARE is not set
+# CONFIG_FEATURE_MDEV_DAEMON is not set
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb b/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
new file mode 100755
index 0000000..7b8ff1d
--- /dev/null
+++ b/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
@@ -0,0 +1,66 @@
+#inherit externalsrc package
+
+DESCRIPTION = "lynq sim"
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=e1696b147d49d491bcb4da1a57173fff"
+DEPENDS += "libpal gstreamer1.0 glib-2.0 libapn liblynq-log libvendor-ril liblynq-shm libbinder"
+#inherit workonsrc
+WORKONSRC = "${TOPDIR}/../src/lynq/lib/liblynq-sim/"
+FILESEXTRAPATHS_prepend :="${TOPDIR}/../src/lynq/lib/:"
+SRC_URI = " \
+ file://liblynq-sim \
+ "
+
+SRC-DIR = "${S}/../liblynq-sim"
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+BB_INCLUDE_ADD = "--sysroot=${STAGING_DIR_HOST}"
+BB_LDFLAGS_ADD = "--sysroot=${STAGING_DIR_HOST} -Wl,--hash-style=gnu"
+#Parameters passed to do_compile()
+EXTRA_OEMAKE = "'RAT_CONFIG_C2K_SUPPORT = ${RAT_CONFIG_C2K_SUPPORT}'\
+ 'MTK_MULTI_SIM_SUPPORT = ${MTK_MULTI_SIM_SUPPORT}'\
+ 'TARGET_PLATFORM = ${TARGET_PLATFORM}'"
+
+FILES_${PN} = "${base_libdir}/*.so \
+ ${base_bindir}\
+ ${base_sbindir} \
+ /etc/dbus-1/system.d/"
+FILES_${PN}-dev = "/test \
+ ${includedir}"
+
+FILES_${PN}-doc = "/doc"
+
+FILES_${PN}-dbg ="${base_bindir}/.debug \
+ ${base_libdir}/.debug \
+ ${base_sbindir}/.debug"
+
+INSANE_SKIP_${PN} += "already-stripped"
+INSANE_SKIP_${PN} += "installed-vs-shipped"
+
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ if [ "${PACKAGE_ARCH}" = "cortexa7hf-vfp-vfpv4-neon" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ elif [ "${PACKAGE_ARCH}" = "cortexa7hf-neon-vfpv4" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ elif [ "${PACKAGE_ARCH}" = "cortexa53hf-neon-fp-armv8" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE -mhard-float -mfpu=neon-fp-armv8 -mfloat-abi=hard -mcpu=cortex-a53 -mtune=cortex-a53"
+ else
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ fi
+}
+
+do_install () {
+ oe_runmake install -C ${SRC-DIR} ROOT=${D}
+
+ if [ -d "${WORKONSRC}" ] ; then
+ install -d ${D}${includedir}/
+ cp -af ${SRC-DIR}/include/libsim ${D}${includedir}/
+ fi
+}
+
+addtask bachclean
+do_bachclean () {
+ oe_runmake clean
+}
diff --git a/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb b/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
new file mode 100755
index 0000000..69ad466
--- /dev/null
+++ b/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
@@ -0,0 +1,79 @@
+DESCRIPTION = "nvserver"
+#nvserver依赖libnvram库
+DEPENDS = "libmtd libnvram libflags libsd-daemon"
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://nvserver \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://nvserver.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://nvserver.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://nvserver.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append = "${ZXIC_EXTRA_CFLAGS}"
+
+#编译
+do_compile() {
+ make -C nvserver
+}
+
+#库文件的安装
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/nvserver/nvserver ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/nvserver.init ${D}${sysconfdir}/init.d/nvserver
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/nvserver.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/nvserver.sysvinit ${D}${sysconfdir}/init.d/nvserver
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/nvserver ${D}${sysconfdir}/rcS.d/S16nvserver
+ ln -s ../init.d/nvserver ${D}${sysconfdir}/rcS.d/K84nvserver
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/nvserver/nvserver ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/nvserver
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "nvserver.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+RDEPENDS_${PN} = "libmtd libnvram libflags libsd-daemon"
+
diff --git a/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc b/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
new file mode 100755
index 0000000..2efbe4d
--- /dev/null
+++ b/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
@@ -0,0 +1,510 @@
+SUMMARY = "Tiny versions of many common UNIX utilities in a single small executable"
+DESCRIPTION = "BusyBox combines tiny versions of many common UNIX utilities into a single small executable. It provides minimalist replacements for most of the utilities you usually find in GNU fileutils, shellutils, etc. The utilities in BusyBox generally have fewer options than their full-featured GNU cousins; however, the options that are included provide the expected functionality and behave very much like their GNU counterparts. BusyBox provides a fairly complete POSIX environment for any small or embedded system."
+HOMEPAGE = "https://www.busybox.net"
+BUGTRACKER = "https://bugs.busybox.net/"
+
+DEPENDS += "kern-tools-native virtual/crypt libnvram"
+
+# bzip2 applet in busybox is based on lightly-modified bzip2-1.0.4 source
+# the GPL is version 2 only
+LICENSE = "GPLv2 & bzip2-1.0.4"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=de10de48642ab74318e893a61105afbb \
+ file://archival/libarchive/bz/LICENSE;md5=28e3301eae987e8cfe19988e98383dae"
+
+SECTION = "base"
+
+# Whether to split the suid apps into a seperate binary
+BUSYBOX_SPLIT_SUID ?= "1"
+
+export EXTRA_CFLAGS = "${CFLAGS}"
+export EXTRA_LDFLAGS = "${LDFLAGS}"
+
+EXTRA_OEMAKE = "CC='${CC}' LD='${CCLD}' V=1 ARCH=${TARGET_ARCH} CROSS_COMPILE=${TARGET_PREFIX} SKIP_STRIP=y HOSTCC='${BUILD_CC}' HOSTCPP='${BUILD_CPP}'"
+
+PACKAGES =+ "${PN}-httpd ${PN}-udhcpd ${PN}-udhcpc ${PN}-syslog ${PN}-mdev ${PN}-hwclock"
+
+FILES_${PN}-httpd = "${sysconfdir}/init.d/busybox-httpd /srv/www"
+FILES_${PN}-syslog = "${sysconfdir}/init.d/syslog* ${sysconfdir}/syslog-startup.conf* ${sysconfdir}/syslog.conf* ${systemd_unitdir}/system/syslog.service ${sysconfdir}/default/busybox-syslog"
+FILES_${PN}-mdev = "${sysconfdir}/init.d/mdev ${sysconfdir}/mdev.conf ${sysconfdir}/mdev/*"
+FILES_${PN}-udhcpd = "${sysconfdir}/init.d/busybox-udhcpd"
+FILES_${PN}-udhcpc = "${sysconfdir}/udhcpc.d ${datadir}/udhcpc"
+FILES_${PN}-hwclock = "${sysconfdir}/init.d/hwclock.sh"
+
+INITSCRIPT_PACKAGES = "${PN}-httpd ${PN}-syslog ${PN}-udhcpd ${PN}-mdev ${PN}-hwclock"
+
+INITSCRIPT_NAME_${PN}-httpd = "busybox-httpd"
+INITSCRIPT_NAME_${PN}-hwclock = "hwclock.sh"
+INITSCRIPT_NAME_${PN}-mdev = "mdev"
+INITSCRIPT_PARAMS_${PN}-mdev = "start 04 S ."
+INITSCRIPT_NAME_${PN}-syslog = "syslog"
+INITSCRIPT_NAME_${PN}-udhcpd = "busybox-udhcpd"
+
+SYSTEMD_PACKAGES = "${PN}-syslog"
+SYSTEMD_SERVICE_${PN}-syslog = "${@bb.utils.contains('SRC_URI', 'file://syslog.cfg', 'busybox-syslog.service', '', d)}"
+
+RDEPENDS_${PN}-syslog = "busybox"
+CONFFILES_${PN}-syslog = "${sysconfdir}/syslog-startup.conf"
+RCONFLICTS_${PN}-syslog = "rsyslog sysklogd syslog-ng"
+
+CONFFILES_${PN}-mdev = "${sysconfdir}/mdev.conf"
+
+RRECOMMENDS_${PN} = "${PN}-udhcpc"
+
+RDEPENDS_${PN} = "${@["", "busybox-inittab"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]}"
+
+inherit cml1 systemd update-rc.d ptest
+
+# busybox's unzip test case needs zip command, which busybox itself does not provide
+RDEPENDS_${PN}-ptest = "zip"
+
+# internal helper
+def busybox_cfg(feature, tokens, cnf, rem):
+ if type(tokens) == type(""):
+ tokens = [tokens]
+ rem.extend(['/^[# ]*' + token + '[ =]/d' for token in tokens])
+ if feature:
+ cnf.extend([token + '=y' for token in tokens])
+ else:
+ cnf.extend(['# ' + token + ' is not set' for token in tokens])
+
+# Map distro features to config settings
+def features_to_busybox_settings(d):
+ cnf, rem = ([], [])
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv6', True, False, d), 'CONFIG_FEATURE_IPV6', cnf, rem)
+ busybox_cfg(True, 'CONFIG_LFS', cnf, rem)
+ busybox_cfg(True, 'CONFIG_FDISK_SUPPORT_LARGE_DISKS', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'nls', True, False, d), 'CONFIG_LOCALE_SUPPORT', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv4', True, False, d), 'CONFIG_FEATURE_IFUPDOWN_IPV4', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv6', True, False, d), 'CONFIG_FEATURE_IFUPDOWN_IPV6', cnf, rem)
+ busybox_cfg(bb.utils.contains_any('DISTRO_FEATURES', 'bluetooth wifi', True, False, d), 'CONFIG_RFKILL', cnf, rem)
+ return "\n".join(cnf), "\n".join(rem)
+
+# X, Y = ${@features_to_busybox_settings(d)}
+# unfortunately doesn't seem to work with bitbake, workaround:
+def features_to_busybox_conf(d):
+ cnf, rem = features_to_busybox_settings(d)
+ return cnf
+def features_to_busybox_del(d):
+ cnf, rem = features_to_busybox_settings(d)
+ return rem
+
+configmangle = '/CONFIG_EXTRA_CFLAGS/d; \
+ '
+OE_FEATURES := "${@features_to_busybox_conf(d)}"
+OE_DEL := "${@features_to_busybox_del(d)}"
+DO_IPv4 := "${@bb.utils.contains('DISTRO_FEATURES', 'ipv4', 1, 0, d)}"
+DO_IPv6 := "${@bb.utils.contains('DISTRO_FEATURES', 'ipv6', 1, 0, d)}"
+
+python () {
+ if "${OE_DEL}":
+ d.setVar('configmangle_append', "${OE_DEL}" + "\n")
+ if "${OE_FEATURES}":
+ d.setVar('configmangle_append',
+ "/^### DISTRO FEATURES$/a\\\n%s\n\n" %
+ ("\\n".join((d.expand("${OE_FEATURES}").split("\n")))))
+ d.setVar('configmangle_append',
+ "/^### CROSS$/a\\\n%s\n" %
+ ("\\n".join(["CONFIG_EXTRA_CFLAGS=\"${CFLAGS} ${HOST_CC_ARCH}\""
+ ])
+ ))
+}
+
+do_prepare_config () {
+ if [ "${BUILD_REPRODUCIBLE_BINARIES}" = "1" ]; then
+ export KCONFIG_NOTIMESTAMP=1
+ fi
+ sed -e '/CONFIG_STATIC/d' \
+ < ${WORKDIR}/busybox-1.33.1/defconfig > ${S}/.config
+ echo "# CONFIG_STATIC is not set" >> .config
+ for i in 'CROSS' 'DISTRO FEATURES'; do echo "### $i"; done >> \
+ ${S}/.config
+ sed -i -e '${configmangle}' ${S}/.config
+ if test ${DO_IPv4} -eq 0 && test ${DO_IPv6} -eq 0; then
+ # disable networking applets
+ mv ${S}/.config ${S}/.config.oe-tmp
+ awk 'BEGIN{net=0}
+ /^# Networking Utilities/{net=1}
+ /^#$/{if(net){net=net+1}}
+ {if(net==2&&$0 !~ /^#/&&$1){print("# "$1" is not set")}else{print}}' \
+ ${S}/.config.oe-tmp > ${S}/.config
+ fi
+ sed -i 's/CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"/CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -b"/' ${S}/.config
+ if [ -n "${DEBUG_PREFIX_MAP}" ]; then
+ sed -i 's|${DEBUG_PREFIX_MAP}||g' ${S}/.config
+ fi
+}
+
+do_configure () {
+ set -x
+ do_prepare_config
+ merge_config.sh -m .config ${@" ".join(find_cfgs(d))}
+ cml1_do_configure
+}
+
+do_compile() {
+ unset CFLAGS CPPFLAGS CXXFLAGS LDFLAGS
+ if [ "${BUILD_REPRODUCIBLE_BINARIES}" = "1" ]; then
+ export KCONFIG_NOTIMESTAMP=1
+ fi
+ if [ "${BUSYBOX_SPLIT_SUID}" = "1" -a x`grep "CONFIG_FEATURE_INDIVIDUAL=y" .config` = x ]; then
+ # split the .config into two parts, and make two busybox binaries
+ if [ -e .config.orig ]; then
+ # Need to guard again an interrupted do_compile - restore any backup
+ cp .config.orig .config
+ fi
+ cp .config .config.orig
+ oe_runmake busybox.cfg.suid
+ oe_runmake busybox.cfg.nosuid
+
+ # workaround for suid bug 10346
+ if ! grep -q "CONFIG_SH_IS_NONE" busybox.cfg.nosuid; then
+ echo "CONFIG_SH_IS_NONE" >> busybox.cfg.suid
+ fi
+
+ for i in `cat busybox.cfg.suid busybox.cfg.nosuid`; do
+ echo "# $i is not set" >> .config.disable.apps
+ done
+ merge_config.sh -m .config.orig .config.disable.apps
+ cp .config .config.nonapps
+ for s in suid nosuid; do
+ cat busybox.cfg.$s | while read item; do
+ grep -w "$item" .config.orig
+ done > .config.app.$s
+
+ # workaround for suid bug 10346
+ if [ "$s" = "suid" ] ; then
+ sed "s/.*CONFIG_SH_IS_NONE.*$/CONFIG_SH_IS_NONE=y/" -i .config.app.suid
+ fi
+
+ merge_config.sh -m .config.nonapps .config.app.$s
+ oe_runmake busybox_unstripped
+ mv busybox_unstripped busybox.$s
+ oe_runmake busybox.links
+ sort busybox.links > busybox.links.$s
+ rm busybox.links
+ done
+
+ # hard fail if sh is being linked to the suid busybox (detects bug 10346)
+ if grep -q -x "/bin/sh" busybox.links.suid; then
+ bbfatal "busybox suid binary incorrectly provides /bin/sh"
+ fi
+
+ # copy .config.orig back to .config, because the install process may check this file
+ cp .config.orig .config
+ # cleanup
+ rm .config.orig .config.app.suid .config.app.nosuid .config.disable.apps .config.nonapps
+ else
+ oe_runmake busybox_unstripped
+ cp busybox_unstripped busybox
+ oe_runmake busybox.links
+ fi
+}
+
+do_install () {
+ sed -i "s:^/bin/:BASE_BINDIR/:" busybox.links*
+ sed -i "s:^/sbin/:BASE_SBINDIR/:" busybox.links*
+ sed -i "s:^/usr/bin/:BINDIR/:" busybox.links*
+ sed -i "s:^/usr/sbin/:SBINDIR/:" busybox.links*
+
+ # Move arch/link to BINDIR to match coreutils
+ sed -i "s:^BASE_BINDIR/arch:BINDIR/arch:" busybox.links*
+ sed -i "s:^BASE_BINDIR/link:BINDIR/link:" busybox.links*
+
+ sed -i "s:^BASE_BINDIR/:${base_bindir}/:" busybox.links*
+ sed -i "s:^BASE_SBINDIR/:${base_sbindir}/:" busybox.links*
+ sed -i "s:^BINDIR/:${bindir}/:" busybox.links*
+ sed -i "s:^SBINDIR/:${sbindir}/:" busybox.links*
+
+ install -d ${D}${sysconfdir}/init.d
+
+ if ! grep -q "CONFIG_FEATURE_INDIVIDUAL=y" ${B}/.config; then
+ # Install ${base_bindir}/busybox, and the ${base_bindir}/sh link so the postinst script
+ # can run. Let update-alternatives handle the rest.
+ install -d ${D}${base_bindir}
+ if [ "${BUSYBOX_SPLIT_SUID}" = "1" ]; then
+ install -m 4755 ${B}/busybox.suid ${D}${base_bindir}
+ install -m 0755 ${B}/busybox.nosuid ${D}${base_bindir}
+ install -m 0644 ${S}/busybox.links.suid ${D}${sysconfdir}
+ install -m 0644 ${S}/busybox.links.nosuid ${D}${sysconfdir}
+ if grep -q "CONFIG_SH_IS_ASH=y" ${B}/.config; then
+ ln -sf busybox.nosuid ${D}${base_bindir}/sh
+ fi
+ # Keep a default busybox for people who want to invoke busybox directly.
+ # This is also useful for the on device upgrade. Because we want
+ # to use the busybox command in postinst.
+ ln -sf busybox.nosuid ${D}${base_bindir}/busybox
+ else
+ if grep -q "CONFIG_FEATURE_SUID=y" ${B}/.config; then
+ install -m 4755 ${B}/busybox ${D}${base_bindir}
+ else
+ install -m 0755 ${B}/busybox ${D}${base_bindir}
+ fi
+ install -m 0644 ${S}/busybox.links ${D}${sysconfdir}
+ if grep -q "CONFIG_SH_IS_ASH=y" ${B}/.config; then
+ ln -sf busybox ${D}${base_bindir}/sh
+ fi
+ # We make this symlink here to eliminate the error when upgrading together
+ # with busybox-syslog. Without this symlink, the opkg may think of the
+ # busybox.nosuid as obsolete and remove it, resulting in dead links like
+ # ${base_bindir}/sed -> ${base_bindir}/busybox.nosuid. This will make upgrading busybox-syslog fail.
+ # This symlink will be safely deleted in postinst, thus no negative effect.
+ ln -sf busybox ${D}${base_bindir}/busybox.nosuid
+ fi
+ else
+ install -d ${D}${base_bindir} ${D}${bindir} ${D}${libdir}
+ cat busybox.links | while read FILE; do
+ NAME=`basename "$FILE"`
+ install -m 0755 "0_lib/$NAME" "${D}$FILE.${BPN}"
+ done
+ # add suid bit where needed
+ for i in `grep -E "APPLET.*BB_SUID_((MAYBE|REQUIRE))" include/applets.h | grep -v _BB_SUID_DROP | cut -f 3 -d '(' | cut -f 1 -d ','`; do
+ find ${D} -name $i.${BPN} -exec chmod a+s {} \;
+ done
+ install -m 0755 0_lib/libbusybox.so.${PV} ${D}${libdir}/libbusybox.so.${PV}
+ ln -sf sh.${BPN} ${D}${base_bindir}/sh
+ ln -sf ln.${BPN} ${D}${base_bindir}/ln
+ ln -sf test.${BPN} ${D}${bindir}/test
+ if [ -f ${D}/linuxrc.${BPN} ]; then
+ mv ${D}/linuxrc.${BPN} ${D}/linuxrc
+ fi
+ install -m 0644 ${S}/busybox.links ${D}${sysconfdir}
+ fi
+
+ if grep -q "CONFIG_SYSLOGD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/syslog ${D}${sysconfdir}/init.d/syslog
+ install -m 644 ${WORKDIR}/syslog-startup.conf ${D}${sysconfdir}/syslog-startup.conf
+ install -m 644 ${WORKDIR}/syslog.conf ${D}${sysconfdir}/syslog.conf
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/syslog ${D}${sysconfdir}/rcS.d/S18syslog
+ fi
+ if grep -q "CONFIG_CROND=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-cron ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_HTTPD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-httpd ${D}${sysconfdir}/init.d/
+ install -d ${D}/srv/www
+ fi
+ if grep -q "CONFIG_UDHCPD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-udhcpd ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_HWCLOCK=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/hwclock.sh ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_UDHCPC=y" ${B}/.config; then
+ install -d ${D}${sysconfdir}/udhcpc.d
+ install -d ${D}${datadir}/udhcpc
+ install -m 0755 ${WORKDIR}/simple.script ${D}${sysconfdir}/udhcpc.d/50default
+ sed -i "s:/SBIN_DIR/:${base_sbindir}/:" ${D}${sysconfdir}/udhcpc.d/50default
+ install -m 0755 ${WORKDIR}/default.script ${D}${datadir}/udhcpc/default.script
+ fi
+ if grep -q "CONFIG_INETD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/inetd ${D}${sysconfdir}/init.d/inetd.${BPN}
+ sed -i "s:/usr/sbin/:${sbindir}/:" ${D}${sysconfdir}/init.d/inetd.${BPN}
+ install -m 0644 ${WORKDIR}/inetd.conf ${D}${sysconfdir}/
+ fi
+ if grep -q "CONFIG_MDEV=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/files-1.33.1/mdev ${D}${sysconfdir}/init.d/mdev
+ if grep "CONFIG_FEATURE_MDEV_CONF=y" ${B}/.config; then
+ install -m 644 ${WORKDIR}/mdev.conf ${D}${sysconfdir}/mdev.conf
+ install -d ${D}${sysconfdir}/mdev
+ install -m 0755 ${WORKDIR}/find-touchscreen.sh ${D}${sysconfdir}/mdev
+ install -m 0755 ${WORKDIR}/mdev-mount.sh ${D}${sysconfdir}/mdev
+ fi
+ fi
+ if grep -q "CONFIG_INIT=y" ${B}/.config && ${@bb.utils.contains('VIRTUAL-RUNTIME_init_manager','busybox','true','false',d)}; then
+ install -D -m 0755 ${WORKDIR}/rcS ${D}${sysconfdir}/init.d/rcS
+ install -D -m 0755 ${WORKDIR}/rcK ${D}${sysconfdir}/init.d/rcK
+ install -D -m 0755 ${WORKDIR}/rcS.default ${D}${sysconfdir}/default/rcS
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ if grep -q "CONFIG_KLOGD=y" ${B}/.config; then
+ install -d ${D}${systemd_unitdir}/system
+ sed 's,@base_sbindir@,${base_sbindir},g' < ${WORKDIR}/busybox-klogd.service.in \
+ > ${D}${systemd_unitdir}/system/busybox-klogd.service
+ fi
+
+ if grep -q "CONFIG_SYSLOGD=y" ${B}/.config; then
+ install -d ${D}${systemd_unitdir}/system
+ sed 's,@base_sbindir@,${base_sbindir},g' < ${WORKDIR}/busybox-syslog.service.in \
+ > ${D}${systemd_unitdir}/system/busybox-syslog.service
+ if [ ! -e ${D}${systemd_unitdir}/system/busybox-klogd.service ] ; then
+ sed -i '/klog/d' ${D}${systemd_unitdir}/system/busybox-syslog.service
+ fi
+ if [ -f ${WORKDIR}/busybox-syslog.default ] ; then
+ install -d ${D}${sysconfdir}/default
+ install -m 0644 ${WORKDIR}/busybox-syslog.default ${D}${sysconfdir}/default/busybox-syslog
+ fi
+ fi
+ fi
+
+ # Remove the sysvinit specific configuration file for systemd systems to avoid confusion
+ if ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'false', 'true', d)}; then
+ rm -f ${D}${sysconfdir}/syslog-startup.conf
+ fi
+}
+
+PTEST_BINDIR = "1"
+
+do_install_ptest () {
+ cp -r ${B}/testsuite ${D}${PTEST_PATH}/
+ # These access the internet which is not guaranteed to work on machines running the tests
+ rm -rf ${D}${PTEST_PATH}/testsuite/wget
+ sort ${B}/.config > ${D}${PTEST_PATH}/.config
+ ln -s /bin/busybox ${D}${PTEST_PATH}/busybox
+}
+
+inherit update-alternatives
+
+ALTERNATIVE_PRIORITY = "50"
+
+python do_package_prepend () {
+ # We need to load the full set of busybox provides from the /etc/busybox.links
+ # Use this to see the update-alternatives with the right information
+
+ dvar = d.getVar('D')
+ pn = d.getVar('PN')
+ def set_alternative_vars(links, target):
+ links = d.expand(links)
+ target = d.expand(target)
+ f = open('%s%s' % (dvar, links), 'r')
+ for alt_link_name in f:
+ alt_link_name = alt_link_name.strip()
+ alt_name = os.path.basename(alt_link_name)
+ # Match coreutils
+ if alt_name == '[':
+ alt_name = 'lbracket'
+ if alt_name == 'klogd' or alt_name == 'syslogd':
+ d.appendVar('ALTERNATIVE_%s-syslog' % (pn), ' ' + alt_name)
+ else:
+ d.appendVar('ALTERNATIVE_%s' % (pn), ' ' + alt_name)
+ d.setVarFlag('ALTERNATIVE_LINK_NAME', alt_name, alt_link_name)
+ if os.path.exists('%s%s' % (dvar, target)):
+ d.setVarFlag('ALTERNATIVE_TARGET', alt_name, target)
+ f.close()
+ return
+
+ if os.path.exists('%s/etc/busybox.links' % (dvar)):
+ set_alternative_vars("${sysconfdir}/busybox.links", "${base_bindir}/busybox")
+ else:
+ set_alternative_vars("${sysconfdir}/busybox.links.nosuid", "${base_bindir}/busybox.nosuid")
+ set_alternative_vars("${sysconfdir}/busybox.links.suid", "${base_bindir}/busybox.suid")
+}
+
+# This part of code is dedicated to the on target upgrade problem. It's known
+# that if we don't make appropriate symlinks before update-alternatives calls,
+# there will be errors indicating missing commands such as 'sed'.
+# These symlinks will later be updated by update-alternatives calls.
+# The update-alternatives.bbclass' postinst script runs firstly before other
+# postinst, but this part of code needs run firstly, so add this funtion.
+python populate_packages_updatealternatives_append() {
+ postinst = """
+test -n 2 > /dev/null || alias test='busybox test'
+if test "x$D" = "x"; then
+ # Remove busybox.nosuid if it's a symlink, because this situation indicates
+ # that we're installing or upgrading to a one-binary busybox.
+ if test -h ${base_bindir}/busybox.nosuid; then
+ rm -f ${base_bindir}/busybox.nosuid
+ fi
+ for suffix in "" ".nosuid" ".suid"; do
+ if test -e ${sysconfdir}/busybox.links$suffix; then
+ while read link; do
+ if test ! -e "$link"; then
+ # we can use busybox here because even if we are using splitted busybox
+ # we've made a symlink from /bin/busybox to /bin/busybox.nosuid.
+ busybox rm -f $link
+ busybox ln -s "${base_bindir}/busybox$suffix" $link
+ fi
+ done < ${sysconfdir}/busybox.links$suffix
+ fi
+ done
+fi
+if grep -q "^${base_bindir}/bash$" $D${sysconfdir}/busybox.links*; then
+ grep -q "^${base_bindir}/bash$" $D${sysconfdir}/shells || echo ${base_bindir}/bash >> $D${sysconfdir}/shells
+fi
+
+"""
+ d.prependVar('pkg_postinst_%s' % pkg, postinst)
+}
+
+pkg_postinst_${PN}_prepend () {
+ # Need path to saved utils, but they may have be removed on upgrade of busybox
+ # Only use shell to get paths. Also capture if busybox was saved.
+ BUSYBOX=""
+ if [ "x$D" = "x" ] ; then
+ for busybox_rmdir in /tmp/busyboxrm-*; do
+ if [ "$busybox_rmdir" != '/tmp/busyboxrm-*' ] ; then
+ export PATH=$busybox_rmdir:$PATH
+ if [ -e $busybox_rmdir/busybox* ] ; then
+ BUSYBOX="$busybox_rmdir/busybox*"
+ fi
+ fi
+ done
+ fi
+}
+
+pkg_postinst_${PN}_append () {
+ # If busybox exists in the remove directory it is because it was the only shell left.
+ if [ "x$D" = "x" ] ; then
+ if [ "x$BUSYBOX" != "x" ] ; then
+ update-alternatives --remove sh $BUSYBOX
+ rm -f $BUSYBOX
+ fi
+ fi
+}
+
+pkg_prerm_${PN} () {
+ # This is so you can make busybox commit suicide - removing busybox with no other packages
+ # providing its files, this will make update-alternatives work, but the update-rc.d part
+ # for syslog, httpd and/or udhcpd will fail if there is no other package providing sh
+ tmpdir=`mktemp -d /tmp/busyboxrm-XXXXXX`
+ ln -s ${base_bindir}/busybox $tmpdir/[
+ ln -s ${base_bindir}/busybox $tmpdir/test
+ ln -s ${base_bindir}/busybox $tmpdir/head
+ ln -s ${base_bindir}/busybox $tmpdir/sh
+ ln -s ${base_bindir}/busybox $tmpdir/basename
+ ln -s ${base_bindir}/busybox $tmpdir/echo
+ ln -s ${base_bindir}/busybox $tmpdir/mv
+ ln -s ${base_bindir}/busybox $tmpdir/ln
+ ln -s ${base_bindir}/busybox $tmpdir/dirname
+ ln -s ${base_bindir}/busybox $tmpdir/rm
+ ln -s ${base_bindir}/busybox $tmpdir/sed
+ ln -s ${base_bindir}/busybox $tmpdir/sort
+ ln -s ${base_bindir}/busybox $tmpdir/grep
+ ln -s ${base_bindir}/busybox $tmpdir/tail
+ export PATH=$PATH:$tmpdir
+
+ # If busybox is the shell, we need to save it since its the lowest priority shell
+ # Register saved bitbake as the lowest priority shell possible as back up.
+ if [ -n "$(readlink -f /bin/sh | grep busybox)" ] ; then
+ BUSYBOX=$(readlink -f /bin/sh)
+ cp $BUSYBOX $tmpdir/$(basename $BUSYBOX)
+ update-alternatives --install /bin/sh sh $tmpdir/$(basename $BUSYBOX) 1
+ fi
+}
+
+pkg_postrm_${PN} () {
+ # Add path to remove dir in case we removed our only grep
+ if [ "x$D" = "x" ] ; then
+ for busybox_rmdir in /tmp/busyboxrm-*; do
+ if [ "$busybox_rmdir" != '/tmp/busyboxrm-*' ] ; then
+ export PATH=$busybox_rmdir:$PATH
+ fi
+ done
+ fi
+
+ if grep -q "^${base_bindir}/bash$" $D${sysconfdir}/busybox.links* && [ ! -e $D${base_bindir}/bash ]; then
+ printf "$(grep -v "^${base_bindir}/bash$" $D${sysconfdir}/shells)\n" > $D${sysconfdir}/shells
+ fi
+}
+
+pkg_prerm_${PN}-syslog () {
+ # remove syslog
+ if test "x$D" = "x"; then
+ if test "$1" = "upgrade" -o "$1" = "remove"; then
+ ${sysconfdir}/init.d/syslog stop || :
+ fi
+ fi
+}
+
+RPROVIDES_${PN} += "${@bb.utils.contains('DISTRO_FEATURES', 'usrmerge', '/bin/sh /bin/ash', '', d)}"
diff --git a/upstream/linux-5.10/drivers/mfd/zx234290-core.c b/upstream/linux-5.10/drivers/mfd/zx234290-core.c
new file mode 100755
index 0000000..d43085f
--- /dev/null
+++ b/upstream/linux-5.10/drivers/mfd/zx234290-core.c
@@ -0,0 +1,680 @@
+/*
+ * zx234290-core.c -- Device access for ZX234290 PMICs
+ *
+ * Copyright 2016 ZTE Inc.
+ *
+ * Author: yuxiang<yu.xiang5@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/zx234290.h>
+
+#include <linux/debugfs.h>
+#include <asm/uaccess.h>
+
+#include <linux/of_gpio.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/delay.h>
+#include <dma_cfg.h>
+#include <linux/reboot.h>
+
+
+#define USER_RST_TO_NORMAL 1
+
+//#include <mach/peri_cfg.h>
+extern int zx234290_i2c_write_simple(u8 reg, void *src);
+extern int zx234290_i2c_read_simple(u8 reg, void *dest);
+
+//void __iomem * s_poweron_type_addr;
+ unsigned long s_poweron_type_addr;
+
+/*the power on info, boot_reason */
+typedef enum
+{
+ POWER_ON_NORMAL = 0,
+ POWER_ON_FOTA,
+ POWER_ON_CHARGING,
+ POWER_ON_RTC,
+ POWER_ON_RESET,
+ POWER_ON_HDT_TEST,
+ POWER_ON_EXCEPTRESET,
+ POWER_ON_LOCALUPDATE,
+ POWER_ON_BOOST_IN,
+ POWER_ON_AMT,
+ POWER_ON_PRODUCTION,
+ POWER_ON_INVALID,
+}T_ZDrvSys_PowerOn_Type;
+
+static struct resource regulator_resources[] = {
+ {
+ .name = "bulk-error",
+ .start = ZX234290_INT_BUCK_FAUL,
+ .end = ZX234290_INT_BUCK_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "ldo_error",
+ .start = ZX234290_INT_LDO_FAUL,
+ .end = ZX234290_INT_LDO_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource rtc_resources[] = {
+ {
+ .name = "zx234290-rtc-alarm",
+ .start = ZX234290_INT_RTC_ALRM,
+ .end = ZX234290_INT_RTC_ALRM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-min",
+ .start = ZX234290_INT_RTC_MIN,
+ .end = ZX234290_INT_RTC_MIN,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-hour",
+ .start = ZX234290_INT_RTC_HOUR,
+ .end = ZX234290_INT_RTC_HOUR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct resource powerkey_resources[] = {
+ {
+ .name = "zx234290-pwrkey-int",
+ .start = ZX234290_INT_PWRON,
+ .end = ZX234290_INT_PWRON,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+static struct mfd_cell zx234290_cell[] = {
+ {
+ .name = "zx234290-regulators",
+ .num_resources = 2,
+ .resources = ®ulator_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-rtc",
+ .num_resources = 3,
+ .resources = &rtc_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-gpadc",
+ },
+ {
+ .name = "zx234290-powerkey",
+ .num_resources = 1,
+ .resources = &powerkey_resources[0],
+ .id = -1,
+ },
+};
+
+unsigned int boot_reason = POWER_ON_NORMAL;
+struct wakeup_source * adc_wakelock;
+
+unsigned int * get_boot_reason_addr(void)
+{
+ return (unsigned int *)s_poweron_type_addr;
+}
+EXPORT_SYMBOL(get_boot_reason_addr);
+
+static void get_boot_reason(void)
+{
+ //boot_reason = *(unsigned int *)POWERON_TYPE_BASE;
+ if(s_poweron_type_addr){
+ boot_reason = readl(s_poweron_type_addr/*+0xf8*/);
+
+ printk(KERN_INFO "[PMU] get boot_reason = %d from 0x%x.\n",boot_reason,s_poweron_type_addr);
+ }
+ else
+ printk(KERN_INFO "[PMU] boot_reason is unknown.\n");
+}
+
+#if 1
+int zx234290_set_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data |= mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_set_bits);
+
+int zx234290_clear_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data &= ~mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_clear_bits);
+#endif
+
+static inline int zx234290_read(struct zx234290 *zx234290, u8 reg)
+{
+ u8 val;
+ int err;
+
+ err = zx234290->read(zx234290, reg, 1, &val);
+ if (err < 0)
+ return err;
+
+ return val;
+}
+
+static inline int zx234290_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ return zx234290->write(zx234290, reg, 1, &val);
+}
+
+#if 1
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg)
+{
+ int data;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ data = zx234290_read(zx234290, reg);
+ if (data < 0)
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return data;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_read);
+
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290_write(zx234290, reg, val);
+ if (err < 0)
+ dev_err(zx234290->dev, "Write for reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_write);
+#endif
+#if 1
+extern int Zx234290_SetUserReg_PSM(unsigned char data);
+
+void zx29_restart(const char * cmd)
+{
+ /*set reset value = 1*/
+ unsigned char status = ZX234290_USER_RST_TO_NORMAL;
+
+ printk(KERN_INFO"restart:enter reboot :reset to normal\n");
+
+ status = ZX234290_USER_RST_TO_NORMAL;
+ Zx234290_SetUserReg_PSM(status);
+}
+
+
+int pmu_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+
+ printk(" pmu reboot,in user,task is: %s\n", current->comm);
+ zx29_restart((char *) ptr);
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block pmu_reboot_notifier = {
+ .notifier_call = pmu_reboot_event
+};
+
+#endif
+
+
+
+int Zx234290_SetVldo6Onoff(void)
+{
+ int ret = 0;
+ u8 reg_addr=0, reg_val=0;
+ reg_addr = 0x21;
+ ret = zx234290_i2c_read_simple(reg_addr,®_val);
+ if (ret) {
+ return -EIO;
+ }
+ reg_val = reg_val&(~(1<<5));
+ ret = zx234290_i2c_write_simple(reg_addr, ®_val);
+ if (ret) {
+ return -EIO;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(Zx234290_SetVldo6Onoff);
+#if 0
+int zx297510_write_pmu_flag_charging(void)
+{
+ int ret = 0;
+ unsigned char reg = 0;
+ ret = zx234290_i2c_read_simple(0xf, ®);
+ reg = reg|0xff;
+ ret += zx234290_i2c_write_simple(0xf, ®);
+ ret = zx234290_i2c_read_simple(0xe, ®);
+ reg = reg|0x3;
+ ret += zx234290_i2c_write_simple(0xe, ®);
+ return ret;
+}
+#endif
+//static void __iomem* PMU_ADDR_VIR;
+//#define GPIO_PMU_PSHOLD ZX29_GPIO_51
+unsigned int gpio_num_pshold;
+
+void zx234290_pshold_pull_down(void)
+{
+ //PMU_ADDR_VIR = ioremap(0x10d6c0,4);
+ //__raw_writel(0x0,PMU_ADDR_VIR);
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,0);
+ else
+ printk("zx234290_pshold_pull_down error\n");
+}
+
+//extern int zx234290_rtc_disable_timer_alarm();
+EXPORT_SYMBOL(zx234290_pshold_pull_down);
+
+/***********yuwei added at 20170523**************/
+void zx234290_pshold_pull_up(void)
+{
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,1);
+ else
+ printk("zx234290_pshold_pull_up error\n");
+}
+/**************/
+
+static int zx234290_set_softon(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+static int zx234290_set_softon_PSM(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+
+static bool debug_stop_poweroff = false;
+module_param(debug_stop_poweroff, bool, 0644);
+//extern void zx29_restart(char str,const char * cmd);
+static void zx234290_power_off(void)
+{
+ //void __iomem *reset_charging_reg;
+ //reset_charging_reg = ZX29_TOP_VA;
+ //zx234290_rtc_disable_timer_alarm();
+ //Zx234290_SetVldo6Onoff();
+ u8 reg_poweron = 0;
+ int ret;
+
+ if(debug_stop_poweroff )
+ {
+ printk(KERN_INFO"debug_stop_poweroff= 0x%x, for debug, bug_on!!!!\n", debug_stop_poweroff);
+ panic("poweroff");
+ }
+ zx234290_set_softon_PSM(0);
+ zx234290_pshold_pull_down();
+#if 1
+ while(1){
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_STSA, ®_poweron);
+ if (ret) {
+ printk(KERN_INFO"power off pmu i2c read err\n");
+ break;
+ }
+ if((reg_poweron&(1<<ZX234290_STATUSA_POWERON_LSH))== 0)
+ break;
+ }
+ mdelay(50);
+ /*reset to charging*/
+ //zx29_restart(NULL,"drv_key reboot");
+#endif
+}
+
+
+#if defined(CONFIG_DEBUG_FS)
+static ssize_t debugfs_regs_write(struct file *file, const char __user *buf,size_t nbytes, loff_t *ppos)
+{
+ struct zx234290 *zx234290 = file->private_data;
+
+ unsigned int val1, val2;
+ u8 reg, value;
+ int ret;
+ char *kern_buf;
+
+ kern_buf = kzalloc(nbytes, GFP_KERNEL);
+
+ if (!kern_buf) {
+ printk(KERN_INFO "zx234290-core: Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ if (copy_from_user(kern_buf, (void __user *)buf, nbytes)) {
+ kfree(kern_buf);
+ return -ENOMEM;
+ }
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, kern_buf,nbytes);
+
+ ret = sscanf(kern_buf, "%x:%x", &val1, &val2);
+ if (ret < 2 || val1 > ZX234290_MAX_REGISTER ) {
+ printk(KERN_INFO "zx234290-core: failed to read user buf, ret=%d, input 0x%x:0x%x\n",
+ ret, val1, val2);
+ kfree(kern_buf);
+ return -EINVAL;
+ }
+ kfree(kern_buf);
+
+ reg = val1 & 0xff;
+ value = val2 & 0xff;
+ printk(KERN_INFO "%s input %x,%x; reg=%x,value=%x\n", __func__, val1, val2, reg, value);
+ ret = zx234290_i2c_write_simple(reg, &value);
+
+ return ret ? ret : nbytes;
+}
+
+static int debugfs_regs_show(struct seq_file *s, void *v)
+{
+ int i;
+ u8 value[ZX234290_MAX_REGISTER];
+ int ret=0;
+ u8 reg_rtc_ctrl2 = 0;
+
+ printk(KERN_INFO "%s\n", __func__);
+ memset(value, 0, sizeof(value));
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++){
+ ret = zx234290_i2c_read_simple(i, &(value[i]));
+ if(ret){
+ printk(KERN_INFO "%s err=%d, break\n", __func__, ret);
+ seq_printf(s, "%s err=%d, break", __func__, ret);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++) {
+ if((i+1)%9 == 0)
+ seq_printf(s, "\n");
+
+ seq_printf(s, "[0x%x]%02x ", i, value[i]);
+ }
+
+ reg_rtc_ctrl2 = value[ZX234290_REG_ADDR_RTC_CTRL2];
+ seq_printf(s, "\nAF=%d,TF=%d,Alarm %s,Timer %s\n",(reg_rtc_ctrl2&0x8),(reg_rtc_ctrl2&0x4),
+ (reg_rtc_ctrl2&0x2)? "enable":"disable",(reg_rtc_ctrl2&0x1)? "enable":"disable");
+ if(value[ZX234290_REG_ADDR_BUCK_FAULT_STATUS]||value[ZX234290_REG_ADDR_LDO_FAULT_STATUS])
+ seq_printf(s, "ldo or bulk fault!!!!!\n ");
+ else
+ seq_printf(s, "no ldo or bulk fault\n ");
+ if(value[ZX234290_REG_ADDR_TIMER_CTRL]&0x80)
+ seq_printf(s, "timer enable\n ");
+ else
+ seq_printf(s, "timer disable\n ");
+
+
+ return ret;
+}
+
+#define DEBUGFS_FILE_ENTRY(name) \
+static int debugfs_##name##_open(struct inode *inode, struct file *file) \
+{\
+return single_open(file, debugfs_##name##_show, inode->i_private); \
+}\
+\
+static const struct file_operations debugfs_##name##_fops = { \
+.owner= THIS_MODULE, \
+.open= debugfs_##name##_open, \
+.write=debugfs_##name##_write, \
+.read= seq_read, \
+.llseek= seq_lseek, \
+.release= single_release, \
+}
+
+DEBUGFS_FILE_ENTRY(regs);
+
+int zx234290_rtc_settimer(int sec);
+
+static int debugfs_adc_get(void *data, u64 *val)
+{
+ switch ((int)data) {
+ case 0:
+ *val = get_battery_voltage();
+ //zx234290_rtc_settimer(10);
+ break;
+ case 1:
+ *val = get_adc1_voltage();
+ break;
+ case 2:
+ *val = get_adc2_voltage();
+ break;
+ default:
+ *val = -1;
+ break;
+ }
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fops_adc_ro, debugfs_adc_get, NULL, "%llumV\n");
+
+static struct dentry *g_pmu_root;
+
+extern u32 int_irq_times;
+extern u32 int_thread_times;
+
+static void debugfs_pmu_init(struct zx234290 *zx234290)
+{
+ struct dentry *root;
+ struct dentry *node;
+ int i;
+
+ if(!zx234290)
+ return;
+ //create root
+ root = debugfs_create_dir("pmu_zx29", NULL);
+ if (!root){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(root));
+ goto err;
+ }
+ //print regs;
+ node = debugfs_create_file("regs", S_IRUGO | S_IWUGO, root, zx234290, &debugfs_regs_fops);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc0;
+ node = debugfs_create_file("adc0", S_IRUGO, root, 0, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc1;
+ node = debugfs_create_file("adc1", S_IRUGO, root, 1, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc2;
+ node = debugfs_create_file("adc2", S_IRUGO, root, 2, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print u32
+ debugfs_create_u32("irq_cnt", S_IRUGO, root, &int_irq_times);
+
+ //print u32
+ debugfs_create_u32("thread_cnt", S_IRUGO, root, &int_thread_times);
+
+ g_pmu_root = (void *)root;
+ return;
+err:
+ dev_err(zx234290->dev, "debugfs_pmu_init err\n");
+}
+
+#endif
+
+
+int zx234290_device_init(struct zx234290 *zx234290)
+{
+ //struct zx234290_board *pmic_plat_data = zx234290->dev->platform_data;
+ enum of_gpio_flags flags;
+ //struct zx234290_platform_data *init_data;
+ int ret;
+ int irq;
+
+ s_poweron_type_addr = (unsigned long)ioremap(POWERON_TYPE_ADDR,0x800);
+ get_boot_reason();
+ /*
+ init_data = kzalloc(sizeof(struct zx234290_platform_data), GFP_KERNEL);
+ if (init_data == NULL)
+ return -ENOMEM;
+ */
+ mutex_init(&zx234290->io_mutex);
+ dev_set_drvdata(zx234290->dev, zx234290);
+
+ ret = mfd_add_devices(zx234290->dev, -1,
+ zx234290_cell, ARRAY_SIZE(zx234290_cell),
+ NULL,0, 0);
+ if (ret < 0)
+ goto err;
+
+ gpio_num_pshold= of_get_gpio_flags(zx234290->dev->of_node, 0, &flags);
+ if (!gpio_is_valid(gpio_num_pshold)) {
+ pr_info("pmu pshold error\n");
+ }
+ gpio_direction_input(gpio_num_pshold);
+
+ //gpio_num_pshold = pmic_plat_data->pshold_gpio_num;//by yuxiang
+ // gpio_func_pshold= pmic_plat_data->pshold_gpio_func;//by yuxiang
+ if (!pm_power_off)
+ pm_power_off = zx234290_power_off;
+
+#ifdef PSHOLD_PULLUP_IN_POWEROFFCHARGING
+ /* CPE MDL don't control ps_hold pin. */
+ if (boot_reason == POWER_ON_CHARGING) {
+ zx234290_pshold_pull_up();
+ }
+#endif
+/***********PJT added **************/
+ zx234290_get_chip_version();
+ adc_wakelock = wakeup_source_register(NULL, "adc_wake");
+ if (!adc_wakelock)
+ return -ENOMEM;
+
+ //init_data->irq = pmic_plat_data->irq;
+ //init_data->irq_base = pmic_plat_data->irq_base;
+ //irq = gpio_to_irq(pmic_plat_data->irq_gpio_num);
+ ret = zx234290_irq_init(zx234290);
+ if (ret < 0)
+ goto err;
+
+ register_reboot_notifier(&pmu_reboot_notifier);
+
+#if defined(CONFIG_DEBUG_FS)
+ debugfs_pmu_init(zx234290);
+#endif
+ //kfree(init_data);
+ return ret;
+
+err:
+ //kfree(init_data);
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+ return ret;
+}
+
+void zx234290_device_exit(struct zx234290 *zx234290)
+{
+#if defined(CONFIG_DEBUG_FS)
+ if(g_pmu_root){
+ printk(KERN_INFO "zx234290_device_exit:debugfs_remove_recursive \n");
+ debugfs_remove_recursive(g_pmu_root);
+ }
+#endif
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+}
+
+
+MODULE_AUTHOR("yuxiang");
+MODULE_DESCRIPTION("ZX234290 chip family multi-function driver");
+MODULE_LICENSE("GPL");
diff --git a/upstream/linux-5.10/drivers/mtd/mtdcore.c b/upstream/linux-5.10/drivers/mtd/mtdcore.c
new file mode 100755
index 0000000..a52a2c8
--- /dev/null
+++ b/upstream/linux-5.10/drivers/mtd/mtdcore.c
@@ -0,0 +1,2257 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Core registration and callback routines for MTD
+ * drivers and users.
+ *
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
+ * Copyright © 2006 Red Hat UK Limited
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/ioctl.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/proc_fs.h>
+#include <linux/idr.h>
+#include <linux/backing-dev.h>
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/reboot.h>
+#include <linux/leds.h>
+#include <linux/debugfs.h>
+#include <linux/nvmem-provider.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include "mtdcore.h"
+
+struct backing_dev_info *mtd_bdi;
+
+#ifdef CONFIG_PM_SLEEP
+
+static int mtd_cls_suspend(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return mtd ? mtd_suspend(mtd) : 0;
+}
+
+static int mtd_cls_resume(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ if (mtd)
+ mtd_resume(mtd);
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mtd_cls_pm_ops, mtd_cls_suspend, mtd_cls_resume);
+#define MTD_CLS_PM_OPS (&mtd_cls_pm_ops)
+#else
+#define MTD_CLS_PM_OPS NULL
+#endif
+
+static struct class mtd_class = {
+ .name = "mtd",
+ .owner = THIS_MODULE,
+ .pm = MTD_CLS_PM_OPS,
+};
+
+static DEFINE_IDR(mtd_idr);
+
+/* These are exported solely for the purpose of mtd_blkdevs.c. You
+ should not use them for _anything_ else */
+DEFINE_MUTEX(mtd_table_mutex);
+EXPORT_SYMBOL_GPL(mtd_table_mutex);
+
+struct mtd_info *__mtd_next_device(int i)
+{
+ return idr_get_next(&mtd_idr, &i);
+}
+EXPORT_SYMBOL_GPL(__mtd_next_device);
+
+static LIST_HEAD(mtd_notifiers);
+
+
+#define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2)
+
+/* REVISIT once MTD uses the driver model better, whoever allocates
+ * the mtd_info will probably want to use the release() hook...
+ */
+static void mtd_release(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ dev_t index = MTD_DEVT(mtd->index);
+
+ /* remove /dev/mtdXro node */
+ device_destroy(&mtd_class, index + 1);
+}
+
+static ssize_t mtd_type_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ char *type;
+
+ switch (mtd->type) {
+ case MTD_ABSENT:
+ type = "absent";
+ break;
+ case MTD_RAM:
+ type = "ram";
+ break;
+ case MTD_ROM:
+ type = "rom";
+ break;
+ case MTD_NORFLASH:
+ type = "nor";
+ break;
+ case MTD_NANDFLASH:
+ type = "nand";
+ break;
+ case MTD_DATAFLASH:
+ type = "dataflash";
+ break;
+ case MTD_UBIVOLUME:
+ type = "ubi";
+ break;
+ case MTD_MLCNANDFLASH:
+ type = "mlc-nand";
+ break;
+ default:
+ type = "unknown";
+ }
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", type);
+}
+static DEVICE_ATTR(type, S_IRUGO, mtd_type_show, NULL);
+
+static ssize_t mtd_flags_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)mtd->flags);
+}
+static DEVICE_ATTR(flags, S_IRUGO, mtd_flags_show, NULL);
+
+static ssize_t mtd_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%llu\n",
+ (unsigned long long)mtd->size);
+}
+static DEVICE_ATTR(size, S_IRUGO, mtd_size_show, NULL);
+
+static ssize_t mtd_erasesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize);
+}
+static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL);
+
+static ssize_t mtd_writesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->writesize);
+}
+static DEVICE_ATTR(writesize, S_IRUGO, mtd_writesize_show, NULL);
+
+static ssize_t mtd_subpagesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int subpagesize = mtd->writesize >> mtd->subpage_sft;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", subpagesize);
+}
+static DEVICE_ATTR(subpagesize, S_IRUGO, mtd_subpagesize_show, NULL);
+
+static ssize_t mtd_oobsize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->oobsize);
+}
+static DEVICE_ATTR(oobsize, S_IRUGO, mtd_oobsize_show, NULL);
+
+static ssize_t mtd_oobavail_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->oobavail);
+}
+static DEVICE_ATTR(oobavail, S_IRUGO, mtd_oobavail_show, NULL);
+
+static ssize_t mtd_numeraseregions_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->numeraseregions);
+}
+static DEVICE_ATTR(numeraseregions, S_IRUGO, mtd_numeraseregions_show,
+ NULL);
+
+static ssize_t mtd_name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", mtd->name);
+}
+static DEVICE_ATTR(name, S_IRUGO, mtd_name_show, NULL);
+
+static ssize_t mtd_ecc_strength_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_strength);
+}
+static DEVICE_ATTR(ecc_strength, S_IRUGO, mtd_ecc_strength_show, NULL);
+
+static ssize_t mtd_bitflip_threshold_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->bitflip_threshold);
+}
+
+static ssize_t mtd_bitflip_threshold_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int bitflip_threshold;
+ int retval;
+
+ retval = kstrtouint(buf, 0, &bitflip_threshold);
+ if (retval)
+ return retval;
+
+ mtd->bitflip_threshold = bitflip_threshold;
+ return count;
+}
+static DEVICE_ATTR(bitflip_threshold, S_IRUGO | S_IWUSR,
+ mtd_bitflip_threshold_show,
+ mtd_bitflip_threshold_store);
+
+static ssize_t mtd_ecc_step_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_step_size);
+
+}
+static DEVICE_ATTR(ecc_step_size, S_IRUGO, mtd_ecc_step_size_show, NULL);
+
+static ssize_t mtd_ecc_stats_corrected_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->corrected);
+}
+static DEVICE_ATTR(corrected_bits, S_IRUGO,
+ mtd_ecc_stats_corrected_show, NULL);
+
+static ssize_t mtd_ecc_stats_errors_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->failed);
+}
+static DEVICE_ATTR(ecc_failures, S_IRUGO, mtd_ecc_stats_errors_show, NULL);
+
+static ssize_t mtd_badblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->badblocks);
+}
+static DEVICE_ATTR(bad_blocks, S_IRUGO, mtd_badblocks_show, NULL);
+
+static ssize_t mtd_bbtblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->bbtblocks);
+}
+static DEVICE_ATTR(bbt_blocks, S_IRUGO, mtd_bbtblocks_show, NULL);
+
+static struct attribute *mtd_attrs[] = {
+ &dev_attr_type.attr,
+ &dev_attr_flags.attr,
+ &dev_attr_size.attr,
+ &dev_attr_erasesize.attr,
+ &dev_attr_writesize.attr,
+ &dev_attr_subpagesize.attr,
+ &dev_attr_oobsize.attr,
+ &dev_attr_oobavail.attr,
+ &dev_attr_numeraseregions.attr,
+ &dev_attr_name.attr,
+ &dev_attr_ecc_strength.attr,
+ &dev_attr_ecc_step_size.attr,
+ &dev_attr_corrected_bits.attr,
+ &dev_attr_ecc_failures.attr,
+ &dev_attr_bad_blocks.attr,
+ &dev_attr_bbt_blocks.attr,
+ &dev_attr_bitflip_threshold.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(mtd);
+
+static const struct device_type mtd_devtype = {
+ .name = "mtd",
+ .groups = mtd_groups,
+ .release = mtd_release,
+};
+
+static int mtd_partid_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partid);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partid_debug);
+
+static int mtd_partname_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partname);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partname_debug);
+
+static struct dentry *dfs_dir_mtd;
+
+static void mtd_debugfs_populate(struct mtd_info *mtd)
+{
+ struct device *dev = &mtd->dev;
+ struct dentry *root;
+
+ if (IS_ERR_OR_NULL(dfs_dir_mtd))
+ return;
+
+ root = debugfs_create_dir(dev_name(dev), dfs_dir_mtd);
+ mtd->dbg.dfs_dir = root;
+
+ if (mtd->dbg.partid)
+ debugfs_create_file("partid", 0400, root, mtd,
+ &mtd_partid_debug_fops);
+
+ if (mtd->dbg.partname)
+ debugfs_create_file("partname", 0400, root, mtd,
+ &mtd_partname_debug_fops);
+}
+
+#ifndef CONFIG_MMU
+unsigned mtd_mmap_capabilities(struct mtd_info *mtd)
+{
+ switch (mtd->type) {
+ case MTD_RAM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ | NOMMU_MAP_WRITE;
+ case MTD_ROM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ;
+ default:
+ return NOMMU_MAP_COPY;
+ }
+}
+EXPORT_SYMBOL_GPL(mtd_mmap_capabilities);
+#endif
+
+static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
+ void *cmd)
+{
+ struct mtd_info *mtd;
+
+ mtd = container_of(n, struct mtd_info, reboot_notifier);
+ mtd->_reboot(mtd);
+
+ return NOTIFY_DONE;
+}
+
+/**
+ * mtd_wunit_to_pairing_info - get pairing information of a wunit
+ * @mtd: pointer to new MTD device info structure
+ * @wunit: write unit we are interested in
+ * @info: returned pairing information
+ *
+ * Retrieve pairing information associated to the wunit.
+ * This is mainly useful when dealing with MLC/TLC NANDs where pages can be
+ * paired together, and where programming a page may influence the page it is
+ * paired with.
+ * The notion of page is replaced by the term wunit (write-unit) to stay
+ * consistent with the ->writesize field.
+ *
+ * The @wunit argument can be extracted from an absolute offset using
+ * mtd_offset_to_wunit(). @info is filled with the pairing information attached
+ * to @wunit.
+ *
+ * From the pairing info the MTD user can find all the wunits paired with
+ * @wunit using the following loop:
+ *
+ * for (i = 0; i < mtd_pairing_groups(mtd); i++) {
+ * info.pair = i;
+ * mtd_pairing_info_to_wunit(mtd, &info);
+ * ...
+ * }
+ */
+int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
+ struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master);
+
+ if (wunit < 0 || wunit >= npairs)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_info)
+ return master->pairing->get_info(master, wunit, info);
+
+ info->group = 0;
+ info->pair = wunit;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info);
+
+/**
+ * mtd_pairing_info_to_wunit - get wunit from pairing information
+ * @mtd: pointer to new MTD device info structure
+ * @info: pairing information struct
+ *
+ * Returns a positive number representing the wunit associated to the info
+ * struct, or a negative error code.
+ *
+ * This is the reverse of mtd_wunit_to_pairing_info(), and can help one to
+ * iterate over all wunits of a given pair (see mtd_wunit_to_pairing_info()
+ * doc).
+ *
+ * It can also be used to only program the first page of each pair (i.e.
+ * page attached to group 0), which allows one to use an MLC NAND in
+ * software-emulated SLC mode:
+ *
+ * info.group = 0;
+ * npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
+ * for (info.pair = 0; info.pair < npairs; info.pair++) {
+ * wunit = mtd_pairing_info_to_wunit(mtd, &info);
+ * mtd_write(mtd, mtd_wunit_to_offset(mtd, blkoffs, wunit),
+ * mtd->writesize, &retlen, buf + (i * mtd->writesize));
+ * }
+ */
+int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
+ const struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+
+ if (!info || info->pair < 0 || info->pair >= npairs ||
+ info->group < 0 || info->group >= ngroups)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_wunit)
+ return mtd->pairing->get_wunit(master, info);
+
+ return info->pair;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit);
+
+/**
+ * mtd_pairing_groups - get the number of pairing groups
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Returns the number of pairing groups.
+ *
+ * This number is usually equal to the number of bits exposed by a single
+ * cell, and can be used in conjunction with mtd_pairing_info_to_wunit()
+ * to iterate over all pages of a given pair.
+ */
+int mtd_pairing_groups(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->pairing || !master->pairing->ngroups)
+ return 1;
+
+ return master->pairing->ngroups;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_groups);
+
+static int mtd_nvmem_reg_read(void *priv, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct mtd_info *mtd = priv;
+ size_t retlen;
+ int err;
+
+ err = mtd_read(mtd, offset, bytes, &retlen, val);
+ if (err && err != -EUCLEAN)
+ return err;
+
+ return retlen == bytes ? 0 : -EIO;
+}
+
+static int mtd_nvmem_add(struct mtd_info *mtd)
+{
+ struct nvmem_config config = {};
+
+ config.id = -1;
+ config.dev = &mtd->dev;
+ config.name = dev_name(&mtd->dev);
+ config.owner = THIS_MODULE;
+ config.reg_read = mtd_nvmem_reg_read;
+ config.size = mtd->size;
+ config.word_size = 1;
+ config.stride = 1;
+ config.read_only = true;
+ config.root_only = true;
+ config.no_of_node = true;
+ config.priv = mtd;
+
+ mtd->nvmem = nvmem_register(&config);
+ if (IS_ERR(mtd->nvmem)) {
+ /* Just ignore if there is no NVMEM support in the kernel */
+ if (PTR_ERR(mtd->nvmem) == -EOPNOTSUPP) {
+ mtd->nvmem = NULL;
+ } else {
+ dev_err(&mtd->dev, "Failed to register NVMEM device\n");
+ return PTR_ERR(mtd->nvmem);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * add_mtd_device - register an MTD device
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Add a device to the list of MTD devices present in the system, and
+ * notify each currently active MTD 'user' of its arrival. Returns
+ * zero on success or non-zero on failure.
+ */
+
+int add_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_notifier *not;
+ int i, error;
+
+ /*
+ * May occur, for instance, on buggy drivers which call
+ * mtd_device_parse_register() multiple times on the same master MTD,
+ * especially with CONFIG_MTD_PARTITIONED_MASTER=y.
+ */
+ if (WARN_ONCE(mtd->dev.type, "MTD already registered\n"))
+ return -EEXIST;
+
+ BUG_ON(mtd->writesize == 0);
+
+ /*
+ * MTD drivers should implement ->_{write,read}() or
+ * ->_{write,read}_oob(), but not both.
+ */
+ if (WARN_ON((mtd->_write && mtd->_write_oob) ||
+ (mtd->_read && mtd->_read_oob)))
+ return -EINVAL;
+
+ if (WARN_ON((!mtd->erasesize || !master->_erase) &&
+ !(mtd->flags & MTD_NO_ERASE)))
+ return -EINVAL;
+
+ /*
+ * MTD_SLC_ON_MLC_EMULATION can only be set on partitions, when the
+ * master is an MLC NAND and has a proper pairing scheme defined.
+ * We also reject masters that implement ->_writev() for now, because
+ * NAND controller drivers don't implement this hook, and adding the
+ * SLC -> MLC address/length conversion to this path is useless if we
+ * don't have a user.
+ */
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION &&
+ (!mtd_is_partition(mtd) || master->type != MTD_MLCNANDFLASH ||
+ !master->pairing || master->_writev))
+ return -EINVAL;
+
+ mutex_lock(&mtd_table_mutex);
+
+ i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL);
+ if (i < 0) {
+ error = i;
+ goto fail_locked;
+ }
+
+ mtd->index = i;
+ mtd->usecount = 0;
+
+ /* default value if not set by driver */
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ int ngroups = mtd_pairing_groups(master);
+
+ mtd->erasesize /= ngroups;
+ mtd->size = (u64)mtd_div_by_eb(mtd->size, master) *
+ mtd->erasesize;
+ }
+
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+
+ mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+ mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+
+ /* Some chips always power up locked. Unlock them now */
+ if ((mtd->flags & MTD_WRITEABLE) && (mtd->flags & MTD_POWERUP_LOCK)) {
+ error = mtd_unlock(mtd, 0, mtd->size);
+ if (error && error != -EOPNOTSUPP)
+ printk(KERN_WARNING
+ "%s: unlock failed, writes may not work\n",
+ mtd->name);
+ /* Ignore unlock failures? */
+ error = 0;
+ }
+
+ /* Caller should have set dev.parent to match the
+ * physical device, if appropriate.
+ */
+ mtd->dev.type = &mtd_devtype;
+ mtd->dev.class = &mtd_class;
+ mtd->dev.devt = MTD_DEVT(i);
+ dev_set_name(&mtd->dev, "mtd%d", i);
+ dev_set_drvdata(&mtd->dev, mtd);
+ of_node_get(mtd_get_of_node(mtd));
+ error = device_register(&mtd->dev);
+ if (error)
+ goto fail_added;
+
+ /* Add the nvmem provider */
+ error = mtd_nvmem_add(mtd);
+ if (error)
+ goto fail_nvmem_add;
+
+ mtd_debugfs_populate(mtd);
+
+ device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
+ "mtd%dro", i);
+
+ pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name);
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+ /* We _know_ we aren't being removed, because
+ our caller is still holding us here. So none
+ of this try_ nonsense, and no bitching about it
+ either. :) */
+ __module_get(THIS_MODULE);
+ return 0;
+
+fail_nvmem_add:
+ device_unregister(&mtd->dev);
+fail_added:
+ of_node_put(mtd_get_of_node(mtd));
+ idr_remove(&mtd_idr, i);
+fail_locked:
+ mutex_unlock(&mtd_table_mutex);
+ return error;
+}
+
+/**
+ * del_mtd_device - unregister an MTD device
+ * @mtd: pointer to MTD device info structure
+ *
+ * Remove a device from the list of MTD devices present in the system,
+ * and notify each currently active MTD 'user' of its departure.
+ * Returns zero on success or 1 on failure, which currently will happen
+ * if the requested device does not appear to be present in the list.
+ */
+
+int del_mtd_device(struct mtd_info *mtd)
+{
+ int ret;
+ struct mtd_notifier *not;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (idr_find(&mtd_idr, mtd->index) != mtd) {
+ ret = -ENODEV;
+ goto out_error;
+ }
+
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->remove(mtd);
+
+ if (mtd->usecount) {
+ printk(KERN_NOTICE "Removing MTD device #%d (%s) with use count %d\n",
+ mtd->index, mtd->name, mtd->usecount);
+ ret = -EBUSY;
+ } else {
+ debugfs_remove_recursive(mtd->dbg.dfs_dir);
+
+ /* Try to remove the NVMEM provider */
+ if (mtd->nvmem)
+ nvmem_unregister(mtd->nvmem);
+
+ device_unregister(&mtd->dev);
+
+ idr_remove(&mtd_idr, mtd->index);
+ of_node_put(mtd_get_of_node(mtd));
+
+ module_put(THIS_MODULE);
+ ret = 0;
+ }
+
+out_error:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+
+/*
+ * Set a few defaults based on the parent devices, if not provided by the
+ * driver
+ */
+static void mtd_set_dev_defaults(struct mtd_info *mtd)
+{
+ if (mtd->dev.parent) {
+ if (!mtd->owner && mtd->dev.parent->driver)
+ mtd->owner = mtd->dev.parent->driver->owner;
+ if (!mtd->name)
+ mtd->name = dev_name(mtd->dev.parent);
+ } else {
+ pr_debug("mtd device won't show a device symlink in sysfs\n");
+ }
+
+ INIT_LIST_HEAD(&mtd->partitions);
+ mutex_init(&mtd->master.partitions_lock);
+}
+
+/**
+ * mtd_device_parse_register - parse partitions and register an MTD device.
+ *
+ * @mtd: the MTD device to register
+ * @types: the list of MTD partition probes to try, see
+ * 'parse_mtd_partitions()' for more information
+ * @parser_data: MTD partition parser-specific data
+ * @parts: fallback partition information to register, if parsing fails;
+ * only valid if %nr_parts > %0
+ * @nr_parts: the number of partitions in parts, if zero then the full
+ * MTD device is registered if no partition info is found
+ *
+ * This function aggregates MTD partitions parsing (done by
+ * 'parse_mtd_partitions()') and MTD device and partitions registering. It
+ * basically follows the most common pattern found in many MTD drivers:
+ *
+ * * If the MTD_PARTITIONED_MASTER option is set, then the device as a whole is
+ * registered first.
+ * * Then It tries to probe partitions on MTD device @mtd using parsers
+ * specified in @types (if @types is %NULL, then the default list of parsers
+ * is used, see 'parse_mtd_partitions()' for more information). If none are
+ * found this functions tries to fallback to information specified in
+ * @parts/@nr_parts.
+ * * If no partitions were found this function just registers the MTD device
+ * @mtd and exits.
+ *
+ * Returns zero in case of success and a negative error code in case of failure.
+ */
+int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
+ struct mtd_part_parser_data *parser_data,
+ const struct mtd_partition *parts,
+ int nr_parts)
+{
+ int ret;
+
+ mtd_set_dev_defaults(mtd);
+
+ if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) {
+ ret = add_mtd_device(mtd);
+ if (ret)
+ return ret;
+ }
+
+ /* Prefer parsed partitions over driver-provided fallback */
+ ret = parse_mtd_partitions(mtd, types, parser_data);
+ if (ret == -EPROBE_DEFER)
+ goto out;
+
+ if (ret > 0)
+ ret = 0;
+ else if (nr_parts)
+ ret = add_mtd_partitions(mtd, parts, nr_parts);
+ else if (!device_is_registered(&mtd->dev))
+ ret = add_mtd_device(mtd);
+ else
+ ret = 0;
+
+ if (ret)
+ goto out;
+
+ /*
+ * FIXME: some drivers unfortunately call this function more than once.
+ * So we have to check if we've already assigned the reboot notifier.
+ *
+ * Generally, we can make multiple calls work for most cases, but it
+ * does cause problems with parse_mtd_partitions() above (e.g.,
+ * cmdlineparts will register partitions more than once).
+ */
+ WARN_ONCE(mtd->_reboot && mtd->reboot_notifier.notifier_call,
+ "MTD already registered\n");
+ if (mtd->_reboot && !mtd->reboot_notifier.notifier_call) {
+ mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
+ register_reboot_notifier(&mtd->reboot_notifier);
+ }
+
+out:
+ if (ret && device_is_registered(&mtd->dev))
+ del_mtd_device(mtd);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_device_parse_register);
+
+/**
+ * mtd_device_unregister - unregister an existing MTD device.
+ *
+ * @master: the MTD device to unregister. This will unregister both the master
+ * and any partitions if registered.
+ */
+int mtd_device_unregister(struct mtd_info *master)
+{
+ int err;
+
+ if (master->_reboot)
+ unregister_reboot_notifier(&master->reboot_notifier);
+
+ err = del_mtd_partitions(master);
+ if (err)
+ return err;
+
+ if (!device_is_registered(&master->dev))
+ return 0;
+
+ return del_mtd_device(master);
+}
+EXPORT_SYMBOL_GPL(mtd_device_unregister);
+
+/**
+ * register_mtd_user - register a 'user' of MTD devices.
+ * @new: pointer to notifier info structure
+ *
+ * Registers a pair of callbacks function to be called upon addition
+ * or removal of MTD devices. Causes the 'add' callback to be immediately
+ * invoked for each MTD device currently present in the system.
+ */
+void register_mtd_user (struct mtd_notifier *new)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ list_add(&new->list, &mtd_notifiers);
+
+ __module_get(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ new->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+}
+EXPORT_SYMBOL_GPL(register_mtd_user);
+
+/**
+ * unregister_mtd_user - unregister a 'user' of MTD devices.
+ * @old: pointer to notifier info structure
+ *
+ * Removes a callback function pair from the list of 'users' to be
+ * notified upon addition or removal of MTD devices. Causes the
+ * 'remove' callback to be immediately invoked for each MTD device
+ * currently present in the system.
+ */
+int unregister_mtd_user (struct mtd_notifier *old)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ module_put(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ old->remove(mtd);
+
+ list_del(&old->list);
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(unregister_mtd_user);
+
+/**
+ * get_mtd_device - obtain a validated handle for an MTD device
+ * @mtd: last known address of the required MTD device
+ * @num: internal device number of the required MTD device
+ *
+ * Given a number and NULL address, return the num'th entry in the device
+ * table, if any. Given an address and num == -1, search the device table
+ * for a device with that address and return if it's still present. Given
+ * both, return the num'th driver only if its address matches. Return
+ * error code if not.
+ */
+struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num)
+{
+ struct mtd_info *ret = NULL, *other;
+ int err = -ENODEV;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (num == -1) {
+ mtd_for_each_device(other) {
+ if (other == mtd) {
+ ret = mtd;
+ break;
+ }
+ }
+ } else if (num >= 0) {
+ ret = idr_find(&mtd_idr, num);
+ if (mtd && mtd != ret)
+ ret = NULL;
+ }
+
+ if (!ret) {
+ ret = ERR_PTR(err);
+ goto out;
+ }
+
+ err = __get_mtd_device(ret);
+ if (err)
+ ret = ERR_PTR(err);
+out:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(get_mtd_device);
+
+
+int __get_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int err;
+
+ if (!try_module_get(master->owner))
+ return -ENODEV;
+
+ if (master->_get_device) {
+ err = master->_get_device(mtd);
+
+ if (err) {
+ module_put(master->owner);
+ return err;
+ }
+ }
+
+ master->usecount++;
+
+ while (mtd->parent) {
+ mtd->usecount++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__get_mtd_device);
+
+/**
+ * get_mtd_device_nm - obtain a validated handle for an MTD device by
+ * device name
+ * @name: MTD device name to open
+ *
+ * This function returns MTD device description structure in case of
+ * success and an error code in case of failure.
+ */
+struct mtd_info *get_mtd_device_nm(const char *name)
+{
+ int err = -ENODEV;
+ struct mtd_info *mtd = NULL, *other;
+
+ mutex_lock(&mtd_table_mutex);
+
+ mtd_for_each_device(other) {
+ if (!strcmp(name, other->name)) {
+ mtd = other;
+ break;
+ }
+ }
+
+ if (!mtd)
+ goto out_unlock;
+
+ err = __get_mtd_device(mtd);
+ if (err)
+ goto out_unlock;
+
+ mutex_unlock(&mtd_table_mutex);
+ return mtd;
+
+out_unlock:
+ mutex_unlock(&mtd_table_mutex);
+ return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(get_mtd_device_nm);
+
+void put_mtd_device(struct mtd_info *mtd)
+{
+ mutex_lock(&mtd_table_mutex);
+ __put_mtd_device(mtd);
+ mutex_unlock(&mtd_table_mutex);
+
+}
+EXPORT_SYMBOL_GPL(put_mtd_device);
+
+void __put_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ while (mtd->parent) {
+ --mtd->usecount;
+ BUG_ON(mtd->usecount < 0);
+ mtd = mtd->parent;
+ }
+
+ master->usecount--;
+
+ if (master->_put_device)
+ master->_put_device(master);
+
+ module_put(master->owner);
+}
+EXPORT_SYMBOL_GPL(__put_mtd_device);
+
+/*
+ * Erase is an synchronous operation. Device drivers are epected to return a
+ * negative error code if the operation failed and update instr->fail_addr
+ * to point the portion that was not properly erased.
+ */
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ u64 mst_ofs = mtd_get_master_ofs(mtd, 0);
+ struct erase_info adjinstr;
+ int ret;
+
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ adjinstr = *instr;
+
+ if (!mtd->erasesize || !master->_erase)
+ return -ENOTSUPP;
+
+ if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!instr->len)
+ return 0;
+
+ ledtrig_mtd_activity();
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ adjinstr.addr = (loff_t)mtd_div_by_eb(instr->addr, mtd) *
+ master->erasesize;
+ adjinstr.len = ((u64)mtd_div_by_eb(instr->addr + instr->len, mtd) *
+ master->erasesize) -
+ adjinstr.addr;
+ }
+
+ adjinstr.addr += mst_ofs;
+
+ ret = master->_erase(master, &adjinstr);
+
+ if (adjinstr.fail_addr != MTD_FAIL_ADDR_UNKNOWN) {
+ instr->fail_addr = adjinstr.fail_addr - mst_ofs;
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ instr->fail_addr = mtd_div_by_eb(instr->fail_addr,
+ master);
+ instr->fail_addr *= mtd->erasesize;
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_erase);
+
+/*
+ * This stuff for eXecute-In-Place. phys is optional and may be set to NULL.
+ */
+int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ void **virt, resource_size_t *phys)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ *virt = NULL;
+ if (phys)
+ *phys = 0;
+ if (!master->_point)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ from = mtd_get_master_ofs(mtd, from);
+ return master->_point(master, from, len, retlen, virt, phys);
+}
+EXPORT_SYMBOL_GPL(mtd_point);
+
+/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
+int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unpoint)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+ return master->_unpoint(master, mtd_get_master_ofs(mtd, from), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unpoint);
+
+/*
+ * Allow NOMMU mmap() to directly map the device (if not NULL)
+ * - return the address to which the offset maps
+ * - return -ENOSYS to indicate refusal to do the mapping
+ */
+unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len,
+ unsigned long offset, unsigned long flags)
+{
+ size_t retlen;
+ void *virt;
+ int ret;
+
+ ret = mtd_point(mtd, offset, len, &retlen, &virt, NULL);
+ if (ret)
+ return ret;
+ if (retlen != len) {
+ mtd_unpoint(mtd, offset, retlen);
+ return -ENOSYS;
+ }
+ return (unsigned long)virt;
+}
+EXPORT_SYMBOL_GPL(mtd_get_unmapped_area);
+
+static void mtd_update_ecc_stats(struct mtd_info *mtd, struct mtd_info *master,
+ const struct mtd_ecc_stats *old_stats)
+{
+ struct mtd_ecc_stats diff;
+
+ if (master == mtd)
+ return;
+
+ diff = master->ecc_stats;
+ diff.failed -= old_stats->failed;
+ diff.corrected -= old_stats->corrected;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.failed += diff.failed;
+ mtd->ecc_stats.corrected += diff.corrected;
+ mtd = mtd->parent;
+ }
+}
+
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = buf,
+ };
+ int ret;
+
+ ret = mtd_read_oob(mtd, from, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_read);
+
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = (u8 *)buf,
+ };
+ int ret;
+
+ ret = mtd_write_oob(mtd, to, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_write);
+
+/*
+ * In blackbox flight recorder like scenarios we want to make successful writes
+ * in interrupt context. panic_write() is only intended to be called when its
+ * known the kernel is about to panic and we need the write to succeed. Since
+ * the kernel is not going to be running for much longer, this function can
+ * break locks and delay to ensure the write succeeds (but not sleep).
+ */
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_panic_write)
+ return -EOPNOTSUPP;
+ if (to < 0 || to >= mtd->size || len > mtd->size - to)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+ if (!len)
+ return 0;
+ if (!master->oops_panic_write)
+ master->oops_panic_write = true;
+
+ return master->_panic_write(master, mtd_get_master_ofs(mtd, to), len,
+ retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_panic_write);
+
+static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs,
+ struct mtd_oob_ops *ops)
+{
+ /*
+ * Some users are setting ->datbuf or ->oobbuf to NULL, but are leaving
+ * ->len or ->ooblen uninitialized. Force ->len and ->ooblen to 0 in
+ * this case.
+ */
+ if (!ops->datbuf)
+ ops->len = 0;
+
+ if (!ops->oobbuf)
+ ops->ooblen = 0;
+
+ if (offs < 0 || offs + ops->len > mtd->size)
+ return -EINVAL;
+
+ if (ops->ooblen) {
+ size_t maxooblen;
+
+ if (ops->ooboffs >= mtd_oobavail(mtd, ops))
+ return -EINVAL;
+
+ maxooblen = ((size_t)(mtd_div_by_ws(mtd->size, mtd) -
+ mtd_div_by_ws(offs, mtd)) *
+ mtd_oobavail(mtd, ops)) - ops->ooboffs;
+ if (ops->ooblen > maxooblen)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtd_read_oob_std(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ from = mtd_get_master_ofs(mtd, from);
+ if (master->_read_oob)
+ ret = master->_read_oob(master, from, ops);
+ else
+ ret = master->_read(master, from, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_write_oob_std(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ to = mtd_get_master_ofs(mtd, to);
+ if (master->_write_oob)
+ ret = master->_write_oob(master, to, ops);
+ else
+ ret = master->_write(master, to, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_io_emulated_slc(struct mtd_info *mtd, loff_t start, bool read,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+ struct mtd_oob_ops adjops = *ops;
+ unsigned int wunit, oobavail;
+ struct mtd_pairing_info info;
+ int max_bitflips = 0;
+ u32 ebofs, pageofs;
+ loff_t base, pos;
+
+ ebofs = mtd_mod_by_eb(start, mtd);
+ base = (loff_t)mtd_div_by_eb(start, mtd) * master->erasesize;
+ info.group = 0;
+ info.pair = mtd_div_by_ws(ebofs, mtd);
+ pageofs = mtd_mod_by_ws(ebofs, mtd);
+ oobavail = mtd_oobavail(mtd, ops);
+
+ while (ops->retlen < ops->len || ops->oobretlen < ops->ooblen) {
+ int ret;
+
+ if (info.pair >= npairs) {
+ info.pair = 0;
+ base += master->erasesize;
+ }
+
+ wunit = mtd_pairing_info_to_wunit(master, &info);
+ pos = mtd_wunit_to_offset(mtd, base, wunit);
+
+ adjops.len = ops->len - ops->retlen;
+ if (adjops.len > mtd->writesize - pageofs)
+ adjops.len = mtd->writesize - pageofs;
+
+ adjops.ooblen = ops->ooblen - ops->oobretlen;
+ if (adjops.ooblen > oobavail - adjops.ooboffs)
+ adjops.ooblen = oobavail - adjops.ooboffs;
+
+ if (read) {
+ ret = mtd_read_oob_std(mtd, pos + pageofs, &adjops);
+ if (ret > 0)
+ max_bitflips = max(max_bitflips, ret);
+ } else {
+ ret = mtd_write_oob_std(mtd, pos + pageofs, &adjops);
+ }
+
+ if (ret < 0)
+ return ret;
+
+ max_bitflips = max(max_bitflips, ret);
+ ops->retlen += adjops.retlen;
+ ops->oobretlen += adjops.oobretlen;
+ adjops.datbuf += adjops.retlen;
+ adjops.oobbuf += adjops.oobretlen;
+ adjops.ooboffs = 0;
+ pageofs = 0;
+ info.pair++;
+ }
+
+ return max_bitflips;
+}
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_ecc_stats old_stats = master->ecc_stats;
+ int ret_code;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ ret_code = mtd_check_oob_ops(mtd, from, ops);
+ if (ret_code)
+ return ret_code;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_read */
+ if (!master->_read_oob && (!master->_read || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ret_code = mtd_io_emulated_slc(mtd, from, true, ops);
+ else
+ ret_code = mtd_read_oob_std(mtd, from, ops);
+
+ mtd_update_ecc_stats(mtd, master, &old_stats);
+
+ /*
+ * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics
+ * similar to mtd->_read(), returning a non-negative integer
+ * representing max bitflips. In other cases, mtd->_read_oob() may
+ * return -EUCLEAN. In all cases, perform similar logic to mtd_read().
+ */
+ if (unlikely(ret_code < 0))
+ return ret_code;
+ if (mtd->ecc_strength == 0)
+ return 0; /* device lacks ecc */
+ //printk("ecc strength = %d.\n",mtd->ecc_strength);
+ //printk("bitflip_threshold = %d.\n",mtd->bitflip_threshold);
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+ return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0;
+}
+EXPORT_SYMBOL_GPL(mtd_read_oob);
+
+int mtd_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ ret = mtd_check_oob_ops(mtd, to, ops);
+ if (ret)
+ return ret;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_write */
+ if (!master->_write_oob && (!master->_write || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ return mtd_io_emulated_slc(mtd, to, false, ops);
+
+ return mtd_write_oob_std(mtd, to, ops);
+}
+EXPORT_SYMBOL_GPL(mtd_write_oob);
+
+/**
+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section
+ * @mtd: MTD device structure
+ * @section: ECC section. Depending on the layout you may have all the ECC
+ * bytes stored in a single contiguous section, or one section
+ * per ECC chunk (and sometime several sections for a single ECC
+ * ECC chunk)
+ * @oobecc: OOB region struct filled with the appropriate ECC position
+ * information
+ *
+ * This function returns ECC section information in the OOB area. If you want
+ * to get all the ECC bytes information, then you should call
+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobecc, 0, sizeof(*oobecc));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->ecc)
+ return -ENOTSUPP;
+
+ return master->ooblayout->ecc(master, section, oobecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
+
+/**
+ * mtd_ooblayout_free - Get the OOB region definition of a specific free
+ * section
+ * @mtd: MTD device structure
+ * @section: Free section you are interested in. Depending on the layout
+ * you may have all the free bytes stored in a single contiguous
+ * section, or one section per ECC chunk plus an extra section
+ * for the remaining bytes (or other funky layout).
+ * @oobfree: OOB region struct filled with the appropriate free position
+ * information
+ *
+ * This function returns free bytes position in the OOB area. If you want
+ * to get all the free bytes information, then you should call
+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobfree, 0, sizeof(*oobfree));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->free)
+ return -ENOTSUPP;
+
+ return master->ooblayout->free(master, section, oobfree);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
+
+/**
+ * mtd_ooblayout_find_region - Find the region attached to a specific byte
+ * @mtd: mtd info structure
+ * @byte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: used to retrieve the ECC position
+ * @iter: iterator function. Should be either mtd_ooblayout_free or
+ * mtd_ooblayout_ecc depending on the region type you're searching for
+ *
+ * This function returns the section id and oobregion information of a
+ * specific byte. For example, say you want to know where the 4th ECC byte is
+ * stored, you'll use:
+ *
+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc);
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte,
+ int *sectionp, struct mtd_oob_region *oobregion,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ int pos = 0, ret, section = 0;
+
+ memset(oobregion, 0, sizeof(*oobregion));
+
+ while (1) {
+ ret = iter(mtd, section, oobregion);
+ if (ret)
+ return ret;
+
+ if (pos + oobregion->length > byte)
+ break;
+
+ pos += oobregion->length;
+ section++;
+ }
+
+ /*
+ * Adjust region info to make it start at the beginning at the
+ * 'start' ECC byte.
+ */
+ oobregion->offset += byte - pos;
+ oobregion->length -= byte - pos;
+ *sectionp = section;
+
+ return 0;
+}
+
+/**
+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific
+ * ECC byte
+ * @mtd: mtd info structure
+ * @eccbyte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: OOB region information
+ *
+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC
+ * byte.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion)
+{
+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion);
+
+/**
+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @buf: destination buffer to store OOB bytes
+ * @oobbuf: OOB buffer
+ * @start: first byte to retrieve
+ * @nbytes: number of bytes to retrieve
+ * @iter: section iterator
+ *
+ * Extract bytes attached to a specific category (ECC or free)
+ * from the OOB buffer and copy them into buf.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf,
+ const u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(buf, oobbuf + oobregion.offset, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @buf: source buffer to get OOB bytes from
+ * @oobbuf: OOB buffer
+ * @start: first OOB byte to set
+ * @nbytes: number of OOB bytes to set
+ * @iter: section iterator
+ *
+ * Fill the OOB buffer with data provided in buf. The category (ECC or free)
+ * is selected by passing the appropriate iterator.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf,
+ u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(oobbuf + oobregion.offset, buf, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category
+ * @mtd: mtd info structure
+ * @iter: category iterator
+ *
+ * Count the number of bytes in a given category.
+ *
+ * Returns a positive value on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section = 0, ret, nbytes = 0;
+
+ while (1) {
+ ret = iter(mtd, section++, &oobregion);
+ if (ret) {
+ if (ret == -ERANGE)
+ ret = nbytes;
+ break;
+ }
+
+ nbytes += oobregion.length;
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes);
+
+/**
+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get ECC bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes);
+
+/**
+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes);
+
+/**
+ * mtd_ooblayout_set_databytes - set data bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: source buffer to get data bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes);
+
+/**
+ * mtd_ooblayout_count_eccbytes - count the number of ECC bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes);
+
+/*
+ * Method to access the protection register area, present in some flash
+ * devices. The user data is one time programmable but the factory data is read
+ * only.
+ */
+int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_fact_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_fact_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info);
+
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_fact_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_fact_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg);
+
+int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_user_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_user_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_user_prot_info);
+
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_user_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg);
+
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ *retlen = 0;
+ if (!master->_write_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ ret = master->_write_user_prot_reg(master, to, len, retlen, buf);
+ if (ret)
+ return ret;
+
+ /*
+ * If no data could be written at all, we are out of memory and
+ * must return -ENOSPC.
+ */
+ return (*retlen) ? 0 : -ENOSPC;
+}
+EXPORT_SYMBOL_GPL(mtd_write_user_prot_reg);
+
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_lock_user_prot_reg(master, from, len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
+
+/* Chip-supported device locking */
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_lock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock);
+
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unlock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_unlock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unlock);
+
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_is_locked)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_is_locked(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_is_locked);
+
+int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isreserved)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isreserved(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isreserved);
+
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isbad)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isbad(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isbad);
+
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ if (!master->_block_markbad)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ ret = master->_block_markbad(master, mtd_get_master_ofs(mtd, ofs));
+ if (ret)
+ return ret;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.badblocks++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_block_markbad);
+
+/*
+ * default_mtd_writev - the default writev method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+static int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ unsigned long i;
+ size_t totlen = 0, thislen;
+ int ret = 0;
+
+ for (i = 0; i < count; i++) {
+ if (!vecs[i].iov_len)
+ continue;
+ ret = mtd_write(mtd, to, vecs[i].iov_len, &thislen,
+ vecs[i].iov_base);
+ totlen += thislen;
+ if (ret || thislen != vecs[i].iov_len)
+ break;
+ to += vecs[i].iov_len;
+ }
+ *retlen = totlen;
+ return ret;
+}
+
+/*
+ * mtd_writev - the vector-based MTD write method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!master->_writev)
+ return default_mtd_writev(mtd, vecs, count, to, retlen);
+
+ return master->_writev(master, vecs, count,
+ mtd_get_master_ofs(mtd, to), retlen);
+}
+EXPORT_SYMBOL_GPL(mtd_writev);
+
+/**
+ * mtd_kmalloc_up_to - allocate a contiguous buffer up to the specified size
+ * @mtd: mtd device description object pointer
+ * @size: a pointer to the ideal or maximum size of the allocation, points
+ * to the actual allocation size on success.
+ *
+ * This routine attempts to allocate a contiguous kernel buffer up to
+ * the specified size, backing off the size of the request exponentially
+ * until the request succeeds or until the allocation size falls below
+ * the system page size. This attempts to make sure it does not adversely
+ * impact system performance, so when allocating more than one page, we
+ * ask the memory allocator to avoid re-trying, swapping, writing back
+ * or performing I/O.
+ *
+ * Note, this function also makes sure that the allocated buffer is aligned to
+ * the MTD device's min. I/O unit, i.e. the "mtd->writesize" value.
+ *
+ * This is called, for example by mtd_{read,write} and jffs2_scan_medium,
+ * to handle smaller (i.e. degraded) buffer allocations under low- or
+ * fragmented-memory situations where such reduced allocations, from a
+ * requested ideal, are allowed.
+ *
+ * Returns a pointer to the allocated buffer on success; otherwise, NULL.
+ */
+void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size)
+{
+ gfp_t flags = __GFP_NOWARN | __GFP_DIRECT_RECLAIM | __GFP_NORETRY;
+ size_t min_alloc = max_t(size_t, mtd->writesize, PAGE_SIZE);
+ void *kbuf;
+
+ *size = min_t(size_t, *size, KMALLOC_MAX_SIZE);
+
+ while (*size > min_alloc) {
+ kbuf = kmalloc(*size, flags);
+ if (kbuf)
+ return kbuf;
+
+ *size >>= 1;
+ *size = ALIGN(*size, mtd->writesize);
+ }
+
+ /*
+ * For the last resort allocation allow 'kmalloc()' to do all sorts of
+ * things (write-back, dropping caches, etc) by using GFP_KERNEL.
+ */
+ return kmalloc(*size, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(mtd_kmalloc_up_to);
+
+#ifdef CONFIG_PROC_FS
+
+/*====================================================================*/
+/* Support for /proc/mtd */
+
+static int mtd_proc_show(struct seq_file *m, void *v)
+{
+ struct mtd_info *mtd;
+
+ seq_puts(m, "dev: size erasesize name\n");
+ mutex_lock(&mtd_table_mutex);
+ mtd_for_each_device(mtd) {
+ seq_printf(m, "mtd%d: %8.8llx %8.8x \"%s\"\n",
+ mtd->index, (unsigned long long)mtd->size,
+ mtd->erasesize, mtd->name);
+ }
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+#endif /* CONFIG_PROC_FS */
+
+/*====================================================================*/
+/* Init code */
+
+static struct backing_dev_info * __init mtd_bdi_init(char *name)
+{
+ struct backing_dev_info *bdi;
+ int ret;
+
+ bdi = bdi_alloc(NUMA_NO_NODE);
+ if (!bdi)
+ return ERR_PTR(-ENOMEM);
+ bdi->ra_pages = 0;
+ bdi->io_pages = 0;
+
+ /*
+ * We put '-0' suffix to the name to get the same name format as we
+ * used to get. Since this is called only once, we get a unique name.
+ */
+ ret = bdi_register(bdi, "%.28s-0", name);
+ if (ret)
+ bdi_put(bdi);
+
+ return ret ? ERR_PTR(ret) : bdi;
+}
+
+static struct proc_dir_entry *proc_mtd;
+
+static int __init init_mtd(void)
+{
+ int ret;
+
+ ret = class_register(&mtd_class);
+ if (ret)
+ goto err_reg;
+
+ mtd_bdi = mtd_bdi_init("mtd");
+ if (IS_ERR(mtd_bdi)) {
+ ret = PTR_ERR(mtd_bdi);
+ goto err_bdi;
+ }
+
+ proc_mtd = proc_create_single("mtd", 0, NULL, mtd_proc_show);
+
+ ret = init_mtdchar();
+ if (ret)
+ goto out_procfs;
+
+ dfs_dir_mtd = debugfs_create_dir("mtd", NULL);
+
+ return 0;
+
+out_procfs:
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ bdi_put(mtd_bdi);
+err_bdi:
+ class_unregister(&mtd_class);
+err_reg:
+ pr_err("Error registering mtd class or bdi: %d\n", ret);
+ return ret;
+}
+
+static void __exit cleanup_mtd(void)
+{
+ debugfs_remove_recursive(dfs_dir_mtd);
+ cleanup_mtdchar();
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ class_unregister(&mtd_class);
+ bdi_put(mtd_bdi);
+ idr_destroy(&mtd_idr);
+}
+
+module_init(init_mtd);
+module_exit(cleanup_mtd);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
+MODULE_DESCRIPTION("Core MTD registration and access routines");
diff --git a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
new file mode 100755
index 0000000..668d9d9
--- /dev/null
+++ b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
@@ -0,0 +1,2063 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/device.h>
+#include "zx29_gmac.h"
+
+#define gmac_printk(_format, _args...) do{printk(KERN_INFO"gmac," _format "\n",##_args);}while(0)
+
+static u8 zx29_gmac_addr[MAC_ADDR_LENTH] = {0xec,0x1d,0x7f,0xb0,0x2f,0x32};
+static struct tasklet_struct *g_gmac_tasklet = NULL;
+/*struct zx29_gmac_dev *g_gmac_dev = NULL; */ /* no use possible */
+extern void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void* puf);
+extern int gmac_event_init(const char *name);
+static void gmac_hw_deinit(struct net_device *dev);
+//extern void v7_dma_map_area(const void *, size_t, int);
+//extern unsigned long virt_to_phys_ap(unsigned long virt);
+extern void dma_map(const void *addr, size_t len, int flags);
+extern unsigned long virt_to_phys_ap_new(unsigned long virt_addr);
+extern void kobj_gmac_del(struct kobject *kobject);
+
+
+void dump_pkt_trace(unsigned char *data,int len)
+{
+ int i;
+ len = len > 128?128:len;
+ printk("********************\n");
+ for(i=0;i<len;i++){
+ printk("%.2x ",data[i]);
+ if((i&0xf) == 0xf)
+ printk("\n");
+ }
+ printk("\n");
+ printk("********************\n");
+}
+
+static u32 zx29_gmac_get_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+
+ return prv->link.isup;
+}
+
+
+static void gmac_start(void* io)
+{
+ volatile unsigned *gmac = (unsigned*)io;
+
+ mac_int_enable();
+ dma_enable();
+ mac_enable();
+}
+
+static inline int mod_sub(int left, int right, int mod)
+{
+ return (mod - right + left) % mod;
+}
+
+static struct bd_tx *get_txed_bd(struct net_device *ndev)
+{
+ struct bd_tx *d;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int n = priv->txed_bd;
+
+ d = (struct bd_tx *)priv->dma_tx_vir;
+
+ if (n == priv->tx_bd_offset)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER)
+ return 0;
+
+ if (d[n].skb == NULL)
+ return 0;
+
+ priv->txed_bd++;
+ priv->txed_bd %= GMAC_TX_BD_NUM;
+
+ return &d[n];
+}
+
+static inline struct bd_tx *get_tx_bd(struct net_device *ndev)
+{
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+ int n = priv->tx_bd_offset;
+ struct bd_tx *d = (struct bd_tx*)priv->dma_tx_vir;
+
+ if (mod_sub(priv->tx_bd_offset, priv->txed_bd, GMAC_TX_BD_NUM) > GMAC_TX_BD_NUM - 2)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER) {
+ return 0;
+ } else {
+ return &d[n];
+ }
+}
+
+static struct bd_rx *get_rx_bd(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+ int n = prv->rx_bd_offset;
+ struct bd_rx *d = (struct bd_rx*)prv->dma_rx_vir;
+
+ if(d[n].RDES0 & DMA_OWNER)
+ {
+ return 0;
+ }
+ else
+ {
+ return &d[n];
+ }
+}
+
+static void gmac_trig_transmit(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 20) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 6:
+ dma_continue_tx();
+ break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 7:
+ default:
+ break;
+
+ }
+}
+
+static void gmac_trig_receive(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 17) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 4:
+ dma_continue_rx();
+ break;
+ default:
+ break;
+ }
+}
+
+static inline void gmac_update_mac(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned char *mac = (unsigned char*)ndev->dev_addr;
+
+ MAC(0x0044) = mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24;
+ MAC(0x0040) = mac[4] | mac[5] << 8;
+}
+
+static int zx29mii_read(struct mii_bus *bus, int phy_addr, int regnum)
+{
+ unsigned long flags;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 0 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irqsave(&prv->lock,flags);
+ while(mac_mii_is_busy());
+ MAC(0x0010) = val;
+ spin_unlock_irqrestore(&prv->lock,flags);
+
+ while(mac_mii_is_busy());
+
+ return (MAC(0x0014) & 0xFFFF);
+}
+
+static int zx29mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
+{
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 1 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irq(&prv->lock);
+ while(mac_mii_is_busy());
+ MAC(0x0014) = value;
+ MAC(0x0010) = val;
+
+ spin_unlock_irq(&prv->lock);
+
+ while(mac_mii_is_busy());
+
+ return 0;
+}
+
+static int zx29mii_reset(struct mii_bus *bus)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)priv->base_addr;
+
+ gmac_start((void *)priv->base_addr);
+ while (mac_mii_is_busy());
+ return 0;
+}
+
+static inline void zx29_gmac_set_macaddr(struct net_device *ndev)
+{
+ int i = 0;
+#if MAC_ADDR_SET
+ for (i = 0; i < MAC_ADDR_LENTH; i++)
+ ndev->dev_addr[i] = zx29_gmac_addr[i];
+
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ random_ether_addr(ndev->dev_addr);
+#else
+ random_ether_addr(ndev->dev_addr);
+#endif
+}
+
+static void zx29_gmac_tx(struct net_device *ndev)
+{
+ register unsigned status;
+ struct net_device_stats s = ndev->stats;
+ struct bd_tx *tx = get_txed_bd(ndev);
+
+
+ while (tx) {
+ status = tx->TDES0;
+
+ if (tx->TDES0 & ERR_TX_ES) {
+ s.tx_errors++;
+ if(status & ERR_TX_LC) s.tx_carrier_errors++;
+ if(status & ERR_TX_NC) s.tx_carrier_errors++;
+ if(status & ERR_TX_EC) s.tx_window_errors++;
+ if(status & ERR_TX_LATECOL) s.tx_window_errors++;
+ if(status & ERR_TX_UF) s.tx_aborted_errors++;
+ if(status & ERR_TX_ED) s.tx_aborted_errors++;
+ if(status & ERR_TX_JT) s.tx_fifo_errors++;
+ if(status & ERR_TX_FF) s.tx_fifo_errors++;
+
+ printk("%s, status=0x%x, err_cnt=%ld\n", __FUNCTION__,status, s.tx_errors);
+ }
+ dev_kfree_skb_any(tx->skb);
+ tx->skb = NULL;
+ tx = get_txed_bd(ndev);
+
+ }
+
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
+}
+
+static int zx29_gmac_rx(struct net_device *ndev)
+{
+ struct bd_rx *rx;
+ struct sk_buff *skb;
+ struct sk_buff *skb_new;
+ unsigned len;
+ int exhausted = 0;
+
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+
+ rx = get_rx_bd(ndev);
+
+ if(unlikely(!rx)) goto rcv_done;
+
+ while (rx) {
+ if ((rx->RDES0 & ERR_RX_ES) || (rx->RDES0 & ERR_RX_LE)) {
+ ndev->stats.rx_errors++;
+ if(rx->RDES0 & ERR_RX_LE) ndev->stats.rx_length_errors++;
+ if(rx->RDES0 & ERR_RX_OE) ndev->stats.rx_over_errors++;
+ if(rx->RDES0 & ERR_RX_IPC) ndev->stats.rx_frame_errors++;
+ if(rx->RDES0 & ERR_RX_LC) ndev->stats.rx_fifo_errors++;
+ if(rx->RDES0 & ERR_RX_CE) ndev->stats.rx_crc_errors++;
+ } else {
+
+ len = ((rx->RDES0 >> 16) & 0x3FFF) - 4;
+ if(len > (ETH_FRAME_LEN+8)) {
+ ndev->stats.rx_dropped++;
+ goto rx_bd_reset;
+ }
+
+ skb_new = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb_new)) {
+ ndev->stats.rx_dropped++;
+ exhausted++;
+ } else {
+ exhausted = 0;
+ ndev->stats.rx_packets++;
+ ndev->stats.rx_bytes += len;
+
+ dma_sync_single_for_cpu(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_FROM_DEVICE);
+ skb = rx->skb;
+ skb_put(skb, len); /*in fact , use for?*/
+
+// dump_pkt_trace(skb->data, len);
+ skb->protocol = eth_type_trans(skb, ndev);
+ netif_rx(skb);
+
+ skb_reserve(skb_new, NET_IP_ALIGN);
+// rx->dma_buf = virt_to_phys_ap((unsigned long)skb_new->data);
+ rx->dma_buf = virt_to_phys_ap_new((unsigned long)skb_new->data);
+ if(rx->dma_buf == NULL)
+ rx->dma_buf = __pa((unsigned)skb_new->data);
+ rx->skb = skb_new;
+ wmb();
+ dma_sync_single_for_device(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+ }
+ }
+rx_bd_reset:
+ rx->RDES0 = rx->RDES0 | DMA_OWNER;
+ priv->rx_bd_offset++;
+ priv->rx_bd_offset %= GMAC_RX_BD_NUM;
+ wmb();
+
+ if (exhausted >= 10)
+ break;
+ gmac_trig_receive((void*)ndev->base_addr);
+ rx = get_rx_bd(ndev);
+ }
+
+rcv_done:
+
+ gmac_trig_receive((void*)ndev->base_addr);
+
+ return (exhausted > 10);
+}
+
+
+#ifndef GMAC_NO_INT
+static irqreturn_t zx29_gmac_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned * gmac = (unsigned *)ndev->base_addr;
+
+ priv->int_event = MAC(0x1014);
+ MAC(0x1014) = priv->int_event;
+
+ mac_int_disable();
+ tasklet_schedule(&priv->tasklet);
+
+ return IRQ_HANDLED;
+}
+
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int events = prv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX)
+ zx29_gmac_rx(ndev);
+
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_TX | INT_ST_RX));
+
+ mac_int_enable();
+}
+
+#else
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned events = priv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX) {
+ if (zx29_gmac_rx(ndev))
+ break;
+ }
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_RX | INT_ST_TX));
+}
+
+enum hrtimer_restart gmac_timer_callback(struct hrtimer *timer)
+{
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+
+ hrtimer_forward_now(timer, gmac_schdule_time);
+ tasklet_schedule(g_gmac_tasklet);
+ return HRTIMER_RESTART;
+}
+#endif
+
+static inline void zx29_gmac_linkisup(struct net_device *dev, int isup)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+
+ priv->link.duplex = phydev->duplex;
+ priv->link.giga = (phydev->speed == 100);
+ if (priv->link.speed != phydev->speed)
+ priv->link.speed = phydev->speed;
+
+
+ priv->link.isup = isup;
+ if (isup)
+ netif_carrier_on(dev);
+ phy_print_status(phydev);
+}
+
+static void zx29_gmac_adjust_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+ volatile unsigned *gmac = (unsigned *)dev->base_addr;
+
+ if (priv->link.isup &&
+ (!phydev->link ||
+ (priv->link.speed != phydev->speed) ||
+ (priv->link.duplex != phydev->duplex))) {
+ priv->link.isup = 0;
+ netif_tx_disable(dev);
+ if (!phydev->link) {
+ netif_carrier_off(dev);
+ phy_print_status(phydev);
+ }
+ }
+
+ if (!priv->link.isup && phydev->link) {
+ if (priv->link.duplex != phydev->duplex) {
+ if (phydev->duplex)
+ mac_set_full_duplex_mode();
+ else
+ mac_set_half_duplex_mode();
+ }
+
+ if (priv->link.giga != (phydev->speed == 100)) {
+ if (phydev->speed == 100)
+ mac_set_speed_100m_mode();
+ else
+ mac_set_speed_10m_mode();
+ }
+ netif_wake_queue(dev);
+ zx29_gmac_linkisup(dev, 1);
+ }
+
+}
+
+static inline int zx29_gmac_phy_start(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *p = NULL;
+ struct mdio_device *mdio_dev = NULL;
+ int ret = 0;
+
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 start
+ int i = 0;
+ for(i = 0;i <= 5;i++)
+ {
+ if (priv->nports == 1) {
+ p = phy_find_first(priv->mii.bus);
+ } else if (priv->rmii_port < PHY_MAX_ADDR) {
+ mdio_dev = priv->mii.bus->mdio_map[priv->rmii_port];
+ p = container_of(mdio_dev, struct phy_device, mdio);
+ }
+
+ if (!p) {
+ if(i == 5){
+ gpio_direction_output(priv->gpio_power[0], 0);
+#ifdef CONFIG_MDIO_C45
+ gpio_direction_output(priv->gpio_power[1], 0);
+#endif
+ }
+ else
+ continue;
+ printk("%s: no PHY found\n", dev->name);
+ return -ENODEV;
+ }
+ else
+ break;
+ }
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 end
+
+ ret = phy_connect_direct(dev, p, zx29_gmac_adjust_link, PHY_INTERFACE_MODE_RMII); /* phy_start_machine */
+ /* supported and advertising */
+ priv->phydev = p;
+ return 0;
+}
+
+
+static int gmac_init_rx_bd(struct net_device *ndev, struct zx29_gmac_dev *priv)
+{
+ struct sk_buff *skb = NULL;
+ struct bd_rx *rx = (struct bd_rx *)priv->dma_rx_vir;
+ int i = 0;
+
+ priv->rx_bd_offset = 0;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ skb = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb)) {
+ gmac_hw_deinit(ndev);
+ return -1;
+ }
+
+ skb_reserve(skb, NET_IP_ALIGN);
+
+ rx[i].RDES0 |= DMA_OWNER; /* when to change? */
+ rx[i].RDES1 = 0;
+ rx[i].RDES1 = GMAC_FRAME_LEN | 1 << 14;
+ rx[i].dma_buf = __pa((unsigned)skb->data); /* __pa ? */
+ rx[i].next = priv->dma_rx_phy + ((i + 1) << 5); /* why phy? */
+ rx[i].skb = skb;
+#if 0
+ if(i%4 != 0)
+ {
+ rx[i].RDES1 |= 0x80000000;
+ }
+#endif
+ dma_sync_single_for_device(&ndev->dev, rx[i].dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+
+ }
+ rx[GMAC_RX_BD_NUM - 1].next = priv->dma_rx_phy;
+ rx[GMAC_RX_BD_NUM - 1].RDES1 = GMAC_FRAME_LEN | 1 << 14 | 1 << 15;
+
+ return 0;
+}
+
+static void gmac_init_tx_bd(struct zx29_gmac_dev *priv)
+{
+ struct bd_tx *tx = (struct bd_tx *)priv->dma_tx_vir;
+ int i = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ tx[i].TDES0 = (1 << 20 | 1 << 30);
+ tx[i].TDES1 = GMAC_FRAME_LEN;
+ tx[i].next = priv->dma_tx_phy + ((i + 1) << 5);
+ }
+
+ tx[GMAC_TX_BD_NUM - 1].next = priv->dma_tx_phy;
+ tx[GMAC_TX_BD_NUM - 1].TDES0 = 1 << 20 | 1 << 21 | 1 << 30;
+
+}
+
+static void gmac_stop(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ dma_clear_tx_fifo();
+ dma_wait_tx_fifo_cleared();
+}
+
+static void gmac_set_speed_duplex(struct net_device *ndev, int speed, int duplex)
+{
+ unsigned val;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+
+ val = MAC(0x0000) | 1 << 11 | 1 << 14;
+ if (SPEED_10 == speed)
+ val &= ~(1 << 14);
+ if (DUPLEX_HALF == duplex) {
+ val &= (~(1 << 11));
+ val |= (1 << 16);
+ }
+ MAC(0x0000) = val;
+}
+
+static void mac_init(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int i = 0, j = 0, mac_rst = 0;
+ unsigned long long mac_time_start = 0;
+ unsigned long long mac_time_end = 0;
+
+ mac_provide_clock();
+#ifdef __DEAD_LOOP_POLL__
+ mac_reset();
+ mac_set_gmii_mode();
+ mac_wait_reset_finished();
+#else
+ mac_time_start = local_clock();
+ for (i = 0; i < MAC_RESET_NUM; i++) {
+ mac_reset();
+ mac_set_mii_mode();
+ for (j = 0; j < MAC_WAIT_TIME; j++) {
+// printk(".");
+ if (!((MAC(0x1000)) & 1)) {
+ mac_time_end = local_clock();
+ printk("ok:time:%llu ns\n", mac_time_end - mac_time_start);
+ mac_rst = 1;
+ goto mac_reset_option;
+ }
+ udelay(100);
+ }
+ }
+ mac_time_end = local_clock();
+mac_reset_option:
+ if(!mac_rst)
+ printk("gmac reset failed!time:%llu us\n", mac_time_end - mac_time_start);
+#endif
+ while(mac_mii_is_busy());
+}
+
+static void gmac_hw_deinit(struct net_device *ndev)
+{
+ int i;
+ struct bd_rx *rx_bd;
+ struct bd_tx *tx_bd;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ gmac_stop((void *)ndev->base_addr);
+
+ if (priv->dma_rx_phy) {
+ rx_bd = (struct bd_rx *)priv->dma_rx_vir;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ if (rx_bd[i].skb)
+ dev_kfree_skb_any(rx_bd[i].skb);
+ }
+
+ tx_bd = (struct bd_tx *)priv->dma_tx_vir;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ if (tx_bd[i].skb)
+ dev_kfree_skb_any(tx_bd[i].skb);
+ }
+ }
+
+ dma_set_tx_buffer(0); //设置首个BD的缓冲区为0；
+ dma_set_rx_buffer(0);
+
+ priv->rx_bd_offset = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+ priv->dma_rx_phy = 0;
+ priv->dma_rx_vir = 0;
+ priv->dma_tx_phy = 0;
+ priv->dma_tx_vir = 0;
+
+}
+
+static int gmac_hw_init(struct net_device *ndev)
+{
+ int ret = -1;
+ unsigned val;
+
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (priv->dma_rx_phy)
+ gmac_hw_deinit(ndev);
+
+ priv->dma_rx_vir = priv->dma_rx_vir_init;
+ priv->dma_rx_phy = priv->dma_rx_phy_init;
+ priv->dma_tx_vir = priv->dma_rx_vir + GMAC_RX_BUF_LEN;
+ priv->dma_tx_phy = priv->dma_rx_phy + GMAC_RX_BUF_LEN; /* ifconfig up, clear fifo*/
+
+ memset(priv->dma_rx_vir, 0, GMAC_BUF_LEN);
+
+ ret = gmac_init_rx_bd(ndev, priv);
+ if (ret < 0) {
+ printk("hw_net_init,init_rx_bd fail\n");
+ return ret;
+ }
+ gmac_init_tx_bd(priv);
+
+ mac_init(ndev);
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ val = MAC(0x1000);
+ val &= ~(0x3F << 8);
+ val |= (0x10 << 8);
+ MAC(0x1000) = val;
+
+ dma_set_rx_buffer(priv->dma_rx_phy);
+ dma_set_tx_buffer(priv->dma_tx_phy);
+
+ mac_int_clear(0x0001FFFF);
+ while (mac_mii_is_busy());
+
+ gmac_set_speed_duplex(ndev, priv->phydev->speed, priv->phydev->duplex);
+
+ mac_rece_all_data();
+
+ gmac_start((void *)ndev->base_addr);
+ return 0;
+}
+
+static int zx29_gmac_open(struct net_device *ndev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ unsigned long flags;
+ int ret;
+ int err = 0;
+#ifdef GMAC_NO_INT
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time;
+#endif
+ err = phy_read_status(priv->phydev); /*interal, phy drv provide*/
+ if (err < 0)
+ return err;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->link.speed = 0;
+
+ zx29_gmac_linkisup(ndev, priv->phydev->link);
+
+ ret = gmac_hw_init(ndev);
+ if(ret) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+
+ netif_carrier_on(ndev);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ phy_start(priv->phydev);
+
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+ if (priv->timer)
+ hrtimer_start(priv->timer, gmac_schdule_time, HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+
+ printk("TSP zx29 gmac net open\n");
+
+ return 0;
+}
+
+static int zx29_gmac_stop(struct net_device *ndev)
+{
+ unsigned long flags = 0;
+ int ret = 0;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (!priv->stopped) {
+ spin_lock_irqsave(&priv->lock, flags);
+#ifdef GMAC_NO_INT
+ ret = hrtimer_cancel(priv->timer);
+ if (ret < 0) {
+ BUG_ON(1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+#endif
+
+ priv->stopped = 1;
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ phy_stop(priv->phydev);
+ gmac_hw_deinit(ndev);
+
+ memset(&ndev->stats, 0, sizeof(struct net_device_stats));
+ spin_unlock_irqrestore(&priv->lock, flags);
+ printk("TSP zx29 gmac net stop\n");
+ }
+ return 0;
+}
+
+
+static netdev_tx_t zx29_gmac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ unsigned long flags;
+ unsigned len;
+ struct sk_buff *skb_old;
+ struct bd_tx *tx;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (0 == priv->link.isup) {
+ dev_kfree_skb_any(skb);
+ printk("TSP zx29 gmac xmit phy not link\n");
+ return NETDEV_TX_OK; /* ? */
+ }
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if(priv->stopped)
+ {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+
+ printk("zx_net_start_xmit when stopped\n");
+
+ return NETDEV_TX_OK;
+ }
+
+ tx = get_tx_bd(ndev);
+
+ if (!tx) {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ priv->tx_bd_offset++;
+ priv->tx_bd_offset %= GMAC_TX_BD_NUM;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ if(skb->len > ETH_FRAME_LEN + 4) /* why 4*/
+ printk("TSP zx29 gmac start xmit len too long\n");
+
+// v7_dma_map_area(skb->data, skb->len, DMA_TO_DEVICE);
+ dma_map(skb->data, skb->len, DMA_TO_DEVICE);
+ if (NULL == skb)
+ BUG_ON(1);
+
+ len = MIN(skb->len, GMAC_FRAME_LEN - NET_IP_ALIGN);
+
+ tx->TDES0 |= (0x07 << 28);
+// tx->dma_buf = virt_to_phys_ap((unsigned long)skb->data);
+ tx->dma_buf = virt_to_phys_ap_new((unsigned long)skb->data);
+
+ if(tx->dma_buf == NULL)
+ tx->dma_buf = virt_to_phys((unsigned)skb->data);
+ tx->skb = skb;
+
+ tx->TDES1 = len;
+ tx->TDES0 |= DMA_OWNER;
+
+ wmb();
+ ndev->stats.tx_bytes += len;
+ ndev->stats.tx_packets++;
+/* ndev->trans_start = jiffies; */
+
+
+ gmac_trig_transmit((void*)ndev->base_addr);
+// dump_pkt_trace(skb->data, len);
+// printk("[%s]\n", __func__);
+
+ return NETDEV_TX_OK;
+}
+
+static void zx29_gmac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ genphy_update_link(priv->phydev);
+#endif
+ priv->link.isup = priv->phydev->link;
+
+ if (0 == priv->link.isup) {
+ printk("TSP zx29 gmac net timeout phy not link\n"); // PHY 未连接
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ } else {
+ printk("TSP zx29 gmac net timeout phy linked\n");
+ gmac_trig_transmit(ndev);
+ gmac_trig_receive(ndev);
+
+ netif_carrier_on(ndev);
+ netif_wake_queue(ndev);
+/* ndev->trans_start = jiffies; */ /* modify */
+ ndev->stats.tx_errors++;
+ ndev->stats.tx_dropped++;
+ }
+}
+
+void __iomem *base_clk = NULL;
+void __iomem *base_phy_release = NULL;
+
+static int zx29_gmac_phy_disable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+
+ enum of_gpio_flags flags;
+ unsigned long flag;
+ int gpio = 0;
+ int ret = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if (ndev && !priv->stopped) {
+ if (netif_running(ndev)) {
+
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+ printk("[%s] netif_running\n", __func__);
+
+ gpio_direction_output(priv->gpio_power[0], 0);
+
+ gmac_stop((void*)ndev->base_addr);
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+// netif_device_detach(ndev);
+ }
+ pm_relax(&pdev->dev);
+ // printk("[%s] sleep\n");
+ }
+#endif
+ //printk("[%s] exit\n", __func__);
+ return 0;
+}
+
+static int zx29_gmac_phy_enable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ int ret = 0;
+ int status = 0;
+ int islink = 0;
+ unsigned int num= 0;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if(ndev && priv->stopped) {
+ pm_stay_awake(&pdev->dev);
+ if( netif_running(ndev)) {
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+// netif_device_attach(ndev);
+ }
+ }
+#endif
+ return 0;
+}
+
+#define C45_READ 1
+#define C45_WRITE 0
+static int zx29_c22_2_c45(struct phy_device *phydev, int addr, u16 devad, u32 regnum, int rw, int write_val)
+{
+ int val = 0;
+ phy_lock_mdio_bus(phydev);
+ /* Write the desired MMD Devad */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL, devad);
+ /* Write the desired MMD register address */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, regnum);
+ /* Select the Function : DATA with no post increment */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL,
+ devad | MII_MMD_CTRL_NOINCR);
+ /* Read the content of the MMD's selected register */
+ if (rw == C45_READ)
+ val = __mdiobus_read(phydev->mdio.bus, addr, MII_MMD_DATA);
+ else
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, write_val);
+ phy_unlock_mdio_bus(phydev);
+
+ return val;
+}
+
+static int zx29_c45_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
+{
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ u16 val = mii_data->val_in;
+ bool change_autoneg = false;
+ int prtad, devad, reg_num;
+
+ switch (cmd) {
+ case SIOCGMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);//phy id
+ devad = mdio_phy_id_devad(mii_data->phy_id);//dev id / mmd
+ reg_num = mii_data->reg_num;
+ mii_data->val_out = zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_READ, 0);
+ return 0;
+
+ case SIOCSMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);
+ devad = mdio_phy_id_devad(mii_data->phy_id);
+ reg_num = mii_data->reg_num;
+
+ if (prtad == phydev->mdio.addr) {
+ switch (devad) {
+ case MII_BMCR:
+ if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) {
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_DISABLE;
+ if (val & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ if (val & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (val & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else phydev->speed = SPEED_10;
+ }
+ else {
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_ENABLE;
+ }
+ break;
+ case MII_ADVERTISE:
+ mii_adv_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ case MII_CTRL1000:
+ mii_ctrl1000_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+
+ zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_WRITE, val);
+
+ if (prtad == phydev->mdio.addr &&
+ devad == MII_BMCR &&
+ val & BMCR_RESET)
+ return phy_init_hw(phydev);
+
+ if (change_autoneg)
+ return phy_start_aneg(phydev);
+
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int zx29_gmac_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ int is_c45 = mdio_phy_id_is_c45(mii_data->phy_id);
+
+ if (!(netif_running(ndev)))
+ return -EINVAL;
+ if (!priv->phydev)
+ return -EINVAL;
+ if (cmd == SIOCDISABLEPHY)
+ return zx29_gmac_phy_disable(ndev->dev.parent);
+
+ if (cmd == SIOCENABLEPHY)
+ return zx29_gmac_phy_enable(ndev->dev.parent);
+
+ if (is_c45)
+ return zx29_c45_mii_ioctl(priv->phydev, ifr, cmd);
+
+ return phy_mii_ioctl(priv->phydev, ifr, cmd);
+}
+
+static int eth_change_mtu(struct net_device *ndev, int new_mtu)
+{
+ if (new_mtu < 68 || new_mtu > ETH_DATA_LEN)
+ return -EINVAL;
+ ndev->mtu = new_mtu;
+ return 0;
+}
+
+static int zx29_gmac_set_mac_address(struct net_device *ndev, void *p)
+{
+ int ret = eth_mac_addr(ndev, p);
+ if (!ret) {
+ gmac_update_mac(ndev);
+ printk(" zx29 gmac set mac addr ok\n");
+ }
+ return ret;
+}
+
+
+static int zx29_gmac_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ unsigned long flag;
+
+ if(ndev) {
+ if(netif_running(ndev)) {
+// netif_device_detach(ndev);
+// gmac_stop((void*)ndev->base_addr);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ phy_stop(priv->phydev);
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+
+ printk("[%s] netif_running\n", __func__);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gmac_stop((void*)ndev->base_addr);
+#else
+ gmac_stop((void*)ndev->base_addr);
+ gpio_direction_output(priv->gpio_power[0], 0);
+#endif
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+#endif
+ }
+ }
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_sleep_state(&pdev->dev);
+#endif
+ return 0;
+}
+
+static int zx29_gmac_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_default_state(&pdev->dev);
+#endif
+ if(ndev) {
+ if(netif_running(ndev)) {
+// gmac_start((void*)ndev->base_addr);
+// netif_device_attach(ndev);
+// zx29_gmac_phy_enable(dev);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+
+ phy_start(priv->phydev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+#endif
+
+ }
+ }
+ return 0;
+}
+
+static const struct ethtool_ops zx29_gmac_ethtool_ops = {
+ .get_link = zx29_gmac_get_link,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ /* other func */
+};
+
+static const struct net_device_ops zx29_gmac_netdev_ops = {
+ .ndo_open = zx29_gmac_open,
+ .ndo_stop = zx29_gmac_stop,
+ .ndo_start_xmit = zx29_gmac_start_xmit,
+ .ndo_tx_timeout = zx29_gmac_tx_timeout,
+ .ndo_do_ioctl = zx29_gmac_ioctl,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = zx29_gmac_set_mac_address,
+};
+
+
+
+ssize_t show_fun(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ int status = 0;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ printk("MAC(1000) :0x%x\n", MAC(0x1000));
+ printk("MAC(1004) :0x%x\n", MAC(0x1004));
+ printk("MAC(1008) :0x%x\n", MAC(0x1008));
+ printk("MAC(100c) :0x%x\n", MAC(0x100c));
+ printk("MAC(1010) :0x%x\n", MAC(0x1010));
+ printk("MAC(1014) int status:0x%x\n", MAC(0x1014));
+ printk("MAC(1018) :0x%x\n", MAC(0x1018));
+ printk("MAC(101c) :0x%x\n", MAC(0x101c));
+ printk("MAC(0000) :0x%x\n", MAC(0x0000));
+ printk("MAC(0004) :0x%x\n", MAC(0x0004));
+ printk("MAC(0010) :0x%x\n", MAC(0x0010));
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 1);
+ printk("phy status:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 0, 1);
+ printk("phy status port0:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 1, 1);
+ printk("phy status port1:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 2, 1);
+ printk("phy status port2:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 3, 1);
+ printk("phy status port3:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 4, 1);
+ printk("phy status port4:0x%x\n", status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 20);
+ status |= 0x4;
+ mdiobus_write(priv->phydev->mdio.bus, 21, 20, status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 21);
+ printk("phy status loop port:0x%x\n", status);
+
+
+ return 0;
+}
+
+ssize_t store_fun(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ printk("[%s]", __func__);
+ return 1;
+}
+
+
+ssize_t mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x", &rd_wt, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ return count;
+}
+
+
+ssize_t free_mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t free_mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ int phy_addr = 8;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x,%x", &rd_wt, &phy_addr, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, phy_addr, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,phy_addr,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ return count;
+}
+
+extern int debug_on;
+ssize_t debug_on_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if (ret < 1) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input %d\n",
+ ret,val);
+ return count;
+ }
+ debug_on = val;
+ return count;
+}
+
+ssize_t debug_on_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (debug_on)
+ memcpy(buf, "on", 3);
+ else
+ memcpy(buf, "off", 4);
+ return 0;
+}
+
+/*jb.qi add for gamc power down on 20231116 start*/
+
+extern int gmac_power = 1;
+int gmac_power_flag = 0;
+
+ssize_t gmac_power_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if(ret < 1)
+ {
+ printk(KERN_INFO "gmac: failed ti read user buf, ret=%d, input %d\n", ret,val);
+ return count;
+ }
+ gmac_power = val;
+ gpio_direction_output(gmac_power_flag, val);
+ return count;
+}
+
+ssize_t gmac_power_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ if(gmac_power)
+ memcpy(buf, "on",3);
+ else
+ memcpy(buf, "off", 4);
+
+ printk("gmac_power %s\n", buf);
+ return 0;
+
+}
+/*jb.qi add for gamc power down on 20231116 end */
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 start*/
+static int mode_type = -1;
+static int enter_only_one = 0;
+
+ssize_t gmac_master_or_slave_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///read mode_type
+ ret = sscanf(buf, "%d", &mode_type);
+ if (ret < 1) {
+ printk(KERN_ERR "Please enter the number 0-3 to enable the corresponding mode \n"
+ "Enter values in the non-0-3 range to get pattern description \n");
+ return count;
+ }
+
+ ///Judgment model
+ if (mode_type < 0 || mode_type > 3) {
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ return ret ? ret : count;
+ }
+
+ ///Set the Ethernet slave mode
+ if (mode_type == 0) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val & (~BIT(14)));
+ }
+ ///Set the Ethernet master mode
+ else if (mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val | BIT(14));
+ }
+ return count;
+}
+
+ssize_t gmac_master_or_slave_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int len = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///Reentrant prevention
+ if(enter_only_one == 1)
+ {
+ return 0;
+ }
+ enter_only_one = 1;
+
+ ///Read the network master/slave
+ if (mode_type == 0 || mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e) & BIT(14);
+ if(val)
+ memcpy(buf, "Master\n",7);
+ else
+ memcpy(buf, "Slave\n", 6);
+
+ printk(KERN_DEBUG "mode_type %d - gmac_master_or_slave is %s\n", mode_type, buf);
+
+ }
+ ///Obtain the cable quality SQI value
+ else if(mode_type == 2){
+ mmd = 0x1;
+ reg = 0x8B10;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "0x%x\n", val);
+ sprintf(buf, "SQI : 0x%x\n", val);
+ printk(KERN_DEBUG "mode_type %d - SQI is 0x%x", mode_type, val);
+
+ }
+ ///Obtain short circuit, open circuit and normal connection of VCT
+ else if(mode_type == 3){
+ ///--TDR Enable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, BIT(14) | BIT(12));
+ msleep(10);
+ ///--Read VCT
+ mmd = 0x1;
+ reg = 0x8B02;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ printk(KERN_DEBUG "Open status: %s - Short status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ sprintf(buf, "Open status: %s\nShort status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ reg = 0x8B01;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "%sDistance status: 0x%x\n", buf, val);
+ printk(KERN_DEBUG "mode_type %d - Distance status is 0x%x\n", mode_type, val);
+
+ ///--TDR Disable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, 0);
+
+ }
+ ///Get model help information
+ else{
+ sprintf(buf, "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ }
+ enter_only_one = 0;
+ return strlen(buf);
+
+}
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 end */
+
+static DEVICE_ATTR(gmac_test, 0664, show_fun, store_fun);
+static DEVICE_ATTR(mdio_test, 0664, mdio_show, mdio_store);
+static DEVICE_ATTR(free_mdio, 0664, free_mdio_show, free_mdio_store);
+static DEVICE_ATTR(debug_on, 0664, debug_on_show, debug_on_store);
+static DEVICE_ATTR(gmac_power, 0664, gmac_power_show, gmac_power_store);//jb.qi add for gamc power down on 20231116
+static DEVICE_ATTR(gmac_master_or_slave, 0664, gmac_master_or_slave_show, gmac_master_or_slave_store);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+
+static int zx29_gmac_probe(struct platform_device *pdev)
+{
+ struct zx29_gmac_dev *prv = NULL;
+ struct net_device *ndev = alloc_etherdev(sizeof(struct zx29_gmac_dev));
+ volatile unsigned int *gmac = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ int ret = -1;
+ unsigned long i;
+ struct mii_bus *mb;
+ struct resource *iomem;
+ void __iomem *base = NULL;
+ struct pinctrl *pctrl;
+ struct pinctrl_state *state0;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ char board_name[128] = {"init_failed"};
+
+ printk("[%s] #########zx29_gmac_probe begin.\n", __func__);
+ if (!ndev)
+ return -ENOMEM;
+
+ device_create_file(&pdev->dev, &dev_attr_gmac_test);
+ device_create_file(&pdev->dev, &dev_attr_mdio_test);
+ device_create_file(&pdev->dev, &dev_attr_free_mdio);
+ device_create_file(&pdev->dev, &dev_attr_debug_on);
+ device_create_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_create_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+
+ prv = netdev_priv(ndev);
+ memset(prv, 0, sizeof(*prv));
+ prv->stopped = 1;
+
+ pctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(pctrl)) {
+ dev_warn(&pdev->dev, "Failed to get test pins");
+ pctrl = NULL;
+ goto errirq;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ state0 = pinctrl_lookup_state(pctrl, "state0");
+#else
+ state0 = pinctrl_lookup_state(pctrl, "default");
+#endif
+ if (IS_ERR(state0)) {
+ dev_err(&pdev->dev, "TEST: missing state0\n");
+ goto pinctrl_init_end;
+ }
+
+ if (pinctrl_select_state(pctrl, state0) < 0) {
+ dev_err(&pdev->dev, "setting state0 failed\n");
+ goto pinctrl_init_end;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ prv->gpio_power[2] = of_get_gpio_flags(pdev->dev.of_node, 2, &flags);
+ ret = gpio_request(prv->gpio_power[2], "phy_power"); /* gpio 51 */
+ gpio_direction_output(prv->gpio_power[2], 1);
+ mdelay(15);
+#endif
+
+ prv->gpio_power[0] = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
+ ret = gpio_request(prv->gpio_power[0], "gmac_power"); /* gpio 83/124 */
+ gpio_direction_output(prv->gpio_power[0], 1);
+ mdelay(15);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ prv->gpio_power[1] = of_get_gpio_flags(pdev->dev.of_node, 1, &flags);
+ ret = gpio_request(prv->gpio_power[1], "phy_rst"); /* gpio 63 */
+ gpio_direction_output(prv->gpio_power[1], 0);
+ mdelay(10);
+ gpio_direction_output(prv->gpio_power[1], 1);
+ mdelay(15);
+#endif
+
+ SET_NETDEV_DEV(ndev, &pdev->dev); //if not, will panic
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ gmac_power_flag = prv->gpio_power[0];//jb.qi add for gamc power down on 20231116
+ ndev->base_addr = base;/*iomem->start;*/
+ if (!ndev->base_addr)
+ return -ENXIO;
+
+#ifndef GMAC_NO_INT
+ ndev->irq = platform_get_irq(pdev, 0);
+#endif
+ ndev->netdev_ops = &zx29_gmac_netdev_ops;
+ ndev->ethtool_ops = &zx29_gmac_ethtool_ops;
+
+ gmac = (unsigned *)ndev->base_addr;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ spin_lock_init(&prv->lock);
+
+
+/* wake_lock_init(&prv->wake_lock, WAKE_LOCK_SUSPEND, "gmac_pm"); //what replace?
+ wake_lock(&prv->wake_lock); */
+ device_init_wakeup(&pdev->dev, true);
+
+
+ zx29_gmac_set_macaddr(ndev);
+
+#ifndef GMAC_NO_INT
+ ret = request_irq(ndev->irq, zx29_gmac_interrupt, 0, ndev->name, ndev);
+ if (ret) {
+ printk(KERN_ERR "irq request failed: %d\n", ndev->irq);
+ goto errirq;
+ }
+#endif
+
+ ret = register_netdev(ndev);
+ if (ret) {
+ printk(KERN_ERR "error registering device %s\n",
+ ndev->name);
+ goto errdev;
+ }
+
+ of_property_read_u32(np, "port-nums", &prv->nports);
+ of_property_read_u32(np, "rmii-ports", &prv->rmii_port);
+ prv->base_addr = ndev->base_addr;
+
+ prv->netdev = ndev;
+
+ mb = mdiobus_alloc();
+ if (!mb) {
+ printk(KERN_ERR "error allocating mii bus\n");
+ goto errmii;
+ }
+ mb->name = "zx29_gmac_mii";
+ mb->read = zx29mii_read;
+ mb->write = zx29mii_write;
+ mb->reset = zx29mii_reset;
+ mb->priv = prv;
+ snprintf(mb->id, MII_BUS_ID_SIZE, "%s-%x", "zx29_gmac", 0);
+ of_property_read_u32(np, "port-mask", &mb->phy_mask);
+/* mb->irq = &prv->mii.irq[0]; */
+ for (i = 0; i < PHY_MAX_ADDR; i++) {
+ int n = platform_get_irq(pdev, i + 1); /* devtrrr modify */
+ if (n < 0)
+ n = PHY_POLL;
+ prv->mii.irq[i] = n;
+ mb->irq[i] = n;
+ }
+
+ base = devm_platform_ioremap_resource(pdev, 2);
+ gmac_set_clk();
+ base_clk = base;
+
+ base = devm_platform_ioremap_resource(pdev, 1);
+ gmac_phy_release();
+ base_phy_release = base;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ mdelay(500);
+#else
+ mdelay(10); //zw.wang@20240306 modify. Here, the jl3103 is set as an example, and other phy peripherals need to be optimized according to different reset stability times
+#endif
+
+ ret = mdiobus_register(mb);
+ if (ret < 0) {
+ printk("[%s] mdiobus register failed!\n", __func__);
+ goto errmdioregister;
+ }
+
+ prv->mii.bus = mb;
+ ret = zx29_gmac_phy_start(ndev);
+ if (ret)
+ goto errphystart;
+
+ if (!(prv->phydev->phy_id == 0x00000000 || prv->phydev->phy_id == 0xffffffff)) {
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ pm_stay_awake(&pdev->dev);
+#endif
+ strcpy(board_name, "cpe");
+
+ printk("[%s] phy id = 0x%x \n", __func__, prv->phydev->phy_id);
+ printk("set gmac wakelock!\n");
+ } else {
+ strcpy(board_name, "mdl");
+ netif_device_detach(ndev);
+ }
+
+ platform_set_drvdata(pdev, ndev);
+
+ tasklet_init(&prv->tasklet, zx29_gmac_tasklet, (unsigned long)ndev);
+ g_gmac_tasklet = &prv->tasklet;
+
+
+ prv->dma_rx_vir = dma_alloc_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_phy, GFP_KERNEL);
+ if (!prv->dma_rx_vir) { // null, ndev->dev.parent difference?
+ BUG_ON(1);
+ goto errphystart;
+ }
+
+ prv->dma_rx_phy_init = prv->dma_rx_phy;
+ prv->dma_rx_vir_init = prv->dma_rx_vir;
+ prv->dma_tx_phy = prv->dma_rx_phy + GMAC_RX_BUF_LEN;
+ prv->dma_tx_vir = prv->dma_rx_vir + GMAC_RX_BUF_LEN;
+
+#ifdef GMAC_NO_INT
+ sema_init(&prv->sem, 0);
+
+ prv->timer = kzalloc(sizeof(struct hrtimer), GFP_KERNEL);
+ if (!prv->timer) {
+ BUG_ON(1);
+ goto errmalloc;
+ }
+ hrtimer_init(prv->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+
+ prv->timer->function = gmac_timer_callback;
+#endif
+
+ gmac_event_init(board_name);
+/* g_gmac_dev = prv; */ /* no use possible*/
+
+ printk("[%s] probe end\n", __func__);
+ return 0;
+errmalloc:
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_vir, prv->dma_rx_phy);
+
+
+errphystart:
+ mdiobus_unregister(mb);
+
+
+errmdioregister:
+ mdiobus_free(mb);
+
+errmii:
+ unregister_netdev(ndev);
+
+errdev:
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+
+pinctrl_init_end:
+
+errirq:
+ free_netdev(ndev);
+
+ printk("#########zx29_gmac_probe fail.\n");
+ return ret;
+}
+
+static int zx29_gmac_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ volatile unsigned *gmac = NULL;
+ if (ndev) {
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+
+// gpio_direction_output(priv->gpio_power[0], 1);
+// msleep(500);
+ unregister_netdev(ndev);
+
+ phy_disconnect(priv->phydev);
+
+ kobj_gmac_del(NULL);
+
+ mdiobus_unregister(priv->mii.bus);
+ mdiobus_free(priv->mii.bus);
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+ tasklet_disable(&priv->tasklet);
+ tasklet_kill(&priv->tasklet);
+
+ if (priv->dma_rx_vir)
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, priv->dma_rx_vir, priv->dma_rx_phy);
+
+ pm_relax(&pdev->dev);
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ gpio_free(priv->gpio_power[1]);
+#endif
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gpio_free(priv->gpio_power[0]);
+
+ device_remove_file(&pdev->dev, &dev_attr_gmac_test);
+ device_remove_file(&pdev->dev, &dev_attr_mdio_test);
+ device_remove_file(&pdev->dev, &dev_attr_free_mdio);
+ device_remove_file(&pdev->dev, &dev_attr_debug_on);
+ device_remove_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_remove_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+ }
+ return 0;
+}
+
+static struct dev_pm_ops zx29_gmac_pm_ops = {
+ .suspend = zx29_gmac_suspend,
+ .resume = zx29_gmac_resume,
+};
+
+static const struct of_device_id gmac_match_table[] = {
+ {.compatible = "zte, zx29_gmac",},
+};
+
+static struct platform_driver zx29_gmac_driver = {
+ .probe = zx29_gmac_probe,
+ .remove = zx29_gmac_remove,
+ .driver = {
+ .name = "zx29_gmac",
+ .owner = THIS_MODULE,
+ .pm = &zx29_gmac_pm_ops,
+ .of_match_table = gmac_match_table,
+ },
+};
+
+static int __init zx29_gmac_init(void)
+{
+ return platform_driver_register(&zx29_gmac_driver);
+}
+
+static void __exit zx29_gmac_exit(void)
+{
+ printk("[%s] start exit!\n", __func__);
+ platform_driver_unregister(&zx29_gmac_driver);
+}
+
+module_init(zx29_gmac_init);
+module_exit(zx29_gmac_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ZX29 on chip Ethernet driver");
+MODULE_AUTHOR("zhu jianlinag <zhu.jianliang@zte.com.cn>");
diff --git a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
new file mode 100755
index 0000000..750580b
--- /dev/null
+++ b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
@@ -0,0 +1,298 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include "zx29_gmac.h"
+
+extern void v7_dma_map_area(const void *, size_t, int);
+extern unsigned long virt_to_phys_ap(unsigned long virt);
+
+void dma_map(const void * addr, size_t len, int flags)
+{
+ v7_dma_map_area(addr, len, flags);
+}
+EXPORT_SYMBOL(dma_map);
+
+unsigned long virt_to_phys_ap_new(unsigned long virt_addr)
+{
+ return virt_to_phys_ap(virt_addr);
+}
+EXPORT_SYMBOL(virt_to_phys_ap_new);
+
+int debug_on = 0;
+EXPORT_SYMBOL(debug_on);
+
+struct kset *kset_gmac;
+struct kobject *gmackobj = NULL;
+struct kobject *typekobj = NULL;
+char type[8] = { 0 };
+u32 zx29_gmac_plug_state[3] = {0}; /* 0:phy 1:sw_wan 2:sw_lan */
+
+static struct attribute gmac_phy_plug_attr = {
+ .name = "eth_phy_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_wan_plug_attr = {
+ .name = "eth_sw_wan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_lan_plug_attr = {
+ .name = "eth_sw_lan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute board_type = {
+ .name = "type",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute *gmac_status_attrs[] = {
+ &gmac_phy_plug_attr,
+ &gmac_sw_wan_plug_attr,
+ &gmac_sw_lan_plug_attr,
+ &board_type,
+ NULL,
+};
+
+ssize_t kobj_gmac_show(struct kobject *kobject,struct attribute *attr,char *buf)
+{
+ unsigned link =0;
+
+ if(!strcmp(attr->name,"eth_phy_state")) {
+ if(zx29_gmac_plug_state[0] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_wan_state")) {
+ if(zx29_gmac_plug_state[1] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_lan_state")) {
+ if(zx29_gmac_plug_state[2] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if (!strcmp(attr->name,"type")) {
+ sprintf(buf, "%s", type);
+ } else {
+ printk("invalidate attr name.\n");
+ }
+
+ return strlen(buf);
+}
+
+ssize_t kobj_gmac_store(struct kobject *kobject, struct attribute *attr, const char *buf, size_t size)
+{
+ unsigned int value = 0;
+ value = simple_strtoul(buf, NULL, 4);
+ printk("attrname: %s.\n", attr->name);
+ if (!strcmp(attr->name, "eth_phy_state")) {
+ zx29_gmac_plug_state[0] = value;
+ } else if (!strcmp(attr->name,"eth_sw_wan_state")) {
+ zx29_gmac_plug_state[1] = value;
+ } else if (!strcmp(attr->name,"eth_sw_lan_state")) {
+ zx29_gmac_plug_state[2] = value;
+ } else {
+ printk("invalidate attr name.\n");
+ }
+ return size;
+}
+
+static struct sysfs_ops obj_gmac_sysops = {
+ .show = kobj_gmac_show,
+ .store = kobj_gmac_store,
+};
+
+static void kobj_gmac_release(struct kobject *kobject)
+{
+ printk("[gmac kobj_test: release!]\n");
+}
+
+static void kobj_type_release(struct kobject *kobject)
+{
+ printk("[type kobj_test: release!]\n");
+}
+
+
+void kobj_gmac_del(struct kobject *kobject)
+{
+ kset_unregister(kset_gmac);
+
+ kobject_uevent(typekobj, KOBJ_REMOVE);
+ kobject_del(typekobj);
+ kobject_put(typekobj);
+ kfree(typekobj);
+
+ kobject_uevent(gmackobj, KOBJ_REMOVE);
+ kobject_del(gmackobj);
+ kobject_put(gmackobj);
+
+ kfree(gmackobj);
+
+ printk("[gmac kobj_test: delete!]\n");
+}
+EXPORT_SYMBOL(kobj_gmac_del);
+
+static struct kobj_type gmacktype =
+{ .release = kobj_gmac_release,
+ .sysfs_ops = &obj_gmac_sysops,
+ .default_attrs = gmac_status_attrs,
+};
+
+static struct kobj_type typektype =
+{ .release = kobj_type_release,
+// .sysfs_ops = &obj_gmac_sysops,
+// .default_attrs = gmac_status_attrs,
+};
+
+
+static int kset_filter(struct kset *kset,struct kobject *kobj)
+{
+ printk("kset Filter: kobj %s.\n",kobj->name);
+ return 1;
+}
+
+static const char *kset_name(struct kset *kset,struct kobject *kobj)
+{
+ static char buf[20];
+ printk("Name: kobj %s.\n",kobj->name);
+ sprintf(buf,"%s","gmac");
+ return buf;
+}
+
+static int kset_uevent(struct kset *kset, struct kobject *kobj, struct kobj_uevent_env *env)
+{
+ int i = 0;
+ printk("uevent: kobj %s.\n",kobj->name);
+ while (i < env->envp_idx) {
+ printk("%s.\n",env->envp[i]);
+ i++;
+ }
+
+ return 0;
+}
+
+static struct kset_uevent_ops gmac_uevent_ops =
+{
+ .filter = kset_filter,
+ .name = kset_name,
+ .uevent = kset_uevent,
+};
+
+void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void *puf)
+{
+ int rtv = -1;
+ enum kobject_action action = KOBJ_UNBIND;
+ char *envp_phy_ext[] = {"GMACEVENT=gmac_eth_phy",NULL};
+ char *envp_sw_wan_ext[] = {"GMACEVENT=gmac_eth_sw_wan",NULL};
+ char *envp_sw_lan_ext[] = {"GMACEVENT=gmac_eth_sw_lan",NULL};
+
+ switch (notify_type) {
+ case GMAC_ETH_PHY_PLUGIN:
+ printk("gmac eth phy plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[0] = 1;
+ if (gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action, envp_phy_ext);
+ break;
+
+ case GMAC_ETH_PHY_PLUGOUT:
+ printk("gmac eth phy plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[0] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_phy_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGIN:
+ printk("gmac eth switch wan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[1] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGOUT:
+ printk("gmac eth switch wan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[1] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGIN:
+ printk("gmac eth switch lan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[2] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGOUT:
+ printk("gmac eth switch lan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[2] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ default:
+ printk(KERN_WARNING "UNKWON GMAC EVENT \n");
+ break;
+ }
+
+ printk(KERN_WARNING "rtv:%d \n",rtv);
+}
+
+EXPORT_SYMBOL(gmac_event_notify);
+
+int gmac_event_init(const char *name)
+{
+ int ret = 0;
+ /* 创建并注册 kset_p */
+ gmackobj = kzalloc(sizeof(*gmackobj),GFP_KERNEL);
+ if(!gmackobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+ kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(gmackobj, &gmacktype);
+ kobject_add(gmackobj,&kset_gmac->kobj,"%s","gmacconfig");
+ gmackobj->kset = kset_gmac;
+
+ typekobj = kzalloc(sizeof(*typekobj),GFP_KERNEL);
+ if(!typekobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+// kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(typekobj, &typektype);
+ kobject_add(typekobj,&kset_gmac->kobj,"%s",name);
+ typekobj->kset = kset_gmac;
+
+ strcpy(type, name);
+
+ return ret;
+}
+EXPORT_SYMBOL(gmac_event_init);
diff --git a/upstream/linux-5.10/drivers/net/phy/phy_device.c b/upstream/linux-5.10/drivers/net/phy/phy_device.c
new file mode 100755
index 0000000..d9b53ba
--- /dev/null
+++ b/upstream/linux-5.10/drivers/net/phy/phy_device.c
@@ -0,0 +1,3113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Framework for finding and configuring PHYs.
+ * Also contains generic PHY driver
+ *
+ * Author: Andy Fleming
+ *
+ * Copyright (c) 2004 Freescale Semiconductor, Inc.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/bitmap.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mdio.h>
+#include <linux/mii.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/phy_led_triggers.h>
+#include <linux/property.h>
+#include <linux/sfp.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+
+MODULE_DESCRIPTION("PHY library");
+MODULE_AUTHOR("Andy Fleming");
+MODULE_LICENSE("GPL");
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_t1_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_fibre_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_all_ports_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_fec_features);
+
+const int phy_basic_ports_array[3] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_ports_array);
+
+const int phy_fibre_port_array[1] = {
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_fibre_port_array);
+
+const int phy_all_ports_features_array[7] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+ ETHTOOL_LINK_MODE_AUI_BIT,
+ ETHTOOL_LINK_MODE_BNC_BIT,
+ ETHTOOL_LINK_MODE_Backplane_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_all_ports_features_array);
+
+const int phy_10_100_features_array[4] = {
+ ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10_100_features_array);
+
+const int phy_basic_t1_features_array[2] = {
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);
+
+const int phy_gbit_features_array[2] = {
+ ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_gbit_features_array);
+
+const int phy_10gbit_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10gbit_features_array);
+
+static const int phy_10gbit_fec_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
+};
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_full_features);
+
+static const int phy_10gbit_full_features_array[] = {
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+
+//status = phy_read_cl(phydev, MII_BMSR);
+static int phy_read_cl(struct phy_device *phydev, u32 regnum)
+{
+ int val = 0;
+
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 1);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0e, regnum);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 0x4000 | 1);
+ val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 0x0e);
+
+ return val;
+}
+
+static void features_init(void)
+{
+ /* 10/100 half/full*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_basic_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_basic_features);
+
+ /* 100 full, TP */
+ linkmode_set_bit_array(phy_basic_t1_features_array,
+ ARRAY_SIZE(phy_basic_t1_features_array),
+ phy_basic_t1_features);
+
+ /* 10/100 half/full + 1000 half/full */
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_features);
+
+ /* 10/100 half/full + 1000 half/full + fibre*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_fibre_port_array,
+ ARRAY_SIZE(phy_fibre_port_array),
+ phy_gbit_fibre_features);
+
+ /* 10/100 half/full + 1000 half/full + TP/MII/FIBRE/AUI/BNC/Backplane*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_all_ports_features);
+
+ /* 10/100 half/full + 1000 half/full + 10G full*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10gbit_features_array,
+ ARRAY_SIZE(phy_10gbit_features_array),
+ phy_10gbit_features);
+
+ /* 10/100/1000/10G full */
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_full_features);
+ linkmode_set_bit_array(phy_10gbit_full_features_array,
+ ARRAY_SIZE(phy_10gbit_full_features_array),
+ phy_10gbit_full_features);
+ /* 10G FEC only */
+ linkmode_set_bit_array(phy_10gbit_fec_features_array,
+ ARRAY_SIZE(phy_10gbit_fec_features_array),
+ phy_10gbit_fec_features);
+}
+
+void phy_device_free(struct phy_device *phydev)
+{
+ put_device(&phydev->mdio.dev);
+}
+EXPORT_SYMBOL(phy_device_free);
+
+static void phy_mdio_device_free(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_free(phydev);
+}
+
+static void phy_device_release(struct device *dev)
+{
+ kfree(to_phy_device(dev));
+}
+
+static void phy_mdio_device_remove(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_remove(phydev);
+}
+
+static struct phy_driver genphy_driver;
+
+static LIST_HEAD(phy_fixup_list);
+static DEFINE_MUTEX(phy_fixup_lock);
+
+static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
+{
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (!drv || !phydrv->suspend)
+ return false;
+
+ /* PHY not attached? May suspend if the PHY has not already been
+ * suspended as part of a prior call to phy_disconnect() ->
+ * phy_detach() -> phy_suspend() because the parent netdev might be the
+ * MDIO bus driver and clock gated at this point.
+ */
+ if (!netdev)
+ goto out;
+
+ if (netdev->wol_enabled)
+ return false;
+
+ /* As long as not all affected network drivers support the
+ * wol_enabled flag, let's check for hints that WoL is enabled.
+ * Don't suspend PHY if the attached netdev parent may wake up.
+ * The parent may point to a PCI device, as in tg3 driver.
+ */
+ if (netdev->dev.parent && device_may_wakeup(netdev->dev.parent))
+ return false;
+
+ /* Also don't suspend PHY if the netdev itself may wakeup. This
+ * is the case for devices w/o underlaying pwr. mgmt. aware bus,
+ * e.g. SoC devices.
+ */
+ if (device_may_wakeup(&netdev->dev))
+ return false;
+
+out:
+ return !phydev->suspended;
+}
+
+static __maybe_unused int mdio_bus_phy_suspend(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ /* We must stop the state machine manually, otherwise it stops out of
+ * control, possibly with the phydev->lock held. Upon resume, netdev
+ * may call phy routines that try to grab the same lock, and that may
+ * lead to a deadlock.
+ */
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_stop_machine(phydev);
+
+ if (!mdio_bus_phy_may_suspend(phydev))
+ return 0;
+
+ phydev->suspended_by_mdio_bus = 1;
+
+ return phy_suspend(phydev);
+}
+
+static __maybe_unused int mdio_bus_phy_resume(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ int ret;
+
+ if (!phydev->suspended_by_mdio_bus)
+ goto no_resume;
+
+ phydev->suspended_by_mdio_bus = 0;
+
+ ret = phy_init_hw(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_resume(phydev);
+ if (ret < 0)
+ return ret;
+no_resume:
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_start_machine(phydev);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mdio_bus_phy_pm_ops, mdio_bus_phy_suspend,
+ mdio_bus_phy_resume);
+
+/**
+ * phy_register_fixup - creates a new phy_fixup and adds it to the list
+ * @bus_id: A string which matches phydev->mdio.dev.bus_id (or PHY_ANY_ID)
+ * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
+ * It can also be PHY_ANY_UID
+ * @phy_uid_mask: Applied to phydev->phy_id and fixup->phy_uid before
+ * comparison
+ * @run: The actual code to be run when a matching PHY is found
+ */
+int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ struct phy_fixup *fixup = kzalloc(sizeof(*fixup), GFP_KERNEL);
+
+ if (!fixup)
+ return -ENOMEM;
+
+ strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id));
+ fixup->phy_uid = phy_uid;
+ fixup->phy_uid_mask = phy_uid_mask;
+ fixup->run = run;
+
+ mutex_lock(&phy_fixup_lock);
+ list_add_tail(&fixup->list, &phy_fixup_list);
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_register_fixup);
+
+/* Registers a fixup to be run on any PHY with the UID in phy_uid */
+int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_uid);
+
+/* Registers a fixup to be run on the PHY with id string bus_id */
+int phy_register_fixup_for_id(const char *bus_id,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_id);
+
+/**
+ * phy_unregister_fixup - remove a phy_fixup from the list
+ * @bus_id: A string matches fixup->bus_id (or PHY_ANY_ID) in phy_fixup_list
+ * @phy_uid: A phy id matches fixup->phy_id (or PHY_ANY_UID) in phy_fixup_list
+ * @phy_uid_mask: Applied to phy_uid and fixup->phy_uid before comparison
+ */
+int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask)
+{
+ struct list_head *pos, *n;
+ struct phy_fixup *fixup;
+ int ret;
+
+ ret = -ENODEV;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_safe(pos, n, &phy_fixup_list) {
+ fixup = list_entry(pos, struct phy_fixup, list);
+
+ if ((!strcmp(fixup->bus_id, bus_id)) &&
+ ((fixup->phy_uid & phy_uid_mask) ==
+ (phy_uid & phy_uid_mask))) {
+ list_del(&fixup->list);
+ kfree(fixup);
+ ret = 0;
+ break;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_unregister_fixup);
+
+/* Unregisters a fixup of any PHY with the UID in phy_uid */
+int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask)
+{
+ return phy_unregister_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_uid);
+
+/* Unregisters a fixup of the PHY with id string bus_id */
+int phy_unregister_fixup_for_id(const char *bus_id)
+{
+ return phy_unregister_fixup(bus_id, PHY_ANY_UID, 0xffffffff);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_id);
+
+/* Returns 1 if fixup matches phydev in bus_id and phy_uid.
+ * Fixups can be set to match any in one or more fields.
+ */
+static int phy_needs_fixup(struct phy_device *phydev, struct phy_fixup *fixup)
+{
+ if (strcmp(fixup->bus_id, phydev_name(phydev)) != 0)
+ if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ return 0;
+
+ if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+ (phydev->phy_id & fixup->phy_uid_mask))
+ if (fixup->phy_uid != PHY_ANY_UID)
+ return 0;
+
+ return 1;
+}
+
+/* Runs any matching fixups for this phydev */
+static int phy_scan_fixups(struct phy_device *phydev)
+{
+ struct phy_fixup *fixup;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_entry(fixup, &phy_fixup_list, list) {
+ if (phy_needs_fixup(phydev, fixup)) {
+ int err = fixup->run(phydev);
+
+ if (err < 0) {
+ mutex_unlock(&phy_fixup_lock);
+ return err;
+ }
+ phydev->has_fixups = true;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+
+static int phy_bus_match(struct device *dev, struct device_driver *drv)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
+ int i;
+
+ if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
+ return 0;
+
+ if (phydrv->match_phy_device)
+ return phydrv->match_phy_device(phydev);
+
+ if (phydev->is_c45) {
+ for (i = 1; i < num_ids; i++) {
+ if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ continue;
+
+ if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->c45_ids.device_ids[i] &
+ phydrv->phy_id_mask))
+ return 1;
+ }
+ return 0;
+ } else {
+ return (phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->phy_id & phydrv->phy_id_mask);
+ }
+}
+
+static ssize_t
+phy_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "0x%.8lx\n", (unsigned long)phydev->phy_id);
+}
+static DEVICE_ATTR_RO(phy_id);
+
+static ssize_t
+phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ const char *mode = NULL;
+
+ if (phy_is_internal(phydev))
+ mode = "internal";
+ else
+ mode = phy_modes(phydev->interface);
+
+ return sprintf(buf, "%s\n", mode);
+}
+static DEVICE_ATTR_RO(phy_interface);
+
+static ssize_t
+phy_has_fixups_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", phydev->has_fixups);
+}
+static DEVICE_ATTR_RO(phy_has_fixups);
+
+static struct attribute *phy_dev_attrs[] = {
+ &dev_attr_phy_id.attr,
+ &dev_attr_phy_interface.attr,
+ &dev_attr_phy_has_fixups.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(phy_dev);
+
+static const struct device_type mdio_bus_phy_type = {
+ .name = "PHY",
+ .groups = phy_dev_groups,
+ .release = phy_device_release,
+ .pm = pm_ptr(&mdio_bus_phy_pm_ops),
+};
+
+static int phy_request_driver_module(struct phy_device *dev, u32 phy_id)
+{
+ int ret;
+
+ ret = request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT,
+ MDIO_ID_ARGS(phy_id));
+ /* We only check for failures in executing the usermode binary,
+ * not whether a PHY driver module exists for the PHY ID.
+ * Accept -ENOENT because this may occur in case no initramfs exists,
+ * then modprobe isn't available.
+ */
+ if (IS_ENABLED(CONFIG_MODULES) && ret < 0 && ret != -ENOENT) {
+ phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n",
+ ret, (unsigned long)phy_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
+ bool is_c45,
+ struct phy_c45_device_ids *c45_ids)
+{
+ struct phy_device *dev;
+ struct mdio_device *mdiodev;
+ int ret = 0;
+
+ /* We allocate the device, and initialize the default values */
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ mdiodev = &dev->mdio;
+ mdiodev->dev.parent = &bus->dev;
+ mdiodev->dev.bus = &mdio_bus_type;
+ mdiodev->dev.type = &mdio_bus_phy_type;
+ mdiodev->bus = bus;
+ mdiodev->bus_match = phy_bus_match;
+ mdiodev->addr = addr;
+ mdiodev->flags = MDIO_DEVICE_FLAG_PHY;
+ mdiodev->device_free = phy_mdio_device_free;
+ mdiodev->device_remove = phy_mdio_device_remove;
+
+ dev->speed = SPEED_UNKNOWN;
+ dev->duplex = DUPLEX_UNKNOWN;
+ dev->pause = 0;
+ dev->asym_pause = 0;
+ dev->link = 0;
+ dev->port = PORT_TP;
+ dev->interface = PHY_INTERFACE_MODE_GMII;
+
+ dev->autoneg = AUTONEG_ENABLE;
+
+ dev->is_c45 = is_c45;
+ dev->phy_id = phy_id;
+ if (c45_ids)
+ dev->c45_ids = *c45_ids;
+ dev->irq = bus->irq[addr];
+
+ dev_set_name(&mdiodev->dev, PHY_ID_FMT, bus->id, addr);
+ device_initialize(&mdiodev->dev);
+
+ dev->state = PHY_DOWN;
+
+ mutex_init(&dev->lock);
+ INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
+
+ /* Request the appropriate module unconditionally; don't
+ * bother trying to do so only if it isn't already loaded,
+ * because that gets complicated. A hotplug event would have
+ * done an unconditional modprobe anyway.
+ * We don't do normal hotplug because it won't work for MDIO
+ * -- because it relies on the device staying around for long
+ * enough for the driver to get loaded. With MDIO, the NIC
+ * driver will get bored and give up as soon as it finds that
+ * there's no driver _already_ loaded.
+ */
+ if (is_c45 && c45_ids) {
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ int i;
+
+ for (i = 1; i < num_ids; i++) {
+ if (c45_ids->device_ids[i] == 0xffffffff)
+ continue;
+
+ ret = phy_request_driver_module(dev,
+ c45_ids->device_ids[i]);
+ if (ret)
+ break;
+ }
+ } else {
+ ret = phy_request_driver_module(dev, phy_id);
+ }
+
+ if (ret) {
+ put_device(&mdiodev->dev);
+ dev = ERR_PTR(ret);
+ }
+
+ return dev;
+}
+EXPORT_SYMBOL(phy_device_create);
+
+/* phy_c45_probe_present - checks to see if a MMD is present in the package
+ * @bus: the target MII bus
+ * @prtad: PHY package address on the MII bus
+ * @devad: PHY device (MMD) address
+ *
+ * Read the MDIO_STAT2 register, and check whether a device is responding
+ * at this address.
+ *
+ * Returns: negative error number on bus access error, zero if no device
+ * is responding, or positive if a device is present.
+ */
+static int phy_c45_probe_present(struct mii_bus *bus, int prtad, int devad)
+{
+ int stat2;
+
+ stat2 = mdiobus_c45_read(bus, prtad, devad, MDIO_STAT2);
+ if (stat2 < 0)
+ return stat2;
+
+ return (stat2 & MDIO_STAT2_DEVPRST) == MDIO_STAT2_DEVPRST_VAL;
+}
+
+/* get_phy_c45_devs_in_pkg - reads a MMD's devices in package registers.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @dev_addr: MMD address in the PHY.
+ * @devices_in_package: where to store the devices in package information.
+ *
+ * Description: reads devices in package registers of a MMD at @dev_addr
+ * from PHY at @addr on @bus.
+ *
+ * Returns: 0 on success, -EIO on failure.
+ */
+static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr,
+ u32 *devices_in_package)
+{
+ int phy_reg;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package |= phy_reg;
+
+ return 0;
+}
+
+/**
+ * get_phy_c45_ids - reads the specified addr for its 802.3-c45 IDs.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @c45_ids: where to store the c45 ID information.
+ *
+ * Read the PHY "devices in package". If this appears to be valid, read
+ * the PHY identifiers for each device. Return the "devices in package"
+ * and identifiers in @c45_ids.
+ *
+ * Returns zero on success, %-EIO on bus access error, or %-ENODEV if
+ * the "devices in package" is invalid.
+ */
+static int get_phy_c45_ids(struct mii_bus *bus, int addr,
+ struct phy_c45_device_ids *c45_ids)
+{
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ u32 devs_in_pkg = 0;
+ int i, ret, phy_reg;
+
+ /* Find first non-zero Devices In package. Device zero is reserved
+ * for 802.3 c45 complied PHYs, so don't probe it at first.
+ */
+ for (i = 1; i < MDIO_MMD_NUM && (devs_in_pkg == 0 ||
+ (devs_in_pkg & 0x1fffffff) == 0x1fffffff); i++) {
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Check that there is a device present at this
+ * address before reading the devices-in-package
+ * register to avoid reading garbage from the PHY.
+ * Some PHYs (88x3310) vendor space is not IEEE802.3
+ * compliant.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return -EIO;
+
+ if (!ret)
+ continue;
+ }
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, i, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+ }
+
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff) {
+ /* If mostly Fs, there is no device there, then let's probe
+ * MMD 0, as some 10G PHYs have zero Devices In package,
+ * e.g. Cortina CS4315/CS4340 PHY.
+ */
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, 0, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+
+ /* no device there, let's get out of here */
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+ }
+
+ /* Now probe Device Identifiers for each device present. */
+ for (i = 1; i < num_ids; i++) {
+ if (!(devs_in_pkg & (1 << i)))
+ continue;
+
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Probe the "Device Present" bits for the vendor MMDs
+ * to ignore these if they do not contain IEEE 802.3
+ * registers.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return ret;
+
+ if (!ret)
+ continue;
+ }
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID1);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID2);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] |= phy_reg;
+ }
+
+ c45_ids->devices_in_package = devs_in_pkg;
+ /* Bit 0 doesn't represent a device, it indicates c22 regs presence */
+ c45_ids->mmds_present = devs_in_pkg & ~BIT(0);
+
+ return 0;
+}
+
+/**
+ * get_phy_c22_id - reads the specified addr for its clause 22 ID.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @phy_id: where to store the ID retrieved.
+ *
+ * Read the 802.3 clause 22 PHY ID from the PHY at @addr on the @bus,
+ * placing it in @phy_id. Return zero on successful read and the ID is
+ * valid, %-EIO on bus access error, or %-ENODEV if no device responds
+ * or invalid ID.
+ */
+static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id)
+{
+ int phy_reg;
+
+ /* Grab the bits from PHYIR1, and put them in the upper half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 2);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id = phy_reg << 16;
+
+ /* Grab the bits from PHYIR2, and put them in the lower half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#ifdef CONFIG_MDIO_C45
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 3);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id |= phy_reg;
+
+#ifdef CONFIG_MDIO_C45
+ printk("[%s] read with c45 phy id:0x%x\n", __func__, *phy_id);
+#else
+ printk("[%s] read with c22 phy id:0x%x\n", __func__, *phy_id);
+#endif
+ /* If the phy_id is mostly Fs, there is no device there */
+ if ((*phy_id & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+
+ return 0;
+}
+
+/**
+ * get_phy_device - reads the specified PHY device and returns its @phy_device
+ * struct
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @is_c45: If true the PHY uses the 802.3 clause 45 protocol
+ *
+ * Probe for a PHY at @addr on @bus.
+ *
+ * When probing for a clause 22 PHY, then read the ID registers. If we find
+ * a valid ID, allocate and return a &struct phy_device.
+ *
+ * When probing for a clause 45 PHY, read the "devices in package" registers.
+ * If the "devices in package" appears valid, read the ID registers for each
+ * MMD, allocate and return a &struct phy_device.
+ *
+ * Returns an allocated &struct phy_device on success, %-ENODEV if there is
+ * no PHY present, or %-EIO on bus access error.
+ */
+struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
+{
+ struct phy_c45_device_ids c45_ids;
+ u32 phy_id = 0;
+ int r;
+
+ c45_ids.devices_in_package = 0;
+ c45_ids.mmds_present = 0;
+ memset(c45_ids.device_ids, 0xff, sizeof(c45_ids.device_ids));
+
+ if (is_c45)
+ r = get_phy_c45_ids(bus, addr, &c45_ids);
+ else
+ r = get_phy_c22_id(bus, addr, &phy_id);
+
+ if (r)
+ return ERR_PTR(r);
+
+ return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids);
+}
+EXPORT_SYMBOL(get_phy_device);
+
+/**
+ * phy_device_register - Register the phy device on the MDIO bus
+ * @phydev: phy_device structure to be added to the MDIO bus
+ */
+int phy_device_register(struct phy_device *phydev)
+{
+ int err;
+
+ err = mdiobus_register_device(&phydev->mdio);
+ if (err)
+ return err;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ /* Run all of the fixups for this PHY */
+ err = phy_scan_fixups(phydev);
+ if (err) {
+ phydev_err(phydev, "failed to initialize\n");
+ goto out;
+ }
+
+ err = device_add(&phydev->mdio.dev);
+ if (err) {
+ phydev_err(phydev, "failed to add\n");
+ goto out;
+ }
+
+ return 0;
+
+ out:
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+ return err;
+}
+EXPORT_SYMBOL(phy_device_register);
+
+/**
+ * phy_device_remove - Remove a previously registered phy device from the MDIO bus
+ * @phydev: phy_device structure to remove
+ *
+ * This doesn't free the phy_device itself, it merely reverses the effects
+ * of phy_device_register(). Use phy_device_free() to free the device
+ * after calling this function.
+ */
+void phy_device_remove(struct phy_device *phydev)
+{
+ if (phydev->mii_ts)
+ unregister_mii_timestamper(phydev->mii_ts);
+
+ device_del(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+}
+EXPORT_SYMBOL(phy_device_remove);
+
+/**
+ * phy_find_first - finds the first PHY device on the bus
+ * @bus: the target MII bus
+ */
+struct phy_device *phy_find_first(struct mii_bus *bus)
+{
+ struct phy_device *phydev;
+ int addr;
+
+ for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+ phydev = mdiobus_get_phy(bus, addr);
+ if (phydev) {
+ printk("[%s] addr:%d\n", __func__, addr);
+ return phydev;
+ }
+ }
+ return NULL;
+}
+EXPORT_SYMBOL(phy_find_first);
+
+static void phy_link_change(struct phy_device *phydev, bool up)
+{
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (up)
+ netif_carrier_on(netdev);
+ else
+ netif_carrier_off(netdev);
+ phydev->adjust_link(netdev);
+ if (phydev->mii_ts && phydev->mii_ts->link_state)
+ phydev->mii_ts->link_state(phydev->mii_ts, phydev);
+}
+
+/**
+ * phy_prepare_link - prepares the PHY layer to monitor link status
+ * @phydev: target phy_device struct
+ * @handler: callback function for link status change notifications
+ *
+ * Description: Tells the PHY infrastructure to handle the
+ * gory details on monitoring link status (whether through
+ * polling or an interrupt), and to call back to the
+ * connected device driver when the link status changes.
+ * If you want to monitor your own link state, don't call
+ * this function.
+ */
+static void phy_prepare_link(struct phy_device *phydev,
+ void (*handler)(struct net_device *))
+{
+ phydev->adjust_link = handler;
+}
+
+/**
+ * phy_connect_direct - connect an ethernet device to a specific phy_device
+ * @dev: the network device to connect
+ * @phydev: the pointer to the phy device
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ */
+int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ int rc;
+
+ if (!dev)
+ return -EINVAL;
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ if (rc)
+ return rc;
+
+ phy_prepare_link(phydev, handler);
+ if (phy_interrupt_is_valid(phydev))
+ phy_request_interrupt(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_connect_direct);
+
+/**
+ * phy_connect - connect an ethernet device to a PHY device
+ * @dev: the network device to connect
+ * @bus_id: the id string of the PHY device to connect
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ *
+ * Description: Convenience function for connecting ethernet
+ * devices to PHY devices. The default behavior is for
+ * the PHY infrastructure to handle everything, and only notify
+ * the connected driver when the link status changes. If you
+ * don't want, or can't use the provided functionality, you may
+ * choose to call only the subset of functions which provide
+ * the desired functionality.
+ */
+struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(&mdio_bus_type, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_connect_direct(dev, phydev, handler, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_connect);
+
+/**
+ * phy_disconnect - disable interrupts, stop state machine, and detach a PHY
+ * device
+ * @phydev: target phy_device struct
+ */
+void phy_disconnect(struct phy_device *phydev)
+{
+ if (phy_is_started(phydev))
+ phy_stop(phydev);
+
+ if (phy_interrupt_is_valid(phydev))
+ phy_free_interrupt(phydev);
+
+ phydev->adjust_link = NULL;
+
+ phy_detach(phydev);
+}
+EXPORT_SYMBOL(phy_disconnect);
+
+/**
+ * phy_poll_reset - Safely wait until a PHY reset has properly completed
+ * @phydev: The PHY device to poll
+ *
+ * Description: According to IEEE 802.3, Section 2, Subsection 22.2.4.1.1, as
+ * published in 2008, a PHY reset may take up to 0.5 seconds. The MII BMCR
+ * register must be polled until the BMCR_RESET bit clears.
+ *
+ * Furthermore, any attempts to write to PHY registers may have no effect
+ * or even generate MDIO bus errors until this is complete.
+ *
+ * Some PHYs (such as the Marvell 88E1111) don't entirely conform to the
+ * standard and do not fully reset after the BMCR_RESET bit is set, and may
+ * even *REQUIRE* a soft-reset to properly restart autonegotiation. In an
+ * effort to support such broken PHYs, this function is separate from the
+ * standard phy_init_hw() which will zero all the other bits in the BMCR
+ * and reapply all driver-specific and board-specific fixups.
+ */
+static int phy_poll_reset(struct phy_device *phydev)
+{
+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
+ int ret, val;
+
+ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+ 50000, 600000, true);
+ if (ret)
+ return ret;
+ /* Some chips (smsc911x) may still need up to another 1ms after the
+ * BMCR_RESET bit is cleared before they are usable.
+ */
+ msleep(1);
+ return 0;
+}
+
+int phy_init_hw(struct phy_device *phydev)
+{
+ int ret = 0;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (!phydev->drv)
+ return 0;
+
+ if (phydev->drv->soft_reset) {
+ ret = phydev->drv->soft_reset(phydev);
+ /* see comment in genphy_soft_reset for an explanation */
+ if (!ret)
+ phydev->suspended = 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ ret = phy_scan_fixups(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->drv->config_init) {
+ ret = phydev->drv->config_init(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (phydev->drv->config_intr) {
+ ret = phydev->drv->config_intr(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_init_hw);
+
+void phy_attached_info(struct phy_device *phydev)
+{
+ phy_attached_print(phydev, NULL);
+}
+EXPORT_SYMBOL(phy_attached_info);
+
+#define ATTACHED_FMT "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%s)"
+char *phy_attached_info_irq(struct phy_device *phydev)
+{
+ char *irq_str;
+ char irq_num[8];
+
+ switch(phydev->irq) {
+ case PHY_POLL:
+ irq_str = "POLL";
+ break;
+ case PHY_IGNORE_INTERRUPT:
+ irq_str = "IGNORE";
+ break;
+ default:
+ snprintf(irq_num, sizeof(irq_num), "%d", phydev->irq);
+ irq_str = irq_num;
+ break;
+ }
+
+ return kasprintf(GFP_KERNEL, "%s", irq_str);
+}
+EXPORT_SYMBOL(phy_attached_info_irq);
+
+void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
+{
+ const char *drv_name = phydev->drv ? phydev->drv->name : "unbound";
+ char *irq_str = phy_attached_info_irq(phydev);
+
+ if (!fmt) {
+ phydev_info(phydev, ATTACHED_FMT "\n",
+ drv_name, phydev_name(phydev),
+ irq_str);
+ } else {
+ va_list ap;
+
+ phydev_info(phydev, ATTACHED_FMT,
+ drv_name, phydev_name(phydev),
+ irq_str);
+
+ va_start(ap, fmt);
+ vprintk(fmt, ap);
+ va_end(ap);
+ }
+ kfree(irq_str);
+}
+EXPORT_SYMBOL(phy_attached_print);
+
+static void phy_sysfs_create_links(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ int err;
+
+ if (!dev)
+ return;
+
+ err = sysfs_create_link(&phydev->mdio.dev.kobj, &dev->dev.kobj,
+ "attached_dev");
+ if (err)
+ return;
+
+ err = sysfs_create_link_nowarn(&dev->dev.kobj,
+ &phydev->mdio.dev.kobj,
+ "phydev");
+ if (err) {
+ dev_err(&dev->dev, "could not add device link to %s err %d\n",
+ kobject_name(&phydev->mdio.dev.kobj),
+ err);
+ /* non-fatal - some net drivers can use one netdevice
+ * with more then one phy
+ */
+ }
+
+ phydev->sysfs_links = true;
+}
+
+static ssize_t
+phy_standalone_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", !phydev->attached_dev);
+}
+static DEVICE_ATTR_RO(phy_standalone);
+
+/**
+ * phy_sfp_attach - attach the SFP bus to the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .attach member.
+ */
+void phy_sfp_attach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = bus;
+ phydev->sfp_bus_attached = true;
+}
+EXPORT_SYMBOL(phy_sfp_attach);
+
+/**
+ * phy_sfp_detach - detach the SFP bus from the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .detach member.
+ */
+void phy_sfp_detach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = NULL;
+ phydev->sfp_bus_attached = false;
+}
+EXPORT_SYMBOL(phy_sfp_detach);
+
+/**
+ * phy_sfp_probe - probe for a SFP cage attached to this PHY device
+ * @phydev: Pointer to phy_device
+ * @ops: SFP's upstream operations
+ */
+int phy_sfp_probe(struct phy_device *phydev,
+ const struct sfp_upstream_ops *ops)
+{
+ struct sfp_bus *bus;
+ int ret = 0;
+
+ if (phydev->mdio.dev.fwnode) {
+ bus = sfp_bus_find_fwnode(phydev->mdio.dev.fwnode);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ phydev->sfp_bus = bus;
+
+ ret = sfp_bus_add_upstream(bus, phydev, ops);
+ sfp_bus_put(bus);
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_sfp_probe);
+
+/**
+ * phy_attach_direct - attach a network device to a given PHY device pointer
+ * @dev: network device to attach
+ * @phydev: Pointer to phy_device to attach
+ * @flags: PHY device's dev_flags
+ * @interface: PHY device's interface
+ *
+ * Description: Called by drivers to attach to a particular PHY
+ * device. The phy_device is found, and properly hooked up
+ * to the phy_driver. If no driver is attached, then a
+ * generic driver is used. The phy_device is given a ptr to
+ * the attaching device, and given a callback for link status
+ * change. The phy_device is returned to the attaching driver.
+ * This function takes a reference on the phy device.
+ */
+int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
+ u32 flags, phy_interface_t interface)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct device *d = &phydev->mdio.dev;
+ struct module *ndev_owner = NULL;
+ bool using_genphy = false;
+ int err;
+
+ /* For Ethernet device drivers that register their own MDIO bus, we
+ * will have bus->owner match ndev_mod, so we do not want to increment
+ * our own module->refcnt here, otherwise we would not be able to
+ * unload later on.
+ */
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner && !try_module_get(bus->owner)) {
+ phydev_err(phydev, "failed to get the bus module\n");
+ return -EIO;
+ }
+
+ get_device(d);
+
+ /* Assume that if there is no driver, that it doesn't
+ * exist, and we should use the genphy driver.
+ */
+ if (!d->driver) {
+ if (phydev->is_c45)
+ d->driver = &genphy_c45_driver.mdiodrv.driver;
+ else
+ d->driver = &genphy_driver.mdiodrv.driver;
+
+ using_genphy = true;
+ }
+
+ if (!try_module_get(d->driver->owner)) {
+ phydev_err(phydev, "failed to get the device driver module\n");
+ err = -EIO;
+ goto error_put_device;
+ }
+
+ if (using_genphy) {
+ err = d->driver->probe(d);
+ if (err >= 0)
+ err = device_bind_driver(d);
+
+ if (err)
+ goto error_module_put;
+ }
+
+ if (phydev->attached_dev) {
+ dev_err(&dev->dev, "PHY already attached\n");
+ err = -EBUSY;
+ goto error;
+ }
+
+ phydev->phy_link_change = phy_link_change;
+ if (dev) {
+ phydev->attached_dev = dev;
+ dev->phydev = phydev;
+
+ if (phydev->sfp_bus_attached)
+ dev->sfp_bus = phydev->sfp_bus;
+ }
+
+ /* Some Ethernet drivers try to connect to a PHY device before
+ * calling register_netdevice() -> netdev_register_kobject() and
+ * does the dev->dev.kobj initialization. Here we only check for
+ * success which indicates that the network device kobject is
+ * ready. Once we do that we still need to keep track of whether
+ * links were successfully set up or not for phy_detach() to
+ * remove them accordingly.
+ */
+ phydev->sysfs_links = false;
+
+ phy_sysfs_create_links(phydev);
+
+ if (!phydev->attached_dev) {
+ err = sysfs_create_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+ if (err)
+ phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n");
+ }
+
+ phydev->dev_flags |= flags;
+
+ phydev->interface = interface;
+
+ phydev->state = PHY_READY;
+
+ /* Port is set to PORT_TP by default and the actual PHY driver will set
+ * it to different value depending on the PHY configuration. If we have
+ * the generic PHY driver we can't figure it out, thus set the old
+ * legacy PORT_MII value.
+ */
+ if (using_genphy)
+ phydev->port = PORT_MII;
+
+ /* Initial carrier state is off as the phy is about to be
+ * (re)initialized.
+ */
+ if (dev)
+ netif_carrier_off(phydev->attached_dev);
+
+ /* Do initial configuration here, now that
+ * we have certain key parameters
+ * (dev_flags and interface)
+ */
+ err = phy_init_hw(phydev);
+ if (err)
+ goto error;
+
+ err = phy_disable_interrupts(phydev);
+ if (err)
+ return err;
+
+ phy_resume(phydev);
+ phy_led_triggers_register(phydev);
+
+ return err;
+
+error:
+ /* phy_detach() does all of the cleanup below */
+ phy_detach(phydev);
+ return err;
+
+error_module_put:
+ module_put(d->driver->owner);
+error_put_device:
+ put_device(d);
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+ return err;
+}
+EXPORT_SYMBOL(phy_attach_direct);
+
+/**
+ * phy_attach - attach a network device to a particular PHY device
+ * @dev: network device to attach
+ * @bus_id: Bus ID of PHY device to attach
+ * @interface: PHY device's interface
+ *
+ * Description: Same as phy_attach_direct() except that a PHY bus_id
+ * string is passed instead of a pointer to a struct phy_device.
+ */
+struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
+ phy_interface_t interface)
+{
+ struct bus_type *bus = &mdio_bus_type;
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(bus, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_attach);
+
+static bool phy_driver_is_genphy_kind(struct phy_device *phydev,
+ struct device_driver *driver)
+{
+ struct device *d = &phydev->mdio.dev;
+ bool ret = false;
+
+ if (!phydev->drv)
+ return ret;
+
+ get_device(d);
+ ret = d->driver == driver;
+ put_device(d);
+
+ return ret;
+}
+
+bool phy_driver_is_genphy(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
+
+bool phy_driver_is_genphy_10g(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_c45_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
+
+/**
+ * phy_package_join - join a common PHY group
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * This joins a PHY group and provides a shared storage for all phydevs in
+ * this group. This is intended to be used for packages which contain
+ * more than one PHY, for example a quad PHY transceiver.
+ *
+ * The addr parameter serves as a cookie which has to have the same value
+ * for all members of one group and as a PHY address to access generic
+ * registers of a PHY package. Usually, one of the PHY addresses of the
+ * different PHYs in the package provides access to these global registers.
+ * The address which is given here, will be used in the phy_package_read()
+ * and phy_package_write() convenience functions. If your PHY doesn't have
+ * global registers you can just pick any of the PHY addresses.
+ *
+ * This will set the shared pointer of the phydev to the shared storage.
+ * If this is the first call for a this cookie the shared storage will be
+ * allocated. If priv_size is non-zero, the given amount of bytes are
+ * allocated for the priv member.
+ *
+ * Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
+ * with the same cookie but a different priv_size is an error.
+ */
+int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct phy_package_shared *shared;
+ int ret;
+
+ if (addr < 0 || addr >= PHY_MAX_ADDR)
+ return -EINVAL;
+
+ mutex_lock(&bus->shared_lock);
+ shared = bus->shared[addr];
+ if (!shared) {
+ ret = -ENOMEM;
+ shared = kzalloc(sizeof(*shared), GFP_KERNEL);
+ if (!shared)
+ goto err_unlock;
+ if (priv_size) {
+ shared->priv = kzalloc(priv_size, GFP_KERNEL);
+ if (!shared->priv)
+ goto err_free;
+ shared->priv_size = priv_size;
+ }
+ shared->addr = addr;
+ refcount_set(&shared->refcnt, 1);
+ bus->shared[addr] = shared;
+ } else {
+ ret = -EINVAL;
+ if (priv_size && priv_size != shared->priv_size)
+ goto err_unlock;
+ refcount_inc(&shared->refcnt);
+ }
+ mutex_unlock(&bus->shared_lock);
+
+ phydev->shared = shared;
+
+ return 0;
+
+err_free:
+ kfree(shared);
+err_unlock:
+ mutex_unlock(&bus->shared_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_package_join);
+
+/**
+ * phy_package_leave - leave a common PHY group
+ * @phydev: target phy_device struct
+ *
+ * This leaves a PHY group created by phy_package_join(). If this phydev
+ * was the last user of the shared data between the group, this data is
+ * freed. Resets the phydev->shared pointer to NULL.
+ */
+void phy_package_leave(struct phy_device *phydev)
+{
+ struct phy_package_shared *shared = phydev->shared;
+ struct mii_bus *bus = phydev->mdio.bus;
+
+ if (!shared)
+ return;
+
+ if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+ bus->shared[shared->addr] = NULL;
+ mutex_unlock(&bus->shared_lock);
+ kfree(shared->priv);
+ kfree(shared);
+ }
+
+ phydev->shared = NULL;
+}
+EXPORT_SYMBOL_GPL(phy_package_leave);
+
+static void devm_phy_package_leave(struct device *dev, void *res)
+{
+ phy_package_leave(*(struct phy_device **)res);
+}
+
+/**
+ * devm_phy_package_join - resource managed phy_package_join()
+ * @dev: device that is registering this PHY package
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * Managed phy_package_join(). Shared storage fetched by this function,
+ * phy_package_leave() is automatically called on driver detach. See
+ * phy_package_join() for more information.
+ */
+int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+ int addr, size_t priv_size)
+{
+ struct phy_device **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_phy_package_leave, sizeof(*ptr),
+ GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = phy_package_join(phydev, addr, priv_size);
+
+ if (!ret) {
+ *ptr = phydev;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_phy_package_join);
+
+/**
+ * phy_detach - detach a PHY device from its network device
+ * @phydev: target phy_device struct
+ *
+ * This detaches the phy device from its network device and the phy
+ * driver, and drops the reference count taken in phy_attach_direct().
+ */
+void phy_detach(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ struct module *ndev_owner = NULL;
+ struct mii_bus *bus;
+
+ if (phydev->sysfs_links) {
+ if (dev)
+ sysfs_remove_link(&dev->dev.kobj, "phydev");
+ sysfs_remove_link(&phydev->mdio.dev.kobj, "attached_dev");
+ }
+
+ if (!phydev->attached_dev)
+ sysfs_remove_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+
+ phy_suspend(phydev);
+ if (dev) {
+ phydev->attached_dev->phydev = NULL;
+ phydev->attached_dev = NULL;
+ }
+ phydev->phylink = NULL;
+
+ phy_led_triggers_unregister(phydev);
+
+ if (phydev->mdio.dev.driver)
+ module_put(phydev->mdio.dev.driver->owner);
+
+ /* If the device had no specific driver before (i.e. - it
+ * was using the generic driver), we unbind the device
+ * from the generic driver so that there's a chance a
+ * real driver could be loaded
+ */
+ if (phy_driver_is_genphy(phydev) ||
+ phy_driver_is_genphy_10g(phydev))
+ device_release_driver(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ /*
+ * The phydev might go away on the put_device() below, so avoid
+ * a use-after-free bug by reading the underlying bus first.
+ */
+ bus = phydev->mdio.bus;
+
+ put_device(&phydev->mdio.dev);
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+}
+EXPORT_SYMBOL(phy_detach);
+
+int phy_suspend(struct phy_device *phydev)
+{
+ struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
+ struct net_device *netdev = phydev->attached_dev;
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ if (phydev->suspended)
+ return 0;
+
+ /* If the device has WOL enabled, we cannot suspend the PHY */
+ phy_ethtool_get_wol(phydev, &wol);
+ if (wol.wolopts || (netdev && netdev->wol_enabled))
+ return -EBUSY;
+
+ if (!phydrv || !phydrv->suspend)
+ return 0;
+
+ ret = phydrv->suspend(phydev);
+ if (!ret)
+ phydev->suspended = true;
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_suspend);
+
+int __phy_resume(struct phy_device *phydev)
+{
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ WARN_ON(!mutex_is_locked(&phydev->lock));
+
+ if (!phydrv || !phydrv->resume)
+ return 0;
+
+ ret = phydrv->resume(phydev);
+ if (!ret)
+ phydev->suspended = false;
+
+ return ret;
+}
+EXPORT_SYMBOL(__phy_resume);
+
+int phy_resume(struct phy_device *phydev)
+{
+ int ret;
+
+ mutex_lock(&phydev->lock);
+ ret = __phy_resume(phydev);
+ mutex_unlock(&phydev->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_resume);
+
+int phy_loopback(struct phy_device *phydev, bool enable)
+{
+ struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver);
+ int ret = 0;
+
+ mutex_lock(&phydev->lock);
+
+ if (enable && phydev->loopback_enabled) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ if (!enable && !phydev->loopback_enabled) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (phydev->drv && phydrv->set_loopback)
+ ret = phydrv->set_loopback(phydev, enable);
+ else
+ ret = -EOPNOTSUPP;
+
+ if (ret)
+ goto out;
+
+ phydev->loopback_enabled = enable;
+
+out:
+ mutex_unlock(&phydev->lock);
+ return ret;
+}
+EXPORT_SYMBOL(phy_loopback);
+
+/**
+ * phy_reset_after_clk_enable - perform a PHY reset if needed
+ * @phydev: target phy_device struct
+ *
+ * Description: Some PHYs are known to need a reset after their refclk was
+ * enabled. This function evaluates the flags and perform the reset if it's
+ * needed. Returns < 0 on error, 0 if the phy wasn't reset and 1 if the phy
+ * was reset.
+ */
+int phy_reset_after_clk_enable(struct phy_device *phydev)
+{
+ if (!phydev || !phydev->drv)
+ return -ENODEV;
+
+ if (phydev->drv->flags & PHY_RST_AFTER_CLK_EN) {
+ phy_device_reset(phydev, 1);
+ phy_device_reset(phydev, 0);
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_reset_after_clk_enable);
+
+/* Generic PHY support and helper functions */
+
+/**
+ * genphy_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed.
+ */
+static int genphy_config_advert(struct phy_device *phydev)
+{
+ int err, bmsr, changed = 0;
+ u32 adv;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
+
+ /* Setup standard advertisement */
+ err = phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_100BASE4 |
+ ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ bmsr = phy_read(phydev, MII_BMSR);
+ if (bmsr < 0)
+ return bmsr;
+
+ /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
+ * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
+ * logical 1.
+ */
+ if (!(bmsr & BMSR_ESTATEN))
+ return changed;
+
+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+
+ err = phy_modify_changed(phydev, MII_CTRL1000,
+ ADVERTISE_1000FULL | ADVERTISE_1000HALF,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ return changed;
+}
+
+/**
+ * genphy_c37_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed. This function is intended
+ * for Clause 37 1000Base-X mode.
+ */
+static int genphy_c37_config_advert(struct phy_device *phydev)
+{
+ u16 adv = 0;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XFULL;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPAUSE;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPSE_ASYM;
+
+ return phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
+ ADVERTISE_1000XHALF | ADVERTISE_1000XPSE_ASYM,
+ adv);
+}
+
+/**
+ * genphy_config_eee_advert - disable unwanted eee mode advertisement
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MDIO_AN_EEE_ADV after disabling unsupported energy
+ * efficent ethernet modes. Returns 0 if the PHY's advertisement hasn't
+ * changed, and 1 if it has changed.
+ */
+int genphy_config_eee_advert(struct phy_device *phydev)
+{
+ int err;
+
+ /* Nothing to disable */
+ if (!phydev->eee_broken_modes)
+ return 0;
+
+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ phydev->eee_broken_modes, 0);
+ /* If the call failed, we assume that EEE is not supported */
+ return err < 0 ? 0 : err;
+}
+EXPORT_SYMBOL(genphy_config_eee_advert);
+
+/**
+ * genphy_setup_forced - configures/forces speed/duplex from @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Configures MII_BMCR to force speed/duplex
+ * to the values in phydev. Assumes that the values are valid.
+ * Please see phy_sanitize_settings().
+ */
+int genphy_setup_forced(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (SPEED_1000 == phydev->speed)
+ ctl |= BMCR_SPEED1000;
+ else if (SPEED_100 == phydev->speed)
+ ctl |= BMCR_SPEED100;
+
+ if (DUPLEX_FULL == phydev->duplex)
+ ctl |= BMCR_FULLDPLX;
+
+ return phy_modify(phydev, MII_BMCR,
+ ~(BMCR_LOOPBACK | BMCR_ISOLATE | BMCR_PDOWN), ctl);
+}
+EXPORT_SYMBOL(genphy_setup_forced);
+
+static int genphy_setup_master_slave(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ if (!phydev->is_gigabit_capable)
+ return 0;
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ ctl |= CTL1000_PREFER_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ break;
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ ctl |= CTL1000_AS_MASTER;
+ fallthrough;
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ ctl |= CTL1000_ENABLE_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_UNKNOWN:
+ case MASTER_SLAVE_CFG_UNSUPPORTED:
+ return 0;
+ default:
+ phydev_warn(phydev, "Unsupported Master/Slave mode\n");
+ return -EOPNOTSUPP;
+ }
+
+ return phy_modify_changed(phydev, MII_CTRL1000,
+ (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
+ CTL1000_PREFER_MASTER), ctl);
+}
+
+static int genphy_read_master_slave(struct phy_device *phydev)
+{
+ int cfg, state;
+ int val;
+
+ if (!phydev->is_gigabit_capable) {
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
+ return 0;
+ }
+
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+
+ val = phy_read(phydev, MII_CTRL1000);
+ if (val < 0)
+ return val;
+
+ if (val & CTL1000_ENABLE_MASTER) {
+ if (val & CTL1000_AS_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_FORCE;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_FORCE;
+ } else {
+ if (val & CTL1000_PREFER_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_PREFERRED;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
+ }
+
+ val = phy_read(phydev, MII_STAT1000);
+ if (val < 0)
+ return val;
+
+ if (val & LPA_1000MSFAIL) {
+ state = MASTER_SLAVE_STATE_ERR;
+ } else if (phydev->link) {
+ /* this bits are valid only for active link */
+ if (val & LPA_1000MSRES)
+ state = MASTER_SLAVE_STATE_MASTER;
+ else
+ state = MASTER_SLAVE_STATE_SLAVE;
+ } else {
+ state = MASTER_SLAVE_STATE_UNKNOWN;
+ }
+
+ phydev->master_slave_get = cfg;
+ phydev->master_slave_state = state;
+
+ return 0;
+}
+
+/**
+ * genphy_restart_aneg - Enable and Restart Autonegotiation
+ * @phydev: target phy_device struct
+ */
+int genphy_restart_aneg(struct phy_device *phydev)
+{
+ /* Don't isolate the PHY if we're negotiating */
+ return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+}
+EXPORT_SYMBOL(genphy_restart_aneg);
+
+/**
+ * genphy_check_and_restart_aneg - Enable and restart auto-negotiation
+ * @phydev: target phy_device struct
+ * @restart: whether aneg restart is requested
+ *
+ * Check, and restart auto-negotiation if needed.
+ */
+int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
+{
+ int ret;
+
+ if (!restart) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+
+ if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
+ restart = true;
+ }
+
+ if (restart)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_check_and_restart_aneg);
+
+/**
+ * __genphy_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ * @changed: whether autoneg is requested
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR.
+ */
+int __genphy_config_aneg(struct phy_device *phydev, bool changed)
+{
+ int err;
+
+ if (genphy_config_eee_advert(phydev))
+ changed = true;
+
+ err = genphy_setup_master_slave(phydev);
+ if (err < 0)
+ return err;
+ else if (err)
+ changed = true;
+
+ if (AUTONEG_ENABLE != phydev->autoneg)
+ return genphy_setup_forced(phydev);
+
+ err = genphy_config_advert(phydev);
+ if (err < 0) /* error */
+ return err;
+ else if (err)
+ changed = true;
+
+ return genphy_check_and_restart_aneg(phydev, changed);
+}
+EXPORT_SYMBOL(__genphy_config_aneg);
+
+/**
+ * genphy_c37_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR. This function is intended
+ * for use with Clause 37 1000Base-X mode.
+ */
+int genphy_c37_config_aneg(struct phy_device *phydev)
+{
+ int err, changed;
+
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return genphy_setup_forced(phydev);
+
+ err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
+ BMCR_SPEED1000);
+ if (err)
+ return err;
+
+ changed = genphy_c37_config_advert(phydev);
+ if (changed < 0) /* error */
+ return changed;
+
+ if (!changed) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ int ctl = phy_read(phydev, MII_BMCR);
+
+ if (ctl < 0)
+ return ctl;
+
+ if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
+ changed = 1; /* do restart aneg */
+ }
+
+ /* Only restart aneg if we are advertising something different
+ * than we were before.
+ */
+ if (changed > 0)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_config_aneg);
+
+/**
+ * genphy_aneg_done - return auto-negotiation status
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the status register and returns 0 either if
+ * auto-negotiation is incomplete, or if there was an error.
+ * Returns BMSR_ANEGCOMPLETE if auto-negotiation is done.
+ */
+int genphy_aneg_done(struct phy_device *phydev)
+{
+ int retval = phy_read(phydev, MII_BMSR);
+
+ return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
+}
+EXPORT_SYMBOL(genphy_aneg_done);
+
+/**
+ * genphy_update_link - update link status in @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Update the value in phydev->link to reflect the
+ * current link value. In order to do this, we need to read
+ * the status register twice, keeping the second value.
+ */
+int genphy_update_link(struct phy_device *phydev)
+{
+ int status = 0, bmcr;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ bmcr = phy_read(phydev, MII_BMCR);
+#endif
+ if (bmcr < 0)
+ return bmcr;
+
+ /* Autoneg is being started, therefore disregard BMSR value and
+ * report link as down.
+ */
+ if (bmcr & BMCR_ANRESTART)
+ goto done;
+
+ /* The link state is latched low so that momentary link
+ * drops can be detected. Do not double-read the status
+ * in polling mode to detect such short link drops except
+ * the link was already down.
+ */
+ if (!phy_polling_mode(phydev) || !phydev->link) {
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+ else if (status & BMSR_LSTATUS)
+ goto done;
+ }
+
+ /* Read link and autonegotiation status */
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+done:
+ phydev->link = status & BMSR_LSTATUS ? 1 : 0;
+ phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0;
+
+ /* Consider the case that autoneg was started and "aneg complete"
+ * bit has been reset, but "link up" bit not yet.
+ */
+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
+ phydev->link = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_update_link);
+
+int genphy_read_lpa(struct phy_device *phydev)
+{
+ int lpa, lpagb;
+
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ if (!phydev->autoneg_complete) {
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ 0);
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
+ return 0;
+ }
+
+ if (phydev->is_gigabit_capable) {
+ lpagb = phy_read(phydev, MII_STAT1000);
+ if (lpagb < 0)
+ return lpagb;
+
+ if (lpagb & LPA_1000MSFAIL) {
+ int adv = phy_read(phydev, MII_CTRL1000);
+
+ if (adv < 0)
+ return adv;
+
+ if (adv & CTL1000_ENABLE_MASTER)
+ phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
+ else
+ phydev_err(phydev, "Master/Slave resolution failed\n");
+ return -ENOLINK;
+ }
+
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ lpagb);
+ }
+
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
+ } else {
+ linkmode_zero(phydev->lp_advertising);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_lpa);
+
+/**
+ * genphy_read_status_fixed - read the link parameters for !aneg mode
+ * @phydev: target phy_device struct
+ *
+ * Read the current duplex and speed state for a PHY operating with
+ * autonegotiation disabled.
+ */
+int genphy_read_status_fixed(struct phy_device *phydev)
+{
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ int bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ int bmcr = phy_read(phydev, MII_BMCR);
+#endif
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (bmcr & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status_fixed);
+
+/**
+ * genphy_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. Start by checking the gigabit possibilities,
+ * then move on to 10/100.
+ */
+int genphy_read_status(struct phy_device *phydev)
+{
+ int err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ err = genphy_read_master_slave(phydev);
+ if (err < 0)
+ return err;
+
+ err = genphy_read_lpa(phydev);
+ if (err < 0)
+ return err;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ err = genphy_read_status_fixed(phydev);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status);
+
+/**
+ * genphy_c37_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. This function is for Clause 37 1000Base-X mode.
+ */
+int genphy_c37_read_status(struct phy_device *phydev)
+{
+ int lpa, err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->lp_advertising, lpa & LPA_LPACK);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XPAUSE);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->lp_advertising,
+ lpa & LPA_1000XPAUSE_ASYM);
+
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ int bmcr = phy_read(phydev, MII_BMCR);
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_read_status);
+
+/**
+ * genphy_soft_reset - software reset the PHY via BMCR_RESET bit
+ * @phydev: target phy_device struct
+ *
+ * Description: Perform a software PHY reset using the standard
+ * BMCR_RESET bit and poll for the reset bit to be cleared.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_soft_reset(struct phy_device *phydev)
+{
+ u16 res = BMCR_RESET;
+ int ret;
+
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ res |= BMCR_ANRESTART;
+
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res);
+ if (ret < 0)
+ return ret;
+
+ /* Clause 22 states that setting bit BMCR_RESET sets control registers
+ * to their default value. Therefore the POWER DOWN bit is supposed to
+ * be cleared after soft reset.
+ */
+ phydev->suspended = 0;
+
+ ret = phy_poll_reset(phydev);
+ if (ret)
+ return ret;
+
+ /* BMCR may be reset to defaults */
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ ret = genphy_setup_forced(phydev);
+
+ return ret;
+}
+EXPORT_SYMBOL(genphy_soft_reset);
+
+/**
+ * genphy_read_abilities - read PHY abilities from Clause 22 registers
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the PHY's abilities and populates
+ * phydev->supported accordingly.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_read_abilities(struct phy_device *phydev)
+{
+ int val;
+
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phydev->supported);
+
+ val = phy_read(phydev, MII_BMSR);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
+ val & BMSR_ANEGCAPABLE);
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
+ val & BMSR_100FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
+ val & BMSR_100HALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
+ val & BMSR_10FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
+ val & BMSR_10HALF);
+
+ if (val & BMSR_ESTATEN) {
+ val = phy_read(phydev, MII_ESTATUS);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_TFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported, val & ESTATUS_1000_THALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_XFULL);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_abilities);
+
+/* This is used for the phy device which doesn't support the MMD extended
+ * register access, but it does have side effect when we are trying to access
+ * the MMD register via indirect method.
+ */
+int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_read_mmd_unsupported);
+
+int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
+ u16 regnum, u16 val)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_write_mmd_unsupported);
+
+int genphy_suspend(struct phy_device *phydev)
+{
+ return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_suspend);
+
+int genphy_resume(struct phy_device *phydev)
+{
+ return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_resume);
+
+int genphy_loopback(struct phy_device *phydev, bool enable)
+{
+ return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
+ enable ? BMCR_LOOPBACK : 0);
+}
+EXPORT_SYMBOL(genphy_loopback);
+
+/**
+ * phy_remove_link_mode - Remove a supported link mode
+ * @phydev: phy_device structure to remove link mode from
+ * @link_mode: Link mode to be removed
+ *
+ * Description: Some MACs don't support all link modes which the PHY
+ * does. e.g. a 1G MAC often does not support 1000Half. Add a helper
+ * to remove a link mode.
+ */
+void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode)
+{
+ linkmode_clear_bit(link_mode, phydev->supported);
+ phy_advertise_supported(phydev);
+}
+EXPORT_SYMBOL(phy_remove_link_mode);
+
+static void phy_copy_pause_bits(unsigned long *dst, unsigned long *src)
+{
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, src));
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, src));
+}
+
+/**
+ * phy_advertise_supported - Advertise all supported modes
+ * @phydev: target phy_device struct
+ *
+ * Description: Called to advertise all supported modes, doesn't touch
+ * pause mode advertising.
+ */
+void phy_advertise_supported(struct phy_device *phydev)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(new);
+
+ linkmode_copy(new, phydev->supported);
+ phy_copy_pause_bits(new, phydev->advertising);
+ linkmode_copy(phydev->advertising, new);
+}
+EXPORT_SYMBOL(phy_advertise_supported);
+
+/**
+ * phy_support_sym_pause - Enable support of symmetrical pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports symmetrical
+ * Pause, but not asym pause.
+ */
+void phy_support_sym_pause(struct phy_device *phydev)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_sym_pause);
+
+/**
+ * phy_support_asym_pause - Enable support of asym pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports Asym Pause.
+ */
+void phy_support_asym_pause(struct phy_device *phydev)
+{
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_asym_pause);
+
+/**
+ * phy_set_sym_pause - Configure symmetric Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ * @autoneg: Auto neg should be used
+ *
+ * Description: Configure advertised Pause support depending on if
+ * receiver pause and pause auto neg is supported. Generally called
+ * from the set_pauseparam .ndo.
+ */
+void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
+ bool autoneg)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
+
+ if (rx && tx && autoneg)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+
+ linkmode_copy(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_set_sym_pause);
+
+/**
+ * phy_set_asym_pause - Configure Pause and Asym Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ *
+ * Description: Configure advertised Pause support depending on if
+ * transmit and receiver pause is supported. If there has been a
+ * change in adverting, trigger a new autoneg. Generally called from
+ * the set_pauseparam .ndo.
+ */
+void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(oldadv);
+
+ linkmode_copy(oldadv, phydev->advertising);
+ linkmode_set_pause(phydev->advertising, tx, rx);
+
+ if (!linkmode_equal(oldadv, phydev->advertising) &&
+ phydev->autoneg)
+ phy_start_aneg(phydev);
+}
+EXPORT_SYMBOL(phy_set_asym_pause);
+
+/**
+ * phy_validate_pause - Test if the PHY/MAC support the pause configuration
+ * @phydev: phy_device struct
+ * @pp: requested pause configuration
+ *
+ * Description: Test if the PHY/MAC combination supports the Pause
+ * configuration the user is requesting. Returns True if it is
+ * supported, false otherwise.
+ */
+bool phy_validate_pause(struct phy_device *phydev,
+ struct ethtool_pauseparam *pp)
+{
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported) && pp->rx_pause)
+ return false;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported) &&
+ pp->rx_pause != pp->tx_pause)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL(phy_validate_pause);
+
+/**
+ * phy_get_pause - resolve negotiated pause modes
+ * @phydev: phy_device struct
+ * @tx_pause: pointer to bool to indicate whether transmit pause should be
+ * enabled.
+ * @rx_pause: pointer to bool to indicate whether receive pause should be
+ * enabled.
+ *
+ * Resolve and return the flow control modes according to the negotiation
+ * result. This includes checking that we are operating in full duplex mode.
+ * See linkmode_resolve_pause() for further details.
+ */
+void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause)
+{
+ if (phydev->duplex != DUPLEX_FULL) {
+ *tx_pause = false;
+ *rx_pause = false;
+ return;
+ }
+
+ return linkmode_resolve_pause(phydev->advertising,
+ phydev->lp_advertising,
+ tx_pause, rx_pause);
+}
+EXPORT_SYMBOL(phy_get_pause);
+
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ s32 int_delay;
+ int ret;
+
+ ret = device_property_read_u32(dev, name, &int_delay);
+ if (ret)
+ return ret;
+
+ return int_delay;
+}
+#else
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ return -EINVAL;
+}
+#endif
+
+/**
+ * phy_get_delay_index - returns the index of the internal delay
+ * @phydev: phy_device struct
+ * @dev: pointer to the devices device struct
+ * @delay_values: array of delays the PHY supports
+ * @size: the size of the delay array
+ * @is_rx: boolean to indicate to get the rx internal delay
+ *
+ * Returns the index within the array of internal delay passed in.
+ * If the device property is not present then the interface type is checked
+ * if the interface defines use of internal delay then a 1 is returned otherwise
+ * a 0 is returned.
+ * The array must be in ascending order. If PHY does not have an ascending order
+ * array then size = 0 and the value of the delay property is returned.
+ * Return -EINVAL if the delay is invalid or cannot be found.
+ */
+s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev,
+ const int *delay_values, int size, bool is_rx)
+{
+ s32 delay;
+ int i;
+
+ if (is_rx) {
+ delay = phy_get_int_delay_property(dev, "rx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ return 1;
+ else
+ return 0;
+ }
+
+ } else {
+ delay = phy_get_int_delay_property(dev, "tx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ return 1;
+ else
+ return 0;
+ }
+ }
+
+ if (delay < 0)
+ return delay;
+
+ if (delay && size == 0)
+ return delay;
+
+ if (delay < delay_values[0] || delay > delay_values[size - 1]) {
+ phydev_err(phydev, "Delay %d is out of range\n", delay);
+ return -EINVAL;
+ }
+
+ if (delay == delay_values[0])
+ return 0;
+
+ for (i = 1; i < size; i++) {
+ if (delay == delay_values[i])
+ return i;
+
+ /* Find an approximate index by looking up the table */
+ if (delay > delay_values[i - 1] &&
+ delay < delay_values[i]) {
+ if (delay - delay_values[i - 1] <
+ delay_values[i] - delay)
+ return i - 1;
+ else
+ return i;
+ }
+ }
+
+ phydev_err(phydev, "error finding internal delay index for %d\n",
+ delay);
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(phy_get_internal_delay);
+
+static bool phy_drv_supports_irq(struct phy_driver *phydrv)
+{
+ return phydrv->config_intr && phydrv->ack_interrupt;
+}
+
+/**
+ * phy_probe - probe and init a PHY device
+ * @dev: device to probe and init
+ *
+ * Description: Take care of setting up the phy_device structure,
+ * set the state to READY (the driver's init function should
+ * set it to STARTING if needed).
+ */
+static int phy_probe(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ int err = 0;
+
+ phydev->drv = phydrv;
+
+ /* Disable the interrupt if the PHY doesn't support it
+ * but the interrupt is still a valid one
+ */
+ if (!phy_drv_supports_irq(phydrv) && phy_interrupt_is_valid(phydev))
+ phydev->irq = PHY_POLL;
+
+ if (phydrv->flags & PHY_IS_INTERNAL)
+ phydev->is_internal = true;
+
+ mutex_lock(&phydev->lock);
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (phydev->drv->probe) {
+ err = phydev->drv->probe(phydev);
+ if (err)
+ goto out;
+ }
+
+ /* Start out supporting everything. Eventually,
+ * a controller will attach, and may modify one
+ * or both of these values
+ */
+ if (phydrv->features) {
+ linkmode_copy(phydev->supported, phydrv->features);
+ } else if (phydrv->get_features) {
+ err = phydrv->get_features(phydev);
+ } else if (phydev->is_c45) {
+ err = genphy_c45_pma_read_abilities(phydev);
+ } else {
+ err = genphy_read_abilities(phydev);
+ }
+
+ if (err)
+ goto out;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported))
+ phydev->autoneg = 0;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+
+ of_set_phy_supported(phydev);
+ phy_advertise_supported(phydev);
+
+ /* Get the EEE modes we want to prohibit. We will ask
+ * the PHY stop advertising these mode later on
+ */
+ of_set_phy_eee_broken(phydev);
+
+ /* The Pause Frame bits indicate that the PHY can support passing
+ * pause frames. During autonegotiation, the PHYs will determine if
+ * they should allow pause frames to pass. The MAC driver should then
+ * use that result to determine whether to enable flow control via
+ * pause frames.
+ *
+ * Normally, PHY drivers should not set the Pause bits, and instead
+ * allow phylib to do that. However, there may be some situations
+ * (e.g. hardware erratum) where the driver wants to set only one
+ * of these bits.
+ */
+ if (!test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported) &&
+ !test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported)) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported);
+ }
+
+ /* Set the state to READY by default */
+ phydev->state = PHY_READY;
+
+out:
+ /* Assert the reset signal */
+ if (err)
+ phy_device_reset(phydev, 1);
+
+ mutex_unlock(&phydev->lock);
+
+ return err;
+}
+
+static int phy_remove(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ cancel_delayed_work_sync(&phydev->state_queue);
+
+ mutex_lock(&phydev->lock);
+ phydev->state = PHY_DOWN;
+ mutex_unlock(&phydev->lock);
+
+ sfp_bus_del_upstream(phydev->sfp_bus);
+ phydev->sfp_bus = NULL;
+
+ if (phydev->drv && phydev->drv->remove)
+ phydev->drv->remove(phydev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ phydev->drv = NULL;
+
+ return 0;
+}
+
+/**
+ * phy_driver_register - register a phy_driver with the PHY layer
+ * @new_driver: new phy_driver to register
+ * @owner: module owning this PHY
+ */
+int phy_driver_register(struct phy_driver *new_driver, struct module *owner)
+{
+ int retval;
+
+ /* Either the features are hard coded, or dynamically
+ * determined. It cannot be both.
+ */
+ if (WARN_ON(new_driver->features && new_driver->get_features)) {
+ pr_err("%s: features and get_features must not both be set\n",
+ new_driver->name);
+ return -EINVAL;
+ }
+
+ new_driver->mdiodrv.flags |= MDIO_DEVICE_IS_PHY;
+ new_driver->mdiodrv.driver.name = new_driver->name;
+ new_driver->mdiodrv.driver.bus = &mdio_bus_type;
+ new_driver->mdiodrv.driver.probe = phy_probe;
+ new_driver->mdiodrv.driver.remove = phy_remove;
+ new_driver->mdiodrv.driver.owner = owner;
+ new_driver->mdiodrv.driver.probe_type = PROBE_FORCE_SYNCHRONOUS;
+
+ retval = driver_register(&new_driver->mdiodrv.driver);
+ if (retval) {
+ pr_err("%s: Error %d in registering driver\n",
+ new_driver->name, retval);
+
+ return retval;
+ }
+
+ pr_debug("%s: Registered new driver\n", new_driver->name);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_driver_register);
+
+int phy_drivers_register(struct phy_driver *new_driver, int n,
+ struct module *owner)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < n; i++) {
+ ret = phy_driver_register(new_driver + i, owner);
+ if (ret) {
+ while (i-- > 0)
+ phy_driver_unregister(new_driver + i);
+ break;
+ }
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_drivers_register);
+
+void phy_driver_unregister(struct phy_driver *drv)
+{
+ driver_unregister(&drv->mdiodrv.driver);
+}
+EXPORT_SYMBOL(phy_driver_unregister);
+
+void phy_drivers_unregister(struct phy_driver *drv, int n)
+{
+ int i;
+
+ for (i = 0; i < n; i++)
+ phy_driver_unregister(drv + i);
+}
+EXPORT_SYMBOL(phy_drivers_unregister);
+
+static struct phy_driver genphy_driver = {
+ .phy_id = 0xffffffff,
+ .phy_id_mask = 0xffffffff,
+ .name = "Generic PHY",
+ .get_features = genphy_read_abilities,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .set_loopback = genphy_loopback,
+};
+
+static const struct ethtool_phy_ops phy_ethtool_phy_ops = {
+ .get_sset_count = phy_ethtool_get_sset_count,
+ .get_strings = phy_ethtool_get_strings,
+ .get_stats = phy_ethtool_get_stats,
+ .start_cable_test = phy_start_cable_test,
+ .start_cable_test_tdr = phy_start_cable_test_tdr,
+};
+
+static int __init phy_init(void)
+{
+ int rc;
+
+ rc = mdio_bus_init();
+ if (rc)
+ return rc;
+
+ ethtool_set_ethtool_phy_ops(&phy_ethtool_phy_ops);
+ features_init();
+
+ rc = phy_driver_register(&genphy_c45_driver, THIS_MODULE);
+ if (rc)
+ goto err_c45;
+
+ rc = phy_driver_register(&genphy_driver, THIS_MODULE);
+ if (rc) {
+ phy_driver_unregister(&genphy_c45_driver);
+err_c45:
+ mdio_bus_exit();
+ }
+
+ return rc;
+}
+
+static void __exit phy_exit(void)
+{
+ phy_driver_unregister(&genphy_c45_driver);
+ phy_driver_unregister(&genphy_driver);
+ mdio_bus_exit();
+ ethtool_set_ethtool_phy_ops(NULL);
+}
+
+subsys_initcall(phy_init);
+module_exit(phy_exit);
diff --git a/upstream/linux-5.10/include/linux/mfd/zx234290.h b/upstream/linux-5.10/include/linux/mfd/zx234290.h
new file mode 100755
index 0000000..ea89815
--- /dev/null
+++ b/upstream/linux-5.10/include/linux/mfd/zx234290.h
@@ -0,0 +1,1130 @@
+/*
+ * zx234290.h -- ZTE ZX234290
+ *
+ * Copyright 2016 ZTE Corporation.
+ *
+ * Author: yuxiang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_ZX234290_H
+#define __LINUX_MFD_ZX234290_H
+
+#include <linux/mutex.h>
+
+#define zx234290_rails(_name) "zx234290_"#_name
+
+#define u8 unsigned char
+
+/* LDOs */
+#define ZX234290_REG_LDO1 0
+#define ZX234290_REG_LDO2 1
+#define ZX234290_REG_LDO3 2
+#define ZX234290_REG_LDO4 3
+#define ZX234290_REG_LDO5 4
+#define ZX234290_REG_LDO6 5
+#define ZX234290_REG_LDO7 6
+#define ZX234290_REG_LDO8 7
+
+#define ZX234290_REG_LDO9 8
+#define ZX234290_REG_LDO10 9
+#define ZX234290_REG_LDO11 10
+
+/* DCDC's */
+#define ZX234290_REG_DCDC0 11
+#define ZX234290_REG_DCDC1 12
+#define ZX234290_REG_DCDC2 13
+#define ZX234290_REG_DCDC3 14
+#define ZX234290_REG_DCDC4 15
+
+/* ZX regulator type list */
+#ifndef ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_INT_LDO_FAUL 0
+#define ZX234290_INT_BUCK_FAUL 1
+#endif
+
+#define ZX234290_INT_EOADC 2 /* xxxx x100 */
+#define ZX234290_INT_PWRON_SHORT 3
+#define ZX234290_INT_PWRON_LONG 4
+#define ZX234290_INT_PWRON 5
+
+#define ZX234290_INT_RTC_ALRM 8
+#define ZX234290_INT_BATT_DET 10
+#define ZX234290_INT_RTC_MIN 11
+#define ZX234290_INT_RTC_HOUR 12
+
+#define ZX234290_NUM_IRQ 13
+
+#ifdef ZX234290_PWR_FAUL_PROCESS
+int zx234290_register_client(struct notifier_block *nb);
+int zx234290_unregister_client(struct notifier_block *nb);
+int zx234290_notifier_call_chain(unsigned long val, void *v);
+#endif
+
+#if 0
+/* External controls requests */
+enum zx234290_ext_control {
+ PWR_REQ_INPUT_NONE = 0x00000000,
+ PWR_REQ_INPUT_PREQ1 = 0x00000001,
+ PWR_REQ_INPUT_PREQ2 = 0x00000002,
+ PWR_REQ_INPUT_PREQ3 = 0x00000004,
+ PWR_OFF_ON_SLEEP = 0x00000008,
+ PWR_ON_ON_SLEEP = 0x00000010,
+};
+#endif
+
+#if 0
+typedef enum
+{
+ RESET_TO_NORMAL, /*reset to idle*/
+ RESET_TO_CHARGER, /*reset to charger*/
+ RESET_TO_ALRAM, /*reset to alarm*/
+ RESET_TO_EXCEPTRESET,
+ MAX_RESET_TYPE,
+} T_ZDrvSys_RESET_TYPE;
+#endif
+
+typedef enum _T_ZDrvPmic_Enable{
+ PM_DISABLE = 0,
+ PM_ENABLE,
+ PM_ENABLE_NOT_SUPPORT = -100,
+ PM_ENABLE_MAX_STATUS = -255
+} T_ZDrvPmic_Enable;
+
+typedef enum _T_ZDrvPmic_NrmMode{
+ PM_NRMMODE_AUTO = 0,
+ PM_NRMMODE_PFM,
+ PM_NRMMODE_PWM,
+ PM_NRMMODE_NOT_SUPPORT = -100,
+ PM_NRMMODE_MAX_STATUS = -255
+}T_ZDrvPmic_NrmMode;
+
+typedef enum _T_ZDrvPmic_SlpMode{
+ PM_SLPMODE_AUTO_NORMAL = 0, //auto in dcdc, normal in ldo
+ PM_SLPMODE_ECO_NRMV, //normal voltage
+ PM_SLPMODE_ECO_SLPV, //sleep voltage
+ PM_SLPMODE_OFF, //OFF
+ PM_SLPMODE_NOT_SUPPORT = -100,
+ PM_SLPMODE_MAX_STATUS = -255
+}T_ZDrvPmic_SlpMode;
+
+//consumer
+typedef enum _T_ZDrvPmic_Regulator{
+ VCORE0 = 0,
+ VCORE1,
+ VDDR,
+ VMMC,
+ VSD0,
+ VSD1,
+ VIO_LO,
+ VIO_HI,
+ VUSB_0V9,
+ VUSB_3V3,
+ VPLL_LO,
+ VPLL_HI,
+ VSIM1,
+ VSIM2,
+ VRF_LO,
+ VRF_HI,
+ VRF_SW,
+ VPA,
+ VCTCXO1,
+ VCTCXO2,
+ VSSBUF,
+ VRTC,
+} T_ZDrvPmic_Regulator;
+
+typedef enum _T_ZDrvPmic_Vcore{
+ PM_VOLT_0_6750 = 0,
+ PM_VOLT_0_6875 ,
+ PM_VOLT_0_7000 ,
+ PM_VOLT_0_7125 ,
+ PM_VOLT_0_7250 = 0x04,
+ PM_VOLT_0_7375 ,
+ PM_VOLT_0_7500 ,
+ PM_VOLT_0_7625 ,
+ PM_VOLT_0_7750 = 0x08 ,
+ PM_VOLT_0_7875 ,
+ PM_VOLT_0_8000 ,
+ PM_VOLT_0_8125 ,
+ PM_VOLT_0_8250 = 0x0c,
+ PM_VOLT_0_8375 ,
+ PM_VOLT_0_8500 ,
+ PM_VOLT_0_8625 ,
+ PM_VOLT_0_8750 = 0x10 ,
+ PM_VOLT_0_8875 ,
+ PM_VOLT_0_9000 ,
+ PM_VOLT_0_9125 ,
+ PM_VOLT_0_9250 = 0x14,
+ PM_VOLT_0_9375 ,
+ PM_VOLT_0_9500 ,
+ PM_VOLT_0_9625 ,
+ PM_VOLT_0_9750 = 0x18 ,
+ PM_VOLT_0_9875 ,
+ PM_VOLT_1_0000 ,
+ PM_VOLT_1_0125 ,
+ PM_VOLT_1_0250 = 0x1c,
+ PM_VOLT_1_0375 ,
+ PM_VOLT_1_0500 ,
+ PM_VOLT_1_0625 ,
+ PM_VOLT_1_0750 = 0x20 ,
+ PM_VOLT_1_0875 ,
+ PM_VOLT_1_1000 ,
+ PM_VOLT_1_1125 ,
+ PM_VOLT_1_1250 = 0x24,
+ PM_VOLT_1_1375 ,
+ PM_VOLT_1_1500 ,
+ PM_VOLT_1_1625 ,
+ PM_VOLT_1_1750 = 0x28 ,
+ PM_VOLT_1_1875 ,
+ PM_VOLT_1_2000 ,
+ PM_VOLT_1_2125 ,
+ PM_VOLT_1_2250 = 0x2c,
+ PM_VOLT_1_2375 ,
+ PM_VOLT_1_2500 = 0x2e,
+ PM_VOLT_1_2625 ,
+ PM_VOLT_1_2750 = 0x30 ,
+ PM_VOLT_1_2875 ,
+ PM_VOLT_1_3000 ,
+ PM_VOLT_1_3125 ,
+ PM_VOLT_1_3250 = 0x34,
+ PM_VOLT_1_3375 ,
+ PM_VOLT_1_3500 ,
+ PM_VOLT_1_3625 ,
+ PM_VOLT_1_3750 = 0x38 ,
+ PM_VOLT_1_3875 ,
+ PM_VOLT_1_4000 ,
+ PM_VOLT_1_4125 ,
+ PM_VOLT_1_4250 = 0x3c,
+ PM_VOLT_1_4375 ,
+ PM_VOLT_1_4500 ,
+ PM_VOLT_1_4625 ,
+ PM_VOLT_1_4750 = 0x40 ,
+ PM_VOLT_1_4875 ,
+ PM_VOLT_1_5000 ,
+ PM_VOLT_1_5125 ,
+ PM_VOLT_1_5250 = 0x44,
+ PM_VOLT_1_5375 ,
+ PM_VOLT_1_5500 ,
+ PM_VOLT_1_5625 ,
+ PM_VOLT_1_5750 = 0x48,
+ PM_VOLT_1_5875 ,
+ PM_VOLT_1_6000 ,
+ PM_VOLT_1_6125 ,
+ PM_VOLT_1_6250 = 0x4c,
+ PM_VOLT_1_6375 ,
+ PM_VOLT_1_6500 ,
+ PM_VOLT_1_6625 ,
+ PM_VOLT_1_6750 = 0x50,
+ PM_VOLT_1_6875 ,
+ PM_VOLT_1_7000 ,
+ PM_VOLT_1_7125 ,
+ PM_VOLT_1_7250 = 0x54,
+ PM_VOLT_1_7375 ,
+ PM_VOLT_1_7500 ,
+ PM_VOLT_1_7625 ,
+ PM_VOLT_1_7750 = 0x58,
+ PM_VOLT_1_7875 ,
+ PM_VOLT_1_8000 ,
+ PM_VOLT_1_8125 ,
+ PM_VOLT_1_8250 = 0x5c,
+ PM_VOLT_1_8375 ,
+ PM_VOLT_1_8500 ,
+ PM_VOLT_1_8625 ,
+ PM_VOLT_1_8750 = 0x60 ,
+ PM_VOLT_1_8875 ,
+ PM_VOLT_1_9000 ,
+ PM_VOLT_1_9125 ,
+ PM_VOLT_1_9250 = 0x64,
+ PM_VOLT_1_9375 ,
+ PM_VOLT_1_9500 ,
+ PM_VOLT_1_9625 ,
+ PM_VOLT_1_9750 = 0x68,
+ PM_VOLT_1_9875 ,
+ PM_VOLT_2_0000 ,
+ PM_VOLT_2_0125 ,
+ PM_VOLT_2_0250 = 0x6c,
+ PM_VOLT_2_0375 ,
+ PM_VOLT_2_0500 ,
+ PM_VOLT_2_0625 ,
+ PM_VOLT_2_0750 = 0x70,
+ PM_VOLT_2_0875 ,
+ PM_VOLT_2_1000 ,
+ PM_VOLT_2_1125 ,
+ PM_VOLT_2_1250 = 0x74,
+ PM_VOLT_2_1375 ,
+ PM_VOLT_2_1500 ,
+ PM_VOLT_2_1625 ,
+ PM_VOLT_2_1750 = 0x78 ,
+ PM_VOLT_2_1875 ,
+ PM_VOLT_2_2000 ,
+ PM_VOLT_2_2125 ,
+ PM_VOLT_2_2250 = 0x7c,
+ PM_VOLT_2_2375 ,
+ PM_VOLT_2_2500 ,
+ PM_VOLT_2_2625 ,
+ PM_VOLT_2_2750 = 0x80,
+ PM_VOLT_2_2875 ,
+ PM_VOLT_2_3000 ,
+ PM_VOLT_2_3125 ,
+ PM_VOLT_2_3250 = 0x84,
+ PM_VOLT_2_3375 ,
+ PM_VOLT_2_3500 ,
+ PM_VOLT_2_3625 ,
+ PM_VOLT_2_3750 = 0x88 ,
+ PM_VOLT_2_3875 ,
+ PM_VOLT_2_4000 ,
+ PM_VOLT_2_4125 ,
+ PM_VOLT_2_4250 = 0x8c,
+ PM_VOLT_2_4375 ,
+ PM_VOLT_2_4500 ,
+ PM_VOLT_2_4625 ,
+ PM_VOLT_2_4750 = 0x90,
+ PM_VOLT_2_4875 ,
+ PM_VOLT_2_5000 ,
+ PM_VOLT_2_5125 ,
+ PM_VOLT_2_5250 = 0x94,
+ PM_VOLT_2_5375 ,
+ PM_VOLT_2_5500 ,
+ PM_VOLT_2_5625 ,
+ PM_VOLT_2_5750 = 0x98 ,
+ PM_VOLT_2_5875 ,
+ PM_VOLT_2_6000 ,
+ PM_VOLT_2_6125 ,
+ PM_VOLT_2_6250 = 0x9c,
+ PM_VOLT_2_6375 ,
+ PM_VOLT_2_6500 ,
+ PM_VOLT_2_6625 ,
+ PM_VOLT_2_6750 = 0xa0,
+ PM_VOLT_2_6875 ,
+ PM_VOLT_2_7000 ,
+ PM_VOLT_2_7125 ,
+ PM_VOLT_2_7250 = 0xa4,
+ PM_VOLT_2_7375 ,
+ PM_VOLT_2_7500 ,
+ PM_VOLT_2_7625 ,
+ PM_VOLT_2_7750 = 0xa8,
+ PM_VOLT_2_7875 ,
+ PM_VOLT_2_8000 ,
+ PM_VOLT_2_8125 ,
+ PM_VOLT_2_8250 = 0xac,
+ PM_VOLT_2_8375 ,
+ PM_VOLT_2_8500 ,
+ PM_VOLT_2_8625 ,
+ PM_VOLT_2_8750 = 0xb0,
+ PM_VOLT_2_8875 ,
+ PM_VOLT_2_9000 ,
+ PM_VOLT_2_9125 ,
+ PM_VOLT_2_9250 = 0xb4,
+ PM_VOLT_2_9375 ,
+ PM_VOLT_2_9500 ,
+ PM_VOLT_2_9625 ,
+ PM_VOLT_2_9750 = 0xb8,
+ PM_VOLT_2_9875 ,
+ PM_VOLT_3_0000 ,
+ PM_VOLT_3_0125 ,
+ PM_VOLT_3_0250 = 0xbc,
+ PM_VOLT_3_0375 ,
+ PM_VOLT_3_0500 ,
+ PM_VOLT_3_0625 ,
+ PM_VOLT_3_0750 = 0xc0 ,
+ PM_VOLT_3_0875 ,
+ PM_VOLT_3_1000 ,
+ PM_VOLT_3_1125 ,
+ PM_VOLT_3_1250 = 0xc4,
+ PM_VOLT_3_1375 ,
+ PM_VOLT_3_1500 ,
+ PM_VOLT_3_1625 ,
+ PM_VOLT_3_1750 = 0xc8 ,
+ PM_VOLT_3_1875 ,
+ PM_VOLT_3_2000 ,
+ PM_VOLT_3_2125 ,
+ PM_VOLT_3_2250 = 0xcc,
+ PM_VOLT_3_2375 ,
+ PM_VOLT_3_2500 ,
+ PM_VOLT_3_2625 ,
+ PM_VOLT_3_2750 = 0xd0 ,
+ PM_VOLT_3_2875 ,
+ PM_VOLT_3_3000 ,
+ PM_VOLT_3_3125 ,
+ PM_VOLT_3_3250 = 0xd4,
+ PM_VOLT_3_3375 ,
+ PM_VOLT_3_3500 ,
+ PM_VOLT_3_3625 ,
+ PM_VOLT_3_3750 = 0xd8 ,
+ PM_VOLT_3_3875 ,
+
+ PM_VOLT_NOT_SUPPORT = -100,
+ PM_VOLT_MAX_STATUS = -255,
+ } T_ZDrvPmic_Voltage;
+
+
+
+
+/**
+ * struct zx234290 - zx234290 sub-driver chip access routines
+ */
+
+struct zx234290 {
+ struct device *dev;
+ /* for read/write acces */
+ struct mutex io_mutex;
+
+ /* For device IO interfaces: I2C or SPI */
+ void *control_data;
+
+ int (*read)(struct zx234290 *zx234290, u8 reg, int size, void *dest);
+ int (*write)(struct zx234290 *zx234290, u8 reg, int size, void *src);
+
+ /* Client devices */
+ struct zx234290_regulator *regulator;
+
+ /* GPIO Handling */
+
+ /* IRQ Handling */
+ struct mutex irq_lock;
+ int chip_irq;
+ int irq_base;
+ struct irq_domain * irq_domain;
+ int irq_num;
+ unsigned int irq_mask;
+};
+int zx234290_i2c_read_simple(u8 reg, void *dest);
+int zx234290_i2c_write_simple(u8 reg, void *src);
+int zx234290_i2c_read_simple_PSM(u8 reg, void *dest);
+int zx234290_i2c_write_simple_PSM(u8 reg, void *src);
+
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg);
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val);
+int zx234290_device_init(struct zx234290 *zx234290);
+void zx234290_device_exit(struct zx234290 *zx234290);
+
+
+/*regulator defines*/
+#if 1
+/*
+ * List of registers for ZX234290
+*/
+
+/////////////////////////////////////////////////
+/*slave address 0x12*/
+/////////////////////////////////////////////////
+#define ZX234290_I2C_SLAVE_ADDR0 (0x12)
+
+ /* interrupt and mask */
+#define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */
+#define ZX234290_REG_ADDR_INTB 0x01
+#define ZX234290_REG_ADDR_INTA_MASK 0x02
+#define ZX234290_REG_ADDR_INTB_MASK 0x03
+
+ /* interrupt status */
+#define ZX234290_REG_ADDR_STSA 0x04
+#define ZX234290_REG_ADDR_STSB 0x05
+#define ZX234290_REG_ADDR_STS_STARTUP 0x06
+
+ /* adc & softon select */
+#define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/
+
+ /* bucks normal voltage and sleep voltage */
+#define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/
+#define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D
+
+ /* bucks mode */
+#define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/
+#define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/
+#define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */
+
+ /* ldo normal voltage */
+#define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */
+#define ZX234290_REG_ADDR_LDO34_VOL 0x13
+#define ZX234290_REG_ADDR_LDO56_VOL 0x14
+#define ZX234290_REG_ADDR_LDO78_VOL 0x15
+#define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */
+#define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/
+
+
+#define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */
+
+ /* ldo sleep voltage */
+#define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/
+#define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */
+#define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/
+#define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */
+#define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */
+
+ /* ldo mode */
+#define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/
+#define ZX234290_REG_ADDR_LDO5678_MODE 0x1F
+#define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */
+
+ /* ldo enable */
+#define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */
+#define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/
+
+ /* adc code */
+#define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/
+#define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/
+#define ZX234290_REG_ADDR_ADC1_MSB 0x25
+#define ZX234290_REG_ADDR_ADC1_LSB 0x26
+#define ZX234290_REG_ADDR_ADC2_MSB 0x27
+#define ZX234290_REG_ADDR_ADC2_LSB 0x28
+
+ /* sink control */
+#define ZX234297_REG_ADDR_SINK_CONTROL 0x29
+
+ /* rtc */
+#define ZX234290_REG_ADDR_RTC_CTRL1 0x30
+#define ZX234290_REG_ADDR_RTC_CTRL2 0x31
+
+ /* date and time */
+#define ZX234290_REG_ADDR_SECONDS 0x32
+#define ZX234290_REG_ADDR_MINUTES 0x33
+#define ZX234290_REG_ADDR_HOURS 0x34
+#define ZX234290_REG_ADDR_DAY 0x35
+#define ZX234290_REG_ADDR_WEEK 0x36
+#define ZX234290_REG_ADDR_MONTH 0x37
+#define ZX234290_REG_ADDR_YEAR 0x38
+
+ /* alarm */
+#define ZX234290_REG_ADDR_ALARM_MINUTE 0x39
+#define ZX234290_REG_ADDR_ALARM_HOUR 0x3A
+#define ZX234290_REG_ADDR_ALARM_DAY 0x3B
+#define ZX234290_REG_ADDR_ALARM_WEEK 0x3C
+#define ZX234290_REG_ADDR_ALARM_SECOND 0x3D
+
+#define ZX234290_REG_ADDR_TIMER_CTRL 0x3E
+#define ZX234290_REG_ADDR_TIMER_CNT 0x3F
+
+ /* enable ldo output discharge resistance */
+#define ZX234290_REG_ADDR_EN_DISCH1 0x40
+#define ZX234290_REG_ADDR_EN_DISCH2 0x41
+
+ /* power key control */
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43
+
+#define ZX234290_REG_ADDR_VERSION 0x44
+
+ /*fault status*/
+#define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45
+#define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46
+
+#define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47
+#define ZX234290_REG_ADDR_LDO_INT_MASK 0x48
+
+#define ZX234290_REG_ADDR_USER_RESERVED 0x50
+#define ZX234290_REG_ADDR_GMT_TESTING 0xf1
+
+#define ZX234290_MAX_REGISTER 0x51 //yuxiang ?
+
+/*0x04 status A*/
+#define ZX234290_STATUSA_POWERON_LSH (5)
+#define ZX234290_STATUSA_POWERON_WID (1)
+#define ZX234290_STATUSA_EOCADC_LSH (2)
+#define ZX234290_STATUSA_EOCADC_WID (1)
+
+/* 0x06 STATUS REG -- STARTUP */
+#define ZX234290_SYSPOR_STATUS_PWRON_STARTUP (0x1 << 0) /* PWR ON button */
+#define ZX234290_SYSPOR_STATUS_RTC_ALARM_STARTUP (0x1 << 1)
+#define ZX234290_SYSPOR_STATUS_PSHOLD_STARTUP (0x1 << 2)
+#define ZX234290_SYSPOR_STATUS_PWRONLLP_STARTUP (0x1 << 3)
+
+/* discharger */
+#define ZX234290_DISCHG1_LSB_LSH (0)
+#define ZX234290_DISCHG1_LSB_WID (4)
+
+#define ZX234290_DISCHG1_MSB_LSH (5)
+#define ZX234290_DISCHG1_MSB_WID (2)
+
+#define ZX234290_DISCHG2_LSH (0)
+#define ZX234290_DISCHG2_WID (8)
+
+
+/* BUCK VOLTAGE */
+#define ZX234290_BUCK01_VSEL_LSH (0)
+#define ZX234290_BUCK01_VSEL_WID (6)
+
+/* BUCK SLEEP VOLTAGE */
+#define ZX234290_BUCK01_SLEEP_VSEL_LSH (0)
+#define ZX234290_BUCK01_SLEEP_VSEL_WID (6)
+
+/* BUCKS MODE CTROL */
+#define ZX234290_REGULATOR_MODE_WID (2)
+
+#define ZX234290_BUCK0_SLPMODE_LSH (0)
+#define ZX234290_BUCK0_NRMMODE_LSH (2)
+#define ZX234290_BUCK1_SLPMODE_LSH (4)
+#define ZX234290_BUCK1_NRMMODE_LSH (6) /*[7:6]*/
+#define ZX234290_BUCK2_SLPMODE_LSH (0)
+#define ZX234290_BUCK2_NRMMODE_LSH (2)
+#define ZX234290_BUCK3_SLPMODE_LSH (4)
+#define ZX234290_BUCK3_NRMMODE_LSH (6)
+#define ZX234290_BUCK4_SLPMODE_LSH (0)
+#define ZX234290_BUCK4_NRMMODE_LSH (2)
+
+/* LDO MODE, ONLY SLEEP MODE */
+#define ZX234290_LDO1_SLPMODE_LSH (0)
+#define ZX234290_LDO2_SLPMODE_LSH (2)
+#define ZX234290_LDO3_SLPMODE_LSH (4)
+#define ZX234290_LDO4_SLPMODE_LSH (6)
+#define ZX234290_LDO5_SLPMODE_LSH (0)
+#define ZX234290_LDO6_SLPMODE_LSH (2)
+#define ZX234290_LDO7_SLPMODE_LSH (4)
+#define ZX234290_LDO8_SLPMODE_LSH (6)
+#define ZX234290_LDO9_SLPMODE_LSH (2)
+#define ZX234290_LDO10_SLPMODE_LSH (4)
+//#define ZX234290_LDO11_SLPMODE_LSH (6)
+
+/* LDO VOLTAGE SELECT */
+#define ZX234290_LDO_VSEL_WID (4)
+
+#define ZX234290_LDO1_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_VSEL_LSH (0)
+#define ZX234290_LDO4_VSEL_LSH (4)
+#define ZX234290_LDO5_VSEL_LSH (0)
+#define ZX234290_LDO6_VSEL_LSH (4)
+#define ZX234290_LDO7_VSEL_LSH (0)
+#define ZX234290_LDO8_VSEL_LSH (4)
+#define ZX234290_LDO9_VSEL_LSH (4)
+#define ZX234290_LDO10_VSEL_LSH (0)
+#define ZX234290_LDO11_VSEL_LSH (0) /* [3:0] */
+
+#define ZX234290_VORTC_VSEL_WID (2)
+#define ZX234290_VORTC_VSEL_LSH (4) /* [5][4] */
+#define ZX234290_LDO5_VSEL_WID (2) /* [1][0]*/
+
+
+/* LDO SLEEP VOLTAGE */
+#define ZX234290_BUCK2_VSEL_WID (5)
+
+#define ZX234290_BUCK2_VSEL_LSH (0)
+
+#define ZX234290_LDO1_SLP_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_SLP_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_SLP_VSEL_LSH (0)
+#define ZX234290_LDO7_SLP_VSEL_LSH (0)
+#define ZX234290_LDO8_SLP_VSEL_LSH (0)
+#define ZX234290_LDO11_SLP_VSEL_LSH (0) /* [3:0] */
+
+/* ENABLE 0x21-0x22 */
+#define ZX234290_LDOS_ON_WID (1)
+
+#define ZX234290_LDO1_ON_LSH (0)
+#define ZX234290_LDO2_ON_LSH (1)
+#define ZX234290_LDO3_ON_LSH (2)
+#define ZX234290_LDO4_ON_LSH (3)
+#define ZX234290_LDO5_ON_LSH (4)
+#define ZX234290_LDO6_ON_LSH (5)
+#define ZX234290_LDO7_ON_LSH (6)
+#define ZX234290_LDO8_ON_LSH (7)
+
+#define ZX234290_LDO9_ON_LSH (1)
+#define ZX234297_LDO9_ON_LSH (0)
+#define ZX234290_LDO10_ON_LSH (2)
+#define ZX234297_LDO10_ON_LSH (1)
+#define ZX234290_BUCK1_ON_LSH (4)
+#define ZX234290_BUCK2_ON_LSH (5)
+#define ZX234290_BUCK3_ON_LSH (6)
+#define ZX234290_BUCK4_ON_LSH (7)
+
+/* LONG PRESSED TIME */
+#define ZX234290_PWRON_TIME_LSH (0)
+#define ZX234290_PWRON_TIME_WID (2)
+#define ZX234290_PWRON_LONGPRESS_EN_LSH (2)
+#define ZX234290_PWRON_LONGPRESS_EN_WID (1)
+#define ZX234290_PWRON_LLP_TODO_LSH (3) /* LLP long long pressed */
+#define ZX234290_PWRON_LLP_TODO_WID (1)
+
+/* sys ctrol 0x07 */
+#define ZX234290_SINK1_EN_LSH (0)
+#define ZX234290_SINK1_EN_WID (1)
+#define ZX234290_SINK2_EN_LSH (1)
+#define ZX234290_SINK2_EN_WID (1)
+#define ZX234290_ADC1_EN_LSH (4)
+#define ZX234290_ADC1_EN_WID (1)
+#define ZX234290_ADC2_EN_LSH (3)
+#define ZX234290_ADC2_EN_WID (1)
+#define ZX234290_ADC_START_LSH (5)
+#define ZX234290_ADC_START_WID (1)
+#define ZX234290_SOFTON_LSH (7)
+
+/* 0x08 */
+#define ZX234290_SINK2_CURSEL_LSH (0)
+#define ZX234290_SINK2_CURSEL_WID (4)
+/* 0x09 */
+#define ZX234290_SINK1_CURSEL_LSH (0)
+#define ZX234290_SINK1_CURSEL_WID (4)
+
+/* 0x20 */
+#define ZX234297_SINK1_SLP_MODE_LSH (6)
+#define ZX234297_SINK2_SLP_MODE_LSH (7)
+#define ZX234297_SINK_SLP_MODE_WID (1)
+/* 0x22 */
+#define ZX234297_SINK1_ON_LSH (2)
+#define ZX234297_SINK2_ON_LSH (3)
+#define ZX234297_SINK_ON_WID (1)
+/* 0x29 */
+#define ZX234297_SINK1_CURRENT_LSH (0)
+#define ZX234297_SINK2_CURRENT_LSH (4)
+#define ZX234297_SINK_CURRENT_WID (4)
+
+#define ZX234290_LDO_RSTERR_LSH (0)
+#define ZX234290_LDO_RSTERR_WID (1)
+
+#endif /* end of ZX234290 */
+
+#define ZX234290_BITFVAL(var, lsh) ( (var) << (lsh) )
+#define ZX234290_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) )
+#define ZX234290_BITFEXT(var, wid, lsh) ((var & ZX234290_BITFMASK(wid, lsh)) >> (lsh))
+
+/* VBA - BUCK1 6bit */
+typedef enum _T_ZDrvZx234290_VbuckA
+{
+ VBUCKA_0_675 = 0x00,
+ VBUCKA_0_700 = 0x02,
+ VBUCKA_0_750 = 0x06,
+ VBUCKA_0_800 = 0x0a,
+ VBUCKA_0_850 = 0x0e,
+ VBUCKA_0_900 = 0x12,/*default*/
+ VBUCKA_0_950 = 0x16,
+ VBUCKA_1_000 = 0x1a,
+ VBUCKA_1_050 = 0x1e,
+ VBUCKA_1_100 = 0x22,
+ VBUCKA_1_150 = 0x26,
+ VBUCKA_1_200 = 0x2a,
+ VBUCKA_1_250 = 0x2e,
+
+ VBUCKA_MAX
+
+}T_ZDrvZx234290_VbuckA;
+
+/* VBC - BUCK2 */
+typedef enum _T_ZDrvZx234290_VbuckC
+{
+ VBUCKC_0_850 = 0x00,
+ VBUCKC_0_900 = 0x02,
+ VBUCKC_0_950 = 0x04,
+ VBUCKC_1_000 = 0x06,
+ VBUCKC_1_050 = 0x08,
+ VBUCKC_1_100 = 0x0a,
+ VBUCKC_1_150 = 0x0c,
+ VBUCKC_1_200 = 0x0e,/*default*/
+ VBUCKC_1_250 = 0x10,
+ VBUCKC_1_300 = 0x12,
+ VBUCKC_1_350 = 0x14,
+ VBUCKC_1_400 = 0x16,
+ VBUCKC_1_450 = 0x18,
+ VBUCKC_1_500 = 0x1a,
+ VBUCKC_1_550 = 0x1c,
+ VBUCKC_1_600 = 0x1e,
+
+ VBUCKC_MAX
+
+}T_ZDrvZx234290_VbuckC;
+
+/* VLA - ldo1/9/10 */
+typedef enum _T_ZDrvZx234290_VldoA
+{
+ VLDOA_0_725 = 0,
+ VLDOA_0_750 = 1,
+ VLDOA_0_775 = 2,
+ VLDOA_0_800 = 3,
+ VLDOA_0_825 = 4,
+ VLDOA_0_850 = 5,
+ VLDOA_0_875 = 6,
+ VLDOA_0_900 = 7,
+ VLDOA_0_925 = 8,
+ VLDOA_0_950 = 9,
+ VLDOA_0_975 = 10,
+ VLDOA_1_000 = 11,
+ VLDOA_1_025 = 12,
+ VLDOA_1_050 = 13,
+ VLDOA_1_075 = 14,
+ VLDOA_1_100 = 15,
+
+ VLDOA_MAX
+
+}T_ZDrvZx234290_VldoA;
+
+/* VLB - ldo5 2bit */
+typedef enum _T_ZDrvZx234290_VldoB
+{
+ VLDOB_3_300 = 0,
+ VLDOB_3_150 = 1,
+ VLDOB_3_000 = 2,
+ VLDOB_1_800 = 3, /* 11 */
+
+ VLDOB_MAX
+
+}T_ZDrvZx234290_VldoB;
+
+/* VLC - ldo2/ldo3 */
+typedef enum _T_ZDrvZx234290_VldoC
+{
+ VLDOC_0_750 = 0,
+ VLDOC_0_800 = 1,
+ VLDOC_0_850 = 2,
+ VLDOC_0_900 = 3,
+ VLDOC_0_950 = 4,
+ VLDOC_1_000 = 5,
+ VLDOC_1_050 = 6,
+ VLDOC_1_100 = 7,
+ VLDOC_1_200 = 8,
+ VLDOC_1_500 = 9,
+ VLDOC_1_800 = 10,
+ VLDOC_2_000 = 11,
+ VLDOC_2_500 = 12,
+ VLDOC_2_800 = 13,
+ VLDOC_3_000 = 14,
+ VLDOC_3_300 = 15,
+
+ VLDOC_MAX
+
+}T_ZDrvZx234290_VldoC;
+
+/* VLD - ldo4/6/7/8 */
+typedef enum _T_ZDrvZx234290_VldoD
+{
+ VLDOD_1_400 = 0,
+ VLDOD_1_500 = 1,
+ VLDOD_1_600 = 2,
+ VLDOD_1_800 = 3,
+ VLDOD_1_850 = 4,
+ VLDOD_2_000 = 5,
+ VLDOD_2_050 = 6,
+ VLDOD_2_500 = 7,
+ VLDOD_2_550 = 8,
+ VLDOD_2_700 = 9,
+ VLDOD_2_750 = 10,
+ VLDOD_2_800 = 11,
+ VLDOD_2_850 = 12,
+ VLDOD_2_900 = 13,
+ VLDOD_2_950 = 14,
+ VLDOD_3_000 = 15,
+
+ VLDOD_MAX
+
+}T_ZDrvZx234290_VldoD;
+
+/* VORTC 2bit */
+typedef enum _T_ZDrvZx234290_VldoE
+{
+ VLDOE_1_800 = 0,
+ VLDOE_2_500 = 1,
+ VLDOE_3_000 = 2,
+ VLDOE_3_300 = 3, /* 11 */
+
+ VLDOE_MAX
+
+}T_ZDrvZx234290_VldoE;
+
+/* VLF - ldo10 */
+typedef enum _T_ZDrvZx234297_VldoF
+{
+ VLDOF_0_800 = 0,
+ VLDOF_0_850 = 1,
+ VLDOF_0_900 = 2,
+ VLDOF_0_950 = 3,
+
+ VLDOF_1_000 = 4,
+ VLDOF_1_050 = 5,
+ VLDOF_1_100 = 6,
+ VLDOF_1_200 = 7,
+
+ VLDOF_1_300 = 8,
+ VLDOF_1_400 = 9,
+ VLDOF_1_500 = 10,
+ VLDOF_1_800 = 11,
+
+ VLDOF_2_500 = 12,
+ VLDOF_2_800 = 13,
+ VLDOF_3_000 = 14,
+ VLDOF_3_300 = 15,
+
+ VLDOF_MAX
+
+}T_ZDrvZx234297_VldoF;
+
+/* BUCK3/4 EXTERNAL ADJUSTABLE */
+
+typedef enum _T_ZDrvZx234290_LDO_ENABLE
+{
+ LDO_ENABLE_OFF = 0, /* 00 */
+ LDO_ENABLE_ON = 1, /* 10 */
+
+ LDO_AVTICE_MAX
+}T_ZDrvZx234290_LDO_ENABLE;
+
+
+/*
+ ¹ØÓÚ BUCKSµÄģʽ£¬·ÖΪÕý³£Ä£Ê½Óë˯Ãßģʽ£¬ Õý³£Ä£Ê½Ö»¹Ø×¢PFM/PWM£¬²»¹Ø×¢¿ª¹Ø¡£
+ ˯Ãßģʽ¹Ø×¢PFM/PWM/ECO/OFF/NRM£¬Ó¦¸Ã½âÊÍΪ ˯ÃßģʽµÄ״̬²»½ö¹Ø×¢PWM/PFM£¬
+ ¶øÇÒ¹Ø×¢´ò¿ª¹Ø±Õ£¬³ýÁËOFF£¬ÆäËû¶¼ÊÇÔÚ¿ª×ŵÄÇé¿öϵÄģʽ£»¶øĬÈÏ¿ªµÄÇé¿öÔòÊÇ
+ NRMMODE£¬µçѹÓÃ˯Ãßµçѹ£»
+ ¶øLDOSµÄ˯Ãßģʽ£¬Ò»ÑùÓëÕý³£Ä£Ê½²»Ïà¸É¡£ÆäÒ²ÓÐNRM/ECO/OFFÕ⼸ÖÖ״̬
+*/
+
+/* BUCK1/2/3/4 NORMAL MODE */
+typedef enum _T_ZDrvZx234290_BUCK_NRMMODE
+{
+ BUCK_NRM_AUTO_WITH_ECO = 0, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRM_FORCE_PWM = 2, /* 10 FORCE PWM */
+ BUCK_NRM_AUTO_WITHOUT_ECO = 3, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRMMODE_MAX
+}T_ZDrvZx234290_BUCK_NRMMODE;
+
+/* BUCK1 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK1_SLPMODE
+{
+ BUCK1_SLP_AUTO_WITHOUT_ECO = 0, /* 00/11 AUTO PWM/PFM */
+ BUCK1_SLP_AUTO_ECO = 1, /*BUCK1_SLP_AUTO_ECO_VOLT output voltage configred by FBDC1[5:0]*/
+ BUCK1_SLP_AUTO_ECO_SLP = 2, /* output voltage configred by FBDC1_SLP[5:0]*/
+ BUCK1_SLP_SHUTDOWN = 3, /* 11 OFF */
+ BUCK1_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK1_SLPMODE;
+
+/* BUCK2/3/4 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK234_SLPMODE
+{
+ BUCK234_SLP_AUTO_WITHOUT_ECO = 0, /* 00 AUTO PWM/PFM without eco*/
+ BUCK234_SLP_ECO_WITH_ECO = 1, /* 01Óë10¾ùÊÇ ECO */
+ BUCK234_SLP_SHUTDOWN = 3, /* 11 OFF */
+
+ BUCK234_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK234_SLPMODE;
+
+/* LDO1/2/3/7/8/9/10 SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOA_SLPMODE
+{
+ LDOA_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT_SLP = 2, /* VOLDOx_SLP[3:0] */
+ LDOA_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOA_SLPMODE_MAX
+}T_ZDrvZx234290_LDOA_SLPMODE;
+
+/* LDO4/5/6/ SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOB_SLPMODE
+{
+ LDOB_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOB_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOB_SLP_NRM_MODE_VOLT = 2, /* VOLDOx[3:0] */
+ LDOB_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOB_SLPMODE_MAX
+}T_ZDrvZx234290_LDOB_SLPMODE;
+
+typedef enum _T_ZDrvZx234290_LdoDischarger
+{
+ DISCHARGER_LDO_9 = 0,
+ DISCHARGER_LDO_10,
+ DISCHARGER_LDO_X, /*not support*/
+ DISCHARGER_BUCK_4,
+ DISCHARGER_BUCK_3,
+ DISCHARGER_BUCK_2,
+ DISCHARGER_BUCK_1,
+ DISCHARGER_BUCK_X, /*not support*/
+
+ DISCHARGER_LDO_1,
+ DISCHARGER_LDO_2,
+ DISCHARGER_LDO_3,
+ DISCHARGER_LDO_4,
+ DISCHARGER_LDO_5,
+ DISCHARGER_LDO_6,
+ DISCHARGER_LDO_7,
+ DISCHARGER_LDO_8,
+
+ DISCHARGER_MAX
+}T_ZDrvZx234290_LdoDischarger;
+
+typedef enum _T_ZDrvZx234290_DISCHARGER_ENABLE
+{
+ DISCHARGER_DISBALE = 0, /* 00 */
+ DISCHARGER_ENABLE = 1, /* 10 */
+
+ DISCHARGER_ENABLE_MAX
+}T_ZDrvZx234290_DISCHARGER_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LdoList
+{
+ LDOLIST_BUCK_1 = 0,
+ LDOLIST_BUCK_2,
+ LDOLIST_BUCK_3,
+ LDOLIST_BUCK_4,
+ LDOLIST_LDO_1,
+ LDOLIST_LDO_2,
+ LDOLIST_LDO_3,
+
+ LDOLIST_LDO_4,
+ LDOLIST_LDO_5,
+ LDOLIST_LDO_6,//default off
+ LDOLIST_LDO_7,
+ LDOLIST_LDO_8,
+ LDOLIST_LDO_9,//default off
+ LDOLIST_LDO_10,
+ LDOLIST_LDO_RTC,
+
+ LDOLIST_MAX
+}T_ZDrvZx234290_LdoList;
+
+typedef enum _T_ZDrvZx234297_SINK
+{
+ ZX234297_SINK1 = 0, /* 00 */
+ ZX234297_SINK2 = 1, /* 10 */
+
+ ZX234297_SINK_MAX
+}T_ZDrvZx234297_SINK;
+
+typedef enum _T_ZDrvZx234297_SINK_SLPMODE
+{
+ SLPMODE_NORMAL = 0, /* 00 */
+ SLPMODE_SHUTDOWN = 1, /* 10 */
+
+ SLPMODE_MAX
+}T_ZDrvZx234297_SINK_SLPMODE;
+
+typedef enum _T_ZDrvZx234297_SINK_CURRENT
+{
+ SINK_CURRENT_5MA,
+ SINK_CURRENT_10MA,
+ SINK_CURRENT_15MA,
+ SINK_CURRENT_20MA,
+ SINK_CURRENT_30MA,
+ SINK_CURRENT_40MA,
+ SINK_CURRENT_50MA,
+ SINK_CURRENT_60MA,
+ SINK_CURRENT_70MA,
+ SINK_CURRENT_80MA,
+ SINK_CURRENT_90MA,
+ SINK_CURRENT_100MA,
+ SINK_CURRENT_110MA,
+ SINK_CURRENT_120MA,
+
+ SINK_CURRENT_MAX
+}T_ZDrvZx234297_SINK_CURRENT;
+
+typedef enum _T_ZDrvZx234290_ResetType
+{
+#if 0
+ ZX234290_USER_RST_UNDEFINE = 0,
+ ZX234290_USER_RST_TO_NORMAL = 1,
+ ZX234290_USER_RST_TO_CHARGER = 2,
+ ZX234290_USER_RST_TO_ALARM = 3,
+#else
+ ZX234290_USER_RST_UNDEFINE = 3,
+ ZX234290_USER_RST_TO_NORMAL = 0,
+ ZX234290_USER_RST_TO_CHARGER = 1,
+ ZX234290_USER_RST_TO_ALARM = 2,
+#endif
+ ZX234290_USER_RST_TO_EXCEPT = 4,
+
+ ZX234290_USER_RST_MAX
+}T_ZDrvZx234290_ResetType;
+
+
+int zx234290_get_chip_version(void);
+int zx234290_irq_init(struct zx234290 *zx234290);
+
+int zx234290_set_buck1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_buck1_onoff(void);
+int zx234290_set_buck1_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+T_ZDrvZx234290_BUCK_NRMMODE zx234290_get_buck1_active_mode(void);
+int zx234290_set_buck1_voltage(T_ZDrvZx234290_VbuckA vol);
+T_ZDrvZx234290_VbuckA zx234290_get_buck1_voltage(void);
+int zx234290_set_buck1_sleep_mode(T_ZDrvZx234290_BUCK1_SLPMODE status);
+T_ZDrvZx234290_BUCK1_SLPMODE zx234290_get_buck1_sleep_mode(void);
+int zx234290_set_buck1_sleep_voltage(T_ZDrvZx234290_VbuckA vol);
+
+int zx234290_set_buck2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck2_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck2_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+int zx234290_set_buck3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck3_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck3_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+int zx234290_set_buck4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck4_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck4_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+
+int zx234290_set_ldo1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo1_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo1_onoff(void);
+int zx234290_set_ldo1_voltage(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA zx234290_get_ldo1_voltage(void);
+int zx234290_set_ldo1_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo1_sleep_mode(void);
+
+
+int zx234290_set_ldo2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo2_onoff(void);
+int zx234290_set_ldo2_voltage(T_ZDrvZx234290_VldoC vol);
+T_ZDrvZx234290_VldoC zx234290_get_ldo2_voltage(void);
+int zx234290_set_ldo2_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo2_sleep_mode(void);
+
+int zx234290_set_ldo3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo3_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo4_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+
+
+int zx234290_set_ldo5_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo5_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo5_onoff(void);
+int zx234290_set_ldo5_voltage(T_ZDrvZx234290_VldoB vol);
+T_ZDrvZx234290_VldoB zx234290_get_ldo5_voltage(void);
+int zx234290_set_ldo5_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo5_sleep_mode(void);
+
+int zx234290_set_ldo6_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo6_onoff(void);
+int zx234290_set_ldo6_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo6_voltage(void);
+int zx234290_set_ldo6_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo6_sleep_mode(void);
+
+int zx234290_set_ldo7_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo7_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo8_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo8_onoff(void);
+int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo8_voltage(void);
+int zx234290_set_ldo8_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo8_sleep_mode(void);
+int zx234290_set_ldo9_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo9_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo10_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo10_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo10_onoff(void);
+T_ZDrvZx234297_VldoF zx234290_get_ldo10_voltageF(void);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo10_sleep_mode(void);
+int zx234297_set_ldo10_voltageF(T_ZDrvZx234297_VldoF vol);
+
+int zDrvPmic_SetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Onoff_PSM(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_SetSleep_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_GetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable* enable);
+int zDrvPmic_GetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int* voltage);
+
+
+/*adc fun*/
+uint get_battery_voltage(void);
+uint get_adc1_voltage(void);
+uint get_adc2_voltage(void);
+
+
+#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/upstream/linux-5.10/include/linux/mmc/mmc_func.h b/upstream/linux-5.10/include/linux/mmc/mmc_func.h
new file mode 100755
index 0000000..b2636ab
--- /dev/null
+++ b/upstream/linux-5.10/include/linux/mmc/mmc_func.h
@@ -0,0 +1,37 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2014, ÉîÛÚÊÐÖÐÐËͨѶ΢µç×Ó
+*
+* ÎļþÃû³Æ£º emmc_ramdump.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+
+
+#ifndef LINUX_MMC_MMC_FUNC_H
+#define LINUX_MMC_MMC_FUNC_H
+
+#include <linux/types.h>
+
+int mmc_ramdump_init(void);
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file stored;
+*/
+int mmc_bwrite(u32 start_addr, u32 data_size, void *src_buf);
+
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file will store;
+*/
+
+int mmc_bread(u32 start_addr, u32 data_size, void *dst);
+
+#endif /* LINUX_MMC_MMC_FUNC_H */
diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c b/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
new file mode 100755
index 0000000..bcb6a53
--- /dev/null
+++ b/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
@@ -0,0 +1,457 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_client_cap.c
+* Îļþ±êʶ: ramdump_client_cap.c
+* ÄÚÈÝÕªÒª: ramdump cap¿Í»§¶ËÒì³£ËÀ»úÏÖ³¡Êý¾Ýµ¼³öʵÏÖ
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2019/10/10 V1.0 Create 00130574 ´´½¨
+*
+*******************************************************************************/
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_arch.h"
+#include <linux/module.h>
+#include <linux/soc/zte/rpmsg.h>
+#include "ram_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* ³£Á¿¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* º¯ÊýÉùÃ÷ *
+*******************************************************************************/
+extern void ramdump_register_callbacks(void);
+extern unsigned char *ramdump_phy_to_vir(unsigned long phy, unsigned long size);
+extern void ramdump_shared_mem_init(void);
+extern void ramdump_data_transfer_to_device(void);
+extern void ramdump_oss_data_trans_init(void);
+extern unsigned char *ramdump_export_flag_base;
+
+/*******************************************************************************
+* ¾Ö²¿¾²Ì¬±äÁ¿¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_ON_DEFAULT_VAL (1)
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿¶¨Òå *
+*******************************************************************************/
+/*
+ * run time control dump or not, use ( echo "0" > ramdump_on ) to close ramdump
+ */
+int sysctl_ramdump_on_panic = RAMDUMP_ON_DEFAULT_VAL;
+int ramdump_cap_init_flag = -1;
+int ramdump_count = 0;
+int ramdump_server_exp_core = RAMDUMP_FALSE;
+#ifdef CONFIG_RAMDUMP_USER
+unsigned int sysctl_ramdump_on_user = 1;
+#endif
+unsigned int ramdump_export_mode = 0xFF;
+/* Cmm file content */
+unsigned char *ramdump_cap_cmm_buf = NULL;
+/* err log file */
+unsigned char *ramdump_cap_error_log = NULL;
+unsigned int *cap_ddr_len_base = NULL;
+unsigned int sysctl_ramdump_emmc_size = 0x0;
+unsigned int sysctl_ramdump_emmc_start_addr = 0xFFFF;
+
+static struct ctl_table cfg_ramdump_array[] = {
+#ifdef CONFIG_RAMDUMP_USER
+ {
+ .procname = "sysctl_ramdump_on_user",
+ .data = &sysctl_ramdump_on_user,
+ .maxlen = sizeof(sysctl_ramdump_on_user),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ .extra1 = SYSCTL_ZERO,
+ .extra2 = SYSCTL_ONE,
+ },
+#endif
+ {
+ .procname = "ramdump_start_addr",
+ .data = &sysctl_ramdump_emmc_start_addr,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ },
+ {
+ .procname = "ramdump_emmc_size",
+ .data = &sysctl_ramdump_emmc_size,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_doulongvec_minmax,
+ },
+
+ { }
+};
+
+static struct ctl_table sysctl_ramdump_table[] = {
+ {
+ .procname = "ramdump_ap",
+ .mode = 0555,
+ .child = cfg_ramdump_array,
+ },
+ { }
+};
+
+/*******************************************************************************
+* ¾Ö²¿º¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_handle
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) buf: icp msg addr
+* len: icp msg len
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp msg handle, common entry
+*******************************************************************************/
+static void ramdump_cap_icp_handle(void *buf, unsigned int len)
+{
+ ramdump_msg_t *icp_msg = (ramdump_msg_t *)buf;
+
+ ramdump_server_exp_core = RAMDUMP_SUCCESS;
+
+ switch(icp_msg->msg_id)
+ {
+ case RAMDUMP_MSG_EXCEPT:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+
+ default:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_create_channel
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ size: icp channel size
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_create_channel(T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
+{
+ return rpmsgCreateChannel(dstCoreID, chID, size);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_regcallback
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ callback:icp callback fun
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_regcallback (T_RpMsg_CoreID coreID, unsigned int chID, T_RpMsg_Callback callback)
+{
+ return rpmsgRegCallBack(coreID, chID, callback);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init_sysctl_table
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ×¢²ásysctlÃüÁÓû§Ì¬Ê¹ÓÃsysctl¿ØÖÆramdump´æ´¢µØÖ·
+*******************************************************************************/
+void ramdump_init_sysctl_table(void)
+{
+ register_sysctl_table(sysctl_ramdump_table);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp init
+*******************************************************************************/
+static int ramdump_cap_icp_init(void)
+{
+ int ret = 0;
+
+ ret = ramdump_cap_icp_create_channel(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ RAMDUMP_CHANNEL_SIZE);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ ret = ramdump_cap_icp_regcallback(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ ramdump_cap_icp_handle);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_notify_server_panic
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for cap notify ramdump server to panic
+*******************************************************************************/
+static int ramdump_notify_server_panic(void)
+{
+ int ret = 0;
+ T_RpMsg_Msg rpMsg = {0};
+ ramdump_msg_t ramdumpMsg = {0};
+
+ ramdumpMsg.msg_id = RAMDUMP_MSG_EXCEPT;
+ ramdumpMsg.cpu_id = CORE_AP;
+
+ rpMsg.coreID = RAMDUMP_SERVER_AP;
+ rpMsg.chID = RAMDUMP_CHANNEL;
+ rpMsg.flag = RPMSG_WRITE_INT | RPMSG_WRITE_IRQLOCK;
+ rpMsg.len = sizeof(ramdump_msg_t);
+ rpMsg.buf = &ramdumpMsg;
+
+ ret = rpmsgWrite(&rpMsg);
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_store_ram_conf
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) mem: addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: unsigend char*: changed addr
+* ÆäËü˵Ã÷: This function is used to store ram conf
+*******************************************************************************/
+static unsigned char *ramdump_cap_store_ram_conf(unsigned char *mem)
+{
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_ddr.bin",
+ (unsigned int)DDR_BASE_CAP_ADDR_PA,
+ (unsigned int)(DDR_BASE_CAP_ADDR_PA + *cap_ddr_len_base - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap.cmm",
+ (unsigned int)RAMDUMP_CAP_CMM_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_CMM_BUF_ADDR + RAMDUMP_CAP_CMM_BUF_LEN_REAL - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_err_log.txt",
+ (unsigned int)RAMDUMP_CAP_LOG_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_LOG_BUF_ADDR + RAMDUMP_CAP_LOG_BUF_LEN - 1));
+ return mem;
+}
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_cmm_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for server to generate cmm scripts
+*******************************************************************************/
+static void ramdump_cap_cmm_create(void)
+{
+ unsigned char *pcmm_buf = ramdump_cap_cmm_buf;
+
+ memset(ramdump_cap_cmm_buf, 0, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+
+ // store the cmm BEGIN
+ pcmm_buf += sprintf(pcmm_buf, "ENTRY &ramdump_dir\n");
+
+ // store procmodes regs
+ pcmm_buf = ramdump_arch_store_modes_regs(pcmm_buf);
+
+ // store ram config
+ pcmm_buf = ramdump_cap_store_ram_conf(pcmm_buf);
+
+ // store memory map control regs
+ pcmm_buf = ramdump_arch_store_mm_regs(pcmm_buf);
+
+ // store end symbol
+ pcmm_buf += sprintf(pcmm_buf, "ENDDO\n");
+
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_trans_cap_error_log_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to create err log file
+*******************************************************************************/
+static void ramdump_cap_error_log_create(void)
+{
+ unsigned char *buf = ramdump_cap_error_log;
+
+ memset(ramdump_cap_error_log, 0, RAMDUMP_CAP_LOG_BUF_LEN);
+ buf += sprintf(buf, "dump at core%d,", smp_processor_id());
+ if (current->mm != NULL)
+ buf += sprintf(buf, "in user,task is: %s\n", current->comm);
+ else
+ buf += sprintf(buf, "in kernel,task is: %s\n", current->comm);
+
+ if (ramdump_server_exp_core)
+ buf += sprintf(buf, "recv dumpinfo from ap\n");
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_ram_conf_table_add
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) ram_name: dump ram name
+ ram_start: dump ram start(virtual addr)
+ ram_size: dump ram size
+ ram_virt: dump ram virt addr
+ ram_flag: dump ram flag(copy/exter/callback)
+ ram_extra: dump ram extra access addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to add dump ram conf into public table
+*******************************************************************************/
+void ramdump_ram_conf_table_add(
+ char *ram_name,
+ unsigned long ram_phy,
+ unsigned long ram_size,
+ unsigned long ram_virt,
+ unsigned long ram_flag,
+ unsigned long ram_extra)
+{
+}
+void ramdump_init_cmm_buf(void)
+{
+ /* Cmm file content */
+ ramdump_cap_cmm_buf = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_CMM_BUF_ADDR, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+ /* err log file */
+ ramdump_cap_error_log = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_LOG_BUF_ADDR, RAMDUMP_CAP_LOG_BUF_LEN);
+ cap_ddr_len_base = (unsigned int *)ramdump_phy_to_vir((unsigned long)IRAM_BASE_ADDR_BOOT_DDR, sizeof(unsigned long));
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: RAMDUMP_SUCCESS or RAMDUMP_FAILED
+* ÆäËü˵Ã÷: This function is used for ramdump init
+*******************************************************************************/
+int __init ramdump_init(void)
+{
+ int ret = 0;
+ ramdump_printf("Ramdump cap init start!!!!!\n");
+
+ if (ramdump_cap_init_flag == RAMDUMP_TRUE)
+ return RAMDUMP_SUCCESS;
+ ramdump_printf("Ramdump cap init rpmsg start!!!!!\n");
+ ret = ramdump_cap_icp_init();
+ if (ret != RAMDUMP_ICP_SUCCESS)
+ return ret;
+
+ ramdump_register_callbacks();
+
+ ramdump_init_cmm_buf();
+
+ ramdump_init_sysctl_table();
+
+ ramdump_shared_mem_init();
+ ramdump_oss_data_trans_init();
+
+ ramdump_printf("Ramdump cap init success!\n");
+ ramdump_cap_init_flag = RAMDUMP_TRUE;
+
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_entry
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump entry
+*******************************************************************************/
+void ramdump_entry (void)
+{
+ unsigned long flags;
+ if (sysctl_ramdump_on_panic == false)
+ return;
+
+ /*
+ * we need lock the irq, this can`t be interrupt.
+ */
+ ramdump_irq_lock(flags);
+
+ if (!ramdump_cap_init_flag)
+ while(true); /* endless circle */
+
+ if (++ramdump_count > 1)
+ while(true); /* endless circle */
+
+ /*
+ * save all regs first.
+ */
+ ramdump_arch_save_all_regs();
+ // generate error log
+ ramdump_cap_error_log_create();
+
+ //Éú³Écmm½Å±¾µÄµ¼³öÅäÖÃ
+ ramdump_cap_cmm_create();
+
+ /* notify client ramdump */
+ ramdump_notify_server_panic();
+
+ ramdump_arch_clean_caches();
+ ramdump_export_mode = *(unsigned int *)ramdump_export_flag_base;
+
+ if((ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ || (ramdump_export_mode == RAMDUMP_MODE_SPINAND))
+ ramdump_data_transfer_to_device();
+
+ while(true)
+ ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
new file mode 100755
index 0000000..0c28f27
--- /dev/null
+++ b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
@@ -0,0 +1,170 @@
+/**
+ * @file oss_ramdump_osa.c
+ * @brief Implementation of Ramdump os adapt
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Qing Wang <wang.qing@sanechips.com.cn>
+ * @ingroup si_ap_oss_ramdump_id
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_emmc.h"
+#include "ram_config.h"
+#include "ramdump_compress.h"
+#include <linux/lzo.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Extern function declarations *
+*******************************************************************************/
+
+/*******************************************************************************
+* Extern variable declarations *
+*******************************************************************************/
+extern unsigned char *ramdump_shared_mem_base;
+extern unsigned char *ramdump_emmc_flag_base;
+extern unsigned int ramdump_compress_flag;
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define RAMDUMP_DELAY_MS_COUNT (2500)
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+unsigned int ramdump_emmc_size = 0;
+volatile unsigned int ramdump_emmc_offset = 0;
+extern unsigned int ramdump_device_file_cnt;
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+static inline void ramdump_wait_delay( unsigned long ms)
+{
+ volatile int j = 0;
+ for (j = 0; j < 10000; j++);
+}
+
+/*******************************************************************************
+ * Local function implementations *
+ ******************************************************************************/
+int ramdump_emmc_init(ramdump_file_t *fp)
+{
+ fp->magic = 0x2A2A2A2A;
+ ramdump_emmc_offset = roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE);
+
+ if(RAMDUMP_TRANS_EMMC_LEN > ramdump_emmc_offset)
+ {
+ ramdump_emmc_size = RAMDUMP_TRANS_EMMC_LEN - ramdump_emmc_offset;
+ }
+ else
+ {
+ printk("[ramdump] emmc start addr is %ld, emmc size= %ld, error: size smaller than ramdump file header, return!\n", sysctl_ramdump_emmc_start_addr, sysctl_ramdump_emmc_size);
+ return -1;
+ }
+
+ if(mmc_ramdump_init()){
+ ramdump_printf("EMMC init failed! No ramdump data trans to emmc!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp)
+{
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+ if (ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
+ return -1;
+
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, file_name, RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+}
+
+int ramdump_emmc_write_file_head(ramdump_file_t *fp)
+{
+ int ret = -1;
+ mmc_bwrite(RAMDUMP_EMMC_ADDR, roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE), fp);
+ return ret;
+}
+
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size)
+{
+ int ret = 0;
+ unsigned int buffer = RAMDUMP_EMMC_ADDR + ramdump_emmc_offset;
+
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+ if(msg->size >= (ramdump_emmc_size - fp->file_fp[ramdump_device_file_cnt].offset))
+ return -1;
+ ret = mmc_bwrite(buffer, msg->size, msg->buf);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(msg->size, RAMDUMP_EMMC_ALIGN_SIZE);
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+ ret = msg->size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+int ramdump_emmc_read(char *buffer, ramdump_shmem_t *msg, unsigned int size)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+void ramdump_emmc_close(ramdump_file_t *fp)
+{
+ fp->file_size = ramdump_emmc_offset;
+ ramdump_emmc_write_file_head(fp);
+ ramdump_printf("ramdump trans emmc finished!\n");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
new file mode 100755
index 0000000..1028ab2
--- /dev/null
+++ b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_emmc.h
+* Îļþ±êʶ: ramdump_emmc.h
+* ÄÚÈÝÕªÒª: ramdump emmcÍ·Îļþ
+* ʹÓ÷½·¨: #include "ramdump_emmc.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2016/3/10 V1.0 Create ÕÔ¾ü¿ü ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAMDUMP_EMMC_H
+#define _RAMDUMP_EMMC_H
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include <linux/mmc/mmc_func.h>
+
+/*******************************************************************************
+* Íⲿ±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+extern unsigned int sysctl_ramdump_emmc_start_addr;
+extern unsigned int sysctl_ramdump_emmc_size;
+extern volatile unsigned int ramdump_emmc_offset;
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_EMMC_ADDR (sysctl_ramdump_emmc_start_addr * 512)
+#define RAMDUMP_TRANS_EMMC_LEN (sysctl_ramdump_emmc_size * 512)
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+/**
+ * @brief ramdump_emmc_init .
+ *
+ * @param void.
+ *
+ * @return int.
+ * @retval standard error
+ * @note This function is used for ramdump init
+ */
+int ramdump_emmc_init(ramdump_file_t *fp);
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp);
+int ramdump_emmc_write_file_head(ramdump_file_t *fp);
+int ramdump_emmc_modify_file_size(ramdump_file_t *fp, unsigned int file_size);
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size);
+int ramdump_emmc_write_logbuf(ramdump_file_t *fp);
+void ramdump_emmc_close(ramdump_file_t *fp);
+int ramdump_emmc_write_log_txt(ramdump_file_t *fp);
+
+/*******************************************************************************
+* ÄÚÁªº¯ÊýʵÏÖ *
+*******************************************************************************/
+
+#endif //#ifndef _RAMDUMP_EMMC_H
+
diff --git a/upstream/linux-5.10/kernel/tracker.c b/upstream/linux-5.10/kernel/tracker.c
new file mode 100755
index 0000000..6f7e1ab
--- /dev/null
+++ b/upstream/linux-5.10/kernel/tracker.c
@@ -0,0 +1,459 @@
+/*
+ * tracker.c - System accounting over taskstats interface
+ *
+ * Copyright (C) Jay Lan, <jlan@sgi.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/export.h>
+#include <linux/sched/clock.h>
+#include "ram_config.h"
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define _OS_LINUX 1
+
+#if defined(_OS_TOS)
+# define OS_STATISTIC_IRAM_BASE (IRAM_BASE_ADDR_OS_STATISTIC_PSCPU)
+# define OS_STATISTIC_TIME zDrvTimer_Stamp()
+#elif defined(_OS_LINUX)
+# define OS_STATISTIC_IRAM_BASE g_zxic_trace_apcpu_addr //(IRAM_BASE_ADDR_OS_STATISTIC_APCPU)
+# define OS_STATISTIC_TIME (cpu_clock(0)>>10)
+#else
+# error "unknown os"
+#endif
+
+
+
+#define OS_IRAM_STATISTIC_CNT (5)
+#define OS_IRAM_STATISTIC_NAME_LEN (16)
+#define OS_DDR_STATISTIC_CNT (1000)
+
+#define OS_IRAM_THREAD_SWAPIN (OS_STATISTIC_IRAM_BASE)
+#define OS_IRAM_IRQ_START (OS_IRAM_THREAD_SWAPIN + sizeof(t_os_iram_thread_statistic))
+#define OS_IRAM_IRQ_END (OS_IRAM_IRQ_START + sizeof(t_os_iram_statistic))
+
+#if defined(_OS_TOS)
+#define OS_IRAM_DSR_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_DSR_END (OS_IRAM_DSR_START + sizeof(t_os_iram_statistic))
+#elif defined(_OS_LINUX)
+#define OS_IRAM_SOFTIRQ_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_SOFTIRQ_END (OS_IRAM_SOFTIRQ_START + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_START (OS_IRAM_SOFTIRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_END (OS_IRAM_TIMER_START + sizeof(t_os_iram_statistic))
+#endif
+
+#define os_statistic_check() *((volatile unsigned long *)OS_STATISTIC_IRAM_BASE)
+#define os_statistic_enabled() g_os_statistic_enable
+
+/*******************************************************************************
+* Êý¾Ý½á¹¹¶¨Òå *
+*******************************************************************************/
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned char name[OS_IRAM_STATISTIC_NAME_LEN];
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_thread_statistic;
+
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_statistic;
+
+typedef struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_DDR_STATISTIC_CNT];
+}t_os_ddr_statistic;
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ *
+*******************************************************************************/
+#if defined(_OS_LINUX)
+volatile static char *g_zxic_trace_apcpu_addr;
+#endif
+
+volatile static int g_os_statistic_enable;
+volatile static unsigned int g_os_statistic_cnt;
+
+volatile static t_os_iram_thread_statistic *g_os_iram_swapin_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_iram_statistic *g_os_iram_dsr_start_statistic;
+static t_os_iram_statistic *g_os_iram_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_iram_statistic *g_os_iram_softirq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_softirq_end_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_end_statistic;
+#endif
+
+volatile static t_os_ddr_statistic *g_os_ddr_swapin_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_ddr_statistic *g_os_ddr_dsr_start_statistic;
+static t_os_ddr_statistic *g_os_ddr_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_end_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_end_statistic;
+#endif
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+void os_statistic_enable(void);
+/*******************************************************************************
+* ¾Ö²¿º¯Êý *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_statistic *iram;
+
+ iram = (t_os_iram_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+ iram->statistics[index].data1 = (unsigned int)data;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: Ï̹߳켣ͳ¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_thread_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_thread_statistic *iram;
+
+ iram = (t_os_iram_thread_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+#if defined(_OS_TOS)
+ strncpy((char *)(iram->statistics[index].name), cyg_thread_get_name((cyg_handle_t)data), OS_IRAM_STATISTIC_NAME_LEN - 1);
+#elif defined(_OS_LINUX)
+ strncpy((char *)(iram->statistics[index].name), ((struct task_struct *)data)->comm, OS_IRAM_STATISTIC_NAME_LEN - 1);
+#else
+# error "unkown os"
+#endif
+ iram->statistics[index].name[OS_IRAM_STATISTIC_NAME_LEN - 1] = 0;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_ddr(void *ddr_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_ddr_statistic *ddr;
+
+ ddr = (t_os_ddr_statistic *)ddr_addr;
+
+ index = ddr->index;
+ if (index >= OS_DDR_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+ ddr->statistics[index].data1 = (unsigned int)data;
+ ddr->statistics[index].data2 = time;
+ index++;
+
+ ddr->index = index;
+ ddr->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_info_update(void)
+{
+ g_os_statistic_cnt++;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¶¨Ê±Æ÷»Øµ÷¹³×Ó
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý)
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static int os_statistic_delayed_work_timer_fn(unsigned long data)
+{
+ int sec = 0;
+ msleep(20000);
+ while(!os_statistic_check())
+ {
+ //³¬¹ý40s£¬Ö±½ÓÍ˳ö
+ if(sec >= 4)
+ return 0;
+ msleep(10000);
+ sec++;
+ }
+ os_statistic_enable();
+ return 0;
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ʹÄܹ켣ͳ¼Æ¹¦ÄÜ
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) address: ¼Ç¼µ½IRAMÖеĵØÖ·
+ size: IRAM¿Õ¼ä´óС
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+void os_statistic_enable(void)
+{
+#if defined(_OS_TOS)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_dsr_start_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_START;
+ g_os_iram_dsr_end_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+#elif defined(_OS_LINUX)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_softirq_start_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_START;
+ g_os_iram_softirq_end_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_END;
+ g_os_iram_timer_start_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_START;
+ g_os_iram_timer_end_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+
+#else
+# error "unkown os"
+#endif
+ if ((unsigned int )g_os_iram_timer_end_statistic - (unsigned int )g_os_iram_swapin_statistic > (unsigned int )IRAM_BASE_LEN_OS_STATISTIC_PSCPU )
+ {
+ BUG();
+ }
+ g_os_statistic_enable = 1;
+}
+EXPORT_SYMBOL(os_statistic_enable);
+
+void zxic_trace_task_switch(struct task_struct *next)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_thread_in_iram(g_os_iram_swapin_statistic, next, time);
+ os_statistic_in_ddr(g_os_ddr_swapin_statistic, next, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_enter(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_start_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_start_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_exit(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_end_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_end_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_enter(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_start_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_start_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_exit(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_end_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_end_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_enter(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_start_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_start_statistic, func, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_exit(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_end_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_end_statistic, func, time);
+ os_statistic_info_update();
+}
+
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+int __init zxic_enable_tracer(void)
+{
+ struct timer_list timer;
+ struct task_struct *task;
+
+#ifdef IRAM_BASE_ADDR_VA
+ g_zxic_trace_apcpu_addr = IRAM_BASE_ADDR_OS_STATISTIC_PSCPU;
+#else
+ g_zxic_trace_apcpu_addr = ioremap(IRAM_BASE_ADDR_OS_STATISTIC_PSCPU, IRAM_BASE_LEN_OS_STATISTIC_PSCPU);
+#endif
+
+ /*
+ init_timer(&timer);
+ timer.expires = jiffies + 40*HZ;//msecs_to_jiffies(40*1000);//ÑÓ³Ù40Ãë
+ timer.data = 0;
+ timer.function = os_statistic_delayed_work_timer_fn;
+ setup_timer(&timer, os_statistic_delayed_work_timer_fn, 0);
+ add_timer(&timer);
+ */
+ //task = kthread_create(os_statistic_delayed_work_timer_fn, 0, "g_zxic_trace_sync_thread", 0);
+ //wake_up_process(task);
+ os_statistic_enable();
+ return 0x0;
+}
+module_init(zxic_enable_tracer);
+
+
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
new file mode 100755
index 0000000..f730067
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
@@ -0,0 +1,2041 @@
+/*
+ * zx297520v3_es8312.c -- zx29-ak4940 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/ak4940.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0xac
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ak4940_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "ak4940.1-0012",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, voice_platform),
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, dummy),
+
+},
+
+#if 0
+
+ [AUDIO_DL_MEDIA] = {
+ .name = "ak4940",
+ .stream_name = "MultiMedia",
+ .nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940, media_platform),
+ },
+
+ [AUDIO_DL_VOICE] = {
+
+ .name = "voice_call",
+ .stream_name = "voice",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ },
+ [AUDIO_DL_2G_AND_3G_VOICE] = {
+
+ .name = "voice_2g_3g",
+ .stream_name = "voice_2g_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice_2g_3g, ak4940, voice_audio),
+
+ },
+ [AUDIO_DL_VP_LOOP] = {
+
+ .name = "loop_test",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "snd-soc-dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops2,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ }, .stream_name = "loop_voice",
+
+ [AUDIO_DL_3G_VOICE] = {
+
+ .name = "voice_3g", // 3g nb,wb
+ .stream_name = "voice_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, voice_audio),
+
+ }
+#endif
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ak4940_of_match[] = {
+ { .compatible = "zxic,zx29_ak4940", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ak4940_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<15);
+ val |= 0x1<<15;; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+
+ val &= 0xfffffff8;
+ val |= 0x00000001;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ak4940_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_ak4940";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_ak4940",
+ .of_match_table = of_match_ptr(zx29_ak4940_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ak4940");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
new file mode 100755
index 0000000..1a8cf3e
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
@@ -0,0 +1,1346 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-dummycodec ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+ unsigned int armRegBit = 0;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x1;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ //if (ret < 0){
+ // print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ // return ret;
+ // }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ti3100_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0012", "tlv320aic31xx-hifi")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_dummycodec_of_match[] = {
+ { .compatible = "zxic,zx29_dummycodec", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_dummycodec_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+
+
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+ board->name = "zx29_dummycodec";
+ board->dev = &pdev->dev;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_dummycodec_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ //platform_set_drvdata(pdev, board);
+
+
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_dummycodec",
+ .of_match_table = of_match_ptr(zx29_dummycodec_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-dummycodec");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
new file mode 100755
index 0000000..ea874ee
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
@@ -0,0 +1,2012 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/max9867.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define CODEC_CLK_ID 0
+#define CODEC_SCLK_MCLK_ID 0
+#define CODEC_SCLK_PLL_ID 1
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ #if 0
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+ #endif
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(max9867_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("max9867.1-001a", "max9867-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, max9867_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_max9867_of_match[] = {
+ { .compatible = "zxic,zx29_max9867", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_max9867_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p,*p2;
+ struct pinctrl_state *s,*s2;
+ int ret = 0;
+ printk("%s start n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s0 end!\n", __func__);
+ /*
+ p2 = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+ */
+
+ s2 = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ ret = pinctrl_select_state(p, s2);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s1 end!\n", __func__);
+
+
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_max9867_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_max9867";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static void zx29_audio_shutdown(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ;
+}
+static int zx29_audio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_max9867",
+ .of_match_table = of_match_ptr(zx29_max9867_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ .shutdown = zx29_audio_shutdown,
+ .suspend = zx29_audio_suspend,
+ .resume = zx29_audio_resume,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-max9867");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
new file mode 100755
index 0000000..1e5777d
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
@@ -0,0 +1,2325 @@
+/*
+ * zx297520v3_nau8810.c -- zx297520v3-nau8810 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/nau8810.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define NAU_CLK_ID 0
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+ static int zx29_hw_params_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_tdm,
+#else
+ .hw_params = zx29_hw_params,
+#endif
+
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_lp_tdm,
+#else
+ .hw_params = zx29_hw_params_lp,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_voice_tdm,
+#else
+ .hw_params = zx29_hw_params_voice,
+#endif
+
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx29_nau8810",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to nau8810 */
+#define ZX29_CODEC_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_codec_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(cpu_tdm, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1412000.tdm")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(nau8810, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-0012", "nau8810-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(nau8810_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-001a", "nau8810-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+
+ SND_SOC_DAILINK_DEF(media_platform_tdm, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1412000.tdm")));
+
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, dummy_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+#endif
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, nau8810_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, nau8810_codec, media_platform),
+#endif
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_nau8810_of_match[] = {
+ { .compatible = "zxic,zx29_nau8810", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_nau8810_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+ int ret = 0;
+ printk("%s start \n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: board name(%s)!\n", __func__,info->name);
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#elif defined(CONFIG_USE_TOP_I2S1)//defined(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+#if defined(CONFIG_USE_TOP_I2S0)
+ dev_info(dev, "%s: top_i2s0 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+
+
+#elif defined(CONFIG_USE_TOP_I2S1)
+ dev_info(dev, "%s: top_i2s1 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s1_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#elif defined(CONFIG_USE_TOP_TDM)
+ dev_info(dev, "%s: top_tdm pinctrl sel!!\n", __func__);
+ s = pinctrl_lookup_state(p, "top_tdm");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "toptdm_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#else
+ dev_info(dev, "%s: default top_i2s pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#endif
+ if(info != NULL){
+
+ info->p = p;
+ info->s = s;
+ info->s_sleep = s_sleep;
+ }
+
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+/*
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+*/
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_nau8810_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_nau8810";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+
+#ifdef CONFIG_PM
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(&pdev->dev);
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(&pdev->dev);
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(dev);
+ if((info->p != NULL)&&(info->s_sleep != NULL)){
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl sleep end!\n", __func__);
+ }
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(dev);
+ if((info->p != NULL)&&(info->s != NULL)){
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl active end!\n", __func__);
+ }
+
+
+ return snd_soc_resume(dev);
+
+}
+
+#else
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+
+
+ return snd_soc_resume(dev);
+
+}
+
+
+#endif
+
+
+struct dev_pm_ops zx29_snd_soc_pm_ops = {
+ .suspend = zx29_snd_soc_suspend,
+ .resume = zx29_snd_soc_resume,
+ .freeze = snd_soc_suspend,
+ .thaw = snd_soc_resume,
+ .poweroff = snd_soc_poweroff,
+ .restore = snd_soc_resume,
+};
+
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_nau8810",
+ .of_match_table = of_match_ptr(zx29_nau8810_of_match),
+ //.pm = &snd_soc_pm_ops,
+ .pm = &zx29_snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_nau8810_snd_device, &zx29xx_nau8810, sizeof(zx29xx_nau8810));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-nau8810");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
new file mode 100755
index 0000000..9959350
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
@@ -0,0 +1,2011 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/tlv320aic31xx.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_TI3100_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_TI3100_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018", "tlv320aic3x-hifi")));
+
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+#else
+
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+
+#endif
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, codec, dummy),
+ SND_SOC_DAILINK_REG(voice_cpu, codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ti3100_of_match[] = {
+ { .compatible = "zxic,zx29_ti3100", .data = &zx29_platform_data },
+ { .compatible = "zxic,zx29_ti3104", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ti3100_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ti3100_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ board->name = "zx29_ti3104";
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ board->name = "zx29_ti3100";
+#else
+ board->name = "zx29_ti3100";
+
+#endif
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ .name = "zx29_ti3104",
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ .name = "zx29_ti3100",
+#else
+ .name = "zx29_ti3100",
+
+#endif
+ .of_match_table = of_match_ptr(zx29_ti3100_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ti3100");