[Feature][T106_eSDK]T106-V2.01.01.02P56U06.AP.15.11_CAP.15.11(SDK4.6)diff_16.08(SDK4.7)
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I7a7c42775e2ffdd23aaec4fff782adcc99d7890b
diff --git a/upstream/pub/include/infra/pub_debug_info.h b/upstream/pub/include/infra/pub_debug_info.h
new file mode 100755
index 0000000..10357aa
--- /dev/null
+++ b/upstream/pub/include/infra/pub_debug_info.h
@@ -0,0 +1,67 @@
+#ifndef _PUB_DEBUG_INFO_H_
+#define _PUB_DEBUG_INFO_H_
+
+#include <stdarg.h>
+
+#define DEBUG_INFO_DEV_PATH "/dev/debug_info"
+
+/* AP²àºÍCAP²àµÄPS\KERNEL\DRIVER\FS\APP ÒÔSTART~ENDΪÇø¼ä£¬¸÷²¿·ÖÔ¤ÁôÁË100¸öID */
+#define MODULE_ID_PS_START (1)
+#define MODULE_ID_PS_NAS (1)
+#define MODULE_ID_PS_RRC (2)
+#define MODULE_ID_PS_L2 (3)
+#define MODULE_ID_PS_UICC (99)
+#define MODULE_ID_PS_END (100)
+
+#define MODULE_ID_AP_KERNEL_START (101)
+#define MODULE_ID_AP_KERNEL_END (200)
+
+#define MODULE_ID_CAP_KERNEL_START (201)
+#define MODULE_ID_CAP_KERNEL_END (300)
+
+#define MODULE_ID_AP_DRIVES_START (301)
+#define MODULE_ID_AP_USB (301)
+#define MODULE_ID_AP_REBOOT (302)
+#define MODULE_ID_AP_TSC (303)
+#define MODULE_ID_AP_PSM (304)
+#define MODULE_ID_AP_NAND (305)
+#define MODULE_ID_AP_MMC (306)
+#define MODULE_ID_AP_WIFI (307)
+#define MODULE_ID_AP_DRIVES_END (400)
+
+#define MODULE_ID_CAP_DRIVES_START (401)
+#define MODULE_ID_CAP_USB (401)
+#define MODULE_ID_CAP_TSC (402)
+#define MODULE_ID_CAP_PSM (403)
+#define MODULE_ID_CAP_NAND (404)
+#define MODULE_ID_CAP_SPI (405)
+#define MODULE_ID_CAP_MMC (406)
+#define MODULE_ID_CAP_UART (407)
+#define MODULE_ID_CAP_DRIVES_END (500)
+
+#define MODULE_ID_AP_FS_START (501)
+#define MODULE_ID_AP_JFFS2 (501)
+#define MODULE_ID_AP_FS_END (600)
+
+#define MODULE_ID_CAP_FS_START (601)
+#define MODULE_ID_CAP_FS_END (700)
+
+#define MODULE_ID_AP_APP_START (701)
+#define MODULE_ID_AP_FOTA (701)
+#define MODULE_ID_AP_FS_CHECK (702)
+#define MODULE_ID_AP_APP_END (800)
+
+#define MODULE_ID_CAP_APP_START (801)
+#define MODULE_ID_CAP_FOTA (801)
+#define MODULE_ID_CAP_FS_CHECK (802)
+#define MODULE_ID_CAP_APP_END (900)
+
+#if defined(_USE_ZXIC_DEBUG_INFO) && !defined(CONFIG_SYSTEM_RECOVERY)
+int sc_debug_info_vrecord(unsigned int id, const char *format, va_list args);
+int sc_debug_info_record(unsigned int id, const char *format, ...);
+#else
+static inline int sc_debug_info_vrecord(unsigned int id, const char *format, va_list args) { return 0; }
+static inline int sc_debug_info_record(unsigned int id, const char *format, ...) { return 0; }
+#endif
+
+#endif
\ No newline at end of file
diff --git a/upstream/pub/project/zx297520v3/include/drv/NvParam_drv.h b/upstream/pub/project/zx297520v3/include/drv/NvParam_drv.h
new file mode 100755
index 0000000..66c6f6d
--- /dev/null
+++ b/upstream/pub/project/zx297520v3/include/drv/NvParam_drv.h
@@ -0,0 +1,223 @@
+/***********************************************************************
+* Copyright (C) 2016, ZTE Corporation.
+*
+* File Name: nvparam_drv.h
+* File Mark:
+* Description:
+* Others:
+* Version: v1.0
+* Author: wangxia
+* Date: 2016-03-12
+*
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+#ifndef NVPARAM_DRV_H
+#define NVPARAM_DRV_H
+
+/**************************************************************************
+ * Include files *
+ **************************************************************************/
+#include "RWNvConfig.h"
+#include "NvParam_tsc.h"
+/**************************************************************************
+ * Macro *
+ **************************************************************************/
+#define DRV_NV_ADDR OS_FLASH_DRV_RW_NONFAC_BASE_ADDR
+#define DRV_NV_SIZE OS_FLASH_DRV_RW_NONFAC_SIZE /*16K*/
+
+/*=====================================================================================================================
+|----------------|----------------|---------------|--------------|----------------|-----------------|-----------------|
+| public(256B) | system(3K) | platfor(3K) | highspeed(4K)| peripheral(3K) | audio(1K) | reserved(1.75K) |
+|----------------|----------------|---------------|--------------|----------------|-----------------|-----------------|
+=======================================================================================================================*/
+
+#define DRV_PUB_NV_ADDR DRV_NV_ADDR
+#define DRV_PUB_NV_SIZE (256)
+#define DRV_SYS_NV_ADDR (DRV_PUB_NV_ADDR + DRV_PUB_NV_SIZE)
+#define DRV_SYS_NV_SIZE (3 * 1024)
+#define DRV_PLAT_NV_ADDR (DRV_SYS_NV_ADDR + DRV_SYS_NV_SIZE)
+#define DRV_PLAT_NV_SIZE (3 * 1024)
+#define DRV_HS_PERI_NV_ADDR (DRV_PLAT_NV_ADDR + DRV_PLAT_NV_SIZE)
+#define DRV_HS_PERI_NV_SIZE (4 * 1024)
+#define DRV_PERI_NV_ADDR (DRV_HS_PERI_NV_ADDR + DRV_HS_PERI_NV_SIZE)
+#define DRV_PERI_NV_SIZE (3 * 1024)
+#define DRV_AUDIO_NV_ADDR (DRV_PERI_NV_ADDR + DRV_PERI_NV_SIZE)
+#define DRV_AUDIO_NV_SIZE (1 * 1024)
+#define DRV_RSVD_NV_ADDR (DRV_AUDIO_NV_ADDR + DRV_AUDIO_NV_SIZE)
+#define DRV_RSVD_NV_SIZE (1 * 1024 + 768)
+
+#define DRV_TOTAL_NV_SIZE (DRV_PUB_NV_SIZE+DRV_SYS_NV_SIZE+DRV_PLAT_NV_SIZE+DRV_HS_PERI_NV_SIZE+DRV_PERI_NV_SIZE+DRV_AUDIO_NV_SIZE+DRV_RSVD_NV_SIZE)
+
+/* user interface */
+#define DRV_PUB_NV_ITEM_ADDR(x) (DRV_PUB_NV_ADDR + (UINT32)(&(((T_ZDrvNv_PubData*)(0x0))->x)))
+#define DRV_PUB_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_PubData*)(0x0))->x))
+
+#define DRV_SYS_NV_ITEM_ADDR(x) (DRV_SYS_NV_ADDR + (UINT32)(&(((T_ZDrvNv_SysData*)(0x0))->x)))
+#define DRV_SYS_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_SysData*)(0x0))->x))
+
+#define DRV_PLAT_NV_ITEM_ADDR(x) (DRV_PLAT_NV_ADDR + (UINT32)(&(((T_ZDrvNv_PlatData*)(0x0))->x)))
+#define DRV_PLAT_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_PlatData*)(0x0))->x))
+
+#define DRV_HS_PERI_NV_ITEM_ADDR(x) (DRV_HS_PERI_NV_ADDR + (UINT32)(&(((T_ZDrvNv_HSPeriData*)(0x0))->x)))
+#define DDRV_HS_PER_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_HSPeriData*)(0x0))->x))
+
+#define DRV_PER_NV_ITEM_ADDR(x) (DRV_PERI_NV_ADDR + (UINT32)(&(((T_ZDrvNv_PeriData*)(0x0))->x)))
+#define DRV_PER_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_PeriData*)(0x0))->x))
+
+#define DRV_AUDIO_NV_ITEM_ADDR(x) (DRV_AUDIO_NV_ADDR + (UINT32)(&(((T_ZDrvNv_AudioData*)(0x0))->x)))
+#define DRV_AUDIO_NV_ITEM_SIZE(x) (sizeof(((T_ZDrvNv_AudioData*)(0x0))->x))
+
+#define OS_FLASH_VOICE_DRV_RW_NONFAC_BASE_ADDR (OS_FLASH_DRV_RW_NONFAC_BASE_ADDR + 15360)
+#define OS_FLASH_VOICE_DRV_NONFAC_SIZE 1024
+
+#if DRV_TOTAL_NV_SIZE > (OS_FLASH_DRV_RW_NONFAC_SIZE)
+#error "error drv nv config!!!"
+#endif
+
+/****************************************************************************
+* Types
+****************************************************************************/
+
+
+/******************************************************
+* Drv NV Config
+******************************************************/
+/***********************************
+1. public nv_data
+************************************/
+typedef struct _T_ZDrvNv_PubData
+{
+ /* 0x00 */ CHAR chipName[16];
+ /* 0x10 */ CHAR prjName[16];
+ /* 0x20 */ CHAR externalVer[16];
+ /* 0x30 */ CHAR internalVer[16];
+ /* 0x40 */ CHAR releaseTime[16];
+ /* 0x50 */ UINT8 productType;
+ /* 0x51 */ UINT8 reserved[DRV_PUB_NV_SIZE - 0x51];
+} __attribute__ ((packed)) T_ZDrvNv_PubData;
+
+/***********************************
+2. system group nv_data
+************************************/
+typedef struct _T_ZDrvNv_SysData
+{
+ /* 0x000 */ T_SYS_NV_TSC_CONFIG tsc_config;
+ UINT8 reserved0[12];
+ /* 0x70 */ UINT32 buck1OnoffFlag;
+ /* 0x74 */ UINT32 wdtSwitch;
+ /* 0x78 */ UINT32 wdtPriority;
+ /* 0x7C */ UINT8 uiccmodeSwitch;
+ /* 0x7D */ UINT8 uiccPreSwitch;
+ /* 0x7E */ UINT8 uicc1modeSwitch;
+ /* 0x7F */ UINT8 uicc1PreSwitch;
+ /* 0x80 */ UINT8 ishpnotsupported;
+ UINT8 reserved[DRV_SYS_NV_SIZE - 129];
+} __attribute__ ((packed)) T_ZDrvNv_SysData;
+
+/***********************************
+3. platform group nv_data
+************************************/
+typedef struct _T_ZDrvNv_PlatData
+{
+ UINT8 reserved[DRV_PLAT_NV_SIZE];
+} __attribute__ ((packed)) T_ZDrvNv_PlatData;
+
+/***********************************
+4. hign-speed peripheral group nv_data
+************************************/
+typedef struct _T_ZDrvNv_HSPeriData
+{
+ UINT8 reserved[DRV_HS_PERI_NV_SIZE];
+} __attribute__ ((packed)) T_ZDrvNv_HSPeriData;
+
+/***********************************
+5. common peripheral group nv_data
+************************************/
+typedef struct _T_ZDrvNv_PeriData
+{
+ UINT8 bat_det;
+ UINT8 reserved[DRV_PERI_NV_SIZE-1];
+} __attribute__ ((packed)) T_ZDrvNv_PeriData;
+
+/***********************************
+6. audio group nv_data
+************************************/
+typedef struct _T_ZDrvNv_AudioData
+{
+ UINT8 reserved[DRV_AUDIO_NV_SIZE];
+} __attribute__ ((packed)) T_ZDrvNv_AudioData;
+
+/***********************************
+7. all driver_used nv_data
+************************************/
+typedef struct _T_ZDrv_NvData
+{
+ /* 0x0000 */ T_ZDrvNv_PubData pubData;
+ /* 0x0100 */ T_ZDrvNv_SysData sysData;
+ /* 0x0D00 */ T_ZDrvNv_PlatData platData;
+ /* 0x1900 */ T_ZDrvNv_HSPeriData HSPeriData;
+ /* 0x2900 */ T_ZDrvNv_PeriData periData;
+ /* 0x3500 */ T_ZDrvNv_AudioData audioData;
+ /* 0x3900 */ UINT8 reserved[DRV_RSVD_NV_SIZE];
+} T_ZDrv_NvData;
+
+
+/******************************************************
+* check struct size
+******************************************************/
+static inline CHAR zDrvNv_CheckTypeSize(void)
+{ \
+ CHAR __dummy1[(sizeof(T_ZDrv_NvData)==DRV_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy2[(sizeof(T_ZDrvNv_PubData)==DRV_PUB_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy3[(sizeof(T_ZDrvNv_SysData)==DRV_SYS_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy4[(sizeof(T_ZDrvNv_PlatData)==DRV_PLAT_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy5[(sizeof(T_ZDrvNv_HSPeriData)==DRV_HS_PERI_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy6[(sizeof(T_ZDrvNv_PeriData)==DRV_PERI_NV_SIZE)?1:-1]={0}; \
+ CHAR __dummy7[(sizeof(T_ZDrvNv_AudioData)==DRV_AUDIO_NV_SIZE)?1:-1]={0}; \
+ return (__dummy1[0]+__dummy2[0]+__dummy3[0]+__dummy4[0]+__dummy5[0]+__dummy6[0]+__dummy7[0]); \
+}
+
+/******************************************************
+* old struct
+******************************************************/
+#if 0
+typedef struct _T_Sys_Drv_Nv_Data
+{
+ T_SYS_NV_TSC_CONFIG tsc_config;
+ UINT8 reserved[6];
+ UINT32 wdtSwitch;
+}T_Sys_Drv_Nv_Data;
+#endif
+typedef struct _T_Drv_Nv_Data
+{
+ UINT32 VpData[1024];//add by lvwenhua for voice 2013.12.6
+}T_Drv_Nv_Data;
+
+#define DRV_NV_ITEM_ADDRESS(x) (DRV_AUDIO_NV_ADDR + (UINT32)(&(((T_Drv_Nv_Data*)(0x0))->x)))
+//flag use 32byte
+typedef struct _T_Audio_NvFlag
+{
+ UINT8 isVpConfigInitOn;
+ UINT8 isVpParamInNv;
+ UINT8 isUseSlicCodec;
+ UINT8 isUseVoiceProc;//4 UINT8 isUseNXP;
+ UINT8 isUseCodecDsp;
+ UINT8 isUseNvWrite;
+ UINT8 isCloseVpBufferBak;
+ UINT8 isUseTdm;//8
+ UINT8 isUseRxDtmfDet;
+ UINT8 isUseTxDtmfDet;
+ UINT8 isUseRxMixData;
+ UINT8 isUseTxMixData;//12
+ UINT8 isUseEcall;
+ UINT8 reserved[19];//32-13
+
+} T_Audio_NvFlag;
+
+#endif
+
diff --git a/upstream/pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h b/upstream/pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h
new file mode 100755
index 0000000..6a1626d
--- /dev/null
+++ b/upstream/pub/project/zx297520v3/include/infra/ram_base_config_7520v3.h
@@ -0,0 +1,347 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ram_config_7520v3.h
+* Îļþ±êʶ: ram_config_7520v3.h
+* ÄÚÈÝÕªÒª: zx297520v3оƬƽ̨´æ´¢µØÖ·ÅäÖÃÍ·Îļþ
+* ʹÓ÷½·¨: #include "ram_config.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2015/06/08 V1.0 Create ÁõÑÇÄÏ ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAM_BASE_CONFIG_7520V3
+#define _RAM_BASE_CONFIG_7520V3
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+
+/* IRAM0»ùµØÖ· */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define IRAM_BASE_ADDR ((unsigned long)(ZX_IRAM0_BASE))
+#else
+#define IRAM_BASE_ADDR (0x82000000UL>>CPU_SHIFT)
+#endif
+#define IRAM_BASE_LEN (0x00010000UL>>CPU_SHIFT)
+
+/* 1K, Òì³£ÏòÁ¿±í: 0x82000000/0x41000000 */
+#define IRAM_BASE_ADDR_VECTOR (IRAM_BASE_ADDR)
+#define IRAM_BASE_LEN_VECTOR ((1 * 1024UL)>>CPU_SHIFT)
+#define OTP_SECURE_PUK_BASE IRAM_BASE_ADDR_VECTOR + 0x4
+
+/* 12K£¬Çý¶¯ºË¼äͨѶ */
+#define IRAM_BASE_ADDR_DRV (IRAM_BASE_ADDR_VECTOR + IRAM_BASE_LEN_VECTOR)
+#define IRAM_BASE_LEN_DRV ((12 * 1024UL)>>CPU_SHIFT)
+
+/* 1K£¬Ê¡µçÃüÁî½»»¥ */
+#define IRAM_BASE_ADDR_PSM (IRAM_BASE_ADDR_DRV + IRAM_BASE_LEN_DRV)
+#define IRAM_BASE_LEN_PSM ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 4K£¬PSÓëPHYÐÅÏ¢½»»¥£¬¹«¹²ÒµÎñ */
+#define IRAM_BASE_ADDR_PUB (IRAM_BASE_ADDR_PSM + IRAM_BASE_LEN_PSM)
+#define IRAM_BASE_LEN_PUB ((4 * 1024UL)>>CPU_SHIFT)
+
+/* 512B£¬PSÓëPHYÐÅÏ¢½»»¥£¬ÉäƵ¹«¹²ÒµÎñ */
+#define IRAM_BASE_ADDR_PUB_RF (IRAM_BASE_ADDR_PUB)
+#define IRAM_BASE_LEN_PUB_RF (512UL>>CPU_SHIFT)
+
+/* 32B£¬¸¨Ä£Ê½AFC»º´æÊý¾Ý¿Õ¼ä */
+#define IRAM_BASE_ADDR_SLAVE_AFC (IRAM_BASE_ADDR_PUB_RF + IRAM_BASE_LEN_PUB_RF)
+#define IRAM_BASE_LEN_SLAVE_AFC (32UL>>CPU_SHIFT)
+
+/* 1K£¬Î¿ØÊý¾Ý´æ·Å */
+#define IRAM_BASE_ADDR_TPC (IRAM_BASE_ADDR_PUB + IRAM_BASE_LEN_PUB)
+#define IRAM_BASE_LEN_TPC ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 2K£¬ÖжÏÏ̹߳켣´æ·Å */
+#define IRAM_BASE_ADDR_OS_STATISTIC (IRAM_BASE_ADDR_TPC + IRAM_BASE_LEN_TPC)
+#define IRAM_BASE_LEN_OS_STATISTIC ((2 * 1024UL)>>CPU_SHIFT)
+
+/* 1K,ϵͳ¸ú×ټǼ */
+#define IRAM_BASE_ADDR_SYS_TRACE (IRAM_BASE_ADDR_OS_STATISTIC + IRAM_BASE_LEN_OS_STATISTIC)
+#define IRAM_BASE_LEN_SYS_TRACE ((1 * 1024UL)>>CPU_SHIFT)
+
+/* IRAM ICPµØÖ· */
+#define ICP_CMD_BASE_ADDR (IRAM_BASE_ADDR)
+#define ICP_DRV_BASE_ADDR (IRAM_BASE_ADDR_DRV)
+#define DUAL_STANDBY_INTERF_GSM_USE_INFO_BASE_ADDR (IRAM_BASE_ADDR_GSM)
+
+/* ¸÷ºËIRAM¹ì¼£µØÖ· */
+#define IRAM_BASE_ADDR_OS_STATISTIC_PSCPU (IRAM_BASE_ADDR_OS_STATISTIC)
+#define IRAM_BASE_LEN_OS_STATISTIC_PSCPU (0x200UL>>CPU_SHIFT)
+#define IRAM_BASE_ADDR_OS_STATISTIC_PHYCPU (IRAM_BASE_ADDR_OS_STATISTIC_PSCPU + IRAM_BASE_LEN_OS_STATISTIC_PSCPU)
+#define IRAM_BASE_LEN_OS_STATISTIC_PHYCPU (0x200UL>>CPU_SHIFT)
+#define IRAM_BASE_ADDR_OS_STATISTIC_APCPU (IRAM_BASE_ADDR_OS_STATISTIC_PHYCPU + IRAM_BASE_LEN_OS_STATISTIC_PHYCPU)
+#define IRAM_BASE_LEN_OS_STATISTIC_APCPU (0x400UL>>CPU_SHIFT)
+
+/* ¸÷ºËIRAM¸ú×ÙµØÖ· */
+#define IRAM_BASE_ADDR_SYS_TRACE_RMCPU (IRAM_BASE_ADDR_SYS_TRACE)
+#define IRAM_BASE_ADDR_SYS_TRACE_APCPU (IRAM_BASE_ADDR_SYS_TRACE + (0x10>>CPU_SHIFT))
+#define IRAM_BASE_ADDR_SYS_TRACE_PSCPU (IRAM_BASE_ADDR_SYS_TRACE + (0x20>>CPU_SHIFT))
+#define IRAM_BASE_ADDR_SYS_TRACE_PHYCPU (IRAM_BASE_ADDR_SYS_TRACE + (0x30>>CPU_SHIFT))
+
+/* phy logÓÅ»¯·½°¸¸´Óà IRAM_BASE_ADDR_SYS_TRACE ºó512×Ö½Ú¿Õ¼ä */
+#define IRAM_BASE_ADDR_ZCAT_PHY_LOG (IRAM_BASE_ADDR_SYS_TRACE + (0x200>>CPU_SHIFT))
+
+/* phy log¶ªÊ§¸ú×Ù·½°¸¸´Óà IRAM_BASE_ADDR_SYS_TRACE ºó64×Ö½Ú¿Õ¼ä */
+#define IRAM_BASE_PHY_LOG_DROP_TRACE (IRAM_BASE_ADDR_ZCAT_PHY_LOG + (0x200>>CPU_SHIFT) - (0x40>>CPU_SHIFT))
+
+/* ¼Ç¼ramdumpģʽ: 4×Ö½Ú¿Õ¼ä*/
+#define IRAM_BASE_ADDR_RAMDUMP_MODE (IRAM_BASE_PHY_LOG_DROP_TRACE - (0x04>>CPU_SHIFT))
+
+/* ¼Ç¼SHM bufferµØÖ·: 16×Ö½Ú¿Õ¼ä*/
+#define IRAM_BASE_ADDR_SHM_REMOTE_REGION (IRAM_BASE_ADDR_RAMDUMP_MODE - (0x10>>CPU_SHIFT))
+
+/* ¼Ç¼zcatģʽ: 4×Ö½Ú¿Õ¼ä*/
+#define IRAM_BASE_ADDR_ZCAT_MODE (IRAM_BASE_ADDR_SHM_REMOTE_REGION - (0x04>>CPU_SHIFT))
+
+/* ¸´Óù켣µÄÇ°4¸ö×ֽڼǼboot´«µÝµÄDDR sizeÐÅÏ¢ */
+#define IRAM_BASE_ADDR_BOOT_DDR (IRAM_BASE_ADDR_DRV - (0x04>>CPU_SHIFT))
+
+/* IRAM1»ùµØÖ· */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define IRAM1_BASE_ADDR ((unsigned long)(ZX_IRAM1_BASE))
+#else
+#define IRAM1_BASE_ADDR (0x00100000>>CPU_SHIFT)
+#endif
+#define IRAM1_BASE_LEN (0x00003000>>CPU_SHIFT)
+
+
+#define DDR_BASE_ADDR (0x20000000UL>>CPU_SHIFT)
+
+/* 3M£¬ÎïÀí²ã°æ±¾£¬ÓÉPS¼ÓÔØ */
+/* 7520µÄZSPÅäÖÃΪ·ÇCacheÇø£¬Ö»ÄÜÅäÖÃ4¸ö¶Î£¬ÇÒÿ¸ö¶ÎµØÖ·»¹ÓÐÌض¨ÒªÇ󣬸õØÖ·±ä¶¯ÐèÓëÎïÀí²ãÈ·ÈÏ */
+#ifdef DDR_BASE_ADDR_LINUX_VA
+#define DDR_BASE_ADDR_PHY ((unsigned long)(ZX_DDR_PHYCODE_BASE))
+#else
+#define DDR_BASE_ADDR_PHY (DDR_BASE_ADDR)
+#endif
+
+#ifdef _USE_LTE_ONLY
+#define DDR_BASE_LEN_PHY (0x00200000UL>>CPU_SHIFT)
+#else
+#define DDR_BASE_LEN_PHY (0x00300000UL>>CPU_SHIFT)
+#endif
+#define DDR_BASE_OFF_PHY (0)
+
+/* 1.5M£¬ÎïÀí²ãDATA/HARQ/CRC */
+#define DDR_BASE_ADDR_PHY_DATA (DDR_BASE_ADDR_PHY + DDR_BASE_LEN_PHY)
+#define DDR_BASE_LEN_PHY_DATA (0x00180000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_PHY_DATA (DDR_BASE_OFF_PHY + DDR_BASE_LEN_PHY)
+
+/* 1.0M£¬ÐÒéÕ»ÓëÎïÀí²ã½»»¥ */
+#define DDR_BASE_ADDR_LTE_DATA (DDR_BASE_ADDR_PHY + DDR_BASE_LEN_PHY) //DDR_BASE_LEN_PHY_NV
+#define DDR_BASE_LEN_LTE_DATA (0x00100000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_LTE_DATA (DDR_BASE_OFF_PHY + DDR_BASE_LEN_PHY)
+
+/* 0.25M£¬Ö§³Åµ¼³öRamdump */
+#define DDR_BASE_ADDR_RAMDUMP (DDR_BASE_ADDR_LTE_DATA + DDR_BASE_LEN_LTE_DATA)
+#define DDR_BASE_LEN_RAMDUMP (0x00040000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_RAMDUMP (DDR_BASE_OFF_LTE_DATA + DDR_BASE_LEN_LTE_DATA)
+
+#ifdef _USE_VEHICLE_DC /* ³µÔØË«ºËLinux */
+/* 37.75M£¬AP¹²ºË°æ±¾(´Ë´óСÊÇ°´ÕÕº¬CAPºËµÄ64MÄÚ´æÅäÖö¨Ò壬¸Ãºê±ð´¦²»»á±»Ê¹ÓÃ) */
+#define DDR_BASE_ADDR_AP (DDR_BASE_ADDR_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+#define DDR_BASE_LEN_AP (0x025C0000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_AP (DDR_BASE_OFF_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+
+/* 2M, share memory between ap and cap */
+#define DDR_BASE_ADDR_CAP_BUF (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP)
+#define DDR_BASE_LEN_CAP_BUF (0x00200000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_CAP_BUF (DDR_BASE_OFF_AP + DDR_BASE_LEN_AP)
+
+/* 84M/212M, cap°æ±¾ */
+#define DDR_BASE_ADDR_CAP (DDR_BASE_ADDR_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#define DDR_BASE_LEN_CAP (0x05400000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_CAP (DDR_BASE_OFF_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+
+/* capºËµÄdtbµØÖ·¹©ubootºËcap kernelʹÓà */
+#define DDR_BASE_CAP_DTB_ADDR (DDR_BASE_ADDR_CAP_BUF + (0x00100000UL>>CPU_SHIFT))
+#else
+/* 42.75M£¬AP¹²ºË°æ±¾(´Ë´óСÊÇ°´ÕÕº¬CAPºËµÄ64MÄÚ´æÅäÖö¨Ò壬¸Ãºê±ð´¦²»»á±»Ê¹ÓÃ) */
+#define DDR_BASE_ADDR_AP (DDR_BASE_ADDR_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+#ifdef _USE_LTE_ONLY
+#define DDR_BASE_LEN_AP (0x02BC0000UL>>CPU_SHIFT)
+#else
+#define DDR_BASE_LEN_AP (0x02AC0000UL>>CPU_SHIFT)
+#endif
+#define DDR_BASE_OFF_AP (DDR_BASE_OFF_RAMDUMP + DDR_BASE_LEN_RAMDUMP)
+
+/* 1M, share memory between ap and cap */
+#define DDR_BASE_ADDR_CAP_BUF (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP)
+#ifndef DDR_BASE_LEN_CAP_BUF
+#define DDR_BASE_LEN_CAP_BUF (0x00100000UL>>CPU_SHIFT)
+#endif
+#define DDR_BASE_OFF_CAP_BUF (DDR_BASE_OFF_AP + DDR_BASE_LEN_AP)
+
+/* 16M, cap°æ±¾ */
+#define DDR_BASE_ADDR_CAP (DDR_BASE_ADDR_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#ifndef DDR_BASE_LEN_CAP
+#define DDR_BASE_LEN_CAP (0x01000000UL>>CPU_SHIFT)
+#endif
+#define DDR_BASE_OFF_CAP (DDR_BASE_OFF_CAP_BUF + DDR_BASE_LEN_CAP_BUF)
+#endif
+
+#define DDR_BASE_PHYCODE_ADDR_PA (DDR_BASE_ADDR)
+#define DDR_BASE_MODEM_ADDR_PA (DDR_BASE_PHYCODE_ADDR_PA + DDR_BASE_LEN_PHY)
+#define DDR_BASE_MODEM_SIZE (DDR_BASE_LEN_LTE_DATA + DDR_BASE_LEN_RAMDUMP)
+#define DDR_BASE_AP_ADDR_PA (DDR_BASE_MODEM_ADDR_PA + DDR_BASE_MODEM_SIZE)
+
+#define DDR_BASE_CAPBUF_ADDR_PA (DDR_BASE_AP_ADDR_PA + DDR_BASE_LEN_AP)
+#define DDR_BASE_CAP_ADDR_PA (DDR_BASE_CAPBUF_ADDR_PA + DDR_BASE_LEN_CAP_BUF)
+
+
+/* 1M£¬ÎïÀí²ãNV ¿Õ¼ä¸´Óà */
+#define DDR_BASE_ADDR_PHY_NV (DDR_BASE_ADDR_LTE_DATA)
+#define DDR_BASE_LEN_PHY_NV (0x00100000UL>>CPU_SHIFT)
+
+/* 0.375M£¬Çý¶¯Ê¡µç·þÓÃPS<->PHY½»»¥¿Õ¼ä */
+#define DDR_BASE_ADDR_PSM (DDR_BASE_ADDR_LTE_DATA)
+#define DDR_BASE_LEN_PSM (0x00060000UL>>CPU_SHIFT)
+#define DDR_BASE_OFF_PSM (DDR_BASE_OFF_RAMDUMP)
+
+/* 1M£¬ÐÒéÕ»ÓëÎïÀí²ã½»»¥ ¿Õ¼ä¸´Óà */
+#define DDR_BASE_ADDR_WCDMA_DATA (DDR_BASE_ADDR_LTE_DATA)
+#define DDR_BASE_LEN_WCDMA_DATA (DDR_BASE_LEN_LTE_DATA)
+
+#if 0
+/* PsBuffer»ùÖ· */
+#define PS_BUF_BASE_ADDR (DDR_BASE_ADDR_PSBUF)
+#endif
+
+/* ICP»ùÖ· */
+#define ICP_DATA_BASE_ADDR (DDR_BASE_ADDR_LTE_DATA)
+
+/* WCDMA»ùÖ· */
+#define DDR_BASE_ADDR_FOR_W (DDR_BASE_ADDR_WCDMA_DATA)
+
+/* ¹¤¾ß´úÀí»ùÖ· */
+/* #define TOOL_AGENT_BASE_ADDR (DDR_BASE_ADDR_TOOL_AGENT) */
+
+#if 0
+/* PPP»ùÖ· */
+#define PLAT_PPP_BASE_ADDR (PS_BUF_BASE_ADDR)
+#endif
+
+/**/
+#define SHARE_BUF_AP_CP_BASE_ADDR (DDR_BASE_ADDR_AP_CP_SHAREBUF)
+
+#if defined(_USE_CAP_SYS) || defined(_USE_VEHICLE_DC)
+#define ICP_CAP_BUF_ADDR DDR_BASE_ADDR_CAP_BUF
+#define ICP_CAP_BUF_LEN ((924 * 1024UL)>>CPU_SHIFT)
+#define TOOL_CAP_BUF_ADDR (ICP_CAP_BUF_ADDR + ICP_CAP_BUF_LEN)
+#define TOOL_CAP_BUF_LEN ((60 * 1024UL)>>CPU_SHIFT)
+#define RINGBUF_CAP_TO_AP_ADDR (TOOL_CAP_BUF_ADDR + TOOL_CAP_BUF_LEN)
+#define RINGBUF_CAP_TO_AP_LEN ((32 * 1024UL)>>CPU_SHIFT)
+#define ADB_CAP_BUF_ADDR (RINGBUF_CAP_TO_AP_ADDR + RINGBUF_CAP_TO_AP_LEN)
+#define ADB_CAP_BUF_LEN ((4 * 1024UL)>>CPU_SHIFT)
+#define RAMDUMP_CAP_CMM_BUF_ADDR (ADB_CAP_BUF_ADDR + ADB_CAP_BUF_LEN)
+#define RAMDUMP_CAP_CMM_BUF_LEN ((4 * 1024UL)>>CPU_SHIFT)
+#define RINGBUF_AP_TO_CAP_ADDR (RAMDUMP_CAP_CMM_BUF_ADDR + RAMDUMP_CAP_CMM_BUF_LEN)
+#define RINGBUF_AP_TO_CAP_LEN ((128 * 1024UL)>>CPU_SHIFT)
+#define TOOL_ZSP_TO_CAP_LOG_ADDR (RINGBUF_AP_TO_CAP_ADDR + RINGBUF_AP_TO_CAP_LEN)
+#define TOOL_ZSP_TO_CAP_LOG_LEN ((384 * 1024UL)>>CPU_SHIFT)
+#define RAMDUMP_AP_TO_CAP_BUF_ADDR (TOOL_ZSP_TO_CAP_LOG_ADDR + TOOL_ZSP_TO_CAP_LOG_LEN)
+#define RAMDUMP_AP_TO_CAP_BUF_LEN ((128 * 1024UL)>>CPU_SHIFT)
+#define TEE_SHARE_BUF_ADDR (RAMDUMP_AP_TO_CAP_BUF_ADDR + RAMDUMP_AP_TO_CAP_BUF_LEN)
+#define TEE_SHARE_BUF_LEN ((384 * 1024UL)>>CPU_SHIFT)
+
+#define ICP_CAP_BUF_ADDR_PA DDR_BASE_CAPBUF_ADDR_PA
+#define TOOL_CAP_BUF_ADDR_PA (ICP_CAP_BUF_ADDR_PA + ICP_CAP_BUF_LEN)
+#define RINGBUF_CAP_TO_AP_ADDR_PA (TOOL_CAP_BUF_ADDR_PA + TOOL_CAP_BUF_LEN)
+#define ADB_CAP_BUF_ADDR_PA (RINGBUF_CAP_TO_AP_ADDR_PA + RINGBUF_CAP_TO_AP_LEN)
+#define RAMDUMP_CAP_CMM_BUF_ADDR_PA (ADB_CAP_BUF_ADDR_PA + ADB_CAP_BUF_LEN)
+#define RINGBUF_AP_TO_CAP_ADDR_PA (RAMDUMP_CAP_CMM_BUF_ADDR_PA + RAMDUMP_CAP_CMM_BUF_LEN)
+#define TOOL_ZSP_TO_CAP_LOG_ADDR_PA (RINGBUF_AP_TO_CAP_ADDR_PA + RINGBUF_AP_TO_CAP_LEN)
+#define RAMDUMP_AP_TO_CAP_BUF_ADDR_PA (TOOL_ZSP_TO_CAP_LOG_ADDR_PA + TOOL_ZSP_TO_CAP_LOG_LEN)
+#define TEE_SHARE_BUF_ADDR_PA (RAMDUMP_AP_TO_CAP_BUF_ADDR_PA + RAMDUMP_AP_TO_CAP_BUF_LEN)
+#endif
+
+/* 7520V3оƬIRAM0ѹËõ£¬ÐÒéÕ»ÎïÀí²ã½»»¥¿Õ¼äÒƶ¯µ½DDR£¬¸´ÓÃRamdump¿Õ¼ä */
+/* 34K£¬PSÓëPHYÐÅÏ¢½»»¥£¬LTEÒµÎñ */
+/* #define IRAM_BASE_ADDR_LTE (DDR_BASE_ADDR_RAMDUMP) */
+/* 10K£¬PSÓëPHYÐÅÏ¢½»»¥£¬LTEÒµÎñ ʹÓÃIRAM0£¬¹¦ºÄÓÅ»¯ 7K+3K, 3k for embms*/
+#define IRAM_BASE_ADDR_LTE (IRAM_BASE_ADDR_SYS_TRACE + IRAM_BASE_LEN_SYS_TRACE)
+#define IRAM_BASE_LEN_LTE ((10 * 1024UL)>>CPU_SHIFT)
+
+/* 24K£¬PSÓëPHYµÄICP½»»¥£¬Ê¹ÓÃIRAM*/
+#define IRAM_BASE_ADDR_PS_PHY_SHAREBUF (IRAM_BASE_ADDR_LTE + IRAM_BASE_LEN_LTE)
+#define IRAM_BASE_LEN_PS_PHY_SHAREBUF ((24 * 1024UL)>>CPU_SHIFT)
+
+/* 221K£¬PSÓëPHYµÄICP½»»¥£¬Ê¹ÓÃDDR, ¸´ÓÃRAMDUMP*/
+#define DDR_BASE_ADDR_PS_PHY_SHAREBUF (DDR_BASE_ADDR_RAMDUMP)
+#define DDR_BASE_LEN_PS_PHY_SHAREBUF ((221 * 1024UL)>>CPU_SHIFT)
+
+/* 2k£¬zsp RAMDUMP*/
+#define DDR_BASE_ADDR_PHY_RAMDUMP (DDR_BASE_ADDR_PS_PHY_SHAREBUF + DDR_BASE_LEN_PS_PHY_SHAREBUF)
+#define DDR_BASE_LEN_PHY_RAMDUMP ((2 * 1024UL)>>CPU_SHIFT)
+
+/* 1K£¬PSÓëPHYÐÅÏ¢½»»¥£¬TDÒµÎñ ʹÓÃDDR*/
+#define IRAM_BASE_ADDR_TD (DDR_BASE_ADDR_PHY_RAMDUMP + DDR_BASE_LEN_PHY_RAMDUMP)
+/* #define IRAM_BASE_LEN_TD ((25 * 1024UL)>>CPU_SHIFT) */
+#define IRAM_BASE_LEN_TD ((1 * 1024UL)>>CPU_SHIFT)
+
+/* 12K£¬PSÓëPHYÐÅÏ¢½»»¥£¬WÒµÎñ ʹÓÃDDR*/
+#define IRAM_BASE_ADDR_WCDMA (IRAM_BASE_ADDR_TD + IRAM_BASE_LEN_TD)
+/* #define IRAM_BASE_LEN_WCDMA ((48 * 1024UL)>>CPU_SHIFT) */
+#define IRAM_BASE_LEN_WCDMA ((12 * 1024UL)>>CPU_SHIFT)
+
+/* 20K£¬W UPA ¿Õ¼ä */
+#define DDR_BASE_ADDR_WUPA_DATA (IRAM_BASE_ADDR_WCDMA + IRAM_BASE_LEN_WCDMA)
+#define DDR_BASE_LEN_WUPA_DATA ((20 * 1024UL)>>CPU_SHIFT)
+
+/* IRAM WCDMA»ùÖ· */
+#define IRAM_BASE_ADDR_FOR_W (IRAM_BASE_ADDR_WCDMA)
+
+/* DPRAM»ùÖ· */
+#define DPRAM_BASE_ADDR (IRAM_BASE_ADDR_TD)
+
+/* DPRAM DDR»ùÖ· */
+#define DPRAM_MEM_BASE_ADDR (IRAM_BASE_ADDR_TD)
+
+/* PS tcm config for ramdump */
+#define RAMDUMP_PS_ITCM_BASE_EXTER (0x0)
+#define RAMDUMP_PS_ITCM_BASE_INTER (0x0)
+#define RAMDUMP_PS_ITCM_SIZE (0x0)
+#define RAMDUMP_PS_DTCM_BASE_EXTER (0x0)
+#define RAMDUMP_PS_DTCM_BASE_INTER (0x0)
+#define RAMDUMP_PS_DTCM_SIZE (0x0)
+
+/* ZSP Ramdump */
+/* #ifdef _USE_ZSP_RAMDUMP */
+# define RAMDUMP_ZSP_ITCM_BASE (0x81040000UL)
+# define RAMDUMP_ZSP_ITCM_SIZE (0x00010000UL)
+# define RAMDUMP_ZSP_DTCM_BASE (0x81000000UL)
+# define RAMDUMP_ZSP_DTCM_SIZE (0x00010000UL)
+
+# define RAMDUMP_ZSP_CODE_SIZE (0x1b0000>>CPU_SHIFT)
+# define RAMDUMP_ZSP_IDDR_BASE (DDR_BASE_ADDR_PHY)
+# define RAMDUMP_ZSP_IDDR_SIZE (RAMDUMP_ZSP_CODE_SIZE)
+# define RAMDUMP_ZSP_DDDR_BASE (RAMDUMP_ZSP_IDDR_BASE + RAMDUMP_ZSP_CODE_SIZE)
+# define RAMDUMP_ZSP_DDDR_SIZE (DDR_BASE_LEN_PHY - RAMDUMP_ZSP_CODE_SIZE)
+
+# define RAMDUMP_ZSP_ITCM_SELF_BASE (0x0)
+# define RAMDUMP_ZSP_DTCM_SELF_BASE (0x10000UL)
+/* #endif */
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+
+#endif // #ifndef _RAM_BASE_CONFIG_7520V3
+