[Feature][T106_eSDK]update from T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01 to T106-M42-PLXXXX-P56U11.AP.19.00_CAP.19.00.01 -- patch
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I3b30b65bf2baf5d89fe5307c03e0206a1536e62d
diff --git a/patch/17.09_19.00/code/17.09_19.00.diff b/patch/17.09_19.00/code/17.09_19.00.diff
new file mode 100644
index 0000000..0d63832
--- /dev/null
+++ b/patch/17.09_19.00/code/17.09_19.00.diff
@@ -0,0 +1,3863 @@
+From 6b423c71c98d90471eb2a34f1dd8217a6bad3510 Mon Sep 17 00:00:00 2001
+From: xf.li <xf.li@mobiletek.cn>
+Date: Fri, 14 Mar 2025 00:07:42 -0700
+Subject: [PATCH] [Feature][T106_eSDK]update from T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01 to T106-M42-PLXXXX-P56U11.AP.19.00_CAP.19.00.01 -- code
+
+Only Configure: No
+Affected branch: master
+Affected module: unknow
+Is it affected on both ZXIC and MTK: only ZXIC
+Self-test: Yes
+Doc Update: No
+
+Change-Id: I5eb7f586f78a987785b0f9885f1300c42bfd6819
+---
+
+diff --git a/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc b/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
+index 439b293..fe9fc43 100755
+--- a/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
++++ b/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
+@@ -2,9 +2,19 @@
+ ERASEBLOCK = "0x40000"
+ UBI_LEB_SIZE = "253952"
+ UBI_IMAGE_SEQ = "1024"
+-
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++LYNQ_M22_PAGESIZE = "0x800"
++LYNQ_M22_ERASEBLOCK = "0x20000"
++LYNQ_M22_UBI_LEB_SIZE = "126976"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ #rootfs ubi参数配置
+ #MKUBIFS_ARGS = "-m ${PAGESIZE} -e ${UBI_LEB_SIZE} -c 122 -x zlib -F"
+ UBINIZE_ARGS = "-m ${PAGESIZE} -p ${ERASEBLOCK} -s ${PAGESIZE} -Q ${UBI_IMAGE_SEQ}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++LYNQ_M22_UBINIZE_ARGS = "-m ${LYNQ_M22_PAGESIZE} -p ${LYNQ_M22_ERASEBLOCK} -s ${LYNQ_M22_PAGESIZE} -Q ${UBI_IMAGE_SEQ}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ #userdata ubi参数配置
+ USERDATA_UBINIZE_ARGS = "${UBINIZE_ARGS}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++LYNQ_M22_USERDATA_UBINIZE_ARGS = "${LYNQ_M22_UBINIZE_ARGS}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+diff --git a/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf b/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
+index 50c2f6e..231b4a1 100755
+--- a/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
++++ b/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
+@@ -51,7 +51,9 @@
+
+ # storage type: nand or emmc
+ STRORAGE_TYPE = "nand"
+-STRORAGE_CONF = "nand-config-4k"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++STRORAGE_CONF = "nand-config-default"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ require conf/distro/include/${STRORAGE_CONF}.inc
+
+ #rootfs文件系统类型
+@@ -467,6 +469,9 @@
+ #xf.li@20240716 add for MOBILETEK_LOG_ENCRYPT value: "enable","disable"
+ MOBILETEK_LOG_ENCRYPT = "disable"
+
++#xf.li@20250123 add for M22 SDK value (support M22 or not): "M22", "default"
++MOBILETEK_NAND_TYPE = "M22"
++
+ LYNQ_CONFIG_COMMITID = "e2a3410390ff0ad762462ccb6af8faa5e16dcd61"
+-LYNQ_CONFIG_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
+-LYNQ_CONFIG_SW_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
++LYNQ_CONFIG_VERSION = "T106-M42-PLXXXX-P56U11.AP.19.00_CAP.19.00.01"
++LYNQ_CONFIG_SW_VERSION = "T106-MXX-PLXXXX-P56U11.AP.19.00_CAP.19.00"
+diff --git a/esdk/layers/meta-zxic-custom/conf/lynq_base.conf b/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
+index 8126a9e..73d9856 100755
+--- a/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
++++ b/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
+@@ -67,6 +67,6 @@
+ #OEMAPP_CFG value:"PLATFORM","GSW"
+ MOBILETEK_OEMAPP_CFG = "PLATFORM"
+
+-LYNQ_CONFIG_COMMITID = "db2a7e1b3aa519b00153f78dcb223c2eb539f891"
+-LYNQ_CONFIG_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
+-LYNQ_CONFIG_SW_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
++LYNQ_CONFIG_COMMITID = "7b4d681bdad8b0a31c564ea665a424b81038791a"
++LYNQ_CONFIG_VERSION = "T106-M42-PLXXXX-P56U11.AP.19.00_CAP.19.00.01"
++LYNQ_CONFIG_SW_VERSION = "T106-MXX-PLXXXX-P56U11.AP.19.00_CAP.19.00"
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
+index 2b48930..34e65ab 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
++++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
+@@ -50,7 +50,7 @@
+ CONFIG_SYSROOT=""
+ CONFIG_EXTRA_CFLAGS=""
+ CONFIG_EXTRA_LDFLAGS=""
+-CONFIG_EXTRA_LDLIBS="-lnvram"
++CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+ #
+ # Installation Options ("make install" behavior)
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
+index 2b48930..34e65ab 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
++++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
+@@ -50,7 +50,7 @@
+ CONFIG_SYSROOT=""
+ CONFIG_EXTRA_CFLAGS=""
+ CONFIG_EXTRA_LDFLAGS=""
+-CONFIG_EXTRA_LDLIBS="-lnvram"
++CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+ #
+ # Installation Options ("make install" behavior)
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
+index 2b48930..34e65ab 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
++++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
+@@ -50,7 +50,7 @@
+ CONFIG_SYSROOT=""
+ CONFIG_EXTRA_CFLAGS=""
+ CONFIG_EXTRA_LDFLAGS=""
+-CONFIG_EXTRA_LDLIBS="-lnvram"
++CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+ #
+ # Installation Options ("make install" behavior)
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
+index 5d7d82f..bd0c63c 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
++++ b/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
+@@ -50,7 +50,7 @@
+ CONFIG_SYSROOT=""
+ CONFIG_EXTRA_CFLAGS=""
+ CONFIG_EXTRA_LDFLAGS=""
+-CONFIG_EXTRA_LDLIBS="-lnvram"
++CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+ #
+ # Installation Options ("make install" behavior)
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
+index 5234be8..7570274 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
++++ b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
+@@ -500,4 +500,5 @@
+ telog_path=
+ zpsstate_detect=1
+ zpsstate_detect_period=60
+-zpsstate_restart=0
+\ No newline at end of file
++zpsstate_restart=0
++ap_reset_app=default
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
+index 7147993..63f20d3 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
++++ b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
+@@ -499,4 +499,5 @@
+ telog_path=
+ zpsstate_detect=1
+ zpsstate_detect_period=60
+-zpsstate_restart=0
+\ No newline at end of file
++zpsstate_restart=0
++ap_reset_app=default
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
+index f082891..f7695af 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
++++ b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
+@@ -551,4 +551,5 @@
+ telog_path=
+ zpsstate_detect=1
+ zpsstate_detect_period=60
+-zpsstate_restart=0
+\ No newline at end of file
++zpsstate_restart=0
++ap_reset_app=default
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
+index 92191d4..4c1dd17 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
++++ b/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
+@@ -495,3 +495,4 @@
+ xlat_enable=1
+ telog_path_cap=
+ telog_path=
++ap_reset_app=default
+diff --git a/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb b/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
+index b86b882..1a77daa 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
++++ b/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
+@@ -147,6 +147,11 @@
+ cp -arfp ${BSPDIR}/sources/meta-zxic-custom/conf/distro/include/${USERDATA_UBINIZE_CFG} ${B}
+ mkdir -p ${BINS-PATH}
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/${USEDATA_FS_NAME}" "${B}/${USERDATA_UBINIZE_CFG}" "${USERDATA_UBINIZE_ARGS}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
++ ${B}/ubinize-cfg.sh "${BINS-PATH}/ap_capuserdata_M22.img" "${B}/${USERDATA_UBINIZE_CFG}" "${LYNQ_M22_USERDATA_UBINIZE_ARGS}"
++fi
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ mkdir -p ${IMAGE_ROOTFS}/etc_ro/
+ cp -v "${BINS-PATH}/${USEDATA_FS_NAME}" ${IMAGE_ROOTFS}/etc_ro/
+ fi
+@@ -207,6 +212,11 @@
+ cp -arfp ${BSPDIR}/sources/meta-zxic-custom/conf/distro/include/${OEMDATA_UBINIZE_CFG} ${B}
+ mkdir -p ${BINS-PATH}
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/${OEMDATA_FS_NAME}" "${B}/${OEMDATA_UBINIZE_CFG}" "${USERDATA_UBINIZE_ARGS}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
++ ${B}/ubinize-cfg.sh "${BINS-PATH}/cap_oemdata_M22.img" "${B}/${OEMDATA_UBINIZE_CFG}" "${LYNQ_M22_USERDATA_UBINIZE_ARGS}"
++fi
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ mkdir -p ${IMAGE_ROOTFS}/etc_ro/
+ cp -v "${BINS-PATH}/${OEMDATA_FS_NAME}" ${IMAGE_ROOTFS}/etc_ro/
+ fi
+@@ -234,12 +244,21 @@
+ ${S}/squashfs_dm-verity.sh ${S}/${ROOT_FS_NAME}.unsigned ${S} \
+ ${BINS-PATH}/ap_caprootfs.img.dm ${SIGNIMAGE_PRIVATE_KEY} ${BSPDIR}/tools/SignTool/SignImage
+ ${S}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs.img" ${BINS-PATH}/ap_caprootfs.img.dm "${UBINIZE_ARGS}"
+-
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
++ ${S}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs_M22.img" ${BINS-PATH}/ap_caprootfs.img.dm "${LYNQ_M22_UBINIZE_ARGS}"
++fi
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ if ${@bb.utils.contains('DISTRO_FEATURES','oemfs','true','false',d)}; then
+ rm -fv ${BINS-PATH}/cap_oem.img.dm
+ ${B}/squashfs_dm-verity.sh ${S}/cap_oem.img.unsigned ${B} \
+ ${BINS-PATH}/cap_oem.img.dm ${SIGNIMAGE_PRIVATE_KEY} ${BSPDIR}/tools/SignTool/SignImage
+ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem.img" ${BINS-PATH}/cap_oem.img.dm "${UBINIZE_ARGS}"
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
++if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
++ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem_M22.img" ${BINS-PATH}/cap_oem.img.dm "${LYNQ_M22_UBINIZE_ARGS}"
++fi
++#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ fi
+ fi
+ }
+@@ -258,6 +277,8 @@
+ "
+ #xf.li@20240716 add start
+ do_oem_config() {
++ LYNQ_INSIDE_VERSION_UCI=" option LYNQ_SW_INSIDE_VERSION '${LYNQ_CONFIG_VERSION}'"
++ eval sed -i 's/^.*LYNQ_SW_INSIDE_VERSION.*$/"${LYNQ_INSIDE_VERSION_UCI}"/' ${IMAGE_ROOTFS}/etc/config/lynq_uci_ro
+ cp -R ${TOPDIR}/prebuilt/rootfs/* ${IMAGE_ROOTFS}/
+ if [ "${MOBILETEK_LOG_ENCRYPT}" = "enable" ]; then
+ touch ${IMAGE_ROOTFS}/etc/syslog_encrypt_flag
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb b/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
+index 7b8ff1d..65d5358 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
+@@ -3,7 +3,7 @@
+ DESCRIPTION = "lynq sim"
+ LICENSE = "CLOSED"
+ LIC_FILES_CHKSUM = "file://LICENSE;md5=e1696b147d49d491bcb4da1a57173fff"
+-DEPENDS += "libpal gstreamer1.0 glib-2.0 libapn liblynq-log libvendor-ril liblynq-shm libbinder"
++DEPENDS += "libpal gstreamer1.0 glib-2.0 libapn liblynq-log libvendor-ril liblynq-shm libbinder liblynq-uci libsctel"
+ #inherit workonsrc
+ WORKONSRC = "${TOPDIR}/../src/lynq/lib/liblynq-sim/"
+ FILESEXTRAPATHS_prepend :="${TOPDIR}/../src/lynq/lib/:"
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb b/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
+index aeecf6e..c709cf9 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
+@@ -4,7 +4,7 @@
+ #LICENSE = "Mobiletek""
+ LICENSE = "CLOSED"
+ LIC_FILES_CHKSUM = "file://LICENSE;md5=d759532d295a4ec07250edf931caef80"
+-DEPENDS += "bootchart liblynq-log libsctel libscrtc"
++DEPENDS += "bootchart liblynq-log libsctel libscrtc libsoftap"
+
+ #inherit workonsrc
+ WORKONSRC = "${TOPDIR}/../src/lynq/lib/libpoweralarm/"
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
+index aee4285..a6c8e15 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
+@@ -42,23 +42,25 @@
+ }E_QSER_NW_IMS_MODE_TYPE_T;
+
+ /** Configures the OOS (out of service) settings that define the MCM network interface. */
+-#define QSER_NW_OOS_CFG_TYPE_FAST_SCAN 0x00 /**< fast net scan */
+-#define QSER_NW_OOS_CFG_TYPE_FULL_BAND_SCAN 0x01 /**< full band scan */
++#define QSER_NW_OOS_CFG_TYPE_FAST_SCAN 0x00 /**< fast net scan, only for normal mode */
++#define QSER_NW_OOS_CFG_TYPE_FULL_BAND_SCAN 0x01 /**< full band scan, only for low power mode */
+
+ typedef struct
+ {
+- /* Configuration parameters for MCM network fast network scan when OOS (out of service)*/
+- char enable;
+- uint16_t time_interval;
++ /* Configuration parameters for MCM network fast network scan when OOS (out of service) in normal mode*/
++ char enable; /*[0, 1]*/
++ uint16_t time_interval; /*[1, 65535],unit: second, valid when enable equal 1*/
+ }QSER_NW_OOS_CONFIG_FAST_SCAN_INFO_T;
+
+ typedef struct
+ {
+- /* Configuration parameters for MCM network full band network scan when OOS (out of service)*/
+- int t_min;
+- int t_step;
+- int t_num;
+- int t_max;
++ /* Configuration parameters for MCM network full band network scan when OOS (out of service) in low power mode*/
++ /*t_min,t_step,t_num,t_max all are 0, or all are not 0*/
++ /*if t_min > t_max, time interval will be t_max*/
++ int t_min; /*[0, 65535], unit: second*/
++ int t_step; /*[0, 65535], unit: second*/
++ int t_num; /*[0, 65535]*/
++ int t_max; /*[0, 65535], unit: second*/
+ }QSER_NW_OOS_CONFIG_FULL_BAND_SCAN_INFO_T;
+
+
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
+index e7eebc3..e9730f1 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
+@@ -31,6 +31,8 @@
+ #endif
+ {9, "qser_voice_set_audio_mode"},
+ {10, "qser_voice_get_audio_mode"},
++ {11, "qser_voice_set_mic_volume"},
++ {12, "qser_voice_get_mic_volume"},
+ {-1, NULL}
+ };
+
+@@ -56,6 +58,9 @@
+ int (*qser_voice_set_audio_mode)(const int audio_mode);
+ int (*qser_voice_get_audio_mode)(int* audio_mode);
+
++int (*qser_voice_set_mic_volume)(const int volume);
++int (*qser_voice_get_mic_volume)(int *volume);
++
+
+ #ifdef ECALL_SUPPORT
+ int (*qser_voice_set_test_num)(voice_client_handle_type* h_voice,E_QSER_VOICE_ECALL_SET_TYPE_T type, const char *test_num, int test_num_length);
+@@ -252,6 +257,19 @@
+ printf("qser_voice_get_audio_mode not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
++ qser_voice_set_mic_volume = (int (*)(const int ))dlsym(dlHandle_call,"qser_voice_set_mic_volume");
++ if(qser_voice_set_mic_volume == NULL)
++ {
++ printf("qser_voice_set_mic_volume not defined or exported in %s\n", lynqLibPath_Call);
++ return -1;
++ }
++
++ qser_voice_get_mic_volume = (int (*)(int* ))dlsym(dlHandle_call,"qser_voice_get_mic_volume");
++ if(qser_voice_get_mic_volume == NULL)
++ {
++ printf("qser_voice_get_mic_volume not defined or exported in %s\n", lynqLibPath_Call);
++ return -1;
++ }
+
+
+ ret = qser_voice_call_client_init(&h_voice);
+@@ -419,7 +437,25 @@
+ printf("qser_voice_get_audio_mode ret = %d, audio_mode is %d\n", ret, audio_mode);
+ break;
+ }
++ case 11:
++ {
++ int volume = 0;
++ printf("Please set mic volume:0-5 level\n");
++ scanf("%d",&volume);
++ ret = qser_voice_set_mic_volume(volume);
++ printf("ret is %d\n",ret);
++ break;
+
++ }
++
++ case 12:
++ {
++ int volume = -1;
++ printf("Enter get mic volume\n");
++ ret = qser_voice_get_mic_volume(&volume);
++ printf("ret is %d,get volume is %d\n",ret,volume);
++ break;
++ }
+ default:
+ print_help();
+ break;
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
+index fc94d2a..a3e6499 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
+@@ -14,12 +14,17 @@
+ #include <semaphore.h>
+ #include <sys/types.h>
+ #include <pthread.h>
++#include <log/log.h>
++#include <time.h>
++#define LOG_TAG "VB_DEMO"
++
++
+
+ /*command max len*/
+ #define VOICE_CMD_MAX_LEN 64
+
+-#define EXIT_CMD_STOP "stop\n"
+-#define EXIT_CMD_Q "q\n"
++#define EXIT_CMD_STOP "stop\n"
++#define EXIT_CMD_Q "q\n"
+ #define EXIT_CMD_EXIT "exit\n"
+
+ #define REQ_VOICE_BUFFER_TEST_START "voice_buffer_test_start"
+@@ -38,7 +43,7 @@
+
+
+
+-#define VB_MAX_INT 0x7fffffff
++#define VB_MAX_INT 0x7fffffff
+ #define VB_MIN_INT 0
+ #define VB_INT_OVERFLOW(x) if((x < VB_MIN_INT)||(x > VB_MAX_INT)) x = 0;
+
+@@ -49,21 +54,21 @@
+ typedef int (vb_thread_proc)(void*);
+ struct vbuf_info_t
+ {
+- int fd;
+- pthread_t rx_test_thread;
+- pthread_t tx_test_thread;
+- pthread_t loop_test_thread;
+- int quit;
+- char *tx_buf;
+- char *rx_buf;
+- int buf_size;
+- char *tx_filename;
+- char *rx_filename;
++ int fd;
++ pthread_t rx_test_thread;
++ pthread_t tx_test_thread;
++ pthread_t loop_test_thread;
++ int quit;
++ char *tx_buf;
++ char *rx_buf;
++ int buf_size;
++ char *tx_filename;
++ char *rx_filename;
+ FILE *tx_file;
+- FILE *rx_file;
++ FILE *rx_file;
+ int tx_filesize;
+- int rx_filesize;
+- int fs;
++ int rx_filesize;
++ int fs;
+ };
+
+ static struct vbuf_info_t vbuf_rec;
+@@ -74,40 +79,47 @@
+
+ printf("voice_buffer_test_start value: 8000,16000\n");
+ printf("voice_buffer_test_stop no value input\n");
+- printf("voice_buffer_loop_test_start value: 8000,16000\n");
++ printf("voice_buffer_loop_test_start value: 8000,16000\n");
+ printf("voice_buffer_loop_test_stop no value input\n");
+ printf("\n");
+ }
+
+ static int vbuffer_start_flag = 0;
+ static int tx_optcount = 0;
+-static int rx_optcount = 0;
++static int rx_optcount = 0;
+ static int first_rderr_flag = 0;
+ static int first_wrerr_flag = 0;
+
++static pthread_mutex_t s_vb_demo_mtx = PTHREAD_MUTEX_INITIALIZER;
++
+ static int vb_close_fd_release_buf()
+-{
+- int ret = voice_buffer_close(vbuf_rec.fd);
+- if(ret != 0)
++{
++ int ret=0;
++ if(vbuf_rec.fd>0)
+ {
+- printf("%s : vb close fail \n",__func__);
++ ret = voice_buffer_close(vbuf_rec.fd);
++ if(ret != 0)
++ {
++ RLOGE("%s : vb close fail ret is %d\n",__func__,ret);
++ }
++ vbuf_rec.fd = -1;
+ }
+- vbuf_rec.fd = -1;
++
+
+ if(vbuf_rec.rx_buf)
+ {
+- free(vbuf_rec.rx_buf);
+- vbuf_rec.rx_buf = NULL;
++ free(vbuf_rec.rx_buf);
++ vbuf_rec.rx_buf = NULL;
+ }
+
+ if(vbuf_rec.tx_buf)
+ {
+ free(vbuf_rec.tx_buf);
+- vbuf_rec.tx_buf = NULL;
++ vbuf_rec.tx_buf = NULL;
+ }
+
+- vbuffer_start_flag = 0;
+- printf("close buf fd and release buf end\n");
++ vbuffer_start_flag = 0;
++ RLOGD("close buf fd and release buf end\n");
+ return ret;
+ }
+
+@@ -124,56 +136,56 @@
+ int r_size;
+
+
+- printf( "%s: start size=%d! \n",__func__,size);
++ RLOGD( "%s: start size=%d! \n",__func__,size);
+ memset (buf,0, size);
+
+ while (!vbuf_rec.quit)
+ {
+- rx_optcount ++;
+- VB_INT_OVERFLOW(rx_optcount);
+- if((rx_optcount%1000) == 0){
+- printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
++ rx_optcount ++;
++ VB_INT_OVERFLOW(rx_optcount);
++ if((rx_optcount%1000) == 0){
++ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+
+- }
+- else if(rx_optcount == 1000000){
+- printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+- rx_optcount = 0;
+-
+- }
++ }
++ else if(rx_optcount == 1000000){
++ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
++ rx_optcount = 0;
++
++ }
+
+ //read form ps
+- r_size = voice_buffer_read(vbuf_rec.fd, buf, size);
++ r_size = voice_buffer_read(vbuf_rec.fd, buf, size);
+ if(r_size <= 0)
+ {
+- first_rderr_flag++;
+- VB_INT_OVERFLOW(first_rderr_flag);
++ first_rderr_flag++;
++ VB_INT_OVERFLOW(first_rderr_flag);
+ continue ;
+ }
+- else{
+- first_rderr_flag = 0;
++ else{
++ first_rderr_flag = 0;
+
+- }
+-
++ }
++
+ if(vbuf_rec.rx_file != NULL)
+ {
+- r_size = fwrite(buf, 1,size, vbuf_rec.rx_file);
++ r_size = fwrite(buf, 1,size, vbuf_rec.rx_file);
+
+- if (r_size != size) {
+- //printf("Error fwrite size not eq,r_size=%d,size=%d\n",r_size,size);
+- }
+- else{
+-
+- bytes_read += size;
+- if(bytes_read >= vbuf_rec.rx_filesize){
+- fseek(vbuf_rec.rx_file, 0, SEEK_SET);
+- bytes_read = 0;
+- printf("fwrite over write maxsize(%d)!!!\n",vbuf_rec.rx_filesize);
+-
+- }
+- }
++ if (r_size != size) {
++ //printf("Error fwrite size not eq,r_size=%d,size=%d\n",r_size,size);
++ }
++ else{
++
++ bytes_read += size;
++ if(bytes_read >= vbuf_rec.rx_filesize){
++ fseek(vbuf_rec.rx_file, 0, SEEK_SET);
++ bytes_read = 0;
++ RLOGD("fwrite over write maxsize(%d)!!!\n",vbuf_rec.rx_filesize);
++
++ }
++ }
+ }
+-
+-
++
++
+ }
+
+ return 0;
+@@ -184,65 +196,65 @@
+ int ret;
+ int num_read;
+
+-
++
+ char* buf = vbuf_rec.tx_buf;
+-
++
+ int size = vbuf_rec.buf_size;
+ int w_size;
+
+- printf("%s: start size=%d! \n",__func__,size);
++ RLOGD("%s: start size=%d! \n",__func__,size);
+
+-
++
+ memset(buf, 0,size);
+ while (!vbuf_rec.quit)
+ {
+
+- if(vbuf_rec.tx_file != NULL)
+- {
++ if(vbuf_rec.tx_file != NULL)
++ {
+
+- num_read = fread(buf,1,size, vbuf_rec.tx_file);
+-
+- if (num_read != size) {
+- //printf("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
+- }
+- if (num_read <= 0) {
+- printf("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
+- fseek(vbuf_rec.tx_file, 0, SEEK_SET);
+- }
+- }
+- tx_optcount ++;
+- VB_INT_OVERFLOW(tx_optcount);
+-
+- w_size = voice_buffer_write(vbuf_rec.fd, buf, size);
++ num_read = fread(buf,1,size, vbuf_rec.tx_file);
++
++ if (num_read != size) {
++ //printf("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
++ }
++ if (num_read <= 0) {
++ RLOGD("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
++ fseek(vbuf_rec.tx_file, 0, SEEK_SET);
++ }
++ }
++ tx_optcount ++;
++ VB_INT_OVERFLOW(tx_optcount);
++
++ w_size = voice_buffer_write(vbuf_rec.fd, buf, size);
+ if(w_size <= 0)
+ {
+- first_wrerr_flag++;
+-
+- VB_INT_OVERFLOW(first_wrerr_flag);
+-
++ first_wrerr_flag++;
++
++ VB_INT_OVERFLOW(first_wrerr_flag);
++
+ continue;
+ }
+- else{
+- first_wrerr_flag = 0;
++ else{
++ first_wrerr_flag = 0;
+
+- }
++ }
+
+ }
+ return 0;
+ }
+
+
+-static int vb_thread_create( const char *name,pthread_t *thread_t, vb_thread_proc *proc,
+- int stack_size, unsigned priority,void *arg )
++static int vb_thread_create( const char *name,pthread_t *thread_t, vb_thread_proc *proc,
++ int stack_size, unsigned priority,void *arg )
+ {
+ pthread_attr_t thread_attr;
+ int ret;
+- int default_size;
++ int default_size;
+
+ struct sched_param param;
+ int policy = SCHED_FIFO;
+
+- printf("%s: start! \n",__func__);
++ RLOGD("%s: start! \n",__func__);
+
+ /* Init thread attributes */
+ pthread_attr_init(&thread_attr);
+@@ -251,18 +263,18 @@
+ ret = pthread_create( thread_t, &thread_attr,proc, arg);
+ if (ret != 0)
+ {
+- printf("%s: pthread_create fail,ret=%d! \n",__func__,ret);
++ RLOGE("%s: pthread_create fail,ret=%d! \n",__func__,ret);
+
+- pthread_attr_destroy(&thread_attr);
++ pthread_attr_destroy(&thread_attr);
+ return ret;
+ }
+-
++
+ pthread_attr_getstacksize(&thread_attr, &default_size);
+- printf("%s: pthread_attr_getstacksize(%d)! \n",__func__,default_size);
++ RLOGD("%s: pthread_attr_getstacksize(%d)! \n",__func__,default_size);
+
+ pthread_attr_destroy(&thread_attr);
+-
+- printf("%s: end \n",__func__);
++
++ RLOGD("%s: end \n",__func__);
+ return 0;
+ }
+
+@@ -273,136 +285,136 @@
+ {
+ int ret = 0;
+ int buf_size = 320;
+- tx_optcount = 0;
+- rx_optcount = 0;
++ tx_optcount = 0;
++ rx_optcount = 0;
+ int* buf_int;
+
+- int i;
++ int i;
+
+- if(vbuffer_start_flag == 1){
+- printf(" VB already start,return \n");
++ if(vbuffer_start_flag == 1){
++ RLOGE(" VB already start,return \n");
+
+- return 0;
+- }
++ return 0;
++ }
+
+- vbuffer_start_flag = 1;
++ vbuffer_start_flag = 1;
+
+
+
+- if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
+- printf(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
+- }
++ if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
++ RLOGE(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
++ }
+
+- if(fs == 8000){
++ if(fs == 8000){
+
+- buf_size = 320;
+- }
+- else if(fs == 16000){
++ buf_size = 320;
++ }
++ else if(fs == 16000){
+
+- buf_size = 640;
+- }
+- else
+- {
+- buf_size = 320;
+- }
+- printf("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
++ buf_size = 640;
++ }
++ else
++ {
++ buf_size = 320;
++ }
++ RLOGD("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
+
+- printf("%s:open tx and rx file \n",__func__);
+- if(fs == 8000){
++ RLOGD("%s:open tx and rx file \n",__func__);
++ if(fs == 8000){
+
+- vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
+- vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
++ vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
++ vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
+
+- }
+- else if(fs == 16000){
++ }
++ else if(fs == 16000){
+
+- vbuf_rec.tx_filename = VBUFFER_TX16_FILE_NAME;//"/cache/tx16.pcm";
+- vbuf_rec.rx_filename = VBUFFER_RX16_FILE_NAME;//"/cache/rx16.pcm";
++ vbuf_rec.tx_filename = VBUFFER_TX16_FILE_NAME;//"/cache/tx16.pcm";
++ vbuf_rec.rx_filename = VBUFFER_RX16_FILE_NAME;//"/cache/rx16.pcm";
+
+- }
+- else
+- {
+- vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
+- vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
++ }
++ else
++ {
++ vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
++ vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
+
+- }
++ }
+
+
+
+-
++
+ vbuf_rec.tx_file = fopen(vbuf_rec.tx_filename , "rb");
+ if (!vbuf_rec.tx_file) {
+- printf("Unable to open file '%s'\n", vbuf_rec.tx_filename);
++ RLOGE("Unable to open file '%s'\n", vbuf_rec.tx_filename);
+ //return -1;
+ }
+
+
+ vbuf_rec.rx_file = fopen(vbuf_rec.rx_filename, "wb");
+ if (!vbuf_rec.rx_file) {
+- printf(stderr, "Unable to create file '%s'\n", vbuf_rec.rx_filename);
+- //fclose(vbuf_rec.tx_file);
++ RLOGE("Unable to create file '%s'\n", vbuf_rec.rx_filename);
++ //fclose(vbuf_rec.tx_file);
+
+ //return -1;
+ }
+- vbuf_rec.rx_filesize = RX_FILE_LEN_MAX;
+- printf("%s : vbuf_rec.rx_filesize(%d) \n",__func__,vbuf_rec.rx_filesize);
++ vbuf_rec.rx_filesize = RX_FILE_LEN_MAX;
++ RLOGD("%s : vbuf_rec.rx_filesize(%d) \n",__func__,vbuf_rec.rx_filesize);
+
+ vbuf_rec.rx_buf = (char*) malloc(buf_size);
+- if(!vbuf_rec.rx_buf) {
+- printf("%s : malloc buf fail,return \n",__func__);
+- goto err;
+- }
++ if(!vbuf_rec.rx_buf) {
++ RLOGE("%s : malloc buf fail,return \n",__func__);
++ goto err;
++ }
+ vbuf_rec.tx_buf = (char*) malloc(buf_size);
+- if(!vbuf_rec.tx_buf) {
+- free(vbuf_rec.rx_buf);
+- printf("%s : malloc buf fail,return \n",__func__);
+- vbuf_rec.rx_buf = NULL;
+- goto err;
+- }
+- vbuf_rec.buf_size = buf_size;
+-
++ if(!vbuf_rec.tx_buf) {
++ free(vbuf_rec.rx_buf);
++ RLOGE("%s : malloc buf fail,return \n",__func__);
++ vbuf_rec.rx_buf = NULL;
++ goto err;
++ }
++ vbuf_rec.buf_size = buf_size;
++
+ vbuf_rec.quit = 0;
+-
+- printf("%s : vb open start \n",__func__);
++
++ RLOGD("%s : vb open start \n",__func__);
+
+-
++
+ vbuf_rec.fd = voice_buffer_open();
+- if(vbuf_rec.fd <= 0){
+- printf("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
+- ret = -1;
+- goto err;
+-
+- }
+- printf("%s :voice_buffer_open end \n",__func__);
+-
+- printf("%s :rx tx vb_thread_create start \n",__func__);
++ if(vbuf_rec.fd <= 0){
++ RLOGE("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
++ ret = -1;
++ goto err;
++
++ }
++ RLOGD("%s :voice_buffer_open end \n",__func__);
++
++ RLOGD("%s :rx tx vb_thread_create start \n",__func__);
+ ret = vb_thread_create ("vb_playback_test",&vbuf_rec.rx_test_thread, vb_rx_test_thread_func,
+- 4*1024,35,NULL);
++ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+- printf("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
++ RLOGE("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ vbuf_rec.rx_test_thread = NULL;
+- goto err;
++ goto err;
+ }
+
+- printf("%s :rx vb_thread_create end \n",__func__);
++ RLOGD("%s :rx vb_thread_create end \n",__func__);
+
+ ret = vb_thread_create ( "vbuf_record_test", &vbuf_rec.tx_test_thread, vb_tx_test_thread_func,
+- 4*1024,35,NULL);
++ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+
+- printf("%s :tx vb_thread_create fail ret=%d,return \n",__func__,ret);
++ RLOGE("%s :tx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ vbuf_rec.tx_test_thread = NULL;
+- goto err;
++ goto err;
+ }
+- printf("%s :tx vb_thread_create end \n",__func__);
++ RLOGD("%s :tx vb_thread_create end \n",__func__);
+
+ return 0;
+
+ err:
+ voice_buffer_stream_test_stop();
+-
++
+ return ret;
+ }
+
+@@ -411,42 +423,42 @@
+ int voice_buffer_stream_test_stop(void)
+ {
+ int ret = 0;
+- printf("%s:rx tx thread exit start \n",__func__);
+- if(vbuf_rec.quit == 1) {
+- printf("%s,already stop ,return\n",__func__);
++ RLOGD("%s:rx tx thread exit start \n",__func__);
++ if(vbuf_rec.quit == 1) {
++ RLOGD("%s,already stop ,return\n",__func__);
+
+- }
++ }
+
+ vbuf_rec.quit = 1;
+- voice_buffer_stop(vbuf_rec.fd);
++ voice_buffer_stop(vbuf_rec.fd);
+ if (vbuf_rec.tx_test_thread)
+ {
+ pthread_join (vbuf_rec.tx_test_thread,NULL);
+ vbuf_rec.tx_test_thread = NULL;
+-
++
+ }
+
+ if (vbuf_rec.rx_test_thread)
+- {
++ {
+ pthread_join (vbuf_rec.rx_test_thread,NULL);
+ vbuf_rec.rx_test_thread = NULL;
+ }
+-
+- if(vbuf_rec.tx_file != NULL)
+- {
+- fclose(vbuf_rec.tx_file);
+- printf("%s : vb close ,close tx file \n",__func__);
+- vbuf_rec.tx_file = NULL;
+- }
+-
+- if(vbuf_rec.rx_file != NULL)
+- {
++
++ if(vbuf_rec.tx_file != NULL)
++ {
++ fclose(vbuf_rec.tx_file);
++ RLOGD("%s : vb close ,close tx file \n",__func__);
++ vbuf_rec.tx_file = NULL;
++ }
++
++ if(vbuf_rec.rx_file != NULL)
++ {
+
+- fclose(vbuf_rec.rx_file);
+- printf("%s : vb close ,close rx file \n",__func__);
+- vbuf_rec.rx_file = NULL;
+-
+- }
++ fclose(vbuf_rec.rx_file);
++ RLOGD("%s : vb close ,close rx file \n",__func__);
++ vbuf_rec.rx_file = NULL;
++
++ }
+
+ vb_close_fd_release_buf();
+ return 0;
+@@ -460,55 +472,55 @@
+ char* buf = vbuf_rec.rx_buf;
+ int size = vbuf_rec.buf_size;
+
+- //char* buf = vbuf_rec.tx_buf;
+-
++ //char* buf = vbuf_rec.tx_buf;
++
+ //int size = vbuf_rec.buf_size;
+ int w_size;
+ int r_size;
+
+
+- printf( "%s: start size=%d! \n",__func__,size);
++ RLOGD( "%s: start size=%d! \n",__func__,size);
+ memset (buf,0, size);
+
+ while (!vbuf_rec.quit)
+ {
+- rx_optcount ++;
+- VB_INT_OVERFLOW(rx_optcount);
+- if((rx_optcount%1000) == 0){
+- printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
++ rx_optcount ++;
++ VB_INT_OVERFLOW(rx_optcount);
++ if((rx_optcount%1000) == 0){
++ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+
+- }
+- else if(rx_optcount == 1000000){
+- printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+- rx_optcount = 0;
+-
+- }
++ }
++ else if(rx_optcount == 1000000){
++ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
++ rx_optcount = 0;
++
++ }
+
+ //read form ps
+- r_size = voice_buffer_read(vbuf_rec.fd, vbuf_rec.rx_buf, size);
++ r_size = voice_buffer_read(vbuf_rec.fd, vbuf_rec.rx_buf, size);
+ if(r_size <= 0)
+ {
+- first_rderr_flag++;
+- VB_INT_OVERFLOW(first_rderr_flag);
++ first_rderr_flag++;
++ VB_INT_OVERFLOW(first_rderr_flag);
+ continue ;
+ }
+- else{
+- first_rderr_flag = 0;
+- }
++ else{
++ first_rderr_flag = 0;
++ }
+ memcpy(vbuf_rec.tx_buf,vbuf_rec.rx_buf,size);
+- w_size = voice_buffer_write(vbuf_rec.fd, vbuf_rec.tx_buf, size);
++ w_size = voice_buffer_write(vbuf_rec.fd, vbuf_rec.tx_buf, size);
+ if(w_size <= 0)
+ {
+- first_wrerr_flag++;
+-
+- VB_INT_OVERFLOW(first_wrerr_flag);
+-
++ first_wrerr_flag++;
++
++ VB_INT_OVERFLOW(first_wrerr_flag);
++
+ continue;
+ }
+- else{
+- first_wrerr_flag = 0;
+- }
+-
++ else{
++ first_wrerr_flag = 0;
++ }
++
+ }
+
+ return 0;
+@@ -521,98 +533,98 @@
+ {
+ int ret = -1;
+ int buf_size = 320;
+- tx_optcount = 0;
+- rx_optcount = 0;
++ tx_optcount = 0;
++ rx_optcount = 0;
+ int* buf_int;
+
+- int i;
++ int i;
+
+- if(vbuffer_start_flag == 1){
+- printf(" VB already start,return \n");
++ if(vbuffer_start_flag == 1){
++ RLOGE(" VB already start,return \n");
+
+- return 0;
+- }
+-
+- if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
+- printf(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
+- }
+-
+- vbuffer_start_flag = 1;
+-
+- if(fs == 8000){
+-
+- buf_size = 320;
+- }
+- else if(fs == 16000){
+-
+- buf_size = 640;
+- }
+- else
+- {
+- buf_size = 320;
+- }
+- printf("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
+-
+- vbuf_rec.rx_buf = (char*) malloc(buf_size);
+- if(!vbuf_rec.rx_buf) {
+- printf("%s : malloc buf fail,return \n",__func__);
+- goto err;
+- }
+- vbuf_rec.tx_buf = (char*) malloc(buf_size);
+- if(!vbuf_rec.tx_buf) {
+- printf("%s : malloc buf fail,return \n",__func__);
+- goto err;
+- }
+- vbuf_rec.buf_size = buf_size;
+-
+- vbuf_rec.quit = 0;
+-
+- printf("%s : vb open start \n",__func__);
+-
+-
+- vbuf_rec.fd = voice_buffer_open();
+- if(vbuf_rec.fd <= 0){
+- printf("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
+- goto err;
+-
+- }
+- printf("%s :loop vb_thread_create start \n",__func__);
+- ret = vb_thread_create ("vb_playback_test",&vbuf_rec.loop_test_thread, vb_loop_test_thread_func,
+- 4*1024,35,NULL);
+- if (ret != 0)
+- {
+- printf("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
+- goto err;
++ return 0;
+ }
+
+- printf("%s :rx vb_thread_create end \n",__func__);
++ if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
++ RLOGE(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
++ }
++
++ vbuffer_start_flag = 1;
++
++ if(fs == 8000){
++
++ buf_size = 320;
++ }
++ else if(fs == 16000){
++
++ buf_size = 640;
++ }
++ else
++ {
++ buf_size = 320;
++ }
++ RLOGD("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
++
++ vbuf_rec.rx_buf = (char*) malloc(buf_size);
++ if(!vbuf_rec.rx_buf) {
++ RLOGE("%s : malloc buf fail,return \n",__func__);
++ goto err;
++ }
++ vbuf_rec.tx_buf = (char*) malloc(buf_size);
++ if(!vbuf_rec.tx_buf) {
++ RLOGE("%s : malloc buf fail,return \n",__func__);
++ goto err;
++ }
++ vbuf_rec.buf_size = buf_size;
++
++ vbuf_rec.quit = 0;
++
++ RLOGD("%s : vb open start \n",__func__);
++
++
++ vbuf_rec.fd = voice_buffer_open();
++ if(vbuf_rec.fd <= 0){
++ RLOGE("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
++ goto err;
++
++ }
++ RLOGD("%s :loop vb_thread_create start \n",__func__);
++ ret = vb_thread_create ("vb_playback_test",&vbuf_rec.loop_test_thread, vb_loop_test_thread_func,
++ 4*1024,35,NULL);
++ if (ret != 0)
++ {
++ RLOGE("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
++ goto err;
++ }
++
++ RLOGD("%s :rx vb_thread_create end \n",__func__);
+
+ return 0;
+
+ err:
+- voice_buffer_stream_loop_test_stop();
+-
++ voice_buffer_stream_loop_test_stop();
++
+ return ret;
+ }
+
+ int voice_buffer_stream_loop_test_stop(void)
+ {
+ int ret = 0;
+- printf("%s:loop thread exit start \n",__func__);
+- if(vbuf_rec.quit == 1) {
+- printf("%s,already stop ,return\n",__func__);
++ RLOGD("%s:loop thread exit start \n",__func__);
++ if(vbuf_rec.quit == 1) {
++ RLOGD("%s,already stop ,return\n",__func__);
+
+- }
++ }
+
+ vbuf_rec.quit = 1;
+- voice_buffer_stop(vbuf_rec.fd);
++ voice_buffer_stop(vbuf_rec.fd);
+ if (vbuf_rec.loop_test_thread)
+ {
+ pthread_join (vbuf_rec.loop_test_thread,NULL);
+ vbuf_rec.tx_test_thread = NULL;
+-
++
+ }
+-
++
+ vb_close_fd_release_buf();
+ return 0;
+ }
+@@ -635,102 +647,110 @@
+ void voice_buffer_cmd_proc(char *cmdstr)
+ {
+ int ret = 0;
+- char data[VOICE_CMD_MAX_LEN];
+- int cmdstr_len = strlen(cmdstr); //-strlen("\r")
++ char data[VOICE_CMD_MAX_LEN];
++ int cmdstr_len = strlen(cmdstr); //-strlen("\r")
+ int value = 0;
+ int *p_value = &value;
++
++
+
+ cmdstr[cmdstr_len] = '\0'; //+strlen("\0")
+
+- ret = sscanf(cmdstr, "%s", data);
++ ret = sscanf(cmdstr, "%s", data);
+ if(1 != ret){
+- printf("data sscanf failed!(%d)\n", ret);
++ RLOGE("data sscanf failed!(%d)\n", ret);
+ return;
+ }
+- if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_START, strlen(REQ_VOICE_BUFFER_TEST_START))){
+
+- ret = sscanf(cmdstr, "%*s %d", &value);
++ pthread_mutex_lock(&s_vb_demo_mtx);
++ if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_START, strlen(REQ_VOICE_BUFFER_TEST_START))){
++
++ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+- printf("%s,value sscanf failed!(%d)\n",data, ret);
+- return;
++ RLOGE("%s,value sscanf failed!(%d)\n",data, ret);
++ goto vb_cmd_end;
+ }
+-
+- printf("%s set value %d\n", data, value);
+- ret = voice_buffer_stream_test_start(value);
++
++ RLOGD("%s set value %d\n", data, value);
++ ret = voice_buffer_stream_test_start(value);
+
+- printf("%s return ret=%d\n", data, ret);
+-
+- }
+- else if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_STOP, strlen(REQ_VOICE_BUFFER_TEST_STOP))){
+- ret = voice_buffer_stream_test_stop();
+- printf("%s return %d\n", data, ret);
+- }
+- else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_START, strlen(REQ_VOICE_BUFFER_LOOP_TEST_START))){
++ RLOGD("%s return ret=%d\n", data, ret);
++
++ }
++ else if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_STOP, strlen(REQ_VOICE_BUFFER_TEST_STOP))){
++ ret = voice_buffer_stream_test_stop();
++ RLOGD("%s return %d\n", data, ret);
++ }
++ else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_START, strlen(REQ_VOICE_BUFFER_LOOP_TEST_START))){
+
+- ret = sscanf(cmdstr, "%*s %d", &value);
++ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+- printf("%s,value sscanf failed!(%d)\n",data, ret);
+- return;
++ RLOGE("%s,value sscanf failed!(%d)\n",data, ret);
++ goto vb_cmd_end;
+ }
+-
+- printf("%s set value %d\n", data, value);
+- ret = voice_buffer_stream_loop_test_start(value);
++
++ RLOGD("%s set value %d\n", data, value);
++ ret = voice_buffer_stream_loop_test_start(value);
+
+- printf("%s return ret=%d\n", data, ret);
+-
+- }
+- else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_STOP, strlen(REQ_VOICE_BUFFER_LOOP_TEST_STOP))){
+- printf("voice_buffer_stream_loop_test_stop \n");
+- ret = voice_buffer_stream_loop_test_stop();
+- printf("%s return %d\n", data, ret);
+- }
++ RLOGD("%s return ret=%d\n", data, ret);
++
++ }
++ else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_STOP, strlen(REQ_VOICE_BUFFER_LOOP_TEST_STOP))){
++ RLOGD("voice_buffer_stream_loop_test_stop \n");
++ ret = voice_buffer_stream_loop_test_stop();
++ RLOGD("%s return %d\n", data, ret);
++ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_START, strlen(REQ_VOICE_BUFFER_RTP_TEST_START))){
+
+- ret = sscanf(cmdstr, "%*s %d", &value);
++ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+- printf("%s,value sscanf failed!(%d)\n",data, ret);
+- return;
++ RLOGE("%s,value sscanf failed!(%d)\n",data, ret);
++ goto vb_cmd_end;
+ }
+-
+- printf("%s set value %d\n", data, value);
+- ret = voice_buffer_rtp_test_start(value);
++
++ RLOGD("%s set value %d\n", data, value);
++ ret = voice_buffer_rtp_test_start(value);
+
+- printf("%s return ret=%d\n", data, ret);
+-
+- }
+- else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_STOP, strlen(REQ_VOICE_BUFFER_RTP_TEST_STOP))){
+- ret = voice_buffer_rtp_test_stop();
+- printf("%s return %d\n", data, ret);
+- }
++ RLOGD("%s return ret=%d\n", data, ret);
++
++ }
++ else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_STOP, strlen(REQ_VOICE_BUFFER_RTP_TEST_STOP))){
++ ret = voice_buffer_rtp_test_stop();
++ RLOGD("%s return %d\n", data, ret);
++ }
+ else{
+- printf("Request unknow.\n");
++ RLOGE("Request unknow.\n");
+ printUsage(cmdstr);
+- }
++ }
++vb_cmd_end:
++ pthread_mutex_unlock(&s_vb_demo_mtx);
+ }
+
+ void vb_buffer_stop_all()
+ {
+- voice_buffer_stream_loop_test_stop();
++ voice_buffer_stream_loop_test_stop();
+ voice_buffer_stream_test_stop();
+ voice_buffer_rtp_test_stop();
+ }
+
+ void signal_handle_func(int sig)
+ {
+- printf("sig(%d) signal_handle_func exit ",sig);
+-
++ RLOGD("sig(%d) signal_handle_func exit ",sig);
++
++ pthread_mutex_lock(&s_vb_demo_mtx);
+ vb_buffer_stop_all();
+- exit(0);
++ pthread_mutex_unlock(&s_vb_demo_mtx);
++ exit(0);
+ }
+
+ int main(int argc, char **argv)
+ {
+ char cmdstr[VOICE_CMD_MAX_LEN];
+-
+- signal(SIGINT, signal_handle_func);
+- signal(SIGQUIT, signal_handle_func);
+- signal(SIGTERM, signal_handle_func);
+- signal(SIGPIPE, signal_handle_func);
++
++ signal(SIGINT, signal_handle_func);
++ signal(SIGQUIT, signal_handle_func);
++ signal(SIGTERM, signal_handle_func);
++ signal(SIGPIPE, signal_handle_func);
+
+ memset(&vbuf_rec,0,sizeof(vbuf_rec));
+ #if 0
+@@ -743,27 +763,28 @@
+ else
+ {
+ #endif
+- while(1){
+- printf("Please input an voice_demo command:\n");
++ printf("Please input an voice_demo command:\n");
++ while(1){
+ if(NULL != fgets(cmdstr, VOICE_CMD_MAX_LEN - 1, stdin)){
+ if(0 == strcmp(EXIT_CMD_STOP, cmdstr) ||
+ 0 == strcmp(EXIT_CMD_Q, cmdstr) ||
+ 0 == strcmp(EXIT_CMD_EXIT, cmdstr)){
+- vb_buffer_stop_all();
+- break;
+- }
++ vb_buffer_stop_all();
++ break;
++ }
+
+- printf("len:%d, cmdstr:%s\n", strlen(cmdstr), cmdstr);
++ RLOGI("len:%d, cmdstr:%s\n", strlen(cmdstr), cmdstr);
+
+ if(1 >= strlen(cmdstr)){
+- continue;
+- }
+- voice_buffer_cmd_proc(cmdstr);
++ continue;
++ }
++ voice_buffer_cmd_proc(cmdstr);
+ }
+- }
+-// }
++ sleep(5);
++ }
++
+
+- printf("voice_demo end\n");
++ RLOGD("voice_demo end\n");
+
+ return 0;
+ }
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
+index 6a6f960..7117ebc 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
+@@ -26,6 +26,7 @@
+ LOCAL_LIBS := \
+ -L. \
+ -ldl \
++ -llog \
+ -lpthread \
+ -lvoice \
+
+diff --git a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
+index b01d3b0..5691603 100755
+--- a/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
++++ b/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
+@@ -3,7 +3,7 @@
+ DESCRIPTION = "lynq-vb-demo"
+ LICENSE = "CLOSED"
+ LIC_FILES_CHKSUM = "file://LICENSE;md5=b1e07e8d88e26263e71d3a9e2aa9a2ff"
+-DEPENDS += "libvoice"
++DEPENDS += "libbinder libvoice"
+ SRC_URI = "file://lynq_vb_demo.c \
+ file://makefile \
+ "
+diff --git a/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb b/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
+index b413ee2..236850c 100755
+--- a/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
++++ b/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
+@@ -1,5 +1,5 @@
+ DESCRIPTION = "libvoice"
+-DEPENDS = "libtinyalsa libnvram libsoftap libsofttimer"
++DEPENDS = "libtinyalsa libnvram libsoftap libsofttimer libdebug-info"
+ SECTION = "lib"
+ LICENSE = "zte"
+ PV = "1.0.0"
+@@ -15,11 +15,13 @@
+ S = "${WORKDIR}"
+ #引用公用头文件和编译选项。
+ include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
++include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+ CFLAGS_append = "-I ${BSPDIR}/zxic_code/zxic_source/zxic_app_open/platform/libtinyalsa/include"
+ CFLAGS_append = "-I ${BSPDIR}/zxic_code/zxic_source/linux-5.10/include/linux"
+
+
+ CFLAGS_append += "${@bb.utils.contains("CONFIG_VB_TRANSMIT_INTF", "RTP", "-I ${BSPDIR}/zxic_code/zxic_source/zxic_app/librtp/include", "", d)}"
++CFLAGS_append += "${ZXIC_EXTRA_CFLAGS}"
+ DEPENDS += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', 'librtp', '', d)}"
+ #编译
+ do_compile () {
+diff --git a/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb b/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
+index 69ad466..e7cf838 100755
+--- a/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
++++ b/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
+@@ -1,6 +1,6 @@
+ DESCRIPTION = "nvserver"
+ #nvserver依赖libnvram库
+-DEPENDS = "libmtd libnvram libflags libsd-daemon"
++DEPENDS = "libmtd libnvram libflags libsd-daemon libdebug-info"
+ SECTION = "app"
+ LICENSE = "zte"
+ PV = "1.0.0"
+diff --git a/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb b/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
+index dd579d3..37b2b5f 100755
+--- a/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
++++ b/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
+@@ -50,7 +50,9 @@
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/sntp.sysvinit ${D}${sysconfdir}/init.d/sntp
+ install -d ${D}${sysconfdir}/rcS.d
+- ln -s ../init.d/sntp ${D}${sysconfdir}/rcS.d/S22sntp
++ #xy.he@20250211 bug-view-378 add for disable sntp autostart start
++ #ln -s ../init.d/sntp ${D}${sysconfdir}/rcS.d/S22sntp
++ #xy.he@20250211 bug-view-378 add for disable sntp autostart end
+ fi
+
+ #install elfs
+@@ -73,4 +75,4 @@
+ SYSTEMD_SERVICE_${PN} = "sntp.service"
+ SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+-RDEPENDS_${PN} = " libdebug-info libnvram libsoftap libsofttimer"
+\ No newline at end of file
++RDEPENDS_${PN} = " libdebug-info libnvram libsoftap libsofttimer"
+diff --git a/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb b/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
+index 61650fa..0386349 100755
+--- a/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
++++ b/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
+@@ -1,6 +1,6 @@
+ DESCRIPTION = "zxic-debug"
+ #zxic-debug依赖libnvram库
+-DEPENDS = "libnvram"
++DEPENDS = "libnvram openssl "
+ SECTION = "app"
+ LICENSE = "zte"
+ PV = "1.0.0"
+diff --git a/esdk/layers/meta-zxic/recipes-core/busybox/busybox/busybox-1.33.1/0104-zxic-reboot-print-ppid.patch b/esdk/layers/meta-zxic/recipes-core/busybox/busybox/busybox-1.33.1/0104-zxic-reboot-print-ppid.patch
+new file mode 100755
+index 0000000..fe957aa
+--- /dev/null
++++ b/esdk/layers/meta-zxic/recipes-core/busybox/busybox/busybox-1.33.1/0104-zxic-reboot-print-ppid.patch
+@@ -0,0 +1,105 @@
++From 788511a2255d0416dfba782853bd20cb55b5ea67 Mon Sep 17 00:00:00 2001
++From: =?utf-8?q?=E5=91=A8=E5=9B=BD=E5=9D=A10318000136?=
++ <zhou.guopo@sanechips.com.cn>
++Date: Thu, 7 Nov 2024 14:18:56 +0800
++Subject: [PATCH] zxic reboot print ppid
++
++---
++ init/halt.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
++ 1 file changed, 74 insertions(+)
++
++diff --git a/init/halt.c b/init/halt.c
++index ddb03e2..93980b6 100644
++--- a/init/halt.c
+++++ b/init/halt.c
++@@ -154,6 +154,78 @@ static int init_was_not_there(void)
++ # define init_was_not_there() 0
++ #endif
++
+++extern int sc_debug_info_record(char *id, const char *format, ...);
+++static void get_app_name_by_pid(int pid, char *app_name, int app_name_len)
+++{
+++ char file_comm[256];
+++ FILE *pfile;
+++ size_t len;
+++
+++ memset(file_comm, 0, sizeof(file_comm));
+++ snprintf(file_comm, sizeof(file_comm), "/proc/%d/comm", pid);
+++
+++ pfile = fopen(file_comm, "r");
+++ if (pfile)
+++ {
+++ memset(app_name, 0, app_name_len);
+++ fgets(app_name, app_name_len, pfile);
+++ app_name[app_name_len-1] = '\0';
+++ app_name[strlen(app_name) - 1] = '\0'; //last byte is \n
+++ fclose(pfile);
+++ }
+++}
+++
+++static int get_ppid(int pid) {
+++ char path[256];
+++ snprintf(path, sizeof(path), "/proc/%d/stat", pid);
+++
+++ FILE *fp = fopen(path, "r");
+++ if (fp == NULL) {
+++ perror("fopen");
+++ return -1;
+++ }
+++
+++ int ppid = -1;
+++ // 通过解析第4列（ppid）来获取父进程ID
+++ fscanf(fp, "%*d %*s %*c %d", &ppid);
+++ fclose(fp);
+++ return ppid;
+++}
+++
+++static int get_reboot_caller(char *applet_name)
+++{
+++ int pid = get_ppid(getpid());
+++ char app_name[32];
+++ int app_name_len = sizeof(app_name);
+++ int try_cnt = 0;
+++
+++ while(1)
+++ {
+++ if (try_cnt > 5) {
+++ strcpy(app_name, "unkown");
+++ break;
+++ }
+++ try_cnt++;
+++ if (pid == 1) {
+++ get_app_name_by_pid(pid, app_name, app_name_len);
+++ break; //init
+++ }
+++ get_app_name_by_pid(pid, app_name, app_name_len);
+++ if ((strcmp(app_name, "sh") == 0) || (strcmp(app_name, "bash") == 0)) {
+++ //printf("shell %s continue %d\n", app_name, strlen(app_name));
+++ pid = get_ppid(pid); //sh continue
+++ } else {
+++ //printf("not sh break %s %d\n", app_name, strlen(app_name));
+++ break; //not sh
+++ }
+++ }
+++
+++ sc_debug_info_record("cap_reboot", "call %s reset_by %s(%d)\n", applet_name, app_name, pid);
+++ printf("call %s by %s(%d)\n", applet_name, app_name, pid);
+++
+++ return 0;
+++}
+++
++ int halt_main(int argc, char **argv) MAIN_EXTERNALLY_VISIBLE;
++ int halt_main(int argc UNUSED_PARAM, char **argv)
++ {
++@@ -180,6 +252,8 @@ int halt_main(int argc UNUSED_PARAM, char **argv)
++ for (which = 0; "hpr"[which] != applet_name[0]; which++)
++ continue;
++
+++ get_reboot_caller(applet_name); //add by zxic, print parent proccess name and pid
+++
++ /* Parse and handle arguments */
++ /* We support -w even if !ENABLE_FEATURE_WTMP,
++ * in order to not break scripts.
++--
++2.17.1
++
+diff --git a/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb b/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
+index a5a5bf4..43a4540 100755
+--- a/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
++++ b/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
+@@ -52,8 +52,9 @@
+ file://busybox-1.33.1/0100-zxic-tty-disable-soft-flow-control.patch \
+ file://busybox-1.33.1/700-dhcpd-fix.patch \
+ "
+-
+-SRC_URI += "file://busybox-1.33.1/010-syslogd-recive-remote-log.patch"
++#LYNQ_MODIFY_ZXW_TASK935_XF.Li_20250122_START
++#SRC_URI += "file://busybox-1.33.1/010-syslogd-recive-remote-log.patch"
++#LYNQ_MODIFY_ZXW_TASK935_XF.Li_20250122_END
+ SRC_URI += "file://busybox-1.33.1/020-syslogd-filesize-and-filenum-parameter-nvcfg.patch"
+ #SRC_URI += "file://busybox-1.33.1/022-syslogd-replace-remote-log-facility.patch"
+ SRC_URI += "file://busybox-1.33.1/0100-zxic-add-sync-after-chmod.patch"
+@@ -61,6 +62,7 @@
+ SRC_URI += "file://busybox-1.33.1/0102-zxic-ash-read-etc-profile.patch"
+ SRC_URI += "file://busybox-1.33.1/0103-top-short-lived-processes-optimize.patch"
+ SRC_URI += "file://busybox-1.33.1/0103-syslogd-data-encryption.patch"
++SRC_URI += "file://busybox-1.33.1/0104-zxic-reboot-print-ppid.patch"
+
+ SRC_URI_append_libc-musl = " file://busybox-1.33.1/musl.cfg "
+
+diff --git a/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc b/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
+index 2efbe4d..1b610f9 100755
+--- a/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
++++ b/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
+@@ -3,7 +3,7 @@
+ HOMEPAGE = "https://www.busybox.net"
+ BUGTRACKER = "https://bugs.busybox.net/"
+
+-DEPENDS += "kern-tools-native virtual/crypt libnvram"
++DEPENDS += "kern-tools-native virtual/crypt libnvram libdebug-info"
+
+ # bzip2 applet in busybox is based on lightly-modified bzip2-1.0.4 source
+ # the GPL is version 2 only
+diff --git a/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend b/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
+index 1ea730c..7a45c61 100755
+--- a/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
++++ b/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
+@@ -2,8 +2,7 @@
+ FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+ SRC_URI += " \
+- file://0001-write-log-to-zcat-tool.patch \
+- file://0002-fix-y2038-time_t-unsigned-long.patch \
++ file://0001-write-log-to-zcat-tool.patch \
+ "
+
+ do_install_append() {
+diff --git a/upstream/linux-5.10/drivers/mfd/zx234290-core.c b/upstream/linux-5.10/drivers/mfd/zx234290-core.c
+index d43085f..6da76d2 100755
+--- a/upstream/linux-5.10/drivers/mfd/zx234290-core.c
++++ b/upstream/linux-5.10/drivers/mfd/zx234290-core.c
+@@ -246,15 +246,16 @@
+ #endif
+ #if 1
+ extern int Zx234290_SetUserReg_PSM(unsigned char data);
++extern void zxic_reset_reason(int reason, const char *cpu, const char *app);
+
+ void zx29_restart(const char * cmd)
+ {
+ /*set reset value = 1*/
+- unsigned char status = ZX234290_USER_RST_TO_NORMAL;
++ unsigned char status = USER_RST_TO_NORMAL;
+
+ printk(KERN_INFO"restart:enter reboot :reset to normal\n");
++ zxic_reset_reason(2, "cap", current->comm);
+
+- status = ZX234290_USER_RST_TO_NORMAL;
+ Zx234290_SetUserReg_PSM(status);
+ }
+
+diff --git a/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c b/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
+index be7309c..9235ec4 100755
+--- a/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
++++ b/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
+@@ -530,7 +530,7 @@
+ }
+
+ //ÉèÖöÁÊý¾Ý´óС
+-int mmc_bread(u32 start_addr, u32 data_size, void *dst)
++int mmc_bread(u64 start_addr, u32 data_size, void *dst)
+ {
+ int ret;
+ u32 src = 0;
+@@ -548,7 +548,7 @@
+ if(block_addr == 0)
+ src = start_addr;
+ else
+- src = start_addr/MMC_BLOCK_SIZE;
++ src = (u32)(start_addr/MMC_BLOCK_SIZE);
+
+ if(blk_count){
+ ret= zx_mmc_read(src, (u8 *) dst, blk_count * MMC_BLOCK_SIZE);
+@@ -573,7 +573,7 @@
+ return data_size;
+ }
+
+-int mmc_bwrite(u32 start_addr, u32 data_size, void *src_buf)
++int mmc_bwrite(u64 start_addr, u32 data_size, void *src_buf)
+ {
+ int ret;
+ u32 start_blk = 0;
+@@ -594,7 +594,7 @@
+ if(block_addr == 0)
+ start_blk = start_addr;
+ else
+- start_blk = (start_addr/MMC_BLOCK_SIZE);
++ start_blk = (u32)(start_addr/MMC_BLOCK_SIZE);
+
+ if(blk_count){
+ ret= zx_mmc_write(start_blk, (u8 *)src_buf, blk_count * MMC_BLOCK_SIZE);
+diff --git a/upstream/linux-5.10/drivers/mtd/mtdcore.c b/upstream/linux-5.10/drivers/mtd/mtdcore.c
+index a52a2c8..c07e824 100755
+--- a/upstream/linux-5.10/drivers/mtd/mtdcore.c
++++ b/upstream/linux-5.10/drivers/mtd/mtdcore.c
+@@ -228,6 +228,17 @@
+ }
+ static DEVICE_ATTR(ecc_strength, S_IRUGO, mtd_ecc_strength_show, NULL);
+
++#define MTD_RECORD_NAME_MAX (16)
++struct zxic_mtd_record
++{
++ char name[MTD_RECORD_NAME_MAX];
++ unsigned int erase_times;
++ unsigned int write_times;
++};
++
++static struct zxic_mtd_record g_zxic_mtd_record; //save data
++static int record_mtd_trigger_flag; // 0 stop record, 1 start record
++
+ static ssize_t mtd_bitflip_threshold_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+@@ -1111,6 +1122,9 @@
+
+ adjinstr.addr += mst_ofs;
+
++ if (record_mtd_trigger_flag && (strcmp(mtd->name, g_zxic_mtd_record.name) == 0))
++ g_zxic_mtd_record.erase_times++;
++
+ ret = master->_erase(master, &adjinstr);
+
+ if (adjinstr.fail_addr != MTD_FAIL_ADDR_UNKNOWN) {
+@@ -1232,6 +1246,9 @@
+ };
+ int ret;
+
++ if (record_mtd_trigger_flag && (strcmp(mtd->name, g_zxic_mtd_record.name) == 0))
++ g_zxic_mtd_record.write_times++;
++
+ ret = mtd_write_oob(mtd, to, &ops);
+ *retlen = ops.retlen;
+
+@@ -2203,6 +2220,107 @@
+
+ static struct proc_dir_entry *proc_mtd;
+
++/* Started by AICoder, pid:5fc9ey6dc555c241432c0bd800e0358e8d683380 */
++static struct proc_dir_entry *proc_record_mtd_name;
++static struct proc_dir_entry *proc_record_mtd_trigger;
++static struct proc_dir_entry *proc_record_mtd_erase_times;
++
++static ssize_t proc_record_mtd_name_read(struct file *file, char __user *user_buffer, size_t count, loff_t *offset) {
++ if (g_zxic_mtd_record.name[0] != '\0')
++ return simple_read_from_buffer(user_buffer, count, offset, g_zxic_mtd_record.name, strlen(g_zxic_mtd_record.name));
++ else
++ return 0;
++}
++
++static ssize_t proc_record_mtd_name_write(struct file *file, const char __user *user_buffer, size_t count, loff_t *offset) {
++ if (count <= 1 || count >= MTD_RECORD_NAME_MAX) {
++ return -EINVAL;
++ }
++
++ if (copy_from_user(g_zxic_mtd_record.name, user_buffer, count)) {
++ return -EFAULT;
++ }
++
++ g_zxic_mtd_record.name[count-1] = '\0'; // last 1 byte 0x0a
++ g_zxic_mtd_record.erase_times = 0;
++ g_zxic_mtd_record.write_times = 0;
++
++ return count;
++}
++
++static ssize_t proc_record_mtd_trigger_read(struct file *file, char __user *user_buffer, size_t count, loff_t *offset) {
++ if (record_mtd_trigger_flag)
++ return simple_read_from_buffer(user_buffer, count, offset, "start\n", 6);
++ else
++ return simple_read_from_buffer(user_buffer, count, offset, "stop\n", 5);
++}
++
++static ssize_t proc_record_mtd_trigger_write(struct file *file, const char __user *user_buffer, size_t count, loff_t *offset) {
++ char buffer[10];
++
++ if (count < 4 || count > 6)
++ return -EINVAL;
++ if (g_zxic_mtd_record.name[0] == '\0')
++ return -EINVAL; // mtd name not set
++ if (copy_from_user(buffer, user_buffer, count))
++ return -EFAULT;
++
++ buffer[count-1] = '\0'; // last 1 byte 0x0a
++ //printk("record mtd trigger:%s\n", buffer);
++
++ if (memcmp(buffer, "start", 5) == 0) {
++ printk(KERN_WARNING "record mtd erase and write start\n");
++ g_zxic_mtd_record.erase_times = 0;
++ g_zxic_mtd_record.write_times = 0;
++ record_mtd_trigger_flag = 1;
++ } else {
++ if (memcmp(buffer, "stop", 4) == 0)
++ {
++ printk(KERN_WARNING "record mtd erase and write stop\n");
++ record_mtd_trigger_flag = 0;
++ }
++ else
++ {
++ return -EINVAL;
++ }
++ }
++
++ return count;
++}
++
++static int proc_record_mtd_erase_times_show(struct seq_file *m, void *v)
++{
++ seq_printf(m, "mtd:%s\n", g_zxic_mtd_record.name);
++ seq_printf(m, "erase_times:%u\n", g_zxic_mtd_record.erase_times);
++ seq_printf(m, "write_times:%u\n", g_zxic_mtd_record.write_times);
++ return 0;
++}
++
++static const struct proc_ops proc_record_mtd_name_fops = {
++ .proc_read = proc_record_mtd_name_read,
++ .proc_write = proc_record_mtd_name_write,
++};
++
++static const struct proc_ops proc_record_mtd_trigger_fops = {
++ .proc_read = proc_record_mtd_trigger_read,
++ .proc_write = proc_record_mtd_trigger_write,
++};
++
++static int zxic_record_proc_init(void)
++{
++ proc_record_mtd_name = proc_create("record_mtd_name", 0666, NULL, &proc_record_mtd_name_fops);
++ if (!proc_record_mtd_name)
++ return -ENOMEM;
++ proc_record_mtd_trigger = proc_create("record_mtd_trigger", 0666, NULL, &proc_record_mtd_trigger_fops);
++ if (!proc_record_mtd_trigger)
++ return -ENOMEM;
++ proc_record_mtd_erase_times = proc_create_single("record_mtd_erase_times", 0, NULL, proc_record_mtd_erase_times_show);
++ if (!proc_record_mtd_erase_times)
++ return -ENOMEM;
++ return 0;
++}
++/* Ended by AICoder, pid:5fc9ey6dc555c241432c0bd800e0358e8d683380 */
++
+ static int __init init_mtd(void)
+ {
+ int ret;
+@@ -2219,6 +2337,9 @@
+
+ proc_mtd = proc_create_single("mtd", 0, NULL, mtd_proc_show);
+
++ if (zxic_record_proc_init() < 0)
++ printk(KERN_ERR "zxic_record_proc_init error\n");
++
+ ret = init_mtdchar();
+ if (ret)
+ goto out_procfs;
+diff --git a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
+index 668d9d9..32cb5a5 100755
+--- a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
++++ b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
+@@ -25,8 +25,11 @@
+ #include <linux/gpio.h>
+ #include <linux/of_gpio.h>
+ #include <linux/device.h>
++#include <uapi/linux/sched/types.h>
+ #include "zx29_gmac.h"
+
++#define GMAC_RX_WORKER_TH 1
++
+ #define gmac_printk(_format, _args...) do{printk(KERN_INFO"gmac," _format "\n",##_args);}while(0)
+
+ static u8 zx29_gmac_addr[MAC_ADDR_LENTH] = {0xec,0x1d,0x7f,0xb0,0x2f,0x32};
+@@ -86,10 +89,11 @@
+
+ d = (struct bd_tx *)priv->dma_tx_vir;
+
++
+ if (n == priv->tx_bd_offset)
+ return 0;
+
+- if (d[n].TDES0 & DMA_OWNER)
++ if ( (!d) || (d[n].TDES0 & DMA_OWNER))
+ return 0;
+
+ if (d[n].skb == NULL)
+@@ -123,7 +127,7 @@
+ int n = prv->rx_bd_offset;
+ struct bd_rx *d = (struct bd_rx*)prv->dma_rx_vir;
+
+- if(d[n].RDES0 & DMA_OWNER)
++ if ((!d) || (d[n].RDES0 & DMA_OWNER))
+ {
+ return 0;
+ }
+@@ -359,6 +363,56 @@
+ return (exhausted > 10);
+ }
+
++#ifdef GMAC_RX_WORKER_TH
++static struct task_struct *s_gmac_rx_worker = 0;
++static int ko_remove_flag = 0;
++struct semaphore s_gmac_rx_sem = {0};
++static int gmac_rx_worker(void *dev)
++{
++ struct net_device *ndev = (struct net_device *)dev;
++ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)netdev_priv(ndev);
++ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
++ unsigned int events = prv->int_event;
++
++ do {
++ down(&s_gmac_rx_sem);
++ if (ko_remove_flag)
++ return 0;
++ events = prv->int_event;
++ do {
++ if (events & INT_ST_TX)
++ zx29_gmac_tx(ndev);
++
++ if (events & INT_ST_RX)
++ zx29_gmac_rx(ndev);
++
++ events = MAC(0x1014);
++ MAC(0x1014) = events;
++ } while (events & (INT_ST_TX | INT_ST_RX));
++
++ #ifndef GMAC_NO_INT
++ mac_int_enable();
++ #endif
++ } while(1);
++
++ return 0;
++}
++
++static int zx29_gmac_worker(struct net_device* pnetdev)
++{
++ struct sched_param param = {.sched_priority = 40};
++
++ sema_init(&s_gmac_rx_sem, 0);
++
++ s_gmac_rx_worker = kthread_create(gmac_rx_worker, (void *)pnetdev, "gmac_rx_worker");
++
++ //sched_setscheduler(s_gmac_rx_worker, SCHED_RR, ¶m);
++ wake_up_process(s_gmac_rx_worker);
++
++ return 0;
++}
++
++#endif
+
+ #ifndef GMAC_NO_INT
+ static irqreturn_t zx29_gmac_interrupt(int irq, void *dev_id)
+@@ -371,8 +425,11 @@
+ MAC(0x1014) = priv->int_event;
+
+ mac_int_disable();
++#ifndef GMAC_RX_WORKER_TH
+ tasklet_schedule(&priv->tasklet);
+-
++#else
++ up(&s_gmac_rx_sem);
++#endif
+ return IRQ_HANDLED;
+ }
+
+@@ -424,7 +481,11 @@
+ ktime_t gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+
+ hrtimer_forward_now(timer, gmac_schdule_time);
++#ifndef GMAC_RX_WORKER_TH
+ tasklet_schedule(g_gmac_tasklet);
++#else
++ up(&s_gmac_rx_sem);
++#endif
+ return HRTIMER_RESTART;
+ }
+ #endif
+@@ -759,7 +820,7 @@
+ return ret;
+ }
+
+- netif_carrier_on(ndev);
++// netif_carrier_on(ndev);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ phy_start(priv->phydev);
+@@ -1725,12 +1786,46 @@
+
+ /*zw.wang add for switching the primary/secondary mode of gmac on 20240118 end */
+
++/*zw.wang add a new interface to obtain the PHY link status on 20250226 begin*/
++ssize_t phy_pma_link_show(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ int val = 0;
++ struct platform_device *pdev = to_platform_device(dev);
++ if (!pdev) {
++ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__,
++ pdev);
++ return -1;
++ }
++ struct net_device *ndev = platform_get_drvdata(pdev);
++ if (!ndev) {
++ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__,
++ ndev);
++ return -1;
++ }
++ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
++ if (!priv) {
++ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__,
++ priv);
++ return -1;
++ }
++ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d,0x1);
++ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e,0x1);
++ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d,0x4000 | 0x1);
++ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr,0x0e);
++ sprintf(buf, "link : %s\n", (val & BIT(2)) ? "yes":"no");
++ return strlen(buf);
++}
++
++/*zw.wang add a new interface to obtain the PHY link status on 20250226 end*/
++
+ static DEVICE_ATTR(gmac_test, 0664, show_fun, store_fun);
+ static DEVICE_ATTR(mdio_test, 0664, mdio_show, mdio_store);
+ static DEVICE_ATTR(free_mdio, 0664, free_mdio_show, free_mdio_store);
+ static DEVICE_ATTR(debug_on, 0664, debug_on_show, debug_on_store);
+ static DEVICE_ATTR(gmac_power, 0664, gmac_power_show, gmac_power_store);//jb.qi add for gamc power down on 20231116
+ static DEVICE_ATTR(gmac_master_or_slave, 0664, gmac_master_or_slave_show, gmac_master_or_slave_store);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
++static DEVICE_ATTR_RO(phy_pma_link); //zw.wang add a new interface to obtain the PHY link status on 20250226
+
+ static int zx29_gmac_probe(struct platform_device *pdev)
+ {
+@@ -1759,6 +1854,7 @@
+ device_create_file(&pdev->dev, &dev_attr_debug_on);
+ device_create_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_create_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
++ device_create_file(&pdev->dev, &dev_attr_phy_pma_link); //zw.wang add a new interface to obtain the PHY link status on 20250226
+
+ prv = netdev_priv(ndev);
+ memset(prv, 0, sizeof(*prv));
+@@ -1851,6 +1947,10 @@
+ goto errdev;
+ }
+
++#ifdef GMAC_RX_WORKER_TH
++ zx29_gmac_worker(ndev);//gmac_rx_worker
++#endif
++
+ of_property_read_u32(np, "port-nums", &prv->nports);
+ of_property_read_u32(np, "rmii-ports", &prv->rmii_port);
+ prv->base_addr = ndev->base_addr;
+@@ -1987,9 +2087,10 @@
+
+ // gpio_direction_output(priv->gpio_power[0], 1);
+ // msleep(500);
+- unregister_netdev(ndev);
++// unregister_netdev(ndev);
+
+ phy_disconnect(priv->phydev);
++ unregister_netdev(ndev);
+
+ kobj_gmac_del(NULL);
+
+@@ -1998,11 +2099,17 @@
+ #ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+ #endif
++
++#ifdef GMAC_RX_WORKER_TH
++ ko_remove_flag = 1;
++ up(&s_gmac_rx_sem);
++#endif
++
+ tasklet_disable(&priv->tasklet);
+ tasklet_kill(&priv->tasklet);
+
+- if (priv->dma_rx_vir)
+- dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, priv->dma_rx_vir, priv->dma_rx_phy);
++ if (priv->dma_rx_vir_init)
++ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, priv->dma_rx_vir_init, priv->dma_rx_phy_init);
+
+ pm_relax(&pdev->dev);
+ free_netdev(ndev);
+@@ -2020,6 +2127,7 @@
+ device_remove_file(&pdev->dev, &dev_attr_debug_on);
+ device_remove_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_remove_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
++ device_remove_file(&pdev->dev, &dev_attr_phy_pma_link); //zw.wang add a new interface to obtain the PHY link status on 20250226
+ }
+ return 0;
+ }
+diff --git a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
+index 750580b..6df9cfd 100755
+--- a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
++++ b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
+@@ -137,7 +137,7 @@
+
+ void kobj_gmac_del(struct kobject *kobject)
+ {
+- kset_unregister(kset_gmac);
++// kset_unregister(kset_gmac);
+
+ kobject_uevent(typekobj, KOBJ_REMOVE);
+ kobject_del(typekobj);
+@@ -150,6 +150,7 @@
+
+ kfree(gmackobj);
+
++ kset_unregister(kset_gmac);
+ printk("[gmac kobj_test: delete!]\n");
+ }
+ EXPORT_SYMBOL(kobj_gmac_del);
+@@ -278,8 +279,8 @@
+ }
+ kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(gmackobj, &gmacktype);
+- kobject_add(gmackobj,&kset_gmac->kobj,"%s","gmacconfig");
+ gmackobj->kset = kset_gmac;
++ kobject_add(gmackobj,&kset_gmac->kobj,"%s","gmacconfig");
+
+ typekobj = kzalloc(sizeof(*typekobj),GFP_KERNEL);
+ if(!typekobj){
+@@ -288,8 +289,8 @@
+ }
+ // kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(typekobj, &typektype);
+- kobject_add(typekobj,&kset_gmac->kobj,"%s",name);
+ typekobj->kset = kset_gmac;
++ kobject_add(typekobj,&kset_gmac->kobj,"%s",name);
+
+ strcpy(type, name);
+
+diff --git a/upstream/linux-5.10/drivers/net/phy/phy_device.c b/upstream/linux-5.10/drivers/net/phy/phy_device.c
+index d9b53ba..f6a5a56 100755
+--- a/upstream/linux-5.10/drivers/net/phy/phy_device.c
++++ b/upstream/linux-5.10/drivers/net/phy/phy_device.c
+@@ -1316,6 +1316,10 @@
+ }
+ EXPORT_SYMBOL(phy_sfp_probe);
+
++static bool phy_drv_supports_irq(struct phy_driver *phydrv)
++{
++ return phydrv->config_intr && phydrv->ack_interrupt;
++}
+ /**
+ * phy_attach_direct - attach a network device to a given PHY device pointer
+ * @dev: network device to attach
+@@ -1421,6 +1425,8 @@
+
+ phydev->state = PHY_READY;
+
++ if (!phy_drv_supports_irq(phydev->drv) && phy_interrupt_is_valid(phydev))
++ phydev->irq = PHY_POLL;
+ /* Port is set to PORT_TP by default and the actual PHY driver will set
+ * it to different value depending on the PHY configuration. If we have
+ * the generic PHY driver we can't figure it out, thus set the old
+@@ -2819,7 +2825,7 @@
+ if (delay < 0)
+ return delay;
+
+- if (delay && size == 0)
++ if (size == 0)
+ return delay;
+
+ if (delay < delay_values[0] || delay > delay_values[size - 1]) {
+@@ -2852,10 +2858,6 @@
+ }
+ EXPORT_SYMBOL(phy_get_internal_delay);
+
+-static bool phy_drv_supports_irq(struct phy_driver *phydrv)
+-{
+- return phydrv->config_intr && phydrv->ack_interrupt;
+-}
+
+ /**
+ * phy_probe - probe and init a PHY device
+diff --git a/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c b/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
+index c7da7a4..ffade7e 100755
+--- a/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
++++ b/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
+@@ -9,6 +9,8 @@
+ #include "ram_config.h"
+ #include <net/netfilter/nf_conntrack.h>
+ #include <net/SI/fast_common.h>
++#include <pub_debug_info.h>
++
+ /*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+@@ -50,6 +52,18 @@
+ unsigned short flag;
+ struct T_zvnet_pkt_stats pkt[2];
+ };
++struct zvnet_arphdr {
++ unsigned short ar_hrd; /* format of hardware address */
++ unsigned short ar_pro; /* format of protocol address */
++ unsigned char ar_hln; /* length of hardware address */
++ unsigned char ar_pln; /* length of protocol address */
++ unsigned short ar_op; /* ARP opcode (command) */
++ unsigned char ar_sha[ETH_ALEN]; /* sender hardware address */
++ unsigned char ar_sip[4]; /* sender IP address */
++ unsigned char ar_tha[ETH_ALEN]; /* target hardware address */
++ unsigned char ar_tip[4]; /* target IP address */
++};
++
+ /*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+@@ -65,6 +79,7 @@
+ struct semaphore g_zvnet_free_sem;
+ struct semaphore g_zvnet_xmit_sem;
+ struct sk_buff_head g_zvnet_skb_xmit_queue;
++atomic_t g_zvnet_pm_flag;
+
+ unsigned int g_wrap_packet_size = 1000;
+ module_param(g_wrap_packet_size, int, 0644);
+@@ -152,7 +167,7 @@
+ unsigned char *p = data;
+ for(i = 0; i < len && i < limit_len; i+=16)
+ {
+- printk("0x%04x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",i,
++ printk("0x%04x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",i,
+ p[0],p[1],p[2],p[3],p[4],p[5],p[6],p[7],
+ p[8],p[9],p[10],p[11],p[12],p[13],p[14],p[15]);
+ p += 16;
+@@ -160,6 +175,11 @@
+ }
+ /* Ended by AICoder, pid:z5702yf8bad07ad1448a083e806dc31250b2418f */
+
++void zvnet_set_pm_flag(unsigned int flag){
++ if(flag & 0x100000)
++ atomic_set(&g_zvnet_pm_flag, 1);
++}
++
+ int zvnet_get_index_by_netdev(struct net_device *net)
+ {
+ int i;
+@@ -304,11 +324,127 @@
+ /* make sure we initialize shinfo sequentially */
+ skb_reset_network_header(skb);
+ skb_set_kcov_handle(skb, kcov_common_handle());
+- if(unlikely(g_trace_limit > 0)){
+- printk("-%s-dump_packet-start-%d\n", skb->dev->name, skb->len);
++ if(unlikely(g_trace_limit & 1)){
++ printk("-%s-dump_fromap-start-%d\n", skb->dev->name, skb->len);
+ zvnet_dump_packet(skb->data, skb->len, g_trace_limit);
+- printk("-%s-dump_packet-end-\n", skb->dev->name);
++ printk("-%s-dump_fromap-end-\n", skb->dev->name);
+ }
++/* Started by AICoder, pid:j2d34uccf7y1f37146a108290182771184940711 */
++ if (atomic_read(&g_zvnet_pm_flag)) {
++ unsigned short l2_hdr_len = 0;
++ unsigned short h_proto = htons(*(unsigned short *)(skb->data + ETH_ALEN + ETH_ALEN));
++ again:
++ if (l2_hdr_len + ETH_HLEN < skb->len) {
++ switch (h_proto) {
++ case ETH_P_IP: {
++ struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN + l2_hdr_len);
++ if (iph->protocol == IPPROTO_TCP) {
++ struct tcphdr *tcph = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl * 4);
++ char *flag;
++ if (tcph->ack) {
++ if (tcph->fin)
++ flag = "FA";
++ else if (tcph->syn)
++ flag = "SA";
++ else if (tcph->psh)
++ flag = "PA";
++ else
++ flag = "A";
++ } else {
++ if (tcph->fin)
++ flag = "F";
++ else if (tcph->syn)
++ flag = "S";
++ else if (tcph->rst)
++ flag = "R";
++ else
++ flag = "";
++ }
++ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u%s %u:%u/%u\n",
++ pbuf_temp->dev, &iph->saddr, &iph->daddr,
++ iph->protocol, flag, ntohs(tcph->source), ntohs(tcph->dest), skb->len);
++ } else if (iph->protocol == IPPROTO_UDP) {
++ struct udphdr *udph = (struct udphdr *)(((unsigned char *)iph) + iph->ihl * 4);
++ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u %u:%u/%u\n",
++ pbuf_temp->dev, &iph->saddr, &iph->daddr,
++ iph->protocol, ntohs(udph->source), ntohs(udph->dest), skb->len);
++ } else if (iph->protocol == IPPROTO_ICMP) {
++ struct icmphdr *icmph = (struct icmphdr *)(((unsigned char *)iph) + iph->ihl * 4);
++ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u %u:%u/%u\n",
++ pbuf_temp->dev, &iph->saddr, &iph->daddr,
++ iph->protocol, icmph->type, icmph->code, skb->len);
++ } else {
++ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u/%u\n",
++ pbuf_temp->dev, &iph->saddr, &iph->daddr,
++ iph->protocol, skb->len);
++ }
++ break;
++ }
++ case ETH_P_IPV6: {
++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN + l2_hdr_len);
++ if (iph->nexthdr == NEXTHDR_TCP) {
++ struct tcphdr *tcph = (struct tcphdr *)(((unsigned char *)iph) + sizeof(struct ipv6hdr));
++ char *flag;
++ if (tcph->ack) {
++ if (tcph->fin)
++ flag = "FA";
++ else if (tcph->syn)
++ flag = "SA";
++ else if (tcph->psh)
++ flag = "PA";
++ else
++ flag = "A";
++ } else {
++ if (tcph->fin)
++ flag = "F";
++ else if (tcph->syn)
++ flag = "S";
++ else if (tcph->rst)
++ flag = "R";
++ else
++ flag = "";
++ }
++ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u%s %u:%u/%u\n",
++ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
++ iph->nexthdr, flag, ntohs(tcph->source), ntohs(tcph->dest), skb->len);
++ } else if (iph->nexthdr == NEXTHDR_UDP) {
++ struct udphdr *udph = (struct udphdr *)(((unsigned char *)iph) + sizeof(struct ipv6hdr));
++ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u %u:%u/%u\n",
++ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
++ iph->nexthdr, ntohs(udph->source), ntohs(udph->dest), skb->len);
++ } else if (iph->nexthdr == NEXTHDR_ICMP) {
++ struct icmp6hdr *icmph = (struct icmp6hdr *)(((unsigned char *)iph) + sizeof(struct ipv6hdr));
++ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u %u:%u/%u\n",
++ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
++ iph->nexthdr, icmph->icmp6_type, icmph->icmp6_code,skb->len);
++ } else {
++ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u/%u\n",
++ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
++ iph->nexthdr, skb->len);
++ }
++ break;
++ }
++ case ETH_P_ARP: {
++ struct zvnet_arphdr *arph = (struct zvnet_arphdr *)(skb->data + ETH_HLEN + l2_hdr_len);
++ sc_debug_info_record("cap_net", "%u:%04x-%pI4-%pI4-%u/%u\n",
++ pbuf_temp->dev, h_proto, arph->ar_sip, arph->ar_tip, htons(arph->ar_op), skb->len);
++ break;
++ }
++ case ETH_P_8021Q: {
++ struct vlan_hdr *vlanh = (struct vlan_hdr *)(skb->data + ETH_HLEN + l2_hdr_len);
++ sc_debug_info_record("cap_net", "%u:%04x-%u\n",
++ pbuf_temp->dev, h_proto, htons(vlanh->h_vlan_TCI) & VLAN_VID_MASK);
++ l2_hdr_len += VLAN_HLEN;
++ h_proto = htons(vlanh->h_vlan_encapsulated_proto);
++ goto again;
++ }
++ default:
++ sc_debug_info_record("cap_net", "%u:%04x/%u\n", pbuf_temp->dev, h_proto, skb->len);
++ }
++ }
++ atomic_set(&g_zvnet_pm_flag, 0);
++ }
++/* Ended by AICoder, pid:j2d34uccf7y1f37146a108290182771184940711 */
+ return skb;
+ }
+
+@@ -400,6 +536,11 @@
+ buff[i].len = skb->len;
+ buff[i].end_off = skb->end - skb->head;
+ buff[i].dev = zvnet_get_index_by_netdev(skb->dev);
++ if(unlikely(g_trace_limit & 2)){
++ printk("-%s-dump_toap-start-%d\n", skb->dev->name, skb->len);
++ zvnet_dump_packet(skb->data, skb->len, g_trace_limit);
++ printk("-%s-dump_toap-end-\n", skb->dev->name);
++ }
+ if(skb->capHead){
+ buff[i].buff = skb->capHead;
+ #ifdef CONFIG_FASTNAT_MODULE
+@@ -500,11 +641,11 @@
+ data->dev = net;
+ data->isToap = 1;
+ v7_dma_map_area(data->head, data->end - data->head + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
++ net->stats.tx_packets++;
++ net->stats.tx_bytes += data->len;
+ skb_queue_tail(&g_zvnet_skb_xmit_queue, data);
+ if(data->len < g_wrap_packet_size || g_zvnet_skb_xmit_queue.qlen > g_wrap_num)
+ up(&g_zvnet_xmit_sem);
+- net->stats.tx_packets++;
+- net->stats.tx_bytes += skb->len;
+ #else
+ struct zvnet *dev = netdev_priv(net);
+ struct zvnet_device *zvnetdev = (struct zvnet_device *)dev->dev_priv;
+@@ -1240,6 +1381,7 @@
+ struct net_device *net = NULL;
+ struct zvnet_device *zvnetdev = NULL;
+
++ atomic_set(&g_zvnet_pm_flag, 0);
+ #ifdef USE_ZVNET_PACKET
+ skb_queue_head_init(&g_zvnet_skb_xmit_queue);
+ spin_lock_init(&g_zvnet_free_lock);
+diff --git a/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c b/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
+index 3c5ba58..0e1ca16 100755
+--- a/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
++++ b/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
+@@ -324,7 +324,7 @@
+ [40] = "at channel 40",
+ [41] = "voice buffer",
+ };
+-
++extern void zvnet_set_pm_flag(unsigned int flag);
+ void show_icp_state(T_ZDrvRpMsg_ActorID actorID)
+ {
+ unsigned int hw, lw;
+@@ -334,6 +334,7 @@
+ return;
+
+ icp_get_int_info(actorID, &hw, &lw);
++ zvnet_set_pm_flag(lw);
+ pr_info("[SLP] icpwake: 0x%x 0x%x\n", hw, lw);
+ sc_debug_info_record(MODULE_ID_CAP_PM, " icpwake: 0x%x 0x%x\n", hw, lw);
+
+diff --git a/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c b/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
+index b29437a..7029976 100755
+--- a/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
++++ b/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
+@@ -591,6 +591,48 @@
+ );
+ }
+ DEVICE_ATTR(statics, S_IRUGO, statics_show, NULL);
++
++static unsigned int uart_io_seletc = 0;
++
++
++static ssize_t uart_io_select_show(struct device *_dev,
++struct device_attribute *attr, char *buf)
++{
++struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
++//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
++
++return sprintf(buf, "%d\n",uart_io_seletc );
++
++}
++
++static ssize_t uart_io_select_store(struct device *_dev,
++struct device_attribute *attr,
++const char *buf, size_t count)
++{
++ uint32_t flag = 0;
++struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
++flag = simple_strtoul(buf, NULL, 16);
++
++if(flag == 1){
++ printk("uart io is 1\n");
++pinctrl_pm_select_default_state(_dev);
++}else if(flag == 0){
++pinctrl_pm_select_sleep_state(_dev);
++}
++else{
++printk("uart io select flag invaild\n");
++}
++
++uart_io_seletc = flag;
++
++
++
++return count;
++}
++
++DEVICE_ATTR(uart_io_select, S_IRUGO | S_IWUSR, uart_io_select_show,
++ uart_io_select_store);
++
+ #define VEHICLE_USE_ONE_UART_LOG 1
+ #if VEHICLE_USE_ONE_UART_LOG
+ #define ICP_CORE_ID_PS CORE_PS0
+@@ -4412,6 +4454,9 @@
+ error = device_create_file(&pdev->dev, &dev_attr_app_ctrl);
+
+ }
++ if(pdev->id == 2){
++ error = device_create_file(&pdev->dev, &dev_attr_uart_io_select);
++ }
+ error = device_create_file(&pdev->dev, &dev_attr_statics);
+ device_init_wakeup(&pdev->dev, true);
+ /*
+diff --git a/upstream/linux-5.10/include/linux/mfd/zx234290.h b/upstream/linux-5.10/include/linux/mfd/zx234290.h
+index ea89815..40e71bf 100755
+--- a/upstream/linux-5.10/include/linux/mfd/zx234290.h
++++ b/upstream/linux-5.10/include/linux/mfd/zx234290.h
+@@ -1009,24 +1009,6 @@
+ SINK_CURRENT_MAX
+ }T_ZDrvZx234297_SINK_CURRENT;
+
+-typedef enum _T_ZDrvZx234290_ResetType
+-{
+-#if 0
+- ZX234290_USER_RST_UNDEFINE = 0,
+- ZX234290_USER_RST_TO_NORMAL = 1,
+- ZX234290_USER_RST_TO_CHARGER = 2,
+- ZX234290_USER_RST_TO_ALARM = 3,
+-#else
+- ZX234290_USER_RST_UNDEFINE = 3,
+- ZX234290_USER_RST_TO_NORMAL = 0,
+- ZX234290_USER_RST_TO_CHARGER = 1,
+- ZX234290_USER_RST_TO_ALARM = 2,
+-#endif
+- ZX234290_USER_RST_TO_EXCEPT = 4,
+-
+- ZX234290_USER_RST_MAX
+-}T_ZDrvZx234290_ResetType;
+-
+
+ int zx234290_get_chip_version(void);
+ int zx234290_irq_init(struct zx234290 *zx234290);
+diff --git a/upstream/linux-5.10/include/linux/mmc/mmc_func.h b/upstream/linux-5.10/include/linux/mmc/mmc_func.h
+index b2636ab..911c010 100755
+--- a/upstream/linux-5.10/include/linux/mmc/mmc_func.h
++++ b/upstream/linux-5.10/include/linux/mmc/mmc_func.h
+@@ -23,7 +23,7 @@
+ * data_size: the size of data you want to write .defined by byte
+ * src_buf: data buffer where log or file stored;
+ */
+-int mmc_bwrite(u32 start_addr, u32 data_size, void *src_buf);
++int mmc_bwrite(u64 start_addr, u32 data_size, void *src_buf);
+
+ /*
+ * start_addr: the address is the emmc address you want to write,and it size is
+@@ -32,6 +32,6 @@
+ * src_buf: data buffer where log or file will store;
+ */
+
+-int mmc_bread(u32 start_addr, u32 data_size, void *dst);
++int mmc_bread(u64 start_addr, u32 data_size, void *dst);
+
+ #endif /* LINUX_MMC_MMC_FUNC_H */
+diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c b/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
+index bcb6a53..1492b49 100755
+--- a/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
++++ b/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
+@@ -45,6 +45,7 @@
+ extern void ramdump_data_transfer_to_device(void);
+ extern void ramdump_oss_data_trans_init(void);
+ extern unsigned char *ramdump_export_flag_base;
++extern void zxic_reset_reason(int reason, const char *cpu, const char *app);
+
+ /*******************************************************************************
+ * ¾Ö²¿¾²Ì¬±äÁ¿¶¨Òå *
+@@ -71,7 +72,7 @@
+ unsigned char *ramdump_cap_error_log = NULL;
+ unsigned int *cap_ddr_len_base = NULL;
+ unsigned int sysctl_ramdump_emmc_size = 0x0;
+-unsigned int sysctl_ramdump_emmc_start_addr = 0xFFFF;
++u64 sysctl_ramdump_emmc_start_addr = 0xFFFF;
+
+ static struct ctl_table cfg_ramdump_array[] = {
+ #ifdef CONFIG_RAMDUMP_USER
+@@ -128,7 +129,7 @@
+ {
+ ramdump_msg_t *icp_msg = (ramdump_msg_t *)buf;
+
+- ramdump_server_exp_core = RAMDUMP_SUCCESS;
++ ramdump_server_exp_core = RAMDUMP_TRUE;
+
+ switch(icp_msg->msg_id)
+ {
+@@ -413,6 +414,9 @@
+ void ramdump_entry (void)
+ {
+ unsigned long flags;
++
++ if (ramdump_server_exp_core == RAMDUMP_FALSE)
++ zxic_reset_reason(1, "cap", current->comm); /* not ap ramdump and cap ramdump */
+ if (sysctl_ramdump_on_panic == false)
+ return;
+
+diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c b/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
+index f3e91e9..0b0f0dc 100755
+--- a/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
++++ b/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
+@@ -51,6 +51,8 @@
+ extern unsigned int ramdump_compress_flag;
+ extern unsigned char *ramdump_log_buf;
+ extern unsigned int ramdump_export_mode;
++extern unsigned int ramdump_emmc_size;
++extern unsigned int ramdump_spinand_size;
+
+ /*******************************************************************************
+ * Macro definitions *
+@@ -288,6 +290,8 @@
+ *******************************************************************************/
+ void ramdump_device_close(void)
+ {
++ g_ramdump_dev_fp->file_num = ramdump_device_file_cnt;
++
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+ #ifdef CONFIG_RAMDUMP_EMMC
+@@ -333,11 +337,16 @@
+ int ramdump_device_write_file(ramdump_trans_server_file_info_req *server_to_cap)
+ {
+ int ret = -1;
++ unsigned int file_size = 0;
++
++ /* Started by AICoder, pid:wcfb91c2aa35add146d90b5530cd112845133621 */
++ file_size = server_to_cap->file_size;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+ #ifdef CONFIG_RAMDUMP_EMMC
+- if (ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
++ if ((ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
++ || ((ramdump_emmc_offset + file_size) > ramdump_emmc_size))
+ return -1;
+
+ ret = ramdump_fill_header(server_to_cap->file_name,
+@@ -349,9 +358,11 @@
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+ #ifdef CONFIG_MTD_SPI_NAND
+- if (ramdump_spinand_offset >= RAMDUMP_SPINAND_LEN)
++ if ((ramdump_spinand_offset >= RAMDUMP_SPINAND_LEN)
++ || ((ramdump_spinand_offset + file_size) > ramdump_spinand_size))
+ return -1;
+-
++ /* Ended by AICoder, pid:wcfb91c2aa35add146d90b5530cd112845133621 */
++
+ ret = ramdump_fill_header(server_to_cap->file_name,
+ server_to_cap->file_size,
+ &ramdump_spinand_fp,
+@@ -557,9 +568,9 @@
+ int ramdump_device_write_data(ramdump_shmem_t *msg, unsigned int size, ssize_t *dstlen)
+ {
+ int ret = 0;
+-
++
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+- {
++ {
+ #ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_write_data(msg, &ramdump_device_fp, size);
+ if(ret < 0)
+@@ -637,8 +648,6 @@
+ ramdump_trans_server_interactive_req *server_to_cap_msg = (ramdump_trans_server_interactive_req *)req_buf;
+ /* data from server to cap */
+ ramdump_file_num = server_to_cap_msg->file_num;
+- ramdump_device_fp.file_num += ramdump_file_num;
+- ramdump_spinand_fp.file_num += ramdump_file_num;
+
+ /* data from cap to server */
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_INFO_READ_REQ;
+@@ -658,8 +667,12 @@
+ /*device memory file create*/
+ if(ramdump_device_write_file(server_to_cap_msg) == -1){
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
+- ramdump_device_write_file_head();//±£Ö¤³ö´íÇ°¼¸¸öÎļþ¾ùд¶Ô¡£
+- ramdump_printf("ramdump write emmc file error!\n");
++ /* Started by AICoder, pid:ddd3ag3c37x6798145ec08ac1067150b58735197 */
++ ramdump_oss_data_trans_write(
++ (unsigned char*)(&cap_to_server_msg),
++ sizeof(cap_to_server_msg));
++ break;
++ /* Ended by AICoder, pid:ddd3ag3c37x6798145ec08ac1067150b58735197 */
+ }
+ file_size = server_to_cap_msg->file_size;
+ file_offset = 0;
+@@ -675,7 +688,8 @@
+ file_trans_size = cap_to_server_msg.length;
+ file_left_size = file_left_size - cap_to_server_msg.length;
+ file_offset = file_offset + cap_to_server_msg.length;
+- printk("device memory trans file:%s !!!\n", server_to_cap_msg->file_name);
++
++ printk("device memory trans file:%-30s size %9d, offset %9d!!!\n", server_to_cap_msg->file_name, file_size, ramdump_emmc_offset);
+ /* interactive data trans */
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+@@ -690,14 +704,24 @@
+ /* data from server to cap */
+ ramdump_shmem_t *server_to_cap_msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+ server_to_cap_msg->core_flag = 0;
++
+ /*data from cap to emmc*/
+-
+ write_len = ramdump_device_write_data(server_to_cap_msg, file_left_size, &file_dstlen);
+- if(write_len < 0)
++ if(write_len < 0 )
+ {
+- ramdump_printf("ramdump write emmc data error!\n");
++ /* Started by AICoder, pid:u5befs8483y615f142ce0bda306d660bed685275 */
++ if(write_len == -RAMDUMP_NO_FREE_SPACE)
++ {
++ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
++ ramdump_oss_data_trans_write(
++ (unsigned char*)(&cap_to_server_msg),
++ sizeof(cap_to_server_msg));
++ break;
++ }
++ else
++ ramdump_printf("ramdump write emmc data error!\n");
++ /* Ended by AICoder, pid:u5befs8483y615f142ce0bda306d660bed685275 */
+ }
+-
+ /*ÅжÏÊ£Óà´óС*/
+ if (file_left_size == 0)
+ {
+diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
+index 0c28f27..5054440 100755
+--- a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
++++ b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
+@@ -128,16 +128,28 @@
+ int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size)
+ {
+ int ret = 0;
+- unsigned int buffer = RAMDUMP_EMMC_ADDR + ramdump_emmc_offset;
++ u64 buffer = RAMDUMP_EMMC_ADDR + ramdump_emmc_offset;
+
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+- if(msg->size >= (ramdump_emmc_size - fp->file_fp[ramdump_device_file_cnt].offset))
+- return -1;
++ /* Started by AICoder, pid:fe298k6b27edc1c14f9e0be2e0451e1abfc5830e */
++ if((ramdump_emmc_size < ramdump_emmc_offset)
++ || (msg->size >= (ramdump_emmc_size - fp->file_fp[ramdump_device_file_cnt].offset)))
++ {
++ printk("[ramdump] No space left in emmc, Emmc_size is %ld,ramdump_emmc_offset is %d!\n", ramdump_emmc_size, ramdump_emmc_offset);
++ return -RAMDUMP_NO_FREE_SPACE;
++ }
+ ret = mmc_bwrite(buffer, msg->size, msg->buf);
++ if(ret < 0)
++ {
++ printk("[ramdump] ramdump_emmc_write_data Error.\n");
++ ramdump_wait_delay(0);
++ continue;
++ }
++ /* Ended by AICoder, pid:fe298k6b27edc1c14f9e0be2e0451e1abfc5830e */
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(msg->size, RAMDUMP_EMMC_ALIGN_SIZE);
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
+index 1028ab2..6c9817e 100755
+--- a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
++++ b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
+@@ -24,13 +24,14 @@
+ /*******************************************************************************
+ * Íⲿ±äÁ¿ÉùÃ÷ *
+ *******************************************************************************/
+-extern unsigned int sysctl_ramdump_emmc_start_addr;
++extern u64 sysctl_ramdump_emmc_start_addr;
+ extern unsigned int sysctl_ramdump_emmc_size;
+ extern volatile unsigned int ramdump_emmc_offset;
+
+ /*******************************************************************************
+ * ºê¶¨Òå *
+ *******************************************************************************/
++#define RAMDUMP_NO_FREE_SPACE (2)
+ #define RAMDUMP_EMMC_ADDR (sysctl_ramdump_emmc_start_addr * 512)
+ #define RAMDUMP_TRANS_EMMC_LEN (sysctl_ramdump_emmc_size * 512)
+
+diff --git a/upstream/linux-5.10/kernel/tracker.c b/upstream/linux-5.10/kernel/tracker.c
+index 6f7e1ab..792818b 100755
+--- a/upstream/linux-5.10/kernel/tracker.c
++++ b/upstream/linux-5.10/kernel/tracker.c
+@@ -63,6 +63,7 @@
+ #define OS_IRAM_SOFTIRQ_END (OS_IRAM_SOFTIRQ_START + sizeof(t_os_iram_statistic))
+ #define OS_IRAM_TIMER_START (OS_IRAM_SOFTIRQ_END + sizeof(t_os_iram_statistic))
+ #define OS_IRAM_TIMER_END (OS_IRAM_TIMER_START + sizeof(t_os_iram_statistic))
++#define OS_IRAM_RESET_REASON_START (OS_STATISTIC_IRAM_BASE + 0x800 - sizeof(T_Reset_Reason))
+ #endif
+
+ #define os_statistic_check() *((volatile unsigned long *)OS_STATISTIC_IRAM_BASE)
+@@ -98,6 +99,12 @@
+ } statistics[OS_DDR_STATISTIC_CNT];
+ }t_os_ddr_statistic;
+
++typedef struct
++{
++ char ramdump_reason[32]; //±ÈÈ磺ramdump_ap_appname
++ char kernel_reboot[32]; //±ÈÈ磺reboot_ap_appname
++} T_Reset_Reason;
++
+ /*******************************************************************************
+ * È«¾Ö±äÁ¿ *
+ *******************************************************************************/
+@@ -134,6 +141,7 @@
+ volatile static t_os_ddr_statistic *g_os_ddr_softirq_end_statistic;
+ volatile static t_os_ddr_statistic *g_os_ddr_timer_start_statistic;
+ volatile static t_os_ddr_statistic *g_os_ddr_timer_end_statistic;
++volatile T_Reset_Reason *g_os_reset_reason;
+ #endif
+
+ /*******************************************************************************
+@@ -418,7 +426,32 @@
+ os_statistic_in_ddr(g_os_ddr_timer_end_statistic, func, time);
+ os_statistic_info_update();
+ }
++/*
++reason: 1 for ramdump, 2 for reboot
++cpu: ap/cap/rpm/phy
++app: current->comm
++*/
++/* Started by AICoder, pid:pf139dce4f7776c149ec081b508bae14e6084ede */
++void zxic_reset_reason(int reason, const char *cpu, const char *app)
++{
++ char buffer[32];
+
++ memset(buffer, 0, sizeof(buffer));
++ switch (reason)
++ {
++ case 1:
++ snprintf(buffer, 32, "reset_ramdump_%s_%s", cpu, app);
++ memcpy(g_os_reset_reason->ramdump_reason, buffer, sizeof(buffer));
++ break;
++ case 2:
++ snprintf(buffer, 32, "reset_kreboot_%s_%s", cpu, app);
++ memcpy(g_os_reset_reason->kernel_reboot, buffer, sizeof(buffer));
++ break;
++ default:
++ break;
++ }
++}
++/* Ended by AICoder, pid:pf139dce4f7776c149ec081b508bae14e6084ede */
+
+ /*******************************************************************************
+ * ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+@@ -438,9 +471,10 @@
+ #ifdef IRAM_BASE_ADDR_VA
+ g_zxic_trace_apcpu_addr = IRAM_BASE_ADDR_OS_STATISTIC_PSCPU;
+ #else
+- g_zxic_trace_apcpu_addr = ioremap(IRAM_BASE_ADDR_OS_STATISTIC_PSCPU, IRAM_BASE_LEN_OS_STATISTIC_PSCPU);
++ g_zxic_trace_apcpu_addr = ioremap(IRAM_BASE_ADDR_OS_STATISTIC_PSCPU, IRAM_BASE_LEN_OS_STATISTIC_PSCPU + IRAM_BASE_LEN_OS_STATISTIC_PHYCPU + IRAM_BASE_LEN_OS_STATISTIC_APCPU);
+ #endif
+
++ g_os_reset_reason = (T_Reset_Reason *)OS_IRAM_RESET_REASON_START;
+ /*
+ init_timer(&timer);
+ timer.expires = jiffies + 40*HZ;//msecs_to_jiffies(40*1000);//ÑÓ³Ù40Ãë
+diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
+index f730067..efdfe9e 100755
+--- a/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
++++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
+@@ -37,6 +37,7 @@
+
+
+ #include "i2s.h"
++#include "pub_debug_info.h"
+
+ #define ZX29_I2S_TOP_LOOP_REG 0xac
+
+@@ -362,48 +363,97 @@
+
+ #endif
+
+- static int zx29startup(struct snd_pcm_substream *substream)
+- {
+- // int ret = 0;
+- print_audio("Alsa Entered func %s\n", __func__);
+- //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++/* Started by AICoder, pid:r53959b7c94916e146e3093b301a356223b009fa */
++static int zx29startup(struct snd_pcm_substream *substream)
++{
++ //int ret = 0;
++ print_audio("Alsa Entered func %s\n", __func__);
++ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++
++ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+- struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+- return -EINVAL;
+- if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+- BUG();
++ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++
++ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
++ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
++ return -EINVAL;
++ }
++ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
++ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
++ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
++ return -EINVAL;
++ }
++ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened,);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
+ #if 0
+- unsigned long flags;
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- mdelay(1);
+-
+- raw_spin_lock_irqsave(&codec_pa_lock, flags);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+- }
++ unsigned long flags;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ mdelay(1);
++
++ raw_spin_lock_irqsave(&codec_pa_lock, flags);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
++ }
+ #endif
+
+-
+- return 0;
+- }
++
++ return 0;
++}
++/* Ended by AICoder, pid:r53959b7c94916e146e3093b301a356223b009fa */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
+index 1a8cf3e..ff07416 100755
+--- a/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
++++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
+@@ -36,6 +36,7 @@
+
+
+ #include "i2s.h"
++#include "pub_debug_info.h"
+
+ #define ZX29_I2S_TOP_LOOP_REG 0x60
+
+@@ -361,53 +362,102 @@
+
+ #endif
+
+- static int zx29startup(struct snd_pcm_substream *substream)
+- {
+- // int ret = 0;
+- print_audio("Alsa Entered func %s\n", __func__);
+- //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++/* Started by AICoder, pid:53525s2951m0dfb1406409962017998611b17cc1 */
++static int zx29startup(struct snd_pcm_substream *substream)
++{
++ //int ret = 0;
++ print_audio("Alsa Entered func %s\n", __func__);
++ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++
++ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+- struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+- return -EINVAL;
+- if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+- BUG();
++ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++
++ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
++ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
++ return -EINVAL;
++ }
++ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
++ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
++ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
++ return -EINVAL;
++ }
++ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
+ #if 0
+- unsigned long flags;
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- mdelay(1);
+-
+- raw_spin_lock_irqsave(&codec_pa_lock, flags);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+- }
++ unsigned long flags;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ mdelay(1);
++
++ raw_spin_lock_irqsave(&codec_pa_lock, flags);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
++ }
+ #endif
+-
+- unsigned int armRegBit = 0;
+- //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+- //armRegBit &= 0xfffffffe;
+- //armRegBit |= 0x1;
+- //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+-
+- return 0;
+- }
++
++ unsigned int armRegBit = 0;
++ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
++ //armRegBit &= 0xfffffffe;
++ //armRegBit |= 0x1;
++ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
++
++ return 0;
++}
++/* Ended by AICoder, pid:53525s2951m0dfb1406409962017998611b17cc1 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
+index 1204542..0aaf23f 100755
+--- a/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
++++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
+@@ -39,6 +39,7 @@
+
+
+ #include "i2s.h"
++#include "pub_debug_info.h"
+
+ #define ZX29_I2S_TOP_LOOP_REG 0x60
+ //#define NAU_CLK_ID 0
+@@ -101,29 +102,97 @@
+ struct snd_ctl_elem_value *ucontrol);
+
+
+- static int zx29startup(struct snd_pcm_substream *substream)
+- {
+- // int ret = 0;
+- print_audio("Alsa Entered func %s\n", __func__);
+- //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++/* Started by AICoder, pid:i3fd98546erae28145550ba82095535ff4895652 */
++static int zx29startup(struct snd_pcm_substream *substream)
++{
++ //int ret = 0;
++ print_audio("Alsa Entered func %s\n", __func__);
++ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++
++ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+- struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+- return -EINVAL;
+- if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+- BUG();
++ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++
++ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
++ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
++ return -EINVAL;
++ }
++ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
++ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
++ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
++ return -EINVAL;
++ }
++ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
+
+-
+- return 0;
+- }
++#if 0
++ unsigned long flags;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ mdelay(1);
++
++ raw_spin_lock_irqsave(&codec_pa_lock, flags);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
++ }
++#endif
++
++
++ return 0;
++}
++/* Ended by AICoder, pid:i3fd98546erae28145550ba82095535ff4895652 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
+index ea874ee..7cb0c36 100755
+--- a/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
++++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
+@@ -37,6 +37,7 @@
+
+
+ #include "i2s.h"
++#include "pub_debug_info.h"
+
+ #define ZX29_I2S_TOP_LOOP_REG 0x60
+ #define CODEC_CLK_ID 0
+@@ -371,48 +372,97 @@
+
+
+
+- static int zx29startup(struct snd_pcm_substream *substream)
+- {
+- // int ret = 0;
+- print_audio("Alsa Entered func %s\n", __func__);
+- //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++/* Started by AICoder, pid:g33a6vccc4k69881474b0948e0153c719773e1fe */
++static int zx29startup(struct snd_pcm_substream *substream)
++{
++ //int ret = 0;
++ print_audio("Alsa Entered func %s\n", __func__);
++ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++
++ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+- struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+- return -EINVAL;
+- if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+- BUG();
++ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++
++ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
++ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
++ return -EINVAL;
++ }
++ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
++ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
++ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
++ return -EINVAL;
++ }
++ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened;
++
++ return -EBUSY;
++ //BUG();
++ }
++
+ #if 0
+- unsigned long flags;
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- mdelay(1);
+-
+- raw_spin_lock_irqsave(&codec_pa_lock, flags);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+- }
++ unsigned long flags;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ mdelay(1);
++
++ raw_spin_lock_irqsave(&codec_pa_lock, flags);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
++ }
+ #endif
+-
+-
+- return 0;
+- }
++
++
++ return 0;
++}
++/* Ended by AICoder, pid:g33a6vccc4k69881474b0948e0153c719773e1fe */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
+index 1e5777d..4dc8672 100755
+--- a/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
++++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
+@@ -37,6 +37,7 @@
+
+
+ #include "i2s.h"
++#include "pub_debug_info.h"
+
+ #define ZX29_I2S_TOP_LOOP_REG 0x60
+ #define NAU_CLK_ID 0
+@@ -373,48 +374,97 @@
+
+
+
+- static int zx29startup(struct snd_pcm_substream *substream)
+- {
+- // int ret = 0;
+- print_audio("Alsa Entered func %s\n", __func__);
+- //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++/* Started by AICoder, pid:we8d34d80fbc7981449d0b1590d6b753b789d779 */
++static int zx29startup(struct snd_pcm_substream *substream)
++{
++ //int ret = 0;
++ print_audio("Alsa Entered func %s\n", __func__);
++ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++
++ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+- struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+- return -EINVAL;
+- if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+- BUG();
++ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++
++ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
++ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
++ return -EINVAL;
++ }
++ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
++ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
++ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
++ return -EINVAL;
++ }
++ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
+ #if 0
+- unsigned long flags;
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- mdelay(1);
+-
+- raw_spin_lock_irqsave(&codec_pa_lock, flags);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+- }
++ unsigned long flags;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ mdelay(1);
++
++ raw_spin_lock_irqsave(&codec_pa_lock, flags);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
++ }
+ #endif
+-
+-
+- return 0;
+- }
++
++
++ return 0;
++}
++/* Ended by AICoder, pid:we8d34d80fbc7981449d0b1590d6b753b789d779 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
+index 9959350..3b9bedf 100755
+--- a/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
++++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
+@@ -37,6 +37,7 @@
+
+
+ #include "i2s.h"
++#include "pub_debug_info.h"
+
+ #define ZX29_I2S_TOP_LOOP_REG 0x60
+
+@@ -370,48 +371,97 @@
+
+
+
+- static int zx29startup(struct snd_pcm_substream *substream)
+- {
+- // int ret = 0;
+- print_audio("Alsa Entered func %s\n", __func__);
+- //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++/* Started by AICoder, pid:cd752b8f85qb5fa14ec60aceb0c11d619783bee6 */
++static int zx29startup(struct snd_pcm_substream *substream)
++{
++ //int ret = 0;
++ print_audio("Alsa Entered func %s\n", __func__);
++ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
++
++ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
++ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+- struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+- if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+- return -EINVAL;
+- if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+- (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+- (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+- BUG();
++ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
++
++ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
++ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
++ return -EINVAL;
++ }
++ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
++ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
++ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
++ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
++ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
++ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
++ {
++ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
++ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
++ return -EINVAL;
++ }
++ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
++ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
++ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
++ {
++ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
++ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
++ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
++
++ return -EBUSY;
++ //BUG();
++ }
++
+ #if 0
+- unsigned long flags;
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- mdelay(1);
+-
+- raw_spin_lock_irqsave(&codec_pa_lock, flags);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+- udelay(2);
+- gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+- raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+- }
++ unsigned long flags;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ mdelay(1);
++
++ raw_spin_lock_irqsave(&codec_pa_lock, flags);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
++ udelay(2);
++ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
++ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
++ }
+ #endif
+-
+-
+- return 0;
+- }
++
++
++ return 0;
++}
++/* Ended by AICoder, pid:cd752b8f85qb5fa14ec60aceb0c11d619783bee6 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+diff --git a/upstream/pub/include/infra/pub_debug_info.h b/upstream/pub/include/infra/pub_debug_info.h
+index 95a480f..1ee2f88 100755
+--- a/upstream/pub/include/infra/pub_debug_info.h
++++ b/upstream/pub/include/infra/pub_debug_info.h
+@@ -36,6 +36,10 @@
+
+ #define MODULE_ID_CAP_FOTA ("cap_fota")
+ #define MODULE_ID_CAP_FS_CHECK ("cap_fs_check")
++
++#define MODULE_ID_PS_AUDIO ("ps_audio")
++#define MODULE_ID_AP_AUDIO ("ap_audio")
++#define MODULE_ID_CAP_AUDIO ("cap_audio")
+
+ #if defined(_USE_ZXIC_DEBUG_INFO)
+ int sc_debug_info_vrecord(char *id, const char *format, va_list args);
+diff --git a/upstream/pub/include/ps_phy/atipsevent.h b/upstream/pub/include/ps_phy/atipsevent.h
+index 92e71e6..adc2b63 100755
+--- a/upstream/pub/include/ps_phy/atipsevent.h
++++ b/upstream/pub/include/ps_phy/atipsevent.h
+@@ -952,6 +952,7 @@
+ #define MMIA_UMM_FAST_FREQ_SCAN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 35)
+ #define MMIA_UMM_IMSAIRREL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 36)
+ #define MMIA_UMM_SOFTPOWER_STATUS_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 37)
++#define MMIA_UMM_IMS_CALL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 38)
+
+
+ #define MMIA_UMM_PLMN_INFO_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 0)
+@@ -1012,6 +1013,7 @@
+ #define MMIA_CC_T9TIMER_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 18)
+ #define MMIA_CC_VOICEMODE_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 19)
+ #define MMIA_CC_RESETIVS_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 20)
++#define MMIA_CC_WAITMSD_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 21)
+
+ #define MMIA_CC_MOC_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 0)
+ #define MMIA_CC_MTC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 1)
+@@ -1048,6 +1050,7 @@
+ #define MMIA_CC_CALLBACK_EVENT_EV (DWORD)(MMIA_CC_RSP_EVENT + 32)
+ #define MMIA_CC_VOICEMODE_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 33)
+ #define MMIA_CC_RESETIVS_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 34)
++#define MMIA_CC_WAITMSD_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 35)
+
+ /* ========================================================================
+ MMIA£SMSÏûÏ¢ºÅ¶¨Òå
+diff --git a/upstream/pub/include/ps_phy/psevent.h b/upstream/pub/include/ps_phy/psevent.h
+index d1fbdf8..4a1897b 100755
+--- a/upstream/pub/include/ps_phy/psevent.h
++++ b/upstream/pub/include/ps_phy/psevent.h
+@@ -1588,6 +1588,7 @@
+ #define IVS_CC_MSD_STATE_IND_EV (DWORD)(CM_MM_EVENT_BASE + 25)
+
+ #define PSAP_UL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 26)
++#define CC_UMM_ECALL_EVENT_IND_EV (DWORD)(CM_MM_EVENT_BASE + 27)
+
+ /* ========================================================================
+ UMM£MM/GMM/EMMÏûÏ¢ºÅ¶¨Òå
+@@ -4000,6 +4001,7 @@
+ /*ESM->UMM*/
+ #define ESM_UMM_DETACH_REQ_EV (DWORD)(ESM_UMM_EVENT_BASE + 0) /*Modified:KangShuJie*/
+ #define ESM_UMM_LOCAL_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 1)
++#define ESM_UMM_EMERPDN_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 2)
+
+ /* ========================================================================
+ SMºÍESMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
new file mode 100755
index 0000000..fe9fc43
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
@@ -0,0 +1,20 @@
+PAGESIZE = "0x1000"
+ERASEBLOCK = "0x40000"
+UBI_LEB_SIZE = "253952"
+UBI_IMAGE_SEQ = "1024"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+LYNQ_M22_PAGESIZE = "0x800"
+LYNQ_M22_ERASEBLOCK = "0x20000"
+LYNQ_M22_UBI_LEB_SIZE = "126976"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+#rootfs ubi参数配置
+#MKUBIFS_ARGS = "-m ${PAGESIZE} -e ${UBI_LEB_SIZE} -c 122 -x zlib -F"
+UBINIZE_ARGS = "-m ${PAGESIZE} -p ${ERASEBLOCK} -s ${PAGESIZE} -Q ${UBI_IMAGE_SEQ}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+LYNQ_M22_UBINIZE_ARGS = "-m ${LYNQ_M22_PAGESIZE} -p ${LYNQ_M22_ERASEBLOCK} -s ${LYNQ_M22_PAGESIZE} -Q ${UBI_IMAGE_SEQ}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+#userdata ubi参数配置
+USERDATA_UBINIZE_ARGS = "${UBINIZE_ARGS}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+LYNQ_M22_USERDATA_UBINIZE_ARGS = "${LYNQ_M22_UBINIZE_ARGS}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
new file mode 100755
index 0000000..231b4a1
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
@@ -0,0 +1,477 @@
+require conf/distro/include/cpe-base.inc
+
+DISTRO = "vehicle_dc_ref"
+DISTRO_NAME = "zxic Distro vehicle_dc_ref"
+DISTRO_VERSION = "1.0"
+SDK_VENDOR = "-zxic"
+MAINTAINER = "Sanechips Co.，Ltd."
+TARGET_VENDOR = "-zxic"
+
+## OPTEE
+DISTRO_FEATURES += "OPTEE"
+meta_optee += " ${@bb.utils.contains("DISTRO_FEATURES", "OPTEE", " optee-client optee-example ", "", d)} "
+
+PREFERRED_PROVIDER_virtual/kernel = "linux-zxic"
+PREFERRED_VERSION_linux-zxic = "5.10.156"
+PREFERRED_VERSION_busybox = "1.33.1"
+#PREFERRED_VERSION_openssl = "1.1.1l"
+
+TCLIBC = "glibc"
+VIRTUAL-RUNTIME_dev_manager = "busybox-mdev"
+VIRTUAL-RUNTIME_login_manager = "busybox"
+VIRTUAL-RUNTIME_init_manager = "busybox"
+VIRTUAL-RUNTIME_initscripts = "initscripts"
+
+# #
+# # Use systemd for system initialization
+# #
+# VIRTUAL-RUNTIME_init_manager = "systemd"
+# PREFERRED_PROVIDER_udev = "systemd"
+# PREFERRED_PROVIDER_udev-utils = "systemd"
+# DISTRO_FEATURES_BACKFILL_CONSIDERED = "sysvinit"
+# VIRTUAL-RUNTIME_initscripts = ""
+# DEFAULT_DISTRO_FEATURES += "systemd"
+# DISTRO_FEATURES_append = " systemd"
+# DISTRO_FEATURES_remove = "sysvinit"
+
+KERNEL_DEVICETREE = " \
+ zx297520v3-vehicle_dc_ref.dtb \
+"
+# selinux 配置
+DISTRO_FEATURES_append=" selinux "
+
+# 默认是强制模式 enforcing ，调试建议采用宽容模式 permissive
+DEFAULT_ENFORCING = "permissive"
+
+# selinux 策略
+PREFERRED_PROVIDER_virtual/refpolicy ?= "refpolicy-mls"
+
+## adb login
+DISTRO_FEATURES += "adb_login"
+
+# storage type: nand or emmc
+STRORAGE_TYPE = "nand"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+STRORAGE_CONF = "nand-config-default"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+require conf/distro/include/${STRORAGE_CONF}.inc
+
+#rootfs文件系统类型
+IMAGE_FSTYPES = "squashfs"
+#IMAGE_FSTYPES = "cpio.gz"
+
+
+#rootfs文件系统squashfs参数配置，压缩方式和块大小可以更改
+#squashfs_xz squashfs_zstd
+DISTRO_FEATURES_append = " squashfs_zstd "
+ROOTFS_SQUASHFS_ARGS = "-nopad -noappend -root-owned -b 256k -p '/dev d 755 0 0' -p '/dev/console c 600 0 0 5 1' -processors 1"
+ROOTFS_SQUASHFS_ARGS += " ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "-xattrs", "", d)} "
+ROOTFS_SQUASHFS_ARGS += "${@bb.utils.contains("DISTRO_FEATURES", "squashfs_zstd", " -comp zstd ","", d)}"
+ROOTFS_SQUASHFS_ARGS += "${@bb.utils.contains("DISTRO_FEATURES", "squashfs_xz", " -comp xz -Xpreset 9 -Xe -Xlc 0 -Xlp 2 -Xpb 2 ","", d)}"
+
+#userdata文件系统类型
+USERDATA_FSTYPE = "ubi"
+USERDATA_UBINIZE_CFG = "userdata-ubi-default.cfg"
+OEMDATA_UBINIZE_CFG = "oemdata-ubi-default.cfg"
+
+#userdata ext4 文件系统大小
+USERDATA_EXT4SIZE = "194018"
+
+#
+# system initialization
+#
+DISTRO_FEATURES_append = " sysvinit "
+
+
+#是否支持MMI LCD功能
+#DISTRO_FEATURES += "MMI_LCD"
+#语音控制
+DISTRO_FEATURES += "voice_alsa"
+DISTRO_FEATURES += "use_voice_buffer"
+#DISTRO_FEATURES += "voice_at"
+
+#cap_oem.img
+DISTRO_FEATURES += " oemfs "
+
+#dm-verity for squashfs
+DISTRO_FEATURES += " dm-verity "
+
+
+#CUSTOM_MACRO在各个产品不变的宏放到cpe-base.inc文件，变化的宏放在产品发布文件。
+CUSTOM_MACRO += " -D_GNU_SOURCE "
+
+#产品linux kernel配置，主要区分cpe、v2x、mdl,fpga文件在./meta-zxic/recipes-kernel/linux/files目录下
+#BOOT_CTL:版本的启动方式，normal/recovery，如：linux-5_4-fpga-normal.defconfig
+LINUX_BASE_CONFIG = "linux-5_10-${DISTRO}-${BOOT_CTL}-defconfig"
+
+#型号机linux kernel配置，主要区分mdlxx、mdlyy等型号机,文件在./meta-zxic-custom/recipes-kernel/linux/files目录下
+#BOOT_CTL:版本的启动方式，normal/recovery，如：linux-5_4-mdl-normal.cfg
+LINUX_CONFIG = "linux-5_10-${DISTRO}-${BOOT_CTL}.cfg"
+
+#busybox 配置 文件在./meta-zxic/recipes-core/busybox/files目录下
+BUSYBOX_CONFIG = "${DISTRO}-${BOOT_CTL}-busybox.cfg"
+
+##############################################################################
+# custom macro for lib and app
+CUSTOM_MACRO += " -DAPP_OS_LINUX=1 "
+CUSTOM_MACRO += " -DAPP_OS_TYPE=APP_OS_LINUX "
+
+ENABLE_TESTBENCH_TTY = "no"
+##testbench macro for mode,notty=0 single=1 uchm=2
+CUSTOM_MACRO += " -DTTY_MODE_NO=0 "
+CUSTOM_MACRO += " -DTTY_MODE_SINGLE=1 "
+CUSTOM_MACRO += " -DTTY_MODE_MUX=2 "
+CUSTOM_MACRO += " -DUSE_UBIFS "
+CUSTOM_MACRO += " -DUSE_CAP_SUPPORT "
+CUSTOM_MACRO += " -DFOTA_AB "
+CUSTOM_MACRO += "${@bb.utils.contains('ENABLE_TESTBENCH_TTY', 'yes', '-DTESTBENCH_TTY_MODE=TTY_MODE_SINGLE', '-DTESTBENCH_TTY_MODE=TTY_MODE_NO', d)}"
+CONFIG_MMI_LCD = "${@bb.utils.contains("DISTRO_FEATURES", "MMI_LCD", "yes","no", d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_MMI_LCD', 'yes', '', '-DDISABLE_LCD', d)}"
+USE_ZXIC_WEBUI = "no"
+CONFIG_USE_WEBUI_SSL="yes"
+CONFIG_USE_WEBUI_SECURITY="yes"
+#security compile options
+CFLAGS_append = " -Wl,-z,noexecstack"
+SECURITY_PIE_CFLAGS = " -pie -fPIE"
+SECURITY_STACK_PROTECTOR = " -fstack-protector-all"
+#CUSTOM_MACRO += " -D_USE_CODEC_TI3100 "
+#CUSTOM_MACRO += " -D_USE_CODEC_NAU8810 "
+#CUSTOM_MACRO += " -D_USE_CODEC_TI3104 "
+#CUSTOM_MACRO += " -D_USE_CODEC_MAX9867 "
+CUSTOM_MACRO += " -D_USE_CODEC_ES8311 "
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'voice_alsa', '-D_USE_VOICE_ALSA', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'use_voice_buffer', '-D_USE_VOICE_BUFFER', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'voice_at', '-D_USE_VOICE_AT', '', d)}"
+#CONFIG_VB_TRANSMIT_INTF = "RTP"
+#CONFIG_VB_TRANSMIT_INTF = "USB"
+CONFIG_VB_TRANSMIT_INTF = "NULL"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', '-D_VB_TRANSMIT_INTF_RTP', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'USB', '-D_VB_TRANSMIT_INTF_USB', '', d)}"
+#wifi 配置
+#"mt7916" "" "" ""
+CONFIG_WIFI_MODULE = "mt7916"
+#"apsta" "sta" "ap"
+CONFIG_WIFI_FUNCTION = "ap"
+#wificfg = "${@bb.utils.contains('CONFIG_WIFI_FUNCTION', 'ap', bb.utils.contains('CONFIG_WIFI_MODULE', 'esp8089', 'lib32-hostapd-2.6', '', d), '', d)}"
+
+#BL接口支持("BL")，RIL接口支持("RIL")
+CONFIG_TEL_API_SUPPORT = "RIL"
+
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'BL', '-D_USE_BL', '', d)}"
+
+#RIL AT通道支持RPMSG模式
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', '-DZXIC_ATCHN_RPMSG_MODE', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', '-DUSE_CUSTOM_YK', '', d)}"
+
+DISTRO_FEATURES += " vehicle_dc_ref "
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'vehicle_dc_ref', '-D_USE_VEHICLE_DC_REF', '', d)}"
+
+#多媒体编解码库支持类型"FFMPEG"，"NONE"
+CONFIG_MSMSVR_CODEC_TYPE = "NONE"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_MSMSVR_CODEC_TYPE', 'FFMPEG', '-D_USE_FFMPEG', '', d)}"
+
+#是否使用新的信号强度命令
+CONFIG_USE_NEW_SIGNAL_STRENGTH = "yes"
+
+# app and libs 配置
+#normal的版本应用及库
+zxic_lib += "\
+ libnvram \
+ libatchn \
+ libsofttimer \
+ libzxic-pbm \
+ libsoftap \
+ libatutils \
+ libsqlite \
+ libscipc \
+ libsctel \
+ libbsp \
+ libtinyalsa\
+ libvoice \
+ libmedia \
+ libdebug-info \
+ libmtd \
+ libsclog \
+ libupi-ab \
+ libbinder \
+ libflags \
+ libmsmsvr \
+ libscrtc \
+ liblynq-uci \
+ liblynq-shm \
+ liblynq-log \
+ libapn \
+ libpal \
+ libvendor-ril \
+ liblynq-call \
+ liblynq-sim \
+ liblynq-network \
+ liblynq-sms \
+ liblynq-data \
+ liblynq-qser-voice \
+ liblynq-qser-sim \
+ liblynq-qser-sms \
+ liblynq-qser-thermal \
+ liblynq-qser-data \
+ liblynq-qser-network \
+ liblynq-qser-gnss \
+ liblynq-qser-fota \
+ liblynq-qser-audio \
+ liblynq-qser-usb \
+ liblynq-qser-wifi \
+ libpoweralarm \
+ liblynq-systime \
+ liblynq-autosuspend \
+ liblynq-qser-autosuspend \
+ liblynq-at-factory \
+ liblynq-gpio \
+ liblynq-irq \
+ liblynq-at-common \
+ liblynq-led \
+ liblynq-adc \
+ liblynq-monitor \
+ "
+
+zxic_lib += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', 'libril', 'libtelsvr', d)}"
+zxic_lib += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', 'librtp', '', d)}"
+#zxic自研应用
+zxic_app_open += "\
+ nvserver cfg-tool adb ab-bootinfo \
+ at-ctl \
+ atchn-test \
+ zxic-mainctrl \
+ zxic-mmi \
+ zxic-script \
+ zxic-hotplug \
+ zxic-ramdump \
+ sntp \
+ zxic-ipv6-slaac \
+ zxic-ipv6-addr-conver \
+ zxic-ndp \
+ rtc-service \
+ dhcp6 \
+ fscheck \
+ nv-rpc-daemon \
+ zlog-agent \
+ cc-demo \
+ sim-demo \
+ sms-demo \
+ socket-demo \
+ i2ctest \
+ spitest \
+ uarttest \
+ bsp-test \
+ zxic-debug \
+ crc \
+ crc-api \
+ voiceipc-mainctrl \
+ voice-demo \
+ fsmonitor \
+ ethtest \
+ sc-at-test \
+ dialtest \
+ sc-nw-mgr-test \
+ sc-cfg-test \
+ sc-softtimer-test \
+ sc-log-test \
+ sc-shm-test \
+ sc-msg-test \
+ adctest \
+ rtc-timer-demo \
+ tsctest \
+ fota-upi-ab \
+ sc-net-test \
+ usbtest \
+ zxic-amt \
+ wlan-proxy \
+ wifi-demo \
+ mnet-whitelist \
+ mnet-whitelist-proxy \
+ flags-tool \
+ msm-svr \
+ phymiitest \
+ player-demo \
+ servicemanager \
+ service \
+ service-test \
+ i2cslavetest \
+ fota-auto-sync \
+ softap-demo \
+ lynq-ril-service \
+ lynq-sdk-ready \
+ lynq-led-demo \
+ lynq-led-sev \
+ uci \
+ gdb \
+ mobiletek-tester-rdit \
+ lynq-qser-voice-demo \
+ lynq-qser-fota-demo \
+ lynq-qser-gnss-demo \
+ lynq-qser-network-demo \
+ poweralarm-demo \
+ lynq-systime-demo \
+ lynq-fota-backup \
+ lynq-qser-sim-demo \
+ lynq-qser-sms-demo \
+ lynq-qser-data-demo \
+ lynq-qser-thermal-demo \
+ lynq-autosuspend \
+ lynq-atcid \
+ lynq-qser-autosuspend-demo \
+ lynq-gpio-demo \
+ lynq-irq-demo \
+ lynq-gnss-update \
+ lynq-audio-demo \
+ lynq-usb-demo \
+ lynq-wifi-demo \
+ lynq-adc-demo \
+ lynq-at-test \
+ lynq-monitor-demo \
+ "
+
+zxic_app_open += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', 'rild', '', d)}"
+zxic_app_open += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'BL', 'tel-svr', '', d)}"
+
+#开源应用及库
+meta_app_open += "\
+ dropbear \
+ dbus \
+ e2fsprogs \
+ iptables \
+ curl \
+ dnsmasq \
+ dhcp6 \
+ radvd \
+ iproute2 \
+ busybox-syslog \
+ ethtool \
+ sqlcipher \
+ iperf3 \
+ tcpdump \
+ python3 \
+ openssl-bin \
+ mtd-utils-ubifs \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'dm-verity', 'cryptsetup', '', d)} \
+ ${meta_optee} \
+ tzdata \
+ fdk-aac-master \
+ opencore-amr \
+ vo-amrwbenc \
+ ffmpeg \
+ python3 \
+ lrzsz \
+ "
+meta_app_open += "${@bb.utils.contains('CONFIG_MSMSVR_CODEC_TYPE', 'FFMPEG', 'fdk-aac-master opencore-amr vo-amrwbenc ffmpeg', '', d)}"
+
+#normal的版本应用及库
+zxic_app += "\
+ ${zxic_lib} \
+ ${zxic_app_open} \
+ ${meta_app_open} \
+ "
+
+#zxic自研recovery版本的应用
+zxic_app_open_recovery += "\
+ "
+#recovery版本的开源应用及库
+meta_app_open_recovery += "\
+ "
+#recovery的版本应用及库
+zxic_app_recovery += "\
+ ${zxic_app_open_recovery} \
+ ${meta_app_open_recovery} "
+
+IMAGE_INSTALL +="\
+ ${@bb.utils.contains("BOOT_CTL", "recovery", "${zxic_app_recovery}", "${zxic_app}", d)} \
+ "
+
+PACKAGE_EXCLUDE = "eudev eudev-dev eudev-dbg"
+PACKAGE_EXCLUDE = "eudev"
+
+#DISTRO = "lynq_vehicle_dc"
+#DISTRO_NAME = "lynq distro vehicle_dc"
+RAT_CONFIG_C2K_SUPPORT = "no"
+MTK_MULTI_SIM_SUPPORT = "dsds"
+TARGET_PLATFORM = "T106"
+MTK_LED_SUPPORT = "yes"
+#support lynq_atsvc [hong.liu add for lynq atsvc on 2022.12.1]
+LYNQ_ATSVC_SUPPORT = "yes"
+
+#GPIO_CFG value:"PLATFORM" , "GENVICT" ,"GSW"
+MOBILETEK_GPIO_CFG = "PLATFORM"
+
+#PLL_CFG value:"PLATFORM","GSW"
+MOBILETEK_PLL_CFG = "PLATFORM"
+
+#RTP_CFG value:"PLATFORM","GSW"
+MOBILETEK_RTP_CFG = "PLATFORM"
+
+#MEDIA_CFG value:"PLATFORM","GSW"
+MOBILETEK_MEDIA_CFG = "PLATFORM"
+
+#LOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_LOG_CFG = "PLATFORM"
+
+#FOTA_CFG value:"PLATFORM","GSW"
+MOBILETEK_FOTA_CFG = "PLATFORM"
+
+#RIL_CFG value:"PLATFORM","GSW"
+MOBILETEK_RIL_CFG = "PLATFORM"
+
+#UART_CFG value:"PLATFORM","GSW"
+MOBILETEK_UART_CFG = "PLATFORM"
+
+#USB_CFG value:"PLATFORM","GSW"
+MOBILETEK_USB_CFG = "PLATFORM"
+
+#ndis_CFG value:"PLATFORM","GSW"
+MOBILETEK_NDIS_CFG = "PLATFORM"
+
+#SUSPEND_CFG value:"PLATFORM","GSW"
+MOBILETEK_SUSPEND_CFG = "PLATFORM"
+
+#MNLDLOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_MNLDLOG_CFG = "PLATFORM"
+
+#OPTEE_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPTEE_CFG = "PLATFORM"
+
+#EMMC_CFG value:"PLATFORM","GSW"
+MOBILETEK_EMMC_CFG = "PLATFORM"
+
+#WIFIKERNELCODE_CFG value:"PLATFORM","GSW"
+MOBILETEK_WIFIKERNELCODE_CFG = "PLATFORM"
+
+#SYSTEMD_CFG value:"PLATFORM","GSW"
+MOBILETEK_SYSTEMD_CFG = "PLATFORM"
+
+#GSTREAMER_CFG value:"PLATFORM","GSW"
+MOBILETEK_GSTREAMER_CFG = "PLATFORM"
+
+#BUSYBOX_CFG value:"PLATFORM","GSW"
+MOBILETEK_BUSYBOX_CFG = "PLATFORM"
+
+#OPENSSH_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPENSSH_CFG = "PLATFORM"
+
+#OEMAPP_CFG value:"PLATFORM","GSW"
+MOBILETEK_OEMAPP_CFG = "PLATFORM"
+
+#cz.li@20240221 add for choosing GNSS's chip: "HD","HX"
+MOBILETEK_GNSS_TYPE = "HD"
+
+#MOBILETEK_ADB_LOGIN value:"YES","NO"
+MOBILETEK_ADB_LOGIN = "NO"
+
+#cz.li@20240221 add for MOBILETEK_GNSS_UPDATE_ENABLE value: "yes","no"
+MOBILETEK_GNSS_UPDATE_ENABLE = "yes"
+
+#xf.li@20240716 add for MOBILETEK_LOG_ENCRYPT value: "enable","disable"
+MOBILETEK_LOG_ENCRYPT = "disable"
+
+#xf.li@20250123 add for M22 SDK value (support M22 or not): "M22", "default"
+MOBILETEK_NAND_TYPE = "M22"
+
+LYNQ_CONFIG_COMMITID = "e2a3410390ff0ad762462ccb6af8faa5e16dcd61"
+LYNQ_CONFIG_VERSION = "T106-M42-PLXXXX-P56U11.AP.19.00_CAP.19.00.01"
+LYNQ_CONFIG_SW_VERSION = "T106-MXX-PLXXXX-P56U11.AP.19.00_CAP.19.00"
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/lynq_base.conf b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
new file mode 100755
index 0000000..73d9856
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
@@ -0,0 +1,72 @@
+#DISTRO = "lynq_vehicle_dc"
+#DISTRO_NAME = "lynq distro vehicle_dc"
+RAT_CONFIG_C2K_SUPPORT = "no"
+MTK_MULTI_SIM_SUPPORT = "dsds"
+TARGET_PLATFORM = "T106"
+MTK_LED_SUPPORT = "yes"
+#support lynq_atsvc [hong.liu add for lynq atsvc on 2022.12.1]
+LYNQ_ATSVC_SUPPORT = "yes"
+
+#GPIO_CFG value:"PLATFORM" , "GENVICT" ,"GSW"
+MOBILETEK_GPIO_CFG = "PLATFORM"
+
+#PLL_CFG value:"PLATFORM","GSW"
+MOBILETEK_PLL_CFG = "PLATFORM"
+
+#RTP_CFG value:"PLATFORM","GSW"
+MOBILETEK_RTP_CFG = "PLATFORM"
+
+#MEDIA_CFG value:"PLATFORM","GSW"
+MOBILETEK_MEDIA_CFG = "PLATFORM"
+
+#LOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_LOG_CFG = "PLATFORM"
+
+#FOTA_CFG value:"PLATFORM","GSW"
+MOBILETEK_FOTA_CFG = "PLATFORM"
+
+#RIL_CFG value:"PLATFORM","GSW"
+MOBILETEK_RIL_CFG = "PLATFORM"
+
+#UART_CFG value:"PLATFORM","GSW"
+MOBILETEK_UART_CFG = "PLATFORM"
+
+#USB_CFG value:"PLATFORM","GSW"
+MOBILETEK_USB_CFG = "PLATFORM"
+
+#ndis_CFG value:"PLATFORM","GSW"
+MOBILETEK_NDIS_CFG = "PLATFORM"
+
+#SUSPEND_CFG value:"PLATFORM","GSW"
+MOBILETEK_SUSPEND_CFG = "PLATFORM"
+
+#MNLDLOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_MNLDLOG_CFG = "PLATFORM"
+
+#OPTEE_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPTEE_CFG = "PLATFORM"
+
+#EMMC_CFG value:"PLATFORM","GSW"
+MOBILETEK_EMMC_CFG = "PLATFORM"
+
+#WIFIKERNELCODE_CFG value:"PLATFORM","GSW"
+MOBILETEK_WIFIKERNELCODE_CFG = "PLATFORM"
+
+#SYSTEMD_CFG value:"PLATFORM","GSW"
+MOBILETEK_SYSTEMD_CFG = "PLATFORM"
+
+#GSTREAMER_CFG value:"PLATFORM","GSW"
+MOBILETEK_GSTREAMER_CFG = "PLATFORM"
+
+#BUSYBOX_CFG value:"PLATFORM","GSW"
+MOBILETEK_BUSYBOX_CFG = "PLATFORM"
+
+#OPENSSH_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPENSSH_CFG = "PLATFORM"
+
+#OEMAPP_CFG value:"PLATFORM","GSW"
+MOBILETEK_OEMAPP_CFG = "PLATFORM"
+
+LYNQ_CONFIG_COMMITID = "7b4d681bdad8b0a31c564ea665a424b81038791a"
+LYNQ_CONFIG_VERSION = "T106-M42-PLXXXX-P56U11.AP.19.00_CAP.19.00.01"
+LYNQ_CONFIG_SW_VERSION = "T106-MXX-PLXXXX-P56U11.AP.19.00_CAP.19.00"
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
new file mode 100755
index 0000000..34e65ab
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
new file mode 100755
index 0000000..34e65ab
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
new file mode 100755
index 0000000..34e65ab
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
new file mode 100755
index 0000000..bd0c63c
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
@@ -0,0 +1,1137 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram -ldebug_info"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+# CONFIG_INIT is not set
+# CONFIG_LINUXRC is not set
+# CONFIG_FEATURE_USE_INITTAB is not set
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+# CONFIG_FEATURE_INIT_SCTTY is not set
+# CONFIG_FEATURE_INIT_SYSLOG is not set
+# CONFIG_FEATURE_INIT_QUIET is not set
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE=""
+# CONFIG_FEATURE_INIT_MODIFY_CMDLINE is not set
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+# CONFIG_MDEV is not set
+# CONFIG_FEATURE_MDEV_CONF is not set
+# CONFIG_FEATURE_MDEV_RENAME is not set
+# CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set
+# CONFIG_FEATURE_MDEV_EXEC is not set
+# CONFIG_FEATURE_MDEV_LOAD_FIRMWARE is not set
+# CONFIG_FEATURE_MDEV_DAEMON is not set
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..7570274
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,504 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=5
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+#yes-on no-off
+cc_at_debug=no
+xlat_enable=1
+ecallmode=2
+telog_path_cap=
+telog_path=
+zpsstate_detect=1
+zpsstate_detect_period=60
+zpsstate_restart=0
+ap_reset_app=default
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..63f20d3
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,503 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=5
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+#yes-on no-off
+cc_at_debug=no
+xlat_enable=1
+telog_path_cap=
+telog_path=
+zpsstate_detect=1
+zpsstate_detect_period=60
+zpsstate_restart=0
+ap_reset_app=default
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..f7695af
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,555 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+path_voice=/mnt/oem/voice
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=3
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_prof_ssid=
+wifi_prof_ssid1=
+wifi_prof_ssid2=
+wifi_prof_ssid3=
+wifi_prof_ssid4=
+wifi_prof_ssid5=
+wifi_prof_ssid6=
+wifi_prof_ssid7=
+wifi_prof_ssid8=
+wifi_prof_ssid9=
+wifi_prof_pw=
+wifi_prof_pw1=
+wifi_prof_pw2=
+wifi_prof_pw3=
+wifi_prof_pw4=
+wifi_prof_pw5=
+wifi_prof_pw6=
+wifi_prof_pw7=
+wifi_prof_pw8=
+wifi_prof_pw9=
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+#zw.wang After rndis used the network, the T106 sleep was repeatedly awakened on 20240429 start
+wifiAvailable=1
+#zw.wang After rndis used the network, the T106 sleep was repeatedly awakened on 20240429 end
+# zw.wang WiFi for MAC is obtained from firmware and set on 20240508 start
+wifi_mac_num=1
+# zw.wang WiFi for MAC is obtained from firmware and set on 20240508 end
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+SSID1_5g=Ufi_
+m_SSID_5g=Ufi_
+HideSSID_5g=0
+m_HideSSID_5g=0
+AuthMode_5g=WPA2PSK
+m_AuthMode_5g=WPA2PSK
+EncrypType_5g=AES
+m_EncrypType_5g=AES
+WPAPSK1_encode_5g=MTIzNDU2Nzg=
+WPAPSK1_aes_5g=
+m_WPAPSK1_encode_5g=MTIzNDU2Nzg=
+m_WPAPSK1_aes_5g=
+wifi_11n_cap_5g=1
+WirelessMode_5g=6
+Channel_5g=0
+# zw.wang [wifi] If the 5G hotspot is enabled, the country code cannot be obtained by calling qser_wifi_ap_channel_get on 20240829 start
+CountryCode_5g=CN
+# zw.wang [wifi] If the 5G hotspot is enabled, the country code cannot be obtained by calling qser_wifi_ap_channel_get on 20240829 end
+MAX_Access_num_5g=32
+m_MAX_Access_num_5g=0
+ACL_mode_5g=0
+wifi_mac_black_list_5g=
+wifi_mac_white_list_5g=
+wifi_sup_5g_band=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0+/dev/ttyGS1
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+#yes-on no-off
+cc_at_debug=no
+xlat_enable=1
+ecallmode=2
+telog_path_cap=
+telog_path=
+zpsstate_detect=1
+zpsstate_detect_period=60
+zpsstate_restart=0
+ap_reset_app=default
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..4c1dd17
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,498 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=5
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+xlat_enable=1
+telog_path_cap=
+telog_path=
+ap_reset_app=default
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
new file mode 100755
index 0000000..1a77daa
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
@@ -0,0 +1,295 @@
+SUMMARY = "zxic normal image"
+IMAGE_LINGUAS = " "
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+inherit core-image extrausers ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "selinux-image", "", d)}
+
+OPENWRT_FULL ="\
+ packagegroup-openwrt-minimal \
+ packagegroup-openwrt-base \
+ packagegroup-openwrt-full \
+ ugps \
+ usbmode \
+ urngd \
+ mtd-utils-ubifs \
+ fwtool \
+ usign \
+ swconfig \
+ mtd-openwrt \
+ opkg \
+ cgi-io \
+ "
+OPENWRT_RECOVERY ="\
+ packagegroup-openwrt-minimal \
+ mtd-utils-ubifs \
+ mtd-openwrt \
+ "
+
+
+OPENWRT_PACKAGE = "${@bb.utils.contains("BOOT_CTL", "recovery", "${OPENWRT_RECOVERY}", "${OPENWRT_FULL}", d)}"
+IS_OPENWRT = "${@bb.utils.contains('DISTRO_FEATURES', 'OPENWRT', 'true', 'false', d)}"
+ROOT_FS_NAME = "${@bb.utils.contains("BOOT_CTL", "recovery", "ap_recoveryfs.bin", "ap_caprootfs.img", d)}"
+USEDATA_FS_NAME = "${@bb.utils.contains("BOOT_CTL", "recovery", "ap_userdata_recovery.bin", "ap_capuserdata.img", d)}"
+OEMDATA_FS_NAME = "${@bb.utils.contains("BOOT_CTL", "recovery", "ap_oemdata_recovery.bin", "cap_oemdata.img", d)}"
+
+CORE_IMAGE_BASE_INSTALL = '\
+ ${@bb.utils.contains("DISTRO_FEATURES", "OPENWRT", "${OPENWRT_PACKAGE}", "", d)} \
+ packagegroup-core-boot-zxic \
+ packagegroup-lynq-t106 \
+ ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "packagegroup-selinux-minimal", "", d)} \
+ ${MACHINE_EXTRA_RDEPENDS} \
+ ${CORE_IMAGE_EXTRA_INSTALL} \
+ '
+
+# Include modules in rootfs
+IMAGE_INSTALL += "${CORE_IMAGE_BASE_INSTALL}"
+
+IMAGE_INSTALL += " \
+ kernel-modules \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'dpkg-start-stop', '', d)} \
+ "
+
+#pub include
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+
+DEPENDS += "\
+ u-boot-tools-native rsync-native \
+ ${@bb.utils.contains("USERDATA_FSTYPE", "ubi", "mtd-utils-native", "", d)} \
+ ${@bb.utils.contains('IMAGE_FSTYPES', 'squashfs', 'squashfskit-native', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','cryptsetup-native','',d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','coreutils-native','',d)} \
+ "
+
+# Add \ in front of $
+ROOT_PASSWD = "\$6\$GnJN6BAFj7TmbOS\$o4tptoaFJYZe79CWh2VzAgGhQGqfDHoraVUs0nr4TT2e9V2ubq.l.nLrF80ECrtfvPrJDL1J3fbR62nei9A3F1"
+#EXTRA_USERS_PARAMS += "usermod -p '${ROOT_PASSWD}' root;"
+EXTRA_USERS_PARAMS += "${@bb.utils.contains("DISTRO_FEATURES", "OPENWRT", "usermod -p '${ROOT_PASSWD}' root;", "", d)}"
+
+fakeroot distro_rootfs_files_systemd() {
+ rm -rf ${IMAGE_ROOTFS}/boot
+ cp -arfp ${FS-DIR}/fs/${BOOT_CTL}/rootfs/* ${IMAGE_ROOTFS}/
+}
+
+fakeroot distro_rootfs_files_fpga() {
+ rm -rf ${IMAGE_ROOTFS}/boot
+ rm -rf ${IMAGE_ROOTFS}/linuxrc
+ rm -rf ${IMAGE_ROOTFS}/etc/systemd/system.conf
+ cp -arfp ${FS-DIR}/fs/${BOOT_CTL}/rootfs/* ${IMAGE_ROOTFS}/
+ chmod 644 ${IMAGE_ROOTFS}/etc/passwd
+ chmod 644 ${IMAGE_ROOTFS}/etc/group
+ chmod 644 ${IMAGE_ROOTFS}/etc/inittab
+ chmod 400 ${IMAGE_ROOTFS}/etc/shadow
+ chmod a+x ${IMAGE_ROOTFS}/etc/init.d/rcS
+ chmod a+r ${IMAGE_ROOTFS}/etc/init.d/rcS
+}
+
+fakeroot distro_rootfs_files_sysvinit() {
+ rm -rf ${IMAGE_ROOTFS}/boot
+ cp -arfp ${FS-DIR}/fs/${BOOT_CTL}/rootfs/* ${IMAGE_ROOTFS}/
+
+ rm -rf ${IMAGE_ROOTFS}/etc/rc[0-6].d
+ rm -f ${IMAGE_ROOTFS}/etc/fstab
+ rm -f ${IMAGE_ROOTFS}/etc/default/rcS
+ chmod 644 ${IMAGE_ROOTFS}/etc/passwd
+ chmod 644 ${IMAGE_ROOTFS}/etc/group
+ chmod 644 ${IMAGE_ROOTFS}/etc/inittab
+ chmod 400 ${IMAGE_ROOTFS}/etc/shadow
+ chmod a+x ${IMAGE_ROOTFS}/etc/init.d/rcS
+ find ${IMAGE_ROOTFS}/ -name '.gitkeep' -print0 | xargs -0 rm -fr
+}
+
+ROOTFS_POSTPROCESS_COMMAND += "\
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "distro_rootfs_files_sysvinit;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "distro_rootfs_files_systemd;", "", d)} \
+ "
+
+fakeroot do_cprootfs() {
+ #rm -fv ${BINS-PATH}/${ROOT_FS_NAME}
+ mkdir -p ${BINS-PATH} ${ELFS-PATH}
+
+ if [ ${IMAGE_FSTYPES} = 'cpio.gz' ]; then
+ cd ${IMAGE_ROOTFS} && find . | cpio -o -H newc | gzip -9 > ${IMAGE_ROOTFS}/ramdisk.image.gz
+ mv ${IMAGE_ROOTFS}/ramdisk.image.gz ${BINS-PATH}/${ROOT_FS_NAME}
+ if [ -d "${TMPDIR}/work/zx298501-zxic-linux-musl/linux-zxic/5.4.154-r0" ]; then
+ cp -arfp ${THISDIR}/files/Makefile_dtb ${B}/Makefile
+ cp -arfp ${THISDIR}/files/fix_rootfs_dts.sh ${B}/
+ ${B}/fix_rootfs_dts.sh ${MACHINE}-${DISTRO} ${TMPDIR}/work-shared/zx298501/kernel-source ${BINS-PATH}
+ oe_runmake -C ${B} S=${TMPDIR}/work/zx298501-zxic-linux-musl/linux-zxic/5.4.154-r0 BINS-PATH=${ELFS-PATH} DTB=${MACHINE}-${DISTRO}.dtb
+ fi
+ else
+ #cp -v ${IMGDEPLOYDIR}/${IMAGE_LINK_NAME}.${IMAGE_FSTYPES} ${BINS-PATH}/${ROOT_FS_NAME}
+ cp -v ${IMGDEPLOYDIR}/rootfs.tgz ${ELFS-PATH}/${ROOT_FS_NAME}.tgz
+ fi
+}
+
+fakeroot do_cleanrootfs () {
+ rm -fv ${BINS-PATH}/${ROOT_FS_NAME}
+ rm -fv ${BINS-PATH}/${USEDATA_FS_NAME}
+ rm -fv ${BINS-PATH}/*.img*
+}
+
+do_product_ini() {
+ mkdir -p ${BINS-PATH}
+ echo "[imagefs]" > ${BINS-PATH}/product.ini
+ echo "mkfs_ubifs=${IMAGEFS_MKUBIFS_ARGS}" >> ${BINS-PATH}/product.ini
+ echo "ubinize=${IMAGEFS_UBINIZE_ARGS}" >> ${BINS-PATH}/product.ini
+}
+
+do_all_flags_bin() {
+ ${BSPDIR}/zxic_code/pub/tools/libflags/flags_tool -f ${BINS-PATH}/all_flags.bin ${FLAGS_ARGS}
+}
+
+fakeroot do_mkubifs(){
+ if [ ${BOOT_CTL} = 'normal' ]; then
+ cp -arfp ${THISDIR}/files/ubinize-cfg.sh ${B}
+ cp -arfp ${BSPDIR}/sources/meta-zxic-custom/conf/distro/include/${USERDATA_UBINIZE_CFG} ${B}
+ mkdir -p ${BINS-PATH}
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/${USEDATA_FS_NAME}" "${B}/${USERDATA_UBINIZE_CFG}" "${USERDATA_UBINIZE_ARGS}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/ap_capuserdata_M22.img" "${B}/${USERDATA_UBINIZE_CFG}" "${LYNQ_M22_USERDATA_UBINIZE_ARGS}"
+fi
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ mkdir -p ${IMAGE_ROOTFS}/etc_ro/
+ cp -v "${BINS-PATH}/${USEDATA_FS_NAME}" ${IMAGE_ROOTFS}/etc_ro/
+ fi
+}
+
+
+fakeroot do_rootfs_squashfs(){
+ cp -arfp ${THISDIR}/files/ubinize-static.sh ${B}
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp -arfp ${THISDIR}/files/squashfs_dm-verity.sh ${B}
+ cp -arfp ${THISDIR}/files/zxic_generate_squashfs_verity ${B}
+ fi
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ touch ${IMAGE_ROOTFS}/etc_ro/dm-verity
+ else
+ rm -fv ${IMAGE_ROOTFS}/etc_ro/dm-verity
+ fi
+
+ rm -fv ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp
+ mksquashfs4 ${IMAGE_ROOTFS} ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp ${ROOTFS_SQUASHFS_ARGS}
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp ${S}/${ROOT_FS_NAME}.unsigned
+ echo "veritysetup and ubinize in do_dm_verity() later ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}"
+ else
+ echo "rootfs squashfs need ubinize-image on nand flash"
+ ${B}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs.img" ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp "${UBINIZE_ARGS}"
+ fi
+ cd ${IMAGE_ROOTFS}/../ && tar -czvf ${IMGDEPLOYDIR}/rootfs.tgz rootfs
+}
+
+fakeroot do_oemfs_squashfs(){
+ cp -arfp ${THISDIR}/files/ubinize-static.sh ${B}
+ cp -arfp ${FS-DIR}/fs/normal/oem/ ${S}/
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp -arfp ${THISDIR}/files/squashfs_dm-verity.sh ${B}
+ cp -arfp ${THISDIR}/files/zxic_generate_squashfs_verity ${B}
+ fi
+
+ rm -fv ${IMGDEPLOYDIR}/oem.squashfs_tmp
+ mksquashfs4 ${S}/oem ${IMGDEPLOYDIR}/oem.squashfs_tmp ${ROOTFS_SQUASHFS_ARGS}
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp ${IMGDEPLOYDIR}/oem.squashfs_tmp ${S}/cap_oem.img.unsigned
+ echo "veritysetup and ubinize in do_dm_verity() later"
+ else
+ echo "oem squashfs need ubinize-image on nand flash"
+ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem.img" ${IMGDEPLOYDIR}/oem.squashfs_tmp "${UBINIZE_ARGS}"
+ mkdir -p ${ELFS-PATH}
+ rm -rf ${IMGDEPLOYDIR}/oem.squashfs_tmp
+ fi
+ mkdir -p ${ELFS-PATH}
+ cd ${S}/oem/../ && tar -czvf ${ELFS-PATH}/oem.tgz oem
+
+}
+
+fakeroot do_oemfs_oemdata(){
+ if [ ${BOOT_CTL} = 'normal' ]; then
+ cp -arfp ${THISDIR}/files/ubinize-cfg.sh ${B}
+ cp -arfp ${BSPDIR}/sources/meta-zxic-custom/conf/distro/include/${OEMDATA_UBINIZE_CFG} ${B}
+ mkdir -p ${BINS-PATH}
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/${OEMDATA_FS_NAME}" "${B}/${OEMDATA_UBINIZE_CFG}" "${USERDATA_UBINIZE_ARGS}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/cap_oemdata_M22.img" "${B}/${OEMDATA_UBINIZE_CFG}" "${LYNQ_M22_USERDATA_UBINIZE_ARGS}"
+fi
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ mkdir -p ${IMAGE_ROOTFS}/etc_ro/
+ cp -v "${BINS-PATH}/${OEMDATA_FS_NAME}" ${IMAGE_ROOTFS}/etc_ro/
+ fi
+}
+
+ROOTFS_POSTPROCESS_COMMAND_remove += 'empty_var_volatile;'
+
+fakeroot do_postinstall(){
+ if [ -f ${IMAGE_ROOTFS}/postinstall.sh ]; then
+ cd ${IMAGE_ROOTFS} && sh postinstall.sh && rm -v ${IMAGE_ROOTFS}/postinstall.sh
+ fi
+}
+
+fakeroot do_ln_musl_ld(){
+ if [ ! -L ${IMAGE_ROOTFS}/lib/ld-linux-aarch64.so.1 ]; then
+ if [ -L ${IMAGE_ROOTFS}/lib/ld-musl-aarch64.so.1 ]; then
+ cd ${IMAGE_ROOTFS}/lib && ln -snf ld-musl-aarch64.so.1 ld-linux-aarch64.so.1
+ fi
+ fi
+}
+
+do_dm_verity(){
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ rm -fv ${BINS-PATH}/ap_caprootfs.dm
+ ${S}/squashfs_dm-verity.sh ${S}/${ROOT_FS_NAME}.unsigned ${S} \
+ ${BINS-PATH}/ap_caprootfs.img.dm ${SIGNIMAGE_PRIVATE_KEY} ${BSPDIR}/tools/SignTool/SignImage
+ ${S}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs.img" ${BINS-PATH}/ap_caprootfs.img.dm "${UBINIZE_ARGS}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
+ ${S}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs_M22.img" ${BINS-PATH}/ap_caprootfs.img.dm "${LYNQ_M22_UBINIZE_ARGS}"
+fi
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ if ${@bb.utils.contains('DISTRO_FEATURES','oemfs','true','false',d)}; then
+ rm -fv ${BINS-PATH}/cap_oem.img.dm
+ ${B}/squashfs_dm-verity.sh ${S}/cap_oem.img.unsigned ${B} \
+ ${BINS-PATH}/cap_oem.img.dm ${SIGNIMAGE_PRIVATE_KEY} ${BSPDIR}/tools/SignTool/SignImage
+ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem.img" ${BINS-PATH}/cap_oem.img.dm "${UBINIZE_ARGS}"
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_START
+if ${@bb.utils.contains('MOBILETEK_NAND_TYPE','M22','true','false',d)}; then
+ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem_M22.img" ${BINS-PATH}/cap_oem.img.dm "${LYNQ_M22_UBINIZE_ARGS}"
+fi
+#LYNQ_MODIFY_ZXW_TASK944_XF.Li_20250123_END
+ fi
+ fi
+}
+
+IMAGE_POSTPROCESS_COMMAND_prepend = ' \
+ do_postinstall; \
+ ${@bb.utils.contains("TCLIBC", "musl", "do_ln_musl_ld;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "selinux_set_labels ;", "", d)} \
+ '
+
+IMAGE_POSTPROCESS_COMMAND += "\
+ ${@bb.utils.contains("USERDATA_FSTYPE", "ubi", "do_mkubifs;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "oemfs", "do_oemfs_squashfs;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "oemfs", "do_oemfs_oemdata;", "", d)} \
+ ${@bb.utils.contains("IMAGE_FSTYPES", "squashfs", "do_rootfs_squashfs;", "", d)} \
+ "
+#xf.li@20240716 add start
+do_oem_config() {
+ LYNQ_INSIDE_VERSION_UCI=" option LYNQ_SW_INSIDE_VERSION '${LYNQ_CONFIG_VERSION}'"
+ eval sed -i 's/^.*LYNQ_SW_INSIDE_VERSION.*$/"${LYNQ_INSIDE_VERSION_UCI}"/' ${IMAGE_ROOTFS}/etc/config/lynq_uci_ro
+ cp -R ${TOPDIR}/prebuilt/rootfs/* ${IMAGE_ROOTFS}/
+ if [ "${MOBILETEK_LOG_ENCRYPT}" = "enable" ]; then
+ touch ${IMAGE_ROOTFS}/etc/syslog_encrypt_flag
+ else
+ rm -rf ${IMAGE_ROOTFS}/etc/syslog_encrypt_flag
+ touch ${IMAGE_ROOTFS}/etc/no_log_encrypt
+ fi
+}
+addtask do_oem_config after do_rootfs before do_image
+#xf.li@20240716 add end
+addtask cprootfs after do_dm_verity before do_build
+addtask do_dm_verity after do_image_complete before do_build
+addtask cleanrootfs after do_clean before do_cleansstate
+
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
new file mode 100755
index 0000000..65d5358
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
@@ -0,0 +1,66 @@
+#inherit externalsrc package
+
+DESCRIPTION = "lynq sim"
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=e1696b147d49d491bcb4da1a57173fff"
+DEPENDS += "libpal gstreamer1.0 glib-2.0 libapn liblynq-log libvendor-ril liblynq-shm libbinder liblynq-uci libsctel"
+#inherit workonsrc
+WORKONSRC = "${TOPDIR}/../src/lynq/lib/liblynq-sim/"
+FILESEXTRAPATHS_prepend :="${TOPDIR}/../src/lynq/lib/:"
+SRC_URI = " \
+ file://liblynq-sim \
+ "
+
+SRC-DIR = "${S}/../liblynq-sim"
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+BB_INCLUDE_ADD = "--sysroot=${STAGING_DIR_HOST}"
+BB_LDFLAGS_ADD = "--sysroot=${STAGING_DIR_HOST} -Wl,--hash-style=gnu"
+#Parameters passed to do_compile()
+EXTRA_OEMAKE = "'RAT_CONFIG_C2K_SUPPORT = ${RAT_CONFIG_C2K_SUPPORT}'\
+ 'MTK_MULTI_SIM_SUPPORT = ${MTK_MULTI_SIM_SUPPORT}'\
+ 'TARGET_PLATFORM = ${TARGET_PLATFORM}'"
+
+FILES_${PN} = "${base_libdir}/*.so \
+ ${base_bindir}\
+ ${base_sbindir} \
+ /etc/dbus-1/system.d/"
+FILES_${PN}-dev = "/test \
+ ${includedir}"
+
+FILES_${PN}-doc = "/doc"
+
+FILES_${PN}-dbg ="${base_bindir}/.debug \
+ ${base_libdir}/.debug \
+ ${base_sbindir}/.debug"
+
+INSANE_SKIP_${PN} += "already-stripped"
+INSANE_SKIP_${PN} += "installed-vs-shipped"
+
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ if [ "${PACKAGE_ARCH}" = "cortexa7hf-vfp-vfpv4-neon" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ elif [ "${PACKAGE_ARCH}" = "cortexa7hf-neon-vfpv4" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ elif [ "${PACKAGE_ARCH}" = "cortexa53hf-neon-fp-armv8" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE -mhard-float -mfpu=neon-fp-armv8 -mfloat-abi=hard -mcpu=cortex-a53 -mtune=cortex-a53"
+ else
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ fi
+}
+
+do_install () {
+ oe_runmake install -C ${SRC-DIR} ROOT=${D}
+
+ if [ -d "${WORKONSRC}" ] ; then
+ install -d ${D}${includedir}/
+ cp -af ${SRC-DIR}/include/libsim ${D}${includedir}/
+ fi
+}
+
+addtask bachclean
+do_bachclean () {
+ oe_runmake clean
+}
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
new file mode 100755
index 0000000..c709cf9
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
@@ -0,0 +1,58 @@
+#inherit externalsrc package
+DESCRIPTION = "libpoweralarm.so "
+SECTION = "base"
+#LICENSE = "Mobiletek""
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=d759532d295a4ec07250edf931caef80"
+DEPENDS += "bootchart liblynq-log libsctel libscrtc libsoftap"
+
+#inherit workonsrc
+WORKONSRC = "${TOPDIR}/../src/lynq/lib/libpoweralarm/"
+
+FILESEXTRAPATHS_prepend :="${TOPDIR}/../src/lynq/lib/:"
+SRC_URI = " \
+ file://libpoweralarm \
+ "
+SRC-DIR = "${S}/../libpoweralarm"
+TARGET_CC_ARCH += "${LDFLAGS}"
+BB_INCLUDE_ADD = "--sysroot=${STAGING_DIR_HOST}"
+BB_LDFLAGS_ADD = "--sysroot=${STAGING_DIR_HOST} -Wl,--hash-style=gnu"
+
+#Parameters passed to do_compile()
+
+FILES_${PN} = "${base_libdir}/*.so \
+ ${base_bindir}\
+ ${base_sbindir}"
+
+
+FILES_${PN}-dev = "/test \
+ ${includedir}"
+
+FILES_${PN}-doc = "/doc"
+
+FILES_${PN}-dbg ="${base_bindir}/.debug \
+ ${base_libdir}/.debug \
+ ${base_sbindir}/.debug"
+
+INSANE_SKIP_${PN} += "already-stripped"
+INSANE_SKIP_${PN} += "installed-vs-shipped"
+
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -Wl,--hash-style=gnu -DTELEPHONYWARE"
+}
+
+do_install () {
+ oe_runmake install -C ${SRC-DIR} ROOT=${D}
+
+ if [ -d "${WORKONSRC}" ] ; then
+ install -d ${D}${includedir}/
+ cp -af ${SRC-DIR}/include/ ${D}${includedir}/
+ fi
+}
+
+addtask bachclean
+do_bachclean () {
+ oe_runmake clean
+}
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
new file mode 100755
index 0000000..a6c8e15
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
@@ -0,0 +1,483 @@
+/**
+ *@file QSER_nw.h
+ *@date 2018-02-22
+ *@author
+ *@brief
+ */
+#ifndef __LYNQ_QSER_NETWORK_H__
+#define __LYNQ_QSER_NETWORK_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t nw_client_handle_type;
+
+
+#define QSER_NW_MODE_NONE 0x00 /**< No network. */
+#define QSER_NW_MODE_GSM 0x01 /**< Include GSM networks. */
+#define QSER_NW_MODE_WCDMA 0x02 /**< Include WCDMA networks. */
+#define QSER_NW_MODE_CDMA 0x04 /**< Include CDMA networks. */
+#define QSER_NW_MODE_EVDO 0x08 /**< Include EVDO networks. */
+#define QSER_NW_MODE_LTE 0x10 /**< Include LTE networks. */
+#define QSER_NW_MODE_TDSCDMA 0x20 /**< Include TDSCDMA networks. */
+
+typedef enum
+{
+ E_QSER_NW_ROAM_STATE_OFF = 0, /**< None, or roaming indicator off. */
+ E_QSER_NW_ROAM_STATE_ON = 1 /**< Roaming indicator on. */
+}E_QSER_NW_ROAM_STATE_TYPE_T;
+
+/** Configures the settings that define the MCM network interface. */
+typedef struct
+{
+ /* Configuration parameters for MCM network registration Network registration details Technology dependent network registration details */
+ uint64_t preferred_nw_mode; /**< Preferred network mode for connections; a bitmask of QSER_NW_MODE_xxxx.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming_pref; /**< Roaming preference.*/
+}QSER_NW_CONFIG_INFO_T;
+
+typedef enum
+{
+ E_QSER_NW_IMS_MODE_OFF = 0, /**< close ims. */
+ E_QSER_NW_IMS_MODE_VOLTE_ENABLE = 1, /**< support volte. */
+}E_QSER_NW_IMS_MODE_TYPE_T;
+
+/** Configures the OOS (out of service) settings that define the MCM network interface. */
+#define QSER_NW_OOS_CFG_TYPE_FAST_SCAN 0x00 /**< fast net scan, only for normal mode */
+#define QSER_NW_OOS_CFG_TYPE_FULL_BAND_SCAN 0x01 /**< full band scan, only for low power mode */
+
+typedef struct
+{
+ /* Configuration parameters for MCM network fast network scan when OOS (out of service) in normal mode*/
+ char enable; /*[0, 1]*/
+ uint16_t time_interval; /*[1, 65535],unit: second, valid when enable equal 1*/
+}QSER_NW_OOS_CONFIG_FAST_SCAN_INFO_T;
+
+typedef struct
+{
+ /* Configuration parameters for MCM network full band network scan when OOS (out of service) in low power mode*/
+ /*t_min,t_step,t_num,t_max all are 0, or all are not 0*/
+ /*if t_min > t_max, time interval will be t_max*/
+ int t_min; /*[0, 65535], unit: second*/
+ int t_step; /*[0, 65535], unit: second*/
+ int t_num; /*[0, 65535]*/
+ int t_max; /*[0, 65535], unit: second*/
+}QSER_NW_OOS_CONFIG_FULL_BAND_SCAN_INFO_T;
+
+
+typedef struct
+{
+ char type; /**< QSER_NW_OOS_CFG_TYPE_xxxx.*/
+ union {
+ QSER_NW_OOS_CONFIG_FAST_SCAN_INFO_T fast_can_info; // 00
+ QSER_NW_OOS_CONFIG_FULL_BAND_SCAN_INFO_T full_band_scan_info; // 01
+ } u;
+}QSER_NW_OOS_CONFIG_INFO_T;
+
+//defined for QSER_NW_EventRegister
+#define NW_IND_VOICE_REG_EVENT_IND_FLAG (1 << 0) /**< msg format : QSER_NW_VOICE_REG_EVENT_IND_T */
+#define NW_IND_DATA_REG_EVENT_IND_FLAG (1 << 1) /**< msg format : QSER_NW_DATA_REG_EVENT_IND_T */
+#define NW_IND_SIGNAL_STRENGTH_EVENT_IND_FLAG (1 << 2) /**< msg format : QSER_NW_SINGNAL_EVENT_IND_T */
+//#define NW_IND_CELL_ACCESS_STATE_CHG_EVENT_IND_FLAG (1 << 3) /**< msg format : QL_MCM_NW_CELL_ACCESS_STATE_EVENT_IND_T */
+//#define NW_IND_NITZ_TIME_UPDATE_EVENT_IND_FLAG (1 << 4) /**< msg format : QL_MCM_NW_NITZ_TIME_EVENT_IND_T */
+#define NW_IND_IMS_REG_EVENT_IND_FLAG (1 << 5) /**< msg format : NULL */
+
+typedef struct
+{
+ char long_eons[512 + 1]; /**< Long EONS.*/
+ char short_eons[512 + 1]; /**< Short EONS.*/
+ char mcc[3 + 1]; /**< Mobile country code.*/
+ char mnc[3 + 1]; /**< Mobile network code.*/
+}QSER_NW_OPERATOR_NAME_INFO_T;
+
+typedef enum
+{
+ E_QSER_NW_RADIO_TECH_TD_SCDMA = 1,
+ E_QSER_NW_RADIO_TECH_GSM = 2, /**< GSM; only supports voice. */
+ E_QSER_NW_RADIO_TECH_HSPAP = 3, /**< HSPA+. */
+ E_QSER_NW_RADIO_TECH_LTE = 4, /**< LTE. */
+ E_QSER_NW_RADIO_TECH_EHRPD = 5, /**< EHRPD. */
+ E_QSER_NW_RADIO_TECH_EVDO_B = 6, /**< EVDO B. */
+ E_QSER_NW_RADIO_TECH_HSPA = 7, /**< HSPA. */
+ E_QSER_NW_RADIO_TECH_HSUPA = 8, /**< HSUPA. */
+ E_QSER_NW_RADIO_TECH_HSDPA = 9, /**< HSDPA. */
+ E_QSER_NW_RADIO_TECH_EVDO_A = 10, /**< EVDO A. */
+ E_QSER_NW_RADIO_TECH_EVDO_0 = 11, /**< EVDO 0. */
+ E_QSER_NW_RADIO_TECH_1xRTT = 12, /**< 1xRTT. */
+ E_QSER_NW_RADIO_TECH_IS95B = 13, /**< IS95B. */
+ E_QSER_NW_RADIO_TECH_IS95A = 14, /**< IS95A. */
+ E_QSER_NW_RADIO_TECH_UMTS = 15, /**< UMTS. */
+ E_QSER_NW_RADIO_TECH_EDGE = 16, /**< EDGE. */
+ E_QSER_NW_RADIO_TECH_GPRS = 17, /**< GPRS. */
+ E_QSER_NW_RADIO_TECH_NONE = 18 /**< No technology selected. */
+}E_QSER_NW_RADIO_TECH_TYPE_T;
+
+
+typedef enum
+{
+ E_QSER_NW_TECH_DOMAIN_NONE = 0, /**< None. */
+ E_QSER_NW_TECH_DOMAIN_3GPP = 1, /**< 3GPP. */
+ E_QSER_NW_TECH_DOMAIN_3GPP2 = 2, /**< 3GPP2. */
+}E_QSER_NW_TECH_DOMAIN_TYPE_T;
+
+typedef enum
+{
+ E_QSER_NW_IMSI_UNKNOWN_HLR_DENY_REASON = 1, /**< IMSI unknown in HLR. */
+ E_QSER_NW_ILLEGAL_MS_DENY_REASON = 2, /**< Illegal MS. */
+ E_QSER_NW_IMSI_UNKNOWN_VLR_DENY_REASON = 3, /**< IMSI unknown in VLR. */
+ E_QSER_NW_IMEI_NOT_ACCEPTED_DENY_REASON = 4, /**< IMEI not accepted. */
+ E_QSER_NW_ILLEGAL_ME_DENY_REASON = 5, /**< Illegal ME. */
+ E_QSER_NW_PLMN_NOT_ALLOWED_DENY_REASON = 6, /**< PLMN not allowed. */
+ E_QSER_NW_LA_NOT_ALLOWED_DENY_REASON = 7, /**< Location area not allowed. */
+ E_QSER_NW_ROAMING_NOT_ALLOWED_LA_DENY_REASON = 8, /**< Roaming not allowed in this location area. */
+ E_QSER_NW_NO_SUITABLE_CELLS_LA_DENY_REASON = 9, /**< No suitable cells in location area. */
+ E_QSER_NW_NETWORK_FAILURE_DENY_REASON = 10, /**< Network failure. */
+ E_QSER_NW_MAC_FAILURE_DENY_REASON = 11, /**< MAC failure. */
+ E_QSER_NW_SYNCH_FAILURE_DENY_REASON = 12, /**< Sync failure. */
+ E_QSER_NW_CONGESTION_DENY_REASON = 13, /**< Congestion. */
+ E_QSER_NW_GSM_AUTHENTICATION_UNACCEPTABLE_DENY_REASON = 14, /**< GSM authentication unacceptable. */
+ E_QSER_NW_NOT_AUTHORIZED_CSG_DENY_REASON = 15, /**< Not authorized in this CSG. */
+ E_QSER_NW_SERVICE_OPTION_NOT_SUPPORTED_DENY_REASON = 16, /**< Service option not supported. */
+ E_QSER_NW_REQ_SERVICE_OPTION_NOT_SUBSCRIBED_DENY_REASON = 17, /**< Requested service option not subscribed. */
+ E_QSER_NW_CALL_CANNOT_BE_IDENTIFIED_DENY_REASON = 18, /**< Call cannot be identified. */
+ E_QSER_NW_SEMANTICALLY_INCORRECT_MSG_DENY_REASON = 19, /**< Semantically incorrect message. */
+ E_QSER_NW_INVALID_MANDATORY_INFO_DENY_REASON = 20, /**< Invalid mandatory information. */
+ E_QSER_NW_MSG_TYPE_NON_EXISTENT_DENY_REASON = 21, /**< Message type non-existent or not implemented. */
+ E_QSER_NW_INFO_ELEMENT_NON_EXISTENT_DENY_REASON = 22, /**< Message type not compatible with the protocol state. */
+ E_QSER_NW_CONDITIONAL_IE_ERR_DENY_REASON = 23, /**< Conditional IE error. */
+ E_QSER_NW_MSG_INCOMPATIBLE_PROTOCOL_STATE_DENY_REASON = 24, /**< Message not compatible with the protocol state. */
+ E_QSER_NW_PROTOCOL_ERROR_DENY_REASON = 25, /**< Unspecified protocol error. */
+}E_QSER_NW_DENY_REASON_TYPE_T;
+
+
+typedef enum
+{
+ E_QSER_NW_SERVICE_NONE = 0x0000, /**< Not registered or no data. */
+ E_QSER_NW_SERVICE_LIMITED = 0x0001, /**< Registered; emergency service only. */
+ E_QSER_NW_SERVICE_FULL = 0x0002, /**< Registered, full service. */
+}E_QSER_NW_SERVICE_TYPE_T;
+
+typedef struct
+{
+ E_QSER_NW_TECH_DOMAIN_TYPE_T tech_domain; /**< Technology, used to determine the structure type tech: 0 -- None, 1 -- 3GPP, 2 -- 3GPP2.*/
+ E_QSER_NW_RADIO_TECH_TYPE_T radio_tech; /**< Radio technology; see #nw_radio_tech_t_v01.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming; /**< 0 -- Off, 1 -- Roaming (3GPP2 has extended values).*/
+ E_QSER_NW_DENY_REASON_TYPE_T deny_reason; /**< Set when registration state is #nw_deny_reason_t_v01.*/
+ E_QSER_NW_SERVICE_TYPE_T registration_state; /**< Registration state.*/
+}QSER_NW_COMMON_REG_INFO_T;
+
+
+typedef struct
+{
+ E_QSER_NW_TECH_DOMAIN_TYPE_T tech_domain; /**< Technology, used to determine the structure type tech: 0 -- None, 1 -- 3GPP, 2 -- 3GPP2.*/
+ E_QSER_NW_RADIO_TECH_TYPE_T radio_tech; /**< Radio technology; see #nw_radio_tech_t_v01.*/
+ char mcc[3+1]; /**< Mobile country code.*/
+ char mnc[3+1]; /**< Mobile network code.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming; /**< 0 -- Off, 1 -- Roaming (3GPP2 has extended values).*/
+ uint8_t forbidden; /**< Forbidden: 0 -- No, 1 -- Yes.*/
+ uint32_t cid; /**< Cell ID for the registered 3GPP system.*/
+ uint16_t lac; /**< Locatin area code for the registered 3GPP system.*/
+ uint16_t psc; /**< Primary scrambling code (WCDMA only); 0 -- None.*/
+ uint16_t tac; /**< Tracking area code information for LTE.*/
+}QSER_NW_3GPP_REG_INFO_T;
+
+
+typedef struct
+{
+ E_QSER_NW_TECH_DOMAIN_TYPE_T tech_domain; /**< Technology, used to determine structure type tech: 0 -- None, 1 -- 3GPP, 2 -- 3GPP2.*/
+ E_QSER_NW_RADIO_TECH_TYPE_T radio_tech; /**< Radio technology; see #nw_radio_tech_t_v01.*/
+ char mcc[3+1]; /**< Mobile country code.*/
+ char mnc[3+1]; /**< Mobile network code.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming; /**< Roaming status; see #nw_roam_state_t_v01.*/
+ uint8_t forbidden; /**< Forbidden: 0 -- No, 1 -- Yes.*/
+ uint8_t inPRL; /**< 0 -- Not in PRL, 1 -- In PRL.*/
+ uint8_t css; /**< Concurrent services supported: 0 -- No, 1 -- Yes.*/
+ uint16_t sid; /**< CDMA system ID.*/
+ uint16_t nid; /**< CDMA network ID.*/
+ uint16_t bsid; /**< Base station ID. @newpagetable */
+}QSER_NW_3GPP2_REG_INFO_T;
+
+/** Gets the status associated with the connection of \<id\>. */
+typedef struct
+{
+ uint8_t voice_registration_valid; /**< Must be set to TRUE if voice_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T voice_registration; /**< Voice registration. */
+
+ uint8_t data_registration_valid; /**< Must be set to TRUE if data_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T data_registration; /**< Data registration. */
+
+ uint8_t voice_registration_details_3gpp_valid; /**< Must be set to TRUE if voice_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T voice_registration_details_3gpp; /**< Voice registration details for 3GPP. */
+
+ uint8_t data_registration_details_3gpp_valid; /**< Must be set to TRUE if data_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T data_registration_details_3gpp; /**< Data registration details for 3GPP. */
+
+ uint8_t voice_registration_details_3gpp2_valid; /**< Must be set to TRUE if voice_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T voice_registration_details_3gpp2; /**< Voice registration details for 3GPP2. */
+
+ uint8_t data_registration_details_3gpp2_valid; /**< Must be set to TRUE if data_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T data_registration_details_3gpp2; /**< Data registration details for 3GPP2. */
+}QSER_NW_REG_STATUS_INFO_T;
+
+typedef enum
+{
+ E_QSER_NW_IMS_SERVICE_NONE = 0x0000, /**< Not registered */
+ E_QSER_NW_IMS_SERVICE_REGISTERED = 0x0001, /**< Registered*/
+}E_QSER_NW_IMS_SERVICE_TYPE_T;
+
+typedef struct
+{
+ E_QSER_NW_IMS_SERVICE_TYPE_T registration_state; /**< Registration state.*/
+}QSER_NW_IMS_REG_STATUS_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates received signal strength. A signed value; -125 or lower indicates no signal.*/
+}QSER_NW_GSM_SIGNAL_INFO_T;
+
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Ec. A signed value; -125 or lower indicates no signal.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+}QSER_NW_WCDMA_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Ec. a signed value; -125 or lower indicates no signal.*/
+ int8_t rscp; /**< RSCP in dBm.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+ int8_t sinr; /**< Measured SINR in dB. @newpagetable */
+}QSER_NW_TDSCDMA_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Ec. A signed value; -125 or lower indicates no signal.*/
+ int8_t rsrq; /**< RSRQ value in dB (signed integer value), as measured by L1. Range: -3 to -20 (-3 equals -3 dB, -20 equals -20 dB).*/
+ int16_t rsrp; /**< Current RSRP in dBm, as measured by L1. Range: -44 to -140 (-44 equals -44 dBm, -140 equals -140 dBm).*/
+ int16_t snr; /**< SNR level as a scaled integer in units of 0.1 dB; e.g., -16 dB has a value of -160 and 24.6 dB has a value of 246.*/
+}QSER_NW_LTE_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Power (AGC) + Ec/Io. A signed value; -125 or lower indicates no signal.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+}QSER_NW_CDMA_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Power (AGC) + Ec/Io. A signed value; -125 or lower indicates no signal.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+ int8_t sinr; /**< SINR level.*/
+ int32_t io; /**< Received IO in dBm. */
+}QSER_NW_HDR_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int16_t ssRsrp; /* SS(Synchronization Signal) reference signal received power, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [44, 140], INT_MAX means invalid/unreported.*/
+ int16_t ssRsrq; /* SS reference signal received quality, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [3, 20], INT_MAX means invalid/unreported.*/
+ int16_t ssSinr; /* SS signal-to-noise and interference ratio.
+ * Reference: 3GPP TS 38.215 section 5.1.*, 3GPP TS 38.133 section 10.1.16.1.
+ * Range [-23, 40], INT_MAX means invalid/unreported.*/
+ int16_t csiRsrp; /* CSI reference signal received power, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [44, 140], INT_MAX means invalid/unreported.*/
+ int16_t csiRsrq; /* CSI reference signal received quality, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [3, 20], INT_MAX means invalid/unreported.*/
+ int16_t csiSinr; /* CSI signal-to-noise and interference ratio.
+ * Reference: 3GPP TS 138.215 section 5.1.*, 3GPP TS 38.133 section 10.1.16.1.
+ * Range [-23, 40], INT_MAX means invalid/unreported.*/
+}QSER_NW_NR_SIGNAL_INFO_T;
+
+
+/** Gets signal strength information. */
+typedef struct
+{
+ uint8_t gsm_sig_info_valid; /**< Must be set to TRUE if gsm_sig_info is being passed. */
+ QSER_NW_GSM_SIGNAL_INFO_T gsm_sig_info; /**< GSM signal information. */
+ uint8_t wcdma_sig_info_valid; /**< Must be set to TRUE if wcdma_sig_info is being passed. */
+ QSER_NW_WCDMA_SIGNAL_INFO_T wcdma_sig_info; /**< WCDMA signal information. */
+ uint8_t tdscdma_sig_info_valid; /**< Must be set to TRUE if tdscdma_sig_info is being passed. */
+ QSER_NW_TDSCDMA_SIGNAL_INFO_T tdscdma_sig_info; /**< TDSCDMA signal information. */
+ uint8_t lte_sig_info_valid; /**< Must be set to TRUE if lte_sig_info is being passed. */
+ QSER_NW_LTE_SIGNAL_INFO_T lte_sig_info; /**< LTE signal information. */
+ uint8_t cdma_sig_info_valid; /**< Must be set to TRUE if cdma_sig_info is being passed. */
+ QSER_NW_CDMA_SIGNAL_INFO_T cdma_sig_info; /**< CDMA signal information. */
+ uint8_t hdr_sig_info_valid; /**< Must be set to TRUE if hdr_sig_info is being passed. */
+ QSER_NW_HDR_SIGNAL_INFO_T hdr_sig_info; /**< HDR signal information. */
+ uint8_t nr_sig_info_valid;
+ QSER_NW_NR_SIGNAL_INFO_T nr_sig_info;
+}QSER_NW_SIGNAL_STRENGTH_INFO_T;
+
+
+
+
+
+/* @bridef Callback function registered to QSER_NW_AddRxMsgHandler
+ * map of ind_flag and ind_msg_buf as bellow :
+ * NW_IND_VOICE_REG_EVENT_IND_FLAG : QSER_NW_VOICE_REG_EVENT_IND_T
+ * NW_IND_DATA_REG_EVENT_IND_FLAG : QSER_NW_DATA_REG_EVENT_IND_T
+ * NW_IND_SIGNAL_STRENGTH_EVENT_IND_FLAG : QSER_NW_SINGNAL_EVENT_IND_T
+ * NW_IND_CELL_ACCESS_STATE_CHG_EVENT_IND_FLAG : QSER_NW_CELL_ACCESS_STATE_EVENT_IND_T
+ * NW_IND_NITZ_TIME_UPDATE_EVENT_IND_FLAG : QSER_NW_NITZ_TIME_EVENT_IND_T
+ * NW_IND_IMS_REG_EVENT_IND_FLAG : NULL
+ * */
+typedef void (*QSER_NW_RxMsgHandlerFunc_t)(
+ nw_client_handle_type h_nw,
+ uint32_t ind_flag,
+ void *ind_msg_buf,
+ uint32_t ind_msg_len,
+ void *contextPtr
+);
+
+
+/** Indication message; Indication for the corresponding registered event flag NW_IND_VOICE_REG_EVENT_IND_FLAG */
+typedef struct {
+
+ uint8_t registration_valid; /**< Must be set to TRUE if voice_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T registration; /**< Voice registration. */
+
+ uint8_t registration_details_3gpp_valid; /**< Must be set to TRUE if voice_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T registration_details_3gpp; /**< Voice registration details for 3GPP. */
+
+ uint8_t registration_details_3gpp2_valid; /**< Must be set to TRUE if voice_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T registration_details_3gpp2; /**< Voice registration details for 3GPP2. */
+}QSER_NW_VOICE_REG_EVENT_IND_T;
+
+/** Indication message; Indication for the corresponding registered event flag NW_IND_DATA_REG_EVENT_IND_FLAG */
+typedef struct {
+
+ uint8_t registration_valid; /**< Must be set to TRUE if data_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T registration; /**< Data registration. */
+
+ uint8_t registration_details_3gpp_valid; /**< Must be set to TRUE if data_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T registration_details_3gpp; /**< Data registration details for 3GPP. */
+
+ uint8_t registration_details_3gpp2_valid; /**< Must be set to TRUE if data_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T registration_details_3gpp2; /**< Data registration details for 3GPP2. */
+}QSER_NW_DATA_REG_EVENT_IND_T;
+
+
+/** Indication message; Indication for the corresponding registered event flag NW_IND_SIGNAL_STRENGTH_EVENT_IND_FLAG */
+typedef struct {
+ uint8_t gsm_sig_info_valid; /**< Must be set to TRUE if gsm_sig_info is being passed. */
+ QSER_NW_GSM_SIGNAL_INFO_T gsm_sig_info; /**< GSM singal information. */
+
+ uint8_t wcdma_sig_info_valid; /**< Must be set to TRUE if wcdma_sig_info is being passed. */
+ QSER_NW_WCDMA_SIGNAL_INFO_T wcdma_sig_info; /**< WCDMA singal information. */
+
+ uint8_t tdscdma_sig_info_valid; /**< Must be set to TRUE if tdscdma_sig_info is being passed. */
+ QSER_NW_TDSCDMA_SIGNAL_INFO_T tdscdma_sig_info; /**< TDSCDMA singal information. */
+
+ uint8_t lte_sig_info_valid; /**< Must be set to TRUE if lte_sig_info is being passed. */
+ QSER_NW_LTE_SIGNAL_INFO_T lte_sig_info; /**< LTE singal information. */
+
+ uint8_t cdma_sig_info_valid; /**< Must be set to TRUE if cdma_sig_info is being passed. */
+ QSER_NW_CDMA_SIGNAL_INFO_T cdma_sig_info; /**< CDMA singal information. */
+
+ uint8_t hdr_sig_info_valid; /**< Must be set to TRUE if hdr_sig_info is being passed. */
+ QSER_NW_HDR_SIGNAL_INFO_T hdr_sig_info; /**< HDR singal information. */
+
+ uint8_t nr_sig_info_valid;
+ QSER_NW_NR_SIGNAL_INFO_T nr_sig_info;
+}QSER_NW_SINGNAL_EVENT_IND_T;
+
+typedef enum
+{
+ E_QSER_NW_RF_MODE_CFUN_0 = 0, /**< CFUN 0. */
+ E_QSER_NW_RF_MODE_CFUN_1 = 1, /**< CFUN 1. */
+ E_QSER_NW_RF_MODE_FLIGHT = 4, /**< Flight Mode, CFUN 4. */
+}E_QSER_NW_RF_MODE_TYPE_T;
+
+int qser_nw_client_init(nw_client_handle_type *ph_nw);
+
+int qser_nw_client_deinit(nw_client_handle_type h_nw);
+
+int qser_nw_set_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_get_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_set_ims_enable
+(
+ nw_client_handle_type h_nw,
+ E_QSER_NW_IMS_MODE_TYPE_T ims_mode
+);
+
+int qser_nw_set_oos_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_OOS_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_get_oos_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_OOS_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_event_register
+(
+ nw_client_handle_type h_nw,
+ uint32_t bitmask // bit OR of NW_IND_xxxx_EVENT_ON
+);
+
+int qser_nw_get_operator_name
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_OPERATOR_NAME_INFO_T *pt_info //You should malloc this or may cause stack overflow
+);
+
+int qser_nw_get_reg_status
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_REG_STATUS_INFO_T *pt_info
+);
+
+int qser_nw_get_ims_reg_status
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_IMS_REG_STATUS_INFO_T *pt_info
+);
+
+int qser_nw_get_signal_strength
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_SIGNAL_STRENGTH_INFO_T *pt_info
+);
+
+int qser_nw_add_rx_msg_handler
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_RxMsgHandlerFunc_t handlerPtr,
+ void* contextPtr
+);
+
+int qser_nw_set_rf_mode
+(
+ nw_client_handle_type h_nw,
+ E_QSER_NW_RF_MODE_TYPE_T rf_mode
+);
+
+int qser_nw_get_rf_mode
+(
+ nw_client_handle_type h_nw,
+ E_QSER_NW_RF_MODE_TYPE_T *rf_mode
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif//__QSER_NW_H__
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
new file mode 100755
index 0000000..e9730f1
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
@@ -0,0 +1,488 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <pthread.h>
+#include <unistd.h>
+#include <dlfcn.h>
+#include <stdint.h>
+
+#include"lynq-qser-voice-demo.h"
+
+typedef struct
+{
+ int cmdIdx;
+ char *funcName;
+} st_api_test_case;
+
+//for server test
+st_api_test_case at_api_testcases[] =
+{
+ {0, "print_help"},
+ {1, "qser_voice_call_start"},
+ {2, "qser_voice_call_end"},
+ {3, "qser_voice_call_answer"},
+ {4, "qser_voice_set_speech_volume"},
+ {5, "qser_voice_get_speech_volume"},
+ {6, "qser_voice_set_dtmf"},
+#ifdef ECALL_SUPPORT
+ {7, "qser_voice_set_test_num"},
+ {8, "qser_voice_fast_ecall"},
+#endif
+ {9, "qser_voice_set_audio_mode"},
+ {10, "qser_voice_get_audio_mode"},
+ {11, "qser_voice_set_mic_volume"},
+ {12, "qser_voice_get_mic_volume"},
+ {-1, NULL}
+};
+
+typedef uint32_t voice_client_handle_type;
+
+
+int (*qser_voice_call_client_init)(voice_client_handle_type *ph_voice);
+int (*qser_voice_call_client_deinit)(voice_client_handle_type );
+int (*qser_voice_call_addstatehandler)(voice_client_handle_type h_voice,
+ QSER_VoiceCall_StateHandlerFunc_t handlerPtr,
+ void *contextPtr);
+
+int (*qser_voice_call_removestatehandle)(voice_client_handle_type );
+int (*qser_voice_call_start)(voice_client_handle_type h_voice,
+ E_QSER_VCALL_ID_T simId,
+ char *phone_number, int *call_id);
+
+int (*qser_voice_call_end)(voice_client_handle_type ,int );
+int (*qser_voice_call_answer)(voice_client_handle_type ,int );
+int (*qser_voice_set_speech_volume)(const int volume);
+int (*qser_voice_get_speech_volume)(int *volume);
+int (*qser_voice_set_dtmf)(const char callnum);
+int (*qser_voice_set_audio_mode)(const int audio_mode);
+int (*qser_voice_get_audio_mode)(int* audio_mode);
+
+int (*qser_voice_set_mic_volume)(const int volume);
+int (*qser_voice_get_mic_volume)(int *volume);
+
+
+#ifdef ECALL_SUPPORT
+int (*qser_voice_set_test_num)(voice_client_handle_type* h_voice,E_QSER_VOICE_ECALL_SET_TYPE_T type, const char *test_num, int test_num_length);
+int (*qser_voice_fast_ecall)(voice_client_handle_type* h_voice,
+ int *call_id,
+ E_QSER_VOICE_ECALL_CATEGORY_T cat,
+ E_QSER_VOICE_ECALL_VARIANT_T variant,
+ const char *addr,
+ int addr_length,
+ const unsigned char *msd_data,
+ int msd_length); //msd_length should <= QSER_MSD_MAX_LENGTH
+int (*qser_voice_set_msd)(int callid, const unsigned char *msd_data, int msd_length); //msd_length should <= QSER_MSD_MAX_LENGTH
+int (*qser_voice_add_ecall_indhandler)(voice_client_handle_type* h_voice,
+ QSER_ECall_IndHandlerFunc_t handlerPtr,
+ void* contextPtr);
+
+static void yk_voice_ecall_cb_func(int callid, E_QSER_VOICE_ECALL_INDICATION_T ind, void* contextPtr)
+{
+ unsigned char msd_data[QSER_MSD_MAX_LENGTH]={1,1,2,2,3,3,4,4};
+
+ printf("######### Call id=%d, event=%d! ######\n", callid, ind);
+
+ if(ind == E_QSER_VOICE_ECALL_IND_SENDING_START_IN_VOICE || ind == E_QSER_VOICE_ECALL_IND_PSAP_CALLBACK_START)
+ {
+ /*customer should construct msd including GPS data, here use msd_data for illustrate,*/
+ qser_voice_set_msd(callid,msd_data,8);
+ }
+}
+
+#endif
+
+
+void *dlHandle_call = NULL;
+
+static void yk_voice_call_cb_func(int call_id,
+ char* phone_num,
+ qser_voice_call_state_t state,
+ void *contextPtr)
+{
+ char *call_state[] = {"INCOMING", "DIALING", "ALERTING", "ACTIVE", "HOLDING", "END", "WAITING"};
+
+ printf("######### Call id=%d, PhoneNum:%s, event=%s! ######\n", call_id, phone_num, call_state[state]);
+}
+
+
+
+void print_help(void)
+{
+ int i;
+ printf("Supported test cases:\n");
+ for(i = 0; ; i++)
+ {
+ if(at_api_testcases[i].cmdIdx == -1)
+ {
+ break;
+ }
+ printf("%d:\t%s\n", at_api_testcases[i].cmdIdx, at_api_testcases[i].funcName);
+ }
+}
+
+
+
+int main(int argc, char const *argv[])
+{
+ int cmdIdx = 0;
+ int ret = 0;
+ int voice_call_id = 0;
+ voice_client_handle_type h_voice = 0;
+ int audio_mode = 0;
+
+ const char *lynqLibPath_Call = "/lib/liblynq-qser-voice.so";
+ dlHandle_call = dlopen(lynqLibPath_Call, RTLD_NOW);
+ if (dlHandle_call == NULL)
+ {
+ printf("dlopen dlHandle_call failed: %s\n", dlerror());
+ exit(EXIT_FAILURE);
+ }
+
+ qser_voice_call_client_init = (int(*)(voice_client_handle_type *ph_voice))dlsym(dlHandle_call, "qser_voice_call_client_init");
+ if(qser_voice_call_client_init == NULL)
+ {
+ printf("qser_voice_call_client_init not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_addstatehandler = (int(*)(voice_client_handle_type h_voice,
+ QSER_VoiceCall_StateHandlerFunc_t handlerPtr,
+ void *contextPtr))dlsym(dlHandle_call,"qser_voice_call_addstatehandler");
+ if(qser_voice_call_addstatehandler == NULL)
+ {
+ printf("qser_voice_call_addstatehandler not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_answer = (int(*)(voice_client_handle_type,int ))dlsym(dlHandle_call,"qser_voice_call_answer");
+ if(qser_voice_call_answer == NULL)
+ {
+ printf("qser_voice_call_answer not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_start = (int(*)(voice_client_handle_type h_voice,E_QSER_VCALL_ID_T simId,
+ char *phone_number, int *call_id))dlsym(dlHandle_call,"qser_voice_call_start");
+ if(qser_voice_call_start == NULL)
+ {
+ printf("qser_voice_call_start not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_end = (int(*)(voice_client_handle_type ,int))dlsym(dlHandle_call,"qser_voice_call_end");
+ if(qser_voice_call_end == NULL)
+ {
+ printf("qser_voice_call_end not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+
+ qser_voice_call_client_deinit = (int (*)(voice_client_handle_type h_voice))dlsym(dlHandle_call,"qser_voice_call_client_deinit");
+ if(qser_voice_call_client_deinit == NULL)
+ {
+ printf("qser_voice_call_client_deinit not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_removestatehandle = (int (*)(voice_client_handle_type))dlsym(dlHandle_call,"qser_voice_call_removestatehandle");
+ if(qser_voice_call_removestatehandle == NULL)
+ {
+ printf("qser_voice_call_removestatehandle not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_speech_volume = (int (*)(const int ))dlsym(dlHandle_call,"qser_voice_set_speech_volume");
+ if(qser_voice_set_speech_volume == NULL)
+ {
+ printf("qser_voice_set_speech_volume not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_get_speech_volume = (int (*)(int* ))dlsym(dlHandle_call,"qser_voice_get_speech_volume");
+ if(qser_voice_get_speech_volume == NULL)
+ {
+ printf("qser_voice_get_speech_volume not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_dtmf = (int (*)(const char ))dlsym(dlHandle_call,"qser_voice_set_dtmf");
+ if(qser_voice_set_dtmf == NULL)
+ {
+ printf("qser_voice_set_dtmf not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+#ifdef ECALL_SUPPORT
+ qser_voice_fast_ecall = (int (*)(voice_client_handle_type*, int*, E_QSER_VOICE_ECALL_CATEGORY_T, E_QSER_VOICE_ECALL_VARIANT_T, const char*, int, const unsigned char*, int))dlsym(dlHandle_call,"qser_voice_fast_ecall");
+ if(qser_voice_fast_ecall == NULL)
+ {
+ printf("qser_voice_fast_ecall not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_test_num = (int (*)(voice_client_handle_type*, E_QSER_VOICE_ECALL_SET_TYPE_T, const char* , int))dlsym(dlHandle_call,"qser_voice_set_test_num");
+ if(qser_voice_set_test_num == NULL)
+ {
+ printf("qser_voice_set_test_num not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_msd = (int (*)(int , const unsigned char *, int))dlsym(dlHandle_call,"qser_voice_set_msd");
+ if(qser_voice_set_msd == NULL)
+ {
+ printf("qser_voice_set_msd not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_add_ecall_indhandler = (int (*)(voice_client_handle_type* h_voice, QSER_ECall_IndHandlerFunc_t, void*))dlsym(dlHandle_call,"qser_voice_add_ecall_indhandler");
+ if(qser_voice_add_ecall_indhandler == NULL)
+ {
+ printf("qser_voice_add_ecall_indhandler not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+#endif
+
+ qser_voice_set_audio_mode = (int(*)(const int audio_mode))dlsym(dlHandle_call, "qser_voice_set_audio_mode");
+ if(qser_voice_set_audio_mode == NULL)
+ {
+ printf("qser_voice_set_audio_mode not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+
+ qser_voice_get_audio_mode = (int(*)(int* audio_mode))dlsym(dlHandle_call, "qser_voice_get_audio_mode");
+ if(qser_voice_get_audio_mode == NULL)
+ {
+ printf("qser_voice_get_audio_mode not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+ qser_voice_set_mic_volume = (int (*)(const int ))dlsym(dlHandle_call,"qser_voice_set_mic_volume");
+ if(qser_voice_set_mic_volume == NULL)
+ {
+ printf("qser_voice_set_mic_volume not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_get_mic_volume = (int (*)(int* ))dlsym(dlHandle_call,"qser_voice_get_mic_volume");
+ if(qser_voice_get_mic_volume == NULL)
+ {
+ printf("qser_voice_get_mic_volume not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+
+ ret = qser_voice_call_client_init(&h_voice);
+ if(ret != 0 )
+ {
+ printf("qser_voice_call_client_init FAIL\n");
+ return -1;
+ }
+
+ ret = qser_voice_call_addstatehandler(h_voice, yk_voice_call_cb_func, &voice_call_id);
+ if(ret != 0)
+ {
+ printf("qser_voice_call_addstatehandler FAIL\n");
+ return -1;
+ }
+
+#ifdef ECALL_SUPPORT
+ ret = qser_voice_add_ecall_indhandler(&h_voice, yk_voice_ecall_cb_func, NULL);
+ if(ret != 0)
+ {
+ printf("qser_voice_add_ecall_indhandler FAIL\n");
+ return -1;
+ }
+#endif
+
+ print_help();
+ while(1)
+ {
+ printf("\nplease input cmd index(-1 exit): ");
+ scanf("%d", &cmdIdx);
+ if(cmdIdx == -1)
+ {
+ break;
+ }
+
+ switch(cmdIdx)
+ {
+ //"print_help
+ case 0:
+ print_help();
+ break;
+
+ //"qser_voice_call_start"
+ case 1:
+ {
+ char PhoneNum[32] = {0};
+
+ printf("please input dest phone number: \n");
+ scanf("%s", PhoneNum);
+
+ ret = qser_voice_call_start(h_voice, E_QSER_VCALL_EXTERNAL_SLOT_1, PhoneNum, &voice_call_id);
+ printf("qser_voice_call_start ret = %d, with voice_call_id=%d\n", ret, voice_call_id);
+ break;
+ }
+
+ //"qser_voice_call_end"
+ case 2:
+ {
+ int call_id = -1;
+ printf("please input end call id: \n");
+ scanf("%d", &call_id);
+ ret = qser_voice_call_end(h_voice, call_id);
+ printf(" ret = %d\n", ret);
+ break;
+ }
+
+ //"qser_voice_call_answer"
+ case 3:
+ {
+ int call_id = -1;
+ printf(" please input answer call id\n");
+ scanf("%d", &call_id);
+ ret = qser_voice_call_answer(h_voice, call_id);
+ printf(" ret = %d\n", ret);
+ break;
+ }
+
+ case 4:
+ {
+ int volume = 0;
+ printf("Please set speech volume:0-5 level\n");
+ scanf("%d",&volume);
+ ret = qser_voice_set_speech_volume(volume);
+ printf("ret is %d\n",ret);
+ break;
+
+ }
+
+ case 5:
+ {
+ int volume = -1;
+ printf("Enter get speech volume\n");
+ ret = qser_voice_get_speech_volume(&volume);
+ printf("ret is %d,get volume is %d\n",ret,volume);
+ break;
+
+ }
+ case 6:
+ {
+
+ int ret;
+ char inputChar;
+
+ printf("Enter set dtmf\n");
+ scanf(" %c", &inputChar);
+ printf("inputChar is %c\n", inputChar);
+ ret = qser_voice_set_dtmf(inputChar);
+
+ if (ret != 0)
+ {
+ printf("qser set voice dtmf failed\n");
+ return -1;
+ }
+ break;
+ }
+#ifdef ECALL_SUPPORT
+ case 7:
+ {
+ char PhoneNum[32] = {0};
+ printf("please input test phone number(input null means \"\"): \n");
+ scanf("%s", PhoneNum);
+ if(0 == strcmp(PhoneNum, "null"))
+ {
+ PhoneNum[0]='\0';
+ }
+ ret = qser_voice_set_test_num(&h_voice, E_QSER_VOICE_ECALL_SET_NUMBER, PhoneNum, strlen(PhoneNum)+1);
+ printf("qser_voice_set_test_num ret = %d\n", ret);
+ break;
+ }
+ case 8:
+ {
+ int call_id = -1;
+ int cat;
+ int var;
+ int length;
+ unsigned char msd[QSER_MSD_MAX_LENGTH]={0};
+
+ printf("please input ecall cat: 0 manual, 1 auto\n");
+ scanf("%d", &cat);
+ printf("please input ecall type: 0 test, 1 emergency\n");
+ scanf("%d", &var);
+ printf("please input msd content length (max length is 140)\n");
+ scanf("%d", &length);
+ printf("please input %d unsigned char (0-255):\n", length);
+ for (int i = 0; i < length; i++) {
+ scanf("%hhu", &msd[i]);
+ }
+ ret = qser_voice_fast_ecall(&h_voice, &call_id, (E_QSER_VOICE_ECALL_CATEGORY_T) cat, (E_QSER_VOICE_ECALL_VARIANT_T) var, "null",5,msd,length);
+ printf("qser_voice_fast_ecall ret = %d, call id is %d\n", ret, call_id);
+ break;
+ }
+#endif
+ case 9:
+ {
+
+ printf("please input voice audio mode: 0 codec, 1 rtp\n");
+ scanf("%d", &audio_mode);
+ ret = qser_voice_set_audio_mode(audio_mode);
+ printf("qser_voice_set_audio_mode ret = %d, audio_mode is %d\n", ret, audio_mode);
+ break;
+ }
+ case 10:
+ {
+ ret = qser_voice_get_audio_mode(&audio_mode);
+ printf("qser_voice_get_audio_mode ret = %d, audio_mode is %d\n", ret, audio_mode);
+ break;
+ }
+ case 11:
+ {
+ int volume = 0;
+ printf("Please set mic volume:0-5 level\n");
+ scanf("%d",&volume);
+ ret = qser_voice_set_mic_volume(volume);
+ printf("ret is %d\n",ret);
+ break;
+
+ }
+
+ case 12:
+ {
+ int volume = -1;
+ printf("Enter get mic volume\n");
+ ret = qser_voice_get_mic_volume(&volume);
+ printf("ret is %d,get volume is %d\n",ret,volume);
+ break;
+ }
+ default:
+ print_help();
+ break;
+ }
+
+ }
+
+ ret = qser_voice_call_removestatehandle(h_voice);
+ if(ret != 0 && ret != 1)
+ {
+ printf("qser_voice_call_removestatehandle FAIL!!!\n");
+ return -1;
+ }
+ printf("qser_voice_call_removestatehandle ret = %d\n", ret);
+
+
+ ret = qser_voice_call_client_deinit(h_voice);
+ if(ret != 0)
+ {
+ printf("qser_voice_call_client_deinit FAIL\n");
+ return -1;
+ }
+ printf("qser_voice_call_client_deinit ret = %d, with h_voice=%d\n", ret, h_voice);
+
+ return 0;
+
+
+}
+
+
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
new file mode 100755
index 0000000..a3e6499
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
@@ -0,0 +1,791 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+//#include "voice_ipc.h"
+
+#define _USE_VOICE_BUFFER
+#include "voice_lib.h"
+#include <fcntl.h>
+#include <signal.h>
+#include <semaphore.h>
+#include <sys/types.h>
+#include <pthread.h>
+#include <log/log.h>
+#include <time.h>
+#define LOG_TAG "VB_DEMO"
+
+
+
+/*command max len*/
+#define VOICE_CMD_MAX_LEN 64
+
+#define EXIT_CMD_STOP "stop\n"
+#define EXIT_CMD_Q "q\n"
+#define EXIT_CMD_EXIT "exit\n"
+
+#define REQ_VOICE_BUFFER_TEST_START "voice_buffer_test_start"
+#define REQ_VOICE_BUFFER_TEST_STOP "voice_buffer_test_stop"
+#define REQ_VOICE_BUFFER_LOOP_TEST_START "voice_buffer_loop_test_start"
+#define REQ_VOICE_BUFFER_LOOP_TEST_STOP "voice_buffer_loop_test_stop"
+#define REQ_VOICE_BUFFER_RTP_TEST_START "voice_buffer_rtp_test_start"
+#define REQ_VOICE_BUFFER_RTP_TEST_STOP "voice_buffer_rtp_test_stop"
+
+
+
+#define VBUFFER_TX_FILE_NAME "/mnt/userdata/tx.pcm"
+#define VBUFFER_RX_FILE_NAME "/mnt/userdata/rx.pcm"
+#define VBUFFER_TX16_FILE_NAME "/mnt/userdata/tx16.pcm"
+#define VBUFFER_RX16_FILE_NAME "/mnt/userdata/rx16.pcm"
+
+
+
+#define VB_MAX_INT 0x7fffffff
+#define VB_MIN_INT 0
+#define VB_INT_OVERFLOW(x) if((x < VB_MIN_INT)||(x > VB_MAX_INT)) x = 0;
+
+#define RX_FILE_LEN_MAX 0x100000
+
+
+
+typedef int (vb_thread_proc)(void*);
+struct vbuf_info_t
+{
+ int fd;
+ pthread_t rx_test_thread;
+ pthread_t tx_test_thread;
+ pthread_t loop_test_thread;
+ int quit;
+ char *tx_buf;
+ char *rx_buf;
+ int buf_size;
+ char *tx_filename;
+ char *rx_filename;
+ FILE *tx_file;
+ FILE *rx_file;
+ int tx_filesize;
+ int rx_filesize;
+ int fs;
+};
+
+static struct vbuf_info_t vbuf_rec;
+
+static void printUsage(const char *Opt)
+{
+ printf("Usage: %s\n", Opt);
+
+ printf("voice_buffer_test_start value: 8000,16000\n");
+ printf("voice_buffer_test_stop no value input\n");
+ printf("voice_buffer_loop_test_start value: 8000,16000\n");
+ printf("voice_buffer_loop_test_stop no value input\n");
+ printf("\n");
+}
+
+static int vbuffer_start_flag = 0;
+static int tx_optcount = 0;
+static int rx_optcount = 0;
+static int first_rderr_flag = 0;
+static int first_wrerr_flag = 0;
+
+static pthread_mutex_t s_vb_demo_mtx = PTHREAD_MUTEX_INITIALIZER;
+
+static int vb_close_fd_release_buf()
+{
+ int ret=0;
+ if(vbuf_rec.fd>0)
+ {
+ ret = voice_buffer_close(vbuf_rec.fd);
+ if(ret != 0)
+ {
+ RLOGE("%s : vb close fail ret is %d\n",__func__,ret);
+ }
+ vbuf_rec.fd = -1;
+ }
+
+
+ if(vbuf_rec.rx_buf)
+ {
+ free(vbuf_rec.rx_buf);
+ vbuf_rec.rx_buf = NULL;
+ }
+
+ if(vbuf_rec.tx_buf)
+ {
+ free(vbuf_rec.tx_buf);
+ vbuf_rec.tx_buf = NULL;
+ }
+
+ vbuffer_start_flag = 0;
+ RLOGD("close buf fd and release buf end\n");
+ return ret;
+}
+
+
+
+//whole rx path
+static int vb_rx_test_thread_func(void *arg)
+{
+ int ret;
+
+ char* buf = vbuf_rec.rx_buf;
+ int size = vbuf_rec.buf_size;
+ int bytes_read = 0;
+ int r_size;
+
+
+ RLOGD( "%s: start size=%d! \n",__func__,size);
+ memset (buf,0, size);
+
+ while (!vbuf_rec.quit)
+ {
+ rx_optcount ++;
+ VB_INT_OVERFLOW(rx_optcount);
+ if((rx_optcount%1000) == 0){
+ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+
+ }
+ else if(rx_optcount == 1000000){
+ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+ rx_optcount = 0;
+
+ }
+
+ //read form ps
+ r_size = voice_buffer_read(vbuf_rec.fd, buf, size);
+ if(r_size <= 0)
+ {
+ first_rderr_flag++;
+ VB_INT_OVERFLOW(first_rderr_flag);
+ continue ;
+ }
+ else{
+ first_rderr_flag = 0;
+
+ }
+
+ if(vbuf_rec.rx_file != NULL)
+ {
+ r_size = fwrite(buf, 1,size, vbuf_rec.rx_file);
+
+ if (r_size != size) {
+ //printf("Error fwrite size not eq,r_size=%d,size=%d\n",r_size,size);
+ }
+ else{
+
+ bytes_read += size;
+ if(bytes_read >= vbuf_rec.rx_filesize){
+ fseek(vbuf_rec.rx_file, 0, SEEK_SET);
+ bytes_read = 0;
+ RLOGD("fwrite over write maxsize(%d)!!!\n",vbuf_rec.rx_filesize);
+
+ }
+ }
+ }
+
+
+ }
+
+ return 0;
+}
+
+static int vb_tx_test_thread_func(void *arg)
+{
+ int ret;
+ int num_read;
+
+
+ char* buf = vbuf_rec.tx_buf;
+
+ int size = vbuf_rec.buf_size;
+ int w_size;
+
+ RLOGD("%s: start size=%d! \n",__func__,size);
+
+
+ memset(buf, 0,size);
+ while (!vbuf_rec.quit)
+ {
+
+ if(vbuf_rec.tx_file != NULL)
+ {
+
+ num_read = fread(buf,1,size, vbuf_rec.tx_file);
+
+ if (num_read != size) {
+ //printf("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
+ }
+ if (num_read <= 0) {
+ RLOGD("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
+ fseek(vbuf_rec.tx_file, 0, SEEK_SET);
+ }
+ }
+ tx_optcount ++;
+ VB_INT_OVERFLOW(tx_optcount);
+
+ w_size = voice_buffer_write(vbuf_rec.fd, buf, size);
+ if(w_size <= 0)
+ {
+ first_wrerr_flag++;
+
+ VB_INT_OVERFLOW(first_wrerr_flag);
+
+ continue;
+ }
+ else{
+ first_wrerr_flag = 0;
+
+ }
+
+ }
+ return 0;
+}
+
+
+static int vb_thread_create( const char *name,pthread_t *thread_t, vb_thread_proc *proc,
+ int stack_size, unsigned priority,void *arg )
+{
+ pthread_attr_t thread_attr;
+ int ret;
+ int default_size;
+
+ struct sched_param param;
+ int policy = SCHED_FIFO;
+
+ RLOGD("%s: start! \n",__func__);
+
+ /* Init thread attributes */
+ pthread_attr_init(&thread_attr);
+ /* Create the thread. */
+
+ ret = pthread_create( thread_t, &thread_attr,proc, arg);
+ if (ret != 0)
+ {
+ RLOGE("%s: pthread_create fail,ret=%d! \n",__func__,ret);
+
+ pthread_attr_destroy(&thread_attr);
+ return ret;
+ }
+
+ pthread_attr_getstacksize(&thread_attr, &default_size);
+ RLOGD("%s: pthread_attr_getstacksize(%d)! \n",__func__,default_size);
+
+ pthread_attr_destroy(&thread_attr);
+
+ RLOGD("%s: end \n",__func__);
+ return 0;
+}
+
+
+int voice_buffer_stream_test_stop(void);
+
+int voice_buffer_stream_test_start(int fs)
+{
+ int ret = 0;
+ int buf_size = 320;
+ tx_optcount = 0;
+ rx_optcount = 0;
+ int* buf_int;
+
+ int i;
+
+ if(vbuffer_start_flag == 1){
+ RLOGE(" VB already start,return \n");
+
+ return 0;
+ }
+
+ vbuffer_start_flag = 1;
+
+
+
+ if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
+ RLOGE(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
+ }
+
+ if(fs == 8000){
+
+ buf_size = 320;
+ }
+ else if(fs == 16000){
+
+ buf_size = 640;
+ }
+ else
+ {
+ buf_size = 320;
+ }
+ RLOGD("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
+
+ RLOGD("%s:open tx and rx file \n",__func__);
+ if(fs == 8000){
+
+ vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
+ vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
+
+ }
+ else if(fs == 16000){
+
+ vbuf_rec.tx_filename = VBUFFER_TX16_FILE_NAME;//"/cache/tx16.pcm";
+ vbuf_rec.rx_filename = VBUFFER_RX16_FILE_NAME;//"/cache/rx16.pcm";
+
+ }
+ else
+ {
+ vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
+ vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
+
+ }
+
+
+
+
+ vbuf_rec.tx_file = fopen(vbuf_rec.tx_filename , "rb");
+ if (!vbuf_rec.tx_file) {
+ RLOGE("Unable to open file '%s'\n", vbuf_rec.tx_filename);
+ //return -1;
+ }
+
+
+ vbuf_rec.rx_file = fopen(vbuf_rec.rx_filename, "wb");
+ if (!vbuf_rec.rx_file) {
+ RLOGE("Unable to create file '%s'\n", vbuf_rec.rx_filename);
+ //fclose(vbuf_rec.tx_file);
+
+ //return -1;
+ }
+ vbuf_rec.rx_filesize = RX_FILE_LEN_MAX;
+ RLOGD("%s : vbuf_rec.rx_filesize(%d) \n",__func__,vbuf_rec.rx_filesize);
+
+ vbuf_rec.rx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.rx_buf) {
+ RLOGE("%s : malloc buf fail,return \n",__func__);
+ goto err;
+ }
+ vbuf_rec.tx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.tx_buf) {
+ free(vbuf_rec.rx_buf);
+ RLOGE("%s : malloc buf fail,return \n",__func__);
+ vbuf_rec.rx_buf = NULL;
+ goto err;
+ }
+ vbuf_rec.buf_size = buf_size;
+
+ vbuf_rec.quit = 0;
+
+ RLOGD("%s : vb open start \n",__func__);
+
+
+ vbuf_rec.fd = voice_buffer_open();
+ if(vbuf_rec.fd <= 0){
+ RLOGE("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
+ ret = -1;
+ goto err;
+
+ }
+ RLOGD("%s :voice_buffer_open end \n",__func__);
+
+ RLOGD("%s :rx tx vb_thread_create start \n",__func__);
+ ret = vb_thread_create ("vb_playback_test",&vbuf_rec.rx_test_thread, vb_rx_test_thread_func,
+ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+ RLOGE("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ vbuf_rec.rx_test_thread = NULL;
+ goto err;
+ }
+
+ RLOGD("%s :rx vb_thread_create end \n",__func__);
+
+ ret = vb_thread_create ( "vbuf_record_test", &vbuf_rec.tx_test_thread, vb_tx_test_thread_func,
+ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+
+ RLOGE("%s :tx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ vbuf_rec.tx_test_thread = NULL;
+ goto err;
+ }
+ RLOGD("%s :tx vb_thread_create end \n",__func__);
+
+ return 0;
+
+err:
+ voice_buffer_stream_test_stop();
+
+ return ret;
+}
+
+
+//Stop stream
+int voice_buffer_stream_test_stop(void)
+{
+ int ret = 0;
+ RLOGD("%s:rx tx thread exit start \n",__func__);
+ if(vbuf_rec.quit == 1) {
+ RLOGD("%s,already stop ,return\n",__func__);
+
+ }
+
+ vbuf_rec.quit = 1;
+ voice_buffer_stop(vbuf_rec.fd);
+ if (vbuf_rec.tx_test_thread)
+ {
+ pthread_join (vbuf_rec.tx_test_thread,NULL);
+ vbuf_rec.tx_test_thread = NULL;
+
+ }
+
+ if (vbuf_rec.rx_test_thread)
+ {
+ pthread_join (vbuf_rec.rx_test_thread,NULL);
+ vbuf_rec.rx_test_thread = NULL;
+ }
+
+ if(vbuf_rec.tx_file != NULL)
+ {
+ fclose(vbuf_rec.tx_file);
+ RLOGD("%s : vb close ,close tx file \n",__func__);
+ vbuf_rec.tx_file = NULL;
+ }
+
+ if(vbuf_rec.rx_file != NULL)
+ {
+
+ fclose(vbuf_rec.rx_file);
+ RLOGD("%s : vb close ,close rx file \n",__func__);
+ vbuf_rec.rx_file = NULL;
+
+ }
+
+ vb_close_fd_release_buf();
+ return 0;
+}
+
+
+static int vb_loop_test_thread_func(void *arg)
+{
+ int ret;
+
+ char* buf = vbuf_rec.rx_buf;
+ int size = vbuf_rec.buf_size;
+
+ //char* buf = vbuf_rec.tx_buf;
+
+ //int size = vbuf_rec.buf_size;
+ int w_size;
+ int r_size;
+
+
+ RLOGD( "%s: start size=%d! \n",__func__,size);
+ memset (buf,0, size);
+
+ while (!vbuf_rec.quit)
+ {
+ rx_optcount ++;
+ VB_INT_OVERFLOW(rx_optcount);
+ if((rx_optcount%1000) == 0){
+ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+
+ }
+ else if(rx_optcount == 1000000){
+ RLOGD("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+ rx_optcount = 0;
+
+ }
+
+ //read form ps
+ r_size = voice_buffer_read(vbuf_rec.fd, vbuf_rec.rx_buf, size);
+ if(r_size <= 0)
+ {
+ first_rderr_flag++;
+ VB_INT_OVERFLOW(first_rderr_flag);
+ continue ;
+ }
+ else{
+ first_rderr_flag = 0;
+ }
+ memcpy(vbuf_rec.tx_buf,vbuf_rec.rx_buf,size);
+ w_size = voice_buffer_write(vbuf_rec.fd, vbuf_rec.tx_buf, size);
+ if(w_size <= 0)
+ {
+ first_wrerr_flag++;
+
+ VB_INT_OVERFLOW(first_wrerr_flag);
+
+ continue;
+ }
+ else{
+ first_wrerr_flag = 0;
+ }
+
+ }
+
+ return 0;
+}
+
+
+int voice_buffer_stream_loop_test_stop(void);
+
+int voice_buffer_stream_loop_test_start(int fs)
+{
+ int ret = -1;
+ int buf_size = 320;
+ tx_optcount = 0;
+ rx_optcount = 0;
+ int* buf_int;
+
+ int i;
+
+ if(vbuffer_start_flag == 1){
+ RLOGE(" VB already start,return \n");
+
+ return 0;
+ }
+
+ if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
+ RLOGE(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
+ }
+
+ vbuffer_start_flag = 1;
+
+ if(fs == 8000){
+
+ buf_size = 320;
+ }
+ else if(fs == 16000){
+
+ buf_size = 640;
+ }
+ else
+ {
+ buf_size = 320;
+ }
+ RLOGD("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
+
+ vbuf_rec.rx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.rx_buf) {
+ RLOGE("%s : malloc buf fail,return \n",__func__);
+ goto err;
+ }
+ vbuf_rec.tx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.tx_buf) {
+ RLOGE("%s : malloc buf fail,return \n",__func__);
+ goto err;
+ }
+ vbuf_rec.buf_size = buf_size;
+
+ vbuf_rec.quit = 0;
+
+ RLOGD("%s : vb open start \n",__func__);
+
+
+ vbuf_rec.fd = voice_buffer_open();
+ if(vbuf_rec.fd <= 0){
+ RLOGE("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
+ goto err;
+
+ }
+ RLOGD("%s :loop vb_thread_create start \n",__func__);
+ ret = vb_thread_create ("vb_playback_test",&vbuf_rec.loop_test_thread, vb_loop_test_thread_func,
+ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+ RLOGE("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ goto err;
+ }
+
+ RLOGD("%s :rx vb_thread_create end \n",__func__);
+
+ return 0;
+
+err:
+ voice_buffer_stream_loop_test_stop();
+
+ return ret;
+}
+
+int voice_buffer_stream_loop_test_stop(void)
+{
+ int ret = 0;
+ RLOGD("%s:loop thread exit start \n",__func__);
+ if(vbuf_rec.quit == 1) {
+ RLOGD("%s,already stop ,return\n",__func__);
+
+ }
+
+ vbuf_rec.quit = 1;
+ voice_buffer_stop(vbuf_rec.fd);
+ if (vbuf_rec.loop_test_thread)
+ {
+ pthread_join (vbuf_rec.loop_test_thread,NULL);
+ vbuf_rec.tx_test_thread = NULL;
+
+ }
+
+ vb_close_fd_release_buf();
+ return 0;
+}
+
+int voice_buffer_rtp_test_start(int fs)
+{
+ // refer to voice_buffer_stream_test_start(fs);
+ return 0;
+}
+
+
+
+int voice_buffer_rtp_test_stop(void)
+{
+// refer to voice_buffer_stream_loop_test_stop();
+ return 0;
+
+}
+
+void voice_buffer_cmd_proc(char *cmdstr)
+{
+ int ret = 0;
+ char data[VOICE_CMD_MAX_LEN];
+ int cmdstr_len = strlen(cmdstr); //-strlen("\r")
+ int value = 0;
+ int *p_value = &value;
+
+
+
+ cmdstr[cmdstr_len] = '\0'; //+strlen("\0")
+
+ ret = sscanf(cmdstr, "%s", data);
+ if(1 != ret){
+ RLOGE("data sscanf failed!(%d)\n", ret);
+ return;
+ }
+
+ pthread_mutex_lock(&s_vb_demo_mtx);
+ if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_START, strlen(REQ_VOICE_BUFFER_TEST_START))){
+
+ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+ RLOGE("%s,value sscanf failed!(%d)\n",data, ret);
+ goto vb_cmd_end;
+ }
+
+ RLOGD("%s set value %d\n", data, value);
+ ret = voice_buffer_stream_test_start(value);
+
+ RLOGD("%s return ret=%d\n", data, ret);
+
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_STOP, strlen(REQ_VOICE_BUFFER_TEST_STOP))){
+ ret = voice_buffer_stream_test_stop();
+ RLOGD("%s return %d\n", data, ret);
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_START, strlen(REQ_VOICE_BUFFER_LOOP_TEST_START))){
+
+ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+ RLOGE("%s,value sscanf failed!(%d)\n",data, ret);
+ goto vb_cmd_end;
+ }
+
+ RLOGD("%s set value %d\n", data, value);
+ ret = voice_buffer_stream_loop_test_start(value);
+
+ RLOGD("%s return ret=%d\n", data, ret);
+
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_STOP, strlen(REQ_VOICE_BUFFER_LOOP_TEST_STOP))){
+ RLOGD("voice_buffer_stream_loop_test_stop \n");
+ ret = voice_buffer_stream_loop_test_stop();
+ RLOGD("%s return %d\n", data, ret);
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_START, strlen(REQ_VOICE_BUFFER_RTP_TEST_START))){
+
+ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+ RLOGE("%s,value sscanf failed!(%d)\n",data, ret);
+ goto vb_cmd_end;
+ }
+
+ RLOGD("%s set value %d\n", data, value);
+ ret = voice_buffer_rtp_test_start(value);
+
+ RLOGD("%s return ret=%d\n", data, ret);
+
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_STOP, strlen(REQ_VOICE_BUFFER_RTP_TEST_STOP))){
+ ret = voice_buffer_rtp_test_stop();
+ RLOGD("%s return %d\n", data, ret);
+ }
+ else{
+ RLOGE("Request unknow.\n");
+ printUsage(cmdstr);
+ }
+vb_cmd_end:
+ pthread_mutex_unlock(&s_vb_demo_mtx);
+}
+
+void vb_buffer_stop_all()
+{
+ voice_buffer_stream_loop_test_stop();
+ voice_buffer_stream_test_stop();
+ voice_buffer_rtp_test_stop();
+}
+
+void signal_handle_func(int sig)
+{
+ RLOGD("sig(%d) signal_handle_func exit ",sig);
+
+ pthread_mutex_lock(&s_vb_demo_mtx);
+ vb_buffer_stop_all();
+ pthread_mutex_unlock(&s_vb_demo_mtx);
+ exit(0);
+}
+
+int main(int argc, char **argv)
+{
+ char cmdstr[VOICE_CMD_MAX_LEN];
+
+ signal(SIGINT, signal_handle_func);
+ signal(SIGQUIT, signal_handle_func);
+ signal(SIGTERM, signal_handle_func);
+ signal(SIGPIPE, signal_handle_func);
+
+ memset(&vbuf_rec,0,sizeof(vbuf_rec));
+#if 0
+ /*add by hq for faster start @20240906,begin*/
+ if(argc>1)
+ {
+ voice_buffer_cmd_proc(argv[1]);
+ }
+ /*add by hq for faster start @20240906,end*/
+ else
+ {
+#endif
+ printf("Please input an voice_demo command:\n");
+ while(1){
+ if(NULL != fgets(cmdstr, VOICE_CMD_MAX_LEN - 1, stdin)){
+ if(0 == strcmp(EXIT_CMD_STOP, cmdstr) ||
+ 0 == strcmp(EXIT_CMD_Q, cmdstr) ||
+ 0 == strcmp(EXIT_CMD_EXIT, cmdstr)){
+ vb_buffer_stop_all();
+ break;
+ }
+
+ RLOGI("len:%d, cmdstr:%s\n", strlen(cmdstr), cmdstr);
+
+ if(1 >= strlen(cmdstr)){
+ continue;
+ }
+ voice_buffer_cmd_proc(cmdstr);
+ }
+ sleep(5);
+ }
+
+
+ RLOGD("voice_demo end\n");
+
+ return 0;
+}
+
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
new file mode 100755
index 0000000..7117ebc
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
@@ -0,0 +1,48 @@
+SHELL = /bin/sh
+RM = rm -f
+
+LOCAL_CFLAGS := -Wall \
+ -g -Os \
+ -flto \
+ -fpermissive \
+ -fPIC \
+
+ifeq ($(strip $(TARGET_PLATFORM)), T106)
+LOCAL_CFLAGS += -DBINDER_IPC_32BIT=1 -DHAVE_ENDIAN_H -DHAVE_PTHREADS -DHAVE_SYS_UIO_H -DHAVE_POSIX_FILEMAP -DHAVE_STRLCPY -DHAVE_PRCTL -DHAVE_MEMSET16 -DHAVE_MEMSET32 -DANDROID_SMP=0
+endif
+
+LOCAL_CFLAGS += -Werror=implicit-function-declaration
+
+$(warning ################# rock ROOT: $(ROOT),includedir:$(includedir),)
+
+LOCAL_PATH = .
+
+LOCAL_C_INCLUDES = \
+ -I. \
+ -I$(ROOT)$(includedir)/ \
+
+
+
+LOCAL_LIBS := \
+ -L. \
+ -ldl \
+ -llog \
+ -lpthread \
+ -lvoice \
+
+SOURCES = $(wildcard *.c)
+
+EXECUTABLE = lynq_vb_demo
+
+OBJECTS=$(SOURCES:.c=.o)
+all: $(EXECUTABLE)
+
+$(EXECUTABLE): $(OBJECTS)
+ $(CC) $(OBJECTS) $(LOCAL_LIBS) $(LOCAL_CFLAGS) $(LOCAL_C_INCLUDES) -o $@
+
+%.o : %.c
+ $(CC) $(LOCAL_C_INCLUDES) $(LOCAL_CFLAGS) $(LOCAL_LIBS) -o $@ -c $<
+
+.PHONY: clean
+clean:
+ $(RM) $(OBJECTS) $(EXECUTABLE)
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
new file mode 100755
index 0000000..5691603
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
@@ -0,0 +1,29 @@
+#inherit externalsrc package
+
+DESCRIPTION = "lynq-vb-demo"
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=b1e07e8d88e26263e71d3a9e2aa9a2ff"
+DEPENDS += "libbinder libvoice"
+SRC_URI = "file://lynq_vb_demo.c \
+ file://makefile \
+"
+
+SRC-DIR = "${S}/../lynq-vb-demo"
+FILES_${PN} += "${bindir}/"
+TARGET_CC_ARCH += "${LDFLAGS}"
+
+S = "${WORKDIR}"
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ if test "${PACKAGE_ARCH}" = "cortexa7hf-vfp-vfpv4-neon" || test "${PACKAGE_ARCH}" = "cortexa7hf-neon-vfpv4"; then
+ oe_runmake all ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -mhard-float"
+ else
+ oe_runmake all ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST}"
+ fi
+}
+
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/lynq_vb_demo ${D}${bindir}/
+}
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
new file mode 100755
index 0000000..236850c
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
@@ -0,0 +1,53 @@
+DESCRIPTION = "libvoice"
+DEPENDS = "libtinyalsa libnvram libsoftap libsofttimer libdebug-info"
+SECTION = "lib"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://libvoice \
+ "
+
+S = "${WORKDIR}"
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append = "-I ${BSPDIR}/zxic_code/zxic_source/zxic_app_open/platform/libtinyalsa/include"
+CFLAGS_append = "-I ${BSPDIR}/zxic_code/zxic_source/linux-5.10/include/linux"
+
+
+CFLAGS_append += "${@bb.utils.contains("CONFIG_VB_TRANSMIT_INTF", "RTP", "-I ${BSPDIR}/zxic_code/zxic_source/zxic_app/librtp/include", "", d)}"
+CFLAGS_append += "${ZXIC_EXTRA_CFLAGS}"
+DEPENDS += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', 'librtp', '', d)}"
+#编译
+do_compile () {
+ make -C libvoice CONFIG_VB_TRANSMIT_INTF=${CONFIG_VB_TRANSMIT_INTF}
+}
+
+#库和头文件的安装
+do_install () {
+ install -d ${D}${libdir}/
+ install -d ${D}/usr/include
+ install -m 0755 ${S}/libvoice/libvoice.so ${D}${libdir}/
+ install -m 0755 ${S}/libvoice/libvoice.a ${D}${libdir}/
+ install -m 0644 ${S}/libvoice/include/*.h ${D}/usr/include/
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/libvoice/libvoice.so ${ELFS-PATH}/
+}
+
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/libvoice.so
+}
+
+#rootfs包含的文件
+FILES_${PN} += "${libdir}/*.so"
+FILES_${PN}-dbg += "${libdir}/.debug"
+FILES_SOLIBSDEV = ""
+INSANE_SKIP_${PN} = "dev-so"
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
new file mode 100755
index 0000000..e7cf838
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
@@ -0,0 +1,79 @@
+DESCRIPTION = "nvserver"
+#nvserver依赖libnvram库
+DEPENDS = "libmtd libnvram libflags libsd-daemon libdebug-info"
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://nvserver \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://nvserver.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://nvserver.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://nvserver.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append = "${ZXIC_EXTRA_CFLAGS}"
+
+#编译
+do_compile() {
+ make -C nvserver
+}
+
+#库文件的安装
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/nvserver/nvserver ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/nvserver.init ${D}${sysconfdir}/init.d/nvserver
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/nvserver.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/nvserver.sysvinit ${D}${sysconfdir}/init.d/nvserver
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/nvserver ${D}${sysconfdir}/rcS.d/S16nvserver
+ ln -s ../init.d/nvserver ${D}${sysconfdir}/rcS.d/K84nvserver
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/nvserver/nvserver ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/nvserver
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "nvserver.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+RDEPENDS_${PN} = "libmtd libnvram libflags libsd-daemon"
+
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
new file mode 100755
index 0000000..37b2b5f
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
@@ -0,0 +1,78 @@
+DESCRIPTION = "sntp"
+#sntp依赖libnvram库
+DEPENDS = "libdebug-info libnvram libsoftap libsofttimer"
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://sntp \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://sntp.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://sntp.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://sntp.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append += "${ZXIC_EXTRA_CFLAGS}"
+#编译
+do_compile() {
+ make -C sntp
+}
+
+#库文件的安装，封库的宏MK_SDK_VERSION
+do_install () {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/sntp/sntp ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/sntp.init ${D}${sysconfdir}/init.d/sntp
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/sntp.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/sntp.sysvinit ${D}${sysconfdir}/init.d/sntp
+ install -d ${D}${sysconfdir}/rcS.d
+ #xy.he@20250211 bug-view-378 add for disable sntp autostart start
+ #ln -s ../init.d/sntp ${D}${sysconfdir}/rcS.d/S22sntp
+ #xy.he@20250211 bug-view-378 add for disable sntp autostart end
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/sntp/sntp ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/sntp
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/init.d/sntp","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "sntp.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+RDEPENDS_${PN} = " libdebug-info libnvram libsoftap libsofttimer"
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
new file mode 100755
index 0000000..0386349
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
@@ -0,0 +1,79 @@
+DESCRIPTION = "zxic-debug"
+#zxic-debug依赖libnvram库
+DEPENDS = "libnvram openssl "
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://zxic_debug \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://zxic_debug.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://zxic_debug.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://zxic_debug.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append = "${ZXIC_EXTRA_CFLAGS}"
+
+#编译
+do_compile() {
+ make -C zxic_debug
+}
+
+#库文件的安装
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/zxic_debug/zxic_debug ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/zxic_debug.init ${D}${sysconfdir}/init.d/zxic_debug
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/zxic_debug.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/zxic_debug.sysvinit ${D}${sysconfdir}/init.d/zxic_debug
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/zxic_debug ${D}${sysconfdir}/rcS.d/S90zxic_debug
+ ln -s ../init.d/zxic_debug ${D}${sysconfdir}/rcS.d/K10zxic_debug
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/zxic_debug/zxic_debug ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/zxic_debug
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "zxic_debug.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+
+
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox/busybox-1.33.1/0104-zxic-reboot-print-ppid.patch b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox/busybox-1.33.1/0104-zxic-reboot-print-ppid.patch
new file mode 100755
index 0000000..fe957aa
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox/busybox-1.33.1/0104-zxic-reboot-print-ppid.patch
@@ -0,0 +1,105 @@
+From 788511a2255d0416dfba782853bd20cb55b5ea67 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?=E5=91=A8=E5=9B=BD=E5=9D=A10318000136?=
+ <zhou.guopo@sanechips.com.cn>
+Date: Thu, 7 Nov 2024 14:18:56 +0800
+Subject: [PATCH] zxic reboot print ppid
+
+---
+ init/halt.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+diff --git a/init/halt.c b/init/halt.c
+index ddb03e2..93980b6 100644
+--- a/init/halt.c
++++ b/init/halt.c
+@@ -154,6 +154,78 @@ static int init_was_not_there(void)
+ # define init_was_not_there() 0
+ #endif
+
++extern int sc_debug_info_record(char *id, const char *format, ...);
++static void get_app_name_by_pid(int pid, char *app_name, int app_name_len)
++{
++ char file_comm[256];
++ FILE *pfile;
++ size_t len;
++
++ memset(file_comm, 0, sizeof(file_comm));
++ snprintf(file_comm, sizeof(file_comm), "/proc/%d/comm", pid);
++
++ pfile = fopen(file_comm, "r");
++ if (pfile)
++ {
++ memset(app_name, 0, app_name_len);
++ fgets(app_name, app_name_len, pfile);
++ app_name[app_name_len-1] = '\0';
++ app_name[strlen(app_name) - 1] = '\0'; //last byte is \n
++ fclose(pfile);
++ }
++}
++
++static int get_ppid(int pid) {
++ char path[256];
++ snprintf(path, sizeof(path), "/proc/%d/stat", pid);
++
++ FILE *fp = fopen(path, "r");
++ if (fp == NULL) {
++ perror("fopen");
++ return -1;
++ }
++
++ int ppid = -1;
++ // 通过解析第4列（ppid）来获取父进程ID
++ fscanf(fp, "%*d %*s %*c %d", &ppid);
++ fclose(fp);
++ return ppid;
++}
++
++static int get_reboot_caller(char *applet_name)
++{
++ int pid = get_ppid(getpid());
++ char app_name[32];
++ int app_name_len = sizeof(app_name);
++ int try_cnt = 0;
++
++ while(1)
++ {
++ if (try_cnt > 5) {
++ strcpy(app_name, "unkown");
++ break;
++ }
++ try_cnt++;
++ if (pid == 1) {
++ get_app_name_by_pid(pid, app_name, app_name_len);
++ break; //init
++ }
++ get_app_name_by_pid(pid, app_name, app_name_len);
++ if ((strcmp(app_name, "sh") == 0) || (strcmp(app_name, "bash") == 0)) {
++ //printf("shell %s continue %d\n", app_name, strlen(app_name));
++ pid = get_ppid(pid); //sh continue
++ } else {
++ //printf("not sh break %s %d\n", app_name, strlen(app_name));
++ break; //not sh
++ }
++ }
++
++ sc_debug_info_record("cap_reboot", "call %s reset_by %s(%d)\n", applet_name, app_name, pid);
++ printf("call %s by %s(%d)\n", applet_name, app_name, pid);
++
++ return 0;
++}
++
+ int halt_main(int argc, char **argv) MAIN_EXTERNALLY_VISIBLE;
+ int halt_main(int argc UNUSED_PARAM, char **argv)
+ {
+@@ -180,6 +252,8 @@ int halt_main(int argc UNUSED_PARAM, char **argv)
+ for (which = 0; "hpr"[which] != applet_name[0]; which++)
+ continue;
+
++ get_reboot_caller(applet_name); //add by zxic, print parent proccess name and pid
++
+ /* Parse and handle arguments */
+ /* We support -w even if !ENABLE_FEATURE_WTMP,
+ * in order to not break scripts.
+--
+2.17.1
+
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
new file mode 100755
index 0000000..43a4540
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
@@ -0,0 +1,69 @@
+require busybox_1.33.1.inc
+
+SRC_URI = "https://busybox.net/downloads/busybox-${PV}.tar.bz2;name=tarball \
+ file://busybox-1.33.1/busybox-udhcpc-no_deconfig.patch \
+ file://find-touchscreen.sh \
+ file://busybox-cron \
+ file://busybox-httpd \
+ file://busybox-udhcpd \
+ file://default.script \
+ file://simple.script \
+ file://hwclock.sh \
+ file://syslog \
+ file://syslog-startup.conf \
+ file://syslog.conf \
+ file://busybox-syslog.default \
+ file://files-1.33.1/mdev \
+ file://mdev.conf \
+ file://mdev-mount.sh \
+ file://busybox-1.33.1/defconfig \
+ file://busybox-syslog.service.in \
+ file://busybox-klogd.service.in \
+ file://busybox-1.33.1/fail_on_no_media.patch \
+ file://run-ptest \
+ file://inetd.conf \
+ file://inetd \
+ file://login-utilities.cfg \
+ file://recognize_connmand.patch \
+ file://busybox-cross-menuconfig.patch \
+ file://busybox-1.33.1/0001-Use-CC-when-linking-instead-of-LD-and-use-CFLAGS-and.patch \
+ file://busybox-1.33.1/mount-via-label.cfg \
+ file://sha1sum.cfg \
+ file://sha256sum.cfg \
+ file://getopts.cfg \
+ file://resize.cfg \
+ ${@["", "file://init.cfg"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]} \
+ ${@["", "file://rcS.default"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]} \
+ ${@["", "file://mdev.cfg"][(d.getVar('VIRTUAL-RUNTIME_dev_manager') == 'busybox-mdev')]} \
+ file://syslog.cfg \
+ file://unicode.cfg \
+ file://rev.cfg \
+ file://pgrep.cfg \
+ file://rcS \
+ file://rcK \
+ file://makefile-libbb-race.patch \
+ file://busybox-1.33.1/0001-testsuite-check-uudecode-before-using-it.patch \
+ file://0001-testsuite-use-www.example.org-for-wget-test-cases.patch \
+ file://0001-du-l-works-fix-to-use-145-instead-of-144.patch \
+ file://0001-sysctl-ignore-EIO-of-stable_secret-below-proc-sys-ne.patch \
+ file://busybox-1.33.1/0001-gen_build_files-Use-C-locale-when-calling-sed-on-glo.patch \
+ file://busybox-1.33.1/0001-mktemp-add-tmpdir-option.patch \
+ file://busybox-1.33.1/600-dhcpd-fix.patch \
+ file://busybox-1.33.1/0100-zxic-tty-disable-soft-flow-control.patch \
+ file://busybox-1.33.1/700-dhcpd-fix.patch \
+ "
+#LYNQ_MODIFY_ZXW_TASK935_XF.Li_20250122_START
+#SRC_URI += "file://busybox-1.33.1/010-syslogd-recive-remote-log.patch"
+#LYNQ_MODIFY_ZXW_TASK935_XF.Li_20250122_END
+SRC_URI += "file://busybox-1.33.1/020-syslogd-filesize-and-filenum-parameter-nvcfg.patch"
+#SRC_URI += "file://busybox-1.33.1/022-syslogd-replace-remote-log-facility.patch"
+SRC_URI += "file://busybox-1.33.1/0100-zxic-add-sync-after-chmod.patch"
+SRC_URI += "file://busybox-1.33.1/0101-zxic-bb_get_chunk_from_file-limit-10MB.patch"
+SRC_URI += "file://busybox-1.33.1/0102-zxic-ash-read-etc-profile.patch"
+SRC_URI += "file://busybox-1.33.1/0103-top-short-lived-processes-optimize.patch"
+SRC_URI += "file://busybox-1.33.1/0103-syslogd-data-encryption.patch"
+SRC_URI += "file://busybox-1.33.1/0104-zxic-reboot-print-ppid.patch"
+
+SRC_URI_append_libc-musl = " file://busybox-1.33.1/musl.cfg "
+
+SRC_URI[tarball.sha256sum] = "12cec6bd2b16d8a9446dd16130f2b92982f1819f6e1c5f5887b6db03f5660d28"
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
new file mode 100755
index 0000000..1b610f9
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
@@ -0,0 +1,510 @@
+SUMMARY = "Tiny versions of many common UNIX utilities in a single small executable"
+DESCRIPTION = "BusyBox combines tiny versions of many common UNIX utilities into a single small executable. It provides minimalist replacements for most of the utilities you usually find in GNU fileutils, shellutils, etc. The utilities in BusyBox generally have fewer options than their full-featured GNU cousins; however, the options that are included provide the expected functionality and behave very much like their GNU counterparts. BusyBox provides a fairly complete POSIX environment for any small or embedded system."
+HOMEPAGE = "https://www.busybox.net"
+BUGTRACKER = "https://bugs.busybox.net/"
+
+DEPENDS += "kern-tools-native virtual/crypt libnvram libdebug-info"
+
+# bzip2 applet in busybox is based on lightly-modified bzip2-1.0.4 source
+# the GPL is version 2 only
+LICENSE = "GPLv2 & bzip2-1.0.4"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=de10de48642ab74318e893a61105afbb \
+ file://archival/libarchive/bz/LICENSE;md5=28e3301eae987e8cfe19988e98383dae"
+
+SECTION = "base"
+
+# Whether to split the suid apps into a seperate binary
+BUSYBOX_SPLIT_SUID ?= "1"
+
+export EXTRA_CFLAGS = "${CFLAGS}"
+export EXTRA_LDFLAGS = "${LDFLAGS}"
+
+EXTRA_OEMAKE = "CC='${CC}' LD='${CCLD}' V=1 ARCH=${TARGET_ARCH} CROSS_COMPILE=${TARGET_PREFIX} SKIP_STRIP=y HOSTCC='${BUILD_CC}' HOSTCPP='${BUILD_CPP}'"
+
+PACKAGES =+ "${PN}-httpd ${PN}-udhcpd ${PN}-udhcpc ${PN}-syslog ${PN}-mdev ${PN}-hwclock"
+
+FILES_${PN}-httpd = "${sysconfdir}/init.d/busybox-httpd /srv/www"
+FILES_${PN}-syslog = "${sysconfdir}/init.d/syslog* ${sysconfdir}/syslog-startup.conf* ${sysconfdir}/syslog.conf* ${systemd_unitdir}/system/syslog.service ${sysconfdir}/default/busybox-syslog"
+FILES_${PN}-mdev = "${sysconfdir}/init.d/mdev ${sysconfdir}/mdev.conf ${sysconfdir}/mdev/*"
+FILES_${PN}-udhcpd = "${sysconfdir}/init.d/busybox-udhcpd"
+FILES_${PN}-udhcpc = "${sysconfdir}/udhcpc.d ${datadir}/udhcpc"
+FILES_${PN}-hwclock = "${sysconfdir}/init.d/hwclock.sh"
+
+INITSCRIPT_PACKAGES = "${PN}-httpd ${PN}-syslog ${PN}-udhcpd ${PN}-mdev ${PN}-hwclock"
+
+INITSCRIPT_NAME_${PN}-httpd = "busybox-httpd"
+INITSCRIPT_NAME_${PN}-hwclock = "hwclock.sh"
+INITSCRIPT_NAME_${PN}-mdev = "mdev"
+INITSCRIPT_PARAMS_${PN}-mdev = "start 04 S ."
+INITSCRIPT_NAME_${PN}-syslog = "syslog"
+INITSCRIPT_NAME_${PN}-udhcpd = "busybox-udhcpd"
+
+SYSTEMD_PACKAGES = "${PN}-syslog"
+SYSTEMD_SERVICE_${PN}-syslog = "${@bb.utils.contains('SRC_URI', 'file://syslog.cfg', 'busybox-syslog.service', '', d)}"
+
+RDEPENDS_${PN}-syslog = "busybox"
+CONFFILES_${PN}-syslog = "${sysconfdir}/syslog-startup.conf"
+RCONFLICTS_${PN}-syslog = "rsyslog sysklogd syslog-ng"
+
+CONFFILES_${PN}-mdev = "${sysconfdir}/mdev.conf"
+
+RRECOMMENDS_${PN} = "${PN}-udhcpc"
+
+RDEPENDS_${PN} = "${@["", "busybox-inittab"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]}"
+
+inherit cml1 systemd update-rc.d ptest
+
+# busybox's unzip test case needs zip command, which busybox itself does not provide
+RDEPENDS_${PN}-ptest = "zip"
+
+# internal helper
+def busybox_cfg(feature, tokens, cnf, rem):
+ if type(tokens) == type(""):
+ tokens = [tokens]
+ rem.extend(['/^[# ]*' + token + '[ =]/d' for token in tokens])
+ if feature:
+ cnf.extend([token + '=y' for token in tokens])
+ else:
+ cnf.extend(['# ' + token + ' is not set' for token in tokens])
+
+# Map distro features to config settings
+def features_to_busybox_settings(d):
+ cnf, rem = ([], [])
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv6', True, False, d), 'CONFIG_FEATURE_IPV6', cnf, rem)
+ busybox_cfg(True, 'CONFIG_LFS', cnf, rem)
+ busybox_cfg(True, 'CONFIG_FDISK_SUPPORT_LARGE_DISKS', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'nls', True, False, d), 'CONFIG_LOCALE_SUPPORT', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv4', True, False, d), 'CONFIG_FEATURE_IFUPDOWN_IPV4', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv6', True, False, d), 'CONFIG_FEATURE_IFUPDOWN_IPV6', cnf, rem)
+ busybox_cfg(bb.utils.contains_any('DISTRO_FEATURES', 'bluetooth wifi', True, False, d), 'CONFIG_RFKILL', cnf, rem)
+ return "\n".join(cnf), "\n".join(rem)
+
+# X, Y = ${@features_to_busybox_settings(d)}
+# unfortunately doesn't seem to work with bitbake, workaround:
+def features_to_busybox_conf(d):
+ cnf, rem = features_to_busybox_settings(d)
+ return cnf
+def features_to_busybox_del(d):
+ cnf, rem = features_to_busybox_settings(d)
+ return rem
+
+configmangle = '/CONFIG_EXTRA_CFLAGS/d; \
+ '
+OE_FEATURES := "${@features_to_busybox_conf(d)}"
+OE_DEL := "${@features_to_busybox_del(d)}"
+DO_IPv4 := "${@bb.utils.contains('DISTRO_FEATURES', 'ipv4', 1, 0, d)}"
+DO_IPv6 := "${@bb.utils.contains('DISTRO_FEATURES', 'ipv6', 1, 0, d)}"
+
+python () {
+ if "${OE_DEL}":
+ d.setVar('configmangle_append', "${OE_DEL}" + "\n")
+ if "${OE_FEATURES}":
+ d.setVar('configmangle_append',
+ "/^### DISTRO FEATURES$/a\\\n%s\n\n" %
+ ("\\n".join((d.expand("${OE_FEATURES}").split("\n")))))
+ d.setVar('configmangle_append',
+ "/^### CROSS$/a\\\n%s\n" %
+ ("\\n".join(["CONFIG_EXTRA_CFLAGS=\"${CFLAGS} ${HOST_CC_ARCH}\""
+ ])
+ ))
+}
+
+do_prepare_config () {
+ if [ "${BUILD_REPRODUCIBLE_BINARIES}" = "1" ]; then
+ export KCONFIG_NOTIMESTAMP=1
+ fi
+ sed -e '/CONFIG_STATIC/d' \
+ < ${WORKDIR}/busybox-1.33.1/defconfig > ${S}/.config
+ echo "# CONFIG_STATIC is not set" >> .config
+ for i in 'CROSS' 'DISTRO FEATURES'; do echo "### $i"; done >> \
+ ${S}/.config
+ sed -i -e '${configmangle}' ${S}/.config
+ if test ${DO_IPv4} -eq 0 && test ${DO_IPv6} -eq 0; then
+ # disable networking applets
+ mv ${S}/.config ${S}/.config.oe-tmp
+ awk 'BEGIN{net=0}
+ /^# Networking Utilities/{net=1}
+ /^#$/{if(net){net=net+1}}
+ {if(net==2&&$0 !~ /^#/&&$1){print("# "$1" is not set")}else{print}}' \
+ ${S}/.config.oe-tmp > ${S}/.config
+ fi
+ sed -i 's/CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"/CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -b"/' ${S}/.config
+ if [ -n "${DEBUG_PREFIX_MAP}" ]; then
+ sed -i 's|${DEBUG_PREFIX_MAP}||g' ${S}/.config
+ fi
+}
+
+do_configure () {
+ set -x
+ do_prepare_config
+ merge_config.sh -m .config ${@" ".join(find_cfgs(d))}
+ cml1_do_configure
+}
+
+do_compile() {
+ unset CFLAGS CPPFLAGS CXXFLAGS LDFLAGS
+ if [ "${BUILD_REPRODUCIBLE_BINARIES}" = "1" ]; then
+ export KCONFIG_NOTIMESTAMP=1
+ fi
+ if [ "${BUSYBOX_SPLIT_SUID}" = "1" -a x`grep "CONFIG_FEATURE_INDIVIDUAL=y" .config` = x ]; then
+ # split the .config into two parts, and make two busybox binaries
+ if [ -e .config.orig ]; then
+ # Need to guard again an interrupted do_compile - restore any backup
+ cp .config.orig .config
+ fi
+ cp .config .config.orig
+ oe_runmake busybox.cfg.suid
+ oe_runmake busybox.cfg.nosuid
+
+ # workaround for suid bug 10346
+ if ! grep -q "CONFIG_SH_IS_NONE" busybox.cfg.nosuid; then
+ echo "CONFIG_SH_IS_NONE" >> busybox.cfg.suid
+ fi
+
+ for i in `cat busybox.cfg.suid busybox.cfg.nosuid`; do
+ echo "# $i is not set" >> .config.disable.apps
+ done
+ merge_config.sh -m .config.orig .config.disable.apps
+ cp .config .config.nonapps
+ for s in suid nosuid; do
+ cat busybox.cfg.$s | while read item; do
+ grep -w "$item" .config.orig
+ done > .config.app.$s
+
+ # workaround for suid bug 10346
+ if [ "$s" = "suid" ] ; then
+ sed "s/.*CONFIG_SH_IS_NONE.*$/CONFIG_SH_IS_NONE=y/" -i .config.app.suid
+ fi
+
+ merge_config.sh -m .config.nonapps .config.app.$s
+ oe_runmake busybox_unstripped
+ mv busybox_unstripped busybox.$s
+ oe_runmake busybox.links
+ sort busybox.links > busybox.links.$s
+ rm busybox.links
+ done
+
+ # hard fail if sh is being linked to the suid busybox (detects bug 10346)
+ if grep -q -x "/bin/sh" busybox.links.suid; then
+ bbfatal "busybox suid binary incorrectly provides /bin/sh"
+ fi
+
+ # copy .config.orig back to .config, because the install process may check this file
+ cp .config.orig .config
+ # cleanup
+ rm .config.orig .config.app.suid .config.app.nosuid .config.disable.apps .config.nonapps
+ else
+ oe_runmake busybox_unstripped
+ cp busybox_unstripped busybox
+ oe_runmake busybox.links
+ fi
+}
+
+do_install () {
+ sed -i "s:^/bin/:BASE_BINDIR/:" busybox.links*
+ sed -i "s:^/sbin/:BASE_SBINDIR/:" busybox.links*
+ sed -i "s:^/usr/bin/:BINDIR/:" busybox.links*
+ sed -i "s:^/usr/sbin/:SBINDIR/:" busybox.links*
+
+ # Move arch/link to BINDIR to match coreutils
+ sed -i "s:^BASE_BINDIR/arch:BINDIR/arch:" busybox.links*
+ sed -i "s:^BASE_BINDIR/link:BINDIR/link:" busybox.links*
+
+ sed -i "s:^BASE_BINDIR/:${base_bindir}/:" busybox.links*
+ sed -i "s:^BASE_SBINDIR/:${base_sbindir}/:" busybox.links*
+ sed -i "s:^BINDIR/:${bindir}/:" busybox.links*
+ sed -i "s:^SBINDIR/:${sbindir}/:" busybox.links*
+
+ install -d ${D}${sysconfdir}/init.d
+
+ if ! grep -q "CONFIG_FEATURE_INDIVIDUAL=y" ${B}/.config; then
+ # Install ${base_bindir}/busybox, and the ${base_bindir}/sh link so the postinst script
+ # can run. Let update-alternatives handle the rest.
+ install -d ${D}${base_bindir}
+ if [ "${BUSYBOX_SPLIT_SUID}" = "1" ]; then
+ install -m 4755 ${B}/busybox.suid ${D}${base_bindir}
+ install -m 0755 ${B}/busybox.nosuid ${D}${base_bindir}
+ install -m 0644 ${S}/busybox.links.suid ${D}${sysconfdir}
+ install -m 0644 ${S}/busybox.links.nosuid ${D}${sysconfdir}
+ if grep -q "CONFIG_SH_IS_ASH=y" ${B}/.config; then
+ ln -sf busybox.nosuid ${D}${base_bindir}/sh
+ fi
+ # Keep a default busybox for people who want to invoke busybox directly.
+ # This is also useful for the on device upgrade. Because we want
+ # to use the busybox command in postinst.
+ ln -sf busybox.nosuid ${D}${base_bindir}/busybox
+ else
+ if grep -q "CONFIG_FEATURE_SUID=y" ${B}/.config; then
+ install -m 4755 ${B}/busybox ${D}${base_bindir}
+ else
+ install -m 0755 ${B}/busybox ${D}${base_bindir}
+ fi
+ install -m 0644 ${S}/busybox.links ${D}${sysconfdir}
+ if grep -q "CONFIG_SH_IS_ASH=y" ${B}/.config; then
+ ln -sf busybox ${D}${base_bindir}/sh
+ fi
+ # We make this symlink here to eliminate the error when upgrading together
+ # with busybox-syslog. Without this symlink, the opkg may think of the
+ # busybox.nosuid as obsolete and remove it, resulting in dead links like
+ # ${base_bindir}/sed -> ${base_bindir}/busybox.nosuid. This will make upgrading busybox-syslog fail.
+ # This symlink will be safely deleted in postinst, thus no negative effect.
+ ln -sf busybox ${D}${base_bindir}/busybox.nosuid
+ fi
+ else
+ install -d ${D}${base_bindir} ${D}${bindir} ${D}${libdir}
+ cat busybox.links | while read FILE; do
+ NAME=`basename "$FILE"`
+ install -m 0755 "0_lib/$NAME" "${D}$FILE.${BPN}"
+ done
+ # add suid bit where needed
+ for i in `grep -E "APPLET.*BB_SUID_((MAYBE|REQUIRE))" include/applets.h | grep -v _BB_SUID_DROP | cut -f 3 -d '(' | cut -f 1 -d ','`; do
+ find ${D} -name $i.${BPN} -exec chmod a+s {} \;
+ done
+ install -m 0755 0_lib/libbusybox.so.${PV} ${D}${libdir}/libbusybox.so.${PV}
+ ln -sf sh.${BPN} ${D}${base_bindir}/sh
+ ln -sf ln.${BPN} ${D}${base_bindir}/ln
+ ln -sf test.${BPN} ${D}${bindir}/test
+ if [ -f ${D}/linuxrc.${BPN} ]; then
+ mv ${D}/linuxrc.${BPN} ${D}/linuxrc
+ fi
+ install -m 0644 ${S}/busybox.links ${D}${sysconfdir}
+ fi
+
+ if grep -q "CONFIG_SYSLOGD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/syslog ${D}${sysconfdir}/init.d/syslog
+ install -m 644 ${WORKDIR}/syslog-startup.conf ${D}${sysconfdir}/syslog-startup.conf
+ install -m 644 ${WORKDIR}/syslog.conf ${D}${sysconfdir}/syslog.conf
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/syslog ${D}${sysconfdir}/rcS.d/S18syslog
+ fi
+ if grep -q "CONFIG_CROND=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-cron ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_HTTPD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-httpd ${D}${sysconfdir}/init.d/
+ install -d ${D}/srv/www
+ fi
+ if grep -q "CONFIG_UDHCPD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-udhcpd ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_HWCLOCK=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/hwclock.sh ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_UDHCPC=y" ${B}/.config; then
+ install -d ${D}${sysconfdir}/udhcpc.d
+ install -d ${D}${datadir}/udhcpc
+ install -m 0755 ${WORKDIR}/simple.script ${D}${sysconfdir}/udhcpc.d/50default
+ sed -i "s:/SBIN_DIR/:${base_sbindir}/:" ${D}${sysconfdir}/udhcpc.d/50default
+ install -m 0755 ${WORKDIR}/default.script ${D}${datadir}/udhcpc/default.script
+ fi
+ if grep -q "CONFIG_INETD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/inetd ${D}${sysconfdir}/init.d/inetd.${BPN}
+ sed -i "s:/usr/sbin/:${sbindir}/:" ${D}${sysconfdir}/init.d/inetd.${BPN}
+ install -m 0644 ${WORKDIR}/inetd.conf ${D}${sysconfdir}/
+ fi
+ if grep -q "CONFIG_MDEV=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/files-1.33.1/mdev ${D}${sysconfdir}/init.d/mdev
+ if grep "CONFIG_FEATURE_MDEV_CONF=y" ${B}/.config; then
+ install -m 644 ${WORKDIR}/mdev.conf ${D}${sysconfdir}/mdev.conf
+ install -d ${D}${sysconfdir}/mdev
+ install -m 0755 ${WORKDIR}/find-touchscreen.sh ${D}${sysconfdir}/mdev
+ install -m 0755 ${WORKDIR}/mdev-mount.sh ${D}${sysconfdir}/mdev
+ fi
+ fi
+ if grep -q "CONFIG_INIT=y" ${B}/.config && ${@bb.utils.contains('VIRTUAL-RUNTIME_init_manager','busybox','true','false',d)}; then
+ install -D -m 0755 ${WORKDIR}/rcS ${D}${sysconfdir}/init.d/rcS
+ install -D -m 0755 ${WORKDIR}/rcK ${D}${sysconfdir}/init.d/rcK
+ install -D -m 0755 ${WORKDIR}/rcS.default ${D}${sysconfdir}/default/rcS
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ if grep -q "CONFIG_KLOGD=y" ${B}/.config; then
+ install -d ${D}${systemd_unitdir}/system
+ sed 's,@base_sbindir@,${base_sbindir},g' < ${WORKDIR}/busybox-klogd.service.in \
+ > ${D}${systemd_unitdir}/system/busybox-klogd.service
+ fi
+
+ if grep -q "CONFIG_SYSLOGD=y" ${B}/.config; then
+ install -d ${D}${systemd_unitdir}/system
+ sed 's,@base_sbindir@,${base_sbindir},g' < ${WORKDIR}/busybox-syslog.service.in \
+ > ${D}${systemd_unitdir}/system/busybox-syslog.service
+ if [ ! -e ${D}${systemd_unitdir}/system/busybox-klogd.service ] ; then
+ sed -i '/klog/d' ${D}${systemd_unitdir}/system/busybox-syslog.service
+ fi
+ if [ -f ${WORKDIR}/busybox-syslog.default ] ; then
+ install -d ${D}${sysconfdir}/default
+ install -m 0644 ${WORKDIR}/busybox-syslog.default ${D}${sysconfdir}/default/busybox-syslog
+ fi
+ fi
+ fi
+
+ # Remove the sysvinit specific configuration file for systemd systems to avoid confusion
+ if ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'false', 'true', d)}; then
+ rm -f ${D}${sysconfdir}/syslog-startup.conf
+ fi
+}
+
+PTEST_BINDIR = "1"
+
+do_install_ptest () {
+ cp -r ${B}/testsuite ${D}${PTEST_PATH}/
+ # These access the internet which is not guaranteed to work on machines running the tests
+ rm -rf ${D}${PTEST_PATH}/testsuite/wget
+ sort ${B}/.config > ${D}${PTEST_PATH}/.config
+ ln -s /bin/busybox ${D}${PTEST_PATH}/busybox
+}
+
+inherit update-alternatives
+
+ALTERNATIVE_PRIORITY = "50"
+
+python do_package_prepend () {
+ # We need to load the full set of busybox provides from the /etc/busybox.links
+ # Use this to see the update-alternatives with the right information
+
+ dvar = d.getVar('D')
+ pn = d.getVar('PN')
+ def set_alternative_vars(links, target):
+ links = d.expand(links)
+ target = d.expand(target)
+ f = open('%s%s' % (dvar, links), 'r')
+ for alt_link_name in f:
+ alt_link_name = alt_link_name.strip()
+ alt_name = os.path.basename(alt_link_name)
+ # Match coreutils
+ if alt_name == '[':
+ alt_name = 'lbracket'
+ if alt_name == 'klogd' or alt_name == 'syslogd':
+ d.appendVar('ALTERNATIVE_%s-syslog' % (pn), ' ' + alt_name)
+ else:
+ d.appendVar('ALTERNATIVE_%s' % (pn), ' ' + alt_name)
+ d.setVarFlag('ALTERNATIVE_LINK_NAME', alt_name, alt_link_name)
+ if os.path.exists('%s%s' % (dvar, target)):
+ d.setVarFlag('ALTERNATIVE_TARGET', alt_name, target)
+ f.close()
+ return
+
+ if os.path.exists('%s/etc/busybox.links' % (dvar)):
+ set_alternative_vars("${sysconfdir}/busybox.links", "${base_bindir}/busybox")
+ else:
+ set_alternative_vars("${sysconfdir}/busybox.links.nosuid", "${base_bindir}/busybox.nosuid")
+ set_alternative_vars("${sysconfdir}/busybox.links.suid", "${base_bindir}/busybox.suid")
+}
+
+# This part of code is dedicated to the on target upgrade problem. It's known
+# that if we don't make appropriate symlinks before update-alternatives calls,
+# there will be errors indicating missing commands such as 'sed'.
+# These symlinks will later be updated by update-alternatives calls.
+# The update-alternatives.bbclass' postinst script runs firstly before other
+# postinst, but this part of code needs run firstly, so add this funtion.
+python populate_packages_updatealternatives_append() {
+ postinst = """
+test -n 2 > /dev/null || alias test='busybox test'
+if test "x$D" = "x"; then
+ # Remove busybox.nosuid if it's a symlink, because this situation indicates
+ # that we're installing or upgrading to a one-binary busybox.
+ if test -h ${base_bindir}/busybox.nosuid; then
+ rm -f ${base_bindir}/busybox.nosuid
+ fi
+ for suffix in "" ".nosuid" ".suid"; do
+ if test -e ${sysconfdir}/busybox.links$suffix; then
+ while read link; do
+ if test ! -e "$link"; then
+ # we can use busybox here because even if we are using splitted busybox
+ # we've made a symlink from /bin/busybox to /bin/busybox.nosuid.
+ busybox rm -f $link
+ busybox ln -s "${base_bindir}/busybox$suffix" $link
+ fi
+ done < ${sysconfdir}/busybox.links$suffix
+ fi
+ done
+fi
+if grep -q "^${base_bindir}/bash$" $D${sysconfdir}/busybox.links*; then
+ grep -q "^${base_bindir}/bash$" $D${sysconfdir}/shells || echo ${base_bindir}/bash >> $D${sysconfdir}/shells
+fi
+
+"""
+ d.prependVar('pkg_postinst_%s' % pkg, postinst)
+}
+
+pkg_postinst_${PN}_prepend () {
+ # Need path to saved utils, but they may have be removed on upgrade of busybox
+ # Only use shell to get paths. Also capture if busybox was saved.
+ BUSYBOX=""
+ if [ "x$D" = "x" ] ; then
+ for busybox_rmdir in /tmp/busyboxrm-*; do
+ if [ "$busybox_rmdir" != '/tmp/busyboxrm-*' ] ; then
+ export PATH=$busybox_rmdir:$PATH
+ if [ -e $busybox_rmdir/busybox* ] ; then
+ BUSYBOX="$busybox_rmdir/busybox*"
+ fi
+ fi
+ done
+ fi
+}
+
+pkg_postinst_${PN}_append () {
+ # If busybox exists in the remove directory it is because it was the only shell left.
+ if [ "x$D" = "x" ] ; then
+ if [ "x$BUSYBOX" != "x" ] ; then
+ update-alternatives --remove sh $BUSYBOX
+ rm -f $BUSYBOX
+ fi
+ fi
+}
+
+pkg_prerm_${PN} () {
+ # This is so you can make busybox commit suicide - removing busybox with no other packages
+ # providing its files, this will make update-alternatives work, but the update-rc.d part
+ # for syslog, httpd and/or udhcpd will fail if there is no other package providing sh
+ tmpdir=`mktemp -d /tmp/busyboxrm-XXXXXX`
+ ln -s ${base_bindir}/busybox $tmpdir/[
+ ln -s ${base_bindir}/busybox $tmpdir/test
+ ln -s ${base_bindir}/busybox $tmpdir/head
+ ln -s ${base_bindir}/busybox $tmpdir/sh
+ ln -s ${base_bindir}/busybox $tmpdir/basename
+ ln -s ${base_bindir}/busybox $tmpdir/echo
+ ln -s ${base_bindir}/busybox $tmpdir/mv
+ ln -s ${base_bindir}/busybox $tmpdir/ln
+ ln -s ${base_bindir}/busybox $tmpdir/dirname
+ ln -s ${base_bindir}/busybox $tmpdir/rm
+ ln -s ${base_bindir}/busybox $tmpdir/sed
+ ln -s ${base_bindir}/busybox $tmpdir/sort
+ ln -s ${base_bindir}/busybox $tmpdir/grep
+ ln -s ${base_bindir}/busybox $tmpdir/tail
+ export PATH=$PATH:$tmpdir
+
+ # If busybox is the shell, we need to save it since its the lowest priority shell
+ # Register saved bitbake as the lowest priority shell possible as back up.
+ if [ -n "$(readlink -f /bin/sh | grep busybox)" ] ; then
+ BUSYBOX=$(readlink -f /bin/sh)
+ cp $BUSYBOX $tmpdir/$(basename $BUSYBOX)
+ update-alternatives --install /bin/sh sh $tmpdir/$(basename $BUSYBOX) 1
+ fi
+}
+
+pkg_postrm_${PN} () {
+ # Add path to remove dir in case we removed our only grep
+ if [ "x$D" = "x" ] ; then
+ for busybox_rmdir in /tmp/busyboxrm-*; do
+ if [ "$busybox_rmdir" != '/tmp/busyboxrm-*' ] ; then
+ export PATH=$busybox_rmdir:$PATH
+ fi
+ done
+ fi
+
+ if grep -q "^${base_bindir}/bash$" $D${sysconfdir}/busybox.links* && [ ! -e $D${base_bindir}/bash ]; then
+ printf "$(grep -v "^${base_bindir}/bash$" $D${sysconfdir}/shells)\n" > $D${sysconfdir}/shells
+ fi
+}
+
+pkg_prerm_${PN}-syslog () {
+ # remove syslog
+ if test "x$D" = "x"; then
+ if test "$1" = "upgrade" -o "$1" = "remove"; then
+ ${sysconfdir}/init.d/syslog stop || :
+ fi
+ fi
+}
+
+RPROVIDES_${PN} += "${@bb.utils.contains('DISTRO_FEATURES', 'usrmerge', '/bin/sh /bin/ash', '', d)}"
diff --git a/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
new file mode 100755
index 0000000..7a45c61
--- /dev/null
+++ b/patch/17.09_19.00/code/new/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
@@ -0,0 +1,36 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += " \
+ file://0001-write-log-to-zcat-tool.patch \
+"
+
+do_install_append() {
+ install -d ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/ld-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libc-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libthread_db-1.0.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libpthread-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libm-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_hesiod-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_db-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_files-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_compat-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libpcprofile.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_dns-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/librt-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libdl-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libmemusage.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libSegFault.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libresolv-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libutil-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libanl-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnsl-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libBrokenLocale-2.31.so ${ELFS-PATH}/
+}
+
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/libc.so
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mfd/zx234290-core.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mfd/zx234290-core.c
new file mode 100755
index 0000000..6da76d2
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mfd/zx234290-core.c
@@ -0,0 +1,681 @@
+/*
+ * zx234290-core.c -- Device access for ZX234290 PMICs
+ *
+ * Copyright 2016 ZTE Inc.
+ *
+ * Author: yuxiang<yu.xiang5@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/zx234290.h>
+
+#include <linux/debugfs.h>
+#include <asm/uaccess.h>
+
+#include <linux/of_gpio.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/delay.h>
+#include <dma_cfg.h>
+#include <linux/reboot.h>
+
+
+#define USER_RST_TO_NORMAL 1
+
+//#include <mach/peri_cfg.h>
+extern int zx234290_i2c_write_simple(u8 reg, void *src);
+extern int zx234290_i2c_read_simple(u8 reg, void *dest);
+
+//void __iomem * s_poweron_type_addr;
+ unsigned long s_poweron_type_addr;
+
+/*the power on info, boot_reason */
+typedef enum
+{
+ POWER_ON_NORMAL = 0,
+ POWER_ON_FOTA,
+ POWER_ON_CHARGING,
+ POWER_ON_RTC,
+ POWER_ON_RESET,
+ POWER_ON_HDT_TEST,
+ POWER_ON_EXCEPTRESET,
+ POWER_ON_LOCALUPDATE,
+ POWER_ON_BOOST_IN,
+ POWER_ON_AMT,
+ POWER_ON_PRODUCTION,
+ POWER_ON_INVALID,
+}T_ZDrvSys_PowerOn_Type;
+
+static struct resource regulator_resources[] = {
+ {
+ .name = "bulk-error",
+ .start = ZX234290_INT_BUCK_FAUL,
+ .end = ZX234290_INT_BUCK_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "ldo_error",
+ .start = ZX234290_INT_LDO_FAUL,
+ .end = ZX234290_INT_LDO_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource rtc_resources[] = {
+ {
+ .name = "zx234290-rtc-alarm",
+ .start = ZX234290_INT_RTC_ALRM,
+ .end = ZX234290_INT_RTC_ALRM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-min",
+ .start = ZX234290_INT_RTC_MIN,
+ .end = ZX234290_INT_RTC_MIN,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-hour",
+ .start = ZX234290_INT_RTC_HOUR,
+ .end = ZX234290_INT_RTC_HOUR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct resource powerkey_resources[] = {
+ {
+ .name = "zx234290-pwrkey-int",
+ .start = ZX234290_INT_PWRON,
+ .end = ZX234290_INT_PWRON,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+static struct mfd_cell zx234290_cell[] = {
+ {
+ .name = "zx234290-regulators",
+ .num_resources = 2,
+ .resources = ®ulator_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-rtc",
+ .num_resources = 3,
+ .resources = &rtc_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-gpadc",
+ },
+ {
+ .name = "zx234290-powerkey",
+ .num_resources = 1,
+ .resources = &powerkey_resources[0],
+ .id = -1,
+ },
+};
+
+unsigned int boot_reason = POWER_ON_NORMAL;
+struct wakeup_source * adc_wakelock;
+
+unsigned int * get_boot_reason_addr(void)
+{
+ return (unsigned int *)s_poweron_type_addr;
+}
+EXPORT_SYMBOL(get_boot_reason_addr);
+
+static void get_boot_reason(void)
+{
+ //boot_reason = *(unsigned int *)POWERON_TYPE_BASE;
+ if(s_poweron_type_addr){
+ boot_reason = readl(s_poweron_type_addr/*+0xf8*/);
+
+ printk(KERN_INFO "[PMU] get boot_reason = %d from 0x%x.\n",boot_reason,s_poweron_type_addr);
+ }
+ else
+ printk(KERN_INFO "[PMU] boot_reason is unknown.\n");
+}
+
+#if 1
+int zx234290_set_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data |= mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_set_bits);
+
+int zx234290_clear_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data &= ~mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_clear_bits);
+#endif
+
+static inline int zx234290_read(struct zx234290 *zx234290, u8 reg)
+{
+ u8 val;
+ int err;
+
+ err = zx234290->read(zx234290, reg, 1, &val);
+ if (err < 0)
+ return err;
+
+ return val;
+}
+
+static inline int zx234290_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ return zx234290->write(zx234290, reg, 1, &val);
+}
+
+#if 1
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg)
+{
+ int data;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ data = zx234290_read(zx234290, reg);
+ if (data < 0)
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return data;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_read);
+
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290_write(zx234290, reg, val);
+ if (err < 0)
+ dev_err(zx234290->dev, "Write for reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_write);
+#endif
+#if 1
+extern int Zx234290_SetUserReg_PSM(unsigned char data);
+extern void zxic_reset_reason(int reason, const char *cpu, const char *app);
+
+void zx29_restart(const char * cmd)
+{
+ /*set reset value = 1*/
+ unsigned char status = USER_RST_TO_NORMAL;
+
+ printk(KERN_INFO"restart:enter reboot :reset to normal\n");
+ zxic_reset_reason(2, "cap", current->comm);
+
+ Zx234290_SetUserReg_PSM(status);
+}
+
+
+int pmu_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+
+ printk(" pmu reboot,in user,task is: %s\n", current->comm);
+ zx29_restart((char *) ptr);
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block pmu_reboot_notifier = {
+ .notifier_call = pmu_reboot_event
+};
+
+#endif
+
+
+
+int Zx234290_SetVldo6Onoff(void)
+{
+ int ret = 0;
+ u8 reg_addr=0, reg_val=0;
+ reg_addr = 0x21;
+ ret = zx234290_i2c_read_simple(reg_addr,®_val);
+ if (ret) {
+ return -EIO;
+ }
+ reg_val = reg_val&(~(1<<5));
+ ret = zx234290_i2c_write_simple(reg_addr, ®_val);
+ if (ret) {
+ return -EIO;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(Zx234290_SetVldo6Onoff);
+#if 0
+int zx297510_write_pmu_flag_charging(void)
+{
+ int ret = 0;
+ unsigned char reg = 0;
+ ret = zx234290_i2c_read_simple(0xf, ®);
+ reg = reg|0xff;
+ ret += zx234290_i2c_write_simple(0xf, ®);
+ ret = zx234290_i2c_read_simple(0xe, ®);
+ reg = reg|0x3;
+ ret += zx234290_i2c_write_simple(0xe, ®);
+ return ret;
+}
+#endif
+//static void __iomem* PMU_ADDR_VIR;
+//#define GPIO_PMU_PSHOLD ZX29_GPIO_51
+unsigned int gpio_num_pshold;
+
+void zx234290_pshold_pull_down(void)
+{
+ //PMU_ADDR_VIR = ioremap(0x10d6c0,4);
+ //__raw_writel(0x0,PMU_ADDR_VIR);
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,0);
+ else
+ printk("zx234290_pshold_pull_down error\n");
+}
+
+//extern int zx234290_rtc_disable_timer_alarm();
+EXPORT_SYMBOL(zx234290_pshold_pull_down);
+
+/***********yuwei added at 20170523**************/
+void zx234290_pshold_pull_up(void)
+{
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,1);
+ else
+ printk("zx234290_pshold_pull_up error\n");
+}
+/**************/
+
+static int zx234290_set_softon(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+static int zx234290_set_softon_PSM(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+
+static bool debug_stop_poweroff = false;
+module_param(debug_stop_poweroff, bool, 0644);
+//extern void zx29_restart(char str,const char * cmd);
+static void zx234290_power_off(void)
+{
+ //void __iomem *reset_charging_reg;
+ //reset_charging_reg = ZX29_TOP_VA;
+ //zx234290_rtc_disable_timer_alarm();
+ //Zx234290_SetVldo6Onoff();
+ u8 reg_poweron = 0;
+ int ret;
+
+ if(debug_stop_poweroff )
+ {
+ printk(KERN_INFO"debug_stop_poweroff= 0x%x, for debug, bug_on!!!!\n", debug_stop_poweroff);
+ panic("poweroff");
+ }
+ zx234290_set_softon_PSM(0);
+ zx234290_pshold_pull_down();
+#if 1
+ while(1){
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_STSA, ®_poweron);
+ if (ret) {
+ printk(KERN_INFO"power off pmu i2c read err\n");
+ break;
+ }
+ if((reg_poweron&(1<<ZX234290_STATUSA_POWERON_LSH))== 0)
+ break;
+ }
+ mdelay(50);
+ /*reset to charging*/
+ //zx29_restart(NULL,"drv_key reboot");
+#endif
+}
+
+
+#if defined(CONFIG_DEBUG_FS)
+static ssize_t debugfs_regs_write(struct file *file, const char __user *buf,size_t nbytes, loff_t *ppos)
+{
+ struct zx234290 *zx234290 = file->private_data;
+
+ unsigned int val1, val2;
+ u8 reg, value;
+ int ret;
+ char *kern_buf;
+
+ kern_buf = kzalloc(nbytes, GFP_KERNEL);
+
+ if (!kern_buf) {
+ printk(KERN_INFO "zx234290-core: Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ if (copy_from_user(kern_buf, (void __user *)buf, nbytes)) {
+ kfree(kern_buf);
+ return -ENOMEM;
+ }
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, kern_buf,nbytes);
+
+ ret = sscanf(kern_buf, "%x:%x", &val1, &val2);
+ if (ret < 2 || val1 > ZX234290_MAX_REGISTER ) {
+ printk(KERN_INFO "zx234290-core: failed to read user buf, ret=%d, input 0x%x:0x%x\n",
+ ret, val1, val2);
+ kfree(kern_buf);
+ return -EINVAL;
+ }
+ kfree(kern_buf);
+
+ reg = val1 & 0xff;
+ value = val2 & 0xff;
+ printk(KERN_INFO "%s input %x,%x; reg=%x,value=%x\n", __func__, val1, val2, reg, value);
+ ret = zx234290_i2c_write_simple(reg, &value);
+
+ return ret ? ret : nbytes;
+}
+
+static int debugfs_regs_show(struct seq_file *s, void *v)
+{
+ int i;
+ u8 value[ZX234290_MAX_REGISTER];
+ int ret=0;
+ u8 reg_rtc_ctrl2 = 0;
+
+ printk(KERN_INFO "%s\n", __func__);
+ memset(value, 0, sizeof(value));
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++){
+ ret = zx234290_i2c_read_simple(i, &(value[i]));
+ if(ret){
+ printk(KERN_INFO "%s err=%d, break\n", __func__, ret);
+ seq_printf(s, "%s err=%d, break", __func__, ret);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++) {
+ if((i+1)%9 == 0)
+ seq_printf(s, "\n");
+
+ seq_printf(s, "[0x%x]%02x ", i, value[i]);
+ }
+
+ reg_rtc_ctrl2 = value[ZX234290_REG_ADDR_RTC_CTRL2];
+ seq_printf(s, "\nAF=%d,TF=%d,Alarm %s,Timer %s\n",(reg_rtc_ctrl2&0x8),(reg_rtc_ctrl2&0x4),
+ (reg_rtc_ctrl2&0x2)? "enable":"disable",(reg_rtc_ctrl2&0x1)? "enable":"disable");
+ if(value[ZX234290_REG_ADDR_BUCK_FAULT_STATUS]||value[ZX234290_REG_ADDR_LDO_FAULT_STATUS])
+ seq_printf(s, "ldo or bulk fault!!!!!\n ");
+ else
+ seq_printf(s, "no ldo or bulk fault\n ");
+ if(value[ZX234290_REG_ADDR_TIMER_CTRL]&0x80)
+ seq_printf(s, "timer enable\n ");
+ else
+ seq_printf(s, "timer disable\n ");
+
+
+ return ret;
+}
+
+#define DEBUGFS_FILE_ENTRY(name) \
+static int debugfs_##name##_open(struct inode *inode, struct file *file) \
+{\
+return single_open(file, debugfs_##name##_show, inode->i_private); \
+}\
+\
+static const struct file_operations debugfs_##name##_fops = { \
+.owner= THIS_MODULE, \
+.open= debugfs_##name##_open, \
+.write=debugfs_##name##_write, \
+.read= seq_read, \
+.llseek= seq_lseek, \
+.release= single_release, \
+}
+
+DEBUGFS_FILE_ENTRY(regs);
+
+int zx234290_rtc_settimer(int sec);
+
+static int debugfs_adc_get(void *data, u64 *val)
+{
+ switch ((int)data) {
+ case 0:
+ *val = get_battery_voltage();
+ //zx234290_rtc_settimer(10);
+ break;
+ case 1:
+ *val = get_adc1_voltage();
+ break;
+ case 2:
+ *val = get_adc2_voltage();
+ break;
+ default:
+ *val = -1;
+ break;
+ }
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fops_adc_ro, debugfs_adc_get, NULL, "%llumV\n");
+
+static struct dentry *g_pmu_root;
+
+extern u32 int_irq_times;
+extern u32 int_thread_times;
+
+static void debugfs_pmu_init(struct zx234290 *zx234290)
+{
+ struct dentry *root;
+ struct dentry *node;
+ int i;
+
+ if(!zx234290)
+ return;
+ //create root
+ root = debugfs_create_dir("pmu_zx29", NULL);
+ if (!root){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(root));
+ goto err;
+ }
+ //print regs;
+ node = debugfs_create_file("regs", S_IRUGO | S_IWUGO, root, zx234290, &debugfs_regs_fops);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc0;
+ node = debugfs_create_file("adc0", S_IRUGO, root, 0, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc1;
+ node = debugfs_create_file("adc1", S_IRUGO, root, 1, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc2;
+ node = debugfs_create_file("adc2", S_IRUGO, root, 2, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print u32
+ debugfs_create_u32("irq_cnt", S_IRUGO, root, &int_irq_times);
+
+ //print u32
+ debugfs_create_u32("thread_cnt", S_IRUGO, root, &int_thread_times);
+
+ g_pmu_root = (void *)root;
+ return;
+err:
+ dev_err(zx234290->dev, "debugfs_pmu_init err\n");
+}
+
+#endif
+
+
+int zx234290_device_init(struct zx234290 *zx234290)
+{
+ //struct zx234290_board *pmic_plat_data = zx234290->dev->platform_data;
+ enum of_gpio_flags flags;
+ //struct zx234290_platform_data *init_data;
+ int ret;
+ int irq;
+
+ s_poweron_type_addr = (unsigned long)ioremap(POWERON_TYPE_ADDR,0x800);
+ get_boot_reason();
+ /*
+ init_data = kzalloc(sizeof(struct zx234290_platform_data), GFP_KERNEL);
+ if (init_data == NULL)
+ return -ENOMEM;
+ */
+ mutex_init(&zx234290->io_mutex);
+ dev_set_drvdata(zx234290->dev, zx234290);
+
+ ret = mfd_add_devices(zx234290->dev, -1,
+ zx234290_cell, ARRAY_SIZE(zx234290_cell),
+ NULL,0, 0);
+ if (ret < 0)
+ goto err;
+
+ gpio_num_pshold= of_get_gpio_flags(zx234290->dev->of_node, 0, &flags);
+ if (!gpio_is_valid(gpio_num_pshold)) {
+ pr_info("pmu pshold error\n");
+ }
+ gpio_direction_input(gpio_num_pshold);
+
+ //gpio_num_pshold = pmic_plat_data->pshold_gpio_num;//by yuxiang
+ // gpio_func_pshold= pmic_plat_data->pshold_gpio_func;//by yuxiang
+ if (!pm_power_off)
+ pm_power_off = zx234290_power_off;
+
+#ifdef PSHOLD_PULLUP_IN_POWEROFFCHARGING
+ /* CPE MDL don't control ps_hold pin. */
+ if (boot_reason == POWER_ON_CHARGING) {
+ zx234290_pshold_pull_up();
+ }
+#endif
+/***********PJT added **************/
+ zx234290_get_chip_version();
+ adc_wakelock = wakeup_source_register(NULL, "adc_wake");
+ if (!adc_wakelock)
+ return -ENOMEM;
+
+ //init_data->irq = pmic_plat_data->irq;
+ //init_data->irq_base = pmic_plat_data->irq_base;
+ //irq = gpio_to_irq(pmic_plat_data->irq_gpio_num);
+ ret = zx234290_irq_init(zx234290);
+ if (ret < 0)
+ goto err;
+
+ register_reboot_notifier(&pmu_reboot_notifier);
+
+#if defined(CONFIG_DEBUG_FS)
+ debugfs_pmu_init(zx234290);
+#endif
+ //kfree(init_data);
+ return ret;
+
+err:
+ //kfree(init_data);
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+ return ret;
+}
+
+void zx234290_device_exit(struct zx234290 *zx234290)
+{
+#if defined(CONFIG_DEBUG_FS)
+ if(g_pmu_root){
+ printk(KERN_INFO "zx234290_device_exit:debugfs_remove_recursive \n");
+ debugfs_remove_recursive(g_pmu_root);
+ }
+#endif
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+}
+
+
+MODULE_AUTHOR("yuxiang");
+MODULE_DESCRIPTION("ZX234290 chip family multi-function driver");
+MODULE_LICENSE("GPL");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
new file mode 100755
index 0000000..9235ec4
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
@@ -0,0 +1,680 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2014, ÉîÛÚÊÐÖÐÐËͨѶ΢µç×Ó
+*
+* ÎļþÃû³Æ£º emmc_ramdump.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+//#include <common.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/mfd/zx234290.h>
+#include <linux/stddef.h>
+
+
+#define MMC1_REG_BASE 0x1211000
+#define MATRIX_CRM_REG_BASE 0x1306000
+#define CFG_EMMC_CLK_ENUM 400000
+#define CFG_EMMC_CLK_WORK 50000000
+#define CFG_EMMC_CLK_REF 50000000
+
+#define ZXMCI_FIFO_DEPTH 128
+#define MMC_BLOCK_SIZE 512
+
+#define mci_read(base, reg) \
+ (*(volatile u32*)(base + reg))
+#define mci_write(base, reg, value) \
+ (*(volatile u32*)(base+ reg) = (value))
+
+u8 mmc_data_buf[512]={0};
+//CMD register
+//bit6 1=response from card
+//bit7 1=long response from card
+//bit8 1=check response CRC
+//bit9 1=data transfer expect
+//bit12 1=send stop command at the end of data transfer
+//bit13 1=wait for previous data transfer completion before sending command
+#define R1 ((1 << 6) | (1 << 8))
+#define R2 ((1 << 6) | (1 << 7) | (1 << 8))
+#define R3 (1 << 6)
+#define CF_DATA ((1 << 9) | (1 << 12) | (1 << 13))
+#define CF_DATA_WR ((1 << 9)|(1 << 10) | (1 << 12) | (1 << 13))
+
+
+static u32 mmc_rca;
+static u32 block_addr = 1;
+//extern struct dw_mci *dw_mci_host_ptr[2];
+extern u32 * g_reg_base[2];
+struct mmc_cid
+{
+ u32 psn;
+ u8 oid;
+ u8 mid;
+ u8 prv;
+ u8 mdt;
+ char pnm[7];
+};
+
+// ¸´Î»EMMCʱÖÓ
+static void emmc_clk_reset(void)
+{
+return ;
+#if 0
+ volatile u32 *crm = (u32*)MATRIX_CRM_REG_BASE;
+
+ crm[0x50>>2] &= ~(0x7<<8);//bit8~10 000:26Mhz 001:100Mhz
+
+ crm[0x54>>2] |= 0x03 << 4; // clk enable
+
+ udelay(10);
+
+ crm[0x58>>2] |= 0x01 << 1; // reset release
+#endif
+}
+
+// emmc ·¢ËÍÃüÁî
+static int emmc_cmd(u32 cmd, u32 arg, void *resp, u32 flags)
+{
+
+#define ERR_STATUS (1 << 1 | 1 << 6 | 1 << 8) // bit1:response error
+ // bit6:response CRC error
+ // bit8:response timeout
+ volatile u32 i;
+ u32 cmdreg;
+ u32 *response = resp;
+ u32 response_words = 0;
+ // volatile u32 *emmc = (u32*)MMC1_REG_BASE;
+ u32 reg_val = 0;
+ u32 regs_base = g_reg_base[1];
+
+ //printk("(%s) cmd = %d start\n",__func__,cmd);
+
+ //Clear all raw interrupt status
+ reg_val = mci_read(regs_base,0x44);
+ mci_write(regs_base,0x44,reg_val|((u32)-1));
+
+ cmdreg = cmd & 0x3F;
+ cmdreg |= flags|(1 << 29) | 0x80000000;
+
+ if(flags &(1 << 7))
+ {
+ response_words = 4; // long response expected from card
+ }
+ else if(flags & (1 << 6))
+ {
+ response_words = 1; // response expected from card
+ }
+ //send command
+ reg_val = mci_read(regs_base,0x44);
+ mci_write(regs_base,0x44,reg_val|((u32)-1));
+ mci_write(regs_base,0x28,arg);
+ mci_write(regs_base,0x2C,cmdreg);
+
+ // check command done
+ i= 0;
+ do
+ {
+ udelay(10);
+ if(++i > 1000)
+ {
+ printk("SEND CMD FAILED,CMD = %d,reg= 0x%x\n",cmd,mci_read(regs_base,0x44));
+
+ break;
+ }
+
+ } while(!(mci_read(regs_base,0x44) & (1 << 2)));
+
+ // check error
+ if(mci_read(regs_base,0x44) & ERR_STATUS)
+ {
+
+ printk("SEND CMD ERR,reg_0x44=0x%x\n",mci_read(regs_base,0x44));
+ return -1;
+ }
+
+ if(response == NULL)
+ return 0;
+
+ for(i = 0; i < response_words; i++)
+ {
+ response[i]= mci_read(regs_base,(0x30 + i));
+ }
+
+ return 0;
+}
+
+//¸´Î»ËùÓп¨£¬Ê¹Æä½øÈëIDLE״̬
+static u32 emmc_idle_cards(void)
+{
+ int i;
+ u32 ret;
+ u32 regs_base = g_reg_base[1];
+
+ // Reset and initialize all cards
+ ret = (u32)emmc_cmd(0, 0, NULL, (1 << 15));
+ if(ret)
+ {
+ printk("ENTER IDLE ERR\n");
+ return (int)ret;
+ }
+
+ // wait for 80 clock at least
+ for(i = 0; i < 100; i++)
+ {
+ ret = mci_read(regs_base,0x70);
+ }
+
+ return 0;
+}
+
+//·¢ËÍCMD1
+static inline int mmc_send_op_cond(u32 ocr,u32 *rocr)
+{
+ int i;
+ int ret = 0;
+ u32 resp[4];
+
+ // ÖÁÉÙ1s£¬ÕâÀïÉèÖÃΪ4s
+ for(i = 50000; i > 0; i--)
+ {
+ ret = emmc_cmd(1,ocr,resp,R3);
+ if(ret)
+ break;
+
+ if(ocr == 0)
+ break;
+ if(resp[0] & 0x80000000)
+ break;
+
+ udelay(80);
+
+ ret= -1;
+ }
+
+ if(rocr)
+ *rocr = resp[0];
+
+ return ret;
+}
+
+//ö¾ÙEMMC¿¨
+static u32 ramdump_mmc_init_card(struct mmc_cid *cid, u32 ocr)
+{
+ u32 resp[4];
+ u32 rocr;
+
+ // CMD0
+ emmc_idle_cards();
+
+ // CMD1
+ mmc_send_op_cond(ocr/* | (1 << 30)*/, &rocr);
+
+ if((rocr & 0x80000000) != 0)
+ {
+ if((rocr & 0x40000000) == 0)
+ {
+ block_addr = 0;
+ }
+ else
+ {
+ block_addr = 1;
+ }
+ }
+ else
+ {
+ printk("ERR\n");
+ }
+ // CMD2
+ emmc_cmd(2, 0, resp, R2);
+
+ // CMD3
+ // Set RCA of the card that responded
+
+ mmc_rca = 1 << 16;
+ emmc_cmd(3, mmc_rca, resp, R1);
+
+ return 0;
+}
+
+// card detected numbers
+static inline int emmc_card_present(void)
+{
+ u32 regs_base = g_reg_base[1];
+
+ return ((mci_read(regs_base,0x50) & 0x3FFFFFFF) != 0x01);
+}
+
+// ²ÉÓÃCPU¶ÁÈ¡FIFO£¬½ûÖ¹ÖжÏ
+static inline void emmc_init(void)
+{
+ u32 tmp,cardnums;
+ u32 i = 0;
+ u32 reg_val=0;
+ u32 regs_base = g_reg_base[1];
+
+ mci_read(regs_base,0x00) = (0 << 5)|(1 << 1)|(1 << 0); //½ûÖ¹dma //¸´Î»fifo //¸´Î»¿ØÖÆÆ÷
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00)&3);
+
+ cardnums = mci_read(regs_base,0x70)&0x3E;
+ cardnums = (cardnums >> 1) + 1;
+
+ //ÉèÖÃCTRL¼Ä´æÆ÷£¬¶ÔÓÚMMC-Ver3.3-onlyģʽ£¬ÐèÒªÉèÖÃenable_OD_pullupλ¡£
+ mci_write(regs_base,0x00,0x0);
+
+ //¸øCARD¹©µç
+ mci_write(regs_base,0x04,0x01);
+ //µÈ´ýµçÔ´Îȶ¨
+ udelay(500);
+
+ //ÇåÖжÏ״̬¼Ä´æÆ÷£¬ÒÔ¼°ÉèÖÃINTMSK¼Ä´æÆ÷
+ mci_write(regs_base,0x44,((u32)-1));
+ //ÆÁ±ÎËùÓÐÖжϣ¬¸ß16λÊǶÔÓ¦sdio£¬µÍ16λ¶ÔӦÿ¸ö¿¨
+ mci_write(regs_base,0x24,0x00);
+
+ //ÐÞ¸ÄCARDµÄʱÖÓÔ´¡£ÎÒÃÇÓõÄʱÖÓÀ´Ô´ÊÇclksrc0. 2bit¶ÔÓ¦Ò»¸ö¿¨(32/2=16)
+ mci_write(regs_base,0x0C,0x0);
+
+ //ÉèÖÃHOST IPµÄһЩȱʡ²ÎÊý¡£¶ÔÓ¦TMOUT,DEBNCE,FIFOTH¼Ä´æÆ÷
+ mci_write(regs_base,0x14,((u32)-1)); //data_timeout
+ //response_timeout,ĬÈÏ0x40
+ //·´Ìø¼ÆÊý¼Ä´æÆ÷,25ms
+ mci_write(regs_base,0x64,0xFFFFFF);
+
+ //fifo·§ÖµÎªÄ¬ÈÏ
+ tmp = (2 << 28) |(((ZXMCI_FIFO_DEPTH >> 1)-1) << 16) |((ZXMCI_FIFO_DEPTH >> 1) << 0); //dma multiple transaction size,ÄÚ²¿dma//RX WMARK //TX WMARK
+ mci_write(regs_base,0x4c,tmp);
+
+ //SD¿¨ÉϵçÖ®ºó£¬ÔËÐÐÔÚ1BITģʽ£¬ËùÒÔÈ·±£host¹¤×÷ÔÚ1BITģʽ
+ mci_write(regs_base,0x18,0);
+ mci_write(regs_base,0x100,1);
+
+ //ÉèÖÃCTRL¼Ä´æÆ÷£¬ÔÊÐíÖжÏ
+ mci_write(regs_base,0x00,(0 << 5)|(0 << 4)|(1 << 1));// ½ûÖ¹dma // ½ûֹȫ¾ÖÖжÏ// ¸´Î»fifo
+
+ i= 0;
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("FIFO RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00)& 2);
+}
+//¸üÐÂʱÖÓ
+static int emmc_update_clock_reg_only(void)
+{
+ //Ö»ÐèÒªÖÃλbit21,ÒòΪ²»·¢Ë͵½¿¨£¬ËùÒÔ²»»á²úÉúÖжÏ
+ u32 rintsts;
+ u32 repeat = 0;
+ u32 cmdr = (1 << 21)| (1 << 13) | 0x80000000;
+ u32 regs_base = g_reg_base[1];
+
+ do
+ {
+ mci_write(regs_base,0x2c,cmdr);
+ rintsts = mci_read(regs_base,0x44);
+ repeat++;
+ } while(((rintsts & (1 << 12)) != 0) && (repeat < 10));
+
+ if(repeat >= 10)
+ {
+ printk("HW LOCK ERR\n");
+ return -2;
+ }
+
+ repeat = 0;
+
+ while((mci_read(regs_base,0x2C) & 0x80000000) != 0)
+ {
+ udelay(50);
+ if(++repeat >=1000)
+ {
+ printk("UPDATE CLOCK TIMEOUT\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+//ÉèÖÃʱÖÓ
+static inline void emmc_set_clk(u32 clock)
+{
+ u32 clk_div;
+ u32 regs_base = g_reg_base[1];
+
+ //ʱÖӵıà³ÌÁ÷³Ì£¬²Î¿¼IPÊÖ²áP167
+ //È·±£CardûÓÐÔÚ´«ÊäÊý¾Ý
+ //½ûÖ¹ËùÓÐʱÖÓ
+ mci_write(regs_base,0x10,0x0);
+ emmc_update_clock_reg_only();
+ //ÉèÖÃCLKDIV,CLKSRCÁ½¸ö¼Ä´æÆ÷£¬CLKSRC²ÉÓÃĬÈÏÖµ
+ //ÕâÀïÓÃÄ£¿éʱÖÓ2·ÖƵ = 66625000.ÎÒÃǵķÖƵÆ÷¿ÉÒÔ×öµ½2*n(n=255) = 510¸ö·ÖƵ,0=1·ÖƵ
+ //ËùÒÔ×îµÍƵÂÊΪ66625000/510 = 130.637KHz,×î´ó= 66625000.
+ if(clock <= (CFG_EMMC_CLK_REF / 510))
+ {
+ clk_div = 0xff;
+ }
+ else
+ {
+ clk_div = (CFG_EMMC_CLK_REF + clock )/((clock<<1)+1);//ËÄÉáÎåÈë
+ }
+ mci_write(regs_base,0x08,clk_div);
+ emmc_update_clock_reg_only();
+
+ //ÖØÐÂʹÄÜʱÖÓ
+ //»Ö¸´Ê±ÖÓ.¸ß16λ1=µÍ¹¦ºÄģʽ
+ mci_write(regs_base,0x10,0x001);
+ emmc_update_clock_reg_only();
+
+}
+//·¢ËÍEMMC¶ÁÃüÁî
+static s32 zx_mmc_read(u32 src, u8 * dst, u32 size)
+{
+ int ret;
+ u32 resp, data, wordcount, start_addr, fifo_cnt;
+ volatile u32 i= 0;
+ volatile u32 j= 0;
+ u32 *p= (u32 *)dst;
+ u32 regs_base = g_reg_base[1];
+
+ if(size == 0)
+ return -1;
+
+ while((mci_read(regs_base,0x48) & (1 << 9)) != 0)
+ {
+ udelay(10);
+
+ if(++i > 200)
+ break;
+ }
+
+ start_addr = src;
+ data = mci_read(regs_base,0x00) | (1 << 1);
+ mci_write(regs_base,0x00,data);
+ mci_write(regs_base,0x20,size);
+ mci_write(regs_base,0x1C,MMC_BLOCK_SIZE);
+
+ i = 0;
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("FIFO RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00) & 0x02);
+
+
+ if (size > 512)
+ {
+ ret = emmc_cmd(18,start_addr, &resp,(R1 | CF_DATA));
+ if(ret)
+ return -18;
+ }
+ else
+ {
+ ret = emmc_cmd(17,start_addr, &resp,(R1 | CF_DATA));
+ if(ret)
+ return -17;
+ }
+
+ wordcount = 0;
+ do
+ {
+ fifo_cnt =((mci_read(regs_base,0x48) >> 17) & 0x1FFF);
+
+ for(j = 0; j < fifo_cnt; j++)
+ {
+ data = mci_read(regs_base,0x200);
+ *p++= data;
+ wordcount++;
+ }
+
+ } while(wordcount < (size >> 2));
+ udelay(2000);
+
+ return 0;
+
+}
+
+static int zx_mmc_write(u32 blknr, u8 * src_buf, u32 size)
+{
+ int ret;
+ u32 resp, data, wordcount, start_addr, fifo_cnt;
+ volatile u32 i= 0;
+ volatile u32 j= 0;
+ u32 *p= (u32 *)src_buf;
+ u32 regs_base = g_reg_base[1];
+ u32 write_count_per =0;
+
+ if(size == 0)
+ return -1;
+
+ while((mci_read(regs_base,0x48) & (1 << 9)) != 0)
+ {
+ udelay(10);
+
+ if(++i > 200)
+ break;
+ }
+
+ start_addr = blknr;
+ data = mci_read(regs_base,0x00) | (1 << 1);
+ mci_write(regs_base,0x00,data);
+ mci_write(regs_base,0x20,size);
+ mci_write(regs_base,0x1C,MMC_BLOCK_SIZE);
+
+ i = 0;
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("FIFO RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00) & 0x02);
+
+
+ if (size > 512)
+ {
+
+ ret = emmc_cmd(25,start_addr, &resp,(R1 | CF_DATA_WR));
+ if(ret)
+ return -18;
+ }
+ else
+ {
+
+ ret = emmc_cmd(24,start_addr, &resp,(R1 | CF_DATA_WR));
+ if(ret)
+ return -17;
+ }
+
+ wordcount = 0;
+
+ do
+ {
+ fifo_cnt =((mci_read(regs_base,0x48) >> 17) & 0x1FFF);
+ write_count_per = min(((size-wordcount)>>2),(ZXMCI_FIFO_DEPTH-fifo_cnt));
+
+ for(j = 0; j < write_count_per; j++)
+ {
+ mci_write(regs_base,0x200,*p++);
+ wordcount = wordcount+4;
+ }
+
+ } while(size-wordcount);
+
+ udelay(2000);
+
+ return 0;
+
+}
+
+//ÉèÖöÁÊý¾Ý´óС
+int mmc_bread(u64 start_addr, u32 data_size, void *dst)
+{
+ int ret;
+ u32 src = 0;
+ u32 blk_count;
+ u32 remain = 0;
+
+ if((start_addr%MMC_BLOCK_SIZE)||(data_size==0)||(dst==NULL))
+ return -1;//err start addr
+
+ blk_count = data_size/MMC_BLOCK_SIZE;
+ remain = data_size%MMC_BLOCK_SIZE;
+ if(remain)
+ memset(&mmc_data_buf,0x0,MMC_BLOCK_SIZE);
+
+ if(block_addr == 0)
+ src = start_addr;
+ else
+ src = (u32)(start_addr/MMC_BLOCK_SIZE);
+
+ if(blk_count){
+ ret= zx_mmc_read(src, (u8 *) dst, blk_count * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("READ ERR\n");
+ return -1;
+ }
+ }
+
+ if(remain){/*transfer remain*/
+
+ ret= zx_mmc_read(src+blk_count, (u8 *)&mmc_data_buf, 1 * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("READ ERR\n");
+ return -1;
+ }
+ memcpy((dst+blk_count * MMC_BLOCK_SIZE),&mmc_data_buf,remain);
+ }
+
+ return data_size;
+}
+
+int mmc_bwrite(u64 start_addr, u32 data_size, void *src_buf)
+{
+ int ret;
+ u32 start_blk = 0;
+ u32 blk_count;
+ u32 remain = 0;
+ u32 resp[4];
+
+ if((start_addr%MMC_BLOCK_SIZE)||(data_size==0)||(src_buf==NULL))
+ return -1;//err start addr
+
+ blk_count = data_size/MMC_BLOCK_SIZE;
+ remain = data_size%MMC_BLOCK_SIZE;
+ if(remain){
+ memset(&mmc_data_buf,0x00,MMC_BLOCK_SIZE);
+ memcpy(&mmc_data_buf,(src_buf+blk_count*MMC_BLOCK_SIZE),remain);
+ }
+
+ if(block_addr == 0)
+ start_blk = start_addr;
+ else
+ start_blk = (u32)(start_addr/MMC_BLOCK_SIZE);
+
+ if(blk_count){
+ ret= zx_mmc_write(start_blk, (u8 *)src_buf, blk_count * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("WRITE ERR\n");
+ return -1;
+ }
+
+ resp[0]=0;
+ do{
+ emmc_cmd(13, (1<<16), resp, R1);
+ }while(((resp[0] & 0x00001E00) >> 9)!= 4);
+ }
+
+ if(remain){/*transfer remain*/
+
+ ret= zx_mmc_write((start_blk+blk_count), (u8 *)&mmc_data_buf, 1 * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("WRITE remain ERR\n");
+ return -1;
+ }
+
+ resp[0]=0;
+ do{
+ emmc_cmd(13, (1<<16), resp, R1);
+ }while(((resp[0] & 0x00001E00) >> 9)!= 4);
+ }
+ return data_size;
+}
+
+
+// ¶Á4KÊý¾Ý,½öÖ§³Öemmc£¬ºóÐø¿ÉÒÔ¿¼ÂÇ×Ô¶¯Ê¶±ð
+int mmc_ramdump_init(void)
+{
+ struct mmc_cid cid;
+ u32 resp[4];
+ u32 ocr;
+ int ret = 0;
+ block_addr = 0;
+
+ //zDrvPmic_SetNormal_Onoff_PSM(VSD1,PM_DISABLE);
+ //mdelay(10);
+ //zDrvPmic_SetNormal_Onoff_PSM(VSD1,PM_ENABLE);
+ // emmc_clk_reset();
+ emmc_init();
+
+ if(!emmc_card_present())
+ {
+ printk("NO EMMC\n");
+ return -1;
+ }
+
+ emmc_set_clk(CFG_EMMC_CLK_ENUM);
+ emmc_idle_cards();
+
+ ret = mmc_send_op_cond(0, &ocr);
+
+ if(!ret)
+ {
+ ramdump_mmc_init_card(&cid, ocr);
+
+ emmc_cmd(9, mmc_rca, resp, R2);
+
+ ret = emmc_cmd(7, mmc_rca, resp, R1);
+
+ if(ret)
+ {
+ return ret;
+ }
+
+ emmc_cmd(16, 512, resp, R1);
+
+ emmc_set_clk(CFG_EMMC_CLK_WORK);
+ }
+
+// mmc_bread(0, 0, 8, (void *)CFG_LOAD_BASE);
+
+ return 0;
+}
+
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mtd/mtdcore.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mtd/mtdcore.c
new file mode 100755
index 0000000..c07e824
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/mtd/mtdcore.c
@@ -0,0 +1,2378 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Core registration and callback routines for MTD
+ * drivers and users.
+ *
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
+ * Copyright © 2006 Red Hat UK Limited
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/ioctl.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/proc_fs.h>
+#include <linux/idr.h>
+#include <linux/backing-dev.h>
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/reboot.h>
+#include <linux/leds.h>
+#include <linux/debugfs.h>
+#include <linux/nvmem-provider.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include "mtdcore.h"
+
+struct backing_dev_info *mtd_bdi;
+
+#ifdef CONFIG_PM_SLEEP
+
+static int mtd_cls_suspend(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return mtd ? mtd_suspend(mtd) : 0;
+}
+
+static int mtd_cls_resume(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ if (mtd)
+ mtd_resume(mtd);
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mtd_cls_pm_ops, mtd_cls_suspend, mtd_cls_resume);
+#define MTD_CLS_PM_OPS (&mtd_cls_pm_ops)
+#else
+#define MTD_CLS_PM_OPS NULL
+#endif
+
+static struct class mtd_class = {
+ .name = "mtd",
+ .owner = THIS_MODULE,
+ .pm = MTD_CLS_PM_OPS,
+};
+
+static DEFINE_IDR(mtd_idr);
+
+/* These are exported solely for the purpose of mtd_blkdevs.c. You
+ should not use them for _anything_ else */
+DEFINE_MUTEX(mtd_table_mutex);
+EXPORT_SYMBOL_GPL(mtd_table_mutex);
+
+struct mtd_info *__mtd_next_device(int i)
+{
+ return idr_get_next(&mtd_idr, &i);
+}
+EXPORT_SYMBOL_GPL(__mtd_next_device);
+
+static LIST_HEAD(mtd_notifiers);
+
+
+#define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2)
+
+/* REVISIT once MTD uses the driver model better, whoever allocates
+ * the mtd_info will probably want to use the release() hook...
+ */
+static void mtd_release(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ dev_t index = MTD_DEVT(mtd->index);
+
+ /* remove /dev/mtdXro node */
+ device_destroy(&mtd_class, index + 1);
+}
+
+static ssize_t mtd_type_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ char *type;
+
+ switch (mtd->type) {
+ case MTD_ABSENT:
+ type = "absent";
+ break;
+ case MTD_RAM:
+ type = "ram";
+ break;
+ case MTD_ROM:
+ type = "rom";
+ break;
+ case MTD_NORFLASH:
+ type = "nor";
+ break;
+ case MTD_NANDFLASH:
+ type = "nand";
+ break;
+ case MTD_DATAFLASH:
+ type = "dataflash";
+ break;
+ case MTD_UBIVOLUME:
+ type = "ubi";
+ break;
+ case MTD_MLCNANDFLASH:
+ type = "mlc-nand";
+ break;
+ default:
+ type = "unknown";
+ }
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", type);
+}
+static DEVICE_ATTR(type, S_IRUGO, mtd_type_show, NULL);
+
+static ssize_t mtd_flags_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)mtd->flags);
+}
+static DEVICE_ATTR(flags, S_IRUGO, mtd_flags_show, NULL);
+
+static ssize_t mtd_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%llu\n",
+ (unsigned long long)mtd->size);
+}
+static DEVICE_ATTR(size, S_IRUGO, mtd_size_show, NULL);
+
+static ssize_t mtd_erasesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize);
+}
+static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL);
+
+static ssize_t mtd_writesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->writesize);
+}
+static DEVICE_ATTR(writesize, S_IRUGO, mtd_writesize_show, NULL);
+
+static ssize_t mtd_subpagesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int subpagesize = mtd->writesize >> mtd->subpage_sft;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", subpagesize);
+}
+static DEVICE_ATTR(subpagesize, S_IRUGO, mtd_subpagesize_show, NULL);
+
+static ssize_t mtd_oobsize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->oobsize);
+}
+static DEVICE_ATTR(oobsize, S_IRUGO, mtd_oobsize_show, NULL);
+
+static ssize_t mtd_oobavail_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->oobavail);
+}
+static DEVICE_ATTR(oobavail, S_IRUGO, mtd_oobavail_show, NULL);
+
+static ssize_t mtd_numeraseregions_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->numeraseregions);
+}
+static DEVICE_ATTR(numeraseregions, S_IRUGO, mtd_numeraseregions_show,
+ NULL);
+
+static ssize_t mtd_name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", mtd->name);
+}
+static DEVICE_ATTR(name, S_IRUGO, mtd_name_show, NULL);
+
+static ssize_t mtd_ecc_strength_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_strength);
+}
+static DEVICE_ATTR(ecc_strength, S_IRUGO, mtd_ecc_strength_show, NULL);
+
+#define MTD_RECORD_NAME_MAX (16)
+struct zxic_mtd_record
+{
+ char name[MTD_RECORD_NAME_MAX];
+ unsigned int erase_times;
+ unsigned int write_times;
+};
+
+static struct zxic_mtd_record g_zxic_mtd_record; //save data
+static int record_mtd_trigger_flag; // 0 stop record, 1 start record
+
+static ssize_t mtd_bitflip_threshold_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->bitflip_threshold);
+}
+
+static ssize_t mtd_bitflip_threshold_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int bitflip_threshold;
+ int retval;
+
+ retval = kstrtouint(buf, 0, &bitflip_threshold);
+ if (retval)
+ return retval;
+
+ mtd->bitflip_threshold = bitflip_threshold;
+ return count;
+}
+static DEVICE_ATTR(bitflip_threshold, S_IRUGO | S_IWUSR,
+ mtd_bitflip_threshold_show,
+ mtd_bitflip_threshold_store);
+
+static ssize_t mtd_ecc_step_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_step_size);
+
+}
+static DEVICE_ATTR(ecc_step_size, S_IRUGO, mtd_ecc_step_size_show, NULL);
+
+static ssize_t mtd_ecc_stats_corrected_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->corrected);
+}
+static DEVICE_ATTR(corrected_bits, S_IRUGO,
+ mtd_ecc_stats_corrected_show, NULL);
+
+static ssize_t mtd_ecc_stats_errors_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->failed);
+}
+static DEVICE_ATTR(ecc_failures, S_IRUGO, mtd_ecc_stats_errors_show, NULL);
+
+static ssize_t mtd_badblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->badblocks);
+}
+static DEVICE_ATTR(bad_blocks, S_IRUGO, mtd_badblocks_show, NULL);
+
+static ssize_t mtd_bbtblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->bbtblocks);
+}
+static DEVICE_ATTR(bbt_blocks, S_IRUGO, mtd_bbtblocks_show, NULL);
+
+static struct attribute *mtd_attrs[] = {
+ &dev_attr_type.attr,
+ &dev_attr_flags.attr,
+ &dev_attr_size.attr,
+ &dev_attr_erasesize.attr,
+ &dev_attr_writesize.attr,
+ &dev_attr_subpagesize.attr,
+ &dev_attr_oobsize.attr,
+ &dev_attr_oobavail.attr,
+ &dev_attr_numeraseregions.attr,
+ &dev_attr_name.attr,
+ &dev_attr_ecc_strength.attr,
+ &dev_attr_ecc_step_size.attr,
+ &dev_attr_corrected_bits.attr,
+ &dev_attr_ecc_failures.attr,
+ &dev_attr_bad_blocks.attr,
+ &dev_attr_bbt_blocks.attr,
+ &dev_attr_bitflip_threshold.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(mtd);
+
+static const struct device_type mtd_devtype = {
+ .name = "mtd",
+ .groups = mtd_groups,
+ .release = mtd_release,
+};
+
+static int mtd_partid_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partid);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partid_debug);
+
+static int mtd_partname_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partname);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partname_debug);
+
+static struct dentry *dfs_dir_mtd;
+
+static void mtd_debugfs_populate(struct mtd_info *mtd)
+{
+ struct device *dev = &mtd->dev;
+ struct dentry *root;
+
+ if (IS_ERR_OR_NULL(dfs_dir_mtd))
+ return;
+
+ root = debugfs_create_dir(dev_name(dev), dfs_dir_mtd);
+ mtd->dbg.dfs_dir = root;
+
+ if (mtd->dbg.partid)
+ debugfs_create_file("partid", 0400, root, mtd,
+ &mtd_partid_debug_fops);
+
+ if (mtd->dbg.partname)
+ debugfs_create_file("partname", 0400, root, mtd,
+ &mtd_partname_debug_fops);
+}
+
+#ifndef CONFIG_MMU
+unsigned mtd_mmap_capabilities(struct mtd_info *mtd)
+{
+ switch (mtd->type) {
+ case MTD_RAM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ | NOMMU_MAP_WRITE;
+ case MTD_ROM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ;
+ default:
+ return NOMMU_MAP_COPY;
+ }
+}
+EXPORT_SYMBOL_GPL(mtd_mmap_capabilities);
+#endif
+
+static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
+ void *cmd)
+{
+ struct mtd_info *mtd;
+
+ mtd = container_of(n, struct mtd_info, reboot_notifier);
+ mtd->_reboot(mtd);
+
+ return NOTIFY_DONE;
+}
+
+/**
+ * mtd_wunit_to_pairing_info - get pairing information of a wunit
+ * @mtd: pointer to new MTD device info structure
+ * @wunit: write unit we are interested in
+ * @info: returned pairing information
+ *
+ * Retrieve pairing information associated to the wunit.
+ * This is mainly useful when dealing with MLC/TLC NANDs where pages can be
+ * paired together, and where programming a page may influence the page it is
+ * paired with.
+ * The notion of page is replaced by the term wunit (write-unit) to stay
+ * consistent with the ->writesize field.
+ *
+ * The @wunit argument can be extracted from an absolute offset using
+ * mtd_offset_to_wunit(). @info is filled with the pairing information attached
+ * to @wunit.
+ *
+ * From the pairing info the MTD user can find all the wunits paired with
+ * @wunit using the following loop:
+ *
+ * for (i = 0; i < mtd_pairing_groups(mtd); i++) {
+ * info.pair = i;
+ * mtd_pairing_info_to_wunit(mtd, &info);
+ * ...
+ * }
+ */
+int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
+ struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master);
+
+ if (wunit < 0 || wunit >= npairs)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_info)
+ return master->pairing->get_info(master, wunit, info);
+
+ info->group = 0;
+ info->pair = wunit;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info);
+
+/**
+ * mtd_pairing_info_to_wunit - get wunit from pairing information
+ * @mtd: pointer to new MTD device info structure
+ * @info: pairing information struct
+ *
+ * Returns a positive number representing the wunit associated to the info
+ * struct, or a negative error code.
+ *
+ * This is the reverse of mtd_wunit_to_pairing_info(), and can help one to
+ * iterate over all wunits of a given pair (see mtd_wunit_to_pairing_info()
+ * doc).
+ *
+ * It can also be used to only program the first page of each pair (i.e.
+ * page attached to group 0), which allows one to use an MLC NAND in
+ * software-emulated SLC mode:
+ *
+ * info.group = 0;
+ * npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
+ * for (info.pair = 0; info.pair < npairs; info.pair++) {
+ * wunit = mtd_pairing_info_to_wunit(mtd, &info);
+ * mtd_write(mtd, mtd_wunit_to_offset(mtd, blkoffs, wunit),
+ * mtd->writesize, &retlen, buf + (i * mtd->writesize));
+ * }
+ */
+int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
+ const struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+
+ if (!info || info->pair < 0 || info->pair >= npairs ||
+ info->group < 0 || info->group >= ngroups)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_wunit)
+ return mtd->pairing->get_wunit(master, info);
+
+ return info->pair;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit);
+
+/**
+ * mtd_pairing_groups - get the number of pairing groups
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Returns the number of pairing groups.
+ *
+ * This number is usually equal to the number of bits exposed by a single
+ * cell, and can be used in conjunction with mtd_pairing_info_to_wunit()
+ * to iterate over all pages of a given pair.
+ */
+int mtd_pairing_groups(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->pairing || !master->pairing->ngroups)
+ return 1;
+
+ return master->pairing->ngroups;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_groups);
+
+static int mtd_nvmem_reg_read(void *priv, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct mtd_info *mtd = priv;
+ size_t retlen;
+ int err;
+
+ err = mtd_read(mtd, offset, bytes, &retlen, val);
+ if (err && err != -EUCLEAN)
+ return err;
+
+ return retlen == bytes ? 0 : -EIO;
+}
+
+static int mtd_nvmem_add(struct mtd_info *mtd)
+{
+ struct nvmem_config config = {};
+
+ config.id = -1;
+ config.dev = &mtd->dev;
+ config.name = dev_name(&mtd->dev);
+ config.owner = THIS_MODULE;
+ config.reg_read = mtd_nvmem_reg_read;
+ config.size = mtd->size;
+ config.word_size = 1;
+ config.stride = 1;
+ config.read_only = true;
+ config.root_only = true;
+ config.no_of_node = true;
+ config.priv = mtd;
+
+ mtd->nvmem = nvmem_register(&config);
+ if (IS_ERR(mtd->nvmem)) {
+ /* Just ignore if there is no NVMEM support in the kernel */
+ if (PTR_ERR(mtd->nvmem) == -EOPNOTSUPP) {
+ mtd->nvmem = NULL;
+ } else {
+ dev_err(&mtd->dev, "Failed to register NVMEM device\n");
+ return PTR_ERR(mtd->nvmem);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * add_mtd_device - register an MTD device
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Add a device to the list of MTD devices present in the system, and
+ * notify each currently active MTD 'user' of its arrival. Returns
+ * zero on success or non-zero on failure.
+ */
+
+int add_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_notifier *not;
+ int i, error;
+
+ /*
+ * May occur, for instance, on buggy drivers which call
+ * mtd_device_parse_register() multiple times on the same master MTD,
+ * especially with CONFIG_MTD_PARTITIONED_MASTER=y.
+ */
+ if (WARN_ONCE(mtd->dev.type, "MTD already registered\n"))
+ return -EEXIST;
+
+ BUG_ON(mtd->writesize == 0);
+
+ /*
+ * MTD drivers should implement ->_{write,read}() or
+ * ->_{write,read}_oob(), but not both.
+ */
+ if (WARN_ON((mtd->_write && mtd->_write_oob) ||
+ (mtd->_read && mtd->_read_oob)))
+ return -EINVAL;
+
+ if (WARN_ON((!mtd->erasesize || !master->_erase) &&
+ !(mtd->flags & MTD_NO_ERASE)))
+ return -EINVAL;
+
+ /*
+ * MTD_SLC_ON_MLC_EMULATION can only be set on partitions, when the
+ * master is an MLC NAND and has a proper pairing scheme defined.
+ * We also reject masters that implement ->_writev() for now, because
+ * NAND controller drivers don't implement this hook, and adding the
+ * SLC -> MLC address/length conversion to this path is useless if we
+ * don't have a user.
+ */
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION &&
+ (!mtd_is_partition(mtd) || master->type != MTD_MLCNANDFLASH ||
+ !master->pairing || master->_writev))
+ return -EINVAL;
+
+ mutex_lock(&mtd_table_mutex);
+
+ i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL);
+ if (i < 0) {
+ error = i;
+ goto fail_locked;
+ }
+
+ mtd->index = i;
+ mtd->usecount = 0;
+
+ /* default value if not set by driver */
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ int ngroups = mtd_pairing_groups(master);
+
+ mtd->erasesize /= ngroups;
+ mtd->size = (u64)mtd_div_by_eb(mtd->size, master) *
+ mtd->erasesize;
+ }
+
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+
+ mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+ mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+
+ /* Some chips always power up locked. Unlock them now */
+ if ((mtd->flags & MTD_WRITEABLE) && (mtd->flags & MTD_POWERUP_LOCK)) {
+ error = mtd_unlock(mtd, 0, mtd->size);
+ if (error && error != -EOPNOTSUPP)
+ printk(KERN_WARNING
+ "%s: unlock failed, writes may not work\n",
+ mtd->name);
+ /* Ignore unlock failures? */
+ error = 0;
+ }
+
+ /* Caller should have set dev.parent to match the
+ * physical device, if appropriate.
+ */
+ mtd->dev.type = &mtd_devtype;
+ mtd->dev.class = &mtd_class;
+ mtd->dev.devt = MTD_DEVT(i);
+ dev_set_name(&mtd->dev, "mtd%d", i);
+ dev_set_drvdata(&mtd->dev, mtd);
+ of_node_get(mtd_get_of_node(mtd));
+ error = device_register(&mtd->dev);
+ if (error)
+ goto fail_added;
+
+ /* Add the nvmem provider */
+ error = mtd_nvmem_add(mtd);
+ if (error)
+ goto fail_nvmem_add;
+
+ mtd_debugfs_populate(mtd);
+
+ device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
+ "mtd%dro", i);
+
+ pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name);
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+ /* We _know_ we aren't being removed, because
+ our caller is still holding us here. So none
+ of this try_ nonsense, and no bitching about it
+ either. :) */
+ __module_get(THIS_MODULE);
+ return 0;
+
+fail_nvmem_add:
+ device_unregister(&mtd->dev);
+fail_added:
+ of_node_put(mtd_get_of_node(mtd));
+ idr_remove(&mtd_idr, i);
+fail_locked:
+ mutex_unlock(&mtd_table_mutex);
+ return error;
+}
+
+/**
+ * del_mtd_device - unregister an MTD device
+ * @mtd: pointer to MTD device info structure
+ *
+ * Remove a device from the list of MTD devices present in the system,
+ * and notify each currently active MTD 'user' of its departure.
+ * Returns zero on success or 1 on failure, which currently will happen
+ * if the requested device does not appear to be present in the list.
+ */
+
+int del_mtd_device(struct mtd_info *mtd)
+{
+ int ret;
+ struct mtd_notifier *not;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (idr_find(&mtd_idr, mtd->index) != mtd) {
+ ret = -ENODEV;
+ goto out_error;
+ }
+
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->remove(mtd);
+
+ if (mtd->usecount) {
+ printk(KERN_NOTICE "Removing MTD device #%d (%s) with use count %d\n",
+ mtd->index, mtd->name, mtd->usecount);
+ ret = -EBUSY;
+ } else {
+ debugfs_remove_recursive(mtd->dbg.dfs_dir);
+
+ /* Try to remove the NVMEM provider */
+ if (mtd->nvmem)
+ nvmem_unregister(mtd->nvmem);
+
+ device_unregister(&mtd->dev);
+
+ idr_remove(&mtd_idr, mtd->index);
+ of_node_put(mtd_get_of_node(mtd));
+
+ module_put(THIS_MODULE);
+ ret = 0;
+ }
+
+out_error:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+
+/*
+ * Set a few defaults based on the parent devices, if not provided by the
+ * driver
+ */
+static void mtd_set_dev_defaults(struct mtd_info *mtd)
+{
+ if (mtd->dev.parent) {
+ if (!mtd->owner && mtd->dev.parent->driver)
+ mtd->owner = mtd->dev.parent->driver->owner;
+ if (!mtd->name)
+ mtd->name = dev_name(mtd->dev.parent);
+ } else {
+ pr_debug("mtd device won't show a device symlink in sysfs\n");
+ }
+
+ INIT_LIST_HEAD(&mtd->partitions);
+ mutex_init(&mtd->master.partitions_lock);
+}
+
+/**
+ * mtd_device_parse_register - parse partitions and register an MTD device.
+ *
+ * @mtd: the MTD device to register
+ * @types: the list of MTD partition probes to try, see
+ * 'parse_mtd_partitions()' for more information
+ * @parser_data: MTD partition parser-specific data
+ * @parts: fallback partition information to register, if parsing fails;
+ * only valid if %nr_parts > %0
+ * @nr_parts: the number of partitions in parts, if zero then the full
+ * MTD device is registered if no partition info is found
+ *
+ * This function aggregates MTD partitions parsing (done by
+ * 'parse_mtd_partitions()') and MTD device and partitions registering. It
+ * basically follows the most common pattern found in many MTD drivers:
+ *
+ * * If the MTD_PARTITIONED_MASTER option is set, then the device as a whole is
+ * registered first.
+ * * Then It tries to probe partitions on MTD device @mtd using parsers
+ * specified in @types (if @types is %NULL, then the default list of parsers
+ * is used, see 'parse_mtd_partitions()' for more information). If none are
+ * found this functions tries to fallback to information specified in
+ * @parts/@nr_parts.
+ * * If no partitions were found this function just registers the MTD device
+ * @mtd and exits.
+ *
+ * Returns zero in case of success and a negative error code in case of failure.
+ */
+int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
+ struct mtd_part_parser_data *parser_data,
+ const struct mtd_partition *parts,
+ int nr_parts)
+{
+ int ret;
+
+ mtd_set_dev_defaults(mtd);
+
+ if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) {
+ ret = add_mtd_device(mtd);
+ if (ret)
+ return ret;
+ }
+
+ /* Prefer parsed partitions over driver-provided fallback */
+ ret = parse_mtd_partitions(mtd, types, parser_data);
+ if (ret == -EPROBE_DEFER)
+ goto out;
+
+ if (ret > 0)
+ ret = 0;
+ else if (nr_parts)
+ ret = add_mtd_partitions(mtd, parts, nr_parts);
+ else if (!device_is_registered(&mtd->dev))
+ ret = add_mtd_device(mtd);
+ else
+ ret = 0;
+
+ if (ret)
+ goto out;
+
+ /*
+ * FIXME: some drivers unfortunately call this function more than once.
+ * So we have to check if we've already assigned the reboot notifier.
+ *
+ * Generally, we can make multiple calls work for most cases, but it
+ * does cause problems with parse_mtd_partitions() above (e.g.,
+ * cmdlineparts will register partitions more than once).
+ */
+ WARN_ONCE(mtd->_reboot && mtd->reboot_notifier.notifier_call,
+ "MTD already registered\n");
+ if (mtd->_reboot && !mtd->reboot_notifier.notifier_call) {
+ mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
+ register_reboot_notifier(&mtd->reboot_notifier);
+ }
+
+out:
+ if (ret && device_is_registered(&mtd->dev))
+ del_mtd_device(mtd);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_device_parse_register);
+
+/**
+ * mtd_device_unregister - unregister an existing MTD device.
+ *
+ * @master: the MTD device to unregister. This will unregister both the master
+ * and any partitions if registered.
+ */
+int mtd_device_unregister(struct mtd_info *master)
+{
+ int err;
+
+ if (master->_reboot)
+ unregister_reboot_notifier(&master->reboot_notifier);
+
+ err = del_mtd_partitions(master);
+ if (err)
+ return err;
+
+ if (!device_is_registered(&master->dev))
+ return 0;
+
+ return del_mtd_device(master);
+}
+EXPORT_SYMBOL_GPL(mtd_device_unregister);
+
+/**
+ * register_mtd_user - register a 'user' of MTD devices.
+ * @new: pointer to notifier info structure
+ *
+ * Registers a pair of callbacks function to be called upon addition
+ * or removal of MTD devices. Causes the 'add' callback to be immediately
+ * invoked for each MTD device currently present in the system.
+ */
+void register_mtd_user (struct mtd_notifier *new)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ list_add(&new->list, &mtd_notifiers);
+
+ __module_get(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ new->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+}
+EXPORT_SYMBOL_GPL(register_mtd_user);
+
+/**
+ * unregister_mtd_user - unregister a 'user' of MTD devices.
+ * @old: pointer to notifier info structure
+ *
+ * Removes a callback function pair from the list of 'users' to be
+ * notified upon addition or removal of MTD devices. Causes the
+ * 'remove' callback to be immediately invoked for each MTD device
+ * currently present in the system.
+ */
+int unregister_mtd_user (struct mtd_notifier *old)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ module_put(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ old->remove(mtd);
+
+ list_del(&old->list);
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(unregister_mtd_user);
+
+/**
+ * get_mtd_device - obtain a validated handle for an MTD device
+ * @mtd: last known address of the required MTD device
+ * @num: internal device number of the required MTD device
+ *
+ * Given a number and NULL address, return the num'th entry in the device
+ * table, if any. Given an address and num == -1, search the device table
+ * for a device with that address and return if it's still present. Given
+ * both, return the num'th driver only if its address matches. Return
+ * error code if not.
+ */
+struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num)
+{
+ struct mtd_info *ret = NULL, *other;
+ int err = -ENODEV;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (num == -1) {
+ mtd_for_each_device(other) {
+ if (other == mtd) {
+ ret = mtd;
+ break;
+ }
+ }
+ } else if (num >= 0) {
+ ret = idr_find(&mtd_idr, num);
+ if (mtd && mtd != ret)
+ ret = NULL;
+ }
+
+ if (!ret) {
+ ret = ERR_PTR(err);
+ goto out;
+ }
+
+ err = __get_mtd_device(ret);
+ if (err)
+ ret = ERR_PTR(err);
+out:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(get_mtd_device);
+
+
+int __get_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int err;
+
+ if (!try_module_get(master->owner))
+ return -ENODEV;
+
+ if (master->_get_device) {
+ err = master->_get_device(mtd);
+
+ if (err) {
+ module_put(master->owner);
+ return err;
+ }
+ }
+
+ master->usecount++;
+
+ while (mtd->parent) {
+ mtd->usecount++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__get_mtd_device);
+
+/**
+ * get_mtd_device_nm - obtain a validated handle for an MTD device by
+ * device name
+ * @name: MTD device name to open
+ *
+ * This function returns MTD device description structure in case of
+ * success and an error code in case of failure.
+ */
+struct mtd_info *get_mtd_device_nm(const char *name)
+{
+ int err = -ENODEV;
+ struct mtd_info *mtd = NULL, *other;
+
+ mutex_lock(&mtd_table_mutex);
+
+ mtd_for_each_device(other) {
+ if (!strcmp(name, other->name)) {
+ mtd = other;
+ break;
+ }
+ }
+
+ if (!mtd)
+ goto out_unlock;
+
+ err = __get_mtd_device(mtd);
+ if (err)
+ goto out_unlock;
+
+ mutex_unlock(&mtd_table_mutex);
+ return mtd;
+
+out_unlock:
+ mutex_unlock(&mtd_table_mutex);
+ return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(get_mtd_device_nm);
+
+void put_mtd_device(struct mtd_info *mtd)
+{
+ mutex_lock(&mtd_table_mutex);
+ __put_mtd_device(mtd);
+ mutex_unlock(&mtd_table_mutex);
+
+}
+EXPORT_SYMBOL_GPL(put_mtd_device);
+
+void __put_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ while (mtd->parent) {
+ --mtd->usecount;
+ BUG_ON(mtd->usecount < 0);
+ mtd = mtd->parent;
+ }
+
+ master->usecount--;
+
+ if (master->_put_device)
+ master->_put_device(master);
+
+ module_put(master->owner);
+}
+EXPORT_SYMBOL_GPL(__put_mtd_device);
+
+/*
+ * Erase is an synchronous operation. Device drivers are epected to return a
+ * negative error code if the operation failed and update instr->fail_addr
+ * to point the portion that was not properly erased.
+ */
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ u64 mst_ofs = mtd_get_master_ofs(mtd, 0);
+ struct erase_info adjinstr;
+ int ret;
+
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ adjinstr = *instr;
+
+ if (!mtd->erasesize || !master->_erase)
+ return -ENOTSUPP;
+
+ if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!instr->len)
+ return 0;
+
+ ledtrig_mtd_activity();
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ adjinstr.addr = (loff_t)mtd_div_by_eb(instr->addr, mtd) *
+ master->erasesize;
+ adjinstr.len = ((u64)mtd_div_by_eb(instr->addr + instr->len, mtd) *
+ master->erasesize) -
+ adjinstr.addr;
+ }
+
+ adjinstr.addr += mst_ofs;
+
+ if (record_mtd_trigger_flag && (strcmp(mtd->name, g_zxic_mtd_record.name) == 0))
+ g_zxic_mtd_record.erase_times++;
+
+ ret = master->_erase(master, &adjinstr);
+
+ if (adjinstr.fail_addr != MTD_FAIL_ADDR_UNKNOWN) {
+ instr->fail_addr = adjinstr.fail_addr - mst_ofs;
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ instr->fail_addr = mtd_div_by_eb(instr->fail_addr,
+ master);
+ instr->fail_addr *= mtd->erasesize;
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_erase);
+
+/*
+ * This stuff for eXecute-In-Place. phys is optional and may be set to NULL.
+ */
+int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ void **virt, resource_size_t *phys)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ *virt = NULL;
+ if (phys)
+ *phys = 0;
+ if (!master->_point)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ from = mtd_get_master_ofs(mtd, from);
+ return master->_point(master, from, len, retlen, virt, phys);
+}
+EXPORT_SYMBOL_GPL(mtd_point);
+
+/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
+int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unpoint)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+ return master->_unpoint(master, mtd_get_master_ofs(mtd, from), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unpoint);
+
+/*
+ * Allow NOMMU mmap() to directly map the device (if not NULL)
+ * - return the address to which the offset maps
+ * - return -ENOSYS to indicate refusal to do the mapping
+ */
+unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len,
+ unsigned long offset, unsigned long flags)
+{
+ size_t retlen;
+ void *virt;
+ int ret;
+
+ ret = mtd_point(mtd, offset, len, &retlen, &virt, NULL);
+ if (ret)
+ return ret;
+ if (retlen != len) {
+ mtd_unpoint(mtd, offset, retlen);
+ return -ENOSYS;
+ }
+ return (unsigned long)virt;
+}
+EXPORT_SYMBOL_GPL(mtd_get_unmapped_area);
+
+static void mtd_update_ecc_stats(struct mtd_info *mtd, struct mtd_info *master,
+ const struct mtd_ecc_stats *old_stats)
+{
+ struct mtd_ecc_stats diff;
+
+ if (master == mtd)
+ return;
+
+ diff = master->ecc_stats;
+ diff.failed -= old_stats->failed;
+ diff.corrected -= old_stats->corrected;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.failed += diff.failed;
+ mtd->ecc_stats.corrected += diff.corrected;
+ mtd = mtd->parent;
+ }
+}
+
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = buf,
+ };
+ int ret;
+
+ ret = mtd_read_oob(mtd, from, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_read);
+
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = (u8 *)buf,
+ };
+ int ret;
+
+ if (record_mtd_trigger_flag && (strcmp(mtd->name, g_zxic_mtd_record.name) == 0))
+ g_zxic_mtd_record.write_times++;
+
+ ret = mtd_write_oob(mtd, to, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_write);
+
+/*
+ * In blackbox flight recorder like scenarios we want to make successful writes
+ * in interrupt context. panic_write() is only intended to be called when its
+ * known the kernel is about to panic and we need the write to succeed. Since
+ * the kernel is not going to be running for much longer, this function can
+ * break locks and delay to ensure the write succeeds (but not sleep).
+ */
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_panic_write)
+ return -EOPNOTSUPP;
+ if (to < 0 || to >= mtd->size || len > mtd->size - to)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+ if (!len)
+ return 0;
+ if (!master->oops_panic_write)
+ master->oops_panic_write = true;
+
+ return master->_panic_write(master, mtd_get_master_ofs(mtd, to), len,
+ retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_panic_write);
+
+static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs,
+ struct mtd_oob_ops *ops)
+{
+ /*
+ * Some users are setting ->datbuf or ->oobbuf to NULL, but are leaving
+ * ->len or ->ooblen uninitialized. Force ->len and ->ooblen to 0 in
+ * this case.
+ */
+ if (!ops->datbuf)
+ ops->len = 0;
+
+ if (!ops->oobbuf)
+ ops->ooblen = 0;
+
+ if (offs < 0 || offs + ops->len > mtd->size)
+ return -EINVAL;
+
+ if (ops->ooblen) {
+ size_t maxooblen;
+
+ if (ops->ooboffs >= mtd_oobavail(mtd, ops))
+ return -EINVAL;
+
+ maxooblen = ((size_t)(mtd_div_by_ws(mtd->size, mtd) -
+ mtd_div_by_ws(offs, mtd)) *
+ mtd_oobavail(mtd, ops)) - ops->ooboffs;
+ if (ops->ooblen > maxooblen)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtd_read_oob_std(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ from = mtd_get_master_ofs(mtd, from);
+ if (master->_read_oob)
+ ret = master->_read_oob(master, from, ops);
+ else
+ ret = master->_read(master, from, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_write_oob_std(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ to = mtd_get_master_ofs(mtd, to);
+ if (master->_write_oob)
+ ret = master->_write_oob(master, to, ops);
+ else
+ ret = master->_write(master, to, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_io_emulated_slc(struct mtd_info *mtd, loff_t start, bool read,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+ struct mtd_oob_ops adjops = *ops;
+ unsigned int wunit, oobavail;
+ struct mtd_pairing_info info;
+ int max_bitflips = 0;
+ u32 ebofs, pageofs;
+ loff_t base, pos;
+
+ ebofs = mtd_mod_by_eb(start, mtd);
+ base = (loff_t)mtd_div_by_eb(start, mtd) * master->erasesize;
+ info.group = 0;
+ info.pair = mtd_div_by_ws(ebofs, mtd);
+ pageofs = mtd_mod_by_ws(ebofs, mtd);
+ oobavail = mtd_oobavail(mtd, ops);
+
+ while (ops->retlen < ops->len || ops->oobretlen < ops->ooblen) {
+ int ret;
+
+ if (info.pair >= npairs) {
+ info.pair = 0;
+ base += master->erasesize;
+ }
+
+ wunit = mtd_pairing_info_to_wunit(master, &info);
+ pos = mtd_wunit_to_offset(mtd, base, wunit);
+
+ adjops.len = ops->len - ops->retlen;
+ if (adjops.len > mtd->writesize - pageofs)
+ adjops.len = mtd->writesize - pageofs;
+
+ adjops.ooblen = ops->ooblen - ops->oobretlen;
+ if (adjops.ooblen > oobavail - adjops.ooboffs)
+ adjops.ooblen = oobavail - adjops.ooboffs;
+
+ if (read) {
+ ret = mtd_read_oob_std(mtd, pos + pageofs, &adjops);
+ if (ret > 0)
+ max_bitflips = max(max_bitflips, ret);
+ } else {
+ ret = mtd_write_oob_std(mtd, pos + pageofs, &adjops);
+ }
+
+ if (ret < 0)
+ return ret;
+
+ max_bitflips = max(max_bitflips, ret);
+ ops->retlen += adjops.retlen;
+ ops->oobretlen += adjops.oobretlen;
+ adjops.datbuf += adjops.retlen;
+ adjops.oobbuf += adjops.oobretlen;
+ adjops.ooboffs = 0;
+ pageofs = 0;
+ info.pair++;
+ }
+
+ return max_bitflips;
+}
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_ecc_stats old_stats = master->ecc_stats;
+ int ret_code;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ ret_code = mtd_check_oob_ops(mtd, from, ops);
+ if (ret_code)
+ return ret_code;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_read */
+ if (!master->_read_oob && (!master->_read || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ret_code = mtd_io_emulated_slc(mtd, from, true, ops);
+ else
+ ret_code = mtd_read_oob_std(mtd, from, ops);
+
+ mtd_update_ecc_stats(mtd, master, &old_stats);
+
+ /*
+ * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics
+ * similar to mtd->_read(), returning a non-negative integer
+ * representing max bitflips. In other cases, mtd->_read_oob() may
+ * return -EUCLEAN. In all cases, perform similar logic to mtd_read().
+ */
+ if (unlikely(ret_code < 0))
+ return ret_code;
+ if (mtd->ecc_strength == 0)
+ return 0; /* device lacks ecc */
+ //printk("ecc strength = %d.\n",mtd->ecc_strength);
+ //printk("bitflip_threshold = %d.\n",mtd->bitflip_threshold);
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+ return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0;
+}
+EXPORT_SYMBOL_GPL(mtd_read_oob);
+
+int mtd_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ ret = mtd_check_oob_ops(mtd, to, ops);
+ if (ret)
+ return ret;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_write */
+ if (!master->_write_oob && (!master->_write || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ return mtd_io_emulated_slc(mtd, to, false, ops);
+
+ return mtd_write_oob_std(mtd, to, ops);
+}
+EXPORT_SYMBOL_GPL(mtd_write_oob);
+
+/**
+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section
+ * @mtd: MTD device structure
+ * @section: ECC section. Depending on the layout you may have all the ECC
+ * bytes stored in a single contiguous section, or one section
+ * per ECC chunk (and sometime several sections for a single ECC
+ * ECC chunk)
+ * @oobecc: OOB region struct filled with the appropriate ECC position
+ * information
+ *
+ * This function returns ECC section information in the OOB area. If you want
+ * to get all the ECC bytes information, then you should call
+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobecc, 0, sizeof(*oobecc));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->ecc)
+ return -ENOTSUPP;
+
+ return master->ooblayout->ecc(master, section, oobecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
+
+/**
+ * mtd_ooblayout_free - Get the OOB region definition of a specific free
+ * section
+ * @mtd: MTD device structure
+ * @section: Free section you are interested in. Depending on the layout
+ * you may have all the free bytes stored in a single contiguous
+ * section, or one section per ECC chunk plus an extra section
+ * for the remaining bytes (or other funky layout).
+ * @oobfree: OOB region struct filled with the appropriate free position
+ * information
+ *
+ * This function returns free bytes position in the OOB area. If you want
+ * to get all the free bytes information, then you should call
+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobfree, 0, sizeof(*oobfree));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->free)
+ return -ENOTSUPP;
+
+ return master->ooblayout->free(master, section, oobfree);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
+
+/**
+ * mtd_ooblayout_find_region - Find the region attached to a specific byte
+ * @mtd: mtd info structure
+ * @byte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: used to retrieve the ECC position
+ * @iter: iterator function. Should be either mtd_ooblayout_free or
+ * mtd_ooblayout_ecc depending on the region type you're searching for
+ *
+ * This function returns the section id and oobregion information of a
+ * specific byte. For example, say you want to know where the 4th ECC byte is
+ * stored, you'll use:
+ *
+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc);
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte,
+ int *sectionp, struct mtd_oob_region *oobregion,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ int pos = 0, ret, section = 0;
+
+ memset(oobregion, 0, sizeof(*oobregion));
+
+ while (1) {
+ ret = iter(mtd, section, oobregion);
+ if (ret)
+ return ret;
+
+ if (pos + oobregion->length > byte)
+ break;
+
+ pos += oobregion->length;
+ section++;
+ }
+
+ /*
+ * Adjust region info to make it start at the beginning at the
+ * 'start' ECC byte.
+ */
+ oobregion->offset += byte - pos;
+ oobregion->length -= byte - pos;
+ *sectionp = section;
+
+ return 0;
+}
+
+/**
+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific
+ * ECC byte
+ * @mtd: mtd info structure
+ * @eccbyte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: OOB region information
+ *
+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC
+ * byte.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion)
+{
+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion);
+
+/**
+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @buf: destination buffer to store OOB bytes
+ * @oobbuf: OOB buffer
+ * @start: first byte to retrieve
+ * @nbytes: number of bytes to retrieve
+ * @iter: section iterator
+ *
+ * Extract bytes attached to a specific category (ECC or free)
+ * from the OOB buffer and copy them into buf.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf,
+ const u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(buf, oobbuf + oobregion.offset, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @buf: source buffer to get OOB bytes from
+ * @oobbuf: OOB buffer
+ * @start: first OOB byte to set
+ * @nbytes: number of OOB bytes to set
+ * @iter: section iterator
+ *
+ * Fill the OOB buffer with data provided in buf. The category (ECC or free)
+ * is selected by passing the appropriate iterator.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf,
+ u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(oobbuf + oobregion.offset, buf, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category
+ * @mtd: mtd info structure
+ * @iter: category iterator
+ *
+ * Count the number of bytes in a given category.
+ *
+ * Returns a positive value on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section = 0, ret, nbytes = 0;
+
+ while (1) {
+ ret = iter(mtd, section++, &oobregion);
+ if (ret) {
+ if (ret == -ERANGE)
+ ret = nbytes;
+ break;
+ }
+
+ nbytes += oobregion.length;
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes);
+
+/**
+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get ECC bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes);
+
+/**
+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes);
+
+/**
+ * mtd_ooblayout_set_databytes - set data bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: source buffer to get data bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes);
+
+/**
+ * mtd_ooblayout_count_eccbytes - count the number of ECC bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes);
+
+/*
+ * Method to access the protection register area, present in some flash
+ * devices. The user data is one time programmable but the factory data is read
+ * only.
+ */
+int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_fact_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_fact_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info);
+
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_fact_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_fact_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg);
+
+int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_user_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_user_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_user_prot_info);
+
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_user_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg);
+
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ *retlen = 0;
+ if (!master->_write_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ ret = master->_write_user_prot_reg(master, to, len, retlen, buf);
+ if (ret)
+ return ret;
+
+ /*
+ * If no data could be written at all, we are out of memory and
+ * must return -ENOSPC.
+ */
+ return (*retlen) ? 0 : -ENOSPC;
+}
+EXPORT_SYMBOL_GPL(mtd_write_user_prot_reg);
+
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_lock_user_prot_reg(master, from, len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
+
+/* Chip-supported device locking */
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_lock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock);
+
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unlock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_unlock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unlock);
+
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_is_locked)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_is_locked(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_is_locked);
+
+int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isreserved)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isreserved(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isreserved);
+
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isbad)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isbad(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isbad);
+
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ if (!master->_block_markbad)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ ret = master->_block_markbad(master, mtd_get_master_ofs(mtd, ofs));
+ if (ret)
+ return ret;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.badblocks++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_block_markbad);
+
+/*
+ * default_mtd_writev - the default writev method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+static int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ unsigned long i;
+ size_t totlen = 0, thislen;
+ int ret = 0;
+
+ for (i = 0; i < count; i++) {
+ if (!vecs[i].iov_len)
+ continue;
+ ret = mtd_write(mtd, to, vecs[i].iov_len, &thislen,
+ vecs[i].iov_base);
+ totlen += thislen;
+ if (ret || thislen != vecs[i].iov_len)
+ break;
+ to += vecs[i].iov_len;
+ }
+ *retlen = totlen;
+ return ret;
+}
+
+/*
+ * mtd_writev - the vector-based MTD write method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!master->_writev)
+ return default_mtd_writev(mtd, vecs, count, to, retlen);
+
+ return master->_writev(master, vecs, count,
+ mtd_get_master_ofs(mtd, to), retlen);
+}
+EXPORT_SYMBOL_GPL(mtd_writev);
+
+/**
+ * mtd_kmalloc_up_to - allocate a contiguous buffer up to the specified size
+ * @mtd: mtd device description object pointer
+ * @size: a pointer to the ideal or maximum size of the allocation, points
+ * to the actual allocation size on success.
+ *
+ * This routine attempts to allocate a contiguous kernel buffer up to
+ * the specified size, backing off the size of the request exponentially
+ * until the request succeeds or until the allocation size falls below
+ * the system page size. This attempts to make sure it does not adversely
+ * impact system performance, so when allocating more than one page, we
+ * ask the memory allocator to avoid re-trying, swapping, writing back
+ * or performing I/O.
+ *
+ * Note, this function also makes sure that the allocated buffer is aligned to
+ * the MTD device's min. I/O unit, i.e. the "mtd->writesize" value.
+ *
+ * This is called, for example by mtd_{read,write} and jffs2_scan_medium,
+ * to handle smaller (i.e. degraded) buffer allocations under low- or
+ * fragmented-memory situations where such reduced allocations, from a
+ * requested ideal, are allowed.
+ *
+ * Returns a pointer to the allocated buffer on success; otherwise, NULL.
+ */
+void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size)
+{
+ gfp_t flags = __GFP_NOWARN | __GFP_DIRECT_RECLAIM | __GFP_NORETRY;
+ size_t min_alloc = max_t(size_t, mtd->writesize, PAGE_SIZE);
+ void *kbuf;
+
+ *size = min_t(size_t, *size, KMALLOC_MAX_SIZE);
+
+ while (*size > min_alloc) {
+ kbuf = kmalloc(*size, flags);
+ if (kbuf)
+ return kbuf;
+
+ *size >>= 1;
+ *size = ALIGN(*size, mtd->writesize);
+ }
+
+ /*
+ * For the last resort allocation allow 'kmalloc()' to do all sorts of
+ * things (write-back, dropping caches, etc) by using GFP_KERNEL.
+ */
+ return kmalloc(*size, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(mtd_kmalloc_up_to);
+
+#ifdef CONFIG_PROC_FS
+
+/*====================================================================*/
+/* Support for /proc/mtd */
+
+static int mtd_proc_show(struct seq_file *m, void *v)
+{
+ struct mtd_info *mtd;
+
+ seq_puts(m, "dev: size erasesize name\n");
+ mutex_lock(&mtd_table_mutex);
+ mtd_for_each_device(mtd) {
+ seq_printf(m, "mtd%d: %8.8llx %8.8x \"%s\"\n",
+ mtd->index, (unsigned long long)mtd->size,
+ mtd->erasesize, mtd->name);
+ }
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+#endif /* CONFIG_PROC_FS */
+
+/*====================================================================*/
+/* Init code */
+
+static struct backing_dev_info * __init mtd_bdi_init(char *name)
+{
+ struct backing_dev_info *bdi;
+ int ret;
+
+ bdi = bdi_alloc(NUMA_NO_NODE);
+ if (!bdi)
+ return ERR_PTR(-ENOMEM);
+ bdi->ra_pages = 0;
+ bdi->io_pages = 0;
+
+ /*
+ * We put '-0' suffix to the name to get the same name format as we
+ * used to get. Since this is called only once, we get a unique name.
+ */
+ ret = bdi_register(bdi, "%.28s-0", name);
+ if (ret)
+ bdi_put(bdi);
+
+ return ret ? ERR_PTR(ret) : bdi;
+}
+
+static struct proc_dir_entry *proc_mtd;
+
+/* Started by AICoder, pid:5fc9ey6dc555c241432c0bd800e0358e8d683380 */
+static struct proc_dir_entry *proc_record_mtd_name;
+static struct proc_dir_entry *proc_record_mtd_trigger;
+static struct proc_dir_entry *proc_record_mtd_erase_times;
+
+static ssize_t proc_record_mtd_name_read(struct file *file, char __user *user_buffer, size_t count, loff_t *offset) {
+ if (g_zxic_mtd_record.name[0] != '\0')
+ return simple_read_from_buffer(user_buffer, count, offset, g_zxic_mtd_record.name, strlen(g_zxic_mtd_record.name));
+ else
+ return 0;
+}
+
+static ssize_t proc_record_mtd_name_write(struct file *file, const char __user *user_buffer, size_t count, loff_t *offset) {
+ if (count <= 1 || count >= MTD_RECORD_NAME_MAX) {
+ return -EINVAL;
+ }
+
+ if (copy_from_user(g_zxic_mtd_record.name, user_buffer, count)) {
+ return -EFAULT;
+ }
+
+ g_zxic_mtd_record.name[count-1] = '\0'; // last 1 byte 0x0a
+ g_zxic_mtd_record.erase_times = 0;
+ g_zxic_mtd_record.write_times = 0;
+
+ return count;
+}
+
+static ssize_t proc_record_mtd_trigger_read(struct file *file, char __user *user_buffer, size_t count, loff_t *offset) {
+ if (record_mtd_trigger_flag)
+ return simple_read_from_buffer(user_buffer, count, offset, "start\n", 6);
+ else
+ return simple_read_from_buffer(user_buffer, count, offset, "stop\n", 5);
+}
+
+static ssize_t proc_record_mtd_trigger_write(struct file *file, const char __user *user_buffer, size_t count, loff_t *offset) {
+ char buffer[10];
+
+ if (count < 4 || count > 6)
+ return -EINVAL;
+ if (g_zxic_mtd_record.name[0] == '\0')
+ return -EINVAL; // mtd name not set
+ if (copy_from_user(buffer, user_buffer, count))
+ return -EFAULT;
+
+ buffer[count-1] = '\0'; // last 1 byte 0x0a
+ //printk("record mtd trigger:%s\n", buffer);
+
+ if (memcmp(buffer, "start", 5) == 0) {
+ printk(KERN_WARNING "record mtd erase and write start\n");
+ g_zxic_mtd_record.erase_times = 0;
+ g_zxic_mtd_record.write_times = 0;
+ record_mtd_trigger_flag = 1;
+ } else {
+ if (memcmp(buffer, "stop", 4) == 0)
+ {
+ printk(KERN_WARNING "record mtd erase and write stop\n");
+ record_mtd_trigger_flag = 0;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+ }
+
+ return count;
+}
+
+static int proc_record_mtd_erase_times_show(struct seq_file *m, void *v)
+{
+ seq_printf(m, "mtd:%s\n", g_zxic_mtd_record.name);
+ seq_printf(m, "erase_times:%u\n", g_zxic_mtd_record.erase_times);
+ seq_printf(m, "write_times:%u\n", g_zxic_mtd_record.write_times);
+ return 0;
+}
+
+static const struct proc_ops proc_record_mtd_name_fops = {
+ .proc_read = proc_record_mtd_name_read,
+ .proc_write = proc_record_mtd_name_write,
+};
+
+static const struct proc_ops proc_record_mtd_trigger_fops = {
+ .proc_read = proc_record_mtd_trigger_read,
+ .proc_write = proc_record_mtd_trigger_write,
+};
+
+static int zxic_record_proc_init(void)
+{
+ proc_record_mtd_name = proc_create("record_mtd_name", 0666, NULL, &proc_record_mtd_name_fops);
+ if (!proc_record_mtd_name)
+ return -ENOMEM;
+ proc_record_mtd_trigger = proc_create("record_mtd_trigger", 0666, NULL, &proc_record_mtd_trigger_fops);
+ if (!proc_record_mtd_trigger)
+ return -ENOMEM;
+ proc_record_mtd_erase_times = proc_create_single("record_mtd_erase_times", 0, NULL, proc_record_mtd_erase_times_show);
+ if (!proc_record_mtd_erase_times)
+ return -ENOMEM;
+ return 0;
+}
+/* Ended by AICoder, pid:5fc9ey6dc555c241432c0bd800e0358e8d683380 */
+
+static int __init init_mtd(void)
+{
+ int ret;
+
+ ret = class_register(&mtd_class);
+ if (ret)
+ goto err_reg;
+
+ mtd_bdi = mtd_bdi_init("mtd");
+ if (IS_ERR(mtd_bdi)) {
+ ret = PTR_ERR(mtd_bdi);
+ goto err_bdi;
+ }
+
+ proc_mtd = proc_create_single("mtd", 0, NULL, mtd_proc_show);
+
+ if (zxic_record_proc_init() < 0)
+ printk(KERN_ERR "zxic_record_proc_init error\n");
+
+ ret = init_mtdchar();
+ if (ret)
+ goto out_procfs;
+
+ dfs_dir_mtd = debugfs_create_dir("mtd", NULL);
+
+ return 0;
+
+out_procfs:
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ bdi_put(mtd_bdi);
+err_bdi:
+ class_unregister(&mtd_class);
+err_reg:
+ pr_err("Error registering mtd class or bdi: %d\n", ret);
+ return ret;
+}
+
+static void __exit cleanup_mtd(void)
+{
+ debugfs_remove_recursive(dfs_dir_mtd);
+ cleanup_mtdchar();
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ class_unregister(&mtd_class);
+ bdi_put(mtd_bdi);
+ idr_destroy(&mtd_idr);
+}
+
+module_init(init_mtd);
+module_exit(cleanup_mtd);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
+MODULE_DESCRIPTION("Core MTD registration and access routines");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
new file mode 100755
index 0000000..32cb5a5
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
@@ -0,0 +1,2171 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/device.h>
+#include <uapi/linux/sched/types.h>
+#include "zx29_gmac.h"
+
+#define GMAC_RX_WORKER_TH 1
+
+#define gmac_printk(_format, _args...) do{printk(KERN_INFO"gmac," _format "\n",##_args);}while(0)
+
+static u8 zx29_gmac_addr[MAC_ADDR_LENTH] = {0xec,0x1d,0x7f,0xb0,0x2f,0x32};
+static struct tasklet_struct *g_gmac_tasklet = NULL;
+/*struct zx29_gmac_dev *g_gmac_dev = NULL; */ /* no use possible */
+extern void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void* puf);
+extern int gmac_event_init(const char *name);
+static void gmac_hw_deinit(struct net_device *dev);
+//extern void v7_dma_map_area(const void *, size_t, int);
+//extern unsigned long virt_to_phys_ap(unsigned long virt);
+extern void dma_map(const void *addr, size_t len, int flags);
+extern unsigned long virt_to_phys_ap_new(unsigned long virt_addr);
+extern void kobj_gmac_del(struct kobject *kobject);
+
+
+void dump_pkt_trace(unsigned char *data,int len)
+{
+ int i;
+ len = len > 128?128:len;
+ printk("********************\n");
+ for(i=0;i<len;i++){
+ printk("%.2x ",data[i]);
+ if((i&0xf) == 0xf)
+ printk("\n");
+ }
+ printk("\n");
+ printk("********************\n");
+}
+
+static u32 zx29_gmac_get_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+
+ return prv->link.isup;
+}
+
+
+static void gmac_start(void* io)
+{
+ volatile unsigned *gmac = (unsigned*)io;
+
+ mac_int_enable();
+ dma_enable();
+ mac_enable();
+}
+
+static inline int mod_sub(int left, int right, int mod)
+{
+ return (mod - right + left) % mod;
+}
+
+static struct bd_tx *get_txed_bd(struct net_device *ndev)
+{
+ struct bd_tx *d;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int n = priv->txed_bd;
+
+ d = (struct bd_tx *)priv->dma_tx_vir;
+
+
+ if (n == priv->tx_bd_offset)
+ return 0;
+
+ if ( (!d) || (d[n].TDES0 & DMA_OWNER))
+ return 0;
+
+ if (d[n].skb == NULL)
+ return 0;
+
+ priv->txed_bd++;
+ priv->txed_bd %= GMAC_TX_BD_NUM;
+
+ return &d[n];
+}
+
+static inline struct bd_tx *get_tx_bd(struct net_device *ndev)
+{
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+ int n = priv->tx_bd_offset;
+ struct bd_tx *d = (struct bd_tx*)priv->dma_tx_vir;
+
+ if (mod_sub(priv->tx_bd_offset, priv->txed_bd, GMAC_TX_BD_NUM) > GMAC_TX_BD_NUM - 2)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER) {
+ return 0;
+ } else {
+ return &d[n];
+ }
+}
+
+static struct bd_rx *get_rx_bd(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+ int n = prv->rx_bd_offset;
+ struct bd_rx *d = (struct bd_rx*)prv->dma_rx_vir;
+
+ if ((!d) || (d[n].RDES0 & DMA_OWNER))
+ {
+ return 0;
+ }
+ else
+ {
+ return &d[n];
+ }
+}
+
+static void gmac_trig_transmit(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 20) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 6:
+ dma_continue_tx();
+ break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 7:
+ default:
+ break;
+
+ }
+}
+
+static void gmac_trig_receive(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 17) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 4:
+ dma_continue_rx();
+ break;
+ default:
+ break;
+ }
+}
+
+static inline void gmac_update_mac(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned char *mac = (unsigned char*)ndev->dev_addr;
+
+ MAC(0x0044) = mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24;
+ MAC(0x0040) = mac[4] | mac[5] << 8;
+}
+
+static int zx29mii_read(struct mii_bus *bus, int phy_addr, int regnum)
+{
+ unsigned long flags;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 0 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irqsave(&prv->lock,flags);
+ while(mac_mii_is_busy());
+ MAC(0x0010) = val;
+ spin_unlock_irqrestore(&prv->lock,flags);
+
+ while(mac_mii_is_busy());
+
+ return (MAC(0x0014) & 0xFFFF);
+}
+
+static int zx29mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
+{
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 1 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irq(&prv->lock);
+ while(mac_mii_is_busy());
+ MAC(0x0014) = value;
+ MAC(0x0010) = val;
+
+ spin_unlock_irq(&prv->lock);
+
+ while(mac_mii_is_busy());
+
+ return 0;
+}
+
+static int zx29mii_reset(struct mii_bus *bus)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)priv->base_addr;
+
+ gmac_start((void *)priv->base_addr);
+ while (mac_mii_is_busy());
+ return 0;
+}
+
+static inline void zx29_gmac_set_macaddr(struct net_device *ndev)
+{
+ int i = 0;
+#if MAC_ADDR_SET
+ for (i = 0; i < MAC_ADDR_LENTH; i++)
+ ndev->dev_addr[i] = zx29_gmac_addr[i];
+
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ random_ether_addr(ndev->dev_addr);
+#else
+ random_ether_addr(ndev->dev_addr);
+#endif
+}
+
+static void zx29_gmac_tx(struct net_device *ndev)
+{
+ register unsigned status;
+ struct net_device_stats s = ndev->stats;
+ struct bd_tx *tx = get_txed_bd(ndev);
+
+
+ while (tx) {
+ status = tx->TDES0;
+
+ if (tx->TDES0 & ERR_TX_ES) {
+ s.tx_errors++;
+ if(status & ERR_TX_LC) s.tx_carrier_errors++;
+ if(status & ERR_TX_NC) s.tx_carrier_errors++;
+ if(status & ERR_TX_EC) s.tx_window_errors++;
+ if(status & ERR_TX_LATECOL) s.tx_window_errors++;
+ if(status & ERR_TX_UF) s.tx_aborted_errors++;
+ if(status & ERR_TX_ED) s.tx_aborted_errors++;
+ if(status & ERR_TX_JT) s.tx_fifo_errors++;
+ if(status & ERR_TX_FF) s.tx_fifo_errors++;
+
+ printk("%s, status=0x%x, err_cnt=%ld\n", __FUNCTION__,status, s.tx_errors);
+ }
+ dev_kfree_skb_any(tx->skb);
+ tx->skb = NULL;
+ tx = get_txed_bd(ndev);
+
+ }
+
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
+}
+
+static int zx29_gmac_rx(struct net_device *ndev)
+{
+ struct bd_rx *rx;
+ struct sk_buff *skb;
+ struct sk_buff *skb_new;
+ unsigned len;
+ int exhausted = 0;
+
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+
+ rx = get_rx_bd(ndev);
+
+ if(unlikely(!rx)) goto rcv_done;
+
+ while (rx) {
+ if ((rx->RDES0 & ERR_RX_ES) || (rx->RDES0 & ERR_RX_LE)) {
+ ndev->stats.rx_errors++;
+ if(rx->RDES0 & ERR_RX_LE) ndev->stats.rx_length_errors++;
+ if(rx->RDES0 & ERR_RX_OE) ndev->stats.rx_over_errors++;
+ if(rx->RDES0 & ERR_RX_IPC) ndev->stats.rx_frame_errors++;
+ if(rx->RDES0 & ERR_RX_LC) ndev->stats.rx_fifo_errors++;
+ if(rx->RDES0 & ERR_RX_CE) ndev->stats.rx_crc_errors++;
+ } else {
+
+ len = ((rx->RDES0 >> 16) & 0x3FFF) - 4;
+ if(len > (ETH_FRAME_LEN+8)) {
+ ndev->stats.rx_dropped++;
+ goto rx_bd_reset;
+ }
+
+ skb_new = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb_new)) {
+ ndev->stats.rx_dropped++;
+ exhausted++;
+ } else {
+ exhausted = 0;
+ ndev->stats.rx_packets++;
+ ndev->stats.rx_bytes += len;
+
+ dma_sync_single_for_cpu(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_FROM_DEVICE);
+ skb = rx->skb;
+ skb_put(skb, len); /*in fact , use for?*/
+
+// dump_pkt_trace(skb->data, len);
+ skb->protocol = eth_type_trans(skb, ndev);
+ netif_rx(skb);
+
+ skb_reserve(skb_new, NET_IP_ALIGN);
+// rx->dma_buf = virt_to_phys_ap((unsigned long)skb_new->data);
+ rx->dma_buf = virt_to_phys_ap_new((unsigned long)skb_new->data);
+ if(rx->dma_buf == NULL)
+ rx->dma_buf = __pa((unsigned)skb_new->data);
+ rx->skb = skb_new;
+ wmb();
+ dma_sync_single_for_device(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+ }
+ }
+rx_bd_reset:
+ rx->RDES0 = rx->RDES0 | DMA_OWNER;
+ priv->rx_bd_offset++;
+ priv->rx_bd_offset %= GMAC_RX_BD_NUM;
+ wmb();
+
+ if (exhausted >= 10)
+ break;
+ gmac_trig_receive((void*)ndev->base_addr);
+ rx = get_rx_bd(ndev);
+ }
+
+rcv_done:
+
+ gmac_trig_receive((void*)ndev->base_addr);
+
+ return (exhausted > 10);
+}
+
+#ifdef GMAC_RX_WORKER_TH
+static struct task_struct *s_gmac_rx_worker = 0;
+static int ko_remove_flag = 0;
+struct semaphore s_gmac_rx_sem = {0};
+static int gmac_rx_worker(void *dev)
+{
+ struct net_device *ndev = (struct net_device *)dev;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int events = prv->int_event;
+
+ do {
+ down(&s_gmac_rx_sem);
+ if (ko_remove_flag)
+ return 0;
+ events = prv->int_event;
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX)
+ zx29_gmac_rx(ndev);
+
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_TX | INT_ST_RX));
+
+ #ifndef GMAC_NO_INT
+ mac_int_enable();
+ #endif
+ } while(1);
+
+ return 0;
+}
+
+static int zx29_gmac_worker(struct net_device* pnetdev)
+{
+ struct sched_param param = {.sched_priority = 40};
+
+ sema_init(&s_gmac_rx_sem, 0);
+
+ s_gmac_rx_worker = kthread_create(gmac_rx_worker, (void *)pnetdev, "gmac_rx_worker");
+
+ //sched_setscheduler(s_gmac_rx_worker, SCHED_RR, ¶m);
+ wake_up_process(s_gmac_rx_worker);
+
+ return 0;
+}
+
+#endif
+
+#ifndef GMAC_NO_INT
+static irqreturn_t zx29_gmac_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned * gmac = (unsigned *)ndev->base_addr;
+
+ priv->int_event = MAC(0x1014);
+ MAC(0x1014) = priv->int_event;
+
+ mac_int_disable();
+#ifndef GMAC_RX_WORKER_TH
+ tasklet_schedule(&priv->tasklet);
+#else
+ up(&s_gmac_rx_sem);
+#endif
+ return IRQ_HANDLED;
+}
+
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int events = prv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX)
+ zx29_gmac_rx(ndev);
+
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_TX | INT_ST_RX));
+
+ mac_int_enable();
+}
+
+#else
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned events = priv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX) {
+ if (zx29_gmac_rx(ndev))
+ break;
+ }
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_RX | INT_ST_TX));
+}
+
+enum hrtimer_restart gmac_timer_callback(struct hrtimer *timer)
+{
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+
+ hrtimer_forward_now(timer, gmac_schdule_time);
+#ifndef GMAC_RX_WORKER_TH
+ tasklet_schedule(g_gmac_tasklet);
+#else
+ up(&s_gmac_rx_sem);
+#endif
+ return HRTIMER_RESTART;
+}
+#endif
+
+static inline void zx29_gmac_linkisup(struct net_device *dev, int isup)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+
+ priv->link.duplex = phydev->duplex;
+ priv->link.giga = (phydev->speed == 100);
+ if (priv->link.speed != phydev->speed)
+ priv->link.speed = phydev->speed;
+
+
+ priv->link.isup = isup;
+ if (isup)
+ netif_carrier_on(dev);
+ phy_print_status(phydev);
+}
+
+static void zx29_gmac_adjust_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+ volatile unsigned *gmac = (unsigned *)dev->base_addr;
+
+ if (priv->link.isup &&
+ (!phydev->link ||
+ (priv->link.speed != phydev->speed) ||
+ (priv->link.duplex != phydev->duplex))) {
+ priv->link.isup = 0;
+ netif_tx_disable(dev);
+ if (!phydev->link) {
+ netif_carrier_off(dev);
+ phy_print_status(phydev);
+ }
+ }
+
+ if (!priv->link.isup && phydev->link) {
+ if (priv->link.duplex != phydev->duplex) {
+ if (phydev->duplex)
+ mac_set_full_duplex_mode();
+ else
+ mac_set_half_duplex_mode();
+ }
+
+ if (priv->link.giga != (phydev->speed == 100)) {
+ if (phydev->speed == 100)
+ mac_set_speed_100m_mode();
+ else
+ mac_set_speed_10m_mode();
+ }
+ netif_wake_queue(dev);
+ zx29_gmac_linkisup(dev, 1);
+ }
+
+}
+
+static inline int zx29_gmac_phy_start(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *p = NULL;
+ struct mdio_device *mdio_dev = NULL;
+ int ret = 0;
+
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 start
+ int i = 0;
+ for(i = 0;i <= 5;i++)
+ {
+ if (priv->nports == 1) {
+ p = phy_find_first(priv->mii.bus);
+ } else if (priv->rmii_port < PHY_MAX_ADDR) {
+ mdio_dev = priv->mii.bus->mdio_map[priv->rmii_port];
+ p = container_of(mdio_dev, struct phy_device, mdio);
+ }
+
+ if (!p) {
+ if(i == 5){
+ gpio_direction_output(priv->gpio_power[0], 0);
+#ifdef CONFIG_MDIO_C45
+ gpio_direction_output(priv->gpio_power[1], 0);
+#endif
+ }
+ else
+ continue;
+ printk("%s: no PHY found\n", dev->name);
+ return -ENODEV;
+ }
+ else
+ break;
+ }
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 end
+
+ ret = phy_connect_direct(dev, p, zx29_gmac_adjust_link, PHY_INTERFACE_MODE_RMII); /* phy_start_machine */
+ /* supported and advertising */
+ priv->phydev = p;
+ return 0;
+}
+
+
+static int gmac_init_rx_bd(struct net_device *ndev, struct zx29_gmac_dev *priv)
+{
+ struct sk_buff *skb = NULL;
+ struct bd_rx *rx = (struct bd_rx *)priv->dma_rx_vir;
+ int i = 0;
+
+ priv->rx_bd_offset = 0;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ skb = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb)) {
+ gmac_hw_deinit(ndev);
+ return -1;
+ }
+
+ skb_reserve(skb, NET_IP_ALIGN);
+
+ rx[i].RDES0 |= DMA_OWNER; /* when to change? */
+ rx[i].RDES1 = 0;
+ rx[i].RDES1 = GMAC_FRAME_LEN | 1 << 14;
+ rx[i].dma_buf = __pa((unsigned)skb->data); /* __pa ? */
+ rx[i].next = priv->dma_rx_phy + ((i + 1) << 5); /* why phy? */
+ rx[i].skb = skb;
+#if 0
+ if(i%4 != 0)
+ {
+ rx[i].RDES1 |= 0x80000000;
+ }
+#endif
+ dma_sync_single_for_device(&ndev->dev, rx[i].dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+
+ }
+ rx[GMAC_RX_BD_NUM - 1].next = priv->dma_rx_phy;
+ rx[GMAC_RX_BD_NUM - 1].RDES1 = GMAC_FRAME_LEN | 1 << 14 | 1 << 15;
+
+ return 0;
+}
+
+static void gmac_init_tx_bd(struct zx29_gmac_dev *priv)
+{
+ struct bd_tx *tx = (struct bd_tx *)priv->dma_tx_vir;
+ int i = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ tx[i].TDES0 = (1 << 20 | 1 << 30);
+ tx[i].TDES1 = GMAC_FRAME_LEN;
+ tx[i].next = priv->dma_tx_phy + ((i + 1) << 5);
+ }
+
+ tx[GMAC_TX_BD_NUM - 1].next = priv->dma_tx_phy;
+ tx[GMAC_TX_BD_NUM - 1].TDES0 = 1 << 20 | 1 << 21 | 1 << 30;
+
+}
+
+static void gmac_stop(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ dma_clear_tx_fifo();
+ dma_wait_tx_fifo_cleared();
+}
+
+static void gmac_set_speed_duplex(struct net_device *ndev, int speed, int duplex)
+{
+ unsigned val;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+
+ val = MAC(0x0000) | 1 << 11 | 1 << 14;
+ if (SPEED_10 == speed)
+ val &= ~(1 << 14);
+ if (DUPLEX_HALF == duplex) {
+ val &= (~(1 << 11));
+ val |= (1 << 16);
+ }
+ MAC(0x0000) = val;
+}
+
+static void mac_init(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int i = 0, j = 0, mac_rst = 0;
+ unsigned long long mac_time_start = 0;
+ unsigned long long mac_time_end = 0;
+
+ mac_provide_clock();
+#ifdef __DEAD_LOOP_POLL__
+ mac_reset();
+ mac_set_gmii_mode();
+ mac_wait_reset_finished();
+#else
+ mac_time_start = local_clock();
+ for (i = 0; i < MAC_RESET_NUM; i++) {
+ mac_reset();
+ mac_set_mii_mode();
+ for (j = 0; j < MAC_WAIT_TIME; j++) {
+// printk(".");
+ if (!((MAC(0x1000)) & 1)) {
+ mac_time_end = local_clock();
+ printk("ok:time:%llu ns\n", mac_time_end - mac_time_start);
+ mac_rst = 1;
+ goto mac_reset_option;
+ }
+ udelay(100);
+ }
+ }
+ mac_time_end = local_clock();
+mac_reset_option:
+ if(!mac_rst)
+ printk("gmac reset failed!time:%llu us\n", mac_time_end - mac_time_start);
+#endif
+ while(mac_mii_is_busy());
+}
+
+static void gmac_hw_deinit(struct net_device *ndev)
+{
+ int i;
+ struct bd_rx *rx_bd;
+ struct bd_tx *tx_bd;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ gmac_stop((void *)ndev->base_addr);
+
+ if (priv->dma_rx_phy) {
+ rx_bd = (struct bd_rx *)priv->dma_rx_vir;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ if (rx_bd[i].skb)
+ dev_kfree_skb_any(rx_bd[i].skb);
+ }
+
+ tx_bd = (struct bd_tx *)priv->dma_tx_vir;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ if (tx_bd[i].skb)
+ dev_kfree_skb_any(tx_bd[i].skb);
+ }
+ }
+
+ dma_set_tx_buffer(0); //设置首个BD的缓冲区为0；
+ dma_set_rx_buffer(0);
+
+ priv->rx_bd_offset = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+ priv->dma_rx_phy = 0;
+ priv->dma_rx_vir = 0;
+ priv->dma_tx_phy = 0;
+ priv->dma_tx_vir = 0;
+
+}
+
+static int gmac_hw_init(struct net_device *ndev)
+{
+ int ret = -1;
+ unsigned val;
+
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (priv->dma_rx_phy)
+ gmac_hw_deinit(ndev);
+
+ priv->dma_rx_vir = priv->dma_rx_vir_init;
+ priv->dma_rx_phy = priv->dma_rx_phy_init;
+ priv->dma_tx_vir = priv->dma_rx_vir + GMAC_RX_BUF_LEN;
+ priv->dma_tx_phy = priv->dma_rx_phy + GMAC_RX_BUF_LEN; /* ifconfig up, clear fifo*/
+
+ memset(priv->dma_rx_vir, 0, GMAC_BUF_LEN);
+
+ ret = gmac_init_rx_bd(ndev, priv);
+ if (ret < 0) {
+ printk("hw_net_init,init_rx_bd fail\n");
+ return ret;
+ }
+ gmac_init_tx_bd(priv);
+
+ mac_init(ndev);
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ val = MAC(0x1000);
+ val &= ~(0x3F << 8);
+ val |= (0x10 << 8);
+ MAC(0x1000) = val;
+
+ dma_set_rx_buffer(priv->dma_rx_phy);
+ dma_set_tx_buffer(priv->dma_tx_phy);
+
+ mac_int_clear(0x0001FFFF);
+ while (mac_mii_is_busy());
+
+ gmac_set_speed_duplex(ndev, priv->phydev->speed, priv->phydev->duplex);
+
+ mac_rece_all_data();
+
+ gmac_start((void *)ndev->base_addr);
+ return 0;
+}
+
+static int zx29_gmac_open(struct net_device *ndev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ unsigned long flags;
+ int ret;
+ int err = 0;
+#ifdef GMAC_NO_INT
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time;
+#endif
+ err = phy_read_status(priv->phydev); /*interal, phy drv provide*/
+ if (err < 0)
+ return err;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->link.speed = 0;
+
+ zx29_gmac_linkisup(ndev, priv->phydev->link);
+
+ ret = gmac_hw_init(ndev);
+ if(ret) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+
+// netif_carrier_on(ndev);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ phy_start(priv->phydev);
+
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+ if (priv->timer)
+ hrtimer_start(priv->timer, gmac_schdule_time, HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+
+ printk("TSP zx29 gmac net open\n");
+
+ return 0;
+}
+
+static int zx29_gmac_stop(struct net_device *ndev)
+{
+ unsigned long flags = 0;
+ int ret = 0;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (!priv->stopped) {
+ spin_lock_irqsave(&priv->lock, flags);
+#ifdef GMAC_NO_INT
+ ret = hrtimer_cancel(priv->timer);
+ if (ret < 0) {
+ BUG_ON(1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+#endif
+
+ priv->stopped = 1;
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ phy_stop(priv->phydev);
+ gmac_hw_deinit(ndev);
+
+ memset(&ndev->stats, 0, sizeof(struct net_device_stats));
+ spin_unlock_irqrestore(&priv->lock, flags);
+ printk("TSP zx29 gmac net stop\n");
+ }
+ return 0;
+}
+
+
+static netdev_tx_t zx29_gmac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ unsigned long flags;
+ unsigned len;
+ struct sk_buff *skb_old;
+ struct bd_tx *tx;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (0 == priv->link.isup) {
+ dev_kfree_skb_any(skb);
+ printk("TSP zx29 gmac xmit phy not link\n");
+ return NETDEV_TX_OK; /* ? */
+ }
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if(priv->stopped)
+ {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+
+ printk("zx_net_start_xmit when stopped\n");
+
+ return NETDEV_TX_OK;
+ }
+
+ tx = get_tx_bd(ndev);
+
+ if (!tx) {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ priv->tx_bd_offset++;
+ priv->tx_bd_offset %= GMAC_TX_BD_NUM;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ if(skb->len > ETH_FRAME_LEN + 4) /* why 4*/
+ printk("TSP zx29 gmac start xmit len too long\n");
+
+// v7_dma_map_area(skb->data, skb->len, DMA_TO_DEVICE);
+ dma_map(skb->data, skb->len, DMA_TO_DEVICE);
+ if (NULL == skb)
+ BUG_ON(1);
+
+ len = MIN(skb->len, GMAC_FRAME_LEN - NET_IP_ALIGN);
+
+ tx->TDES0 |= (0x07 << 28);
+// tx->dma_buf = virt_to_phys_ap((unsigned long)skb->data);
+ tx->dma_buf = virt_to_phys_ap_new((unsigned long)skb->data);
+
+ if(tx->dma_buf == NULL)
+ tx->dma_buf = virt_to_phys((unsigned)skb->data);
+ tx->skb = skb;
+
+ tx->TDES1 = len;
+ tx->TDES0 |= DMA_OWNER;
+
+ wmb();
+ ndev->stats.tx_bytes += len;
+ ndev->stats.tx_packets++;
+/* ndev->trans_start = jiffies; */
+
+
+ gmac_trig_transmit((void*)ndev->base_addr);
+// dump_pkt_trace(skb->data, len);
+// printk("[%s]\n", __func__);
+
+ return NETDEV_TX_OK;
+}
+
+static void zx29_gmac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ genphy_update_link(priv->phydev);
+#endif
+ priv->link.isup = priv->phydev->link;
+
+ if (0 == priv->link.isup) {
+ printk("TSP zx29 gmac net timeout phy not link\n"); // PHY 未连接
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ } else {
+ printk("TSP zx29 gmac net timeout phy linked\n");
+ gmac_trig_transmit(ndev);
+ gmac_trig_receive(ndev);
+
+ netif_carrier_on(ndev);
+ netif_wake_queue(ndev);
+/* ndev->trans_start = jiffies; */ /* modify */
+ ndev->stats.tx_errors++;
+ ndev->stats.tx_dropped++;
+ }
+}
+
+void __iomem *base_clk = NULL;
+void __iomem *base_phy_release = NULL;
+
+static int zx29_gmac_phy_disable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+
+ enum of_gpio_flags flags;
+ unsigned long flag;
+ int gpio = 0;
+ int ret = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if (ndev && !priv->stopped) {
+ if (netif_running(ndev)) {
+
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+ printk("[%s] netif_running\n", __func__);
+
+ gpio_direction_output(priv->gpio_power[0], 0);
+
+ gmac_stop((void*)ndev->base_addr);
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+// netif_device_detach(ndev);
+ }
+ pm_relax(&pdev->dev);
+ // printk("[%s] sleep\n");
+ }
+#endif
+ //printk("[%s] exit\n", __func__);
+ return 0;
+}
+
+static int zx29_gmac_phy_enable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ int ret = 0;
+ int status = 0;
+ int islink = 0;
+ unsigned int num= 0;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if(ndev && priv->stopped) {
+ pm_stay_awake(&pdev->dev);
+ if( netif_running(ndev)) {
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+// netif_device_attach(ndev);
+ }
+ }
+#endif
+ return 0;
+}
+
+#define C45_READ 1
+#define C45_WRITE 0
+static int zx29_c22_2_c45(struct phy_device *phydev, int addr, u16 devad, u32 regnum, int rw, int write_val)
+{
+ int val = 0;
+ phy_lock_mdio_bus(phydev);
+ /* Write the desired MMD Devad */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL, devad);
+ /* Write the desired MMD register address */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, regnum);
+ /* Select the Function : DATA with no post increment */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL,
+ devad | MII_MMD_CTRL_NOINCR);
+ /* Read the content of the MMD's selected register */
+ if (rw == C45_READ)
+ val = __mdiobus_read(phydev->mdio.bus, addr, MII_MMD_DATA);
+ else
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, write_val);
+ phy_unlock_mdio_bus(phydev);
+
+ return val;
+}
+
+static int zx29_c45_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
+{
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ u16 val = mii_data->val_in;
+ bool change_autoneg = false;
+ int prtad, devad, reg_num;
+
+ switch (cmd) {
+ case SIOCGMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);//phy id
+ devad = mdio_phy_id_devad(mii_data->phy_id);//dev id / mmd
+ reg_num = mii_data->reg_num;
+ mii_data->val_out = zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_READ, 0);
+ return 0;
+
+ case SIOCSMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);
+ devad = mdio_phy_id_devad(mii_data->phy_id);
+ reg_num = mii_data->reg_num;
+
+ if (prtad == phydev->mdio.addr) {
+ switch (devad) {
+ case MII_BMCR:
+ if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) {
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_DISABLE;
+ if (val & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ if (val & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (val & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else phydev->speed = SPEED_10;
+ }
+ else {
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_ENABLE;
+ }
+ break;
+ case MII_ADVERTISE:
+ mii_adv_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ case MII_CTRL1000:
+ mii_ctrl1000_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+
+ zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_WRITE, val);
+
+ if (prtad == phydev->mdio.addr &&
+ devad == MII_BMCR &&
+ val & BMCR_RESET)
+ return phy_init_hw(phydev);
+
+ if (change_autoneg)
+ return phy_start_aneg(phydev);
+
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int zx29_gmac_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ int is_c45 = mdio_phy_id_is_c45(mii_data->phy_id);
+
+ if (!(netif_running(ndev)))
+ return -EINVAL;
+ if (!priv->phydev)
+ return -EINVAL;
+ if (cmd == SIOCDISABLEPHY)
+ return zx29_gmac_phy_disable(ndev->dev.parent);
+
+ if (cmd == SIOCENABLEPHY)
+ return zx29_gmac_phy_enable(ndev->dev.parent);
+
+ if (is_c45)
+ return zx29_c45_mii_ioctl(priv->phydev, ifr, cmd);
+
+ return phy_mii_ioctl(priv->phydev, ifr, cmd);
+}
+
+static int eth_change_mtu(struct net_device *ndev, int new_mtu)
+{
+ if (new_mtu < 68 || new_mtu > ETH_DATA_LEN)
+ return -EINVAL;
+ ndev->mtu = new_mtu;
+ return 0;
+}
+
+static int zx29_gmac_set_mac_address(struct net_device *ndev, void *p)
+{
+ int ret = eth_mac_addr(ndev, p);
+ if (!ret) {
+ gmac_update_mac(ndev);
+ printk(" zx29 gmac set mac addr ok\n");
+ }
+ return ret;
+}
+
+
+static int zx29_gmac_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ unsigned long flag;
+
+ if(ndev) {
+ if(netif_running(ndev)) {
+// netif_device_detach(ndev);
+// gmac_stop((void*)ndev->base_addr);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ phy_stop(priv->phydev);
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+
+ printk("[%s] netif_running\n", __func__);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gmac_stop((void*)ndev->base_addr);
+#else
+ gmac_stop((void*)ndev->base_addr);
+ gpio_direction_output(priv->gpio_power[0], 0);
+#endif
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+#endif
+ }
+ }
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_sleep_state(&pdev->dev);
+#endif
+ return 0;
+}
+
+static int zx29_gmac_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_default_state(&pdev->dev);
+#endif
+ if(ndev) {
+ if(netif_running(ndev)) {
+// gmac_start((void*)ndev->base_addr);
+// netif_device_attach(ndev);
+// zx29_gmac_phy_enable(dev);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+
+ phy_start(priv->phydev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+#endif
+
+ }
+ }
+ return 0;
+}
+
+static const struct ethtool_ops zx29_gmac_ethtool_ops = {
+ .get_link = zx29_gmac_get_link,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ /* other func */
+};
+
+static const struct net_device_ops zx29_gmac_netdev_ops = {
+ .ndo_open = zx29_gmac_open,
+ .ndo_stop = zx29_gmac_stop,
+ .ndo_start_xmit = zx29_gmac_start_xmit,
+ .ndo_tx_timeout = zx29_gmac_tx_timeout,
+ .ndo_do_ioctl = zx29_gmac_ioctl,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = zx29_gmac_set_mac_address,
+};
+
+
+
+ssize_t show_fun(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ int status = 0;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ printk("MAC(1000) :0x%x\n", MAC(0x1000));
+ printk("MAC(1004) :0x%x\n", MAC(0x1004));
+ printk("MAC(1008) :0x%x\n", MAC(0x1008));
+ printk("MAC(100c) :0x%x\n", MAC(0x100c));
+ printk("MAC(1010) :0x%x\n", MAC(0x1010));
+ printk("MAC(1014) int status:0x%x\n", MAC(0x1014));
+ printk("MAC(1018) :0x%x\n", MAC(0x1018));
+ printk("MAC(101c) :0x%x\n", MAC(0x101c));
+ printk("MAC(0000) :0x%x\n", MAC(0x0000));
+ printk("MAC(0004) :0x%x\n", MAC(0x0004));
+ printk("MAC(0010) :0x%x\n", MAC(0x0010));
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 1);
+ printk("phy status:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 0, 1);
+ printk("phy status port0:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 1, 1);
+ printk("phy status port1:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 2, 1);
+ printk("phy status port2:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 3, 1);
+ printk("phy status port3:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 4, 1);
+ printk("phy status port4:0x%x\n", status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 20);
+ status |= 0x4;
+ mdiobus_write(priv->phydev->mdio.bus, 21, 20, status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 21);
+ printk("phy status loop port:0x%x\n", status);
+
+
+ return 0;
+}
+
+ssize_t store_fun(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ printk("[%s]", __func__);
+ return 1;
+}
+
+
+ssize_t mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x", &rd_wt, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ return count;
+}
+
+
+ssize_t free_mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t free_mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ int phy_addr = 8;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x,%x", &rd_wt, &phy_addr, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, phy_addr, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,phy_addr,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ return count;
+}
+
+extern int debug_on;
+ssize_t debug_on_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if (ret < 1) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input %d\n",
+ ret,val);
+ return count;
+ }
+ debug_on = val;
+ return count;
+}
+
+ssize_t debug_on_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (debug_on)
+ memcpy(buf, "on", 3);
+ else
+ memcpy(buf, "off", 4);
+ return 0;
+}
+
+/*jb.qi add for gamc power down on 20231116 start*/
+
+extern int gmac_power = 1;
+int gmac_power_flag = 0;
+
+ssize_t gmac_power_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if(ret < 1)
+ {
+ printk(KERN_INFO "gmac: failed ti read user buf, ret=%d, input %d\n", ret,val);
+ return count;
+ }
+ gmac_power = val;
+ gpio_direction_output(gmac_power_flag, val);
+ return count;
+}
+
+ssize_t gmac_power_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ if(gmac_power)
+ memcpy(buf, "on",3);
+ else
+ memcpy(buf, "off", 4);
+
+ printk("gmac_power %s\n", buf);
+ return 0;
+
+}
+/*jb.qi add for gamc power down on 20231116 end */
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 start*/
+static int mode_type = -1;
+static int enter_only_one = 0;
+
+ssize_t gmac_master_or_slave_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///read mode_type
+ ret = sscanf(buf, "%d", &mode_type);
+ if (ret < 1) {
+ printk(KERN_ERR "Please enter the number 0-3 to enable the corresponding mode \n"
+ "Enter values in the non-0-3 range to get pattern description \n");
+ return count;
+ }
+
+ ///Judgment model
+ if (mode_type < 0 || mode_type > 3) {
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ return ret ? ret : count;
+ }
+
+ ///Set the Ethernet slave mode
+ if (mode_type == 0) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val & (~BIT(14)));
+ }
+ ///Set the Ethernet master mode
+ else if (mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val | BIT(14));
+ }
+ return count;
+}
+
+ssize_t gmac_master_or_slave_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int len = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///Reentrant prevention
+ if(enter_only_one == 1)
+ {
+ return 0;
+ }
+ enter_only_one = 1;
+
+ ///Read the network master/slave
+ if (mode_type == 0 || mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e) & BIT(14);
+ if(val)
+ memcpy(buf, "Master\n",7);
+ else
+ memcpy(buf, "Slave\n", 6);
+
+ printk(KERN_DEBUG "mode_type %d - gmac_master_or_slave is %s\n", mode_type, buf);
+
+ }
+ ///Obtain the cable quality SQI value
+ else if(mode_type == 2){
+ mmd = 0x1;
+ reg = 0x8B10;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "0x%x\n", val);
+ sprintf(buf, "SQI : 0x%x\n", val);
+ printk(KERN_DEBUG "mode_type %d - SQI is 0x%x", mode_type, val);
+
+ }
+ ///Obtain short circuit, open circuit and normal connection of VCT
+ else if(mode_type == 3){
+ ///--TDR Enable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, BIT(14) | BIT(12));
+ msleep(10);
+ ///--Read VCT
+ mmd = 0x1;
+ reg = 0x8B02;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ printk(KERN_DEBUG "Open status: %s - Short status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ sprintf(buf, "Open status: %s\nShort status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ reg = 0x8B01;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "%sDistance status: 0x%x\n", buf, val);
+ printk(KERN_DEBUG "mode_type %d - Distance status is 0x%x\n", mode_type, val);
+
+ ///--TDR Disable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, 0);
+
+ }
+ ///Get model help information
+ else{
+ sprintf(buf, "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ }
+ enter_only_one = 0;
+ return strlen(buf);
+
+}
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 end */
+
+/*zw.wang add a new interface to obtain the PHY link status on 20250226 begin*/
+ssize_t phy_pma_link_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int val = 0;
+ struct platform_device *pdev = to_platform_device(dev);
+ if (!pdev) {
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__,
+ pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if (!ndev) {
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__,
+ ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if (!priv) {
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__,
+ priv);
+ return -1;
+ }
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d,0x1);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e,0x1);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d,0x4000 | 0x1);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr,0x0e);
+ sprintf(buf, "link : %s\n", (val & BIT(2)) ? "yes":"no");
+ return strlen(buf);
+}
+
+/*zw.wang add a new interface to obtain the PHY link status on 20250226 end*/
+
+static DEVICE_ATTR(gmac_test, 0664, show_fun, store_fun);
+static DEVICE_ATTR(mdio_test, 0664, mdio_show, mdio_store);
+static DEVICE_ATTR(free_mdio, 0664, free_mdio_show, free_mdio_store);
+static DEVICE_ATTR(debug_on, 0664, debug_on_show, debug_on_store);
+static DEVICE_ATTR(gmac_power, 0664, gmac_power_show, gmac_power_store);//jb.qi add for gamc power down on 20231116
+static DEVICE_ATTR(gmac_master_or_slave, 0664, gmac_master_or_slave_show, gmac_master_or_slave_store);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+static DEVICE_ATTR_RO(phy_pma_link); //zw.wang add a new interface to obtain the PHY link status on 20250226
+
+static int zx29_gmac_probe(struct platform_device *pdev)
+{
+ struct zx29_gmac_dev *prv = NULL;
+ struct net_device *ndev = alloc_etherdev(sizeof(struct zx29_gmac_dev));
+ volatile unsigned int *gmac = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ int ret = -1;
+ unsigned long i;
+ struct mii_bus *mb;
+ struct resource *iomem;
+ void __iomem *base = NULL;
+ struct pinctrl *pctrl;
+ struct pinctrl_state *state0;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ char board_name[128] = {"init_failed"};
+
+ printk("[%s] #########zx29_gmac_probe begin.\n", __func__);
+ if (!ndev)
+ return -ENOMEM;
+
+ device_create_file(&pdev->dev, &dev_attr_gmac_test);
+ device_create_file(&pdev->dev, &dev_attr_mdio_test);
+ device_create_file(&pdev->dev, &dev_attr_free_mdio);
+ device_create_file(&pdev->dev, &dev_attr_debug_on);
+ device_create_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_create_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+ device_create_file(&pdev->dev, &dev_attr_phy_pma_link); //zw.wang add a new interface to obtain the PHY link status on 20250226
+
+ prv = netdev_priv(ndev);
+ memset(prv, 0, sizeof(*prv));
+ prv->stopped = 1;
+
+ pctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(pctrl)) {
+ dev_warn(&pdev->dev, "Failed to get test pins");
+ pctrl = NULL;
+ goto errirq;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ state0 = pinctrl_lookup_state(pctrl, "state0");
+#else
+ state0 = pinctrl_lookup_state(pctrl, "default");
+#endif
+ if (IS_ERR(state0)) {
+ dev_err(&pdev->dev, "TEST: missing state0\n");
+ goto pinctrl_init_end;
+ }
+
+ if (pinctrl_select_state(pctrl, state0) < 0) {
+ dev_err(&pdev->dev, "setting state0 failed\n");
+ goto pinctrl_init_end;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ prv->gpio_power[2] = of_get_gpio_flags(pdev->dev.of_node, 2, &flags);
+ ret = gpio_request(prv->gpio_power[2], "phy_power"); /* gpio 51 */
+ gpio_direction_output(prv->gpio_power[2], 1);
+ mdelay(15);
+#endif
+
+ prv->gpio_power[0] = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
+ ret = gpio_request(prv->gpio_power[0], "gmac_power"); /* gpio 83/124 */
+ gpio_direction_output(prv->gpio_power[0], 1);
+ mdelay(15);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ prv->gpio_power[1] = of_get_gpio_flags(pdev->dev.of_node, 1, &flags);
+ ret = gpio_request(prv->gpio_power[1], "phy_rst"); /* gpio 63 */
+ gpio_direction_output(prv->gpio_power[1], 0);
+ mdelay(10);
+ gpio_direction_output(prv->gpio_power[1], 1);
+ mdelay(15);
+#endif
+
+ SET_NETDEV_DEV(ndev, &pdev->dev); //if not, will panic
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ gmac_power_flag = prv->gpio_power[0];//jb.qi add for gamc power down on 20231116
+ ndev->base_addr = base;/*iomem->start;*/
+ if (!ndev->base_addr)
+ return -ENXIO;
+
+#ifndef GMAC_NO_INT
+ ndev->irq = platform_get_irq(pdev, 0);
+#endif
+ ndev->netdev_ops = &zx29_gmac_netdev_ops;
+ ndev->ethtool_ops = &zx29_gmac_ethtool_ops;
+
+ gmac = (unsigned *)ndev->base_addr;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ spin_lock_init(&prv->lock);
+
+
+/* wake_lock_init(&prv->wake_lock, WAKE_LOCK_SUSPEND, "gmac_pm"); //what replace?
+ wake_lock(&prv->wake_lock); */
+ device_init_wakeup(&pdev->dev, true);
+
+
+ zx29_gmac_set_macaddr(ndev);
+
+#ifndef GMAC_NO_INT
+ ret = request_irq(ndev->irq, zx29_gmac_interrupt, 0, ndev->name, ndev);
+ if (ret) {
+ printk(KERN_ERR "irq request failed: %d\n", ndev->irq);
+ goto errirq;
+ }
+#endif
+
+ ret = register_netdev(ndev);
+ if (ret) {
+ printk(KERN_ERR "error registering device %s\n",
+ ndev->name);
+ goto errdev;
+ }
+
+#ifdef GMAC_RX_WORKER_TH
+ zx29_gmac_worker(ndev);//gmac_rx_worker
+#endif
+
+ of_property_read_u32(np, "port-nums", &prv->nports);
+ of_property_read_u32(np, "rmii-ports", &prv->rmii_port);
+ prv->base_addr = ndev->base_addr;
+
+ prv->netdev = ndev;
+
+ mb = mdiobus_alloc();
+ if (!mb) {
+ printk(KERN_ERR "error allocating mii bus\n");
+ goto errmii;
+ }
+ mb->name = "zx29_gmac_mii";
+ mb->read = zx29mii_read;
+ mb->write = zx29mii_write;
+ mb->reset = zx29mii_reset;
+ mb->priv = prv;
+ snprintf(mb->id, MII_BUS_ID_SIZE, "%s-%x", "zx29_gmac", 0);
+ of_property_read_u32(np, "port-mask", &mb->phy_mask);
+/* mb->irq = &prv->mii.irq[0]; */
+ for (i = 0; i < PHY_MAX_ADDR; i++) {
+ int n = platform_get_irq(pdev, i + 1); /* devtrrr modify */
+ if (n < 0)
+ n = PHY_POLL;
+ prv->mii.irq[i] = n;
+ mb->irq[i] = n;
+ }
+
+ base = devm_platform_ioremap_resource(pdev, 2);
+ gmac_set_clk();
+ base_clk = base;
+
+ base = devm_platform_ioremap_resource(pdev, 1);
+ gmac_phy_release();
+ base_phy_release = base;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ mdelay(500);
+#else
+ mdelay(10); //zw.wang@20240306 modify. Here, the jl3103 is set as an example, and other phy peripherals need to be optimized according to different reset stability times
+#endif
+
+ ret = mdiobus_register(mb);
+ if (ret < 0) {
+ printk("[%s] mdiobus register failed!\n", __func__);
+ goto errmdioregister;
+ }
+
+ prv->mii.bus = mb;
+ ret = zx29_gmac_phy_start(ndev);
+ if (ret)
+ goto errphystart;
+
+ if (!(prv->phydev->phy_id == 0x00000000 || prv->phydev->phy_id == 0xffffffff)) {
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ pm_stay_awake(&pdev->dev);
+#endif
+ strcpy(board_name, "cpe");
+
+ printk("[%s] phy id = 0x%x \n", __func__, prv->phydev->phy_id);
+ printk("set gmac wakelock!\n");
+ } else {
+ strcpy(board_name, "mdl");
+ netif_device_detach(ndev);
+ }
+
+ platform_set_drvdata(pdev, ndev);
+
+ tasklet_init(&prv->tasklet, zx29_gmac_tasklet, (unsigned long)ndev);
+ g_gmac_tasklet = &prv->tasklet;
+
+
+ prv->dma_rx_vir = dma_alloc_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_phy, GFP_KERNEL);
+ if (!prv->dma_rx_vir) { // null, ndev->dev.parent difference?
+ BUG_ON(1);
+ goto errphystart;
+ }
+
+ prv->dma_rx_phy_init = prv->dma_rx_phy;
+ prv->dma_rx_vir_init = prv->dma_rx_vir;
+ prv->dma_tx_phy = prv->dma_rx_phy + GMAC_RX_BUF_LEN;
+ prv->dma_tx_vir = prv->dma_rx_vir + GMAC_RX_BUF_LEN;
+
+#ifdef GMAC_NO_INT
+ sema_init(&prv->sem, 0);
+
+ prv->timer = kzalloc(sizeof(struct hrtimer), GFP_KERNEL);
+ if (!prv->timer) {
+ BUG_ON(1);
+ goto errmalloc;
+ }
+ hrtimer_init(prv->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+
+ prv->timer->function = gmac_timer_callback;
+#endif
+
+ gmac_event_init(board_name);
+/* g_gmac_dev = prv; */ /* no use possible*/
+
+ printk("[%s] probe end\n", __func__);
+ return 0;
+errmalloc:
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_vir, prv->dma_rx_phy);
+
+
+errphystart:
+ mdiobus_unregister(mb);
+
+
+errmdioregister:
+ mdiobus_free(mb);
+
+errmii:
+ unregister_netdev(ndev);
+
+errdev:
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+
+pinctrl_init_end:
+
+errirq:
+ free_netdev(ndev);
+
+ printk("#########zx29_gmac_probe fail.\n");
+ return ret;
+}
+
+static int zx29_gmac_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ volatile unsigned *gmac = NULL;
+ if (ndev) {
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+
+// gpio_direction_output(priv->gpio_power[0], 1);
+// msleep(500);
+// unregister_netdev(ndev);
+
+ phy_disconnect(priv->phydev);
+ unregister_netdev(ndev);
+
+ kobj_gmac_del(NULL);
+
+ mdiobus_unregister(priv->mii.bus);
+ mdiobus_free(priv->mii.bus);
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+
+#ifdef GMAC_RX_WORKER_TH
+ ko_remove_flag = 1;
+ up(&s_gmac_rx_sem);
+#endif
+
+ tasklet_disable(&priv->tasklet);
+ tasklet_kill(&priv->tasklet);
+
+ if (priv->dma_rx_vir_init)
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, priv->dma_rx_vir_init, priv->dma_rx_phy_init);
+
+ pm_relax(&pdev->dev);
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ gpio_free(priv->gpio_power[1]);
+#endif
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gpio_free(priv->gpio_power[0]);
+
+ device_remove_file(&pdev->dev, &dev_attr_gmac_test);
+ device_remove_file(&pdev->dev, &dev_attr_mdio_test);
+ device_remove_file(&pdev->dev, &dev_attr_free_mdio);
+ device_remove_file(&pdev->dev, &dev_attr_debug_on);
+ device_remove_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_remove_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+ device_remove_file(&pdev->dev, &dev_attr_phy_pma_link); //zw.wang add a new interface to obtain the PHY link status on 20250226
+ }
+ return 0;
+}
+
+static struct dev_pm_ops zx29_gmac_pm_ops = {
+ .suspend = zx29_gmac_suspend,
+ .resume = zx29_gmac_resume,
+};
+
+static const struct of_device_id gmac_match_table[] = {
+ {.compatible = "zte, zx29_gmac",},
+};
+
+static struct platform_driver zx29_gmac_driver = {
+ .probe = zx29_gmac_probe,
+ .remove = zx29_gmac_remove,
+ .driver = {
+ .name = "zx29_gmac",
+ .owner = THIS_MODULE,
+ .pm = &zx29_gmac_pm_ops,
+ .of_match_table = gmac_match_table,
+ },
+};
+
+static int __init zx29_gmac_init(void)
+{
+ return platform_driver_register(&zx29_gmac_driver);
+}
+
+static void __exit zx29_gmac_exit(void)
+{
+ printk("[%s] start exit!\n", __func__);
+ platform_driver_unregister(&zx29_gmac_driver);
+}
+
+module_init(zx29_gmac_init);
+module_exit(zx29_gmac_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ZX29 on chip Ethernet driver");
+MODULE_AUTHOR("zhu jianlinag <zhu.jianliang@zte.com.cn>");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
new file mode 100755
index 0000000..6df9cfd
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
@@ -0,0 +1,299 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include "zx29_gmac.h"
+
+extern void v7_dma_map_area(const void *, size_t, int);
+extern unsigned long virt_to_phys_ap(unsigned long virt);
+
+void dma_map(const void * addr, size_t len, int flags)
+{
+ v7_dma_map_area(addr, len, flags);
+}
+EXPORT_SYMBOL(dma_map);
+
+unsigned long virt_to_phys_ap_new(unsigned long virt_addr)
+{
+ return virt_to_phys_ap(virt_addr);
+}
+EXPORT_SYMBOL(virt_to_phys_ap_new);
+
+int debug_on = 0;
+EXPORT_SYMBOL(debug_on);
+
+struct kset *kset_gmac;
+struct kobject *gmackobj = NULL;
+struct kobject *typekobj = NULL;
+char type[8] = { 0 };
+u32 zx29_gmac_plug_state[3] = {0}; /* 0:phy 1:sw_wan 2:sw_lan */
+
+static struct attribute gmac_phy_plug_attr = {
+ .name = "eth_phy_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_wan_plug_attr = {
+ .name = "eth_sw_wan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_lan_plug_attr = {
+ .name = "eth_sw_lan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute board_type = {
+ .name = "type",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute *gmac_status_attrs[] = {
+ &gmac_phy_plug_attr,
+ &gmac_sw_wan_plug_attr,
+ &gmac_sw_lan_plug_attr,
+ &board_type,
+ NULL,
+};
+
+ssize_t kobj_gmac_show(struct kobject *kobject,struct attribute *attr,char *buf)
+{
+ unsigned link =0;
+
+ if(!strcmp(attr->name,"eth_phy_state")) {
+ if(zx29_gmac_plug_state[0] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_wan_state")) {
+ if(zx29_gmac_plug_state[1] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_lan_state")) {
+ if(zx29_gmac_plug_state[2] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if (!strcmp(attr->name,"type")) {
+ sprintf(buf, "%s", type);
+ } else {
+ printk("invalidate attr name.\n");
+ }
+
+ return strlen(buf);
+}
+
+ssize_t kobj_gmac_store(struct kobject *kobject, struct attribute *attr, const char *buf, size_t size)
+{
+ unsigned int value = 0;
+ value = simple_strtoul(buf, NULL, 4);
+ printk("attrname: %s.\n", attr->name);
+ if (!strcmp(attr->name, "eth_phy_state")) {
+ zx29_gmac_plug_state[0] = value;
+ } else if (!strcmp(attr->name,"eth_sw_wan_state")) {
+ zx29_gmac_plug_state[1] = value;
+ } else if (!strcmp(attr->name,"eth_sw_lan_state")) {
+ zx29_gmac_plug_state[2] = value;
+ } else {
+ printk("invalidate attr name.\n");
+ }
+ return size;
+}
+
+static struct sysfs_ops obj_gmac_sysops = {
+ .show = kobj_gmac_show,
+ .store = kobj_gmac_store,
+};
+
+static void kobj_gmac_release(struct kobject *kobject)
+{
+ printk("[gmac kobj_test: release!]\n");
+}
+
+static void kobj_type_release(struct kobject *kobject)
+{
+ printk("[type kobj_test: release!]\n");
+}
+
+
+void kobj_gmac_del(struct kobject *kobject)
+{
+// kset_unregister(kset_gmac);
+
+ kobject_uevent(typekobj, KOBJ_REMOVE);
+ kobject_del(typekobj);
+ kobject_put(typekobj);
+ kfree(typekobj);
+
+ kobject_uevent(gmackobj, KOBJ_REMOVE);
+ kobject_del(gmackobj);
+ kobject_put(gmackobj);
+
+ kfree(gmackobj);
+
+ kset_unregister(kset_gmac);
+ printk("[gmac kobj_test: delete!]\n");
+}
+EXPORT_SYMBOL(kobj_gmac_del);
+
+static struct kobj_type gmacktype =
+{ .release = kobj_gmac_release,
+ .sysfs_ops = &obj_gmac_sysops,
+ .default_attrs = gmac_status_attrs,
+};
+
+static struct kobj_type typektype =
+{ .release = kobj_type_release,
+// .sysfs_ops = &obj_gmac_sysops,
+// .default_attrs = gmac_status_attrs,
+};
+
+
+static int kset_filter(struct kset *kset,struct kobject *kobj)
+{
+ printk("kset Filter: kobj %s.\n",kobj->name);
+ return 1;
+}
+
+static const char *kset_name(struct kset *kset,struct kobject *kobj)
+{
+ static char buf[20];
+ printk("Name: kobj %s.\n",kobj->name);
+ sprintf(buf,"%s","gmac");
+ return buf;
+}
+
+static int kset_uevent(struct kset *kset, struct kobject *kobj, struct kobj_uevent_env *env)
+{
+ int i = 0;
+ printk("uevent: kobj %s.\n",kobj->name);
+ while (i < env->envp_idx) {
+ printk("%s.\n",env->envp[i]);
+ i++;
+ }
+
+ return 0;
+}
+
+static struct kset_uevent_ops gmac_uevent_ops =
+{
+ .filter = kset_filter,
+ .name = kset_name,
+ .uevent = kset_uevent,
+};
+
+void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void *puf)
+{
+ int rtv = -1;
+ enum kobject_action action = KOBJ_UNBIND;
+ char *envp_phy_ext[] = {"GMACEVENT=gmac_eth_phy",NULL};
+ char *envp_sw_wan_ext[] = {"GMACEVENT=gmac_eth_sw_wan",NULL};
+ char *envp_sw_lan_ext[] = {"GMACEVENT=gmac_eth_sw_lan",NULL};
+
+ switch (notify_type) {
+ case GMAC_ETH_PHY_PLUGIN:
+ printk("gmac eth phy plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[0] = 1;
+ if (gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action, envp_phy_ext);
+ break;
+
+ case GMAC_ETH_PHY_PLUGOUT:
+ printk("gmac eth phy plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[0] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_phy_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGIN:
+ printk("gmac eth switch wan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[1] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGOUT:
+ printk("gmac eth switch wan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[1] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGIN:
+ printk("gmac eth switch lan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[2] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGOUT:
+ printk("gmac eth switch lan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[2] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ default:
+ printk(KERN_WARNING "UNKWON GMAC EVENT \n");
+ break;
+ }
+
+ printk(KERN_WARNING "rtv:%d \n",rtv);
+}
+
+EXPORT_SYMBOL(gmac_event_notify);
+
+int gmac_event_init(const char *name)
+{
+ int ret = 0;
+ /* 创建并注册 kset_p */
+ gmackobj = kzalloc(sizeof(*gmackobj),GFP_KERNEL);
+ if(!gmackobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+ kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(gmackobj, &gmacktype);
+ gmackobj->kset = kset_gmac;
+ kobject_add(gmackobj,&kset_gmac->kobj,"%s","gmacconfig");
+
+ typekobj = kzalloc(sizeof(*typekobj),GFP_KERNEL);
+ if(!typekobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+// kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(typekobj, &typektype);
+ typekobj->kset = kset_gmac;
+ kobject_add(typekobj,&kset_gmac->kobj,"%s",name);
+
+ strcpy(type, name);
+
+ return ret;
+}
+EXPORT_SYMBOL(gmac_event_init);
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/phy/phy_device.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/phy/phy_device.c
new file mode 100755
index 0000000..f6a5a56
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/phy/phy_device.c
@@ -0,0 +1,3115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Framework for finding and configuring PHYs.
+ * Also contains generic PHY driver
+ *
+ * Author: Andy Fleming
+ *
+ * Copyright (c) 2004 Freescale Semiconductor, Inc.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/bitmap.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mdio.h>
+#include <linux/mii.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/phy_led_triggers.h>
+#include <linux/property.h>
+#include <linux/sfp.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+
+MODULE_DESCRIPTION("PHY library");
+MODULE_AUTHOR("Andy Fleming");
+MODULE_LICENSE("GPL");
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_t1_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_fibre_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_all_ports_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_fec_features);
+
+const int phy_basic_ports_array[3] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_ports_array);
+
+const int phy_fibre_port_array[1] = {
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_fibre_port_array);
+
+const int phy_all_ports_features_array[7] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+ ETHTOOL_LINK_MODE_AUI_BIT,
+ ETHTOOL_LINK_MODE_BNC_BIT,
+ ETHTOOL_LINK_MODE_Backplane_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_all_ports_features_array);
+
+const int phy_10_100_features_array[4] = {
+ ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10_100_features_array);
+
+const int phy_basic_t1_features_array[2] = {
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);
+
+const int phy_gbit_features_array[2] = {
+ ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_gbit_features_array);
+
+const int phy_10gbit_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10gbit_features_array);
+
+static const int phy_10gbit_fec_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
+};
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_full_features);
+
+static const int phy_10gbit_full_features_array[] = {
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+
+//status = phy_read_cl(phydev, MII_BMSR);
+static int phy_read_cl(struct phy_device *phydev, u32 regnum)
+{
+ int val = 0;
+
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 1);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0e, regnum);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 0x4000 | 1);
+ val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 0x0e);
+
+ return val;
+}
+
+static void features_init(void)
+{
+ /* 10/100 half/full*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_basic_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_basic_features);
+
+ /* 100 full, TP */
+ linkmode_set_bit_array(phy_basic_t1_features_array,
+ ARRAY_SIZE(phy_basic_t1_features_array),
+ phy_basic_t1_features);
+
+ /* 10/100 half/full + 1000 half/full */
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_features);
+
+ /* 10/100 half/full + 1000 half/full + fibre*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_fibre_port_array,
+ ARRAY_SIZE(phy_fibre_port_array),
+ phy_gbit_fibre_features);
+
+ /* 10/100 half/full + 1000 half/full + TP/MII/FIBRE/AUI/BNC/Backplane*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_all_ports_features);
+
+ /* 10/100 half/full + 1000 half/full + 10G full*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10gbit_features_array,
+ ARRAY_SIZE(phy_10gbit_features_array),
+ phy_10gbit_features);
+
+ /* 10/100/1000/10G full */
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_full_features);
+ linkmode_set_bit_array(phy_10gbit_full_features_array,
+ ARRAY_SIZE(phy_10gbit_full_features_array),
+ phy_10gbit_full_features);
+ /* 10G FEC only */
+ linkmode_set_bit_array(phy_10gbit_fec_features_array,
+ ARRAY_SIZE(phy_10gbit_fec_features_array),
+ phy_10gbit_fec_features);
+}
+
+void phy_device_free(struct phy_device *phydev)
+{
+ put_device(&phydev->mdio.dev);
+}
+EXPORT_SYMBOL(phy_device_free);
+
+static void phy_mdio_device_free(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_free(phydev);
+}
+
+static void phy_device_release(struct device *dev)
+{
+ kfree(to_phy_device(dev));
+}
+
+static void phy_mdio_device_remove(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_remove(phydev);
+}
+
+static struct phy_driver genphy_driver;
+
+static LIST_HEAD(phy_fixup_list);
+static DEFINE_MUTEX(phy_fixup_lock);
+
+static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
+{
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (!drv || !phydrv->suspend)
+ return false;
+
+ /* PHY not attached? May suspend if the PHY has not already been
+ * suspended as part of a prior call to phy_disconnect() ->
+ * phy_detach() -> phy_suspend() because the parent netdev might be the
+ * MDIO bus driver and clock gated at this point.
+ */
+ if (!netdev)
+ goto out;
+
+ if (netdev->wol_enabled)
+ return false;
+
+ /* As long as not all affected network drivers support the
+ * wol_enabled flag, let's check for hints that WoL is enabled.
+ * Don't suspend PHY if the attached netdev parent may wake up.
+ * The parent may point to a PCI device, as in tg3 driver.
+ */
+ if (netdev->dev.parent && device_may_wakeup(netdev->dev.parent))
+ return false;
+
+ /* Also don't suspend PHY if the netdev itself may wakeup. This
+ * is the case for devices w/o underlaying pwr. mgmt. aware bus,
+ * e.g. SoC devices.
+ */
+ if (device_may_wakeup(&netdev->dev))
+ return false;
+
+out:
+ return !phydev->suspended;
+}
+
+static __maybe_unused int mdio_bus_phy_suspend(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ /* We must stop the state machine manually, otherwise it stops out of
+ * control, possibly with the phydev->lock held. Upon resume, netdev
+ * may call phy routines that try to grab the same lock, and that may
+ * lead to a deadlock.
+ */
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_stop_machine(phydev);
+
+ if (!mdio_bus_phy_may_suspend(phydev))
+ return 0;
+
+ phydev->suspended_by_mdio_bus = 1;
+
+ return phy_suspend(phydev);
+}
+
+static __maybe_unused int mdio_bus_phy_resume(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ int ret;
+
+ if (!phydev->suspended_by_mdio_bus)
+ goto no_resume;
+
+ phydev->suspended_by_mdio_bus = 0;
+
+ ret = phy_init_hw(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_resume(phydev);
+ if (ret < 0)
+ return ret;
+no_resume:
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_start_machine(phydev);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mdio_bus_phy_pm_ops, mdio_bus_phy_suspend,
+ mdio_bus_phy_resume);
+
+/**
+ * phy_register_fixup - creates a new phy_fixup and adds it to the list
+ * @bus_id: A string which matches phydev->mdio.dev.bus_id (or PHY_ANY_ID)
+ * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
+ * It can also be PHY_ANY_UID
+ * @phy_uid_mask: Applied to phydev->phy_id and fixup->phy_uid before
+ * comparison
+ * @run: The actual code to be run when a matching PHY is found
+ */
+int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ struct phy_fixup *fixup = kzalloc(sizeof(*fixup), GFP_KERNEL);
+
+ if (!fixup)
+ return -ENOMEM;
+
+ strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id));
+ fixup->phy_uid = phy_uid;
+ fixup->phy_uid_mask = phy_uid_mask;
+ fixup->run = run;
+
+ mutex_lock(&phy_fixup_lock);
+ list_add_tail(&fixup->list, &phy_fixup_list);
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_register_fixup);
+
+/* Registers a fixup to be run on any PHY with the UID in phy_uid */
+int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_uid);
+
+/* Registers a fixup to be run on the PHY with id string bus_id */
+int phy_register_fixup_for_id(const char *bus_id,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_id);
+
+/**
+ * phy_unregister_fixup - remove a phy_fixup from the list
+ * @bus_id: A string matches fixup->bus_id (or PHY_ANY_ID) in phy_fixup_list
+ * @phy_uid: A phy id matches fixup->phy_id (or PHY_ANY_UID) in phy_fixup_list
+ * @phy_uid_mask: Applied to phy_uid and fixup->phy_uid before comparison
+ */
+int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask)
+{
+ struct list_head *pos, *n;
+ struct phy_fixup *fixup;
+ int ret;
+
+ ret = -ENODEV;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_safe(pos, n, &phy_fixup_list) {
+ fixup = list_entry(pos, struct phy_fixup, list);
+
+ if ((!strcmp(fixup->bus_id, bus_id)) &&
+ ((fixup->phy_uid & phy_uid_mask) ==
+ (phy_uid & phy_uid_mask))) {
+ list_del(&fixup->list);
+ kfree(fixup);
+ ret = 0;
+ break;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_unregister_fixup);
+
+/* Unregisters a fixup of any PHY with the UID in phy_uid */
+int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask)
+{
+ return phy_unregister_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_uid);
+
+/* Unregisters a fixup of the PHY with id string bus_id */
+int phy_unregister_fixup_for_id(const char *bus_id)
+{
+ return phy_unregister_fixup(bus_id, PHY_ANY_UID, 0xffffffff);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_id);
+
+/* Returns 1 if fixup matches phydev in bus_id and phy_uid.
+ * Fixups can be set to match any in one or more fields.
+ */
+static int phy_needs_fixup(struct phy_device *phydev, struct phy_fixup *fixup)
+{
+ if (strcmp(fixup->bus_id, phydev_name(phydev)) != 0)
+ if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ return 0;
+
+ if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+ (phydev->phy_id & fixup->phy_uid_mask))
+ if (fixup->phy_uid != PHY_ANY_UID)
+ return 0;
+
+ return 1;
+}
+
+/* Runs any matching fixups for this phydev */
+static int phy_scan_fixups(struct phy_device *phydev)
+{
+ struct phy_fixup *fixup;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_entry(fixup, &phy_fixup_list, list) {
+ if (phy_needs_fixup(phydev, fixup)) {
+ int err = fixup->run(phydev);
+
+ if (err < 0) {
+ mutex_unlock(&phy_fixup_lock);
+ return err;
+ }
+ phydev->has_fixups = true;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+
+static int phy_bus_match(struct device *dev, struct device_driver *drv)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
+ int i;
+
+ if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
+ return 0;
+
+ if (phydrv->match_phy_device)
+ return phydrv->match_phy_device(phydev);
+
+ if (phydev->is_c45) {
+ for (i = 1; i < num_ids; i++) {
+ if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ continue;
+
+ if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->c45_ids.device_ids[i] &
+ phydrv->phy_id_mask))
+ return 1;
+ }
+ return 0;
+ } else {
+ return (phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->phy_id & phydrv->phy_id_mask);
+ }
+}
+
+static ssize_t
+phy_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "0x%.8lx\n", (unsigned long)phydev->phy_id);
+}
+static DEVICE_ATTR_RO(phy_id);
+
+static ssize_t
+phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ const char *mode = NULL;
+
+ if (phy_is_internal(phydev))
+ mode = "internal";
+ else
+ mode = phy_modes(phydev->interface);
+
+ return sprintf(buf, "%s\n", mode);
+}
+static DEVICE_ATTR_RO(phy_interface);
+
+static ssize_t
+phy_has_fixups_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", phydev->has_fixups);
+}
+static DEVICE_ATTR_RO(phy_has_fixups);
+
+static struct attribute *phy_dev_attrs[] = {
+ &dev_attr_phy_id.attr,
+ &dev_attr_phy_interface.attr,
+ &dev_attr_phy_has_fixups.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(phy_dev);
+
+static const struct device_type mdio_bus_phy_type = {
+ .name = "PHY",
+ .groups = phy_dev_groups,
+ .release = phy_device_release,
+ .pm = pm_ptr(&mdio_bus_phy_pm_ops),
+};
+
+static int phy_request_driver_module(struct phy_device *dev, u32 phy_id)
+{
+ int ret;
+
+ ret = request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT,
+ MDIO_ID_ARGS(phy_id));
+ /* We only check for failures in executing the usermode binary,
+ * not whether a PHY driver module exists for the PHY ID.
+ * Accept -ENOENT because this may occur in case no initramfs exists,
+ * then modprobe isn't available.
+ */
+ if (IS_ENABLED(CONFIG_MODULES) && ret < 0 && ret != -ENOENT) {
+ phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n",
+ ret, (unsigned long)phy_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
+ bool is_c45,
+ struct phy_c45_device_ids *c45_ids)
+{
+ struct phy_device *dev;
+ struct mdio_device *mdiodev;
+ int ret = 0;
+
+ /* We allocate the device, and initialize the default values */
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ mdiodev = &dev->mdio;
+ mdiodev->dev.parent = &bus->dev;
+ mdiodev->dev.bus = &mdio_bus_type;
+ mdiodev->dev.type = &mdio_bus_phy_type;
+ mdiodev->bus = bus;
+ mdiodev->bus_match = phy_bus_match;
+ mdiodev->addr = addr;
+ mdiodev->flags = MDIO_DEVICE_FLAG_PHY;
+ mdiodev->device_free = phy_mdio_device_free;
+ mdiodev->device_remove = phy_mdio_device_remove;
+
+ dev->speed = SPEED_UNKNOWN;
+ dev->duplex = DUPLEX_UNKNOWN;
+ dev->pause = 0;
+ dev->asym_pause = 0;
+ dev->link = 0;
+ dev->port = PORT_TP;
+ dev->interface = PHY_INTERFACE_MODE_GMII;
+
+ dev->autoneg = AUTONEG_ENABLE;
+
+ dev->is_c45 = is_c45;
+ dev->phy_id = phy_id;
+ if (c45_ids)
+ dev->c45_ids = *c45_ids;
+ dev->irq = bus->irq[addr];
+
+ dev_set_name(&mdiodev->dev, PHY_ID_FMT, bus->id, addr);
+ device_initialize(&mdiodev->dev);
+
+ dev->state = PHY_DOWN;
+
+ mutex_init(&dev->lock);
+ INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
+
+ /* Request the appropriate module unconditionally; don't
+ * bother trying to do so only if it isn't already loaded,
+ * because that gets complicated. A hotplug event would have
+ * done an unconditional modprobe anyway.
+ * We don't do normal hotplug because it won't work for MDIO
+ * -- because it relies on the device staying around for long
+ * enough for the driver to get loaded. With MDIO, the NIC
+ * driver will get bored and give up as soon as it finds that
+ * there's no driver _already_ loaded.
+ */
+ if (is_c45 && c45_ids) {
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ int i;
+
+ for (i = 1; i < num_ids; i++) {
+ if (c45_ids->device_ids[i] == 0xffffffff)
+ continue;
+
+ ret = phy_request_driver_module(dev,
+ c45_ids->device_ids[i]);
+ if (ret)
+ break;
+ }
+ } else {
+ ret = phy_request_driver_module(dev, phy_id);
+ }
+
+ if (ret) {
+ put_device(&mdiodev->dev);
+ dev = ERR_PTR(ret);
+ }
+
+ return dev;
+}
+EXPORT_SYMBOL(phy_device_create);
+
+/* phy_c45_probe_present - checks to see if a MMD is present in the package
+ * @bus: the target MII bus
+ * @prtad: PHY package address on the MII bus
+ * @devad: PHY device (MMD) address
+ *
+ * Read the MDIO_STAT2 register, and check whether a device is responding
+ * at this address.
+ *
+ * Returns: negative error number on bus access error, zero if no device
+ * is responding, or positive if a device is present.
+ */
+static int phy_c45_probe_present(struct mii_bus *bus, int prtad, int devad)
+{
+ int stat2;
+
+ stat2 = mdiobus_c45_read(bus, prtad, devad, MDIO_STAT2);
+ if (stat2 < 0)
+ return stat2;
+
+ return (stat2 & MDIO_STAT2_DEVPRST) == MDIO_STAT2_DEVPRST_VAL;
+}
+
+/* get_phy_c45_devs_in_pkg - reads a MMD's devices in package registers.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @dev_addr: MMD address in the PHY.
+ * @devices_in_package: where to store the devices in package information.
+ *
+ * Description: reads devices in package registers of a MMD at @dev_addr
+ * from PHY at @addr on @bus.
+ *
+ * Returns: 0 on success, -EIO on failure.
+ */
+static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr,
+ u32 *devices_in_package)
+{
+ int phy_reg;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package |= phy_reg;
+
+ return 0;
+}
+
+/**
+ * get_phy_c45_ids - reads the specified addr for its 802.3-c45 IDs.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @c45_ids: where to store the c45 ID information.
+ *
+ * Read the PHY "devices in package". If this appears to be valid, read
+ * the PHY identifiers for each device. Return the "devices in package"
+ * and identifiers in @c45_ids.
+ *
+ * Returns zero on success, %-EIO on bus access error, or %-ENODEV if
+ * the "devices in package" is invalid.
+ */
+static int get_phy_c45_ids(struct mii_bus *bus, int addr,
+ struct phy_c45_device_ids *c45_ids)
+{
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ u32 devs_in_pkg = 0;
+ int i, ret, phy_reg;
+
+ /* Find first non-zero Devices In package. Device zero is reserved
+ * for 802.3 c45 complied PHYs, so don't probe it at first.
+ */
+ for (i = 1; i < MDIO_MMD_NUM && (devs_in_pkg == 0 ||
+ (devs_in_pkg & 0x1fffffff) == 0x1fffffff); i++) {
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Check that there is a device present at this
+ * address before reading the devices-in-package
+ * register to avoid reading garbage from the PHY.
+ * Some PHYs (88x3310) vendor space is not IEEE802.3
+ * compliant.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return -EIO;
+
+ if (!ret)
+ continue;
+ }
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, i, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+ }
+
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff) {
+ /* If mostly Fs, there is no device there, then let's probe
+ * MMD 0, as some 10G PHYs have zero Devices In package,
+ * e.g. Cortina CS4315/CS4340 PHY.
+ */
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, 0, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+
+ /* no device there, let's get out of here */
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+ }
+
+ /* Now probe Device Identifiers for each device present. */
+ for (i = 1; i < num_ids; i++) {
+ if (!(devs_in_pkg & (1 << i)))
+ continue;
+
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Probe the "Device Present" bits for the vendor MMDs
+ * to ignore these if they do not contain IEEE 802.3
+ * registers.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return ret;
+
+ if (!ret)
+ continue;
+ }
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID1);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID2);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] |= phy_reg;
+ }
+
+ c45_ids->devices_in_package = devs_in_pkg;
+ /* Bit 0 doesn't represent a device, it indicates c22 regs presence */
+ c45_ids->mmds_present = devs_in_pkg & ~BIT(0);
+
+ return 0;
+}
+
+/**
+ * get_phy_c22_id - reads the specified addr for its clause 22 ID.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @phy_id: where to store the ID retrieved.
+ *
+ * Read the 802.3 clause 22 PHY ID from the PHY at @addr on the @bus,
+ * placing it in @phy_id. Return zero on successful read and the ID is
+ * valid, %-EIO on bus access error, or %-ENODEV if no device responds
+ * or invalid ID.
+ */
+static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id)
+{
+ int phy_reg;
+
+ /* Grab the bits from PHYIR1, and put them in the upper half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 2);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id = phy_reg << 16;
+
+ /* Grab the bits from PHYIR2, and put them in the lower half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#ifdef CONFIG_MDIO_C45
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 3);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id |= phy_reg;
+
+#ifdef CONFIG_MDIO_C45
+ printk("[%s] read with c45 phy id:0x%x\n", __func__, *phy_id);
+#else
+ printk("[%s] read with c22 phy id:0x%x\n", __func__, *phy_id);
+#endif
+ /* If the phy_id is mostly Fs, there is no device there */
+ if ((*phy_id & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+
+ return 0;
+}
+
+/**
+ * get_phy_device - reads the specified PHY device and returns its @phy_device
+ * struct
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @is_c45: If true the PHY uses the 802.3 clause 45 protocol
+ *
+ * Probe for a PHY at @addr on @bus.
+ *
+ * When probing for a clause 22 PHY, then read the ID registers. If we find
+ * a valid ID, allocate and return a &struct phy_device.
+ *
+ * When probing for a clause 45 PHY, read the "devices in package" registers.
+ * If the "devices in package" appears valid, read the ID registers for each
+ * MMD, allocate and return a &struct phy_device.
+ *
+ * Returns an allocated &struct phy_device on success, %-ENODEV if there is
+ * no PHY present, or %-EIO on bus access error.
+ */
+struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
+{
+ struct phy_c45_device_ids c45_ids;
+ u32 phy_id = 0;
+ int r;
+
+ c45_ids.devices_in_package = 0;
+ c45_ids.mmds_present = 0;
+ memset(c45_ids.device_ids, 0xff, sizeof(c45_ids.device_ids));
+
+ if (is_c45)
+ r = get_phy_c45_ids(bus, addr, &c45_ids);
+ else
+ r = get_phy_c22_id(bus, addr, &phy_id);
+
+ if (r)
+ return ERR_PTR(r);
+
+ return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids);
+}
+EXPORT_SYMBOL(get_phy_device);
+
+/**
+ * phy_device_register - Register the phy device on the MDIO bus
+ * @phydev: phy_device structure to be added to the MDIO bus
+ */
+int phy_device_register(struct phy_device *phydev)
+{
+ int err;
+
+ err = mdiobus_register_device(&phydev->mdio);
+ if (err)
+ return err;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ /* Run all of the fixups for this PHY */
+ err = phy_scan_fixups(phydev);
+ if (err) {
+ phydev_err(phydev, "failed to initialize\n");
+ goto out;
+ }
+
+ err = device_add(&phydev->mdio.dev);
+ if (err) {
+ phydev_err(phydev, "failed to add\n");
+ goto out;
+ }
+
+ return 0;
+
+ out:
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+ return err;
+}
+EXPORT_SYMBOL(phy_device_register);
+
+/**
+ * phy_device_remove - Remove a previously registered phy device from the MDIO bus
+ * @phydev: phy_device structure to remove
+ *
+ * This doesn't free the phy_device itself, it merely reverses the effects
+ * of phy_device_register(). Use phy_device_free() to free the device
+ * after calling this function.
+ */
+void phy_device_remove(struct phy_device *phydev)
+{
+ if (phydev->mii_ts)
+ unregister_mii_timestamper(phydev->mii_ts);
+
+ device_del(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+}
+EXPORT_SYMBOL(phy_device_remove);
+
+/**
+ * phy_find_first - finds the first PHY device on the bus
+ * @bus: the target MII bus
+ */
+struct phy_device *phy_find_first(struct mii_bus *bus)
+{
+ struct phy_device *phydev;
+ int addr;
+
+ for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+ phydev = mdiobus_get_phy(bus, addr);
+ if (phydev) {
+ printk("[%s] addr:%d\n", __func__, addr);
+ return phydev;
+ }
+ }
+ return NULL;
+}
+EXPORT_SYMBOL(phy_find_first);
+
+static void phy_link_change(struct phy_device *phydev, bool up)
+{
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (up)
+ netif_carrier_on(netdev);
+ else
+ netif_carrier_off(netdev);
+ phydev->adjust_link(netdev);
+ if (phydev->mii_ts && phydev->mii_ts->link_state)
+ phydev->mii_ts->link_state(phydev->mii_ts, phydev);
+}
+
+/**
+ * phy_prepare_link - prepares the PHY layer to monitor link status
+ * @phydev: target phy_device struct
+ * @handler: callback function for link status change notifications
+ *
+ * Description: Tells the PHY infrastructure to handle the
+ * gory details on monitoring link status (whether through
+ * polling or an interrupt), and to call back to the
+ * connected device driver when the link status changes.
+ * If you want to monitor your own link state, don't call
+ * this function.
+ */
+static void phy_prepare_link(struct phy_device *phydev,
+ void (*handler)(struct net_device *))
+{
+ phydev->adjust_link = handler;
+}
+
+/**
+ * phy_connect_direct - connect an ethernet device to a specific phy_device
+ * @dev: the network device to connect
+ * @phydev: the pointer to the phy device
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ */
+int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ int rc;
+
+ if (!dev)
+ return -EINVAL;
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ if (rc)
+ return rc;
+
+ phy_prepare_link(phydev, handler);
+ if (phy_interrupt_is_valid(phydev))
+ phy_request_interrupt(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_connect_direct);
+
+/**
+ * phy_connect - connect an ethernet device to a PHY device
+ * @dev: the network device to connect
+ * @bus_id: the id string of the PHY device to connect
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ *
+ * Description: Convenience function for connecting ethernet
+ * devices to PHY devices. The default behavior is for
+ * the PHY infrastructure to handle everything, and only notify
+ * the connected driver when the link status changes. If you
+ * don't want, or can't use the provided functionality, you may
+ * choose to call only the subset of functions which provide
+ * the desired functionality.
+ */
+struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(&mdio_bus_type, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_connect_direct(dev, phydev, handler, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_connect);
+
+/**
+ * phy_disconnect - disable interrupts, stop state machine, and detach a PHY
+ * device
+ * @phydev: target phy_device struct
+ */
+void phy_disconnect(struct phy_device *phydev)
+{
+ if (phy_is_started(phydev))
+ phy_stop(phydev);
+
+ if (phy_interrupt_is_valid(phydev))
+ phy_free_interrupt(phydev);
+
+ phydev->adjust_link = NULL;
+
+ phy_detach(phydev);
+}
+EXPORT_SYMBOL(phy_disconnect);
+
+/**
+ * phy_poll_reset - Safely wait until a PHY reset has properly completed
+ * @phydev: The PHY device to poll
+ *
+ * Description: According to IEEE 802.3, Section 2, Subsection 22.2.4.1.1, as
+ * published in 2008, a PHY reset may take up to 0.5 seconds. The MII BMCR
+ * register must be polled until the BMCR_RESET bit clears.
+ *
+ * Furthermore, any attempts to write to PHY registers may have no effect
+ * or even generate MDIO bus errors until this is complete.
+ *
+ * Some PHYs (such as the Marvell 88E1111) don't entirely conform to the
+ * standard and do not fully reset after the BMCR_RESET bit is set, and may
+ * even *REQUIRE* a soft-reset to properly restart autonegotiation. In an
+ * effort to support such broken PHYs, this function is separate from the
+ * standard phy_init_hw() which will zero all the other bits in the BMCR
+ * and reapply all driver-specific and board-specific fixups.
+ */
+static int phy_poll_reset(struct phy_device *phydev)
+{
+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
+ int ret, val;
+
+ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+ 50000, 600000, true);
+ if (ret)
+ return ret;
+ /* Some chips (smsc911x) may still need up to another 1ms after the
+ * BMCR_RESET bit is cleared before they are usable.
+ */
+ msleep(1);
+ return 0;
+}
+
+int phy_init_hw(struct phy_device *phydev)
+{
+ int ret = 0;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (!phydev->drv)
+ return 0;
+
+ if (phydev->drv->soft_reset) {
+ ret = phydev->drv->soft_reset(phydev);
+ /* see comment in genphy_soft_reset for an explanation */
+ if (!ret)
+ phydev->suspended = 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ ret = phy_scan_fixups(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->drv->config_init) {
+ ret = phydev->drv->config_init(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (phydev->drv->config_intr) {
+ ret = phydev->drv->config_intr(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_init_hw);
+
+void phy_attached_info(struct phy_device *phydev)
+{
+ phy_attached_print(phydev, NULL);
+}
+EXPORT_SYMBOL(phy_attached_info);
+
+#define ATTACHED_FMT "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%s)"
+char *phy_attached_info_irq(struct phy_device *phydev)
+{
+ char *irq_str;
+ char irq_num[8];
+
+ switch(phydev->irq) {
+ case PHY_POLL:
+ irq_str = "POLL";
+ break;
+ case PHY_IGNORE_INTERRUPT:
+ irq_str = "IGNORE";
+ break;
+ default:
+ snprintf(irq_num, sizeof(irq_num), "%d", phydev->irq);
+ irq_str = irq_num;
+ break;
+ }
+
+ return kasprintf(GFP_KERNEL, "%s", irq_str);
+}
+EXPORT_SYMBOL(phy_attached_info_irq);
+
+void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
+{
+ const char *drv_name = phydev->drv ? phydev->drv->name : "unbound";
+ char *irq_str = phy_attached_info_irq(phydev);
+
+ if (!fmt) {
+ phydev_info(phydev, ATTACHED_FMT "\n",
+ drv_name, phydev_name(phydev),
+ irq_str);
+ } else {
+ va_list ap;
+
+ phydev_info(phydev, ATTACHED_FMT,
+ drv_name, phydev_name(phydev),
+ irq_str);
+
+ va_start(ap, fmt);
+ vprintk(fmt, ap);
+ va_end(ap);
+ }
+ kfree(irq_str);
+}
+EXPORT_SYMBOL(phy_attached_print);
+
+static void phy_sysfs_create_links(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ int err;
+
+ if (!dev)
+ return;
+
+ err = sysfs_create_link(&phydev->mdio.dev.kobj, &dev->dev.kobj,
+ "attached_dev");
+ if (err)
+ return;
+
+ err = sysfs_create_link_nowarn(&dev->dev.kobj,
+ &phydev->mdio.dev.kobj,
+ "phydev");
+ if (err) {
+ dev_err(&dev->dev, "could not add device link to %s err %d\n",
+ kobject_name(&phydev->mdio.dev.kobj),
+ err);
+ /* non-fatal - some net drivers can use one netdevice
+ * with more then one phy
+ */
+ }
+
+ phydev->sysfs_links = true;
+}
+
+static ssize_t
+phy_standalone_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", !phydev->attached_dev);
+}
+static DEVICE_ATTR_RO(phy_standalone);
+
+/**
+ * phy_sfp_attach - attach the SFP bus to the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .attach member.
+ */
+void phy_sfp_attach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = bus;
+ phydev->sfp_bus_attached = true;
+}
+EXPORT_SYMBOL(phy_sfp_attach);
+
+/**
+ * phy_sfp_detach - detach the SFP bus from the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .detach member.
+ */
+void phy_sfp_detach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = NULL;
+ phydev->sfp_bus_attached = false;
+}
+EXPORT_SYMBOL(phy_sfp_detach);
+
+/**
+ * phy_sfp_probe - probe for a SFP cage attached to this PHY device
+ * @phydev: Pointer to phy_device
+ * @ops: SFP's upstream operations
+ */
+int phy_sfp_probe(struct phy_device *phydev,
+ const struct sfp_upstream_ops *ops)
+{
+ struct sfp_bus *bus;
+ int ret = 0;
+
+ if (phydev->mdio.dev.fwnode) {
+ bus = sfp_bus_find_fwnode(phydev->mdio.dev.fwnode);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ phydev->sfp_bus = bus;
+
+ ret = sfp_bus_add_upstream(bus, phydev, ops);
+ sfp_bus_put(bus);
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_sfp_probe);
+
+static bool phy_drv_supports_irq(struct phy_driver *phydrv)
+{
+ return phydrv->config_intr && phydrv->ack_interrupt;
+}
+/**
+ * phy_attach_direct - attach a network device to a given PHY device pointer
+ * @dev: network device to attach
+ * @phydev: Pointer to phy_device to attach
+ * @flags: PHY device's dev_flags
+ * @interface: PHY device's interface
+ *
+ * Description: Called by drivers to attach to a particular PHY
+ * device. The phy_device is found, and properly hooked up
+ * to the phy_driver. If no driver is attached, then a
+ * generic driver is used. The phy_device is given a ptr to
+ * the attaching device, and given a callback for link status
+ * change. The phy_device is returned to the attaching driver.
+ * This function takes a reference on the phy device.
+ */
+int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
+ u32 flags, phy_interface_t interface)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct device *d = &phydev->mdio.dev;
+ struct module *ndev_owner = NULL;
+ bool using_genphy = false;
+ int err;
+
+ /* For Ethernet device drivers that register their own MDIO bus, we
+ * will have bus->owner match ndev_mod, so we do not want to increment
+ * our own module->refcnt here, otherwise we would not be able to
+ * unload later on.
+ */
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner && !try_module_get(bus->owner)) {
+ phydev_err(phydev, "failed to get the bus module\n");
+ return -EIO;
+ }
+
+ get_device(d);
+
+ /* Assume that if there is no driver, that it doesn't
+ * exist, and we should use the genphy driver.
+ */
+ if (!d->driver) {
+ if (phydev->is_c45)
+ d->driver = &genphy_c45_driver.mdiodrv.driver;
+ else
+ d->driver = &genphy_driver.mdiodrv.driver;
+
+ using_genphy = true;
+ }
+
+ if (!try_module_get(d->driver->owner)) {
+ phydev_err(phydev, "failed to get the device driver module\n");
+ err = -EIO;
+ goto error_put_device;
+ }
+
+ if (using_genphy) {
+ err = d->driver->probe(d);
+ if (err >= 0)
+ err = device_bind_driver(d);
+
+ if (err)
+ goto error_module_put;
+ }
+
+ if (phydev->attached_dev) {
+ dev_err(&dev->dev, "PHY already attached\n");
+ err = -EBUSY;
+ goto error;
+ }
+
+ phydev->phy_link_change = phy_link_change;
+ if (dev) {
+ phydev->attached_dev = dev;
+ dev->phydev = phydev;
+
+ if (phydev->sfp_bus_attached)
+ dev->sfp_bus = phydev->sfp_bus;
+ }
+
+ /* Some Ethernet drivers try to connect to a PHY device before
+ * calling register_netdevice() -> netdev_register_kobject() and
+ * does the dev->dev.kobj initialization. Here we only check for
+ * success which indicates that the network device kobject is
+ * ready. Once we do that we still need to keep track of whether
+ * links were successfully set up or not for phy_detach() to
+ * remove them accordingly.
+ */
+ phydev->sysfs_links = false;
+
+ phy_sysfs_create_links(phydev);
+
+ if (!phydev->attached_dev) {
+ err = sysfs_create_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+ if (err)
+ phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n");
+ }
+
+ phydev->dev_flags |= flags;
+
+ phydev->interface = interface;
+
+ phydev->state = PHY_READY;
+
+ if (!phy_drv_supports_irq(phydev->drv) && phy_interrupt_is_valid(phydev))
+ phydev->irq = PHY_POLL;
+ /* Port is set to PORT_TP by default and the actual PHY driver will set
+ * it to different value depending on the PHY configuration. If we have
+ * the generic PHY driver we can't figure it out, thus set the old
+ * legacy PORT_MII value.
+ */
+ if (using_genphy)
+ phydev->port = PORT_MII;
+
+ /* Initial carrier state is off as the phy is about to be
+ * (re)initialized.
+ */
+ if (dev)
+ netif_carrier_off(phydev->attached_dev);
+
+ /* Do initial configuration here, now that
+ * we have certain key parameters
+ * (dev_flags and interface)
+ */
+ err = phy_init_hw(phydev);
+ if (err)
+ goto error;
+
+ err = phy_disable_interrupts(phydev);
+ if (err)
+ return err;
+
+ phy_resume(phydev);
+ phy_led_triggers_register(phydev);
+
+ return err;
+
+error:
+ /* phy_detach() does all of the cleanup below */
+ phy_detach(phydev);
+ return err;
+
+error_module_put:
+ module_put(d->driver->owner);
+error_put_device:
+ put_device(d);
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+ return err;
+}
+EXPORT_SYMBOL(phy_attach_direct);
+
+/**
+ * phy_attach - attach a network device to a particular PHY device
+ * @dev: network device to attach
+ * @bus_id: Bus ID of PHY device to attach
+ * @interface: PHY device's interface
+ *
+ * Description: Same as phy_attach_direct() except that a PHY bus_id
+ * string is passed instead of a pointer to a struct phy_device.
+ */
+struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
+ phy_interface_t interface)
+{
+ struct bus_type *bus = &mdio_bus_type;
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(bus, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_attach);
+
+static bool phy_driver_is_genphy_kind(struct phy_device *phydev,
+ struct device_driver *driver)
+{
+ struct device *d = &phydev->mdio.dev;
+ bool ret = false;
+
+ if (!phydev->drv)
+ return ret;
+
+ get_device(d);
+ ret = d->driver == driver;
+ put_device(d);
+
+ return ret;
+}
+
+bool phy_driver_is_genphy(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
+
+bool phy_driver_is_genphy_10g(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_c45_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
+
+/**
+ * phy_package_join - join a common PHY group
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * This joins a PHY group and provides a shared storage for all phydevs in
+ * this group. This is intended to be used for packages which contain
+ * more than one PHY, for example a quad PHY transceiver.
+ *
+ * The addr parameter serves as a cookie which has to have the same value
+ * for all members of one group and as a PHY address to access generic
+ * registers of a PHY package. Usually, one of the PHY addresses of the
+ * different PHYs in the package provides access to these global registers.
+ * The address which is given here, will be used in the phy_package_read()
+ * and phy_package_write() convenience functions. If your PHY doesn't have
+ * global registers you can just pick any of the PHY addresses.
+ *
+ * This will set the shared pointer of the phydev to the shared storage.
+ * If this is the first call for a this cookie the shared storage will be
+ * allocated. If priv_size is non-zero, the given amount of bytes are
+ * allocated for the priv member.
+ *
+ * Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
+ * with the same cookie but a different priv_size is an error.
+ */
+int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct phy_package_shared *shared;
+ int ret;
+
+ if (addr < 0 || addr >= PHY_MAX_ADDR)
+ return -EINVAL;
+
+ mutex_lock(&bus->shared_lock);
+ shared = bus->shared[addr];
+ if (!shared) {
+ ret = -ENOMEM;
+ shared = kzalloc(sizeof(*shared), GFP_KERNEL);
+ if (!shared)
+ goto err_unlock;
+ if (priv_size) {
+ shared->priv = kzalloc(priv_size, GFP_KERNEL);
+ if (!shared->priv)
+ goto err_free;
+ shared->priv_size = priv_size;
+ }
+ shared->addr = addr;
+ refcount_set(&shared->refcnt, 1);
+ bus->shared[addr] = shared;
+ } else {
+ ret = -EINVAL;
+ if (priv_size && priv_size != shared->priv_size)
+ goto err_unlock;
+ refcount_inc(&shared->refcnt);
+ }
+ mutex_unlock(&bus->shared_lock);
+
+ phydev->shared = shared;
+
+ return 0;
+
+err_free:
+ kfree(shared);
+err_unlock:
+ mutex_unlock(&bus->shared_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_package_join);
+
+/**
+ * phy_package_leave - leave a common PHY group
+ * @phydev: target phy_device struct
+ *
+ * This leaves a PHY group created by phy_package_join(). If this phydev
+ * was the last user of the shared data between the group, this data is
+ * freed. Resets the phydev->shared pointer to NULL.
+ */
+void phy_package_leave(struct phy_device *phydev)
+{
+ struct phy_package_shared *shared = phydev->shared;
+ struct mii_bus *bus = phydev->mdio.bus;
+
+ if (!shared)
+ return;
+
+ if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+ bus->shared[shared->addr] = NULL;
+ mutex_unlock(&bus->shared_lock);
+ kfree(shared->priv);
+ kfree(shared);
+ }
+
+ phydev->shared = NULL;
+}
+EXPORT_SYMBOL_GPL(phy_package_leave);
+
+static void devm_phy_package_leave(struct device *dev, void *res)
+{
+ phy_package_leave(*(struct phy_device **)res);
+}
+
+/**
+ * devm_phy_package_join - resource managed phy_package_join()
+ * @dev: device that is registering this PHY package
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * Managed phy_package_join(). Shared storage fetched by this function,
+ * phy_package_leave() is automatically called on driver detach. See
+ * phy_package_join() for more information.
+ */
+int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+ int addr, size_t priv_size)
+{
+ struct phy_device **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_phy_package_leave, sizeof(*ptr),
+ GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = phy_package_join(phydev, addr, priv_size);
+
+ if (!ret) {
+ *ptr = phydev;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_phy_package_join);
+
+/**
+ * phy_detach - detach a PHY device from its network device
+ * @phydev: target phy_device struct
+ *
+ * This detaches the phy device from its network device and the phy
+ * driver, and drops the reference count taken in phy_attach_direct().
+ */
+void phy_detach(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ struct module *ndev_owner = NULL;
+ struct mii_bus *bus;
+
+ if (phydev->sysfs_links) {
+ if (dev)
+ sysfs_remove_link(&dev->dev.kobj, "phydev");
+ sysfs_remove_link(&phydev->mdio.dev.kobj, "attached_dev");
+ }
+
+ if (!phydev->attached_dev)
+ sysfs_remove_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+
+ phy_suspend(phydev);
+ if (dev) {
+ phydev->attached_dev->phydev = NULL;
+ phydev->attached_dev = NULL;
+ }
+ phydev->phylink = NULL;
+
+ phy_led_triggers_unregister(phydev);
+
+ if (phydev->mdio.dev.driver)
+ module_put(phydev->mdio.dev.driver->owner);
+
+ /* If the device had no specific driver before (i.e. - it
+ * was using the generic driver), we unbind the device
+ * from the generic driver so that there's a chance a
+ * real driver could be loaded
+ */
+ if (phy_driver_is_genphy(phydev) ||
+ phy_driver_is_genphy_10g(phydev))
+ device_release_driver(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ /*
+ * The phydev might go away on the put_device() below, so avoid
+ * a use-after-free bug by reading the underlying bus first.
+ */
+ bus = phydev->mdio.bus;
+
+ put_device(&phydev->mdio.dev);
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+}
+EXPORT_SYMBOL(phy_detach);
+
+int phy_suspend(struct phy_device *phydev)
+{
+ struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
+ struct net_device *netdev = phydev->attached_dev;
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ if (phydev->suspended)
+ return 0;
+
+ /* If the device has WOL enabled, we cannot suspend the PHY */
+ phy_ethtool_get_wol(phydev, &wol);
+ if (wol.wolopts || (netdev && netdev->wol_enabled))
+ return -EBUSY;
+
+ if (!phydrv || !phydrv->suspend)
+ return 0;
+
+ ret = phydrv->suspend(phydev);
+ if (!ret)
+ phydev->suspended = true;
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_suspend);
+
+int __phy_resume(struct phy_device *phydev)
+{
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ WARN_ON(!mutex_is_locked(&phydev->lock));
+
+ if (!phydrv || !phydrv->resume)
+ return 0;
+
+ ret = phydrv->resume(phydev);
+ if (!ret)
+ phydev->suspended = false;
+
+ return ret;
+}
+EXPORT_SYMBOL(__phy_resume);
+
+int phy_resume(struct phy_device *phydev)
+{
+ int ret;
+
+ mutex_lock(&phydev->lock);
+ ret = __phy_resume(phydev);
+ mutex_unlock(&phydev->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_resume);
+
+int phy_loopback(struct phy_device *phydev, bool enable)
+{
+ struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver);
+ int ret = 0;
+
+ mutex_lock(&phydev->lock);
+
+ if (enable && phydev->loopback_enabled) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ if (!enable && !phydev->loopback_enabled) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (phydev->drv && phydrv->set_loopback)
+ ret = phydrv->set_loopback(phydev, enable);
+ else
+ ret = -EOPNOTSUPP;
+
+ if (ret)
+ goto out;
+
+ phydev->loopback_enabled = enable;
+
+out:
+ mutex_unlock(&phydev->lock);
+ return ret;
+}
+EXPORT_SYMBOL(phy_loopback);
+
+/**
+ * phy_reset_after_clk_enable - perform a PHY reset if needed
+ * @phydev: target phy_device struct
+ *
+ * Description: Some PHYs are known to need a reset after their refclk was
+ * enabled. This function evaluates the flags and perform the reset if it's
+ * needed. Returns < 0 on error, 0 if the phy wasn't reset and 1 if the phy
+ * was reset.
+ */
+int phy_reset_after_clk_enable(struct phy_device *phydev)
+{
+ if (!phydev || !phydev->drv)
+ return -ENODEV;
+
+ if (phydev->drv->flags & PHY_RST_AFTER_CLK_EN) {
+ phy_device_reset(phydev, 1);
+ phy_device_reset(phydev, 0);
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_reset_after_clk_enable);
+
+/* Generic PHY support and helper functions */
+
+/**
+ * genphy_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed.
+ */
+static int genphy_config_advert(struct phy_device *phydev)
+{
+ int err, bmsr, changed = 0;
+ u32 adv;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
+
+ /* Setup standard advertisement */
+ err = phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_100BASE4 |
+ ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ bmsr = phy_read(phydev, MII_BMSR);
+ if (bmsr < 0)
+ return bmsr;
+
+ /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
+ * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
+ * logical 1.
+ */
+ if (!(bmsr & BMSR_ESTATEN))
+ return changed;
+
+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+
+ err = phy_modify_changed(phydev, MII_CTRL1000,
+ ADVERTISE_1000FULL | ADVERTISE_1000HALF,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ return changed;
+}
+
+/**
+ * genphy_c37_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed. This function is intended
+ * for Clause 37 1000Base-X mode.
+ */
+static int genphy_c37_config_advert(struct phy_device *phydev)
+{
+ u16 adv = 0;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XFULL;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPAUSE;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPSE_ASYM;
+
+ return phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
+ ADVERTISE_1000XHALF | ADVERTISE_1000XPSE_ASYM,
+ adv);
+}
+
+/**
+ * genphy_config_eee_advert - disable unwanted eee mode advertisement
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MDIO_AN_EEE_ADV after disabling unsupported energy
+ * efficent ethernet modes. Returns 0 if the PHY's advertisement hasn't
+ * changed, and 1 if it has changed.
+ */
+int genphy_config_eee_advert(struct phy_device *phydev)
+{
+ int err;
+
+ /* Nothing to disable */
+ if (!phydev->eee_broken_modes)
+ return 0;
+
+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ phydev->eee_broken_modes, 0);
+ /* If the call failed, we assume that EEE is not supported */
+ return err < 0 ? 0 : err;
+}
+EXPORT_SYMBOL(genphy_config_eee_advert);
+
+/**
+ * genphy_setup_forced - configures/forces speed/duplex from @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Configures MII_BMCR to force speed/duplex
+ * to the values in phydev. Assumes that the values are valid.
+ * Please see phy_sanitize_settings().
+ */
+int genphy_setup_forced(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (SPEED_1000 == phydev->speed)
+ ctl |= BMCR_SPEED1000;
+ else if (SPEED_100 == phydev->speed)
+ ctl |= BMCR_SPEED100;
+
+ if (DUPLEX_FULL == phydev->duplex)
+ ctl |= BMCR_FULLDPLX;
+
+ return phy_modify(phydev, MII_BMCR,
+ ~(BMCR_LOOPBACK | BMCR_ISOLATE | BMCR_PDOWN), ctl);
+}
+EXPORT_SYMBOL(genphy_setup_forced);
+
+static int genphy_setup_master_slave(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ if (!phydev->is_gigabit_capable)
+ return 0;
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ ctl |= CTL1000_PREFER_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ break;
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ ctl |= CTL1000_AS_MASTER;
+ fallthrough;
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ ctl |= CTL1000_ENABLE_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_UNKNOWN:
+ case MASTER_SLAVE_CFG_UNSUPPORTED:
+ return 0;
+ default:
+ phydev_warn(phydev, "Unsupported Master/Slave mode\n");
+ return -EOPNOTSUPP;
+ }
+
+ return phy_modify_changed(phydev, MII_CTRL1000,
+ (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
+ CTL1000_PREFER_MASTER), ctl);
+}
+
+static int genphy_read_master_slave(struct phy_device *phydev)
+{
+ int cfg, state;
+ int val;
+
+ if (!phydev->is_gigabit_capable) {
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
+ return 0;
+ }
+
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+
+ val = phy_read(phydev, MII_CTRL1000);
+ if (val < 0)
+ return val;
+
+ if (val & CTL1000_ENABLE_MASTER) {
+ if (val & CTL1000_AS_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_FORCE;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_FORCE;
+ } else {
+ if (val & CTL1000_PREFER_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_PREFERRED;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
+ }
+
+ val = phy_read(phydev, MII_STAT1000);
+ if (val < 0)
+ return val;
+
+ if (val & LPA_1000MSFAIL) {
+ state = MASTER_SLAVE_STATE_ERR;
+ } else if (phydev->link) {
+ /* this bits are valid only for active link */
+ if (val & LPA_1000MSRES)
+ state = MASTER_SLAVE_STATE_MASTER;
+ else
+ state = MASTER_SLAVE_STATE_SLAVE;
+ } else {
+ state = MASTER_SLAVE_STATE_UNKNOWN;
+ }
+
+ phydev->master_slave_get = cfg;
+ phydev->master_slave_state = state;
+
+ return 0;
+}
+
+/**
+ * genphy_restart_aneg - Enable and Restart Autonegotiation
+ * @phydev: target phy_device struct
+ */
+int genphy_restart_aneg(struct phy_device *phydev)
+{
+ /* Don't isolate the PHY if we're negotiating */
+ return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+}
+EXPORT_SYMBOL(genphy_restart_aneg);
+
+/**
+ * genphy_check_and_restart_aneg - Enable and restart auto-negotiation
+ * @phydev: target phy_device struct
+ * @restart: whether aneg restart is requested
+ *
+ * Check, and restart auto-negotiation if needed.
+ */
+int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
+{
+ int ret;
+
+ if (!restart) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+
+ if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
+ restart = true;
+ }
+
+ if (restart)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_check_and_restart_aneg);
+
+/**
+ * __genphy_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ * @changed: whether autoneg is requested
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR.
+ */
+int __genphy_config_aneg(struct phy_device *phydev, bool changed)
+{
+ int err;
+
+ if (genphy_config_eee_advert(phydev))
+ changed = true;
+
+ err = genphy_setup_master_slave(phydev);
+ if (err < 0)
+ return err;
+ else if (err)
+ changed = true;
+
+ if (AUTONEG_ENABLE != phydev->autoneg)
+ return genphy_setup_forced(phydev);
+
+ err = genphy_config_advert(phydev);
+ if (err < 0) /* error */
+ return err;
+ else if (err)
+ changed = true;
+
+ return genphy_check_and_restart_aneg(phydev, changed);
+}
+EXPORT_SYMBOL(__genphy_config_aneg);
+
+/**
+ * genphy_c37_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR. This function is intended
+ * for use with Clause 37 1000Base-X mode.
+ */
+int genphy_c37_config_aneg(struct phy_device *phydev)
+{
+ int err, changed;
+
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return genphy_setup_forced(phydev);
+
+ err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
+ BMCR_SPEED1000);
+ if (err)
+ return err;
+
+ changed = genphy_c37_config_advert(phydev);
+ if (changed < 0) /* error */
+ return changed;
+
+ if (!changed) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ int ctl = phy_read(phydev, MII_BMCR);
+
+ if (ctl < 0)
+ return ctl;
+
+ if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
+ changed = 1; /* do restart aneg */
+ }
+
+ /* Only restart aneg if we are advertising something different
+ * than we were before.
+ */
+ if (changed > 0)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_config_aneg);
+
+/**
+ * genphy_aneg_done - return auto-negotiation status
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the status register and returns 0 either if
+ * auto-negotiation is incomplete, or if there was an error.
+ * Returns BMSR_ANEGCOMPLETE if auto-negotiation is done.
+ */
+int genphy_aneg_done(struct phy_device *phydev)
+{
+ int retval = phy_read(phydev, MII_BMSR);
+
+ return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
+}
+EXPORT_SYMBOL(genphy_aneg_done);
+
+/**
+ * genphy_update_link - update link status in @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Update the value in phydev->link to reflect the
+ * current link value. In order to do this, we need to read
+ * the status register twice, keeping the second value.
+ */
+int genphy_update_link(struct phy_device *phydev)
+{
+ int status = 0, bmcr;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ bmcr = phy_read(phydev, MII_BMCR);
+#endif
+ if (bmcr < 0)
+ return bmcr;
+
+ /* Autoneg is being started, therefore disregard BMSR value and
+ * report link as down.
+ */
+ if (bmcr & BMCR_ANRESTART)
+ goto done;
+
+ /* The link state is latched low so that momentary link
+ * drops can be detected. Do not double-read the status
+ * in polling mode to detect such short link drops except
+ * the link was already down.
+ */
+ if (!phy_polling_mode(phydev) || !phydev->link) {
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+ else if (status & BMSR_LSTATUS)
+ goto done;
+ }
+
+ /* Read link and autonegotiation status */
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+done:
+ phydev->link = status & BMSR_LSTATUS ? 1 : 0;
+ phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0;
+
+ /* Consider the case that autoneg was started and "aneg complete"
+ * bit has been reset, but "link up" bit not yet.
+ */
+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
+ phydev->link = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_update_link);
+
+int genphy_read_lpa(struct phy_device *phydev)
+{
+ int lpa, lpagb;
+
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ if (!phydev->autoneg_complete) {
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ 0);
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
+ return 0;
+ }
+
+ if (phydev->is_gigabit_capable) {
+ lpagb = phy_read(phydev, MII_STAT1000);
+ if (lpagb < 0)
+ return lpagb;
+
+ if (lpagb & LPA_1000MSFAIL) {
+ int adv = phy_read(phydev, MII_CTRL1000);
+
+ if (adv < 0)
+ return adv;
+
+ if (adv & CTL1000_ENABLE_MASTER)
+ phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
+ else
+ phydev_err(phydev, "Master/Slave resolution failed\n");
+ return -ENOLINK;
+ }
+
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ lpagb);
+ }
+
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
+ } else {
+ linkmode_zero(phydev->lp_advertising);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_lpa);
+
+/**
+ * genphy_read_status_fixed - read the link parameters for !aneg mode
+ * @phydev: target phy_device struct
+ *
+ * Read the current duplex and speed state for a PHY operating with
+ * autonegotiation disabled.
+ */
+int genphy_read_status_fixed(struct phy_device *phydev)
+{
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ int bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ int bmcr = phy_read(phydev, MII_BMCR);
+#endif
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (bmcr & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status_fixed);
+
+/**
+ * genphy_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. Start by checking the gigabit possibilities,
+ * then move on to 10/100.
+ */
+int genphy_read_status(struct phy_device *phydev)
+{
+ int err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ err = genphy_read_master_slave(phydev);
+ if (err < 0)
+ return err;
+
+ err = genphy_read_lpa(phydev);
+ if (err < 0)
+ return err;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ err = genphy_read_status_fixed(phydev);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status);
+
+/**
+ * genphy_c37_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. This function is for Clause 37 1000Base-X mode.
+ */
+int genphy_c37_read_status(struct phy_device *phydev)
+{
+ int lpa, err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->lp_advertising, lpa & LPA_LPACK);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XPAUSE);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->lp_advertising,
+ lpa & LPA_1000XPAUSE_ASYM);
+
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ int bmcr = phy_read(phydev, MII_BMCR);
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_read_status);
+
+/**
+ * genphy_soft_reset - software reset the PHY via BMCR_RESET bit
+ * @phydev: target phy_device struct
+ *
+ * Description: Perform a software PHY reset using the standard
+ * BMCR_RESET bit and poll for the reset bit to be cleared.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_soft_reset(struct phy_device *phydev)
+{
+ u16 res = BMCR_RESET;
+ int ret;
+
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ res |= BMCR_ANRESTART;
+
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res);
+ if (ret < 0)
+ return ret;
+
+ /* Clause 22 states that setting bit BMCR_RESET sets control registers
+ * to their default value. Therefore the POWER DOWN bit is supposed to
+ * be cleared after soft reset.
+ */
+ phydev->suspended = 0;
+
+ ret = phy_poll_reset(phydev);
+ if (ret)
+ return ret;
+
+ /* BMCR may be reset to defaults */
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ ret = genphy_setup_forced(phydev);
+
+ return ret;
+}
+EXPORT_SYMBOL(genphy_soft_reset);
+
+/**
+ * genphy_read_abilities - read PHY abilities from Clause 22 registers
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the PHY's abilities and populates
+ * phydev->supported accordingly.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_read_abilities(struct phy_device *phydev)
+{
+ int val;
+
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phydev->supported);
+
+ val = phy_read(phydev, MII_BMSR);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
+ val & BMSR_ANEGCAPABLE);
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
+ val & BMSR_100FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
+ val & BMSR_100HALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
+ val & BMSR_10FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
+ val & BMSR_10HALF);
+
+ if (val & BMSR_ESTATEN) {
+ val = phy_read(phydev, MII_ESTATUS);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_TFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported, val & ESTATUS_1000_THALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_XFULL);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_abilities);
+
+/* This is used for the phy device which doesn't support the MMD extended
+ * register access, but it does have side effect when we are trying to access
+ * the MMD register via indirect method.
+ */
+int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_read_mmd_unsupported);
+
+int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
+ u16 regnum, u16 val)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_write_mmd_unsupported);
+
+int genphy_suspend(struct phy_device *phydev)
+{
+ return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_suspend);
+
+int genphy_resume(struct phy_device *phydev)
+{
+ return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_resume);
+
+int genphy_loopback(struct phy_device *phydev, bool enable)
+{
+ return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
+ enable ? BMCR_LOOPBACK : 0);
+}
+EXPORT_SYMBOL(genphy_loopback);
+
+/**
+ * phy_remove_link_mode - Remove a supported link mode
+ * @phydev: phy_device structure to remove link mode from
+ * @link_mode: Link mode to be removed
+ *
+ * Description: Some MACs don't support all link modes which the PHY
+ * does. e.g. a 1G MAC often does not support 1000Half. Add a helper
+ * to remove a link mode.
+ */
+void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode)
+{
+ linkmode_clear_bit(link_mode, phydev->supported);
+ phy_advertise_supported(phydev);
+}
+EXPORT_SYMBOL(phy_remove_link_mode);
+
+static void phy_copy_pause_bits(unsigned long *dst, unsigned long *src)
+{
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, src));
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, src));
+}
+
+/**
+ * phy_advertise_supported - Advertise all supported modes
+ * @phydev: target phy_device struct
+ *
+ * Description: Called to advertise all supported modes, doesn't touch
+ * pause mode advertising.
+ */
+void phy_advertise_supported(struct phy_device *phydev)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(new);
+
+ linkmode_copy(new, phydev->supported);
+ phy_copy_pause_bits(new, phydev->advertising);
+ linkmode_copy(phydev->advertising, new);
+}
+EXPORT_SYMBOL(phy_advertise_supported);
+
+/**
+ * phy_support_sym_pause - Enable support of symmetrical pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports symmetrical
+ * Pause, but not asym pause.
+ */
+void phy_support_sym_pause(struct phy_device *phydev)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_sym_pause);
+
+/**
+ * phy_support_asym_pause - Enable support of asym pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports Asym Pause.
+ */
+void phy_support_asym_pause(struct phy_device *phydev)
+{
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_asym_pause);
+
+/**
+ * phy_set_sym_pause - Configure symmetric Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ * @autoneg: Auto neg should be used
+ *
+ * Description: Configure advertised Pause support depending on if
+ * receiver pause and pause auto neg is supported. Generally called
+ * from the set_pauseparam .ndo.
+ */
+void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
+ bool autoneg)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
+
+ if (rx && tx && autoneg)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+
+ linkmode_copy(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_set_sym_pause);
+
+/**
+ * phy_set_asym_pause - Configure Pause and Asym Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ *
+ * Description: Configure advertised Pause support depending on if
+ * transmit and receiver pause is supported. If there has been a
+ * change in adverting, trigger a new autoneg. Generally called from
+ * the set_pauseparam .ndo.
+ */
+void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(oldadv);
+
+ linkmode_copy(oldadv, phydev->advertising);
+ linkmode_set_pause(phydev->advertising, tx, rx);
+
+ if (!linkmode_equal(oldadv, phydev->advertising) &&
+ phydev->autoneg)
+ phy_start_aneg(phydev);
+}
+EXPORT_SYMBOL(phy_set_asym_pause);
+
+/**
+ * phy_validate_pause - Test if the PHY/MAC support the pause configuration
+ * @phydev: phy_device struct
+ * @pp: requested pause configuration
+ *
+ * Description: Test if the PHY/MAC combination supports the Pause
+ * configuration the user is requesting. Returns True if it is
+ * supported, false otherwise.
+ */
+bool phy_validate_pause(struct phy_device *phydev,
+ struct ethtool_pauseparam *pp)
+{
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported) && pp->rx_pause)
+ return false;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported) &&
+ pp->rx_pause != pp->tx_pause)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL(phy_validate_pause);
+
+/**
+ * phy_get_pause - resolve negotiated pause modes
+ * @phydev: phy_device struct
+ * @tx_pause: pointer to bool to indicate whether transmit pause should be
+ * enabled.
+ * @rx_pause: pointer to bool to indicate whether receive pause should be
+ * enabled.
+ *
+ * Resolve and return the flow control modes according to the negotiation
+ * result. This includes checking that we are operating in full duplex mode.
+ * See linkmode_resolve_pause() for further details.
+ */
+void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause)
+{
+ if (phydev->duplex != DUPLEX_FULL) {
+ *tx_pause = false;
+ *rx_pause = false;
+ return;
+ }
+
+ return linkmode_resolve_pause(phydev->advertising,
+ phydev->lp_advertising,
+ tx_pause, rx_pause);
+}
+EXPORT_SYMBOL(phy_get_pause);
+
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ s32 int_delay;
+ int ret;
+
+ ret = device_property_read_u32(dev, name, &int_delay);
+ if (ret)
+ return ret;
+
+ return int_delay;
+}
+#else
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ return -EINVAL;
+}
+#endif
+
+/**
+ * phy_get_delay_index - returns the index of the internal delay
+ * @phydev: phy_device struct
+ * @dev: pointer to the devices device struct
+ * @delay_values: array of delays the PHY supports
+ * @size: the size of the delay array
+ * @is_rx: boolean to indicate to get the rx internal delay
+ *
+ * Returns the index within the array of internal delay passed in.
+ * If the device property is not present then the interface type is checked
+ * if the interface defines use of internal delay then a 1 is returned otherwise
+ * a 0 is returned.
+ * The array must be in ascending order. If PHY does not have an ascending order
+ * array then size = 0 and the value of the delay property is returned.
+ * Return -EINVAL if the delay is invalid or cannot be found.
+ */
+s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev,
+ const int *delay_values, int size, bool is_rx)
+{
+ s32 delay;
+ int i;
+
+ if (is_rx) {
+ delay = phy_get_int_delay_property(dev, "rx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ return 1;
+ else
+ return 0;
+ }
+
+ } else {
+ delay = phy_get_int_delay_property(dev, "tx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ return 1;
+ else
+ return 0;
+ }
+ }
+
+ if (delay < 0)
+ return delay;
+
+ if (size == 0)
+ return delay;
+
+ if (delay < delay_values[0] || delay > delay_values[size - 1]) {
+ phydev_err(phydev, "Delay %d is out of range\n", delay);
+ return -EINVAL;
+ }
+
+ if (delay == delay_values[0])
+ return 0;
+
+ for (i = 1; i < size; i++) {
+ if (delay == delay_values[i])
+ return i;
+
+ /* Find an approximate index by looking up the table */
+ if (delay > delay_values[i - 1] &&
+ delay < delay_values[i]) {
+ if (delay - delay_values[i - 1] <
+ delay_values[i] - delay)
+ return i - 1;
+ else
+ return i;
+ }
+ }
+
+ phydev_err(phydev, "error finding internal delay index for %d\n",
+ delay);
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(phy_get_internal_delay);
+
+
+/**
+ * phy_probe - probe and init a PHY device
+ * @dev: device to probe and init
+ *
+ * Description: Take care of setting up the phy_device structure,
+ * set the state to READY (the driver's init function should
+ * set it to STARTING if needed).
+ */
+static int phy_probe(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ int err = 0;
+
+ phydev->drv = phydrv;
+
+ /* Disable the interrupt if the PHY doesn't support it
+ * but the interrupt is still a valid one
+ */
+ if (!phy_drv_supports_irq(phydrv) && phy_interrupt_is_valid(phydev))
+ phydev->irq = PHY_POLL;
+
+ if (phydrv->flags & PHY_IS_INTERNAL)
+ phydev->is_internal = true;
+
+ mutex_lock(&phydev->lock);
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (phydev->drv->probe) {
+ err = phydev->drv->probe(phydev);
+ if (err)
+ goto out;
+ }
+
+ /* Start out supporting everything. Eventually,
+ * a controller will attach, and may modify one
+ * or both of these values
+ */
+ if (phydrv->features) {
+ linkmode_copy(phydev->supported, phydrv->features);
+ } else if (phydrv->get_features) {
+ err = phydrv->get_features(phydev);
+ } else if (phydev->is_c45) {
+ err = genphy_c45_pma_read_abilities(phydev);
+ } else {
+ err = genphy_read_abilities(phydev);
+ }
+
+ if (err)
+ goto out;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported))
+ phydev->autoneg = 0;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+
+ of_set_phy_supported(phydev);
+ phy_advertise_supported(phydev);
+
+ /* Get the EEE modes we want to prohibit. We will ask
+ * the PHY stop advertising these mode later on
+ */
+ of_set_phy_eee_broken(phydev);
+
+ /* The Pause Frame bits indicate that the PHY can support passing
+ * pause frames. During autonegotiation, the PHYs will determine if
+ * they should allow pause frames to pass. The MAC driver should then
+ * use that result to determine whether to enable flow control via
+ * pause frames.
+ *
+ * Normally, PHY drivers should not set the Pause bits, and instead
+ * allow phylib to do that. However, there may be some situations
+ * (e.g. hardware erratum) where the driver wants to set only one
+ * of these bits.
+ */
+ if (!test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported) &&
+ !test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported)) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported);
+ }
+
+ /* Set the state to READY by default */
+ phydev->state = PHY_READY;
+
+out:
+ /* Assert the reset signal */
+ if (err)
+ phy_device_reset(phydev, 1);
+
+ mutex_unlock(&phydev->lock);
+
+ return err;
+}
+
+static int phy_remove(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ cancel_delayed_work_sync(&phydev->state_queue);
+
+ mutex_lock(&phydev->lock);
+ phydev->state = PHY_DOWN;
+ mutex_unlock(&phydev->lock);
+
+ sfp_bus_del_upstream(phydev->sfp_bus);
+ phydev->sfp_bus = NULL;
+
+ if (phydev->drv && phydev->drv->remove)
+ phydev->drv->remove(phydev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ phydev->drv = NULL;
+
+ return 0;
+}
+
+/**
+ * phy_driver_register - register a phy_driver with the PHY layer
+ * @new_driver: new phy_driver to register
+ * @owner: module owning this PHY
+ */
+int phy_driver_register(struct phy_driver *new_driver, struct module *owner)
+{
+ int retval;
+
+ /* Either the features are hard coded, or dynamically
+ * determined. It cannot be both.
+ */
+ if (WARN_ON(new_driver->features && new_driver->get_features)) {
+ pr_err("%s: features and get_features must not both be set\n",
+ new_driver->name);
+ return -EINVAL;
+ }
+
+ new_driver->mdiodrv.flags |= MDIO_DEVICE_IS_PHY;
+ new_driver->mdiodrv.driver.name = new_driver->name;
+ new_driver->mdiodrv.driver.bus = &mdio_bus_type;
+ new_driver->mdiodrv.driver.probe = phy_probe;
+ new_driver->mdiodrv.driver.remove = phy_remove;
+ new_driver->mdiodrv.driver.owner = owner;
+ new_driver->mdiodrv.driver.probe_type = PROBE_FORCE_SYNCHRONOUS;
+
+ retval = driver_register(&new_driver->mdiodrv.driver);
+ if (retval) {
+ pr_err("%s: Error %d in registering driver\n",
+ new_driver->name, retval);
+
+ return retval;
+ }
+
+ pr_debug("%s: Registered new driver\n", new_driver->name);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_driver_register);
+
+int phy_drivers_register(struct phy_driver *new_driver, int n,
+ struct module *owner)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < n; i++) {
+ ret = phy_driver_register(new_driver + i, owner);
+ if (ret) {
+ while (i-- > 0)
+ phy_driver_unregister(new_driver + i);
+ break;
+ }
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_drivers_register);
+
+void phy_driver_unregister(struct phy_driver *drv)
+{
+ driver_unregister(&drv->mdiodrv.driver);
+}
+EXPORT_SYMBOL(phy_driver_unregister);
+
+void phy_drivers_unregister(struct phy_driver *drv, int n)
+{
+ int i;
+
+ for (i = 0; i < n; i++)
+ phy_driver_unregister(drv + i);
+}
+EXPORT_SYMBOL(phy_drivers_unregister);
+
+static struct phy_driver genphy_driver = {
+ .phy_id = 0xffffffff,
+ .phy_id_mask = 0xffffffff,
+ .name = "Generic PHY",
+ .get_features = genphy_read_abilities,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .set_loopback = genphy_loopback,
+};
+
+static const struct ethtool_phy_ops phy_ethtool_phy_ops = {
+ .get_sset_count = phy_ethtool_get_sset_count,
+ .get_strings = phy_ethtool_get_strings,
+ .get_stats = phy_ethtool_get_stats,
+ .start_cable_test = phy_start_cable_test,
+ .start_cable_test_tdr = phy_start_cable_test_tdr,
+};
+
+static int __init phy_init(void)
+{
+ int rc;
+
+ rc = mdio_bus_init();
+ if (rc)
+ return rc;
+
+ ethtool_set_ethtool_phy_ops(&phy_ethtool_phy_ops);
+ features_init();
+
+ rc = phy_driver_register(&genphy_c45_driver, THIS_MODULE);
+ if (rc)
+ goto err_c45;
+
+ rc = phy_driver_register(&genphy_driver, THIS_MODULE);
+ if (rc) {
+ phy_driver_unregister(&genphy_c45_driver);
+err_c45:
+ mdio_bus_exit();
+ }
+
+ return rc;
+}
+
+static void __exit phy_exit(void)
+{
+ phy_driver_unregister(&genphy_c45_driver);
+ phy_driver_unregister(&genphy_driver);
+ mdio_bus_exit();
+ ethtool_set_ethtool_phy_ops(NULL);
+}
+
+subsys_initcall(phy_init);
+module_exit(phy_exit);
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
new file mode 100755
index 0000000..ffade7e
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
@@ -0,0 +1,1514 @@
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <net/sock.h>
+#include <uapi/linux/sched/types.h>
+#include "zvnet_dev.h"
+#include "ram_config.h"
+#include <net/netfilter/nf_conntrack.h>
+#include <net/SI/fast_common.h>
+#include <pub_debug_info.h>
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define USE_ZVNET_PACKET
+
+#define WATCHDOG_TIMEO (5*HZ)
+#define XMIT_RETRANS_TIMES 3
+#define ZVNET_SKB_PAD 128
+#define ZVNET_TMP_BUFF_LEN 2048
+#define ZVNET_FREE_BUFF_NUM 256
+#define ZVNET_XMIT_BUFF_NUM 64
+#define ZVNET_XMIT_MAX_QUEUE_NUM 2048
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+//AP´«µÝ¸øCAPµÄÊý¾Ý°üÐÅÏ¢£¬¸ÃÄÚÈÝдÈë¹²ÏíDDR
+struct T_zvnet_rpmsg
+{
+ void *buff;//skb_headÖ¸Õ룬ÓÃÓÚÊÍ·Åʱ´«µÝ¸øºË¼ä£¬ÒÔ±ã¿ìËÙÊÍ·Å;
+ void *head;//ºË¼äÄÜʹÓõĵØÖ·±ß½ç£¬²»ÄÜÔ½½ç£¬·ñÔòÄÚ´æÒç³öÒì³£;ÎïÀíµØÖ·
+ unsigned short data_off;//ºË¼ä´«µÝÀ´µÄÊý¾Ý°üÊ×µØÖ·£¬Ö¸ÏòMACÖ¡Í·;ÎïÀíµØÖ·
+ unsigned short len;//Êý¾Ý°üÓÐЧ³¤¶È£¬Ò»°ãΪMACÖ¡³¤¶È
+ unsigned short end_off;//end offset
+ unsigned char dev;//cid 1->8
+ unsigned char flag;//0ÆÕͨ°ü£¬1¶þ´Îת·¢°ü£¬2¶þ´Îfastת·¢°ü
+};
+struct T_zvnet_pkt_stats
+{
+ unsigned int pkt;
+ unsigned int len;
+};
+//AP´«µÝ¸øCAPµÄCTÐÅÏ¢£¬¸ÃÄÚÈÝдÈë¹²ÏíDDR
+struct T_zvnet_rpmsg_ctstat
+{
+ void *cap_nfct;
+ unsigned char in;
+ unsigned char out;
+ unsigned short flag;
+ struct T_zvnet_pkt_stats pkt[2];
+};
+struct zvnet_arphdr {
+ unsigned short ar_hrd; /* format of hardware address */
+ unsigned short ar_pro; /* format of protocol address */
+ unsigned char ar_hln; /* length of hardware address */
+ unsigned char ar_pln; /* length of protocol address */
+ unsigned short ar_op; /* ARP opcode (command) */
+ unsigned char ar_sha[ETH_ALEN]; /* sender hardware address */
+ unsigned char ar_sip[4]; /* sender IP address */
+ unsigned char ar_tha[ETH_ALEN]; /* target hardware address */
+ unsigned char ar_tip[4]; /* target IP address */
+};
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+struct zvnet_device zvnet_dev[DDR_ZVNET_DEV_MAX];
+int *vir_addr_ap = NULL;
+struct sk_buff_head g_zvnet_skb_queue;
+struct zvnet_channel g_zvnet_chn_info;
+
+#ifdef USE_ZVNET_PACKET
+void *g_zvnet_free_buff[ZVNET_FREE_BUFF_NUM];
+int g_zvnet_free_num;
+spinlock_t g_zvnet_free_lock;
+struct semaphore g_zvnet_free_sem;
+struct semaphore g_zvnet_xmit_sem;
+struct sk_buff_head g_zvnet_skb_xmit_queue;
+atomic_t g_zvnet_pm_flag;
+
+unsigned int g_wrap_packet_size = 1000;
+module_param(g_wrap_packet_size, int, 0644);
+unsigned int g_wrap_num = 10;
+module_param(g_wrap_num, int, 0644);
+unsigned int g_wrap_timeout = 10;
+module_param(g_wrap_timeout, int, 0644);
+unsigned int g_trace_limit = 0;
+module_param(g_trace_limit, int, 0644);
+#endif
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+extern int (*fast_from_driver)(struct sk_buff *skb, struct net_device* dev);
+extern void v7_dma_map_area(const void *, size_t, int);
+extern void *get_ct_for_ap(struct sk_buff *skb);
+extern void put_ct_for_ap(void *ct);
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+static int zvnet_open(struct net_device *net);
+static int zvnet_close(struct net_device *net);
+static netdev_tx_t zvnet_xmit(struct sk_buff *skb, struct net_device *net);
+static void zvnet_tx_timeout(struct net_device *net, unsigned int txqueue);
+static struct net_device_stats *zvnet_get_stats(struct net_device *net);
+static void v2xnet_init_netdev(struct net_device *net);
+static void zvnet_skb_return (struct zvnet *dev, struct sk_buff *skb);
+static void zvnet_bh (unsigned long param);
+static struct zvnet *v2xnet_dev_init(struct net_device *net, struct zvnet_device *zvnetdev);
+
+static int zvnet_channel_write(struct zvnet_channel *chninfo, void *buf, unsigned int len);
+static int zvnet_channel_read(struct zvnet_channel *chninfo, void *buf, unsigned int len);
+static int zvnet_channel_clear(struct zvnet_channel *chninfo);
+static int zvnet_read_header(struct zvnet_channel *chninfo, struct zvp_header *phzvp);
+static struct sk_buff *zvnet_direct_read_skb(struct zvnet_channel *chninfo);
+static struct sk_buff *zvnet_read_skb(struct zvnet_channel *chninfo, unsigned int tlen, struct zvnet *dev);
+static int zvnet_receive_thread(void *argv);
+static int rpmsgCreateChannel_v2xnet (T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size);
+static int zvnet_createIcpChannel(T_RpMsg_CoreID core_id, T_RpMsg_ChID channel_id, unsigned int channel_size);
+static int zvnet_channel_create(struct zvnet_device *zvnetdev);
+
+/*******************************************************************************
+ * Local function implementations *
+ ******************************************************************************/
+
+unsigned long virt_to_phys_ap(unsigned long virt)
+{
+ if(virt >= (unsigned long)vir_addr_ap && virt <= ((unsigned long)vir_addr_ap+DDR_BASE_LEN_AP))
+ return DDR_BASE_ADDR_AP + (virt - (unsigned long)vir_addr_ap);
+ return NULL;
+}
+
+unsigned long phys_to_virt_ap(unsigned long phys)
+{
+ if(phys >= DDR_BASE_ADDR_AP && phys <= (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP))
+ return (unsigned long)vir_addr_ap + (phys - DDR_BASE_ADDR_AP);
+ return NULL;
+}
+
+/* Started by AICoder, pid:2fa080381bb2e3d14fbc0aa44091291a60d78e35 */
+void check_skb_test(struct sk_buff *skb)
+{
+ if (skb && vir_addr_ap) {
+ struct sk_buff *tmp_skb;
+ if ((skb->capHead && (virt_to_phys_ap(skb->head) == NULL))
+ || ((skb->capHead == NULL) && virt_to_phys_ap(skb->head))) {
+ dump_stack();
+ panic("capHead err");
+ }
+ skb_queue_walk(&g_zvnet_skb_queue, tmp_skb) {
+ if (tmp_skb == skb) {
+ dump_stack();
+ panic("dup free");
+ }
+ }
+ }
+}
+/* Ended by AICoder, pid:2fa080381bb2e3d14fbc0aa44091291a60d78e35 */
+
+/* Started by AICoder, pid:z5702yf8bad07ad1448a083e806dc31250b2418f */
+void zvnet_dump_packet(unsigned char * data, int len, int limit_len)
+{
+ int i = 0;
+ unsigned char *p = data;
+ for(i = 0; i < len && i < limit_len; i+=16)
+ {
+ printk("0x%04x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",i,
+ p[0],p[1],p[2],p[3],p[4],p[5],p[6],p[7],
+ p[8],p[9],p[10],p[11],p[12],p[13],p[14],p[15]);
+ p += 16;
+ }
+}
+/* Ended by AICoder, pid:z5702yf8bad07ad1448a083e806dc31250b2418f */
+
+void zvnet_set_pm_flag(unsigned int flag){
+ if(flag & 0x100000)
+ atomic_set(&g_zvnet_pm_flag, 1);
+}
+
+int zvnet_get_index_by_netdev(struct net_device *net)
+{
+ int i;
+
+ for (i = 0; i < DDR_ZVNET_DEV_MAX; i++) {
+ if(zvnet_dev[i].net == net)
+ return i;
+ }
+ return -1;
+}
+#ifdef USE_ZVNET_PACKET
+void write_free_apbuf_packet(void)
+{
+ int ret,size;
+ unsigned long flags;
+ void *buf[ZVNET_FREE_BUFF_NUM];
+
+ spin_lock_irqsave(&g_zvnet_free_lock, flags);
+ if(g_zvnet_free_num == 0){
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+ return;
+ }
+ size = (g_zvnet_free_num << 2);
+ memcpy(buf, g_zvnet_free_buff, size);
+ g_zvnet_free_num = 0;
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+ {
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = RPMSG_WRITE_INT|RPMSG_WRITE_IRQLOCK};
+ if((size >> 2) > ZVNET_FREE_BUFF_NUM)
+ panic("free packet err");
+ msg.buf = &buf;
+ msg.len = size;
+ zv_info("tofree size=%d", size);
+ ret = zvnetWrite(&msg);
+ if(ret < 0)
+ panic("err, ret:%d!!!!!!", ret);
+ }
+}
+#endif
+//½«CAP²à´«µÝÀ´µÄcapbufÖ¸ÕëдÈëDDR£¬ÒÔICP·½Ê½Í¨ÖªCAP²à
+void write_free_apbuf(void *head)
+{
+#ifdef USE_ZVNET_PACKET
+ unsigned long flags;
+
+ zv_info("g_zvnet_free_num=%d skb=0x%x", g_zvnet_free_num, head);
+ spin_lock_irqsave(&g_zvnet_free_lock, flags);
+ g_zvnet_free_buff[g_zvnet_free_num] = head;
+ g_zvnet_free_num++;
+ if(g_zvnet_free_num == ZVNET_FREE_BUFF_NUM){
+ int size;
+ void *buf[ZVNET_FREE_BUFF_NUM];
+
+ size = (g_zvnet_free_num << 2);
+ memcpy(buf, g_zvnet_free_buff, size);
+ g_zvnet_free_num = 0;
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+ if((size >> 2) > ZVNET_FREE_BUFF_NUM)
+ panic("free packet err");
+ {
+ int ret;
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = RPMSG_WRITE_INT|RPMSG_WRITE_IRQLOCK};
+ msg.buf = &buf;
+ msg.len = size;
+ if(printk_ratelimit())
+ zv_warn("tofree quick size=%d", size);
+ ret = zvnetWrite(&msg);
+ if(ret < 0)
+ panic("err, ret:%d!!!!!!", ret);
+ }
+ return;
+ }
+ if(g_zvnet_free_num > g_wrap_num)
+ up(&g_zvnet_free_sem);
+ if(g_zvnet_free_num > ZVNET_FREE_BUFF_NUM)
+ panic("free_buff err");
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+#else
+ int ret = 0;
+ long buf = (long)head;
+
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = RPMSG_WRITE_INT,
+ .buf = NULL,
+ .len = 4 };
+ msg.buf = &buf;
+ zv_info("tofree 0x%x", head);
+ ret = zvnetWrite(&msg);
+ if(ret < 0)
+ panic("err, ret:%d!!!!!!", ret);
+#endif
+}
+
+struct sk_buff *skb_build_apbuf(struct T_zvnet_rpmsg *pbuf_temp)
+{
+ struct skb_shared_info *shinfo;
+ struct sk_buff *skb;
+ zv_info("build 0x%x 0x%x %d %d", pbuf_temp->buff, pbuf_temp->head, pbuf_temp->data_off, pbuf_temp->len);
+ if((unsigned long )pbuf_temp->head < DDR_BASE_ADDR_AP || (unsigned long )pbuf_temp->head > (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP)){
+ zv_err("err 0x%x 0x%x %d %d", pbuf_temp->buff, pbuf_temp->head, pbuf_temp->data_off, pbuf_temp->len);
+ panic("addr is not APBUF mem!!!");
+ return NULL;
+ }
+ skb = kmem_cache_alloc(skbuff_head_cache, GFP_ATOMIC);
+ if (!skb)
+ {
+ write_free_apbuf(pbuf_temp->buff);
+ zv_err("alloc fail");
+ return NULL;
+ }
+ memset(skb, 0, offsetof(struct sk_buff, tail));
+
+ //ÅжÏÊÇ·ñÊÇapbuff
+
+ if(pbuf_temp->dev < 0 || pbuf_temp->dev >= DDR_ZVNET_DEV_MAX)
+ panic("dev index error!!!");
+ skb->head = phys_to_virt_ap((unsigned long )pbuf_temp->head);
+ skb->data = skb->head + pbuf_temp->data_off;
+ skb->capHead = pbuf_temp->buff;
+ //ÐèÒª¿¼ÂÇcacheÐжÔÆë
+ skb->truesize = SKB_TRUESIZE(skb->data - skb->head + pbuf_temp->len);//°´µÀÀíβ²¿»¹ÓпÉÓõÄÄÚ´æ¿Õ¼ä£¬ÔÝʱδ¿¼ÂÇ;SKB_DATA_ALIGN
+
+ refcount_set(&skb->users, 1);
+ skb_reset_tail_pointer(skb);
+ skb->tail += pbuf_temp->len;
+ skb->len = pbuf_temp->len;
+ skb->end = skb->head + pbuf_temp->end_off;
+ skb->mac_header = (typeof(skb->mac_header))~0U;
+ skb->transport_header = (typeof(skb->transport_header))~0U;
+ skb->dev = zvnet_dev[pbuf_temp->dev].net;
+ if(skb->len == 0 || skb->len > 2000)
+ panic("len ERR!!!!!!!!!!\n");
+ v7_dma_map_area(skb->head, sizeof(struct skb_shared_info) + pbuf_temp->end_off, DMA_FROM_DEVICE);
+ if(IFF_NOARP & skb->dev->flags)
+ memcpy(skb->data, skb->dev->dev_addr, 6);
+ atomic_set(&skb_shinfo(skb)->dataref, 1);
+ /* make sure we initialize shinfo sequentially */
+ skb_reset_network_header(skb);
+ skb_set_kcov_handle(skb, kcov_common_handle());
+ if(unlikely(g_trace_limit & 1)){
+ printk("-%s-dump_fromap-start-%d\n", skb->dev->name, skb->len);
+ zvnet_dump_packet(skb->data, skb->len, g_trace_limit);
+ printk("-%s-dump_fromap-end-\n", skb->dev->name);
+ }
+/* Started by AICoder, pid:j2d34uccf7y1f37146a108290182771184940711 */
+ if (atomic_read(&g_zvnet_pm_flag)) {
+ unsigned short l2_hdr_len = 0;
+ unsigned short h_proto = htons(*(unsigned short *)(skb->data + ETH_ALEN + ETH_ALEN));
+ again:
+ if (l2_hdr_len + ETH_HLEN < skb->len) {
+ switch (h_proto) {
+ case ETH_P_IP: {
+ struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN + l2_hdr_len);
+ if (iph->protocol == IPPROTO_TCP) {
+ struct tcphdr *tcph = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl * 4);
+ char *flag;
+ if (tcph->ack) {
+ if (tcph->fin)
+ flag = "FA";
+ else if (tcph->syn)
+ flag = "SA";
+ else if (tcph->psh)
+ flag = "PA";
+ else
+ flag = "A";
+ } else {
+ if (tcph->fin)
+ flag = "F";
+ else if (tcph->syn)
+ flag = "S";
+ else if (tcph->rst)
+ flag = "R";
+ else
+ flag = "";
+ }
+ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u%s %u:%u/%u\n",
+ pbuf_temp->dev, &iph->saddr, &iph->daddr,
+ iph->protocol, flag, ntohs(tcph->source), ntohs(tcph->dest), skb->len);
+ } else if (iph->protocol == IPPROTO_UDP) {
+ struct udphdr *udph = (struct udphdr *)(((unsigned char *)iph) + iph->ihl * 4);
+ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u %u:%u/%u\n",
+ pbuf_temp->dev, &iph->saddr, &iph->daddr,
+ iph->protocol, ntohs(udph->source), ntohs(udph->dest), skb->len);
+ } else if (iph->protocol == IPPROTO_ICMP) {
+ struct icmphdr *icmph = (struct icmphdr *)(((unsigned char *)iph) + iph->ihl * 4);
+ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u %u:%u/%u\n",
+ pbuf_temp->dev, &iph->saddr, &iph->daddr,
+ iph->protocol, icmph->type, icmph->code, skb->len);
+ } else {
+ sc_debug_info_record("cap_net", "%u-%pI4-%pI4-%u/%u\n",
+ pbuf_temp->dev, &iph->saddr, &iph->daddr,
+ iph->protocol, skb->len);
+ }
+ break;
+ }
+ case ETH_P_IPV6: {
+ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN + l2_hdr_len);
+ if (iph->nexthdr == NEXTHDR_TCP) {
+ struct tcphdr *tcph = (struct tcphdr *)(((unsigned char *)iph) + sizeof(struct ipv6hdr));
+ char *flag;
+ if (tcph->ack) {
+ if (tcph->fin)
+ flag = "FA";
+ else if (tcph->syn)
+ flag = "SA";
+ else if (tcph->psh)
+ flag = "PA";
+ else
+ flag = "A";
+ } else {
+ if (tcph->fin)
+ flag = "F";
+ else if (tcph->syn)
+ flag = "S";
+ else if (tcph->rst)
+ flag = "R";
+ else
+ flag = "";
+ }
+ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u%s %u:%u/%u\n",
+ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
+ iph->nexthdr, flag, ntohs(tcph->source), ntohs(tcph->dest), skb->len);
+ } else if (iph->nexthdr == NEXTHDR_UDP) {
+ struct udphdr *udph = (struct udphdr *)(((unsigned char *)iph) + sizeof(struct ipv6hdr));
+ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u %u:%u/%u\n",
+ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
+ iph->nexthdr, ntohs(udph->source), ntohs(udph->dest), skb->len);
+ } else if (iph->nexthdr == NEXTHDR_ICMP) {
+ struct icmp6hdr *icmph = (struct icmp6hdr *)(((unsigned char *)iph) + sizeof(struct ipv6hdr));
+ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u %u:%u/%u\n",
+ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
+ iph->nexthdr, icmph->icmp6_type, icmph->icmp6_code,skb->len);
+ } else {
+ sc_debug_info_record("cap_net", "%u-%pI6-%pI6-%u/%u\n",
+ pbuf_temp->dev, iph->saddr.s6_addr32, iph->daddr.s6_addr32,
+ iph->nexthdr, skb->len);
+ }
+ break;
+ }
+ case ETH_P_ARP: {
+ struct zvnet_arphdr *arph = (struct zvnet_arphdr *)(skb->data + ETH_HLEN + l2_hdr_len);
+ sc_debug_info_record("cap_net", "%u:%04x-%pI4-%pI4-%u/%u\n",
+ pbuf_temp->dev, h_proto, arph->ar_sip, arph->ar_tip, htons(arph->ar_op), skb->len);
+ break;
+ }
+ case ETH_P_8021Q: {
+ struct vlan_hdr *vlanh = (struct vlan_hdr *)(skb->data + ETH_HLEN + l2_hdr_len);
+ sc_debug_info_record("cap_net", "%u:%04x-%u\n",
+ pbuf_temp->dev, h_proto, htons(vlanh->h_vlan_TCI) & VLAN_VID_MASK);
+ l2_hdr_len += VLAN_HLEN;
+ h_proto = htons(vlanh->h_vlan_encapsulated_proto);
+ goto again;
+ }
+ default:
+ sc_debug_info_record("cap_net", "%u:%04x/%u\n", pbuf_temp->dev, h_proto, skb->len);
+ }
+ }
+ atomic_set(&g_zvnet_pm_flag, 0);
+ }
+/* Ended by AICoder, pid:j2d34uccf7y1f37146a108290182771184940711 */
+ return skb;
+}
+
+int eth_change_mtu(struct net_device *dev, int new_mtu)
+{
+ netdev_warn(dev, "%s is deprecated!\n", __func__);
+ dev->mtu = new_mtu;
+ return 0;
+}
+
+/* Started by AICoder, pid:b001dtf2551fd53146790a57201be3321cf0a682 */
+static void skb_debug_test(struct sk_buff *skb)
+{
+ int i;
+ int vcount = skb->len / 10;
+ int rcount = skb->len % 10;
+ char tmp[64] = {0};
+ char strbuf[64] = {0};
+ const unsigned char *data = skb->data;
+
+ zv_info("\n");
+ for (i = 0; i < vcount; i++) {
+ zv_info("%d---%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", i,
+ data[0 + 10 * i], data[1 + 10 * i], data[2 + 10 * i], data[3 + 10 * i],
+ data[4 + 10 * i], data[5 + 10 * i], data[6 + 10 * i], data[7 + 10 * i],
+ data[8 + 10 * i], data[9 + 10 * i]);
+ }
+ if (vcount > 0) {
+ memset(tmp, 0, sizeof(tmp));
+ sprintf(strbuf, "%d---", vcount);
+ char *p = strbuf + strlen(strbuf);
+
+ for (i = 0; i < rcount; i++) {
+ sprintf(p, "%02x,", data[10 * vcount + i]);
+ p += strlen(p);
+ }
+ *(p - 1) = '\0'; // ÒƳý×îºóÒ»¸ö¶ººÅ
+ zv_info("%s ", strbuf);
+ }
+ zv_info("\n");
+}
+/* Ended by AICoder, pid:b001dtf2551fd53146790a57201be3321cf0a682 */
+
+static int zvnet_open(struct net_device *net)
+{
+ struct zvnet *dev = netdev_priv(net);
+
+ if(net->flags & IFF_UP) {
+ zv_dbg("%s has been opened!", dev->net->name);
+ return -EBUSY;
+ }
+ netif_start_queue (net);
+
+ return 0;
+}
+
+static int zvnet_close(struct net_device *net)
+{
+ struct zvnet *dev = netdev_priv(net);
+
+ zv_info("%s", dev->net->name);
+ netif_stop_queue(net);
+ tasklet_kill (&dev->bh);
+
+ return 0;
+}
+#ifdef USE_ZVNET_PACKET
+static void zvnet_xmit_packet(void)
+{
+ int i,j,k,ret,num;
+ unsigned long flags;
+ unsigned long flags1;
+ struct sk_buff *skb, *tmp;
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 20,
+ .flag = RPMSG_WRITE_INT};
+ static struct T_zvnet_rpmsg buff[ZVNET_XMIT_MAX_QUEUE_NUM+1];
+
+ spin_lock_irqsave(&g_zvnet_skb_xmit_queue.lock, flags);
+ if (skb_queue_empty(&g_zvnet_skb_xmit_queue)) {
+ spin_unlock_irqrestore(&g_zvnet_skb_xmit_queue.lock, flags);
+ return;
+ }
+ i = 0;
+ skb_queue_walk_safe(&g_zvnet_skb_xmit_queue, skb, tmp) {
+ //buff[i].buff = skb;
+ buff[i].data_off = skb->data - skb->head;
+ //buff[i].head = virt_to_phys(skb->head);
+ buff[i].len = skb->len;
+ buff[i].end_off = skb->end - skb->head;
+ buff[i].dev = zvnet_get_index_by_netdev(skb->dev);
+ if(unlikely(g_trace_limit & 2)){
+ printk("-%s-dump_toap-start-%d\n", skb->dev->name, skb->len);
+ zvnet_dump_packet(skb->data, skb->len, g_trace_limit);
+ printk("-%s-dump_toap-end-\n", skb->dev->name);
+ }
+ if(skb->capHead){
+ buff[i].buff = skb->capHead;
+#ifdef CONFIG_FASTNAT_MODULE
+ if(skb->isFastnat){
+ buff[i].head = get_ct_for_ap(skb);
+ buff[i].flag = 2;
+ }else
+#endif
+ {
+ buff[i].head = NULL;
+ buff[i].flag = 1;
+ }
+ __skb_unlink(skb, &g_zvnet_skb_xmit_queue);
+ kfree_skb(skb);
+ }else{
+ buff[i].buff = skb;
+ buff[i].head = virt_to_phys(skb->head);
+ buff[i].flag = 0;
+ }
+ i++;
+ zv_info("xmit skb=0x%x i=%d", skb, i);
+ if(i > ZVNET_XMIT_MAX_QUEUE_NUM){
+ panic("qlen:%d!", i);
+ break;
+ }
+ }
+ spin_lock_irqsave(&g_zvnet_skb_queue.lock, flags1);
+ skb_queue_splice_tail_init(&g_zvnet_skb_xmit_queue, &g_zvnet_skb_queue);
+ spin_unlock_irqrestore(&g_zvnet_skb_queue.lock, flags1);
+ spin_unlock_irqrestore(&g_zvnet_skb_xmit_queue.lock, flags);
+ zv_info("g_zvnet_skb_queue.qlen=%d i=%d", g_zvnet_skb_queue.qlen, i);
+ for(j = 0; j < i; j = j + ZVNET_XMIT_BUFF_NUM){
+ if(i <= (j + ZVNET_XMIT_BUFF_NUM)){
+ msg.buf = (void *)&buff[j];
+ msg.len = sizeof(struct T_zvnet_rpmsg)*(i-j);/*±¾´ÎÄÜÈ¡¹â*/
+ ret = zvnetWrite(&msg);
+ }else{
+ msg.buf = (void *)&buff[j];
+ msg.len = sizeof(struct T_zvnet_rpmsg)*ZVNET_XMIT_BUFF_NUM;
+ ret = zvnetWrite(&msg);
+ }
+ zv_info("xmit write ret=%d size=%d i=%d j=%d", ret, msg.len, i, j);
+ if(ret < 0) {
+ if(printk_ratelimit())
+ zv_warn("zvnet_channel_write ret=%d fail.",ret);
+ num = msg.len / sizeof(struct T_zvnet_rpmsg);
+ for(k = j; k < j+num; k++){
+ if(buff[k].flag == 0){
+ skb = (struct sk_buff *)buff[k].buff;
+ skb_unlink(skb, &g_zvnet_skb_queue);
+ skb->isToap = 0;
+ kfree_skb(skb);
+ }else{
+ if(buff[k].head)
+ put_ct_for_ap(buff[k].head);
+ write_free_apbuf(buff[k].buff);
+ }
+ }
+ }
+ }
+}
+#endif
+static netdev_tx_t zvnet_xmit(struct sk_buff *skb, struct net_device *net)
+{
+#ifdef USE_ZVNET_PACKET
+ struct sk_buff *data = NULL;
+
+ //zv_info("g_zvnet_skb_xmit_queue.qlen=%d", g_zvnet_skb_xmit_queue.qlen);
+ if(g_zvnet_skb_xmit_queue.qlen >= ZVNET_XMIT_MAX_QUEUE_NUM){
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ zv_err("write err, qlen:%d!", g_zvnet_skb_xmit_queue.qlen);
+ kfree_skb(skb);
+ return NET_XMIT_SUCCESS;
+ }
+
+ if(unlikely(skb->next//|| skb->capHead || skb_headroom(skb) < NET_SKB_PAD
+ || skb->fclone || skb->cloned || (skb_shinfo(skb)->nr_frags) || skb->sk || (skb->indev == NULL)
+ || (skb_shinfo(skb)->tx_flags & SKBTX_DEV_ZEROCOPY) || (skb_has_frag_list(skb)))){
+ int ret_len = skb->len;
+
+ data = dev_alloc_skb(ret_len + NET_IP_ALIGN);
+ if (unlikely(!data)) {
+ zv_err("dev_alloc_skb fail,len %d",ret_len);
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ kfree_skb(skb);
+ return NET_XMIT_SUCCESS;
+ }
+ skb_put(data,ret_len);
+ skb_reserve(data, NET_IP_ALIGN);
+ memcpy(data->data, skb->data, ret_len);
+ zv_info("ap=0x%x next=0x%x clone=%d nr_frags=%d tx_flags=%d frag_list=0x%x", skb->capHead, skb->next, skb->cloned, (skb_shinfo(skb)->nr_frags), skb_shinfo(skb)->tx_flags, skb_shinfo(skb)->frag_list);
+ kfree_skb(skb);
+ }else{
+ data = skb;
+ }
+ data->dev = net;
+ data->isToap = 1;
+ v7_dma_map_area(data->head, data->end - data->head + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
+ net->stats.tx_packets++;
+ net->stats.tx_bytes += data->len;
+ skb_queue_tail(&g_zvnet_skb_xmit_queue, data);
+ if(data->len < g_wrap_packet_size || g_zvnet_skb_xmit_queue.qlen > g_wrap_num)
+ up(&g_zvnet_xmit_sem);
+#else
+ struct zvnet *dev = netdev_priv(net);
+ struct zvnet_device *zvnetdev = (struct zvnet_device *)dev->dev_priv;
+ int ret = 0;
+ struct zvp_header hzvp;
+
+ if (!skb) {
+ zv_err("err: skb == 0!");
+ }
+#if 0
+ if (skb->len > ZVNET_TMP_BUFF_LEN) {
+ zv_err("err: skb->len(%d)>%d!", skb->len, ZVNET_TMP_BUFF_LEN);
+ }
+
+send_header:
+ ret = zvnet_channel_write(&(zvnetdev->chn_info), skb->data, skb->len);
+
+ if((ret < 0) && (zvnetdev->retran_times < XMIT_RETRANS_TIMES)) {
+ zvnetdev->retran_times ++;
+ zv_warn("The retran_times is %d.",zvnetdev->retran_times);
+ goto send_header;
+ }
+
+ if (ret >= 0) {
+ net->stats.tx_packets++;
+ net->stats.tx_bytes += skb->len;
+ } else {
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ zv_err("write err, ret:%d!", ret);
+ }
+
+exit:
+ kfree_skb(skb);
+#else
+ struct T_zvnet_rpmsg buff = {0};
+ struct sk_buff *data = NULL;
+ if(unlikely(skb_headroom(skb) < NET_SKB_PAD || skb->capHead || skb->next
+ || skb->fclone || skb->cloned || (skb_shinfo(skb)->nr_frags)
+ || (skb_shinfo(skb)->tx_flags & SKBTX_DEV_ZEROCOPY) || (skb_has_frag_list(skb)))){
+ int ret_len = skb->len;
+
+ data = dev_alloc_skb(ret_len + NET_IP_ALIGN);
+ if (unlikely(!data)) {
+ zv_err("dev_alloc_skb fail,len %d",ret_len);
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ kfree_skb(skb);
+ return NET_XMIT_SUCCESS;
+ }
+ skb_put(data,ret_len);
+ skb_reserve(data, NET_IP_ALIGN);
+ memcpy(data->data, skb->data, ret_len);
+ data->isToap = 1;
+ buff.buff = data;
+ buff.data_off = data->data - data->head;
+ buff.head = virt_to_phys(data->head);
+ buff.len = ret_len;
+ buff.end_off = data->end - data->head;
+ buff.dev = zvnet_get_index_by_netdev(net);
+ zv_info("alloc 0x%x 0x%x %d %d", buff.buff, buff.head, buff.data_off, buff.len);
+ zv_info("ap=0x%x next=0x%x clone=%d nr_frags=%d tx_flags=%d frag_list=0x%x", skb->capHead, skb->next, skb->cloned, (skb_shinfo(skb)->nr_frags), skb_shinfo(skb)->tx_flags, skb_shinfo(skb)->frag_list);
+ v7_dma_map_area(data->head, buff.end_off + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
+ }else{
+ skb->isToap = 1;
+ buff.buff = skb;
+ buff.data_off = skb->data - skb->head;
+ buff.head = virt_to_phys(skb->head);
+ buff.len = skb->len;
+ buff.end_off = skb->end - skb->head;
+ buff.dev = zvnet_get_index_by_netdev(net);
+ zv_info("transfer 0x%x %d 0x%x %d", buff.buff, buff.head, buff.data_off, buff.len);
+ v7_dma_map_area(skb->head, buff.end_off + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
+ }
+send_header:
+ ret = zvnet_channel_write(&g_zvnet_chn_info, &buff, sizeof(struct T_zvnet_rpmsg));
+
+ if((ret < 0) && (zvnetdev->retran_times < XMIT_RETRANS_TIMES)) {
+ zvnetdev->retran_times ++;
+ zv_warn("The retran_times is %d.",zvnetdev->retran_times);
+ goto send_header;
+ }
+
+ if (ret >= 0) {
+ net->stats.tx_packets++;
+ net->stats.tx_bytes += skb->len;
+ if(data){
+ kfree_skb(skb);
+ skb_queue_tail(&g_zvnet_skb_queue, data);
+ }else
+ skb_queue_tail(&g_zvnet_skb_queue, skb);
+ zvnetdev->retran_times = 0;
+ } else {
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ zv_err("write err, ret:%d!", ret);
+ if(data){
+ data->isToap = 0;
+ kfree_skb(data);
+ }
+ else
+ skb->isToap = 0;
+ kfree_skb(skb);
+ }
+#endif
+#endif
+ return NET_XMIT_SUCCESS;
+}
+
+/* Called by the kernel when transmit times out */
+static void zvnet_tx_timeout(struct net_device *net, unsigned int txqueue)
+{
+ zv_warn("sent timeout!");
+ net->stats.tx_errors++;
+ netif_wake_queue(net);
+}
+
+static struct net_device_stats *zvnet_get_stats(struct net_device *net)
+{
+ return &net->stats;
+}
+
+const struct net_device_ops zvnet_netdev_ops = {
+ .ndo_open = zvnet_open,
+ .ndo_stop = zvnet_close,
+ .ndo_start_xmit = zvnet_xmit,
+ .ndo_tx_timeout = zvnet_tx_timeout,
+ .ndo_get_stats = zvnet_get_stats,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = eth_mac_addr,
+};
+
+static void v2xnet_init_netdev(struct net_device *net)
+{
+ u8 node_id [ETH_ALEN];
+
+ random_ether_addr(node_id);
+ memcpy (net->dev_addr, node_id, sizeof node_id);
+
+ net->netdev_ops = &zvnet_netdev_ops;
+ net->watchdog_timeo = WATCHDOG_TIMEO;
+ net->flags |= IFF_NOARP;
+}
+
+static void zvnet_skb_return (struct zvnet *dev, struct sk_buff *skb)
+{
+ int status;
+
+ //zv_info("enter...");
+
+ //skb->protocol = eth_type_trans(skb, dev->net);
+
+ status = netif_rx (skb);
+ if (status == NET_RX_SUCCESS) {
+ dev->net->stats.rx_packets++;
+ dev->net->stats.rx_bytes += skb->len;
+ } else {
+ dev->net->stats.rx_errors++;
+ zv_err("netif_rx status %d.", status);
+ }
+}
+
+static void zvnet_bh (unsigned long param)
+{
+ struct zvnet *dev = (struct zvnet *)param;
+ struct sk_buff *skb;
+
+ while((skb = skb_dequeue(&dev->rxq)) != NULL) {
+ if (skb->len)
+ zvnet_skb_return(dev, skb);
+ else {
+ dev->net->stats.rx_errors++;
+ dev_kfree_skb (skb);
+ zv_err("drop!!!ddrnet_bh skb len == 0.");
+ }
+ }
+}
+
+static struct zvnet *v2xnet_dev_init(struct net_device *net, struct zvnet_device *zvnetdev)
+{
+ struct zvnet *dev = NULL;
+
+ dev = netdev_priv(net);
+ if(!dev) {
+ zv_err("dev is null.\n");
+ return NULL;
+ }
+
+ dev->net = net;
+ dev->bh.func = zvnet_bh;
+ dev->bh.data = (unsigned long) dev;
+
+ skb_queue_head_init (&dev->rxq);
+
+ dev->dev_priv = zvnetdev;
+
+ return dev;
+}
+
+/*·µ»ØÖµ´óÓÚµÈÓÚ0£¬±íʾдͨµÀ³É¹¦£»Ð¡ÓÚ0±íʾдͨµÀʧ°Ü*/
+static int zvnet_channel_write(struct zvnet_channel *chninfo, void *buf, unsigned int len)
+{
+ T_RpMsg_Msg msg;
+
+ if(NULL == buf) {
+ return -EINVAL;
+ }
+ memset(&msg, 0, sizeof(msg));
+ msg.coreID = chninfo->core_id;
+ msg.chID = chninfo->channel_id;
+ msg.flag |= RPMSG_WRITE_INT; //| RPMSG_WRITE_IRQLOCK;
+ msg.buf = buf;
+ msg.len = len;
+
+ return zvnetWrite(&msg);
+}
+
+/*·µ»ØÖµ´óÓÚ0£¬±íʾ¶ÁȡͨµÀ³É¹¦£»Ð¡ÓÚµÈÓÚ0±íʾͨµÀÊý¾ÝΪ¿Õ»òʧ°Ü*/
+static int zvnet_channel_read(struct zvnet_channel *chninfo, void *buf, unsigned int len)
+{
+ T_RpMsg_Msg msg;
+ int ret = 0;
+
+ if(NULL == buf) {
+ return -EINVAL;
+ }
+
+ memset(&msg, 0, sizeof(msg));
+ msg.coreID = chninfo->core_id;
+ msg.chID = chninfo->channel_id;
+ msg.buf = buf;
+ msg.len = len;
+
+ ret = zvnetRead(&msg);
+ if (ret <= 0) {
+ zv_err("rpm read err=%d!",ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int zvnet_channel_clear(struct zvnet_channel *chninfo)
+{
+ char *tbuf = NULL;
+ unsigned int tlen = chninfo->channel_size/2;
+ int ret = 0;
+
+ tbuf = (char *)kzalloc(tlen,GFP_ATOMIC);
+ if(IS_ERR(tbuf)) {
+ zv_err("kzalloc fail! %d byte.", tlen);
+ return -ENOMEM;
+ }
+ ret = zvnet_channel_read(chninfo, tbuf, tlen);
+ if(ret < 0) {
+ zv_err("zvnet_channel_read fail!");
+ ret = 0;
+ }
+ kfree(tbuf);
+ zv_err("Drop channel data. %d byte.",ret);
+
+ return ret;
+}
+
+static int zvnet_read_header(struct zvnet_channel *chninfo, struct zvp_header *phzvp)
+{
+ return zvnet_channel_read(chninfo, phzvp, sizeof(struct zvp_header));
+}
+
+static struct sk_buff *zvnet_read_skb(struct zvnet_channel *chninfo, unsigned int tlen, struct zvnet *dev)
+{
+ struct sk_buff *skb;
+
+ if(NULL == chninfo || 0 >= tlen || NULL == dev) {
+ return NULL;
+ }
+ skb = dev_alloc_skb(tlen);
+ if (unlikely(!skb)) {
+ zv_err("netdev_alloc_skb fail,len %d",tlen);
+ return NULL;
+ }
+ skb_put(skb,tlen);
+
+ if(zvnet_channel_read(chninfo, (void *)skb->data, tlen) != tlen) {
+ zv_err("zvnet_channel_read fail.\n");
+ kfree_skb(skb);
+ return NULL;
+ }
+
+ zv_info("%s dev receive packet %d byte.",dev->net->name, tlen);
+
+ skb->dev = dev->net;
+
+ return skb;
+}
+
+static struct sk_buff *zvnet_direct_read_skb(struct zvnet_channel *chninfo)
+{
+ struct sk_buff *skb;
+#if 0
+/* Started by AICoder, pid:sd1cfsbc2eu87c41445f09652039f525fa147687 */
+int ret_len = 0;
+struct sk_buff *skb;
+
+ret_len = zvnet_channel_read(chninfo, NULL, 0); // »ñÈ¡ÐèÒª¶ÁÈ¡µÄÊý¾Ý³¤¶È
+if(ret_len <= 0) {
+ zv_err("zvnet_channel_read fail.\n");
+ return NULL;
+}
+
+skb = dev_alloc_skb(ret_len + ZVNET_SKB_PAD);
+if (unlikely(!skb)) {
+ zv_err("netdev_alloc_skb fail,len %d",ret_len);
+ return NULL;
+}
+
+ret_len = zvnet_channel_read(chninfo, skb->data, ret_len); // ¶ÁÈ¡Êý¾Ýµ½skb->data
+if(ret_len <= 0) {
+ kfree_skb(skb); // Èç¹û¶Áȡʧ°Ü£¬ÊÍ·ÅÒÑ·ÖÅäµÄskb
+ zv_err("zvnet_channel_read fail.\n");
+ return NULL;
+}
+
+skb_put(skb,ret_len);
+skb_reserve(skb, ZVNET_SKB_PAD);
+/* Ended by AICoder, pid:sd1cfsbc2eu87c41445f09652039f525fa147687 */
+#else
+ struct T_zvnet_rpmsg buff = {0};
+ int ret_len = 0;
+ ret_len = zvnet_channel_read(chninfo, (void *)&buff, sizeof(struct T_zvnet_rpmsg));
+
+ if(ret_len <= 0) {
+ zv_err("rpm read err=%d", ret_len);
+ msleep(1000);
+ return NULL;
+ }
+ if(ret_len != sizeof(struct T_zvnet_rpmsg)) {
+ panic("err, ret:%d!!!!!!", ret_len);
+ }
+ skb = skb_build_apbuf(&buff);
+ if (unlikely(!skb)) {
+ zv_err("netdev_alloc_skb fail,len %d",ret_len);
+ return NULL;
+ }
+#endif
+ //skb->dev = dev->net;
+ return skb;
+}
+
+static int zvnet_receive_thread(void *argv)
+{
+ //struct zvnet_device *zvnetdev = (struct zvnet_device *)argv;
+ //struct zvnet_channel *chninfo = NULL;
+ struct zvnet *dev = NULL;
+ int index,ret_len,i,num;
+ unsigned long flags;
+ struct sk_buff *skb = NULL;
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 20,
+ .flag = 0};
+ struct T_zvnet_rpmsg buff[ZVNET_XMIT_BUFF_NUM];
+ //struct zvp_header hzvp;
+/*
+ if(IS_ERR(zvnetdev)) {
+ zv_err("The receive thread create fail!");
+ return -EINVAL;
+ }
+ chninfo = &zvnetdev->chn_info;
+ dev = zvnetdev->dev;
+*/
+ while(1) {
+/*
+ if(unlikely(!(zvnetdev->net->flags & IFF_UP))) {
+ msleep(1000);
+ continue;
+ }
+*/
+ //memset(&hzvp, 0, sizeof(hzvp));
+#ifdef USE_ZVNET_PACKET
+ //ret_len = zvnet_channel_read(&g_zvnet_chn_info, (void *)buff, sizeof(struct T_zvnet_rpmsg)*ZVNET_XMIT_BUFF_NUM);
+ msg.buf = (void *)(buff); // Êý¾Ý
+ msg.len = sizeof(struct T_zvnet_rpmsg)*ZVNET_XMIT_BUFF_NUM;// ¶ÁÈ¡µÄ³¤¶È
+ ret_len = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+ zv_info("zvnetRead ret=%d", ret_len);
+ if(ret_len <= 0) {
+ zv_err("rpm read err=%d", ret_len);
+ msleep(1000);
+ continue;
+ }
+ if((ret_len % sizeof(struct T_zvnet_rpmsg)) != 0) {
+ panic("err, ret:%d!!!!!!", ret_len);
+ }
+ num = ret_len / sizeof(struct T_zvnet_rpmsg);
+ for(i = 0; i < num; i++){
+ skb = skb_build_apbuf(&buff[i]);
+ if (unlikely(!skb)) {
+ zv_err("skb_build_apbuf fail,len=%d i=%d",ret_len,i);
+ continue;
+ }
+ if(unlikely(!(skb->dev->flags & IFF_UP))) {
+ if(printk_ratelimit())
+ zv_err("drop!!!%s is down.", skb->dev->name);
+ dev_kfree_skb (skb);
+ continue;
+ }
+ skb->protocol = eth_type_trans(skb, skb->dev);
+ if (fast_from_driver && fast_from_driver(skb, skb->dev))
+ {
+ continue;
+ }
+ index = zvnet_get_index_by_netdev(skb->dev);
+ if(index < 0)
+ panic("");
+ dev = zvnet_dev[index].dev;
+ spin_lock_irqsave(&dev->rxq.lock, flags);
+ __skb_queue_tail(&dev->rxq, skb);
+ spin_unlock_irqrestore(&dev->rxq.lock, flags);
+ tasklet_schedule(&dev->bh);
+ }
+#else
+ if(0 != (skb = zvnet_direct_read_skb(&g_zvnet_chn_info))) {
+ //skb_debug_test(skb);
+ if(unlikely(!(skb->dev->flags & IFF_UP))) {
+ zv_err("drop!!!%s is down.", skb->dev->name);
+ dev_kfree_skb (skb);
+ continue;
+ }
+ skb->protocol = eth_type_trans(skb, skb->dev);
+#if 1
+ if (fast_from_driver && fast_from_driver(skb, skb->dev))
+ {
+ continue;
+ }
+#endif
+ index = zvnet_get_index_by_netdev(skb->dev);
+ if(index < 0)
+ panic("");
+ dev = zvnet_dev[index].dev;
+ spin_lock_irqsave(&dev->rxq.lock, flags);
+ __skb_queue_tail(&dev->rxq, skb);
+ spin_unlock_irqrestore(&dev->rxq.lock, flags);
+ tasklet_schedule(&dev->bh);
+ }
+ else {
+ zv_err("zvnet_read_header fail.");
+ msleep(1000);
+ }
+#endif
+ }
+
+ zv_err("The receive thread exit!");
+ return 0;
+}
+
+static int rpmsgCreateChannel_v2xnet (T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
+{
+ return zvnetCreateChannel (dstCoreID, chID, size);
+}
+
+static int zvnet_createIcpChannel(T_RpMsg_CoreID core_id, T_RpMsg_ChID channel_id, unsigned int channel_size)
+{
+ int retval;
+
+ retval = rpmsgCreateChannel_v2xnet (core_id, channel_id, channel_size);
+ if(retval != RPMSG_SUCCESS && retval != RPMSG_CHANNEL_ALREADY_EXIST)
+ goto out;
+
+ return retval;
+
+out:
+ zv_err("could not create channel.");
+ return retval;
+}
+/*
+static int zvnet_channel_create(struct zvnet_device *zvnetdev)
+{
+ struct task_struct *th = NULL;
+ int retval = 0;
+ struct zvnet_channel *chninfo = NULL;
+
+ if (IS_ERR(zvnetdev)) {
+ return -EINVAL;
+ }
+ chninfo = &(zvnetdev->chn_info);
+ retval = zvnet_createIcpChannel(chninfo->core_id, chninfo->channel_id, chninfo->channel_size);
+ if(retval < 0) {
+ zv_err("Create IcpChannel fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_receive_thread, (void *)zvnetdev, "zvnet-recv%d", chninfo->channel_id);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start receive thread.");
+ return PTR_ERR(th);
+ }
+ chninfo->rcv_thread = th;
+
+ return 0;
+}
+*/
+static int zvnet_release_thread(void * nouse)
+{
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = 0};
+ void *buff[ZVNET_FREE_BUFF_NUM];
+ int i,num,retval;
+ struct sk_buff *skb;
+ struct sched_param param = { .sched_priority = 1 };
+ param.sched_priority = 37;
+ sched_setscheduler(current, SCHED_FIFO, ¶m);
+
+ while(1) {
+ zv_info("g_zvnet_skb_queue.qlen=%d", g_zvnet_skb_queue.qlen);
+#ifdef USE_ZVNET_PACKET
+ msg.buf = (unsigned char *)(buff); // Êý¾Ý
+ msg.len = 4*ZVNET_FREE_BUFF_NUM;// ¶ÁÈ¡µÄ³¤¶È
+ retval = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+ zv_info("free read ret=%d", retval);
+ if (retval <= 0) {
+ zv_err("rpm read err=%d", retval);
+ msleep(1000);
+ continue;
+ }
+ if((retval%4) != 0) {
+ panic("err, ret:%d!!!!!!", retval);
+ }
+ num = retval>>2;
+ for(i = 0; i < num; i++){
+ skb = (struct sk_buff *)buff[i];
+ zv_info("free 0x%x", skb);
+ if (skb == NULL || skb->next == NULL || skb->prev == NULL) {
+ panic("rpm read=%d i=%d NULL", retval, i);
+ continue;
+ }
+ skb_unlink(skb, &g_zvnet_skb_queue);
+ if(skb->isToap != 1)
+ panic("");
+ skb->isToap = 0;
+ kfree_skb(skb);
+ }
+#else
+ void *buff;
+ msg.coreID = CORE_PS0;
+ msg.chID = 29;
+ msg.buf = (unsigned char *)(&buff); // Êý¾Ý
+ msg.len = 4;// ¶ÁÈ¡µÄ³¤¶È
+ //msg.flag |= RPMSG_READ_POLL;
+
+ retval = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+ if (retval <= 0) {
+ zv_err("no msg or threand exited");
+ msleep(1000);
+ continue;
+ }
+ if(retval != 4) {
+ panic("err, ret:%d!!!!!!", retval);
+ }
+ zv_info("free 0x%x", buff);
+ skb = (struct sk_buff *)buff;
+ skb_unlink(skb, &g_zvnet_skb_queue);
+ if(skb->isToap != 1)
+ panic("");
+ skb->isToap = 0;
+ kfree_skb(skb);
+#endif
+ }
+ zv_err("The realse thread exit!");
+ return 0;
+}
+#ifdef USE_ZVNET_PACKET
+static int zvnet_xmit_warp_thread(void * nouse)
+{
+ while(1) {
+ down_timeout(&g_zvnet_xmit_sem, msecs_to_jiffies(g_wrap_timeout));
+ zvnet_xmit_packet();
+ }
+ zv_err("The xmit warp thread exit!");
+ return 0;
+}
+
+static int zvnet_free_warp_thread(void * nouse)
+{
+ while(1) {
+ down_timeout(&g_zvnet_free_sem, msecs_to_jiffies(g_wrap_timeout));
+ write_free_apbuf_packet();
+ }
+ zv_err("The free warp thread exit!");
+ return 0;
+}
+#endif
+
+static int zvnet_update_thread(void * nouse)
+{
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 21,
+ .flag = 0};
+ int ret_len = 0;
+ struct nf_conn *ct;
+ fast_entry_t *entry;
+ struct net_device *in;
+ struct net_device *out;
+
+ while(1) {
+ struct T_zvnet_rpmsg_ctstat buff = {0};
+ msg.buf = (void *)(&buff); // Êý¾Ý
+ msg.len = sizeof(struct T_zvnet_rpmsg_ctstat);// ¶ÁÈ¡µÄ³¤¶È
+ ret_len = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+
+ if(ret_len <= 0) {
+ zv_err("rpm read err=%d", ret_len);
+ msleep(1000);
+ continue;
+ }
+ if(ret_len != sizeof(struct T_zvnet_rpmsg_ctstat)) {
+ panic("err, ret:%d!!!!!!", ret_len);
+ }
+ ct = (struct nf_conn *)buff.cap_nfct;
+ WARN_ON(atomic_read(&ct->ct_general.use) == 0);
+ if(buff.flag){
+ if(!(buff.pkt[0].pkt || buff.pkt[0].len || buff.pkt[1].pkt || buff.pkt[1].len))
+ continue;
+ BUG_ON(buff.in <= 0 || buff.out <= 0);
+ in = zvnet_dev[buff.in-1].net;
+ out = zvnet_dev[buff.out-1].net;
+ if(buff.pkt[0].pkt && buff.pkt[0].len){
+ zv_info("nf_update %x %s %s %d %d", buff.cap_nfct, ct->indev[0]->name, ct->outdev[0]->name, buff.in, buff.out);
+ in->stats.rx_packets += buff.pkt[0].pkt;
+ in->stats.rx_bytes += buff.pkt[0].len;
+ out->stats.tx_packets += buff.pkt[0].pkt;
+ out->stats.tx_bytes += buff.pkt[0].len;
+ }
+ if(buff.pkt[1].pkt && buff.pkt[1].len){
+ zv_info("nf_update %x %s %s %d %d", buff.cap_nfct, ct->indev[1]->name, ct->outdev[1]->name, buff.out, buff.in);
+ out->stats.rx_packets += buff.pkt[1].pkt;
+ out->stats.rx_bytes += buff.pkt[1].len;
+ in->stats.tx_packets += buff.pkt[1].pkt;
+ in->stats.tx_bytes += buff.pkt[1].len;
+ }
+ spin_lock_bh(&fast_fw_spinlock);
+ /*¸üÐÂÁ´½Ó³¬Ê±*/
+ if (IPPROTO_TCP == nf_ct_protonum(ct))
+ {
+ ct->timeout = jiffies + tcp_timeouts[ct->proto.tcp.state];
+ }else if (IPPROTO_UDP == nf_ct_protonum(ct)){
+ /*udp*/
+ if (test_bit(IPS_SEEN_REPLY_BIT, &ct->status)){
+ ct->timeout = jiffies + fast_udp_timeout_stream;
+ }else{
+ ct->timeout = jiffies + fast_udp_timeout;
+ }
+ }
+ entry = (fast_entry_t *)ct->fast_entry;
+ if(entry){
+ WARN_ON(entry->ct != ct);
+ mod_timer(&entry->timeout, ct->timeout);
+ }
+ ct->packet_info[IP_CT_DIR_ORIGINAL].bytes += buff.pkt[IP_CT_DIR_ORIGINAL].len;
+ ct->packet_info[IP_CT_DIR_ORIGINAL].packets += buff.pkt[IP_CT_DIR_ORIGINAL].pkt;
+ ct->packet_info[IP_CT_DIR_REPLY].bytes += buff.pkt[IP_CT_DIR_REPLY].len;
+ ct->packet_info[IP_CT_DIR_REPLY].packets += buff.pkt[IP_CT_DIR_REPLY].pkt;
+ if(ct->indev[0] && is_vlan_dev(ct->indev[0])){
+ struct net_device *tmp = vlan_dev_real_dev(ct->indev[0]);
+ struct vlan_pcpu_stats *stats = this_cpu_ptr(vlan_dev_priv(ct->indev[0])->vlan_pcpu_stats);
+
+ if(tmp == in){
+/* Started by AICoder, pid:tbef0151bf4135d1479d0a5d108c870bc756e858 */
+u64_stats_update_begin(&stats->syncp);
+stats->rx_packets += buff.pkt[0].pkt;
+stats->rx_bytes += buff.pkt[0].len;
+stats->tx_packets += buff.pkt[1].pkt;
+stats->tx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:tbef0151bf4135d1479d0a5d108c870bc756e858 */
+ }else if(tmp == out){
+/* Started by AICoder, pid:y34f7id6bcs049f144f10bb8a05c9703b196635b */
+u64_stats_update_begin(&stats->syncp);
+stats->tx_packets += buff.pkt[0].pkt;
+stats->tx_bytes += buff.pkt[0].len;
+stats->rx_packets += buff.pkt[1].pkt;
+stats->rx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:y34f7id6bcs049f144f10bb8a05c9703b196635b */
+ }else
+ zv_err("nf_update0 %s->%s!=%s-%s", in->name, out->name, tmp->name, ct->indev[0]->name);
+ }
+ if(ct->indev[1] && is_vlan_dev(ct->indev[1])){
+ struct net_device *tmp = vlan_dev_real_dev(ct->indev[1]);
+ struct vlan_pcpu_stats *stats = this_cpu_ptr(vlan_dev_priv(ct->indev[1])->vlan_pcpu_stats);
+
+ if(tmp == in){
+/* Started by AICoder, pid:8bef0t51bfu135d1479d0a5d108c870bc756e858 */
+u64_stats_update_begin(&stats->syncp);
+stats->rx_packets += buff.pkt[0].pkt;
+stats->rx_bytes += buff.pkt[0].len;
+stats->tx_packets += buff.pkt[1].pkt;
+stats->tx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:8bef0t51bfu135d1479d0a5d108c870bc756e858 */
+ }else if(tmp == out){
+/* Started by AICoder, pid:934f7zd6bcl049f144f10bb8a05c9703b196635b */
+u64_stats_update_begin(&stats->syncp);
+stats->tx_packets += buff.pkt[0].pkt;
+stats->tx_bytes += buff.pkt[0].len;
+stats->rx_packets += buff.pkt[1].pkt;
+stats->rx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:934f7zd6bcl049f144f10bb8a05c9703b196635b */
+ }else
+ zv_err("nf_update1 %s->%s!=%s-%s", in->name, out->name, tmp->name, ct->indev[1]->name);
+ }
+ spin_unlock_bh(&fast_fw_spinlock);
+ zv_info("nf_update %x %d %d %d %d", buff.cap_nfct, buff.pkt[0].pkt, buff.pkt[0].len, buff.pkt[1].pkt, buff.pkt[1].len);
+ }else{
+ zv_info("nf_put %x", buff.cap_nfct);
+ WRITE_ONCE(ct->timeout, nfct_time_stamp);
+ nf_conntrack_put(buff.cap_nfct);
+ }
+ }
+ zv_err("The update thread exit!");
+ return 0;
+}
+
+/*******************************************************************************
+ * Global function implementations *
+ ******************************************************************************/
+static int __init zvnet_init(void)
+{
+ int i;
+ int err = -ENOMEM;
+ struct zvnet *dev = NULL;
+ struct net_device *net = NULL;
+ struct zvnet_device *zvnetdev = NULL;
+
+ atomic_set(&g_zvnet_pm_flag, 0);
+#ifdef USE_ZVNET_PACKET
+ skb_queue_head_init(&g_zvnet_skb_xmit_queue);
+ spin_lock_init(&g_zvnet_free_lock);
+ sema_init(&g_zvnet_free_sem, 0);
+ sema_init(&g_zvnet_xmit_sem, 0);
+#endif
+ skb_queue_head_init(&g_zvnet_skb_queue);
+ g_zvnet_chn_info.core_id = CORE_PS0;
+ g_zvnet_chn_info.channel_id = ICP_CHN_ZVNET1;
+ g_zvnet_chn_info.channel_size = ICP_CHANNEL_SIZE;
+ for (i = 0; i < DDR_ZVNET_DEV_MAX; i++) {
+ zvnetdev = &zvnet_dev[i];
+ memset(zvnetdev, 0, sizeof(struct zvnet_device));
+ net = alloc_etherdev(sizeof(struct zvnet));
+ if (!net) {
+ zv_err("could not allocate device.\n");
+ return err;
+ }
+
+ //net->needed_headroom += ZVNET_SKB_PAD;//NET_SKB_PAD;
+ sprintf(net->name, "%s%d", ZVNET_IFNAME_PREFIX, i);
+ dev = v2xnet_dev_init(net, zvnetdev);
+ v2xnet_init_netdev(net);
+ if(0 == i || i > 8){
+ net->flags = (net->flags & (~IFF_NOARP));
+ }
+ err = register_netdev(net);
+ if (err) {
+ zv_err("register_netdev error:%d :%d\n",err,i);
+ return err;
+ }
+ zvnetdev->dev = dev;
+ zvnetdev->net = net;
+/*
+ zvnetdev->chn_info.core_id = CAP_ID;
+ zvnetdev->chn_info.channel_id = ICP_CHN_ZVNET1 + i;//zvnet_collect[i];
+ zvnetdev->chn_info.channel_size = ICP_CHANNEL_SIZE;
+ err = zvnet_channel_create(zvnetdev);
+ if(0 != err) {
+ zv_err("zvnet_channel_create error:%d :%d\n",err,i);
+ goto out_unregister_netdev;
+ }
+*/
+ }
+ {
+ struct task_struct *th = NULL;
+ int retval = 0;
+ retval = zvnet_createIcpChannel(CORE_PS0, 21, 64);
+ if(retval < 0) {
+ zv_err("Create IcpChannel channel_21 fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_update_thread, 0, "zvnet-update%d", 21);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start update thread.");
+ return PTR_ERR(th);
+ }
+ retval = zvnet_createIcpChannel(CORE_PS0, 20, ICP_CHANNEL_SIZE);
+ if(retval < 0) {
+ zv_err("Create IcpChannel channel_20 fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_receive_thread, 0, "zvnet-recv%d", 20);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start receive thread.");
+ return PTR_ERR(th);
+ }
+ g_zvnet_chn_info.rcv_thread = th;
+
+ retval = zvnet_createIcpChannel(CORE_PS0, 29, ICP_CHANNEL_SIZE);
+ if(retval < 0) {
+ zv_err("Create IcpChannel channel_29 fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_release_thread, 0, "zvnet-free%d", 29);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start release thread.");
+ return PTR_ERR(th);
+ }
+#ifdef USE_ZVNET_PACKET
+ th = kthread_run(zvnet_xmit_warp_thread, 0, "zvnet-xmit-wrap");
+ if (IS_ERR(th)) {
+ zv_err("Unable to start xmit_warp thread.");
+ return PTR_ERR(th);
+ }
+
+ th = kthread_run(zvnet_free_warp_thread, 0, "zvnet-free-wrap");
+ if (IS_ERR(th)) {
+ zv_err("Unable to start free_warp thread.");
+ return PTR_ERR(th);
+ }
+#endif
+ vir_addr_ap = ioremap_cache(DDR_BASE_ADDR_AP, DDR_BASE_LEN_AP);
+ zv_warn("vir_addr_ap vir=0x%x phy=0x%x len=0x%x", vir_addr_ap, DDR_BASE_ADDR_AP, DDR_BASE_LEN_AP);
+ if(vir_addr_ap == NULL)
+ {
+ zv_err("AP mmap failed.\n");
+ return -1;
+ }
+
+ }
+ zv_dbg("success.\n");
+ return 0;
+
+}
+
+static void __exit zvnet_exit(void)
+{
+ int i;
+ struct net_device *net;
+
+ for (i = 0; i < DDR_ZVNET_DEV_MAX; i++) {
+ net = zvnet_dev[i].net;
+ unregister_netdev(net);
+ free_netdev(net);
+ zvnet_dev[i].net = NULL;
+ }
+ zv_warn("success.\n");
+}
+
+late_initcall(zvnet_init);
+module_exit(zvnet_exit);
+
+MODULE_AUTHOR("ZXIC");
+MODULE_DESCRIPTION("ZXIC CAP LAN NET DEVICE");
+MODULE_LICENSE("GPL");
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
new file mode 100755
index 0000000..0e1ca16
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
@@ -0,0 +1,493 @@
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/syscore_ops.h>
+#include <linux/gpio.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/sc/common.h>
+#include <linux/soc/sc/spinlock.h>
+#include <pub_debug_info.h>
+
+#include "icp_dev.h"
+#include "zx29_icp.h"
+#include "icp_rpmsg.h"
+
+static icp_callback_fn _icp_fn;
+static T_HalIcp_Reg *icp_ap2m0_reg;
+static T_HalIcp_Reg *icp_ap2ps_reg;
+
+static inline T_HalIcp_Reg *icp_get_reg(T_ZDrvRpMsg_ActorID actor_id)
+{
+ if (CORE_M0 == actor_id )
+ return icp_ap2m0_reg;
+ else if (CORE_PS0 == actor_id )
+ return icp_ap2ps_reg;
+ else
+ BUG();
+}
+
+/*******************************************************************************
+* Function: icp_set_int
+* Description: This function is used for generating icp interrupt to inform remote cpu;
+* Parameters:
+* Input:
+ actorID: id of remote cpu
+ chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+static int icp_set_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
+ return -EINVAL;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ icp_reg->control.low_word = (1<<chID);
+ else
+ icp_reg->control.high_word = (1<<(chID-32));
+
+ return 0;
+}
+
+/*******************************************************************************
+* Function: icp_clear_int
+* Description: This function is used for clear icp interrupt from remote cpu;
+* Parameters:
+* Input:
+ actorID: id of remote cpu
+ chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+static void icp_clear_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ icp_reg->clear.low_word = (1<<chID);
+ else
+ icp_reg->clear.high_word = (1<<(chID-32)) ;
+}
+
+/*******************************************************************************
+* Function: icp_get_int
+* Description: This function is used for get icp interrupt from remote cpu;
+* Parameters:
+* Input:
+* actorID: id of remote cpu
+* chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+T_HalIcp_Dword icp_get_int(T_ZDrvRpMsg_ActorID actorID)
+{
+ T_HalIcp_Dword IcpState;
+ T_HalIcp_Reg *icp_reg;
+
+ if (actorID >= CORE_MAXID)
+ {
+ IcpState.high_word = 0;
+ IcpState.low_word = 0;
+
+ return IcpState;
+ }
+
+ icp_reg = icp_get_reg(actorID);
+
+ IcpState.high_word = icp_reg->state.high_word;
+ IcpState.low_word = icp_reg->state.low_word;
+
+ return IcpState;
+}
+
+/*******************************************************************************
+* Function: icp_get_int_state
+* Description: This function is used for get the state of icp interruptting of remote cpu;
+* Parameters:
+* Input:
+ actorID: id of remote cpu
+ chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+static int icp_get_int_state(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ {
+ if(icp_reg->in_state.low_word & (0x1<<chID))
+ return true;
+ }
+ else
+ {
+ if(icp_reg->in_state.high_word & (0x1<<(chID-32)))
+ return true;
+ }
+
+ return false;
+}
+
+/*******************************************************************************
+* Function: icp_mask_int
+* Description: This function is used for Mask interrupt of channel;
+* Parameters:
+* Input:
+* Output:
+*
+* Returns: NONE
+*
+*
+* Others:
+********************************************************************************/
+static int icp_mask_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
+ return -EINVAL;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ icp_reg->mask.low_word |= (0x1<<chID);
+ else
+ icp_reg->mask.high_word |= (0x1<<(chID-32));
+
+ return 0;
+}
+
+/*******************************************************************************
+* Function: icp_unmask_int
+* Description: This function is used for unmask interrupt of channel;
+* Parameters:
+* Input:
+* Output:
+*
+* Returns:
+* NONE
+*
+*
+* Others:
+********************************************************************************/
+static int icp_unmask_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
+ return -EINVAL;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID < 32)
+ icp_reg->mask.low_word &= ~(0x1<<chID);
+ else
+ icp_reg->mask.high_word &= ~(0x1<<(chID-32));
+
+ return 0;
+}
+
+int icp_int_count = 0;
+#ifdef CONFIG_ZX29_WATCHDOG
+extern void zx_wdt_icp_wake(void);
+#endif
+irqreturn_t icp_isr(int irq, void *data)
+{
+ icp_msg _icp_msg;
+ T_HalIcp_Dword IcpState;
+ unsigned int i;
+
+ _icp_msg.src_id = (unsigned int)data;
+
+ IcpState = icp_get_int(_icp_msg.src_id);
+
+ for(i=0; i<CHANNEL_MAXID(_icp_msg.src_id); i++)
+ {
+ if((((i<32)&&((IcpState.low_word>>i) & 0x1))||((i>=32)&&((IcpState.high_word>>(i-32)) & 0x1)))) {
+ _icp_msg.event_id = i;
+ #ifdef CONFIG_ZX29_WATCHDOG
+ if((CORE_M0 == _icp_msg.src_id)&&(2 == i))
+ zx_wdt_icp_wake();
+ #endif
+ if(_icp_fn)
+ _icp_fn(&_icp_msg);
+
+ icp_clear_int(_icp_msg.src_id, i);
+ }
+ }
+
+ icp_int_count ++;
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * for loopback test
+ */
+void fake_icp_isr(T_RpMsg_CoreID src_core, T_RpMsg_CoreID dest_core, T_RpMsg_ChID ch)
+{
+ icp_msg _icp_msg;
+ unsigned int i;
+
+ _icp_msg.src_id = src_core;
+ _icp_msg.dest_core = dest_core;
+ _icp_msg.event_id = ch;
+
+ if(_icp_fn)
+ _icp_fn(&_icp_msg);
+}
+
+/*
+ * for get wake state
+ */
+void icp_get_int_info(T_ZDrvRpMsg_ActorID actorID, unsigned int *high_word, unsigned int *low_word)
+{
+ T_HalIcp_Dword IcpState;
+
+ IcpState = icp_get_int(actorID);
+
+ *high_word = IcpState.high_word;
+ *low_word = IcpState.low_word;
+}
+
+static const char * const ps_channel_info[64] = {
+ [0] = "drv test",
+ [2] = "Power Management",
+ [3] = "ADB agent",
+ [4] = "USB app config",
+ [5] = "USB kernel config",
+ [6] = "audio",
+ [7] = "console switch",
+ [8] = "NV",
+ [9] = "debug",
+ [10] = "ramdump",
+ [11] = "tee common",
+ [12] = "tee RPC",
+ [13] = "ap2cap message queue",
+ [14] = "cap2ap message queue",
+ [15] = "AMT framework",
+ [16] = "APP rsvd 16",
+ [17] = "APP rsvd 17",
+ [18] = "APP rsvd 18",
+ [19] = "APP rsvd 19",
+ [20] = "zvnet 20",
+ [21] = "zvnet 21",
+ [22] = "zvnet 22",
+ [23] = "zvnet 23",
+ [24] = "zvnet 24",
+ [25] = "zvnet 25",
+ [26] = "zvnet 26",
+ [27] = "zvnet 27",
+ [28] = "zvnet 28",
+ [29] = "free skb",
+ [30] = "ttygs0",
+ [31] = "ttygs1",
+ [32] = "socket ipc",
+ [33] = "binder ipc",
+ [34] = "at channel 34",
+ [35] = "at channel 35",
+ [36] = "at channel 36",
+ [37] = "at channel 37",
+ [38] = "at channel 38",
+ [39] = "at channel 39",
+ [40] = "at channel 40",
+ [41] = "voice buffer",
+};
+extern void zvnet_set_pm_flag(unsigned int flag);
+void show_icp_state(T_ZDrvRpMsg_ActorID actorID)
+{
+ unsigned int hw, lw;
+ int i;
+
+ if (actorID != CORE_PS0)
+ return;
+
+ icp_get_int_info(actorID, &hw, &lw);
+ zvnet_set_pm_flag(lw);
+ pr_info("[SLP] icpwake: 0x%x 0x%x\n", hw, lw);
+ sc_debug_info_record(MODULE_ID_CAP_PM, " icpwake: 0x%x 0x%x\n", hw, lw);
+
+ for (i=0; i<32; i++)
+ if (lw&BIT(i))
+ pr_info("[SLP] icpwake: channel(%d) function(%s)\n", i, ps_channel_info[i] ? ps_channel_info[i] : "NA");
+
+ for (i=0; i<32; i++)
+ if (hw&BIT(i))
+ pr_info("[SLP] icpwake: channel(%d) function(%s)\n", i+32, ps_channel_info[i+32] ? ps_channel_info[i+32] : "NA");
+}
+
+static void icp_register_callback(icp_callback_fn cb)
+{
+ _icp_fn = cb;
+}
+
+static int icp_send_message(unsigned int core_id, icp_msg *icp_msg)
+{
+ if(!icp_msg || icp_msg->dest_core > CORE_MAXID )
+ return -EINVAL;
+
+ if(icp_get_int_state(icp_msg->dest_core, icp_msg->event_id)==false)
+ {
+ icp_set_int(icp_msg->dest_core, icp_msg->event_id);
+ }
+
+ return 0;
+}
+
+static t_icpdev_ops zx29_icp_ops = {
+ .register_callback = icp_register_callback,
+ .send_message = icp_send_message,
+ .mask_int = icp_mask_int,
+ .unmask_int = icp_unmask_int,
+ .set_int = icp_set_int,
+};
+
+static int icp_ap2ps_init(struct device *dev)
+{
+ void __iomem *reg_base;
+ unsigned int irq;
+ int ret;
+ struct device_node *np = dev->of_node;
+
+ reg_base = of_iomap(np, 0);
+ if ( !reg_base ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_MEM\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2ps_reg = (T_HalIcp_Reg *)reg_base;
+
+ irq = irq_of_parse_and_map(np, 0);
+ if( !irq ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_IRQ\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2ps_reg->mask.high_word = 0xffffffff;
+ icp_ap2ps_reg->mask.low_word = 0xffffffff;
+
+ ret = request_irq(irq, icp_isr, 0, "zx_icp", CORE_PS0);
+ if (ret)
+ {
+ pr_err("%s: [ICP]register irq failed\n", __func__);
+ return ret;
+ }
+
+ enable_irq_wake(irq);
+
+ icpdev_register_ops(&zx29_icp_ops);
+
+ rpmsgInit(CORE_PS0, np);
+/*
+ dev->id = CORE_PS0;
+ ret = icp_rpmsg_device_register(dev);
+*/
+ pr_info("%s: ok! irq(%d) icp_address(%llx \n", __func__, irq, reg_base );
+
+ return ret;
+}
+
+static int icp_ap2m0_init(struct device *dev)
+{
+ void __iomem *reg_base;
+ unsigned int irq;
+ int ret;
+ struct device_node *np = dev->of_node;
+
+ pr_info("%s: enter \n", __func__);
+
+ reg_base = of_iomap(np, 0);
+ if ( !reg_base ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_MEM\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2m0_reg = (T_HalIcp_Reg *)reg_base;
+
+ irq = irq_of_parse_and_map(np, 0);
+ if( !irq ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_IRQ\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2m0_reg->mask.high_word = 0xffffffff;
+ icp_ap2m0_reg->mask.low_word = 0xffffffff;
+
+ ret = request_irq(irq, icp_isr, 0, "zx_icp", CORE_M0);
+ if (ret)
+ {
+ pr_err("%s: [ICP]register irq failed\n", __func__);
+ return ret;
+ }
+
+ enable_irq_wake(irq);
+
+ icpdev_register_ops(&zx29_icp_ops);
+
+ rpmsgInit(CORE_M0, np);
+
+ pr_info("%s: ok! irq(%d) icp_address(%llx \n", __func__, irq, reg_base );
+
+ return 0;
+}
+
+static const struct of_device_id zx29_icp_dt_ids[] = {
+ { .compatible = "zte,zx29-icp-ap2m0", .data = &icp_ap2m0_init },
+ { .compatible = "zte,zx29-icp-ap2ps", .data = &icp_ap2ps_init },
+ { /* sentinel */ }
+};
+
+static int zx29_icp_probe(struct platform_device *pdev)
+{
+ int (*init_fn)(struct device *dev);
+
+ init_fn = of_device_get_match_data(&pdev->dev);
+ if (!init_fn) {
+ dev_err(&pdev->dev, "Error: No device match found\n");
+ return -ENODEV;
+ }
+
+ return init_fn(&pdev->dev);
+}
+
+static struct platform_driver zx29_icp_driver = {
+ .driver = {
+ .name = "zx29-icp",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(zx29_icp_dt_ids),
+ },
+ .probe = zx29_icp_probe,
+};
+
+builtin_platform_driver(zx29_icp_driver)
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
new file mode 100755
index 0000000..7029976
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
@@ -0,0 +1,4555 @@
+/****************************************************************************/
+/*
+ * zx29_uart.c sanchips
+ *
+ * (C) Copyright 2003-2007, gaowei
+ * (C) Copyright 2003-2007, sanchips
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/****************************************************************************/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/printk.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <linux/sched/clock.h>
+#include <linux/soc/zte/spinlock.h>
+
+#if 0
+#include <mach/gpio_def.h>
+#include <mach/irqs.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/debug.h>
+#include <mach/iomap.h>
+#include <mach/dma.h>
+#include <mach/dma_cfg.h>
+#endif
+//#include <linux/wakelock.h>
+#include <linux/kthread.h>
+#include <linux/semaphore.h>
+
+#include <linux/dma/zx-dma.h>
+//#include "../../dma/zte/zx298501_dma.h"
+
+#include "zx29_uart.h"
+#include <linux/soc/zte/rpmsg.h>
+#include <linux/soc/sc/drv_idle.h>
+#include "pub_debug_info.h"
+//#include <linux/soc/zte/pm/drv_idle.h>
+//#include <mach/pcu.h>
+//#define DEBUG_UART
+
+#ifdef DEBUG_UART
+#pragma GCC optimize("O0")
+#endif
+
+#define UART_WCLK_NAME "uartclk"
+#define UART_APBCLK_NAME "apb_pclk"
+
+#define CONFIG_SERIAL_ZX29_DMA 1
+
+
+extern bool xp2xp_Ap2CpIsApWakeup(void);
+extern int xp2xp_enable_4line(void);
+
+extern signed int zx29_dma_stop(unsigned int channel_id);
+extern signed int zx29_dma_get_transfer_num(unsigned int channel_id);
+
+
+
+char uart_names[5][12] = {
+ "zx29_uart.0",
+ "zx29_uart.1",
+ "zx29_uart.2",
+ "zx29_uart.3",
+ "zx29_uart.4"
+};
+
+#if CONFIG_SERIAL_ZX29_DMA
+#define ZX29_DMA_BUFFER_SIZE PAGE_SIZE
+#define UART_DMA_RX_MAX_COUNT 2
+//#define RX_DMA_TIMEOUT (HZ / 10)//60
+#define RX_DMA_TIMEOUT (HZ / 100)
+#define RX_DMA_WORK 1
+struct zx29_sgbuf {
+ struct scatterlist sg;
+ dma_addr_t dma_addr;
+ char *buf;
+};
+
+struct zx29_dmarx_data {
+ struct dma_chan *chan;
+ struct completion complete;
+ dma_channel_def rx_def[UART_DMA_RX_MAX_COUNT];
+ u32 rx_index;
+ bool use_buf_b;
+ struct zx29_sgbuf sgbuf_a;
+ struct zx29_sgbuf sgbuf_b;
+ dma_cookie_t cookie;
+ bool running;
+ atomic_t count;
+ bool used;
+};
+
+struct zx29_dmatx_data {
+ struct dma_chan *chan;
+ struct completion complete;
+ dma_channel_def tx_def;
+ struct scatterlist sg;
+ char *buf;
+ bool queued;
+ atomic_t count;
+};
+#define UART_DEBUG_RECORDER_BYTE 0
+#define UART_DMA_CYCLE_RX_CONFIG_COUNT 5
+struct zx29_dma_cycle_data{
+ int id;
+ int flg_enter_th;
+ int flg_enter_to;
+ char flg_overrun;
+ char flg_pe;
+ char flg_be;
+ char flg_fe;
+ char from_resume;
+ unsigned long cnt_callback_total;
+ unsigned long cnt_th_total;
+ int cnt_callback;
+ int cnt_th;
+ struct zx29_sgbuf sgbuf[UART_DMA_CYCLE_RX_CONFIG_COUNT];
+ dma_channel_def rxdef[UART_DMA_CYCLE_RX_CONFIG_COUNT];
+ bool enter_throttle;
+ bool from_unthrottle;
+ bool used;
+ unsigned int cnt_throttle;
+ unsigned int cnt_unthrottle;
+};
+struct zx29_dma_cycle_data uart_dma_cycle[6];
+#endif
+
+
+
+#define UART_NUM 5
+int g_uart_overrun[5];
+ktime_t g_hr_interval;
+
+
+int g_cons_id_cmdline;
+EXPORT_SYMBOL(g_cons_id_cmdline);
+
+#ifdef DEBUG_CONSOLE
+#undef DEBUG_CONSOLE
+#endif
+#define DEBUG_CONSOLE g_cons_id_cmdline
+/****************************************************************************/
+
+/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
+ * name, but it is legally reserved for the 8250 driver. */
+#define SERIAL_zx29_MAJOR TTY_MAJOR
+#define SERIAL_MINOR_START 64
+
+#define UART_PORT_AUTOBAUD_ON 1
+#define UART_PORT_AUTOBAUD_OFF 0
+#define UART_PORT_AUTOBAUD_BYTE 2
+#define UART_AT_SENDOK_NUM 6
+#define UART_AUTOBAUD_LEVEL 5
+#define UART_AUTOBAUD_CHECKBYTE 4
+#define UART_AUTOBAUD_RATE 115200
+#define UART1_AUTOBAUD_RATE 921600
+
+
+unsigned char uart_port_autobaud_buffer[UART_PORT_AUTOBAUD_BYTE] = {0};
+unsigned char uart_port_autobaud_gtflag = 0 ;
+unsigned char uart_port_autobaud_suflag = 0 ;
+unsigned char g_console_open_flag = 1;
+
+
+unsigned char UART_AT_send_ok[UART_AT_SENDOK_NUM] =
+ {
+ 0x0d,0x0a,0x4F,0x4B,0x0d,0x0a
+ };
+
+unsigned char UART_baud_check[UART_AUTOBAUD_LEVEL][UART_AUTOBAUD_CHECKBYTE]=
+ {
+ {0x61,0x74,0x41,0x54},{0x06,0x9e,0x06,0x98},{0x1c,0x80,0x1c,0x00},
+ {0xe0,0x00,0xe0,0x00},{0x00,0x00,0x00,0x00},
+ };
+unsigned int UART_baud[UART_AUTOBAUD_LEVEL] =
+ {
+ 115200,57600,38400,19200,9600
+ };
+unsigned int UART_termios_cflag[UART_AUTOBAUD_LEVEL] =
+ {
+ B115200,B57600,B38400,B19200,B9600
+ };
+
+#ifdef CONFIG_SERIAL_CORE_CONSOLE
+#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
+#else
+#define uart_console(port) (0)
+#endif
+
+/****************************************************************************/
+/*
+ * Local per-uart structure.
+ */
+struct zx29_uart_port
+{
+ struct uart_port port;
+ unsigned int sigs; /* Local copy of line sigs */
+ unsigned int old_status;
+ unsigned char imr; /* Local interrupt mask reg mirror */
+#if CONFIG_SERIAL_ZX29_DMA
+ unsigned char dmacr; /* DMA reg*/
+#endif
+ bool rts_state;
+ bool autorts; /* hardware flow control */
+ struct clk *wclk; /* uart work clock */
+ struct clk *busclk; /* uart apb clock */
+ bool autobaud;
+ bool autobaud_state;
+ unsigned int baudrate;
+ bool uartwake;
+
+ int irq;
+ int irq_state;
+ int rxd_irq;
+ struct tasklet_struct write_wakeup;
+ bool rxd_wakeup;
+ int rxd_int_depth;
+ bool enter_suspend;
+#if CONFIG_SERIAL_ZX29_DMA
+ /* DMA stuff */
+ bool using_tx_dma;
+ bool using_rx_dma;
+ struct zx29_dmarx_data dmarx;
+ struct zx29_dmatx_data dmatx;
+ struct timer_list rx_dma_timer;
+ struct hrtimer rx_dma_hrtimer;
+ struct task_struct *dma_compl_th;
+ struct semaphore sema;
+ struct semaphore sema_cyclic;
+ bool port_close;
+ bool work_state;
+ size_t pre_pending;
+ struct zx29_sgbuf *sg2tty;
+ size_t sg2tty_len;
+ struct zx29_sgbuf *curr_sg;
+ int enable_ctsrts;
+ int enable_wakeup;
+
+ struct notifier_block wakeup_notifier;
+
+#endif
+ //means application decide close and release DMA &wakelock
+ int app_ctrl;
+ int sleep_state;
+ //if app_ctrl is set or using kernel control sleep,set this flag
+ int uart_power_mode;
+};
+
+
+
+static struct zx29_uart_port zx29_uart_ports[UART_NUM];
+
+#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
+typedef struct __UART_STATIC{
+ int cnt;
+ char head[16];
+ unsigned long long s_time;
+ int func_step;
+ unsigned int fr;
+ unsigned int ris;
+}uart_static;
+#define STATIC_UART_ID 0
+#define UART_STATIC_COUNT 512
+#define UART_STATIC_NUM 4
+uart_static g_uart_static[UART_STATIC_NUM][UART_STATIC_COUNT] = {0};
+int g_uart_static_cnt[UART_STATIC_NUM] = {0};
+void test_uart_static(int uart_id, char *buf, unsigned int cnt, int steps)
+{
+ //if(uart_id != STATIC_UART_ID)
+ // return;
+ if(buf){
+ if(cnt >= 16){
+ memcpy(g_uart_static[uart_id][g_uart_static_cnt[uart_id]].head, buf, 16);
+ }else{
+ memcpy(g_uart_static[uart_id][g_uart_static_cnt[uart_id]].head, buf, cnt);
+ }
+ }
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].cnt = cnt;
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].s_time = local_clock();
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].func_step = steps;
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].fr = UART_GET_FR(&zx29_uart_ports[uart_id].port);
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].ris = UART_GET_RIS(&zx29_uart_ports[uart_id].port);
+
+ if(++g_uart_static_cnt[uart_id] >= UART_STATIC_COUNT)
+ g_uart_static_cnt[uart_id] = 0;
+}
+
+
+
+
+#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
+void zx29_uart_stop_rx(struct uart_port *port);
+
+#if CONFIG_SERIAL_ZX29_DMA
+static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup);
+static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup);
+static bool zx29_dma_tx_irq(struct zx29_uart_port *zup);
+static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup);
+void uart_dma_rx_callback(void *data);
+void uart_dma_rx_callback_use_dma_cyclic(void * data);
+static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
+ //u32 pending, bool use_buf_b,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ bool readfifo, unsigned long *flags);
+static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup);
+static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup);
+static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup);
+static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup);
+static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup);
+
+static void zx29_uart_rx_dma_chars(struct zx29_uart_port *zup, unsigned long *flags);
+dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup);
+
+#if RX_DMA_WORK
+static void zx29_uart_rx_timeout_chars(struct zx29_uart_port *zup, unsigned long *flags);
+static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup);
+
+static void zx29_uart_rt_dma(struct zx29_uart_port *zup, unsigned long *flags);
+static void uart_dma_cycle_deinit(struct zx29_uart_port *zup);
+#endif
+#endif
+
+
+
+/*******************************************************************************
+* Function: uart_wakeup_callback.
+* Description: uart_wakeup_callback.
+* Parameters:
+* Input:val:means wakeup or sleep notify to other device
+*
+* Output:v:means devices been called return result
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+int uart_wakeup_callback(struct notifier_block * nb, unsigned long val, void * v)
+{
+ int *call_result = (int *)v;
+ unsigned long flags = 0;
+ struct zx29_uart_port *zup = container_of(nb, struct zx29_uart_port, wakeup_notifier);
+
+ if(!zup || zup->port_close){
+ *call_result |= 0;
+ return 0;
+ }
+ struct platform_device *pdev = zup->port.private_data;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ if(val == 1){//wakeup
+ zup->sleep_state = 0;
+ pm_stay_awake(&pdev->dev);
+ zx29_uart_rx_dma_chars(zup, &flags);
+
+ }else{//sleep
+ zup->sleep_state = 1;
+ zx29_uart_stop_rx(&zup->port);
+ pm_relax(&pdev->dev);
+
+ }
+ *call_result |= 0;
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return 0;
+}
+
+int zx29_get_sleep_state(int uart_index)
+{
+ if(uart_index < 0 || uart_index > 2){
+ printk("invalid uart index\n");
+ return -1;
+ }
+
+ return zx29_uart_ports[uart_index].sleep_state;
+}
+EXPORT_SYMBOL_GPL(zx29_get_sleep_state);
+
+void zx29_set_sleep_state(int state, int uart_index)
+{
+ if(uart_index < 0 || uart_index > 2){
+ printk("invalid uart index\n");
+ return ;
+ }
+ printk(" uart %d, state change to:%d\n", uart_index, state);
+ zx29_uart_ports[uart_index].sleep_state = (state ? 1: 0);
+}
+EXPORT_SYMBOL_GPL(zx29_set_sleep_state);
+
+static ssize_t sleep_state_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "\n wakeup_enable = %d\n",zx29_uart_ports[pdev->id].sleep_state);
+}
+
+static ssize_t sleep_state_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ flag = simple_strtoul(buf, NULL, 16);
+ //pdata->uart_wakeup_enable = flag;
+ zx29_uart_ports[pdev->id].sleep_state = (flag ? 1: 0);
+ return count;
+}
+
+DEVICE_ATTR(sleep_state, S_IRUGO | S_IWUSR, sleep_state_show,
+ sleep_state_store);
+//bool uart_dma_filter_fn (struct dma_chan *chan, void *param)
+//{
+// dma_peripheral_id peri_id = (dma_peripheral_id) param;
+// if (chan->chan_id == (unsigned int)peri_id){
+// printk("uart_dma_filter_fn, peri_id:%d, ok\n", peri_id);
+// return true;
+// }
+// chan->private = param;
+//
+// return false;
+//}
+static void zx29_uart_console_putc(struct uart_port *port, int c);
+void zx29_uart_putc(struct uart_port *port, int c);
+
+#if CONFIG_SERIAL_ZX29_DMA
+void uart_mod_timer(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ unsigned long t_delay = 0;
+ t_delay = msecs_to_jiffies(RX_DMA_TIMEOUT);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ //printk("uart_mod_timer, delay %d jiffies\n", t_delay);
+ mod_timer(&(zup->rx_dma_timer), jiffies + t_delay);
+
+ spin_lock_irqsave(&zup->port.lock, *flags);
+}
+#endif
+/**
+* Show the console_input attribute.
+*/
+static ssize_t console_input_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "\n console_input = %d\n",g_console_open_flag);
+}
+
+/**
+ * Store the console_input attribure.
+ * 0: disable console input function,only out put log
+ * 1: able console input, can input commands
+ */
+static ssize_t console_input_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ flag = simple_strtoul(buf, NULL, 16);
+ g_console_open_flag = flag;
+
+ return count;
+}
+
+DEVICE_ATTR(console_input, S_IRUGO | S_IWUSR, console_input_show,
+ console_input_store);
+
+static ssize_t ctsrts_input_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ if(pdev->id < 0 || pdev->id >= UART_NUM){
+ printk("ctsrts_input_store, invalid uart id, return error\n");
+ return 0;
+ }
+// return sprintf(buf, "\n ctsrts_input = %d\n",pdata->uart_ctsrtsuse);
+return sprintf(buf, "\n uart %d ctsrts_input = %d\n", pdev->id, zx29_uart_ports[pdev->id].enable_ctsrts);
+
+}
+
+static ssize_t ctsrts_input_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+
+ if(pdev->id != 0){
+ printk("ctsrts_input_store, invalid uart id, only uart support hardware control\n");
+ }
+ flag = simple_strtoul(buf, NULL, 16);
+ zx29_uart_ports[pdev->id].enable_ctsrts = flag;
+
+ return count;
+}
+
+DEVICE_ATTR(ctsrts_input, S_IRUGO | S_IWUSR, ctsrts_input_show,
+ ctsrts_input_store);
+
+static ssize_t wakeup_enable_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "\n wakeup_enable = %d\n",1);
+}
+
+static ssize_t wakeup_enable_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ if(pdev->id != 4){
+ printk("\nctsrts_input_store, invalid uart id, only lp_uart(uart 4) support wakeup\n");
+ }
+ flag = simple_strtoul(buf, NULL, 16);
+ zx29_uart_ports[pdev->id].enable_wakeup = flag;
+
+ return count;
+}
+
+DEVICE_ATTR(wakeup_enable, S_IRUGO | S_IWUSR, wakeup_enable_show,
+ wakeup_enable_store);
+
+static ssize_t app_ctrl_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "%d\n",zx29_uart_ports[pdev->id].app_ctrl);
+}
+
+static ssize_t app_ctrl_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ flag = simple_strtoul(buf, NULL, 16);
+ // pdata->uart_wakeup_enable = flag;
+ zx29_uart_ports[pdev->id].app_ctrl = (flag == 0) ? 0 : 1;
+
+ return count;
+}
+DEVICE_ATTR(app_ctrl, S_IRUGO | S_IWUSR, app_ctrl_show,
+ app_ctrl_store);
+
+int rxd_wake_cnt = 0;
+static ssize_t statics_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "\n RX:%u,TX:%u,OE:%u,brk:%u,FE:%u,PE:%u ,rxd_wake_cnt:%d\n",
+ zx29_uart_ports[pdev->id].port.icount.rx,
+ zx29_uart_ports[pdev->id].port.icount.tx,
+ zx29_uart_ports[pdev->id].port.icount.overrun,
+ zx29_uart_ports[pdev->id].port.icount.brk,
+ zx29_uart_ports[pdev->id].port.icount.frame,
+ zx29_uart_ports[pdev->id].port.icount.parity,
+ rxd_wake_cnt
+ );
+}
+DEVICE_ATTR(statics, S_IRUGO, statics_show, NULL);
+
+static unsigned int uart_io_seletc = 0;
+
+
+static ssize_t uart_io_select_show(struct device *_dev,
+struct device_attribute *attr, char *buf)
+{
+struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+return sprintf(buf, "%d\n",uart_io_seletc );
+
+}
+
+static ssize_t uart_io_select_store(struct device *_dev,
+struct device_attribute *attr,
+const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+flag = simple_strtoul(buf, NULL, 16);
+
+if(flag == 1){
+ printk("uart io is 1\n");
+pinctrl_pm_select_default_state(_dev);
+}else if(flag == 0){
+pinctrl_pm_select_sleep_state(_dev);
+}
+else{
+printk("uart io select flag invaild\n");
+}
+
+uart_io_seletc = flag;
+
+
+
+return count;
+}
+
+DEVICE_ATTR(uart_io_select, S_IRUGO | S_IWUSR, uart_io_select_show,
+ uart_io_select_store);
+
+#define VEHICLE_USE_ONE_UART_LOG 1
+#if VEHICLE_USE_ONE_UART_LOG
+#define ICP_CORE_ID_PS CORE_PS0
+#define ICP_CORE_ID_CAP 1
+#define ICP_CHANNEL_CONSOLE_UART 7
+#define ICP_MSG_LEN_CONSOLE_UART 2
+#define ICP_BUFFERSIZE_CONSOLE_TOGGLE 16
+#define SYMB_PS_CORE_ID ICP_CORE_ID_PS
+#define SYMB_CAP_CORE_ID ICP_CORE_ID_CAP
+#define SYMB_WHAT_CORE_ID 3
+#define ENABLE_CURRENT_CONSOLE_UART 1
+#define DISABLE_CURRENT_CONSOLE_UART 0
+#define ENABLE_TOGGLE 1
+#define DISABLE_TOGGLE 0
+unsigned char g_core_id_occupy_uart = 0;
+unsigned char g_cap_uart_toggle = 0;
+static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id);
+static void restart_current_cons_uart(void)
+{
+ struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
+ struct uart_port *port = &zup->port;
+ enable_irq(port->irq);
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ spin_lock(&zup->port.lock);
+ tasklet_schedule(&zup->write_wakeup);
+ spin_unlock(&zup->port.lock);
+}
+static void forbid_current_cons_uart(void)
+{
+ struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
+ struct uart_port *port = &zup->port;
+ disable_irq(port->irq);
+ g_core_id_occupy_uart = SYMB_PS_CORE_ID;
+}
+static void process_ps2cap_rpmsg(char *arr)
+{
+ if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == ENABLE_CURRENT_CONSOLE_UART)){
+ restart_current_cons_uart();
+ }else if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == DISABLE_CURRENT_CONSOLE_UART)){
+ printk("current console uart not enable.\n");
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_PS_CORE_ID)){
+ g_core_id_occupy_uart = SYMB_PS_CORE_ID;
+ forbid_current_cons_uart();
+ }else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_CAP_CORE_ID)){
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }
+ else{
+ printk("%s error!!\n",__func__);
+ }
+}
+static void icp_callback_ps2cap(void *buf, unsigned int len)
+{
+ char *arr_ps2cap;
+ if (len==0){
+ printk("%s empty.\n", __func__);
+ return ;
+ }
+ arr_ps2cap = (char *)buf;
+ process_ps2cap_rpmsg(arr_ps2cap);
+}
+static void echo_to_change_other_uart(uint32_t val)
+{
+ int ret;
+ if(val > ENABLE_TOGGLE)
+ {
+ printk("echo para error!!!\n");
+ return;
+ }
+ char arr[2] = {0};
+ arr[0] = SYMB_PS_CORE_ID;
+ arr[1] = val;
+ T_RpMsg_Msg icp_msg;
+ icp_msg.coreID = CORE_PS0;
+ icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
+ icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
+ icp_msg.buf = arr;
+ icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
+ ret = rpmsgWrite(&icp_msg);
+ if(ret == 0){
+ if(val == ENABLE_TOGGLE)
+ g_core_id_occupy_uart = SYMB_PS_CORE_ID;
+ else if(val == DISABLE_TOGGLE)
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }else
+ printk("echo_to_change_ohter_uart fail.\n");
+}
+static ssize_t console_uart_toggle_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "\n console_uart_toggle_show %d. \n", g_cap_uart_toggle);
+}
+static ssize_t console_uart_toggle_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ flag = simple_strtoul(buf, NULL, 16);
+ if(flag == ENABLE_TOGGLE){
+ g_cap_uart_toggle = 1;
+ forbid_current_cons_uart();
+ echo_to_change_other_uart(flag);
+ }else if(flag == DISABLE_TOGGLE){
+ g_cap_uart_toggle = 0;
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }
+ return count;
+}
+DEVICE_ATTR(console_uart_toggle, S_IRUGO | S_IWUSR, console_uart_toggle_show,
+ console_uart_toggle_store);
+static void notify_occupy_uart_coreid_to_other(void)
+{
+ char arr[2] = {0};
+ arr[0] = SYMB_WHAT_CORE_ID;
+ arr[1] = g_core_id_occupy_uart;
+ T_RpMsg_Msg icp_msg;
+ icp_msg.coreID = CORE_AP;
+ icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
+ icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
+ icp_msg.buf = arr;
+ icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
+ rpmsgWrite(&icp_msg);
+}
+static ssize_t coreid_occupy_uart_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "\n core %d occupy cons uart now! \n",g_core_id_occupy_uart);
+}
+static ssize_t coreid_occupy_uart_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ flag = simple_strtoul(buf, NULL, 16);
+ g_core_id_occupy_uart = flag;
+ if(flag == SYMB_CAP_CORE_ID){
+ g_cap_uart_toggle = 0;
+ }else if(SYMB_PS_CORE_ID){
+ g_cap_uart_toggle = 1;
+ }
+ return count;
+}
+DEVICE_ATTR(coreid_occupy_uart, S_IRUGO | S_IWUSR, coreid_occupy_uart_show,
+ coreid_occupy_uart_store);
+#endif
+
+//extern int (*pm_callback_fn)(void);
+#ifdef CONFIG_CPU_IDLE
+typedef int (*pm_callback_fn)(void);
+extern int zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb);
+
+extern void disable_irq_nosync(unsigned int irq);
+extern void enable_irq(unsigned int irq);
+
+void uart_rxd_int_disable(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->rxd_int_depth++;
+}
+EXPORT_SYMBOL(uart_rxd_int_disable);
+
+int uart_0_pm_enter(void)
+{
+ struct zx29_uart_port *zup = &zx29_uart_ports[0];
+
+ //zDrvInt_UnmaskIrq(UART0_RXD_INT);
+ if(zup->irq_state == 0 || zup->imr== 0)
+ return 0;
+
+ //pcu_int_clear(PCU_UART0_RXD_INT);
+ if(!zup->rxd_int_depth){
+ //enable_irq(UART0_RXD_INT);
+ zup->rxd_int_depth++;
+ }
+ return 0;
+}
+
+int uart_0_pm_exit(void)
+{
+
+ return 0;
+}
+#endif
+/****************************************************************************/
+
+static int zx29_sgbuf_init(struct dma_chan *chan, struct zx29_sgbuf *sg,
+ enum dma_data_direction dir)
+{
+ dma_addr_t dma_addr;
+
+ sg->buf = dma_alloc_coherent(chan->device->dev,
+ ZX29_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
+ if (!sg->buf){
+ printk("zx29_sgbuf_init fail, no mem\n");
+ return -ENOMEM;
+ }
+ sg_init_table(&sg->sg, 1);
+ sg_set_page(&sg->sg, phys_to_page(dma_addr),
+ ZX29_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
+ sg_dma_address(&sg->sg) = dma_addr;
+ sg_dma_len(&sg->sg) = ZX29_DMA_BUFFER_SIZE;
+ sg->dma_addr = dma_addr;
+ return 0;
+}
+
+static void zx29_sgbuf_free(struct dma_chan *chan, struct zx29_sgbuf *sg,
+ enum dma_data_direction dir)
+{
+ if (sg->buf) {
+ dma_free_coherent(chan->device->dev,
+ ZX29_DMA_BUFFER_SIZE, sg->buf,
+ sg_dma_address(&sg->sg));
+ sg->dma_addr = NULL;
+ }
+}
+
+
+/****************************************************************************/
+static unsigned int zx29_uart_tx_empty(struct uart_port *port)
+{
+ return (UART_GET_FR(port)&(UART_FR_TXBUSY|UART_FR_TXFF)) ? 0 : TIOCSER_TEMT;
+}
+
+/****************************************************************************/
+static void zx29_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ unsigned int control = 0;
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->sigs = mctrl;
+ control = UART_GET_CR(&zup->port);
+ if(mctrl & TIOCM_DTR)
+ control |= UART_CR_DTR;
+ else
+ control &= ~ UART_CR_DTR;
+
+ if(mctrl & TIOCM_RTS)
+ control |= UART_CR_RTS;
+ else
+ control &= ~UART_CR_RTS;
+
+ if(mctrl & TIOCM_LOOP)
+ control |= UART_CR_LBE;
+ else
+ control &= ~UART_CR_LBE;
+
+ /* We need to disable auto-RTS if we want to turn RTS off */
+ if (zup->autorts) {
+ if (mctrl & TIOCM_RTS)
+ control |= UART_CR_RTSEN;
+ else
+ control &= ~UART_CR_RTSEN;
+ }
+ UART_PUT_CR(port, control);
+}
+
+/****************************************************************************/
+static unsigned int zx29_uart_get_mctrl(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned int mctrl = 0;
+ unsigned int uart_flag = 0;
+
+ uart_flag = UART_GET_FR(port);
+
+ mctrl = (uart_flag&UART_FR_CTS) ?TIOCM_CTS : 0;
+ mctrl |= (zup->sigs & TIOCM_RTS);
+ mctrl |= (uart_flag&UART_FR_DCD) ? TIOCM_CD : 0;
+ mctrl |= (uart_flag&UART_FR_DSR) ? TIOCM_DSR : 0;
+ mctrl |= (uart_flag&UART_FR_RI) ? TIOCM_RI : 0;
+
+ return mctrl;
+}
+
+/****************************************************************************/
+static void zx29_uart_start_tx(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned int control = 0;
+ unsigned int reg_bak[10] = {0};
+ struct circ_buf *xmit = &zup->port.state->xmit;
+ int count = 0;
+#if VEHICLE_USE_ONE_UART_LOG
+ if((port->line == DEBUG_CONSOLE))
+ {
+ if(g_core_id_occupy_uart == SYMB_PS_CORE_ID){
+ #if 1
+ count = uart_circ_chars_pending(xmit);
+ while(count-- > 0)
+ {
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ if (uart_circ_empty(xmit))
+ break;
+ }
+ #endif
+ return;
+ }
+ count = uart_circ_chars_pending(xmit);
+ while(count-- > 0)
+ {
+ zx29_uart_console_putc(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit)){
+ break;
+ }
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ {
+ spin_lock(&zup->port.lock);
+ tasklet_schedule(&zup->write_wakeup);
+ spin_unlock(&zup->port.lock);
+ return;
+ }
+ return;
+ }
+else
+#endif
+{
+ if(!(UART_GET_RIS(port)&UART_TXIS) && (UART_GET_FR(port) & UART_FR_TXFE))
+ {
+ if(!(UART_GET_RIS(port)&UART_TXIS))
+ {
+ count = uart_circ_chars_pending(xmit);
+ if(count >= zup->port.fifosize)
+ count = 15;//sent data more than TX ifls, TXIS will coming soon
+ if(count != 0){
+ do {
+ zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit) || (UART_GET_RIS(port)&UART_TXIS))
+ break;
+ } while (--count > 0);
+ }
+ }
+
+ }
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ if(!uart_console(port))
+ {
+ if (!zx29_dma_tx_start(zup))
+ {
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+ if(!(UART_GET_RIS(port)&UART_TXIS)){
+ if((UART_GET_FR(port) & UART_FR_TXFF))
+ return;
+ count = uart_circ_chars_pending(xmit);
+ while (count > 0) {
+ UART_PUT_CHAR(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit) || (UART_GET_RIS(port)&UART_TXIS) ||
+ (UART_GET_FR(port) & UART_FR_TXFF))
+ break;
+ }
+ }
+ }
+ }
+ else
+ {
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+ }
+#else
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+#endif
+}
+
+static void uart_write_wakeup_task(unsigned long _port)
+{
+ struct uart_port *port = (void *)_port;
+struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ struct platform_device *pdev=port->private_data;
+ //printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
+
+ if(zup->rxd_wakeup){
+ //rxd wake
+ printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
+ pm_wakeup_dev_event(&pdev->dev, 5000, false);
+ disable_irq(zup->rxd_irq);
+ zup->rxd_wakeup = false;
+ } else {
+ uart_write_wakeup(port);
+ }
+
+}
+
+#if CONFIG_SERIAL_ZX29_DMA
+#if UART_DEBUG_RECORDER_BYTE
+#define UART_DRIVER_DEBUG_COUNT (4*1024*1024)
+u32 cnt_uart_driver_debug = 0;
+u8 uart_driver_debug[UART_DRIVER_DEBUG_COUNT]={};
+void uart_debug(char *debug_buf, u32 count){
+ if(cnt_uart_driver_debug > (UART_DRIVER_DEBUG_COUNT-1)){
+ cnt_uart_driver_debug = 0;
+ }else{
+ memcpy(uart_driver_debug+cnt_uart_driver_debug,debug_buf,count);
+ cnt_uart_driver_debug = cnt_uart_driver_debug+count;
+ }
+}
+#endif
+int dma_complete_thread_use_dma_cyclic(void *ptr)
+{
+ unsigned long flags;
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)ptr;
+ size_t pending;
+ int dma_count = 0;
+ struct device *dev = NULL;
+ dev = zup->dmarx.chan->device->dev;
+ int uart_id = zup->port.line;
+ while(down_interruptible(&zup->sema_cyclic) == 0)
+ {
+ if(uart_dma_cycle[zup->port.line].cnt_callback > 0)
+ uart_id = zup->port.line;
+ else if(uart_dma_cycle[zup->port.line+3].cnt_callback > 0)
+ uart_id = zup->port.line + 3;
+
+ if(zup->port_close || !uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th].dma_addr)
+ break;
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ uart_dma_cycle[uart_id].cnt_th_total++;
+ uart_dma_cycle[uart_id].cnt_th++;
+ zup->sg2tty = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
+ zup->sg2tty_len = 4096;
+ pending = zup->sg2tty_len;
+ if(uart_dma_cycle[uart_id].flg_be || uart_dma_cycle[uart_id].flg_fe|| uart_dma_cycle[uart_id].flg_pe){
+ printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
+ zup->port.icount.brk,zup->port.icount.parity);
+ uart_dma_cycle[uart_id].flg_be = 0;
+ uart_dma_cycle[uart_id].flg_fe = 0;
+ uart_dma_cycle[uart_id].flg_pe = 0;
+ }
+ dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ zup->sg2tty->buf, pending);
+ test_uart_static(zup->port.line, zup->sg2tty->buf, uart_dma_cycle[zup->port.line].used, 27);
+#if UART_DEBUG_RECORDER_BYTE
+ uart_debug(zup->sg2tty->buf, pending);
+#endif
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock_irqsave(&zup->port.lock, flags);
+ dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ uart_dma_cycle[uart_id].flg_enter_th = (uart_dma_cycle[uart_id].flg_enter_th+1)%UART_DMA_CYCLE_RX_CONFIG_COUNT;
+ uart_dma_cycle[uart_id].cnt_callback--;
+ if(!hrtimer_active(&zup->rx_dma_hrtimer))
+ hrtimer_restart(&zup->rx_dma_hrtimer);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ }
+ return 0;
+}
+int dma_complete_thread(void *ptr)
+{
+ unsigned long flags;
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)ptr;
+
+ size_t pending;
+ struct dma_tx_state state;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ bool lastbuf;
+ int dma_count = 0;
+ struct zx29_sgbuf *sgbuf = NULL;
+ struct device *dev = NULL;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ dev = zup->dmarx.chan->device->dev;
+
+ while(down_interruptible(&zup->sema) == 0)
+ {
+ if(zup->port_close)
+ break;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ // tty = zup->port.state->port.tty;
+ if(!zup->sg2tty)
+ panic("dma_complete_thread, buffer 2 tty is invalid\n");
+ // dev = zup->dmarx.chan->device->dev;
+ pending = zup->sg2tty_len;
+ if(zx29_dma_rx_running(zup)){
+
+ test_uart_static(zup->port.line, NULL, 0, 10);
+ //uart_mod_timer(zup, &flags);
+ if(!hrtimer_active(&zup->rx_dma_hrtimer))
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ }
+ /* Pick everything from the DMA first */
+ if (pending) {
+ /* Sync in buffer */
+ dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+ //BUG();
+
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ zup->sg2tty->buf, pending);
+ test_uart_static(zup->port.line, zup->sg2tty->buf, pending, 11);
+ tty_flip_buffer_push(&zup->port.state->port);
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ /* Return buffer to device */
+ dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->port.icount.rx += dma_count;
+
+ //if(zup->port.line == 0)
+ //printk("yanming dma_complete_thread, dma2tty:%d\n", dma_count);
+ if (dma_count < pending){
+ sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d couldn't insert all characters \n",zup->port.line);
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+
+
+ }
+#if 0
+ zup->work_state = false;
+ zup->pre_pending = 0;
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+#endif
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ }
+
+ return 0;
+}
+#endif
+
+/****************************************************************************/
+static void zx29_uart_stop_tx(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->imr &= ~UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
+ if((port->line == DEBUG_CONSOLE) && uart_tx_stopped(port))
+ {
+ //uart_write_wakeup(port);
+ tasklet_schedule(&zup->write_wakeup);
+ }
+#endif
+
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_tx_stop(zup);
+#endif
+
+ zx_cpuidle_set_free(IDLE_FLAG_UART);
+
+}
+
+/****************************************************************************/
+void zx29_uart_stop_rx(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+
+ zup->imr &= ~(UART_RXIM|UART_RTIM|UART_FEIM|UART_PEIM|UART_BEIM|UART_OEIM);
+ UART_PUT_IMSC(port, zup->imr);
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_rx_stop(zup);
+#endif
+}
+
+/****************************************************************************/
+static void zx29_uart_break_ctl(struct uart_port *port, int break_state)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ unsigned int lcr_h;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ lcr_h = UART_GET_LCRH(port);
+ if (break_state == -1)
+ lcr_h |= UART_LCRH_BRK;
+ else
+ lcr_h &= ~UART_LCRH_BRK;
+ UART_PUT_LCRH(port, lcr_h);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+}
+
+/****************************************************************************/
+static void zx29_uart_enable_ms(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->imr |= UART_RIMIM|UART_CTSMIM|UART_DCDMIM|UART_DSRMIM;
+ UART_PUT_IMSC(port, zup->imr);
+}
+
+/****************************************************************************/
+/*--------------------------------------------------------------------
+ * Reads up to 256 characters from the FIFO or until it's empty and
+ * inserts them into the TTY layer. Returns the number of characters
+ * read from the FIFO.
+ --------------------------------------------------------------------*/
+static int zx29_uart_fifo_to_tty(struct zx29_uart_port *zup)
+{
+ struct uart_port *port = &zup->port;
+ u32 status, ch, i = 0;
+ unsigned int flag, max_count = 256;
+ int fifotaken = 0;
+ u8 uart_poll_char[16] ={0};
+
+ while (max_count--) {
+ status = UART_GET_FR(port);
+ if (status & UART_FR_RXFE)
+ break;
+
+ /* Take chars from the FIFO and update status */
+ ch = UART_GET_CHAR(port) | UART_DUMMY_DR_RX;
+
+#if 0
+ if(g_console_open_flag == 0 &&
+ port->line == DEBUG_CONSOLE){
+ if((ch&0xff) == 't'){
+ memset(uart_poll_char, 0, sizeof(uart_poll_char));
+ uart_poll_char[0] = 't';
+ i = 0;
+ printk("ch = %c i = %d\n",ch,i);
+ }else if ((ch&0xff) == 'y' && (i == 1)){
+ uart_poll_char[1] = 'y';
+ printk("ch = %c i = %d\n",ch,i);
+ }else if ((ch&0xff) == 'o' && (i == 2)){
+ uart_poll_char[2] = 'o';
+ printk("ch = %c i = %d\n",ch,i);
+ }else if ((ch&0xff) == 'p' && (i == 3)){
+ uart_poll_char[3] = 'p';
+ printk("ch = %c i = %d\n",ch,i);
+
+ }else if ((ch&0xff) == 'e' && (i == 4)){
+ uart_poll_char[4] = 'e';
+ printk("ch = %c i = %d\n",ch,i);
+
+ }else if ((ch&0xff) == 'n' && (i == 5)){
+ uart_poll_char[5] = 'n';
+ printk("ch = %c i = %d\n",ch,i);
+ g_console_open_flag = 1;
+ printk("ch = %c i = %d,g_console_open_flag:%d\n",ch,i,g_console_open_flag);
+ }else {
+ i = 10;
+ }
+ i++;
+ }
+#endif
+ flag = TTY_NORMAL;
+ if(zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
+ {
+ if(zup->port.icount.rx < UART_PORT_AUTOBAUD_BYTE)
+ {
+ uart_port_autobaud_buffer[zup->port.icount.rx] = ch;
+ }
+ else
+ {
+ uart_port_autobaud_gtflag = 1 ;
+ }
+ }
+ zup->port.icount.rx++;
+ if(zup->autobaud_state == UART_PORT_AUTOBAUD_OFF)
+ {
+ if(fifotaken < 16){
+ uart_poll_char[fifotaken] = ch & 0xFF;
+ }
+ fifotaken++;
+
+ if (unlikely(ch & UART_DR_ERROR)) {
+ if (ch & UART_DR_BE) {
+ ch &= ~(UART_DR_FE | UART_DR_PE);
+ zup->port.icount.brk++;
+ if (uart_handle_break(&zup->port))
+ continue;
+ } else if (ch & UART_DR_PE)
+ zup->port.icount.parity++;
+ else if (ch & UART_DR_FE)
+ zup->port.icount.frame++;
+ else if (ch & UART_DR_OE){
+ zup->port.icount.overrun++;
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ ch &= zup->port.read_status_mask;
+
+ if (ch & UART_DR_BE)
+ flag = TTY_BREAK;
+ else if (ch & UART_DR_PE)
+ flag = TTY_PARITY;
+ else if (ch & UART_DR_FE)
+ flag = TTY_FRAME;
+ }
+
+ if (uart_handle_sysrq_char(&zup->port, ch & 255))
+ continue;
+ if(g_console_open_flag || port->line != DEBUG_CONSOLE){
+ uart_insert_char(&zup->port, ch, UART_DR_OE, ch, flag);
+ }
+ }
+ }
+
+ test_uart_static(zup->port.line, uart_poll_char, fifotaken, 3);
+
+ return fifotaken;
+}
+
+/****************************************************************************/
+static void zx29_uart_rx_chars(struct zx29_uart_port *zup)
+{
+ unsigned long flags;
+
+ //struct tty_struct *tty = zup->port.state->port.tty;
+
+ zx29_uart_fifo_to_tty(zup);
+ spin_unlock(&zup->port.lock);
+
+ tty_flip_buffer_push(&zup->port.state->port);
+
+#if CONFIG_SERIAL_ZX29_DMA
+ if(!uart_console(&zup->port)){//console doesn't use dma rcv data
+ if (zx29_dma_rx_available(zup)) {
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ dev_dbg(zup->port.dev, "could not trigger RX DMA job "
+ "fall back to interrupt mode again\n");
+ zup->imr |= UART_RXIM;
+ } else{
+ zup->imr &= ~UART_RXIM;
+ }
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }
+ }
+#endif
+RX_END:
+ spin_lock(&zup->port.lock);
+
+}
+
+/****************************************************************************/
+static void zx29_uart_tx_chars(struct zx29_uart_port *zup)
+{
+ struct circ_buf *xmit = &zup->port.state->xmit;
+ unsigned long flags;
+ int count;
+
+ if (zup->port.x_char) {
+ UART_PUT_CHAR(&zup->port, zup->port.x_char);
+ zup->port.icount.tx++;
+ zup->port.x_char = 0;
+ return;
+ }
+ if (uart_circ_empty(xmit) || uart_tx_stopped(&zup->port)) {
+ zx29_uart_stop_tx(&zup->port);
+ return;
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ /* If we are using DMA mode, try to send some characters. */
+ if(!uart_console(&(zup->port)))
+ {
+ if (zx29_dma_tx_irq(zup))
+ return;
+ }
+#endif
+ count = zup->port.fifosize >> 1;
+ do {
+ zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+ } while (--count > 0);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ {
+ spin_unlock(&zup->port.lock);
+ //uart_write_wakeup(&zup->port);
+ tasklet_schedule(&zup->write_wakeup);
+ spin_lock(&zup->port.lock);
+ }
+
+ if (uart_circ_empty(xmit))
+ zx29_uart_stop_tx(&zup->port);
+}
+
+#if CONFIG_SERIAL_ZX29_DMA
+
+dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup)
+{
+ struct uart_port *port = &zup->port;
+ if(port->line < UART0 || port->line > UART4){
+ printk("get_rx_dma_peripheral_id,fail, invalid port->line:%d\n", port->line);
+ }
+ if(port->line == UART0){
+ return DMA_CH_UART0_RX;
+ } else if(port->line == UART1){
+ return DMA_CH_UART1_RX;
+ }else if(port->line == UART2){
+ return DMA_CH_UART2_RX;
+ }
+// else if(port->line == UART3){
+// return DMA_CH_UART3_RX;
+// }else if(port->line == UART4){
+// return DMA_CH_UART4_RX;
+// }
+
+ return DMA_CH_NUM;
+}
+
+/*
+ * We received a transmit interrupt without a pending X-char but with
+ * pending characters.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * false if we want to use PIO to transmit
+ * true if we queued a DMA buffer
+ */
+static bool zx29_dma_tx_irq(struct zx29_uart_port *zup)
+{
+ if (!zup->using_tx_dma)
+ return false;
+
+ /*
+ * If we already have a TX buffer queued, but received a
+ * TX interrupt, it will be because we've just sent an X-char.
+ * Ensure the TX DMA is enabled and the TX IRQ is disabled.
+ */
+ if (zup->dmatx.queued) {
+ zup->dmacr |= UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ zup->imr &= ~UART_TXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ return true;
+ }
+
+ /*
+ * We don't have a TX buffer queued, so try to queue one.
+ * If we successfully queued a buffer, mask the TX IRQ.
+ */
+ if (zx29_uart_dma_tx_chars(zup) > 0) {
+ zup->imr &= ~UART_TXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ return true;
+ }
+ return false;
+}
+
+
+/*
+ * Stop the DMA transmit (eg, due to received XOFF).
+ * Locking: called with port lock held and IRQs disabled.
+ */
+static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup)
+{
+ if (zup->dmatx.queued) {
+ zup->dmacr &= ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ }
+}
+
+
+/*
+ * Try to start a DMA transmit, or in the case of an XON/OFF
+ * character queued for send, try to get that character out ASAP.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * false if we want the TX IRQ to be enabled
+ * true if we have a buffer queued
+ */
+static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup)
+{
+ u16 dmacr;
+
+ if (!zup->using_tx_dma)
+ return false;
+
+ if (!zup->port.x_char) {
+ /* no X-char, try to push chars out in DMA mode */
+ bool ret = true;
+
+ if (!zup->dmatx.queued) {
+ if (zx29_uart_dma_tx_chars(zup) > 0) {
+ zup->imr &= ~UART_TXIM;
+ ret = true;
+ } else {
+ zup->imr |= UART_TXIM;
+ ret = false;
+ }
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ } else if (!(zup->dmacr & UART_TXDMAE)) {
+ zup->dmacr |= UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ }
+ return ret;
+ }
+
+ /*
+ * We have an X-char to send. Disable DMA to prevent it loading
+ * the TX fifo, and then see if we can stuff it into the FIFO.
+ */
+ dmacr = zup->dmacr;
+ zup->dmacr &= ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+
+ if (UART_GET_FR(&zup->port) & UART_FR_TXFF) {
+ /*
+ * No space in the FIFO, so enable the transmit interrupt
+ * so we know when there is space. Note that once we've
+ * loaded the character, we should just re-enable DMA.
+ */
+ return false;
+ }
+
+ UART_PUT_CHAR(&zup->port, zup->port.x_char);
+ //writew(uap->port.x_char, uap->port.membase + UART01x_DR);
+ zup->port.icount.tx++;
+ zup->port.x_char = 0;
+
+ /* Success - restore the DMA state */
+ zup->dmacr = dmacr;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ //writew(dmacr, uap->port.membase + UART011_DMACR);
+
+ return true;
+}
+
+/****************************************************************************/
+
+//#if CONFIG_SERIAL_ZX29_DMA
+/*
+ * Flush the transmit buffer.
+ * Locking: called with port lock held and IRQs disabled.
+ */
+static void zx29_dma_flush_buffer(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)port;
+ if (!zup->using_tx_dma)
+ return;
+
+ /* Avoid deadlock with the DMA engine callback */
+ //dmaengine_terminate_all(zup->dmatx.chan);
+ if (zup->dmatx.queued) {
+
+ //printk(KERN_INFO "zx29_dma_flush_buffer enter[%s][%d] Port[%d]\n",__func__,__LINE__,port->line);
+ dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
+ DMA_TO_DEVICE);
+ zup->dmatx.queued = false;
+ zup->dmacr &= ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ }
+}
+
+static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup)
+{
+ struct dma_chan *rxchan = zup->dmarx.chan;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_async_tx_descriptor *desc;
+ struct zx29_sgbuf *sgbuf;
+
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ if (!rxchan)
+ {
+ printk("[%s][%d]\n",__func__,__LINE__);
+ return -EIO;
+ }
+
+ /* Start the RX DMA job */
+
+ sgbuf = zup->dmarx.use_buf_b ?
+ &zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
+ /*
+
+ sgbuf = zup->dmarx.use_buf_b ?
+ &zup->dmarx.sgbuf_a : &zup->dmarx.sgbuf_b;
+ */
+ zup->dmarx.rx_def[zup->dmarx.rx_index].link_addr=0;
+ zup->dmarx.rx_def[zup->dmarx.rx_index].dest_addr=(unsigned int)(sgbuf->dma_addr);
+ zup->dmarx.rx_def[zup->dmarx.rx_index].count=ZX29_DMA_BUFFER_SIZE;//fifo or max buffer?
+ wmb();
+
+ dmaengine_slave_config(rxchan, (struct dma_slave_config*)&zup->dmarx.rx_def[zup->dmarx.rx_index]);
+ desc = rxchan->device->device_prep_interleaved_dma(rxchan,NULL,0);
+
+
+ /*
+ * If the DMA engine is busy and cannot prepare a
+ * channel, no big deal, the driver will fall back
+ * to interrupt mode as a result of this error code.
+ */
+ if (!desc) {
+ printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
+ sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d ERROR DESC \n",zup->port.line);
+ zup->dmarx.running = false;
+ dmaengine_terminate_all(rxchan);
+ //zx29_dma_force_stop(rx_id);
+ return -EBUSY;
+ }
+
+ /* Some data to go along to the callback */
+ desc->callback = uart_dma_rx_callback;
+ desc->callback_param = zup;
+ zup->curr_sg = sgbuf;
+ wmb();
+
+ dmarx->cookie = dmaengine_submit(desc);
+ dma_async_issue_pending(rxchan);
+ atomic_inc(&zup->dmarx.count);
+ zup->dmarx.rx_index = (zup->dmarx.rx_index +1)%UART_DMA_RX_MAX_COUNT;
+ zup->dmacr |= UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ zup->dmarx.running = true;
+ zup->dmarx.used = true;
+ zup->imr &= ~(UART_RXIM | UART_RTIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+
+
+ return 0;
+}
+static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup)
+{
+ struct dma_chan *rxchan = zup->dmarx.chan;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_async_tx_descriptor *desc;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ int uart_id = zup->port.line;
+ if (!rxchan)
+ {
+ printk("[%s][%d]\n",__func__,__LINE__);
+ return -EIO;
+ }
+
+ if(uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+
+ dmaengine_slave_config(rxchan, (struct dma_slave_config*)&uart_dma_cycle[uart_id].rxdef);
+ desc = rxchan->device->device_prep_dma_cyclic(rxchan,NULL,(ZX29_DMA_BUFFER_SIZE *5) , ZX29_DMA_BUFFER_SIZE,0,0);
+ if (!desc) {
+ printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
+ zup->dmarx.running = false;
+ dmaengine_terminate_all(rxchan);
+ return -EBUSY;
+ }
+ desc->callback = uart_dma_rx_callback_use_dma_cyclic;
+ desc->callback_param = zup;
+ wmb();
+ dmarx->cookie = dmaengine_submit(desc);
+ dma_async_issue_pending(rxchan);
+ zup->dmacr |= UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ uart_dma_cycle[uart_id].flg_enter_th = 0;
+ if(uart_dma_cycle[zup->port.line].used){
+ uart_dma_cycle[zup->port.line].used = false;
+ uart_dma_cycle[zup->port.line+3].used = true;
+ }else{
+ uart_dma_cycle[zup->port.line].used = true;
+ uart_dma_cycle[zup->port.line+3].used = false;
+ }
+
+ zup->dmarx.running = true;
+ zup->dmarx.used = true;
+ zup->imr &= ~(UART_RXIM | UART_RTIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ return 0;
+}
+
+void uart_dma_rx_callback(void *data)
+{
+ unsigned long flags;
+
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)data;
+ int uart_id = zup->port.line;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ struct device *dev = NULL;
+// struct dma_tx_state state;
+ unsigned int ris_status;
+
+ bool lastbuf;
+ int dma_count = 0;
+ struct zx29_sgbuf *sgbuf = zup->curr_sg;
+ size_t pending;
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 4;
+ test_uart_static(zup->port.line, NULL, 0, 20);
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ zx29_dma_stop(rx_id);
+
+ dev = zup->dmarx.chan->device->dev;
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+
+ //spin_lock_irqsave(&zup->port.lock, flags);
+ zup->sg2tty = sgbuf;
+// rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ zup->sg2tty_len = zup->sg2tty->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //zx29_dma_force_stop(rx_id);
+ // dmaengine_terminate_all(rxchan);
+ dmarx->use_buf_b = ! dmarx->use_buf_b;
+ wmb();
+ //BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
+ /* Then we terminate the transfer - we now know our residue */
+ //dmaengine_terminate_all(rxchan);
+
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ test_uart_static(zup->port.line, NULL, 0, 9);
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+
+ up(&zup->sema);
+}
+
+void uart_dma_rx_callback_use_dma_cyclic(void *data)
+{
+ unsigned long flags;
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)data;
+ unsigned int ris_status;
+ int uart_id = zup->port.line;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ if(!uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+ uart_dma_cycle[uart_id].cnt_callback_total++;
+ uart_dma_cycle[uart_id].cnt_callback++;
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ uart_dma_cycle[uart_id].flg_overrun = 1;
+ }
+ if(ris_status & UART_BEIS){
+ uart_dma_cycle[uart_id].flg_be = 1;
+ zup->port.icount.brk++;
+ }
+ if(ris_status & UART_PEIS){
+ uart_dma_cycle[uart_id].flg_pe = 1;
+ zup->port.icount.parity++;
+ }
+ if(ris_status & UART_FEIS){
+ uart_dma_cycle[uart_id].flg_fe = 1;
+ zup->port.icount.frame++;
+ }
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 26);
+ up(&zup->sema_cyclic);
+}
+static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup)
+{
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ //zx29_dma_force_stop(rx_id);
+ //dmaengine_terminate_all(zup->dmarx.chan);
+ /* FIXME. Just disable the DMA enable */
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+#if 0
+ //do we need check data received?
+ if(zup->pre_pending){
+ printk("pre_pending :%d\n ", zup->pre_pending);
+ }
+#endif
+ zup->curr_sg = NULL;
+}
+
+static void zx29_dma_remove(struct zx29_uart_port *zup)
+{
+ /* TODO: remove the initcall if it has not yet executed */
+ if (zup->dmatx.chan)
+ dma_release_channel(zup->dmatx.chan);
+ if (zup->dmarx.chan)
+ dma_release_channel(zup->dmarx.chan);
+}
+
+
+static void zx29_dma_shutdown(struct zx29_uart_port *zup)
+{
+ unsigned long flags;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+
+ if (!(zup->using_tx_dma || zup->using_rx_dma))
+ return;
+ /* Disable RX and TX DMA */
+ while(UART_GET_FR(&zup->port) & (UART_FR_TXBUSY | UART_FR_TXBUSY))
+ barrier();
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ //zx29_dma_force_stop(rx_id);
+ // dmaengine_terminate_all(zup->dmarx.chan);
+ zup->dmacr &= ~(UART_DMAONERR | UART_RXDMAE | UART_TXDMAE);
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->curr_sg = NULL;
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ if (zup->using_tx_dma) {
+ /* In theory, this should already be done by zx29_dma_flush_buffer */
+ dmaengine_terminate_all(zup->dmatx.chan);
+ if (zup->dmatx.queued) {
+ dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
+ DMA_TO_DEVICE);
+ zup->dmatx.queued = false;
+ }
+ if(!zup->dmatx.buf)
+ kfree(zup->dmatx.buf);
+ zup->dmatx.buf = NULL;
+ zup->using_tx_dma = false;
+ }
+ if (zup->using_rx_dma) {
+ //dmaengine_terminate_all(zup->dmarx.chan);
+ /* Clean up the RX DMA */
+ if(!zup->uart_power_mode){
+ zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a, DMA_FROM_DEVICE);
+ zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_b, DMA_FROM_DEVICE);
+ }else if(zup->uart_power_mode == 1){
+ uart_dma_cycle_deinit(zup);
+ }else
+ printk("uart%d dma shutdown fail.\n",zup->port.line);
+ zup->using_rx_dma = false;
+ zup->dmarx.used = false;
+ zup->dmarx.running = false;
+ zup->dmarx.use_buf_b = false;
+ zup->dmarx.rx_index = 0;
+ }
+ zup->pre_pending = 0;
+ zup->work_state = false;
+
+}
+
+static void zx29_shutdown_channel(struct zx29_uart_port *zup,
+ unsigned int lcrh)
+{
+ unsigned long val;
+
+ val = UART_GET_LCRH(&zup->port);
+ val &= ~(UART_LCRH_BRK | UART_LCRH_FEN);
+ UART_PUT_LCRH(&zup->port, val);
+}
+
+
+static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma;
+}
+
+static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma && zup->dmarx.running;
+}
+
+static inline bool zx29_dma_rx_used(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma && zup->dmarx.used;
+}
+
+static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma && zup->work_state;
+}
+
+
+void uart_dma_tx_callback(void *data)
+{
+ struct zx29_uart_port *zup = data;
+ struct zx29_dmatx_data *dmatx = &zup->dmatx;
+
+ unsigned long flags;
+ u16 dmacr;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ if (zup->dmatx.queued)
+ dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
+ DMA_TO_DEVICE);
+
+ dmacr = zup->dmacr;
+ zup->dmacr = dmacr & ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+
+ /*
+ * If TX DMA was disabled, it means that we've stopped the DMA for
+ * some reason (eg, XOFF received, or we want to send an X-char.)
+ *
+ * Note: we need to be careful here of a potential race between DMA
+ * and the rest of the driver - if the driver disables TX DMA while
+ * a TX buffer completing, we must update the tx queued status to
+ * get further refills (hence we check dmacr).
+ */
+ if (!(dmacr & UART_TXDMAE) || uart_tx_stopped(&zup->port) ||
+ uart_circ_empty(&zup->port.state->xmit)) {
+ zup->dmatx.queued = false;
+
+
+ zx_cpuidle_set_free(IDLE_FLAG_UART);
+
+
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ return;
+ }
+
+ if (zx29_uart_dma_tx_chars(zup) <= 0) {
+ /*
+ * We didn't queue a DMA buffer for some reason, but we
+ * have data pending to be sent. Re-enable the TX IRQ.
+ */
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+}
+
+static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup)
+{
+ struct zx29_dmatx_data *dmatx = &zup->dmatx;
+ struct dma_chan *tx_chan = dmatx->chan;
+ struct dma_device *dma_dev = tx_chan->device;
+ struct dma_async_tx_descriptor *desc;
+ struct circ_buf *xmit = &zup->port.state->xmit;
+ unsigned int count;
+
+ /*
+ * Try to avoid the overhead involved in using DMA if the
+ * transaction fits in the first half of the FIFO, by using
+ * the standard interrupt handling. This ensures that we
+ * issue a uart_write_wakeup() at the appropriate time.
+ */
+
+ count = uart_circ_chars_pending(xmit);
+ if (count < (16 >> 1)) {
+ zup->dmatx.queued = false;
+ return 0;
+ }
+
+ if (xmit->tail < xmit->head)
+ memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
+ else {
+ size_t first = UART_XMIT_SIZE - xmit->tail;
+ size_t second ;//= xmit->head;
+
+ if (first > count)
+ first = count;
+ second = count - first;
+ memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
+ if (second)
+ memcpy(&dmatx->buf[first], &xmit->buf[0], second);
+ }
+ dmatx->sg.length = count;
+
+ if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
+ zup->dmatx.queued = false;
+ dev_dbg(zup->port.dev, "unable to map TX DMA\n");
+ return -EBUSY;
+ }
+
+
+ zup->dmatx.tx_def.link_addr=0;
+ zup->dmatx.tx_def.src_addr=(unsigned int)(dmatx->sg.dma_address);
+ zup->dmatx.tx_def.count=count;
+ wmb();
+ dmaengine_slave_config(tx_chan, (struct dma_slave_config*)&zup->dmatx.tx_def);
+ desc = tx_chan->device->device_prep_interleaved_dma(tx_chan,NULL,0);
+
+ if (!desc) {
+ printk(KERN_INFO "!!!!!ERROR TX DESC[%s][%d]\n",__func__,__LINE__);
+ dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
+ zup->dmatx.queued = false;
+ /*
+ * If DMA cannot be used right now, we complete this
+ * transaction via IRQ and let the TTY layer retry.
+ */
+ dev_dbg(zup->port.dev, "TX DMA busy\n");
+ return -EBUSY;
+ }
+ desc->callback = (dma_async_tx_callback)uart_dma_tx_callback;
+ desc->callback_param = (void *)zup;
+ dmaengine_submit(desc);
+ dma_async_issue_pending(tx_chan);
+ atomic_inc(&zup->dmatx.count);
+ zup->dmacr |= UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zup->dmatx.queued = true;
+
+ /*
+ * Now we know that DMA will fire, so advance the ring buffer
+ * with the stuff we just dispatched.
+ */
+ xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx += count;
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ //uart_write_wakeup(&zup->port);
+ tasklet_schedule(&zup->write_wakeup);
+
+ return 1;
+}
+
+static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
+ //u32 pending, bool use_buf_b,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ bool readfifo, unsigned long *flags)
+{
+ struct tty_struct *tty = zup->port.state->port.tty;
+#if 0
+ struct zx29_sgbuf *sgbuf = use_buf_b ?
+ &zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
+#endif
+ struct device *dev = zup->dmarx.chan->device->dev;
+ int dma_count = 0;
+ u32 fifotaken = 0; /* only used for vdbg() */
+ //unsigned long flags;
+
+ /* Pick everything from the DMA first */
+ if (pending) {
+ /* Sync in buffer */
+
+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+
+ /*
+ * First take all chars in the DMA pipe, then look in the FIFO.
+ * Note that tty_insert_flip_buf() tries to take as many chars
+ * as it can.
+ */
+
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ sgbuf->buf, pending);
+
+ test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ /* Return buffer to device */
+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+
+ /*
+ * Only continue with trying to read the FIFO if all DMA chars have
+ * been taken first.
+ */
+ //if (dma_count == pending && readfifo) {
+ if (readfifo) {
+ /* Clear any error flags */
+ //UART_PUT_ICR(&zup->port,UART_OEIC | UART_BEIC | UART_PEIC | UART_FEIC);
+ /*
+ * If we read all the DMA'd characters, and we had an
+ * incomplete buffer, that could be due to an rx error, or
+ * maybe we just timed out. Read any pending chars and check
+ * the error status.
+ *
+ * Error conditions will only occur in the FIFO, these will
+ * trigger an immediate interrupt and stop the DMA job, so we
+ * will always find the error in the FIFO, never in the DMA
+ * buffer.
+ */
+ test_uart_static(zup->port.line, NULL, 0, 7);
+ fifotaken = zx29_uart_fifo_to_tty(zup);
+ }
+ if((pending > 0) || (fifotaken > 0)) {
+ spin_unlock(&zup->port.lock);
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock(&zup->port.lock);
+ }
+}
+static void zx29_uart_deal_dma_fifo_rx_chars_cyclic(struct zx29_uart_port *zup,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ unsigned long *flags, char *fifo_buf, int fifo_len)
+{
+ struct tty_struct *tty = zup->port.state->port.tty;
+ struct device *dev = zup->dmarx.chan->device->dev;
+ int dma_count = 0;
+ int fifo_count = 0;
+ u32 fifotaken = 0; /* only used for vdbg() */
+ if ((pending) && (pending != 4096)) {
+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ sgbuf->buf, pending);
+ test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
+#if UART_DEBUG_RECORDER_BYTE
+ uart_debug(sgbuf->buf, pending);
+#endif
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+ if(fifo_len){
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ fifo_count = tty_insert_flip_string(&zup->port.state->port,
+ fifo_buf, fifo_len);
+ test_uart_static(zup->port.line, fifo_buf, fifo_len, 50);
+#if UART_DEBUG_RECORDER_BYTE
+ uart_debug(fifo_buf, fifo_len);
+#endif
+ fifo_buf[0] = '\0';
+ fifo_buf[1] = '\0';
+ fifo_buf[2] = '\0';
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ }
+ zup->port.icount.rx += fifo_count;
+ if(((pending) && (pending != 4096)) || (fifo_len > 0)){
+ spin_unlock(&zup->port.lock);
+ tty_flip_buffer_push(&zup->port.state->port);
+ test_uart_static(zup->port.line, NULL, (fifo_count+dma_count), 51);
+ spin_lock(&zup->port.lock);
+ }
+}
+
+static void zx29_uart_deal_dma_fifo_rx_chars(struct zx29_uart_port *zup,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ unsigned long *flags, char *fifo_buf, int fifo_len)
+{
+ struct tty_struct *tty = zup->port.state->port.tty;
+
+ struct device *dev = zup->dmarx.chan->device->dev;
+ int dma_count = 0;
+ int fifo_count = 0;
+ u32 fifotaken = 0; /* only used for vdbg() */
+ if (pending) {
+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ sgbuf->buf, pending);
+ test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+
+ if(fifo_len){
+ //printk("qq >> fifo len %d.\n",fifo_len);
+ fifo_count = tty_insert_flip_string(&zup->port.state->port,
+ fifo_buf, fifo_len);
+ //printk("qq >>fifo count %d,buf is %x %x %x .\n",fifo_count, fifo_buf[0],fifo_buf[1],fifo_buf[2]);
+ fifo_buf[0] = '\0';
+ fifo_buf[1] = '\0';
+ fifo_buf[2] = '\0';
+ //memset(fifo_buf, '\0', 4);
+ }
+
+ zup->port.icount.rx += fifo_count;
+ test_uart_static(zup->port.line, fifo_buf, fifo_count, 18);
+ if(pending > 0 || (fifo_len > 0)){
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ }
+}
+
+#if 0
+static void zx29_dma_rx_irq(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ struct zx29_sgbuf *sgbuf = dmarx->use_buf_b ?
+ &dmarx->sgbuf_b : &dmarx->sgbuf_a;
+ size_t pending;
+ struct dma_tx_state state;
+ enum dma_status dmastat;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+
+ uint32_t ris_status = UART_GET_RIS(&zup->port);
+ //printk("rx irq\n");
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+
+ if(zx29_dma_rx_running(zup)){
+ /*
+ * Pause the transfer so we can trust the current counter,
+ * do this before we pause the block, else we may
+ * overflow the FIFO.
+ */
+ // if(zx29_dma_stop(rx_id))
+ // printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ //zx29_dma_force_stop(rx_id);
+ //dmaengine_terminate_all(rxchan);
+
+ //dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
+
+ /* Disable RX DMA - incoming data will wait in the FIFO */
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
+ BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
+ /* Then we terminate the transfer - we now know our residue */
+ //dmaengine_terminate_all(rxchan);
+
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ /*
+ * This will take the chars we have so far and insert
+ * into the framework.
+ */
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, false, flags);
+ }
+
+ /* Switch buffer & re-trigger DMA job */
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("uart%d could not retrigger RX DMA job\n",zup->port.line);
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ }
+#if RX_DMA_WORK
+ //printk("add timer\n");
+ else{
+ // mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
+ uart_mod_timer(zup, flags);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+#endif
+
+}
+#endif
+/****************************************************************************/
+static void zx29_uart_rx_dma_chars(struct zx29_uart_port *zup, unsigned long *flags)
+{
+
+ struct tty_struct *tty = zup->port.state->port.tty;
+ //zx29_uart_fifo_to_tty(zup);
+// spin_unlock(&zup->port.lock);
+ if (zx29_dma_rx_available(zup)) {
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM | UART_RTIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }
+#if RX_DMA_WORK
+//printk("add timer\n");
+ else{
+ //mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
+ uart_mod_timer(zup, flags);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+#endif
+ }
+
+ //tty_flip_buffer_push(tty);
+ //spin_lock(&zup->port.lock);
+}
+
+
+/****************************************************************************/
+static void zx29_uart_rx_timeout_chars(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ int rt_cnt = 0;
+// unsigned long flags;
+
+ int fr = UART_GET_FR(&zup->port);
+ //printk("rx_timeout_chars\n");
+
+ rt_cnt = zx29_uart_fifo_to_tty(zup);
+ if(rt_cnt){
+ if(g_console_open_flag == 1 || zup->port.line != DEBUG_CONSOLE){
+ spin_unlock(&zup->port.lock);
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock(&zup->port.lock);
+ }
+ }
+}
+
+static void zx29_uart_rt_dma(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ struct zx29_sgbuf *sgbuf = zup->curr_sg;
+ size_t pending;
+ struct dma_tx_state state;
+ enum dma_status dmastat;
+
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ uint32_t ris_status = UART_GET_RIS(&zup->port);
+
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //printk("---zx29_uart_rt_dma, pending:%d, residue:%d\n", pending, state.residue);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ // if(!uart_console(&zup->port))
+ //BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+
+ if(zx29_dma_rx_running(zup)){
+ /*
+ * Pause the transfer so we can trust the current counter,
+ * do this before we pause the block, else we may
+ * overflow the FIFO.
+ */
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ //printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
+ //dmastat = rxchan->device->device_tx_status(rxchan,
+ // dmarx->cookie, &state);
+ // dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
+
+ //zx29_dma_force_stop(rx_id);
+ //dmaengine_terminate_all(rxchan);
+
+ /* Disable RX DMA - incoming data will wait in the FIFO */
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ zup->curr_sg = zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
+
+ //printk("---zx29_uart_rt_dma, after stop pending:%d, residue:%d\n", pending, state.residue);
+ BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
+ /* Then we terminate the transfer - we now know our residue */
+ //dmaengine_terminate_all(rxchan);
+
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ wmb();
+ /*
+ * This will take the chars we have so far and insert
+ * into the framework.
+ */
+ test_uart_static(zup->port.line, NULL, 0, 5);
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, flags);
+ }
+
+#if 0
+//printk("rt dma\n");
+ /* Switch buffer & re-trigger DMA job */
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("zx29_dma_rx_trigger_dma fail,uart:%d\n", zup->port.line);
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ }
+#if RX_DMA_WORK
+ //printk("add timer\n");
+ else{
+ //mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
+ uart_mod_timer(zup, flags);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ zup->dmarx.used = true;
+ }
+#endif
+
+#endif
+
+}
+char g_fifo_residue_buf[5][4];
+char g_fifo_residue_all[5][20];
+unsigned char g_fifo_cnt[5];
+static void zx29_uart_rx_dma_timeout(struct timer_list *t)
+{
+ struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_timer);
+
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ static bool dma_timeout_flag = false;
+ size_t pending, tmp_len;
+ uint32_t ris_status = 0;
+ int cancel_timer = 0;
+ int sg_idx = (dmarx->use_buf_b ? 1 : 0);
+
+ unsigned long flags;
+ struct zx29_sgbuf *sgbuf = NULL;
+ int uart_id = zup->port.line;
+ if(!zx29_dma_rx_running(zup))
+ //printk("---uart_rx_dma_timeout enter, dma stopped\n");
+ return;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ if(zup->port_close || (zup->curr_sg == NULL)){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return;
+ }
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ if(zup->sg2tty) {//dma complete now, later check again
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 14);
+ mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ return;
+ }
+ sgbuf = zup->curr_sg;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //printk("---uart_rx_dma_timeout enter,sg.length:%d, pending:%d, state.residue:%d\n", sgbuf->sg.length, pending, state.residue);
+ if(pending == zup->pre_pending){
+ int fr = UART_GET_FR(&zup->port);
+ //if RXBUSY,means data come again
+
+ if((fr & UART_FR_RXBUSY)){
+
+ uart_mod_timer(zup, &flags);
+ test_uart_static(zup->port.line, NULL, 0, 12);
+ goto deal_end;
+
+ }
+
+ ris_status = UART_GET_RIS(&zup->port);
+
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 1;
+ test_uart_static(zup->port.line, NULL, 0, 19);
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(tmp_len != pending){
+ pending = tmp_len;
+ }
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ wmb();
+ if(zup->uart_power_mode){
+ int i;
+ for(i= 0;i < 3;i++){
+ fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXFE) == 0){
+ g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+ else
+ break;
+ }
+ if(i){
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+
+ //zup->sg2tty = sgbuf;
+ //when app ctrl sleep ,always start dma receive
+ if(zup->sleep_state == 0){
+ //now start dma again
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ uart_mod_timer(zup, &flags);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ }
+ if(pending || (i > 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
+ }
+
+ }else{
+ //for normal mode, dma start only on rx busy after timeout came
+ if(pending || (( fr & UART_FR_RXFE) == 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
+ }
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ zup->pre_pending = 0;
+ zup->work_state = false;
+ if((UART_GET_RIS(&zup->port) & (UART_RXIS | UART_RTIS)) ||
+ (UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
+ zup->imr &= ~(UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ uart_mod_timer(zup, &flags);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
+ }
+ }
+
+ }
+deal_end:
+
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ }else{
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ zup->pre_pending = pending;
+ mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ //uart_mod_timer(zup, &flags);
+ }
+
+
+}
+enum hrtimer_restart zx29_uart_rx_dma_hrtimeout(struct hrtimer *t)
+{
+ struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ static bool dma_timeout_flag = false;
+ size_t pending, tmp_len;
+ uint32_t ris_status = 0;
+ int cancel_timer = 0;
+ int sg_idx = (dmarx->use_buf_b ? 1 : 0);
+ int uart_id = zup->port.line;
+ unsigned long flags;
+ struct zx29_sgbuf *sgbuf = NULL;
+ if(!zx29_dma_rx_running(zup))
+ return HRTIMER_NORESTART;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ if(zup->port_close || (zup->curr_sg == NULL)){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_NORESTART;
+ }
+ if(zup->sg2tty) {//dma complete now, later check again
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 14);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ if(zup->enter_suspend){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 15);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ sgbuf = zup->curr_sg;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if((pending == zup->pre_pending)) {
+ int fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXBUSY)){
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, 0, 12);
+ goto deal_end;
+ }
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 1;
+ test_uart_static(zup->port.line, NULL, 0, 19);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(tmp_len != pending){
+ pending = tmp_len;
+ }
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ wmb();
+ if(zup->uart_power_mode){
+ int i;
+ for(i= 0;i < 3;i++){
+ fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXFE) == 0){
+ g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+ else
+ break;
+ }
+ if(i){
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+ if(zup->sleep_state == 0){
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ }
+ if(pending || (i > 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
+ }
+ }else{
+ if(pending || (( fr & UART_FR_RXFE) == 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
+ printk("at pending %d.\n",pending);
+ }
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ zup->pre_pending = 0;
+ zup->work_state = false;
+ if((UART_GET_RIS(&zup->port) & (UART_RXIS | UART_RTIS)) ||
+ (UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
+ zup->imr &= ~(UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
+ }
+ }
+ }
+deal_end:
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_RESTART;
+ }else{
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ zup->pre_pending = pending;
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
+ return HRTIMER_RESTART;
+ }
+}
+enum hrtimer_restart zx29_uart_rx_dma_hrtimeout_cyclic(struct hrtimer *t)
+{
+ struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ size_t pending, tmp_len;
+ uint32_t ris_status = 0;
+ unsigned long flags;
+ struct zx29_sgbuf *sgbuf = NULL;
+ int uart_id = zup->port.line;
+
+
+ if(!zx29_dma_rx_running(zup))
+ return HRTIMER_NORESTART;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+
+ if((uart_dma_cycle[zup->port.line].cnt_callback > 0) || (uart_dma_cycle[zup->port.line+3].cnt_callback > 0)){
+ test_uart_static(zup->port.line, NULL, uart_dma_cycle[zup->port.line].used, 46);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_NORESTART;
+ }
+
+ if(!uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+
+ sgbuf = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
+ if(zup->port_close || (sgbuf == NULL)){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_NORESTART;
+ }
+ if(zup->sema_cyclic.count > 0){
+ printk("uart has th not deal.\n");
+ //test_uart_static(zup->port.line, NULL, uart_id, 11);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+
+ if((zup->sg2tty)){//dma not complete now, later check again
+ printk("dmath_cyclic not end.\n");
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 14);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ if(zup->enter_suspend || uart_dma_cycle[uart_id].enter_throttle){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 15);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(((pending == zup->pre_pending) && pending) || uart_dma_cycle[uart_id].from_resume
+ || uart_dma_cycle[uart_id].from_unthrottle){
+ uart_dma_cycle[uart_id].from_resume = 0;
+ uart_dma_cycle[uart_id].from_unthrottle = false;
+#if 0
+ if(uart_dma_cycle[uart_id].flg_enter_th == 0)
+ uart_dma_cycle[uart_id].flg_enter_to = 4;
+ else
+ uart_dma_cycle[uart_id].flg_enter_to = uart_dma_cycle[uart_id].flg_enter_th - 1;
+ struct zx29_sgbuf *sgbuf_tmp = NULL;
+ sgbuf_tmp = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_to];
+ test_uart_static(zup->port.line, NULL, 0, 61);
+ if (sgbuf->sg.dma_address != (zx29_dma_cur_dst(rx_id)&0xfffff000)){
+ if(sgbuf_tmp->sg.dma_address != ((zx29_dma_cur_dst(rx_id)&0xfffff000)-0x1000)){
+ printk("uart lose dma isr enter self resume.\n");
+ up(&zup->sema_cyclic);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ return;
+ }
+ }
+ #endif
+ int fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXBUSY)){
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, 0, 12);
+ goto deal_end;
+ }
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ uart_dma_cycle[uart_id].flg_overrun = 1;
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
+ zup->port.icount.brk,zup->port.icount.parity);
+ }
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ dmaengine_terminate_all(rxchan);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(tmp_len != pending){
+ pending = tmp_len;
+ //test_uart_static(zup->port.line, NULL, tmp_len, 48);
+ }
+ wmb();
+ int i = 0;
+ for(i= 0;i < 3;i++){
+ fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXFE) == 0){
+ g_fifo_residue_buf[zup->port.line][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
+ g_fifo_residue_all[zup->port.line][g_fifo_cnt[zup->port.line]++] = g_fifo_residue_buf[zup->port.line][i];
+ if(g_fifo_cnt[zup->port.line] >= 20) g_fifo_cnt[zup->port.line] = 0;
+ }
+ else
+ break;
+ }
+ if(i){
+ g_fifo_residue_all[zup->port.line][g_fifo_cnt[zup->port.line]++]=i;
+ if(g_fifo_cnt[zup->port.line] >= 20) g_fifo_cnt[zup->port.line] = 0;
+ }
+ if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, (pending+i), 49);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ if((pending && (pending != 4096)) || (i > 0)){
+ zx29_uart_deal_dma_fifo_rx_chars_cyclic(zup, pending, sgbuf, &flags, g_fifo_residue_buf[zup->port.line],i);
+ }
+ uart_dma_cycle[uart_id].cnt_th = 0;
+ uart_dma_cycle[uart_id].cnt_callback=0;
+deal_end:
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_RESTART;
+ }else{
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ zup->pre_pending = pending;
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
+ return HRTIMER_RESTART;
+ }
+}
+#endif
+
+
+static void zx29_uart_modem_status(struct zx29_uart_port *zup)
+{
+ unsigned int status, delta;
+
+ status = UART_GET_FR(&zup->port)& UART_FR_MODEM_ANY;
+
+ delta = status ^ zup->old_status;
+ zup->old_status = status;
+
+ if (!delta)
+ return;
+
+ if (delta & UART_FR_DCD)
+ uart_handle_dcd_change(&zup->port, status & UART_FR_DCD);
+
+ if (delta & UART_FR_DSR)
+ zup->port.icount.dsr++;
+
+ if (delta & UART_FR_CTS)
+ uart_handle_cts_change(&zup->port, status & UART_FR_CTS);
+
+ wake_up_interruptible(&zup->port.state->port.delta_msr_wait);
+}
+
+/****************************************************************************/
+static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id)
+{
+ struct uart_port *port = (struct uart_port *)dev_id;
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ unsigned int status,ris, pass_counter = 256;
+ int handled = 0;
+ int uart_id = zup->port.line;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ status = UART_GET_MIS(port) & zup->imr;
+ ris = UART_GET_RIS(port);
+ if (status) {
+ do {
+ UART_PUT_ICR(port,(status & ~(UART_TXIS|UART_RTIS|UART_RXIS)));
+ if(uart_console(&zup->port)){
+ if (status & (UART_RTIS|UART_RXIS))
+ zx29_uart_rx_chars(zup);
+ }else{
+#ifdef CONFIG_CPU_IDLE
+ zup->rxd_int_depth = 0;
+#endif
+ if (status & (UART_RXIS)){
+#if CONFIG_SERIAL_ZX29_DMA
+ if(ris & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 8;
+ test_uart_static(zup->port.line, NULL, 0, 21);
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if (zx29_dma_rx_used(zup)){
+ UART_PUT_ICR(port,UART_RXIS);
+ if(!(zup->imr & UART_RTIM)){
+ zup->imr |= UART_RTIM;
+ UART_PUT_IMSC(port,zup->imr);
+ }
+
+ test_uart_static(port->line, NULL, 0, 8);
+ uart_mod_timer(zup, &flags);
+
+ }else{
+ test_uart_static(port->line, NULL, 0, 1);
+
+ zup->imr &= ~UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ zx29_uart_rx_dma_chars(zup, &flags);
+
+ zup->dmarx.used = true;
+ //when RX&RT comes both, we trigger dma and add timer,so clear RT,waiting the timer
+ if(status & (UART_RTIS))
+ status &= ~UART_RTIS;
+ }
+#else
+ zx29_uart_rx_chars(zup);
+#endif
+ }
+
+ if (status & (UART_RTIS)){
+#if CONFIG_SERIAL_ZX29_DMA
+ if(!zx29_dma_rx_running(zup)){
+ test_uart_static(port->line, NULL, 0, 2);
+ zx29_uart_rx_timeout_chars(zup, &flags);
+ }else{
+ UART_PUT_ICR(port, UART_RTIS);
+ test_uart_static(port->line, NULL, 0, 4);
+ zx29_uart_rt_dma(zup, &flags);
+ }
+#else
+ zx29_uart_rx_chars(zup);
+#endif
+ }
+ }
+
+ if (status & (UART_DSRMIS|UART_DCDMIS|UART_CTSMIS|UART_RIMIS))
+ zx29_uart_modem_status(zup);
+
+ if (status & UART_TXIS)
+ zx29_uart_tx_chars(zup);
+
+ if (pass_counter-- == 0)
+ break;
+
+ status = UART_GET_MIS(port);
+ } while (status != 0);
+ handled = IRQ_HANDLED;
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+
+ return IRQ_RETVAL(handled);
+}
+
+#if CONFIG_SERIAL_ZX29_DMA
+extern bool zx29_dma_filter_fn(struct dma_chan *chan, void *param);
+static void uart_dma_init(struct zx29_uart_port *zup)
+{
+ int i=0;
+ struct dma_chan *chan = NULL;
+
+ atomic_set(&zup->dmarx.count, 1);
+ atomic_set(&zup->dmatx.count, 1);
+#if 1
+ if(zup->port.line == UART0)
+ {
+ zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART0_BASE +zx29_UART_DR);
+ }
+ else if(zup->port.line == UART1)
+ {
+ zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART1_BASE+zx29_UART_DR);
+ }
+ else if(zup->port.line == UART2)
+ {
+ zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART2_BASE+zx29_UART_DR);
+ }
+
+ zup->dmatx.tx_def.dma_control.tran_mode = TRAN_MEM_TO_PERI;
+ zup->dmatx.tx_def.dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ zup->dmatx.tx_def.dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmatx.tx_def.dma_control.src_burst_len = DMA_BURST_LEN_4;
+ zup->dmatx.tx_def.dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmatx.tx_def.dma_control.dest_burst_len = DMA_BURST_LEN_4;
+
+ dma_cap_mask_t mask;
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ if(zup->port.line == UART0)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_TX);
+ }
+ else if(zup->port.line == UART1)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_TX);
+ }
+ else if(zup->port.line == UART2)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_TX);
+ }
+ if(!chan){
+ printk("UART%d DMA TX channel request fail.\n", zup->port.line);
+ return;
+ }
+ zup->dmatx.chan = chan;
+
+
+
+ for(i=0;i<UART_DMA_RX_MAX_COUNT;i++)
+ {
+ if(zup->port.line == UART0)
+ {
+ zup->dmarx.rx_def[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
+ }
+ else if(zup->port.line == UART1)
+ {
+ zup->dmarx.rx_def[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
+ }
+ else if(zup->port.line == UART2)
+ {
+ zup->dmarx.rx_def[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
+ }
+
+ zup->dmarx.rx_def[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
+ zup->dmarx.rx_def[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ zup->dmarx.rx_def[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmarx.rx_def[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
+ zup->dmarx.rx_def[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmarx.rx_def[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
+ }
+
+ zup->dmarx.rx_index = 0;
+ chan = NULL;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ if(zup->port.line == UART0)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_RX);
+ }
+ else if(zup->port.line == UART1)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_RX);
+ }
+ else if(zup->port.line == UART2)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_RX);
+ }
+ if(!chan){
+ printk("UART%d DMA RX channel request fail.\n", zup->port.line);
+ return;
+ }
+ zup->dmarx.chan = chan;
+#endif
+}
+
+static int uart_dma_cycle_init(struct zx29_uart_port *zup)
+{
+ int ret;
+ int uart_id = zup->port.line;
+ uart_dma_cycle[uart_id].id = zup->port.line;
+ int i,j;
+ for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
+ if(ret){
+ printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", zup->port.line, ret);
+ for(j=0;j<i;j++){
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[j],DMA_FROM_DEVICE);
+ }
+ return -1;
+ }
+
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[i],DMA_FROM_DEVICE);
+ if(ret){
+ printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", (zup->port.line+3), ret);
+ for(j=0;j<i;j++){
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[j],DMA_FROM_DEVICE);
+ }
+ return -1;
+ }
+ }
+ for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
+ if(zup->port.line == UART0){
+ uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id].used = false;
+ uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id+3].used = false;
+ }
+ else if(zup->port.line == UART1){
+ uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id].used = false;
+ uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id+3].used = false;
+ }
+ else if(zup->port.line == UART2){
+ uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id].used = false;
+ uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id+3].used = false;
+ }
+ uart_dma_cycle[uart_id].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id].sgbuf[i].dma_addr);
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ uart_dma_cycle[uart_id].rxdef[i].link_addr = 1;
+
+ uart_dma_cycle[uart_id+3].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id+3].sgbuf[i].dma_addr);
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id+3].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ uart_dma_cycle[uart_id+3].rxdef[i].link_addr = 1;
+
+ }
+ return 0;
+}
+static void uart_dma_cycle_deinit(struct zx29_uart_port *zup)
+{
+ int i;
+ int uart_id = zup->port.line;
+ for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[i],DMA_FROM_DEVICE);
+ }
+ memset(uart_dma_cycle[uart_id].rxdef, 0, sizeof(uart_dma_cycle[uart_id].rxdef));
+ memset(uart_dma_cycle[uart_id+3].rxdef, 0, sizeof(uart_dma_cycle[uart_id+3].rxdef));
+}
+static void uart_dma_startup(struct zx29_uart_port *zup)
+{
+ int ret = 0;
+ if (!zup->dmatx.chan)
+ {
+ printk("tx_chan is error[%s][%d]\n",__func__,__LINE__);
+ return;
+ }
+
+ zup->dmatx.buf = kmalloc(ZX29_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
+ if (!zup->dmatx.buf) {
+ printk("tx_buf is error[%s][%d]\n",__func__,__LINE__);
+ return;
+ }
+
+ sg_init_one(&zup->dmatx.sg, zup->dmatx.buf, ZX29_DMA_BUFFER_SIZE);
+
+ /* The DMA buffer is now the FIFO the TTY subsystem can use */
+ zup->port.fifosize = 16;//ZX29_DMA_BUFFER_SIZE;
+ zup->using_tx_dma = true;
+
+ if(!zup->uart_power_mode)
+ {
+ if (!zup->dmarx.chan)
+ {
+ printk(KERN_INFO "[%s][%d]uart_%d rx_chan is error\n",__func__,__LINE__, zup->port.line);
+ goto skip_rx;
+ }
+
+ /* Allocate and map DMA RX buffers */
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
+ DMA_FROM_DEVICE);
+ if (ret) {
+ printk(KERN_INFO "[%s][%d] uart_%d rx_buf_a is error\n",__func__,__LINE__, zup->port.line);
+ //dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
+ // "RX buffer A", ret);
+ goto skip_rx;
+ }
+
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_b,
+ DMA_FROM_DEVICE);
+ if (ret) {
+ printk( "failed to init DMA uart: %d RX buffer B ,ret:%d\n", zup->port.line, ret);
+ zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
+ DMA_FROM_DEVICE);
+ goto skip_rx;
+ }
+
+ zup->using_rx_dma = true;
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->curr_sg = NULL;
+#if RX_DMA_WORK
+ timer_setup(&(zup->rx_dma_timer), zx29_uart_rx_dma_timeout, 0);
+ hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout;
+ g_hr_interval = ktime_set(0, 1500000);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ zup->dmarx.use_buf_b = false;
+ zup->dmarx.rx_index = 0;
+
+ zup->pre_pending = 0;
+ zup->work_state = false;
+
+ zup->dma_compl_th = kthread_run(dma_complete_thread, zup, "uart_dma_compl");
+ BUG_ON(IS_ERR(zup->dma_compl_th));
+#endif
+
+skip_rx:
+
+ /* Turn on DMA error (RX/TX will be enabled on demand) */
+ printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
+ zup->dmacr &= ~UART_DMAONERR;
+ //zup->dmacr |= UART_DMAONERR;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ if(zup->uart_power_mode){
+ if (zup->using_rx_dma) {
+ //printk(KERN_INFO "[%s][%d]\n",__func__,__LINE__);
+ if (zx29_dma_rx_trigger_dma(zup)){
+ dev_dbg(zup->port.dev, "could not trigger initial "
+ "RX DMA job, fall back to interrupt mode\n");
+ }else{
+ mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+ }
+ }
+ }
+ else if(zup->uart_power_mode == 1)
+ {
+ ret = uart_dma_cycle_init(zup);
+ if(ret){
+ printk("uart%d dma cycle init failed,ret %d.\n",zup->port.line,ret);
+ return;
+ }
+ zup->using_rx_dma = true;
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->curr_sg = NULL;
+#if RX_DMA_WORK
+ hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout_cyclic;
+ g_hr_interval = ktime_set(0, 1500000);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ zup->dmarx.use_buf_b = false;
+ zup->dmarx.rx_index = 0;
+ zup->pre_pending = 0;
+ zup->work_state = false;
+ sema_init(&zup->sema_cyclic, 0);
+ zup->dma_compl_th = kthread_run(dma_complete_thread_use_dma_cyclic, zup, "uart_dma_th_cyc");
+ BUG_ON(IS_ERR(zup->dma_compl_th));
+#endif
+ printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
+ zup->dmacr &= ~UART_DMAONERR;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ if(zup->uart_power_mode){
+ if (zup->using_rx_dma) {
+ if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)){
+ dev_dbg(zup->port.dev, "could not trigger initial "
+ "RX DMA job, fall back to interrupt mode\n");
+ }else{
+ hrtimer_start(&zup->rx_dma_hrtimer, g_hr_interval, HRTIMER_MODE_REL);
+ //mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+ }
+ }
+ }else
+ printk("uart%d power mode set error,dma dont startup.\n",zup->port.line);
+}
+
+
+#endif
+
+static irqreturn_t zx29_uart_rxd_irq(int irq, void *dev_id)
+{
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)dev_id;
+
+ rxd_wake_cnt++;
+ zup->rxd_wakeup = true;
+ tasklet_schedule(&zup->write_wakeup);
+ zup->rxd_int_depth = 0;
+ return IRQ_HANDLED;//IRQ_RETVAL(retval);
+}
+
+/****************************************************************************/
+static int zx29_uart_startup(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags = 0;
+ unsigned long control = 0;
+ int retval = 0;
+ struct platform_device *pdev=port->private_data;
+// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ int i = 0,j = 0,iflag = 0;
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned int ibrd, fbrd,lcr_h, old_cr;
+ int ret=0;
+ printk("-----zx29_uart_startup, port:%d\n", port->line);
+ #if 0//def CONFIG_ARCH_ZX297520V3_WATCH
+
+ if(port->line == 0)
+ {
+ gpio_free(pdata->uart_txd.gpionum);
+ gpio_free(pdata->uart_rxd.gpionum);
+ //printk("gpio_free err err!\n");
+ }
+
+ wmb();
+
+ #endif
+ if(DEBUG_CONSOLE != pdev->id){
+ char temp_buf[TASK_COMM_LEN]= {0};
+ int th_ctrl = 0;
+ if((strlen(get_task_comm(temp_buf,get_current())) > 0) && (strcmp(get_task_comm(temp_buf,get_current()),"at_ctl") != 0))
+ th_ctrl = 1;
+
+ //app ctrl or kernel ctrl set this
+ int kernel_ctrl = xp2xp_enable_4line();
+ zup->uart_power_mode = (kernel_ctrl | zup->app_ctrl | th_ctrl);
+ printk("zx29_uart%d open task is %s,power_mode is %d.\n",pdev->id, get_task_comm(temp_buf,get_current()),zup->uart_power_mode);
+ if(zup->uart_power_mode){
+ //pm_stay_awake(&pdev->dev);
+ }
+ }
+ //when open, clear last statistic info
+ port->icount.brk = port->icount.buf_overrun = port->icount.frame = 0;
+ port->icount.overrun = port->icount.parity = port->icount.rng = 0;
+ port->icount.rx = port->icount.tx = 0;
+ /*
+ *enable uart clock
+ *if uart is used for console, don't need do these, these was done before
+ */
+ if (DEBUG_CONSOLE != port->line) {
+ /* config uart apb_clk */
+ clk_prepare_enable(zup->busclk);
+ /* enable uart work clock */
+ clk_prepare_enable(zup->wclk);
+ }
+
+ /* Clear all pending error and receive interrupts */
+ UART_PUT_ICR(port, 0xfff);
+
+ /* Allocate the IRQ */
+ retval = request_irq(port->irq, zx29_uart_interrupt, 0, "uart-zx29", zup);
+ if (retval){
+ printk("[UART]unable to attach zx29 UART %d "
+ "interrupt vector=%d\n", port->line, port->irq);
+ return retval;
+ }
+
+ /* set interrupt fifo level RX:1/2 Full, TX:1/2 Full */
+#if 0//CONFIG_SERIAL_ZX29_DMA
+ UART_PUT_IFLS(port, UART_IFLS_RX2_8|UART_IFLS_TX6_8);
+#else
+ UART_PUT_IFLS(port, UART_IFLS_RX2_8|UART_IFLS_TX4_8);
+#endif
+
+#if 0
+ /* Provoke TX FIFO interrupt into asserting. */
+ control = UART_CR_UARTEN | UART_CR_TXE | UART_CR_LBE;
+ UART_PUT_CR(port, control);
+ UART_PUT_FBRD(port, 0);
+ UART_PUT_IBRD(port, 1);
+ UART_PUT_LCRH(port, 0);
+ UART_PUT_CHAR(port, 0);
+ while (UART_GET_FR(port) & UART_FR_TXBUSY)
+ barrier();
+#endif
+ control = UART_CR_UARTEN | UART_CR_RXE | UART_CR_TXE;
+ //console & lp_uart don't need dma
+ if ((DEBUG_CONSOLE != port->line) && (port->line != 4)) {
+#if CONFIG_SERIAL_ZX29_DMA
+ UART_PUT_DMACR(port, UART_TXDMAE | UART_RXDMAE);
+ uart_dma_startup(zup);
+#endif
+ }
+
+ tasklet_init(&zup->write_wakeup, uart_write_wakeup_task, (unsigned long) port);
+ if((pdev->id == 0) && (zup->irq_state == 0) && (zup->uart_power_mode == 0)){
+ ret = request_irq(zup->rxd_irq,
+ zx29_uart_rxd_irq,
+ 0,
+ "uart0_rxd_wake",
+ zup);
+ if(ret<0){
+ panic("request uart0 rxd wake irq fail\n");
+ }
+ printk("--------rxd wake up interrupt ok\n");
+ enable_irq_wake(zup->rxd_irq);
+ zup->irq_state = 1;
+ zup->rxd_int_depth = 1;
+ }
+#if 0
+ /*configure gpio pin to UART*/
+ if((pdata->uart_use)/*&&(port->line == UART0 )*/)
+ {
+ retval=gpio_request(pdata->uart_rxd.gpionum,pdata->uart_rxd.gpioname);
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_txd.gpioname);
+ if(retval)
+ BUG();
+ /*uart rxd*/
+ zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
+ if(pdata->uart_rxd.gpionum == ZX29_GPIO_121 ) {
+ //pull up gpio121
+ *(volatile unsigned int *)0xf843c82c |= 0xf0;
+ }
+ /*uart txd*/
+ zx29_gpio_config(pdata->uart_txd.gpionum, pdata->uart_txd.gpiofnc);
+#ifdef CONFIG_ARCH_ZX297520V3
+ if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 0)){
+ zup->irq = platform_get_irq_byname(pdev, "zx29_uart_rxd_wakeup");
+ printk(KERN_INFO"zx29_uart_startup,irq:%d,%s.%d\n",zup->irq,pdata->uart_cts.gpioname,zup->irq_state);
+ if(zup->irq >= 0){
+
+ pcu_int_set_type(PCU_UART0_RXD_INT, IRQF_TRIGGER_FALLING);
+ pcu_int_clear(PCU_UART0_RXD_INT);
+ ret = request_irq(zup->irq, zx29_uart_rxd_irq,
+ IRQF_ONESHOT , "uart_rxd_irq",
+ zup);
+ printk(KERN_INFO"zx29_uart_startup, retval:%d\n",ret);
+ irq_set_irq_wake(zup->irq,1);
+#ifdef CONFIG_CPU_IDLE
+ zup->rxd_int_depth = rxd_wake_cnt = 0;
+ zx_pm_register_callback(uart_0_pm_enter, uart_0_pm_exit);
+ disable_irq_nosync(UART0_RXD_INT);
+#endif
+ zup->irq_state = 1;
+ }else{
+ printk("uart_startup, request wake irq fail:%d\n",zup->irq);
+ }
+ }
+#endif
+ if(pdata->uart_ctsrtsuse)
+ {
+ retval=gpio_request(pdata->uart_cts.gpionum,pdata->uart_cts.gpioname);
+ if(retval)
+ BUG();
+
+ retval=gpio_request(pdata->uart_rts.gpionum,pdata->uart_rts.gpioname);
+ if(retval)
+ BUG();
+/*uart cts*/
+ zx29_gpio_config(pdata->uart_cts.gpionum, pdata->uart_cts.gpiofnc);
+/*uart rts*/
+ zx29_gpio_config(pdata->uart_rts.gpionum, pdata->uart_rts.gpiofnc);
+
+ control |= (UART_CR_RTSEN |UART_CR_CTSEN );
+ control |= UART_CR_RTS; //wl write1 for allow send
+ }
+ zup->autobaud = pdata->uart_abauduse ;
+ }
+#if 0
+ if((pdata->uart_use)&&(port->line == UART1 ))
+ {
+ retval=gpio_request(pdata->uart_rx.gpionum,pdata->uart_rx.gpioname);
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_tx.gpioname);
+ if(retval)
+ BUG();
+/*uart rxd*/
+ zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
+/*uart txd*/
+ zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
+
+ if(pdata->uart_ctsrtsuse)
+ {
+ retval=gpio_request(pdata->uart_ctsnum,"uart1_cts");
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_rtsnum,"uart1_rts");
+ if(retval)
+ BUG();
+/*uart cts*/
+ zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
+/*uart rts*/
+ zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
+
+ control |= (UART_CR_RTSEN |UART_CR_CTSEN );
+ control |= UART_CR_RTS; //wl write1 for allow send
+ }
+ zup->autobaud = pdata->uart_abauduse;
+ }
+ if((pdata->uart_use)&&(port->line == UART2 ))
+ {
+ retval=gpio_request(pdata->uart_rxdnum,"uart2_rxd");
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_txdnum,"uart2_txd");
+ if(retval)
+ BUG();
+
+/*uart rxd*/
+ zx29_gpio_config(pdata->uart_rxdnum, pdata->uart_rxdfnc);
+ if(pdata->uart_rxdnum == ZX29_GPIO_121 ) {
+ //pull up gpio121
+ *(volatile unsigned int *)0xf843c82c |= 0xf0;
+ }
+/*uart txd*/
+ zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
+
+ if(pdata->uart_ctsrtsuse)
+ {
+ retval=gpio_request(pdata->uart_ctsnum,"uart2_cts");
+ if(retval)
+ BUG();
+
+ retval=gpio_request(pdata->uart_rtsnum,"uart2_rts");
+ if(retval)
+ BUG();
+/*uart cts*/
+ zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
+/*uart rts*/
+ zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
+
+ control |= (UART_CR_RTSEN |UART_CR_CTSEN );
+ control |= UART_CR_RTS; //wl write1 for allow send
+ }
+ zup->autobaud = pdata->uart_abauduse ;
+ }
+#endif
+#endif
+ zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
+ UART_PUT_CR(port, control);
+
+ /*
+ * Finally, enable interrupts, only timeouts when using DMA
+ * if initial RX DMA job failed, start in interrupt mode
+ * as well.
+ */
+ spin_lock_irqsave(&zup->port.lock, flags);
+ /* Clear out any spuriously appearing RX interrupts */
+ UART_PUT_ICR(port, (UART_RTIS | UART_RXIS));
+ //when dma not running,set UART_RTIM | UART_RXIM
+ if(!zx29_dma_rx_running(zup)){
+ zup->imr = UART_RTIM | UART_RXIM;
+ UART_PUT_IMSC(port, zup->imr);
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ zup->port_close = false;
+#endif
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+
+
+ return 0;
+}
+
+/****************************************************************************/
+static void zx29_uart_shutdown(struct uart_port *port)
+{
+ printk("zx29_uart%d_shutdown.\n",port->line);
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ uint32_t val;
+ int retval = 0;
+ struct platform_device *pdev=port->private_data;
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+#if CONFIG_SERIAL_ZX29_DMA
+ zup->port_close = true;
+ if(zup->uart_power_mode)
+ up(&zup->sema_cyclic);
+ else
+ up(&zup->sema);
+#endif
+ int ret;
+ tasklet_kill(&zup->write_wakeup);
+#if RX_DMA_WORK
+ if(zx29_dma_rx_work_scheduled(zup)){
+ ret = del_timer_sync(&(zup->rx_dma_timer));
+ ret = hrtimer_cancel(&zup->rx_dma_hrtimer);
+ zup->work_state = 0;
+ }
+#endif
+ /* Disable and clear all interrupts now */
+ spin_lock_irqsave(&port->lock, flags);
+ zup->imr = 0;
+ UART_PUT_IMSC(port, zup->imr);
+ UART_PUT_ICR(port, 0xFFFF);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_shutdown(zup);
+#endif
+ /* Free the interrupt */
+ free_irq(zup->port.irq, zup);
+
+ /* Disable UART transmitter and receiver */
+ zup->autorts = false;
+ val = UART_GET_CR(port);
+ if (val & UART_CR_RTS) {
+ zup->rts_state = true;
+ val = UART_CR_RTS;
+ } else
+ zup->rts_state = false;
+ val = UART_CR_UARTEN | UART_CR_TXE;
+ UART_PUT_CR(port, val);
+
+ /* disable break condition and fifos */
+ val = UART_GET_LCRH(port);
+ val &= ~(UART_LCRH_BRK | UART_LCRH_FEN);
+ UART_PUT_LCRH(port, val);
+ if(zup->uart_power_mode){
+ //pm_relax(&pdev->dev);
+ zup->app_ctrl = 0;
+ zup->uart_power_mode = 0;
+ }
+
+ if((pdev->id == 0) && (zup->irq_state == 1) && (zup->uart_power_mode == 0)){
+ free_irq(zup->rxd_irq, zup);
+ disable_irq_wake(zup->rxd_irq);
+ zup->irq_state = 0;
+ }
+
+#if 0
+ if(pdata->uart_use)
+ {
+ if(pdata->uart_ctsrtsuse)
+ {
+ gpio_free(pdata->uart_cts.gpionum);
+ gpio_free(pdata->uart_rts.gpionum);
+ }
+#ifdef CONFIG_ARCH_ZX297520V3
+ if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 1)){
+ printk(KERN_INFO"zx29_uart_shutdown,irq:%d,%s\n",zup->irq,pdata->uart_cts.gpioname);
+ if(zup->irq){
+ free_irq(zup->irq, zup);
+ pcu_int_clear(PCU_UART0_RXD_INT);
+ irq_set_irq_wake(zup->irq, 0);
+ zup->irq_state = 0;
+ zup->rxd_int_depth = 0;
+ }
+ }
+#endif
+ gpio_free(pdata->uart_rxd.gpionum);
+ gpio_free(pdata->uart_txd.gpionum);
+
+#ifdef CONFIG_ARCH_ZX297520V3_WATCH
+ if(port->line == 0)
+ {
+ retval = gpio_request(pdata->uart_txd.gpionum, pdata->uart_txd.gpioname);
+ if(retval)
+ {
+ BUG();
+ }
+ zx29_gpio_config(pdata->uart_txd.gpionum, GPIO30_GPIO30);
+ gpio_direction_input(pdata->uart_txd.gpionum);
+
+ retval = gpio_request(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpioname);
+ if(retval)
+ {
+ BUG();
+ }
+ zx29_gpio_config(pdata->uart_rxd.gpionum, GPIO29_GPIO29);
+ gpio_direction_input(pdata->uart_rxd.gpionum);
+ }
+#endif
+
+ }
+#endif
+ /* Shutdown uart clock */
+}
+
+/****************************************************************************/
+static void zx29_uart_set_termios(struct uart_port *port, struct ktermios *termios,
+ struct ktermios *old)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned int lcr_h, old_cr;
+ unsigned long flags;
+ unsigned int baud, ibrd, fbrd,j;
+
+ //temple change,using setting from cmm script
+ //if(port->line == DEBUG_CONSOLE)
+ //return;
+
+ /* Set baud rate */
+ /* Ask the core to calculate the divisor for us. */
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ printk("uart port %d baud is %d.\n",port->line,baud);
+
+ //this should not hapend
+ if(baud == 0)
+ BUG_ON(1);
+ zup->baudrate = baud;
+ ibrd = port->uartclk / (baud<<4);
+ fbrd = ((port->uartclk % (baud<<4) )*8 + baud)/(2*baud);
+ UART_PUT_FBRD(port, fbrd);
+ UART_PUT_IBRD(port, ibrd);
+
+printk("-------zx29_uart_set_termios,line:%d, new baud:%d, uartclk:%d,ibrd:%d, fbrd:%d \n", port->line,
+ baud, port->uartclk, ibrd, fbrd);
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ lcr_h = UART_LCRH_WLEN_5;
+ break;
+ case CS6:
+ lcr_h = UART_LCRH_WLEN_6;
+ break;
+ case CS7:
+ lcr_h = UART_LCRH_WLEN_7;
+ break;
+ default: // CS8
+ lcr_h = UART_LCRH_WLEN_8;
+ break;
+ }
+ if (termios->c_cflag & CSTOPB)
+ lcr_h |= UART_LCRH_STP2;
+ if (termios->c_cflag & PARENB) {
+ lcr_h |= UART_LCRH_PEN;
+ if (!(termios->c_cflag & PARODD))
+ lcr_h |= UART_LCRH_EPS;
+ }
+ if (port->fifosize > 1)
+ lcr_h |= UART_LCRH_FEN;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /*
+ * Update the per-port timeout.
+ */
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ port->read_status_mask = UART_DR_OE | 255;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= UART_DR_FE | UART_DR_PE;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= UART_DR_BE;
+
+ /*
+ * Characters to ignore
+ */
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART_DR_FE | UART_DR_PE;
+ if (termios->c_iflag & IGNBRK) {
+ port->ignore_status_mask |= UART_DR_BE;
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART_DR_OE;
+ }
+
+ /*
+ * Ignore all characters if CREAD is not set.
+ */
+ if ((termios->c_cflag & CREAD) == 0)
+ port->ignore_status_mask |= UART_DUMMY_DR_RX;
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ zx29_uart_enable_ms(port);
+
+ /* first, disable everything */
+ old_cr = UART_GET_CR(port);
+ UART_PUT_CR(port, 0);
+
+ if (termios->c_cflag & CRTSCTS) {
+ if (old_cr & UART_CR_RTS)
+ old_cr |= UART_CR_RTSEN;
+
+ old_cr |= UART_CR_CTSEN;
+ port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
+ zup->autorts = true;
+ } else {
+ old_cr &= ~(UART_CR_CTSEN | UART_CR_RTSEN);
+ zup->autorts = false;
+ port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
+ }
+
+ /*
+ * ----------v----------v----------v----------v-----
+ * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+ * ----------^----------^----------^----------^-----
+ */
+ UART_PUT_LCRH(port, lcr_h);
+ UART_PUT_CR(port, old_cr);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+ if( zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
+ {
+ msleep(50);
+ zup->port.icount.rx = 0;
+
+ for( j = 0; j<UART_AT_SENDOK_NUM; j++)
+ {
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(&zup->port, UART_AT_send_ok[j]);
+ }
+
+ zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
+ }
+}
+
+/****************************************************************************/
+static const char *zx29_uart_type(struct uart_port *port)
+{
+ return (port->type == PORT_ZX29) ? "zx29_UART" : NULL;
+}
+
+/****************************************************************************/
+
+static int zx29_uart_request_port(struct uart_port *port)
+{
+ /* UARTs always present */
+// return request_mem_region(port->mapbase, SZ_4K, "uart-zx29")!= NULL ? 0 : -EBUSY;
+ return 0;
+}
+
+/****************************************************************************/
+static void zx29_uart_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_ZX29;
+ zx29_uart_request_port(port);
+ }
+}
+
+/****************************************************************************/
+
+static void zx29_uart_release_port(struct uart_port *port)
+{
+// release_mem_region(port->mapbase, SZ_4K);
+}
+
+/****************************************************************************/
+
+static int zx29_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+ if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ZX29))
+ return -EINVAL;
+ return 0;
+}
+
+
+void zx29_uart_putc(struct uart_port *port, int c)
+{
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, c);
+}
+
+
+#ifdef CONFIG_CONSOLE_POLL
+/****************************************************************************/
+static int zx29_get_poll_char(struct uart_port *port)
+{
+ if (UART_GET_FR(port) & UART_FR_RXFE)
+ return NO_POLL_CHAR;
+
+ return UART_PUT_CHAR(port);
+}
+
+/****************************************************************************/
+static void zx29_put_poll_char(struct uart_port *port, unsigned char ch)
+{
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, ch);
+}
+#endif /* CONFIG_CONSOLE_POLL */
+extern int tty_buffer_space_avail(struct tty_port *port);
+static void zx29_uart_throttle_rx(struct uart_port *port)
+{
+ test_uart_static(port->line, NULL, 0, 80);
+ unsigned long flags;
+ int uart_id = port->line;
+
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ spin_lock_irqsave(&port->lock, flags);
+ if(!uart_dma_cycle[port->line].used)
+ uart_id = uart_id + 3;
+ if(!tty_buffer_space_avail(&port->state->port)){
+ zx29_dma_stop(DMA_CH_UART0_RX);
+ uart_dma_cycle[uart_id].enter_throttle = true;
+ uart_dma_cycle[uart_id].cnt_throttle++;
+ }
+ spin_unlock_irqrestore(&port->lock, flags);
+ #if 0
+ while(zx29_dma_get_transfer_num(rx_id) != 4096)
+ msleep(1);
+ spin_lock_irqsave(&port->lock, flags);
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ uart_dma_cycle[port->line].enter_throttle = true;
+ spin_unlock_irqrestore(&port->lock, flags);
+ #endif
+}
+static void zx29_uart_unthrottle_rx(struct uart_port *port)
+{
+ test_uart_static(port->line, NULL, 0, 81);
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ int uart_id = port->line;
+ spin_lock_irqsave(&port->lock, flags);
+ if(!uart_dma_cycle[port->line].used)
+ uart_id = uart_id + 3;
+ uart_dma_cycle[uart_id].enter_throttle = false;
+ uart_dma_cycle[uart_id].from_unthrottle = true;
+ uart_dma_cycle[uart_id].cnt_unthrottle++;
+ #if 0
+ if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
+ }
+ #endif
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/****************************************************************************/
+/*
+ * Define the basic serial functions we support.
+ */
+static const struct uart_ops zx29_uart_ops = {
+ .tx_empty = zx29_uart_tx_empty,
+ .set_mctrl = zx29_uart_set_mctrl,
+ .get_mctrl = zx29_uart_get_mctrl,
+ .start_tx = zx29_uart_start_tx,
+ .stop_tx = zx29_uart_stop_tx,
+ .stop_rx = zx29_uart_stop_rx,
+ .throttle = zx29_uart_throttle_rx,
+ .unthrottle = zx29_uart_unthrottle_rx,
+ .enable_ms = zx29_uart_enable_ms,
+ .break_ctl = zx29_uart_break_ctl,
+ .startup = zx29_uart_startup,
+ .shutdown = zx29_uart_shutdown,
+ .set_termios = zx29_uart_set_termios,
+#if CONFIG_SERIAL_ZX29_DMA
+ .flush_buffer = zx29_dma_flush_buffer,
+#endif
+ .type = zx29_uart_type,
+ .request_port = zx29_uart_request_port,
+ .release_port = zx29_uart_release_port,
+ .config_port = zx29_uart_config_port,
+ .verify_port = zx29_uart_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+ .poll_get_char = zx29_get_poll_char,
+ .poll_put_char = zx29_put_poll_char,
+#endif
+
+};
+
+
+/****************************************************************************/
+static int zx29_init_ports(struct zx29_uart_port *zx29_port,
+ struct platform_device *pdev)
+{
+ int ret = 0;
+ struct uart_port *port=&zx29_port->port;
+ unsigned int offset=(unsigned int)(pdev->id);
+ struct device_node *np = pdev->dev.of_node;
+ unsigned int baud, ibrd, fbrd;
+
+ struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ //struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+ if(!regs){
+ dev_err(&pdev->dev, "zx29_init_ports, get resource fail,\n");
+ return -ENODEV;
+ }
+/*get apb clock*/
+ zx29_port->busclk = devm_clk_get(&pdev->dev, UART_APBCLK_NAME);
+ if (IS_ERR(zx29_port->busclk)) {
+ ret = PTR_ERR(zx29_port->busclk);
+ printk("failed to get zx29_port->busclk: %d\n", ret);
+ return ret;
+ }
+
+ /*get work clock*/
+ zx29_port->wclk = devm_clk_get(&pdev->dev, UART_WCLK_NAME);
+
+ if (IS_ERR(zx29_port->wclk)) {
+ ret = PTR_ERR(zx29_port->wclk);
+ printk("failed to get zx29_port->wclk: %d\n", ret);
+ return ret;
+ }
+ if(offset == 0){
+ clk_set_rate(zx29_port->wclk, 104 * 1000000);
+ }
+ port->line = offset;
+ port->type = PORT_ZX29;
+ port->fifosize = UART_TXFIFO_SIZE;
+ //port->iotype = UPIO_MEM;
+ //port->irq = irq->start;
+ port->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+ if(pdev->id == 0){
+ zx29_port->rxd_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
+ }
+ //port->membase = devm_ioremap_nocache(&pdev->dev, regs->start,
+ // resource_size(regs));
+ port->membase = devm_platform_ioremap_resource(pdev, 0);
+
+ if (!port->membase)
+ return -ENODEV;
+ port->mapbase = regs->start;
+ port->mapsize = resource_size(regs);
+
+ //port->flags = UPF_BOOT_AUTOCONF;
+ port->ops = &zx29_uart_ops;
+ port->uartclk = clk_get_rate(zx29_port->wclk);
+
+ port->private_data = pdev;
+ //here is temple def
+ if(port->uartclk == 0){
+ printk("---zx29_init_ports, uartclk hard set to 26M\n");
+ port->uartclk = 26000000;
+ }
+ printk("---zx29_init_ports, line:%d, irq:%d, membase:%08x, uartclk:%d\n", port->line, port->irq, port->membase, port->uartclk);
+ /*
+ * just configure clock,
+ * actually pin configuration is needed, but now gpio driver is not OK
+ * use bootloader default configuration
+ */
+ if(DEBUG_CONSOLE == pdev->id){
+ /* config uart apb_clk */
+ clk_prepare_enable(zx29_port->busclk);
+
+ /* enable uart work clock */
+ clk_prepare_enable(zx29_port->wclk);
+ }
+ return 0;
+}
+
+
+#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
+
+#if VEHICLE_USE_ONE_UART_LOG
+static void zx29_uart_console_putc(struct uart_port *port, int c)
+{
+ if(g_core_id_occupy_uart == SYMB_PS_CORE_ID)
+ return;
+ int ret = soft_spin_lock_printf(UART_SFLOCK);
+ if(ret)
+ return;
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, c);
+ soft_spin_unlock(UART_SFLOCK);
+}
+#else
+static void zx29_uart_console_putc(struct uart_port *port, int c)
+{
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, c);
+}
+
+#endif
+
+
+
+/****************************************************************************/
+static void zx29_uart_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct uart_port *port = &zx29_uart_ports[co->index].port;
+
+ //spin_lock(&port->lock);
+ for (; (count); count--, s++) {
+ zx29_uart_console_putc(port, *s);
+ if (*s == '\n')
+ zx29_uart_console_putc(port, '\r');
+ }
+
+ //spin_unlock(&port->lock);
+}
+
+/***************************************************************************
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ ****************************************************************************/
+static void __init zx29_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits)
+{
+ if (UART_GET_CR(port) & UART_CR_UARTEN) {
+ unsigned int lcr_h, ibrd, fbrd;
+
+ lcr_h = UART_GET_LCRH(port);
+ *parity = 'n';
+ if (lcr_h & UART_LCRH_PEN) {
+ if (lcr_h & UART_LCRH_EPS)
+ *parity = 'e';
+ else
+ *parity = 'o';
+ }
+ if ((lcr_h & 0x60) == UART_LCRH_WLEN_7)
+ *bits = 7;
+ else
+ *bits = 8;
+
+ ibrd = UART_GET_IBRD(port);
+ fbrd = UART_GET_FBRD(port);
+
+ *baud = port->uartclk * 8 / (16*8 * ibrd + 2*fbrd-1);
+ }
+}
+
+/****************************************************************************/
+static int __init zx29_uart_console_setup(struct console *co, char *options)
+{
+ printk("zx29_uart_console_setup.\n");
+ struct uart_port *port;
+ int baud = 115200;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+ unsigned int uart_cr = 0;
+
+ if ((co->index < 0) || (co->index >= zx29_MAXPORTS))
+ co->index = CONFIG_UART_CONSOLE_ID;
+
+ port = &zx29_uart_ports[co->index].port;
+ if (port->membase == NULL)
+ return -ENODEV;
+
+ uart_cr = UART_GET_CR(port);
+ uart_cr |= UART_CR_UARTEN | UART_CR_TXE;
+ UART_PUT_CR(port,uart_cr);
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ else
+ zx29_console_get_options(port, &baud, &parity, &bits);
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+/****************************************************************************/
+
+static struct uart_driver zx29_uart_driver;
+int zx29_get_console_index(void)
+{
+#if 0
+ int dev_cnt = zx29_device_table_num;
+ int idx = 0;
+ struct platform_device *pdev = NULL;
+ for(idx = 0; idx < dev_cnt; idx++)
+ {
+ pdev = zx29_device_table[idx];
+ if(strcmp(pdev->name,"zx29_uart") == 0 && pdev->id == CONFIG_UART_CONSOLE_ID)
+ return idx;
+ }
+#endif
+ return CONFIG_UART_CONSOLE_ID;
+ //return -1;
+}
+static struct console zx29_uart_console = {
+ .name = "ttyS",
+ .write = zx29_uart_console_write,
+ .device = uart_console_device,
+ .setup = zx29_uart_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &zx29_uart_driver,
+};
+static int __init zx29_uart_console_init(void)
+{
+ int console_dev_id = zx29_get_console_index();
+
+ if(console_dev_id < 0){
+ printk("console init fail, uart config fail, console_dev_id is: %d", console_dev_id);
+ return -1;
+ }
+ //zx29_init_ports(&zx29_uart_ports[DEBUG_CONSOLE], zx29_device_table[console_dev_id]);
+ register_console(&zx29_uart_console);
+ pr_info("[UART]register_console: zx29 console registered!\n");
+
+ return 0;
+}
+
+//console_initcall(zx29_uart_console_init);
+
+#define zx29_UART_CONSOLE (&zx29_uart_console)
+
+
+static void zx29_uart_early_write(struct console *con, const char *s, unsigned n)
+{
+ struct earlycon_device *dev = con->data;
+
+ uart_console_write(&dev->port, s, n, zx29_uart_console_putc);
+}
+
+static int __init zx29_uart_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ if (!device->port.membase)
+ return -ENODEV;
+
+ device->con->write = zx29_uart_early_write;
+
+ return 0;
+}
+
+OF_EARLYCON_DECLARE(zx29_uart, "zxic,zx29-uart", zx29_uart_early_console_setup);
+#else
+#define zx29_UART_CONSOLE NULL
+#endif /* CONFIG_zx29_UART_CONSOLE */
+static void zx29_uart_pin_ctrl(struct platform_device *pdev)
+{
+ struct pinctrl *pin_ctrl;
+ struct pinctrl_state *state0;
+ pin_ctrl = devm_pinctrl_get(&pdev->dev);
+ switch(pdev->id){
+ case 0:
+ printk("zx29_uart %d use default pinctrl.",pdev->id);
+ break;
+ case 1:
+ printk("zx29_uart %d use default pinctrl.",pdev->id);
+ break;
+
+ case 2:
+ if(IS_ERR(pin_ctrl)){
+ dev_warn(&pdev->dev, "fail to get uart2 pins.");
+ pin_ctrl = NULL;
+ return;
+ }
+ state0 = pinctrl_lookup_state(pin_ctrl, "default");
+ if(IS_ERR(state0)){
+ dev_err(&pdev->dev, "uart2 pinstate get fail.\n");
+ }
+ if(pinctrl_select_state(pin_ctrl, state0)){
+ dev_err(&pdev->dev, "uart2 select pinstate fail.\n");
+ }
+ break;
+ }
+}
+
+/*
+ * Define the zx29 UART driver structure.
+ */
+static struct uart_driver zx29_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "zx29_uart",
+ .dev_name = "ttyS",
+ .major = SERIAL_zx29_MAJOR,
+ .minor = SERIAL_MINOR_START,
+ .nr = zx29_MAXPORTS,
+ .cons = zx29_UART_CONSOLE,
+};
+
+unsigned char uart_wakelock_name[zx29_MAXPORTS][20]={{0}};
+/****************************************************************************/
+
+
+#ifdef CONFIG_PM_SLEEP
+static int zx29_uart_suspend(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_uart_port *zup = dev_get_drvdata(dev);
+ unsigned int flags;
+ if (!zup)
+ return -EINVAL;
+ if(zup->port.line == UART1)
+ return 0;
+#if 1
+ pinctrl_pm_select_sleep_state(dev);
+#endif
+
+ printk("zx29_uart%d suspend.\n",zup->port.line);
+
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ zup->enter_suspend = 1;
+ if(zup->port.line == UART2){
+ zx29_dma_stop(DMA_CH_UART2_RX);
+ zx29_dma_stop(DMA_CH_UART2_TX);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return 0;
+ }
+
+ zx29_dma_stop(DMA_CH_UART0_RX);
+ zx29_dma_stop(DMA_CH_UART0_TX);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+#if 0
+ ret = irq_set_irq_type(unsigned int irq, unsigned int type);
+
+#endif
+ //pcu_int_clear(PCU_UART0_RXD_INT);
+ if(zup->irq_state && (zup->rxd_int_depth == 0)){
+ struct irq_data *data_rxd;
+ data_rxd= irq_get_irq_data(zup->rxd_irq);
+ if(data_rxd){
+ if(irqd_irq_disabled(data_rxd))
+ enable_irq(zup->rxd_irq);
+ }
+ zup->rxd_int_depth = 1;
+ }
+
+ return 0;
+}
+
+static int zx29_uart_resume(struct device *dev)
+{
+ struct zx29_uart_port *zup = dev_get_drvdata(dev);
+
+ if (!zup)
+ return -EINVAL;
+ int uart_id = zup->port.line;
+ if(!uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+ if(zup->port.line == UART1)
+ return 0;
+#if 1
+ pinctrl_pm_select_default_state(dev);
+#endif
+
+ printk("zx29_uart%d resume.\n",zup->port.line);
+
+ zup->enter_suspend = 0;
+ uart_dma_cycle[uart_id].from_resume = 1;
+ return 0;
+}
+
+
+#endif
+
+static SIMPLE_DEV_PM_OPS(zx29_uart_dev_pm_ops, zx29_uart_suspend, zx29_uart_resume);
+
+
+
+static int zx29_uart_probe(struct platform_device *pdev)
+{
+ int ret=0;
+ int error;
+ char wakelock_name[20];
+ struct device_node *np = pdev->dev.of_node;
+ ret = of_alias_get_id(np, "uart");
+
+ if(ret < 0){
+ printk("-----zx29_uart_probe,of_alias_get_id fail ret:%d\n", ret);
+ return -ENODEV;
+ }
+ pdev->id = ret;
+ printk("-----zx29_uart_probe,ret:%d\n", ret);
+ // struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ struct zx29_uart_port *port = &zx29_uart_ports[pdev->id];
+
+
+#if 0//def CONFIG_SERIAL_ZX29_UART_CONSOLE
+ if(DEBUG_CONSOLE != pdev->id){
+ ret = zx29_init_ports(port,pdev);
+ }
+#else
+ ret = zx29_init_ports(port,pdev);
+
+#endif
+ if(ret < 0){
+ printk("-----zx29_uart_probe,zx29_init_ports fail ret:%d\n", ret);
+ }
+ zx29_uart_pin_ctrl(pdev);
+#if CONFIG_SERIAL_ZX29_DMA
+ if((DEBUG_CONSOLE != pdev->id ) && (pdev->id != 4))
+ {
+ uart_dma_init(port);
+ printk(KERN_INFO "[%s][%d]UART_%d DMA is OPENED\n",__func__,__LINE__,pdev->id);
+ }
+#endif
+ ret = 0;
+ ret=uart_add_one_port(&zx29_uart_driver, &port->port);
+
+ if(ret)
+ {
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_remove(port);
+#endif
+ return ret;
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ sema_init(&port->sema, 0);
+#endif
+
+ platform_set_drvdata(pdev, port);
+
+ if(pdev->id == DEBUG_CONSOLE){
+ //g_console_open_flag = pdata->uart_input_enable ? pdata->uart_input_enable : 0;
+ error = device_create_file(&pdev->dev, &dev_attr_console_input);
+#if VEHICLE_USE_ONE_UART_LOG
+ error = device_create_file(&pdev->dev, &dev_attr_console_uart_toggle);
+ error = device_create_file(&pdev->dev, &dev_attr_coreid_occupy_uart);
+ int ret;
+ ret = rpmsgCreateChannel(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, ICP_BUFFERSIZE_CONSOLE_TOGGLE);
+ if(ret){
+ printk("linux5 request icp channel for uart fail %d.\n",ret);
+ }
+ rpmsgRegCallBack(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, icp_callback_ps2cap);
+#endif
+ }
+
+ if(pdev->id != DEBUG_CONSOLE){
+ error = device_create_file(&pdev->dev, &dev_attr_ctsrts_input);
+ error = device_create_file(&pdev->dev, &dev_attr_wakeup_enable);
+ error = device_create_file(&pdev->dev, &dev_attr_sleep_state);
+ error = device_create_file(&pdev->dev, &dev_attr_app_ctrl);
+
+ }
+ if(pdev->id == 2){
+ error = device_create_file(&pdev->dev, &dev_attr_uart_io_select);
+ }
+ error = device_create_file(&pdev->dev, &dev_attr_statics);
+ device_init_wakeup(&pdev->dev, true);
+/*
+ strcpy(wakelock_name, "uart_wakelock_x");
+ wakelock_name[14] = '0' + pdev->id;
+ strcpy(uart_wakelock_name[pdev->id], wakelock_name);
+ wake_lock_init(&(port->port.port_wakelock),WAKE_LOCK_SUSPEND,uart_wakelock_name[pdev->id]);
+*/
+
+ printk(KERN_INFO "TSP zx29 UART_%d probe OK\n",pdev->id);
+ return 0;
+}
+
+/****************************************************************************/
+static int /*__devexit*/ zx29_uart_remove(struct platform_device *pdev)
+{
+ struct uart_port *port = NULL;
+#if CONFIG_SERIAL_ZX29_DMA
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+#endif
+ int i;
+ if(pdev->id == DEBUG_CONSOLE){
+ device_remove_file(&pdev->dev, &dev_attr_console_input);
+ }
+
+ if(pdev->id != DEBUG_CONSOLE){
+ device_remove_file(&pdev->dev, &dev_attr_ctsrts_input);
+ device_remove_file(&pdev->dev, &dev_attr_wakeup_enable);
+ }
+
+ for (i = 0; (i < zx29_MAXPORTS); i++) {
+ port = &zx29_uart_ports[i].port;
+ if (port){
+ uart_remove_one_port(&zx29_uart_driver, port);
+
+
+#if CONFIG_SERIAL_ZX29_DMA
+ zup=container_of(port,struct zx29_uart_port,port);
+ zx29_dma_remove(zup);
+
+#endif
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id zx29_uart_of_match[] = {
+ { .compatible = "zxic,zx29-uart"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_uart_of_match);
+
+static struct platform_driver zx29_uart_platform_driver = {
+ .probe = zx29_uart_probe,
+ //.remove = __devexit_p(zx29_uart_remove),
+ .remove = zx29_uart_remove,
+ .driver = {
+ .name = "zx29_uart",
+ .pm = &zx29_uart_dev_pm_ops,
+ .of_match_table = of_match_ptr(zx29_uart_of_match),
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init zx29_uart_init(void)
+{
+ int rc;
+
+ rc = uart_register_driver(&zx29_uart_driver);
+ if (rc)
+ return rc;
+ rc = platform_driver_register(&zx29_uart_platform_driver);
+ if (rc){
+ uart_unregister_driver(&zx29_uart_driver);
+ return rc;
+ }
+
+ printk(KERN_INFO "zx29 UART driver registered\n");
+
+ return 0;
+}
+
+static void __exit zx29_uart_exit(void)
+{
+#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
+ unregister_console(&zx29_uart_console);
+#endif
+ platform_driver_unregister(&zx29_uart_platform_driver);
+ uart_unregister_driver(&zx29_uart_driver);
+}
+//arch_initcall(zx29_uart_init);
+
+//subsys_initcall(zx29_uart_init);
+module_init(zx29_uart_init);
+module_exit(zx29_uart_exit);
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/include/linux/mfd/zx234290.h b/patch/17.09_19.00/code/new/upstream/linux-5.10/include/linux/mfd/zx234290.h
new file mode 100755
index 0000000..40e71bf
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/include/linux/mfd/zx234290.h
@@ -0,0 +1,1112 @@
+/*
+ * zx234290.h -- ZTE ZX234290
+ *
+ * Copyright 2016 ZTE Corporation.
+ *
+ * Author: yuxiang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_ZX234290_H
+#define __LINUX_MFD_ZX234290_H
+
+#include <linux/mutex.h>
+
+#define zx234290_rails(_name) "zx234290_"#_name
+
+#define u8 unsigned char
+
+/* LDOs */
+#define ZX234290_REG_LDO1 0
+#define ZX234290_REG_LDO2 1
+#define ZX234290_REG_LDO3 2
+#define ZX234290_REG_LDO4 3
+#define ZX234290_REG_LDO5 4
+#define ZX234290_REG_LDO6 5
+#define ZX234290_REG_LDO7 6
+#define ZX234290_REG_LDO8 7
+
+#define ZX234290_REG_LDO9 8
+#define ZX234290_REG_LDO10 9
+#define ZX234290_REG_LDO11 10
+
+/* DCDC's */
+#define ZX234290_REG_DCDC0 11
+#define ZX234290_REG_DCDC1 12
+#define ZX234290_REG_DCDC2 13
+#define ZX234290_REG_DCDC3 14
+#define ZX234290_REG_DCDC4 15
+
+/* ZX regulator type list */
+#ifndef ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_INT_LDO_FAUL 0
+#define ZX234290_INT_BUCK_FAUL 1
+#endif
+
+#define ZX234290_INT_EOADC 2 /* xxxx x100 */
+#define ZX234290_INT_PWRON_SHORT 3
+#define ZX234290_INT_PWRON_LONG 4
+#define ZX234290_INT_PWRON 5
+
+#define ZX234290_INT_RTC_ALRM 8
+#define ZX234290_INT_BATT_DET 10
+#define ZX234290_INT_RTC_MIN 11
+#define ZX234290_INT_RTC_HOUR 12
+
+#define ZX234290_NUM_IRQ 13
+
+#ifdef ZX234290_PWR_FAUL_PROCESS
+int zx234290_register_client(struct notifier_block *nb);
+int zx234290_unregister_client(struct notifier_block *nb);
+int zx234290_notifier_call_chain(unsigned long val, void *v);
+#endif
+
+#if 0
+/* External controls requests */
+enum zx234290_ext_control {
+ PWR_REQ_INPUT_NONE = 0x00000000,
+ PWR_REQ_INPUT_PREQ1 = 0x00000001,
+ PWR_REQ_INPUT_PREQ2 = 0x00000002,
+ PWR_REQ_INPUT_PREQ3 = 0x00000004,
+ PWR_OFF_ON_SLEEP = 0x00000008,
+ PWR_ON_ON_SLEEP = 0x00000010,
+};
+#endif
+
+#if 0
+typedef enum
+{
+ RESET_TO_NORMAL, /*reset to idle*/
+ RESET_TO_CHARGER, /*reset to charger*/
+ RESET_TO_ALRAM, /*reset to alarm*/
+ RESET_TO_EXCEPTRESET,
+ MAX_RESET_TYPE,
+} T_ZDrvSys_RESET_TYPE;
+#endif
+
+typedef enum _T_ZDrvPmic_Enable{
+ PM_DISABLE = 0,
+ PM_ENABLE,
+ PM_ENABLE_NOT_SUPPORT = -100,
+ PM_ENABLE_MAX_STATUS = -255
+} T_ZDrvPmic_Enable;
+
+typedef enum _T_ZDrvPmic_NrmMode{
+ PM_NRMMODE_AUTO = 0,
+ PM_NRMMODE_PFM,
+ PM_NRMMODE_PWM,
+ PM_NRMMODE_NOT_SUPPORT = -100,
+ PM_NRMMODE_MAX_STATUS = -255
+}T_ZDrvPmic_NrmMode;
+
+typedef enum _T_ZDrvPmic_SlpMode{
+ PM_SLPMODE_AUTO_NORMAL = 0, //auto in dcdc, normal in ldo
+ PM_SLPMODE_ECO_NRMV, //normal voltage
+ PM_SLPMODE_ECO_SLPV, //sleep voltage
+ PM_SLPMODE_OFF, //OFF
+ PM_SLPMODE_NOT_SUPPORT = -100,
+ PM_SLPMODE_MAX_STATUS = -255
+}T_ZDrvPmic_SlpMode;
+
+//consumer
+typedef enum _T_ZDrvPmic_Regulator{
+ VCORE0 = 0,
+ VCORE1,
+ VDDR,
+ VMMC,
+ VSD0,
+ VSD1,
+ VIO_LO,
+ VIO_HI,
+ VUSB_0V9,
+ VUSB_3V3,
+ VPLL_LO,
+ VPLL_HI,
+ VSIM1,
+ VSIM2,
+ VRF_LO,
+ VRF_HI,
+ VRF_SW,
+ VPA,
+ VCTCXO1,
+ VCTCXO2,
+ VSSBUF,
+ VRTC,
+} T_ZDrvPmic_Regulator;
+
+typedef enum _T_ZDrvPmic_Vcore{
+ PM_VOLT_0_6750 = 0,
+ PM_VOLT_0_6875 ,
+ PM_VOLT_0_7000 ,
+ PM_VOLT_0_7125 ,
+ PM_VOLT_0_7250 = 0x04,
+ PM_VOLT_0_7375 ,
+ PM_VOLT_0_7500 ,
+ PM_VOLT_0_7625 ,
+ PM_VOLT_0_7750 = 0x08 ,
+ PM_VOLT_0_7875 ,
+ PM_VOLT_0_8000 ,
+ PM_VOLT_0_8125 ,
+ PM_VOLT_0_8250 = 0x0c,
+ PM_VOLT_0_8375 ,
+ PM_VOLT_0_8500 ,
+ PM_VOLT_0_8625 ,
+ PM_VOLT_0_8750 = 0x10 ,
+ PM_VOLT_0_8875 ,
+ PM_VOLT_0_9000 ,
+ PM_VOLT_0_9125 ,
+ PM_VOLT_0_9250 = 0x14,
+ PM_VOLT_0_9375 ,
+ PM_VOLT_0_9500 ,
+ PM_VOLT_0_9625 ,
+ PM_VOLT_0_9750 = 0x18 ,
+ PM_VOLT_0_9875 ,
+ PM_VOLT_1_0000 ,
+ PM_VOLT_1_0125 ,
+ PM_VOLT_1_0250 = 0x1c,
+ PM_VOLT_1_0375 ,
+ PM_VOLT_1_0500 ,
+ PM_VOLT_1_0625 ,
+ PM_VOLT_1_0750 = 0x20 ,
+ PM_VOLT_1_0875 ,
+ PM_VOLT_1_1000 ,
+ PM_VOLT_1_1125 ,
+ PM_VOLT_1_1250 = 0x24,
+ PM_VOLT_1_1375 ,
+ PM_VOLT_1_1500 ,
+ PM_VOLT_1_1625 ,
+ PM_VOLT_1_1750 = 0x28 ,
+ PM_VOLT_1_1875 ,
+ PM_VOLT_1_2000 ,
+ PM_VOLT_1_2125 ,
+ PM_VOLT_1_2250 = 0x2c,
+ PM_VOLT_1_2375 ,
+ PM_VOLT_1_2500 = 0x2e,
+ PM_VOLT_1_2625 ,
+ PM_VOLT_1_2750 = 0x30 ,
+ PM_VOLT_1_2875 ,
+ PM_VOLT_1_3000 ,
+ PM_VOLT_1_3125 ,
+ PM_VOLT_1_3250 = 0x34,
+ PM_VOLT_1_3375 ,
+ PM_VOLT_1_3500 ,
+ PM_VOLT_1_3625 ,
+ PM_VOLT_1_3750 = 0x38 ,
+ PM_VOLT_1_3875 ,
+ PM_VOLT_1_4000 ,
+ PM_VOLT_1_4125 ,
+ PM_VOLT_1_4250 = 0x3c,
+ PM_VOLT_1_4375 ,
+ PM_VOLT_1_4500 ,
+ PM_VOLT_1_4625 ,
+ PM_VOLT_1_4750 = 0x40 ,
+ PM_VOLT_1_4875 ,
+ PM_VOLT_1_5000 ,
+ PM_VOLT_1_5125 ,
+ PM_VOLT_1_5250 = 0x44,
+ PM_VOLT_1_5375 ,
+ PM_VOLT_1_5500 ,
+ PM_VOLT_1_5625 ,
+ PM_VOLT_1_5750 = 0x48,
+ PM_VOLT_1_5875 ,
+ PM_VOLT_1_6000 ,
+ PM_VOLT_1_6125 ,
+ PM_VOLT_1_6250 = 0x4c,
+ PM_VOLT_1_6375 ,
+ PM_VOLT_1_6500 ,
+ PM_VOLT_1_6625 ,
+ PM_VOLT_1_6750 = 0x50,
+ PM_VOLT_1_6875 ,
+ PM_VOLT_1_7000 ,
+ PM_VOLT_1_7125 ,
+ PM_VOLT_1_7250 = 0x54,
+ PM_VOLT_1_7375 ,
+ PM_VOLT_1_7500 ,
+ PM_VOLT_1_7625 ,
+ PM_VOLT_1_7750 = 0x58,
+ PM_VOLT_1_7875 ,
+ PM_VOLT_1_8000 ,
+ PM_VOLT_1_8125 ,
+ PM_VOLT_1_8250 = 0x5c,
+ PM_VOLT_1_8375 ,
+ PM_VOLT_1_8500 ,
+ PM_VOLT_1_8625 ,
+ PM_VOLT_1_8750 = 0x60 ,
+ PM_VOLT_1_8875 ,
+ PM_VOLT_1_9000 ,
+ PM_VOLT_1_9125 ,
+ PM_VOLT_1_9250 = 0x64,
+ PM_VOLT_1_9375 ,
+ PM_VOLT_1_9500 ,
+ PM_VOLT_1_9625 ,
+ PM_VOLT_1_9750 = 0x68,
+ PM_VOLT_1_9875 ,
+ PM_VOLT_2_0000 ,
+ PM_VOLT_2_0125 ,
+ PM_VOLT_2_0250 = 0x6c,
+ PM_VOLT_2_0375 ,
+ PM_VOLT_2_0500 ,
+ PM_VOLT_2_0625 ,
+ PM_VOLT_2_0750 = 0x70,
+ PM_VOLT_2_0875 ,
+ PM_VOLT_2_1000 ,
+ PM_VOLT_2_1125 ,
+ PM_VOLT_2_1250 = 0x74,
+ PM_VOLT_2_1375 ,
+ PM_VOLT_2_1500 ,
+ PM_VOLT_2_1625 ,
+ PM_VOLT_2_1750 = 0x78 ,
+ PM_VOLT_2_1875 ,
+ PM_VOLT_2_2000 ,
+ PM_VOLT_2_2125 ,
+ PM_VOLT_2_2250 = 0x7c,
+ PM_VOLT_2_2375 ,
+ PM_VOLT_2_2500 ,
+ PM_VOLT_2_2625 ,
+ PM_VOLT_2_2750 = 0x80,
+ PM_VOLT_2_2875 ,
+ PM_VOLT_2_3000 ,
+ PM_VOLT_2_3125 ,
+ PM_VOLT_2_3250 = 0x84,
+ PM_VOLT_2_3375 ,
+ PM_VOLT_2_3500 ,
+ PM_VOLT_2_3625 ,
+ PM_VOLT_2_3750 = 0x88 ,
+ PM_VOLT_2_3875 ,
+ PM_VOLT_2_4000 ,
+ PM_VOLT_2_4125 ,
+ PM_VOLT_2_4250 = 0x8c,
+ PM_VOLT_2_4375 ,
+ PM_VOLT_2_4500 ,
+ PM_VOLT_2_4625 ,
+ PM_VOLT_2_4750 = 0x90,
+ PM_VOLT_2_4875 ,
+ PM_VOLT_2_5000 ,
+ PM_VOLT_2_5125 ,
+ PM_VOLT_2_5250 = 0x94,
+ PM_VOLT_2_5375 ,
+ PM_VOLT_2_5500 ,
+ PM_VOLT_2_5625 ,
+ PM_VOLT_2_5750 = 0x98 ,
+ PM_VOLT_2_5875 ,
+ PM_VOLT_2_6000 ,
+ PM_VOLT_2_6125 ,
+ PM_VOLT_2_6250 = 0x9c,
+ PM_VOLT_2_6375 ,
+ PM_VOLT_2_6500 ,
+ PM_VOLT_2_6625 ,
+ PM_VOLT_2_6750 = 0xa0,
+ PM_VOLT_2_6875 ,
+ PM_VOLT_2_7000 ,
+ PM_VOLT_2_7125 ,
+ PM_VOLT_2_7250 = 0xa4,
+ PM_VOLT_2_7375 ,
+ PM_VOLT_2_7500 ,
+ PM_VOLT_2_7625 ,
+ PM_VOLT_2_7750 = 0xa8,
+ PM_VOLT_2_7875 ,
+ PM_VOLT_2_8000 ,
+ PM_VOLT_2_8125 ,
+ PM_VOLT_2_8250 = 0xac,
+ PM_VOLT_2_8375 ,
+ PM_VOLT_2_8500 ,
+ PM_VOLT_2_8625 ,
+ PM_VOLT_2_8750 = 0xb0,
+ PM_VOLT_2_8875 ,
+ PM_VOLT_2_9000 ,
+ PM_VOLT_2_9125 ,
+ PM_VOLT_2_9250 = 0xb4,
+ PM_VOLT_2_9375 ,
+ PM_VOLT_2_9500 ,
+ PM_VOLT_2_9625 ,
+ PM_VOLT_2_9750 = 0xb8,
+ PM_VOLT_2_9875 ,
+ PM_VOLT_3_0000 ,
+ PM_VOLT_3_0125 ,
+ PM_VOLT_3_0250 = 0xbc,
+ PM_VOLT_3_0375 ,
+ PM_VOLT_3_0500 ,
+ PM_VOLT_3_0625 ,
+ PM_VOLT_3_0750 = 0xc0 ,
+ PM_VOLT_3_0875 ,
+ PM_VOLT_3_1000 ,
+ PM_VOLT_3_1125 ,
+ PM_VOLT_3_1250 = 0xc4,
+ PM_VOLT_3_1375 ,
+ PM_VOLT_3_1500 ,
+ PM_VOLT_3_1625 ,
+ PM_VOLT_3_1750 = 0xc8 ,
+ PM_VOLT_3_1875 ,
+ PM_VOLT_3_2000 ,
+ PM_VOLT_3_2125 ,
+ PM_VOLT_3_2250 = 0xcc,
+ PM_VOLT_3_2375 ,
+ PM_VOLT_3_2500 ,
+ PM_VOLT_3_2625 ,
+ PM_VOLT_3_2750 = 0xd0 ,
+ PM_VOLT_3_2875 ,
+ PM_VOLT_3_3000 ,
+ PM_VOLT_3_3125 ,
+ PM_VOLT_3_3250 = 0xd4,
+ PM_VOLT_3_3375 ,
+ PM_VOLT_3_3500 ,
+ PM_VOLT_3_3625 ,
+ PM_VOLT_3_3750 = 0xd8 ,
+ PM_VOLT_3_3875 ,
+
+ PM_VOLT_NOT_SUPPORT = -100,
+ PM_VOLT_MAX_STATUS = -255,
+ } T_ZDrvPmic_Voltage;
+
+
+
+
+/**
+ * struct zx234290 - zx234290 sub-driver chip access routines
+ */
+
+struct zx234290 {
+ struct device *dev;
+ /* for read/write acces */
+ struct mutex io_mutex;
+
+ /* For device IO interfaces: I2C or SPI */
+ void *control_data;
+
+ int (*read)(struct zx234290 *zx234290, u8 reg, int size, void *dest);
+ int (*write)(struct zx234290 *zx234290, u8 reg, int size, void *src);
+
+ /* Client devices */
+ struct zx234290_regulator *regulator;
+
+ /* GPIO Handling */
+
+ /* IRQ Handling */
+ struct mutex irq_lock;
+ int chip_irq;
+ int irq_base;
+ struct irq_domain * irq_domain;
+ int irq_num;
+ unsigned int irq_mask;
+};
+int zx234290_i2c_read_simple(u8 reg, void *dest);
+int zx234290_i2c_write_simple(u8 reg, void *src);
+int zx234290_i2c_read_simple_PSM(u8 reg, void *dest);
+int zx234290_i2c_write_simple_PSM(u8 reg, void *src);
+
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg);
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val);
+int zx234290_device_init(struct zx234290 *zx234290);
+void zx234290_device_exit(struct zx234290 *zx234290);
+
+
+/*regulator defines*/
+#if 1
+/*
+ * List of registers for ZX234290
+*/
+
+/////////////////////////////////////////////////
+/*slave address 0x12*/
+/////////////////////////////////////////////////
+#define ZX234290_I2C_SLAVE_ADDR0 (0x12)
+
+ /* interrupt and mask */
+#define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */
+#define ZX234290_REG_ADDR_INTB 0x01
+#define ZX234290_REG_ADDR_INTA_MASK 0x02
+#define ZX234290_REG_ADDR_INTB_MASK 0x03
+
+ /* interrupt status */
+#define ZX234290_REG_ADDR_STSA 0x04
+#define ZX234290_REG_ADDR_STSB 0x05
+#define ZX234290_REG_ADDR_STS_STARTUP 0x06
+
+ /* adc & softon select */
+#define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/
+
+ /* bucks normal voltage and sleep voltage */
+#define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/
+#define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D
+
+ /* bucks mode */
+#define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/
+#define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/
+#define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */
+
+ /* ldo normal voltage */
+#define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */
+#define ZX234290_REG_ADDR_LDO34_VOL 0x13
+#define ZX234290_REG_ADDR_LDO56_VOL 0x14
+#define ZX234290_REG_ADDR_LDO78_VOL 0x15
+#define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */
+#define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/
+
+
+#define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */
+
+ /* ldo sleep voltage */
+#define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/
+#define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */
+#define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/
+#define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */
+#define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */
+
+ /* ldo mode */
+#define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/
+#define ZX234290_REG_ADDR_LDO5678_MODE 0x1F
+#define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */
+
+ /* ldo enable */
+#define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */
+#define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/
+
+ /* adc code */
+#define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/
+#define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/
+#define ZX234290_REG_ADDR_ADC1_MSB 0x25
+#define ZX234290_REG_ADDR_ADC1_LSB 0x26
+#define ZX234290_REG_ADDR_ADC2_MSB 0x27
+#define ZX234290_REG_ADDR_ADC2_LSB 0x28
+
+ /* sink control */
+#define ZX234297_REG_ADDR_SINK_CONTROL 0x29
+
+ /* rtc */
+#define ZX234290_REG_ADDR_RTC_CTRL1 0x30
+#define ZX234290_REG_ADDR_RTC_CTRL2 0x31
+
+ /* date and time */
+#define ZX234290_REG_ADDR_SECONDS 0x32
+#define ZX234290_REG_ADDR_MINUTES 0x33
+#define ZX234290_REG_ADDR_HOURS 0x34
+#define ZX234290_REG_ADDR_DAY 0x35
+#define ZX234290_REG_ADDR_WEEK 0x36
+#define ZX234290_REG_ADDR_MONTH 0x37
+#define ZX234290_REG_ADDR_YEAR 0x38
+
+ /* alarm */
+#define ZX234290_REG_ADDR_ALARM_MINUTE 0x39
+#define ZX234290_REG_ADDR_ALARM_HOUR 0x3A
+#define ZX234290_REG_ADDR_ALARM_DAY 0x3B
+#define ZX234290_REG_ADDR_ALARM_WEEK 0x3C
+#define ZX234290_REG_ADDR_ALARM_SECOND 0x3D
+
+#define ZX234290_REG_ADDR_TIMER_CTRL 0x3E
+#define ZX234290_REG_ADDR_TIMER_CNT 0x3F
+
+ /* enable ldo output discharge resistance */
+#define ZX234290_REG_ADDR_EN_DISCH1 0x40
+#define ZX234290_REG_ADDR_EN_DISCH2 0x41
+
+ /* power key control */
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43
+
+#define ZX234290_REG_ADDR_VERSION 0x44
+
+ /*fault status*/
+#define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45
+#define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46
+
+#define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47
+#define ZX234290_REG_ADDR_LDO_INT_MASK 0x48
+
+#define ZX234290_REG_ADDR_USER_RESERVED 0x50
+#define ZX234290_REG_ADDR_GMT_TESTING 0xf1
+
+#define ZX234290_MAX_REGISTER 0x51 //yuxiang ?
+
+/*0x04 status A*/
+#define ZX234290_STATUSA_POWERON_LSH (5)
+#define ZX234290_STATUSA_POWERON_WID (1)
+#define ZX234290_STATUSA_EOCADC_LSH (2)
+#define ZX234290_STATUSA_EOCADC_WID (1)
+
+/* 0x06 STATUS REG -- STARTUP */
+#define ZX234290_SYSPOR_STATUS_PWRON_STARTUP (0x1 << 0) /* PWR ON button */
+#define ZX234290_SYSPOR_STATUS_RTC_ALARM_STARTUP (0x1 << 1)
+#define ZX234290_SYSPOR_STATUS_PSHOLD_STARTUP (0x1 << 2)
+#define ZX234290_SYSPOR_STATUS_PWRONLLP_STARTUP (0x1 << 3)
+
+/* discharger */
+#define ZX234290_DISCHG1_LSB_LSH (0)
+#define ZX234290_DISCHG1_LSB_WID (4)
+
+#define ZX234290_DISCHG1_MSB_LSH (5)
+#define ZX234290_DISCHG1_MSB_WID (2)
+
+#define ZX234290_DISCHG2_LSH (0)
+#define ZX234290_DISCHG2_WID (8)
+
+
+/* BUCK VOLTAGE */
+#define ZX234290_BUCK01_VSEL_LSH (0)
+#define ZX234290_BUCK01_VSEL_WID (6)
+
+/* BUCK SLEEP VOLTAGE */
+#define ZX234290_BUCK01_SLEEP_VSEL_LSH (0)
+#define ZX234290_BUCK01_SLEEP_VSEL_WID (6)
+
+/* BUCKS MODE CTROL */
+#define ZX234290_REGULATOR_MODE_WID (2)
+
+#define ZX234290_BUCK0_SLPMODE_LSH (0)
+#define ZX234290_BUCK0_NRMMODE_LSH (2)
+#define ZX234290_BUCK1_SLPMODE_LSH (4)
+#define ZX234290_BUCK1_NRMMODE_LSH (6) /*[7:6]*/
+#define ZX234290_BUCK2_SLPMODE_LSH (0)
+#define ZX234290_BUCK2_NRMMODE_LSH (2)
+#define ZX234290_BUCK3_SLPMODE_LSH (4)
+#define ZX234290_BUCK3_NRMMODE_LSH (6)
+#define ZX234290_BUCK4_SLPMODE_LSH (0)
+#define ZX234290_BUCK4_NRMMODE_LSH (2)
+
+/* LDO MODE, ONLY SLEEP MODE */
+#define ZX234290_LDO1_SLPMODE_LSH (0)
+#define ZX234290_LDO2_SLPMODE_LSH (2)
+#define ZX234290_LDO3_SLPMODE_LSH (4)
+#define ZX234290_LDO4_SLPMODE_LSH (6)
+#define ZX234290_LDO5_SLPMODE_LSH (0)
+#define ZX234290_LDO6_SLPMODE_LSH (2)
+#define ZX234290_LDO7_SLPMODE_LSH (4)
+#define ZX234290_LDO8_SLPMODE_LSH (6)
+#define ZX234290_LDO9_SLPMODE_LSH (2)
+#define ZX234290_LDO10_SLPMODE_LSH (4)
+//#define ZX234290_LDO11_SLPMODE_LSH (6)
+
+/* LDO VOLTAGE SELECT */
+#define ZX234290_LDO_VSEL_WID (4)
+
+#define ZX234290_LDO1_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_VSEL_LSH (0)
+#define ZX234290_LDO4_VSEL_LSH (4)
+#define ZX234290_LDO5_VSEL_LSH (0)
+#define ZX234290_LDO6_VSEL_LSH (4)
+#define ZX234290_LDO7_VSEL_LSH (0)
+#define ZX234290_LDO8_VSEL_LSH (4)
+#define ZX234290_LDO9_VSEL_LSH (4)
+#define ZX234290_LDO10_VSEL_LSH (0)
+#define ZX234290_LDO11_VSEL_LSH (0) /* [3:0] */
+
+#define ZX234290_VORTC_VSEL_WID (2)
+#define ZX234290_VORTC_VSEL_LSH (4) /* [5][4] */
+#define ZX234290_LDO5_VSEL_WID (2) /* [1][0]*/
+
+
+/* LDO SLEEP VOLTAGE */
+#define ZX234290_BUCK2_VSEL_WID (5)
+
+#define ZX234290_BUCK2_VSEL_LSH (0)
+
+#define ZX234290_LDO1_SLP_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_SLP_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_SLP_VSEL_LSH (0)
+#define ZX234290_LDO7_SLP_VSEL_LSH (0)
+#define ZX234290_LDO8_SLP_VSEL_LSH (0)
+#define ZX234290_LDO11_SLP_VSEL_LSH (0) /* [3:0] */
+
+/* ENABLE 0x21-0x22 */
+#define ZX234290_LDOS_ON_WID (1)
+
+#define ZX234290_LDO1_ON_LSH (0)
+#define ZX234290_LDO2_ON_LSH (1)
+#define ZX234290_LDO3_ON_LSH (2)
+#define ZX234290_LDO4_ON_LSH (3)
+#define ZX234290_LDO5_ON_LSH (4)
+#define ZX234290_LDO6_ON_LSH (5)
+#define ZX234290_LDO7_ON_LSH (6)
+#define ZX234290_LDO8_ON_LSH (7)
+
+#define ZX234290_LDO9_ON_LSH (1)
+#define ZX234297_LDO9_ON_LSH (0)
+#define ZX234290_LDO10_ON_LSH (2)
+#define ZX234297_LDO10_ON_LSH (1)
+#define ZX234290_BUCK1_ON_LSH (4)
+#define ZX234290_BUCK2_ON_LSH (5)
+#define ZX234290_BUCK3_ON_LSH (6)
+#define ZX234290_BUCK4_ON_LSH (7)
+
+/* LONG PRESSED TIME */
+#define ZX234290_PWRON_TIME_LSH (0)
+#define ZX234290_PWRON_TIME_WID (2)
+#define ZX234290_PWRON_LONGPRESS_EN_LSH (2)
+#define ZX234290_PWRON_LONGPRESS_EN_WID (1)
+#define ZX234290_PWRON_LLP_TODO_LSH (3) /* LLP long long pressed */
+#define ZX234290_PWRON_LLP_TODO_WID (1)
+
+/* sys ctrol 0x07 */
+#define ZX234290_SINK1_EN_LSH (0)
+#define ZX234290_SINK1_EN_WID (1)
+#define ZX234290_SINK2_EN_LSH (1)
+#define ZX234290_SINK2_EN_WID (1)
+#define ZX234290_ADC1_EN_LSH (4)
+#define ZX234290_ADC1_EN_WID (1)
+#define ZX234290_ADC2_EN_LSH (3)
+#define ZX234290_ADC2_EN_WID (1)
+#define ZX234290_ADC_START_LSH (5)
+#define ZX234290_ADC_START_WID (1)
+#define ZX234290_SOFTON_LSH (7)
+
+/* 0x08 */
+#define ZX234290_SINK2_CURSEL_LSH (0)
+#define ZX234290_SINK2_CURSEL_WID (4)
+/* 0x09 */
+#define ZX234290_SINK1_CURSEL_LSH (0)
+#define ZX234290_SINK1_CURSEL_WID (4)
+
+/* 0x20 */
+#define ZX234297_SINK1_SLP_MODE_LSH (6)
+#define ZX234297_SINK2_SLP_MODE_LSH (7)
+#define ZX234297_SINK_SLP_MODE_WID (1)
+/* 0x22 */
+#define ZX234297_SINK1_ON_LSH (2)
+#define ZX234297_SINK2_ON_LSH (3)
+#define ZX234297_SINK_ON_WID (1)
+/* 0x29 */
+#define ZX234297_SINK1_CURRENT_LSH (0)
+#define ZX234297_SINK2_CURRENT_LSH (4)
+#define ZX234297_SINK_CURRENT_WID (4)
+
+#define ZX234290_LDO_RSTERR_LSH (0)
+#define ZX234290_LDO_RSTERR_WID (1)
+
+#endif /* end of ZX234290 */
+
+#define ZX234290_BITFVAL(var, lsh) ( (var) << (lsh) )
+#define ZX234290_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) )
+#define ZX234290_BITFEXT(var, wid, lsh) ((var & ZX234290_BITFMASK(wid, lsh)) >> (lsh))
+
+/* VBA - BUCK1 6bit */
+typedef enum _T_ZDrvZx234290_VbuckA
+{
+ VBUCKA_0_675 = 0x00,
+ VBUCKA_0_700 = 0x02,
+ VBUCKA_0_750 = 0x06,
+ VBUCKA_0_800 = 0x0a,
+ VBUCKA_0_850 = 0x0e,
+ VBUCKA_0_900 = 0x12,/*default*/
+ VBUCKA_0_950 = 0x16,
+ VBUCKA_1_000 = 0x1a,
+ VBUCKA_1_050 = 0x1e,
+ VBUCKA_1_100 = 0x22,
+ VBUCKA_1_150 = 0x26,
+ VBUCKA_1_200 = 0x2a,
+ VBUCKA_1_250 = 0x2e,
+
+ VBUCKA_MAX
+
+}T_ZDrvZx234290_VbuckA;
+
+/* VBC - BUCK2 */
+typedef enum _T_ZDrvZx234290_VbuckC
+{
+ VBUCKC_0_850 = 0x00,
+ VBUCKC_0_900 = 0x02,
+ VBUCKC_0_950 = 0x04,
+ VBUCKC_1_000 = 0x06,
+ VBUCKC_1_050 = 0x08,
+ VBUCKC_1_100 = 0x0a,
+ VBUCKC_1_150 = 0x0c,
+ VBUCKC_1_200 = 0x0e,/*default*/
+ VBUCKC_1_250 = 0x10,
+ VBUCKC_1_300 = 0x12,
+ VBUCKC_1_350 = 0x14,
+ VBUCKC_1_400 = 0x16,
+ VBUCKC_1_450 = 0x18,
+ VBUCKC_1_500 = 0x1a,
+ VBUCKC_1_550 = 0x1c,
+ VBUCKC_1_600 = 0x1e,
+
+ VBUCKC_MAX
+
+}T_ZDrvZx234290_VbuckC;
+
+/* VLA - ldo1/9/10 */
+typedef enum _T_ZDrvZx234290_VldoA
+{
+ VLDOA_0_725 = 0,
+ VLDOA_0_750 = 1,
+ VLDOA_0_775 = 2,
+ VLDOA_0_800 = 3,
+ VLDOA_0_825 = 4,
+ VLDOA_0_850 = 5,
+ VLDOA_0_875 = 6,
+ VLDOA_0_900 = 7,
+ VLDOA_0_925 = 8,
+ VLDOA_0_950 = 9,
+ VLDOA_0_975 = 10,
+ VLDOA_1_000 = 11,
+ VLDOA_1_025 = 12,
+ VLDOA_1_050 = 13,
+ VLDOA_1_075 = 14,
+ VLDOA_1_100 = 15,
+
+ VLDOA_MAX
+
+}T_ZDrvZx234290_VldoA;
+
+/* VLB - ldo5 2bit */
+typedef enum _T_ZDrvZx234290_VldoB
+{
+ VLDOB_3_300 = 0,
+ VLDOB_3_150 = 1,
+ VLDOB_3_000 = 2,
+ VLDOB_1_800 = 3, /* 11 */
+
+ VLDOB_MAX
+
+}T_ZDrvZx234290_VldoB;
+
+/* VLC - ldo2/ldo3 */
+typedef enum _T_ZDrvZx234290_VldoC
+{
+ VLDOC_0_750 = 0,
+ VLDOC_0_800 = 1,
+ VLDOC_0_850 = 2,
+ VLDOC_0_900 = 3,
+ VLDOC_0_950 = 4,
+ VLDOC_1_000 = 5,
+ VLDOC_1_050 = 6,
+ VLDOC_1_100 = 7,
+ VLDOC_1_200 = 8,
+ VLDOC_1_500 = 9,
+ VLDOC_1_800 = 10,
+ VLDOC_2_000 = 11,
+ VLDOC_2_500 = 12,
+ VLDOC_2_800 = 13,
+ VLDOC_3_000 = 14,
+ VLDOC_3_300 = 15,
+
+ VLDOC_MAX
+
+}T_ZDrvZx234290_VldoC;
+
+/* VLD - ldo4/6/7/8 */
+typedef enum _T_ZDrvZx234290_VldoD
+{
+ VLDOD_1_400 = 0,
+ VLDOD_1_500 = 1,
+ VLDOD_1_600 = 2,
+ VLDOD_1_800 = 3,
+ VLDOD_1_850 = 4,
+ VLDOD_2_000 = 5,
+ VLDOD_2_050 = 6,
+ VLDOD_2_500 = 7,
+ VLDOD_2_550 = 8,
+ VLDOD_2_700 = 9,
+ VLDOD_2_750 = 10,
+ VLDOD_2_800 = 11,
+ VLDOD_2_850 = 12,
+ VLDOD_2_900 = 13,
+ VLDOD_2_950 = 14,
+ VLDOD_3_000 = 15,
+
+ VLDOD_MAX
+
+}T_ZDrvZx234290_VldoD;
+
+/* VORTC 2bit */
+typedef enum _T_ZDrvZx234290_VldoE
+{
+ VLDOE_1_800 = 0,
+ VLDOE_2_500 = 1,
+ VLDOE_3_000 = 2,
+ VLDOE_3_300 = 3, /* 11 */
+
+ VLDOE_MAX
+
+}T_ZDrvZx234290_VldoE;
+
+/* VLF - ldo10 */
+typedef enum _T_ZDrvZx234297_VldoF
+{
+ VLDOF_0_800 = 0,
+ VLDOF_0_850 = 1,
+ VLDOF_0_900 = 2,
+ VLDOF_0_950 = 3,
+
+ VLDOF_1_000 = 4,
+ VLDOF_1_050 = 5,
+ VLDOF_1_100 = 6,
+ VLDOF_1_200 = 7,
+
+ VLDOF_1_300 = 8,
+ VLDOF_1_400 = 9,
+ VLDOF_1_500 = 10,
+ VLDOF_1_800 = 11,
+
+ VLDOF_2_500 = 12,
+ VLDOF_2_800 = 13,
+ VLDOF_3_000 = 14,
+ VLDOF_3_300 = 15,
+
+ VLDOF_MAX
+
+}T_ZDrvZx234297_VldoF;
+
+/* BUCK3/4 EXTERNAL ADJUSTABLE */
+
+typedef enum _T_ZDrvZx234290_LDO_ENABLE
+{
+ LDO_ENABLE_OFF = 0, /* 00 */
+ LDO_ENABLE_ON = 1, /* 10 */
+
+ LDO_AVTICE_MAX
+}T_ZDrvZx234290_LDO_ENABLE;
+
+
+/*
+ ¹ØÓÚ BUCKSµÄģʽ£¬·ÖΪÕý³£Ä£Ê½Óë˯Ãßģʽ£¬ Õý³£Ä£Ê½Ö»¹Ø×¢PFM/PWM£¬²»¹Ø×¢¿ª¹Ø¡£
+ ˯Ãßģʽ¹Ø×¢PFM/PWM/ECO/OFF/NRM£¬Ó¦¸Ã½âÊÍΪ ˯ÃßģʽµÄ״̬²»½ö¹Ø×¢PWM/PFM£¬
+ ¶øÇÒ¹Ø×¢´ò¿ª¹Ø±Õ£¬³ýÁËOFF£¬ÆäËû¶¼ÊÇÔÚ¿ª×ŵÄÇé¿öϵÄģʽ£»¶øĬÈÏ¿ªµÄÇé¿öÔòÊÇ
+ NRMMODE£¬µçѹÓÃ˯Ãßµçѹ£»
+ ¶øLDOSµÄ˯Ãßģʽ£¬Ò»ÑùÓëÕý³£Ä£Ê½²»Ïà¸É¡£ÆäÒ²ÓÐNRM/ECO/OFFÕ⼸ÖÖ״̬
+*/
+
+/* BUCK1/2/3/4 NORMAL MODE */
+typedef enum _T_ZDrvZx234290_BUCK_NRMMODE
+{
+ BUCK_NRM_AUTO_WITH_ECO = 0, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRM_FORCE_PWM = 2, /* 10 FORCE PWM */
+ BUCK_NRM_AUTO_WITHOUT_ECO = 3, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRMMODE_MAX
+}T_ZDrvZx234290_BUCK_NRMMODE;
+
+/* BUCK1 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK1_SLPMODE
+{
+ BUCK1_SLP_AUTO_WITHOUT_ECO = 0, /* 00/11 AUTO PWM/PFM */
+ BUCK1_SLP_AUTO_ECO = 1, /*BUCK1_SLP_AUTO_ECO_VOLT output voltage configred by FBDC1[5:0]*/
+ BUCK1_SLP_AUTO_ECO_SLP = 2, /* output voltage configred by FBDC1_SLP[5:0]*/
+ BUCK1_SLP_SHUTDOWN = 3, /* 11 OFF */
+ BUCK1_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK1_SLPMODE;
+
+/* BUCK2/3/4 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK234_SLPMODE
+{
+ BUCK234_SLP_AUTO_WITHOUT_ECO = 0, /* 00 AUTO PWM/PFM without eco*/
+ BUCK234_SLP_ECO_WITH_ECO = 1, /* 01Óë10¾ùÊÇ ECO */
+ BUCK234_SLP_SHUTDOWN = 3, /* 11 OFF */
+
+ BUCK234_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK234_SLPMODE;
+
+/* LDO1/2/3/7/8/9/10 SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOA_SLPMODE
+{
+ LDOA_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT_SLP = 2, /* VOLDOx_SLP[3:0] */
+ LDOA_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOA_SLPMODE_MAX
+}T_ZDrvZx234290_LDOA_SLPMODE;
+
+/* LDO4/5/6/ SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOB_SLPMODE
+{
+ LDOB_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOB_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOB_SLP_NRM_MODE_VOLT = 2, /* VOLDOx[3:0] */
+ LDOB_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOB_SLPMODE_MAX
+}T_ZDrvZx234290_LDOB_SLPMODE;
+
+typedef enum _T_ZDrvZx234290_LdoDischarger
+{
+ DISCHARGER_LDO_9 = 0,
+ DISCHARGER_LDO_10,
+ DISCHARGER_LDO_X, /*not support*/
+ DISCHARGER_BUCK_4,
+ DISCHARGER_BUCK_3,
+ DISCHARGER_BUCK_2,
+ DISCHARGER_BUCK_1,
+ DISCHARGER_BUCK_X, /*not support*/
+
+ DISCHARGER_LDO_1,
+ DISCHARGER_LDO_2,
+ DISCHARGER_LDO_3,
+ DISCHARGER_LDO_4,
+ DISCHARGER_LDO_5,
+ DISCHARGER_LDO_6,
+ DISCHARGER_LDO_7,
+ DISCHARGER_LDO_8,
+
+ DISCHARGER_MAX
+}T_ZDrvZx234290_LdoDischarger;
+
+typedef enum _T_ZDrvZx234290_DISCHARGER_ENABLE
+{
+ DISCHARGER_DISBALE = 0, /* 00 */
+ DISCHARGER_ENABLE = 1, /* 10 */
+
+ DISCHARGER_ENABLE_MAX
+}T_ZDrvZx234290_DISCHARGER_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LdoList
+{
+ LDOLIST_BUCK_1 = 0,
+ LDOLIST_BUCK_2,
+ LDOLIST_BUCK_3,
+ LDOLIST_BUCK_4,
+ LDOLIST_LDO_1,
+ LDOLIST_LDO_2,
+ LDOLIST_LDO_3,
+
+ LDOLIST_LDO_4,
+ LDOLIST_LDO_5,
+ LDOLIST_LDO_6,//default off
+ LDOLIST_LDO_7,
+ LDOLIST_LDO_8,
+ LDOLIST_LDO_9,//default off
+ LDOLIST_LDO_10,
+ LDOLIST_LDO_RTC,
+
+ LDOLIST_MAX
+}T_ZDrvZx234290_LdoList;
+
+typedef enum _T_ZDrvZx234297_SINK
+{
+ ZX234297_SINK1 = 0, /* 00 */
+ ZX234297_SINK2 = 1, /* 10 */
+
+ ZX234297_SINK_MAX
+}T_ZDrvZx234297_SINK;
+
+typedef enum _T_ZDrvZx234297_SINK_SLPMODE
+{
+ SLPMODE_NORMAL = 0, /* 00 */
+ SLPMODE_SHUTDOWN = 1, /* 10 */
+
+ SLPMODE_MAX
+}T_ZDrvZx234297_SINK_SLPMODE;
+
+typedef enum _T_ZDrvZx234297_SINK_CURRENT
+{
+ SINK_CURRENT_5MA,
+ SINK_CURRENT_10MA,
+ SINK_CURRENT_15MA,
+ SINK_CURRENT_20MA,
+ SINK_CURRENT_30MA,
+ SINK_CURRENT_40MA,
+ SINK_CURRENT_50MA,
+ SINK_CURRENT_60MA,
+ SINK_CURRENT_70MA,
+ SINK_CURRENT_80MA,
+ SINK_CURRENT_90MA,
+ SINK_CURRENT_100MA,
+ SINK_CURRENT_110MA,
+ SINK_CURRENT_120MA,
+
+ SINK_CURRENT_MAX
+}T_ZDrvZx234297_SINK_CURRENT;
+
+
+int zx234290_get_chip_version(void);
+int zx234290_irq_init(struct zx234290 *zx234290);
+
+int zx234290_set_buck1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_buck1_onoff(void);
+int zx234290_set_buck1_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+T_ZDrvZx234290_BUCK_NRMMODE zx234290_get_buck1_active_mode(void);
+int zx234290_set_buck1_voltage(T_ZDrvZx234290_VbuckA vol);
+T_ZDrvZx234290_VbuckA zx234290_get_buck1_voltage(void);
+int zx234290_set_buck1_sleep_mode(T_ZDrvZx234290_BUCK1_SLPMODE status);
+T_ZDrvZx234290_BUCK1_SLPMODE zx234290_get_buck1_sleep_mode(void);
+int zx234290_set_buck1_sleep_voltage(T_ZDrvZx234290_VbuckA vol);
+
+int zx234290_set_buck2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck2_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck2_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+int zx234290_set_buck3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck3_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck3_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+int zx234290_set_buck4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck4_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck4_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+
+int zx234290_set_ldo1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo1_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo1_onoff(void);
+int zx234290_set_ldo1_voltage(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA zx234290_get_ldo1_voltage(void);
+int zx234290_set_ldo1_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo1_sleep_mode(void);
+
+
+int zx234290_set_ldo2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo2_onoff(void);
+int zx234290_set_ldo2_voltage(T_ZDrvZx234290_VldoC vol);
+T_ZDrvZx234290_VldoC zx234290_get_ldo2_voltage(void);
+int zx234290_set_ldo2_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo2_sleep_mode(void);
+
+int zx234290_set_ldo3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo3_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo4_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+
+
+int zx234290_set_ldo5_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo5_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo5_onoff(void);
+int zx234290_set_ldo5_voltage(T_ZDrvZx234290_VldoB vol);
+T_ZDrvZx234290_VldoB zx234290_get_ldo5_voltage(void);
+int zx234290_set_ldo5_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo5_sleep_mode(void);
+
+int zx234290_set_ldo6_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo6_onoff(void);
+int zx234290_set_ldo6_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo6_voltage(void);
+int zx234290_set_ldo6_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo6_sleep_mode(void);
+
+int zx234290_set_ldo7_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo7_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo8_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo8_onoff(void);
+int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo8_voltage(void);
+int zx234290_set_ldo8_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo8_sleep_mode(void);
+int zx234290_set_ldo9_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo9_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo10_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo10_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo10_onoff(void);
+T_ZDrvZx234297_VldoF zx234290_get_ldo10_voltageF(void);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo10_sleep_mode(void);
+int zx234297_set_ldo10_voltageF(T_ZDrvZx234297_VldoF vol);
+
+int zDrvPmic_SetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Onoff_PSM(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_SetSleep_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_GetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable* enable);
+int zDrvPmic_GetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int* voltage);
+
+
+/*adc fun*/
+uint get_battery_voltage(void);
+uint get_adc1_voltage(void);
+uint get_adc2_voltage(void);
+
+
+#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/include/linux/mmc/mmc_func.h b/patch/17.09_19.00/code/new/upstream/linux-5.10/include/linux/mmc/mmc_func.h
new file mode 100755
index 0000000..911c010
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/include/linux/mmc/mmc_func.h
@@ -0,0 +1,37 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2014, ÉîÛÚÊÐÖÐÐËͨѶ΢µç×Ó
+*
+* ÎļþÃû³Æ£º emmc_ramdump.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+
+
+#ifndef LINUX_MMC_MMC_FUNC_H
+#define LINUX_MMC_MMC_FUNC_H
+
+#include <linux/types.h>
+
+int mmc_ramdump_init(void);
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file stored;
+*/
+int mmc_bwrite(u64 start_addr, u32 data_size, void *src_buf);
+
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file will store;
+*/
+
+int mmc_bread(u64 start_addr, u32 data_size, void *dst);
+
+#endif /* LINUX_MMC_MMC_FUNC_H */
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
new file mode 100755
index 0000000..1492b49
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
@@ -0,0 +1,461 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_client_cap.c
+* Îļþ±êʶ: ramdump_client_cap.c
+* ÄÚÈÝÕªÒª: ramdump cap¿Í»§¶ËÒì³£ËÀ»úÏÖ³¡Êý¾Ýµ¼³öʵÏÖ
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2019/10/10 V1.0 Create 00130574 ´´½¨
+*
+*******************************************************************************/
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_arch.h"
+#include <linux/module.h>
+#include <linux/soc/zte/rpmsg.h>
+#include "ram_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* ³£Á¿¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* º¯ÊýÉùÃ÷ *
+*******************************************************************************/
+extern void ramdump_register_callbacks(void);
+extern unsigned char *ramdump_phy_to_vir(unsigned long phy, unsigned long size);
+extern void ramdump_shared_mem_init(void);
+extern void ramdump_data_transfer_to_device(void);
+extern void ramdump_oss_data_trans_init(void);
+extern unsigned char *ramdump_export_flag_base;
+extern void zxic_reset_reason(int reason, const char *cpu, const char *app);
+
+/*******************************************************************************
+* ¾Ö²¿¾²Ì¬±äÁ¿¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_ON_DEFAULT_VAL (1)
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿¶¨Òå *
+*******************************************************************************/
+/*
+ * run time control dump or not, use ( echo "0" > ramdump_on ) to close ramdump
+ */
+int sysctl_ramdump_on_panic = RAMDUMP_ON_DEFAULT_VAL;
+int ramdump_cap_init_flag = -1;
+int ramdump_count = 0;
+int ramdump_server_exp_core = RAMDUMP_FALSE;
+#ifdef CONFIG_RAMDUMP_USER
+unsigned int sysctl_ramdump_on_user = 1;
+#endif
+unsigned int ramdump_export_mode = 0xFF;
+/* Cmm file content */
+unsigned char *ramdump_cap_cmm_buf = NULL;
+/* err log file */
+unsigned char *ramdump_cap_error_log = NULL;
+unsigned int *cap_ddr_len_base = NULL;
+unsigned int sysctl_ramdump_emmc_size = 0x0;
+u64 sysctl_ramdump_emmc_start_addr = 0xFFFF;
+
+static struct ctl_table cfg_ramdump_array[] = {
+#ifdef CONFIG_RAMDUMP_USER
+ {
+ .procname = "sysctl_ramdump_on_user",
+ .data = &sysctl_ramdump_on_user,
+ .maxlen = sizeof(sysctl_ramdump_on_user),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ .extra1 = SYSCTL_ZERO,
+ .extra2 = SYSCTL_ONE,
+ },
+#endif
+ {
+ .procname = "ramdump_start_addr",
+ .data = &sysctl_ramdump_emmc_start_addr,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ },
+ {
+ .procname = "ramdump_emmc_size",
+ .data = &sysctl_ramdump_emmc_size,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_doulongvec_minmax,
+ },
+
+ { }
+};
+
+static struct ctl_table sysctl_ramdump_table[] = {
+ {
+ .procname = "ramdump_ap",
+ .mode = 0555,
+ .child = cfg_ramdump_array,
+ },
+ { }
+};
+
+/*******************************************************************************
+* ¾Ö²¿º¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_handle
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) buf: icp msg addr
+* len: icp msg len
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp msg handle, common entry
+*******************************************************************************/
+static void ramdump_cap_icp_handle(void *buf, unsigned int len)
+{
+ ramdump_msg_t *icp_msg = (ramdump_msg_t *)buf;
+
+ ramdump_server_exp_core = RAMDUMP_TRUE;
+
+ switch(icp_msg->msg_id)
+ {
+ case RAMDUMP_MSG_EXCEPT:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+
+ default:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_create_channel
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ size: icp channel size
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_create_channel(T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
+{
+ return rpmsgCreateChannel(dstCoreID, chID, size);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_regcallback
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ callback:icp callback fun
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_regcallback (T_RpMsg_CoreID coreID, unsigned int chID, T_RpMsg_Callback callback)
+{
+ return rpmsgRegCallBack(coreID, chID, callback);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init_sysctl_table
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ×¢²ásysctlÃüÁÓû§Ì¬Ê¹ÓÃsysctl¿ØÖÆramdump´æ´¢µØÖ·
+*******************************************************************************/
+void ramdump_init_sysctl_table(void)
+{
+ register_sysctl_table(sysctl_ramdump_table);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp init
+*******************************************************************************/
+static int ramdump_cap_icp_init(void)
+{
+ int ret = 0;
+
+ ret = ramdump_cap_icp_create_channel(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ RAMDUMP_CHANNEL_SIZE);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ ret = ramdump_cap_icp_regcallback(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ ramdump_cap_icp_handle);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_notify_server_panic
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for cap notify ramdump server to panic
+*******************************************************************************/
+static int ramdump_notify_server_panic(void)
+{
+ int ret = 0;
+ T_RpMsg_Msg rpMsg = {0};
+ ramdump_msg_t ramdumpMsg = {0};
+
+ ramdumpMsg.msg_id = RAMDUMP_MSG_EXCEPT;
+ ramdumpMsg.cpu_id = CORE_AP;
+
+ rpMsg.coreID = RAMDUMP_SERVER_AP;
+ rpMsg.chID = RAMDUMP_CHANNEL;
+ rpMsg.flag = RPMSG_WRITE_INT | RPMSG_WRITE_IRQLOCK;
+ rpMsg.len = sizeof(ramdump_msg_t);
+ rpMsg.buf = &ramdumpMsg;
+
+ ret = rpmsgWrite(&rpMsg);
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_store_ram_conf
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) mem: addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: unsigend char*: changed addr
+* ÆäËü˵Ã÷: This function is used to store ram conf
+*******************************************************************************/
+static unsigned char *ramdump_cap_store_ram_conf(unsigned char *mem)
+{
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_ddr.bin",
+ (unsigned int)DDR_BASE_CAP_ADDR_PA,
+ (unsigned int)(DDR_BASE_CAP_ADDR_PA + *cap_ddr_len_base - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap.cmm",
+ (unsigned int)RAMDUMP_CAP_CMM_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_CMM_BUF_ADDR + RAMDUMP_CAP_CMM_BUF_LEN_REAL - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_err_log.txt",
+ (unsigned int)RAMDUMP_CAP_LOG_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_LOG_BUF_ADDR + RAMDUMP_CAP_LOG_BUF_LEN - 1));
+ return mem;
+}
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_cmm_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for server to generate cmm scripts
+*******************************************************************************/
+static void ramdump_cap_cmm_create(void)
+{
+ unsigned char *pcmm_buf = ramdump_cap_cmm_buf;
+
+ memset(ramdump_cap_cmm_buf, 0, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+
+ // store the cmm BEGIN
+ pcmm_buf += sprintf(pcmm_buf, "ENTRY &ramdump_dir\n");
+
+ // store procmodes regs
+ pcmm_buf = ramdump_arch_store_modes_regs(pcmm_buf);
+
+ // store ram config
+ pcmm_buf = ramdump_cap_store_ram_conf(pcmm_buf);
+
+ // store memory map control regs
+ pcmm_buf = ramdump_arch_store_mm_regs(pcmm_buf);
+
+ // store end symbol
+ pcmm_buf += sprintf(pcmm_buf, "ENDDO\n");
+
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_trans_cap_error_log_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to create err log file
+*******************************************************************************/
+static void ramdump_cap_error_log_create(void)
+{
+ unsigned char *buf = ramdump_cap_error_log;
+
+ memset(ramdump_cap_error_log, 0, RAMDUMP_CAP_LOG_BUF_LEN);
+ buf += sprintf(buf, "dump at core%d,", smp_processor_id());
+ if (current->mm != NULL)
+ buf += sprintf(buf, "in user,task is: %s\n", current->comm);
+ else
+ buf += sprintf(buf, "in kernel,task is: %s\n", current->comm);
+
+ if (ramdump_server_exp_core)
+ buf += sprintf(buf, "recv dumpinfo from ap\n");
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_ram_conf_table_add
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) ram_name: dump ram name
+ ram_start: dump ram start(virtual addr)
+ ram_size: dump ram size
+ ram_virt: dump ram virt addr
+ ram_flag: dump ram flag(copy/exter/callback)
+ ram_extra: dump ram extra access addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to add dump ram conf into public table
+*******************************************************************************/
+void ramdump_ram_conf_table_add(
+ char *ram_name,
+ unsigned long ram_phy,
+ unsigned long ram_size,
+ unsigned long ram_virt,
+ unsigned long ram_flag,
+ unsigned long ram_extra)
+{
+}
+void ramdump_init_cmm_buf(void)
+{
+ /* Cmm file content */
+ ramdump_cap_cmm_buf = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_CMM_BUF_ADDR, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+ /* err log file */
+ ramdump_cap_error_log = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_LOG_BUF_ADDR, RAMDUMP_CAP_LOG_BUF_LEN);
+ cap_ddr_len_base = (unsigned int *)ramdump_phy_to_vir((unsigned long)IRAM_BASE_ADDR_BOOT_DDR, sizeof(unsigned long));
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: RAMDUMP_SUCCESS or RAMDUMP_FAILED
+* ÆäËü˵Ã÷: This function is used for ramdump init
+*******************************************************************************/
+int __init ramdump_init(void)
+{
+ int ret = 0;
+ ramdump_printf("Ramdump cap init start!!!!!\n");
+
+ if (ramdump_cap_init_flag == RAMDUMP_TRUE)
+ return RAMDUMP_SUCCESS;
+ ramdump_printf("Ramdump cap init rpmsg start!!!!!\n");
+ ret = ramdump_cap_icp_init();
+ if (ret != RAMDUMP_ICP_SUCCESS)
+ return ret;
+
+ ramdump_register_callbacks();
+
+ ramdump_init_cmm_buf();
+
+ ramdump_init_sysctl_table();
+
+ ramdump_shared_mem_init();
+ ramdump_oss_data_trans_init();
+
+ ramdump_printf("Ramdump cap init success!\n");
+ ramdump_cap_init_flag = RAMDUMP_TRUE;
+
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_entry
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump entry
+*******************************************************************************/
+void ramdump_entry (void)
+{
+ unsigned long flags;
+
+ if (ramdump_server_exp_core == RAMDUMP_FALSE)
+ zxic_reset_reason(1, "cap", current->comm); /* not ap ramdump and cap ramdump */
+ if (sysctl_ramdump_on_panic == false)
+ return;
+
+ /*
+ * we need lock the irq, this can`t be interrupt.
+ */
+ ramdump_irq_lock(flags);
+
+ if (!ramdump_cap_init_flag)
+ while(true); /* endless circle */
+
+ if (++ramdump_count > 1)
+ while(true); /* endless circle */
+
+ /*
+ * save all regs first.
+ */
+ ramdump_arch_save_all_regs();
+ // generate error log
+ ramdump_cap_error_log_create();
+
+ //Éú³Écmm½Å±¾µÄµ¼³öÅäÖÃ
+ ramdump_cap_cmm_create();
+
+ /* notify client ramdump */
+ ramdump_notify_server_panic();
+
+ ramdump_arch_clean_caches();
+ ramdump_export_mode = *(unsigned int *)ramdump_export_flag_base;
+
+ if((ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ || (ramdump_export_mode == RAMDUMP_MODE_SPINAND))
+ ramdump_data_transfer_to_device();
+
+ while(true)
+ ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
new file mode 100755
index 0000000..0b0f0dc
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
@@ -0,0 +1,778 @@
+/**
+ * @file oss_ramdump_osa.c
+ * @brief Implementation of Ramdump os adapt
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Qing Wang <wang.qing@sanechips.com.cn>
+ * @ingroup si_ap_oss_ramdump_id
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "ramdump.h"
+#include <linux/lzo.h>
+#include "ramdump_compress.h"
+#ifdef CONFIG_RAMDUMP_EMMC
+#include "ramdump_emmc.h"
+#endif
+#ifdef CONFIG_MTD_SPI_NAND
+#include "ramdump_spinand.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Extern function declarations *
+*******************************************************************************/
+extern unsigned char *ramdump_phy_to_vir(unsigned long phy, unsigned long size);
+extern int dump_printk_text(char *buffer, unsigned long len);
+
+/*******************************************************************************
+* Extern variable declarations *
+*******************************************************************************/
+extern unsigned int ramdump_compress_flag;
+extern unsigned char *ramdump_log_buf;
+extern unsigned int ramdump_export_mode;
+extern unsigned int ramdump_emmc_size;
+extern unsigned int ramdump_spinand_size;
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+/*Ö¸ÁîÖ¡³¤¶È */
+#define RAMDUMP_INTERACTIVE_DATA_LEN 40
+#define RAMDUMP_INTERACTIVE_ARRAY_LEN 10
+
+/* ramdump ºÍ ¹²ÏíÄÚ´æ½»»¥ÃüÁîÔ¼¶¨ */
+/*ͬ²½ÇëÇó*/
+#define RAMDUMP_PC_INTERACTIVE_REQ 1
+/*ͬ²½ÇëÇóÓ¦´ð,´«ÊäramdumpµÄÎļþÊýÄ¿*/
+#define RAMDUMP_TRANS_SERVER_INTERACTIVE_RSP 2
+/*ÇëÇó´«µÝÖ¸¶¨Îļþ±àºÅµÄÎļþÐÅÏ¢*/
+#define RAMDUMP_PC_FILE_INFO_READ_REQ 3
+/*ÇëÇó´«µÝÖ¸¶¨Îļþ±àºÅµÄÎļþÐÅÏ¢µÄÓ¦´ð£¬´«ÊäÎļþÃû¼°´óС*/
+#define RAMDUMP_TRANS_SERVER_FILE_INFO_READ_RSP 4
+/*ÇëÇó¶ÁÈ¡Ö¸¶¨Îļþ±àºÅµÄÎļþÄÚÈÝ*/
+#define RAMDUMP_PC_FILE_DATA_TRANS_REQ 5
+/*ÇëÇó¶ÁÈ¡Ö¸¶¨Îļþ±àºÅµÄÎļþÄÚÈݵÄÓ¦´ð£¬´«ÊäÎļþÄÚÈÝ*/
+#define RAMDUMP_TRANS_SERVER_FILE_DATA_TRANS_RSP 6
+/*´«Êä½áÊø*/
+#define RAMDUMP_PC_FILE_TRANS_DONE_REQ 7
+/*´«Êä½áÊøÓ¦´ð*/
+#define RAMDUMP_TRANS_SERVER_FILE_TRANS_DONE_RSP 8
+
+/* ´íÎóÀàÐÍ */
+/*Ö¸Áî´íÎó*/
+#define RAMDUMP_INTERACTIVE_CMD_ERROR 9
+/*ÇëÇó´«µÝÖ¸¶¨Îļþ±àºÅ´í*/
+#define RAMDUMP_FILE_NUMBER_ERROR 10
+/*ÇëÇó´«µÝÖ¸¶¨ÎļþλÖôóС´í*/
+#define RAMDUMP_FILE_SIZE_ERROR 11
+
+#define RAMDUMP_DELAY_MS_COUNT (2500)
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+/*
+ * struct TRANS WITH AP
+ */
+
+/* trans_server rsp pc, interactive msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int file_num;
+} ramdump_trans_server_interactive_req;
+
+/* trans_server rsp pc, file info msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ char file_name[RAMDUMP_RAMCONF_FILENAME_MAXLEN];
+ unsigned int file_size;
+} ramdump_trans_server_file_info_req;
+
+/* pc req trans_server, file info msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int file_id;
+} ramdump_pc_file_info_rsp;
+
+/* trans_server rsp pc, trans data msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int buf_addr;
+ unsigned int buf_left_size;
+} ramdump_trans_server_data_trans_req;
+
+/* pc req trans_server, trans data msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int file_id; /* Îļþ±àºÅ */
+ unsigned int offset; /* offsetΪÊý¾ÝÆ«ÒÆ */
+ unsigned int length; /* lengthΪÊý¾Ý³¤¶È */
+} ramdump_pc_trans_data_rsp;
+
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+char *ramdump_log_buf_region = NULL;
+unsigned int ramdump_log_buf_len = 0;
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+unsigned char *ramdump_shared_mem_base = NULL;
+unsigned char *ramdump_export_flag_base = NULL;
+int ramdump_file_num = 0;
+ramdump_file_t ramdump_device_fp = {0};
+ramdump_file_t ramdump_spinand_fp = {0};
+ramdump_file_t *g_ramdump_dev_fp;
+unsigned int ramdump_device_file_cnt = 0;
+unsigned char *ramdump_log_buf = NULL; /* ¸´ÓÃramdump´æ´¢µÄ128KB(Æ«ÒÆ16KB) */
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+static inline void ramdump_wait_delay( unsigned long ms)
+{
+ volatile int j = 0;
+ for (j = 0; j < 10000; j++);
+}
+/*******************************************************************************
+ * extern function implementations *
+ ******************************************************************************/
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_data_trans_write
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump to trans dump data to PC
+*******************************************************************************/
+int ramdump_oss_data_trans_write(unsigned char *buffer, unsigned int size)
+{
+ int ret;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ if (size > (RAMDUMP_SHARED_MEM_LEN- roundup(sizeof(ramdump_shmem_t), RAMDUMP_SHMEM_ALIGN_SIZE)));
+ ret = -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 1)){
+ memcpy(msg->buf, buffer, size);
+ msg->size = size;
+ msg->core_flag = 0;
+ msg->rw_flag = 2;
+ ret = size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_data_trans_read
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump to trans dump data to PC
+*******************************************************************************/
+int ramdump_oss_data_trans_read(unsigned char *buffer, unsigned int size)
+{
+ int ret;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ if (size > (RAMDUMP_SHARED_MEM_LEN - roundup(sizeof(ramdump_shmem_t), RAMDUMP_SHMEM_ALIGN_SIZE)))
+ ret = -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+ if (size < msg->size)
+ return -1;
+ memcpy(buffer, msg->buf, msg->size);
+ msg->size = size;
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+ ret = size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_data_trans_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for map ramdump_shared_mem_base
+*******************************************************************************/
+void ramdump_oss_data_trans_init(void)
+{
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ memset(msg, 0, sizeof(ramdump_shmem_t));
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for init fp head
+*******************************************************************************/
+int ramdump_device_init(void)
+{
+ int ret = 0;
+
+ ramdump_lzo_init();
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_init(&ramdump_device_fp);
+#endif
+ g_ramdump_dev_fp = &ramdump_device_fp;
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ret = ramdump_spinand_init(&ramdump_spinand_fp);
+#endif
+ g_ramdump_dev_fp = &ramdump_spinand_fp;
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_close
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for print close msg
+*******************************************************************************/
+void ramdump_device_close(void)
+{
+ g_ramdump_dev_fp->file_num = ramdump_device_file_cnt;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ramdump_emmc_close(&ramdump_device_fp);
+#endif
+ }
+ else if (ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ramdump_spinand_close(&ramdump_spinand_fp);
+#endif
+ }
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_fill_header
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý)
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump file header
+*******************************************************************************/
+int ramdump_fill_header(char *file_name, unsigned int file_size, ramdump_file_t *fp, unsigned int offset)
+{
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, file_name, RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+ fp->file_fp[ramdump_device_file_cnt].offset = offset;
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_file
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write file infomation
+*******************************************************************************/
+int ramdump_device_write_file(ramdump_trans_server_file_info_req *server_to_cap)
+{
+ int ret = -1;
+ unsigned int file_size = 0;
+
+ /* Started by AICoder, pid:wcfb91c2aa35add146d90b5530cd112845133621 */
+ file_size = server_to_cap->file_size;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ if ((ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
+ || ((ramdump_emmc_offset + file_size) > ramdump_emmc_size))
+ return -1;
+
+ ret = ramdump_fill_header(server_to_cap->file_name,
+ server_to_cap->file_size,
+ &ramdump_device_fp,
+ ramdump_emmc_offset);
+#endif
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ if ((ramdump_spinand_offset >= RAMDUMP_SPINAND_LEN)
+ || ((ramdump_spinand_offset + file_size) > ramdump_spinand_size))
+ return -1;
+ /* Ended by AICoder, pid:wcfb91c2aa35add146d90b5530cd112845133621 */
+
+ ret = ramdump_fill_header(server_to_cap->file_name,
+ server_to_cap->file_size,
+ &ramdump_spinand_fp,
+ ramdump_spinand_offset);
+#endif
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_file
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) fp£º Îļþ¾ä±ú
+* (´«³ö²ÎÊý) file_size Îļþ´óС
+* ·µ »Ø Öµ: ³É¹¦·µ»Ø0£¬Ê§°Ü·µ»Ø-1
+* ÆäËü˵Ã÷: This function is used for write file infomation
+*******************************************************************************/
+int ramdump_device_modify_file_size(ssize_t file_size)
+{
+ int ret = -1;
+ ramdump_file_t *fp = g_ramdump_dev_fp;
+
+ if(fp)
+ {
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_file_head
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write file head
+*******************************************************************************/
+int ramdump_device_write_file_head(void)
+{
+ int ret = -1;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_write_file_head(&ramdump_device_fp);
+#endif
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ret = ramdump_spinand_write_file_head(&ramdump_spinand_fp);
+#endif
+ }
+ return ret;
+}
+
+int ramdump_do_write_log_txt(ramdump_file_t *fp)
+{
+ int ret = -1;
+ size_t dst_len = 0;
+ size_t send_len = 0;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+ char *buf = NULL;
+
+ memset(ramdump_log_buf, 0, RAMDUMP_LOG_BUF);
+ ret = dump_printk_text(ramdump_log_buf, RAMDUMP_LOG_BUF);
+ if(ret < 0){
+ printk("ramdump printk log buf failed!!\n");
+ return ret;
+ }
+ if (ramdump_compress_flag == 1){
+ ret = ramdump_lzo_compress(ramdump_log_buf, RAMDUMP_LOG_BUF, msg->buf, &dst_len);
+ buf = msg->buf;
+ }
+ if (ret != LZO_E_OK){
+ dst_len = RAMDUMP_LOG_BUF;
+ buf = ramdump_log_buf;
+ }
+ fp->file_num += 1;
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, "cap_log_buf.txt", RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+
+ if (fp == &ramdump_device_fp)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ fp->file_fp[ramdump_device_file_cnt].size = roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ ret = mmc_bwrite(RAMDUMP_EMMC_ADDR + ramdump_emmc_offset, dst_len, buf);
+ ramdump_emmc_write_file_head(fp);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+#endif
+ }
+ else if (fp == &ramdump_spinand_fp)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ send_len = roundup(dst_len, RAMDUMP_FLASH_ALIGN_SIZE);
+ fp->file_fp[ramdump_device_file_cnt].size = send_len;
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_spinand_offset;
+ ret = write_data(RAMDUMP_SPINAND_ADDR + ramdump_spinand_offset, send_len, buf);
+ ramdump_spinand_offset = ramdump_spinand_offset + send_len;
+#endif
+ }
+ else
+ {
+ printk("ramdump_do_write_logbuf error fp!\n");
+ return -1;
+ }
+ ramdump_device_file_cnt += 1;
+ return ret;
+}
+
+int ramdump_do_write_logbuf(ramdump_file_t *fp)
+{
+ char *buf = NULL;
+ int ret = -1;
+ size_t dst_len = 0;
+ size_t send_len = 0;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ if(!fp)
+ {
+ printk("ramdump_do_write_logbuf error: fp is Null\n");
+ return -1;
+ }
+
+ ramdump_log_buf_region = log_buf_addr_get();
+ ramdump_log_buf_len = log_buf_len_get();
+
+ if (ramdump_compress_flag == 1){
+ ret = ramdump_lzo_compress(ramdump_log_buf_region, ramdump_log_buf_len, msg->buf, &dst_len);
+ buf = msg->buf;
+ }
+ if (ret != LZO_E_OK){
+ dst_len = ramdump_log_buf_len;
+ buf = ramdump_log_buf_region;
+ }
+
+ fp->file_num += 1;
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, "cap_log_buf.bin", RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+
+ if (fp == &ramdump_device_fp)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ fp->file_fp[ramdump_device_file_cnt].size = roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+ ret = mmc_bwrite(RAMDUMP_EMMC_ADDR + ramdump_emmc_offset, dst_len, buf);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ ramdump_emmc_write_file_head(fp);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+#endif
+ }
+ else if (fp == &ramdump_spinand_fp)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ send_len = roundup(dst_len, RAMDUMP_FLASH_ALIGN_SIZE);
+ fp->file_fp[ramdump_device_file_cnt].size = send_len;
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_spinand_offset;
+ ret = write_data(RAMDUMP_SPINAND_ADDR + ramdump_spinand_offset, send_len, buf);
+ ramdump_spinand_offset = ramdump_spinand_offset + send_len;
+#endif
+ }
+ else
+ {
+ printk("ramdump_do_write_logbuf error fp!\n");
+ return -1;
+ }
+
+ ramdump_device_file_cnt += 1;
+ ramdump_do_write_log_txt(fp);
+
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_logbuf
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write cap logbuf
+*******************************************************************************/
+int ramdump_device_write_logbuf(void)
+{
+ int ret = -1;
+
+ ret = ramdump_do_write_logbuf(g_ramdump_dev_fp);
+ if (ret < 0)
+ ramdump_printf("device memory trans file:cap_log_buf error!!!\n");
+ else
+ ramdump_printf("device memory trans file:cap_log_buf success!!!\n");
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_data
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write data
+*******************************************************************************/
+int ramdump_device_write_data(ramdump_shmem_t *msg, unsigned int size, ssize_t *dstlen)
+{
+ int ret = 0;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_write_data(msg, &ramdump_device_fp, size);
+ if(ret < 0)
+ *dstlen = 0;
+ else
+ *dstlen += roundup(ret, RAMDUMP_EMMC_ALIGN_SIZE);
+#endif
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ret = ramdump_spinand_write_data(msg, &ramdump_spinand_fp, size);
+ if(ret < 0)
+ *dstlen = 0;
+ else
+ *dstlen += ret;
+#endif
+ }
+ else
+ return 0;
+ return ret;
+}
+
+/*******************************************************************************
+ * Global function implementations *
+ ******************************************************************************/
+void ramdump_shared_mem_init(void)
+{
+ ramdump_shared_mem_base = ramdump_phy_to_vir((unsigned long)RAMDUMP_SHARED_MEM_BASE, (unsigned long)RAMDUMP_MEM_LEN);
+ ramdump_export_flag_base = ramdump_phy_to_vir((unsigned long)IRAM_BASE_ADDR_RAMDUMP_MODE, sizeof(unsigned long));
+ ramdump_log_buf = ramdump_shared_mem_base + 0x4000;
+ ramdump_flash_alloc_transbuf();
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_data_transfer_to_device
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump to trans dump data to ap
+*******************************************************************************/
+void ramdump_data_transfer_to_device(void)
+{
+ int data_trans_max;
+ int file_cnt = 0;
+ int file_size = 0;
+ int file_offset = 0;
+ int file_left_size = 0;
+ int file_trans_size = 0;
+ int error_cmd = 0;
+ int ret = 0;
+ ssize_t file_dstlen = 0;
+
+ unsigned int req_buf[RAMDUMP_INTERACTIVE_ARRAY_LEN] = {0};
+ ramdump_trans_server_interactive_req cap_to_server_msg = {0};
+
+ /* interactive begin */
+ if(ramdump_device_init() < 0)
+ return;
+
+ ramdump_device_write_logbuf();
+ data_trans_max = RAMDUMP_SHARED_MEM_LEN - roundup(sizeof(ramdump_shmem_t), RAMDUMP_SHMEM_ALIGN_SIZE) - RAMDUMP_COMPRESS_OUT_LEN;
+ cap_to_server_msg.cmd = RAMDUMP_PC_INTERACTIVE_REQ;
+ ramdump_oss_data_trans_write((unsigned char*)(&cap_to_server_msg), sizeof(cap_to_server_msg));
+
+ for(;;)
+ {
+ ramdump_oss_data_trans_read((unsigned char *)req_buf, RAMDUMP_INTERACTIVE_DATA_LEN);
+ switch (*(unsigned int *)req_buf)
+ {
+ case RAMDUMP_TRANS_SERVER_INTERACTIVE_RSP:
+ {
+ ramdump_pc_file_info_rsp cap_to_server_msg ={0};
+ ramdump_trans_server_interactive_req *server_to_cap_msg = (ramdump_trans_server_interactive_req *)req_buf;
+ /* data from server to cap */
+ ramdump_file_num = server_to_cap_msg->file_num;
+
+ /* data from cap to server */
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_INFO_READ_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+ sizeof(cap_to_server_msg));
+
+ break;
+ }
+ case RAMDUMP_TRANS_SERVER_FILE_INFO_READ_RSP:
+ {
+ ramdump_pc_trans_data_rsp cap_to_server_msg = {0};
+ ramdump_trans_server_file_info_req *server_to_cap_msg = (ramdump_trans_server_file_info_req *)req_buf;
+ /* data from server to cap */
+ /*device memory file create*/
+ if(ramdump_device_write_file(server_to_cap_msg) == -1){
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
+ /* Started by AICoder, pid:ddd3ag3c37x6798145ec08ac1067150b58735197 */
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+ sizeof(cap_to_server_msg));
+ break;
+ /* Ended by AICoder, pid:ddd3ag3c37x6798145ec08ac1067150b58735197 */
+ }
+ file_size = server_to_cap_msg->file_size;
+ file_offset = 0;
+ file_left_size = file_size;
+ /* data from cap to server */
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_DATA_TRANS_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+ cap_to_server_msg.offset = file_offset;
+ if (file_size >= data_trans_max)
+ cap_to_server_msg.length = data_trans_max;
+ else
+ cap_to_server_msg.length = file_size;
+ file_trans_size = cap_to_server_msg.length;
+ file_left_size = file_left_size - cap_to_server_msg.length;
+ file_offset = file_offset + cap_to_server_msg.length;
+
+ printk("device memory trans file:%-30s size %9d, offset %9d!!!\n", server_to_cap_msg->file_name, file_size, ramdump_emmc_offset);
+ /* interactive data trans */
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+ sizeof(cap_to_server_msg));
+
+ break;
+ }
+ case RAMDUMP_TRANS_SERVER_FILE_DATA_TRANS_RSP:
+ {
+ int write_len = 0;
+ ramdump_pc_trans_data_rsp cap_to_server_msg = {0};
+ /* data from server to cap */
+ ramdump_shmem_t *server_to_cap_msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+ server_to_cap_msg->core_flag = 0;
+
+ /*data from cap to emmc*/
+ write_len = ramdump_device_write_data(server_to_cap_msg, file_left_size, &file_dstlen);
+ if(write_len < 0 )
+ {
+ /* Started by AICoder, pid:u5befs8483y615f142ce0bda306d660bed685275 */
+ if(write_len == -RAMDUMP_NO_FREE_SPACE)
+ {
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+ sizeof(cap_to_server_msg));
+ break;
+ }
+ else
+ ramdump_printf("ramdump write emmc data error!\n");
+ /* Ended by AICoder, pid:u5befs8483y615f142ce0bda306d660bed685275 */
+ }
+ /*ÅжÏÊ£Óà´óС*/
+ if (file_left_size == 0)
+ {
+ file_cnt++;
+ if (file_cnt == ramdump_file_num)
+ {
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
+ }
+ else
+ {
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_INFO_READ_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+ }
+ ramdump_device_modify_file_size(file_dstlen);
+ file_dstlen = 0;
+ ramdump_device_file_cnt++;
+ }
+ else
+ {
+ /* data from cap to server */
+ if (file_left_size >= data_trans_max)
+ cap_to_server_msg.length = data_trans_max;
+ else
+ cap_to_server_msg.length = file_left_size;
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_DATA_TRANS_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+ cap_to_server_msg.offset = file_offset;
+ file_left_size = file_left_size - cap_to_server_msg.length;
+ file_offset= file_offset + cap_to_server_msg.length;
+ }
+
+ ramdump_oss_data_trans_write((unsigned char *)(&cap_to_server_msg), sizeof(cap_to_server_msg));
+ continue;
+ }
+ case RAMDUMP_TRANS_SERVER_FILE_TRANS_DONE_RSP:
+ {
+ ramdump_device_close();
+ return;
+ }
+ default:
+ {
+ error_cmd = RAMDUMP_INTERACTIVE_CMD_ERROR;
+ ramdump_printf("ramdump trans emmc error:%d!\n", error_cmd);
+ /* interactive data trans */
+ break;
+ }
+ }
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
new file mode 100755
index 0000000..5054440
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
@@ -0,0 +1,182 @@
+/**
+ * @file oss_ramdump_osa.c
+ * @brief Implementation of Ramdump os adapt
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Qing Wang <wang.qing@sanechips.com.cn>
+ * @ingroup si_ap_oss_ramdump_id
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_emmc.h"
+#include "ram_config.h"
+#include "ramdump_compress.h"
+#include <linux/lzo.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Extern function declarations *
+*******************************************************************************/
+
+/*******************************************************************************
+* Extern variable declarations *
+*******************************************************************************/
+extern unsigned char *ramdump_shared_mem_base;
+extern unsigned char *ramdump_emmc_flag_base;
+extern unsigned int ramdump_compress_flag;
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define RAMDUMP_DELAY_MS_COUNT (2500)
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+unsigned int ramdump_emmc_size = 0;
+volatile unsigned int ramdump_emmc_offset = 0;
+extern unsigned int ramdump_device_file_cnt;
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+static inline void ramdump_wait_delay( unsigned long ms)
+{
+ volatile int j = 0;
+ for (j = 0; j < 10000; j++);
+}
+
+/*******************************************************************************
+ * Local function implementations *
+ ******************************************************************************/
+int ramdump_emmc_init(ramdump_file_t *fp)
+{
+ fp->magic = 0x2A2A2A2A;
+ ramdump_emmc_offset = roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE);
+
+ if(RAMDUMP_TRANS_EMMC_LEN > ramdump_emmc_offset)
+ {
+ ramdump_emmc_size = RAMDUMP_TRANS_EMMC_LEN - ramdump_emmc_offset;
+ }
+ else
+ {
+ printk("[ramdump] emmc start addr is %ld, emmc size= %ld, error: size smaller than ramdump file header, return!\n", sysctl_ramdump_emmc_start_addr, sysctl_ramdump_emmc_size);
+ return -1;
+ }
+
+ if(mmc_ramdump_init()){
+ ramdump_printf("EMMC init failed! No ramdump data trans to emmc!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp)
+{
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+ if (ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
+ return -1;
+
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, file_name, RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+}
+
+int ramdump_emmc_write_file_head(ramdump_file_t *fp)
+{
+ int ret = -1;
+ mmc_bwrite(RAMDUMP_EMMC_ADDR, roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE), fp);
+ return ret;
+}
+
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size)
+{
+ int ret = 0;
+ u64 buffer = RAMDUMP_EMMC_ADDR + ramdump_emmc_offset;
+
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+ /* Started by AICoder, pid:fe298k6b27edc1c14f9e0be2e0451e1abfc5830e */
+ if((ramdump_emmc_size < ramdump_emmc_offset)
+ || (msg->size >= (ramdump_emmc_size - fp->file_fp[ramdump_device_file_cnt].offset)))
+ {
+ printk("[ramdump] No space left in emmc, Emmc_size is %ld,ramdump_emmc_offset is %d!\n", ramdump_emmc_size, ramdump_emmc_offset);
+ return -RAMDUMP_NO_FREE_SPACE;
+ }
+ ret = mmc_bwrite(buffer, msg->size, msg->buf);
+ if(ret < 0)
+ {
+ printk("[ramdump] ramdump_emmc_write_data Error.\n");
+ ramdump_wait_delay(0);
+ continue;
+ }
+ /* Ended by AICoder, pid:fe298k6b27edc1c14f9e0be2e0451e1abfc5830e */
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(msg->size, RAMDUMP_EMMC_ALIGN_SIZE);
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+ ret = msg->size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+int ramdump_emmc_read(char *buffer, ramdump_shmem_t *msg, unsigned int size)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+void ramdump_emmc_close(ramdump_file_t *fp)
+{
+ fp->file_size = ramdump_emmc_offset;
+ ramdump_emmc_write_file_head(fp);
+ ramdump_printf("ramdump trans emmc finished!\n");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
new file mode 100755
index 0000000..6c9817e
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_emmc.h
+* Îļþ±êʶ: ramdump_emmc.h
+* ÄÚÈÝÕªÒª: ramdump emmcÍ·Îļþ
+* ʹÓ÷½·¨: #include "ramdump_emmc.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2016/3/10 V1.0 Create ÕÔ¾ü¿ü ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAMDUMP_EMMC_H
+#define _RAMDUMP_EMMC_H
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include <linux/mmc/mmc_func.h>
+
+/*******************************************************************************
+* Íⲿ±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+extern u64 sysctl_ramdump_emmc_start_addr;
+extern unsigned int sysctl_ramdump_emmc_size;
+extern volatile unsigned int ramdump_emmc_offset;
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_NO_FREE_SPACE (2)
+#define RAMDUMP_EMMC_ADDR (sysctl_ramdump_emmc_start_addr * 512)
+#define RAMDUMP_TRANS_EMMC_LEN (sysctl_ramdump_emmc_size * 512)
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+/**
+ * @brief ramdump_emmc_init .
+ *
+ * @param void.
+ *
+ * @return int.
+ * @retval standard error
+ * @note This function is used for ramdump init
+ */
+int ramdump_emmc_init(ramdump_file_t *fp);
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp);
+int ramdump_emmc_write_file_head(ramdump_file_t *fp);
+int ramdump_emmc_modify_file_size(ramdump_file_t *fp, unsigned int file_size);
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size);
+int ramdump_emmc_write_logbuf(ramdump_file_t *fp);
+void ramdump_emmc_close(ramdump_file_t *fp);
+int ramdump_emmc_write_log_txt(ramdump_file_t *fp);
+
+/*******************************************************************************
+* ÄÚÁªº¯ÊýʵÏÖ *
+*******************************************************************************/
+
+#endif //#ifndef _RAMDUMP_EMMC_H
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/tracker.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/tracker.c
new file mode 100755
index 0000000..792818b
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/kernel/tracker.c
@@ -0,0 +1,493 @@
+/*
+ * tracker.c - System accounting over taskstats interface
+ *
+ * Copyright (C) Jay Lan, <jlan@sgi.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/export.h>
+#include <linux/sched/clock.h>
+#include "ram_config.h"
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define _OS_LINUX 1
+
+#if defined(_OS_TOS)
+# define OS_STATISTIC_IRAM_BASE (IRAM_BASE_ADDR_OS_STATISTIC_PSCPU)
+# define OS_STATISTIC_TIME zDrvTimer_Stamp()
+#elif defined(_OS_LINUX)
+# define OS_STATISTIC_IRAM_BASE g_zxic_trace_apcpu_addr //(IRAM_BASE_ADDR_OS_STATISTIC_APCPU)
+# define OS_STATISTIC_TIME (cpu_clock(0)>>10)
+#else
+# error "unknown os"
+#endif
+
+
+
+#define OS_IRAM_STATISTIC_CNT (5)
+#define OS_IRAM_STATISTIC_NAME_LEN (16)
+#define OS_DDR_STATISTIC_CNT (1000)
+
+#define OS_IRAM_THREAD_SWAPIN (OS_STATISTIC_IRAM_BASE)
+#define OS_IRAM_IRQ_START (OS_IRAM_THREAD_SWAPIN + sizeof(t_os_iram_thread_statistic))
+#define OS_IRAM_IRQ_END (OS_IRAM_IRQ_START + sizeof(t_os_iram_statistic))
+
+#if defined(_OS_TOS)
+#define OS_IRAM_DSR_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_DSR_END (OS_IRAM_DSR_START + sizeof(t_os_iram_statistic))
+#elif defined(_OS_LINUX)
+#define OS_IRAM_SOFTIRQ_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_SOFTIRQ_END (OS_IRAM_SOFTIRQ_START + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_START (OS_IRAM_SOFTIRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_END (OS_IRAM_TIMER_START + sizeof(t_os_iram_statistic))
+#define OS_IRAM_RESET_REASON_START (OS_STATISTIC_IRAM_BASE + 0x800 - sizeof(T_Reset_Reason))
+#endif
+
+#define os_statistic_check() *((volatile unsigned long *)OS_STATISTIC_IRAM_BASE)
+#define os_statistic_enabled() g_os_statistic_enable
+
+/*******************************************************************************
+* Êý¾Ý½á¹¹¶¨Òå *
+*******************************************************************************/
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned char name[OS_IRAM_STATISTIC_NAME_LEN];
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_thread_statistic;
+
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_statistic;
+
+typedef struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_DDR_STATISTIC_CNT];
+}t_os_ddr_statistic;
+
+typedef struct
+{
+ char ramdump_reason[32]; //±ÈÈ磺ramdump_ap_appname
+ char kernel_reboot[32]; //±ÈÈ磺reboot_ap_appname
+} T_Reset_Reason;
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ *
+*******************************************************************************/
+#if defined(_OS_LINUX)
+volatile static char *g_zxic_trace_apcpu_addr;
+#endif
+
+volatile static int g_os_statistic_enable;
+volatile static unsigned int g_os_statistic_cnt;
+
+volatile static t_os_iram_thread_statistic *g_os_iram_swapin_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_iram_statistic *g_os_iram_dsr_start_statistic;
+static t_os_iram_statistic *g_os_iram_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_iram_statistic *g_os_iram_softirq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_softirq_end_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_end_statistic;
+#endif
+
+volatile static t_os_ddr_statistic *g_os_ddr_swapin_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_ddr_statistic *g_os_ddr_dsr_start_statistic;
+static t_os_ddr_statistic *g_os_ddr_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_end_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_end_statistic;
+volatile T_Reset_Reason *g_os_reset_reason;
+#endif
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+void os_statistic_enable(void);
+/*******************************************************************************
+* ¾Ö²¿º¯Êý *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_statistic *iram;
+
+ iram = (t_os_iram_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+ iram->statistics[index].data1 = (unsigned int)data;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: Ï̹߳켣ͳ¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_thread_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_thread_statistic *iram;
+
+ iram = (t_os_iram_thread_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+#if defined(_OS_TOS)
+ strncpy((char *)(iram->statistics[index].name), cyg_thread_get_name((cyg_handle_t)data), OS_IRAM_STATISTIC_NAME_LEN - 1);
+#elif defined(_OS_LINUX)
+ strncpy((char *)(iram->statistics[index].name), ((struct task_struct *)data)->comm, OS_IRAM_STATISTIC_NAME_LEN - 1);
+#else
+# error "unkown os"
+#endif
+ iram->statistics[index].name[OS_IRAM_STATISTIC_NAME_LEN - 1] = 0;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_ddr(void *ddr_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_ddr_statistic *ddr;
+
+ ddr = (t_os_ddr_statistic *)ddr_addr;
+
+ index = ddr->index;
+ if (index >= OS_DDR_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+ ddr->statistics[index].data1 = (unsigned int)data;
+ ddr->statistics[index].data2 = time;
+ index++;
+
+ ddr->index = index;
+ ddr->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_info_update(void)
+{
+ g_os_statistic_cnt++;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¶¨Ê±Æ÷»Øµ÷¹³×Ó
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý)
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static int os_statistic_delayed_work_timer_fn(unsigned long data)
+{
+ int sec = 0;
+ msleep(20000);
+ while(!os_statistic_check())
+ {
+ //³¬¹ý40s£¬Ö±½ÓÍ˳ö
+ if(sec >= 4)
+ return 0;
+ msleep(10000);
+ sec++;
+ }
+ os_statistic_enable();
+ return 0;
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ʹÄܹ켣ͳ¼Æ¹¦ÄÜ
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) address: ¼Ç¼µ½IRAMÖеĵØÖ·
+ size: IRAM¿Õ¼ä´óС
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+void os_statistic_enable(void)
+{
+#if defined(_OS_TOS)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_dsr_start_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_START;
+ g_os_iram_dsr_end_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+#elif defined(_OS_LINUX)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_softirq_start_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_START;
+ g_os_iram_softirq_end_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_END;
+ g_os_iram_timer_start_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_START;
+ g_os_iram_timer_end_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+
+#else
+# error "unkown os"
+#endif
+ if ((unsigned int )g_os_iram_timer_end_statistic - (unsigned int )g_os_iram_swapin_statistic > (unsigned int )IRAM_BASE_LEN_OS_STATISTIC_PSCPU )
+ {
+ BUG();
+ }
+ g_os_statistic_enable = 1;
+}
+EXPORT_SYMBOL(os_statistic_enable);
+
+void zxic_trace_task_switch(struct task_struct *next)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_thread_in_iram(g_os_iram_swapin_statistic, next, time);
+ os_statistic_in_ddr(g_os_ddr_swapin_statistic, next, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_enter(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_start_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_start_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_exit(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_end_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_end_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_enter(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_start_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_start_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_exit(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_end_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_end_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_enter(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_start_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_start_statistic, func, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_exit(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_end_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_end_statistic, func, time);
+ os_statistic_info_update();
+}
+/*
+reason: 1 for ramdump, 2 for reboot
+cpu: ap/cap/rpm/phy
+app: current->comm
+*/
+/* Started by AICoder, pid:pf139dce4f7776c149ec081b508bae14e6084ede */
+void zxic_reset_reason(int reason, const char *cpu, const char *app)
+{
+ char buffer[32];
+
+ memset(buffer, 0, sizeof(buffer));
+ switch (reason)
+ {
+ case 1:
+ snprintf(buffer, 32, "reset_ramdump_%s_%s", cpu, app);
+ memcpy(g_os_reset_reason->ramdump_reason, buffer, sizeof(buffer));
+ break;
+ case 2:
+ snprintf(buffer, 32, "reset_kreboot_%s_%s", cpu, app);
+ memcpy(g_os_reset_reason->kernel_reboot, buffer, sizeof(buffer));
+ break;
+ default:
+ break;
+ }
+}
+/* Ended by AICoder, pid:pf139dce4f7776c149ec081b508bae14e6084ede */
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+int __init zxic_enable_tracer(void)
+{
+ struct timer_list timer;
+ struct task_struct *task;
+
+#ifdef IRAM_BASE_ADDR_VA
+ g_zxic_trace_apcpu_addr = IRAM_BASE_ADDR_OS_STATISTIC_PSCPU;
+#else
+ g_zxic_trace_apcpu_addr = ioremap(IRAM_BASE_ADDR_OS_STATISTIC_PSCPU, IRAM_BASE_LEN_OS_STATISTIC_PSCPU + IRAM_BASE_LEN_OS_STATISTIC_PHYCPU + IRAM_BASE_LEN_OS_STATISTIC_APCPU);
+#endif
+
+ g_os_reset_reason = (T_Reset_Reason *)OS_IRAM_RESET_REASON_START;
+ /*
+ init_timer(&timer);
+ timer.expires = jiffies + 40*HZ;//msecs_to_jiffies(40*1000);//ÑÓ³Ù40Ãë
+ timer.data = 0;
+ timer.function = os_statistic_delayed_work_timer_fn;
+ setup_timer(&timer, os_statistic_delayed_work_timer_fn, 0);
+ add_timer(&timer);
+ */
+ //task = kthread_create(os_statistic_delayed_work_timer_fn, 0, "g_zxic_trace_sync_thread", 0);
+ //wake_up_process(task);
+ os_statistic_enable();
+ return 0x0;
+}
+module_init(zxic_enable_tracer);
+
+
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
new file mode 100755
index 0000000..efdfe9e
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
@@ -0,0 +1,2091 @@
+/*
+ * zx297520v3_es8312.c -- zx29-ak4940 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/ak4940.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+#include "pub_debug_info.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0xac
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+/* Started by AICoder, pid:r53959b7c94916e146e3093b301a356223b009fa */
+static int zx29startup(struct snd_pcm_substream *substream)
+{
+ //int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
+ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
+ return -EINVAL;
+ }
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
+ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
+ return -EINVAL;
+ }
+ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened,);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+}
+/* Ended by AICoder, pid:r53959b7c94916e146e3093b301a356223b009fa */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ak4940_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "ak4940.1-0012",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, voice_platform),
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, dummy),
+
+},
+
+#if 0
+
+ [AUDIO_DL_MEDIA] = {
+ .name = "ak4940",
+ .stream_name = "MultiMedia",
+ .nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940, media_platform),
+ },
+
+ [AUDIO_DL_VOICE] = {
+
+ .name = "voice_call",
+ .stream_name = "voice",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ },
+ [AUDIO_DL_2G_AND_3G_VOICE] = {
+
+ .name = "voice_2g_3g",
+ .stream_name = "voice_2g_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice_2g_3g, ak4940, voice_audio),
+
+ },
+ [AUDIO_DL_VP_LOOP] = {
+
+ .name = "loop_test",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "snd-soc-dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops2,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ }, .stream_name = "loop_voice",
+
+ [AUDIO_DL_3G_VOICE] = {
+
+ .name = "voice_3g", // 3g nb,wb
+ .stream_name = "voice_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, voice_audio),
+
+ }
+#endif
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ak4940_of_match[] = {
+ { .compatible = "zxic,zx29_ak4940", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ak4940_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<15);
+ val |= 0x1<<15;; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+
+ val &= 0xfffffff8;
+ val |= 0x00000001;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ak4940_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_ak4940";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_ak4940",
+ .of_match_table = of_match_ptr(zx29_ak4940_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ak4940");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
new file mode 100755
index 0000000..ff07416
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
@@ -0,0 +1,1396 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-dummycodec ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+#include "pub_debug_info.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+/* Started by AICoder, pid:53525s2951m0dfb1406409962017998611b17cc1 */
+static int zx29startup(struct snd_pcm_substream *substream)
+{
+ //int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
+ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
+ return -EINVAL;
+ }
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
+ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
+ return -EINVAL;
+ }
+ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+ unsigned int armRegBit = 0;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x1;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ return 0;
+}
+/* Ended by AICoder, pid:53525s2951m0dfb1406409962017998611b17cc1 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ //if (ret < 0){
+ // print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ // return ret;
+ // }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ti3100_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0012", "tlv320aic31xx-hifi")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_dummycodec_of_match[] = {
+ { .compatible = "zxic,zx29_dummycodec", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_dummycodec_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+
+
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+ board->name = "zx29_dummycodec";
+ board->dev = &pdev->dev;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_dummycodec_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ //platform_set_drvdata(pdev, board);
+
+
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_dummycodec",
+ .of_match_table = of_match_ptr(zx29_dummycodec_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-dummycodec");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
new file mode 100755
index 0000000..0aaf23f
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
@@ -0,0 +1,1430 @@
+/*
+ * zx29_es83xx.c -- zx29-es83xx ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifdef CONFIG_SND_SOC_ES8311
+
+#include "../codecs/es8311.h"
+#endif
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+#include "pub_debug_info.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+//#define NAU_CLK_ID 0
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+/* System Clock Source */
+enum {
+ CODEC_SCLK_MCLK,
+ CODEC_SCLK_PLL,
+};
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+/* Started by AICoder, pid:i3fd98546erae28145550ba82095535ff4895652 */
+static int zx29startup(struct snd_pcm_substream *substream)
+{
+ //int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
+ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
+ return -EINVAL;
+ }
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
+ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
+ return -EINVAL;
+ }
+ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+}
+/* Ended by AICoder, pid:i3fd98546erae28145550ba82095535ff4895652 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+ static int zx29_hw_params_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret =-EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8311_MCLK_PIN,params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+ static int zx29_hw_params_lp_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret =-EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ static int zx29_hw_params_voice_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret =-EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8311_MCLK_PIN,params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_tdm,
+#else
+ .hw_params = zx29_hw_params,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_lp_tdm,
+#else
+ .hw_params = zx29_hw_params_lp,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_voice_tdm,
+#else
+ .hw_params = zx29_hw_params_voice,
+#endif
+ //.prepare = zx29_prepare2,
+ };
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+ //static struct zx298501_nau8810_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(cpu_tdm, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1412000.tdm")));
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("es8311.1-0018", "ES8311 HiFi")));
+
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("es8374.1-001a", "es8374-hifi")));
+#else
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("es8311.1-0018", "es8311-hifi")));
+
+#endif
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(media_platform_tdm, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1412000.tdm")));
+
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, dummy_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+#endif
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, codec, media_platform),
+#endif
+},
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, dummy),
+
+},
+
+};
+
+
+
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef CONFIG_USE_TOP_TDM
+#else
+ #ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+ #endif
+#endif
+};
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+static const struct of_device_id zx29_codec_of_match[] = {
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+ { .compatible = "zxic,zx29_es8311", .data = &zx29_platform_data },
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+ { .compatible = "zxic,zx29_es8374", .data = &zx29_platform_data },
+#else
+ { .compatible = "zxic,zx29_es8311", .data = &zx29_platform_data },
+
+#endif
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_codec_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+ int ret = 0;
+ printk("%s start \n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: board name(%s)!\n", __func__,info->name);
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+#ifdef CONFIG_USE_TOP_TDM
+ //#if 1 //CONFIG_USE_PIN_I2S0
+ #if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+
+ #elif defined(CONFIG_USE_PIN_I2S1)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+ #endif
+
+#else
+
+ //#if 1 //CONFIG_USE_PIN_I2S0
+ #if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+
+ #elif defined(CONFIG_USE_TOP_I2S1)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+ #endif
+#endif
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+#if defined(CONFIG_USE_TOP_I2S0)
+ dev_info(dev, "%s: top_i2s0 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+
+
+#elif defined(CONFIG_USE_TOP_I2S1)
+ dev_info(dev, "%s: top_i2s1 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s1_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#elif defined(CONFIG_USE_TOP_TDM)
+ dev_info(dev, "%s: top_tdm pinctrl sel!!\n", __func__);
+ s = pinctrl_lookup_state(p, "top_tdm");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "toptdm_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#else
+ dev_info(dev, "%s: default top_i2s pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#endif
+ if(info != NULL){
+
+ info->p = p;
+ info->s = s;
+ info->s_sleep = s_sleep;
+ }
+//yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment start
+ ret = pinctrl_select_state(p, s_sleep);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+
+int zx29_i2s_config_default_pin(void)
+{
+ struct zx29_board_data *info = s_board;
+ int ret;
+
+ if (!info || !info->p || !info->s)
+ return -ENODEV;
+
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ pr_err(" %s select state failure %d!!\n", __func__, ret);
+ }
+
+ return ret;
+}
+
+int zx29_i2s_config_sleep_pin(void)
+{
+ struct zx29_board_data *info = s_board;
+ int ret;
+
+ if (!info || !info->p || !info->s_sleep)
+ return -ENODEV;
+
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ pr_err(" %s select state failure %d!!\n", __func__, ret);
+ }
+
+ return ret;
+}
+//yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment end
+
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+#ifdef CONFIG_USE_TOP_TDM
+#else
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+ }
+#endif
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ id = of_match_device(of_match_ptr(zx29_codec_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+ board->name = "zx29_es8311";
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+ board->name = "zx29_es8374";
+#else
+ board->name = "zx29_es8311";
+
+#endif
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+#ifdef CONFIG_PM
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(&pdev->dev);
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(&pdev->dev);
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start![8311]\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(dev);
+ if((info->p != NULL)&&(info->s_sleep != NULL)){
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl sleep end!\n", __func__);
+ }
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(dev);
+ if((info->p != NULL)&&(info->s != NULL)){
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl active end!\n", __func__);
+ }
+
+
+ return snd_soc_resume(dev);
+
+}
+
+#else
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+
+
+ return snd_soc_resume(dev);
+
+}
+
+
+#endif
+
+struct dev_pm_ops zx29_snd_soc_pm_ops = {
+ .suspend = zx29_snd_soc_suspend,
+ .resume = zx29_snd_soc_resume,
+};
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+ .name = "zx29_es8311",
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+ .name = "zx29_es8374",
+
+#else
+ .name = "zx29_es8311",
+#endif
+ .of_match_table = of_match_ptr(zx29_codec_of_match),
+ .pm = &zx29_snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-es83xx");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
new file mode 100755
index 0000000..7cb0c36
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
@@ -0,0 +1,2062 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/max9867.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+#include "pub_debug_info.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define CODEC_CLK_ID 0
+#define CODEC_SCLK_MCLK_ID 0
+#define CODEC_SCLK_PLL_ID 1
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+/* Started by AICoder, pid:g33a6vccc4k69881474b0948e0153c719773e1fe */
+static int zx29startup(struct snd_pcm_substream *substream)
+{
+ //int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
+ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
+ return -EINVAL;
+ }
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
+ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
+ return -EINVAL;
+ }
+ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened;
+
+ return -EBUSY;
+ //BUG();
+ }
+
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+}
+/* Ended by AICoder, pid:g33a6vccc4k69881474b0948e0153c719773e1fe */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ #if 0
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+ #endif
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(max9867_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("max9867.1-001a", "max9867-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, max9867_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_max9867_of_match[] = {
+ { .compatible = "zxic,zx29_max9867", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_max9867_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p,*p2;
+ struct pinctrl_state *s,*s2;
+ int ret = 0;
+ printk("%s start n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s0 end!\n", __func__);
+ /*
+ p2 = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+ */
+
+ s2 = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ ret = pinctrl_select_state(p, s2);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s1 end!\n", __func__);
+
+
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_max9867_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_max9867";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static void zx29_audio_shutdown(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ;
+}
+static int zx29_audio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_max9867",
+ .of_match_table = of_match_ptr(zx29_max9867_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ .shutdown = zx29_audio_shutdown,
+ .suspend = zx29_audio_suspend,
+ .resume = zx29_audio_resume,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-max9867");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
new file mode 100755
index 0000000..4dc8672
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
@@ -0,0 +1,2375 @@
+/*
+ * zx297520v3_nau8810.c -- zx297520v3-nau8810 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/nau8810.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+#include "pub_debug_info.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define NAU_CLK_ID 0
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+/* Started by AICoder, pid:we8d34d80fbc7981449d0b1590d6b753b789d779 */
+static int zx29startup(struct snd_pcm_substream *substream)
+{
+ //int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
+ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
+ return -EINVAL;
+ }
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
+ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
+ return -EINVAL;
+ }
+ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+}
+/* Ended by AICoder, pid:we8d34d80fbc7981449d0b1590d6b753b789d779 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+ static int zx29_hw_params_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_tdm,
+#else
+ .hw_params = zx29_hw_params,
+#endif
+
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_lp_tdm,
+#else
+ .hw_params = zx29_hw_params_lp,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_voice_tdm,
+#else
+ .hw_params = zx29_hw_params_voice,
+#endif
+
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx29_nau8810",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to nau8810 */
+#define ZX29_CODEC_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_codec_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(cpu_tdm, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1412000.tdm")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(nau8810, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-0012", "nau8810-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(nau8810_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-001a", "nau8810-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+
+ SND_SOC_DAILINK_DEF(media_platform_tdm, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1412000.tdm")));
+
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, dummy_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+#endif
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, nau8810_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, nau8810_codec, media_platform),
+#endif
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_nau8810_of_match[] = {
+ { .compatible = "zxic,zx29_nau8810", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_nau8810_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+ int ret = 0;
+ printk("%s start \n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: board name(%s)!\n", __func__,info->name);
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#elif defined(CONFIG_USE_TOP_I2S1)//defined(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+#if defined(CONFIG_USE_TOP_I2S0)
+ dev_info(dev, "%s: top_i2s0 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+
+
+#elif defined(CONFIG_USE_TOP_I2S1)
+ dev_info(dev, "%s: top_i2s1 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s1_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#elif defined(CONFIG_USE_TOP_TDM)
+ dev_info(dev, "%s: top_tdm pinctrl sel!!\n", __func__);
+ s = pinctrl_lookup_state(p, "top_tdm");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "toptdm_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#else
+ dev_info(dev, "%s: default top_i2s pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#endif
+ if(info != NULL){
+
+ info->p = p;
+ info->s = s;
+ info->s_sleep = s_sleep;
+ }
+
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+/*
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+*/
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_nau8810_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_nau8810";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+
+#ifdef CONFIG_PM
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(&pdev->dev);
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(&pdev->dev);
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(dev);
+ if((info->p != NULL)&&(info->s_sleep != NULL)){
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl sleep end!\n", __func__);
+ }
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(dev);
+ if((info->p != NULL)&&(info->s != NULL)){
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl active end!\n", __func__);
+ }
+
+
+ return snd_soc_resume(dev);
+
+}
+
+#else
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+
+
+ return snd_soc_resume(dev);
+
+}
+
+
+#endif
+
+
+struct dev_pm_ops zx29_snd_soc_pm_ops = {
+ .suspend = zx29_snd_soc_suspend,
+ .resume = zx29_snd_soc_resume,
+ .freeze = snd_soc_suspend,
+ .thaw = snd_soc_resume,
+ .poweroff = snd_soc_poweroff,
+ .restore = snd_soc_resume,
+};
+
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_nau8810",
+ .of_match_table = of_match_ptr(zx29_nau8810_of_match),
+ //.pm = &snd_soc_pm_ops,
+ .pm = &zx29_snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_nau8810_snd_device, &zx29xx_nau8810, sizeof(zx29xx_nau8810));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-nau8810");
diff --git a/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
new file mode 100755
index 0000000..3b9bedf
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
@@ -0,0 +1,2061 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/tlv320aic31xx.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+#include "pub_debug_info.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_TI3100_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_TI3100_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+/* Started by AICoder, pid:cd752b8f85qb5fa14ec60aceb0c11d619783bee6 */
+static int zx29startup(struct snd_pcm_substream *substream)
+{
+ //int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ //struct snd_pcm *pcmC0D4p = snd_lookup_minor_data(20, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+
+ struct snd_pcm *pcmC0D0c = snd_lookup_minor_data(24, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D1c = snd_lookup_minor_data(25, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D2c = snd_lookup_minor_data(26, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ struct snd_pcm *pcmC0D3c = snd_lookup_minor_data(27, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+ //struct snd_pcm *pcmC0D4c = snd_lookup_minor_data(28, SNDRV_DEVICE_TYPE_PCM_CAPTURE);
+
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0p=%p, pcmC0D1p=%p, pcmC0D2p=%p, pcmC0D3p=%p\n", __func__,
+ pcmC0D0p, pcmC0D1p, pcmC0D2p, pcmC0D3p);
+ return -EINVAL;
+ }
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0p.opened=%d, pcmC0D1p.opened=%d, pcmC0D2p.opened=%d, pcmC0D3p.opened=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0p=%d, pcmC0D1p=%d, pcmC0D2p=%d, pcmC0D3p=%d\n",
+ __func__, pcmC0D0p->streams[0].substream_opened, pcmC0D1p->streams[0].substream_opened,
+ pcmC0D2p->streams[0].substream_opened, pcmC0D3p->streams[0].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+ if ((pcmC0D0c == NULL) || (pcmC0D1c == NULL) || (pcmC0D2c == NULL) || (pcmC0D3c == NULL))
+ {
+ print_audio("Alsa Entered func %s, pcmC0D0c=%p, pcmC0D1c=%p, pcmC0D2c=%p, pcmC0D3c=%p\n", __func__,
+ pcmC0D0c, pcmC0D1c, pcmC0D2c, pcmC0D3c);
+ return -EINVAL;
+ }
+ if ((pcmC0D0c->streams[1].substream_opened && pcmC0D1c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D0c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D2c->streams[1].substream_opened) ||
+ (pcmC0D1c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened) ||
+ (pcmC0D2c->streams[1].substream_opened && pcmC0D3c->streams[1].substream_opened))
+ {
+ print_audio("Alsa Entered func %s error busy, pcmC0D0c.opened=%d, pcmC0D1c.opened=%d, pcmC0D2c.opened=%d,pcmC0D3c.opened=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+ sc_debug_info_record(MODULE_ID_CAP_AUDIO, "Alsa %s err, opened value pcmC0D0c=%d, pcmC0D1c=%d, pcmC0D2c=%d, pcmC0D3c=%d\n",
+ __func__, pcmC0D0c->streams[1].substream_opened, pcmC0D1c->streams[1].substream_opened,
+ pcmC0D2c->streams[1].substream_opened, pcmC0D3c->streams[1].substream_opened);
+
+ return -EBUSY;
+ //BUG();
+ }
+
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+}
+/* Ended by AICoder, pid:cd752b8f85qb5fa14ec60aceb0c11d619783bee6 */
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018", "tlv320aic3x-hifi")));
+
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+#else
+
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+
+#endif
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, codec, dummy),
+ SND_SOC_DAILINK_REG(voice_cpu, codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ti3100_of_match[] = {
+ { .compatible = "zxic,zx29_ti3100", .data = &zx29_platform_data },
+ { .compatible = "zxic,zx29_ti3104", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ti3100_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ti3100_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ board->name = "zx29_ti3104";
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ board->name = "zx29_ti3100";
+#else
+ board->name = "zx29_ti3100";
+
+#endif
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ .name = "zx29_ti3104",
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ .name = "zx29_ti3100",
+#else
+ .name = "zx29_ti3100",
+
+#endif
+ .of_match_table = of_match_ptr(zx29_ti3100_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ti3100");
diff --git a/patch/17.09_19.00/code/new/upstream/pub/include/infra/pub_debug_info.h b/patch/17.09_19.00/code/new/upstream/pub/include/infra/pub_debug_info.h
new file mode 100755
index 0000000..1ee2f88
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/pub/include/infra/pub_debug_info.h
@@ -0,0 +1,52 @@
+#ifndef _PUB_DEBUG_INFO_H_
+#define _PUB_DEBUG_INFO_H_
+
+#include <stdarg.h>
+
+#define DEBUG_INFO_DEV_PATH "/dev/debug_info"
+
+/* AP²àºÍCAP²àµÄPS\KERNEL\DRIVER\FS\APP ÒÔSTART~ENDΪÇø¼ä£¬¸÷²¿·ÖÔ¤ÁôÁË100¸öID */
+
+#define MODULE_ID_PS_NAS ("ps_nas")
+#define MODULE_ID_PS_RRC ("ps_rrc")
+#define MODULE_ID_PS_L2 ("ps_l2")
+#define MODULE_ID_PS_UICC ("ps_uicc")
+#define MODULE_ID_AP_USB ("ap_usb")
+#define MODULE_ID_AP_REBOOT ("ap_reboot")
+#define MODULE_ID_AP_TSC ("ap_tsc")
+#define MODULE_ID_AP_PSM ("ap_psm")
+#define MODULE_ID_AP_NAND ("ap_nand")
+#define MODULE_ID_AP_MMC ("ap_mmc")
+#define MODULE_ID_AP_WIFI ("ap_wifi")
+
+
+#define MODULE_ID_CAP_USB ("cap_usb")
+#define MODULE_ID_CAP_TSC ("cap_tsc")
+#define MODULE_ID_CAP_PSM ("cap_psm")
+#define MODULE_ID_CAP_NAND ("cap_nand")
+#define MODULE_ID_CAP_SPI ("cap_spi")
+#define MODULE_ID_CAP_MMC ("cap_mmc")
+#define MODULE_ID_CAP_UART ("cap_uart")
+#define MODULE_ID_CAP_PM ("cap_pm")
+
+
+#define MODULE_ID_AP_JFFS2 ("ap_jffs2")
+#define MODULE_ID_AP_FOTA ("ap_fota")
+#define MODULE_ID_AP_FS_CHECK ("ap_fs_check")
+
+#define MODULE_ID_CAP_FOTA ("cap_fota")
+#define MODULE_ID_CAP_FS_CHECK ("cap_fs_check")
+
+#define MODULE_ID_PS_AUDIO ("ps_audio")
+#define MODULE_ID_AP_AUDIO ("ap_audio")
+#define MODULE_ID_CAP_AUDIO ("cap_audio")
+
+#if defined(_USE_ZXIC_DEBUG_INFO)
+int sc_debug_info_vrecord(char *id, const char *format, va_list args);
+int sc_debug_info_record(char *id, const char *format, ...);
+#else
+static inline int sc_debug_info_vrecord(char *id, const char *format, va_list args) { return 0; }
+static inline int sc_debug_info_record(char *id, const char *format, ...) { return 0; }
+#endif
+
+#endif
\ No newline at end of file
diff --git a/patch/17.09_19.00/code/new/upstream/pub/include/ps_phy/atipsevent.h b/patch/17.09_19.00/code/new/upstream/pub/include/ps_phy/atipsevent.h
new file mode 100755
index 0000000..adc2b63
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/pub/include/ps_phy/atipsevent.h
@@ -0,0 +1,1681 @@
+/*****************************************************************
+*°æ±¾ËùÓÐ (C)2016ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
+*Ä£¿éÃû:
+*ÎļþÃû:atipsevent.h
+*ʵÏÖ¹¦ÄÜ:ATIÏà¹ØÏûÏ¢ºÅ
+*°æ±¾:V1.0
+*****************************************************************/
+#ifndef ZPS_ATI_PSECENT_DEF_H
+#define ZPS_ATI_PSECENT_DEF_H
+
+/*ÐÒéÕ»×Óϵͳ, ÓÉÓÚºÍSDL½ø³Ì»¥Í¨£¬ÆäʼþºÅ¶¨ÒåΪ16룬¹ÊÐÒéջʼþºÅ½öµÍ16λÓÐЧ£¬²»Ê¹Óøß16λ*/
+#define EVENT_PS_BASE (DWORD)0x0000A000
+#define EVENT_PS_END (DWORD)(EVENT_PS_BASE + 0x00005f3f)
+
+/**************************************************PS msg range start (5530)********************************************************/
+/*UICC¶ÔÍâÏûÏ¢·¶Î§(200)*/
+#define AP_UICC_EVENT_BASE (DWORD)EVENT_PS_BASE
+#define AP_UICC_RSP_EVENT (DWORD)(AP_UICC_EVENT_BASE + 100)
+#define AP_UICC_EVENT_END (DWORD)(AP_UICC_RSP_EVENT + 99)
+
+/*MMIA¶ÔÍâÏûÏ¢·¶Î§(1625)*/
+#define AP_MMIA_EVENT_BASE (DWORD)(AP_UICC_EVENT_END + 1)
+
+#define AP_MMIA_EVENT_MM_BASE (DWORD)AP_MMIA_EVENT_BASE
+#define AP_MMIA_MM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_MM_BASE + 100)
+#define AP_MMIA_EVENT_MM_END (DWORD)(AP_MMIA_MM_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_CC_BASE (DWORD)(AP_MMIA_EVENT_MM_END + 1)
+#define AP_MMIA_CC_RSP_EVENT (DWORD)(AP_MMIA_EVENT_CC_BASE + 100)
+#define AP_MMIA_EVENT_CC_END (DWORD)(AP_MMIA_CC_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_SMS_BASE (DWORD)(AP_MMIA_EVENT_CC_END + 1)
+#define AP_MMIA_SMS_RSP_EVENT (DWORD)(AP_MMIA_EVENT_SMS_BASE + 100)
+#define AP_MMIA_EVENT_SMS_END (DWORD)(AP_MMIA_SMS_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_SS_BASE (DWORD)(AP_MMIA_EVENT_SMS_END + 1)
+#define AP_MMIA_SS_RSP_EVENT (DWORD)(AP_MMIA_EVENT_SS_BASE + 50)
+#define AP_MMIA_EVENT_SS_END (DWORD)(AP_MMIA_SS_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_SM_BASE (DWORD)(AP_MMIA_EVENT_SS_END + 1)
+#define AP_MMIA_SM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_SM_BASE + 100)
+#define AP_MMIA_EVENT_SM_END (DWORD)(AP_MMIA_SM_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_ESM_BASE (DWORD)(AP_MMIA_EVENT_SM_END + 1)
+#define AP_MMIA_ESM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_ESM_BASE + 50)
+#define AP_MMIA_EVENT_ESM_END (DWORD)(AP_MMIA_ESM_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_UICC_BASE (DWORD)(AP_MMIA_EVENT_ESM_END + 1)
+#define AP_MMIA_UICC_RSP_EVENT (DWORD)(AP_MMIA_EVENT_UICC_BASE + 100)
+#define AP_MMIA_EVENT_UICC_END (DWORD)(AP_MMIA_UICC_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_USAT_BASE (DWORD)(AP_MMIA_EVENT_UICC_END + 1)
+#define AP_MMIA_USAT_RSP_EVENT (DWORD)(AP_MMIA_EVENT_USAT_BASE + 5)
+#define AP_MMIA_EVENT_USAT_END (DWORD)(AP_MMIA_USAT_RSP_EVENT + 4)
+
+#define AP_MMIA_EVENT_CBS_BASE (DWORD)(AP_MMIA_EVENT_USAT_END + 1)
+#define AP_MMIA_CBS_RSP_EVENT (DWORD)(AP_MMIA_EVENT_CBS_BASE + 5)
+#define AP_MMIA_EVENT_CBS_END (DWORD)(AP_MMIA_CBS_RSP_EVENT + 9)
+
+#define AP_MMIA_EVENT_PB_BASE (DWORD)(AP_MMIA_EVENT_CBS_END + 1)
+#define AP_MMIA_PB_RSP_EVENT (DWORD)(AP_MMIA_EVENT_PB_BASE + 100)
+#define AP_MMIA_EVENT_PB_END (DWORD)(AP_MMIA_PB_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_EM_BASE (DWORD)(AP_MMIA_EVENT_PB_END + 1)
+#define AP_MMIA_EM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_EM_BASE + 50)
+#define AP_MMIA_EVENT_EM_END (DWORD)(AP_MMIA_EM_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_OTHER_BASE (DWORD)(AP_MMIA_EVENT_EM_END + 1)
+#define AP_MMIA_OTHER_RSP_EVENT (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 50)
+#define AP_MMIA_EVENT_OTHER_END (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_END (DWORD)AP_MMIA_EVENT_OTHER_END
+
+
+/*ATIÓëPDIÏûÏ¢·¶Î§(20)*/
+#define ATI_PDI_EVENT_BASE (DWORD)(EVENT_PS_BASE + 1850)
+#define ATI_PDI_RSP_EVENT (DWORD)(ATI_PDI_EVENT_BASE + 10)
+#define ATI_PDI_EVENT_END (DWORD)(ATI_PDI_RSP_EVENT + 9)
+
+/*ATIÓëCSDÏûÏ¢·¶Î§(10)*/
+#define ATI_CSD_EVENT_BASE (DWORD)(ATI_PDI_EVENT_END + 1)
+#define ATI_CSD_RSP_EVENT (DWORD)(ATI_CSD_EVENT_BASE + 5)
+#define ATI_CSD_EVENT_END (DWORD)(ATI_CSD_RSP_EVENT + 4)
+
+/*MMIAÓëUMM/CC/SS/SMS/SM/UICC/ESM/ASÏûÏ¢·¶Î§(690)*/
+#define MMIA_NAS_EVENT_BASE (DWORD)(EVENT_PS_BASE + 1880)
+
+#define MMIA_UMM_EVENT_BASE (DWORD)MMIA_NAS_EVENT_BASE
+#define MMIA_UMM_RSP_EVENT (DWORD)(MMIA_UMM_EVENT_BASE + 50)
+#define MMIA_UMM_EVENT_END (DWORD)(MMIA_UMM_RSP_EVENT + 49)
+
+#define MMIA_CC_EVENT_BASE (DWORD)(MMIA_UMM_EVENT_END + 1)
+#define MMIA_CC_RSP_EVENT (DWORD)(MMIA_CC_EVENT_BASE + 50)
+#define MMIA_CC_EVENT_END (DWORD)(MMIA_CC_RSP_EVENT + 49)
+
+#define MMIA_SMS_EVENT_BASE (DWORD)(MMIA_CC_EVENT_END + 1)
+#define MMIA_SMS_RSP_EVENT (DWORD)(MMIA_SMS_EVENT_BASE + 50)
+#define MMIA_SMS_EVENT_END (DWORD)(MMIA_SMS_RSP_EVENT + 49)
+
+#define MMIA_SS_EVENT_BASE (DWORD)(MMIA_SMS_EVENT_END + 1)
+#define MMIA_SS_RSP_EVENT (DWORD)(MMIA_SS_EVENT_BASE + 50)
+#define MMIA_SS_EVENT_END (DWORD)(MMIA_SS_RSP_EVENT + 49)
+
+#define MMIA_SM_EVENT_BASE (DWORD)(MMIA_SS_EVENT_END + 1)
+#define MMIA_SM_RSP_EVENT (DWORD)(MMIA_SM_EVENT_BASE + 50)
+#define MMIA_SM_EVENT_END (DWORD)(MMIA_SM_RSP_EVENT + 49)
+
+#define MMIA_ESM_EVENT_BASE (DWORD)(MMIA_SM_EVENT_END + 1)
+#define MMIA_ESM_RSP_EVENT (DWORD)(MMIA_ESM_EVENT_BASE + 15)
+#define MMIA_ESM_EVENT_END (DWORD)(MMIA_ESM_RSP_EVENT + 14)
+
+#define MMIA_CBS_EVENT_BASE (DWORD)(MMIA_ESM_EVENT_END + 1)
+#define MMIA_CBS_RSP_EVENT (DWORD)(MMIA_CBS_EVENT_BASE + 15)
+#define MMIA_CBS_EVENT_END (DWORD)(MMIA_CBS_RSP_EVENT + 14)
+
+#define MMIA_SNDCP_EVENT_BASE (DWORD)(MMIA_CBS_EVENT_END + 1)
+#define MMIA_SNDCP_RSP_EVENT (DWORD)(MMIA_SNDCP_EVENT_BASE + 15)
+#define MMIA_SNDCP_EVENT_END (DWORD)(MMIA_SNDCP_RSP_EVENT + 14)
+
+#define MMIA_NAS_EVENT_END (DWORD)MMIA_SNDCP_EVENT_END
+
+#define MMIA_AS_EVENT_BASE (DWORD)(MMIA_NAS_EVENT_END + 1)
+#define MMIA_AS_RSP_EVENT (DWORD)(MMIA_AS_EVENT_BASE + 50)
+#define MMIA_AS_EVENT_END (DWORD)(MMIA_AS_RSP_EVENT + 49)
+
+/*** ÔSIG_CODE.HÖÐÒÆÖ²¹ýÀ´µÄÏûÏ¢(660) ***/
+#define EVENT_PS_GSM_NORMAL_BASE (DWORD)(EVENT_PS_BASE + 4300)
+
+#define LAPDM_EVENT_BASE (DWORD)EVENT_PS_GSM_NORMAL_BASE
+#define LAPDM_EVENT_END (DWORD)(LAPDM_EVENT_BASE + 19)
+
+#define GRR_EVENT_BASE (DWORD)(LAPDM_EVENT_END + 1)
+#define GRR_EVENT_END (DWORD)(GRR_EVENT_BASE + 199)
+
+#define GMAC_EVENT_BASE (DWORD)(GRR_EVENT_END + 1)
+#define GMAC_EVENT_END (DWORD)(GMAC_EVENT_BASE + 69)
+
+#define GRLC_EVENT_BASE (DWORD)(GMAC_EVENT_END + 1)
+#define GRLC_EVENT_END (DWORD)(GRLC_EVENT_BASE + 69)
+
+#define GLLC_EVENT_BASE (DWORD)(GRLC_EVENT_END + 1)
+#define GLLC_EVENT_END (DWORD)(GLLC_EVENT_BASE + 49)
+
+#define SNDCP_EVENT_BASE (DWORD)(GLLC_EVENT_END + 1)
+#define SNDCP_EVENT_END (DWORD)(SNDCP_EVENT_BASE + 49)
+
+#define GRRC_EVENT_BASE (DWORD)(SNDCP_EVENT_END + 1)
+#define GRRC_EVENT_END (DWORD)(GRRC_EVENT_BASE + 49)
+
+#define GSMA_EVENT_BASE (DWORD)(GRRC_EVENT_END + 1)
+#define GSMA_EVENT_END (DWORD)(GSMA_EVENT_BASE + 149)
+
+#define EVENT_PS_GSM_NORMAL_END (DWORD)GSMA_EVENT_END
+
+/*ATI¶¨Ê±Æ÷ÏûÏ¢·¶Î§*/
+#define TIMER_EVENT_BASE (DWORD)(EVENT_PS_BASE + 5000)
+
+#define MMIA_TIMER_EVENT_BASE (DWORD)TIMER_EVENT_BASE
+#define MMIA_TIMER_EVENT_END (DWORD)(MMIA_TIMER_EVENT_BASE + 19)
+
+/**************************************************TOOLS & ROADTEST msg range start********************************************************/
+/*±ê×¼ÐÅÁîʼþºÅ·¶Î§(100)*/
+#define STANDARD_SIG_EVENT_BASE (DWORD)(EVENT_PS_BASE + 7000)
+#define STANDARD_SIG_EVENT_END (DWORD)(STANDARD_SIG_EVENT_BASE + 99)
+
+/*·²âÈí¼þʼþºÅ·¶Î§(800)*/
+#define PS_ROADTEST_EVENT_BASE (DWORD)(EVENT_PS_BASE + 7100)
+#define PS_ROADTEST_RSP_EVENT (DWORD)(PS_ROADTEST_EVENT_BASE + 200)
+#define PS_ROADTEST_EVENT_END (DWORD)(PS_ROADTEST_RSP_EVENT + 599)
+
+/*LTE BTrunkʼþºÅ·¶Î§*/
+#define EVENT_PS_LTE_BTRUNK_BASE (DWORD)(EVENT_PS_BASE + 15000)
+#define EVENT_PS_LTE_BTRUNK_END (DWORD)(EVENT_PS_BASE + 16383)
+/**************************************************TOOLS & ROADTEST msg range end***********************************************************/
+
+/**************************************************PS test msg range start********************************************************/
+/*ÐÒéÕ»ÄÚ²âÊÔÏûÏ¢·¶Î§(130)*/
+#define PRI_TEST_EVENT_BASE (DWORD)(PS_ROADTEST_EVENT_END + 1)
+#define PRI_TEST_EVENT_END (DWORD)(PRI_TEST_EVENT_BASE + 19)
+
+#define TAF_TEST_EVENT_BASE (DWORD)(PRI_TEST_EVENT_END + 1)
+#define TAF_TEST_EVENT_END (DWORD)(TAF_TEST_EVENT_BASE + 9)
+
+#define TC_EVENT_BASE (DWORD)(TAF_TEST_EVENT_END + 1)
+#define TC_EVENT_END (DWORD)(TC_EVENT_BASE + 29)
+
+#define NCBS_EVENT_BASE (DWORD)(TC_EVENT_END + 1)
+#define NCBS_EVENT_END (DWORD)(NCBS_EVENT_BASE + 19)
+
+#define USIR_TEST_EVENT_BASE (DWORD)(NCBS_EVENT_END + 1)
+#define USIR_TEST_EVENT_END (DWORD)(USIR_TEST_EVENT_BASE + 9)
+
+#define NURLC_EVENT_BASE (DWORD)(USIR_TEST_EVENT_END + 1)
+#define NURLC_EVENT_END (DWORD)(NURLC_EVENT_BASE + 19)
+
+#define NUMAC_EVENT_BASE (DWORD)(NURLC_EVENT_END + 1)
+#define NUMAC_EVENT_END (DWORD)(NUMAC_EVENT_BASE + 9)
+
+#define NPDCP_EVENT_BASE (DWORD)(NUMAC_EVENT_END + 1)
+#define NPDCP_EVENT_END (DWORD)(NPDCP_EVENT_BASE + 9)
+
+/*GSM²âÊÔ½ø³ÌÏûÏ¢·¶Î§(300)*/
+#define EVENT_PS_GSM_SIMU_BASE (DWORD)(NPDCP_EVENT_END + 1)
+#define L1SIMU_EVENT_BASE (DWORD)EVENT_PS_GSM_SIMU_BASE
+#define L1SIMU_EVENT_END (DWORD)(L1SIMU_EVENT_BASE + 49)
+
+#define NLAPDM_EVENT_BASE (DWORD)(L1SIMU_EVENT_END + 1)
+#define NLAPDM_EVENT_END (DWORD)(NLAPDM_EVENT_BASE + 49)
+
+#define NGMAC_EVENT_BASE (DWORD)(NLAPDM_EVENT_END + 1)
+#define NGMAC_EVENT_END (DWORD)(NGMAC_EVENT_BASE + 99)
+
+#define NLLC_EVENT_BASE (DWORD)(NGMAC_EVENT_END + 1)
+#define NLLC_EVENT_END (DWORD)(NLLC_EVENT_BASE + 49)
+
+#define NRLC_EVENT_BASE (DWORD)(NLLC_EVENT_END + 1)
+#define NRLC_EVENT_END (DWORD)(NRLC_EVENT_BASE + 49)
+
+#define EVENT_PS_GSM_SIMU_END (DWORD)NRLC_EVENT_END
+
+/*GSM AS¶ÔµÈ²ãÐÅÁî¸ú×ÙʼþºÅ·¶Î§¶¨Òå(100)*/
+#define SIGTRACE_EVENT_BASE (DWORD)(EVENT_PS_GSM_SIMU_END + 1)
+
+/*L1GÐÅÁî¸ú×ÙʼþºÅ·¶Î§¶¨Òå(50)*/
+#define L1G_ST_EVENT_BASE (DWORD)(SIGTRACE_EVENT_BASE + 100)
+#define L1G_ST_EVENT_END (DWORD)(L1G_ST_EVENT_BASE + 49)
+
+#define SIGTRACE_EVENT_END (DWORD)L1G_ST_EVENT_END
+
+/*GRRº¯Êý¸ú×ÙÏûÏ¢·¶Î§(100)*/
+#define GSM_FUNC_EVENT_BASE (DWORD)(SIGTRACE_EVENT_END + 1)
+#define GRR_FUNC_EVENT_BASE (DWORD)GSM_FUNC_EVENT_BASE
+#define GRR_FUNC_EVENT_END (DWORD)(GRR_FUNC_EVENT_BASE + 99)
+
+/*º¯ÊýÐÅÁî¸ú×ÙÏûÏ¢·¶Î§(60)*/
+#define FUNC_EVENT_BASE (DWORD)(GRR_FUNC_EVENT_END + 1)
+#define URRC_FUNC_EVENT_BASE (DWORD)FUNC_EVENT_BASE
+#define URRC_FUNC_EVENT_END (DWORD)(URRC_FUNC_EVENT_BASE + 49)
+
+#define TAF_FUNC_EVENT_BASE (DWORD)(URRC_FUNC_EVENT_END + 1)
+#define TAF_FUNC_EVENT_END (DWORD)(TAF_FUNC_EVENT_BASE + 9)
+#define FUNC_EVENT_END (DWORD)TAF_FUNC_EVENT_END
+
+/*È«¾Ö±äÁ¿»ñȡʼþºÅ·¶Î§¶¨Òå(150)*/
+#define GVAR_EVENT_BASE (DWORD)(FUNC_EVENT_END + 1)
+#define GVAR_EVENT_END (DWORD)(GVAR_EVENT_BASE + 149)
+/* ========================================================================
+ UICC¶ÔÍâÌṩÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_UICC_INIT_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 0)
+#define AP_UICC_VERIFY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 1)
+#define AP_UICC_READ_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 2)
+#define AP_UICC_UPDATE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 3)
+#define AP_UICC_AUTH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 4)
+#define AP_UICC_PWROFF_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 5)
+#define AP_UICC_PIN_REMAIN_NUM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 6)
+#define AP_UICC_USAT_ENVELOP_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 7)
+#define AP_UICC_USAT_TERMNL_RSP_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 8)
+#define AP_UICC_USAT_TERMNL_PROF_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 9)
+#define AP_UICC_PIN_ENABLE_QUERY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 10)
+#define AP_UICC_PIN_STAT_QUERY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 11)
+#define AP_UICC_PIN_APPL_SET_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 12)
+#define AP_UICC_PIN_APPL_READ_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 13)
+#define AP_UICC_CARD_MODE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 14)
+#define AP_UICC_WRITE_ITEM_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 15)
+#define AP_UICC_UPDATE_ITEM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 16)
+#define AP_UICC_VERIFY_PIN2_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 17)
+#define AP_UICC_ZPUK_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 18)
+#define AP_UICC_INCREASE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 19)
+#define AP_UICC_RESET_ACM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 20)
+#define AP_UICC_UNBLOCK_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 21)
+#define AP_UICC_CHANGE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 22)
+#define AP_UICC_FACILITY_PIN_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 23)
+#define AP_UICC_REFRESH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 24)
+#define AP_UICC_DEACTEND_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 25)
+#define AP_UICC_FILECHANGEEND_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 26)
+#define AP_UICC_TO_READ_CARD_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 27)
+#define AP_UICC_CSIM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 28)
+#define AP_UICC_AP_PWROFF_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 29)
+#define AP_UICC_CCHO_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 30)
+#define AP_UICC_CCHC_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 31)
+#define AP_UICC_CGLA_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 32)
+#define AP_UICC_CRSM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 33)
+#define AP_UICC_MOVECARD_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 34)
+#define AP_UICC_INSERTCARD_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 35)
+#define AP_UICC_GET_INFO_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 36)
+#define AP_UICC_EFSTATUS_QUERY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 37)
+#define AP_UICC_EFSTATUS_MODIFY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 38)
+#define AP_UICC_PREPERSONREC_SEARCH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 39)
+#define AP_UICC_PB_SEARCH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 40)
+#define AP_UICC_READ_TO_PSDEV_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 45)
+#define AP_UICC_GET_REC_NUM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 46)
+#define AP_UICC_AIR_AUTH_RSP_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 47)
+#define AP_UICC_READ_EID_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 48)
+#define AP_UICC_READ_REC_DIRECT_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 50)
+
+#define AP_UICC_INIT_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 0)
+#define AP_UICC_UICCOK_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 1)
+#define AP_UICC_INIT_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 2)
+#define AP_UICC_SLOT_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 3)
+#define AP_UICC_READ_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 4)
+#define AP_UICC_UPDATE_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 5)
+#define AP_UICC_AUTH_RSP_EV (DWORD)(AP_UICC_RSP_EVENT + 6)
+#define AP_UICC_AUTH_FAIL_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 7)
+#define AP_UICC_NOCARD_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 8)
+#define AP_UICC_PIN_REMAIN_NUM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 9)
+#define AP_UICC_USAT_ENVELOP_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 10)
+#define AP_UICC_USAT_COMMON_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 11)
+#define AP_UICC_USAT_PROV_CMD_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 12)
+#define AP_UICC_PIN_ENABLE_QUERY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 13)
+#define AP_UICC_PIN_STAT_QUERY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 14)
+#define AP_UICC_PIN_APPL_SET_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 15)
+#define AP_UICC_PIN_APPL_READ_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 16)
+#define AP_UICC_CARD_MODE_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 17)
+#define AP_UICC_PWROFF_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 18)
+#define AP_UICC_COMMON_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 19)
+#define AP_UICC_UICC_UNSYNC_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 20)
+#define AP_UICC_NO_PROC_NOTIFY_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 21)
+#define AP_UICC_CARD_LOCK_STATUS_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 22)
+#define AP_UICC_PWROFF_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 23)
+#define AP_UICC_UPDATE_ITEM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 24)
+#define AP_UICC_VERIFY_PIN2_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 25)
+#define AP_UICC_INCREASE_ACM_FAIL_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 26)
+#define AP_UICC_FILECHANGE_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 27)
+#define AP_UICC_CSIM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 28)
+#define AP_UICC_ATR_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 29)
+#define AP_UICC_CCHO_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 30)
+#define AP_UICC_CGLA_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 31)
+#define AP_UICC_CRSM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 32)
+#define AP_UICC_USAT_FETCH_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 33)
+#define AP_UICC_GET_INFO_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 34)
+#define AP_UICC_EFSTATUS_QUERY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 35)
+#define AP_UICC_EFSTATUS_MODIFY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 36)
+#define AP_UICC_PREPERSNREC_SRCH_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 37)
+#define AP_UICC_PB_SEARCH_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 38) /* ·ÖÅäÁË50ÌõÏûÏ¢Çø¼ä£¬ÒÑÓÃÁË39¸ö */
+#define AP_UICC_REFRESH_HAPPEN_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 39)
+#define AP_UICC_AIR_AUTH_REQ_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 40)
+#define AP_UICC_READ_EID_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 41)
+#define AP_UICC_CCHC_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 42)
+#define AP_UICC_LOC_STAT_IND (DWORD)(AP_UICC_RSP_EVENT + 43)
+
+/* ========================================================================
+ MMIA¶ÔÍâÌṩÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* ========================================================================
+ AP-MMIA MMÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_CREG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 0)
+#define AP_MMIA_CREG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 1)
+#define AP_MMIA_COPS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 2)
+#define AP_MMIA_COPS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 3)
+#define AP_MMIA_COPS_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 4)
+#define AP_MMIA_CGATT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 5)
+#define AP_MMIA_CGATT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 6)
+#define AP_MMIA_CGREG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 7)
+#define AP_MMIA_CGREG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 8)
+#define AP_MMIA_CFUN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 9)
+#define AP_MMIA_CFUN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 10)
+#define AP_MMIA_CPLS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 11)
+#define AP_MMIA_CPLS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 12)
+#define AP_MMIA_CPOL_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 13)
+#define AP_MMIA_CPOL_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 14)
+#define AP_MMIA_CPOL_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 15)
+#define AP_MMIA_ZMMI_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 16)
+#define AP_MMIA_ZMMI_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 17)
+#define AP_MMIA_MODE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 18)
+#define AP_MMIA_ZATT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 19)
+#define AP_MMIA_ZATT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 20)
+#define AP_MMIA_ZGAAT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 21)
+#define AP_MMIA_ZGAAT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 22)
+#define AP_MMIA_SYSINFO_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 23)
+#define AP_MMIA_ZACT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 24)
+#define AP_MMIA_ZACT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 25)
+#define AP_MMIA_MODE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 26)
+#define AP_MMIA_SYSCONFIG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 27)
+#define AP_MMIA_SYSCONFIG_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 28)
+#define AP_MMIA_CEREG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 29)
+#define AP_MMIA_CEREG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 30)
+#define AP_MMIA_ZCSG_SEL_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 31)
+#define AP_MMIA_ZCSG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 32)
+#define AP_MMIA_ZCSG_LIST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 33)
+#define AP_MMIA_CEMODE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 34)
+#define AP_MMIA_CEMODE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 35)
+#define AP_MMIA_ZEACT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 36)
+#define AP_MMIA_ZEACT_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 37)
+#define AP_MMIA_CVMOD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 38)
+#define AP_MMIA_CVMOD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 39)
+#define AP_MMIA_CS_SRV_RSP_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 40)
+#define AP_MMIA_LTEBGPLMN_TESTREQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 41)
+#define AP_MMIA_SMSOVERIPNET_SETREQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 42)
+#define AP_MMIA_SMSOVERIPNET_QUERYREQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 43)
+#define AP_MMIA_FPLMN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 44)
+#define AP_MMIA_FPLMN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 45)
+#define AP_MMIA_FPLMN_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 46)
+
+#define AP_MMIA_CREG_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 0)
+#define AP_MMIA_CGREG_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 1)
+#define AP_MMIA_ZMMI_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 2)
+#define AP_MMIA_COPS_TEST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 3)
+#define AP_MMIA_CGATT_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 4)
+#define AP_MMIA_CPOL_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 5)
+#define AP_MMIA_ZATT_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 6)
+#define AP_MMIA_MODE_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 7)
+#define AP_MMIA_ZACT_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 8)
+#define AP_MMIA_SYSCONFIG_READ_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 9)
+#define AP_MMIA_CEREG_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 10)
+#define AP_MMIA_ZCSG_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 11)
+#define AP_MMIA_ZCSG_LIST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 12)
+#define AP_MMIA_CEMODE_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 13)
+#define AP_MMIA_CVMOD_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 14)
+#define AP_MMIA_CS_SRV_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 15)
+#define AP_MMIA_LTEBGPLMN_TESTCNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 16)
+#define AP_MMIA_IMSVOPS_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 17)
+#define AP_MMIA_FPLMN_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 18)
+#define AP_MMIA_FPLMN_TEST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 19)
+#define AP_MMIA_EMERBER_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 20)
+#define AP_MMIA_EMERNUM_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 21)
+#define AP_MMIA_PSCFGSTART_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 22)
+#define AP_MMIA_PSCFGEND_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 23)
+#define AP_MMIA_USER_CARD_SEL_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 24)
+#define AP_MMIA_ZCOPS_TEST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 25)
+#define AP_MMIA_TIMEZONE_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 26)
+#define AP_MMIA_ZULRTIND_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 27)
+#define AP_MMIA_ZPSABNORMAL_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 28)
+/* ========================================================================
+ AP-MMIA CCÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_CC_SETUP_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 0)
+#define AP_MMIA_CC_ANSWER_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 1)
+#define AP_MMIA_CC_MODIFY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 2)
+#define AP_MMIA_CC_STATE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 3)
+#define AP_MMIA_CC_DISC_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 4)
+#define AP_MMIA_CC_DTMF_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 5)
+#define AP_MMIA_CC_CHLD_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 6)
+#define AP_MMIA_CC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 7)
+#define AP_MMIA_CC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 8)
+#define AP_MMIA_DS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 9)
+#define AP_MMIA_DS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 10)
+#define AP_MMIA_MOD_TO_MULTMEDIA_RSP_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 11)
+#define AP_MMIA_CC_MTC_RSP_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 12)
+#define AP_MMIA_DSCI_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 13)
+#define AP_MMIA_DSCI_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 14)
+#define AP_MMIA_CAOC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 15)
+#define AP_MMIA_CAOC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 16)
+#define AP_MMIA_CACM_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 17)
+#define AP_MMIA_CAMM_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 18)
+#define AP_MMIA_CPUC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 19)
+#define AP_MMIA_CCWE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 20)
+#define AP_MMIA_CACM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 21)
+#define AP_MMIA_CAMM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 22)
+#define AP_MMIA_CPUC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 23)
+#define AP_MMIA_CCWE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 24)
+#define AP_MMIA_CALL_LINE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 25)
+#define AP_MMIA_CALL_LINE_QRY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 26)
+
+#define AP_MMIA_CC_CBST_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 27)
+#define AP_MMIA_CC_CBST_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 28)
+#define AP_MMIA_CC_CCUG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 29)
+#define AP_MMIA_CC_CCUG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 30)
+#define AP_MMIA_CC_CMOD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 31)
+#define AP_MMIA_CC_CMOD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 32)
+#define AP_MMIA_CC_CR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 33)
+#define AP_MMIA_CC_CR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 34)
+#define AP_MMIA_CC_CRC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 35)
+#define AP_MMIA_CC_CRC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 36)
+#define AP_MMIA_CC_CSNS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 37)
+#define AP_MMIA_CC_CSNS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 38)
+#define AP_MMIA_CC_CSSN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 39)
+#define AP_MMIA_CC_CSSN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 40)
+#define AP_MMIA_CC_FCLASS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 41)
+#define AP_MMIA_CC_FCLASS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 42)
+#define AP_MMIA_SS_CHSN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 43)
+#define AP_MMIA_SS_CHSN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 44)
+#define AP_MMIA_SS_CRLP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 45)
+#define AP_MMIA_SS_CRLP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 46)
+#define AP_MMIA_SS_ETBM_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 47)
+#define AP_MMIA_SS_ETBM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 48)
+
+#define AP_MMIA_CC_SETUP_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 0)
+#define AP_MMIA_CC_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 1)
+#define AP_MMIA_CC_ANSWER_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 2)
+#define AP_MMIA_CC_MODIFY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 3)
+#define AP_MMIA_CC_STATE_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 4)
+#define AP_MMIA_CC_DISC_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 5)
+#define AP_MMIA_DS_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 6)
+#define AP_MMIA_COLP_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 7)
+#define AP_MMIA_CR_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 8)
+#define AP_MMIA_MT_CALL_SS_NOTIFY_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 9)
+#define AP_MMIA_CLIP_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 10)
+#define AP_MMIA_CC_PROC_INFO_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 11)
+#define AP_MMIA_RING_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 12)
+#define AP_MMIA_CRING_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 13)
+#define AP_MMIA_CCWA_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 14)
+#define AP_MMIA_MO_CALL_SS_NOTIFY_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 15)
+#define AP_MMIA_MOD_TO_MULTMEDIA_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 16)
+#define AP_MMIA_CONN_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 17)
+#define AP_MMIA_ORIG_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 18)
+#define AP_MMIA_CONF_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 19)
+#define AP_MMIA_CEND_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 20)
+#define AP_MMIA_CALL_STATE_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 21)
+#define AP_MMIA_DSCI_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 22)
+#define AP_MMIA_CAOC_SET_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 23)
+#define AP_MMIA_CPUC_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 24)
+#define AP_MMIA_CCCM_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 25)
+#define AP_MMIA_CCWV_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 26)
+#define AP_MMIA_REDIALEND_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 27)
+
+/* ========================================================================
+ AP-MMIA SMSÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_SMS_TCMGS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 0)
+#define AP_MMIA_SMS_CMSS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 1)
+#define AP_MMIA_SMS_TCMGW_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 2)
+#define AP_MMIA_SMS_CMGD_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 3)
+#define AP_MMIA_SMS_TCMGC_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 4)
+#define AP_MMIA_SMS_CMMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 5)
+#define AP_MMIA_SMS_CNMI_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 6)
+#define AP_MMIA_SMS_CMGL_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 7)
+#define AP_MMIA_SMS_CMGR_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 8)
+#define AP_MMIA_SMS_TCNMA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 9)
+#define AP_MMIA_SMS_CGSMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 10)
+#define AP_MMIA_SMS_CSMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 11)
+#define AP_MMIA_SMS_CPMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 12)
+#define AP_MMIA_SMS_CMGF_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 13)
+#define AP_MMIA_SMS_CSCA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 14)
+#define AP_MMIA_SMS_TCSMP_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 15)
+#define AP_MMIA_SMS_TCSDH_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 16)
+#define AP_MMIA_SMS_PCMGS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 17)
+#define AP_MMIA_SMS_PCMGW_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 18)
+#define AP_MMIA_SMS_PCMGC_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 19)
+#define AP_MMIA_SMS_PCNMA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 20)
+#define AP_MMIA_SMS_CPMS_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 21)
+#define AP_MMIA_SMS_ZMENA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 22)
+#define AP_MMIA_SMS_QUERY_MODE_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 23)
+#define AP_MMIA_SMS_QUERY_MAX_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 24)
+#define AP_MMIA_SMS_CNMA_QUERY_MODE_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 25)
+
+#define AP_MMIA_SMS_TCMGS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 0)
+#define AP_MMIA_SMS_TCMSS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 1)
+#define AP_MMIA_SMS_CMGW_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 2)
+#define AP_MMIA_SMS_TCMGC_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 3)
+#define AP_MMIA_SMS_STORE_REC_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 4)
+#define AP_MMIA_SMS_TCMT_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 5)
+#define AP_MMIA_SMS_TCDS_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 6)
+#define AP_MMIA_SMS_TDELI_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 7)
+#define AP_MMIA_SMS_TSUB_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 8)
+#define AP_MMIA_SMS_TSTAT_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 9)
+#define AP_MMIA_SMS_TCOM_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 10)
+#define AP_MMIA_SMS_TDELI_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 11)
+#define AP_MMIA_SMS_TSUB_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 12)
+#define AP_MMIA_SMS_TSTAT_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 13)
+#define AP_MMIA_SMS_TCOM_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 14)
+#define AP_MMIA_SMS_CPMS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 15)
+#define AP_MMIA_SMS_PCMGS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 16)
+#define AP_MMIA_SMS_PCMSS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 17)
+#define AP_MMIA_SMS_PCMGC_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 18)
+#define AP_MMIA_SMS_PCMTIND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 19)
+#define AP_MMIA_SMS_PCDSIND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 20)
+#define AP_MMIA_SMS_PCMGL_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 21)
+#define AP_MMIA_SMS_PCMGR_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 22)
+#define AP_MMIA_SMS_CPMS_TEST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 23)
+#define AP_MMIA_SMS_QUERY_MAX_INDEX_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 24)
+#define AP_MMIA_SMS_SAVE_FAILURE_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 25)
+#define AP_MMIA_SMS_ZCMTIND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 26)
+
+/* ========================================================================
+ AP-MMIA SSÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_CLCK_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 0)
+#define AP_MMIA_CPWD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 1)
+#define AP_MMIA_CLIP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 2)
+#define AP_MMIA_CLIP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 3)
+#define AP_MMIA_CLIR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 4)
+#define AP_MMIA_CLIR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 5)
+#define AP_MMIA_COLP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 6)
+#define AP_MMIA_COLP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 7)
+#define AP_MMIA_CCFC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 8)
+#define AP_MMIA_CCWA_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 9)
+#define AP_MMIA_CCWA_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 10)
+#define AP_MMIA_CUSD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 11)
+#define AP_MMIA_CUSD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 12)
+#define AP_MMIA_COLR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 13)
+#define AP_MMIA_CNAP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 14)
+#define AP_MMIA_CNAP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 15)
+
+#define AP_MMIA_CLCK_STATUS_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 0)
+#define AP_MMIA_CLIP_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 1)
+#define AP_MMIA_CLIR_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 2)
+#define AP_MMIA_COLP_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 3)
+#define AP_MMIA_CCFC_STATUS_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 4)
+#define AP_MMIA_CCWA_STATUS_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 5)
+#define AP_MMIA_CCWA_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 6)
+#define AP_MMIA_CUSD_IND_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 7)
+#define AP_MMIA_COLR_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 8)
+#define AP_MMIA_CNAP_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 9)
+#define AP_MMIA_CNAP_IND_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 10)
+
+/* ========================================================================
+ AP-MMIA SMÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_SM_PARAM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 0)
+#define AP_MMIA_SM_PARAM_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 1)
+#define AP_MMIA_SM_PDP_STATUS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 2)
+#define AP_MMIA_SM_ACTIVED_CID_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 3)
+#define AP_MMIA_SM_DEF_CID_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 4)
+#define AP_MMIA_SM_PDP_ADDR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 5)
+#define AP_MMIA_SM_NEG_QOS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 6)
+#define AP_MMIA_SM_NEG_EQOS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 7)
+#define AP_MMIA_SM_ACT_DEACT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 8)
+#define AP_MMIA_SM_MOD_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 9)
+#define AP_MMIA_SM_DATA_STATE_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 10)
+#define AP_MMIA_SM_MT_ACT_ANS_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 11)
+#define AP_MMIA_SM_CPSB_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 12)
+#define AP_MMIA_SM_CGCONTRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 13)
+#define AP_MMIA_SM_CGSCONTRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 14)
+#define AP_MMIA_SM_CGTFTRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 15)
+#define AP_MMIA_SM_CGDEL_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 16)
+#define AP_MMIA_SM_ZGACT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 17)
+/* ÒÔÉÏΪATÃüÁî¶ÔÓ¦ÏûÏ¢*/
+#define AP_MMIA_SM_GET_PCO_RSP_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 18)
+#define AP_MMIA_SM_IP_PDP_ACT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 19)
+#define AP_MMIA_SM_OPEN_CHNL_RSP_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 20)
+#define AP_MMIA_SM_IDLE_CHNL_QUERY_RSP_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 21)
+#define AP_MMIA_DISCONNECT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 22)
+
+
+#define AP_MMIA_SM_PDP_STATUS_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 0)
+#define AP_MMIA_SM_ACTIVED_CID_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 1)
+#define AP_MMIA_SM_PDP_ADDR_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 2)
+#define AP_MMIA_SM_NEG_QOS_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 3)
+#define AP_MMIA_SM_NEG_EQOS_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 4)
+#define AP_MMIA_SM_NO_CARRIER_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 5)
+#define AP_MMIA_SM_ACT_DEACT_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 6)
+#define AP_MMIA_SM_MOD_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 7)
+#define AP_MMIA_SM_MT_ACTIVATE_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 8)
+#define AP_MMIA_SM_CGEV_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 9)
+#define AP_MMIA_SM_IP_PDP_ACT_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 10)
+#define AP_MMIA_SM_CLOSE_CHNL_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 11)
+#define AP_MMIA_SM_QUERY_IDLE_CHNL_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 12)
+#define AP_MMIA_SM_GET_PCO_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 13)
+#define AP_MMIA_SM_CONNECT_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 14)
+#define AP_MMIA_SM_CPSB_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 15)
+#define AP_MMIA_SM_CGCONTRDP_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 16)
+#define AP_MMIA_SM_CGSCONTRDP_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 17)
+#define AP_MMIA_SM_CGTFTRDP_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 18)
+#define AP_MMIA_SM_CGDEL_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 19)
+#define AP_MMIA_SM_DEACT_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 20)
+
+/* ========================================================================
+ AP-MMIA ESMÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_ESM_CGETFADS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 0)
+#define AP_MMIA_ESM_TFAD_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 1)
+#define AP_MMIA_ESM_CGATFT_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 2)
+#define AP_MMIA_ESM_BEARER_MOD_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 3)
+#define AP_MMIA_ESM_EBR_MOD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 4)
+#define AP_MMIA_CGEQOSRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 5) /*only for R7&R5*/
+#define AP_MMIA_ESM_TFAD_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 6)
+#define AP_MMIA_CGEQOS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 7) /*only for R7&R5*/
+#define AP_MMIA_CGEQOS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 8) /*only for R7&R5*/
+
+#define AP_MMIA_ESM_BEARER_ACT_IND_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 0)
+#define AP_MMIA_ESM_BEARER_DEACT_IND_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 1)
+#define AP_MMIA_ESM_BEARER_MOD_IND_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 2)
+#define AP_MMIA_ESM_TFAD_READ_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 3)
+#define AP_MMIA_ESM_CGATFT_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 4)
+#define AP_MMIA_ESM_BEARER_MOD_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 5)
+#define AP_MMIA_ESM_BEARER_MOD_REJ_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 6)
+#define AP_MMIA_ESM_EBRMOD_QUERY_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 7)
+#define AP_MMIA_CGEQOSRDP_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 8) /*only for R7&R5*/
+#define AP_MMIA_ESM_TFADTEST_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 9)
+
+/* ========================================================================
+ AP-MMIA UICCÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_UICC_INIT_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 0)
+#define AP_MMIA_CPIN_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 1)
+#define AP_MMIA_PIN_REMAIN_NUM_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 2)
+#define AP_MMIA_CPBS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 3)
+#define AP_MMIA_CPBS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 4)
+#define AP_MMIA_CPBR_EXE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 5)
+#define AP_MMIA_CPBR_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 6)
+#define AP_MMIA_CPBF_EXE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 7)
+#define AP_MMIA_CPBF_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 8)
+#define AP_MMIA_CPBW_EXE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 9)
+#define AP_MMIA_CPBW_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 10)
+#define AP_MMIA_UICC_COMMAND_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 11)
+#define AP_MMIA_PIN_APPL_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 12)
+#define AP_MMIA_PIN_APPL_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 13)
+#define AP_MMIA_CARD_MODE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 14)
+#define AP_MMIA_CPIN_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 15)
+#define AP_MMIA_CPBS_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 16)
+#define AP_MMIA_SCPBR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 17)
+#define AP_MMIA_SCPBR_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 18)
+#define AP_MMIA_SCPBW_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 19)
+#define AP_MMIA_SCPBW_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 20)
+#define AP_MMIA_CNUM_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 21)
+#define AP_MMIA_ZIMG_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 22)
+#define AP_MMIA_ZGIIDF_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 23)
+#define AP_MMIA_ZPUK_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 24)
+#define AP_MMIA_CPBW_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 25)
+#define AP_MMIA_ZCPBQ_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 26)
+#define AP_MMIA_ZCPBQ_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 27)
+#define AP_MMIA_ZEER_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 28)
+#define AP_MMIA_MB_AUTH_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 29)
+#define AP_MMIA_MB_CELL_ID_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 30)
+#define AP_MMIA_PSEUDO_FR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 31)
+#define AP_MMIA_PSEUDO_FR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 32)
+#define AP_MMIA_REFRESH_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 33)
+#define AP_MMIA_CARD_SRV_LIST_QRY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 34)
+
+#define AP_MMIA_UICC_INIT_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 0)
+#define AP_MMIA_UICC_OKIND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 1)
+#define AP_MMIA_UICC_INTI_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 2)
+#define AP_MMIA_UICC_SLOT_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 3)
+#define AP_MMIA_PIN_REMAI_NNUM_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 4)
+#define AP_MMIA_CPBS_QUERY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 5)
+#define AP_MMIA_CPBR_EXE_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 6)
+#define AP_MMIA_CPBR_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 7)
+#define AP_MMIA_CPBF_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 8)
+#define AP_MMIA_CPBW_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 9)
+#define AP_MMIA_PIN_APPL_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 10)
+#define AP_MMIA_PIN_APPL_READ_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 11)
+#define AP_MMIA_CARD_MODE_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 12)
+#define AP_MMIA_CPIN_READ_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 13)
+#define AP_MMIA_CPBR_SET_END_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 14)
+#define AP_MMIA_CPBS_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 15)
+#define AP_MMIA_SCPBR_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 16)
+#define AP_MMIA_SCPBR_SET_END_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 17)
+#define AP_MMIA_SCPBR_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 18)
+#define AP_MMIA_SCPBW_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 19)
+#define AP_MMIA_CNUM_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 20)
+#define AP_MMIA_ZIMG_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 21)
+#define AP_MMIA_ZGIIDF_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 22)
+#define AP_MMIA_CPBW_EXE_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 23)
+#define AP_MMIA_ZCPBQ_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 24)
+#define AP_MMIA_ZCPBQ_QUERY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 25)
+#define AP_MMIA_ZEER_READ_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 26)
+#define AP_MMIA_MB_AUTH_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 27)
+#define AP_MMIA_PSEUDO_FR_QUERY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 28)
+#define AP_MMIA_CARD_SRV_LIST_QRY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 29)
+#define AP_MMIA_ICCID_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 30)
+#define AP_MMIA_ZCFIS_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 31)
+#define AP_MMIA_ZISIMINIT_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 32)
+#define AP_MMIA_COPN_EXE_CNF (DWORD)(AP_MMIA_UICC_RSP_EVENT + 33)
+#define AP_MMIA_COPN_END_CNF (DWORD)(AP_MMIA_UICC_RSP_EVENT + 34)
+
+/* ========================================================================
+ AP-MMIA USATÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_USAT_ENVELOP_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 0)
+#define AP_MMIA_USAT_TERMNL_RSP_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 1)
+#define AP_MMIA_USAT_TERMNL_PROF_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 2)
+#define AP_MMIA_USAT_LOC_INFO_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 3)
+#define AP_MMIA_USAT_TO_READ_CARD_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 4)
+
+#define AP_MMIA_USAT_ENVELOP_CNF_EV (DWORD)(AP_MMIA_USAT_RSP_EVENT + 0)
+#define AP_MMIA_USAT_PROV_CMD_IND_EV (DWORD)(AP_MMIA_USAT_RSP_EVENT + 1)
+#define AP_MMIA_USAT_NOPROC_NOTIFY_IND_EV (DWORD)(AP_MMIA_USAT_RSP_EVENT + 2)
+
+/* ========================================================================
+ AP-MMIA CBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_CBS_CSCB_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 0)
+#define AP_MMIA_CBS_CSCB_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 1)
+#define AP_MMIA_CBS_SAVING_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 2)
+#define AP_MMIA_CBS_RESTORE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 3)
+
+#define AP_MMIA_CBS_TCBM_IND_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 0)
+#define AP_MMIA_CBS_PCBM_IND_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 1)
+#define AP_MMIA_CBS_TCBM_LIST_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 2)
+#define AP_MMIA_CBS_PCBM_LIST_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 3)
+#define AP_MMIA_CBS_TCBM_READ_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 4)
+#define AP_MMIA_CBS_PCBM_READ_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 5)
+
+/* ========================================================================
+ AP-MMIA PB(´æ´¢¹ÜÀí)ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_SM_SAVE_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 0)
+#define AP_MMIA_SM_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 1)
+#define AP_MMIA_SM_LIST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 2)
+#define AP_MMIA_SM_DELETE_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 3)
+#define AP_MMIA_SM_MEM_AVAIL_RSP_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 4)
+#define AP_MMIA_PB_FIND_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 5)
+#define AP_MMIA_PB_FIND_TEXT_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 6)
+#define AP_MMIA_PB_EDIT_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 7)
+#define AP_MMIA_PB_STORAGE_STATUS_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 8)
+#define AP_MMIA_PB_PREF_MSG_STO_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 9)
+#define AP_MMIA_PB_PREF_MSG_STO_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 10)
+#define AP_MMIA_PB_TPMR_UPDATE_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 11)
+#define AP_MMIA_PB_MEM_CAPA_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 12)
+#define AP_MMIA_PB_MT_PARA_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 13)
+#define AP_MMIA_PB_EMER_NUM_LIST_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 14)
+#define AP_MMIA_PB_STO_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 15)
+#define AP_MMIA_PB_STO_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 16)
+#define AP_MMIA_PB_QUERY_SMS_MAX_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 17)
+#define AP_MMIA_PB_S_FIND_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 18)
+#define AP_MMIA_PB_S_EDIT_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 19)
+#define AP_MMIA_PB_C_NUM_REQ (DWORD)(AP_MMIA_EVENT_PB_BASE + 20)
+#define AP_MMIA_PB_CLCK_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 21)
+#define AP_MMIA_PB_SCPBR_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 22)
+#define AP_MMIA_PB_SCPBW_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 23)
+#define AP_MMIA_PB_UICC_OK_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 24)
+#define AP_MMIA_PB_CPBR_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 25)
+#define AP_MMIA_PB_CPBF_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 26)
+#define AP_MMIA_PB_SCPBR_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 27)
+#define AP_MMIA_PB_CMGL_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 28)
+#define AP_MMIA_PB_CPBW_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 29)
+#define AP_MMIA_PB_READ_CAPA_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 30)
+#define AP_MMIA_PB_READ_SET_NUM_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 31)
+#define AP_MMIA_PB_READ_LAST_EXT_ERR_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 32)
+
+#define AP_MMIA_SM_SAVE_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 0)
+#define AP_MMIA_SM_READ_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 1)
+#define AP_MMIA_SM_LIST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 2)
+#define AP_MMIA_SM_DELETE_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 3)
+#define AP_MMIA_SM_MEM_AVAIL_IND_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 4)
+#define AP_MMIA_PB_FIND_INDEX_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 5)
+#define AP_MMIA_PB_FIND_TEXT_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 6)
+#define AP_MMIA_PB_EDIT_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 7)
+#define AP_MMIA_PB_STORAGE_STATUS_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 8)
+#define AP_MMIA_PB_FIND_INDEX_END_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 9)
+#define AP_MMIA_PB_PREF_MSG_STO_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 10)
+#define AP_MMIA_PB_PREF_MSG_STO_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 11)
+#define AP_MMIA_PB_COMMON_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 12)
+#define AP_MMIA_PB_INIT_COMP_IND_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 13)
+#define AP_MMIA_PB_STO_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 14)
+#define AP_MMIA_PB_QUERY_SMS_MAX_INDEX_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 15)
+#define AP_MMIA_PB_S_FIND_INDEX_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 16)
+#define AP_MMIA_PB_S_FIND_INDEX_END_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 17)
+#define AP_MMIA_PB_S_EDIT_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 18)
+#define AP_MMIA_PB_SCPBR_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 19)
+#define AP_MMIA_PB_SCPBW_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 20)
+#define AP_MMIA_PB_C_NUM_CNF (DWORD)(AP_MMIA_PB_RSP_EVENT + 21)
+#define AP_MMIA_PB_CLCK_STATUS_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 22)
+#define AP_MMIA_PB_CHG_INDEX_IND_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 23)
+#define AP_MMIA_PB_CPBW_QUERY_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 24)
+#define AP_MMIA_PB_READ_CAPA_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 25)
+#define AP_MMIA_PB_READ_SET_NUM_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 26)
+#define AP_MMIA_PB_READ_LAST_EXT_ERR_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 27)
+
+/* ========================================================================
+ AP-MMIA ¹¤³ÌģʽºÍÏúÁ¿Í³¼ÆÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_EM_CELL_INFO_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 0)
+#define AP_MMIA_EM_CELL_INFO_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 1)
+#define AP_MMIA_EM_LOCK_CELL_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 2)
+#define AP_MMIA_EM_HO_INFO_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 3)
+#define AP_MMIA_EM_HO_INFO_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 4)
+#define AP_MMIA_SELL_STAT_SWITCH_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 5)
+#define AP_MMIA_SELL_STAT_SWITCH_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 6)
+#define AP_MMIA_SELL_STAT_UDPINFO_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 7)
+#define AP_MMIA_SELL_STAT_TEST_SEND_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 8)
+#define AP_MMIA_SELL_STAT_DOMAIN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 9)
+#define AP_MMIA_SELL_STAT_DOMAIN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 10)
+#define AP_MMIA_SELL_STAT_CRC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 11)
+#define AP_MMIA_SELL_STAT_CRC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 12)
+#define AP_MMIA_SELL_STAT_DEBUG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 13)
+#define AP_MMIA_SELL_STAT_DEBUG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 14)
+#define AP_MMIA_SELL_STAT_PORT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 15)
+#define AP_MMIA_SELL_STAT_PORT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 16)
+#define AP_MMIA_SELL_STAT_TRI_TYPE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 17)
+#define AP_MMIA_SELL_STAT_DNS_CNT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 18)
+
+
+#define AP_MMIA_EM_CELL_INFO_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 0)
+#define AP_MMIA_EM_HO_INFO_IND_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 1)
+#define AP_MMIA_EM_HO_INFO_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 2)
+#define AP_MMIA_SELL_STAT_SWITCH_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 3)
+#define AP_MMIA_SELL_STAT_UDPINFO_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 4)
+#define AP_MMIA_SELL_STAT_DOMAIN_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 5)
+#define AP_MMIA_SELL_STAT_CRC_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 6)
+#define AP_MMIA_SELL_STAT_DEBUG_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 7)
+#define AP_MMIA_SELL_STAT_PORT_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 8)
+#define AP_MMIA_SELL_STAT_TRI_TYPE_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 9)
+#define AP_MMIA_SELL_STAT_DNS_CNT_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 10)
+
+/* ========================================================================
+ AP-MMIA ÐźÅÇ¿¶ÈÖ÷¶¯Éϱ¨ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_RXLEV_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 0)
+#define AP_MMIA_ZRPT_RXLEV_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 1)
+#define AP_MMIA_ZRPT_RXLEV_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 2)
+#define AP_MMIA_QUERY_IMSI_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 3)
+#define AP_MMIA_QUERY_IMEI_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 4)
+#define AP_MMIA_ABORT_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 5)
+#define AP_MMIA_CAUSE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 6)
+#define AP_MMIA_SPN_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 7)
+#define AP_MMIA_ZETWS_PRIMARY_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 8)
+#define AP_MMIA_ZETWS_PRIMARY_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 9)
+#define AP_MMIA_ZETWS_SECONDARY_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 10)
+#define AP_MMIA_ZETWS_SECONDARY_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 11)
+#define AP_MMIA_SET_IMSI_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 12)
+#define AP_MMIA_AUTO_START_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 13)
+#define AP_MMIA_CHNEL_STATE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 14)
+#define AP_MMIA_ZOPERLTEBAND_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 15)
+
+
+#define AP_MMIA_RXLEV_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 0)
+#define AP_MMIA_ZRPT_RXLEVIND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 1)
+#define AP_MMIA_ZRPT_RXLEV_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 2)
+#define AP_MMIA_QUERY_IMSI_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 3)
+#define AP_MMIA_QUERY_IMEI_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 4)
+#define AP_MMIA_COMMON_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 5)
+#define AP_MMIA_CAUSE_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 6)
+#define AP_MMIA_ZPBIC_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 7)
+#define AP_MMIA_SPN_READ_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 8)
+#define AP_MMIA_ZETWS_PRIMARY_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 9)
+#define AP_MMIA_ZETWS_SECONDARY_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 10)
+#define AP_MMIA_ZETWS_PRIMARY_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 11)
+#define AP_MMIA_ZETWS_SECONDARY_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 12)
+#define AP_MMIA_CHG_INDEX_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 13)
+
+/* ========================================================================
+ MMIA-UMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_UMM_SEARCH_PLMN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 0)
+#define MMIA_UMM_PLMN_LIST_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 1)
+#define MMIA_UMM_ACTIVE_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 2)
+#define MMIA_UMM_RF_CTRL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 3)
+#define MMIA_UMM_ABORT_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 4)
+#define MMIA_UMM_EM_LOCK_CELL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 5)
+#define MMIA_UMM_CSG_SEL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 6)
+#define MMIA_UMM_CURRENT_CSG_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 7)
+#define MMIA_UMM_CSG_LIST_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 8)
+#define MMIA_UMM_SYSCONFIG_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 9)
+#define MMIA_UMM_CGATT_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 10)
+#define MMIA_UMM_ZATT_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 11)
+#define MMIA_UMM_EPS_MODE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 12)
+#define MMIA_UMM_EPS_MODE_SET_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 13)
+#define MMIA_UMM_SET_LTE_ACT_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 14)
+#define MMIA_UMM_CS_SRV_CNF_EV (DWORD)(MMIA_UMM_EVENT_BASE + 15)
+#define MMIA_UMM_IMS_REGISTER_STATES_EV (DWORD)(MMIA_UMM_EVENT_BASE + 16)
+#define MMIA_UMM_VOICE_MODE_SET_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 17)
+#define MMIA_UMM_VOICE_MODE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 18)
+#define MMIA_UMM_SYSCONFIG_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 19)
+#define MMIA_UMM_SMSOVERIPNET_SETREQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 20)
+#define Z_TD_LTE_CELL_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 21)
+#define MMIA_UMM_PS_CONTEXT_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 22)
+#define MMIA_UMM_PS_CONTEXT_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 23)
+#define MMIA_UMM_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 24)
+#define MMIA_UMM_UPDATE_OPERPLMN_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 25)
+#define MMIA_UMM_CS_CALL_START_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 26)
+#define MMIA_UMM_CS_CALL_END_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 27)
+#define MMIA_UMM_XCELLINFO_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 28)
+#define MMIA_UMM_LASTCID_APNMODIFY_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 29)
+#define MMIA_UMM_CSVOICE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 30)
+#define MMIA_UMM_CARDSWITCH_CMP_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 31)
+#define MMIA_UMM_ECALLSPT_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 32)
+#define MMIA_UMM_ECALLONLY_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 33)
+#define MMIA_UMM_FREQ_SCAN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 34)
+#define MMIA_UMM_FAST_FREQ_SCAN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 35)
+#define MMIA_UMM_IMSAIRREL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 36)
+#define MMIA_UMM_SOFTPOWER_STATUS_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 37)
+#define MMIA_UMM_IMS_CALL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 38)
+
+
+#define MMIA_UMM_PLMN_INFO_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 0)
+#define MMIA_UMM_PLMN_LIST_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 1)
+#define MMIA_UMM_ACTIVE_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 2)
+#define MMIA_UMM_MM_INFO_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 3)
+#define MMIA_UMM_RF_CTRL_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 4)
+#define MMIA_UMM_EM_LOCK_CELL_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 5)
+#define MMIA_UMM_CSG_SEL_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 6)
+#define MMIA_UMM_CURRENT_CSG_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 7)
+#define MMIA_UMM_CSG_LIST_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 8)
+#define MMIA_UMM_COMMON_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 9)
+#define MMIA_UMM_CGATT_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 10)
+#define MMIA_UMM_ZATT_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 11)
+#define MMIA_UMM_EPS_MODE_SET_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 12)
+#define MMIA_UMM_EPS_MODE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 13)
+#define MMIA_UMM_SEARCH_PLMN_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 14)
+#define MMIA_UMM_CS_SRV_IND_Ev (DWORD)(MMIA_UMM_RSP_EVENT + 15)
+#define MMIA_UMM_VOICE_MODE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 16)
+#define MMIA_UMM_SYSCONFIG_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 17)
+#define MMIA_UMM_NOTIFY_PS_STATE_EV (DWORD)(MMIA_UMM_RSP_EVENT + 18)
+#define MMIA_UMM_SUBMODE_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 19)
+#define MMIA_UMM_SRVCC_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 20)
+#define MMIA_UMM_PS_CONTEXT_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 21)
+#define MMIA_UMM_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 22)
+#define MMIA_UMM_UPDATE_DUALPSSYSCONFIG_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 23)
+#define MMIA_UMM_IMSNOTSUPPORT_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 24)
+#define MMIA_UMM_PLMNLIST_BANDINFO_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 25)
+#define MMIA_UMM_XCELLINFO_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 26)
+#define MMIA_UMM_CSVOICE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 27)
+#define MMIA_UMM_SCAN_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 28)
+#define MMIA_UMM_CARDSWITCH_REQ_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 29)
+#define MMIA_UMM_ECALLSPT_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 30)
+#define MMIA_UMM_ECALLONLY_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 31)
+#define MMIA_UMM_CAUSE_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 32)
+#define MMIA_UMM_T10DEREG_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 33)
+/* ========================================================================
+ MMIA£CCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_CC_MOC_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 0)
+#define MMIA_CC_MTC_RSP_EV (DWORD)(MMIA_CC_EVENT_BASE + 1)
+#define MMIA_CC_ANS_MODE_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 2)
+#define MMIA_CC_MODIFY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 3)
+#define MMIA_CC_DIS_MODE_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 4)
+#define MMIA_CC_DTMF_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 5)
+#define MMIA_CC_CHLD_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 6)
+#define MMIA_CC_STATE_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 7)
+#define MMIA_CC_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 8)
+#define MMIA_CC_CSTA_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 9)
+#define MMIA_CC_CSTA_SET_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 10)
+#define MMIA_CC_MODE_TO_MULTMEDIA_RSP_EV (DWORD)(MMIA_CC_EVENT_BASE + 11)
+#define MMIA_CC_CCM_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 12)
+#define MMIA_CC_ABORT_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 13)
+#define MMIA_CC_STATE_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 14)
+#define MMIA_CC_OPEN_VOICECHNL_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 15)
+#define MMIA_CC_SRVCC_NOTOPEN_VOICECHNL_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 16)
+#define MMIA_CC_T9TIMER_SET_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 17)
+#define MMIA_CC_T9TIMER_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 18)
+#define MMIA_CC_VOICEMODE_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 19)
+#define MMIA_CC_RESETIVS_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 20)
+#define MMIA_CC_WAITMSD_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 21)
+
+#define MMIA_CC_MOC_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 0)
+#define MMIA_CC_MTC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 1)
+#define MMIA_CC_ANS_MODE_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 2)
+#define MMIA_CC_MODIFY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 3)
+#define MMIA_CC_DISC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 4)
+#define MMIA_CC_NOTIFY_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 5)
+#define MMIA_CC_AOC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 6)
+#define MMIA_CC_SS_NOTIFY_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 7)
+#define MMIA_CC_STATE_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 8)
+#define MMIA_CC_COMMON_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 9)
+#define MMIA_CC_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 10)
+#define MMIA_CC_PROC_INFO_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 11)
+#define MMIA_CC_CSTA_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 12)
+#define MMIA_CC_MODE_TO_MULTMEDIAIND_EV (DWORD)(MMIA_CC_RSP_EVENT + 13)
+#define MMIA_CC_DISC_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 14)
+#define MMIA_CC_CALL_STATE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 15)
+#define MMIA_CC_OPEN_VOICE_CHNL_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 16)
+#define MMIA_CC_CLOSE_VOICE_CHNL_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 17)
+#define MMIA_CC_CCM_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 18)
+#define MMIA_CC_CCWV_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 19)
+#define MMIA_CC_NOTIFY_AOC_TIMER_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 20)
+#define MMIA_CC_CNAP_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 21)
+#define MMIA_CC_DUALPSCFG_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 22)
+#define MMIA_CC_STOP_LOCALVOICE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 23)
+#define MMIA_CC_CHLD_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 24)
+#define MMIA_CC_DTMF_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 25)
+#define MMIA_CC_CSTA_SET_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 26)
+#define MMIA_CC_START_LOCALVOICE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 27)
+#define MMIA_CC_ZECALL_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 28)
+#define MMIA_CC_CECN_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 29)
+#define MMIA_CC_ECALL_WORKSTATE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 30)
+#define MMIA_CC_T9TIMER_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 31)
+#define MMIA_CC_CALLBACK_EVENT_EV (DWORD)(MMIA_CC_RSP_EVENT + 32)
+#define MMIA_CC_VOICEMODE_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 33)
+#define MMIA_CC_RESETIVS_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 34)
+#define MMIA_CC_WAITMSD_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 35)
+
+/* ========================================================================
+ MMIA£SMSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_SMS_SUBMIT_SEND_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 0)
+#define MMIA_SMS_COMMAND_SEND_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 1)
+#define MMIA_SMS_REC_RSP_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 2)
+#define MMIA_SMS_MEM_AVAIL_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 3)
+#define MMIA_SMS_STORE_REPORT_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 4)
+#define MMIA_SMS_ABORT_MO_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 5)
+
+#define MMIA_SMS_MSG_SEND_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 0)
+#define MMIA_SMS_DELIVER_REC_IND_EV (DWORD)(MMIA_SMS_RSP_EVENT + 1)
+#define MMIA_SMS_STATUS_REC_IND_EV (DWORD)(MMIA_SMS_RSP_EVENT + 2)
+#define MMIA_SMS_REC_RSP_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 3)
+#define MMIA_SMS_MMS_DISABLE_IND_EV (DWORD)(MMIA_SMS_RSP_EVENT + 4)
+#define MMIA_SMS_MEM_AVAIL_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 5)
+#define MMIA_SMS_COMMON_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 6)
+
+/* ========================================================================
+ MMIA£SSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_SS_CLCK_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 0)
+#define MMIA_SS_CPWD_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 1)
+#define MMIA_SS_CLIP_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 2)
+#define MMIA_SS_CLIR_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 3)
+#define MMIA_SS_COLP_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 4)
+#define MMIA_SS_COLR_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 5)
+#define MMIA_SS_CCFC_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 6)
+#define MMIA_SS_CCWA_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 7)
+#define MMIA_SS_CUSD_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 8)
+#define MMIA_SS_ABORT_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 9)
+#define MMIA_SS_USSD_CANCEL_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 10)
+#define MMIA_SS_CNAP_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 11)
+#define MMIA_SS_MOLR_ENABLE_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 12)
+#define MMIA_SS_MOLR_DISABLE_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 13)
+#define MMIA_SS_MTLR_ANS_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 14)
+
+#define MMIA_SS_COMMON_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 0)
+#define MMIA_SS_CLCK_QUERY_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 1)
+#define MMIA_SS_CLIP_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 2)
+#define MMIA_SS_CLIR_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 3)
+#define MMIA_SS_COLP_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 4)
+#define MMIA_SS_COLR_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 5)
+#define MMIA_SS_CCFC_QUERY_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 6)
+#define MMIA_SS_CCWA_QUERY_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 7)
+#define MMIA_SS_CUSD_MT_IND_EV (DWORD)(MMIA_SS_RSP_EVENT + 8)
+#define MMIA_SS_CNAP_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 9)
+#define MMIA_SS_MOLR_RES_IND_EV (DWORD)(MMIA_SS_RSP_EVENT + 10)
+#define MMIA_SS_MTLOCIREQ_NOTIFY_IND_EV (DWORD)(MMIA_SS_RSP_EVENT + 11)
+/* ========================================================================
+ MMIA£SMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_SM_NEG_QOS_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 0)
+#define MMIA_SM_NEG_EQOS_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 1)
+#define MMIA_SM_ACTIVATED_CID_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 2)
+#define MMIA_SM_PDP_STATUS_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 3)
+#define MMIA_SM_PDP_ADDR_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 4)
+#define MMIA_SM_PDP_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 5)
+#define MMIA_SM_PDP_ACTIVATE_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 6)
+#define MMIA_SM_PDP_DEACTIVATE_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 7)
+#define MMIA_SM_PDP_MODIFY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 8)
+#define MMIA_SM_DATA_STATE_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 9)
+#define MMIA_SM_MT_ACT_ANS_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 10)
+#define MMIA_SM_CPSB_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 11)
+#define MMIA_SM_CGCONTRDP_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 12)
+#define MMIA_SM_CGSCONTRDP_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 13)
+#define MMIA_SM_CGTFTRDP_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 14)
+
+/* ÒÔÉÏÏûÏ¢ÓжÔÓ¦µÄATÃüÁî */
+#define MMIA_SM_ABORT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 15)
+#define MMIA_SM_IP_PDP_ACT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 16)
+#define MMIA_SM_IDLE_CHNL_QUERY_RSP_EV (DWORD)(MMIA_SM_EVENT_BASE + 17)
+#define MMIA_SM_GET_PCO_RSP_EV (DWORD)(MMIA_SM_EVENT_BASE + 18)
+#define MMIA_SM_DISCONNECT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 19)
+#define MMIA_SM_CONTEXT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 20)
+#define MMIA_SM_CONTEXT_IND_EV (DWORD)(MMIA_SM_EVENT_BASE + 21)
+
+#define MMIA_SM_NEG_QOS_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 0)
+#define MMIA_SM_NEG_EQOS_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 1)
+#define MMIA_SM_ACTIVATED_CID_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 2)
+#define MMIA_SM_PDP_STATUS_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 3)
+#define MMIA_SM_PDP_ADDR_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 4)
+#define MMIA_SM_PDP_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 5)
+#define MMIA_SM_PDP_ACTIVATE_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 6)
+#define MMIA_SM_PDP_DEACTIVATE_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 7)
+#define MMIA_SM_PDP_MODIFY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 8)
+#define MMIA_SM_PDP_ACTIVATE_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 9)
+#define MMIA_SM_CGEV_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 10)
+#define MMIA_SM_IP_PDP_ACT_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 11)
+#define MMIA_SM_CLOSE_CHNL_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 12)
+#define MMIA_SM_IDLE_CHNL_QUERY_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 13)
+#define MMIA_SM_GET_PCO_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 14)
+#define MMIA_SM_COMMON_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 15)
+#define MMIA_SM_CONNECT_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 16)
+#define MMIA_SM_NO_CARRIER_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 17)
+#define MMIA_SM_CID_DEACT_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 18)
+#define MMIA_SM_CPSB_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 19)
+#define MMIA_SM_CPSB_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 20)
+#define MMIA_SM_CGCONTRDP_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 21)
+#define MMIA_SM_CGSCONTRDP_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 22)
+#define MMIA_SM_CGTFTRDP_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 23)
+#define MMIA_SM_NOTIFICATION_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 24)
+#define MMIA_SM_MT_ACT_ANS_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 25)
+#define MMIA_SM_CONTEXT_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 26)
+#define MMIA_SM_MSISDN_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 27)
+
+/* ========================================================================
+ ESM- MMIAÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_ESM_MT_EPS_BEARER_ACT_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 0) /*only for R7&R5*/
+#define MMIA_ESM_EPS_BEARER_MOD_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 1)
+#define MMIA_ESM_EBR_MOD_QUERY_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 2)
+#define MMIA_ESM_EPS_QOS_QUERY_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 3) /*only for R7&R5*/
+#define MMIA_ESM_CGATFT_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 4)
+#define MMIA_ESM_ABORT_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 5) /*only for R7&R5*/
+#ifdef BTRUNK_SUPPORT
+#define PTT_MMIA_ESM_TAUTYPE_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 6) /*¼¯ÈºÌí¼Ó*/
+#endif
+#define MMIA_ESM_PDP_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 7)
+
+#define MMIA_ESM_EPS_BEARER_ACT_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 0)
+#define MMIA_ESM_EPS_BEARER_DEACT_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 1)
+#define MMIA_ESM_EPS_BEARER_MOD_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 2)
+#define MMIA_ESM_MT_EPS_BEARER_ACT_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 3) /*only for R7&R5*/
+#define MMIA_ESM_EPS_BEARER_MOD_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 4)
+#define MMIA_ESM_EPS_BEARER_MOD_REJ_EV (DWORD)(MMIA_ESM_RSP_EVENT + 5)
+#define MMIA_ESM_EBR_MOD_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 6)
+#define MMIA_ESM_EPS_QOS_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 7) /*only for R7&R5*/
+#define MMIA_ESM_CGATFT_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 8)
+#define MMIA_ESM_PDP_ADDR_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 9) /*only for R7&R5*/
+#ifdef BTRUNK_SUPPORT
+#define PTT_MMIA_ESM_TAUTYPE_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 10) /*¼¯ÈºÌí¼Ó*/
+#endif
+#define MMIA_ESM_PDP_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 11)
+
+/* ========================================================================
+ MMIA£CBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_CBS_ACTIVATE_REQ_EV (DWORD)(MMIA_CBS_EVENT_BASE + 0)
+
+#define MMIA_CBS_ACTIVATE_CNF_EV (DWORD)(MMIA_CBS_RSP_EVENT + 0)
+#define MMIA_CBS_DATA_IND_EV (DWORD)(MMIA_CBS_RSP_EVENT + 1)
+
+/* ========================================================================
+ MMIA£ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_AS_EM_CELL_INFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 0)
+#define MMIA_AS_EM_HO_INFO_REQ (DWORD)(MMIA_AS_EVENT_BASE + 1)
+#define MMIA_AS_EM_CELLRESORCCOCOUNT_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 2)
+#define MMIA_AS_RPT_RXLEV_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 3)
+#define MMIA_AS_QUERY_RXLEV_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 4)
+#define MMIA_PDI_SELL_STAT_START_SEND_PACKET_IND_EV (DWORD)(MMIA_AS_EVENT_BASE + 5)
+#define MMIA_PDI_SELL_STAT_ABORT_IND_EV (DWORD)(MMIA_AS_EVENT_BASE + 6)
+#define MMIA_EUCSR_LTEINFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 7)
+#define MMIA_L1E_ZEPCG_REQ (DWORD)(MMIA_AS_EVENT_BASE + 8)
+#define MMIA_AS_B39_INFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 9)
+#define MMIA_AS_RSSI_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 10)
+#define MMIA_AS_SINR_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 11)
+#define MMIA_AS_QUERY_EM_CELL_INFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 12)
+#define MMIA_AS_TMGI_ACTIVATE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 13)
+#define MMIA_AS_TMGI_DEACTIVATE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 14)
+#define MMIA_AS_SAI_LIST_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 15)
+#define MMIA_AS_TMGI_LIST_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 16)
+#define MMIA_AS_TMGI_LIST_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 17)
+#define MMIA_AS_MBMS_PREFERENCE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 18)
+#define MMIA_AS_TMGI_LIST_REPORT_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 19)
+#define MMIA_AS_SAI_LIST_REPORT_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 20)
+#define MMIA_AS_NW_TIME_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 21)
+#define MMIA_AS_QUERY_CESQ_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 22)
+#define MMIA_AS_EM_LTE_HO_SET_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 23)
+#define MMIA_AS_EM_LTE_HO_SET_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 24)
+#define MMIA_L1W_ZWPCG_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 25)
+#define MMIA_L1T_ZTPCG_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 26)
+#define MMIA_GRR_ZGPCG_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 27)
+#define MMIA_AS_QUERY_ZCSQ_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 28)
+#define MMIA_AS_LBS_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 29)
+#define MMIA_AS_IMS_DATA_DELETE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 30)
+#define MMIA_AS_CARD_SWITCH_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 31)
+#define MMIA_AS_CARD_SWITCH_IND_EV (DWORD)(MMIA_AS_EVENT_BASE + 32)
+
+#define MMIA_AS_EM_UCELL_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 0)
+#define MMIA_AS_EM_UHO_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 1)
+#define MMIA_AS_RPT_RXLEV_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 2)
+#define MMIA_AS_QUERY_RXLEV_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 3)
+#define MMIA_EUSIR_ETWS_PRIMARY_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 4)
+#define MMIA_EUSIR_ETWS_SECONDARY_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 5)
+#define MMIA_AS_EM_EUCELL_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 6)
+#define MMIA_EUCSR_LTEINFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 7)
+#define MMIA_L1E_ZEPCG_CNF (DWORD)(MMIA_AS_RSP_EVENT + 8)
+#define MMIA_AS_B39_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 9)
+#define AS_EM_CELL_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 10)
+#define MMIA_AS_RSSI_QUERY_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 11)
+#define MMIA_AS_SINR_QUERY_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 12)
+#define MMIA_AS_QUERY_EM_UCELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 13)
+#define MMIA_AS_QUERY_EM_EUCELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 14)
+#define RR_QUERY_EM_CELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 15)
+#define AS_QUERY_EM_CELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 16)
+#define MMIA_AS_TMGI_ACTIVATE_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 17)
+#define MMIA_AS_TMGI_DEACTIVATE_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 18)
+#define MMIA_AS_SAI_LIST_QUERY_RESP_EV (DWORD)(MMIA_AS_RSP_EVENT + 19)
+#define MMIA_AS_SAI_LIST_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 20)
+#define MMIA_AS_TMGI_LIST_QUERY_RESP_EV (DWORD)(MMIA_AS_RSP_EVENT + 21)
+#define MMIA_AS_TMGI_LIST_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 22)
+#define MMIA_AS_MBMS_SERVICE_SUSPEND_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 23)
+#define MMIA_AS_MBMS_SERVICE_RESUME_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 24)
+#define MMIA_AS_COMMON_CFG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 25)
+#define MMIA_AS_NW_TIME_QUERY_RESP_EV (DWORD)(MMIA_AS_RSP_EVENT + 26)
+#define ATI_EUCSR_HIGHT_CALL_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 27)
+#define MMIA_AS_QUERY_CESQ_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 28)
+#define ATI_EUCSR_BUSY_ALERTING_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 29)
+#define MMIA_ASC_LTE_LOSTCOVERAGE_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 30)
+#define MMIA_AS_EM_LTE_HO_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 31)
+#define MMIA_AS_EM_LTE_HO_SET_QUERY_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 32)
+#define MMIA_L1W_ZWPCG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 33)
+#define MMIA_L1T_ZTPCG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 34)
+#define MMIA_GRR_ZGPCG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 35)
+#define MMIA_AS_QUERY_ZCSQ_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 36)
+#define MMIA_AS_LBS_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 37)
+#define MMIA_AS_UL_PARAM_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 38)
+#define MMIA_AS_CARD_SWITCH_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 39)
+/* ========================================================================
+ PDI - ATI ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ATI_PDI_DATA_REQ_EV (DWORD)(ATI_PDI_EVENT_BASE + 0)
+#define ATI_PDI_DATA_IND_EV (DWORD)(ATI_PDI_EVENT_BASE + 1)
+#define PSI_PDI_DATA_IND_EV (DWORD)(ATI_PDI_EVENT_BASE + 2)
+
+/* ========================================================================
+ CSD - ATI ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ATI_CSD_DATA_IND_EV (DWORD)(ATI_CSD_EVENT_BASE + 0)
+
+#define ATI_CSD_FLOW_CTRL_ON_EV (DWORD)(ATI_CSD_RSP_EVENT + 0)
+#define ATI_CSD_FLOW_CTRL_OFF_EV (DWORD)(ATI_CSD_RSP_EVENT + 1)
+
+/*È«¾Ö±äÁ¿ÉèÖᢻñÈ¡ÏûÏ¢¶¨Òå*/
+#define GVAR_MMIA_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 0)
+#define GVAR_MMIA_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 1)
+
+#define GVAR_UMM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 2)
+#define GVAR_UMM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 3)
+
+#define GVAR_MM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 4)
+#define GVAR_MM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 5)
+
+#define GVAR_GMM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 6)
+#define GVAR_GMM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 7)
+
+#define GVAR_UICCMNG_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 8)
+#define GVAR_UICCMNG_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 9)
+
+#define GVAR_CC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 10)
+#define GVAR_CC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 11)
+
+#define GVAR_SM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 12)
+#define GVAR_SM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 13)
+
+#define GVAR_SMS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 14)
+#define GVAR_SMS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 15)
+
+#define GVAR_SS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 16)
+#define GVAR_SS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 17)
+
+#define GVAR_DS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 18)
+#define GVAR_DS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 19)
+#define GVAR_RA_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 20)
+#define GVAR_RA_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 21)
+#define GVAR_RLP_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 22)
+#define GVAR_RLP_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 23)
+
+#define GVAR_CBS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 24)
+#define GVAR_CBS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 25)
+
+#define GVAR_URRC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 26)
+#define GVAR_URRC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 27)
+
+#define GVAR_UMTC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 28)
+#define GVAR_UMTC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 29)
+
+#define GVAR_UCER_CONTEXT_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 30)
+#define GVAR_UCER_CONTEXT_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 31)
+#define GVAR_UCER_SECURITY_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 32)
+#define GVAR_UCER_SECURITY_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 33)
+
+#define GVAR_UCSR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 34)
+#define GVAR_UCSR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 35)
+
+#define GVAR_USIR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 36)
+#define GVAR_USIR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 37)
+
+#define GVAR_UMCR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 38)
+#define GVAR_UMCR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 39)
+
+#define GVAR_URBC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 40)
+#define GVAR_URBC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 41)
+
+#define GVAR_UCMR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 42)
+#define GVAR_UCMR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 43)
+
+#define GVAR_URLC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 44)
+#define GVAR_URLC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 45)
+
+#define GVAR_UMAC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 46)
+#define GVAR_UMAC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 47)
+#define GVAR_PDCP_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 48)
+#define GVAR_PDCP_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 49)
+#define GVAR_RABM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 50)
+#define GVAR_RABM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 51)
+
+#define GVAR_PDI_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 52)
+#define GVAR_PDI_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 53)
+
+#define GVAR_SCI_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 54)
+#define GVAR_SCI_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 55)
+
+#define GVAR_GSMA_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 56)
+#define GVAR_GSMA_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 57)
+
+#define GVAR_UICC_DEV_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 58)
+#define GVAR_UICC_DEV_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 59)
+
+#define GVAR_ATMEM_DEV_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 60)
+#define GVAR_ATMEM_DEV_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 61)
+
+#define GVAR_NV_DEV_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 62)
+#define GVAR_NV_DEV_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 63)
+
+#define GVAR_ASC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 64)
+#define GVAR_ASC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 65)
+
+#define GVAR_EMM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 66)
+#define GVAR_EMM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 67)
+
+#define GVAR_ESM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 68)
+#define GVAR_ESM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 69)
+
+/*WCDMA GVAR_EVENT_BASE=150*/
+#define GVAR_WRRC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 70)
+#define GVAR_WRRC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 71)
+
+#define GVAR_WMTC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 72)
+#define GVAR_WMTC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 73)
+
+#define GVAR_WCER_CONTEXT_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 74)
+#define GVAR_WCER_CONTEXT_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 75)
+#define GVAR_WCER_SECURITY_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 76)
+#define GVAR_WCER_SECURITY_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 77)
+
+#define GVAR_WCSR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 78)
+#define GVAR_WCSR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 79)
+
+#define GVAR_WSIR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 80)
+#define GVAR_WSIR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 81)
+
+#define GVAR_WMCR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 82)
+#define GVAR_WMCR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 83)
+
+#define GVAR_WRBC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 84)
+#define GVAR_WRBC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 85)
+
+#define GVAR_WCMR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 86)
+#define GVAR_WCMR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 87)
+
+#define GVAR_WRLC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 88)
+#define GVAR_WRLC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 89)
+
+#define GVAR_WMAC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 90)
+#define GVAR_WMAC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 91)
+
+#define GVAR_ECSR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 92)
+#define GVAR_ECSR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 93)
+
+#define GVAR_ECER_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 94)
+#define GVAR_ECER_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 95)
+
+#define GVAR_STM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 96)
+#define GVAR_STM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 97)
+#define GVAR_TSM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 98)
+#define GVAR_TSM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 99)
+
+#define GVAR_LPP_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 100)
+#define GVAR_LPP_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 101)
+
+
+#define RRAT_RXSTAT_IND (DWORD)(GRR_EVENT_BASE + 140)
+#define RRMI_RXSTAT_IND (DWORD)(GRR_EVENT_BASE + 141)
+#define RR_EM_HO_INFO_IND (DWORD)(GRR_EVENT_BASE + 142)
+#define RR_EM_CELL_INFO_IND (DWORD)(GRR_EVENT_BASE + 143)
+#define ERRC_CELL_CHANGE_CNF_EV (DWORD)(GRR_EVENT_BASE + 144)
+#define ERRC_CELL_CHANGE_REJ_EV (DWORD)(GRR_EVENT_BASE + 145)
+#define ERRC_RESEL_CNF_EV (DWORD)(GRR_EVENT_BASE + 146)
+#define ERRC_RESEL_REJ_EV (DWORD)(GRR_EVENT_BASE + 147)
+#define ERRC_CELL_SEARCH_CNF_EV (DWORD)(GRR_EVENT_BASE + 148)
+#define ERRC_CELL_SEARCH_REJ_EV (DWORD)(GRR_EVENT_BASE + 149)
+#define URRC_PSHO_CNF_EV (DWORD)(GRR_EVENT_BASE + 150)
+#define URRC_PSHO_REJ_EV (DWORD)(GRR_EVENT_BASE + 151)
+#define ERRC_PSHO_CNF_EV (DWORD)(GRR_EVENT_BASE + 152)
+#define ERRC_PSHO_REJ_EV (DWORD)(GRR_EVENT_BASE + 153)
+#define RR_PSHO_REQ_EV (DWORD)(GRR_EVENT_BASE + 154)
+#define MAC_GRR_PSHO_CNF_EV (DWORD)(GRR_EVENT_BASE + 155)
+#define MAC_GRR_PSHO_REJ_EV (DWORD)(GRR_EVENT_BASE + 156)
+#define MAC_GRR_PSHO_RETURN_CNF_EV (DWORD)(GRR_EVENT_BASE + 157)
+#define MAC_GRR_PSHO_RETURN_FAIL_EV (DWORD)(GRR_EVENT_BASE + 158)
+#define MAC_GRR_PSHO_DEACT_CNF_EV (DWORD)(GRR_EVENT_BASE + 159)
+#define Z_RRMI_INTER_RAT_NCELL_IND_EV (DWORD)(GRR_EVENT_BASE + 160)
+#define RR_XCELLINFO_REQ (DWORD)(GRR_EVENT_BASE + 161)
+#define RR_XCELLINFO_ABORT_REQ (DWORD)(GRR_EVENT_BASE + 162)
+
+/* START OF RRC */
+#define LLC_RRC_DATA_REQ (DWORD)(GRRC_EVENT_BASE + 0)
+#define RR_EM_HO_INFO_REQ (DWORD)(GRRC_EVENT_BASE + 1)
+#define RR_ABORT_REQ (DWORD)(GRRC_EVENT_BASE + 2)
+#define RR_DATA_REQ (DWORD)(GRRC_EVENT_BASE + 3)
+#define RR_HO_START_INFO (DWORD)(GRRC_EVENT_BASE + 4)
+#define GRR_RRC_CLASSMARK_IND (DWORD)(GRRC_EVENT_BASE + 5)
+#define GRR_RRC_UPDATE_PARAM_REQ (DWORD)(GRRC_EVENT_BASE + 6)
+#define GRR_RRC_ASSIGN_REQ (DWORD)(GRRC_EVENT_BASE + 7)
+#define GRR_RRC_EST_REQ (DWORD)(GRRC_EVENT_BASE + 8)
+#define GRR_RRC_ERROR_IND (DWORD)(GRRC_EVENT_BASE + 9)
+#define GRR_RRC_DEACT_REQ (DWORD)(GRRC_EVENT_BASE + 10)
+#define GRR_RRC_RXSTAT_REQ (DWORD)(GRRC_EVENT_BASE + 11)
+#define GRR_RRC_TESTPARAM_REQ (DWORD)(GRRC_EVENT_BASE + 12)
+#define GRR_RRC_MN_MEAS_REQ (DWORD)(GRRC_EVENT_BASE + 13)
+#define GRR_RRC_RRAT_RXSTAT_REQ (DWORD)(GRRC_EVENT_BASE + 14)
+#define GRR_RRC_RRL_DATA_REQ (DWORD)(GRRC_EVENT_BASE + 15)
+#define GRR_RRC_DTM_REQ (DWORD)(GRRC_EVENT_BASE + 16)
+#define GRR_RRC_PDCH_COMPLETE_IND (DWORD)(GRRC_EVENT_BASE + 17)
+#define GRR_RRC_REL_PS_CNF (DWORD)(GRRC_EVENT_BASE + 18)
+#define GRR_RRC_REL_PS_IND (DWORD)(GRRC_EVENT_BASE + 19)
+#define DL_UNIT_DATA_IND (DWORD)(GRRC_EVENT_BASE + 20)
+#define DL_DATA_IND (DWORD)(GRRC_EVENT_BASE + 21)
+#define DL_DATA_REJ (DWORD)(GRRC_EVENT_BASE + 22)
+#define DL_ESTABLISH_IND (DWORD)(GRRC_EVENT_BASE + 23)
+#define DL_ESTABLISH_CON (DWORD)(GRRC_EVENT_BASE + 24)
+#define DL_IRAT_HO_CON (DWORD)(GRRC_EVENT_BASE + 25)
+#define DL_RELEASE_IND (DWORD)(GRRC_EVENT_BASE + 26)
+#define DL_RELEASE_CON (DWORD)(GRRC_EVENT_BASE + 27)
+#define DL_SUSPEND_CON (DWORD)(GRRC_EVENT_BASE + 28)
+#define MDL_ERROR_IND (DWORD)(GRRC_EVENT_BASE + 29)
+#define URRC_HO_INFO_RES (DWORD)(GRRC_EVENT_BASE + 30)
+#define URRC_HO_CNF (DWORD)(GRRC_EVENT_BASE + 31)
+#define URRC_HO_REJ (DWORD)(GRRC_EVENT_BASE + 32)
+#define RR_HO_REQ (DWORD)(GRRC_EVENT_BASE + 33)
+#define RR_VSD_INFO (DWORD)(GRRC_EVENT_BASE + 34)
+#define DL_SENDCMP_IND_EV (DWORD)(GRRC_EVENT_BASE + 35)
+#define GRR_RRC_POWEROFF_IND_EV (DWORD)(GRRC_EVENT_BASE + 36)
+#define T3110 (DWORD)(GRRC_EVENT_BASE + 37)
+#define T3124 (DWORD)(GRRC_EVENT_BASE + 38)
+#define GRRC_T3230_EV (DWORD)(GRRC_EVENT_BASE + 39) // R9 UPDATE
+#define T3148 (DWORD)(GRRC_EVENT_BASE + 40)
+
+ /* END OF RRC */
+
+/* START OF GRR */
+#define RRMN_MEAS_RESULTS_REQ (DWORD)(GRR_EVENT_BASE + 0)
+#define RR_TESTPARAM_REQ (DWORD)(GRR_EVENT_BASE + 1)
+#define RR_EM_CELL_INFO_REQ (DWORD)(GRR_EVENT_BASE + 2)
+#define RR_ACT_REQ (DWORD)(GRR_EVENT_BASE + 3)
+#define RR_CELL_PARAMETER_REQ (DWORD)(GRR_EVENT_BASE + 4)
+#define RR_CLASSMARK_IND (DWORD)(GRR_EVENT_BASE + 5)
+#define RR_DEACT_REQ (DWORD)(GRR_EVENT_BASE + 6)
+#define RR_HPLMN_ACT_REQ (DWORD)(GRR_EVENT_BASE + 7)
+#define RR_PCH_PREFERENCE_REQ (DWORD)(GRR_EVENT_BASE + 8)
+#define RR_PLMN_ABORT_REQ (DWORD)(GRR_EVENT_BASE + 9)
+#define RR_PLMN_REQ (DWORD)(GRR_EVENT_BASE + 10)
+#define RR_UPDATE_PLMN_REQ (DWORD)(GRR_EVENT_BASE + 11)
+#define RR_INACTIVE_REQ (DWORD)(GRR_EVENT_BASE + 12)
+#define RR_HPLMN_ABORT_REQ (DWORD)(GRR_EVENT_BASE + 13)
+#define RR_EST_REQ (DWORD)(GRR_EVENT_BASE + 14)
+#define RR_UPDATE_PARAM_REQ (DWORD)(GRR_EVENT_BASE + 15)
+#define GMMRR_ASSIGN_REQ (DWORD)(GRR_EVENT_BASE + 16)
+#define GMMRR_INFO_REQ (DWORD)(GRR_EVENT_BASE + 17)
+#define GMMRR_RELEASE_REQ (DWORD)(GRR_EVENT_BASE + 18)
+#define RR_TEST_COUNT_REQ (DWORD)(GRR_EVENT_BASE + 19)
+#define RRMI_START_RXSTAT_REQ (DWORD)(GRR_EVENT_BASE + 20)
+#define RRMI_END_RXSTAT_REQ (DWORD)(GRR_EVENT_BASE + 21)
+#define RRL_RR_DATA_REQ (DWORD)(GRR_EVENT_BASE + 22)
+#define RRC_GRR_EST_CNF (DWORD)(GRR_EVENT_BASE + 23)
+#define RRC_GRR_EST_FAIL (DWORD)(GRR_EVENT_BASE + 24)
+#define RRC_GRR_CHN_REL_IND (DWORD)(GRR_EVENT_BASE + 25)
+#define RRC_GRR_DEACT_CNF (DWORD)(GRR_EVENT_BASE + 26)
+#define RRC_GRR_TESTPARAM_CNF (DWORD)(GRR_EVENT_BASE + 27)
+#define RRC_GRR_MN_MEAS_CNF (DWORD)(GRR_EVENT_BASE + 28)
+#define RRC_GRR_RRAT_RXSTAT_IND (DWORD)(GRR_EVENT_BASE + 29)
+#define RRC_GRR_RRL_DATA_IND (DWORD)(GRR_EVENT_BASE + 30)
+#define RRC_GRR_RRL_ABORT_EVENT_IND (DWORD)(GRR_EVENT_BASE + 31)
+#define RRC_GRR_DTM_CNF (DWORD)(GRR_EVENT_BASE + 32)
+#define RRC_GRR_DTM_IND (DWORD)(GRR_EVENT_BASE + 33)
+#define RRC_GRR_DTM_ASS_IND (DWORD)(GRR_EVENT_BASE + 34)
+#define RRC_GRR_DTM_REJ (DWORD)(GRR_EVENT_BASE + 35)
+#define RRC_GRR_PKT_NOTI_IND (DWORD)(GRR_EVENT_BASE + 36)
+#define RRC_GRR_REL_PS_REQ (DWORD)(GRR_EVENT_BASE + 37)
+#define RRC_GRR_CONNECTED_IND (DWORD)(GRR_EVENT_BASE + 38)
+#define RRC_GRR_HO_TO_UTRAN_IND (DWORD)(GRR_EVENT_BASE + 39)
+#define RLC_GRR_ACCESS_REQ (DWORD)(GRR_EVENT_BASE + 40)
+#define RLC_GRR_UPLINK_PDCH_IND (DWORD)(GRR_EVENT_BASE + 41)
+#define RLC_GRR_REL_PDCH_CNF (DWORD)(GRR_EVENT_BASE + 42)
+#define RLC_GRR_UPLINK_PDCH_REL_IND (DWORD)(GRR_EVENT_BASE + 43)
+#define RLC_GRR_STATUS_IND (DWORD)(GRR_EVENT_BASE + 44)
+#define RLC_GRR_UPLINK_PDCH_EST_IND (DWORD)(GRR_EVENT_BASE + 45)
+#define RLC_GRR_TESTPARAM_IND (DWORD)(GRR_EVENT_BASE + 46)
+#define MAC_GRR_DOWNLINK_PDCH_IND (DWORD)(GRR_EVENT_BASE + 47)
+#define MAC_GRR_DOWNLINK_PDCH_REL_IND (DWORD)(GRR_EVENT_BASE + 48)
+#define MAC_GRR_POLLING_CNF (DWORD)(GRR_EVENT_BASE + 49)
+#define MAC_GRR_CIRCUIT_CNF (DWORD)(GRR_EVENT_BASE + 50)
+#define MAC_GRR_CIRCUIT_FAIL (DWORD)(GRR_EVENT_BASE + 51)
+#define MAC_GRR_CIRCUIT_ABORT_CNF (DWORD)(GRR_EVENT_BASE + 52)
+#define MAC_GRR_DATA_IND (DWORD)(GRR_EVENT_BASE + 53)
+#define MAC_GRR_FREQ_UPDATE_REQ (DWORD)(GRR_EVENT_BASE + 54)
+#define MAC_GRR_DEACT_CNF (DWORD)(GRR_EVENT_BASE + 55)
+#define MAC_GRR_IDLE_CHN_REQ (DWORD)(GRR_EVENT_BASE + 56)
+#define MAC_GRR_PERS_LEVEL_IND (DWORD)(GRR_EVENT_BASE + 57)
+#define MAC_GRR_START_TIMER (DWORD)(GRR_EVENT_BASE + 58)
+#define MAC_GRR_STOP_TIMER (DWORD)(GRR_EVENT_BASE + 59)
+#define MAC_GRR_TESTPARAM_IND (DWORD)(GRR_EVENT_BASE + 60)
+#define MAC_GRR_SUSPEND_CNF (DWORD)(GRR_EVENT_BASE + 61)
+#define MAC_GRR_PDCH_FAIL_IND (DWORD)(GRR_EVENT_BASE + 62)
+#define RRAT_RXSTAT_REQ (DWORD)(GRR_EVENT_BASE + 63)
+#define RRAT_CHANGE_REL_REQ (DWORD)(GRR_EVENT_BASE + 64)
+#define RR_CELL_CHANGE_REQ (DWORD)(GRR_EVENT_BASE + 65)
+#define URRC_CELL_CHANGE_CNF (DWORD)(GRR_EVENT_BASE + 66)
+#define URRC_CELL_CHANGE_REJ (DWORD)(GRR_EVENT_BASE + 67)
+#define URRC_RESEL_REJ (DWORD)(GRR_EVENT_BASE + 68)
+#define URRC_RESEL_CNF (DWORD)(GRR_EVENT_BASE + 69)
+#define URRC_SET_INACTIVE_CNF (DWORD)(GRR_EVENT_BASE + 70)
+#define RR_SET_INACTIVE_REQ (DWORD)(GRR_EVENT_BASE + 71)
+#define URRC_ABORT_READ_PREDEF_CNF (DWORD)(GRR_EVENT_BASE + 72)/*WCDMAÏÂʹÓÃ*/
+#define URRC_L1_RSRC_CNF (DWORD)(GRR_EVENT_BASE + 73)
+#define URRC_L1_RSRC_REJ (DWORD)(GRR_EVENT_BASE + 74)
+#define RR_L1_RSRC_REQ (DWORD)(GRR_EVENT_BASE + 75)
+#define RR_L1_RSRC_FREE_IND (DWORD)(GRR_EVENT_BASE + 76)
+#define RR_CELL_SEARCH_REQ (DWORD)(GRR_EVENT_BASE + 77)
+#define URRC_READ_PREDEF_CONF_CNF (DWORD)(GRR_EVENT_BASE + 78)/*WCDMAÏÂʹÓÃ*/
+#define URRC_CELL_RESEL_PARAM_IND (DWORD)(GRR_EVENT_BASE + 79)
+#define URRC_CELL_SEARCH_CNF (DWORD)(GRR_EVENT_BASE + 80)
+#define URRC_CELL_SEARCH_REJ (DWORD)(GRR_EVENT_BASE + 81)
+#define RR_RESEL_REQ (DWORD)(GRR_EVENT_BASE + 82)
+/* ========================================================================
+ MMIA¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_EM_HO_INFO_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 0)
+#define MMIA_SELL_STAT_ONE_PDP_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 1)
+#define MMIA_SELL_STAT_SUM_PDP_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 2)
+#define MMIA_SELL_STAT_REG_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 3)
+#define MMIA_AOC_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 4)
+#define MMIA_ZGDT_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 5)
+#define MMIA_SOFTRESET_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 6)
+#define MMIA_ZULRTIND_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 7)
+
+/*´¥·¢ÏûÏ¢*/
+#define MSGTRACEPS_CELL_DISPLAY_REQ_EV (DWORD)(PS_ROADTEST_EVENT_BASE + 0)
+#define ROADTEST_UEINFO_REQ_EV (DWORD)(PS_ROADTEST_EVENT_BASE + 1)
+#define MSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV (DWORD)(PS_ROADTEST_EVENT_BASE + 2)
+
+/*WCDMA PS_ROADTEST_RSP_EVENT =300*/
+#define AT_INFO_RECEIVED_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 18)
+#define AT_INFO_SENT_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 19)
+#define WRLC_UL_DATAPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 20)
+#define WRLC_DL_DATAPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 21)
+#define WRLC_UL_CTRLPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 22)
+#define WRLC_DL_CTRLPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 23)
+#define PDCP2WRLC_DATA_IND_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 24)
+#define PDCP2WRLC_DATA_REQ_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 25)
+#define WMAC_UL_UPA_TB_INFO_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 26)
+
+#ifdef BTRUNK_SUPPORT
+/**************************************************PS LTE BTrunk msg range start********************************************************/
+/* ATI --> TSM */
+#define ATI_TSM_REG_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 1)
+#define ATI_TSM_CALL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 2)
+#define ATI_TSM_CALLCONFIRM_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 3)
+#define ATI_TSM_CALLCONNECT_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 4)
+#define ATI_TSM_CALLRLS_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 5)
+#define ATI_TSM_FLOOR_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 6)
+#define ATI_TSM_FLOORRLS_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 7)
+#define ATI_TSM_STUNINFO_QUERY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 8)
+#define ATI_TSM_GROUPINFO_QUERY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 9)
+#define ATI_TSM_SCANGROUPINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 10)
+#define ATI_TSM_SCANSWITCH_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 11)
+#define ATI_TSM_SHAKEHAND_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 12)
+#define ATI_TSM_SHORT_DATA_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 13)
+#define ATI_TSM_LOCATINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 14)
+#define ATI_TSM_SETABILITY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 15)
+#define ATI_TSM_CALLFORWARD_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 16)
+#define ATI_TSM_CALLMODIFY_RSP_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 17)
+#define ATI_TSM_CALLMODIFY_REJ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 18)
+
+/* TSM --> ATI */
+#define ATI_TSM_FLOORGRT_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 25)
+#define ATI_TSM_FLOORRLS_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 26)
+#define ATI_TSM_FLOORRLS_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 27)
+#define ATI_TSM_FLOORREJ_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 28)
+#define ATI_TSM_FLOORWAIT_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 29)
+#define ATI_TSM_FLOORINFORM_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 30)
+#define ATI_TSM_STUNINFO_QUERY_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 31)
+#define ATI_TSM_STUNINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 32)
+#define ATI_TSM_GROUPINFO_QUERY_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 33)
+#define ATI_TSM_GROUPINFO_UPDATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 34)
+#define ATI_TSM_GROUPCALL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 35)
+#define ATI_TSM_SCANGROUPINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 36)
+#define ATI_TSM_SHAKEHAND_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 37)
+#define ATI_TSM_SHORT_DATA_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 38)
+#define ATI_TSM_LOCATINFO_TYPE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 39)
+#define ATI_TSM_FALLBACK_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 40)
+#define ATI_TSM_REG_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 41)
+#define ATI_TSM_REGSTATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 42)
+#define ATI_TSM_CALL_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 43)
+#define ATI_TSM_CALLRLS_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 44)
+#define ATI_TSM_CALL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 45)
+#define ATI_TSM_CALLPROCEED_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 46)
+#define ATI_TSM_CALLALERTING_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 47)
+#define ATI_TSM_CALLCONNECTACK_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 48)
+#define ATI_TSM_CALLRLS_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 49)
+#define ATI_TSM_SPEAKINGTIMEROUT_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 50)
+#define ATI_TSM_VIDEOSOURCE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 51)
+#define ATI_TSM_SCANGROUPINFO_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 52)
+#define ATI_TSM_SRSTATUS_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 53)
+#define ATI_TSM_CALLHOLD_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 54)
+#define ATI_TSM_PTTBEAR_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 55)
+#define ATI_TSM_BUSY_ALERTING_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 56)
+#define ATI_TSM_CALLFORWARD_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 57)
+#define ATI_TSM_CALLMODIFY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 58)
+#define ATI_TSM_CALLMODIFY_ACK_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 59)
+#define ATI_TSM_REGEXTINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 60)
+#endif
+#endif
+
diff --git a/patch/17.09_19.00/code/new/upstream/pub/include/ps_phy/psevent.h b/patch/17.09_19.00/code/new/upstream/pub/include/ps_phy/psevent.h
new file mode 100755
index 0000000..4a1897b
--- /dev/null
+++ b/patch/17.09_19.00/code/new/upstream/pub/include/ps_phy/psevent.h
@@ -0,0 +1,5174 @@
+/*****************************************************************************
+ *°æ±¾ËùÓÐ (C)2007ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
+ * Ä£¿éÃû £ºPUB
+ * ÎļþÃû £ºpsEvent.h
+ * Îļþ±êʶ£º
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+ * ×÷Õß £º
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+ *
+ * Ð޸ļǼºÅ ÈÕÆÚ ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+ 1 2008.02.23 ½ºè 1)ÐÒéÕ»ÐèÒªºÍCOMNEON´úÂ뻥ͨ£¬ÆäʼþºÅ¶¨ÒåΪ16λ¡£¹ÊÏÞÖÆÐÒéջʼþºÅÓÐЧ·¶Î§ÎªµÍ16λ¡£
+ 2 2008.05.14 ½ºè 1)Ôö¼ÓÁËSCIÓëURRC/CCÖ®¼äµÄʼþºÅ¶¨Òå
+ 3 2008.05.15 ½ºè 1)Ôö¼ÓÁËCCÓëURRC¼äµÄʼþºÅ¶¨Òå:GMMAS_CALLTYPENOTIFYREQ_EV
+ 4 2008.05.19 ½ºè 1Ôö¼ÓTAFÓëL1G¼äµÄʼþºÅ¶¨Òå
+ 5 2008.05.29 ½ºè 1)Ôö¼ÓGSM²âÊÔÄ£¿é¼äʼþºÅ
+ 6 2008.06.05 ½ºè 1)Ôö¼ÓGVAR_SCI_GETREQ_EV¡¢GVAR_SCI_GETCNF_EV¡¢CSCI_CONFIGREL_EV
+ 7 2008.06.12 ½ºè 1)Ôö¼ÓATIÓëCSD¼äµÄʼþºÅ¶¨Òå
+ 8 2008.06.12 ½ºè 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁË£º
+ LLGMM_USERDATAPRESENT_EV;
+ GMMAS_ASSIGNREQ_EV¡¢GMMAS_INFOREQ_EV¡¢GMMAS_SUSPENDIND_EV
+ CPDI_SENDDATAIND_EV£»
+ SM_PDCP_RATACTIND_EV¡¢SM_PDCP_RATACTRSP_EV¡¢SM_PDCP_RATDEACTIND_EV¡¢
+ SM_PDCP_RATSEQIND_EV¡¢SM_PDCP_RATSEQRSP_EV¡¢SM_PDCP_READYIND_EV£»
+ SNSM_RATDEACTRSP_EV£»
+ UMMAS_PLMNLISTREJ_EV¡¢UMMAS_PCHPRE_REQ¡¢UMMAS_ABORTHPPLMNREQ_EV¡¢
+ UMMAS_UPDATEPARAMREQ_EV¡¢UMMAS_INACTIVEREQ_EV¡¢UMMAS_INACTIVECNF_EV¡¢
+ UMMAS_RATCHNIND_EV¡¢UMMAS_HOSTARTIND_EV¡¢UMMAS_CCOSTARTIND_EV
+ 9 2008.06.14 ½ºè 1)Ôö¼ÓTOOL_NGMAC_PMO_REQ_EV¡¢TOOL_NGMAC_PSI_REQ_EV¶¨Òå
+ 2)¸üÃû£ºUMMAS_PCHPRE_REQ £½¡·UMMAS_PCHPREREQ_EV
+ 10 2008.06.16 ËïÒÔÀ× 1)Ôö¼ÓSNDCP-SMÖ®¼äʼþºÅ
+ 2)Ôö¼ÓGSMA²âÊÔʼþºÅ:GVAR_GSMA_GETREQ_EV¡¢GVAR_GSMA_GETCNF_EV
+ 11 2008.06.17 ÕÅÅô³Ì 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁËURRC-GRR¡¢URRCÄÚ²¿¡¢URRC-PHYÖ®¼äʼþºÅ
+ 12 2008.06.18 ÕÅÅô³Ì 1)Ôö¼ÓUMMAS_TRYHPPLMNCNF_EV
+ 13 2008.06.18 ½ºè 1)ÐÞ¸ÄÁËURRC-GRRÖ®¼äʼþºÅÃû³Æ
+ 14 2008.06.19 ÍõÀò 1)Ôö¼ÓSNSM_READYIND_EV,ɾ³ýSNSM_RATDEACTRSP_EV
+ 15 2008.06.20 ËïȪ 1)Ôö¼ÓTOOL_L1SIMU_DCCHFAIL_CFG_EV
+ 16 2008.06.20 ÕÅÅô³Ì 1)Ôö¼ÓURRCGRR_CAMPONCELLCNF_EV¡¢URRCGRR_CAMPONCELLIND_EV
+ 17 2008.06.30 Ç®¿¡ 1)Ôö¼ÓNGMACʼþºÅ:
+ TOOL_NGMAC_ULTBF_EST_CFG_EV ¡¢TOOL_NGMAC_DLTBF_EST_CFG_EV
+ TOOL_NGMAC_ULTBF_REL_CFG_EV ¡¢TOOL_NGMAC_DLTBF_REL_CFG_EV
+ TOOL_NGMAC_PKTTSRECFG_REQ_EV ¡¢TOOL_NGMAC_PKTTBFREL_REQ_EV
+ TOOL_NGMAC_PKTPDCHREL_REQ_EV ¡¢TOOL_NGMAC_PKTCCC_REQ_EV
+ TOOL_NGMAC_PKTCCO_REQ_EV ¡¢TOOL_NGMAC_PKTNCD_REQ_EV
+ TOOL_NGMAC_PKTPOLL_REQ_EV ¡¢TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV
+ TOOL_NGMAC_PKTPRACHPARA_REQ_EV ¡¢TOOL_NGMAC_PKTSCD_REQ_EV
+ TOOL_NGMAC_PKTQUENOTI_REQ_EV ¡¢TOOL_NGMAC_PKTACCREJ_REQ_EV
+ NGMAC_TOOL_PKTMEARPT_EV¡¢NGMAC_TOOL_PKTMOBTBFSTA_EV
+ NGMAC_TOOL_PKTPSISTA_EV ¡¢NGMAC_TOOL_PKTPAUSE_EV
+ NGMAC_TOOL_PKTEMEARPT_EV ¡¢NGMAC_TOOL_PKTADDMSRAC_EV
+ NGMAC_TOOL_PKTCCN_EV ¡¢NGMAC_TOOL_PKTSISTA_EV
+ 2)Ôö¼ÓNGRLCʼþºÅ:
+ TOOL_NGRLC_ULTBF_EST_CFG_EV ¡¢TOOL_NRLC_PUAN_REQ_EV
+ TOOL_NGRLC_DLTBF_CFG_EV ¡¢NGRLC_TOOL_DLTBF_HALF_IND_EV
+ NGRLC_TOOL_DLTBF_FINAL_IND_EV ¡¢NGRLC_TOOL_ULTBF_HALF_IND_EV
+ NGRLC_TOOL_ULTBF_FINAL_IND_EV ¡¢TOOL_NGRLC_ULTBF_REL_EV
+ NGRLC_TOOL_ULTBF_FAI_IND_EV
+ 3)À©Õ¹ÁËNGMACʼþ·¶Î§£º50-¡·100
+ 18 2008.07.02 ½¯Õ×´º 1)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄǰ׺°´AP-MMIAʼþºÅǰ׺
+ 2)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄ·¶Î§ÓÉÔÀ´µÄMMIA-NASÒƵ½AP-MMIA
+ 19 2008.07.03 ½ºè 1)Ôö¼ÓÉèÖÃNUMAC¡¢NURLCÓ¦´ð¿ØÖÆÏûÏ¢:
+ TEST_URLCACKCTRL_UTRAN_EV¡¢TEST_UMACACKCTRL_UTRAN_EV
+ 20 2008.07.19 ½ºè 1)Ôö¼ÓTOOL_L1SIMU_SYSINFOFAIL_CFG_EV¡¢
+ GMAC_GET_BLOCKS_EV¡¢GMAC_ACK_BLOCKS_EV¡¢TOOL_NGMAC_PKTPGREQ_REQ_EV
+ 2)ÐÞ¸ÄNGRLCʼþºÅ¶¨Òå
+ 21 2008.07.22 ½ºè 1)Ôö¼ÓGSMÄ£ÄâʼþºÅ·¶Î§ºê¶¨Ò壺EVENT_PS_GSM_SIMU_BEGIN/EVENT_PS_GSM_SIMU_END
+ 22 2008.07.25 ÅËÀÚ 1)Ôö¼ÓÓëTCÏà¹ØʼþºÅ¶¨Òå
+ 23 2008.08.13 ½ºè 1)Ôö¼ÓÁËUMCR-GPHYÖ®¼äµÄʼþºÅ·¶Î§¶¨Òå
+ 2)½«UMCRÓëGSM²âÁ¿Ïà¹ØʼþºÅ¶¨ÒåÒÆÈëUMCR-GPHY·¶Î§ÄÚ
+ 3)Ôö¼ÓÁËURRAÄ£¿éµÄ¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 24 2008.08.14 ÕÅÅô³Ì 1)Ôö¼ÓÁËURRC-GRR¼äURRCGRR_HOINFOCNF_EV¡¢URRCGRR_HOINFOIND_EV
+ 2)Ôö¼ÓÁ˺¯ÊýÐÅÁî¸ú×ÙʼþºÅ·¶Î§ºÍURRCÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+ 25 2008.08.15 ÌÀÔ±¦ 1)Ôö¼ÓURRCINTRA_RADIOLINKFAIL_IND_EVÏûÏ¢
+ 26 2008.08.18 ÍõÀò 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_RXLEVREQ_CFG_EV
+ L1SIMU_TOOL_SYNCREQ_CFG_EV
+ L1SIMU_TOOL_SYSREQ_CFG_EV
+ L1SIMU_TOOL_IDLEMODEREQ_CFG_EV
+ L1SIMU_TOOL_NCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_SCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_MEAS_REPORT_CFG_EV
+ L1SIMU_TOOL_DLTBFRELIND_EV
+ L1SIMU_TOOL_ULTBFRELIND_EV
+ 2)Ôö¼ÓNGMACʼþºÅ£ºTOOL_NGMAC_CTRLBLOCK_REQ_EV
+ ʯ×ÚÀ¤ 1)Ôö¼ÓURRAÓëTD PHYÖ®¼äʼþºÅ¶¨Òå
+ 2)Ôö¼ÓL1G-GSMAÖ®¼äʼþºÅ¶¨Òå
+ ×ÞÑÞ 1)Ôö¼ÓGMMAS_CCSYNCIND_GSM_EVʼþºÅ
+ ÕŽ¡ 1)Ôö¼ÓNLAPDMºÍTRSÖ®¼äÓÃÓÚ²»Í¬SAPI¼äÏûÏ¢·¢ËͺÍÒì³£²âÊÔµÄʼþºÅ¶¨Òå
+ NLAPDM_L2_DATA_IND_EV
+ NLAPDM_TOOL_SABM_IND_EV
+ TOOL_NLAPDM_UA_RSP_EV
+ NLAPDM_TOOL_SABM_COR_IND_EV
+ TOOL_NLAPDM_UA_COR_RSP_EV
+ TOOL_NLAPDM_EXCEPT_DATA_EV
+ NLAPDM_TOOL_I_IND_EV
+ ׿Խ 1)Ôö¼ÓURRC_FUNC_SUSPENDMEASREQ_EV
+ 27 2008.08.20 ʯ×ÚÀ¤ 1)Ôö¼ÓL1GÐÅÁî¸ú×ÙʼþºÅ¶¨Ò壺L1G_ST_....
+ 2)Ôö¼ÓURRA-GPHYʼþºÅ·¶Î§¶¨Òå
+ 28 2008.08.30 ½ª²¨ 1)ÓÉÓÚ´¦Àí¸ÕפÁôijСÇø1SÄÚ²»ÄܶԲâÁ¿¸üºÃµÄСÇø½øÐÐÖØÑ¡£¬Ôö¼ÓUCSR_TCAMP1S_EXPIRY_EV
+ Ç®¿¡ 2)Ôö¼ÓGSMÐÅÁî¸ú×ÙʼþºÅ¶¨Òå¡£
+ 29 2008.09.03 ½ºè 1)L1G_GSMA_EVENT_BASE/L1G_GSMA_EVENT_END ÐÞ¸ÄΪ£ºL1G_DM_EVENT_BASE/L1G_DM_EVENT_END
+ 2)L1GË«Ä£ÏûϢǰ׺¸ü¸ÄΪ£ºL1G_DM_
+ 3)Ôö¼ÓÁËL1G_DM_TDD_CELL_MEAS_REQ
+ 4)Ôö¼ÓÁËL1SIMU_TOOL_TAFIND_EV¡¢L1SIMU_TOOL_TAFREQ_EV
+ 30 2008.09.16 ÍõÀò 1)Ôö¼Ó3Gʱ,UMMÏòRBCÅäÖÃÑ°ºôµÄÇëÇóʼþºÅ£º
+ UMMAS_PAGEREQ_EV
+ 31 2008.09.19 ½ºè 1)SDLÈÎÎñºÍÆÕͨÈÎÎñ¼äÏûÏ¢¶¨ÒåͳһÔÚSIG_CODE.HÖУ¬ÏÂÁкêÃû±»ÒÆ×ߣº
+ L1G_DM_DEACT_UMTS_REQ¡¢L1G_DM_DEACT_GSM_CNF
+ L1G_DM_TDD_CELL_MEAS_REQ¡¢L1G_UTRAN_MEAS_PERIOD_IND
+ 2)ɾ³ýÁË£º
+ L1G_DM_EVENT_BASE¡¢L1G_DM_EVENT_END
+ P_GSM_INACT_TIME_REQ_EV¡¢P_ABORT_GSM_GAP_REQ_EV¡¢P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ 32 2008.09.22 ÍõС½ø 1)Ôö¼ÓAP_MMIA_SMSABORTMOREQ_EV¡¢MMIASMS_ABORTMOREQ_EV
+ 33 2008.10.10 ÍõÀò 1)Ôö¼ÓUMMAS_PWRONREQ_EV
+ 34 2008.10.15 Íõ¾´Ò¢ 1)Ôö¼ÓNGMACʼþºÅ:
+ NGMAC_TOOL_CCF_IND_EV
+ 35 2008.10.24 ʯ×ÚÀ¤ 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV¡¢
+ L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV
+ 36 2008.11.05 ½ºè 1)ÐÞ¸ÄËùÓÐZ_ǰ׺Ϊ
+ 37 2008.11.13 ÍõÀò 1)Ôö¼ÓGMM_TPOWEROFF_EXPIRY_EV:2G¹Ø»ú¼à¿ØÈ¥»îÁ÷³Ì¶¨Ê±Æ÷
+ 38 2008.11.17 ÑîÎÄÇ¿ 1)È¡ÏûÏûÏ¢NGRLC_START_TIMER_EV(²»ÔÙʹÓÃ)
+ 2)Ôö¼Ó ÏûÏ¢NGRLC_TOOL_DLTBF_FAI_IND_EV¡¢TOOL_NGRLC_BEGINTESTMODE_EV¡¢NGRLC_TOOL_PDANNOTIFY_EV
+ 39 2008.11.27 ¸ßÏè 1)Ôö¼ÓCUMAC_GETTVBOCMPIND_EV£¬ÒÔ֪ͨUMCRÄ£¿é²ÉÑùÍê³É£¬¿ÉÒÔ½øÐÐÏà¹ØÆÀ¹ÀºÍ±¨¸æ¡£
+ ΤÓñÕä 1)Ôö¼ÓP_GSM_MEAS_DONE_REQ_EV
+ 40 2008.11.28 ׿Խ 1)ɾ³ýÁËMAC²âÁ¿²¿·ÖÐÅÁî¸ú×ÙÏûÏ¢URRC_FUNC_SUSPENDMEASREQ_EV,URRC_FUNC_TVMEASREQ_EV,URRC_FUNC_QUAMEASREQ_EV,URRC_FUNC_UEINTERMEASREQ_EV,
+ URRC_FUNC_RESUMEMEASREQ_EV,URRC_FUNC_MACRPT_EV,URRC_FUNC_TVDISTRIBUTE_EV,URRC_FUNC_QUADISTRIBUTE_EV,URRC_FUNC_UEINTERDISTRIBUTE_EV
+ 41 2008.12.10 ½¯Õ×´º 1)Ôö¼ÓUMMAS_ABORTCNF_EV
+ 42 2008.12.29 ½ºè 1)Ϊ֧³Ö½Å±¾¿ØÖÆCSDÒµÎñ£¬Ôö¼ÓTEST_TAFDATAIND_UTRAN_EV
+ ¸ßÏè148725 1)ÐÞ¸ÄSM¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 2)Ôö¼ÓMMIASM_PDPAUTOACTIND_EV
+ 43 2008.12.31 ×ÞÑÞ 1)Ôö¼ÓÁËCC¶¨Ê±Æ÷ʼþºÅ £ºCC_TMMCONN_EXPIRY_EV ¼à¿ØMMÁ¬½ÓµÄ½¨Á¢
+ 44 2009.02.10 ÑîÔÊ 1)Ôö¼ÓÁËMMÄ£¿é¶¨Ê±Æ÷ÏûÏ¢£ºMM_T3231_EXPIRY_EV¡¢MM_T3232_EXPIRY_EV
+ 45 2009.02.12 ½ºè 1)TAFÓëL1GÏûÏ¢¶¨ÒåÒÆÈëSIG_CODE.H£¬É¾³ýTAF_L1GÏûÏ¢·¶Î§
+ 2)Ôö¼ÓTAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢£ºTAF_FUNC_L1GDATAREQ_EV
+ 46 2009.02.16 ÍõС½ø 1)UMMÐÂÔöATÃüÁIMSI¼¤»îÈ¥»îÇëÇ󡢶ÔÁ½¸öÓòͬʱ½øÐÐÈ¥»îµÄÇëÇó¡¢ÉèÖÃGPRS×Ô¶¯¸½×ÅÇëÇó£¬
+ Ôö¼ÓÏûÏ¢¶¨Ò壺AP_MMIA_ZATTSETREQ_EV¡¢AP_MMIA_ZATTQUERYREQ_EV¡¢
+ AP_MMIA_ZGAATSETREQ_EV¡¢AP_MMIA_ZGAATQUERYREQ_EV¡¢
+ AP_MMIA_ZATTQUERYCNF_EV¡¢AP_MMIA_ZGAATQUERYCNF_EV
+ 47 2009.02.19 Ëﳤ½ 1)MM/GMM/CC£RRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºGMMAS_CSRABRELIND_EV;
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_ABORTCFGREQ_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_ACTTIMENOTIFY_REQ_EV£»
+ 48 2009.02.21 ×ÞÑÞ 1)Ö§³ÖMODIFY¹ý³Ì£¬Ôö¼ÓCCÓëTAFʼþºÅ¶¨Ò壺
+ CCTAF_PEND_REQ_EV¡¢CCTAF_RESUME_REQ_EV¡¢CCTAF_MODIFYBC_REQ_EV¡¢CCTAF_MODIFYBC_CNF_EV
+ 2)Ôö¼ÓCC¶¨Ê±Æ÷ʼþºÅ¶¨Ò壺
+ CC_TRELTAF_EXPIRY_EV
+ CC_TCONNTAF_EXPIRY_EV
+ CC_TSYNCIND_EXPIRY_EV
+ CC_TMODIFYBC_EXPIRY_EV
+ 49 2009.02.24 ½»¶ 1)Ϊ֧³ÖUSAT¹¦ÄÜ£¬Ôö¼ÓMMIAÓëATI/UICCÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_USAT_ENVELOPREQ_EV
+ AP_MMIA_USAT_ENVELOPCNF_EV
+ AP_MMIA_USAT_TERMNLRSPREQ_EV
+ AP_MMIA_USAT_TERMNLPROFREQ_EV
+ AP_MMIA_USAT_PROCMDIND_EV
+ AP_UICC_USAT_ENVELOPREQ_EV
+ AP_UICC_USAT_ENVELOPCNF_EV
+ AP_UICC_USAT_TERMNLRSPREQ_EV
+ AP_UICC_USAT_TERMNLPROFREQ_EV
+ AP_UICC_USAT_COMMONCNF_EV
+ AP_UICC_USAT_PROVCMDIND_EV
+ 50 2009.03.05 ÍõС½ø 1)UICCNOCARDIND²»ÔÙÉϱ¨¸øATI£¬ËùÒÔɾ³ýAP_MMIA_UICCNOCARDIND_EV
+ 51 2009.03.10 ½ºè Ôö¼ÓÖ§³ÖCBS¹¦ÄÜ
+ 1)Ôö¼ÓMMIA-ATI¡¢MMIA-CBSÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_CBS_CSCBSETREQ_EV
+ AP_MMIA_CBS_CSCBREADREQ_EV
+ AP_MMIA_CBS_SAVINGSETREQ_EV
+ AP_MMIA_CBS_RESTORESETREQ_EV
+ AP_MMIA_CBS_CSCBREADCNF_EV
+ AP_MMIA_CBS_TCBMIND_EV
+ AP_MMIA_CBS_PCBMIND_EV
+ AP_MMIA_CBS_TCBMLISTCNF_EV
+ AP_MMIA_CBS_PCBMLISTCNF_EV
+ AP_MMIA_CBS_TCBMREADCNF_EV
+ AP_MMIA_CBS_PCBMREADCNF_EV
+ MMIACBS_ACTIVATEREQ_EV
+ MMIACBS_ACTIVATECNF_EV
+ MMIACBS_DATAIND_EV
+ 2)CBSÏà¹ØATÃüÁî¶ÔÓ¦ÏûÏ¢´ÓAP-MMIA SMS²¿·Ö¶¨ÒåÖÐɾ³ý£º
+ AP_MMIA_SMSCSCBREQ_EV
+ AP_MMIA_SMSCSASREQ_EV
+ AP_MMIA_SMSCRESREQ_EV
+ AP_MMIA_SMSTCBMIND_EV
+ AP_MMIA_SMSTCBMREADCNF_EV
+ AP_MMIA_SMSCSCBCNF_EV
+ AP_MMIA_SMSCSASCNF_EV
+ AP_MMIA_SMSCRESCNF_EV
+ AP_MMIA_SMSTCBMLISTCNF_EV
+ 3)CBSÓëURBCµÄÖ®¼äµÄʼþºÅ¶¨Òå:
+ CBSAS_NODRXREQ_EV
+ CBSAS_DRXRSVREQ_EV
+ CBSAS_STOPREQ_EV
+ CBSAS_PCHCELLINFOIND_EV
+ 4)CBSÓëUMMÖ®¼äµÄʼþºÅ¶¨ÒåµÄ¶¨Òå:
+ UMMCBS_STARTREQ_EV
+ UMMCBS_STOPREQ_EV
+ UMMCBS_CELLINFOIND_EV
+ 5)CBS¶¨Ê±Æ÷ÏûϢʼþºÅµÄ¶¨Òå:
+ CBS_TSCHEDCHECK_EXPIRY_EV
+ 6)Ôö¼ÓURBCÓëURLCÖ®¼ä½Ó¿Ú¶¨Ò壺
+ CURLC_CBSRBCONFIGREQ_EV
+ 7)Ôö¼ÓURBCÓëPHYÖ®¼ä½Ó¿Ú¶¨Ò壺
+ P_CBS_NODRX_REQ_EV
+ P_CBS_DRX_REQ_EV
+ P_ADD_MODIFY_CBS_REQ_EV
+ P_STOP_CBS_REQ_EV
+ 52 2009.03.20 ÍõС½ø 1)Ôö¼ÓÖ§³ÖATÃüÁ+ZUSTAT,+ZURDY,+ZUSLOT,+ZPINSTAT
+ AP_MMIA_UICCCOMMANDREQ_EV
+ AP_MMIA_UICCCOMMANDQUERYCNF_EV
+ 53 2009.03.23 ÍõС½ø 1)Ôö¼ÓÏûÏ¢£º
+ AP_MMIA_USAT_LOCINFOCNF_EV
+ AP_MMIA_USAT_LOCINFOREQ_EV
+ 54 2009.03.31 ½»¶ 1)Ôö¼ÓÖ§³Ö¹¤³Ìģʽ£º
+ AP_MMIA_EM_CELLINFOREQ_EV
+ AP_MMIA_EM_CELLINFOQUERYREQ_EV
+ AP_MMIA_EM_LOCKCELLREQ_EV
+ AP_MMIA_EM_HOINFOREQ_EV
+ AP_MMIA_EM_HOINFOQUERYREQ_EV
+ AP_MMIA_EM_CELLINFOIND_EV
+ AP_MMIA_EM_CELLINFOQUERYCNF_EV
+ AP_MMIA_EM_HOINFOIND_EV
+ AP_MMIA_EM_HOINFOQUERYCNF_EV
+ MMIAUMM_EM_LOCKCELLREQ_EV
+ MMIAUMM_EM_LOCKCELLCNF_EV
+ MMIAAS_EM_CELLINFOREQ_EV
+ MMIAAS_EM_HOINFO_REQ
+ MMIAAS_EM_UCELLINFOIND_EV
+ MMIAAS_EM_UHOINFOIND_EV
+ UMMAS_LOCKCELLREQ_EV
+ UMMAS_UNLOCKCELLREQ_EV
+ UMMAS_LOCKCELLCNF_EV
+ MMIA_EM_HOINFO_EXPIRY_EV
+ UMCR_EM_CELLINFO_EXPIRY_EV
+ 55 2009.04.02 ΤÓñÕä 1)ÐÞ¸ÄÐźÅÇ¿¶ÈÉϱ¨·½Ê½£¬Ôö¼Ó£º
+ AP_MMIA_RXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVQUERYREQ_EV
+ AP_MMIA_RXLEVCNF_EV
+ AP_MMIA_ZRPTRXLEVIND_EV
+ AP_MMIA_ZRPTRXLEVQUERYCNF_EV
+ MMIAAS_RPTRXLEV_REQ_EV
+ MMIAAS_QUERYRXLEV_REQ_EV
+ MMIAAS_RPTRXLEV_IND_EV
+ MMIAAS_QUERYRXLEV_IND_EV
+ ɾ³ý:
+ MMIAMCR_RPTPRDREQ_EV
+ MMIAMCR_RSSIIND_EV
+ AP_MMIA_CSQEXEREQ_EV
+ AP_MMIA_ZSQSETREQ_EV
+ AP_MMIA_ZSQQUERYREQ_EV
+ AP_MMIA_ZSQIND_EV
+ AP_MMIA_CSQEXECNF_EV
+ AP_MMIA_ZSQQUERYCNF_EV
+ 56 2009.04.13 ½ºè 1)ΪÔö¼ÓL1GÓëPHYÖ®¼ä˫ģʼþºÅ¶¨Ò壺
+ P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ P_GSM_INACT_TIME_REQ_EV
+ P_ABORT_GSM_GAP_REQ_EV
+ 2)ºô½ÐÐÅÏ¢Éϱ¨£º
+ AP_MMIA_CCPROCINFOIND_EV
+ MMIACC_PROCINFOIND_EV
+ 3)Ϊ±ÜÃⲻͬ½á¹¹¶ÔӦͬÃûÏûÏ¢£¬Ôö¼Ó£º
+ TEST_UURLCDATAIND_UTRAN_EV
+ TEST_UURLCCONFIGREQ_UTRAN_EV
+ 57 2009.05.08 ½ª²¨ 1)Ôö¼ÓUMCRͬUCSRÖ®¼ä֪ͨÁÚÇø¸ü¸ÄµÄURRCÄÚ²¿Ê¼þºÅ:
+ URRCINTRA_NEIBCELLCHGIND_EV
+ 58 2009.05.11 ½ª²¨ 1)ɾ³ýUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CAMPONCELLREQ_EV
+ URRCGRR_CAMPONCELLCNF_EV
+ URRCGRR_CAMPONCELLIND_EV
+ URRCGRR_CAMPONCELLRSP_EV
+ 2)Ôö¼ÓUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CELLRESELREQ_EV
+ URRCGRR_ANYCELLRESELREQ_EV
+ URRCGRR_CELLRESELIND_EV
+ URRCGRR_CELLRESELREJ_EV
+
+ 59 2009.05.19 ½¯Õ×´º 1)Ôö¼ÓUMMͬGSMAÖ®¼äµÄʼþºÅ
+ UMMAS_GSMSRVNOTIFYREQ_EV
+ 60 2009.05.20 Ëﳤ½ 1)URLC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCURLC_CONFIGCNF_EV£»
+ ɾ³ýÏûÏ¢ºÅCURLC_STOPREQ_EV£»
+ 2)URRC/CC£SCIÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCSCI_CONFIGCNF_EV£»
+ 3)PDCP£URRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCPDCP_CONFIGCNF_EV£»
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_FACHCFGREQ_EV£»
+ URRCINTRA_FACHCFGIND_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_CONTINUEREQ_EV£»
+
+ 61 2009.5.22 ËïÒÔÀ× 1)Ôö¼ÓGSMA¶¨Ê±Æ÷µÄʼþºÅ¶¨Òå
+ GSMA_PROCTIMER_EXPIRY_EV
+ GSMA_INACTTIMER_EXPIRY_EV
+
+ 62 2009.06.04 ʷѧºì 1)PDCP£URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£º
+ CPDCP_RELOCREJ_EV
+ CPDCP_RELOCCOMPIND_EV
+ CPDCP_RELOCFAILIND_EV
+ CPDCP_DLPDUSIZECHANGEREQ_EV
+ CPDCP_DLPDUSIZECHANGECNF_EV
+ CPDCP_ROHCTARGETMODEREQ_EV
+ 2)PDCP£URRC ÏûÏ¢ºÅ¶¨Òåɾ³ý£º
+ CPDCP_RELOCCOMPREQ_EV
+
+ 63 2009.06.22 ΤÓñÕä 1)ÐÂÔöMACUL->MACDLÏûÏ¢£º
+ CUMAC_NOTIFYDLPERIODREPORTREQ_EV
+ 2)ɾ³ýÒÔÏÂÏûÏ¢£º
+ CUMAC_MEASRELREQ_EV
+ CUMAC_MEASREPORTIND_EV
+ CUMAC_PERIODMEASDELNOTIFYREQ_EV
+ CUMAC_GETTVBOCMPIND_EV
+ 3)ÐÂÔöRRCÓëUMAC½Ó¿ÚÏûÏ¢£º
+ CUMAC_TRAFFICMEASREQ_EV
+ CUMAC_QUANLITYMEASREQ_EV
+ CUMAC_INTERNALMEASREQ_EV
+ CUMAC_TVMEASRELREQ_EV
+ CUMAC_QMEASRELREQ_EV
+ CUMAC_UEMEASRELREQ_EV
+ CUMAC_TVMEASRESUMEREQ_EV
+ CUMAC_TVMEASSUSPENDREQ_EV
+ CUMAC_DLMEASSUSPENDREQ_EV
+ CUMAC_DLMEASRESUMEREQ_EV
+ CUMAC_ADDTVMEASREPORTREQ_EV
+ CUMAC_ADDQMEASREPORTREQ_EV
+ CUMAC_ADDUEMEASREPORTREQ_EV
+
+65 2009.06.23 ÑîÔÊ 1)Ôö¼ÓGMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ GMM_TWSPN_EXPIRY_EV
+ GMM_TWCRS_EXPIRY_EV
+ GMM_TWTRG_EXPIRY_EV
+
+66 2009.06.24 ½ºè 1)ÐÞ¸ÄTEST_GVAR_XXXΪGVAR_XXX
+ 2)ÖØÐÂÕûÀíÁ˲âÊÔÏûϢʼþ¶¨Ò巶Χ
+ 3)Ôö¼ÓÁËNCBSÏà¹ØÏûÏ¢¶¨Ò壺£¨½ªéª£©
+ TEST_UCBSSCHEDCFG_UTRAN_EV
+ TEST_UCBSDATAREQ_UTRAN_EV
+ TEST_UCBSOUTPUTEND_UTRAN_EV
+ TEST_UCBSUMAC_TFSCFG_UTRAN_EV
+ TEST_UCBSUMAC_SFNINFO_UTRAN_EV
+ TEST_UURLCDATACNF_UTRAN_EV
+ TOOL_L1SIMU_CBSBLK_START_EV
+ TOOL_L1SIMU_CBSFSTBLK_REQ_EV
+ TOOL_L1SIMU_CBSOTHERBLK_REQ_EV
+
+67 2009.06.29 QIANJUN155488 1)Ôö¼ÓÓû§ÃæÐÅÁî¸ú×ÙαÏûÏ¢¶¨Òå
+ ATIPDI_DATAREQ_TRACE_EV
+ UPDI_DATAREQ_TRACE_EV
+ SN_DATA_REQ_TRACE
+ SN_UNITDATA_REQ_TRACE
+ LL_DATA_REQ_TRACE
+ LL_UNITDATA_REQ_TRACE
+ LLC_GET_NEXT_PDU_TRACE_EV
+ GMAC_GET_BLOCKS_TRACE_EV
+ GMAC_ACK_BLOCKS_TRACE_EV
+ PDCP_UPDATA_TRACE_EV
+ URLC_GETBO_TRACE_EV
+ URLC_SENDPDU_TRACE_EV
+ UMAC_TFCSEL_TRACE_EV
+ PH_MAC_DATA_IND_TRACE
+ PH_RLC_DATA_IND_TRACE
+ MAC_RLC_DATA_IND_TRACE
+ RLC_DATA_IND_TRACE
+ RLC_UNITDATA_IND_TRACE
+ LL_DATA_IND_TRACE
+ LL_UNITDATA_IND_TRACE
+ SN_DATA_IND_TRACE
+ SN_UNITDATA_IND_TRACE
+ UPDI_DATAIND_TRACE_EV
+ ATIPDI_DATAIND_TRACE_EV
+ UUMAC_DATAIND_TRACE_EV
+ PDCP_DOWNDATA_TRACE_EV
+ TAF_COUNTER_TRACE_EV
+ TAF_RLP_XID_ULFRAME_TRACE_EV
+ TAF_RLP_XID_DLFRAME_TRACE_EV
+ TAF_RLP_SABM_ULFRAME_TRACE_EV
+ TAF_RLP_SABM_DLFRAME_TRACE_EV
+ TAF_RLP_UA_ULFRAME_TRACE_EV
+ TAF_RLP_UA_DLFRAME_TRACE_EV
+ TAF_RLP_DISC_ULFRAME_TRACE_EV
+ TAF_RLP_DISC_DLFRAME_TRACE_EV
+ TAF_RLP_DM_ULFRAME_TRACE_EV
+ TAF_RLP_DM_DLFRAME_TRACE_EV
+ TAFL1G_DATA_IND_TRACE_EV
+ TAFL1G_DATA_REQ_TRACE_EV
+ TAF_FUNC_UURLCDATAIND_EV
+ TAF_FUNC_UURLCDATAREQ_EV
+68 2009.7.2 ½»¶ 1)Ϊ֧³ÖÖÐÒÆËæEÐÐATÃüÁÔö¼ÓÏÂÁÐÏûÏ¢£º
+ AP_UICC_PINENABLEQUERYREQ_EV
+ AP_UICC_PINENABLEQUERYCNF_EV
+ AP_UICC_PINSTATQUREYREQ_EV
+ AP_UICC_PINSTATQUREYCNF_EV
+ AP_UICC_CARDMODEREQ_EV
+ AP_UICC_CARDMODECNF_EV
+ AP_MMIA_SETPINAPPLREQ_EV
+ AP_MMIA_SETPINAPPLCNF_EV
+ AP_MMIA_PINAPPLREADREQ_EV
+ AP_MMIA_PINAPPLREADCNF_EV
+ AP_MMIA_CPINREQ_EV
+ AP_MMIA_CPINREADREQ_EV
+ AP_MMIA_CPINREADCNF_EV
+ AP_MMIA_CARDMODEREQ_EV
+ AP_MMIA_CARDMODECNF_EV
+ AP_MMIA_MODEREQ_EV
+ AP_MMIA_MODECNF_EV
+69 2009.7.15 ½ºè 1)Òƶ¯L1G_ST_EVENT·¶Î§µ½SIGTRACE_EVENT·¶Î§ÄÚ
+ 2)Ôö¼ÓGVAR_CBS_GETREQ_EV¡¢GVAR_CBS_GETCNF_EV
+70 2009.7.17 Áõµ¤ 1)Ôö¼ÓURRC-URLCµÄʼþºÅ:
+ CURLC_SETDATANOTIFYMODE_EV
+ CURLC_PCHULDATATRREQ_EV
+71 2009.7.21 ½»¶ 1)ɾ³ý£º
+ AP_MMIA_ZBDMDSETREQ_EV
+ AP_MMIA_ZBDMDQUERYREQ_EV
+ AP_MMIA_ZBDMDQUERYCNF_EV
+ 2)ÐÂÔö£º
+ AP_MMIA_ZACTSETREQ_EV
+ AP_MMIA_ZACTQUERYREQ_EV
+ AP_MMIA_ZACTQUERYCNF_EV
+ AP_MMIA_MODEQRYREQ_EV
+ AP_MMIA_MODEQRYCNF_EV
+ AP_MMIA_MODESETREQ_EV
+72 2009.7.23 ÍõÀò 1)Ôö¼Ó£¬UMCRÔÚ½øÈë·ÉÐÐģʽʱ£¬Í¨ÖªURRCA½øÈë¿ÕÏеÄÏûÏ¢£º
+ P_GSM_MEAS_TONULL_REQ_EV
+73 2009.7.28 ΤÓñÕä 1)Ö§³ÖÈý°æÐб꣬Ôö¼ÓURRCÄÚ²¿Ê¼þºÅURBC-UMCR: URRCINTRA_DRXCHGIND_EV
+ Ôö¼ÓUMCR-URRCAµÄʼþºÅ: P_GSM_MEAS_DRX_CHANGE_REQ_EV
+74 2009.7.28 ʷѧºì 1)Ôö¼ÓNPDCP_EVENT_BASE¡¢NPDCP_EVENT_END
+ 2)Ôö¼ÓNPDCPʼþºÅ£º
+ CPDCP_CONFIGREQ_UTRAN_EV
+ CPDCP_RELEASEREQ_UTRAN_EV
+ NPDCP_DATAREQ_UTRAN_EV
+ NPDCP_DATAIND_UTRAN_EV
+ TEST_NPDCP_DATAERRIND_UTRAN_EV
+ TEST_NPDCP_DATACNF_UTRAN_EV
+75 2009.8.11 ÍõÀò CC/SM/SS²¿·ÖÓëATIÓÅ»¯½Ó¿ÚÐÞ¸Ä
+ 1)Ôö¼ÓºÍÐÞ¸ÄCCÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ Ôö¼Ó£ºAP_MMIA_CCQUERYREQ_EV/AP_MMIA_RINGIND_EV/AP_MMIA_CRINGIND_EV/AP_MMIA_CCWAIND_EV
+ AP_MMIA_MOCALLSSNOTIFY_EV/AP_MMIA_MTCALLSSNOTIFY_EV/AP_MMIA_CCQUERYCNF_EV/AP_MMIA_CLIPIND_EV
+ AP_MMIA_CRIND_EV/AP_MMIA_CCSETREQ_EV/AP_MMIA_COLPIND_EV/MMIACC_CSTAQUERYREQ_EV
+ MMIACC_CSTASETREQ_EV/MMIACC_CSTAQUERYCNF_EV/AP_MMIA_MODTOMULTMEDIARSP_EV
+ AP_MMIA_MODTOMULTMEDIAIND_EV/MMIACC_MODTOMULTMEDIARSP_EV/MMIACC_MODTOMULTMEDIAIND_EV
+ ɾ³ý£ºAP_MMIA_CRLPSETREQ_EV/AP_MMIA_CRLPQUERYREQ_EV/AP_MMIA_CHSNSETREQ_EV/AP_MMIA_CHSNQUERYREQ_EV
+ AP_MMIA_ETBMSETREQ_EV/AP_MMIA_ETBMQUERYREQ_EV
+ AP_MMIA_CCSETREQ_EV/AP_MMIA_CCSETUPIND_EV/AP_MMIA_CCCOMMANDCNF_EV/AP_MMIA_SSNOTIFYIND_EV
+ AP_MMIA_CHSNQUERYCNF_EV/AP_MMIA_DSQUERYCNF_EV/AP_MMIA_ETBMQUERYCNF_EV/AP_MMIA_CRLPQUERYCNF_EV
+ AP_MMIA_CCCAUSEQUERYREQ_EV/AP_MMIA_CCCAUSEQUERYCNF_EV
+
+ 2)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£º AP_MMIA_SMQUERYREQ_EV¡¢AP_MMIA_SMHANDLEREQ_EV¡¢AP_MMIA_SMANSREQ_EV
+ AP_MMIA_SMPDPADDRREQ_EV¡¢AP_MMIA_SMNEGQOSREQ_EV¡¢AP_MMIA_SMMODEMMOREQ_EV¡¢
+ AP_MMIA_SMMODEMANSREQ_EV¡¢AP_MMIA_SMCAUSEREQ_EV¡¢AP_MMIA_SMCANCELREQ_EV¡¢
+ AP_MMIA_SMQUERYPDPINFOREQ_EV¡¢AP_MMIA_SMQUERYCNF_EV¡¢AP_MMIA_SMHANDLECNF_EV¡¢
+ AP_MMIA_SMANSCNF_EV¡¢AP_MMIA_SMPDPADDRCNF_EV¡¢AP_MMIA_SMNEGQOSCNF_EV¡¢
+ AP_MMIA_SMMODEMMOCNF_EV¡¢AP_MMIA_SMMODEMANSCNF_EV¡¢AP_MMIA_SMCAUSECNF_EV¡¢
+ AP_MMIA_SMMTDEACTIVATEIND_EV¡¢AP_MMIA_SML2PIND_EV¡¢AP_MMIA_SMQUERYPDPINFOCNF_EV
+ Ôö¼Ó£ºAP_MMIA_SMREADREQ_EV¡¢AP_MMIA_SMQUERYPDPSTATUSREQ_EV¡¢AP_MMIA_SMQUERYACTCIDREQ_EV¡¢
+ AP_MMIA_SMQUERYDEFCIDREQ_EV¡¢AP_MMIA_SMQUERYPDPADDRREQ_EV¡¢AP_MMIA_SMQUERYNEGQOSREQ_EV¡¢
+ AP_MMIA_SMQUERYNEGEQOSREQ_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV¡¢AP_MMIA_SMACTDEACTREQ_EV¡¢
+ AP_MMIA_SMMODREQ_EV¡¢AP_MMIA_SMMTACTANSREQ_EV¡¢AP_MMIA_SMIPPDPACTREQ_EV¡¢
+ AP_MMIA_SMOPENCHRSP_EV¡¢AP_MMIA_SMQUERYIDLECHRSP_EV¡¢AP_MMIA_SMGETPCORSP_EV¡¢
+ AP_MMIA_SMQUERYPDPSTATUSCNF_EV¡¢AP_MMIA_SMQUERYACTCIDCNF_EV¡¢AP_MMIA_SMQUERYDEFCIDCNF_EV¡¢
+ AP_MMIA_SMQUERYPDPADDRCNF_EV¡¢AP_MMIA_SMQUERYNEGQOSCNF_EV¡¢AP_MMIA_SMQUERYNEGEQOSCNF_EV¡¢
+ AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMACTDEACTCNF_EV¡¢AP_MMIA_SMMODCNF_EV¡¢
+ AP_MMIA_SMCGEVIND_EV¡¢AP_MMIA_SMIPPDPACTCNF_EV¡¢AP_MMIA_SMOPENCHIND_EV¡¢
+ AP_MMIA_SMCLOSECHIND_EV¡¢AP_MMIA_SMQUERYIDLECHIND_EV¡¢AP_MMIA_SMGETPCOIND_EV¡¢
+ AP_MMIA_SMCONNECTIND_EV¡¢AP_MMIA_SMNOCARRIERCNF_EV
+
+ 3)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£ºAP_MMIA_CAAPTESTREQ_EV/AP_MMIA_CFCSQUERYREQ_EV/AP_MMIA_CPPSEXEREQ_EV/AP_MMIA_CFCSTESTREQ_EV
+ AP_MMIA_CAAPQUERYREQ_EV/AP_MMIA_CPPSEXECNF_EV/AP_MMIA_CFCSQUERYCNF_EV/AP_MMIA_CFCSTESTCNF_EV
+ Ôö¼Ó£ºAP_MMIA_COLRQUERYREQ_EV/AP_MMIA_COLRQUERYCNF_EV
+ ÆÁ±ÎÔÝδʵÏÖ¹¦ÄܵÄʼþºÅ£ºAP_MMIA_CAEMLPPSETREQ_EV /AP_MMIA_CAEMLPPQUERYREQ_EV /AP_MMIA_CFCSSETREQ_EV
+ AP_MMIA_CAAPSETREQ_EV/AP_MMIA_CAEMLPPQUERYCNF_EV /AP_MMIA_CAAPQUERYCNF_EV
+ AP_MMIA_CAAPTESTCNF_EV
+
+ 4)Ôö¼ÓIMEI/IMSI²éѯºÍ֤ʵµÄÏûϢʼþºÅ AP_MMIAÖ®¼ä
+ AP_MMIA_QUERYIMSIREQ_EV/AP_MMIA_QUERYIMEIREQ_EV/AP_MMIA_QUERYIMSICNF_EV/AP_MMIA_QUERYIMEICNF_EV
+
+ 5)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯µÄʼþºÅ MMIASSÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ Ôö¼Ó:MMIASS_COLRREADREQ_EV/MMIASS_ABORTREQ_EV/MMIASS_COMMONCNF_EV/SS_WAIT_TIMER_EXPIRY_EV
+ MMIASS_CUSDMTIND_EV
+
+ ɾ³ý:MMIASS_CAEMLPPSETREQ_EV/MMIASS_CAEMLPPREADREQ_EV/MMIASS_CPWDSETCNF_EV/MMIASS_CCFCSETCNF_EV
+ MMIASS_CCWASETCNF_EV/MMIASS_CAEMLPPSETCNF_EV/MMIASS_CAEMLPPREADCNF_EV/MMIASS_FORWARDCHECK_IND_EV
+ SS_T5000_EXPIRY_EV/MMIASS_CUSDUNSCNF_EV
+
+ 6)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯µÄʼþºÅ MMIASMÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ ɾ³ý:
+ MMIASM_PDPSTATUSREQ_EV¡¢MMIASM_NEGQOSREQ_EV¡¢MMIASM_PDPADDRREQ_EV¡¢
+ MMIASM_CAUSEREQ_EV¡¢MMIASM_PDPACTREJ_EV¡¢MMIASM_QUERYPDPINFOREQ_EV¡¢
+ MMIASM_PDPDEACTIVATEIND_EV¡¢MMIASM_PDPSTATUSCNF_EV¡¢MMIASM_NEGQOSCNF_EV¡¢
+ MMIASM_PDPADDRCNF_EV¡¢MMIASM_CAUSECNF_EV¡¢MMIASM_QUERYPDPINFOCNF_EV
+ SM_ATHRELEASE_EXPIRY_EV¡¢AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV
+ Ôö¼Ó:
+ MMIASM_QUERYNEGQOSREQ_EV¡¢MMIASM_QUERYNEGEQOSREQ_EV¡¢MMIASM_QUERYACTCIDREQ_EV¡¢
+ MMIASM_QUERYPDPSTATUSREQ_EV¡¢MMIASM_QUERYPDPADDRREQ_EV¡¢MMIASM_QUERYPDPCAUSEREQ_EV¡¢
+ MMIASM_MTACTANSREQ_EV¡¢MMIASM_IPPDPACTREQ_EV¡¢MMIASM_OPENCHRSP_EV¡¢
+ MMIASM_QUERYIDLECHRSP_EV¡¢MMIASM_GETPCORSP_EV¡¢MMIASM_QUERYNEGQOSCNF_EV¡¢
+ MMIASM_QUERYNEGEQOSCNF_EV¡¢MMIASM_QUERYACTCIDCNF_EV¡¢MMIASM_QUERYPDPSTATUSCNF_EV¡¢
+ MMIASM_QUERYPDPADDRCNF_EV¡¢MMIASM_QUERYPDPCAUSECNF_EV¡¢MMIASM_CGEVIND_EV¡¢
+ MMIASM_IPPDPACTCNF_EV¡¢MMIASM_OPENCHIND_EV¡¢MMIASM_CLOSECHIND_EV¡¢
+ MMIASM_QUERYIDLECHIND_EV¡¢MMIASM_GETPCOIND_EV¡¢MMIASM_COMMONCNF_EV¡¢
+ MMIASM_CONNECTIND_EV¡¢MMIASM_NOCARRIERCNF_EV
+ SM_AUTOANSMTACT_EXPIRY_EV
+ 7)Ôö¼ÓAP_MMIA_CAUSEQUERYREQ_EV, AP_MMIA_CAUSEQUERYCNF_EV
+ ɾ³ýAP_MMIA_SMSABORTMOREQ_EV/AP_MMIA_ABORTSEARCHPLMNREQ_EV
+
+76 2009.9.10 ºÎ½¨Î° 1)Ôö¼ÓLTEÖÆʽÏÂÏà¹ØµÄʼþºÅ
+ ½»¶ 2)½«AP_MMIA_EVENT_UICC_ENDºêÖµÔö¼Ó1
+
+77 2009.9.16 ÓÈ±ó ½«SIG_CODE.HÖÐÔÀ´²¿·ÖSDLÏûÏ¢£¨ÕâЩÏûÏ¢µÄÔ´ºÍÄ¿Ç°Ä£¿é¶¼¸ÄΪÁËÆÕͨÈÎÎñ£©µÄ¶¨Ò壬¸ÄΪÆÕͨÈÎÎñÏûÏ¢µÄ¶¨Òå
+
+78 2009.9.27 ÍõС½ø ΪʵÏÖ´æ´¢¹ÜÀí¹¦ÄÜÔö¼ÓÈçÏÂÏûÏ¢:
+ AP_MMIA_SMSCPMSTESTREQ_EV,AP_MMIA_SMSZMENAREQ_EV,AP_MMIA_SMSCPMSTESTCNF_EV,
+ AP_MMIA_CPBSTESTREQ_EV,AP_MMIA_CPBRSETENDCNF_EV,AP_MMIA_CPBSTESTCNF_EV,
+ AP_MMIA_PBPREFMSGSTOREQ_EV,AP_MMIA_PBPREFMSGSTOTESTREQ_EV,AP_MMIA_PBTPMRUPDATEREQ_EV,
+ AP_MMIA_PBMEMCAPAREQ_EV,AP_MMIA_PBMTPARAIND_EV,AP_MMIA_PBEMERNUMLISTIND_EV,
+ AP_MMIA_PBSTOSETREQ_EV,AP_MMIA_PBSTOTESTREQ_EV,AP_MMIA_PBFINDINDEXENDCNF_EV,
+ AP_MMIA_PBPREFMSGSTOCNF_EV,AP_MMIA_PBPREFMSGSTOTESTCNF_EV,AP_MMIA_PBCOMMONCNF_EV ,
+ AP_MMIA_PBINITCMPLTIND_EV,AP_MMIA_ZPBICIND_EV,
+
+79 2009.9.28 ΤÓñÕä ±ÜÃâ3GÖ÷ģʽÏ£¬¸ø³öGAPºó£¬ÓÖ·¢ÆðËæ»ú½ÓÈë¹ý³Ì¶øµ¼ÖµÄÉäƵͬÇÀ¶øÔö¼ÓµÄÏûÏ¢:
+ CUMAC_URRCAMEASSUSPENDREQ_EV
+ CUMAC_URRCAMEASRESUMEREQ_EV
+ P_GSM_RACH_ACTIVE_CNF_EV
+80 2009.9.28 ½ª²¨ Ôö¼ÓUSIRÖÜÆÚÐÔ½ÓÊÕϵͳÐÅÏ¢µÄ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ:
+ USIR_TIMER_R_EXPIRY_EV
+
+81 2009.9.28 ³Â¹â»ª 1)AP-MMIA SMSÏûÏ¢ºÅ¶¨Ò壬Ôö¼Ó
+ AP_MMIA_CPMSTESTREQ_EV
+ AP_MMIA_CPMSTESTCNF_EV
+ AP_MMIA_SMSZPBICIND_EV
+82 2009.9.28 ½¯Õ×´º 1)Ôö¼ÓUMM/GSMA½Ó¿ÚÏûÏ¢UMMAS_TBFRELEASEIND_EV
+ 2)Ôö¼ÓUMM¶¨Ê±Æ÷ÏûÏ¢UMM_TLIST_EXPIRY_EV
+
+83 2009.9.28 ½»¶ 1¡¢Ôö¼Ó»ñÈ¡PSDEVÊý¾ÝʼþºÅ
+ GVAR_UICC_DEV_GETREQ_EV
+ GVAR_UICC_DEV_GETCNF_EV
+ 2¡¢Ôö¼Ó¹Ø¿¨È·ÈÏÏûÏ¢£ºAP_UICC_PWROFFCNF_EV
+ 3¡¢È¡Ïû¹Ø¿¨¶¨Ê±Æ÷ÏûÏ¢£ºUICC_TIMER_EXPIRY_EV
+84 2009.9.29 ½»¶ 1¡¢Ôö¼ÓPBʼþºÅ
+ AP_MMIA_PBSTOTESTCNF_EV
+85 2009.9.30 ʯ×ÚÀ¤ 1¡¢AP-MMIA¼äʼþºÅÒÑʹÓÃÁË510¸ö£¬ÐèÔö¼ÓAP_MMIA_EVENT_BASEµÄ¿Õ¼ä£¬´Ó500£>600
+
+86 2009.10.19 ÑîÔÊ 1¡¢ Ôö¼ÓMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺 MM_TWRRR_EXPIRY_EV
+87 2009.10.27 Ç®¿¡ 1)Ϊ֧³ÖEGPRS,Ôö¼Ó2GÍø²àÄ£ÄâʼþºÅNGMAC_NGRLC_EPDAN_IND_EV,
+ NGRLC_NGRLC_PUAN_REQ_EV,NGRLC_FILL_DATA_QUEUE_REQ_EV,L1SIMU_NGRLC_DATA_IND_EV
+88 2009.10.27 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+89 2009.11.09 ÑîÔÊ 1¡¢Ôö¼ÓÁËMMIAºÍUMMÖ®¼äÔö¼ÓSYSCONFIGÏà¹ØÏûÏ¢ºê¶¨Ò壺
+ MMIAUMM_SYSCONFIGREQ_EV¡¢MMIAUMM_COMMONCNF_EV£»
+ 2¡¢Ôö¼ÓÁËUMMºÍASÖ®¼äϵͳÅäÖÃÏûÏ¢ºê¶¨Ò壺
+ UMMAS_UPDATESYSCONFIGREQ_EV ¡£
+90 2009.11.12 ½ª²¨/Ëﳤ½ ×Óϵͳ·½°¸ÐÞ¸Ä
+ 1.USIR_TBCCHMOD_EXPIRY_EV,UCSR_TBARGSMCELL_EXPIRY_EV
+ 2.URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨ÒåÖÐÔö¼ÓÏûÏ¢ºÅ:
+ URRC_FUNC_RELSCCPCHSTOPMACREQ_EV
+ URRC_FUNC_RESUMEFACHCFGREQ_EV
+91 2009.11.17 ³Â¹â»ª
+ MMIA£SMSÏûÏ¢ºÅ¶¨ÒåÖÐÐÂÔö£ºMMIASMS_COMMONCNF_EV
+
+92 2009.11.17 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+93 2009.11.18 ÑîÎÄÇ¿ Ôö¼ÓEDGEÖ§³ÖµÄÏà¹ØʼþºÅ:
+ TOOL_NGRLC_MODE_CFG_REQ_EV£¬NGRLC_TOOL_UL_DATABLOCK_IND_EV £¬
+ TOOL_NGRLC_DUMMYBLOCK_REQ_EV £¬DOWNLINK_DUMMY_BLOCK_REQ_EV£¬
+ TOOL_NGRLC_DOWNLINKBLOCK_REQ_EV
+94 2009.12.14 ÑîÔÊ Ôö¼Ó¼à¿ØÑ°ºôµÄ¶¨Ê±Æ÷ÏûÏ¢ºÅ:(CQNJ00137720)
+ GMM_TPAGE_EXPIRY_EV, MM_TWPGR_EXPIRY_EV;
+
+95 2009.12.16 ÍõС½ø 1)Ôö¼ÓËæEÐÐÏà¹ØʼþºÅ:
+ MMIACC_CLOSEVOICECHNLIND_EV,MMIACC_OPENVOICECHNLIND_EV,AP_MMIA_PBSFINDINDEXCNF_EV
+ AP_MMIA_PBSFINDINDEXENDCNF_EV,AP_MMIA_PBSEDITCNF_EV,AP_MMIA_PBSCPBRTESTCNF_EV,
+ AP_MMIA_PBSCPBWTESTCNF_EV,AP_MMIA_PBCNUM_CNF,AP_MMIA_PBCLCKSTATUSCNF_EV
+ AP_MMIA_PBSFINDINDEXREQ_EV,AP_MMIA_PBSEDITREQ_EV,AP_MMIA_PBCNUM_REQ
+ AP_MMIA_PBCLCKSETREQ_EV,AP_MMIA_PBSCPBRTESTREQ_EV,AP_MMIA_PBSCPBWTESTREQ_EV
+ AP_MMIA_PBUICCOKIND_EV,AP_MMIA_SCPBRSETCNF_EV ,AP_MMIA_SCPBRSETENDCNF_EV
+ AP_MMIA_SCPBRTESTCNF_EV,AP_MMIA_SCPBWTESTCNF_EV ,AP_MMIA_CNUMCNF_EV
+ AP_MMIA_SCPBRSETREQ_EV ,AP_MMIA_SCPBRTESTREQ_EV,AP_MMIA_SCPBWTESTREQ_EV
+ AP_MMIA_SCPBWSETREQ_EV ,AP_MMIA_CNUMREQ_EV ,AP_UICC_CRSM_CNF_EV
+ AP_UICC_COMMONCNF_EV,
+ 2)ÐÞ¸ÄPB,UICCʼþºÅ·¶Î§Öµ:
+ AP_MMIA_PB_RSP_EVENT,AP_MMIA_EVENT_PB_END
+ AP_MMIA_EVENT_UICC_END,AP_UICC_EVENT_END
+
+96 2009.12.07 ³ÂÎÄ Ôö¼Ó¶ÁдIMEIµÄʼþºÅTEST_SET_NV_DATA_IMEI_EV
+ Ôö¼ÓCRSMÃüÁîʼþºÅAP_UICC_CRSM_REQ_EV
+ Ôö¼ÓUICCÄ£¿éµÄͨÓÃʼþºÅ AP_UICC_COMMONCNF_EV
+
+97 2010.01.05 ΤÓñÕä Ôö¼ÓURRCINTRA_GETSERVCELLINFO_EV,ÒÔ±ãÔÚMSGTRACEÖÐÏÔʾʵʱСÇøÐÅÏ¢
+
+98 2010.01.08 Ëïºóɽ Ôö¼ÓPDIµãµÆºÍÏúÁ¿Í³¼Æ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ PDI_SWITCHLEDTIMER_EXPIRY_EV£¬
+ PDI_WAITDNSACKTIMER_EXPIRY_EV£¬
+ PDI_WAITZSSACKTIMER_EXPIRY_EV£¬
+
+99 2010.01.09 ÍõС½ø 1)Ôö¼ÓÏúÁ¿Í³¼ÆÏà¹ØʼþºÅ:
+ AP_MMIA_SELL_STAT_SWITCHSETREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYREQ_EV,AP_MMIA_SELL_STAT_UDPINFOQUERYREQ_EV
+ AP_MMIA_SELL_STAT_TESTSENDREQ_EV,AP_MMIA_SELL_STAT_DOMAINSETREQ_EV,AP_MMIA_SELL_STAT_DOMAINQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_CRCSETREQ_EV,AP_MMIA_SELL_STAT_CRCQUERYREQ_EV,AP_MMIA_SELL_STAT_DEBUGSETREQ_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYREQ_EV,AP_MMIA_SELL_STAT_PORTSETREQ_EV,AP_MMIA_SELL_STAT_PORTQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_TRITYPEQUERYREQ_EV,AP_MMIA_SELL_STAT_DNSCNTQUERYREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_UDPINFOQUERYCNF_EV,AP_MMIA_SELL_STAT_DOMAINQUERYCNF_EV,AP_MMIA_SELL_STAT_CRCQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYCNF_EV,AP_MMIA_SELL_STAT_PORTQUERYCNF_EV,AP_MMIA_SELL_STAT_TRITYPEQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DNSCNTQUERYCNF_EV,MMIASM_CIDDEACTIND_EV,MMIAPDI_SELLSTAT_STARTSENDPACKETIND_EV,
+ MMIAPDI_SELLSTAT_ABORTIND_EV,MMIA_SELLSTAT_ONEPDP_EXPIRY_EV,MMIA_SELLSTAT_SUMPDP_EXPIRY_EV,
+ MMIA_SELLSTAT_REG_EXPIRY_EV
+ ÐÞ¸ÄAP_MMIA_UICC_RSP_EVENT£¬AP_MMIA_EM_RSP_EVENT
+ 2) Ôö¼ÓZIMGE,ZGIIDFʼþºÅ
+ AP_MMIA_ZIMGREQ_EV,AP_MMIA_ZGIIDFREQ_EV,AP_MMIA_ZIMGCNF_EV,AP_MMIA_ZGIIDFCNF_EV
+ 3)´æ´¢ÁоÙÏûÏ¢µÄ֪ͨÏûÏ¢
+ AP_MMIA_PBCPBRIND_EV,AP_MMIA_PBCPBFIND_EV,AP_MMIA_PBSCPBRIND_EV,AP_MMIA_PBCMGLIND_EV
+
+100 2010.01.21 ʯ×ÚÀ¤ ½«UMCR-UPHY¸ÄΪUMACÉÏÏÂÐÐÁ½¶Î£¬Í¬Ê±½«ÏÂÁÐÏûÏ¢IDµÄ»ùµØÖ·¶¨Òå´ÓUMCR-UPHY¸ÄΪUMAC_DL-UPHY£º
+ P_QUALITY_MEAS_REQ_EV
+ P_UE_INTERNAL_MEAS_REQ_EV
+ P_QUALITY_MEAS_IND_EV
+ P_UE_INTERNAL_MEAS_IND_EV
+
+101 2010.02.05 ³ÂÎÄ Ôö¼ÓUICCʼþºÅ
+ UICC_CARDDETECT_EXPIRY_EV
+ AP_UICC_UICCUNSYNCIND_EV
+
+102 2010.02.20 ÕÅÅô³Ì Ôö¼ÓL1TʼþºÅ
+ P_ABORT_FREQ_SCAN_CNF_EV,P_ABORT_CELL_SEARCH_CNF_EV,P_BCH_RELEASE_CNF_EV,
+ P_CAMPON_A_CELL_CNF_EV,P_CHECK_RF_IND_EV£¨´¦ÀíÉäƵ³åÍ»£©,P_DPCH_CFG_FINAL_EV£¨¸ÃÏûÏ¢²»·¢µ½DPRAM£©,
+ P_DPCH_REL_CNF_EV,P_REL_SCCPCH_CNF_EV,P_STOP_PAGING_CNF_EV,P_STOP_CBS_CNF_EV
+ P_REL_HSDPA_CNF_EV,P_REL_HSUPA_CNF_EV,P_ACTIVE_IND_EV£¨´¦Àí¼¤»îʱ¼äµ½£©
+ P_RACH_PRCEDURE_CNF_EV,P_ERUCCH_PRCEDURE_CNF_EV
+
+103 2010.02.20 YANGYUN ÐÞ¸ÄÖÆʽ¼äÖØÑ¡£¬Ìí¼ÓʼþºÅ£º
+ UMMAS_CELLRESSTARTIND_EV
+
+104 2010.03.09 ʯ×ÚÀ¤ ÐÞ¸ÄL1TµÄÈýÌõÏûÏ¢ID£º
+ P_DPCH_CFG_FINAL_EV¸ÄΪP_L1_RESOURCE_CFG_FINAL_EV
+ P_RACH_PRCEDURE_CNF_EV¸ÄΪP_RACH_PROCEDURE_CNF_EV
+ P_ERUCCH_PRCEDURE_CNF_EV¸ÄΪP_ERUCCH_PROCEDURE_CNF_EV
+
+101 2010 .03.11 ׿Խ/ºÎ« Ôö¼ÓÏûÏ¢£º
+ URRCINTRA_GETNCELLINFO_EV
+ MSGTRACEPS_CELLDISPLAYREQ_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+
+102 2010 .03.12 ËïȪ Ôö¼ÓÏûÏ¢£º
+ MMIASS_USSDCANCELREQ_EV
+
+103 2010 .03.17 ³Â¹â»ª Ôö¼ÓSMS¶¨Ê±Æ÷ʼþºÅ£º
+ SMS_TWSI_EXPIRY_EV
+
+104 2010.3.30 ×ÞÑÞ Ôö¼Ó2GÏÂTCHÊÍ·ÅʱGSMAÉϱ¨¸øCCµÄÏûÏ¢
+ GMMAS_CCTCHRELIND_GSM_EV
+
+105 2010 .04.04 ½ª²¨ ÐÞ¸ÄÁбí¹ý³Ìʱ³¤Ïà¹ØÐÞ¸Ä
+ ½«PS_UMMAS_ABORTPLMNREQ_EV ÐÞ¸ÄΪ UMMAS_STOPPLMNLISTREQ_EV
+ ½«UMMAS_ABORTCNF_EV ÐÞ¸ÄΪ UMMAS_ABORTHPPLMNCNF_EV
+ Ôö¼Ó³¬Ê±ÏûÏ¢: UMM_TPLMNLIST_EXPIRY_EV
+
+106 2010 .04.06 ½ª²¨ Ôö¼ÓURRCÄÚ²¿Ê¼þºÅ£º
+ URRCINTRA_SENDBUFESTREQ_EV
+ URRCINTRA_ABORTCCOREQ_EV
+
+107 2010 .04.13 ½ª²¨ Ð޸ı»BAR´¦ÀíÏà¹Ø£¬Ôö¼ÓÁ½¸öʼþºÅ
+ URRCINTRA_BARRESUMEIND_EV
+ UCSR_TBARFREQ_EXPIRY_EV
+
+108 2010 .04.23 ½»¶ ÐÞ¸ÄSUBMODE,Ôö¼ÓʼþºÅ
+ MMIAAS_SUBMODEIND_EV
+
+ 109 2010 .04.24 ËÕá° Ôö¼ÓUMAC-ULÏòUMAC-DL֪ͨÏÂÐÐÅäÖõı仯
+ CUMAC_ACTDLCFG_EV
+
+110 2010.04.29 ½¯Õ×´º Ôö¼ÓUMM¶ÔMMIAËÑÍøÇëÇóµÄ»Ø¸´£¬Ê¼þºÅ
+ MMIAUMM_SEARCHPLMNCNF_EV
+
+111 2010.04.30 ½¯Õ×´º ɾ³ý UMM_TPROC_EXPIRY_EV
+ Ôö¼Ó UMM_TUICCINIT_EXPIRY_EV
+ UMM_TCAMP_EXPIRY_EV
+ UMM_TDETACH_EXPIRY_EV
+
+ 112 2010 .05.04 ʯ×ÚÀ¤ Ôö¼ÓR7Ö§³Ö
+
+ 113 2010.05.14 Éòº® Ôö¼ÓGSMA֪ͨUCSR2GפÁô³É¹¦µÄָʾ
+ URRCGRR_GSMCAMPSUCCIND_EV
+
+ 114 2010.05.20 ʯ×ÚÀ¤ UICCÏûÏ¢ÒѾ³¬³öÔÓеÄÇø¼ä£¬Õ¼ÓÃÁËÆäËûÄ£¿éµÄÏûÏ¢Çø¼ä£¬µ÷ÕûUICCµÄÏûÏ¢Çø¼ä
+
+115 2010.05.22 ÑîÔÊ Ôö¼ÓCS¡¢PS¸½×Å״̬²éѯÏûÏ¢
+ MMIAUMM_CGATTQUERYREQ_EV
+ MMIAUMM_ZATTQUERYREQ_EV
+ MMIAUMM_CGATTQUERYCNF_EV
+ MMIAUMM_ZATTQUERYCNF_EV
+
+116 2010.05.25 ÑîÔÊ Ôö¼ÓUMM֪ͨGMMÖÆʽ¸ü¸Ä³É¹¦ÏûÏ¢
+ UMM_RATCHNIND_EV
+
+ 117 2010 .05.24 ÍõС½ø Ôö¼ÓAP_MMIA_ESMTFADTESTREQ_EV
+ AP_MMIA_ESMTFADTESTCNF_EV
+
+ 118 2010 .05.29 ³ÂÎÄ Ôö¼Ó£º
+ AP_UICC_ACTIVEORDEACTIVEFILEREQ_EV¡¢AP_UICC_ACTIVEORDEACTIVEFILECNF_EV
+
+119 2010.06.07 ʯ×ÚÀ¤ ÐÞ¸ÄÉϱ¨MSGTRACE·þÎñСÇøºÍÁÚÇøµÄ·½Ê½
+ Ôö¼Ó£ºMSGTRACEPS_SCELLINFOIND_EV£¨·þÎñСÇøÐÅÏ¢£©¡¢MSGTRACEPS_NCELLINFOIND_EV£¨ÁÚÇøÐÅÏ¢£©
+ ɾ³ýÔÓеÄÏûÏ¢£º
+ URRCINTRA_GETSERVCELLINFO_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+ URRCINTRA_GETNCELLINFO_EV
+
+120 2010.06.08 ÍõС½ø ΪUSATÃüÁîÔÚ90 00ʱÔö¼ÓÖ÷¶¯Éϱ¨ÏûÏ¢
+ AP_UICC_NOPROCNOTIFYIND_EV, AP_MMIA_USAT_NOPROCNOTIFYIND_EV
+
+121 2010.06.08 ʯ×ÚÀ¤ ½«RRAT_RXSTAT_IND¡¢RRMI_RXSTAT_IND¡¢RR_EM_HO_INFO_IND¡¢RR_EM_CELL_INFO_IND
+ ÒƵ½PSEVENT.HÖÐÈ¥
+121 2010.07.02 ÍõÀò£¨Ó¦¸ßÏè148604ÒªÇóÐ޸ģ© Ôö¼Ó
+ P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV¡¢
+
+122 2010.07.08 ʯ×ÚÀ¤ ½«P_RESEL_GSMCELL_START_REQ_EV¡¢P_RESEL_GSMCELL_START_CNF_EVÌ滻Ϊ
+ P_TD_RF_REL_REQ_EV¡¢P_TD_RF_REL_CNF_EV
+ ½«P_RESEL_GSMCELL_SUCC_REQ_EV¡¢P_RESEL_GSMCELL_SUCC_CNF_EVºÍ
+ P_TD_CLOSE_REQ_EV¡¢P_TD_CLOSE_IND_EVÌ滻Ϊ
+ P_TD_RESET_REQ_EV¡¢P_TD_RESET_CNF_EV
+ ÐÂÔöP_TD_RF_RESUME_REQ¡¢P_ABORT_GSM_GAP_CNF_EV
+
+123 2010.07.08 ¸ßÏè È¥³ýÏûÏ¢¶¨ÒåP_INTER_FREQ_BLIND_MEAS_IND_EV
+
+124 2010 .07.10 ¹Ë±¦³É Ôö¼Ó£º
+ SM_PDCP_HCMODIND_EV
+
+125 2010.07.10 ΤÓñÕä Ôö¼ÓRRCÄÚ²¿Ê¼þºÅ£ºURRCINTRA_CHANGECAMPONTYPE_EV CSR֪ͨ
+ MCR ÈÎÒâפÁôתºÏÊÊפÁô»òÕßÊǺÏÊÊתÈÎÒâ
+
+126 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ MMIAESM_ABORTREQ_EV
+
+127 2010.07.10 ÕÔÕñ»Ôɾ³ýÏûÏ¢MMIAESM_MTEPSBEARERACT_CNF_EV
+
+128 2010.07.10 ÍõС½øÔö¼Ó £º
+ AP_UICC_EFSTATUSQUERYREQ_EV, AP_UICC_EFSTATUSMODIFYREQ_EV
+ AP_UICC_EFSTATUSQUERYCNF_EV,AP_UICC_EFSTATUSMODIFYCNF_EV
+
+129 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ AP_MMIA_PBCHGINDEXIND_EV
+ AP_MMIA_CHGINDEXIND_EV
+
+130 2010.07.10 ÕÔÕñ»ÔΪ×Û²âÔö¼ÓÏûÏ¢AP_MMIA_AUTOSTARTREQ_EV
+
+131 2010.08.18 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢AP_MMIA_CGEQOSSETREQ_EV¡¢AP_MMIA_CGEQOSQUERYREQ_EV
+ AP_MMIA_CGEQOSQUERYCNF_EV¡¢AP_MMIA_CGEQOSRDPREQ_EV
+ AP_MMIA_CGEQOSRDPCNF_EV¡¢MMIAESM_QUERYPDPADDRCNF_EV
+ ɾ³ýÏûÏ¢MMIAESM_ABORTREQ_EV¡¢AP_MMIA_ESMQOSQUERYREQ_EVºÍAP_MMIA_ESMQOSQUERYCNF_EV
+ µ÷ÕûMMIAºÍATIÏûÏ¢Çø¼ä
+
+132 2010.08.26 ÑîÔÊ Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATELTEACT_EV¡¢MMIAUMM_SETLTEACT_REQ_EV
+
+133 2010.09.13 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_MMIA_ZEACTSETREQ_EV¡¢AP_MMIA_ZEACTREADREQ_EVºÍ
+ AP_MMIA_ZEACTREADCNF_EV
+
+134 2010.09.14 ³Â¹â»ª Ôö¼ÓÏûÏ¢GMMAS_SAPI3RELIND_EV
+
+135 2010.09.25 ÍõС½ø ½â¾ö֪ͨSTMËø¿¨ºÍ½âËø£¬Ôö¼ÓÏûÏ¢AP_UICC_CARDLOCKSTATUSIND_EV
+
+136 2010.09.27 ÀîÎľ² Ôö¼Ó¡¢µ÷ÕûLTEÏà¹ØÏûÏ¢
+
+137 2010.10.18 Ëﳤ½ È¥µôÏûÏ¢ºÅ£ºP_CBS_NODRX_REQ_EV¡¢ P_CBS_DRX_REQ_EVµÄ¶¨Ò壻
+ ºóÃæµÄÏûÏ¢µÄʼþºÅͬʱǰÒÆ£¬ÓУºP_ADD_MODIFY_CBS_REQ_EV¡¢P_STOP_CBS_REQ_EV¡¢P_L1_RESOURCE_CFG_FINAL_EV¡¢
+ P_ADD_HSUPA_REQ_EV¡¢P_REL_HSUPA_REQ_EV¡¢P_PLCCH_ADD_MODIFY_REQ_EV
+
+137 2010.10.28 ΤÓñÕä Ôö¼ÓÏûÏ¢UMCR_TBSIC_EXPIRY_EVÖ§³ÖTD϶ÔGSMСÇøͬ²½ÐÅÏ¢µÄÓÐЧÆÚά»¤
+138 2010.10.29 ÁõÒí Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATESCANUEBANDFG_EV¡¢UMMAS_SCANUEBANDIND_EV
+ ɾ³ýÏûÏ¢£ºUCSR_TFREQSCAN_EXPIRY_EV
+
+139 2010.11.05 YANGYUN Ôö¼ÓUMM_CELLNOCHANGEIND_EV
+
+140 2010.11.15 YANGYUN Ôö¼Ó CM_RRCRELIND_EVÏûÏ¢
+
+141 2010.11.29 ÀîÎľ² ÐÞ¸ÄESM_EPDCP_EVENT_BASEµÄºê¶¨Òå
+
+142 2010.11.30 ÍõС½ø ½â¾ö¿¨³õʼ»¯¹ý³ÌÖйػú»ØÏÔ´íÎóÎÊÌ⣬Ôö¼ÓÏûÏ¢ AP_UICC_PWROFFIND_EV
+ PSDEVÐ޸ķ½°¸£¬Ôö¼ÓÏûÏ¢ AP_UICC_WRITEITEMIND_EV,AP_UICC_UPDATEITEMREQ_EV,AP_UICC_UPDATEITEMCNF_EV
+
+143 2010.12.1 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢GVAR_ATMEM_DEV_GETREQ_EV¡¢GVAR_ATMEM_DEV_GETCNF_EV¡¢GVAR_NV_DEV_GETREQ_EV¡¢
+ GVAR_NV_DEV_GETCNF_EV
+
+144 2010.12.15 ʷѧºì ɾ³ýROHCµÄ¶¨Ê±Æ÷ÏûÏ¢ROHC_FO2IRTIMER_EXPIRY_EV¡¢ROHC_SO2IRTIMER_EXPIRY_EV£¬
+ Ôö¼ÓÒ»¸öÓÉSO¡¢FOµ½IRµÄ¶¨Ê±Æ÷ÏûÏ¢£ºROHC_IRTIMER_EXPIRY_EV
+
+145 2010.12.30 Ëﳤ½ µ¥¶ÀµÄСÇø¸üйý³Ì£¬ÊÕµ½Á½ÌõTI²»Í¬µÄCUCÏûÏ¢µÄ´¦Àí£¬Ðèɾ³ý£º
+ URRCINTRA_ABORTCFGREQ_EV
+
+146 2010.12.31 ׿±Ø²¨ CQNJ00240340 PSEVENT.HÖÐÓÐЩʼþºÅ¶¨ÒåËæ×Å°æ±¾µÄÑݽøÒѾ²»ÔÙʹÓÃ
+
+147 2010.12.31 ÍõС½ø ΪÔö¼Ó¿¨SEARCH¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢ AP_UICC_PREPERSONRECSEARCHREQ_EV,AP_UICC_PREPERSNRECSRCHCNF_EV
+
+148 2011.1.28 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢MMIASM_DISCONNECTREQ_EV¡¢AP_MMIA_DISCONNECTREQ_EV
+
+149 2011.1.30 ׿±Ø²¨ EC 614000686090 ½«MMIA£SMÏûÏ¢ºÅ¶¨Òå°´ÊÇ·ñ
+ ¶ÔÓ¦ATÃüÁî·ÖÀ࣬µ÷ÕûMMIASM_ABORTREQ_EVµÈ3ÌõÏûÏ¢µÄÈ¡Öµ
+150 2011.2.11 ÍõС½ø Ôö¼ÓÏûÏ¢AP_UICC_VERIFYPIN2REQ_EV£¬AP_UICC_VERIFYPIN2CNF_EV
+
+151 2011.01.25 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢
+ AP_MMIA_CAOCSETREQ_EV ¡¢AP_MMIA_CAOCQRYREQ_EV¡¢AP_MMIA_CACMQRYREQ_EV¡¢AP_MMIA_CAMMQRYREQ_EV
+ AP_MMIA_CPUCQRYREQ_EV¡¢AP_MMIA_CCWEQRYREQ_EV¡¢AP_MMIA_CACMSETREQ_EV¡¢AP_MMIA_CAMMSETREQ_EV
+ AP_MMIA_CPUCSETREQ_EV¡¢AP_MMIA_CCWESETREQ_EV¡¢AP_MMIA_CAOCSETCNF_EV¡¢AP_MMIA_CAOCQRYCNF_EV
+ AP_MMIA_CACMQRYCNF_EV¡¢AP_MMIA_CAMMQRYCNF_EV¡¢AP_MMIA_CPUCQRYCNF_EV¡¢AP_MMIA_CCWEQRYCNF_EV
+ AP_MMIA_CCCMIND_EV¡¢AP_MMIA_CCWVIND_EV¡¢MMIACC_CCMQUERYREQ_EV¡¢MMIACC_CCMQUERYCNF_EV
+ MMIACC_CCWVIND_EV¡¢MMIACC_NOTIFYAOCTIMERIND_EV
+
+152 2011.03.01 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_UICC_ZPUKREQ_EV¡¢AP_MMIA_ZPUKREQ_EV
+
+153 2011.3.2 ÍõС½ø Ôö¼Ó¼Æ·Ñ¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢AP_UICC_INCREASEACMFAILIND_EV£¬
+ AP_UICC_INCREASEREQ_EV£¬AP_UICC_RESETACMREQ_EV
+ ¼Æ·Ñ¹¦ÄÜYUZHIMING²¹³ä CC_TACMUPD_EXPIRY_EV ,CC_TCDUR_EXPIRY_EV
+
+154 2011.3.10 ZHANGCHONG ͬ²½LTEÐÞ¸Ä
+
+155 2011.3.16 ʯ×ÚÀ¤ ÃüÃûÐÞ¸Ä
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼ÓGSM PS HOÏûÏ¢id
+ 2£©Ôö¼Ó¶àÄ£Ïà¹ØÏûÏ¢idºÍASCÏà¹ØÏûÏ¢
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼Ó¿ìËÙ˯ÃßÏûÏ¢CPDCP_SCRI_IND_EV/CPDCP_ULDATA_TRANSFER_REQ_EV
+
+157 2011.04.02 ÕÔÕñ»Ô
+ 1) ΪR9Éý¼¶Ôö¼ÓÏûÏ¢
+
+158 2011.04.23 ÕÔÕñ»Ô
+ Õë¶ÔUICCÓÅ»¯£¬É¾³ýÎÞÓõÄÏûÏ¢AP_MMIA_UICC_INFO_REQ_EV ¡¢
+ AP_MMIA_UICC_INFO_CNF_EV¡¢AP_MMIA_PIN_STATE_IND_EV
+
+159 2011.05.03 ÕÔÕñ»ÔΪ3GÃûƬ¼ÐÔö¼ÓÏûÏ¢AP_MMIA_ZCPBQ_SET_REQ_EV¡¢AP_MMIA_ZCPBQ_QUERY_REQ_EV
+ AP_MMIA_ZEER_READ_REQ_EV¡¢AP_MMIA_ZCPBQ_SET_CNF_EV¡¢AP_MMIA_ZCPBQ_QUERY_CNF_EV
+ AP_MMIA_ZEER_READ_CNF_EV¡¢AP_MMIA_PB_READ_CAPA_REQ_EV¡¢AP_MMIA_PB_READ_SET_NUM_REQ_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_REQ_EV¡¢AP_MMIA_PB_READ_CAPA_CNF_EV¡¢AP_MMIA_PB_READ_SET_NUM_CNF_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_CNF_EV
+160 2011.05.31 ʷѧºì
+ Ôö¼ÓROHCv2¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¶Î,Ôö¼ÓROHCv2_T_IR_EXPIRY_EVÏûÏ¢ºÅ
+
+161 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼Ó´¦Àí+ZIMIµÄÏûÏ¢AP_MMIA_SET_IMSI_REQ_EV
+
+162 2011.06.16 ËÎÑÇÅô
+ Ôö¼ÓGMM¼à¿ØMSÖ÷¶¯ÇëÇóÊÍ·ÅÁ´½Ó¶¨Ê±Æ÷Z_GMM_Twrel³¬Ê±µÄÏûÏ¢GMM_T_WREL_EXPIRY_EV
+ EC614000821119£ºGMMÄ£¿éÊÍ·ÅRRCÁ¬½ÓÔö¼ÓÎÕÊÖ¹ý³Ì£¬Ôö¼Ó¶¨Ê±Æ÷Twrel¼à¿Ø´Ë¹ý³Ì£¬Í¬Ê±ÐèÒªÔö¼Ó¶¨Ê±Æ÷³¬Ê±ÏûÏ¢
+163 2011.06.20 ¹ù·å
+ EC614000815619£ºCM²ãÔÚUMM»»Íø¹ý³ÌÖÐÓÐÒµÎñÁ÷³Ì£¬²»¶ÏµÄ·¢ÆðCM_EST£»Í¨¹ý¶¨Ê±Æ÷À´¿ØÖÆÖØ·¢´ÎÊý
+
+ 164 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼ÓÏûÏ¢AP_MMIA_CS_SRV_IND_EV
+
+165 2011.06.30 Ëﳤ½Ôö¼ÓPA+Éý¼¶ÐÞ¸Ä
+ 1£©URBC_UPHY_RSP_EVENTÓëURBC_UPHY_EVENT_BASEÖ®¼äµÄÆ«ÒÆÓÉ20±äΪ30£»
+ 2£©Ôö¼ÓÏûÏ¢ºÅCSCI_UNRECOVER_ERR_EV£¬URRC_EFACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_REQ_EV£¬CUMAC_HSPA_EPCH_CFG_REQ_EV£¬
+ CUMAC_UPDATE_ERNTI_REQ_EV£¬CUMAC_FACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_CNF_EV£¬P_HSPA_PLUS_FACH_REQ_EV£¬P_HSPA_PLUS_PCH_REQ_EV
+ P_HSPA_PLUS_FACH_REL_REQ_EV£¬P_HSPA_PLUS_PCH_REL_REQ_EV£¬P_EFACH_UPDATE_RNTI_REQ_EV£¬P_CELL_RESEL_REQ_EV£¬P_CELL_RESEL_CNF_EV£¬P_SYNC_CMD_RESP_EV,
+ P_HSPA_PLUS_FACH_REL_CNF_EV,P_HSPA_PLUS_FACH_REL_CNF_EV
+ 3£©P_DL_DPCH_SETUP_MODIFY_CNF_EV¸ÄÃûΪP_DL_RL_SETUP_MODIFY_CNF_EV
+
+ 166 2011.7.1 ¹Ë±¦³ÉÔö¼ÓÄ£ÄâPSIÏûÏ¢SIMULPSI_CONFIG_EV
+
+ 167 2011.7.7 ÕÔÕñ»ÔÔö¼Ó¶ÔCSÑ°ºôµÄÓ¦´ðÏûÏ¢AP_MMIA_CS_SRV_RSP_EV
+ 168 2011.7.15 ÕÅÅô³ÌÔö¼ÓÖ§³ÖLTE±³¾°ËÑË÷¹¦ÄÜÐÂÔöµÄʼþºÅ
+ AP_MMIA_BGPLMNSEL_SETREQ_EV¡¢AP_MMIA_BGPLMNSEL_QUERYCNF_EV¡¢AP_MMIA_BGPLMNSEL_QUERYREQ_EV
+ MMIA_UMM_BGPLMNSEL_REQ_EV
+ UMM_ASC_TRY_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_CNF_EV¡¢UMM_ASC_TRY_BGPLMN_REJ_EV¡¢UMM_ASC_TRY_BGPLMN_CNF_EV
+ ASC_LTE_TRY_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_CNF_EV¡¢ASC_LTE_TRY_BGPLMN_REJ_EV¡¢ASC_LTE_TRY_BGPLMN_CNF_EV
+169 2011.7.18 Ëﳤ½ Õë¶Ô614000878724 ɾ³ýÈçÏÂÏûÏ¢ºÅ
+ AS_LTE_TD_CSHO_REQ_EV¡¢AS_LTE_TD_CSHO_CNF_EV¡¢AS_LTE_TD_CSHO_REJ_EV
+170 2011.7.28 ½ª²¨ Õë¶Ô614000920283 Ôö¼ÓÈçÏÂÏûÏ¢ºÅ
+ ASC_LTE_LOCK_CELL_REQ_EV¡¢ASC_LTE_UNLOCK_CELL_REQ_EV¡¢ASC_LTE_LOCK_CELL_CNF_EV
+171 2011.8.2 ÅËÀÚ Ôö¼ÓÏûÏ¢ºÅUURLC_PDCP_DATA_IND_EV
+172 2011.8.2 Ëﳤ½ ÏûÏ¢ºÅ¶¨ÒåÖظ´ÁË£¬ÐèҪɾ³ýÏûÏ¢ºÅCUMAC_RESEL_REQ_EV£¬CUMAC_RESEL_IND_EV
+173 2011.8.15 ³Â¹â»ªÔö¼ÓCBSÏûÏ¢ºÅCBS_ASC_CMAS_NOTIFY_IND_EV
+174 2011.8.17 ¿µÊé½ÜÔö¼ÓCSGÏûÏ¢ºÅEURRC_CSG_PROXIMITY_IND_EV
+175 2011.8.23 ¿µÊé½Üɾ³ýLTE_P_SWITCH_RF_REQ_EV,LTE_P_START_PAGING_REQ_EV,LTE_P_SWITCH_RF_CNF_EV
+ Ôö¼ÓLTE_P_SLEEP_TIME_IND_EV£¬LTE_P_WAKEUP_REQ_EV
+176 2011.8.23 ÕÔÕñ»ÔΪCMMB/×¼FR/Refresh/·þÎñÁбí/CCOͳ¼ÆÔö¼ÓÏûÏ¢AP_MMIA_MB_AUTH_REQ_EV¡¢
+ AP_MMIA_MB_CELL_ID_REQ_EV¡¢AP_MMIA_PSEUDO_FR_SET_REQ_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_REQ_EV¡¢
+ AP_MMIA_REFRESH_REQ_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_REQ_EV¡¢AP_MMIA_MB_AUTH_CNF_EV ¡¢
+ AP_MMIA_MB_CELL_ID_CNF_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_CNF_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_CNF_EV¡¢
+ MSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV
+177 2011.8.24 ΤÓñÕäÔö¼Ólte gap±¨¸æ¸øtrs
+178 2011.8.25 ÑîÔÊÔö¼ÓESM_EMM_EMERGENCY_PDN_ONLY_IND_EV,EMM_ESM_DETACH_NORMAL_IND_EV
+179 2011.8.25 ÑÔö¼ÓESM_UMM_LOCAL_DEACT_IND_EV
+180 2011.8.25 ׿±Ø²¨Ôö¼ÓCM_SM_DEACT_NON_EMERGENCY_EV
+181 2011.8.29 ½ª²¨Ôö¼ÓMSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV¡¢MSGTRACEPS_CELLRESORCCO_IND_EV¡¢MMIA_AS_EM_CELLRESORCCOCOUNT_REQ_EV¡¢
+ ASC_LTE_CMAS_NOTIFY_IND_EV¡¢EUSIR_T_ETWS_EXPIRY_EV¡¢EUSIR_T_CMAS_EXPIRY_EV
+ ÐÞ¸ÄEURRC_ETWS_INFO_EV Ϊ EURRC_WARNING_NOTIFY_INFO_EV
+182 2011.8.29 ÓȺ£Ó¢ refresh Ôö¼Ó AP_UICC_REFRESH_REQ_EV AP_UICC_DEACTEND_IND_EV AP_UICC_FILECHANGEEND_IND_EV AP_UICC_FILECHANGE_IND_EV
+183 2011.9.15 ½ª²¨Ôö¼ÓEURRC_SI_END_FOR_HO_EV
+184 2011.9.15 ÍõÖ¾Ôö¼ÓENBRRC_PROXIMITY_RPT_EV
+185 2011.9.16 Ðì¿¡Ôö¼ÓGRRº¯Êý½Ó¿Ú
+186 2011.9.16 Ëﳤ½ÉêÇëÔö¼ÓENBRRC_UE_INFO_REQ_EV¡¢ENBRRC_UE_INFO_RSP_EV
+187 2011.9.26 ð¿¡µ÷ÕûGRR¶¨Ê±Æ÷ÏûÏ¢ºÅ·¶Î§
+
+188 2011.10.12 lh ɾ³ýÁÚÇøÉϱ¨ºÍ·þÎñСÇøÉϱ¨ÏûÏ¢½Ó¿Ú£¬Ôö¼ÓLTEСÇøÐÅÏ¢Éϱ¨Ê¼þºÅ
+189 2011.10.18 ÕÔÕñ»ÔΪLTE±³¾°ËÑË÷Ôö¼ÓÏûÏ¢AP_MMIA_LTEBGPLMN_TESTREQ_EVºÍAP_MMIA_LTEBGPLMN_TESTCNF_EV
+
+190 2011.10.19 ºÎ«Ôö¼Ó¶¨Ê±Æ÷ʼþºÅT_DISABLE_UMTS_MEAS_EV,T_DISABLE_LTE_MEAS_EV
+191 2011.11.3 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SMSOVERIPNET_SETREQ_EV¡¢AP_MMIA_SMSOVERIPNET_QUERYREQ_EV
+ AP_MMIA_SMSOVERIPNET_QUERYCNF_EV¡¢MMIA_UMM_SMSOVERIPNET_SETREQ_EV
+ EC614001128873
+
+192 2011.11.4 ÕÔÕñ»ÔÔö¼ÓËæeÐа汾IccIdµÄÉϱ¨ºÍ»ú¿¨»¥ËøÐèÇó:
+ Ôö¼ÓÏûÏ¢ZPS_ApUicc_ToReadCardReq_Ev¡¢ZPS_ApMmia_Iccid_Ind_EV¡¢ZPS_ApMmia_USAT_ToReadCardReq_Ev
+
+193 2011.11.4 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SM_DEACT_IND_EV, EC614001103133
+194 2011.11.22 ÓȺ£Ó¢Ôö¼ÓTEST_SET_NV_DATA_SPCLFUNC_EV £¬EC 614001151291
+
+195 2011.12.2 ÁºÐ¡º®Ôö¼ÓÏûÏ¢AP_MMIA_CALL_LINE_SET_REQ_EV¡¢AP_MMIA_CALL_LINE_QRY_REQ_EVºÍAP_MMIA_CALL_LINE_QUERY_CNF_EV 614001181454
+ R9 U115¸£ÖÝ°æ±¾Ò»»úË«ºÅÐèÇó ºÏÈë
+
+196 2011.12.26 EC617001225651,MMIAÔö¼ÓUE InfoµÄÉϱ¨,ÕÔÕñ»ÔÔö¼ÓÏûÏ¢ROADTEST_UEINFO_REQ_EV¡¢ROADTEST_UEINFO_CNF_EV
+197 2011.12.27 ËÎÑÇÅôÐÂÔöPDCP(RABM)֪ͨGMM¹ØÓÚRABÐÅÏ¢
+
+198 2012.1.5 EC617001233064Ôö¼ÓÄ£ÄâPDI·¢Ë͸øGSMAµÄÏûÏ¢PDI_GSM_DATA_REQ_EV
+199 2012.1.11 ¹Ë±¦³ÉÐÂÔöÈýÌõÏûÏ¢ÓÃÓÚÓû§ÃæÌØÊâÐÅÁî¸ú×Ù
+200 2012.03.12 ΤÓñÕä Ôö¼ÓÏûÏ¢P_DETECT_CELL_INFO_IND_EV
+201 2012.03.27 ³ÂΰÐÂÔöLTE_P_DLSCH_DATA_TRACE_EVºÍLTE_P_ULSCH_DATA_TRACE_EVÓÃÓÚEPHYºÍEUMAC¼äµÄÉÏÏÂÐÐÊý¾ÝÐÅÁî¸ú×Ù
+
+202 2012.04.16 ºÎ«ÐÂÔöGRR_RRC_POWEROFF_IND_EVÏûÏ¢ÓÃÀ´Í¨ÖªGRRC(Èí)¹Ø»ú
+203 2012.05.08 Ëﳤ½ÐÂÔöASC_TD_LOSTCOV_CAMP_SUCC_IND_EVÏûÏ¢ÓÃÓÚÆäËüÖÆʽ¶ªÊ§¸²¸ÇÖØÑ¡µ½TD³É¹¦ºó£¬ASC֪ͨUCER±íʾ¿çÖÆʽÖØÑ¡³É¹¦¡£
+204 2012.05.10 ³ÂΰÐÂÔöLTE_P_MAC_SR_REQ_EVÓÃÓÚTMTÐÅÁî¸ú×ÙSRµÄ·¢ËÍ
+205 2012.05.10 Ëﳤ½ÐÂÔöP_UL_PHY_CH_CTRL_REQ_EvÏûÏ¢ÓÃÓÚ½øÐÐUl-DTXÅäÖÃ?
+206 2012.07.15 ÁºÐ¡º®ÐÂÔöMMIA_EUCSR_LTEINFO_REQ_EVµÈÏûÏ¢ÓÃÓÚatÃüÁîÉϱ¨×ÓÖ¡ÅäÖÃÐÅÏ¢
+207 2012.08.02 ÍõС½ø EC617001662142£¬ Ôö¼Ó
+ AP_UICC_CCHO_REQ_EV,AP_UICC_CCHC_REQ_EV,AP_UICC_CGLA_REQ_EV,AP_UICC_CRSM_REQ_EV,
+ AP_UICC_CCHO_CNF_EV,AP_UICC_CGLA_CNF_EV,AP_UICC_CRSM_CNF_EV,AP_UICC_USAT_FETCH_IND_EV,
+208 2012.11.06 W GROUPÐ޸ģºÐÞ¸Äpsenent end,ÔÚÔÀ´µÄ»ù´¡ÉÏÔö¼ÓÁË8000.W·ÇÎïÀí²ãÏûϢλÓÚLTEÏûÏ¢Ö®ºó£¬ÔÚ16384--end
+ WµÄÎïÀí²ãÏûÏ¢·ÅÔÚps+6500---ps+7000µÄµØ·½£¬¶ÔÓÚTW¹²ÓÃÏûÏ¢²ÉÓÃÐÞ¸ÄÃüÃûµÄ·½Ê½TD¸ÄΪUTRA
+209 2012.11.21 ÍõС½ø EC617001860117£¬ ÖÇÄÜ»úÈȲå°ÎÐèÇó£¬Ôö¼ÓÏûÏ¢
+ AP_UICC_MOVECARD_IND_EV AP_UICC_INSERTCARD_IND_EV
+210 2013.10.18 ΤÓñÕäÔö¼ÓATIÓëASµÄÏûÏ¢MMIA_AS_B39_INFO_IND_EV(EUMCR,UMCR->ATI)ºÍMMIA_AS_B39_INFO_REQ_EV(ATI->GRR)
+ *****************************************************************************/
+#ifndef Z_EVENTDEF_H
+#define Z_EVENTDEF_H
+
+#include "atipsevent.h"
+
+/*=====================================================================================================================
+ ÏûÏ¢Çø¼ä£º
+
+ ||______________________|__________UPHY__________|_____________________|_____________________||
+ PS_BASE UPHY_BASE(+6K) UPHY_BASE(+6.5K) PS_LTE_BASE(+10K) PS_END(PS_LTE_END)
+ =====================================================================================================================*/
+
+/*GSM SDLÏûϢʼþºÅ·¶Î§£¬¾ßÌåµÄGSMʼþºÅ¶¨ÒåÔÚSIG_CODE.HÖУ¬½öÔÚpstestÖÐʹÓÃ*/
+#define EVENT_PS_GSM_SDL_BASE (DWORD)0x00010000
+#define EVENT_PS_GSM_SDL_END (DWORD)0xff7d0003
+
+/*LTEʼþºÅ·¶Î§*/
+#define EVENT_PS_LTE_BASE (DWORD)(EVENT_PS_BASE + 10000)
+#define EVENT_PS_LTE_END (DWORD)(EVENT_PS_BASE + 16383)
+
+/*WCDMAʼþºÅ·¶Î§*/
+#define EVENT_PS_W_BASE (DWORD)(EVENT_PS_BASE + 16384)
+#define EVENT_PS_W_END (DWORD)EVENT_PS_END
+/**************************************************PHY msg base-end start********************************************************/
+/*Õⲿ·ÖID²»ÄÜËæÒâÐ޸ģ¬»áÓ°Ïì½Ó¿ÚÖеÄmsgidµÄÖµ£¬´Ó¶øʹÎïÀí²ãµ¼ÖÂÎóÅÐÏûÏ¢*/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define PS_UPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6000)
+/*ÐÒéÕ»ÓëWCDMAÎïÀí²ãÏûÏ¢·¶Î§.TDÓëWÎïÀí²ãÏûÏ¢·¶Î§¹Ì¶¨ÔÚ6000µ½7000.ÆäÖÐÇ°500ÓÃÓÚTD£¬ºó500ÓÃÓÚW*/
+#define PS_WPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6500)
+
+/*ÐÒéÕ»ÓëLTEÎïÀí²ãÏûÏ¢·¶Î§£¬±£Ö¤ÎïÀí²ãºÍÐÒéÕ»IDÆðʼֵµÍ8λȫÁ㣬±£Ö¤Ç¿ÖÆת»»ÎªBYTEΪÕý³£Öµ*/
+#define LTE_PS_EUPHY_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 2544)
+#define LTE_PS_EUPHY_RSP_EVENT (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 60)
+#define LTE_PS_EUPHY_EVENT_END (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 120)
+/**************************************************PHY msg base-end end********************************************************/
+
+/*UMM¡¢MM¡¢GMMÄÚ²¿ÏûÏ¢·¶Î§(50)*/
+#define UMM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2570)
+#define UMM_EVENT_END (DWORD)(UMM_EVENT_BASE + 49)
+
+/*SS/SMS/SM/CC/PDCPÓëMM/GMMµÄÏûÏ¢·¶Î§(50)*/
+#define CM_MM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2620)
+#define CM_MM_EVENT_END (DWORD)(CM_MM_EVENT_BASE + 49)
+
+/*UMMºÍASCµÄÏûÏ¢·¶Î§ (100)*/
+#define UMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2670)
+#define UMM_ASC_RSP_EVENT (DWORD)(UMM_ASC_EVENT_BASE + 50)
+#define UMM_ASC_EVENT_END (DWORD)(UMM_ASC_EVENT_BASE + 99)
+
+/*GMMºÍASCµÄÏûÏ¢·¶Î§(100) */
+#define GMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2770)
+#define GMM_ASC_RSP_EVENT (DWORD)(GMM_ASC_EVENT_BASE + 50)
+#define GMM_ASC_EVENT_END (DWORD)(GMM_ASC_EVENT_BASE + 99)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_UAS_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2870)
+#define ASC_UAS_RSP_EVENT (DWORD)(ASC_UAS_EVENT_BASE + 50)
+#define ASC_UAS_EVENT_END (DWORD)(ASC_UAS_EVENT_BASE + 99)
+
+/*ASCºÍGSM ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_GAS_EVENT_BASE (DWORD)(ASC_UAS_EVENT_END + 1)
+#define ASC_GAS_RSP_EVENT (DWORD)(ASC_GAS_EVENT_BASE + 50)
+#define ASC_GAS_EVENT_END (DWORD)(ASC_GAS_EVENT_BASE + 99)
+
+/*ASCºÍLTE ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_EUAS_EVENT_BASE (DWORD)(ASC_GAS_EVENT_END + 1)
+#define ASC_EUAS_RSP_EVENT (DWORD)(ASC_EUAS_EVENT_BASE + 50)
+#define ASC_EUAS_EVENT_END (DWORD)(ASC_EUAS_EVENT_BASE + 99)
+
+/*ASCºÍ¸÷AS¹«¹²µÄÏûÏ¢·¶Î§(100) */
+#define ASC_AS_EVENT_BASE (DWORD)(ASC_EUAS_EVENT_END + 1)
+#define ASC_AS_EVENT_END (DWORD)(ASC_AS_EVENT_BASE + 149)
+
+/*CBSºÍRRCµÄÏûÏ¢·¶Î§(30)*/
+#define CBS_RRC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 3320)
+#define CBS_RRC_RSP_EVENT (DWORD)(CBS_RRC_EVENT_BASE + 20)
+#define CBS_RRC_EVENT_END (DWORD)(CBS_RRC_EVENT_BASE + 29)
+
+/*GMMºÍSNDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_SNDCP_EVENT_BASE (DWORD)(CBS_RRC_EVENT_END + 1)
+#define GMM_SNDCP_EVENT_END (DWORD)(GMM_SNDCP_EVENT_BASE + 24)
+
+/*GMMºÍPDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_PDCP_EVENT_BASE (DWORD)(GMM_SNDCP_EVENT_END + 1)
+#define GMM_PDCP_EVENT_END (DWORD)(GMM_PDCP_EVENT_BASE + 24)
+
+/*SMºÍPDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_PDCP_EVENT_BASE (DWORD)(GMM_PDCP_EVENT_END + 1)
+#define SM_PDCP_RSP_EVENT (DWORD)(SM_PDCP_EVENT_BASE + 25)
+#define SM_PDCP_EVNET_END (DWORD)(SM_PDCP_EVENT_BASE + 49)
+
+/*SMºÍSNDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_SNDCP_EVENT_BASE (DWORD)(SM_PDCP_EVNET_END + 1)
+#define SM_SNDCP_RSP_EVENT (DWORD)(SM_SNDCP_EVENT_BASE + 20)
+#define SM_SNDCP_EVENT_END (DWORD)(SM_SNDCP_EVENT_BASE + 49)
+
+/*PDIºÍGSMAµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_GSMA_EVENT_BASE (DWORD)(SM_SNDCP_EVENT_END + 1)
+#define PDI_GSMA_RSP_EVENT (DWORD)(PDI_GSMA_EVENT_BASE + 10)
+#define PDI_GSMA_EVENT_END (DWORD)(PDI_GSMA_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_PDCP_EVENT_BASE (DWORD)(PDI_GSMA_EVENT_END + 1)
+#define PDI_PDCP_RSP_EVENT (DWORD)(PDI_PDCP_EVENT_BASE + 10)
+#define PDI_PDCP_EVENT_END (DWORD)(PDI_PDCP_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_URLC_EVENT_BASE (DWORD)(PDI_PDCP_EVENT_END + 1)
+#define PDCP_URLC_EVENT_END (DWORD)(PDCP_URLC_EVENT_BASE + 9)
+
+/*TAFºÍCCÏûÏ¢·¶Î§(50)*/
+#define CC_TAF_EVENT_BASE (DWORD)(PDCP_URLC_EVENT_END + 1)
+#define CC_TAF_EVENT_END (DWORD)(CC_TAF_EVENT_BASE + 49)
+
+/*UMMºÍCBSÏûÏ¢·¶Î§(50)*/
+#define UMM_CBS_EVENT_BASE (DWORD)(CC_TAF_EVENT_END + 1)
+#define UMM_CBS_RSP_EVENT (DWORD)(UMM_CBS_EVENT_BASE + 20)
+#define UMM_CBS_EVENT_END (DWORD)(UMM_CBS_EVENT_BASE + 49)
+
+/*SCIºÍURRC/CCÏûÏ¢·¶Î§(30)*/
+#define AP_SCI_EVENT_BASE (DWORD)(UMM_CBS_EVENT_END + 1)
+#define AP_SCI_EVENT_END (DWORD)(AP_SCI_EVENT_BASE + 29)
+
+/*URLCºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define URLC_URRC_EVENT_BASE (DWORD)(AP_SCI_EVENT_END + 1)
+#define URLC_URRC_RSP_EVENT (DWORD)(URLC_URRC_EVENT_BASE + 30)
+#define URLC_URRC_EVENT_END (DWORD)(URLC_URRC_EVENT_BASE + 59)
+
+/*UMACºÍURRCµÄÏûÏ¢·¶Î§(70)*/
+#define UMAC_URRC_EVENT_BASE (DWORD)(URLC_URRC_EVENT_END + 1)
+#define UMAC_URRC_RSP_EVENT (DWORD)(UMAC_URRC_EVENT_BASE + 40)
+#define UMAC_URRC_EVENT_END (DWORD)(UMAC_URRC_EVENT_BASE + 69)
+
+/*UMAC-UL/DLºÍUMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define UMAC_UMAC_EVENT_BASE (DWORD)(UMAC_URRC_EVENT_END + 1)
+#define UMAC_UMAC_EVENT_END (DWORD)(UMAC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1T_URRC_EVENT_BASE (DWORD)(UMAC_UMAC_EVENT_END + 1)
+#define L1T_URRC_RSP_EVENT (DWORD)(L1T_URRC_EVENT_BASE + 30)
+#define L1T_URRC_EVENT_END (DWORD)(L1T_URRC_EVENT_BASE + 59)
+
+/*PDCPºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_URRC_EVENT_BASE (DWORD)(L1T_URRC_EVENT_END + 1)
+#define PDCP_URRC_RSP_EVENT (DWORD)(PDCP_URRC_EVENT_BASE + 30)
+#define PDCP_URRC_EVENT_END (DWORD)(PDCP_URRC_EVENT_BASE + 59)
+
+/*URLCºÍUMACµÄÏûÏ¢·¶Î§(20)*/
+#define URLC_UMAC_EVENT_BASE (DWORD)(PDCP_URRC_EVENT_END + 1)
+#define URLC_UMAC_EVENT_END (DWORD)(URLC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍUMACµÄÏûÏ¢·¶Î§(10)*/
+#define UMAC_L1T_EVENT_BASE (DWORD)(URLC_UMAC_EVENT_END + 1)
+#define UMAC_L1T_EVENT_END (DWORD)(UMAC_L1T_EVENT_BASE + 9)
+
+/*URRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define URRC_EVENT_BASE (DWORD)(UMAC_L1T_EVENT_END + 1)
+#define URRC_EVENT_END (DWORD)(URRC_EVENT_BASE + 99)
+
+/*L1TÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1T_EVENT_BASE (DWORD)(URRC_EVENT_END + 1)
+#define L1T_EVENT_END (DWORD)(L1T_EVENT_BASE + 19)
+
+/*ÎïÀí²ãÊÊÅä²ãÖ®¼äL1T/L1EÏûÏ¢·¶Î§(30)£¨²»°üº¬L1G£¬ÓëL1G½»»¥µÄÏûϢȫ²¿ÊÇSDLÏûÏ¢£¬¶¨ÒåÔÚsig_code.hÖУ©*/
+#define L1A_EVENT_BASE (DWORD)(L1T_EVENT_END + 1)
+#define L1A_EVENT_END (DWORD)(L1A_EVENT_BASE + 29)
+
+/*ÐÒéÕ»ÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§(530)*/
+#define UMM_TIMER_EVENT_BASE (DWORD)(MMIA_TIMER_EVENT_END + 1)
+#define UMM_TIMER_EVENT_END (DWORD)(UMM_TIMER_EVENT_BASE + 49)
+
+#define MM_TIMER_EVENT_BASE (DWORD)(UMM_TIMER_EVENT_END + 1)
+#define MM_TIMER_EVENT_END (DWORD)(MM_TIMER_EVENT_BASE + 29)
+
+#define GMM_TIMER_EVENT_BASE (DWORD)(MM_TIMER_EVENT_END + 1)
+#define GMM_TIMER_EVENT_END (DWORD)(GMM_TIMER_EVENT_BASE + 29)
+
+#define CC_TIMER_EVENT_BASE (DWORD)(GMM_TIMER_EVENT_END + 1)
+#define CC_TIMER_EVENT_END (DWORD)(CC_TIMER_EVENT_BASE + 49)
+
+#define SMS_TIMER_EVENT_BASE (DWORD)(CC_TIMER_EVENT_END + 1)
+#define SMS_TIMER_EVENT_END (DWORD)(SMS_TIMER_EVENT_BASE + 19)
+
+#define SM_TIMER_EVENT_BASE (DWORD)(SMS_TIMER_EVENT_END + 1)
+#define SM_TIMER_EVENT_END (DWORD)(SM_TIMER_EVENT_BASE + 19)
+
+#define SS_TIMER_EVENT_BASE (DWORD)(SM_TIMER_EVENT_END + 1)
+#define SS_TIMER_EVENT_END (DWORD)(SS_TIMER_EVENT_BASE + 9)
+
+#define CBS_TIMER_EVENT_BASE (DWORD)(SS_TIMER_EVENT_END + 1)
+#define CBS_TIMER_EVENT_END (DWORD)(CBS_TIMER_EVENT_BASE + 9)
+
+#define UICC_TIMER_EVENT_BASE (DWORD)(CBS_TIMER_EVENT_END + 1)
+#define UICC_TIMER_EVENT_END (DWORD)(UICC_TIMER_EVENT_BASE + 19)
+
+#define URRC_TIMER_EVENT_BASE (DWORD)(UICC_TIMER_EVENT_END + 1)
+#define URRC_TIMER_EVENT_END (DWORD)(URRC_TIMER_EVENT_BASE + 79)
+
+#define URLC_TIMER_EVENT_BASE (DWORD)(URRC_TIMER_EVENT_END + 1)
+#define URLC_TIMER_EVENT_END (DWORD)(URLC_TIMER_EVENT_BASE + 19)
+
+#define UMAC_TIMER_EVENT_BASE (DWORD)(URLC_TIMER_EVENT_END + 1)
+#define UMAC_TIMER_EVENT_END (DWORD)(UMAC_TIMER_EVENT_BASE + 19)
+
+#define L1T_TIMER_EVENT_BASE (DWORD)(UMAC_TIMER_EVENT_END + 1)
+#define L1T_TIMER_EVENT_END (DWORD)(L1T_TIMER_EVENT_BASE + 19)
+
+#define PDCP_TIMER_EVENT_BASE (DWORD)(L1T_TIMER_EVENT_END + 1)
+#define PDCP_TIMER_EVENT_END (DWORD)(PDCP_TIMER_EVENT_BASE + 9)
+
+#define ROHCv1_TIMER_EVENT_BASE (DWORD)(PDCP_TIMER_EVENT_END + 1)
+#define ROHCv1_TIMER_EVENT_END (DWORD)(ROHCv1_TIMER_EVENT_BASE + 19)
+
+#define TAF_TIMER_EVENT_BASE (DWORD)(ROHCv1_TIMER_EVENT_END + 1)
+#define TAF_TIMER_EVENT_END (DWORD)(TAF_TIMER_EVENT_BASE + 19)
+
+#define GSMA_TIMER_EVENT_BASE (DWORD)(TAF_TIMER_EVENT_END + 1)
+#define GSMA_TIMER_EVENT_END (DWORD)(GSMA_TIMER_EVENT_BASE + 19)
+
+#define PDI_TIMER_EVENT_BASE (DWORD)(GSMA_TIMER_EVENT_END + 1)
+#define PDI_TIMER_EVENT_END (DWORD)(PDI_TIMER_EVENT_BASE + 19)
+
+#define ROHCv2_TIMER_EVENT_BASE (DWORD)(PDI_TIMER_EVENT_END + 1)
+#define ROHCv2_TIMER_EVENT_END (DWORD)(ROHCv2_TIMER_EVENT_BASE + 19)
+
+#define SCI_TIMER_EVENT_BASE (DWORD)(ROHCv2_TIMER_EVENT_END + 1)
+#define SCI_TIMER_EVENT_END (DWORD)(SCI_TIMER_EVENT_BASE + 9)
+
+#define STM_TIMER_EVENT_BASE (DWORD)(SCI_TIMER_EVENT_END + 1)
+#define STM_TIMER_EVENT_END (DWORD)(STM_TIMER_EVENT_BASE + 9)
+
+#define USAT_TIMER_EVENT_BASE (DWORD)(STM_TIMER_EVENT_END + 1)
+#define USAT_TIMER_EVENT_END (DWORD)(USAT_TIMER_EVENT_BASE + 9)
+
+#define TIMER_EVENT_END (DWORD)USAT_TIMER_EVENT_END
+
+/**************************************************PS msg range end********************************************************/
+
+/**************************************************UPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§(300)*/
+#define USIR_UPHY_EVENT_BASE (DWORD)PS_UPHY_EVENT_BASE
+#define USIR_UPHY_RSP_EVENT (DWORD)(USIR_UPHY_EVENT_BASE + 20)
+#define USIR_UPHY_EVENT_END (DWORD)(USIR_UPHY_EVENT_BASE + 49)
+
+#define UCSR_UPHY_EVENT_BASE (DWORD)(USIR_UPHY_EVENT_END + 1)
+#define UCSR_UPHY_RSP_EVENT (DWORD)(UCSR_UPHY_EVENT_BASE + 20)
+#define UCSR_UPHY_EVENT_END (DWORD)(UCSR_UPHY_EVENT_BASE + 49)
+
+#define UMCR_UPHY_EVENT_BASE (DWORD)(UCSR_UPHY_EVENT_END + 1)
+#define UMCR_UPHY_RSP_EVENT (DWORD)(UMCR_UPHY_EVENT_BASE + 20)
+#define UMCR_UPHY_EVENT_END (DWORD)(UMCR_UPHY_EVENT_BASE + 49)
+
+#define URBC_UPHY_EVENT_BASE (DWORD)(UMCR_UPHY_EVENT_END + 1)
+#define URBC_UPHY_RSP_EVENT (DWORD)(URBC_UPHY_EVENT_BASE + 30)
+#define URBC_UPHY_EVENT_END (DWORD)(URBC_UPHY_EVENT_BASE + 49)
+
+#define UMAC_UL_UPHY_EVENT_BASE (DWORD)(URBC_UPHY_EVENT_END + 1)
+#define UMAC_UL_UPHY_EVENT_END (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 19)
+
+#define UMAC_DL_UPHY_EVENT_BASE (DWORD)(UMAC_UL_UPHY_EVENT_END + 1)
+#define UMAC_DL_UPHY_EVENT_END (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 29)
+
+/*L1TÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1T_UPHY_EVENT_BASE (DWORD)(UMAC_DL_UPHY_EVENT_END + 1)
+#define L1T_UPHY_RSP_EVENT (DWORD)(L1T_UPHY_EVENT_BASE + 20)
+#define L1T_UPHY_EVENT_END (DWORD)(L1T_UPHY_EVENT_BASE + 49)
+
+#define PS_UPHY_EVENT_END (DWORD)L1T_UPHY_EVENT_END
+/**************************************************WPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define WSIR_WPHY_EVENT_BASE (DWORD)PS_WPHY_EVENT_BASE
+#define WSIR_WPHY_RSP_EVENT (DWORD)(WSIR_WPHY_EVENT_BASE + 20)
+#define WSIR_WPHY_EVENT_END (DWORD)(WSIR_WPHY_EVENT_BASE + 49)
+
+#define WCSR_WPHY_EVENT_BASE (DWORD)(WSIR_WPHY_EVENT_END + 1)
+#define WCSR_WPHY_RSP_EVENT (DWORD)(WCSR_WPHY_EVENT_BASE + 20)
+#define WCSR_WPHY_EVENT_END (DWORD)(WCSR_WPHY_EVENT_BASE + 49)
+
+#define WMCR_WPHY_EVENT_BASE (DWORD)(WCSR_WPHY_EVENT_END + 1)
+#define WMCR_WPHY_RSP_EVENT (DWORD)(WMCR_WPHY_EVENT_BASE + 20)
+#define WMCR_WPHY_EVENT_END (DWORD)(WMCR_WPHY_EVENT_BASE + 49)
+
+#define WRBC_WPHY_EVENT_BASE (DWORD)(WMCR_WPHY_EVENT_END + 1)
+#define WRBC_WPHY_RSP_EVENT (DWORD)(WRBC_WPHY_EVENT_BASE + 30)
+#define WRBC_WPHY_EVENT_END (DWORD)(WRBC_WPHY_EVENT_BASE + 49)
+
+#define WMAC_UL_WPHY_EVENT_BASE (DWORD)(WRBC_WPHY_EVENT_END + 1)
+#define WMAC_UL_WPHY_EVENT_END (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 19)
+
+#define WMAC_DL_WPHY_EVENT_BASE (DWORD)(WMAC_UL_WPHY_EVENT_END + 1)
+#define WMAC_DL_WPHY_EVENT_END (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 29)
+
+/*L1WÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1W_WPHY_EVENT_BASE (DWORD)(WMAC_DL_WPHY_EVENT_END + 1)
+#define L1W_WPHY_RSP_EVENT (DWORD)(L1W_WPHY_EVENT_BASE + 20)
+#define L1W_WPHY_EVENT_END (DWORD)(L1W_WPHY_EVENT_BASE + 49)
+
+#define PS_WPHY_EVENT_END (DWORD)L1W_WPHY_EVENT_END
+/**************************************************WPHY msg range end********************************************************/
+
+/**************************************************PS LTE msg range start********************************************************/
+/*EMMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EMM_TIMER_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1)
+#define EMM_TIMER_EVENT_END (DWORD)(EMM_TIMER_EVENT_BASE + 19)
+
+/*ESMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define ESM_TIMER_EVENT_BASE (DWORD)(EMM_TIMER_EVENT_END + 1)
+#define ESM_TIMER_EVENT_END (DWORD)(ESM_TIMER_EVENT_BASE + 19)
+
+/*EUPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EPDCP_TIMER_EVENT_BASE (DWORD)(ESM_TIMER_EVENT_END + 1)
+#define EPDCP_TIMER_EVENT_END (DWORD)(EPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EURLC_TIMER_EVENT_BASE (DWORD)(EPDCP_TIMER_EVENT_END + 1)
+#define EURLC_TIMER_EVENT_END (DWORD)(EURLC_TIMER_EVENT_BASE + 9)
+
+/*EUMACÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EUMAC_TIMER_EVENT_BASE (DWORD)(EURLC_TIMER_EVENT_END + 1)
+#define EUMAC_TIMER_EVENT_END (DWORD)(EUMAC_TIMER_EVENT_BASE + 9)
+
+/*EURRCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define EURRC_TIMER_EVENT_BASE (DWORD)(EUMAC_TIMER_EVENT_END + 1)
+
+/*EUCER×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCER_TIMER_EVENT_BASE (DWORD)(EURRC_TIMER_EVENT_BASE + 1)
+#define EUCER_TIMER_EVENT_END (DWORD)(EUCER_TIMER_EVENT_BASE + 19)
+
+/*EUMCR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUMCR_TIMER_EVENT_BASE (DWORD)(EUCER_TIMER_EVENT_END + 1)
+#define EUMCR_TIMER_EVENT_END (DWORD)(EUMCR_TIMER_EVENT_BASE + 19)
+
+/*EUCSR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCSR_TIMER_EVENT_BASE (DWORD)(EUMCR_TIMER_EVENT_END + 1)
+#define EUCSR_TIMER_EVENT_END (DWORD)(EUCSR_TIMER_EVENT_BASE + 19)
+
+/*EUSIR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUSIR_TIMER_EVENT_BASE (DWORD)(EUCSR_TIMER_EVENT_END + 1)
+#define EUSIR_TIMER_EVENT_END (DWORD)(EUSIR_TIMER_EVENT_BASE + 19)
+
+#define EURRC_TIMER_EVENT_END (DWORD)EUSIR_TIMER_EVENT_END
+
+/*EMMºÍUMMÄ£¿é¼äµÄÏûÏ¢IDºÅ*/
+#define EMM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 200)
+#define EMM_UMM_RSP_EVENT (DWORD)(EMM_UMM_EVENT_BASE + 19)
+#define EMM_UMM_EVENT_END (DWORD)(EMM_UMM_EVENT_BASE + 29)
+
+/*UMMºÍEPDCPÄ£¿éÖ®¼äµÄÏûÏ¢ID */
+#define UMM_EPDCP_EVENT_BASE (DWORD)(EMM_UMM_EVENT_END + 1)
+#define UMM_EPDCP_RSP_EVENT (DWORD)(UMM_EPDCP_EVENT_BASE + 9)
+#define UMM_EPDCP_EVENT_END (DWORD)(UMM_EPDCP_EVENT_BASE + 19)
+
+/* CM²ãºÍESMÄ£¿é¼äÏûÏ¢IDºÅ(ÐÂÔö)*/
+#define CM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 260)
+#define CM_ESM_RSP_EVENT (DWORD)(CM_ESM_EVENT_BASE + 9)
+#define CM_ESM_EVENT_END (DWORD)(CM_ESM_EVENT_BASE + 19)
+
+/* CM²ãºÍEMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define CM_EMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 280)
+#define CM_EMM_RSP_EVENT (DWORD)(CM_EMM_EVENT_BASE + 9)
+#define CM_EMM_EVENT_END (DWORD)(CM_EMM_EVENT_BASE + 19)
+
+/* EMMºÍESMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_EMM_EVENT_BASE (DWORD)(CM_EMM_EVENT_END + 1)
+#define ESM_EMM_RSP_EVENT (DWORD)(ESM_EMM_EVENT_BASE + 19)
+#define ESM_EMM_EVENT_END (DWORD)(ESM_EMM_EVENT_BASE + 29)
+
+/*EMMºÍERRC(CER)Ä£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_ASC_EVENT_BASE (DWORD)(ESM_EMM_EVENT_END + 1)
+#define EMM_ASC_RSP_EVENT (DWORD)(EMM_ASC_EVENT_BASE + 19)
+#define EMM_ASC_EVENT_END (DWORD)(EMM_ASC_EVENT_BASE + 49)
+
+/*EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_EPDCP_EVENT_BASE (DWORD)(EMM_ASC_EVENT_END + 1)
+#define EMM_EPDCP_RSP_EVENT (DWORD)(EMM_EPDCP_EVENT_BASE + 9)
+#define EMM_EPDCP_EVENT_END (DWORD)(EMM_EPDCP_EVENT_BASE + 19)
+
+/*ESMºÍUMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 400)
+#define ESM_UMM_RSP_EVENT (DWORD)(ESM_UMM_EVENT_BASE + 19)
+#define ESM_UMM_EVENT_END (DWORD)(ESM_UMM_EVENT_BASE + 29)
+
+
+/* ESMºÍPDCP Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define ESM_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 430)
+#define ESM_EPDCP_RSP_EVENT (DWORD)(ESM_EPDCP_EVENT_BASE + 9)
+#define ESM_EPDCP_EVENT_END (DWORD)(ESM_EPDCP_EVENT_BASE + 19)
+
+/*EURRCºÍEPDCPÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 450)
+#define EURRC_EPDCP_RSP_EVENT (DWORD)(EURRC_EPDCP_EVENT_BASE + 25)
+#define EURRC_EPDCP_EVENT_END (DWORD)(EURRC_EPDCP_EVENT_BASE + 49)
+
+/*EURRCºÍEURLCÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EURLC_EVENT_BASE (DWORD)(EURRC_EPDCP_EVENT_END + 1)
+#define EURRC_EURLC_RSP_EVENT (DWORD)(EURRC_EURLC_EVENT_BASE + 19)
+#define EURRC_EURLC_EVENT_END (DWORD)(EURRC_EURLC_EVENT_BASE + 29)
+
+/*EURRCºÍEUMACÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EUMAC_EVENT_BASE (DWORD)(EURRC_EURLC_EVENT_END + 1)
+#define EURRC_EUMAC_RSP_EVENT (DWORD)(EURRC_EUMAC_EVENT_BASE + 25)
+#define EURRC_EUMAC_EVENT_END (DWORD)(EURRC_EUMAC_EVENT_BASE + 49)
+
+/*EURRCºÍMEL2Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_MEL2_EVENT_BASE (DWORD)(EURRC_EUMAC_EVENT_END + 1)
+#define EURRC_MEL2_RSP_EVENT (DWORD)(EURRC_MEL2_EVENT_BASE + 4)
+#define EURRC_MEL2_EVENT_END (DWORD)(EURRC_MEL2_EVENT_BASE + 6)
+
+/*SMºÍESMÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define SM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 750) /*Added:KangShuJie*/
+#define SM_ESM_RSP_EVENT (DWORD)(SM_ESM_EVENT_BASE + 25) /*Added:KangShuJie*/
+#define SM_ESM_EVENT_END (DWORD)(SM_ESM_EVENT_BASE + 49) /*Added:KangShuJie*/
+
+/*EURRCÄÚ²¿ÏûϢʼþID*/
+#define EURRC_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1000)
+#define EURRC_EVENT_END (DWORD)(EURRC_EVENT_BASE + 54)
+
+#define EUPDCP_EURLC_EVENT_BASE (DWORD)(EURRC_EVENT_END + 1)
+#define EUPDCP_EURLC_EVENT_END (DWORD)(EUPDCP_EURLC_EVENT_BASE + 4)
+
+/*EURRCºÍL1EÄ£¿éÖ®¼äÏûϢʼþ*/
+#define EURRC_L1E_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1200)
+#define EURRC_L1E_RSP_EVENT (DWORD)(EURRC_L1E_EVENT_BASE + 20)
+#define EURRC_L1E_EVENT_END (DWORD)(EURRC_L1E_EVENT_BASE + 39)
+
+
+#define EUDBG_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1400)
+#define EUDBG_EVENT_END (DWORD)(EUDBG_EVENT_BASE + 19)
+
+#define LPP_ECID_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1450)
+#define LPP_ECID_EVENT_END (DWORD)(EVENT_PS_LTE_BASE + 1499)
+
+/* LTE¼¯³É²âÊÔ¼ÓÈëµÄ²âÊÔÄ£¿éʹÓõÄÏûÏ¢ */
+#define TRS_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1500)
+#define TRS_ESM_RSP_EVENT (DWORD)(TRS_ESM_EVENT_BASE + 9)
+#define TRS_ESM_EVENT_END (DWORD)(TRS_ESM_EVENT_BASE + 29)
+
+#define TRS_EMM_EVENT_BASE (DWORD)(TRS_ESM_EVENT_END + 1)
+#define TRS_EMM_RSP_EVENT (DWORD)(TRS_EMM_EVENT_BASE + 5)
+#define TRS_EMM_EVENT_END (DWORD)(TRS_EMM_EVENT_BASE + 29)
+
+#define ENB_EMM_ESM_EVENT_BASE (DWORD)(TRS_EMM_EVENT_END + 1)
+#define ENB_EMM_ESM_RSP_EVENT (DWORD)(ENB_EMM_ESM_EVENT_BASE + 9)
+#define ENB_EMM_ESM_EVENT_END (DWORD)(ENB_EMM_ESM_EVENT_BASE + 19)
+
+#define ENB_RRC_EMM_EVENT_BASE (DWORD)(ENB_EMM_ESM_EVENT_END + 1)
+#define ENB_RRC_EMM_RSP_EVENT (DWORD)(ENB_RRC_EMM_EVENT_BASE + 9)
+#define ENB_RRC_EMM_EVENT_END (DWORD)(ENB_RRC_EMM_EVENT_BASE + 19)
+
+#define ENB_RRC_EVENT_BASE (DWORD)(ENB_RRC_EMM_EVENT_END + 1)
+#define ENB_RRC_RSP_EVENT (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENB_RRC_EVENT_END (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+/* LTE ¼¯³É²âÊÔÊý¾ÝÃæÔö¼ÓµÄÏûÏ¢ÆðʼºêADD BY LIUZHIPENG AT 09-12-28 */
+
+#define ENRRC_ENPDCP_EVENT_BASE (DWORD)(ENB_RRC_EVENT_END + 1)
+#define ENRRC_ENPDCP_RSP_EVENT (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 20)
+#define ENRRC_ENPDCP_EVENT_END (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 44)
+/* EDCP Ó²¼þ¼ÓËÙ½Ó¿ÚÏûÏ¢ */
+#define PS_ENDCP_EVENT_BASE (DWORD)(ENRRC_ENPDCP_EVENT_END + 1)
+#define PS_ENDCP_RSP_EVENT (DWORD)(PS_ENDCP_EVENT_BASE + 9)
+#define PS_ENDCP_EVENT_END (DWORD)(PS_ENDCP_EVENT_BASE + 19)
+
+/* ENPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENPDCP_TIMER_EVENT_BASE (DWORD)(PS_ENDCP_EVENT_END + 1)
+#define ENPDCP_TIMER_EVENT_END (DWORD)(ENPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENRLC_TIMER_EVENT_BASE (DWORD)(ENPDCP_TIMER_EVENT_END + 1)
+#define ENRLC_TIMER_EVENT_END (DWORD)(ENRLC_TIMER_EVENT_BASE + 9)
+
+/* ENRRCÓëENRLCµÄÏûÏ¢¿Õ¼ä */
+#define ENRRC_ENRLC_EVENT_BASE (DWORD)(ENRLC_TIMER_EVENT_END + 1)
+#define ENRRC_ENRLC_RSP_EVENT (DWORD)(ENRRC_ENRLC_EVENT_BASE + 9)
+#define ENRRC_ENRLC_EVENT_END (DWORD)(ENRRC_ENRLC_EVENT_BASE + 19)
+/* ENMACÓëEPHYµÄÏûÏ¢¿Õ¼ä*/
+#define ENMAC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENRLC_EVENT_END + 1)
+#define ENMAC_EPHY_RSP_EVENT (DWORD)(ENMAC_EPHY_EVENT_BASE + 9)
+#define ENMAC_EPHY_EVENT_END (DWORD)(ENMAC_EPHY_EVENT_BASE + 19)
+
+#define ENRRC_ENMAC_EVENT_BASE (DWORD)(ENMAC_EPHY_EVENT_END + 1)
+#define ENRRC_ENMAC_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 9)
+#define ENRRC_ENMAC_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 19)
+
+#define ENRRC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENMAC_EVENT_END + 1)
+#define ENRRC_EPHY_RSP_EVENT (DWORD)(ENRRC_EPHY_EVENT_BASE + 9)
+#define ENRRC_EPHY_EVENT_END (DWORD)(ENRRC_EPHY_EVENT_BASE + 19)
+
+#define TRS_EPHY_EVENT_BASE (DWORD)(ENRRC_EPHY_EVENT_END + 1)
+#define TRS_EPHY_RSP_EVENT (DWORD)(TRS_EPHY_EVENT_BASE + 10)
+#define TRS_EPHY_EVENT_END (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+
+#define TRS_ENMAC_EVENT_BASE (DWORD)(TRS_EPHY_EVENT_END + 1)
+#define TRS_ENMAC_RSP_EVENT (DWORD)(TRS_ENMAC_EVENT_BASE + 10)
+#define TRS_ENMAC_EVENT_END (DWORD)(TRS_ENMAC_EVENT_BASE + 19)
+
+#define ENPDI_ENPDCP_EVENT_BASE (DWORD)(TRS_ENMAC_EVENT_END + 1)
+#define ENPDI_ENPDCP_RSP_EVENT (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 10)
+#define ENPDI_ENPDCP_EVENT_END (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 19)
+
+#define TRS_SIMULPDI_EVENT_BASE (DWORD)(ENPDI_ENPDCP_EVENT_END + 1)
+#define TRS_SIMULPDI_RSP_EVENT (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define TRS_SIMULPDI_EVENT_END (DWORD)(TRS_SIMULPDI_EVENT_BASE + 19)
+
+#define TRS_SIMULENPDI_EVENT_BASE (DWORD)(TRS_SIMULPDI_EVENT_END + 1)
+#define TRS_SIMULENPDI_RSP_EVENT (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define TRS_SIMULENPDI_EVENT_END (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 19)
+
+/* =========================================================================
+ TRS --ΪÁËGCF²âÊÔ¶ø¶¨Òå2010/3/3 SHIFANGMING
+=========================================================================*/
+#define LTE_GCF_TRS_EVENT_BASE (DWORD)(TRS_SIMULENPDI_EVENT_END + 1)
+#define LTE_GCF_TRS_RSP_EVENT (DWORD)(LTE_GCF_TRS_EVENT_BASE + 10)
+#define LTE_GCF_TRS_EVENT_END (DWORD)(LTE_GCF_TRS_EVENT_BASE + 19)
+
+#define LTE_GCF_TIMER_EVENT_BASE (DWORD)(LTE_GCF_TRS_EVENT_END + 1)
+#define LTE_GCF_TIMER_EVENT_END (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 19)
+
+
+/*TRSºÍENRLCÄ£¿éÖ®¼äµÄÏûϢʼþ2010/3/1 LIUHUAN*/
+#define TRS_ENRLC_EVENT_BASE (DWORD)(LTE_GCF_TIMER_EVENT_END + 1)
+#define TRS_ENRLC_RSP_EVENT (DWORD)(TRS_ENRLC_EVENT_BASE + 10)
+#define TRS_ENRLC_EVENT_END (DWORD)(TRS_ENRLC_EVENT_BASE + 19)
+
+#define ENPDCP_ENRLC_EVENT_BASE (DWORD)(TRS_ENRLC_EVENT_END + 1)
+#define ENPDCP_ENRLC_EVENT_END (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 9)
+
+//--ENMEL2ÏûϢʼþ
+#define ENMEL2_EVENT_BASE (DWORD)(ENPDCP_ENRLC_EVENT_END + 1)
+#define ENMEL2_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5)
+#define ENMEL2_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6)
+/**************************************************PS LTE msg range end********************************************************/
+
+
+/**************************************************PS W msg range start********************************************************/
+
+/*WRLCºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_WRLC_EVENT_BASE (DWORD)(EVENT_PS_W_BASE + 1)
+#define PDCP_WRLC_EVENT_END (DWORD)(PDCP_WRLC_EVENT_BASE + 9)
+
+
+/*WRLCºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define WRLC_WRRC_EVENT_BASE (DWORD)(PDCP_WRLC_EVENT_END + 1)
+#define WRLC_WRRC_RSP_EVENT (DWORD)(WRLC_WRRC_EVENT_BASE + 30)
+#define WRLC_WRRC_EVENT_END (DWORD)(WRLC_WRRC_EVENT_BASE + 59)
+
+/*WMACºÍWRRCµÄÏûÏ¢·¶Î§(70)*/
+#define WMAC_WRRC_EVENT_BASE (DWORD)(WRLC_WRRC_EVENT_END + 1)
+#define WMAC_WRRC_RSP_EVENT (DWORD)(WMAC_WRRC_EVENT_BASE + 40)
+#define WMAC_WRRC_EVENT_END (DWORD)(WMAC_WRRC_EVENT_BASE + 69)
+
+/*WMAC-UL/DLºÍWMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define WMAC_WMAC_EVENT_BASE (DWORD)(WMAC_WRRC_EVENT_END + 1)
+#define WMAC_WMAC_EVENT_END (DWORD)(WMAC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1W_WRRC_EVENT_BASE (DWORD)(WMAC_WMAC_EVENT_END + 1)
+#define L1W_WRRC_RSP_EVENT (DWORD)(L1W_WRRC_EVENT_BASE + 30)
+#define L1W_WRRC_EVENT_END (DWORD)(L1W_WRRC_EVENT_BASE + 59)
+
+/*PDCPºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_WRRC_EVENT_BASE (DWORD)(L1W_WRRC_EVENT_END + 1)
+#define PDCP_WRRC_RSP_EVENT (DWORD)(PDCP_WRRC_EVENT_BASE + 30)
+#define PDCP_WRRC_EVENT_END (DWORD)(PDCP_WRRC_EVENT_BASE + 59)
+
+/*WRLCºÍWMACµÄÏûÏ¢·¶Î§(20)*/
+#define WRLC_WMAC_EVENT_BASE (DWORD)(PDCP_WRRC_EVENT_END + 1)
+#define WRLC_WMAC_EVENT_END (DWORD)(WRLC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWMACµÄÏûÏ¢·¶Î§(10)*/
+#define WMAC_L1W_EVENT_BASE (DWORD)(WRLC_WMAC_EVENT_END + 1)
+#define WMAC_L1W_EVENT_END (DWORD)(WMAC_L1W_EVENT_BASE + 9)
+
+/*WRRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define WRRC_EVENT_BASE (DWORD)(WMAC_L1W_EVENT_END + 1)
+#define WRRC_EVENT_END (DWORD)(WRRC_EVENT_BASE + 99)
+
+/*L1WÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1W_EVENT_BASE (DWORD)(WRRC_EVENT_END + 1)
+#define L1W_EVENT_END (DWORD)(L1W_EVENT_BASE + 19)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_WAS_EVENT_BASE (DWORD)(L1W_EVENT_END + 1)
+#define ASC_WAS_RSP_EVENT (DWORD)(ASC_WAS_EVENT_BASE + 50)
+#define ASC_WAS_EVENT_END (DWORD)(ASC_WAS_EVENT_BASE + 99)
+
+/*WÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§140()*/
+
+#define WRRC_TIMER_EVENT_BASE (DWORD)(ASC_WAS_EVENT_END + 1)
+#define WRRC_TIMER_EVENT_END (DWORD)(WRRC_TIMER_EVENT_BASE + 79)
+
+#define WRLC_TIMER_EVENT_BASE (DWORD)(WRRC_TIMER_EVENT_END + 1)
+#define WRLC_TIMER_EVENT_END (DWORD)(WRLC_TIMER_EVENT_BASE + 19)
+
+#define WMAC_TIMER_EVENT_BASE (DWORD)(WRLC_TIMER_EVENT_END + 1)
+#define WMAC_TIMER_EVENT_END (DWORD)(WMAC_TIMER_EVENT_BASE + 19)
+
+#define L1W_TIMER_EVENT_BASE (DWORD)(WMAC_TIMER_EVENT_END + 1)
+#define L1W_TIMER_EVENT_END (DWORD)(L1W_TIMER_EVENT_BASE + 19)
+
+/*W²âÊÔÏûÏ¢·¶Î§(40)*/
+
+#define WSIR_TEST_EVENT_BASE (DWORD)(L1W_TIMER_EVENT_END + 1)
+#define WSIR_TEST_EVENT_END (DWORD)(WSIR_TEST_EVENT_BASE + 9)
+
+#define NWRLC_EVENT_BASE (DWORD)(WSIR_TEST_EVENT_END + 1)
+#define NWRLC_EVENT_END (DWORD)(NWRLC_EVENT_BASE + 19)
+
+#define NWMAC_EVENT_BASE (DWORD)(NWRLC_EVENT_END + 1)
+#define NWMAC_EVENT_END (DWORD)(NWMAC_EVENT_BASE + 9)
+
+/*º¯ÊýÐÅÁî¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define WRRC_FUNC_EVENT_BASE (DWORD)(NWMAC_EVENT_END + 1)
+#define WRRC_FUNC_EVENT_END (DWORD)(WRRC_FUNC_EVENT_BASE + 49)
+
+/*º¯Êý·µ»ØÖµ¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define RRC_FUNC_TRACE_BASE (DWORD)(WRRC_FUNC_EVENT_END + 1)
+#define RRC_FUNC_TRACE_END (DWORD)(RRC_FUNC_TRACE_BASE + 49)
+
+/**************************************************PS W msg range end********************************************************/
+/* ========================================================================
+ CM-MM/GMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 0)
+#define CM_EST_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 1)
+#define CM_REL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 2)
+#define CM_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 3)
+#define CM_CANCEL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 4)
+#define CM_REEST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 5)
+#define CM_CMSRV_IND_EV (DWORD)(CM_MM_EVENT_BASE + 6)
+#define CM_IN_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 7)
+#define CM_OUT_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 8)
+#define CM_DATA_IND_EV (DWORD)(CM_MM_EVENT_BASE + 9)
+#define CM_RATCHG_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 10)
+#define CM_RATCHG_END_IND_EV (DWORD)(CM_MM_EVENT_BASE + 11)
+#define CM_RRC_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 12)
+#define CM_SRVCC_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 13)
+#define CM_SRVCC_SUCC_IND_EV (DWORD)(CM_MM_EVENT_BASE + 14)
+#define CM_SRVCC_FAIL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 15)
+#define CM_SM_ONLY_ONE_EPDNCON_EV (DWORD)(CM_MM_EVENT_BASE + 16)
+#define CM_ESM_DETACH_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 17)
+#define CM_SM_DEACT_NON_EMERGENCY_EV (DWORD)(CM_MM_EVENT_BASE + 18)
+#define CC_UMM_RETURN_IMS_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 19)
+#define UMM_CC_RETURN_IMS_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 20)
+/*IVSÏ߳̽ÓÊÕÏûÏ¢*/
+#define IVS_DL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 21)
+#define CC_IVS_RESET_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 22)
+#define CC_IVS_MSD_IND_EV (DWORD)(CM_MM_EVENT_BASE + 23)
+/*IVS·¢¸øCC*/
+#define IVS_CC_MSD_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 24)
+#define IVS_CC_MSD_STATE_IND_EV (DWORD)(CM_MM_EVENT_BASE + 25)
+
+#define PSAP_UL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 26)
+#define CC_UMM_ECALL_EVENT_IND_EV (DWORD)(CM_MM_EVENT_BASE + 27)
+
+/* ========================================================================
+ UMM£MM/GMM/EMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 0)
+#define UMM_DETACH_REQ_EV (DWORD)(UMM_EVENT_BASE + 1)
+#define UMM_PENDING_REQ_EV (DWORD)(UMM_EVENT_BASE + 2)
+#define UMM_RESUME_REQ_EV (DWORD)(UMM_EVENT_BASE + 3)
+#define UMM_ABORT_REQ_EV (DWORD)(UMM_EVENT_BASE + 4)
+#define UMM_EMERGENCY_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 5)
+#define UMM_CSEST_REQ_EV (DWORD)(UMM_EVENT_BASE + 6)
+#define UMM_PAGE_IND_EV (DWORD)(UMM_EVENT_BASE + 7)
+#define UMM_CCO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 8)
+#define UMM_HO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 9)
+#define UMM_CELL_RESEL_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 10)
+#define UMM_LU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 11)
+#define UMM_FAIL_IND_EV (DWORD)(UMM_EVENT_BASE + 12)
+#define UMM_RU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 13)
+#define UMM_DETACH_IND_EV (DWORD)(UMM_EVENT_BASE + 14)
+#define UMM_DETACH_CNF_EV (DWORD)(UMM_EVENT_BASE + 15)
+#define UMM_MM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 16)
+#define UMM_GMM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 17)
+#define UMM_EMERGENCY_T3412_EXPIRY_IND_EV (DWORD)(UMM_EVENT_BASE + 18)
+#define UMM_CELL_NO_CHG_IND_EV (DWORD)(UMM_EVENT_BASE + 19)
+#define UMM_CS_EST_REJ_EV (DWORD)(UMM_EVENT_BASE + 20)
+#define UMM_CS_SRV_NOTIFY_IND_EV (DWORD)(UMM_EVENT_BASE + 21)
+#define UMM_CCO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 22)
+#define UMM_HO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 23)
+#define UMM_CELL_RESEL_END_IND_EV (DWORD)(UMM_EVENT_BASE + 24)
+#define UMM_ATTACH_STATE_SYNC_REQ_EV (DWORD)(UMM_EVENT_BASE + 25)
+#define UMM_CHECK_REL_RRC_REQ_EV (DWORD)(UMM_EVENT_BASE + 26)
+#define UMM_PS_CONTEXT_IND_EV (DWORD)(UMM_EVENT_BASE + 27)
+#define UMM_START_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 28)
+#define UMM_STOP_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 29)
+#define UMM_POWEROFF_IND_RV (DWORD)(UMM_EVENT_BASE + 30)
+#define UMM_SWITCH_CARD_END_EV (DWORD)(UMM_EVENT_BASE + 31)
+/* ========================================================================
+ UMM£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_ASC_CAMPON_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 0)
+#define UMM_ASC_CAMPON_ANYCELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 1)
+#define UMM_ASC_UPDATE_PLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 2)
+#define UMM_ASC_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 3)
+#define UMM_ASC_SWITCH_RADIO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 4)
+#define UMM_ASC_TRY_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 5)
+#define UMM_ASC_STOP_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 6)
+#define UMM_ASC_PCH_PRE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 7)
+#define UMM_ASC_ABORT_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 8)
+#define UMM_ASC_UPDATE_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 9)
+#define UMM_ASC_INACTIVE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 10)
+#define UMM_ASC_PAGE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 11)
+#define UMM_ASC_LOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 12)
+#define UMM_ASC_UNLOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 13)
+#define UMM_ASC_GSM_SRV_NOTIFY_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 14)
+#define UMM_ASC_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 15)
+#define UMM_ASC_UPDATE_SYSCONFIG_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 16)
+#define UMM_ASC_UPDATE_LTE_ACT_EV (DWORD)(UMM_ASC_EVENT_BASE + 17)
+#define UMM_ASC_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(UMM_ASC_EVENT_BASE + 18)
+#define UMM_ASC_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 19)
+#define UMM_ASC_STOP_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 20)
+#define UMM_ASC_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 21)
+#define UMM_ASC_SYS_CAMP_LTESUBACT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 22)
+#define UMM_ASC_DELFORBIDDENLAILIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 23)
+#define UMM_ASC_HPPLMN_END_IND_EV (DWORD)(UMM_ASC_EVENT_BASE + 24)
+#define UMM_ASC_XCELLINFO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 25)
+#define UMM_ASC_XCELLINFO_ABORT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 26)
+#define UMM_ASC_UPDATE_ECALLMODE_EV (DWORD)(UMM_ASC_EVENT_BASE + 27)
+
+#define UMM_ASC_CELL_INFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 0)
+#define UMM_ASC_NOCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 1)
+#define UMM_ASC_PLMN_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 2)
+#define UMM_ASC_SWITCH_RADIO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 3)
+#define UMM_ASC_CNINFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 4)
+#define UMM_ASC_TRY_HPPLMN_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 5)
+#define UMM_ASC_PLMN_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 6)
+#define UMM_ASC_INACTIVE_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 7)
+#define UMM_ASC_HO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 9)
+#define UMM_ASC_CCO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 10)
+#define UMM_ASC_CELL_RESEL_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 11)
+#define UMM_ASC_HO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 12)
+#define UMM_ASC_CCO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 13)
+#define UMM_ASC_CELL_RESEL_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 14)
+#define UMM_ASC_TRY_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 15)
+#define UMM_ASC_ABORT_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 16)
+#define UMM_ASC_LOCK_CELL_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 17)
+#define UMM_ASC_CSG_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 18)
+#define UMM_ASC_CSG_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 19)
+#define UMM_ASC_TBF_RELEASE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 20)
+#define UMM_ASC_SCAN_UE_BAND_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 21)
+#define UMM_ASC_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(UMM_ASC_RSP_EVENT + 22)
+#define UMM_ASC_CELL_UPDATE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 23) /*GRR֪ͨUMM×öСÇø¸üÐÂ*/
+#define UMM_ASC_RECONST_PSRES_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 24)
+#define UMM_ASC_SUBMODE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 25)
+#define UMM_ASC_CELL_LOST_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 26)
+#define UMM_ASC_CELL_RECOVERAGE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 27)
+#define UMM_ASC_XCELLINFO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 28)
+#define UMM_ASC_XCELLINFO_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 29)
+#define UMM_ASC_NEIGCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 30)
+#define UMM_ASC_SCAN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 31)
+/* ========================================================================
+ MM/GMM/CC£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_ASC_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 0)
+#define GMM_ASC_REL_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 1)
+#define GMM_ASC_DATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 2)
+#define GMM_ASC_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 3)
+#define GMM_ASC_GRR_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 4)
+#define GMM_ASC_GRR_INFO_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 5)
+#define GMM_ASC_LL_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 6)
+#define GMM_ASC_LL_TRIGGER_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 7)
+#define GMM_ASC_LL_SUSPEND_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 8)
+#define GMM_ASC_LL_RESUME_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 9)
+#define GMM_ASC_LL_UNITDATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 10)
+#define GMM_ASC_CLEAN_PEND_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 11)
+
+#define GMM_ASC_EST_CNF_EV (DWORD)(GMM_ASC_RSP_EVENT + 0)
+#define GMM_ASC_EST_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 1)
+#define GMM_ASC_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 2)
+#define GMM_ASC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 3)
+#define GMM_ASC_CCSYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 4)
+#define GMM_ASC_PAGE_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 5)
+#define GMM_ASC_DATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 6)
+#define GMM_ASC_SUSPEND_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 7)
+#define GMM_ASC_GSM_CC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 8)
+#define GMM_ASC_CS_RAB_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 9)
+#define GMM_ASC_GSM_CC_TCH_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 10)
+#define GMM_ASC_SAPI3_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 11)
+#define GMM_ASC_SRVCC_START_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 12)
+#define GMM_ASC_SRVCC_END_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 13)
+#define GMM_ASC_LL_UNITDATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 14)
+#define GMM_ASC_LL_TRIGGER_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 15)
+#define GMM_ASC_LL_STATUS_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 16)
+#define GMM_ASC_LL_USER_DATA_PRESENT_EV (DWORD)(GMM_ASC_RSP_EVENT + 17)
+#define GMM_ASC_GSM_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 18)
+#define GMM_ASC_UTRA_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 19)/*WCDMA*//*¶ÔÓ¦AS²ãµÄASC_TD_CURR_BEAR_IND_EVºÍASC_W_CURR_BEAR_IND_EV*/
+#define GMM_ASC_PSHO_INFO_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 20) /*LLC֪ͨGMMÇл»Ïà¹Ø¼ÓÃÜËã·¨ ASC£>GMM*/
+#define GMM_ASC_SEND_CMP_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 21)
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* ========================================================================
+ ASC£TD ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->UCSR*/
+#define ASC_TD_SWITCH_RADIO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 0)
+#define ASC_TD_CAMPON_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 1)
+#define ASC_TD_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 2)
+#define ASC_TD_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 3)
+#define ASC_TD_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 4)
+#define ASC_TD_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 5)
+#define ASC_TD_TRY_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 6)
+#define ASC_TD_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 7)
+#define ASC_TD_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_UAS_EVENT_BASE + 8)
+#define ASC_TD_IRAT_CAMPON_REJ_EV (DWORD)(ASC_UAS_EVENT_BASE + 9)
+#define ASC_TD_IRAT_CAMPON_CNF_EV (DWORD)(ASC_UAS_EVENT_BASE + 10)
+#define ASC_TD_ABORT_RSP_EV (DWORD)(ASC_UAS_EVENT_BASE + 11)
+
+/*NAS->ASC->AS*/
+#define ASC_TD_LOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 12)
+#define ASC_TD_UNLOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 13)
+#define ASC_TD_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 14)
+#define ASC_TD_DATA_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 15)
+#define ASC_TD_REL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 16)
+#define ASC_TD_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 17)
+#define ASC_TD_PAGE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 18)
+#define ASC_TD_INACTIVE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 19)
+#define ASC_TD_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 20)
+#define ASC_TD_NO_DRX_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 21)
+#define ASC_TD_DRX_RSV_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 22)
+#define ASC_TD_STOP_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 23)
+#define ASC_TD_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 24)
+#define ASC_TD_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 25)
+#define ASC_TD_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 26)
+#define ASC_TD_XCELLINFO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 27)
+#define ASC_TD_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 28)
+
+/*UCSR->ASC */
+#define ASC_TD_SWITCH_RADIO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 0)
+#define ASC_TD_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 1)
+#define ASC_TD_IRAT_CAMPON_REQ_EV (DWORD)(ASC_UAS_RSP_EVENT + 2)
+#define ASC_TD_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 3)
+#define ASC_TD_TRY_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 4)
+
+#define ASC_TD_NOCELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 5)
+#define ASC_TD_PLMN_LIST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 6)
+#define ASC_TD_PLMN_LIST_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 7)
+#define ASC_TD_TRY_HPPLMN_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 8)
+#define ASC_TD_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 9)
+#define ASC_TD_ABORT_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 10)
+#define ASC_TD_SUBMODE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 11)
+#define ASC_TD_LOCK_CELL_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 12)
+#define ASC_TD_SCAN_UE_BAND_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 13)
+
+/*UCSR->ASC or UCER->ASC*/
+#define ASC_TD_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_UAS_RSP_EVENT + 14)
+#define ASC_TD_INACTIVE_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 15)
+#define ASC_TD_EST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 16)
+#define ASC_TD_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 17)
+#define ASC_TD_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 18)
+#define ASC_TD_PAGING_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 19)
+#define ASC_TD_SYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 20)
+#define ASC_TD_PCH_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 21)
+#define ASC_TD_UURLC_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 22)
+#define ASC_TD_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 23)
+#define ASC_TD_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 24)
+#define ASC_TD_SRVCC_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 25)
+#define ASC_TD_SRVCC_END_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 26)
+#define ASC_TD_CCSYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 27)
+#define ASC_TD_CS_RAB_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 28)
+#define ASC_TD_CNINFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 29)
+
+/* URBC->ASC */
+#define ASC_TD_CURR_BEAR_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 30)
+#define ASC_TD_RECONST_PSRES_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 31)
+#define ASC_TD_CELL_LOST_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 32)
+#define ASC_TD_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 33)
+
+/*UCSR->ASC add*/
+#define ASC_TD_XCELLINFO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 34)
+#define ASC_TD_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 35)
+#define ASC_TD_XCELLINFO_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 36)
+
+/* ========================================================================
+ ASC£WCDMA ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->WCSR*/
+#define ASC_W_SWITCH_RADIO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 0)
+#define ASC_W_CAMPON_CELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 1)
+#define ASC_W_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 2)
+#define ASC_W_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 3)
+#define ASC_W_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 4)
+#define ASC_W_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 5)
+#define ASC_W_TRY_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 6)
+#define ASC_W_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 7)
+#define ASC_W_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_WAS_EVENT_BASE + 8)
+#define ASC_W_IRAT_CAMPON_REJ_EV (DWORD)(ASC_WAS_EVENT_BASE + 9)
+#define ASC_W_IRAT_CAMPON_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 10)
+#define ASC_W_ABORT_RSP_EV (DWORD)(ASC_WAS_EVENT_BASE + 11)
+#define ASC_W_IRAT_INACTIVE_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 12)
+
+/*NAS->ASC->AS*/
+#define ASC_W_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 13)
+#define ASC_W_DATA_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 14)
+#define ASC_W_REL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 15)
+#define ASC_W_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 16)
+#define ASC_W_PAGE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 17)
+#define ASC_W_INACTIVE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 18)
+#define ASC_W_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 19)
+#define ASC_W_NO_DRX_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 20)
+#define ASC_W_DRX_RSV_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 21)
+#define ASC_W_STOP_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 22)
+#define ASC_W_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 23)
+#define ASC_W_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 24)
+#define ASC_W_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 25)
+#define ASC_W_XCELLINFO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 26)
+#define ASC_W_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 27)
+
+/*WCSR->ASC */
+#define ASC_W_SWITCH_RADIO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 0)
+#define ASC_W_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 1)
+#define ASC_W_IRAT_CAMPON_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 2)
+#define ASC_W_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 3)
+#define ASC_W_TRY_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 4)
+#define ASC_W_IRAT_INACTIVE_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 5)
+
+#define ASC_W_NOCELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 6)
+#define ASC_W_PLMN_LIST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 7)
+#define ASC_W_PLMN_LIST_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 8)
+#define ASC_W_TRY_HPPLMN_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 9)
+#define ASC_W_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 10)
+#define ASC_W_ABORT_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 11)
+#define ASC_W_SUBMODE_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 12)
+#define ASC_W_SCAN_UE_BAND_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 13)
+
+/*WCSR->ASC or WCER->ASC*/
+#define ASC_W_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_WAS_RSP_EVENT + 14)
+#define ASC_W_INACTIVE_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 15)
+#define ASC_W_EST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 16)
+#define ASC_W_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 17)
+#define ASC_W_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 18)
+#define ASC_W_PAGING_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 19)
+#define ASC_W_SYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 20)
+#define ASC_W_PCH_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 21)
+#define ASC_W_UURLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 22)
+#define ASC_W_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 23)
+#define ASC_W_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 24)
+#define ASC_W_SRVCC_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 25)
+#define ASC_W_SRVCC_END_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 26)
+#define ASC_W_CCSYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 27)
+#define ASC_W_CS_RAB_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 28)
+#define ASC_W_CNINFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 29)
+/* WRBC->ASC */
+#define ASC_W_CURR_BEAR_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 30)
+#define ASC_W_RECONST_PSRES_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 31)
+/*WCDMA*/
+#define ASC_W_UWRLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 32)
+/*WCSR/UCSR -> ASC*/
+#define ASC_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 33)
+#define ASC_UTRA_RESEL_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 34)
+#define ASC_UTRA_COMPLETE_EV (DWORD)(ASC_WAS_RSP_EVENT + 35)
+#define ASC_W_XCELLINFO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 36)
+#define ASC_W_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 37)
+#define ASC_W_XCELLINFO_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 38)
+
+/* ========================================================================
+ ASC£GSM ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->GSMAÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 0)
+#define ASC_GSM_CAMPON_CELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 1)
+#define ASC_GSM_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 2)
+#define ASC_GSM_INACTIVE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 3)
+#define ASC_GSM_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 4)
+#define ASC_GSM_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 5)
+#define ASC_GSM_TRY_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 6)
+#define ASC_GSM_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 7)
+#define ASC_GSM_UPDATE_PARAM_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 8)
+#define ASC_GSM_UPDATE_EPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 9)
+#define ASC_GSM_GSM_SRV_NOTIFY_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 10)
+#define ASC_GSM_PCHPRE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 11)
+#define ASC_GSM_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 12)
+#define ASC_GSM_EST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 13)
+#define ASC_GSM_DATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 14)
+#define ASC_GSM_REL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 15)
+#define ASC_GSM_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 16)
+#define ASC_GSM_INFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 17)
+#define ASC_GSM_ABORT_RSP_EV (DWORD)(ASC_GAS_EVENT_BASE + 18)
+
+/*ASC->GSMAµÄ,GSMAÊÊÅäLLCµÄÏûϢʼþºÅ*/
+#define ASC_LLC_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 19)
+#define ASC_LLC_TRIGGER_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 20)
+#define ASC_LLC_SUSPEND_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 21)
+#define ASC_LLC_RESUME_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 22)
+#define ASC_LLC_UNITDATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 23)
+#define ASC_SNP_GMM_SEQ_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 24)
+
+//ÁÚÇøÐÅÏ¢»ñÈ¡ÏûÏ¢
+#define ASC_GSM_XCELLINFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 25)
+#define ASC_GSM_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 26)
+
+/*GSMA->ASCÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 0)
+#define ASC_GSM_CELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 1)
+#define ASC_GSM_NOCELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 2)
+#define ASC_GSM_INACTIVE_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 3)
+#define ASC_GSM_PLMN_LIST_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 4)
+#define ASC_GSM_PLMN_LIST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 5)
+#define ASC_GSM_ABORT_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 6)
+#define ASC_GSM_TRY_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 7)
+#define ASC_GSM_TRY_HPPLMN_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 8)
+#define ASC_GSM_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 9)
+#define ASC_GSM_CELL_UPDATE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 10)
+#define ASC_GSM_SUBMODE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 11)
+#define ASC_GSM_EST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 12)
+#define ASC_GSM_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 13)
+#define ASC_GSM_SYNC_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 14)
+#define ASC_GSM_CCSYNC_IND_GSM_EV (DWORD)(ASC_GAS_RSP_EVENT + 15)
+#define ASC_GSM_SUSPEND_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 16)
+#define ASC_GSM_PAGE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 17)
+#define ASC_GSM_EST_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 18)
+#define ASC_GSM_DATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 19)
+#define ASC_GSM_SAPI3_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 20)
+#define ASC_GSM_CCTCH_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 21)
+#define ASC_GSM_TBF_RELEASE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 22)
+#define ASC_GSM_UTRA_CSHO_ENDIND_EV (DWORD)(ASC_GAS_RSP_EVENT + 23)
+
+#define ASC_LLC_UNITDATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 24)
+#define ASC_LLC_TRIGGER_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 25)
+#define ASC_LLC_STATUS_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 26)
+#define ASC_LLC_USER_DATA_PRESENT_EV (DWORD)(ASC_GAS_RSP_EVENT + 27)
+#define ASC_LLC_PSHO_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 28)
+
+/*GSMA->ASC->CBS (ASC͸´«)*/
+#define ASC_GSM_ETWS_NOTIFY_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 29)
+/*AS_GSM_LTE_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_REDIRECT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 30)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_RESEL_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 31)
+
+/*GSMA->ASC->SM (ASC͸´«)*/
+#define ASC_GSM_CURR_BEAR_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 32)
+#define ASC_SNP_GMM_SEQ_RSP_EV (DWORD)(ASC_GAS_RSP_EVENT + 33)
+
+/*GSMA->ASC->SMS (ASC͸´«)*/
+#define ASC_GSM_SEND_CMP_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 34)
+
+#define ASC_GSM_XCELLINFO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 35)
+#define ASC_GSM_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 36)
+#define ASC_GSM_XCELLINFO_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 37)
+
+/* ========================================================================
+ ASC£LTE ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC-->EURRC*/
+#define ASC_LTE_SWITCH_RADIO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 0)
+#define ASC_LTE_CAMPON_CELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 1)
+#define ASC_LTE_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 2)
+#define ASC_LTE_UPDATE_PLMN_FTAI_IND_EV (DWORD)(ASC_EUAS_EVENT_BASE + 3)
+#define ASC_LTE_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 4)
+#define ASC_LTE_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 5)
+#define ASC_LTE_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 6)
+#define ASC_LTE_STOP_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 7)
+#define ASC_LTE_TRY_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 8)
+#define ASC_LTE_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 9)
+#define ASC_LTE_EST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 10)
+#define ASC_LTE_EST_ABT_EV (DWORD)(ASC_EUAS_EVENT_BASE + 11)
+#define ASC_LTE_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 12)
+#define ASC_LTE_KENB_RSP_EV (DWORD)(ASC_EUAS_EVENT_BASE + 13)
+#define ASC_LTE_REL_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 14)
+#define ASC_LTE_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 15)
+#define ASC_LTE_INACTIVE_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 16)
+#define ASC_LTE_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_EUAS_EVENT_BASE + 17)
+#define ASC_LTE_DETACH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 18)
+#define ASC_LTE_GROUP_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 19)
+#define ASC_LTE_SCANSWITCH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 20)
+#define ASC_LTE_XCELLINFO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 21)
+#define ASC_LTE_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 22)
+#define ASC_LTE_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 23)
+
+/* EURRC->ASC */
+#define ASC_LTE_SWITCH_RADIO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 0)
+#define ASC_LTE_CELL_INFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 1)
+#define ASC_LTE_NOCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 2)
+#define ASC_LTE_PAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 3)
+#define ASC_LTE_PLMN_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 4)
+#define ASC_LTE_PLMN_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 5)
+#define ASC_LTE_CSG_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 6)
+#define ASC_LTE_CSG_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 7)
+#define ASC_LTE_TRY_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 8)
+#define ASC_LTE_TRY_HPPLMN_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 9)
+#define ASC_LTE_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 10)
+#define ASC_LTE_ABORT_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 11)
+#define ASC_LTE_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 13)
+#define ASC_LTE_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 14)
+#define ASC_LTE_DATA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 15)
+#define ASC_LTE_EST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 16)
+#define ASC_LTE_EST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 17)
+#define ASC_LTE_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 18)
+#define ASC_LTE_ABA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 19)
+#define ASC_LTE_DRB_SETUP_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 20)
+#define ASC_LTE_TRANS_FAIL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 21)
+#define ASC_LTE_KENB_REQ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 22)
+#define ASC_LTE_UE_INFO_CHANGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 23)
+#define ASC_LTE_DATA_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 24)
+#define ASC_LTE_SEC_PARA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 25)
+#define ASC_LTE_INACTIVE_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 26)
+#define ASC_LTE_ABORT_RSP_EV (DWORD)(ASC_EUAS_RSP_EVENT + 27)
+/*AS_LTE_TD_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_REDIRECT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 28)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_RESEL_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 29)
+#define ASC_LTE_SRVCC_START_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 30)
+#define ASC_LTE_SRVCC_END_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 31)
+#define ASC_LTE_CMAS_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 32)
+#define ASC_LTE_SCAN_UE_BAND_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 33)
+#define ASC_LTE_CELL_LOST_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 34)
+#define ASC_LTE_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 35)
+#define ASC_LTE_GROUP_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 36)
+#define ASC_LTE_TGCCH_MSG_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 37)
+#define ASC_LTE_SCANGROUPINFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 38)
+#define ASC_LTE_SET_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 39)
+#define ASC_LTE_REL_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 40)
+#define ASC_LTE_XCELLINFO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 41)
+#define ASC_LTE_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 42)
+#define ASC_LTE_XCELLINFO_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 43)
+#define ASC_LTE_NEIGCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 44)
+#define ASC_LTE_SCAN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 45)
+/* ========================================================================
+ ASC£¸÷AS¹«¹²ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*LTE->UTRAÖØÑ¡*/
+#define AS_LTE_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 0)
+#define AS_LTE_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 1)
+#define AS_LTE_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 2)
+
+/*LTE->UTRAÖض¨Ïò*/
+#define AS_LTE_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 3)
+#define AS_LTE_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 4)
+#define AS_LTE_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 5)
+
+/*LTE->UTRA PSÇл»*/
+#define AS_LTE_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 6)
+#define AS_LTE_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 7)
+#define AS_LTE_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 8)
+
+/*LTE->GSMÖØÑ¡*/
+#define AS_LTE_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 9)
+#define AS_LTE_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 10)
+#define AS_LTE_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 11)
+
+/*LTE->GSMÖض¨Ïò*/
+#define AS_LTE_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 12)
+#define AS_LTE_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 13)
+#define AS_LTE_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 14)
+
+/*LTE->TD CSÇл»*/
+#define AS_LTE_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 15)
+#define AS_LTE_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 16)
+#define AS_LTE_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 17)
+
+/*LTE->GSM CCO*/
+#define AS_LTE_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 18)
+#define AS_LTE_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 19)
+#define AS_LTE_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 20)
+
+/*LTE->GSM PSÇл»*/
+#define AS_LTE_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 21)
+#define AS_LTE_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 22)
+#define AS_LTE_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 23)
+
+/*UTRA->LTEÖØÑ¡*/
+#define AS_UTRA_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 24)
+#define AS_UTRA_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 25)
+#define AS_UTRA_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 26)
+
+/*UTRA->LTEÖض¨Ïò*/
+#define AS_UTRA_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 27)
+#define AS_UTRA_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 28)
+#define AS_UTRA_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 29)
+
+/*UTRA->LTE PSÇл»*/
+#define AS_UTRA_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 30)
+#define AS_UTRA_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 31)
+#define AS_UTRA_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 32)
+
+/*UTRA->GSMÖØÑ¡*/
+#define AS_UTRA_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 33)
+#define AS_UTRA_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 34)
+#define AS_UTRA_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 35)
+
+/*UTRA>GSMÖض¨Ïò*/
+#define AS_UTRA_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 36)
+#define AS_UTRA_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 37)
+#define AS_UTRA_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 38)
+
+/*UTRA->GSM CSÇл»*/
+#define AS_UTRA_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 39)
+#define AS_UTRA_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 40)
+#define AS_UTRA_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 41)
+
+/*UTRA->GSM CCO*/
+#define AS_UTRA_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 42)
+#define AS_UTRA_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 43)
+#define AS_UTRA_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 44)
+
+/*UTRA->GSM PSÇл»*/
+#define AS_UTRA_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 45)
+#define AS_UTRA_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 46)
+#define AS_UTRA_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 47)
+
+/*UTRA->GSM Êý¾Ý°áÒÆ*/
+#define AS_UTRA_GSM_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 48)
+
+/*GSM->LTEÖØÑ¡*/
+#define AS_GSM_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 49)
+#define AS_GSM_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 50)
+#define AS_GSM_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 51)
+
+/*GSM->LTEÖض¨Ïò*/
+#define AS_GSM_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 52)
+#define AS_GSM_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 53)
+#define AS_GSM_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 54)
+
+/*GSM->LTE PSÇл»*/
+#define AS_GSM_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 55)
+#define AS_GSM_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 56)
+#define AS_GSM_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 57)
+
+/*GSM->LTE CCO*/
+#define AS_GSM_LTE_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 58)
+#define AS_GSM_LTE_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 59)
+#define AS_GSM_LTE_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 60)
+
+/*GSM->UTRAÖØÑ¡*/
+#define AS_GSM_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 61)
+#define AS_GSM_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 62)
+#define AS_GSM_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 63)
+
+/*GSM->UTRAÖض¨Ïò*/
+#define AS_GSM_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 64)
+#define AS_GSM_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 65)
+#define AS_GSM_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 66)
+
+/*GSM->UTRA CSÇл»*/
+#define AS_GSM_UTRA_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 67)
+#define AS_GSM_UTRA_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 68)
+#define AS_GSM_UTRA_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 69)
+
+/*GSM->UTRA PSÇл»*/
+#define AS_GSM_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 70)
+#define AS_GSM_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 71)
+#define AS_GSM_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 72)
+
+/*GSM->UTRA CCO*/
+#define AS_GSM_UTRA_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 73)
+#define AS_GSM_UTRA_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 74)
+#define AS_GSM_UTRA_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 75)
+
+/*GSM->UTRA Êý¾Ý°áÒÆ*/
+#define AS_GSM_UTRA_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 76)
+/*WCDMA PREDEF*/
+#define AS_GSM_UTRA_READ_PREDEF_CONF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 77)
+#define AS_GSM_UTRA_READ_PREDEF_CONF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 78)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 79)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 80)
+
+
+/*NAS->ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_UPDATE_SYSCONFIG_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 81)
+#define AS_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 82)
+
+/*ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_L1_RSRC_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 83)
+#define AS_L1_RSRC_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 84)
+#define AS_L1_RSRC_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 85)
+#define AS_L1_RSRC_FREE_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 86)
+
+/*.(UCSR EUCSR GSMA)AS->ASC*/
+#define AS_IRAT_CCO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 87)
+#define AS_IRAT_HO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 88)
+#define AS_IRAT_CELL_RESEL_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 89)
+
+#define AS_LTE_GSM_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 90)
+#define AS_LTE_GSM_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 91)
+#define AS_LTE_GSM_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 92)
+#define AS_LTE_GSM_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 93)
+
+#define AS_LTE_UTRA_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 94)
+#define AS_LTE_UTRA_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 95)
+#define AS_LTE_UTRA_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 96)
+#define AS_LTE_UTRA_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 97)
+
+#define AS_LTE_TD_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 98)
+#define AS_LTE_W_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 99)
+
+/* ========================================================================
+ CBS£ASCÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_ASC_NO_DRX_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 0)
+#define CBS_ASC_DRX_RSV_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 1)
+#define CBS_ASC_STOP_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 2)
+
+#define CBS_ASC_PCH_CELL_INFO_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 0)
+#define CBS_ASC_UURLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 1)
+#define CBS_ASC_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 2)
+#define CBS_ASC_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 3)
+#define CBS_ASC_CMAS_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 4)
+/*WCDMA*/
+#define CBS_ASC_UWRLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ GMM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_GMM_SEQ_IND_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 0)
+#define SNP_GMM_SEQ_RSP_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ GMM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDCP_GMM_NW_REL_ANYRB_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 0)
+#define GMM_PDCP_RB_CHG_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ SM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_SM_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 0)
+#define SNP_SM_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 1)
+#define SNP_SM_MOD_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 2)
+#define SNP_SM_RAT_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 3)
+#define SNP_SM_RAT_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 4)
+#define SNP_SM_RAT_SEQ_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 5)
+#define SNP_SM_RAT_CHG_COMP_EV (DWORD)(SM_SNDCP_EVENT_BASE + 6)
+
+#define SNP_SM_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 0)
+#define SNP_SM_MOD_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 1)
+#define SNP_SM_STATUS_REQ_EV (DWORD)(SM_SNDCP_RSP_EVENT + 2)
+#define SNP_SM_RAT_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 3)
+#define SNP_SM_RAT_SEQ_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 4)
+#define SNP_SM_RAT_DEACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 5)
+
+/* ========================================================================
+ TAF£CCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_TAF_CONNECT_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 0)
+#define CC_TAF_CONNECT_CNF_EV (DWORD)(CC_TAF_EVENT_BASE + 1)
+#define CC_TAF_CONNECT_CNF_NEG_EV (DWORD)(CC_TAF_EVENT_BASE + 2)
+#define CC_TAF_RELEASE_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 3)
+#define CC_TAF_RELEASE_IND_EV (DWORD)(CC_TAF_EVENT_BASE + 4)
+#define CC_TAF_PEND_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 5)
+#define CC_TAF_RESUME_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS-UMMÖ®¼äµÄÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define UMM_CBS_START_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 0)
+#define UMM_CBS_STOP_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 1)
+
+#define UMM_CBS_CELL_INFO_IND_EV (DWORD)(UMM_CBS_RSP_EVENT + 0)
+
+/* ========================================================================
+ URRC/CC£SCIÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CSCI_CONFIG_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 0)
+#define CSCI_CDEC_CTRL_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 1)
+#define CSCI_CONFIG_REL_EV (DWORD)(AP_SCI_EVENT_BASE + 2)
+#define CSCI_CONFIG_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 3)
+#define CSCI_UNRECOVER_ERR_EV (DWORD)(AP_SCI_EVENT_BASE + 4)
+#define CSCI_CDEC_CTRL_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 5)
+
+/* ========================================================================
+ URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_READ_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 0)
+#define URRC_READ_SYSINFO_IND_EV (DWORD)(URRC_EVENT_BASE + 1)
+#define URRC_READ_SYSINFO_REJ_EV (DWORD)(URRC_EVENT_BASE + 2)
+#define URRC_STOP_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 3)
+#define URRC_READ_DYN_SIB_REQ_EV (DWORD)(URRC_EVENT_BASE + 4)
+#define URRC_READ_DYN_SIB_CNF_EV (DWORD)(URRC_EVENT_BASE + 5)
+#define URRC_SIB_MODIFIED_IND_EV (DWORD)(URRC_EVENT_BASE + 6)
+#define URRC_CELLUPDATE_REQ_EV (DWORD)(URRC_EVENT_BASE + 7)
+#define URRC_CELL_RESEL_REQ_EV (DWORD)(URRC_EVENT_BASE + 8)
+#define URRC_CELL_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 9)
+#define URRC_REL_CONN_REQ_EV (DWORD)(URRC_EVENT_BASE + 10)
+#define URRC_RESUME_CELL_REQ_EV (DWORD)(URRC_EVENT_BASE + 11)
+#define URRC_RPLMN_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 12)
+#define URRC_RESOURE_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 13)
+#define URRC_RESOURCE_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 14)
+#define URRC_UPDATE_EPLMN_REQ_EV (DWORD)(URRC_EVENT_BASE + 15)
+#define URRC_HIGH_MOBILITY_IND (DWORD)(URRC_EVENT_BASE + 16)
+#define URRC_HO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 17)
+#define URRC_HO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 18)
+#define URRC_HO_TO_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 19)
+#define URRC_HO_TO_UTRAN_CNF_EV (DWORD)(URRC_EVENT_BASE + 20)
+#define URRC_HO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 21)
+#define URRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 22)
+#define URRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 23)
+#define URRC_CCO_TO_UTRAN_IND_EV (DWORD)(URRC_EVENT_BASE + 24)
+#define URRC_CCO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 25)
+#define URRC_RADIO_LINK_FAIL_IND_EV (DWORD)(URRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define URRC_NEIBCELL_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 27)
+#define URRC_FACH_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 28)
+#define URRC_FACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 29)
+#define URRC_DRX_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 30)
+#define URRC_SEND_BUF_EST_REQ_EV (DWORD)(URRC_EVENT_BASE + 31)
+#define URRC_ABORT_RATCHG_REQ_EV (DWORD)(URRC_EVENT_BASE + 32)
+#define URRC_BAR_RESUME_IND_EV (DWORD)(URRC_EVENT_BASE + 33)
+#define URRC_CHG_CAMPON_TYPE_EV (DWORD)(URRC_EVENT_BASE + 34)
+#define URRC_GET_RF_REQ_EV (DWORD)(URRC_EVENT_BASE + 35) /*USIR->UCSR*/
+#define URRC_GET_RF_CNF_EV (DWORD)(URRC_EVENT_BASE + 36) /*UCSR->USIR*/
+#define URRC_SYSINFO_CONTAINER_IND_EV (DWORD)(URRC_EVENT_BASE + 37) /*UCSR->USIR*/
+#define URRC_ETWS_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 38)
+#define URRC_ETWS_CFG_END_EV (DWORD)(URRC_EVENT_BASE + 39)
+#define URRC_ETWS_CONTINUE_REQ_EV (DWORD)(URRC_EVENT_BASE + 40)
+#define URRC_DRX_CHANGE_IND_EV (DWORD)(URRC_EVENT_BASE + 41) /*URBC->UMCR*/
+#define URRC_EFACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 42)/*UCMR->URBC*/
+#define URRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(URRC_EVENT_BASE + 43)
+#define URRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(URRC_EVENT_BASE + 44)
+#define URRC_OUT_OF_SYNC_EV (DWORD)(URRC_EVENT_BASE + 45)
+#define URRC_RESUME_IN_SYNC_EV (DWORD)(URRC_EVENT_BASE + 46)
+#define URRC_LBS_MEAS_IND (DWORD)(URRC_EVENT_BASE + 47)
+/* ========================================================================
+ URLC - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CURLC_CONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 0)
+#define CURLC_RELEASE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 1)
+#define CURLC_LOOP_TEST_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 2)
+#define CURLC_SUSPEND_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 3)
+#define CURLC_RESUME_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 4)
+#define CURLC_CONTINUE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 5)
+#define UURLC_DATA_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 6)
+#define CURLC_CBS_RBCONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 7)
+#define CURLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(URLC_URRC_EVENT_BASE + 8)
+
+#define CURLC_SUSPEND_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 0)
+#define CURLC_LOOP_TEST_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 1)
+#define UURLC_DATA_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 2)
+#define CURLC_STATUS_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 3)
+#define UURLC_DATA_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 4)
+#define CURLC_CONFIG_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 5)
+#define CURLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(URLC_URRC_RSP_EVENT + 6)
+
+/* ========================================================================
+ UMAC - URRC/UMAC - UMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 0)
+#define CUMAC_RACH_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 1)
+#define CUMAC_RNTI_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 2)
+#define CUMAC_HS_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 3)
+#define CUMAC_HS_RESET_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 4)
+#define CUMAC_TFC_CTRL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 5)
+#define CUMAC_CONFIG_ABORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 6)
+#define CUMAC_ASC_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 7)
+#define CUMAC_DEL_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 8)
+#define CUMAC_TV_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 9)
+#define CUMAC_Q_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 10)
+#define CUMAC_UE_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 11)
+#define CUMAC_TV_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 12)
+#define CUMAC_Q_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 13)
+#define CUMAC_UE_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 14)
+#define CUMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 15)
+#define CUMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 16)
+#define CUMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 17)
+#define CUMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 18)
+#define CUMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 19)
+#define CUMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 20)
+#define CUMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 21)
+#define CUMAC_CRC_RESULT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 22)
+#define CUMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 23)
+#define CUMAC_CONTINUE_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 24)
+#define CUMAC_IDLE_PERIOD_EV (DWORD)(UMAC_URRC_EVENT_BASE + 25)
+#define CUMAC_CELL_RESEL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 26)
+#define CUMAC_HSPA_EPCH_CFG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 27)
+#define CUMAC_UPDATE_ERNTI_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 28)
+
+#define CUMAC_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 0)
+#define UUMAC_PCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 1)
+#define UUMAC_BCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 2)
+#define CUMAC_CONFIG_CHG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 3)
+#define CUMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 4)
+#define CUMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 5)
+#define CUMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 6)
+#define CUMAC_TV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 7)
+#define CUMAC_Q_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 8)
+#define CUMAC_UE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 9)
+#define CUMAC_ERUCCH_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 10)
+#define CUMAC_FACH_CFG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 11)
+#define CUMAC_CELL_RESEL_CNF_EV (DWORD)(UMAC_URRC_RSP_EVENT + 12)
+/* ========================================================================
+ UMAC - UL/DL - UMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(UMAC_UMAC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1T - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_GSM_MEAS_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 0)
+#define L1T_GSM_BSIC_VERIFY_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 1)
+#define L1T_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 3)
+#define L1T_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 4)
+#define L1T_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 5)
+#define L1T_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 6)
+#define L1T_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 7)
+#define L1T_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 8)
+#define L1T_TD_GET_RF_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 9)
+#define L1T_PLMN_END_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 10)
+#define L1T_IRAT_RSRC_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 11)
+
+#define L1T_GSM_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 0)
+#define L1T_TD_GET_RF_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 1)
+#define L1T_IRAT_RSRC_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 2)
+#define L1T_LTE_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDCP - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 1)
+#define CPDCP_RELOC_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 2)
+#define CPDCP_RELOC_COMP_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 3)
+#define CPDCP_RELOC_FAIL_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 4)
+#define CPDCP_DL_PDU_SIZE_CHG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 5)
+#define CPDCP_ROHC_TARGET_MODE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 6)
+#define CPDCP_SCRI_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 7)
+#define CPDCP_FD_MONITOR_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 8)
+#define CPDCP_FD_NO_DATA_CNF_EV (DWORD)(PDCP_URRC_EVENT_BASE + 9)
+
+
+#define CPDCP_RELOC_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 0)
+#define CPDCP_CONFIG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 1)
+#define CPDCP_RELOC_REJ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 2)
+#define CPDCP_DL_PDU_SIZE_CHG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 3)
+#define CPDCP_DATA_TRANSFER_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 4)
+#define CPDCP_FD_NO_DATA_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 5)
+
+
+/* ========================================================================
+ URLC - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UUMAC_DATA_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 0)
+#define CUMAC_HS_RESET_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 2)
+#define UURLC_DL_CTRL_PDU_REQ_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 3)
+#define UURLC_MAKE_AMDPDU_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ISR_FRAME_IND_EV (DWORD)(UMAC_L1T_EVENT_BASE + 0)
+
+/* ========================================================================
+ SM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_PDCP_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 0)
+#define SM_PDCP_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 1)
+#define SM_PDCP_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 2)
+#define SM_PDCP_ACT_ALREADY_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 3)
+#define SM_PDCP_RAT_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 4)
+#define SM_PDCP_RAT_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 5)
+#define SM_PDCP_RAT_SEQ_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 6)
+#define SM_PDCP_HC_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 7)
+#define SM_PDCP_RAT_CHG_COMP_EV (DWORD)(SM_PDCP_EVENT_BASE + 8)
+#define SM_PDCP_MODIFY_CNF_EV (DWORD)(SM_PDCP_EVENT_BASE + 9)
+
+#define SM_PDCP_STATUS_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 0)
+#define SM_PDCP_RAT_ACT_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 1)
+#define SM_PDCP_RAT_SEQ_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 2)
+#define SM_PDCP_MODIFY_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDI - GSMA ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDI_GSM_DATA_REQ_EV (DWORD)(PDI_GSMA_EVENT_BASE + 0)
+
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UPDI_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 0)
+#define UPDI_DATA_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 1)
+#define CPDI_NOT_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 2)
+#define CPDI_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 3)
+#define PDI_EPDCP_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 4)
+
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UURLC_PDCP_DATA_REQ_EV (DWORD)(PDCP_URLC_EVENT_BASE + 0)
+#define UURLC_PDCP_DATA_IND_EV (DWORD)(PDCP_URLC_EVENT_BASE + 1)
+/* ========================================================================
+ PDCP - RLC ÏûÏ¢ºÅ¶¨Òå(²Î¿¼RLC - RRC)
+======================================================================== */
+
+
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_BCH_READ_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 1)
+#define P_BCH_OPEN_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 2)
+#define P_BCH_RELEASE_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 3)
+
+#define P_SFN_DECODE_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 1)
+#define P_BCH_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 2)
+#define P_BCH_OPEN_REJ_EV (DWORD)(USIR_UPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ UCSR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_FREQUENCY_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 1)
+#define P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 2)
+#define P_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 3)
+#define P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 4)
+#define P_CAMPON_A_CELL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 5)
+#define P_TD_REL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 6)
+#define P_TD_RESET_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 7)
+#define P_TD_SLEEP_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 8)
+#define P_TD_SET_IRAT_MODE_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 9)
+
+#define P_FREQUENCY_SCAN_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 1)
+#define P_CELL_SEARCH_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 2)
+#define P_TD_RESET_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 3)
+#define P_TD_REL_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMCR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 1)
+#define P_INTER_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 2)
+#define P_MEAS_REL_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 5)
+#define P_FMO_INFO_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 6)
+
+#define P_INTRA_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 1)
+#define P_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 2)
+#define P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 3)
+#define P_DETECT_CELL_INFO_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 4)
+#define P_SERVCELL_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 7)
+/* ========================================================================
+ URBC - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 1)
+#define P_DL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 2)
+#define P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 3)
+#define P_UL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 4)
+#define P_DL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 5)
+#define P_UL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 6)
+#define P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 7)
+#define P_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 8)
+#define P_STOP_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 9)
+#define P_ADD_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 10)
+#define P_REL_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 11)
+#define P_REL_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 12)
+#define P_ADD_MODIFY_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 13)
+#define P_STOP_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 14)
+#define P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(URBC_UPHY_EVENT_BASE + 15)
+#define P_ADD_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 16)
+#define P_REL_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 17)
+#define P_PLCCH_ADD_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 18)
+#define P_HSPA_PLUS_FACH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 19)
+#define P_HSPA_PLUS_PCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 20)
+#define P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 21)
+#define P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 22)
+#define P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 23)
+#define P_UL_PHY_CH_CTRL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 24)
+
+#define P_DL_RL_SETUP_MODIFY_CNF_EV (DWORD)(URBC_UPHY_RSP_EVENT + 1)
+#define P_IN_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 2)
+#define P_OUT_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 3)
+#define P_UL_ESTABLISH_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMAC_UL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_RACH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 0)
+#define P_DL_DATA_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 1)
+#define P_TFC_POWER_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 2)
+#define P_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 3)
+#define P_UL_DATA_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 4)
+#define P_ABORT_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 5)
+#define P_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 6)
+#define P_ERUCCH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 7)
+#define P_ABORT_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 8)
+#define P_SET_AGCH_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 9)
+#define P_CELL_RESEL_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 10)
+#define P_CELL_RESEL_CNF_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 11)
+#define P_SYNC_CMD_RESP_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 12)
+/* ========================================================================
+ UMAC_DL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_QUALITY_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 0)
+#define P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 1)
+#define P_QUALITY_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 2)
+#define P_UE_INTERNAL_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1T - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G_L1T_GSM_INACT_TIME_IND_EV*/
+#define P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G_L1T_ABORT_GSM_GAP_REQ_EV*/
+#define P_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 3)
+#define P_CARD2_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 4) /*T_zTD_P_card2_gap_req*/
+#define P_CARD2_GAP_REL_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 5) /*T_zTD_P_card2_gap_rel_req*/
+#define P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 6) /*T_zTD_P_card2_stop_gap_req*/
+#define P_CARD1_SUSPEND_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 7) /*T_zTD_P_card1_suspend_req*/
+#define P_CARD1_RESUME_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 8) /*T_zTD_P_card1_resume_req*/
+#define P_TD_ZTPCG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 9)
+
+#define P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 1)
+#define P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 2)
+#define P_BCH_RELEASE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 3)
+#define P_CAMPON_A_CELL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 4)
+#define P_DPCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 5)
+#define P_REL_SCCPCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 6)
+#define P_STOP_PAGING_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 7)
+#define P_STOP_CBS_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 8)
+#define P_REL_HSDPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 9)
+#define P_REL_HSUPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 10)
+#define P_RACH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 11)
+#define P_ERUCCH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 12)
+#define P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 13)
+#define P_UMTS_TIMER_SNAPSHOT_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 14)
+#define P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 15)
+#define P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 16)
+#define P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 17)
+#define P_CARD2_GAP_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 18) /*T_zTD_P_card2_gap_ind*/
+#define P_CARD2_GAP_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 19) /*T_zTD_P_card2_gap_rel_cnf*/
+#define P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 20) /*T_zTD_P_card2_stop_gap_cnf*/
+#define P_CARD1_SUSPEND_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 21) /*T_zTD_P_card1_suspend_cnf*/
+#define P_TD_ZTPCG_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 22)
+
+/* ========================================================================
+ L1T ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_CHECK_RF_IND_EV (DWORD)(L1T_EVENT_BASE + 1)
+#define P_ACTIVE_IND_EV (DWORD)(L1T_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_DONE_REQ_EV (DWORD)(L1T_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1E/L1Gµ÷L1T º¯ÊýÉèÖÃÖ÷¸¨Ä£Ê½µÄº¯ÊýÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_FUNC_SET_MODE_REQ_EV (DWORD)(L1T_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T/L1E/L1WÖ®¼äÏûÏ¢ºÅ¶¨Òå(ÎïÀí²ãÊÊÅä²ãL1A)
+======================================================================== */
+#define L1_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 0)
+#define L1_GET_RF_CNF_EV (DWORD)(L1A_EVENT_BASE + 1)
+#define UTRAN_IRAT_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 2)
+#define UTRAN_BLIND_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 3)
+/*WCDMA*/
+#define L1A_FUNC_SET_MODE_REQ_EV (DWORD)(L1A_EVENT_BASE + 4)
+#define L1A_TD_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 5)/*TDÏòÖ÷ÖÆʽҪÉäƵÇëÇóÏûÏ¢*/
+#define L1A_GET_RF_FROM_TD_CNF_EV (DWORD)(L1A_EVENT_BASE + 6)/*TDÈóöÉäƵºó¸øÆäËûÖÆʽµÄ»Ø¸´ÏûÏ¢*/
+#define L1A_W_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 7)
+#define L1A_GET_RF_FROM_W_CNF_EV (DWORD)(L1A_EVENT_BASE + 8)
+#define L1A_LTE_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 9)
+#define L1A_GET_RF_FROM_LTE_CNF_EV (DWORD)(L1A_EVENT_BASE + 10)
+/*w¸¨Ä£Ï²âÁ¿Éϱ¨¹²ÓÃW_P_INTER_FREQ_MEAS_IND_EV*/
+/*** ÔSIG_CODE.HÖÐÒÆÖ²¹ýÀ´µÄÏûÏ¢ ***/
+ /* START OF DLL */
+#define L2_CONNECT_IND (DWORD)(LAPDM_EVENT_BASE + 0)
+#define L2_DATA_IND (DWORD)(LAPDM_EVENT_BASE + 1)
+#define DL_UNIT_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 2)
+#define DL_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 3)
+#define DL_ESTABLISH_REQ (DWORD)(LAPDM_EVENT_BASE + 4)
+#define DL_IRAT_HO_REQ (DWORD)(LAPDM_EVENT_BASE + 5)
+#define DL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 6)
+#define DL_RECONNECT_REQ (DWORD)(LAPDM_EVENT_BASE + 7)
+#define DL_RESUME_REQ (DWORD)(LAPDM_EVENT_BASE + 8)
+#define DL_SUSPEND_REQ (DWORD)(LAPDM_EVENT_BASE + 9)
+#define MDL_CONFIG (DWORD)(LAPDM_EVENT_BASE + 10)
+#define MDL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 11)
+#define PH_START_T200 (DWORD)(LAPDM_EVENT_BASE + 12)
+#define T200 (DWORD)(LAPDM_EVENT_BASE + 13)
+ /* END OF DLL */
+
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äBEGIN**************************/
+#define T_SI2N_AVAIL (DWORD)(GRR_EVENT_BASE + 83)
+#define T3206 (DWORD)(GRR_EVENT_BASE + 84)
+#define T3208 (DWORD)(GRR_EVENT_BASE + 85)
+#define T3210 (DWORD)(GRR_EVENT_BASE + 86)
+#define T_NCELL_VALID_TIMER (DWORD)(GRR_EVENT_BASE + 87)
+#define T_P_SI_STATUS_TIMER (DWORD)(GRR_EVENT_BASE + 88)
+#define T_CELL_SUPERVISION (DWORD)(GRR_EVENT_BASE + 89)
+#define T_PENALTY_0 (DWORD)(GRR_EVENT_BASE + 90)
+#define T_PENALTY_1 (DWORD)(GRR_EVENT_BASE + 91)
+#define T_PENALTY_2 (DWORD)(GRR_EVENT_BASE + 92)
+#define T_PENALTY_3 (DWORD)(GRR_EVENT_BASE + 93)
+#define T_PENALTY_4 (DWORD)(GRR_EVENT_BASE + 94)
+#define T_PENALTY_5 (DWORD)(GRR_EVENT_BASE + 95)
+#define T_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 96)
+#define T_RESELECTION_DELAY (DWORD)(GRR_EVENT_BASE + 97)
+#define T_SCELL_RESEL_DELAY (DWORD)(GRR_EVENT_BASE + 98)
+#define T_SYS_INFO_READ (DWORD)(GRR_EVENT_BASE + 99)
+#define T_PSI_CYCLE (DWORD)(GRR_EVENT_BASE + 100)
+#define T_NCELL_SI_READ (DWORD)(GRR_EVENT_BASE + 101)
+#define T_CALL_REEST_TIMEOUT (DWORD)(GRR_EVENT_BASE + 102)
+#define T3122 (DWORD)(GRR_EVENT_BASE + 103)
+#define T3142 (DWORD)(GRR_EVENT_BASE + 104)
+#define T3172 (DWORD)(GRR_EVENT_BASE + 105)
+#define T3200 (DWORD)(GRR_EVENT_BASE + 106)
+#define T_SYS_INFO_VALID (DWORD)(GRR_EVENT_BASE + 107)
+#define T_RXLEV_VALID (DWORD)(GRR_EVENT_BASE + 108)
+#define T_BETTER_C2 (DWORD)(GRR_EVENT_BASE + 109)
+#define T_SYNC_READ (DWORD)(GRR_EVENT_BASE + 110)
+#define T_NON_DRX (DWORD)(GRR_EVENT_BASE + 111)
+#define T_MONITOR_OLD_SCELL (DWORD)(GRR_EVENT_BASE + 112)
+#define T_TWO_IA_SUPERVISION (DWORD)(GRR_EVENT_BASE + 113)
+#define T_SENT_MEAS_REPORT (DWORD)(GRR_EVENT_BASE + 114)
+#define T_PSI_UNSOLICITED (DWORD)(GRR_EVENT_BASE + 115)
+#define T_ABN_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 116)
+#define T_ABN_CELL_RESEL_SCELL (DWORD)(GRR_EVENT_BASE + 117)
+#define T_TESTPARAM (DWORD)(GRR_EVENT_BASE + 118)
+#define T_CELL_BARRED_TIMER (DWORD)(GRR_EVENT_BASE + 119)
+#define T_CELL_SEL_IND (DWORD)(GRR_EVENT_BASE + 120)
+#define T3218 (DWORD)(GRR_EVENT_BASE + 121)
+#define T309 (DWORD)(GRR_EVENT_BASE + 122)
+#define T_BETTER_UTRAN (DWORD)(GRR_EVENT_BASE + 123)
+#define T_IR_WAIT_TIMER (DWORD)(GRR_EVENT_BASE + 124)
+#define T_IR_CELL_INVALID_TIMER (DWORD)(GRR_EVENT_BASE + 125)
+#define T3232_EV (DWORD)(GRR_EVENT_BASE + 126)
+#define T_RESELECTION_EV (DWORD)(GRR_EVENT_BASE + 127)
+#define T3230_EV (DWORD)(GRR_EVENT_BASE + 128)
+#define T_DISABLE_UMTS_MEAS_EV (DWORD)(GRR_EVENT_BASE + 129)
+#define T_DISABLE_LTE_MEAS_EV (DWORD)(GRR_EVENT_BASE + 130)
+
+#define T_IR_READ_PREDEF_CONF_TIMER (DWORD)(GRR_EVENT_BASE + 139)//¸ø¶¨Ê±Æ÷ÏûÏ¢ºÅÔ¤Áô10¸ö
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äEND*****************************/
+ /* END OF GRR */
+
+ /* START OF MAC */
+#define MAC_PDCH_REL_REQ (DWORD)(GMAC_EVENT_BASE + 0)
+#define MAC_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 1)
+#define RLC_MAC_TLLI_ASSIGN_REQ (DWORD)(GMAC_EVENT_BASE + 2)
+#define RLC_MAC_UPLINK_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 3)
+#define RLC_MAC_REL_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 4)
+#define RLC_MAC_DEACT_CNF (DWORD)(GMAC_EVENT_BASE + 5)
+#define RLC_MAC_CTRL_BLOCK_REQ (DWORD)(GMAC_EVENT_BASE + 6)
+#define GRR_MAC_CLASSMARK_IND (DWORD)(GMAC_EVENT_BASE + 7)
+#define GRR_MAC_UPDATE_PARAM_REQ (DWORD)(GMAC_EVENT_BASE + 8)
+#define GRR_MAC_FREQ_UPDATE_REQ (DWORD)(GMAC_EVENT_BASE + 9)
+#define GRR_MAC_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 10)
+#define GRR_MAC_POLLING_REQ (DWORD)(GMAC_EVENT_BASE + 11)
+#define GRR_MAC_CIRCUIT_REQ (DWORD)(GMAC_EVENT_BASE + 12)
+#define GRR_MAC_CIRCUIT_ABORT_REQ (DWORD)(GMAC_EVENT_BASE + 13)
+#define GRR_MAC_DEACT_REQ (DWORD)(GMAC_EVENT_BASE + 14)
+#define GRR_MAC_IDLE_CHN_CNF (DWORD)(GMAC_EVENT_BASE + 15)
+#define GRR_MAC_CELL_CHANGE_IND (DWORD)(GMAC_EVENT_BASE + 16)
+#define GRR_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 17)
+#define GRR_MAC_STOP_TIMER (DWORD)(GMAC_EVENT_BASE + 18)
+#define GRR_MAC_TESTPARAM_REQ (DWORD)(GMAC_EVENT_BASE + 19)
+#define GRR_MAC_SUSPEND_REQ (DWORD)(GMAC_EVENT_BASE + 20)
+#define T3126 (DWORD)(GMAC_EVENT_BASE + 21)
+#define T3146 (DWORD)(GMAC_EVENT_BASE + 22)
+#define T3162 (DWORD)(GMAC_EVENT_BASE + 23)
+#define T3164 (DWORD)(GMAC_EVENT_BASE + 24)
+#define T3166 (DWORD)(GMAC_EVENT_BASE + 25)
+#define T3168_MAC (DWORD)(GMAC_EVENT_BASE + 26)
+#define T3170 (DWORD)(GMAC_EVENT_BASE + 27)
+#define T3174 (DWORD)(GMAC_EVENT_BASE + 28)
+#define T3176 (DWORD)(GMAC_EVENT_BASE + 29)
+#define T3180 (DWORD)(GMAC_EVENT_BASE + 30)
+#define T3184 (DWORD)(GMAC_EVENT_BASE + 31)
+#define T3186 (DWORD)(GMAC_EVENT_BASE + 32)
+#define T3190 (DWORD)(GMAC_EVENT_BASE + 33)
+#define T3192 (DWORD)(GMAC_EVENT_BASE + 34)
+#define T_SINGLE_DL_BLOCK (DWORD)(GMAC_EVENT_BASE + 35)
+#define XPOLLING_RESPONSE (DWORD)(GMAC_EVENT_BASE + 36)
+#define XBLOCK_DL_RELEASE (DWORD)(GMAC_EVENT_BASE + 37)
+#define XBLOCK_UL_RELEASE (DWORD)(GMAC_EVENT_BASE + 38)
+#define GRR_MAC_T3218_EXP_EV (DWORD)(GMAC_EVENT_BASE + 39)
+#define GRR_MAC_PSHO_REQ_EV (DWORD)(GMAC_EVENT_BASE + 40)
+#define GRR_MAC_PSHO_RETURN_REQ_EV (DWORD)(GMAC_EVENT_BASE + 41)
+#define GRR_MAC_PSHO_DEACT_REQ_EV (DWORD)(GMAC_EVENT_BASE + 42)
+#define GMAC_T3216_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 43)
+#define GMAC_T_MULTI_DL_BLOCK_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 44)
+#define GMAC_T3200_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 45)
+
+ /* END OF MAC */
+
+ /* START OF RLC */
+#define RLC_WAKE_UP (DWORD)(GRLC_EVENT_BASE + 0)
+#define RLC_FILL_DATA_QUEUE (DWORD)(GRLC_EVENT_BASE + 1)
+#define RLC_START_TIMER_T3182 (DWORD)(GRLC_EVENT_BASE + 2)
+#define RLC_START_TIMER_T3168 (DWORD)(GRLC_EVENT_BASE + 3)
+#define RLC_FILL_GPRS_TEST_MODE (DWORD)(GRLC_EVENT_BASE + 4)
+#define RLC_UNEXPECTED_INPUT_RECEIVED (DWORD)(GRLC_EVENT_BASE + 5)
+#define RLC_UPL_DEBUG (DWORD)(GRLC_EVENT_BASE + 6)
+#define OM_RLC_TEST_MODE_REQ (DWORD)(GRLC_EVENT_BASE + 7)
+#define GRR_RLC_SUSPEND_REQ (DWORD)(GRLC_EVENT_BASE + 8)
+#define GRR_RLC_RESUME_REQ (DWORD)(GRLC_EVENT_BASE + 9)
+#define GRR_RLC_UPDATE_PARAM_REQ (DWORD)(GRLC_EVENT_BASE + 10)
+#define GRR_RLC_ACCESS_CNF (DWORD)(GRLC_EVENT_BASE + 11)
+#define GRR_RLC_ACCESS_REJ (DWORD)(GRLC_EVENT_BASE + 12)
+#define GRR_RLC_REL_PDCH_REQ (DWORD)(GRLC_EVENT_BASE + 13)
+#define GRR_RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 14)
+#define GRR_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 15)
+#define GRR_RLC_TBF_FAILURE (DWORD)(GRLC_EVENT_BASE + 16)
+#define GRR_RLC_TESTPARAM_REQ (DWORD)(GRLC_EVENT_BASE + 17)
+#define RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 18)
+#define RLC_UNITDATA_REQ (DWORD)(GRLC_EVENT_BASE + 19)
+#define RLC_CLEAR_QUEUE_REQ (DWORD)(GRLC_EVENT_BASE + 20)
+#define LL_RLC_RESUME_MM_REQ (DWORD)(GRLC_EVENT_BASE + 21)
+#define LL_RLC_RESUME_ALL_REQ (DWORD)(GRLC_EVENT_BASE + 22)
+#define RLC_ASSIGN_REQ (DWORD)(GRLC_EVENT_BASE + 23)
+#define RLC_RESET_REQ (DWORD)(GRLC_EVENT_BASE + 24)
+#define MAC_RLC_UPLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 25)
+#define MAC_RLC_UPLINK_PDCH_FAIL (DWORD)(GRLC_EVENT_BASE + 26)
+#define MAC_RLC_REL_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 27)
+#define MAC_RLC_UPLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 28)
+#define MAC_RLC_UPLINK_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 29)
+#define MAC_RLC_DOWNLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 30)
+#define MAC_RLC_DATA_IND (DWORD)(GRLC_EVENT_BASE + 31)
+#define MAC_RLC_UPLINK_DATA_IND (DWORD)(GRLC_EVENT_BASE + 32)
+#define MAC_RLC_ERROR_IND (DWORD)(GRLC_EVENT_BASE + 33)
+#define MAC_RLC_DEACT_REQ (DWORD)(GRLC_EVENT_BASE + 34)
+#define MAC_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 35)
+#define MAC_RLC_TLLI_IND (DWORD)(GRLC_EVENT_BASE + 36)
+#define MAC_RLC_DOWNLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 37)
+#define UPL_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 38)
+#define PTBF_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 39)
+#define T3168 (DWORD)(GRLC_EVENT_BASE + 40)
+#define T3182 (DWORD)(GRLC_EVENT_BASE + 41)
+#define RLC_ENG_MODE_TIMER (DWORD)(GRLC_EVENT_BASE + 42)
+#define GRR_RLC_PSHO_REQ_EV (DWORD)(GRLC_EVENT_BASE + 43)
+#define GRR_RLC_PSHO_SUCC_EV (DWORD)(GRLC_EVENT_BASE + 44)
+#define GRR_RLC_PSHO_FAIL_EV (DWORD)(GRLC_EVENT_BASE + 45)
+
+ /* END OF RLC */
+
+ /* START OF SNP */
+#define SN_DL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 0)
+#define SN_UL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 1)
+#define SN_NPDU_DEL_REQ (DWORD)(SNDCP_EVENT_BASE + 2)
+#define SN_NPDU_AVAIL_REQ (DWORD)(SNDCP_EVENT_BASE + 3)
+#define SN_DATA_REQ (DWORD)(SNDCP_EVENT_BASE + 4)
+#define SN_UNITDATA_REQ (DWORD)(SNDCP_EVENT_BASE + 5)
+#define SN_IR_UL_SUSPEND_RSP (DWORD)(SNDCP_EVENT_BASE + 6)
+#define SN_XID_REQ (DWORD)(SNDCP_EVENT_BASE + 7)
+#define SNSM_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 8)
+#define SNSM_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 9)
+#define SNSM_ASSIGN_IND (DWORD)(SNDCP_EVENT_BASE + 10)
+#define SNSM_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 11)
+#define SNSM_MODIFY_IND (DWORD)(SNDCP_EVENT_BASE + 12)
+#define SNSM_IR_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 13)
+#define SNSM_IR_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 14)
+#define SNSM_IR_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 15)
+#define SNPDU_AVAIL_IND (DWORD)(SNDCP_EVENT_BASE + 16)
+#define SNPDU_DEL_CNF (DWORD)(SNDCP_EVENT_BASE + 17)
+#define SNPDU_DEL_IND (DWORD)(SNDCP_EVENT_BASE + 18)
+#define LL_ESTABLISH_CNF (DWORD)(SNDCP_EVENT_BASE + 19)
+#define LL_ESTABLISH_IND (DWORD)(SNDCP_EVENT_BASE + 20)
+#define LL_RELEASE_CNF (DWORD)(SNDCP_EVENT_BASE + 21)
+#define LL_RELEASE_IND (DWORD)(SNDCP_EVENT_BASE + 22)
+#define LL_STATUS_IND (DWORD)(SNDCP_EVENT_BASE + 23)
+#define LL_RESET_IND (DWORD)(SNDCP_EVENT_BASE + 24)
+#define LL_RESET_PSHO_IND (DWORD)(SNDCP_EVENT_BASE + 25)
+#define LL_DATA_CNF (DWORD)(SNDCP_EVENT_BASE + 26)
+#define LL_XID_CNF (DWORD)(SNDCP_EVENT_BASE + 27)
+#define LL_XID_IND (DWORD)(SNDCP_EVENT_BASE + 28)
+#define LL_DATA_IND (DWORD)(SNDCP_EVENT_BASE + 29)
+#define LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 30)
+#define TIME_REEST (DWORD)(SNDCP_EVENT_BASE + 31)
+#define TIME_LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 32)
+#define TIME_UACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 33)
+#define TIME_ACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 34)
+ /* END OF SNP */
+
+ /* START OF GSMA */
+#define LLSMS_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 0)
+#define SN_NPDU_DEL_IND (DWORD)(GSMA_EVENT_BASE + 1)
+#define SN_NPDU_AVAIL_IND (DWORD)(GSMA_EVENT_BASE + 2)
+#define SN_DATA_IND (DWORD)(GSMA_EVENT_BASE + 3)
+#define SN_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 4)
+#define SN_IR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 5)
+#define SN_IR_TO_UMTS_IND (DWORD)(GSMA_EVENT_BASE + 6)
+#define RR_TESTPARAM_IND (DWORD)(GSMA_EVENT_BASE + 7)
+#define RR_ABORT_IND (DWORD)(GSMA_EVENT_BASE + 8)
+#define RR_ACT_CNF (DWORD)(GSMA_EVENT_BASE + 9)
+#define RR_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 10)
+#define RR_ACT_FAIL (DWORD)(GSMA_EVENT_BASE + 11)
+#define RR_CELL_PARAMETER_IND (DWORD)(GSMA_EVENT_BASE + 12)
+#define RR_ACT_IND (DWORD)(GSMA_EVENT_BASE + 13)
+#define RR_DEACT_CNF (DWORD)(GSMA_EVENT_BASE + 14)
+#define RR_PLMN_CNF (DWORD)(GSMA_EVENT_BASE + 15)
+#define RR_PLMN_REJ (DWORD)(GSMA_EVENT_BASE + 16)
+#define RR_PLMN_IND (DWORD)(GSMA_EVENT_BASE + 17)
+#define RR_PLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 18)
+#define RR_REL_IND (DWORD)(GSMA_EVENT_BASE + 19)
+#define RR_TBF_EST_IND (DWORD)(GSMA_EVENT_BASE + 20)
+#define RR_TBF_REL_IND (DWORD)(GSMA_EVENT_BASE + 21)
+#define RR_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 22)
+#define RR_HPLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 23)
+#define RR_HPLMN_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 24)
+#define RR_EST_CNF (DWORD)(GSMA_EVENT_BASE + 25)
+#define RR_EST_IND (DWORD)(GSMA_EVENT_BASE + 26)
+#define RR_CELL_IND (DWORD)(GSMA_EVENT_BASE + 27)
+#define RR_DATA_IND (DWORD)(GSMA_EVENT_BASE + 28)
+#define RR_SYNC_IND (DWORD)(GSMA_EVENT_BASE + 29)
+#define GMMRR_PAGE_IND (DWORD)(GSMA_EVENT_BASE + 30)
+#define GMMRR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 31)
+#define GMMRR_CELL_UPDATE_IND (DWORD)(GSMA_EVENT_BASE + 32)
+#define RR_DATA_REJ (DWORD)(GSMA_EVENT_BASE + 33)
+#define RR_EST_REJ (DWORD)(GSMA_EVENT_BASE + 34)
+#define RR_HO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 35)
+#define RR_HO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 36)
+#define RR_HO_START_IND (DWORD)(GSMA_EVENT_BASE + 37)
+#define RR_IRAT_RESEL_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 38)
+#define RR_IRAT_RESEL_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 39)
+#define RR_IRAT_RESEL_START_IND (DWORD)(GSMA_EVENT_BASE + 40)
+#define RR_CCO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 41)
+#define RR_CCO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 42)
+#define RR_CCO_START_IND (DWORD)(GSMA_EVENT_BASE + 43)
+#define RR_RAT_CHN_IND (DWORD)(GSMA_EVENT_BASE + 44)
+#define RR_TEST_COUNT_CNF (DWORD)(GSMA_EVENT_BASE + 45)
+#define LLGMM_STATUS_IND (DWORD)(GSMA_EVENT_BASE + 46)
+#define LLGMM_TRIGGER_IND (DWORD)(GSMA_EVENT_BASE + 47)
+#define LLGMM_USER_DATA_PRESENT (DWORD)(GSMA_EVENT_BASE + 48)
+#define LLGMM_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 49)
+#define RR_START_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 50)
+#define RR_END_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 51)
+#define RR_ADD_CELL_RESEL_INFO_IND (DWORD)(GSMA_EVENT_BASE + 52)
+#define RLC_BLOCK_INFO_IND (DWORD)(GSMA_EVENT_BASE + 53)
+#define RRMN_MEAS_RESULTS_CNF (DWORD)(GSMA_EVENT_BASE + 54)
+#define MNRR_CIPHERING_IND (DWORD)(GSMA_EVENT_BASE + 55)
+#define SN_XID_CNF (DWORD)(GSMA_EVENT_BASE + 56)
+#define RR_RRL_DATA_IND (DWORD)(GSMA_EVENT_BASE + 57)
+#define RR_RRL_ABORT_EVENT_IND (DWORD)(GSMA_EVENT_BASE + 58)
+#define RR_RRL_CLASSMARK_IND (DWORD)(GSMA_EVENT_BASE + 59)
+#define SNSM_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 60)
+#define SNSM_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 61)
+#define SNSM_MODIFY_RSP (DWORD)(GSMA_EVENT_BASE + 62)
+#define SNSM_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 63)
+#define SNSM_STATUS_REQ (DWORD)(GSMA_EVENT_BASE + 64)
+#define SNSM_IR_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 65)
+#define SNSM_IR_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 66)
+#define SNSM_IR_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 67)
+#define URRC_RESEL_REQ (DWORD)(GSMA_EVENT_BASE + 68)
+#define URRC_SET_INACTIVE_REQ (DWORD)(GSMA_EVENT_BASE + 69)
+#define RR_SET_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 70)
+#define URRC_READ_PREDEF_CONF_REQ (DWORD)(GSMA_EVENT_BASE + 71)/*WCDMAÏÂʹÓÃ*/
+#define URRC_ABORT_READ_PREDEF_REQ (DWORD)(GSMA_EVENT_BASE + 72)/*WCDMAÏÂʹÓÃ*/
+#define URRC_L1_RSRC_REQ (DWORD)(GSMA_EVENT_BASE + 73)
+#define URRC_L1_RSRC_FREE_IND (DWORD)(GSMA_EVENT_BASE + 74)
+#define RR_L1_RSRC_CNF (DWORD)(GSMA_EVENT_BASE + 75)
+#define RR_L1_RSRC_REJ (DWORD)(GSMA_EVENT_BASE + 76)
+#define RR_CELL_SEARCH_CNF (DWORD)(GSMA_EVENT_BASE + 77)
+#define RR_CELL_SEARCH_REJ (DWORD)(GSMA_EVENT_BASE + 78)
+#define URRC_CELL_SEARCH_REQ (DWORD)(GSMA_EVENT_BASE + 79)
+#define URRC_HO_INFO_REQ (DWORD)(GSMA_EVENT_BASE + 80)
+#define URRC_HO_REQ (DWORD)(GSMA_EVENT_BASE + 81)
+#define URRC_VSD_INFO (DWORD)(GSMA_EVENT_BASE + 82)
+#define RR_HO_CNF (DWORD)(GSMA_EVENT_BASE + 83)
+#define RR_HO_REJ (DWORD)(GSMA_EVENT_BASE + 84)
+#define URRC_CELL_CHANGE_REQ (DWORD)(GSMA_EVENT_BASE + 85)
+#define RR_CELL_CHANGE_CNF (DWORD)(GSMA_EVENT_BASE + 86)
+#define RR_CELL_CHANGE_REJ (DWORD)(GSMA_EVENT_BASE + 87)
+#define RR_RESEL_CNF (DWORD)(GSMA_EVENT_BASE + 88)
+#define RR_RESEL_REJ (DWORD)(GSMA_EVENT_BASE + 89)
+
+#define ERRC_RESEL_REQ_EV (DWORD)(GSMA_EVENT_BASE + 90)
+#define ERRC_CELL_SEARCH_REQ_EV (DWORD)(GSMA_EVENT_BASE + 91)
+#define RR_IRAT_PSHO_START_IND_EV (DWORD)(GSMA_EVENT_BASE + 92)
+#define RR_IRAT_PSHO_COMPLETE_IND_EV (DWORD)(GSMA_EVENT_BASE + 93)
+#define RR_IRAT_PSHO_FAIL_IND_EV (DWORD)(GSMA_EVENT_BASE + 94)
+#define URRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 95)
+#define ERRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 96)
+#define RR_PSHO_CNF_EV (DWORD)(GSMA_EVENT_BASE + 97)
+#define RR_PSHO_REJ_EV (DWORD)(GSMA_EVENT_BASE + 98)
+#define ERRC_CELL_CHANGE_REQ_EV (DWORD)(GSMA_EVENT_BASE + 99)
+#define RR_ETWS_DATA_IND_EV (DWORD)(GSMA_EVENT_BASE + 100)
+#define LLGMM_PSHO_IND_EV (DWORD)(GSMA_EVENT_BASE + 101)
+#define RLC_SM_CURR_BEAR_IND_EV (DWORD)(GSMA_EVENT_BASE + 102)
+#define RR_SENDCMP_IND_EV (DWORD)(GSMA_EVENT_BASE + 103)
+#define RR_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 104)
+#define RR_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 105)
+#define RR_ABORT_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 106)
+#define RR_ABORT_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 107)
+#define RR_XCELLINFO_CNF (DWORD)(GSMA_EVENT_BASE + 108)
+#define RR_XCELLINFO_REJ (DWORD)(GSMA_EVENT_BASE + 109)
+#define RR_XCELLINFO_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 110)
+
+
+ /* START OF LLC */
+#define LLC_START_TIMER_T200 (DWORD)(GLLC_EVENT_BASE + 0)
+#define LLC_START_TIMER_T201 (DWORD)(GLLC_EVENT_BASE + 1)
+#define LLSMS_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 2)
+#define LLGMM_ASSIGN_REQ (DWORD)(GLLC_EVENT_BASE + 3)
+#define LLGMM_RESUME_REQ (DWORD)(GLLC_EVENT_BASE + 4)
+#define LLGMM_SUSPEND_REQ (DWORD)(GLLC_EVENT_BASE + 5)
+#define LLGMM_TRIGGER_REQ (DWORD)(GLLC_EVENT_BASE + 6)
+#define LLGMM_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 7)
+#define LLGMM_CELL_NOTIFICATION_REQ (DWORD)(GLLC_EVENT_BASE + 8)
+#define SNPDU_AVAIL_REQ (DWORD)(GLLC_EVENT_BASE + 9)
+#define SNPDU_DEL_REQ (DWORD)(GLLC_EVENT_BASE + 10)
+#define SNPDU_DEL_RSP (DWORD)(GLLC_EVENT_BASE + 11)
+#define LL_CONFIG_REQ (DWORD)(GLLC_EVENT_BASE + 12)
+#define LL_ESTABLISH_REQ (DWORD)(GLLC_EVENT_BASE + 13)
+#define LL_ESTABLISH_RSP (DWORD)(GLLC_EVENT_BASE + 14)
+#define LL_RELEASE_REQ (DWORD)(GLLC_EVENT_BASE + 15)
+#define LL_DATA_REQ (DWORD)(GLLC_EVENT_BASE + 16)
+#define LL_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 17)
+#define LL_XID_REQ (DWORD)(GLLC_EVENT_BASE + 18)
+#define LL_XID_RSP (DWORD)(GLLC_EVENT_BASE + 19)
+#define GRR_LLC_PSHO_SUCCESS_IND (DWORD)(GLLC_EVENT_BASE + 20)
+#define RRC_LLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 21)
+#define RLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND (DWORD)(GLLC_EVENT_BASE + 23)
+#define RLC_DATA_CNF (DWORD)(GLLC_EVENT_BASE + 24)
+#define RLC_UNITDATA_CNF (DWORD)(GLLC_EVENT_BASE + 25)
+#define RLC_CLEAR_QUEUE_CNF (DWORD)(GLLC_EVENT_BASE + 26)
+#define RLC_CLEAR_QUEUE_IND (DWORD)(GLLC_EVENT_BASE + 27)
+#define RLC_DATA_BUFF_IND (DWORD)(GLLC_EVENT_BASE + 28)
+#define LLC_T200 (DWORD)(GLLC_EVENT_BASE + 29)
+#define T201 (DWORD)(GLLC_EVENT_BASE + 30)
+#define LLC_T100_EV (DWORD)(GLLC_EVENT_BASE + 31)
+ /* END OF LLC */
+
+/* ========================================================================
+ MM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MM_T3210_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 0)
+#define MM_T3211_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 1)
+#define MM_T3212_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 2)
+#define MM_T3213_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 3)
+#define MM_T3214_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 4)
+#define MM_T3216_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 5)
+#define MM_T3218_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 6)
+#define MM_T3220_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 7)
+#define MM_T3221_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 8)
+#define MM_T3230_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 9)
+#define MM_T3240_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 10)
+#define MM_T3241_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 11)
+#define MM_T3225_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 12)
+#define MM_T3222_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 13)
+#define MM_T3231_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 14)
+#define MM_T3232_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 15)
+#define MM_TWRRR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 16)
+#define MM_TWPGR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 17)
+#define MM_TCCSRV_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 18)
+
+/* ========================================================================
+ GMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_T_READY_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 0)
+#define GMM_T3310_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 1)
+#define GMM_T3330_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 2)
+#define GMM_T3317_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 3)
+#define GMM_T3321_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 4)
+#define GMM_T3316_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 5)
+#define GMM_T3318_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 6)
+#define GMM_T3320_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 7)
+#define GMM_T_WRRC_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 8)
+#define GMM_T_WRRR_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 9)
+#define GMM_T_POWER_OFF_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 10)
+#define GMM_T_WSPN_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 11)
+#define GMM_T_WCRS_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 12)
+#define GMM_T_WTRG_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 13)
+#define GMM_T_PAGE_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 14)
+#define GMM_T3319_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 15)
+#define GMM_T_WREL_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 16)/*EC614000821119*/
+/* ========================================================================
+ UMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_T3212_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 0)
+#define UMM_T3311_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 1)
+#define UMM_T3302_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 2)
+#define UMM_T3312_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 3)
+#define UMM_T_NOCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 4)
+#define UMM_T_LIMIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 5)
+#define UMM_T_DELLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 6)
+#define UMM_T_SHHPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 7)
+#define UMM_T_UICCINIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 8) /* ¼àÊÓ¿¨³õʼ»¯¶¨Ê±Æ÷ */
+#define UMM_T_CAMPON_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 9) /* ¼àÊÓפÁô¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_DETACH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 10) /* ¼àÊӹػúÈ¥»î¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_LIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 11) /* ÖØÊÔPLMNÁÐ±í¶¨Ê±Æ÷ */
+#define UMM_T_PLMNLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 12) /* Áбí¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T3411_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 13)
+#define UMM_T3402_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 14)
+#define UMM_T3412_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 15)
+#define UMM_T3442_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 16)
+#define UMM_T_PROC_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 17)
+#define UMM_T_FOCSGLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 18)
+#define UMM_T3323_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 19)
+#define UMM_T3423_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 20)
+#define UMM_TBGSEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 21) /*LTE±³¾°ËÑË÷ÖÜÆÚ¶¨Ê±Æ÷*/
+#define UMM_T_IMSREG_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 22)
+#define UMM_T_NORMALFAILPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 23)
+#define UMM_T_ENABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 24)
+#define UMM_T_DISABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 25)
+#define UMM_T_LOOPTIME_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 26)
+#define UMM_T_DISFRESEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 27)
+#define UMM_T_RESETCAUSEPAR_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 28)
+#define UMM_T_SWITCHCARD_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 29)
+#define UMM_T_ARREARS_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 30)
+#define UMM_TSEARCHECALLCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 31)
+#define UMM_TECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 32)
+#define UMM_TTESTECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 33)
+#define UMM_T_IMSREL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 34)
+/* ========================================================================
+ CC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_T303_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 0)
+#define CC_T305_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 1)
+#define CC_T308_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 2)
+#define CC_T310_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 3)
+#define CC_T313_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 4)
+#define CC_T335_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 5) /*CCBS*/
+#define CC_T332_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 6)
+#define CC_T323_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 7)
+#define CC_T336_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 8)
+#define CC_T337_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 9)
+
+/* ADD A TIMER FOR CALL CONFIRM MESSAGE */
+#define CC_T_CALLCNF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 10)
+
+/* ADD TIMER FOR AOC */
+#define CC_T_ACMUPD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 11)
+#define CC_T_CDUR_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 12)
+
+#define CC_T_HOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 13)
+#define CC_T_RETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 14)
+
+#define CC_T_MPTYBUILD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 15)
+#define CC_T_MPTYHOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 16)
+#define CC_T_MPTYRETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 17)
+#define CC_T_MPTYSPLIT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 18)
+
+#define CC_T322_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 19)
+#define CC_T_SUPPER_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 20)
+#define CC_T_MMCONN_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 21)
+
+#define CC_T_RELTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 22)
+#define CC_T_CONNTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 23)
+#define CC_T_SYNCIND_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 24)
+#define CC_T_MODIFYBC_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 25)
+#define CC_T_DTMFDURA_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 26)
+#define CC_T_MMCONNRETRY_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 27)
+#define CC_T_ALLOWEDCALL_TIME_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 28)
+#define CC_T_ECT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 29)
+#define CC_T_T2_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 30)
+#define CC_T_T5_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 31)
+#define CC_T_T6_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 32)
+#define CC_T_T7_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 33)
+#define CC_T_TIDLE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 34)
+#define CC_T_T9_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 35)
+
+/* ========================================================================
+ SMS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SMS_TR1M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 0) /* FOR MO SM.*/
+#define SMS_TRAM_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 1) /* FOR MO SM.*/
+#define SMS_TC1M_MO_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 2) /* FOR MO SM.*/
+#define SMS_TMMS_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 3) /* FOR MO SM.*/
+#define SMS_TR2M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 4) /* FOR MT SM.*/
+#define SMS_TC1M_MT_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 5) /* FOR MT SM.*/
+/* ========================================================================
+ SS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SS_T_WAIT_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 0)
+#define SS_T_MOLRTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 1)
+#define SS_T_MOLRINTERTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 2)
+#ifdef _USE_SIG_TRACE
+#define SS_DL_L3FACILITY_EV (DWORD)(SS_TIMER_EVENT_BASE + 3)
+#define SS_DL_L3MTREG_EV (DWORD)(SS_TIMER_EVENT_BASE + 4)
+#define SS_DL_L3RELCOMP_EV (DWORD)(SS_TIMER_EVENT_BASE + 5)
+#endif
+
+
+/* ========================================================================
+ SM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_T3380_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 0)
+#define SM_T3381_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 1)
+#define SM_T3390_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 2)
+#define SM_T_CMEST_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 3)
+#define SM_T_PDPHANDLE_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 4)
+#define SM_T_APPANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 5)
+#define SM_T_AUTOANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS¶¨Ê±Æ÷ ÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_T_SCHEDCHECK_EXPIRY_EV (DWORD)(CBS_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ UICC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UICC_CARD_DETECT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 0)
+#define UICC_CARD_USAT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ URRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define USIR_T_BCH_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 0)
+#define USIR_T_SIB7_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 1)
+#define USIR_T_VTSIB_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 2)
+#define USIR_T_R_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 3)
+#define USIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 4)
+#define UCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 5)
+#define UCSR_T_HYSTX_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 6)
+#define UCSR_T_PROTECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 7)
+#define UCSR_T_NCELL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 8)
+#define UCSR_T_OOS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 9)
+#define UCSR_T_CAMP1S_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define UCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 11)
+#define UCSR_T_REDIRECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 12)
+#define UMCR_T_RESELECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 13)
+#define UMCR_T_PERIOD_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 14)
+#define UMCR_T_TRIGGER_EV (DWORD)(URRC_TIMER_EVENT_BASE + 15)
+#define UMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 16)
+#define UCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 17)
+#define UCER_T_ETWS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 18)
+#define UCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 19)
+#define URRC_T300_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 20)
+#define URRC_T302_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 21)
+#define URRC_T304_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 22)
+#define URRC_T305_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 23)
+#define URRC_T307_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 24)
+#define URRC_T308_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 25)
+#define URRC_T309_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 26)
+#define URRC_T312_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 27)
+#define URRC_T313_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 28)
+#define URRC_T314_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 29)
+#define URRC_T315_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 30)
+#define URRC_T316_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 31)
+#define URRC_T319_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 32)
+#define URRC_T320_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 33)
+#define UMCR_T322_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 34)
+#define URRC_T323_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 35)
+#define URRC_T325_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 36)
+#define URRC_T_WAIT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 37)
+#define UCSR_T_LBS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 38)
+
+/* ========================================================================
+ UPDCP¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDCP_T_RABREEST_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 0)
+#define PDCP_T_SNSYNC_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 1)
+#define PDCP_T_DATAMONITOR_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ URLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define URLC_T_DISCARD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 0)
+#define URLC_T_POLL_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 1)
+#define URLC_T_POLLPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 2)
+#define URLC_T_POLLPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 3)
+#define URLC_T_STATUSPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 4)
+#define URLC_T_STATUSPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 5)
+#define URLC_T_RESET_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 6)
+#define URLC_T_MRW_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ UMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define UMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 0)
+#define UMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 1)
+#define UMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 2)
+#define UMAC_T_RACHPROC_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 3)
+#define UMAC_T_HSTIMER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 4)
+#define UMAC_T_RESET_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 5)
+
+
+/* ========================================================================
+ L1T¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define L1T_T_BSIC_EXPIRY_EV (DWORD)(L1T_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ TAF¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define TAF_T_PROC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 0)
+#define TAF_T_DISC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 1)
+#define TAF_T_RA_TSYNC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 2)
+#define TAF_T_RA_TSYNCEND_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 3)
+#define TAF_T_RA_TSBFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 4)
+#define TAF_T_RA_TXFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 5)
+#define TAF_T_RLP_TRCVR_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 6)
+#define TAF_T_RLP_TRCVS_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 7)
+#define TAF_T_RLP_TTEST_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 8)
+#define TAF_T_RLP_TXID_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 9)
+#define TAF_T_RLP_T_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ GSMA¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ ROHCv1¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 0)
+#define ROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 1)
+#define ENROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 2)
+#define ENROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 3)
+#define ROHCv1_T_NACK_FDBK_CNT_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ ROHCv2¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 0)
+#define ENROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ PDI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDI_T_SWITCHLED_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 0)
+#define PDI_T_WAITDNSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 1)
+#define PDI_T_WAITZSSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 2)
+#define PDI_T_WAIT_BUF_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 3)
+#define PDI_LOOPB_TIMER_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 4)
+
+/* ========================================================================
+ SCI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define SCI_T_VOICE_FRAME_EXPIRY_EV (DWORD)(SCI_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ STM¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define STM_MEMAVAILD_EXPIRY_EV (DWORD)(STM_TIMER_EVENT_BASE + 0)
+
+/*========================================================================
+USAT¶¨Ê±Æ÷¶¨Òå
+========================================================================*/
+#define USAT_TIMERMNG_TIMER1_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 0)
+#define USAT_TIMERMNG_TIMER2_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 1)
+#define USAT_TIMERMNG_TIMER3_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 2)
+#define USAT_TIMERMNG_TIMER4_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 3)
+#define USAT_TIMERMNG_TIMER5_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 4)
+#define USAT_TIMERMNG_TIMER6_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 5)
+#define USAT_TIMERMNG_TIMER7_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 6)
+#define USAT_TIMERMNG_TIMER8_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ È«¾ÖÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define FOR_TEST_TEMP_EV (DWORD)(PRI_TEST_EVENT_BASE + 0)
+#define TEST_SET_UICC_RLT_EV (DWORD)(PRI_TEST_EVENT_BASE + 1)
+#define TEST_SET_UICC_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 2)
+#define TEST_SET_NV_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 3)
+#define TEST_SET_NV_DATA_IMEI_EV (DWORD)(PRI_TEST_EVENT_BASE + 4)
+#define TEST_SET_NV_DATA_SPCLFUNC_EV (DWORD)(PRI_TEST_EVENT_BASE + 5)
+#define TEST_SET_COMP_IND_EV (DWORD)(PRI_TEST_EVENT_BASE + 6)
+/* ========================================================================
+ Ä£ÄâTAFÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_TAFDATAIND_UTRAN_EV (DWORD)(TAF_TEST_EVENT_BASE + 0)
+
+/* ========================================================================
+ USIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_BIGSIB_IND_EV (DWORD)(USIR_TEST_EVENT_BASE + 0)
+#define TEST_USIR_DECSIB_EV (DWORD)(USIR_TEST_EVENT_BASE + 1)
+
+/* ========================================================================
+ NURLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UURLC_DATA_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 0)
+#define TEST_UURLC_DATA_IND_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 1)
+#define TEST_CURLC_CONFIG_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 2)
+#define TEST_URLC_ACK_CTRL_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NPDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 1)
+#define NPDCP_DATA_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 2)
+#define NPDCP_DATA_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 3)
+#define TEST_NPDCP_DATA_ERR_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 4)
+#define TEST_NPDCP_DATA_CNF_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 5)
+
+/* ========================================================================
+ NUMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UMAC_ACK_CTRL_UTRAN_EV (DWORD)(NUMAC_EVENT_BASE + 0)
+#define TEST_UMAC_HSUPA_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 1)
+#define TEST_UMAC_HSUPA_CFG_EV (DWORD)(NUMAC_EVENT_BASE + 2)
+#define TEST_UMAC_HSUPA_SIINFO_EV (DWORD)(NUMAC_EVENT_BASE + 3)
+#define TEST_UMAC_HSUPA_HEADER_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 4)
+#define TEST_UMAC_NOTIFY_DATA_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 5)
+#define TEST_UMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 6)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UCBS_SCHED_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 0)
+#define TEST_UCBS_DATA_REQ_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 1)
+#define TEST_UCBS_OUTPUT_END_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 2)
+#define TEST_UCBS_UMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 3)
+#define TEST_UCBS_UMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 4)
+#define TEST_UURLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 5)
+/*WCDMA NCBS_EVENT_BASE=20 */
+#define TEST_UWRLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 6)
+#define TEST_UCBS_WMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 7)
+#define TEST_UCBS_WMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 8)
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TC_ACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 0)
+#define TC_ACTIVE_TEST_CNF_EV (DWORD)(TC_EVENT_BASE + 1)
+#define TC_DEACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 2)
+#define TC_CLOSE_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 3)
+#define TC_CLOSE_LOOP_CNF_EV (DWORD)(TC_EVENT_BASE + 4)
+#define TC_CLOSE_LOOP_REQ_URLC_EV (DWORD)(TC_EVENT_BASE + 5)
+#define TC_OPEN_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 6)
+/*wcdma TC_EVENT_BASE=30*/
+#define TC_CLOSE_LOOP_REQ_WRLC_EV (DWORD)(TC_EVENT_BASE + 7)
+//lte TC_EVERNT
+#define EMM_TC_TEST_CONTROL_REQ_EV (DWORD)(TC_EVENT_BASE + 8)
+#define TC_EMM_TEST_CONTROL_CNF_EV (DWORD)(TC_EVENT_BASE + 9)
+#define TC_PDI_OPEN_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 10)
+#define TC_PDI_CLOSE_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 11)
+/* ========================================================================
+ L1SIMUÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1SIMU_START_EV (DWORD)(L1SIMU_EVENT_BASE + 0) /*Æô¶¯L1_SIMUÄ£¿é*/
+#define L1SIMU_NGMAC_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 1) /*L1_SIMU·¢ËÍÊý¾Ýµ½MAC_N*/
+#define L1SIMU_DLLN_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 2) /*L1_SIMU·¢ËÍÊý¾Ýµ½LAPDM*/
+#define TOOL_L1SIMU_CELL_MEAS_INFO_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 3) /*¹¤¾ß·¢ËÍFCBSBÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_SYSINFO_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 4) /*¹¤¾ß·¢ËÍϵͳÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_PAGING_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 5) /*¹¤¾ß·¢ËÍÑ°ºôÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_DCCH_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 6)
+#define TOOL_L1SIMU_DCCH_REL_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 7)
+#define L1SIMU_DLLN_CONNECT_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 8)
+#define L1SIMU_FRAME_INT_EV (DWORD)(L1SIMU_EVENT_BASE + 9)
+#define TOOL_L1SIMU_SYNC_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 10)
+#define TOOL_L1SIMU_SYSINFO_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 11)
+#define L1SIMU_DLLN_DATA_SENT_CMP_EV (DWORD)(L1SIMU_EVENT_BASE + 12) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define TOOL_L1SIMU_DCCH_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 13) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define TOOL_L1SIMU_SYSINFO_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 14)
+#define L1SIMU_TOOL_RXLEV_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 15)
+#define L1SIMU_TOOL_SYNCREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 16)
+#define L1SIMU_TOOL_SYSREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 17)
+#define L1SIMU_TOOL_IDLE_MODE_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 18)
+#define L1SIMU_TOOL_NCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 19) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define L1SIMU_TOOL_SCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 20) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define L1SIMU_TOOL_MEAS_REPORT_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 21)
+#define L1SIMU_TOOL_DL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 22)
+#define L1SIMU_TOOL_UL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 23)
+#define L1SIMU_TOOL_TAF_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 24)
+#define L1SIMU_TOOL_TAF_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 25)
+#define L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 26)
+#define L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 27)
+#define TOOL_L1SIMU_CBS_BLK_START_EV (DWORD)(L1SIMU_EVENT_BASE + 28)
+#define TOOL_L1SIMU_CBS_FST_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 29)
+#define TOOL_L1SIMU_CBS_OTHER_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 30)
+#define L1SIMU_TOOL_PSHOREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 31)
+#define L1SIMU_TOOL_DEACTIATE_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 32)
+#define TOOL_L1SIMU_ABNORMAL_TA_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 33)
+#define L1SIMU_TOOL_L1G_L1E_GSM_INACT_TIME_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 34)
+#define L1SIMU_TOOL_L1G_L1E_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 35)
+#define L1SIMU_TOOL_L1G_L1E_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 36)
+#define L1SIMU_TOOL_CHANNEL_ASSIGN_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 37)
+#define L1SIMU_TOOL_CHANNEL_TYPE_INFO_EV (DWORD)(L1SIMU_EVENT_BASE + 38)
+
+/* ========================================================================
+ NLAPDMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLAPDM_UNIT_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 0) /*¹¤¾ßÏòLADPN·¢ËÍ·ÇÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_UNIT_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 1) /*LADPNÏò¹¤¾ßÉÏ´«·ÇÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 2) /*¹¤¾ßÏòLADPN·¢ËÍÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 3) /*LADPNÏò¹¤¾ßÉÏ´«È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_ESTABLISH_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 4) /*¹¤¾ßÏòLADPN·¢Ëͽ¨Á´ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 5) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 6) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´È·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_SUSPEND_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 7) /*LADPNÏò¹¤¾ß·¢Ë͹ÒÆðÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_RECONNECT_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 8) /*¹¤¾ßÏòLADPN·¢ËÍÖØÁ¬ÇëÇóÏûÏ¢*/
+#define TOOL_NLAPDM_RELEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 9) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 10) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 11) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_MDL_CONFIG_EV (DWORD)(NLAPDM_EVENT_BASE + 12) /*¹¤¾ßÏòLADPN·¢ËͳõʼÅäÖÃÏûÏ¢*/
+#define NLAPDM_TOOL_MDL_ERROR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 13) /*LADPNÏò¹¤¾ß·¢ËÍ´íÎ󱨸æ*/
+#define TOOL_NLAPDM_MDL_REALEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 14) /*¹¤¾ß·¢ÆðÒì³£±¾µØÊÍ·ÅÏûÏ¢*/
+#define NLAPDM_L2_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 15) /*SAPI0·¢ËÍÏûÏ¢µ½SAPI3*/
+#define NLAPDM_TOOL_SABM_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 16) /*NLAPDMÏò¹¤¾ß·¢ËÍÆÕͨ½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 17) /*¹¤¾ßÏòNLAPDM·¢ËÍÆÕͨ½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define NLAPDM_TOOL_SABM_COR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 18) /*NLAPDMÏò¹¤¾ß·¢ËͳåÍ»½â¾ö½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_COR_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 19) /*¹¤¾ßÏòNLAPDM·¢ËͳåÍ»½â¾ö½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define TOOL_NLAPDM_EXCEPT_DATA_EV (DWORD)(NLAPDM_EVENT_BASE + 20) /*¹¤¾ßÏòNLAPDM·¢ËÍÒì³£Êý¾ÝÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_I_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 21) /*NLAPDMÏò¹¤¾ß·¢ËÍÈ·ÈÏÊý¾ÝÉϱ¨Ö¸Ê¾ÏûÏ¢*/
+
+
+/* ========================================================================
+ NGMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NGMAC_START_EV (DWORD)(NGMAC_EVENT_BASE + 0) /*NGMACÄ£¿éÆô¶¯*/
+#define NGMAC_NGRLC_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 1) /*NGMAC¸øNGRLC·¢ËÍPDANÏûÏ¢*/
+#define NGMAC_NGRLC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 2) /*NGMAC¸øNGRLC·¢ËÍUPLINKÊý¾Ý¿é*/
+#define NGRLC_NGMAC_PUAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 3) /*NGRLC¸øNGMAC·¢ËÍPUANµÄ²ÎÊý*/
+#define NGMAC_NGRLC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 4) /*NGMAC֪ͨNGRLCÊÍ·ÅUPLINK TBF*/
+#define NGRLC_NGMAC_FBI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 5) /*RLC·ÇÈ·ÈÏģʽ£¬NGRLC֪ͨNGMAC×îÖÕ¿éÒÑ·¢³ö£¬NGMACµÈ´ýPCA*/
+#define NGMAC_NGRLC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 6) /*RLC·ÇÈ·ÈÏģʽ£¬NGMAC֪ͨNGRLCÊÍ·ÅTBF*/
+#define NGRLC_NGMAC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 7) /*RLCÈ·ÈÏģʽ£¬NGRLC֪ͨNGMACÊÍ·ÅDOWNLINK TBF*/
+#define NGRLC_NGMAC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 8) /*NGRLC֪ͨNGMACÒì³£ÊÍ·ÅUPLINK TBF*/
+#define NGMAC_NGRLC_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 9) /*NGMAC֪ͨNGRLC DOWNLINK_TBFÒѾÍêÈ«µÃµ½È·ÈÏ*/
+#define TOOL_NGMAC_PUA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 10) /*TOOL¸øNGMAC·¢ËÍPUA*/
+#define NGMAC_TOOL_PRR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 11) /*NGMAC¸øTOOL·¢ËÍPRR£¬Çé¿ö°üÀ¨£ºIDLE̬½¨Á¢µÄUPLINK TBF¡¢ULONULµÄTBF¡¢ULONDLµÄTBF*/
+#define NGMAC_TOOL_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 12) /*NGMAC¸øTOOL·¢ËÍPDANÏûÏ¢£¬½öÔÚÐèÒª½¨Á¢ULONDL TBFʱ²Å·¢*/
+#define TOOL_NGMAC_PUAN_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 13) /*TOOL¸øNGMAC·¢ËÍPUAN£¬½öÔÚ±àÂ뷽ʽ¡¢´°¿Ú´óС¡¢RESEGMENTµÈ¸Ä±äʱ²Å·¢*/
+#define TOOL_NGMAC_PDA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 14) /*TOOL¸øNGMAC·¢ËÍPDA*/
+#define NGMAC_TOOL_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 15) /*NGMAC¸øTOOL·¢ËÍPCA£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR8_IND_EV (DWORD)(NGMAC_EVENT_BASE + 16) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR11_IND_EV (DWORD)(NGMAC_EVENT_BASE + 17) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_CR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 18) /*NGMAC¸øTOOL·¢ËÍCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 19) /*NGMAC֪ͨTOOLÊÍ·ÅDOWNLINK TBF*/
+#define NGMAC_TOOL_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 20) /*NGMAC֪ͨTOOLÊÍ·ÅUPLINK TBF*/
+#define NGMAC_TOOL_TLLI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 21) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬NGMAC¸øTOOLÇëÇóCONT_RES_TLLI*/
+#define TOOL_NGMAC_TLLI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 22) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬TOOL¸øNGMAC·¢ËÍCONT_RES_TLLI*/
+#define TOOL_NGMAC_IMM_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 23) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨*/
+#define TOOL_NGMAC_IMM_EX_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 24) /*TOOL¸øNGMAC·¢ËÍÀ©Õ¹Á¢¼´É趨*/
+#define TOOL_NGMAC_IMM_REJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 25) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨¾Ü¾ø*/
+#define L1_NGMAC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 26) /*L1_SIMU°Ñ´ÓL1G½ÓÊÕµ½µÄÉÏÐÐÊý¾Ý·¢Ë͵½MAC_N*/
+#define NGMAC_NGMAC_TMS_FBI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 27) /*FBI¶¨Ê±Æ÷³¬Ê±*/
+#define NGMAC_NGMAC_TMS_FAI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 28) /*FAI¶¨Ê±Æ÷³¬Ê±*/
+#define TOOL_NGMAC_PMO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 29) /*TOOL¸øNGMAC·¢ËÍPMO*/
+#define TOOL_NGMAC_PSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 30) /*TOOL¸øNGMAC·¢ËÍPSI*/
+#define NGMAC_TOOL_MSACC_IND_EV (DWORD)(NGMAC_EVENT_BASE + 31) /*NGMACÏòTOOLÇëÇóUPLINK TBF½¨Á¢»òÇëÇó½¨Á¢RRÁ¬½Ó*/
+#define TOOL_NGMAC_ULTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 32) /*TOOLÅäÖÃNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 33) /*TOOLÅäÖÃNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_ULTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 34) /*TOOLÊÍ·ÅNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 35) /*TOOLÊÍ·ÅNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PKTTSRECFG_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 36) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TIMESLOT_RECONFIGUREµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTTBFREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 37) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TBF_RELEASEµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTPDCHREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 38) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_PDCH_RELEASEÏûÏ¢*/
+#define TOOL_NGMAC_PKTCCC_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 39) /*TOOLÒªÇóNGMAC·¢ËÍPACKET CELL CHANGE CONTINUE*/
+#define TOOL_NGMAC_PKTCCO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 40) /*TOOLÇëÇóNGMAC·¢ËÍPACKET CELL CHANGE ORDER*/
+#define TOOL_NGMAC_PKTNCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 41) /*TOOLÇëÇóNGMAC·¢ËÍPACKET NEIGHBOUR CELL DATA*/
+#define TOOL_NGMAC_PKTPOLL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 42) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POLLING REQUEST*/
+#define TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 43) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POWER CTRL/TA*/
+#define TOOL_NGMAC_PKTPRACHPARA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 44) /*TOOLÇëÇóNGMAC·¢ËÍPACKET PRACH PARAMETERS*/
+#define TOOL_NGMAC_PKTSCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 45) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVE CELL DATA*/
+#define TOOL_NGMAC_PKTQUENOTI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 46) /*TOOLÇëÇóNGMAC·¢ËÍPACKET QUEUING NOTIFICATION*/
+#define TOOL_NGMAC_PKTACCREJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 47) /*TOOLÇëÇóNGMAC·¢ËÍ·Ö×é½ÓÈë¾Ü¾ø*/
+#define NGMAC_TOOL_PKTMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 48) /*NGMAC½ÓÊÕµ½MS PACKET MEAS REPORT ºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTMOBTBFSTA_EV (DWORD)(NGMAC_EVENT_BASE + 49) /*NGMAC½ÓÊÕµ½MS PACKET MOBILE TBF STATUSºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTPSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 50) /*NGMAC½ÓÊÕµ½MS PACKET PSI STATUSºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTPAUSE_EV (DWORD)(NGMAC_EVENT_BASE + 51) /*NGMAC½ÓÊÕµ½MS PACKET PAUSEºó·¢ËÍÏûÏ¢µ½TOOL*/
+#define NGMAC_TOOL_PKTEMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 52) /*NGMAC½ÓÊÕµ½MS PACKET ENHANCED MEAS REPORTºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTADDMSRAC_EV (DWORD)(NGMAC_EVENT_BASE + 53) /*NGMAC½ÓÊÕµ½MS PACKET ADDITION MS RACºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTCCN_EV (DWORD)(NGMAC_EVENT_BASE + 54) /*NGMAC½ÓÊÕµ½MS PACKET CELL CHANGE NOTIFICATIONºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 55) /*NGMAC½ÓÊÕµ½MS PACKET SI STATUSºó·¢Ë͵½¹¤¾ß*/
+#define GMAC_GET_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 56) /*GMAC·¢ËÍÉÏÐÐÊý¾Ýʱµ÷Óú¯ÊýMAC_GET_BLOCKS,ΪÔö¼ÓTRACEÌí¼ÓµÄʼþºÅ*/
+#define GMAC_ACK_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 57) /*L1Gµ÷ÓÃMAC_ACK_BLOCKSʱΪÔö¼ÓÐÅÁî¸ú×Ù¶øÔö¼ÓµÄʼþºÅ*/
+#define TOOL_NGMAC_PKTPGREQ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 58)
+#define TOOL_NGMAC_CTRLBLOCK_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 59)
+#define NGMAC_TOOL_CCF_IND_EV (DWORD)(NGMAC_EVENT_BASE + 60) /*NGMACÏòTOOL·¢Ë͵ÄPACKET CELL CHANGE FAILUREÏûÏ¢*/
+#define NGMAC_NGRLC_EPDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 61) /*NGMAC¸øNGRLC·¢ËÍEPDANÏûÏ¢*/
+#define TOOL_NGMAC_PSHOCMD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 62) /*TOOLÇëÇóNGMAC·¢ËÍPs Handover Command*/
+#define TOOL_NGMAC_PPI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 63) /*TOOLÇëÇóNGMAC·¢ËÍPacket Physical Information*/
+#define TOOL_NGMAC_PSHO_ULTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 64) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_DLTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 65) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_RETURN_EV (DWORD)(NGMAC_EVENT_BASE + 66) /*TOOL ֪ͨNGMAC ×ÊÔ´»ØÍË*/
+#define TOOL_NGMAC_PSHO_REL_EV (DWORD)(NGMAC_EVENT_BASE + 67) /*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGMAC_TOOL_PSHO_ACC_EV (DWORD)(NGMAC_EVENT_BASE + 68) /*NGMACÏòTOOLÇëÇóPacket Physical Information*/
+#define TOOL_NGMAC_PKTSCELLSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 69) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVING CELL SI*/
+#define TOOL_NGMAC_PKTAPPINF_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 70) /*TOOLÇëÇóNGMAC·¢ËÍPACKET APPLICATION INFORMATION*/
+
+
+/* ========================================================================
+ NLLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLLC_START_EV (DWORD)(NLLC_EVENT_BASE + 0) /*NLLCÄ£¿éÆô¶¯*/
+#define NLLC_NRLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 1) /*֪ͨNRLCÒÔ·ÇÈ·ÈÏģʽ´«ÊäLLC-PDU*/
+#define NRLC_NLLC_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 2) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸öÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define NRLC_NLLC_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 3) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸ö·ÇÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define TOOL_NLLC_ASSIGN_REQ_EV (DWORD)(NLLC_EVENT_BASE + 4) /*¹¤¾ß֪ͨ NLLCÓÐеļÓÃÜËã·¨ºÍ²ÎÊý£¬ÒÔ¼°·ÖÅäTLLI*/
+#define TOOL_NLLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 5) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÓÃÎÞÓ¦´ð´«Êä*/
+#define NLLC_TOOL_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 6) /*NLLC²ãÏòÉϲ㴫ËÍÒÔ·ÇÈ·ÈÏģʽ½ÓÊÕµ½µÄL3_PDU*/
+#define TOOL_NLLC_DATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 7) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÈ·ÈÏ´«Êä*/
+#define NLLC_TOOL_FRMR_RSP_EV (DWORD)(NLLC_EVENT_BASE + 8) /*ÊÕµ½¾Ü¾øÖ¡*/
+#define NLLC_TOOL_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 9) /*NLLCÏòÉϲ㴫ËͽÓÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_DATA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 10) /*¹¤¾ß²àÏìÓ¦ÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_ESTABLISH_REQ_EV (DWORD)(NLLC_EVENT_BASE + 11) /*ÓÃÓÚΪNLLC²ãÖÐÒ»¸öSAPI½¨Á¢»òÖؽ¨ABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_ESTABLISH_RSP_EV (DWORD)(NLLC_EVENT_BASE + 12) /*ÉϲãÔÚ½ÓÊÕµ½LL_ESTABLISHָʾÔÓïÖ®ºóʹÓÃ.Ö÷ÒªÊÇÐÉÌXID²ÎÊý*/
+#define NLLC_TOOL_UA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 13) /*ÊÕµ½UA·µ»Ø*/
+#define NLLC_TOOL_ESTABLISH_IND_EV (DWORD)(NLLC_EVENT_BASE + 14) /*ÓÃÓÚ֪ͨÉϲã²ã¶ÔNLLC²ãÖеÄÒ»¸öSAPIÒѾ½¨Á¢»òÒѾÖؽ¨ÆðÁËABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_RELEASE_REQ_EV (DWORD)(NLLC_EVENT_BASE + 15) /*ÓÃÓÚÊÍ·ÅΪNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽ*/
+#define NLLC_TOOL_DM_RSP_EV (DWORD)(NLLC_EVENT_BASE + 16) /*ÊÕµ½DM·µ»Ø*/
+#define NLLC_TOOL_RELEASE_IND_EV (DWORD)(NLLC_EVENT_BASE + 17) /*ÓÃÓÚָʾNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽÒѱ»ÊÍ·Å*/
+#define TOOL_NLLC_RELEASE_RSP_EV (DWORD)(NLLC_EVENT_BASE + 18) /*ÓÃÓÚ¹¤¾ß֪ͨNLLC·µ»Ø³É¹¦ÊÍ·ÅÏìÓ¦*/
+#define TOOL_NLLC_XID_REQ_EV (DWORD)(NLLC_EVENT_BASE + 19) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÇëÇó*/
+#define TOOL_NLLC_XID_RSP_EV (DWORD)(NLLC_EVENT_BASE + 20) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÏìÓ¦*/
+#define NLLC_TOOL_XID_CNF_EV (DWORD)(NLLC_EVENT_BASE + 21) /*ÓÃÓÚÈ·ÈÏÉϲãXID²ÎÊýÐÉÌÍê³É*/
+#define NLLC_TOOL_XID_IND_EV (DWORD)(NLLC_EVENT_BASE + 22) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐXID²ÎÊýÐèÒªÐÉÌ*/
+#define NLLC_TOOL_NULL_IND_EV (DWORD)(NLLC_EVENT_BASE + 23) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐNULLÖ¡*/
+
+
+/* ========================================================================
+ NRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NRLC_DATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 0)
+#define NRLC_UNITDATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 1)
+#define NRLC_ASSIGN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 2)
+#define TOOL_NGRLC_ULTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 3)
+#define TOOL_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 4)
+#define TOOL_NGRLC_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 5)
+#define NGRLC_TOOL_DLTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 6)
+#define NGRLC_TOOL_DLTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 7)
+#define NGRLC_TOOL_ULTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 8)
+#define NGRLC_TOOL_ULTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 9)
+#define TOOL_NGRLC_ULTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 10)
+#define NGRLC_TOOL_ULTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 11)
+#define TOOL_NGRLC_DLTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 12)
+#define TOOL_NGRLC_DLTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 13)
+#define TOOL_NGRLC_EXTBF_ON_EV (DWORD)(NRLC_EVENT_BASE + 14)
+#define TOOL_NGRLC_EXTBF_OFF_EV (DWORD)(NRLC_EVENT_BASE + 15)
+#define NGRLC_TOOL_DLTBF_TRIGGER_IND_EV (DWORD)(NRLC_EVENT_BASE + 16)
+#define NGRLC_START_TIMER_EV (DWORD)(NRLC_EVENT_BASE + 17) /*ÄÚ²¿ÏûÏ¢£¬ÆäËûÄ£¿é²»»áʹÓÃ*/
+#define NGRLC_TOOL_DLTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 18)
+#define TOOL_NGRLC_BEGINTEST_MODE_EV (DWORD)(NRLC_EVENT_BASE + 19)
+#define NGRLC_TOOL_PDANNOTIFY_EV (DWORD)(NRLC_EVENT_BASE + 20)
+#define NGRLC_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 21)
+#define NGRLC_FILL_DATA_QUEUE_REQ_EV (DWORD)(NRLC_EVENT_BASE + 22)
+#define L1SIMU_NGRLC_DATA_IND_EV (DWORD)(NRLC_EVENT_BASE + 23)
+#define TOOL_NGRLC_MODE_CFG_REQ_EV (DWORD)(NRLC_EVENT_BASE + 24)
+#define NGRLC_TOOL_UL_DATA_BLOCK_IND_EV (DWORD)(NRLC_EVENT_BASE + 25)
+#define TOOL_NGRLC_DUMMYBLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 26)
+#define DOWNLINK_DUMMY_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 27)
+#define TOOL_NGRLC_DOWNLINK_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 28)
+#define TOOL_NGRLC_PSHO_ULTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 29)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 30)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_RETURN_EV (DWORD)(NRLC_EVENT_BASE + 31)/*TOOL ֪ͨNGRLC ×ÊÔ´»ØÍË*/
+#define TOOL_NGRLC_PSHO_REL_EV (DWORD)(NRLC_EVENT_BASE + 32)/*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGRLC_TOOL_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 33)/*NGRLC ֪ͨTOOL PSHO ³É¹¦*/
+#define NGRLC_NGMAC_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 34)/*NGRLC ֪ͨNGMAC PSHO ³É¹¦*/
+/* ========================================================================
+ URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 0)
+#define URRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 1)
+#define URRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 2)
+#define URRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 3)
+#define URRC_FUNC_ENTER_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 4)
+#define URRC_FUNC_READ_SIB_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 5)
+#define URRC_FUNC_READ_SIB_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 6)
+#define URRC_FUNC_SER_CELL_IND_EV (DWORD)(URRC_FUNC_EVENT_BASE + 7)
+#define URRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 8)
+#define URRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 9)
+#define URRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 10)
+#define URRC_FUNC_START_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 11)
+#define URRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 12)
+#define URRC_FUNC_PAGING_TYPE1_EV (DWORD)(URRC_FUNC_EVENT_BASE + 13)
+#define URRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 14)
+#define URRC_FUNC_GET_UE_CAP_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 15)
+#define URRC_FUNC_CFG_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 16)
+#define URRC_FUNC_CFG_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 17)
+#define URRC_FUNC_REL_FACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 18)
+#define URRC_FUNC_REL_FACH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 19)
+#define URRC_FUNC_REL_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 20)
+#define URRC_FUNC_REL_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 21)
+#define URRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 22)
+#define URRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 23)
+#define URRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 24)
+#define URRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 25)
+#define URRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 26)
+#define URRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(URRC_FUNC_EVENT_BASE + 27)
+#define URRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(URRC_FUNC_EVENT_BASE + 28)
+#define URRC_FUNC_STOP_SYSINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 29)
+#define URRC_FUNC_READ_CGIINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 30)
+#define URRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 31)
+#define URRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 32)
+
+/* ========================================================================
+ TAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TAF_FUNC_L1G_DATA_REQ_EV (DWORD)(TAF_FUNC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1GÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1G_ST_MEAS_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 0)
+#define L1G_ST_MEAS_IND_EV (DWORD)(L1G_ST_EVENT_BASE + 1)
+#define L1G_ST_FCB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 2)
+#define L1G_ST_FCB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 3)
+#define L1G_ST_SYNC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 4)
+#define L1G_ST_BSIC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 5)
+#define L1G_ST_SB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 6)
+#define L1G_ST_RX_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 7)
+#define L1G_ST_RX_EQU_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 8)
+#define L1G_ST_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 9)
+#define L1G_ST_RACH_EV (DWORD)(L1G_ST_EVENT_BASE + 10)
+#define L1G_ST_SDCCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 11)
+#define L1G_ST_SACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 12)
+#define L1G_ST_SACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 13)
+#define L1G_ST_FACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 14)
+#define L1G_ST_FACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 15)
+#define L1G_ST_DS_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 16)
+#define L1G_ST_DS_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 17)
+#define L1G_ST_TCH_CTRL_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 18)
+
+/* ========================================================================
+ GRRº¯Êý¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GRR_FUNC_SUSPEND_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 0)
+#define GRR_FUNC_RESUME_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 1)
+#define GRR_FUNC_SUSPEND_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 2)
+#define GRR_FUNC_RESUME_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 3)
+#define GRR_FUNC_IDLE_MODE_SETTING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 4)
+#define GRR_FUNC_LIST_HANDLING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 5)
+#define GRR_FUNC_SCELL_UPDATE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 6)
+#define GRR_FUNC_INIT_SCELL_PARAM_EV (DWORD)(GRR_FUNC_EVENT_BASE + 7)
+#define GRR_FUNC_INIT_GRR_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 8)
+#define GRR_FUNC_INIT_GRR_SCELL_TMP_EV (DWORD)(GRR_FUNC_EVENT_BASE + 9)
+#define GRR_FUNC_INIT_MI_EV (DWORD)(GRR_FUNC_EVENT_BASE + 10)
+#define GRR_FUNC_SI2QUATER_COMPLETE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 11)
+#define GRR_FUNC_CELL_SEL_BCCH_ALL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 12)
+#define GRR_FUNC_CELL_SEL_BCCH_MIN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 13)
+#define GRR_FUNC_RESET_SYSINFO_EV (DWORD)(GRR_FUNC_EVENT_BASE + 14)
+#define GRR_FUNC_STORE_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 15)
+#define GRR_FUNC_STORE_MODIFY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 16)
+#define GRR_FUNC_COPY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 17)
+#define GRR_FUNC_INDIVID_PRIORITY_CHANGE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 18)
+#define GRR_FUNC_GET_QSEARCH_EV (DWORD)(GRR_FUNC_EVENT_BASE + 19)
+#define GRR_FUNC_COPY_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 20)
+
+
+/* ========================================================================
+ αÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GAS_ST_CTRL_BLOCK_TLV_EV (DWORD)(SIGTRACE_EVENT_BASE + 0) /*GRRÏûÏ¢¶ÔµÈ²ãÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_UL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 1) /*GMAC¶ÔµÈ²ãÉÏÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 2) /*GMAC¶ÔµÈ²ãÏÂÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_SEG_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 3) /*GMAC¶ÔµÈ²ãÏÂÐзֶÎÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DLL_READ_DCCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 4)
+#define GAS_ST_DLL_READ_SACCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 5)
+#define ATI_PDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 6)
+#define UPDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 7)
+#define SN_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 8)
+#define SN_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 9)
+#define LL_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 10)
+#define LL_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 11)
+#define LLC_GET_NEXT_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 12)
+#define GMAC_GET_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 13)
+#define GMAC_ACK_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 14)
+#define PDCP_RLC_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 15)
+#define URLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 16)
+#define URLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 17)
+#define UMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 18)
+#define PH_MAC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 19)
+#define PH_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 20)
+#define MAC_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 21)
+#define RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 23)
+#define LL_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 24)
+#define LL_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 25)
+#define SN_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 26)
+#define SN_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 27)
+#define UPDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 28)
+#define ATI_PDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 29)
+#define UUMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 30)
+#define PDCP_RLC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 31)
+#define TAF_COUNTER_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 32)
+#define TAF_RLP_XID_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 33)
+#define TAF_RLP_XID_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 34)
+#define TAF_RLP_SABM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 35)
+#define TAF_RLP_SABM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 36)
+#define TAF_RLP_UA_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 37)
+#define TAF_RLP_UA_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 38)
+#define TAF_RLP_DISC_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 39)
+#define TAF_RLP_DISC_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 40)
+#define TAF_RLP_DM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 41)
+#define TAF_RLP_DM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 42)
+#define TAFL1G_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 43)
+#define TAFL1G_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 44)
+#define TAF_FUNC_UURLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 45)
+#define TAF_FUNC_UURLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 46)
+#define PDI_PDCP_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 47)
+#define PDCP_DATA_BACK_PDI_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 48)
+/*WCDMA(SIGIRACE=100)*/
+#define WRLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 49)
+#define WRLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 50)
+#define WMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 51)
+#define UWMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 52)
+#define TAF_FUNC_UWRLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 53)
+#define TAF_FUNC_UWRLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 54)
+#define WMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 55)
+#define WMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 56)
+#define EUMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 57)
+#define EUMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 58)
+#define EUMAC_HOLD_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 59)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ EMM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_T3410_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 0)
+#define EMM_T3416_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 1)
+#define EMM_T3417_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 2)
+#define EMM_T3418_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 3)
+#define EMM_T3420_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 4)
+#define EMM_T3421_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 5)
+#define EMM_T3430_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 6)
+#define EMM_T3440_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 7)
+#define EMM_T_POWEROFF_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 8)
+#define EMM_T3417EXT_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 9)
+#define EMM_T_WAITRELIND_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ ESM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_TIMER3480_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 0)
+#define ESM_TIMER3481_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 1)
+#define ESM_TIMER3482_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 2)
+#define ESM_TIMER3492_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 3)
+#define ESM_T_MTACTANSWER_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 4)
+#define ESM_T_WAITINGATH_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 5)
+#define ESM_T_PTIBUF_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 6)
+#define ESM_T_CMEST_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ EPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_T_DISCARD_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 0)
+#define EPDCP_T_DELAYMODEB_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 1)
+#define EPDCP_T_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ EURLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURLC_T_POLL_RETRANSMIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 0)
+#define EURLC_T_STATUS_PROHIBIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 1)
+#define EURLC_T_REORDERING_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 2)
+#define EUL2LOG_T_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 3)
+
+/* ========================================================================
+ EUMAC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMAC_T_EXPIRY_EV (DWORD)(EUMAC_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ EUCER×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_T300_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 0)
+#define EURRC_T301_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 1)
+#define EURRC_T302_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 2)
+#define EURRC_T303_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 3)
+#define EURRC_T304_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 4)
+#define EURRC_T305_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 5)
+#define EURRC_T310_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 6)
+#define EURRC_T311_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 7)
+#define EURRC_T60MS_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 8)
+#define EURRC_T3174_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 9)
+#define EURRC_VARRLF_VALID_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 10)
+#define EURRC_T306_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 11)
+#define EURRC_MCCH_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 12)
+#define EURRC_1SECOND_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 13)
+#define EURRC_TGPAGING_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 14)
+#define EURRC_PERIDOSTATUSREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 15)
+#define EURRC_SELFHOREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 16)
+#define EURRC_SINGLEUSEREXIT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 17)
+
+/* ========================================================================
+ EUMCR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMCR_T320_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 0)
+#define EUMCR_T321_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 1)
+#define EUMCR_T_REMAIN_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 2)
+#define EUMCR_T_LEAVE_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 3)
+#define EUMCR_T_HYSTNORMAL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 4)
+#define EUMCR_T_PROXIMITY_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 5)
+#define EUMCR_T_CELLINFO_REPORT_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 6)
+#define EUMCR_T_RESEL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 7)
+#define EUMCR_T_MDT_LOG_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 8)
+#define EUMCR_T330_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 9)
+#define EUMCR_T_48HOURS_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 10)
+#define EUMCR_T_LISTEN_HANDOVER_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 11)
+#define EUMCR_T_MONITOR_PERIOD_CHG_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 12)
+#define EUMCR_T_MONITOR_HO_EXPIR_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 13)
+/* ========================================================================
+ EUCSR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUCSR_T_SI_MODI_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 0)
+#define EUCSR_T_ABORT_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 1)
+#define EUCSR_T_FREQ_SCAN_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 2)
+#define EUCSR_T_CELL_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 3)
+#define EUCSR_T_PLMN_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 4)
+#define EUCSR_T_CSG_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 5)
+#define EUCSR_T_3HOUR_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 6)
+#define EUCSR_T_OOS_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 7)
+#define EUCSR_T_SWITCH_RADIO_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 8)
+#define EUCSR_T_REDIRECT_TO_LTE_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 9)
+#define EUCSR_T_SYNC_BARREDLIST_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 10)
+#define EUCSR_T_WAIT_RESEL_TO_UTRA_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 11)
+#define EUCSR_T_REDIRECT_TO_LTE_OP_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 12)
+#define EUCSR_T_LISTEN_RESEL_SUCC_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 13)
+#define EUCSR_T_LBS_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 14)
+#define EUCSR_T_ECID_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 15)
+
+
+/* ========================================================================
+ EUSIR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUSIR_T_SIB1GUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 0)
+#define EUSIR_T_SIMSGGUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 1)
+#define EUSIR_T_ETWS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 2)
+#define EUSIR_T_CMAS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 3)
+#define EUSIR_T_SIBVALID_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ EMMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_TU_SUCC_IND_EV (DWORD)(EMM_UMM_EVENT_BASE + 0)
+
+#define UMM_CONFIG_REQ_EV (DWORD)(EMM_UMM_RSP_EVENT + 0)
+
+/* ========================================================================
+ UMMºÍEPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_UMM_EST_REJ_EV (DWORD)(UMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_UMM_EST_REQ_EV (DWORD)(UMM_EPDCP_RSP_EVENT + 0)
+
+/* ========================================================================
+ CM²ãºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EMM_DATA_REQ_EV (DWORD)(CM_EMM_EVENT_BASE + 0)
+/* ========================================================================
+ ESMºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESM->EMM*/
+#define ESM_EMM_DEFAULT_ACT_REJ_EV (DWORD)(ESM_EMM_EVENT_BASE + 0)
+#define ESM_EMM_EMERGENCY_PDN_EST_SUCC_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 1)
+#define ESM_EMM_EMERGENCY_PDN_ONLY_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 2)
+
+/* EMM->ESM*/
+#define ESM_EMM_DATA_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 0)
+#define ESM_EMM_ATTACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 1)
+#define ESM_EMM_ATTACH_REJ_EV (DWORD)(ESM_EMM_RSP_EVENT + 2)
+#define ESM_EMM_CONTEXT_STATUS_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 3)
+#define ESM_EMM_DETACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 4)
+#define ESM_EMM_DETACH_EMERGENCY_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 5)
+#define EMM_ESM_DETACH_NORMAL_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 6)
+
+/* ========================================================================
+ EMMºÍASC(ERRC(CER))Ä£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_ASC_EST_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 1)
+#define EMM_ASC_EST_ABT_EV (DWORD)(EMM_ASC_EVENT_BASE + 2)
+#define EMM_ASC_REL_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 3)
+#define EMM_ASC_KENB_RSP_EV (DWORD)(EMM_ASC_EVENT_BASE + 4)
+#define EMM_ASC_REL_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 5)
+#define EMM_ASC_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 6)
+#define EMM_ASC_DETACH_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 7)
+
+/* EURRC->ASC */
+#define EMM_ASC_DATA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 0)
+#define EMM_ASC_EST_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 1)
+#define EMM_ASC_EST_REJ_EV (DWORD)(EMM_ASC_RSP_EVENT + 2)
+#define EMM_ASC_REL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 3)
+#define EMM_ASC_ABA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 4)
+#define EMM_ASC_DRB_SETUP_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 5)
+#define EMM_ASC_TRANS_FAIL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 6)
+#define EMM_ASC_KENB_REQ_EV (DWORD)(EMM_ASC_RSP_EVENT + 7)
+#define EMM_ASC_UE_INFO_CHANGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 8)
+#define EMM_ASC_DATA_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 9)
+#define EMM_ASC_PAGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 10)
+#define EMM_ASC_SEC_PARA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 11)
+/* ========================================================================
+ EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EPDCP_EMM_EST_REJ_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_EMM_BAR_ALLEVIATE_NOTIFY_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 1)
+/* ========================================================================
+ ESMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESMºÍUMMÄ£¿éÖ®¼äµÄÏûϢʼþºÅ--
+* 1.CM_EST_REQ_EV£¬
+* 2.CM_EST_CNF_EV£¬
+* 3.CM_RELIND_EVÑØÓÃÒÔÇ°90AµÄ½Ó¿Ú*/
+/*ESM->UMM*/
+#define ESM_UMM_DETACH_REQ_EV (DWORD)(ESM_UMM_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_UMM_LOCAL_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 1)
+#define ESM_UMM_EMERPDN_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 2)
+
+/* ========================================================================
+ SMºÍESMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*SM->ESM*/
+#define SM_ESM_DATA_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 0) /*Added:KangShuJie*/
+#define SM_ESM_RAT_ACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define SM_ESM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define SM_ESM_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 3) /*Added:KangShuJie*/
+/*ESM->SM*/
+#define ESM_SM_DATA_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 0) /*Added:KangShuJie*/
+#define ESM_SM_RAT_ACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 1) /*Added:KangShuJie*/
+#define ESM_SM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 2) /*Added:KangShuJie*/
+#define ESM_SM_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 3) /*Added:KangShuJie*/
+
+
+/* ========================================================================
+ ESMºÍEPDCP*Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_EPDCP_DEACTIVATE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_MOVE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_DEL_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define ESM_EPDCP_DIAL_IND_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 3)
+#define DEL_USER_PLANE_BUFFER_DATA_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 4)
+
+#define ESM_EPDCP_LOCAL_DEACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 0)
+#define ESM_EPDCP_RAT_SEQ_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 1)
+#define ESM_EPDCP_RAT_ACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 2)
+#define ESM_EPDCP_RAT_CHANGE_COMP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 3) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_SEQ_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 4) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_ACT_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 5) /*Added:KangShuJie*/
+#define EPDCP_ESM_STATUS_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 6) /*Added:KangShuJie*/
+#define ESM_EPDCP_CURR_BEAR_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 7)
+
+/* ========================================================================
+ EURRCºÍEPDCPÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 0)
+#define EURRC_EPDCP_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 1)
+#define EURRC_EPDCP_DATA_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 2)
+#define EURRC_EPDCP_REESTABLISH_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 3)
+#define EURRC_EPDCP_RELEASE_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 4)
+#define EURRC_EPDCP_RESUME_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 5)
+#define EURRC_EPDCP_SUSPEND_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 6)
+#define EURRC_EPDCP_DECIPHER_AND_INT_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 7)
+#define EURRC_EPDCP_HO_SUCC_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 8)
+#define EURRC_EPDCP_HO_FAIL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 9)
+#define EURRC_EPDCP_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 10)/*Added:KangShuJie*/
+#define EURRC_EPDCP_SMC_END_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 11)
+#define EURRC_EPDCP_TRUNKING_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 12)
+#define EURRC_EPDCP_CELL_RESEL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 13)
+
+
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 0)
+#define EURRC_EPDCP_DATA_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 1)
+#define EURRC_EPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 2)
+#define EURRC_EPDCP_CONFIG_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 3)
+#define EURRC_EPDCP_DATA_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 4)
+#define EURRC_EPDCP_REESTABLISH_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 5)
+#define EURRC_EPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 6)
+/* ========================================================================
+ EURRCºÍEURLCÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EURLC_CONFIG_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EURLC_RELEASE_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+
+#define EURRC_EURLC_CONFIG_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EL2_EURRC_RADIOLINK_FAIL_IND_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EURRC_EL2_TRUNKCH_ERROR_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 3)
+/* ========================================================================
+ EURRCºÍEUMACÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EURRC_EUMAC_CCCH_DATA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_COMM_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_DEDI_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_REL_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 3) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESET_MAC_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 4) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESUME_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 5) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_SUSPEND_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 6) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 7) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_HO_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 8)
+#define EURRC_EUMAC_REL_DEDI_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 11)
+#define EURRC_EUMAC_GRNTI_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 12)
+#define EURRC_EUMAC_SR_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 13)
+#define EURRC_EUMAC_LISTENINGCFG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 14)
+
+#define EUMAC_EURRC_CCCH_DATA_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_PROBLEM_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_SUCC_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_HO_CNF_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 3)
+#define EUMAC_EURRC_PUCCH_SRS_REL_REQ (DWORD)(EURRC_EUMAC_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define EURLC_EPDCP_UM_DATA_CNF_EV (DWORD)(EUPDCP_EURLC_EVENT_BASE + 0)
+
+/* ========================================================================
+ EURRCºÍMEL2Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EUMAC_MCH_CONFIG_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 0)
+#define EURRC_EUMAC_MCH_REL_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 1)
+#define MEL2_DMA_COMPLETE_IND (DWORD)(EURRC_MEL2_EVENT_BASE + 2)
+#define EUMAC_EURRC_MCCH_DATA_IND_EV (DWORD)(EURRC_MEL2_RSP_EVENT + 0)
+
+/* ========================================================================
+ EURRCÄÚ²¿ÏûϢʼþºÅ¶¨Òå
+======================================================================== */
+/*EUCER-EUMCR*/
+#define EURRC_MCR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 0)
+#define EURRC_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 1)
+#define EURRC_IDLE_INFO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 2)
+
+#define EURRC_SCELL_UNSUITABLE_IND_EV (DWORD)(EURRC_EVENT_BASE + 3)
+#define EURRC_CER_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 4)
+
+/*EUCER-EUCSR*/
+#define EURRC_CSR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 5)
+#define EURRC_CELL_INFO2NAS_EV (DWORD)(EURRC_EVENT_BASE + 6)
+#define EURRC_BARRED_CELL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 7)
+#define EURRC_REL_EPHY_CNF_EV (DWORD)(EURRC_EVENT_BASE + 8)
+
+#define EURRC_CER_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 9)
+#define EURRC_CELL_SEL_SUCC_IND_EV (DWORD)(EURRC_EVENT_BASE + 10)
+#define EUCER_TRS_TEST_IND_EV (DWORD)(EURRC_EVENT_BASE + 11)
+#define EURRC_REL_EPHY_REQ_EV (DWORD)(EURRC_EVENT_BASE + 12)
+/*EUCER-EUSIR*/
+
+#define EURRC_CER_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 13)
+
+/*EUCSR-EUMCR*/
+#define EURRC_CELL_RESEL_REJ_EV (DWORD)(EURRC_EVENT_BASE + 14)
+#define EURRC_PLMN_SEL_IND_EV (DWORD)(EURRC_EVENT_BASE + 15)
+#define EURRC_MCR_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 16)
+
+#define EURRC_CELL_RESEL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 17)
+#define EURRC_CSR_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 18)
+/*EUCSR-EUSIR*/
+
+#define EURRC_READ_SI_REQ_EV (DWORD)(EURRC_EVENT_BASE + 19)
+#define EURRC_ABORT_SI_READ_REQ_EV (DWORD)(EURRC_EVENT_BASE + 20)
+
+#define EURRC_CSR_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 21)
+#define EURRC_CSG_IND_EV (DWORD)(EURRC_EVENT_BASE + 22)
+#define EURRC_WARNING_NOTIFY_INFO_EV (DWORD)(EURRC_EVENT_BASE + 23)
+
+/*EUCSR-EUCER*/
+#define EURRC_CER_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 24)
+
+
+/*UMCR-EUSIR*/
+ /*UMCR-EUSIR ͬEURRC_READSI_REQ_EV
+ EURRC_ABORTSIREAD_REQ_EV */
+
+#define EURRC_MCR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 25)
+#define EURRC_CGI_CNF_EV (DWORD)(EURRC_EVENT_BASE + 26)
+#define EURRC_GET_RF_REQ_EV (DWORD)(EURRC_EVENT_BASE + 27)
+#define EURRC_GET_RF_CNF_EV (DWORD)(EURRC_EVENT_BASE + 28)
+#define EURRC_CSG_PROXIMITY_IND_EV (DWORD)(EURRC_EVENT_BASE + 29)
+#define EURRC_SI_END_FOR_HO_EV (DWORD)(EURRC_EVENT_BASE + 30)
+#define EURRC_MDT_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 31)
+#define EURRC_MCR_CGI_PEND_REQ_EV (DWORD)(EURRC_EVENT_BASE + 32)
+#define EURRC_MCR_CGI_PEND_CNF_EV (DWORD)(EURRC_EVENT_BASE + 33)
+#define EURRC_INTEREST_FREQ_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 34)
+#define EURRC_CER_SELFHO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 35)
+#define EURRC_NETWORK_TIME_INFO_IND_EV (DWORD)(EURRC_EVENT_BASE + 36)
+#define EURRC_RRC_STATE_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 37)
+#define EURRC_EUCER_RESUME_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 38)
+#define EURRC_EUCER_ABORT_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 39)
+#define EURRC_CSR_XCELL_IND_EV (DWORD)(EURRC_EVENT_BASE + 40)
+#define EURRC_EUMCR_START_MEAS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 41)
+#define EURRC_CSR_RESEL_START_EV (DWORD)(EURRC_EVENT_BASE + 42)
+#define EURRC_CSR_RESEL_END_EV (DWORD)(EURRC_EVENT_BASE + 43)
+#define EURRC_CSR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 44)
+//LBS
+#define EURRC_CELL_MEAS_IND_EV (DWORD)(EURRC_EVENT_BASE + 45)
+#define EURRC_EUMCR_START_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 46)
+#define EURRC_EUMCR_STOP_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 47)
+#define EURRC_EUCER_UE_INFO_RLF_9E0_EV (DWORD)(EURRC_EVENT_BASE + 48)
+#define EURRC_EUCER_UE_CAPA_LTE_9D0_EV (DWORD)(EURRC_EVENT_BASE + 49)
+#define EURRC_MEAS_GAP_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 50)
+#define EURRC_CER_REL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 51)
+
+
+/*EURRC<->L1E*/
+#define EURRC_L1E_MEAS_SUSPEND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 0)
+#define EURRC_L1E_MEAS_RESUME_EV (DWORD)(EURRC_L1E_EVENT_BASE + 1)
+#define EURRC_L1E_GSM_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 2)
+#define EURRC_L1E_UTRA_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 3)
+#define EURRC_L1E_GSM_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 4)
+#define EURRC_L1E_TD_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 5)
+#define EURRC_L1E_RESOURCE_REL_EV (DWORD)(EURRC_L1E_EVENT_BASE + 6)
+#define EURRC_L1E_RESOURCE_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 7)
+#define EURRC_L1E_SI_END_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 8)
+#define EURRC_L1E_GET_RF_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 9)
+#define EURRC_L1E_STATE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 10)
+#define EURRC_L1E_TRACE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 11)
+#define EURRC_L1E_W_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 12)
+#define EURRC_L1E_IRAT_CGI_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 13)
+#define EURRC_L1E_IRAT_CGI_END_EV (DWORD)(EURRC_L1E_EVENT_BASE + 14)
+
+#define L1E_EURRC_RESOURCE_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 0)
+#define L1E_EURRC_GSM_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 1)
+#define L1E_EURRC_TD_LIST_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 2)
+#define L1E_EURRC_TD_BLIND_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 3)
+#define EURRC_L1E_GET_RF_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 4)
+#define L1E_EURRC_W_MEAS_RLT_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 5)
+/* ========================================================================
+ LTEÐÒéÕ»ºÍÎïÀí²ãÏûϢʼþÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* PS -> EPHY MSG ID */
+#define LTE_P_FREQ_SCAN_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 0)
+#define LTE_P_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 1)
+#define LTE_P_READ_SIB1_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 2)
+#define LTE_P_SCHED_SI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 3)
+#define LTE_P_ABORT_SI_READ_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 4)
+#define LTE_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 5)
+#define LTE_P_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 6)
+#define LTE_P_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 7)
+#define LTE_P_MEAS_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 8)
+#define LTE_P_ABORT_MEAS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 9)
+#define LTE_P_EARFCN_BAND_INFO_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 10)
+#define LTE_P_COMMON_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 11)
+#define LTE_P_DEDICATED_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 12)
+#define LTE_P_HANDOVER_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 13)
+#define LTE_P_MAC_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 14)
+#define LTE_P_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 15)
+#define LTE_P_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 16)
+#define LTE_P_ABORT_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 17)
+#define LTE_P_TA_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 18)
+#define LTE_P_DRX_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 19)
+#define LTE_P_TA_TIMER_STOP_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 20)
+#define LTE_P_FREQ_LIST_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 21)
+#define LTE_P_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 22)
+#define LTE_P_ABORT_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 23)
+#define LTE_P_IRAT_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 24)
+#define LTE_P_IDLE_PERIOD_REP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 25)
+#define LTE_P_SET_MODE_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 26)
+#define LTE_P_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 27)
+#define LTE_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 28)
+#define LTE_P_WAKEUP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 29)
+#define ZPS_LTE_ZEPCG_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 30)
+#define LTE_P_GRNTI_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 31)
+#define LTE_P_BTRUNK_TTCH_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 32)
+#define LTE_P_DEDICATECD_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 33)
+#define LTE_P_BTRUNK_CONFIG_REL_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 34)
+#define LTE_P_ACT_DEACT_SCELL_CTRL_ELEMNT_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 35)
+#define LTE_P_MCCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 36)
+#define LTE_P_MTCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 37)
+#define LTE_P_MTCH_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 38)
+#define LTE_P_PMCH_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 39)
+#define LTE_P_MSI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 40)
+#define LTE_P_CARD2_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 41) /*T_zLTE_P_card2_gap_req*/
+#define LTE_P_CARD2_GAP_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 42) /*T_zLTE_P_card2_gap_rel_req*/
+#define LTE_P_CARD2_STOP_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 43) /*T_zLTE_P_card2_stop_gap_req*/
+#define LTE_P_CARD1_SUSPEND_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 44) /*T_zLTE_P_card1_suspend_req*/
+#define LTE_P_CARD1_RESUME_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 45) /*T_zLTE_P_card1_resume_req*/
+#define LTE_P_MEAS_PERIOD_CHG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 46)
+#define LTE_P_AMT_MSG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 47)
+#define LTE_P_RPI_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 48)
+#define LTE_P_RPI_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 49)
+#define LTE_P_OTDOA_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 50)
+#define LTE_P_OTDOA_MEAS_ABORT_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 51)
+#define ZPS_LTE_CARD_SWITCH_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 52)
+
+
+
+/* EPHY -> PS MSG ID */
+#define LTE_P_SI_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 0)
+#define LTE_P_PBCH_READ_FAIL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 1)
+#define LTE_P_FREQ_SCAN_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 2)
+#define LTE_P_CELL_SEARCH_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 3)
+#define LTE_P_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 4)
+#define LTE_P_INTRA_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 5)
+#define LTE_P_INTER_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 6)
+#define LTE_P_DRX_STATE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 7)
+#define LTE_P_HANDOVER_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 8)
+#define LTE_P_OUT_OF_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 9)
+#define LTE_P_RECOVERY_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 10)
+#define LTE_P_PUCCH_SRS_REL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 11)
+#define LTE_P_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 12)
+#define LTE_P_ACCESS_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 13)
+#define LTE_P_EUMAC_INIT_RA_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 14)
+#define LTE_P_RA_RESPONSE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 15)
+#define LTE_P_DLSCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 16)
+#define LTE_P_IRAT_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 17)
+#define LTE_P_ABORT_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 18)
+#define LTE_P_RESET_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 19)
+#define LTE_P_INACTIVE_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 20)
+#define LTE_P_SLEEP_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 21)
+#define ZPS_LTE_ZEPCG_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 22)
+#define LTE_P_EMBMS_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 23)
+#define LTE_P_ULGRANT_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 24)
+#define LTE_P_OTDOA_MEAS_RLT_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 25)
+#define LTE_P_C0_SAVE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 26)
+#define LTE_P_BTRUNK_CQI_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 27)
+#define LTE_P_LISTENINGHO_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 28)
+#define LTE_P_BTRUNK_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 29)
+#define EPDCP_EDCP_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 30)
+#define EURLC_EMAC_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 31)
+#define LTE_P_CARD2_GAP_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 32) /*T_zLTE_P_card2_gap_ind*/
+#define LTE_P_CARD2_GAP_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 33)
+#define LTE_P_CARD2_STOP_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 34)
+#define LTE_P_CARD1_SUSPEND_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 35)
+#define LTE_P_PHYWAKEUPPS_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 36)
+#define LTE_P_ICP_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 37)
+#define LTE_P_AMT_MSG_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 38)
+#define ZPS_LTE_CARD_SWITCH_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 39)
+
+
+#if 0
+#define LTE_P_RF_ERR_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 40)
+#endif
+
+
+/* ========================================================================
+ LTEÐÒéÕ»ºÍTRSÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TRS_ESM_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 0)
+#define TRS_ESM_L3TC_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 1)
+#define TRS_ESM_ACT_DED_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 0)
+#define TRS_ESM_ACT_DED_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 1)
+#define TRS_ESM_ACT_DEF_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 2)
+#define TRS_ESM_ACT_DEF_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 3)
+#define TRS_ESM_BR_ALLOC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 4)
+#define TRS_ESM_BR_MOD_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 5)
+#define TRS_ESM_DEACT_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 6)
+#define TRS_ESM_ESMINFO_RSP_EV (DWORD)(TRS_ESM_RSP_EVENT + 7)
+#define TRS_ESM_ESMSTATUS_EV (DWORD)(TRS_ESM_RSP_EVENT + 8)
+#define TRS_ESM_MOD_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 9)
+#define TRS_ESM_MOD_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 10)
+#define TRS_ESM_PDN_CON_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 11)
+#define TRS_ESM_PDN_DISC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 12)
+#define TRS_ESM_L3TC_CLOSE_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 13)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 14)
+#define TRS_ESM_L3TC_ACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 15)
+#define TRS_ESM_L3TC_DEACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 16)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMBMSPACKETCNT_RESP_EV (DWORD)(TRS_ESM_RSP_EVENT + 17)
+/* TRS -> MME_EMM */
+#define TRS_EMM_DATA_REQ_EV (DWORD)(TRS_EMM_EVENT_BASE + 0)
+#define TRS_EMM_MAPPED_SEC_PARAM_Ev (DWORD)(TRS_EMM_EVENT_BASE + 1)
+#define TRS_EMM_PS_HO_FROM_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 2)
+#define TRS_EMM_PS_HO_TO_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 3)
+/* MME_EMM ->TRS */
+#define ENB_TRS_ESM_CMD_EV (DWORD)(TRS_EMM_RSP_EVENT + 0)
+#define TRS_EMM_L3MSG_ATTACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 1)
+#define TRS_EMM_L3MSG_ATTACH_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 2)
+#define TRS_EMM_L3MSG_AUTH_FAIL_EV (DWORD)(TRS_EMM_RSP_EVENT + 3)
+#define TRS_EMM_L3MSG_AUTH_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 4)
+#define TRS_EMM_L3MSG_AUTH_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 5)
+#define TRS_EMM_L3MSG_DETACH_APT_EV (DWORD)(TRS_EMM_RSP_EVENT + 6)
+#define TRS_EMM_L3MSG_DETACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 7)
+#define TRS_EMM_L3MSG_ULNAS_TRANS_EV (DWORD)(TRS_EMM_RSP_EVENT + 8)
+#define TRS_EMM_L3MSG_SERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 9)
+#define TRS_EMM_L3MSG_EXSERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 10)
+#define TRS_EMM_L3MSG_GUTI_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 11)
+#define TRS_EMM_L3MSG_IDNT_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 12)
+#define TRS_EMM_L3MSG_SMC_COM_EV (DWORD)(TRS_EMM_RSP_EVENT + 13)
+#define TRS_EMM_L3MSG_SMC_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 14)
+#define TRS_EMM_L3MSG_TAU_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 15)
+#define TRS_EMM_L3MSG_TAU_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 16)
+#define TRS_EMM_L3MSG_EMMSTATUS_EV (DWORD)(TRS_EMM_RSP_EVENT + 17)
+#define TRS_EMM_DATA_IND_EV (DWORD)(TRS_EMM_RSP_EVENT + 18)
+
+#define ENB_EMM_ESM_DATA_REQ_EV (DWORD)(ENB_EMM_ESM_EVENT_BASE + 0)
+#define ENB_EMM_ESM_DATA_IND_EV (DWORD)(ENB_EMM_ESM_RSP_EVENT + 0)
+/* MME_EMM -> ENBRRC */
+#define ENB_RRC_EMM_DATA_REQ_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 0)
+#define ENB_RRC_EMM_DLSQN_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 1)
+/* ENBRRC -> MME_EMM */
+#define ENB_RRC_EMM_DATA_IND_EV (DWORD)(ENB_RRC_EMM_RSP_EVENT + 0)
+
+
+/* ÆäËüLTE²âÊÔÄ£¿éÏûÏ¢IDºêÌí¼Ó´¦*/
+#define ENBRRC_RRC_CONN_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 0)
+#define ENBRRC_RRC_CONN_SETUP_EV (DWORD)(ENB_RRC_EVENT_BASE + 1)
+#define ENBRRC_RRC_CONN_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 2)
+#define ENBRRC_RRC_CONN_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 3)
+#define ENBRRC_SEC_MODE_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 4)
+#define ENBRRC_SEC_MODE_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 5)
+#define ENBRRC_SEC_MODE_FAIL_EV (DWORD)(ENB_RRC_EVENT_BASE + 6)
+#define ENBRRC_RRC_CONN_RECONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 7)
+#define ENBRRC_RRC_CONN_RECONFIG_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 8)
+#define ENBRRC_RRC_CONN_REEST_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 9)
+#define ENBRRC_RRC_CONN_REEST_EV (DWORD)(ENB_RRC_EVENT_BASE + 10)
+#define ENBRRC_RRC_CONN_REEST_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 11)
+#define ENBRRC_RRC_CONN_REEST_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 12)
+#define ENBRRC_RRC_CONN_REL_EV (DWORD)(ENB_RRC_EVENT_BASE + 13)
+#define ENBRRC_UE_CAP_ENQUIRY_EV (DWORD)(ENB_RRC_EVENT_BASE + 14)
+#define ENBRRC_UE_CAP_INFO_EV (DWORD)(ENB_RRC_EVENT_BASE + 15)
+#define ENBRRC_UE_MEAS_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 16)
+#define ENB_NASRRC_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 17)
+#define ENB_NASRRC_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 18)
+#define TRS_EPHY_UE_MEAS_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 19)
+#define TRS_EPHY_UE_CER_HO_REQ_CTL_EV (DWORD)(ENB_RRC_EVENT_BASE + 20)
+#define ENBRRC_COUNTER_CHECK_SUCC_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 21)
+#define ENBRRC_COUNTER_CHECK_FAIL_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 22)
+#define ENBRRC_MOBILITY_FROM_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 23)
+#define ENBRRC_START_HO_FROM_EUTRA_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 24)
+#define ENBRRC_START_HO_TO_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENBRRC_PROXIMITY_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 26)
+#define ENBRRC_UE_INFO_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 27)
+#define ENBRRC_UE_INFO_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 28)
+#define ENBRRC_MBSFN_AREA_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 29)
+#define ENBRRC_MBMS_COUNTING_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 30)
+#define ENBRRC_TDLINFO_TRANS_EV (DWORD)(ENB_RRC_EVENT_BASE + 31)
+#define ENBRRC_GROUPCALL_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 32)
+#define ENBRRC_GROUPCALL_RELEASE_EV (DWORD)(ENB_RRC_EVENT_BASE + 33)
+#define ENRRC_NEIGHBOURINFO_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+
+#define ENRRC_ENPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 0)
+#define ENRRC_ENPDCP_CONFIG_CIPHER_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 1)
+#define ENRRC_ENPDCP_CONFIG_INTEGRITY_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 2)
+#define ENRRC_ENPDCP_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 3)
+#define ENRRC_ENPDCP_DATA_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 4)
+#define ENRRC_ENPDCP_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 5)
+#define ENRRC_ENPDCP_RELEASE_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 6)
+#define ENRRC_ENPDCP_RESUME_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 7)
+#define ENRRC_ENPDCP_SUSPEND_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 8)
+#define ENRRC_ENPDCP_DECIPHER_AND_INTCHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 9)
+#define ENRRC_ENPDCP_SEC_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 10)
+
+#define ENRRCENPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 0)
+#define ENRRCENPDCP_DATA_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 1)
+#define ENRRCENPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 2)
+#define ENRRCENPDCP_CONFIG_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 3)
+#define ENRRCENPDCP_DATAC_NF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 4)
+#define ENRRCENPDCP_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 5)
+#define ENRRCENPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 6)
+#define ENRRCENPDCP_ENABLE_UL_DECIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 7)
+#define ENRRCENPDCP_COUNTER_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 8)
+#define ENRRCENPDCP_MDT_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 9)
+
+#define ENPDCP_EDCP_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 0)
+#define ENRLC_ENMAC_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 1)
+/* ========================================================================
+ ENPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDCP_DISCARDTIMER_EV (DWORD)(ENPDCP_TIMER_EVENT_BASE + 0)
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDI_DATA_REQ_EV (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 0)
+
+#define ENPDI_DATA_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 0)
+#define ENPDI_NOT_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 1)
+#define ENPDI_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 2)
+
+
+/* ========================================================================
+ TRS ÏûÏ¢ºÅ¶¨ÒåΪGCF ²âÊÔ¶øÌí¼Ó2010/3/8 SHIFANGMING
+======================================================================== */
+
+#define LTE_GCF_STARTCHECK_REQ_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 0)
+#define LTE_GCF_CHECKPASS_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 1)
+#define LTE_GCF_CHECKFAIL_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 2)
+
+#define LTE_GCF_CHECK_TIMER_EV (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ ENRLC - TRS ÏûÏ¢ºÅ¶¨Òå2010/3/1 LIUHUAN
+======================================================================== */
+#define TRS_ENRLC_UMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 0)
+#define TRS_ENRLC_AMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 1)
+#define TRS_ENRLC_SDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 2)
+#define TRS_ENRLC_AUTOACK_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ PDI - TRS ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SIMULATI_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 0)
+#define SIMULATI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 1)
+#define SIMULATI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 2)
+#define SIMULATI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 3)
+#define SIMULATI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 4)
+#define SIMULATI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 5)
+#define SIMULATI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 6)
+#define SIMULATI_DATA_IND_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 7)
+#define SIMULPSI_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 8)
+#define SIMULATI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 9)
+#define SIMULATI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define SIMULATI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 11)
+#define SIMULATI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 12)
+#define SIMULATI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 13)
+
+#define SIMULENPDI_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 0)
+#define SIMULENPDI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 1)
+#define SIMULENPDI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 2)
+#define SIMULENPDI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 3)
+#define SIMULENPDI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 4)
+#define SIMULENPDI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 5)
+#define SIMULENPDI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 6)
+#define SIMULENPDI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 7)
+#define SIMULENPDI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 8)
+#define SIMULENPDI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 9)
+#define SIMULENPDI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define SIMULENPDI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 11)
+/* ========================================================================
+ ENRRCÓëENRLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRRC_ENRLC_CONFIG_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 0)
+#define ENRRC_ENRLC_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 1)
+#define ENRRC_ENRLC_RELEASE_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 2)
+
+#define ENRLC_ENRRC_CONFIG_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 0)
+#define ENRLC_ENRRC_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 1)
+#define ENRLC_ENRRC_RETX_FAIL_IND_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 2)
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define ENRLC_ENPDCP_UMDATA_CNF_EV (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 0)
+
+
+/* ========================================================================
+ ENRLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRLC_REORDERING_TIMER_EV (DWORD)(ENRLC_TIMER_EVENT_BASE + 0)
+/*EPHY--->ENMAC*/
+#define EPHY_ENMAC_DATA_IND_EV (DWORD)(ENMAC_EPHY_RSP_EVENT + 0) /*EUMAC·¢Ë͵ÄÊý¾Ýµ½´ï*/
+
+/***************************************************** ¶ÔÓ¦UE²àRRC Ïà¹ØÏûÏ¢ *********** Êý¾ÝÃæÕâÀïÓ¦¸Ã²»ÐèÒªÕâЩÏûÏ¢ ÕâÀïµÄ¶¨ÒåÊÇÒÔ·ÀÍòÒ» ******************************************************/
+#define ENMAC_CCCH_DATA_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 0) /*RRC²àÇëÇóCCCHÊý¾Ý*/
+#define ENMAC_COMM_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 1) /*RRC²à·¢ËÍͨÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_DEDI_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 2) /*RRC²à·¢ËÍרÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_REL_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 3) /*RRC²àÇëÇóMACÊÍ·Å×ÊÔ´¡¢Í˳öÁ¬½Ó̬*/
+#define ENMAC_RESET_MAC_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 4) /*RRC²àÇëÇóMAC RESET*/
+#define ENMAC_RESUME_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5) /*RRC²àÇëÇó»Ö¸´RB*/
+#define ENMAC_SUSPEND_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6) /*RRC²àÇëÇóÔÝÍ£RB*/
+#define ENMAC_ACTIVE_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 7)
+
+
+
+#define ENMAC_CCCH_DATA_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 0) /*MAC¸æÖªRRC CCCH Êý¾Ýµ½´ï*/
+#define ENMAC_RA_PROBLEM_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 1) /*MAC¸æÖªRRC RA ÖØ´«´ÎÊý¹ý¶à*/
+#define ENMAC_RA_SUCCESS_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 2) /*MAC¸æÖªRRC RA ³É¹¦*/
+
+/*TRS--->EPHY*/
+#define EPHY_TIMER_INTERUPT_EV (DWORD)(TRS_EPHY_EVENT_BASE + 1) /* ×ÓÖ¡Öжϴ¥·¢ÏûÏ¢ */
+#define TRS_EPHY_DUPLICATE_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 2) /*TRSÏòEPHY·¢ËÍÖظ´·¢ËÍÊý¾ÝµÄÅäÖÃÏûÏ¢*/
+#define EPHY_DL_RARESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 3) /*TRSÏòEPHY·¢ËÍ RA³É¹¦Óë·ñµÄÅäÖà */
+#define EPHY_DL_CRRESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 4) /*TRSÏòEPHY·¢ËÍ CR³É¹¦Óë·ñµÄÅäÖà */
+#define TRS_EPHY_DISCARD_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 5) /*TRSÏòEPHY·¢ËÍ ¶ª°üµÄÅäÖà */
+#define TRS_EPHY_GRANT_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 6) /*TRSÏòEPHY·¢ËÍ ÊÚȨµÄÅäÖòÎÊý */
+#define TRS_EPHY_DISORDER_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 7) /*TRSÏòEPHY·¢ËÍÂÒÐò·¢Ë͵ÄÅäÖÃÏûÏ¢*/
+
+#define EPHY_ULGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 8) /*¼¤·¢ÉÏÐÐ×éÖ¡*/
+#define EPHY_DLGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 9) /*¼¤·¢ÏÂÐÐ×éÖ¡*/
+#define EPHY_GRANTARRAYCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 10) /*ÅäÖÃÉÏÏÂÐÐÊÜȨÊý×é*/
+#define EPHY_IDLE_PERIOD_REP_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 11) /*ÅäÖÿÕÏÐʱ¼ä*/
+#define EPHY_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 12) /*¹¤¾ß¶ÔEPHYµÄÅäÖÃ*/
+/* C# adaptor·¢Ë͵½ephyµÄÏûÏ¢£¬ÁÙʱ´æ·ÅÔÚÕâÀï*/
+#define TRS_FREQ_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 13)
+#define TRS_CELL_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 14)
+#define TRS_CELL_DEL_IND (DWORD)(TRS_EPHY_EVENT_BASE + 15)
+#define TRS_CELL_MOD_IND (DWORD)(TRS_EPHY_EVENT_BASE + 16)
+#define TRS_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 17) // ÉèÖÃC#ģʽ£¬0 - auto £¬ 1- manual
+#define TRS_MSG_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 18) // ÉèÖÃij¸öÏûÏ¢µÄģʽ£¬×Ô¶¯»òÊÖ¶¯
+#define EPHY_CELLINFOCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+#define EPHY_EXTGRANTCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 20)
+/*TRS--->ENMAC*/
+#define TRS_ENMAC_TA_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 1) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà TAÃüÁîÏûÏ¢ Я´øWORDÊý¾Ý£¬Îª0ʱ²»×éTA£¬·Ç0ʱ£¬Ê¹ÓøÃÖµ×éTA*/
+#define TRS_ENMAC_DRX_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 2) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà DRXÃüÁî ÏûÏ¢*/
+#define TRS_ENMAC_CCCH_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 3) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡CCCCHÊý¾Ý*/
+#define TRS_ENMAC_CRID_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 4) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡¾ºÕù½â¾öÉí·ÝÊý¾Ý£¬BIT0Ϊ1£¬
+ BIT1Ϊ0ʱ×éÖ¡·ÇÆ¥ÅäÊý¾Ý£¬ BIT0Ϊ1£¬BIT1Ϊ1ʱ£¬×éÖ¡ÕýÈ·Éí·ÝÊý¾Ý*/
+#define TRS_ENMAC_BACKOFF_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 5) /*Я´øBYTEÊý¾Ý Ôݶ¨*/
+
+#define ENMAC_MCCH_DATA_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 0 )
+#define ENRRC_ENMEL2_REL_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 1)
+#define TRS_ENMEL2_RLC_SDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 2)
+#define TRS_ENMEL2_RLC_PDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 3)
+#define TRS_ENMEL2_MSI_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 4)
+#define EUDBG_EMM_PLAIN_DL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 4)
+#define EUDBG_SEND_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 5)
+#define EUDBG_RECV_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 6)
+#define EUDBG_AM_SEND_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 7)
+#define EUDBG_AM_RECV_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 8)
+#define LTE_P_DLSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 9)
+#define LTE_P_ULSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 10)
+#define LTE_P_MAC_SR_REQ_EV (DWORD)(EUDBG_EVENT_BASE + 11)
+#define LTE_EL2_THROUGHPUT_IND_EV (DWORD)(EUDBG_EVENT_BASE + 12)
+#define LTE_EL2_STATE_IND_EV (DWORD)(EUDBG_EVENT_BASE + 13)
+#define EUDBG_EMM_PLAIN_UL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 14)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå END
+======================================================================== */
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ BEGIN
+======================================================================== */
+
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ END
+======================================================================== */
+/* ========================================================================
+ WÏà¹ØʼþºÅ START
+======================================================================== */
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRC£SCIÏûÏ¢ºÅ¶¨Òå W ÓëTD¹²ÓÃ
+======================================================================== */
+
+/* ========================================================================
+ WRRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_READ_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 0)
+#define WRRC_READ_SYSINFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 1)
+#define WRRC_READ_SYSINFO_REJ_EV (DWORD)(WRRC_EVENT_BASE + 2)
+#define WRRC_STOP_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 3)
+#define WRRC_READ_DYN_SIB_REQ_EV (DWORD)(WRRC_EVENT_BASE + 4)
+#define WRRC_READ_DYN_SIB_CNF_EV (DWORD)(WRRC_EVENT_BASE + 5)
+#define WRRC_SIB_MODIFIED_IND_EV (DWORD)(WRRC_EVENT_BASE + 6)
+#define WRRC_CELLUPDATE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 7)
+#define WRRC_CELL_RESEL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 8)
+#define WRRC_CELL_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 9)
+#define WRRC_REL_CONN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 10)
+#define WRRC_RESUME_CELL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 11)
+#define WRRC_RPLMN_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 12)
+#define WRRC_RESOURE_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 13)
+#define WRRC_RESOURCE_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 14)
+#define WRRC_UPDATE_EPLMN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 15)
+#define WRRC_HIGH_MOBILITY_IND (DWORD)(WRRC_EVENT_BASE + 16)
+#define WRRC_HO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 17)
+#define WRRC_HO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 18)
+#define WRRC_HO_TO_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 19)
+#define WRRC_HO_TO_UTRAN_CNF_EV (DWORD)(WRRC_EVENT_BASE + 20)
+#define WRRC_HO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 21)
+#define WRRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 22)
+#define WRRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 23)
+#define WRRC_CCO_TO_UTRAN_IND_EV (DWORD)(WRRC_EVENT_BASE + 24)
+#define WRRC_CCO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 25)
+#define WRRC_RADIO_LINK_FAIL_IND_EV (DWORD)(WRRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define WRRC_NEIBCELL_CHG_IND_EV (DWORD)(WRRC_EVENT_BASE + 27)
+#define WRRC_FACH_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 28)
+#define WRRC_FACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 29)
+#define WRRC_DRX_CHANGE_IND_EV (DWORD)(WRRC_EVENT_BASE + 30)
+#define WRRC_SEND_BUF_EST_REQ_EV (DWORD)(WRRC_EVENT_BASE + 31)
+#define WRRC_ABORT_RATCHG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 32)
+#define WRRC_CHG_CAMPON_TYPE_EV (DWORD)(WRRC_EVENT_BASE + 33)
+#define WRRC_GET_RF_REQ_EV (DWORD)(WRRC_EVENT_BASE + 34) /*WSIR->WCSR*/
+#define WRRC_GET_RF_CNF_EV (DWORD)(WRRC_EVENT_BASE + 35) /*WCSR->WSIR*/
+#define WRRC_SYSINFO_CONTAINER_IND_EV (DWORD)(WRRC_EVENT_BASE + 36) /*WCSR->WSIR*/
+#define WRRC_ETWS_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 37)
+#define WRRC_ETWS_CFG_END_EV (DWORD)(WRRC_EVENT_BASE + 38)
+#define WRRC_ETWS_CONTINUE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 39)
+#define WRRC_EFACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 40) /*WCMR->WRBC*/
+#define WRRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(WRRC_EVENT_BASE + 41)
+#define WRRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(WRRC_EVENT_BASE + 42)
+/* ========================================================================
+ WRLC - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWRLC_CONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 0)
+#define CWRLC_RELEASE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 1)
+#define CWRLC_SUSPEND_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 2)
+#define CWRLC_RESUME_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 3)
+#define CWRLC_CONTINUE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 4)
+#define UWRLC_DATA_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 5)
+#define CWRLC_CBS_RBCONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 6)
+#define CWRLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 7)
+
+#define CWRLC_SUSPEND_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 0)
+#define UWRLC_DATA_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 1)
+#define CWRLC_STATUS_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 2)
+#define UWRLC_DATA_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 3)
+#define CWRLC_CONFIG_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 4)
+#define CWRLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ WMAC - WRRC/WMAC - WMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWMAC_ASC_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 0)
+#define CWMAC_RACH_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 1)
+#define CWMAC_TFC_CTRL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 2)
+#define CWMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 3)
+#define CWMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 4)
+#define CWMAC_CONTINUE_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 5)
+#define CWMAC_DEL_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 6)
+#define CWMAC_RNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 7)
+#define CWMAC_ERNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 8)
+#define CWMAC_HS_RESET_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 9)
+#define CWMAC_SRB_DELAY_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 10)
+#define CWMAC_TV_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 11)
+#define CWMAC_Q_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 12)
+#define CWMAC_UE_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 13)
+#define CWMAC_TV_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 14)
+#define CWMAC_Q_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 15)
+#define CWMAC_UE_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 16)
+#define CWMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 17)
+#define CWMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 18)
+#define CWMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 19)
+#define CWMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 20)
+#define CWMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 21)
+#define CWMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 22)
+#define CWMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 23)
+#define CWMAC_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 24)
+#define CWMAC_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 25)
+
+#define CWMAC_CONFIG_CHG_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 0)
+#define CWMAC_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 1)
+#define CWMAC_EFACH_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 2)
+#define UWMAC_PCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 3)
+#define UWMAC_BCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 4)
+#define CWMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 5)
+#define CWMAC_TV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 6)
+#define CWMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 7)
+#define CWMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 8)
+#define CWMAC_Q_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 9)
+#define CWMAC_UE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 10)
+#define CWMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 11)
+/* ========================================================================
+ WMAC - UL/DL - WMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+
+/* ========================================================================
+ L1W - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1W_GSM_MEAS_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 0)
+#define L1W_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 1)
+#define L1W_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 2)
+#define L1W_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 3)
+#define L1W_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 4)
+#define L1W_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 5)
+#define L1W_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 6)
+#define L1W_GET_RF_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 7)
+#define L1W_PLMN_END_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 8)
+#define L1W_IRAT_RSRC_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 9)
+#define L1W_CM_CONFIG_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 10)
+#define L1W_CM_FALLBACK_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 11)
+#define L1W_WRRC_LEAVE3G_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 12)
+
+#define L1W_GSM_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 0)
+#define L1W_GET_RF_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 1)
+#define L1W_IRAT_RSRC_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 2)
+#define L1W_LTE_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 3)
+#define L1W_CM_FALLBACK_IND (DWORD)(L1W_WRRC_RSP_EVENT + 4)
+#define L1W_CM_OVERLAP_IND (DWORD)(L1W_WRRC_RSP_EVENT + 5)
+#define L1W_CM_INFO_IND (DWORD)(L1W_WRRC_RSP_EVENT + 6)
+/* ========================================================================
+ PDCP - WRRC ÏûÏ¢ºÅ¶¨Òå(PDCPʼþºÅ¹²ÓÃ)
+======================================================================== */
+
+/* ========================================================================
+ WRLC -WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ L1W - WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WISR_FRAME_IND_EV (DWORD)(WMAC_L1W_EVENT_BASE + 0)
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define UWRLC_PDCP_DATA_IND_EV (DWORD)(PDCP_WRLC_EVENT_BASE + 0)
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_BCH_READ_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 0)
+#define W_P_BCH_OPEN_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 1)
+#define W_P_BCH_RELEASE_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 2)
+
+#define W_P_BCH_IND_EV (DWORD)(WSIR_WPHY_RSP_EVENT + 0)
+/* ========================================================================
+ WCSR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_FREQUENCY_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 0)
+#define W_P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 1)
+#define W_P_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 2)
+#define W_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 3)
+#define W_P_CAMPON_A_CELL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 4)
+#define W_P_REL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 5)
+#define W_P_RESET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 6)
+#define W_P_SET_IRAT_MODE_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 7)
+#define W_P_RPI_SET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 8)
+#define W_P_RPI_CFG_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 9)
+
+
+#define W_P_FREQUENCY_SCAN_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 0)
+#define W_P_CELL_SEARCH_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 1)
+#define W_P_RESET_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 2)
+#define W_P_REL_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ WMCR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 0)
+#define W_P_INTER_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 1)
+#define W_P_FMO_INFO_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 2)
+#define W_P_MEAS_REL_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 3)
+
+#define W_P_INTRA_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 1)
+#define W_P_INTER_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 2)
+#define W_P_SERVCELL_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 3)
+
+
+/* ========================================================================
+ WRBC - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 0)
+#define W_P_DL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 1)
+#define W_P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 2)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 3)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_ABORT_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 4)
+#define W_P_UL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 5)
+#define W_P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 6)
+#define W_P_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 7)
+#define W_P_STOP_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 8)
+#define W_P_ADD_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 9)
+#define W_P_REL_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 10)
+#define W_P_REL_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 11)
+#define W_P_ADD_MODIFY_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 12)
+#define W_P_STOP_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 13)
+#define W_P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 14)
+#define W_P_ADD_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 15)
+#define W_P_REL_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 16)
+#define W_P_HSPA_PLUS_FACH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 17)
+#define W_P_HSPA_PLUS_PCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 18)
+#define W_P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 19)
+#define W_P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 20)
+#define W_P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 21)
+#define W_P_ADD_PRACH_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 22)
+#define W_P_DL_FDPCH_SETUP_MODIFY_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 23)
+
+
+#define W_P_IN_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 0)
+#define W_P_OUT_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 1)
+#define W_P_DPCH_SETUP_MODIFY_CNF (DWORD)(WRBC_WPHY_RSP_EVENT + 2)
+#define W_P_HSSCCH_ORDER_IND (DWORD)(WRBC_WPHY_RSP_EVENT + 3)
+
+
+
+/* ========================================================================
+ WMAC_UL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_RACH_PROCEDURE_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 0)
+#define W_P_RACH_PROCEDURE_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 1)
+#define W_P_EFACH_NO_DATA_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 2)
+#define W_P_ETFC_PARAM_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 3)
+#define W_P_POST_VERFY_FAIL_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 4)
+#define W_P_MAC_DTX_CYCLE_INFO_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 5)
+#define W_P_TFCI_CM_INFO_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 6)
+/* ========================================================================
+ WMAC_DL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 0)
+#define W_P_UE_INTERNAL_MEAS_IND_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 1)
+
+/* ========================================================================
+ L1W - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define W_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G L1W_GSM_INACT_TIME_IND_EV*/
+#define W_P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G L1W_ABORT_GSM_GAP_REQ_EV*/
+#define W_P_COMPRESS_MODE_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 3)
+#define W_P_CARD2_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 4) /*T_zW_P_card2_gap_req*/
+#define W_P_CARD2_GAP_REL_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 5) /*T_zW_P_card2_gap_rel_req*/
+#define W_P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 6) /*T_zW_P_card2_stop_gap_req*/
+#define W_P_CARD1_SUSPEND_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 7) /*T_zW_P_card1_suspend_req*/
+#define W_P_CARD1_RESUME_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 8) /*T_zW_P_card1_resume_req*/
+#define W_P_ZWPCG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 9)
+
+#define W_P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 0)
+#define W_P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 1)
+#define W_P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 2)
+#define W_P_BCH_RELEASE_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 3)
+#define W_P_CAMPON_A_CELL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 4)
+#define W_P_DPCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 5)
+#define W_P_REL_SCCPCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 6)
+#define W_P_STOP_PAGING_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 7)
+#define W_P_STOP_CBS_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 8)
+#define W_P_REL_HSDPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 9)
+#define W_P_REL_HSUPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 10)
+#define W_P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 11)
+#define W_P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 12)
+#define W_P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 13)
+#define W_P_CARD2_GAP_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 14) /*T_zW_P_card2_gap_ind*/
+#define W_P_CARD2_GAP_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 15) /*T_zW_P_card2_gap_rel_cnf*/
+#define W_P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 16) /*T_zW_P_card2_stop_gap_cnf*/
+#define W_P_CARD1_SUSPEND_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 17) /*T_zW_P_card1_suspend_cnf*/
+#define W_P_ZWPCG_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 18)
+
+
+/* ========================================================================
+ L1W ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_CHECK_RF_IND_EV (DWORD)(L1W_EVENT_BASE + 0)
+#define W_P_ACTIVE_IND_EV (DWORD)(L1W_EVENT_BASE + 1)
+#define L1W_MEAS_TIMESTAMP_IND_EV (DWORD)(L1W_EVENT_BASE + 2)
+#define L1W_MEAS_TICKTRACE_IND_EV (DWORD)(L1W_EVENT_BASE + 3)
+
+/* ========================================================================
+ WRRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WSIR_T_BCH_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 0)
+#define WSIR_T_SIB7_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 1)
+#define WSIR_T_VTSIB_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 2)
+#define WSIR_T_R_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 3)
+#define WSIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 4)
+#define WCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 5)
+#define WCSR_T_HYSTX_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 6)
+#define WCSR_T_PROTECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 7)
+#define WCSR_T_NCELL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 8)
+#define WCSR_T_OOS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 9)
+#define WCSR_T_CAMP1S_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define WCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 11)
+#define WCSR_T_REDIRECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 12)
+#define WMCR_T_RESELECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 13)
+#define WMCR_T_PERIOD_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 14)
+#define WMCR_T_TRIGGER_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 15)
+#define WMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 16)
+#define WCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 17)
+#define WCER_T_ETWS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 18)
+#define WCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 19)
+#define WRRC_T300_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 20)
+#define WRRC_T302_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 21)
+#define WRRC_T304_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 22)
+#define WRRC_T305_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 23)
+#define WRRC_T307_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 24)
+#define WRRC_T308_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 25)
+#define WRRC_T309_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 26)
+#define WRRC_T312_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 27)
+#define WRRC_T313_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 28)
+#define WRRC_T314_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 29)
+#define WRRC_T315_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 30)
+#define WRRC_T316_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 31)
+#define WRRC_T319_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 32)
+#define WRRC_T320_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 33)
+#define WMCR_T322_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 34)
+#define WRRC_T323_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 35)
+#define WRRC_T325_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 36)
+#define WRRC_T_WAIT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 37)
+
+/* ========================================================================
+ WPDCP¶¨Ê±Æ÷¶¨Òå(wÎÞÐÂÔö£¬Í¬TD)
+======================================================================== */
+
+
+/* ========================================================================
+ WRLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WRLC_T_DISCARD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 0)
+#define WRLC_T_POLL_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 1)
+#define WRLC_T_POLLPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 2)
+#define WRLC_T_POLLPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 3)
+#define WRLC_T_STATUSPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 4)
+#define WRLC_T_STATUSPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 5)
+#define WRLC_T_RESET_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 6)
+#define WRLC_T_MRW_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ WMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 0)
+#define WMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 1)
+#define WMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 2)
+#define WMAC_T_HSTIMER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 3)
+#define WMAC_T_RESET_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 4)
+#define WMAC_T_BO1_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 5)
+#define WMAC_T_TB_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 6)
+#define WMAC_T_AG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 7)
+#define WMAC_T_RG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 8)
+#define WMAC_T_SING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 9)
+#define WMAC_T_SIG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ L1W¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+/* ========================================================================
+ WSIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_WSIR_DECSIB_EV (DWORD)(WSIR_TEST_EVENT_BASE + 0)
+/* ========================================================================
+ NWRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UWRLC_DATA_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 0)
+#define TEST_UWRLC_DATA_IND_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 1)
+#define TEST_CWRLC_CONFIG_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 2)
+#define TEST_WRLC_ACK_CTRL_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NWMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_WMAC_ACK_CTRL_UTRAN_EV (DWORD)(NWMAC_EVENT_BASE + 0)
+#define TEST_WMAC_HSUPA_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 1)
+#define TEST_WMAC_HSUPA_CFG_EV (DWORD)(NWMAC_EVENT_BASE + 2)
+#define TEST_WMAC_HSUPA_SIINFO_EV (DWORD)(NWMAC_EVENT_BASE + 3)
+#define TEST_WMAC_HSUPA_HEADER_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 4)
+#define TEST_WMAC_NOTIFY_DATA_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 5)
+#define TEST_WMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 6)
+#define TEST_WMAC_CRC_RESULT_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 7)
+#define TEST_UWMAC_DATA_IND_EV (DWORD)(NWMAC_EVENT_BASE + 8)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 0)
+#define WRRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 1)
+#define WRRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 2)
+#define WRRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 3)
+#define WRRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 4)
+#define WRRC_FUNC_READ_SIB_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 5)
+#define WRRC_FUNC_READ_SIB_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 6)
+#define WRRC_FUNC_SER_CELL_IND_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 7)
+#define WRRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 8)
+#define WRRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 9)
+#define WRRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 10)
+#define WRRC_FUNC_START_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 11)
+#define WRRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 12)
+#define WRRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 13)
+#define WRRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 14)
+#define WRRC_FUNC_STOP_SYSINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 15)
+#define WRRC_FUNC_CFG_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 16)
+#define WRRC_FUNC_CFG_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 17)
+#define WRRC_FUNC_REL_FACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 18)
+#define WRRC_FUNC_REL_FACH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 19)
+#define WRRC_FUNC_REL_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 20)
+#define WRRC_FUNC_REL_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 21)
+#define WRRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 22)
+#define WRRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 23)
+#define WRRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 24)
+#define WRRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 25)
+#define WRRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 26)
+#define WRRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 27)
+#define WRRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 28)
+#define WRRC_FUNC_READ_CGIINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 29)
+/* ========================================================================
+ RRCº¯ÊýÖµ¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define RRC_FUNC_GET_TICK_COUNT_EV (DWORD)(RRC_FUNC_TRACE_BASE + 0)
+#define RRC_FUNC_GET_NV_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 1)
+#define RRC_FUNC_GET_UICC_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 2)
+#define RRC_FUNC_GET_PLMN_TYPE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 3)
+#define RRC_FUNC_GET_3A_THREOLD_EV (DWORD)(RRC_FUNC_TRACE_BASE + 4)
+#define RRC_FUNC_GET_PSLOCI_INFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 5)
+#define RRC_FUNC_GET_COUNTC_EV (DWORD)(RRC_FUNC_TRACE_BASE + 6)
+#define RRC_FUNC_GET_MASTER_MODE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 7)
+#define RRC_FUNC_GET_SFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 8)
+#define RRC_FUNC_GET_CFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 9)
+#define RRC_FUNC_GET_AMDLPDU_SIZE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 10)
+#define RRC_FUNC_GET_SIB7_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 11)
+#define RRC_FUNC_GET_VTSIB_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 12)
+/*´òÓ¡µ±Ç°ÊÇ·ñÓÐNASÐÅÁîÕýÔÚ½øÐÐ*/
+#define RRC_FUNC_NAS_SIGNAL_PROC_EXIST_EV (DWORD)(RRC_FUNC_TRACE_BASE + 13)
+#define RRC_FUNC_GET_SRB2_UL_ACT_TIME_EV (DWORD)(RRC_FUNC_TRACE_BASE + 14)
+#define RRC_FUNC_GET_SRB2_MAX_HFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 15)
+//as comÖеÄbarÐÅÏ¢ÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define AS_FUNC_CLEARBARFREQINFO (DWORD)(RRC_FUNC_TRACE_BASE + 50)
+#define AS_FUNC_ADDTDFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 51)
+#define AS_FUNC_DELTDFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 52)
+#define AS_FUNC_CLEARBARCELLINFO (DWORD)(RRC_FUNC_TRACE_BASE + 53)
+#define AS_FUNC_ADDTDCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 54)
+#define AS_FUNC_ADDGSMCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 55)
+#define AS_FUNC_ADDWFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 56)
+#define AS_FUNC_DELWFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 57)
+#define AS_FUNC_ADDWCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 58)
+#define AS_FUNC_GETDEDIPRIOINFO (DWORD)(RRC_FUNC_TRACE_BASE + 59)
+#define AS_FUNC_GETBARINFO (DWORD)(RRC_FUNC_TRACE_BASE + 60)
+#define AS_FUNC_SETFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 61)
+#define AS_FUNC_CLEARFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 62)
+//EUSIRÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define EURRC_EUSIR_SIB1_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 63)
+#define EURRC_EUSIR_SIB2_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 64)
+#define EURRC_EUSIR_SIB5_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 65)
+/* ========================================================================
+WÏà¹ØʼþºÅ END
+======================================================================== */
+#ifdef BTRUNK_SUPPORT
+/* ESM --> TSM */
+#define TSM_ESM_DIALED_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 60)
+#define TSM_ESM_BEARER_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 61)
+
+/* TSM --> ESM */
+#define TSM_ESM_SYN_BEARSTATE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 62)
+
+
+/* TSM --> EMM */
+#define TSM_EST_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 70)
+#define TSM_EMM_DATA_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 71)
+#define TSM_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 72)
+#define TSM_LOCATIONINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 73)
+#define TSM_UMM_DETACHLTE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 74)
+
+
+/* EMM/UMM --> TSM */
+#define TSM_EST_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 80)
+#define TSM_REL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 81)
+#define TSM_EMM_ATTACHSTATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 82)
+#define TSM_EMM_DATA_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 83)
+#define TSM_UMM_PTTINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 84)
+#define TSM_EMM_LOCATIONINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 85)
+
+/*TSM->ASC*/
+#define TSM_ASC_GROUP_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 90)
+#define TSM_ASC_SCANSWITCH_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 91)
+
+/*ASC->TSM*/
+#define TSM_ASC_TGCCH_MSG_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 100)
+#define TSM_ASC_SCANGROUPINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 101)
+#define TSM_ASC_SET_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 102)
+#define TSM_ASC_REL_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 103)
+#define TSM_ASC_REL_GROUP_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 104)
+
+
+/* ========================================================================
+ TSM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TSM_TIMER_BASE (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 300)
+#define TSM_TCMEST_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 1)
+#define TSM_T8001_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 2)
+#define TSM_T8003_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 3)
+#define TSM_T8005_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 4)
+#define TSM_T8006_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 5)
+#define TSM_T8011_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 6)
+#define TSM_T8012_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 7)
+#define TSM_T8014_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 8)
+#define TSM_T8016_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 9)
+#define TSM_T8018_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 10)
+#define TSM_T8020_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 11)
+#define TSM_TPERIOD_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 12)
+#define TSM_TGPS_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 13)
+#define TSM_T8123_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 14)
+#define TSM_TREGRETRY_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 15)
+#define TSM_TCONFIRM_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 16)
+#define TSM_T8125_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 17)
+#define TSM_T8026_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 18)
+/**************************************************PS LTE BTRUNK msg range end********************************************************/
+#endif
+
+/* LPP-ECIDʼþºÅ¶¨Ò壬¹²¼Æ50¸ö */
+
+/* LPP --> ASC */
+#define LPP_ASC_ECID_MEAS_START_EV (DWORD)(LPP_ECID_EVENT_BASE + 0)
+#define LPP_ASC_ECID_MEAS_ABORT_EV (DWORD)(LPP_ASC_ECID_MEAS_START_EV + 1)
+/* LPP --> EURRC */
+#define ASC_EUCSR_ECID_MEAS_START_EV (DWORD)(LPP_ASC_ECID_MEAS_ABORT_EV + 1)
+#define ASC_EUCSR_ECID_MEAS_ABORT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_START_EV + 1)
+/* EURRC --> ASC */
+#define EURRC_ASC_ECID_MEAS_RESULT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_ABORT_EV + 1)
+/* ASC --> LPP */
+#define ASC_LPP_ECID_MEAS_RESULT_EV (DWORD)(EURRC_ASC_ECID_MEAS_RESULT_EV + 1)
+/* SS --> LPP */
+#define SS_LPP_MOLR_START_IND_EV (DWORD)(ASC_LPP_ECID_MEAS_RESULT_EV + 1)
+#define SS_LPP_MOLR_END_IND_EV (DWORD)(SS_LPP_MOLR_START_IND_EV + 1)
+#define SS_LPP_MTLR_START_IND_EV (DWORD)(SS_LPP_MOLR_END_IND_EV + 1)
+#define SS_LPP_MTLR_END_IND_EV (DWORD)(SS_LPP_MTLR_START_IND_EV + 1)
+/* UMM -->LPP */
+#define UMM_LPP_CELLCHG_IND_EV (DWORD)(SS_LPP_MTLR_END_IND_EV + 1)
+/* LPP TIMER EXPIRY EVENT */
+#define LPP_TRIRPT_TIMER_EXP_EV (DWORD)(UMM_LPP_CELLCHG_IND_EV + 1)
+#define LPP_RETRANS_TIMER_EXP_EV (DWORD)(LPP_TRIRPT_TIMER_EXP_EV + 1)
+#define LPP_MSG_TRACE_LOG_EV (DWORD)(LPP_RETRANS_TIMER_EXP_EV + 1)
+
+#endif /* PS_EVENTDEF_H */
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
new file mode 100755
index 0000000..439b293
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/distro/include/nand-config-default.inc
@@ -0,0 +1,10 @@
+PAGESIZE = "0x1000"
+ERASEBLOCK = "0x40000"
+UBI_LEB_SIZE = "253952"
+UBI_IMAGE_SEQ = "1024"
+
+#rootfs ubi参数配置
+#MKUBIFS_ARGS = "-m ${PAGESIZE} -e ${UBI_LEB_SIZE} -c 122 -x zlib -F"
+UBINIZE_ARGS = "-m ${PAGESIZE} -p ${ERASEBLOCK} -s ${PAGESIZE} -Q ${UBI_IMAGE_SEQ}"
+#userdata ubi参数配置
+USERDATA_UBINIZE_ARGS = "${UBINIZE_ARGS}"
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
new file mode 100755
index 0000000..50c2f6e
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/distro/vehicle_dc_ref.conf
@@ -0,0 +1,472 @@
+require conf/distro/include/cpe-base.inc
+
+DISTRO = "vehicle_dc_ref"
+DISTRO_NAME = "zxic Distro vehicle_dc_ref"
+DISTRO_VERSION = "1.0"
+SDK_VENDOR = "-zxic"
+MAINTAINER = "Sanechips Co.，Ltd."
+TARGET_VENDOR = "-zxic"
+
+## OPTEE
+DISTRO_FEATURES += "OPTEE"
+meta_optee += " ${@bb.utils.contains("DISTRO_FEATURES", "OPTEE", " optee-client optee-example ", "", d)} "
+
+PREFERRED_PROVIDER_virtual/kernel = "linux-zxic"
+PREFERRED_VERSION_linux-zxic = "5.10.156"
+PREFERRED_VERSION_busybox = "1.33.1"
+#PREFERRED_VERSION_openssl = "1.1.1l"
+
+TCLIBC = "glibc"
+VIRTUAL-RUNTIME_dev_manager = "busybox-mdev"
+VIRTUAL-RUNTIME_login_manager = "busybox"
+VIRTUAL-RUNTIME_init_manager = "busybox"
+VIRTUAL-RUNTIME_initscripts = "initscripts"
+
+# #
+# # Use systemd for system initialization
+# #
+# VIRTUAL-RUNTIME_init_manager = "systemd"
+# PREFERRED_PROVIDER_udev = "systemd"
+# PREFERRED_PROVIDER_udev-utils = "systemd"
+# DISTRO_FEATURES_BACKFILL_CONSIDERED = "sysvinit"
+# VIRTUAL-RUNTIME_initscripts = ""
+# DEFAULT_DISTRO_FEATURES += "systemd"
+# DISTRO_FEATURES_append = " systemd"
+# DISTRO_FEATURES_remove = "sysvinit"
+
+KERNEL_DEVICETREE = " \
+ zx297520v3-vehicle_dc_ref.dtb \
+"
+# selinux 配置
+DISTRO_FEATURES_append=" selinux "
+
+# 默认是强制模式 enforcing ，调试建议采用宽容模式 permissive
+DEFAULT_ENFORCING = "permissive"
+
+# selinux 策略
+PREFERRED_PROVIDER_virtual/refpolicy ?= "refpolicy-mls"
+
+## adb login
+DISTRO_FEATURES += "adb_login"
+
+# storage type: nand or emmc
+STRORAGE_TYPE = "nand"
+STRORAGE_CONF = "nand-config-4k"
+require conf/distro/include/${STRORAGE_CONF}.inc
+
+#rootfs文件系统类型
+IMAGE_FSTYPES = "squashfs"
+#IMAGE_FSTYPES = "cpio.gz"
+
+
+#rootfs文件系统squashfs参数配置，压缩方式和块大小可以更改
+#squashfs_xz squashfs_zstd
+DISTRO_FEATURES_append = " squashfs_zstd "
+ROOTFS_SQUASHFS_ARGS = "-nopad -noappend -root-owned -b 256k -p '/dev d 755 0 0' -p '/dev/console c 600 0 0 5 1' -processors 1"
+ROOTFS_SQUASHFS_ARGS += " ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "-xattrs", "", d)} "
+ROOTFS_SQUASHFS_ARGS += "${@bb.utils.contains("DISTRO_FEATURES", "squashfs_zstd", " -comp zstd ","", d)}"
+ROOTFS_SQUASHFS_ARGS += "${@bb.utils.contains("DISTRO_FEATURES", "squashfs_xz", " -comp xz -Xpreset 9 -Xe -Xlc 0 -Xlp 2 -Xpb 2 ","", d)}"
+
+#userdata文件系统类型
+USERDATA_FSTYPE = "ubi"
+USERDATA_UBINIZE_CFG = "userdata-ubi-default.cfg"
+OEMDATA_UBINIZE_CFG = "oemdata-ubi-default.cfg"
+
+#userdata ext4 文件系统大小
+USERDATA_EXT4SIZE = "194018"
+
+#
+# system initialization
+#
+DISTRO_FEATURES_append = " sysvinit "
+
+
+#是否支持MMI LCD功能
+#DISTRO_FEATURES += "MMI_LCD"
+#语音控制
+DISTRO_FEATURES += "voice_alsa"
+DISTRO_FEATURES += "use_voice_buffer"
+#DISTRO_FEATURES += "voice_at"
+
+#cap_oem.img
+DISTRO_FEATURES += " oemfs "
+
+#dm-verity for squashfs
+DISTRO_FEATURES += " dm-verity "
+
+
+#CUSTOM_MACRO在各个产品不变的宏放到cpe-base.inc文件，变化的宏放在产品发布文件。
+CUSTOM_MACRO += " -D_GNU_SOURCE "
+
+#产品linux kernel配置，主要区分cpe、v2x、mdl,fpga文件在./meta-zxic/recipes-kernel/linux/files目录下
+#BOOT_CTL:版本的启动方式，normal/recovery，如：linux-5_4-fpga-normal.defconfig
+LINUX_BASE_CONFIG = "linux-5_10-${DISTRO}-${BOOT_CTL}-defconfig"
+
+#型号机linux kernel配置，主要区分mdlxx、mdlyy等型号机,文件在./meta-zxic-custom/recipes-kernel/linux/files目录下
+#BOOT_CTL:版本的启动方式，normal/recovery，如：linux-5_4-mdl-normal.cfg
+LINUX_CONFIG = "linux-5_10-${DISTRO}-${BOOT_CTL}.cfg"
+
+#busybox 配置 文件在./meta-zxic/recipes-core/busybox/files目录下
+BUSYBOX_CONFIG = "${DISTRO}-${BOOT_CTL}-busybox.cfg"
+
+##############################################################################
+# custom macro for lib and app
+CUSTOM_MACRO += " -DAPP_OS_LINUX=1 "
+CUSTOM_MACRO += " -DAPP_OS_TYPE=APP_OS_LINUX "
+
+ENABLE_TESTBENCH_TTY = "no"
+##testbench macro for mode,notty=0 single=1 uchm=2
+CUSTOM_MACRO += " -DTTY_MODE_NO=0 "
+CUSTOM_MACRO += " -DTTY_MODE_SINGLE=1 "
+CUSTOM_MACRO += " -DTTY_MODE_MUX=2 "
+CUSTOM_MACRO += " -DUSE_UBIFS "
+CUSTOM_MACRO += " -DUSE_CAP_SUPPORT "
+CUSTOM_MACRO += " -DFOTA_AB "
+CUSTOM_MACRO += "${@bb.utils.contains('ENABLE_TESTBENCH_TTY', 'yes', '-DTESTBENCH_TTY_MODE=TTY_MODE_SINGLE', '-DTESTBENCH_TTY_MODE=TTY_MODE_NO', d)}"
+CONFIG_MMI_LCD = "${@bb.utils.contains("DISTRO_FEATURES", "MMI_LCD", "yes","no", d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_MMI_LCD', 'yes', '', '-DDISABLE_LCD', d)}"
+USE_ZXIC_WEBUI = "no"
+CONFIG_USE_WEBUI_SSL="yes"
+CONFIG_USE_WEBUI_SECURITY="yes"
+#security compile options
+CFLAGS_append = " -Wl,-z,noexecstack"
+SECURITY_PIE_CFLAGS = " -pie -fPIE"
+SECURITY_STACK_PROTECTOR = " -fstack-protector-all"
+#CUSTOM_MACRO += " -D_USE_CODEC_TI3100 "
+#CUSTOM_MACRO += " -D_USE_CODEC_NAU8810 "
+#CUSTOM_MACRO += " -D_USE_CODEC_TI3104 "
+#CUSTOM_MACRO += " -D_USE_CODEC_MAX9867 "
+CUSTOM_MACRO += " -D_USE_CODEC_ES8311 "
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'voice_alsa', '-D_USE_VOICE_ALSA', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'use_voice_buffer', '-D_USE_VOICE_BUFFER', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'voice_at', '-D_USE_VOICE_AT', '', d)}"
+#CONFIG_VB_TRANSMIT_INTF = "RTP"
+#CONFIG_VB_TRANSMIT_INTF = "USB"
+CONFIG_VB_TRANSMIT_INTF = "NULL"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', '-D_VB_TRANSMIT_INTF_RTP', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'USB', '-D_VB_TRANSMIT_INTF_USB', '', d)}"
+#wifi 配置
+#"mt7916" "" "" ""
+CONFIG_WIFI_MODULE = "mt7916"
+#"apsta" "sta" "ap"
+CONFIG_WIFI_FUNCTION = "ap"
+#wificfg = "${@bb.utils.contains('CONFIG_WIFI_FUNCTION', 'ap', bb.utils.contains('CONFIG_WIFI_MODULE', 'esp8089', 'lib32-hostapd-2.6', '', d), '', d)}"
+
+#BL接口支持("BL")，RIL接口支持("RIL")
+CONFIG_TEL_API_SUPPORT = "RIL"
+
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'BL', '-D_USE_BL', '', d)}"
+
+#RIL AT通道支持RPMSG模式
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', '-DZXIC_ATCHN_RPMSG_MODE', '', d)}"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', '-DUSE_CUSTOM_YK', '', d)}"
+
+DISTRO_FEATURES += " vehicle_dc_ref "
+CUSTOM_MACRO += "${@bb.utils.contains('DISTRO_FEATURES', 'vehicle_dc_ref', '-D_USE_VEHICLE_DC_REF', '', d)}"
+
+#多媒体编解码库支持类型"FFMPEG"，"NONE"
+CONFIG_MSMSVR_CODEC_TYPE = "NONE"
+CUSTOM_MACRO += "${@bb.utils.contains('CONFIG_MSMSVR_CODEC_TYPE', 'FFMPEG', '-D_USE_FFMPEG', '', d)}"
+
+#是否使用新的信号强度命令
+CONFIG_USE_NEW_SIGNAL_STRENGTH = "yes"
+
+# app and libs 配置
+#normal的版本应用及库
+zxic_lib += "\
+ libnvram \
+ libatchn \
+ libsofttimer \
+ libzxic-pbm \
+ libsoftap \
+ libatutils \
+ libsqlite \
+ libscipc \
+ libsctel \
+ libbsp \
+ libtinyalsa\
+ libvoice \
+ libmedia \
+ libdebug-info \
+ libmtd \
+ libsclog \
+ libupi-ab \
+ libbinder \
+ libflags \
+ libmsmsvr \
+ libscrtc \
+ liblynq-uci \
+ liblynq-shm \
+ liblynq-log \
+ libapn \
+ libpal \
+ libvendor-ril \
+ liblynq-call \
+ liblynq-sim \
+ liblynq-network \
+ liblynq-sms \
+ liblynq-data \
+ liblynq-qser-voice \
+ liblynq-qser-sim \
+ liblynq-qser-sms \
+ liblynq-qser-thermal \
+ liblynq-qser-data \
+ liblynq-qser-network \
+ liblynq-qser-gnss \
+ liblynq-qser-fota \
+ liblynq-qser-audio \
+ liblynq-qser-usb \
+ liblynq-qser-wifi \
+ libpoweralarm \
+ liblynq-systime \
+ liblynq-autosuspend \
+ liblynq-qser-autosuspend \
+ liblynq-at-factory \
+ liblynq-gpio \
+ liblynq-irq \
+ liblynq-at-common \
+ liblynq-led \
+ liblynq-adc \
+ liblynq-monitor \
+ "
+
+zxic_lib += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', 'libril', 'libtelsvr', d)}"
+zxic_lib += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', 'librtp', '', d)}"
+#zxic自研应用
+zxic_app_open += "\
+ nvserver cfg-tool adb ab-bootinfo \
+ at-ctl \
+ atchn-test \
+ zxic-mainctrl \
+ zxic-mmi \
+ zxic-script \
+ zxic-hotplug \
+ zxic-ramdump \
+ sntp \
+ zxic-ipv6-slaac \
+ zxic-ipv6-addr-conver \
+ zxic-ndp \
+ rtc-service \
+ dhcp6 \
+ fscheck \
+ nv-rpc-daemon \
+ zlog-agent \
+ cc-demo \
+ sim-demo \
+ sms-demo \
+ socket-demo \
+ i2ctest \
+ spitest \
+ uarttest \
+ bsp-test \
+ zxic-debug \
+ crc \
+ crc-api \
+ voiceipc-mainctrl \
+ voice-demo \
+ fsmonitor \
+ ethtest \
+ sc-at-test \
+ dialtest \
+ sc-nw-mgr-test \
+ sc-cfg-test \
+ sc-softtimer-test \
+ sc-log-test \
+ sc-shm-test \
+ sc-msg-test \
+ adctest \
+ rtc-timer-demo \
+ tsctest \
+ fota-upi-ab \
+ sc-net-test \
+ usbtest \
+ zxic-amt \
+ wlan-proxy \
+ wifi-demo \
+ mnet-whitelist \
+ mnet-whitelist-proxy \
+ flags-tool \
+ msm-svr \
+ phymiitest \
+ player-demo \
+ servicemanager \
+ service \
+ service-test \
+ i2cslavetest \
+ fota-auto-sync \
+ softap-demo \
+ lynq-ril-service \
+ lynq-sdk-ready \
+ lynq-led-demo \
+ lynq-led-sev \
+ uci \
+ gdb \
+ mobiletek-tester-rdit \
+ lynq-qser-voice-demo \
+ lynq-qser-fota-demo \
+ lynq-qser-gnss-demo \
+ lynq-qser-network-demo \
+ poweralarm-demo \
+ lynq-systime-demo \
+ lynq-fota-backup \
+ lynq-qser-sim-demo \
+ lynq-qser-sms-demo \
+ lynq-qser-data-demo \
+ lynq-qser-thermal-demo \
+ lynq-autosuspend \
+ lynq-atcid \
+ lynq-qser-autosuspend-demo \
+ lynq-gpio-demo \
+ lynq-irq-demo \
+ lynq-gnss-update \
+ lynq-audio-demo \
+ lynq-usb-demo \
+ lynq-wifi-demo \
+ lynq-adc-demo \
+ lynq-at-test \
+ lynq-monitor-demo \
+ "
+
+zxic_app_open += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'RIL', 'rild', '', d)}"
+zxic_app_open += "${@bb.utils.contains('CONFIG_TEL_API_SUPPORT', 'BL', 'tel-svr', '', d)}"
+
+#开源应用及库
+meta_app_open += "\
+ dropbear \
+ dbus \
+ e2fsprogs \
+ iptables \
+ curl \
+ dnsmasq \
+ dhcp6 \
+ radvd \
+ iproute2 \
+ busybox-syslog \
+ ethtool \
+ sqlcipher \
+ iperf3 \
+ tcpdump \
+ python3 \
+ openssl-bin \
+ mtd-utils-ubifs \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'dm-verity', 'cryptsetup', '', d)} \
+ ${meta_optee} \
+ tzdata \
+ fdk-aac-master \
+ opencore-amr \
+ vo-amrwbenc \
+ ffmpeg \
+ python3 \
+ lrzsz \
+ "
+meta_app_open += "${@bb.utils.contains('CONFIG_MSMSVR_CODEC_TYPE', 'FFMPEG', 'fdk-aac-master opencore-amr vo-amrwbenc ffmpeg', '', d)}"
+
+#normal的版本应用及库
+zxic_app += "\
+ ${zxic_lib} \
+ ${zxic_app_open} \
+ ${meta_app_open} \
+ "
+
+#zxic自研recovery版本的应用
+zxic_app_open_recovery += "\
+ "
+#recovery版本的开源应用及库
+meta_app_open_recovery += "\
+ "
+#recovery的版本应用及库
+zxic_app_recovery += "\
+ ${zxic_app_open_recovery} \
+ ${meta_app_open_recovery} "
+
+IMAGE_INSTALL +="\
+ ${@bb.utils.contains("BOOT_CTL", "recovery", "${zxic_app_recovery}", "${zxic_app}", d)} \
+ "
+
+PACKAGE_EXCLUDE = "eudev eudev-dev eudev-dbg"
+PACKAGE_EXCLUDE = "eudev"
+
+#DISTRO = "lynq_vehicle_dc"
+#DISTRO_NAME = "lynq distro vehicle_dc"
+RAT_CONFIG_C2K_SUPPORT = "no"
+MTK_MULTI_SIM_SUPPORT = "dsds"
+TARGET_PLATFORM = "T106"
+MTK_LED_SUPPORT = "yes"
+#support lynq_atsvc [hong.liu add for lynq atsvc on 2022.12.1]
+LYNQ_ATSVC_SUPPORT = "yes"
+
+#GPIO_CFG value:"PLATFORM" , "GENVICT" ,"GSW"
+MOBILETEK_GPIO_CFG = "PLATFORM"
+
+#PLL_CFG value:"PLATFORM","GSW"
+MOBILETEK_PLL_CFG = "PLATFORM"
+
+#RTP_CFG value:"PLATFORM","GSW"
+MOBILETEK_RTP_CFG = "PLATFORM"
+
+#MEDIA_CFG value:"PLATFORM","GSW"
+MOBILETEK_MEDIA_CFG = "PLATFORM"
+
+#LOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_LOG_CFG = "PLATFORM"
+
+#FOTA_CFG value:"PLATFORM","GSW"
+MOBILETEK_FOTA_CFG = "PLATFORM"
+
+#RIL_CFG value:"PLATFORM","GSW"
+MOBILETEK_RIL_CFG = "PLATFORM"
+
+#UART_CFG value:"PLATFORM","GSW"
+MOBILETEK_UART_CFG = "PLATFORM"
+
+#USB_CFG value:"PLATFORM","GSW"
+MOBILETEK_USB_CFG = "PLATFORM"
+
+#ndis_CFG value:"PLATFORM","GSW"
+MOBILETEK_NDIS_CFG = "PLATFORM"
+
+#SUSPEND_CFG value:"PLATFORM","GSW"
+MOBILETEK_SUSPEND_CFG = "PLATFORM"
+
+#MNLDLOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_MNLDLOG_CFG = "PLATFORM"
+
+#OPTEE_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPTEE_CFG = "PLATFORM"
+
+#EMMC_CFG value:"PLATFORM","GSW"
+MOBILETEK_EMMC_CFG = "PLATFORM"
+
+#WIFIKERNELCODE_CFG value:"PLATFORM","GSW"
+MOBILETEK_WIFIKERNELCODE_CFG = "PLATFORM"
+
+#SYSTEMD_CFG value:"PLATFORM","GSW"
+MOBILETEK_SYSTEMD_CFG = "PLATFORM"
+
+#GSTREAMER_CFG value:"PLATFORM","GSW"
+MOBILETEK_GSTREAMER_CFG = "PLATFORM"
+
+#BUSYBOX_CFG value:"PLATFORM","GSW"
+MOBILETEK_BUSYBOX_CFG = "PLATFORM"
+
+#OPENSSH_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPENSSH_CFG = "PLATFORM"
+
+#OEMAPP_CFG value:"PLATFORM","GSW"
+MOBILETEK_OEMAPP_CFG = "PLATFORM"
+
+#cz.li@20240221 add for choosing GNSS's chip: "HD","HX"
+MOBILETEK_GNSS_TYPE = "HD"
+
+#MOBILETEK_ADB_LOGIN value:"YES","NO"
+MOBILETEK_ADB_LOGIN = "NO"
+
+#cz.li@20240221 add for MOBILETEK_GNSS_UPDATE_ENABLE value: "yes","no"
+MOBILETEK_GNSS_UPDATE_ENABLE = "yes"
+
+#xf.li@20240716 add for MOBILETEK_LOG_ENCRYPT value: "enable","disable"
+MOBILETEK_LOG_ENCRYPT = "disable"
+
+LYNQ_CONFIG_COMMITID = "e2a3410390ff0ad762462ccb6af8faa5e16dcd61"
+LYNQ_CONFIG_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
+LYNQ_CONFIG_SW_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/lynq_base.conf b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
new file mode 100755
index 0000000..8126a9e
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/conf/lynq_base.conf
@@ -0,0 +1,72 @@
+#DISTRO = "lynq_vehicle_dc"
+#DISTRO_NAME = "lynq distro vehicle_dc"
+RAT_CONFIG_C2K_SUPPORT = "no"
+MTK_MULTI_SIM_SUPPORT = "dsds"
+TARGET_PLATFORM = "T106"
+MTK_LED_SUPPORT = "yes"
+#support lynq_atsvc [hong.liu add for lynq atsvc on 2022.12.1]
+LYNQ_ATSVC_SUPPORT = "yes"
+
+#GPIO_CFG value:"PLATFORM" , "GENVICT" ,"GSW"
+MOBILETEK_GPIO_CFG = "PLATFORM"
+
+#PLL_CFG value:"PLATFORM","GSW"
+MOBILETEK_PLL_CFG = "PLATFORM"
+
+#RTP_CFG value:"PLATFORM","GSW"
+MOBILETEK_RTP_CFG = "PLATFORM"
+
+#MEDIA_CFG value:"PLATFORM","GSW"
+MOBILETEK_MEDIA_CFG = "PLATFORM"
+
+#LOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_LOG_CFG = "PLATFORM"
+
+#FOTA_CFG value:"PLATFORM","GSW"
+MOBILETEK_FOTA_CFG = "PLATFORM"
+
+#RIL_CFG value:"PLATFORM","GSW"
+MOBILETEK_RIL_CFG = "PLATFORM"
+
+#UART_CFG value:"PLATFORM","GSW"
+MOBILETEK_UART_CFG = "PLATFORM"
+
+#USB_CFG value:"PLATFORM","GSW"
+MOBILETEK_USB_CFG = "PLATFORM"
+
+#ndis_CFG value:"PLATFORM","GSW"
+MOBILETEK_NDIS_CFG = "PLATFORM"
+
+#SUSPEND_CFG value:"PLATFORM","GSW"
+MOBILETEK_SUSPEND_CFG = "PLATFORM"
+
+#MNLDLOG_CFG value:"PLATFORM","GSW"
+MOBILETEK_MNLDLOG_CFG = "PLATFORM"
+
+#OPTEE_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPTEE_CFG = "PLATFORM"
+
+#EMMC_CFG value:"PLATFORM","GSW"
+MOBILETEK_EMMC_CFG = "PLATFORM"
+
+#WIFIKERNELCODE_CFG value:"PLATFORM","GSW"
+MOBILETEK_WIFIKERNELCODE_CFG = "PLATFORM"
+
+#SYSTEMD_CFG value:"PLATFORM","GSW"
+MOBILETEK_SYSTEMD_CFG = "PLATFORM"
+
+#GSTREAMER_CFG value:"PLATFORM","GSW"
+MOBILETEK_GSTREAMER_CFG = "PLATFORM"
+
+#BUSYBOX_CFG value:"PLATFORM","GSW"
+MOBILETEK_BUSYBOX_CFG = "PLATFORM"
+
+#OPENSSH_CFG value:"PLATFORM","GSW"
+MOBILETEK_OPENSSH_CFG = "PLATFORM"
+
+#OEMAPP_CFG value:"PLATFORM","GSW"
+MOBILETEK_OEMAPP_CFG = "PLATFORM"
+
+LYNQ_CONFIG_COMMITID = "db2a7e1b3aa519b00153f78dcb223c2eb539f891"
+LYNQ_CONFIG_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
+LYNQ_CONFIG_SW_VERSION = "T106-V2.01.01.02P56U09.AP.17.09_CAP.17.09.01"
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
new file mode 100755
index 0000000..2b48930
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
new file mode 100755
index 0000000..2b48930
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_4Gb-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
new file mode 100755
index 0000000..2b48930
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_ref-normal-busybox.cfg
@@ -0,0 +1,1136 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+CONFIG_INIT=y
+# CONFIG_LINUXRC is not set
+CONFIG_FEATURE_USE_INITTAB=y
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+CONFIG_FEATURE_INIT_SCTTY=y
+CONFIG_FEATURE_INIT_SYSLOG=y
+CONFIG_FEATURE_INIT_QUIET=y
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE="linux"
+CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+CONFIG_MDEV=y
+CONFIG_FEATURE_MDEV_CONF=y
+CONFIG_FEATURE_MDEV_RENAME=y
+CONFIG_FEATURE_MDEV_RENAME_REGEXP=y
+CONFIG_FEATURE_MDEV_EXEC=y
+CONFIG_FEATURE_MDEV_LOAD_FIRMWARE=y
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
new file mode 100755
index 0000000..5d7d82f
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/busybox/busybox/vehicle_dc_systemd-normal-busybox.cfg
@@ -0,0 +1,1137 @@
+#
+# Automatically generated make config: don't edit
+# Busybox version: 1.27.2
+# Mon Sep 25 22:49:52 2017
+#
+CONFIG_HAVE_DOT_CONFIG=y
+
+#
+# Busybox Settings
+#
+CONFIG_DESKTOP=y
+# CONFIG_EXTRA_COMPAT is not set
+# CONFIG_FEDORA_COMPAT is not set
+CONFIG_INCLUDE_SUSv2=y
+# CONFIG_USE_PORTABLE_CODE is not set
+CONFIG_SHOW_USAGE=y
+CONFIG_FEATURE_VERBOSE_USAGE=y
+CONFIG_FEATURE_COMPRESS_USAGE=y
+CONFIG_BUSYBOX=y
+CONFIG_FEATURE_INSTALLER=y
+# CONFIG_INSTALL_NO_USR is not set
+# CONFIG_PAM is not set
+CONFIG_LONG_OPTS=y
+CONFIG_FEATURE_DEVPTS=y
+# CONFIG_FEATURE_CLEAN_UP is not set
+CONFIG_FEATURE_UTMP=y
+CONFIG_FEATURE_WTMP=y
+CONFIG_FEATURE_PIDFILE=y
+CONFIG_PID_FILE_PATH="/var/run"
+CONFIG_FEATURE_SUID=y
+CONFIG_FEATURE_SUID_CONFIG=y
+CONFIG_FEATURE_SUID_CONFIG_QUIET=y
+# CONFIG_SELINUX is not set
+# CONFIG_FEATURE_PREFER_APPLETS is not set
+CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe"
+CONFIG_FEATURE_SYSLOG=y
+# CONFIG_FEATURE_HAVE_RPC is not set
+CONFIG_PLATFORM_LINUX=y
+
+#
+# Build Options
+#
+# CONFIG_PIE is not set
+# CONFIG_NOMMU is not set
+# CONFIG_BUILD_LIBBUSYBOX is not set
+# CONFIG_FEATURE_INDIVIDUAL is not set
+# CONFIG_FEATURE_SHARED_BUSYBOX is not set
+CONFIG_LFS=y
+CONFIG_CROSS_COMPILER_PREFIX=""
+CONFIG_SYSROOT=""
+CONFIG_EXTRA_CFLAGS=""
+CONFIG_EXTRA_LDFLAGS=""
+CONFIG_EXTRA_LDLIBS="-lnvram"
+
+#
+# Installation Options ("make install" behavior)
+#
+CONFIG_INSTALL_APPLET_SYMLINKS=y
+# CONFIG_INSTALL_APPLET_HARDLINKS is not set
+# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set
+# CONFIG_INSTALL_APPLET_DONT is not set
+# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set
+# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set
+# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set
+CONFIG_PREFIX="./_install"
+
+#
+# Debugging Options
+#
+# CONFIG_DEBUG is not set
+# CONFIG_DEBUG_PESSIMIZE is not set
+# CONFIG_DEBUG_SANITIZE is not set
+# CONFIG_UNIT_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_NO_DEBUG_LIB=y
+# CONFIG_DMALLOC is not set
+# CONFIG_EFENCE is not set
+
+#
+# Busybox Library Tuning
+#
+# CONFIG_FEATURE_USE_BSS_TAIL is not set
+CONFIG_FEATURE_RTMINMAX=y
+CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
+# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set
+# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
+CONFIG_PASSWORD_MINLEN=6
+CONFIG_MD5_SMALL=1
+CONFIG_SHA3_SMALL=1
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+CONFIG_FEATURE_EDITING=y
+CONFIG_FEATURE_EDITING_MAX_LEN=1024
+# CONFIG_FEATURE_EDITING_VI is not set
+CONFIG_FEATURE_EDITING_HISTORY=255
+CONFIG_FEATURE_EDITING_SAVEHISTORY=y
+# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set
+CONFIG_FEATURE_REVERSE_SEARCH=y
+CONFIG_FEATURE_TAB_COMPLETION=y
+CONFIG_FEATURE_USERNAME_COMPLETION=y
+CONFIG_FEATURE_EDITING_FANCY_PROMPT=y
+# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set
+# CONFIG_LOCALE_SUPPORT is not set
+CONFIG_UNICODE_SUPPORT=y
+# CONFIG_UNICODE_USING_LOCALE is not set
+# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set
+CONFIG_SUBST_WCHAR=63
+CONFIG_LAST_SUPPORTED_WCHAR=767
+# CONFIG_UNICODE_COMBINING_WCHARS is not set
+# CONFIG_UNICODE_WIDE_WCHARS is not set
+# CONFIG_UNICODE_BIDI_SUPPORT is not set
+# CONFIG_UNICODE_NEUTRAL_TABLE is not set
+# CONFIG_UNICODE_PRESERVE_BROKEN is not set
+CONFIG_FEATURE_NON_POSIX_CP=y
+# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set
+CONFIG_FEATURE_USE_SENDFILE=y
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+CONFIG_MONOTONIC_SYSCALL=y
+CONFIG_IOCTL_HEX2STR_ERROR=y
+CONFIG_FEATURE_HWIB=y
+
+#
+# Applets
+#
+
+#
+# Archival Utilities
+#
+CONFIG_FEATURE_SEAMLESS_XZ=y
+CONFIG_FEATURE_SEAMLESS_LZMA=y
+CONFIG_FEATURE_SEAMLESS_BZ2=y
+CONFIG_FEATURE_SEAMLESS_GZ=y
+# CONFIG_FEATURE_SEAMLESS_Z is not set
+# CONFIG_AR is not set
+# CONFIG_FEATURE_AR_LONG_FILENAMES is not set
+# CONFIG_FEATURE_AR_CREATE is not set
+# CONFIG_UNCOMPRESS is not set
+CONFIG_GUNZIP=y
+CONFIG_ZCAT=y
+CONFIG_FEATURE_GUNZIP_LONG_OPTIONS=y
+CONFIG_BUNZIP2=y
+CONFIG_BZCAT=y
+CONFIG_UNLZMA=y
+CONFIG_LZCAT=y
+CONFIG_LZMA=y
+# CONFIG_FEATURE_LZMA_FAST is not set
+CONFIG_UNXZ=y
+CONFIG_XZCAT=y
+CONFIG_XZ=y
+CONFIG_BZIP2=y
+CONFIG_FEATURE_BZIP2_DECOMPRESS=y
+CONFIG_CPIO=y
+CONFIG_FEATURE_CPIO_O=y
+CONFIG_FEATURE_CPIO_P=y
+CONFIG_DPKG=y
+CONFIG_DPKG_DEB=y
+CONFIG_GZIP=y
+CONFIG_FEATURE_GZIP_LONG_OPTIONS=y
+CONFIG_GZIP_FAST=0
+# CONFIG_FEATURE_GZIP_LEVELS is not set
+CONFIG_FEATURE_GZIP_DECOMPRESS=y
+CONFIG_LZOP=y
+# CONFIG_UNLZOP is not set
+# CONFIG_LZOPCAT is not set
+# CONFIG_LZOP_COMPR_HIGH is not set
+CONFIG_RPM=y
+CONFIG_RPM2CPIO=y
+CONFIG_TAR=y
+CONFIG_FEATURE_TAR_LONG_OPTIONS=y
+CONFIG_FEATURE_TAR_CREATE=y
+CONFIG_FEATURE_TAR_AUTODETECT=y
+CONFIG_FEATURE_TAR_FROM=y
+CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY=y
+CONFIG_FEATURE_TAR_GNU_EXTENSIONS=y
+CONFIG_FEATURE_TAR_TO_COMMAND=y
+CONFIG_FEATURE_TAR_UNAME_GNAME=y
+CONFIG_FEATURE_TAR_NOPRESERVE_TIME=y
+# CONFIG_FEATURE_TAR_SELINUX is not set
+CONFIG_UNZIP=y
+CONFIG_FEATURE_UNZIP_CDF=y
+CONFIG_FEATURE_UNZIP_BZIP2=y
+CONFIG_FEATURE_UNZIP_LZMA=y
+CONFIG_FEATURE_UNZIP_XZ=y
+
+#
+# Coreutils
+#
+CONFIG_BASENAME=y
+CONFIG_CAT=y
+CONFIG_FEATURE_CATV=y
+CONFIG_CHGRP=y
+CONFIG_CHMOD=y
+CONFIG_CHOWN=y
+CONFIG_FEATURE_CHOWN_LONG_OPTIONS=y
+CONFIG_CHROOT=y
+CONFIG_CKSUM=y
+CONFIG_COMM=y
+CONFIG_CP=y
+CONFIG_FEATURE_CP_LONG_OPTIONS=y
+CONFIG_CUT=y
+CONFIG_DATE=y
+CONFIG_FEATURE_DATE_ISOFMT=y
+# CONFIG_FEATURE_DATE_NANO is not set
+CONFIG_FEATURE_DATE_COMPAT=y
+CONFIG_DD=y
+CONFIG_FEATURE_DD_SIGNAL_HANDLING=y
+CONFIG_FEATURE_DD_THIRD_STATUS_LINE=y
+CONFIG_FEATURE_DD_IBS_OBS=y
+CONFIG_FEATURE_DD_STATUS=y
+CONFIG_DF=y
+CONFIG_FEATURE_DF_FANCY=y
+CONFIG_DIRNAME=y
+CONFIG_DOS2UNIX=y
+CONFIG_UNIX2DOS=y
+CONFIG_DU=y
+CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y
+CONFIG_ECHO=y
+CONFIG_FEATURE_FANCY_ECHO=y
+CONFIG_ENV=y
+CONFIG_FEATURE_ENV_LONG_OPTIONS=y
+CONFIG_EXPAND=y
+CONFIG_FEATURE_EXPAND_LONG_OPTIONS=y
+CONFIG_UNEXPAND=y
+CONFIG_FEATURE_UNEXPAND_LONG_OPTIONS=y
+CONFIG_EXPR=y
+CONFIG_EXPR_MATH_SUPPORT_64=y
+CONFIG_FACTOR=y
+CONFIG_FALSE=y
+CONFIG_FOLD=y
+CONFIG_FSYNC=y
+CONFIG_HEAD=y
+CONFIG_FEATURE_FANCY_HEAD=y
+CONFIG_HOSTID=y
+CONFIG_ID=y
+CONFIG_GROUPS=y
+CONFIG_INSTALL=y
+CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y
+CONFIG_LINK=y
+CONFIG_LN=y
+CONFIG_LOGNAME=y
+CONFIG_LS=y
+CONFIG_FEATURE_LS_FILETYPES=y
+CONFIG_FEATURE_LS_FOLLOWLINKS=y
+CONFIG_FEATURE_LS_RECURSIVE=y
+CONFIG_FEATURE_LS_WIDTH=y
+CONFIG_FEATURE_LS_SORTFILES=y
+CONFIG_FEATURE_LS_TIMESTAMPS=y
+CONFIG_FEATURE_LS_USERNAME=y
+# CONFIG_FEATURE_LS_COLOR is not set
+# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set
+CONFIG_MD5SUM=y
+CONFIG_SHA1SUM=y
+CONFIG_SHA256SUM=y
+CONFIG_SHA512SUM=y
+CONFIG_SHA3SUM=y
+
+#
+# Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum
+#
+CONFIG_FEATURE_MD5_SHA1_SUM_CHECK=y
+CONFIG_MKDIR=y
+CONFIG_FEATURE_MKDIR_LONG_OPTIONS=y
+CONFIG_MKFIFO=y
+CONFIG_MKNOD=y
+CONFIG_MKTEMP=y
+CONFIG_MV=y
+CONFIG_FEATURE_MV_LONG_OPTIONS=y
+CONFIG_NICE=y
+CONFIG_NL=y
+CONFIG_NOHUP=y
+CONFIG_NPROC=y
+CONFIG_OD=y
+CONFIG_PASTE=y
+CONFIG_PRINTENV=y
+CONFIG_PRINTF=y
+CONFIG_PWD=y
+CONFIG_READLINK=y
+CONFIG_FEATURE_READLINK_FOLLOW=y
+CONFIG_REALPATH=y
+CONFIG_RM=y
+CONFIG_RMDIR=y
+CONFIG_FEATURE_RMDIR_LONG_OPTIONS=y
+CONFIG_SEQ=y
+CONFIG_SHRED=y
+CONFIG_SHUF=y
+CONFIG_SLEEP=y
+CONFIG_FEATURE_FANCY_SLEEP=y
+CONFIG_FEATURE_FLOAT_SLEEP=y
+CONFIG_SORT=y
+CONFIG_FEATURE_SORT_BIG=y
+CONFIG_SPLIT=y
+CONFIG_FEATURE_SPLIT_FANCY=y
+CONFIG_STAT=y
+CONFIG_FEATURE_STAT_FORMAT=y
+CONFIG_FEATURE_STAT_FILESYSTEM=y
+CONFIG_STTY=y
+CONFIG_SUM=y
+CONFIG_SYNC=y
+CONFIG_FEATURE_SYNC_FANCY=y
+CONFIG_TAC=y
+CONFIG_TAIL=y
+CONFIG_FEATURE_FANCY_TAIL=y
+CONFIG_TEE=y
+CONFIG_FEATURE_TEE_USE_BLOCK_IO=y
+CONFIG_TEST=y
+CONFIG_TEST1=y
+CONFIG_TEST2=y
+CONFIG_FEATURE_TEST_64=y
+CONFIG_TIMEOUT=y
+CONFIG_TOUCH=y
+CONFIG_FEATURE_TOUCH_NODEREF=y
+CONFIG_FEATURE_TOUCH_SUSV3=y
+CONFIG_TR=y
+CONFIG_FEATURE_TR_CLASSES=y
+CONFIG_FEATURE_TR_EQUIV=y
+CONFIG_TRUE=y
+CONFIG_TRUNCATE=y
+CONFIG_TTY=y
+CONFIG_UNAME=y
+CONFIG_UNAME_OSNAME="GNU/Linux"
+CONFIG_UNIQ=y
+CONFIG_UNLINK=y
+CONFIG_USLEEP=y
+CONFIG_UUDECODE=y
+CONFIG_BASE64=y
+CONFIG_UUENCODE=y
+CONFIG_WC=y
+CONFIG_FEATURE_WC_LARGE=y
+CONFIG_WHO=y
+CONFIG_W=y
+CONFIG_USERS=y
+CONFIG_WHOAMI=y
+CONFIG_YES=y
+
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
+#
+# Console Utilities
+#
+CONFIG_CHVT=y
+CONFIG_CLEAR=y
+CONFIG_DEALLOCVT=y
+CONFIG_DUMPKMAP=y
+CONFIG_FGCONSOLE=y
+CONFIG_KBD_MODE=y
+CONFIG_LOADFONT=y
+CONFIG_SETFONT=y
+CONFIG_FEATURE_SETFONT_TEXTUAL_MAP=y
+CONFIG_DEFAULT_SETFONT_DIR=""
+
+#
+# Common options for loadfont and setfont
+#
+CONFIG_FEATURE_LOADFONT_PSF2=y
+CONFIG_FEATURE_LOADFONT_RAW=y
+CONFIG_LOADKMAP=y
+CONFIG_OPENVT=y
+CONFIG_RESET=y
+CONFIG_RESIZE=y
+CONFIG_FEATURE_RESIZE_PRINT=y
+CONFIG_SETCONSOLE=y
+CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS=y
+CONFIG_SETKEYCODES=y
+CONFIG_SETLOGCONS=y
+CONFIG_SHOWKEY=y
+
+#
+# Debian Utilities
+#
+CONFIG_PIPE_PROGRESS=y
+CONFIG_RUN_PARTS=y
+CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS=y
+CONFIG_FEATURE_RUN_PARTS_FANCY=y
+# CONFIG_START_STOP_DAEMON is not set
+CONFIG_WHICH=y
+
+#
+# Editors
+#
+CONFIG_AWK=y
+CONFIG_FEATURE_AWK_LIBM=y
+CONFIG_FEATURE_AWK_GNU_EXTENSIONS=y
+CONFIG_CMP=y
+CONFIG_DIFF=y
+CONFIG_FEATURE_DIFF_LONG_OPTIONS=y
+CONFIG_FEATURE_DIFF_DIR=y
+CONFIG_ED=y
+CONFIG_PATCH=y
+CONFIG_SED=y
+CONFIG_VI=y
+CONFIG_FEATURE_VI_MAX_LEN=4096
+# CONFIG_FEATURE_VI_8BIT is not set
+CONFIG_FEATURE_VI_COLON=y
+CONFIG_FEATURE_VI_YANKMARK=y
+CONFIG_FEATURE_VI_SEARCH=y
+# CONFIG_FEATURE_VI_REGEX_SEARCH is not set
+CONFIG_FEATURE_VI_USE_SIGNALS=y
+CONFIG_FEATURE_VI_DOT_CMD=y
+CONFIG_FEATURE_VI_READONLY=y
+CONFIG_FEATURE_VI_SETOPTS=y
+CONFIG_FEATURE_VI_SET=y
+CONFIG_FEATURE_VI_WIN_RESIZE=y
+CONFIG_FEATURE_VI_ASK_TERMINAL=y
+CONFIG_FEATURE_VI_UNDO=y
+CONFIG_FEATURE_VI_UNDO_QUEUE=y
+CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
+CONFIG_FEATURE_ALLOW_EXEC=y
+
+#
+# Finding Utilities
+#
+CONFIG_FIND=y
+CONFIG_FEATURE_FIND_PRINT0=y
+CONFIG_FEATURE_FIND_MTIME=y
+CONFIG_FEATURE_FIND_MMIN=y
+CONFIG_FEATURE_FIND_PERM=y
+CONFIG_FEATURE_FIND_TYPE=y
+CONFIG_FEATURE_FIND_XDEV=y
+CONFIG_FEATURE_FIND_MAXDEPTH=y
+CONFIG_FEATURE_FIND_NEWER=y
+CONFIG_FEATURE_FIND_INUM=y
+CONFIG_FEATURE_FIND_EXEC=y
+CONFIG_FEATURE_FIND_EXEC_PLUS=y
+CONFIG_FEATURE_FIND_USER=y
+CONFIG_FEATURE_FIND_GROUP=y
+CONFIG_FEATURE_FIND_NOT=y
+CONFIG_FEATURE_FIND_DEPTH=y
+CONFIG_FEATURE_FIND_PAREN=y
+CONFIG_FEATURE_FIND_SIZE=y
+CONFIG_FEATURE_FIND_PRUNE=y
+CONFIG_FEATURE_FIND_DELETE=y
+CONFIG_FEATURE_FIND_PATH=y
+CONFIG_FEATURE_FIND_REGEX=y
+# CONFIG_FEATURE_FIND_CONTEXT is not set
+CONFIG_FEATURE_FIND_LINKS=y
+CONFIG_GREP=y
+CONFIG_EGREP=y
+CONFIG_FGREP=y
+CONFIG_FEATURE_GREP_CONTEXT=y
+CONFIG_XARGS=y
+CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION=y
+CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y
+CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y
+CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y
+CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y
+
+#
+# Init Utilities
+#
+CONFIG_BOOTCHARTD=y
+CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER=y
+CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE=y
+CONFIG_HALT=y
+CONFIG_POWEROFF=y
+CONFIG_REBOOT=y
+# CONFIG_FEATURE_CALL_TELINIT is not set
+CONFIG_TELINIT_PATH=""
+# CONFIG_INIT is not set
+# CONFIG_LINUXRC is not set
+# CONFIG_FEATURE_USE_INITTAB is not set
+# CONFIG_FEATURE_KILL_REMOVED is not set
+CONFIG_FEATURE_KILL_DELAY=0
+# CONFIG_FEATURE_INIT_SCTTY is not set
+# CONFIG_FEATURE_INIT_SYSLOG is not set
+# CONFIG_FEATURE_INIT_QUIET is not set
+# CONFIG_FEATURE_INIT_COREDUMPS is not set
+CONFIG_INIT_TERMINAL_TYPE=""
+# CONFIG_FEATURE_INIT_MODIFY_CMDLINE is not set
+
+#
+# Login/Password Management Utilities
+#
+CONFIG_FEATURE_SHADOWPASSWDS=y
+CONFIG_USE_BB_PWD_GRP=y
+CONFIG_USE_BB_SHADOW=y
+CONFIG_USE_BB_CRYPT=y
+CONFIG_USE_BB_CRYPT_SHA=y
+CONFIG_ADD_SHELL=y
+CONFIG_REMOVE_SHELL=y
+CONFIG_ADDGROUP=y
+CONFIG_FEATURE_ADDGROUP_LONG_OPTIONS=y
+CONFIG_FEATURE_ADDUSER_TO_GROUP=y
+CONFIG_ADDUSER=y
+CONFIG_FEATURE_ADDUSER_LONG_OPTIONS=y
+# CONFIG_FEATURE_CHECK_NAMES is not set
+CONFIG_LAST_ID=60000
+CONFIG_FIRST_SYSTEM_ID=100
+CONFIG_LAST_SYSTEM_ID=999
+CONFIG_CHPASSWD=y
+CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="des"
+CONFIG_CRYPTPW=y
+CONFIG_MKPASSWD=y
+CONFIG_DELUSER=y
+CONFIG_DELGROUP=y
+CONFIG_FEATURE_DEL_USER_FROM_GROUP=y
+CONFIG_GETTY=y
+CONFIG_LOGIN=y
+# CONFIG_LOGIN_SESSION_AS_CHILD is not set
+CONFIG_LOGIN_SCRIPTS=y
+CONFIG_FEATURE_NOLOGIN=y
+CONFIG_FEATURE_SECURETTY=y
+CONFIG_PASSWD=y
+CONFIG_FEATURE_PASSWD_WEAK_CHECK=y
+CONFIG_SU=y
+CONFIG_FEATURE_SU_SYSLOG=y
+CONFIG_FEATURE_SU_CHECKS_SHELLS=y
+# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set
+CONFIG_SULOGIN=y
+CONFIG_VLOCK=y
+
+#
+# Linux Ext2 FS Progs
+#
+CONFIG_CHATTR=y
+CONFIG_FSCK=y
+CONFIG_LSATTR=y
+# CONFIG_TUNE2FS is not set
+
+#
+# Linux Module Utilities
+#
+CONFIG_MODPROBE_SMALL=y
+CONFIG_DEPMOD=y
+CONFIG_INSMOD=y
+CONFIG_LSMOD=y
+# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set
+CONFIG_MODINFO=y
+CONFIG_MODPROBE=y
+# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set
+CONFIG_RMMOD=y
+
+#
+# Options common to multiple modutils
+#
+CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS=y
+CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED=y
+# CONFIG_FEATURE_2_4_MODULES is not set
+# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set
+# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set
+# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set
+# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set
+# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set
+# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set
+# CONFIG_FEATURE_MODUTILS_ALIAS is not set
+# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set
+CONFIG_DEFAULT_MODULES_DIR="/lib/modules"
+CONFIG_DEFAULT_DEPMOD_FILE="modules.dep"
+
+#
+# Linux System Utilities
+#
+CONFIG_ACPID=y
+CONFIG_FEATURE_ACPID_COMPAT=y
+CONFIG_BLKDISCARD=y
+CONFIG_BLKID=y
+# CONFIG_FEATURE_BLKID_TYPE is not set
+CONFIG_BLOCKDEV=y
+CONFIG_CAL=y
+CONFIG_CHRT=y
+CONFIG_DMESG=y
+CONFIG_FEATURE_DMESG_PRETTY=y
+CONFIG_EJECT=y
+CONFIG_FEATURE_EJECT_SCSI=y
+CONFIG_FALLOCATE=y
+CONFIG_FATATTR=y
+CONFIG_FBSET=y
+CONFIG_FEATURE_FBSET_FANCY=y
+CONFIG_FEATURE_FBSET_READMODE=y
+CONFIG_FDFORMAT=y
+CONFIG_FDISK=y
+# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set
+CONFIG_FEATURE_FDISK_WRITABLE=y
+# CONFIG_FEATURE_AIX_LABEL is not set
+# CONFIG_FEATURE_SGI_LABEL is not set
+# CONFIG_FEATURE_SUN_LABEL is not set
+# CONFIG_FEATURE_OSF_LABEL is not set
+CONFIG_FEATURE_GPT_LABEL=y
+CONFIG_FEATURE_FDISK_ADVANCED=y
+CONFIG_FINDFS=y
+CONFIG_FLOCK=y
+CONFIG_FDFLUSH=y
+CONFIG_FREERAMDISK=y
+CONFIG_FSCK_MINIX=y
+CONFIG_FSFREEZE=y
+CONFIG_FSTRIM=y
+CONFIG_GETOPT=y
+CONFIG_FEATURE_GETOPT_LONG=y
+CONFIG_HEXDUMP=y
+CONFIG_FEATURE_HEXDUMP_REVERSE=y
+CONFIG_HD=y
+CONFIG_XXD=y
+CONFIG_HWCLOCK=y
+CONFIG_FEATURE_HWCLOCK_LONG_OPTIONS=y
+# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set
+CONFIG_IONICE=y
+CONFIG_IPCRM=y
+CONFIG_IPCS=y
+CONFIG_LAST=y
+CONFIG_FEATURE_LAST_FANCY=y
+CONFIG_LOSETUP=y
+CONFIG_LSPCI=y
+CONFIG_LSUSB=y
+# CONFIG_MDEV is not set
+# CONFIG_FEATURE_MDEV_CONF is not set
+# CONFIG_FEATURE_MDEV_RENAME is not set
+# CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set
+# CONFIG_FEATURE_MDEV_EXEC is not set
+# CONFIG_FEATURE_MDEV_LOAD_FIRMWARE is not set
+# CONFIG_FEATURE_MDEV_DAEMON is not set
+CONFIG_MESG=y
+CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP=y
+CONFIG_MKE2FS=y
+CONFIG_MKFS_EXT2=y
+CONFIG_MKFS_MINIX=y
+CONFIG_FEATURE_MINIX2=y
+# CONFIG_MKFS_REISER is not set
+CONFIG_MKDOSFS=y
+CONFIG_MKFS_VFAT=y
+CONFIG_MKSWAP=y
+CONFIG_FEATURE_MKSWAP_UUID=y
+CONFIG_MORE=y
+CONFIG_MOUNT=y
+CONFIG_FEATURE_MOUNT_FAKE=y
+CONFIG_FEATURE_MOUNT_VERBOSE=y
+# CONFIG_FEATURE_MOUNT_HELPERS is not set
+CONFIG_FEATURE_MOUNT_LABEL=y
+# CONFIG_FEATURE_MOUNT_NFS is not set
+CONFIG_FEATURE_MOUNT_CIFS=y
+CONFIG_FEATURE_MOUNT_FLAGS=y
+CONFIG_FEATURE_MOUNT_FSTAB=y
+CONFIG_FEATURE_MOUNT_OTHERTAB=y
+CONFIG_MOUNTPOINT=y
+CONFIG_NSENTER=y
+CONFIG_FEATURE_NSENTER_LONG_OPTS=y
+CONFIG_PIVOT_ROOT=y
+CONFIG_RDATE=y
+CONFIG_RDEV=y
+CONFIG_READPROFILE=y
+CONFIG_RENICE=y
+CONFIG_REV=y
+CONFIG_RTCWAKE=y
+CONFIG_SCRIPT=y
+CONFIG_SCRIPTREPLAY=y
+CONFIG_SETARCH=y
+CONFIG_LINUX32=y
+CONFIG_LINUX64=y
+CONFIG_SETPRIV=y
+CONFIG_SETSID=y
+CONFIG_SWAPON=y
+CONFIG_FEATURE_SWAPON_DISCARD=y
+CONFIG_FEATURE_SWAPON_PRI=y
+CONFIG_SWAPOFF=y
+CONFIG_SWITCH_ROOT=y
+CONFIG_TASKSET=y
+CONFIG_FEATURE_TASKSET_FANCY=y
+CONFIG_UEVENT=y
+CONFIG_UMOUNT=y
+CONFIG_FEATURE_UMOUNT_ALL=y
+CONFIG_UNSHARE=y
+CONFIG_WALL=y
+
+#
+# Common options for mount/umount
+#
+CONFIG_FEATURE_MOUNT_LOOP=y
+CONFIG_FEATURE_MOUNT_LOOP_CREATE=y
+# CONFIG_FEATURE_MTAB_SUPPORT is not set
+CONFIG_VOLUMEID=y
+
+#
+# Filesystem/Volume identification
+#
+CONFIG_FEATURE_VOLUMEID_BCACHE=y
+CONFIG_FEATURE_VOLUMEID_BTRFS=y
+CONFIG_FEATURE_VOLUMEID_CRAMFS=y
+CONFIG_FEATURE_VOLUMEID_EXFAT=y
+CONFIG_FEATURE_VOLUMEID_EXT=y
+CONFIG_FEATURE_VOLUMEID_F2FS=y
+CONFIG_FEATURE_VOLUMEID_FAT=y
+CONFIG_FEATURE_VOLUMEID_HFS=y
+CONFIG_FEATURE_VOLUMEID_ISO9660=y
+CONFIG_FEATURE_VOLUMEID_JFS=y
+CONFIG_FEATURE_VOLUMEID_LINUXRAID=y
+CONFIG_FEATURE_VOLUMEID_LINUXSWAP=y
+CONFIG_FEATURE_VOLUMEID_LUKS=y
+CONFIG_FEATURE_VOLUMEID_NILFS=y
+CONFIG_FEATURE_VOLUMEID_NTFS=y
+CONFIG_FEATURE_VOLUMEID_OCFS2=y
+CONFIG_FEATURE_VOLUMEID_REISERFS=y
+CONFIG_FEATURE_VOLUMEID_ROMFS=y
+# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set
+CONFIG_FEATURE_VOLUMEID_SYSV=y
+CONFIG_FEATURE_VOLUMEID_UBIFS=y
+CONFIG_FEATURE_VOLUMEID_UDF=y
+CONFIG_FEATURE_VOLUMEID_XFS=y
+
+#
+# Miscellaneous Utilities
+#
+CONFIG_ADJTIMEX=y
+# CONFIG_BBCONFIG is not set
+# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
+CONFIG_BEEP=y
+CONFIG_FEATURE_BEEP_FREQ=4000
+CONFIG_FEATURE_BEEP_LENGTH_MS=30
+CONFIG_CHAT=y
+CONFIG_FEATURE_CHAT_NOFAIL=y
+# CONFIG_FEATURE_CHAT_TTY_HIFI is not set
+CONFIG_FEATURE_CHAT_IMPLICIT_CR=y
+CONFIG_FEATURE_CHAT_SWALLOW_OPTS=y
+CONFIG_FEATURE_CHAT_SEND_ESCAPES=y
+CONFIG_FEATURE_CHAT_VAR_ABORT_LEN=y
+CONFIG_FEATURE_CHAT_CLR_ABORT=y
+CONFIG_CONSPY=y
+CONFIG_CROND=y
+CONFIG_FEATURE_CROND_D=y
+CONFIG_FEATURE_CROND_CALL_SENDMAIL=y
+CONFIG_FEATURE_CROND_DIR="/var/spool/cron"
+CONFIG_CRONTAB=y
+CONFIG_DC=y
+CONFIG_FEATURE_DC_LIBM=y
+# CONFIG_DEVFSD is not set
+# CONFIG_DEVFSD_MODLOAD is not set
+# CONFIG_DEVFSD_FG_NP is not set
+# CONFIG_DEVFSD_VERBOSE is not set
+# CONFIG_FEATURE_DEVFS is not set
+CONFIG_DEVMEM=y
+CONFIG_FBSPLASH=y
+# CONFIG_FLASH_ERASEALL is not set
+# CONFIG_FLASH_LOCK is not set
+# CONFIG_FLASH_UNLOCK is not set
+# CONFIG_FLASHCP is not set
+CONFIG_HDPARM=y
+CONFIG_FEATURE_HDPARM_GET_IDENTITY=y
+CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET=y
+CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF=y
+CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA=y
+CONFIG_I2CGET=y
+CONFIG_I2CSET=y
+CONFIG_I2CDUMP=y
+CONFIG_I2CDETECT=y
+# CONFIG_INOTIFYD is not set
+CONFIG_LESS=y
+CONFIG_FEATURE_LESS_MAXLINES=9999999
+CONFIG_FEATURE_LESS_BRACKETS=y
+CONFIG_FEATURE_LESS_FLAGS=y
+CONFIG_FEATURE_LESS_TRUNCATE=y
+CONFIG_FEATURE_LESS_MARKS=y
+CONFIG_FEATURE_LESS_REGEXP=y
+CONFIG_FEATURE_LESS_WINCH=y
+CONFIG_FEATURE_LESS_ASK_TERMINAL=y
+CONFIG_FEATURE_LESS_DASHCMD=y
+CONFIG_FEATURE_LESS_LINENUMS=y
+CONFIG_LSSCSI=y
+CONFIG_MAKEDEVS=y
+# CONFIG_FEATURE_MAKEDEVS_LEAF is not set
+CONFIG_FEATURE_MAKEDEVS_TABLE=y
+CONFIG_MAN=y
+CONFIG_MICROCOM=y
+CONFIG_MT=y
+CONFIG_NANDWRITE=y
+CONFIG_NANDDUMP=y
+CONFIG_PARTPROBE=y
+CONFIG_RAIDAUTORUN=y
+CONFIG_READAHEAD=y
+# CONFIG_RFKILL is not set
+CONFIG_RUNLEVEL=y
+CONFIG_RX=y
+CONFIG_SETSERIAL=y
+CONFIG_STRINGS=y
+CONFIG_TIME=y
+CONFIG_TTYSIZE=y
+# CONFIG_UBIATTACH is not set
+# CONFIG_UBIDETACH is not set
+# CONFIG_UBIMKVOL is not set
+# CONFIG_UBIRMVOL is not set
+# CONFIG_UBIRSVOL is not set
+# CONFIG_UBIUPDATEVOL is not set
+# CONFIG_UBIRENAME is not set
+CONFIG_VOLNAME=y
+CONFIG_WATCHDOG=y
+
+#
+# Networking Utilities
+#
+CONFIG_FEATURE_IPV6=y
+# CONFIG_FEATURE_UNIX_LOCAL is not set
+CONFIG_FEATURE_PREFER_IPV4_ADDRESS=y
+# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
+CONFIG_ARP=y
+CONFIG_ARPING=y
+CONFIG_BRCTL=y
+CONFIG_FEATURE_BRCTL_FANCY=y
+CONFIG_FEATURE_BRCTL_SHOW=y
+CONFIG_DNSD=y
+CONFIG_ETHER_WAKE=y
+CONFIG_FTPD=y
+CONFIG_FEATURE_FTPD_WRITE=y
+CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST=y
+CONFIG_FEATURE_FTPD_AUTHENTICATION=y
+CONFIG_FTPGET=y
+CONFIG_FTPPUT=y
+CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS=y
+CONFIG_HOSTNAME=y
+CONFIG_DNSDOMAINNAME=y
+CONFIG_HTTPD=y
+CONFIG_FEATURE_HTTPD_RANGES=y
+CONFIG_FEATURE_HTTPD_SETUID=y
+CONFIG_FEATURE_HTTPD_BASIC_AUTH=y
+CONFIG_FEATURE_HTTPD_AUTH_MD5=y
+CONFIG_FEATURE_HTTPD_CGI=y
+CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR=y
+CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV=y
+CONFIG_FEATURE_HTTPD_ENCODE_URL_STR=y
+CONFIG_FEATURE_HTTPD_ERROR_PAGES=y
+CONFIG_FEATURE_HTTPD_PROXY=y
+CONFIG_FEATURE_HTTPD_GZIP=y
+CONFIG_IFCONFIG=y
+CONFIG_FEATURE_IFCONFIG_STATUS=y
+CONFIG_FEATURE_IFCONFIG_SLIP=y
+CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ=y
+CONFIG_FEATURE_IFCONFIG_HW=y
+CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS=y
+CONFIG_IFENSLAVE=y
+CONFIG_IFPLUGD=y
+CONFIG_IFUP=y
+CONFIG_IFDOWN=y
+CONFIG_IFUPDOWN_IFSTATE_PATH="/var/run/ifstate"
+CONFIG_FEATURE_IFUPDOWN_IP=y
+CONFIG_FEATURE_IFUPDOWN_IPV4=y
+CONFIG_FEATURE_IFUPDOWN_IPV6=y
+CONFIG_FEATURE_IFUPDOWN_MAPPING=y
+# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set
+CONFIG_INETD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME=y
+CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN=y
+# CONFIG_FEATURE_INETD_RPC is not set
+CONFIG_IP=y
+CONFIG_IPADDR=y
+CONFIG_IPLINK=y
+CONFIG_IPROUTE=y
+CONFIG_IPTUNNEL=y
+CONFIG_IPRULE=y
+CONFIG_IPNEIGH=y
+CONFIG_FEATURE_IP_ADDRESS=y
+CONFIG_FEATURE_IP_LINK=y
+CONFIG_FEATURE_IP_ROUTE=y
+CONFIG_FEATURE_IP_ROUTE_DIR="/etc/iproute2"
+CONFIG_FEATURE_IP_TUNNEL=y
+CONFIG_FEATURE_IP_RULE=y
+CONFIG_FEATURE_IP_NEIGH=y
+# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set
+CONFIG_IPCALC=y
+CONFIG_FEATURE_IPCALC_LONG_OPTIONS=y
+CONFIG_FEATURE_IPCALC_FANCY=y
+CONFIG_FAKEIDENTD=y
+CONFIG_NAMEIF=y
+CONFIG_FEATURE_NAMEIF_EXTENDED=y
+CONFIG_NBDCLIENT=y
+CONFIG_NC=y
+CONFIG_NC_SERVER=y
+CONFIG_NC_EXTRA=y
+# CONFIG_NC_110_COMPAT is not set
+CONFIG_NETSTAT=y
+CONFIG_FEATURE_NETSTAT_WIDE=y
+CONFIG_FEATURE_NETSTAT_PRG=y
+CONFIG_NSLOOKUP=y
+CONFIG_NTPD=y
+CONFIG_FEATURE_NTPD_SERVER=y
+CONFIG_FEATURE_NTPD_CONF=y
+CONFIG_PING=y
+CONFIG_PING6=y
+CONFIG_FEATURE_FANCY_PING=y
+CONFIG_PSCAN=y
+CONFIG_ROUTE=y
+CONFIG_SLATTACH=y
+CONFIG_SSL_CLIENT=y
+CONFIG_TCPSVD=y
+CONFIG_UDPSVD=y
+CONFIG_TELNET=y
+CONFIG_FEATURE_TELNET_TTYPE=y
+CONFIG_FEATURE_TELNET_AUTOLOGIN=y
+CONFIG_FEATURE_TELNET_WIDTH=y
+CONFIG_TELNETD=y
+CONFIG_FEATURE_TELNETD_STANDALONE=y
+CONFIG_FEATURE_TELNETD_INETD_WAIT=y
+CONFIG_TFTP=y
+CONFIG_TFTPD=y
+
+#
+# Common options for tftp/tftpd
+#
+CONFIG_FEATURE_TFTP_GET=y
+CONFIG_FEATURE_TFTP_PUT=y
+CONFIG_FEATURE_TFTP_BLOCKSIZE=y
+CONFIG_FEATURE_TFTP_PROGRESS_BAR=y
+# CONFIG_TFTP_DEBUG is not set
+CONFIG_TLS=y
+CONFIG_TRACEROUTE=y
+CONFIG_TRACEROUTE6=y
+CONFIG_FEATURE_TRACEROUTE_VERBOSE=y
+CONFIG_FEATURE_TRACEROUTE_USE_ICMP=y
+CONFIG_TUNCTL=y
+CONFIG_FEATURE_TUNCTL_UG=y
+CONFIG_VCONFIG=y
+CONFIG_WGET=y
+CONFIG_FEATURE_WGET_LONG_OPTIONS=y
+CONFIG_FEATURE_WGET_STATUSBAR=y
+CONFIG_FEATURE_WGET_AUTHENTICATION=y
+CONFIG_FEATURE_WGET_TIMEOUT=y
+CONFIG_FEATURE_WGET_HTTPS=y
+CONFIG_FEATURE_WGET_OPENSSL=y
+CONFIG_WHOIS=y
+CONFIG_ZCIP=y
+# CONFIG_UDHCPC6 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
+# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
+CONFIG_UDHCPD=y
+CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY=y
+# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set
+CONFIG_DHCPD_LEASES_FILE="/var/lib/misc/udhcpd.leases"
+CONFIG_DUMPLEASES=y
+CONFIG_DHCPRELAY=y
+CONFIG_UDHCPC=y
+CONFIG_FEATURE_UDHCPC_ARPING=y
+CONFIG_FEATURE_UDHCPC_SANITIZEOPT=y
+CONFIG_UDHCPC_DEFAULT_SCRIPT="/usr/share/udhcpc/default.script"
+# CONFIG_FEATURE_UDHCP_PORT is not set
+CONFIG_UDHCP_DEBUG=9
+CONFIG_FEATURE_UDHCP_RFC3397=y
+CONFIG_FEATURE_UDHCP_8021Q=y
+CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80
+CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"
+
+#
+# Print Utilities
+#
+CONFIG_LPD=y
+CONFIG_LPR=y
+CONFIG_LPQ=y
+
+#
+# Mail Utilities
+#
+CONFIG_MAKEMIME=y
+CONFIG_POPMAILDIR=y
+CONFIG_FEATURE_POPMAILDIR_DELIVERY=y
+CONFIG_REFORMIME=y
+CONFIG_FEATURE_REFORMIME_COMPAT=y
+CONFIG_SENDMAIL=y
+CONFIG_FEATURE_MIME_CHARSET="us-ascii"
+
+#
+# Process Utilities
+#
+CONFIG_FREE=y
+CONFIG_FUSER=y
+CONFIG_IOSTAT=y
+CONFIG_KILL=y
+CONFIG_KILLALL=y
+CONFIG_KILLALL5=y
+CONFIG_LSOF=y
+CONFIG_MPSTAT=y
+CONFIG_NMETER=y
+CONFIG_PGREP=y
+CONFIG_PKILL=y
+CONFIG_PIDOF=y
+CONFIG_FEATURE_PIDOF_SINGLE=y
+CONFIG_FEATURE_PIDOF_OMIT=y
+CONFIG_PMAP=y
+CONFIG_POWERTOP=y
+CONFIG_FEATURE_POWERTOP_INTERACTIVE=y
+CONFIG_PS=y
+# CONFIG_FEATURE_PS_WIDE is not set
+# CONFIG_FEATURE_PS_LONG is not set
+CONFIG_FEATURE_PS_TIME=y
+# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set
+CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS=y
+CONFIG_PSTREE=y
+CONFIG_PWDX=y
+CONFIG_SMEMCAP=y
+CONFIG_BB_SYSCTL=y
+CONFIG_TOP=y
+CONFIG_FEATURE_TOP_INTERACTIVE=y
+CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y
+CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
+CONFIG_FEATURE_TOP_SMP_CPU=y
+CONFIG_FEATURE_TOP_DECIMALS=y
+CONFIG_FEATURE_TOP_SMP_PROCESS=y
+CONFIG_FEATURE_TOPMEM=y
+CONFIG_UPTIME=y
+CONFIG_FEATURE_UPTIME_UTMP_SUPPORT=y
+CONFIG_WATCH=y
+CONFIG_FEATURE_SHOW_THREADS=y
+
+#
+# Runit Utilities
+#
+CONFIG_CHPST=y
+CONFIG_SETUIDGID=y
+CONFIG_ENVUIDGID=y
+CONFIG_ENVDIR=y
+CONFIG_SOFTLIMIT=y
+CONFIG_RUNSV=y
+CONFIG_RUNSVDIR=y
+# CONFIG_FEATURE_RUNSVDIR_LOG is not set
+CONFIG_SV=y
+CONFIG_SV_DEFAULT_SERVICE_DIR="/var/service"
+CONFIG_SVC=y
+CONFIG_SVLOGD=y
+# CONFIG_CHCON is not set
+# CONFIG_FEATURE_CHCON_LONG_OPTIONS is not set
+# CONFIG_GETENFORCE is not set
+# CONFIG_GETSEBOOL is not set
+# CONFIG_LOAD_POLICY is not set
+# CONFIG_MATCHPATHCON is not set
+# CONFIG_RUNCON is not set
+# CONFIG_FEATURE_RUNCON_LONG_OPTIONS is not set
+# CONFIG_SELINUXENABLED is not set
+# CONFIG_SESTATUS is not set
+# CONFIG_SETENFORCE is not set
+# CONFIG_SETFILES is not set
+# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set
+# CONFIG_RESTORECON is not set
+# CONFIG_SETSEBOOL is not set
+
+#
+# Shells
+#
+CONFIG_SH_IS_ASH=y
+# CONFIG_SH_IS_HUSH is not set
+# CONFIG_SH_IS_NONE is not set
+CONFIG_BASH_IS_ASH=y
+# CONFIG_BASH_IS_HUSH is not set
+# CONFIG_BASH_IS_NONE is not set
+CONFIG_ASH=y
+CONFIG_ASH_OPTIMIZE_FOR_SIZE=y
+CONFIG_ASH_INTERNAL_GLOB=y
+CONFIG_ASH_BASH_COMPAT=y
+CONFIG_ASH_JOB_CONTROL=y
+CONFIG_ASH_ALIAS=y
+CONFIG_ASH_RANDOM_SUPPORT=y
+CONFIG_ASH_EXPAND_PRMT=y
+CONFIG_ASH_IDLE_TIMEOUT=y
+CONFIG_ASH_MAIL=y
+CONFIG_ASH_ECHO=y
+CONFIG_ASH_PRINTF=y
+CONFIG_ASH_TEST=y
+CONFIG_ASH_HELP=y
+CONFIG_ASH_GETOPTS=y
+CONFIG_ASH_CMDCMD=y
+CONFIG_CTTYHACK=y
+# CONFIG_HUSH is not set
+# CONFIG_HUSH_BASH_COMPAT is not set
+# CONFIG_HUSH_BRACE_EXPANSION is not set
+# CONFIG_HUSH_INTERACTIVE is not set
+# CONFIG_HUSH_SAVEHISTORY is not set
+# CONFIG_HUSH_JOB is not set
+# CONFIG_HUSH_TICK is not set
+# CONFIG_HUSH_IF is not set
+# CONFIG_HUSH_LOOPS is not set
+# CONFIG_HUSH_CASE is not set
+# CONFIG_HUSH_FUNCTIONS is not set
+# CONFIG_HUSH_LOCAL is not set
+# CONFIG_HUSH_RANDOM_SUPPORT is not set
+# CONFIG_HUSH_MODE_X is not set
+# CONFIG_HUSH_ECHO is not set
+# CONFIG_HUSH_PRINTF is not set
+# CONFIG_HUSH_TEST is not set
+# CONFIG_HUSH_HELP is not set
+# CONFIG_HUSH_EXPORT is not set
+# CONFIG_HUSH_EXPORT_N is not set
+# CONFIG_HUSH_KILL is not set
+# CONFIG_HUSH_WAIT is not set
+# CONFIG_HUSH_TRAP is not set
+# CONFIG_HUSH_TYPE is not set
+# CONFIG_HUSH_READ is not set
+# CONFIG_HUSH_SET is not set
+# CONFIG_HUSH_UNSET is not set
+# CONFIG_HUSH_ULIMIT is not set
+# CONFIG_HUSH_UMASK is not set
+# CONFIG_HUSH_MEMLEAK is not set
+# CONFIG_MSH is not set
+
+#
+# Options common to all shells
+#
+CONFIG_FEATURE_SH_MATH=y
+CONFIG_FEATURE_SH_MATH_64=y
+CONFIG_FEATURE_SH_EXTRA_QUIET=y
+# CONFIG_FEATURE_SH_STANDALONE is not set
+# CONFIG_FEATURE_SH_NOFORK is not set
+CONFIG_FEATURE_SH_HISTFILESIZE=y
+
+#
+# System Logging Utilities
+#
+CONFIG_KLOGD=y
+
+#
+# klogd should not be used together with syslog to kernel printk buffer
+#
+CONFIG_FEATURE_KLOGD_KLOGCTL=y
+CONFIG_LOGGER=y
+CONFIG_LOGREAD=y
+CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING=y
+CONFIG_SYSLOGD=y
+CONFIG_FEATURE_ROTATE_LOGFILE=y
+CONFIG_FEATURE_REMOTE_LOG=y
+CONFIG_FEATURE_SYSLOGD_DUP=y
+CONFIG_FEATURE_SYSLOGD_CFG=y
+CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=256
+CONFIG_FEATURE_IPC_SYSLOG=y
+CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=16
+CONFIG_FEATURE_KMSG_SYSLOG=y
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..5234be8
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,503 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=5
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+#yes-on no-off
+cc_at_debug=no
+xlat_enable=1
+ecallmode=2
+telog_path_cap=
+telog_path=
+zpsstate_detect=1
+zpsstate_detect_period=60
+zpsstate_restart=0
\ No newline at end of file
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..7147993
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_4Gb/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,502 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=5
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+#yes-on no-off
+cc_at_debug=no
+xlat_enable=1
+telog_path_cap=
+telog_path=
+zpsstate_detect=1
+zpsstate_detect_period=60
+zpsstate_restart=0
\ No newline at end of file
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..f082891
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_ref/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,554 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+path_voice=/mnt/oem/voice
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=3
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_prof_ssid=
+wifi_prof_ssid1=
+wifi_prof_ssid2=
+wifi_prof_ssid3=
+wifi_prof_ssid4=
+wifi_prof_ssid5=
+wifi_prof_ssid6=
+wifi_prof_ssid7=
+wifi_prof_ssid8=
+wifi_prof_ssid9=
+wifi_prof_pw=
+wifi_prof_pw1=
+wifi_prof_pw2=
+wifi_prof_pw3=
+wifi_prof_pw4=
+wifi_prof_pw5=
+wifi_prof_pw6=
+wifi_prof_pw7=
+wifi_prof_pw8=
+wifi_prof_pw9=
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+#zw.wang After rndis used the network, the T106 sleep was repeatedly awakened on 20240429 start
+wifiAvailable=1
+#zw.wang After rndis used the network, the T106 sleep was repeatedly awakened on 20240429 end
+# zw.wang WiFi for MAC is obtained from firmware and set on 20240508 start
+wifi_mac_num=1
+# zw.wang WiFi for MAC is obtained from firmware and set on 20240508 end
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+SSID1_5g=Ufi_
+m_SSID_5g=Ufi_
+HideSSID_5g=0
+m_HideSSID_5g=0
+AuthMode_5g=WPA2PSK
+m_AuthMode_5g=WPA2PSK
+EncrypType_5g=AES
+m_EncrypType_5g=AES
+WPAPSK1_encode_5g=MTIzNDU2Nzg=
+WPAPSK1_aes_5g=
+m_WPAPSK1_encode_5g=MTIzNDU2Nzg=
+m_WPAPSK1_aes_5g=
+wifi_11n_cap_5g=1
+WirelessMode_5g=6
+Channel_5g=0
+# zw.wang [wifi] If the 5G hotspot is enabled, the country code cannot be obtained by calling qser_wifi_ap_channel_get on 20240829 start
+CountryCode_5g=CN
+# zw.wang [wifi] If the 5G hotspot is enabled, the country code cannot be obtained by calling qser_wifi_ap_channel_get on 20240829 end
+MAX_Access_num_5g=32
+m_MAX_Access_num_5g=0
+ACL_mode_5g=0
+wifi_mac_black_list_5g=
+wifi_mac_white_list_5g=
+wifi_sup_5g_band=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0+/dev/ttyGS1
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+#yes-on no-off
+cc_at_debug=no
+xlat_enable=1
+ecallmode=2
+telog_path_cap=
+telog_path=
+zpsstate_detect=1
+zpsstate_detect_period=60
+zpsstate_restart=0
\ No newline at end of file
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
new file mode 100755
index 0000000..92191d4
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/files/zx297520v3/vehicle_dc_systemd/fs/normal/rootfs/etc_ro/default/default_parameter_user
@@ -0,0 +1,497 @@
+apn_auto_config=CMCC($)cmnet($)manual($)*99#($)pap($)($)($)IP($)auto($)($)auto($)($)
+APN_config0=Default($)Default($)manual($)($)($)($)($)IP($)auto($)($)auto($)($)
+APN_config1=
+APN_config2=
+APN_config3=
+APN_config4=
+APN_config5=
+APN_config6=
+APN_config7=
+APN_config8=
+APN_config9=
+apn_index=0
+apn_mode=auto
+at_snap_flag=3
+at_wifi_mac=0
+auto_apn_index=0
+cid_reserved=1
+clear_pb_when_restore=no
+clear_sms_when_restore=no
+default_apn=3gnet
+ipv6_APN_config1=
+ipv6_APN_config2=
+ipv6_APN_config3=
+ipv6_APN_config4=
+ipv6_APN_config5=
+ipv6_APN_config6=
+ipv6_APN_config7=
+ipv6_APN_config8=
+ipv6_APN_config9=
+m_profile_name=Internux
+need_init_modem=no
+net_select=NETWORK_auto
+pdp_type=IP
+ppp_apn=
+max_reconnect_time=3000000
+pppd_auth=noauth
+ppp_auth_mode=none
+ppp_passwd=
+ppp_pdp_type=
+ppp_username=
+ipv6_ppp_auth_mode=none
+ipv6_ppp_passwd=
+ipv6_ppp_username=
+pre_mode=
+prefer_dns_manual=0.0.0.0
+standby_dns_manual=0.0.0.0
+wan_apn=internet
+wan_dial=
+cta_test=0
+safecare_enbale=1
+safecare_hostname=mob.3gcare.cn
+safecare_registed_imei=
+safecare_registed_iccid=
+safecare_contimestart1=
+safecare_contimestart2=
+safecare_contimestart3=
+safecare_contimestop1=
+safecare_contimestop2=
+safecare_contimestop3=
+safecare_contimeinterval=
+safecare_mobsite=http://mob.3gcare.cn
+safecare_chatsite=
+safecare_platno=
+safecare_mobilenumber=
+safecare_version=
+ethwan_dns_mode=auto
+pswan_dns_mode=auto
+wifiwan_dns_mode=auto
+ethwan_ipv6_dns_mode=auto
+wifiwan_ipv6_dns_mode=auto
+pswan_ipv6_dns_mode=auto
+admin_Password=Pass1234
+psw_changed=1
+alg_ftp_enable=0
+alg_sip_enable=0
+blc_wan_auto_mode=AUTO_PPP
+blc_wan_mode=AUTO
+br_ipchange_flag=
+br_node=usblan0+zvnet0
+br_node_cap=zvnet0
+br_node_num=
+br_node0=
+br_node1=
+br_node2=
+clat_fake_subnet=192.0.168.0
+clat_frag_collect_timeout=300
+clat_local_mapping_timeout=300
+clat_mapping_record_timeout=3000
+clat_query_server_port=1464
+DefaultFirewallPolicy=0
+dev_coexist=0
+dhcpDns=192.168.0.1
+dhcpEnabled=1
+dhcpEnd=192.168.0.200
+dhcpLease_hour=24
+dhcpStart=192.168.0.100
+dhcpv6stateEnabled=0
+dhcpv6statelessEnabled=1
+dhcpv6statePdEnabled=0
+dial_mode=auto_dial
+DMZEnable=0
+DMZIPAddress=
+dns_extern=
+ipv6_dns_extern=
+eth_act_type=
+eth_type=lan
+ethlan=
+ethwan=
+ethwan_dialmode=auto
+ethwan_mode=auto
+ethwan_priority=3
+fast_usb=usblan0
+fastnat_level=2
+fastbr_level=1
+IPPortFilterEnable=0
+IPPortFilterRules_0=
+IPPortFilterRules_1=
+IPPortFilterRules_2=
+IPPortFilterRules_3=
+IPPortFilterRules_4=
+IPPortFilterRules_5=
+IPPortFilterRules_6=
+IPPortFilterRules_7=
+IPPortFilterRules_8=
+IPPortFilterRules_9=
+IPPortFilterRulesv6_0=
+IPPortFilterRulesv6_1=
+IPPortFilterRulesv6_2=
+IPPortFilterRulesv6_3=
+IPPortFilterRulesv6_4=
+IPPortFilterRulesv6_5=
+IPPortFilterRulesv6_6=
+IPPortFilterRulesv6_7=
+IPPortFilterRulesv6_8=
+IPPortFilterRulesv6_9=
+ipv4_fake_subnet=192.0.0.0
+ipv6_fake_subnet=2016::1
+lan_ipaddr=192.168.0.1
+webv6_enable=1
+lan_ipv6addr=fe80::1
+lan_name=br0
+lan_netmask=255.255.255.0
+LanEnable=1
+dhcpDns_cap=192.168.0.2
+lan_ipv6addr_cap=fe80::2
+lan_ipaddr_cap=192.168.0.2
+lan_name_cap=br0
+lan_netmask_cap=255.255.255.0
+LanEnable_cap=1
+mac_ip_list=
+mgmt_quicken_power_on=0
+mtu=1400
+natenable=
+dosenable=0
+need_jilian=1
+nofast_port=21+22+23+25+53+67+68+69+110+115+123+443+500+1352+1723+1990+1991+1992+1993+1994+1995+1996+1997+1998+4500+5060
+nv_save_interval=300
+path_conf=/etc_rw
+path_ro=/etc_ro
+path_log=/tmp/
+netlog_limit=yes
+path_sh=/sbin
+path_tmp=/tmp
+permit_gw=
+permit_ip6=
+permit_nm=255.255.255.0
+PortForwardEnable=0
+PortForwardRules_0=
+PortForwardRules_1=
+PortForwardRules_2=
+PortForwardRules_3=
+PortForwardRules_4=
+PortForwardRules_5=
+PortForwardRules_6=
+PortForwardRules_7=
+PortForwardRules_8=
+PortForwardRules_9=
+PortMapEnable=0
+PortMapRules_0=
+PortMapRules_1=
+PortMapRules_2=
+PortMapRules_3=
+PortMapRules_4=
+PortMapRules_5=
+PortMapRules_6=
+PortMapRules_7=
+PortMapRules_8=
+PortMapRules_9=
+ppp_name=ppp0
+pppoe_password=
+pppoe_username=
+ps_ext1=zvnet1
+ps_ext2=zvnet2
+ps_ext3=zvnet3
+ps_ext4=zvnet4
+ps_ext5=zvnet5
+ps_ext6=zvnet6
+ps_ext7=zvnet7
+ps_ext8=zvnet8
+pswan=wan
+pswan_mode=pdp
+pswan_priority=1
+pswan_cap=zvnet
+RemoteManagement=0
+rootdev_friendlyname=DEMO-UPnP
+rootdev_manufacturer=DEMO
+rootdev_modeldes=XXX
+rootdev_modelname=XXX
+os_url=http://www.demo.com
+serialnumber=See-IMEI
+static_dhcp_enable=1
+static_ethwan_gw=
+static_ethwan_ip=
+static_ethwan_nm=
+static_ethwan_pridns=
+static_ethwan_secdns=
+static_wifiwan_ipaddr=
+static_wifiwan_netmask=
+static_wifiwan_gateway=
+wifiwan_pridns_manual=
+wifiwan_secdns_manual=
+static_wan_gateway=0.0.0.0
+static_wan_ipaddr=0.0.0.0
+static_wan_netmask=0.0.0.0
+static_wan_primary_dns=0.0.0.0
+static_wan_secondary_dns=0.0.0.0
+swlanstr=sw0_lan
+swvlan=sw0
+swwanstr=sw0_wan
+tc_downlink=
+tc_uplink=
+tc_local=1310720
+tc_enable=0
+time_limited=
+time_to_2000_when_restore=yes
+upnpEnabled=0
+usblan=usblan0
+WANPingFilter=0
+websURLFilters=
+wifiwan_priority=2
+DDNS=
+DDNS_Enable=0
+DDNSAccount=
+DDNSPassword=
+DDNSProvider=
+iccidPrevious=
+imeiPrevious=
+registerFlag=0
+registeredRound=
+secsEveryRound=1
+secsEveryTime=1
+regver=4.0
+meid=
+uetype=1
+LocalDomain=m.home
+data_volume_alert_percent=
+data_volume_limit_size=
+data_volume_limit_switch=0
+data_volume_limit_unit=0
+flux_day_total=0
+flux_last_day=
+flux_last_month=
+flux_last_year=
+flux_month_total=0
+flux_set_day=
+flux_set_month=
+flux_set_year=
+monthly_rx_bytes=0
+monthly_time=0
+monthly_tx_bytes=0
+MonthlyConTime_Last=
+dm_nextpollingtime=
+fota_allowRoamingUpdate=0
+fota_dl_pkg_size=0
+fota_update_flag=
+fota_updateIntervalDay=15
+fota_upgrade_result=
+fota_version_delta_id=
+fota_version_delta_url=
+fota_pkg_total_size=0
+fota_version_file_size=
+fota_version_md5sum=
+fota_version_name=
+fota_need_user_confirm_update=0
+fota_need_user_confirm_download=0
+fota_version_force_install=0
+polling_nexttime=0
+pwron_auto_check=0
+fota_updateMode=0
+fota_test_mode=0
+fota_pkg_downloaded=0
+fota_upgrade_result_internal=
+mmi_battery_voltage_line=3090+3300+3450+3490+3510+3540+3550+3570+3580+3600+3620+3650+3670+3710+3740+3780+3850+3900+3950+4000+4060
+mmi_fast_poweron=
+mmi_led_mode=sleep_mode
+mmi_new_sms_blink_flag=1
+mmi_show_pagetab=page1+page2+page3
+mmi_showmode=led
+mmi_task_tab=ctrl_task+key_task
+mmi_temp_voltage_line=951+1201+1692+1736
+mmi_use_protect=
+mmi_use_wifi_usernum=1
+leak_full_panic=
+leak_list_max=
+leak_set_flag=
+monitor_period=300
+netinf_flag=
+skb_all_max=
+skb_data_max=
+skb_fromcp_max=
+skb_max_fail=
+skb_max_panic=
+skb_size_max=
+skb_tocp_max=
+sntp_default_ip=134.170.185.211;131.107.13.100;202.112.31.197;202.112.29.82;202.112.10.36;ntp.gwadar.cn;ntp-sz.chl.la;dns.sjtu.edu.cn;news.neu.edu.cn;dns1.synet.edu.cn;time-nw.nist.gov;pool.ntp.org;europe.pool.ntp.org
+sntp_dst_enable=0
+sntp_other_server0=
+sntp_other_server1=
+sntp_other_server2=
+sntp_server0=time-nw.nist.gov
+sntp_server1=pool.ntp.org
+sntp_server2=europe.pool.ntp.org
+sntp_sync_select_interval_time=30
+sntp_time_set_mode=auto
+sntp_timezone=CST-8
+sntp_timezone_index=0
+assert_errno=
+comm_logsize=16384
+cr_inner_version=V1.0.0B08
+cr_version=V1.0.0B01
+hw_version=PCBMF29S2V1.0.0
+TURNOFF_CHR_NUM=
+watchdog_app=0
+HTTP_SHARE_FILE=
+HTTP_SHARE_STATUS=
+HTTP_SHARE_WR_AUTH=readWrite
+ipv6_pdp_type=
+ipv6_wan_apn=
+Language=zh-cn
+manual_time_day=
+manual_time_hour=
+manual_time_minute=
+manual_time_month=
+manual_time_second=
+manual_time_year=
+sdcard_mode_option=0
+AccessControlList0=
+AccessPolicy0=0
+ACL_mode=0
+AuthMode=WPA2PSK
+Channel=0
+wifi_acs_num=5
+closeEnable=0
+closeTime=
+CountryCode=CN
+DefaultKeyID=0
+DtimPeriod=1
+EncrypType=AES
+EX_APLIST=
+EX_APLIST1=
+EX_AuthMode=
+EX_DefaultKeyID=
+EX_EncrypType=
+EX_mac=
+EX_SSID1=Ufi_
+EX_WEPKEY=
+EX_wifi_profile=
+EX_WPAPSK1=
+FragThreshold=2346
+HideSSID=0
+HT_GI=1
+Key1Str1=12345
+Key2Str1=
+Key3Str1=
+Key4Str1=
+Key1Type=1
+Key2Type=
+Key3Type=
+Key4Type=
+m_AuthMode=WPA2PSK
+m_DefaultKeyID=
+m_EncrypType=AES
+m_HideSSID=0
+m_Key1Str1=1234
+m_Key2Str1=
+m_Key3Str1=
+m_Key4Str1=
+m_Key1Type=1
+m_Key2Type=
+m_Key3Type=
+m_Key4Type=
+m_MAX_Access_num=0
+m_NoForwarding=
+m_show_qrcode_flag=0
+m_SSID=Ufi_
+m_ssid_enable=0
+m_wapiType=
+m_wifi_mac=901D45692A5C
+m_WPAPSK1_aes=
+m_WPAPSK1_encode=MTIzNDU2Nzg=
+MAX_Access_num=32
+MAX_Access_num_bak=32
+NoForwarding=0
+openEnable=0
+openTime=
+operater_ap=
+RekeyInterval=3600
+RTSThreshold=2347
+show_qrcode_flag=0
+Sleep_interval=10
+ssid_write_flag=0
+SSID1=Ufi_
+tsw_sleep_time_hour=
+tsw_sleep_time_min=
+tsw_wake_time_hour=
+tsw_wake_time_min=
+wapiType=
+wifi_force_40m=1
+wifi_11n_cap=1
+wifi_band=b
+wifi_coverage=long_mode
+wifi_hostname_black_list=
+wifi_hostname_white_list=
+wifi_mac=901D45692A5B
+wifi_mac_black_list=
+wifi_mac_white_list=
+wifi_profile=
+wifi_profile1=
+wifi_profile2=
+wifi_profile3=
+wifi_profile4=
+wifi_profile5=
+wifi_profile6=
+wifi_profile7=
+wifi_profile8=
+wifi_profile9=
+wifi_profile_num=0
+wifi_root_dir=
+wifi_sta_connection=0
+wifi_wps_index=1
+wifiEnabled=1
+wifilan=wlan0-va0
+wifilan2=wlan0-va1
+WirelessMode=6
+WPAPSK1_aes=
+WPAPSK1_encode=MTIzNDU2Nzg=
+wps_mode=
+WPS_SSID=
+WscModeOption=0
+monitor_apps=
+at_netdog=
+autorspchannel_list=all
+soctime_switch=0
+uart_control=1
+uart_ctstrs_enable=
+uart_softcontrol_enable=
+uart_wakeup_enable=1
+uart_console_coreid=1
+uart_app_ctrl=5
+special_cmd_list=$MYNETREAD
+ra_mtu_enable=
+##为入网入库芯片认证版本添加 begin
+atcmd_stream1=AT+ZSET="w_instrument",1
+atcmd_stream2=AT^SYSCONFIG=24,0,1,2
+atcmd_stream3=AT+ZSET="csiiot",2
+atcmd_stream4=AT+ZSET="dlparaflg",0
+atcmd_stream5=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="CMCC_TEST",1;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0
+atcmd_stream6=AT+ZSET="MTNET_TEST",1;AT+ZGAAT=0;AT+ZSET="LTE_INFO",6348;AT+ZSET="VOICE_SUPPORT",1;AT+ZSET="FDD_RELEASE",7;AT+ZSET="LTE_RELEASE",1;AT+ZSET="UE_PS_RELEASE",5;AT+ZSET="QOS_RELEASE",4;AT+ZSET="TEBS_THRESHOLD",0;AT+ZSET="IGNORE_SECURITY_SUPPORT",0;AT+ZSET="csifilter",0;AT+ZSET="csrhobandflg",0;AT+ZSET="dlparaflg",1;AT+ZSET="csiup",1;AT+ZSET="rfparaflag",0,0,1,0;AT+ZSET="csiiot",1;AT+ZSET="EXCEPT_RESET",0;AT+ZSET="ISIM_SUPPORT",1;AT+ZIMSTEST="MTNET_TEST",1;AT+ZSET="MANUAL_SEARCH",0
+##为入网入库芯片认证版本添加 end
+#for audio ctrl
+audio_priority=0123
+customer_type=
+debug_mode=
+cpIndCmdList=+ZMMI+ZURDY+ZUSLOT+ZICCID^MODE+ZPBIC+ZMSRI+CREG+CEREG+CGREG+CGEV
+zephyr_filter_ip=
+wait_timeout=2
+sntp_sync_time=1
+sntp_static_server0=time-nw.nist.gov
+sntp_static_server1=pool.ntp.org
+sntp_static_server2=europe.pool.ntp.org
+vsim_bin_path=/mnt/userdata/vSim.bin
+at_select_timeout=
+mtnet_test_mcc=+001+002+003+004
+at_atv=
+at_atq=
+at_at_d=
+at_ptsnum=
+quick_dial=1
+cap_port_name=/dev/ttyGS0
+customIndCmdList=
+defrt_cid=1
+MaxRtrAdvInterval=1800
+dhcps_in_cap=1
+gw_in_cap=0
+xlat_enable=1
+telog_path_cap=
+telog_path=
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
new file mode 100755
index 0000000..b86b882
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-core/images/zxic-image.bb
@@ -0,0 +1,274 @@
+SUMMARY = "zxic normal image"
+IMAGE_LINGUAS = " "
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+inherit core-image extrausers ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "selinux-image", "", d)}
+
+OPENWRT_FULL ="\
+ packagegroup-openwrt-minimal \
+ packagegroup-openwrt-base \
+ packagegroup-openwrt-full \
+ ugps \
+ usbmode \
+ urngd \
+ mtd-utils-ubifs \
+ fwtool \
+ usign \
+ swconfig \
+ mtd-openwrt \
+ opkg \
+ cgi-io \
+ "
+OPENWRT_RECOVERY ="\
+ packagegroup-openwrt-minimal \
+ mtd-utils-ubifs \
+ mtd-openwrt \
+ "
+
+
+OPENWRT_PACKAGE = "${@bb.utils.contains("BOOT_CTL", "recovery", "${OPENWRT_RECOVERY}", "${OPENWRT_FULL}", d)}"
+IS_OPENWRT = "${@bb.utils.contains('DISTRO_FEATURES', 'OPENWRT', 'true', 'false', d)}"
+ROOT_FS_NAME = "${@bb.utils.contains("BOOT_CTL", "recovery", "ap_recoveryfs.bin", "ap_caprootfs.img", d)}"
+USEDATA_FS_NAME = "${@bb.utils.contains("BOOT_CTL", "recovery", "ap_userdata_recovery.bin", "ap_capuserdata.img", d)}"
+OEMDATA_FS_NAME = "${@bb.utils.contains("BOOT_CTL", "recovery", "ap_oemdata_recovery.bin", "cap_oemdata.img", d)}"
+
+CORE_IMAGE_BASE_INSTALL = '\
+ ${@bb.utils.contains("DISTRO_FEATURES", "OPENWRT", "${OPENWRT_PACKAGE}", "", d)} \
+ packagegroup-core-boot-zxic \
+ packagegroup-lynq-t106 \
+ ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "packagegroup-selinux-minimal", "", d)} \
+ ${MACHINE_EXTRA_RDEPENDS} \
+ ${CORE_IMAGE_EXTRA_INSTALL} \
+ '
+
+# Include modules in rootfs
+IMAGE_INSTALL += "${CORE_IMAGE_BASE_INSTALL}"
+
+IMAGE_INSTALL += " \
+ kernel-modules \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'dpkg-start-stop', '', d)} \
+ "
+
+#pub include
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+
+DEPENDS += "\
+ u-boot-tools-native rsync-native \
+ ${@bb.utils.contains("USERDATA_FSTYPE", "ubi", "mtd-utils-native", "", d)} \
+ ${@bb.utils.contains('IMAGE_FSTYPES', 'squashfs', 'squashfskit-native', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','cryptsetup-native','',d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','coreutils-native','',d)} \
+ "
+
+# Add \ in front of $
+ROOT_PASSWD = "\$6\$GnJN6BAFj7TmbOS\$o4tptoaFJYZe79CWh2VzAgGhQGqfDHoraVUs0nr4TT2e9V2ubq.l.nLrF80ECrtfvPrJDL1J3fbR62nei9A3F1"
+#EXTRA_USERS_PARAMS += "usermod -p '${ROOT_PASSWD}' root;"
+EXTRA_USERS_PARAMS += "${@bb.utils.contains("DISTRO_FEATURES", "OPENWRT", "usermod -p '${ROOT_PASSWD}' root;", "", d)}"
+
+fakeroot distro_rootfs_files_systemd() {
+ rm -rf ${IMAGE_ROOTFS}/boot
+ cp -arfp ${FS-DIR}/fs/${BOOT_CTL}/rootfs/* ${IMAGE_ROOTFS}/
+}
+
+fakeroot distro_rootfs_files_fpga() {
+ rm -rf ${IMAGE_ROOTFS}/boot
+ rm -rf ${IMAGE_ROOTFS}/linuxrc
+ rm -rf ${IMAGE_ROOTFS}/etc/systemd/system.conf
+ cp -arfp ${FS-DIR}/fs/${BOOT_CTL}/rootfs/* ${IMAGE_ROOTFS}/
+ chmod 644 ${IMAGE_ROOTFS}/etc/passwd
+ chmod 644 ${IMAGE_ROOTFS}/etc/group
+ chmod 644 ${IMAGE_ROOTFS}/etc/inittab
+ chmod 400 ${IMAGE_ROOTFS}/etc/shadow
+ chmod a+x ${IMAGE_ROOTFS}/etc/init.d/rcS
+ chmod a+r ${IMAGE_ROOTFS}/etc/init.d/rcS
+}
+
+fakeroot distro_rootfs_files_sysvinit() {
+ rm -rf ${IMAGE_ROOTFS}/boot
+ cp -arfp ${FS-DIR}/fs/${BOOT_CTL}/rootfs/* ${IMAGE_ROOTFS}/
+
+ rm -rf ${IMAGE_ROOTFS}/etc/rc[0-6].d
+ rm -f ${IMAGE_ROOTFS}/etc/fstab
+ rm -f ${IMAGE_ROOTFS}/etc/default/rcS
+ chmod 644 ${IMAGE_ROOTFS}/etc/passwd
+ chmod 644 ${IMAGE_ROOTFS}/etc/group
+ chmod 644 ${IMAGE_ROOTFS}/etc/inittab
+ chmod 400 ${IMAGE_ROOTFS}/etc/shadow
+ chmod a+x ${IMAGE_ROOTFS}/etc/init.d/rcS
+ find ${IMAGE_ROOTFS}/ -name '.gitkeep' -print0 | xargs -0 rm -fr
+}
+
+ROOTFS_POSTPROCESS_COMMAND += "\
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "distro_rootfs_files_sysvinit;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "distro_rootfs_files_systemd;", "", d)} \
+ "
+
+fakeroot do_cprootfs() {
+ #rm -fv ${BINS-PATH}/${ROOT_FS_NAME}
+ mkdir -p ${BINS-PATH} ${ELFS-PATH}
+
+ if [ ${IMAGE_FSTYPES} = 'cpio.gz' ]; then
+ cd ${IMAGE_ROOTFS} && find . | cpio -o -H newc | gzip -9 > ${IMAGE_ROOTFS}/ramdisk.image.gz
+ mv ${IMAGE_ROOTFS}/ramdisk.image.gz ${BINS-PATH}/${ROOT_FS_NAME}
+ if [ -d "${TMPDIR}/work/zx298501-zxic-linux-musl/linux-zxic/5.4.154-r0" ]; then
+ cp -arfp ${THISDIR}/files/Makefile_dtb ${B}/Makefile
+ cp -arfp ${THISDIR}/files/fix_rootfs_dts.sh ${B}/
+ ${B}/fix_rootfs_dts.sh ${MACHINE}-${DISTRO} ${TMPDIR}/work-shared/zx298501/kernel-source ${BINS-PATH}
+ oe_runmake -C ${B} S=${TMPDIR}/work/zx298501-zxic-linux-musl/linux-zxic/5.4.154-r0 BINS-PATH=${ELFS-PATH} DTB=${MACHINE}-${DISTRO}.dtb
+ fi
+ else
+ #cp -v ${IMGDEPLOYDIR}/${IMAGE_LINK_NAME}.${IMAGE_FSTYPES} ${BINS-PATH}/${ROOT_FS_NAME}
+ cp -v ${IMGDEPLOYDIR}/rootfs.tgz ${ELFS-PATH}/${ROOT_FS_NAME}.tgz
+ fi
+}
+
+fakeroot do_cleanrootfs () {
+ rm -fv ${BINS-PATH}/${ROOT_FS_NAME}
+ rm -fv ${BINS-PATH}/${USEDATA_FS_NAME}
+ rm -fv ${BINS-PATH}/*.img*
+}
+
+do_product_ini() {
+ mkdir -p ${BINS-PATH}
+ echo "[imagefs]" > ${BINS-PATH}/product.ini
+ echo "mkfs_ubifs=${IMAGEFS_MKUBIFS_ARGS}" >> ${BINS-PATH}/product.ini
+ echo "ubinize=${IMAGEFS_UBINIZE_ARGS}" >> ${BINS-PATH}/product.ini
+}
+
+do_all_flags_bin() {
+ ${BSPDIR}/zxic_code/pub/tools/libflags/flags_tool -f ${BINS-PATH}/all_flags.bin ${FLAGS_ARGS}
+}
+
+fakeroot do_mkubifs(){
+ if [ ${BOOT_CTL} = 'normal' ]; then
+ cp -arfp ${THISDIR}/files/ubinize-cfg.sh ${B}
+ cp -arfp ${BSPDIR}/sources/meta-zxic-custom/conf/distro/include/${USERDATA_UBINIZE_CFG} ${B}
+ mkdir -p ${BINS-PATH}
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/${USEDATA_FS_NAME}" "${B}/${USERDATA_UBINIZE_CFG}" "${USERDATA_UBINIZE_ARGS}"
+ mkdir -p ${IMAGE_ROOTFS}/etc_ro/
+ cp -v "${BINS-PATH}/${USEDATA_FS_NAME}" ${IMAGE_ROOTFS}/etc_ro/
+ fi
+}
+
+
+fakeroot do_rootfs_squashfs(){
+ cp -arfp ${THISDIR}/files/ubinize-static.sh ${B}
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp -arfp ${THISDIR}/files/squashfs_dm-verity.sh ${B}
+ cp -arfp ${THISDIR}/files/zxic_generate_squashfs_verity ${B}
+ fi
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ touch ${IMAGE_ROOTFS}/etc_ro/dm-verity
+ else
+ rm -fv ${IMAGE_ROOTFS}/etc_ro/dm-verity
+ fi
+
+ rm -fv ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp
+ mksquashfs4 ${IMAGE_ROOTFS} ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp ${ROOTFS_SQUASHFS_ARGS}
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp ${S}/${ROOT_FS_NAME}.unsigned
+ echo "veritysetup and ubinize in do_dm_verity() later ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}"
+ else
+ echo "rootfs squashfs need ubinize-image on nand flash"
+ ${B}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs.img" ${IMGDEPLOYDIR}/${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.squashfs_tmp "${UBINIZE_ARGS}"
+ fi
+ cd ${IMAGE_ROOTFS}/../ && tar -czvf ${IMGDEPLOYDIR}/rootfs.tgz rootfs
+}
+
+fakeroot do_oemfs_squashfs(){
+ cp -arfp ${THISDIR}/files/ubinize-static.sh ${B}
+ cp -arfp ${FS-DIR}/fs/normal/oem/ ${S}/
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp -arfp ${THISDIR}/files/squashfs_dm-verity.sh ${B}
+ cp -arfp ${THISDIR}/files/zxic_generate_squashfs_verity ${B}
+ fi
+
+ rm -fv ${IMGDEPLOYDIR}/oem.squashfs_tmp
+ mksquashfs4 ${S}/oem ${IMGDEPLOYDIR}/oem.squashfs_tmp ${ROOTFS_SQUASHFS_ARGS}
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ cp ${IMGDEPLOYDIR}/oem.squashfs_tmp ${S}/cap_oem.img.unsigned
+ echo "veritysetup and ubinize in do_dm_verity() later"
+ else
+ echo "oem squashfs need ubinize-image on nand flash"
+ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem.img" ${IMGDEPLOYDIR}/oem.squashfs_tmp "${UBINIZE_ARGS}"
+ mkdir -p ${ELFS-PATH}
+ rm -rf ${IMGDEPLOYDIR}/oem.squashfs_tmp
+ fi
+ mkdir -p ${ELFS-PATH}
+ cd ${S}/oem/../ && tar -czvf ${ELFS-PATH}/oem.tgz oem
+
+}
+
+fakeroot do_oemfs_oemdata(){
+ if [ ${BOOT_CTL} = 'normal' ]; then
+ cp -arfp ${THISDIR}/files/ubinize-cfg.sh ${B}
+ cp -arfp ${BSPDIR}/sources/meta-zxic-custom/conf/distro/include/${OEMDATA_UBINIZE_CFG} ${B}
+ mkdir -p ${BINS-PATH}
+ ${B}/ubinize-cfg.sh "${BINS-PATH}/${OEMDATA_FS_NAME}" "${B}/${OEMDATA_UBINIZE_CFG}" "${USERDATA_UBINIZE_ARGS}"
+ mkdir -p ${IMAGE_ROOTFS}/etc_ro/
+ cp -v "${BINS-PATH}/${OEMDATA_FS_NAME}" ${IMAGE_ROOTFS}/etc_ro/
+ fi
+}
+
+ROOTFS_POSTPROCESS_COMMAND_remove += 'empty_var_volatile;'
+
+fakeroot do_postinstall(){
+ if [ -f ${IMAGE_ROOTFS}/postinstall.sh ]; then
+ cd ${IMAGE_ROOTFS} && sh postinstall.sh && rm -v ${IMAGE_ROOTFS}/postinstall.sh
+ fi
+}
+
+fakeroot do_ln_musl_ld(){
+ if [ ! -L ${IMAGE_ROOTFS}/lib/ld-linux-aarch64.so.1 ]; then
+ if [ -L ${IMAGE_ROOTFS}/lib/ld-musl-aarch64.so.1 ]; then
+ cd ${IMAGE_ROOTFS}/lib && ln -snf ld-musl-aarch64.so.1 ld-linux-aarch64.so.1
+ fi
+ fi
+}
+
+do_dm_verity(){
+ if ${@bb.utils.contains('DISTRO_FEATURES','dm-verity','true','false',d)}; then
+ rm -fv ${BINS-PATH}/ap_caprootfs.dm
+ ${S}/squashfs_dm-verity.sh ${S}/${ROOT_FS_NAME}.unsigned ${S} \
+ ${BINS-PATH}/ap_caprootfs.img.dm ${SIGNIMAGE_PRIVATE_KEY} ${BSPDIR}/tools/SignTool/SignImage
+ ${S}/ubinize-static.sh vol_rootfs "${BINS-PATH}/ap_caprootfs.img" ${BINS-PATH}/ap_caprootfs.img.dm "${UBINIZE_ARGS}"
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','oemfs','true','false',d)}; then
+ rm -fv ${BINS-PATH}/cap_oem.img.dm
+ ${B}/squashfs_dm-verity.sh ${S}/cap_oem.img.unsigned ${B} \
+ ${BINS-PATH}/cap_oem.img.dm ${SIGNIMAGE_PRIVATE_KEY} ${BSPDIR}/tools/SignTool/SignImage
+ ${B}/ubinize-static.sh vol_oem "${BINS-PATH}/cap_oem.img" ${BINS-PATH}/cap_oem.img.dm "${UBINIZE_ARGS}"
+ fi
+ fi
+}
+
+IMAGE_POSTPROCESS_COMMAND_prepend = ' \
+ do_postinstall; \
+ ${@bb.utils.contains("TCLIBC", "musl", "do_ln_musl_ld;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "selinux", "selinux_set_labels ;", "", d)} \
+ '
+
+IMAGE_POSTPROCESS_COMMAND += "\
+ ${@bb.utils.contains("USERDATA_FSTYPE", "ubi", "do_mkubifs;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "oemfs", "do_oemfs_squashfs;", "", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "oemfs", "do_oemfs_oemdata;", "", d)} \
+ ${@bb.utils.contains("IMAGE_FSTYPES", "squashfs", "do_rootfs_squashfs;", "", d)} \
+ "
+#xf.li@20240716 add start
+do_oem_config() {
+ cp -R ${TOPDIR}/prebuilt/rootfs/* ${IMAGE_ROOTFS}/
+ if [ "${MOBILETEK_LOG_ENCRYPT}" = "enable" ]; then
+ touch ${IMAGE_ROOTFS}/etc/syslog_encrypt_flag
+ else
+ rm -rf ${IMAGE_ROOTFS}/etc/syslog_encrypt_flag
+ touch ${IMAGE_ROOTFS}/etc/no_log_encrypt
+ fi
+}
+addtask do_oem_config after do_rootfs before do_image
+#xf.li@20240716 add end
+addtask cprootfs after do_dm_verity before do_build
+addtask do_dm_verity after do_image_complete before do_build
+addtask cleanrootfs after do_clean before do_cleansstate
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
new file mode 100755
index 0000000..7b8ff1d
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/liblynq-sim/liblynq-sim.bb
@@ -0,0 +1,66 @@
+#inherit externalsrc package
+
+DESCRIPTION = "lynq sim"
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=e1696b147d49d491bcb4da1a57173fff"
+DEPENDS += "libpal gstreamer1.0 glib-2.0 libapn liblynq-log libvendor-ril liblynq-shm libbinder"
+#inherit workonsrc
+WORKONSRC = "${TOPDIR}/../src/lynq/lib/liblynq-sim/"
+FILESEXTRAPATHS_prepend :="${TOPDIR}/../src/lynq/lib/:"
+SRC_URI = " \
+ file://liblynq-sim \
+ "
+
+SRC-DIR = "${S}/../liblynq-sim"
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+BB_INCLUDE_ADD = "--sysroot=${STAGING_DIR_HOST}"
+BB_LDFLAGS_ADD = "--sysroot=${STAGING_DIR_HOST} -Wl,--hash-style=gnu"
+#Parameters passed to do_compile()
+EXTRA_OEMAKE = "'RAT_CONFIG_C2K_SUPPORT = ${RAT_CONFIG_C2K_SUPPORT}'\
+ 'MTK_MULTI_SIM_SUPPORT = ${MTK_MULTI_SIM_SUPPORT}'\
+ 'TARGET_PLATFORM = ${TARGET_PLATFORM}'"
+
+FILES_${PN} = "${base_libdir}/*.so \
+ ${base_bindir}\
+ ${base_sbindir} \
+ /etc/dbus-1/system.d/"
+FILES_${PN}-dev = "/test \
+ ${includedir}"
+
+FILES_${PN}-doc = "/doc"
+
+FILES_${PN}-dbg ="${base_bindir}/.debug \
+ ${base_libdir}/.debug \
+ ${base_sbindir}/.debug"
+
+INSANE_SKIP_${PN} += "already-stripped"
+INSANE_SKIP_${PN} += "installed-vs-shipped"
+
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ if [ "${PACKAGE_ARCH}" = "cortexa7hf-vfp-vfpv4-neon" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ elif [ "${PACKAGE_ARCH}" = "cortexa7hf-neon-vfpv4" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ elif [ "${PACKAGE_ARCH}" = "cortexa53hf-neon-fp-armv8" ]; then
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -mfpu=neon-vfpv4 -mhard-float -Wl,--hash-style=gnu -DTELEPHONYWARE -mhard-float -mfpu=neon-fp-armv8 -mfloat-abi=hard -mcpu=cortex-a53 -mtune=cortex-a53"
+ else
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -Wl,--hash-style=gnu -DTELEPHONYWARE"
+ fi
+}
+
+do_install () {
+ oe_runmake install -C ${SRC-DIR} ROOT=${D}
+
+ if [ -d "${WORKONSRC}" ] ; then
+ install -d ${D}${includedir}/
+ cp -af ${SRC-DIR}/include/libsim ${D}${includedir}/
+ fi
+}
+
+addtask bachclean
+do_bachclean () {
+ oe_runmake clean
+}
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
new file mode 100755
index 0000000..aeecf6e
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/libpoweralarm/libpoweralarm.bb
@@ -0,0 +1,58 @@
+#inherit externalsrc package
+DESCRIPTION = "libpoweralarm.so "
+SECTION = "base"
+#LICENSE = "Mobiletek""
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=d759532d295a4ec07250edf931caef80"
+DEPENDS += "bootchart liblynq-log libsctel libscrtc"
+
+#inherit workonsrc
+WORKONSRC = "${TOPDIR}/../src/lynq/lib/libpoweralarm/"
+
+FILESEXTRAPATHS_prepend :="${TOPDIR}/../src/lynq/lib/:"
+SRC_URI = " \
+ file://libpoweralarm \
+ "
+SRC-DIR = "${S}/../libpoweralarm"
+TARGET_CC_ARCH += "${LDFLAGS}"
+BB_INCLUDE_ADD = "--sysroot=${STAGING_DIR_HOST}"
+BB_LDFLAGS_ADD = "--sysroot=${STAGING_DIR_HOST} -Wl,--hash-style=gnu"
+
+#Parameters passed to do_compile()
+
+FILES_${PN} = "${base_libdir}/*.so \
+ ${base_bindir}\
+ ${base_sbindir}"
+
+
+FILES_${PN}-dev = "/test \
+ ${includedir}"
+
+FILES_${PN}-doc = "/doc"
+
+FILES_${PN}-dbg ="${base_bindir}/.debug \
+ ${base_libdir}/.debug \
+ ${base_sbindir}/.debug"
+
+INSANE_SKIP_${PN} += "already-stripped"
+INSANE_SKIP_${PN} += "installed-vs-shipped"
+
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ oe_runmake all -C ${SRC-DIR} ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -Os -Wl,--hash-style=gnu -DTELEPHONYWARE"
+}
+
+do_install () {
+ oe_runmake install -C ${SRC-DIR} ROOT=${D}
+
+ if [ -d "${WORKONSRC}" ] ; then
+ install -d ${D}${includedir}/
+ cp -af ${SRC-DIR}/include/ ${D}${includedir}/
+ fi
+}
+
+addtask bachclean
+do_bachclean () {
+ oe_runmake clean
+}
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
new file mode 100755
index 0000000..aee4285
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-network-demo/files/lynq_qser_network.h
@@ -0,0 +1,481 @@
+/**
+ *@file QSER_nw.h
+ *@date 2018-02-22
+ *@author
+ *@brief
+ */
+#ifndef __LYNQ_QSER_NETWORK_H__
+#define __LYNQ_QSER_NETWORK_H__
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t nw_client_handle_type;
+
+
+#define QSER_NW_MODE_NONE 0x00 /**< No network. */
+#define QSER_NW_MODE_GSM 0x01 /**< Include GSM networks. */
+#define QSER_NW_MODE_WCDMA 0x02 /**< Include WCDMA networks. */
+#define QSER_NW_MODE_CDMA 0x04 /**< Include CDMA networks. */
+#define QSER_NW_MODE_EVDO 0x08 /**< Include EVDO networks. */
+#define QSER_NW_MODE_LTE 0x10 /**< Include LTE networks. */
+#define QSER_NW_MODE_TDSCDMA 0x20 /**< Include TDSCDMA networks. */
+
+typedef enum
+{
+ E_QSER_NW_ROAM_STATE_OFF = 0, /**< None, or roaming indicator off. */
+ E_QSER_NW_ROAM_STATE_ON = 1 /**< Roaming indicator on. */
+}E_QSER_NW_ROAM_STATE_TYPE_T;
+
+/** Configures the settings that define the MCM network interface. */
+typedef struct
+{
+ /* Configuration parameters for MCM network registration Network registration details Technology dependent network registration details */
+ uint64_t preferred_nw_mode; /**< Preferred network mode for connections; a bitmask of QSER_NW_MODE_xxxx.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming_pref; /**< Roaming preference.*/
+}QSER_NW_CONFIG_INFO_T;
+
+typedef enum
+{
+ E_QSER_NW_IMS_MODE_OFF = 0, /**< close ims. */
+ E_QSER_NW_IMS_MODE_VOLTE_ENABLE = 1, /**< support volte. */
+}E_QSER_NW_IMS_MODE_TYPE_T;
+
+/** Configures the OOS (out of service) settings that define the MCM network interface. */
+#define QSER_NW_OOS_CFG_TYPE_FAST_SCAN 0x00 /**< fast net scan */
+#define QSER_NW_OOS_CFG_TYPE_FULL_BAND_SCAN 0x01 /**< full band scan */
+
+typedef struct
+{
+ /* Configuration parameters for MCM network fast network scan when OOS (out of service)*/
+ char enable;
+ uint16_t time_interval;
+}QSER_NW_OOS_CONFIG_FAST_SCAN_INFO_T;
+
+typedef struct
+{
+ /* Configuration parameters for MCM network full band network scan when OOS (out of service)*/
+ int t_min;
+ int t_step;
+ int t_num;
+ int t_max;
+}QSER_NW_OOS_CONFIG_FULL_BAND_SCAN_INFO_T;
+
+
+typedef struct
+{
+ char type; /**< QSER_NW_OOS_CFG_TYPE_xxxx.*/
+ union {
+ QSER_NW_OOS_CONFIG_FAST_SCAN_INFO_T fast_can_info; // 00
+ QSER_NW_OOS_CONFIG_FULL_BAND_SCAN_INFO_T full_band_scan_info; // 01
+ } u;
+}QSER_NW_OOS_CONFIG_INFO_T;
+
+//defined for QSER_NW_EventRegister
+#define NW_IND_VOICE_REG_EVENT_IND_FLAG (1 << 0) /**< msg format : QSER_NW_VOICE_REG_EVENT_IND_T */
+#define NW_IND_DATA_REG_EVENT_IND_FLAG (1 << 1) /**< msg format : QSER_NW_DATA_REG_EVENT_IND_T */
+#define NW_IND_SIGNAL_STRENGTH_EVENT_IND_FLAG (1 << 2) /**< msg format : QSER_NW_SINGNAL_EVENT_IND_T */
+//#define NW_IND_CELL_ACCESS_STATE_CHG_EVENT_IND_FLAG (1 << 3) /**< msg format : QL_MCM_NW_CELL_ACCESS_STATE_EVENT_IND_T */
+//#define NW_IND_NITZ_TIME_UPDATE_EVENT_IND_FLAG (1 << 4) /**< msg format : QL_MCM_NW_NITZ_TIME_EVENT_IND_T */
+#define NW_IND_IMS_REG_EVENT_IND_FLAG (1 << 5) /**< msg format : NULL */
+
+typedef struct
+{
+ char long_eons[512 + 1]; /**< Long EONS.*/
+ char short_eons[512 + 1]; /**< Short EONS.*/
+ char mcc[3 + 1]; /**< Mobile country code.*/
+ char mnc[3 + 1]; /**< Mobile network code.*/
+}QSER_NW_OPERATOR_NAME_INFO_T;
+
+typedef enum
+{
+ E_QSER_NW_RADIO_TECH_TD_SCDMA = 1,
+ E_QSER_NW_RADIO_TECH_GSM = 2, /**< GSM; only supports voice. */
+ E_QSER_NW_RADIO_TECH_HSPAP = 3, /**< HSPA+. */
+ E_QSER_NW_RADIO_TECH_LTE = 4, /**< LTE. */
+ E_QSER_NW_RADIO_TECH_EHRPD = 5, /**< EHRPD. */
+ E_QSER_NW_RADIO_TECH_EVDO_B = 6, /**< EVDO B. */
+ E_QSER_NW_RADIO_TECH_HSPA = 7, /**< HSPA. */
+ E_QSER_NW_RADIO_TECH_HSUPA = 8, /**< HSUPA. */
+ E_QSER_NW_RADIO_TECH_HSDPA = 9, /**< HSDPA. */
+ E_QSER_NW_RADIO_TECH_EVDO_A = 10, /**< EVDO A. */
+ E_QSER_NW_RADIO_TECH_EVDO_0 = 11, /**< EVDO 0. */
+ E_QSER_NW_RADIO_TECH_1xRTT = 12, /**< 1xRTT. */
+ E_QSER_NW_RADIO_TECH_IS95B = 13, /**< IS95B. */
+ E_QSER_NW_RADIO_TECH_IS95A = 14, /**< IS95A. */
+ E_QSER_NW_RADIO_TECH_UMTS = 15, /**< UMTS. */
+ E_QSER_NW_RADIO_TECH_EDGE = 16, /**< EDGE. */
+ E_QSER_NW_RADIO_TECH_GPRS = 17, /**< GPRS. */
+ E_QSER_NW_RADIO_TECH_NONE = 18 /**< No technology selected. */
+}E_QSER_NW_RADIO_TECH_TYPE_T;
+
+
+typedef enum
+{
+ E_QSER_NW_TECH_DOMAIN_NONE = 0, /**< None. */
+ E_QSER_NW_TECH_DOMAIN_3GPP = 1, /**< 3GPP. */
+ E_QSER_NW_TECH_DOMAIN_3GPP2 = 2, /**< 3GPP2. */
+}E_QSER_NW_TECH_DOMAIN_TYPE_T;
+
+typedef enum
+{
+ E_QSER_NW_IMSI_UNKNOWN_HLR_DENY_REASON = 1, /**< IMSI unknown in HLR. */
+ E_QSER_NW_ILLEGAL_MS_DENY_REASON = 2, /**< Illegal MS. */
+ E_QSER_NW_IMSI_UNKNOWN_VLR_DENY_REASON = 3, /**< IMSI unknown in VLR. */
+ E_QSER_NW_IMEI_NOT_ACCEPTED_DENY_REASON = 4, /**< IMEI not accepted. */
+ E_QSER_NW_ILLEGAL_ME_DENY_REASON = 5, /**< Illegal ME. */
+ E_QSER_NW_PLMN_NOT_ALLOWED_DENY_REASON = 6, /**< PLMN not allowed. */
+ E_QSER_NW_LA_NOT_ALLOWED_DENY_REASON = 7, /**< Location area not allowed. */
+ E_QSER_NW_ROAMING_NOT_ALLOWED_LA_DENY_REASON = 8, /**< Roaming not allowed in this location area. */
+ E_QSER_NW_NO_SUITABLE_CELLS_LA_DENY_REASON = 9, /**< No suitable cells in location area. */
+ E_QSER_NW_NETWORK_FAILURE_DENY_REASON = 10, /**< Network failure. */
+ E_QSER_NW_MAC_FAILURE_DENY_REASON = 11, /**< MAC failure. */
+ E_QSER_NW_SYNCH_FAILURE_DENY_REASON = 12, /**< Sync failure. */
+ E_QSER_NW_CONGESTION_DENY_REASON = 13, /**< Congestion. */
+ E_QSER_NW_GSM_AUTHENTICATION_UNACCEPTABLE_DENY_REASON = 14, /**< GSM authentication unacceptable. */
+ E_QSER_NW_NOT_AUTHORIZED_CSG_DENY_REASON = 15, /**< Not authorized in this CSG. */
+ E_QSER_NW_SERVICE_OPTION_NOT_SUPPORTED_DENY_REASON = 16, /**< Service option not supported. */
+ E_QSER_NW_REQ_SERVICE_OPTION_NOT_SUBSCRIBED_DENY_REASON = 17, /**< Requested service option not subscribed. */
+ E_QSER_NW_CALL_CANNOT_BE_IDENTIFIED_DENY_REASON = 18, /**< Call cannot be identified. */
+ E_QSER_NW_SEMANTICALLY_INCORRECT_MSG_DENY_REASON = 19, /**< Semantically incorrect message. */
+ E_QSER_NW_INVALID_MANDATORY_INFO_DENY_REASON = 20, /**< Invalid mandatory information. */
+ E_QSER_NW_MSG_TYPE_NON_EXISTENT_DENY_REASON = 21, /**< Message type non-existent or not implemented. */
+ E_QSER_NW_INFO_ELEMENT_NON_EXISTENT_DENY_REASON = 22, /**< Message type not compatible with the protocol state. */
+ E_QSER_NW_CONDITIONAL_IE_ERR_DENY_REASON = 23, /**< Conditional IE error. */
+ E_QSER_NW_MSG_INCOMPATIBLE_PROTOCOL_STATE_DENY_REASON = 24, /**< Message not compatible with the protocol state. */
+ E_QSER_NW_PROTOCOL_ERROR_DENY_REASON = 25, /**< Unspecified protocol error. */
+}E_QSER_NW_DENY_REASON_TYPE_T;
+
+
+typedef enum
+{
+ E_QSER_NW_SERVICE_NONE = 0x0000, /**< Not registered or no data. */
+ E_QSER_NW_SERVICE_LIMITED = 0x0001, /**< Registered; emergency service only. */
+ E_QSER_NW_SERVICE_FULL = 0x0002, /**< Registered, full service. */
+}E_QSER_NW_SERVICE_TYPE_T;
+
+typedef struct
+{
+ E_QSER_NW_TECH_DOMAIN_TYPE_T tech_domain; /**< Technology, used to determine the structure type tech: 0 -- None, 1 -- 3GPP, 2 -- 3GPP2.*/
+ E_QSER_NW_RADIO_TECH_TYPE_T radio_tech; /**< Radio technology; see #nw_radio_tech_t_v01.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming; /**< 0 -- Off, 1 -- Roaming (3GPP2 has extended values).*/
+ E_QSER_NW_DENY_REASON_TYPE_T deny_reason; /**< Set when registration state is #nw_deny_reason_t_v01.*/
+ E_QSER_NW_SERVICE_TYPE_T registration_state; /**< Registration state.*/
+}QSER_NW_COMMON_REG_INFO_T;
+
+
+typedef struct
+{
+ E_QSER_NW_TECH_DOMAIN_TYPE_T tech_domain; /**< Technology, used to determine the structure type tech: 0 -- None, 1 -- 3GPP, 2 -- 3GPP2.*/
+ E_QSER_NW_RADIO_TECH_TYPE_T radio_tech; /**< Radio technology; see #nw_radio_tech_t_v01.*/
+ char mcc[3+1]; /**< Mobile country code.*/
+ char mnc[3+1]; /**< Mobile network code.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming; /**< 0 -- Off, 1 -- Roaming (3GPP2 has extended values).*/
+ uint8_t forbidden; /**< Forbidden: 0 -- No, 1 -- Yes.*/
+ uint32_t cid; /**< Cell ID for the registered 3GPP system.*/
+ uint16_t lac; /**< Locatin area code for the registered 3GPP system.*/
+ uint16_t psc; /**< Primary scrambling code (WCDMA only); 0 -- None.*/
+ uint16_t tac; /**< Tracking area code information for LTE.*/
+}QSER_NW_3GPP_REG_INFO_T;
+
+
+typedef struct
+{
+ E_QSER_NW_TECH_DOMAIN_TYPE_T tech_domain; /**< Technology, used to determine structure type tech: 0 -- None, 1 -- 3GPP, 2 -- 3GPP2.*/
+ E_QSER_NW_RADIO_TECH_TYPE_T radio_tech; /**< Radio technology; see #nw_radio_tech_t_v01.*/
+ char mcc[3+1]; /**< Mobile country code.*/
+ char mnc[3+1]; /**< Mobile network code.*/
+ E_QSER_NW_ROAM_STATE_TYPE_T roaming; /**< Roaming status; see #nw_roam_state_t_v01.*/
+ uint8_t forbidden; /**< Forbidden: 0 -- No, 1 -- Yes.*/
+ uint8_t inPRL; /**< 0 -- Not in PRL, 1 -- In PRL.*/
+ uint8_t css; /**< Concurrent services supported: 0 -- No, 1 -- Yes.*/
+ uint16_t sid; /**< CDMA system ID.*/
+ uint16_t nid; /**< CDMA network ID.*/
+ uint16_t bsid; /**< Base station ID. @newpagetable */
+}QSER_NW_3GPP2_REG_INFO_T;
+
+/** Gets the status associated with the connection of \<id\>. */
+typedef struct
+{
+ uint8_t voice_registration_valid; /**< Must be set to TRUE if voice_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T voice_registration; /**< Voice registration. */
+
+ uint8_t data_registration_valid; /**< Must be set to TRUE if data_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T data_registration; /**< Data registration. */
+
+ uint8_t voice_registration_details_3gpp_valid; /**< Must be set to TRUE if voice_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T voice_registration_details_3gpp; /**< Voice registration details for 3GPP. */
+
+ uint8_t data_registration_details_3gpp_valid; /**< Must be set to TRUE if data_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T data_registration_details_3gpp; /**< Data registration details for 3GPP. */
+
+ uint8_t voice_registration_details_3gpp2_valid; /**< Must be set to TRUE if voice_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T voice_registration_details_3gpp2; /**< Voice registration details for 3GPP2. */
+
+ uint8_t data_registration_details_3gpp2_valid; /**< Must be set to TRUE if data_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T data_registration_details_3gpp2; /**< Data registration details for 3GPP2. */
+}QSER_NW_REG_STATUS_INFO_T;
+
+typedef enum
+{
+ E_QSER_NW_IMS_SERVICE_NONE = 0x0000, /**< Not registered */
+ E_QSER_NW_IMS_SERVICE_REGISTERED = 0x0001, /**< Registered*/
+}E_QSER_NW_IMS_SERVICE_TYPE_T;
+
+typedef struct
+{
+ E_QSER_NW_IMS_SERVICE_TYPE_T registration_state; /**< Registration state.*/
+}QSER_NW_IMS_REG_STATUS_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates received signal strength. A signed value; -125 or lower indicates no signal.*/
+}QSER_NW_GSM_SIGNAL_INFO_T;
+
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Ec. A signed value; -125 or lower indicates no signal.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+}QSER_NW_WCDMA_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Ec. a signed value; -125 or lower indicates no signal.*/
+ int8_t rscp; /**< RSCP in dBm.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+ int8_t sinr; /**< Measured SINR in dB. @newpagetable */
+}QSER_NW_TDSCDMA_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Ec. A signed value; -125 or lower indicates no signal.*/
+ int8_t rsrq; /**< RSRQ value in dB (signed integer value), as measured by L1. Range: -3 to -20 (-3 equals -3 dB, -20 equals -20 dB).*/
+ int16_t rsrp; /**< Current RSRP in dBm, as measured by L1. Range: -44 to -140 (-44 equals -44 dBm, -140 equals -140 dBm).*/
+ int16_t snr; /**< SNR level as a scaled integer in units of 0.1 dB; e.g., -16 dB has a value of -160 and 24.6 dB has a value of 246.*/
+}QSER_NW_LTE_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Power (AGC) + Ec/Io. A signed value; -125 or lower indicates no signal.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+}QSER_NW_CDMA_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int8_t rssi; /**< RSSI in dBm. Indicates forward link pilot Power (AGC) + Ec/Io. A signed value; -125 or lower indicates no signal.*/
+ int16_t ecio; /**< Ec/Io value representing negative 0.5 dB increments, e.g., 2 equals -1 dbm.*/
+ int8_t sinr; /**< SINR level.*/
+ int32_t io; /**< Received IO in dBm. */
+}QSER_NW_HDR_SIGNAL_INFO_T;
+
+typedef struct
+{
+ int16_t ssRsrp; /* SS(Synchronization Signal) reference signal received power, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [44, 140], INT_MAX means invalid/unreported.*/
+ int16_t ssRsrq; /* SS reference signal received quality, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [3, 20], INT_MAX means invalid/unreported.*/
+ int16_t ssSinr; /* SS signal-to-noise and interference ratio.
+ * Reference: 3GPP TS 38.215 section 5.1.*, 3GPP TS 38.133 section 10.1.16.1.
+ * Range [-23, 40], INT_MAX means invalid/unreported.*/
+ int16_t csiRsrp; /* CSI reference signal received power, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [44, 140], INT_MAX means invalid/unreported.*/
+ int16_t csiRsrq; /* CSI reference signal received quality, multipled by -1.
+ * Reference: 3GPP TS 38.215.
+ * Range [3, 20], INT_MAX means invalid/unreported.*/
+ int16_t csiSinr; /* CSI signal-to-noise and interference ratio.
+ * Reference: 3GPP TS 138.215 section 5.1.*, 3GPP TS 38.133 section 10.1.16.1.
+ * Range [-23, 40], INT_MAX means invalid/unreported.*/
+}QSER_NW_NR_SIGNAL_INFO_T;
+
+
+/** Gets signal strength information. */
+typedef struct
+{
+ uint8_t gsm_sig_info_valid; /**< Must be set to TRUE if gsm_sig_info is being passed. */
+ QSER_NW_GSM_SIGNAL_INFO_T gsm_sig_info; /**< GSM signal information. */
+ uint8_t wcdma_sig_info_valid; /**< Must be set to TRUE if wcdma_sig_info is being passed. */
+ QSER_NW_WCDMA_SIGNAL_INFO_T wcdma_sig_info; /**< WCDMA signal information. */
+ uint8_t tdscdma_sig_info_valid; /**< Must be set to TRUE if tdscdma_sig_info is being passed. */
+ QSER_NW_TDSCDMA_SIGNAL_INFO_T tdscdma_sig_info; /**< TDSCDMA signal information. */
+ uint8_t lte_sig_info_valid; /**< Must be set to TRUE if lte_sig_info is being passed. */
+ QSER_NW_LTE_SIGNAL_INFO_T lte_sig_info; /**< LTE signal information. */
+ uint8_t cdma_sig_info_valid; /**< Must be set to TRUE if cdma_sig_info is being passed. */
+ QSER_NW_CDMA_SIGNAL_INFO_T cdma_sig_info; /**< CDMA signal information. */
+ uint8_t hdr_sig_info_valid; /**< Must be set to TRUE if hdr_sig_info is being passed. */
+ QSER_NW_HDR_SIGNAL_INFO_T hdr_sig_info; /**< HDR signal information. */
+ uint8_t nr_sig_info_valid;
+ QSER_NW_NR_SIGNAL_INFO_T nr_sig_info;
+}QSER_NW_SIGNAL_STRENGTH_INFO_T;
+
+
+
+
+
+/* @bridef Callback function registered to QSER_NW_AddRxMsgHandler
+ * map of ind_flag and ind_msg_buf as bellow :
+ * NW_IND_VOICE_REG_EVENT_IND_FLAG : QSER_NW_VOICE_REG_EVENT_IND_T
+ * NW_IND_DATA_REG_EVENT_IND_FLAG : QSER_NW_DATA_REG_EVENT_IND_T
+ * NW_IND_SIGNAL_STRENGTH_EVENT_IND_FLAG : QSER_NW_SINGNAL_EVENT_IND_T
+ * NW_IND_CELL_ACCESS_STATE_CHG_EVENT_IND_FLAG : QSER_NW_CELL_ACCESS_STATE_EVENT_IND_T
+ * NW_IND_NITZ_TIME_UPDATE_EVENT_IND_FLAG : QSER_NW_NITZ_TIME_EVENT_IND_T
+ * NW_IND_IMS_REG_EVENT_IND_FLAG : NULL
+ * */
+typedef void (*QSER_NW_RxMsgHandlerFunc_t)(
+ nw_client_handle_type h_nw,
+ uint32_t ind_flag,
+ void *ind_msg_buf,
+ uint32_t ind_msg_len,
+ void *contextPtr
+);
+
+
+/** Indication message; Indication for the corresponding registered event flag NW_IND_VOICE_REG_EVENT_IND_FLAG */
+typedef struct {
+
+ uint8_t registration_valid; /**< Must be set to TRUE if voice_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T registration; /**< Voice registration. */
+
+ uint8_t registration_details_3gpp_valid; /**< Must be set to TRUE if voice_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T registration_details_3gpp; /**< Voice registration details for 3GPP. */
+
+ uint8_t registration_details_3gpp2_valid; /**< Must be set to TRUE if voice_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T registration_details_3gpp2; /**< Voice registration details for 3GPP2. */
+}QSER_NW_VOICE_REG_EVENT_IND_T;
+
+/** Indication message; Indication for the corresponding registered event flag NW_IND_DATA_REG_EVENT_IND_FLAG */
+typedef struct {
+
+ uint8_t registration_valid; /**< Must be set to TRUE if data_registration is being passed. */
+ QSER_NW_COMMON_REG_INFO_T registration; /**< Data registration. */
+
+ uint8_t registration_details_3gpp_valid; /**< Must be set to TRUE if data_registration_details_3gpp is being passed. */
+ QSER_NW_3GPP_REG_INFO_T registration_details_3gpp; /**< Data registration details for 3GPP. */
+
+ uint8_t registration_details_3gpp2_valid; /**< Must be set to TRUE if data_registration_details_3gpp2 is being passed. */
+ QSER_NW_3GPP2_REG_INFO_T registration_details_3gpp2; /**< Data registration details for 3GPP2. */
+}QSER_NW_DATA_REG_EVENT_IND_T;
+
+
+/** Indication message; Indication for the corresponding registered event flag NW_IND_SIGNAL_STRENGTH_EVENT_IND_FLAG */
+typedef struct {
+ uint8_t gsm_sig_info_valid; /**< Must be set to TRUE if gsm_sig_info is being passed. */
+ QSER_NW_GSM_SIGNAL_INFO_T gsm_sig_info; /**< GSM singal information. */
+
+ uint8_t wcdma_sig_info_valid; /**< Must be set to TRUE if wcdma_sig_info is being passed. */
+ QSER_NW_WCDMA_SIGNAL_INFO_T wcdma_sig_info; /**< WCDMA singal information. */
+
+ uint8_t tdscdma_sig_info_valid; /**< Must be set to TRUE if tdscdma_sig_info is being passed. */
+ QSER_NW_TDSCDMA_SIGNAL_INFO_T tdscdma_sig_info; /**< TDSCDMA singal information. */
+
+ uint8_t lte_sig_info_valid; /**< Must be set to TRUE if lte_sig_info is being passed. */
+ QSER_NW_LTE_SIGNAL_INFO_T lte_sig_info; /**< LTE singal information. */
+
+ uint8_t cdma_sig_info_valid; /**< Must be set to TRUE if cdma_sig_info is being passed. */
+ QSER_NW_CDMA_SIGNAL_INFO_T cdma_sig_info; /**< CDMA singal information. */
+
+ uint8_t hdr_sig_info_valid; /**< Must be set to TRUE if hdr_sig_info is being passed. */
+ QSER_NW_HDR_SIGNAL_INFO_T hdr_sig_info; /**< HDR singal information. */
+
+ uint8_t nr_sig_info_valid;
+ QSER_NW_NR_SIGNAL_INFO_T nr_sig_info;
+}QSER_NW_SINGNAL_EVENT_IND_T;
+
+typedef enum
+{
+ E_QSER_NW_RF_MODE_CFUN_0 = 0, /**< CFUN 0. */
+ E_QSER_NW_RF_MODE_CFUN_1 = 1, /**< CFUN 1. */
+ E_QSER_NW_RF_MODE_FLIGHT = 4, /**< Flight Mode, CFUN 4. */
+}E_QSER_NW_RF_MODE_TYPE_T;
+
+int qser_nw_client_init(nw_client_handle_type *ph_nw);
+
+int qser_nw_client_deinit(nw_client_handle_type h_nw);
+
+int qser_nw_set_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_get_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_set_ims_enable
+(
+ nw_client_handle_type h_nw,
+ E_QSER_NW_IMS_MODE_TYPE_T ims_mode
+);
+
+int qser_nw_set_oos_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_OOS_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_get_oos_config
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_OOS_CONFIG_INFO_T *pt_info
+);
+
+int qser_nw_event_register
+(
+ nw_client_handle_type h_nw,
+ uint32_t bitmask // bit OR of NW_IND_xxxx_EVENT_ON
+);
+
+int qser_nw_get_operator_name
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_OPERATOR_NAME_INFO_T *pt_info //You should malloc this or may cause stack overflow
+);
+
+int qser_nw_get_reg_status
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_REG_STATUS_INFO_T *pt_info
+);
+
+int qser_nw_get_ims_reg_status
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_IMS_REG_STATUS_INFO_T *pt_info
+);
+
+int qser_nw_get_signal_strength
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_SIGNAL_STRENGTH_INFO_T *pt_info
+);
+
+int qser_nw_add_rx_msg_handler
+(
+ nw_client_handle_type h_nw,
+ QSER_NW_RxMsgHandlerFunc_t handlerPtr,
+ void* contextPtr
+);
+
+int qser_nw_set_rf_mode
+(
+ nw_client_handle_type h_nw,
+ E_QSER_NW_RF_MODE_TYPE_T rf_mode
+);
+
+int qser_nw_get_rf_mode
+(
+ nw_client_handle_type h_nw,
+ E_QSER_NW_RF_MODE_TYPE_T *rf_mode
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif//__QSER_NW_H__
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
new file mode 100755
index 0000000..e7eebc3
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-qser-voice-demo/files/lynq-qser-voice-demo.cpp
@@ -0,0 +1,452 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <pthread.h>
+#include <unistd.h>
+#include <dlfcn.h>
+#include <stdint.h>
+
+#include"lynq-qser-voice-demo.h"
+
+typedef struct
+{
+ int cmdIdx;
+ char *funcName;
+} st_api_test_case;
+
+//for server test
+st_api_test_case at_api_testcases[] =
+{
+ {0, "print_help"},
+ {1, "qser_voice_call_start"},
+ {2, "qser_voice_call_end"},
+ {3, "qser_voice_call_answer"},
+ {4, "qser_voice_set_speech_volume"},
+ {5, "qser_voice_get_speech_volume"},
+ {6, "qser_voice_set_dtmf"},
+#ifdef ECALL_SUPPORT
+ {7, "qser_voice_set_test_num"},
+ {8, "qser_voice_fast_ecall"},
+#endif
+ {9, "qser_voice_set_audio_mode"},
+ {10, "qser_voice_get_audio_mode"},
+ {-1, NULL}
+};
+
+typedef uint32_t voice_client_handle_type;
+
+
+int (*qser_voice_call_client_init)(voice_client_handle_type *ph_voice);
+int (*qser_voice_call_client_deinit)(voice_client_handle_type );
+int (*qser_voice_call_addstatehandler)(voice_client_handle_type h_voice,
+ QSER_VoiceCall_StateHandlerFunc_t handlerPtr,
+ void *contextPtr);
+
+int (*qser_voice_call_removestatehandle)(voice_client_handle_type );
+int (*qser_voice_call_start)(voice_client_handle_type h_voice,
+ E_QSER_VCALL_ID_T simId,
+ char *phone_number, int *call_id);
+
+int (*qser_voice_call_end)(voice_client_handle_type ,int );
+int (*qser_voice_call_answer)(voice_client_handle_type ,int );
+int (*qser_voice_set_speech_volume)(const int volume);
+int (*qser_voice_get_speech_volume)(int *volume);
+int (*qser_voice_set_dtmf)(const char callnum);
+int (*qser_voice_set_audio_mode)(const int audio_mode);
+int (*qser_voice_get_audio_mode)(int* audio_mode);
+
+
+#ifdef ECALL_SUPPORT
+int (*qser_voice_set_test_num)(voice_client_handle_type* h_voice,E_QSER_VOICE_ECALL_SET_TYPE_T type, const char *test_num, int test_num_length);
+int (*qser_voice_fast_ecall)(voice_client_handle_type* h_voice,
+ int *call_id,
+ E_QSER_VOICE_ECALL_CATEGORY_T cat,
+ E_QSER_VOICE_ECALL_VARIANT_T variant,
+ const char *addr,
+ int addr_length,
+ const unsigned char *msd_data,
+ int msd_length); //msd_length should <= QSER_MSD_MAX_LENGTH
+int (*qser_voice_set_msd)(int callid, const unsigned char *msd_data, int msd_length); //msd_length should <= QSER_MSD_MAX_LENGTH
+int (*qser_voice_add_ecall_indhandler)(voice_client_handle_type* h_voice,
+ QSER_ECall_IndHandlerFunc_t handlerPtr,
+ void* contextPtr);
+
+static void yk_voice_ecall_cb_func(int callid, E_QSER_VOICE_ECALL_INDICATION_T ind, void* contextPtr)
+{
+ unsigned char msd_data[QSER_MSD_MAX_LENGTH]={1,1,2,2,3,3,4,4};
+
+ printf("######### Call id=%d, event=%d! ######\n", callid, ind);
+
+ if(ind == E_QSER_VOICE_ECALL_IND_SENDING_START_IN_VOICE || ind == E_QSER_VOICE_ECALL_IND_PSAP_CALLBACK_START)
+ {
+ /*customer should construct msd including GPS data, here use msd_data for illustrate,*/
+ qser_voice_set_msd(callid,msd_data,8);
+ }
+}
+
+#endif
+
+
+void *dlHandle_call = NULL;
+
+static void yk_voice_call_cb_func(int call_id,
+ char* phone_num,
+ qser_voice_call_state_t state,
+ void *contextPtr)
+{
+ char *call_state[] = {"INCOMING", "DIALING", "ALERTING", "ACTIVE", "HOLDING", "END", "WAITING"};
+
+ printf("######### Call id=%d, PhoneNum:%s, event=%s! ######\n", call_id, phone_num, call_state[state]);
+}
+
+
+
+void print_help(void)
+{
+ int i;
+ printf("Supported test cases:\n");
+ for(i = 0; ; i++)
+ {
+ if(at_api_testcases[i].cmdIdx == -1)
+ {
+ break;
+ }
+ printf("%d:\t%s\n", at_api_testcases[i].cmdIdx, at_api_testcases[i].funcName);
+ }
+}
+
+
+
+int main(int argc, char const *argv[])
+{
+ int cmdIdx = 0;
+ int ret = 0;
+ int voice_call_id = 0;
+ voice_client_handle_type h_voice = 0;
+ int audio_mode = 0;
+
+ const char *lynqLibPath_Call = "/lib/liblynq-qser-voice.so";
+ dlHandle_call = dlopen(lynqLibPath_Call, RTLD_NOW);
+ if (dlHandle_call == NULL)
+ {
+ printf("dlopen dlHandle_call failed: %s\n", dlerror());
+ exit(EXIT_FAILURE);
+ }
+
+ qser_voice_call_client_init = (int(*)(voice_client_handle_type *ph_voice))dlsym(dlHandle_call, "qser_voice_call_client_init");
+ if(qser_voice_call_client_init == NULL)
+ {
+ printf("qser_voice_call_client_init not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_addstatehandler = (int(*)(voice_client_handle_type h_voice,
+ QSER_VoiceCall_StateHandlerFunc_t handlerPtr,
+ void *contextPtr))dlsym(dlHandle_call,"qser_voice_call_addstatehandler");
+ if(qser_voice_call_addstatehandler == NULL)
+ {
+ printf("qser_voice_call_addstatehandler not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_answer = (int(*)(voice_client_handle_type,int ))dlsym(dlHandle_call,"qser_voice_call_answer");
+ if(qser_voice_call_answer == NULL)
+ {
+ printf("qser_voice_call_answer not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_start = (int(*)(voice_client_handle_type h_voice,E_QSER_VCALL_ID_T simId,
+ char *phone_number, int *call_id))dlsym(dlHandle_call,"qser_voice_call_start");
+ if(qser_voice_call_start == NULL)
+ {
+ printf("qser_voice_call_start not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_end = (int(*)(voice_client_handle_type ,int))dlsym(dlHandle_call,"qser_voice_call_end");
+ if(qser_voice_call_end == NULL)
+ {
+ printf("qser_voice_call_end not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+
+ qser_voice_call_client_deinit = (int (*)(voice_client_handle_type h_voice))dlsym(dlHandle_call,"qser_voice_call_client_deinit");
+ if(qser_voice_call_client_deinit == NULL)
+ {
+ printf("qser_voice_call_client_deinit not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_call_removestatehandle = (int (*)(voice_client_handle_type))dlsym(dlHandle_call,"qser_voice_call_removestatehandle");
+ if(qser_voice_call_removestatehandle == NULL)
+ {
+ printf("qser_voice_call_removestatehandle not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_speech_volume = (int (*)(const int ))dlsym(dlHandle_call,"qser_voice_set_speech_volume");
+ if(qser_voice_set_speech_volume == NULL)
+ {
+ printf("qser_voice_set_speech_volume not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_get_speech_volume = (int (*)(int* ))dlsym(dlHandle_call,"qser_voice_get_speech_volume");
+ if(qser_voice_get_speech_volume == NULL)
+ {
+ printf("qser_voice_get_speech_volume not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_dtmf = (int (*)(const char ))dlsym(dlHandle_call,"qser_voice_set_dtmf");
+ if(qser_voice_set_dtmf == NULL)
+ {
+ printf("qser_voice_set_dtmf not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+#ifdef ECALL_SUPPORT
+ qser_voice_fast_ecall = (int (*)(voice_client_handle_type*, int*, E_QSER_VOICE_ECALL_CATEGORY_T, E_QSER_VOICE_ECALL_VARIANT_T, const char*, int, const unsigned char*, int))dlsym(dlHandle_call,"qser_voice_fast_ecall");
+ if(qser_voice_fast_ecall == NULL)
+ {
+ printf("qser_voice_fast_ecall not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_test_num = (int (*)(voice_client_handle_type*, E_QSER_VOICE_ECALL_SET_TYPE_T, const char* , int))dlsym(dlHandle_call,"qser_voice_set_test_num");
+ if(qser_voice_set_test_num == NULL)
+ {
+ printf("qser_voice_set_test_num not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_set_msd = (int (*)(int , const unsigned char *, int))dlsym(dlHandle_call,"qser_voice_set_msd");
+ if(qser_voice_set_msd == NULL)
+ {
+ printf("qser_voice_set_msd not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+ qser_voice_add_ecall_indhandler = (int (*)(voice_client_handle_type* h_voice, QSER_ECall_IndHandlerFunc_t, void*))dlsym(dlHandle_call,"qser_voice_add_ecall_indhandler");
+ if(qser_voice_add_ecall_indhandler == NULL)
+ {
+ printf("qser_voice_add_ecall_indhandler not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+#endif
+
+ qser_voice_set_audio_mode = (int(*)(const int audio_mode))dlsym(dlHandle_call, "qser_voice_set_audio_mode");
+ if(qser_voice_set_audio_mode == NULL)
+ {
+ printf("qser_voice_set_audio_mode not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+
+ qser_voice_get_audio_mode = (int(*)(int* audio_mode))dlsym(dlHandle_call, "qser_voice_get_audio_mode");
+ if(qser_voice_get_audio_mode == NULL)
+ {
+ printf("qser_voice_get_audio_mode not defined or exported in %s\n", lynqLibPath_Call);
+ return -1;
+ }
+
+
+ ret = qser_voice_call_client_init(&h_voice);
+ if(ret != 0 )
+ {
+ printf("qser_voice_call_client_init FAIL\n");
+ return -1;
+ }
+
+ ret = qser_voice_call_addstatehandler(h_voice, yk_voice_call_cb_func, &voice_call_id);
+ if(ret != 0)
+ {
+ printf("qser_voice_call_addstatehandler FAIL\n");
+ return -1;
+ }
+
+#ifdef ECALL_SUPPORT
+ ret = qser_voice_add_ecall_indhandler(&h_voice, yk_voice_ecall_cb_func, NULL);
+ if(ret != 0)
+ {
+ printf("qser_voice_add_ecall_indhandler FAIL\n");
+ return -1;
+ }
+#endif
+
+ print_help();
+ while(1)
+ {
+ printf("\nplease input cmd index(-1 exit): ");
+ scanf("%d", &cmdIdx);
+ if(cmdIdx == -1)
+ {
+ break;
+ }
+
+ switch(cmdIdx)
+ {
+ //"print_help
+ case 0:
+ print_help();
+ break;
+
+ //"qser_voice_call_start"
+ case 1:
+ {
+ char PhoneNum[32] = {0};
+
+ printf("please input dest phone number: \n");
+ scanf("%s", PhoneNum);
+
+ ret = qser_voice_call_start(h_voice, E_QSER_VCALL_EXTERNAL_SLOT_1, PhoneNum, &voice_call_id);
+ printf("qser_voice_call_start ret = %d, with voice_call_id=%d\n", ret, voice_call_id);
+ break;
+ }
+
+ //"qser_voice_call_end"
+ case 2:
+ {
+ int call_id = -1;
+ printf("please input end call id: \n");
+ scanf("%d", &call_id);
+ ret = qser_voice_call_end(h_voice, call_id);
+ printf(" ret = %d\n", ret);
+ break;
+ }
+
+ //"qser_voice_call_answer"
+ case 3:
+ {
+ int call_id = -1;
+ printf(" please input answer call id\n");
+ scanf("%d", &call_id);
+ ret = qser_voice_call_answer(h_voice, call_id);
+ printf(" ret = %d\n", ret);
+ break;
+ }
+
+ case 4:
+ {
+ int volume = 0;
+ printf("Please set speech volume:0-5 level\n");
+ scanf("%d",&volume);
+ ret = qser_voice_set_speech_volume(volume);
+ printf("ret is %d\n",ret);
+ break;
+
+ }
+
+ case 5:
+ {
+ int volume = -1;
+ printf("Enter get speech volume\n");
+ ret = qser_voice_get_speech_volume(&volume);
+ printf("ret is %d,get volume is %d\n",ret,volume);
+ break;
+
+ }
+ case 6:
+ {
+
+ int ret;
+ char inputChar;
+
+ printf("Enter set dtmf\n");
+ scanf(" %c", &inputChar);
+ printf("inputChar is %c\n", inputChar);
+ ret = qser_voice_set_dtmf(inputChar);
+
+ if (ret != 0)
+ {
+ printf("qser set voice dtmf failed\n");
+ return -1;
+ }
+ break;
+ }
+#ifdef ECALL_SUPPORT
+ case 7:
+ {
+ char PhoneNum[32] = {0};
+ printf("please input test phone number(input null means \"\"): \n");
+ scanf("%s", PhoneNum);
+ if(0 == strcmp(PhoneNum, "null"))
+ {
+ PhoneNum[0]='\0';
+ }
+ ret = qser_voice_set_test_num(&h_voice, E_QSER_VOICE_ECALL_SET_NUMBER, PhoneNum, strlen(PhoneNum)+1);
+ printf("qser_voice_set_test_num ret = %d\n", ret);
+ break;
+ }
+ case 8:
+ {
+ int call_id = -1;
+ int cat;
+ int var;
+ int length;
+ unsigned char msd[QSER_MSD_MAX_LENGTH]={0};
+
+ printf("please input ecall cat: 0 manual, 1 auto\n");
+ scanf("%d", &cat);
+ printf("please input ecall type: 0 test, 1 emergency\n");
+ scanf("%d", &var);
+ printf("please input msd content length (max length is 140)\n");
+ scanf("%d", &length);
+ printf("please input %d unsigned char (0-255):\n", length);
+ for (int i = 0; i < length; i++) {
+ scanf("%hhu", &msd[i]);
+ }
+ ret = qser_voice_fast_ecall(&h_voice, &call_id, (E_QSER_VOICE_ECALL_CATEGORY_T) cat, (E_QSER_VOICE_ECALL_VARIANT_T) var, "null",5,msd,length);
+ printf("qser_voice_fast_ecall ret = %d, call id is %d\n", ret, call_id);
+ break;
+ }
+#endif
+ case 9:
+ {
+
+ printf("please input voice audio mode: 0 codec, 1 rtp\n");
+ scanf("%d", &audio_mode);
+ ret = qser_voice_set_audio_mode(audio_mode);
+ printf("qser_voice_set_audio_mode ret = %d, audio_mode is %d\n", ret, audio_mode);
+ break;
+ }
+ case 10:
+ {
+ ret = qser_voice_get_audio_mode(&audio_mode);
+ printf("qser_voice_get_audio_mode ret = %d, audio_mode is %d\n", ret, audio_mode);
+ break;
+ }
+
+ default:
+ print_help();
+ break;
+ }
+
+ }
+
+ ret = qser_voice_call_removestatehandle(h_voice);
+ if(ret != 0 && ret != 1)
+ {
+ printf("qser_voice_call_removestatehandle FAIL!!!\n");
+ return -1;
+ }
+ printf("qser_voice_call_removestatehandle ret = %d\n", ret);
+
+
+ ret = qser_voice_call_client_deinit(h_voice);
+ if(ret != 0)
+ {
+ printf("qser_voice_call_client_deinit FAIL\n");
+ return -1;
+ }
+ printf("qser_voice_call_client_deinit ret = %d, with h_voice=%d\n", ret, h_voice);
+
+ return 0;
+
+
+}
+
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
new file mode 100755
index 0000000..fc94d2a
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/lynq_vb_demo.c
@@ -0,0 +1,770 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+//#include "voice_ipc.h"
+
+#define _USE_VOICE_BUFFER
+#include "voice_lib.h"
+#include <fcntl.h>
+#include <signal.h>
+#include <semaphore.h>
+#include <sys/types.h>
+#include <pthread.h>
+
+/*command max len*/
+#define VOICE_CMD_MAX_LEN 64
+
+#define EXIT_CMD_STOP "stop\n"
+#define EXIT_CMD_Q "q\n"
+#define EXIT_CMD_EXIT "exit\n"
+
+#define REQ_VOICE_BUFFER_TEST_START "voice_buffer_test_start"
+#define REQ_VOICE_BUFFER_TEST_STOP "voice_buffer_test_stop"
+#define REQ_VOICE_BUFFER_LOOP_TEST_START "voice_buffer_loop_test_start"
+#define REQ_VOICE_BUFFER_LOOP_TEST_STOP "voice_buffer_loop_test_stop"
+#define REQ_VOICE_BUFFER_RTP_TEST_START "voice_buffer_rtp_test_start"
+#define REQ_VOICE_BUFFER_RTP_TEST_STOP "voice_buffer_rtp_test_stop"
+
+
+
+#define VBUFFER_TX_FILE_NAME "/mnt/userdata/tx.pcm"
+#define VBUFFER_RX_FILE_NAME "/mnt/userdata/rx.pcm"
+#define VBUFFER_TX16_FILE_NAME "/mnt/userdata/tx16.pcm"
+#define VBUFFER_RX16_FILE_NAME "/mnt/userdata/rx16.pcm"
+
+
+
+#define VB_MAX_INT 0x7fffffff
+#define VB_MIN_INT 0
+#define VB_INT_OVERFLOW(x) if((x < VB_MIN_INT)||(x > VB_MAX_INT)) x = 0;
+
+#define RX_FILE_LEN_MAX 0x100000
+
+
+
+typedef int (vb_thread_proc)(void*);
+struct vbuf_info_t
+{
+ int fd;
+ pthread_t rx_test_thread;
+ pthread_t tx_test_thread;
+ pthread_t loop_test_thread;
+ int quit;
+ char *tx_buf;
+ char *rx_buf;
+ int buf_size;
+ char *tx_filename;
+ char *rx_filename;
+ FILE *tx_file;
+ FILE *rx_file;
+ int tx_filesize;
+ int rx_filesize;
+ int fs;
+};
+
+static struct vbuf_info_t vbuf_rec;
+
+static void printUsage(const char *Opt)
+{
+ printf("Usage: %s\n", Opt);
+
+ printf("voice_buffer_test_start value: 8000,16000\n");
+ printf("voice_buffer_test_stop no value input\n");
+ printf("voice_buffer_loop_test_start value: 8000,16000\n");
+ printf("voice_buffer_loop_test_stop no value input\n");
+ printf("\n");
+}
+
+static int vbuffer_start_flag = 0;
+static int tx_optcount = 0;
+static int rx_optcount = 0;
+static int first_rderr_flag = 0;
+static int first_wrerr_flag = 0;
+
+static int vb_close_fd_release_buf()
+{
+ int ret = voice_buffer_close(vbuf_rec.fd);
+ if(ret != 0)
+ {
+ printf("%s : vb close fail \n",__func__);
+ }
+ vbuf_rec.fd = -1;
+
+ if(vbuf_rec.rx_buf)
+ {
+ free(vbuf_rec.rx_buf);
+ vbuf_rec.rx_buf = NULL;
+ }
+
+ if(vbuf_rec.tx_buf)
+ {
+ free(vbuf_rec.tx_buf);
+ vbuf_rec.tx_buf = NULL;
+ }
+
+ vbuffer_start_flag = 0;
+ printf("close buf fd and release buf end\n");
+ return ret;
+}
+
+
+
+//whole rx path
+static int vb_rx_test_thread_func(void *arg)
+{
+ int ret;
+
+ char* buf = vbuf_rec.rx_buf;
+ int size = vbuf_rec.buf_size;
+ int bytes_read = 0;
+ int r_size;
+
+
+ printf( "%s: start size=%d! \n",__func__,size);
+ memset (buf,0, size);
+
+ while (!vbuf_rec.quit)
+ {
+ rx_optcount ++;
+ VB_INT_OVERFLOW(rx_optcount);
+ if((rx_optcount%1000) == 0){
+ printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+
+ }
+ else if(rx_optcount == 1000000){
+ printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+ rx_optcount = 0;
+
+ }
+
+ //read form ps
+ r_size = voice_buffer_read(vbuf_rec.fd, buf, size);
+ if(r_size <= 0)
+ {
+ first_rderr_flag++;
+ VB_INT_OVERFLOW(first_rderr_flag);
+ continue ;
+ }
+ else{
+ first_rderr_flag = 0;
+
+ }
+
+ if(vbuf_rec.rx_file != NULL)
+ {
+ r_size = fwrite(buf, 1,size, vbuf_rec.rx_file);
+
+ if (r_size != size) {
+ //printf("Error fwrite size not eq,r_size=%d,size=%d\n",r_size,size);
+ }
+ else{
+
+ bytes_read += size;
+ if(bytes_read >= vbuf_rec.rx_filesize){
+ fseek(vbuf_rec.rx_file, 0, SEEK_SET);
+ bytes_read = 0;
+ printf("fwrite over write maxsize(%d)!!!\n",vbuf_rec.rx_filesize);
+
+ }
+ }
+ }
+
+
+ }
+
+ return 0;
+}
+
+static int vb_tx_test_thread_func(void *arg)
+{
+ int ret;
+ int num_read;
+
+
+ char* buf = vbuf_rec.tx_buf;
+
+ int size = vbuf_rec.buf_size;
+ int w_size;
+
+ printf("%s: start size=%d! \n",__func__,size);
+
+
+ memset(buf, 0,size);
+ while (!vbuf_rec.quit)
+ {
+
+ if(vbuf_rec.tx_file != NULL)
+ {
+
+ num_read = fread(buf,1,size, vbuf_rec.tx_file);
+
+ if (num_read != size) {
+ //printf("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
+ }
+ if (num_read <= 0) {
+ printf("Error fread size not eq,num_read=%d,size=%d\n",num_read,size);
+ fseek(vbuf_rec.tx_file, 0, SEEK_SET);
+ }
+ }
+ tx_optcount ++;
+ VB_INT_OVERFLOW(tx_optcount);
+
+ w_size = voice_buffer_write(vbuf_rec.fd, buf, size);
+ if(w_size <= 0)
+ {
+ first_wrerr_flag++;
+
+ VB_INT_OVERFLOW(first_wrerr_flag);
+
+ continue;
+ }
+ else{
+ first_wrerr_flag = 0;
+
+ }
+
+ }
+ return 0;
+}
+
+
+static int vb_thread_create( const char *name,pthread_t *thread_t, vb_thread_proc *proc,
+ int stack_size, unsigned priority,void *arg )
+{
+ pthread_attr_t thread_attr;
+ int ret;
+ int default_size;
+
+ struct sched_param param;
+ int policy = SCHED_FIFO;
+
+ printf("%s: start! \n",__func__);
+
+ /* Init thread attributes */
+ pthread_attr_init(&thread_attr);
+ /* Create the thread. */
+
+ ret = pthread_create( thread_t, &thread_attr,proc, arg);
+ if (ret != 0)
+ {
+ printf("%s: pthread_create fail,ret=%d! \n",__func__,ret);
+
+ pthread_attr_destroy(&thread_attr);
+ return ret;
+ }
+
+ pthread_attr_getstacksize(&thread_attr, &default_size);
+ printf("%s: pthread_attr_getstacksize(%d)! \n",__func__,default_size);
+
+ pthread_attr_destroy(&thread_attr);
+
+ printf("%s: end \n",__func__);
+ return 0;
+}
+
+
+int voice_buffer_stream_test_stop(void);
+
+int voice_buffer_stream_test_start(int fs)
+{
+ int ret = 0;
+ int buf_size = 320;
+ tx_optcount = 0;
+ rx_optcount = 0;
+ int* buf_int;
+
+ int i;
+
+ if(vbuffer_start_flag == 1){
+ printf(" VB already start,return \n");
+
+ return 0;
+ }
+
+ vbuffer_start_flag = 1;
+
+
+
+ if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
+ printf(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
+ }
+
+ if(fs == 8000){
+
+ buf_size = 320;
+ }
+ else if(fs == 16000){
+
+ buf_size = 640;
+ }
+ else
+ {
+ buf_size = 320;
+ }
+ printf("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
+
+ printf("%s:open tx and rx file \n",__func__);
+ if(fs == 8000){
+
+ vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
+ vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
+
+ }
+ else if(fs == 16000){
+
+ vbuf_rec.tx_filename = VBUFFER_TX16_FILE_NAME;//"/cache/tx16.pcm";
+ vbuf_rec.rx_filename = VBUFFER_RX16_FILE_NAME;//"/cache/rx16.pcm";
+
+ }
+ else
+ {
+ vbuf_rec.tx_filename = VBUFFER_TX_FILE_NAME;//"/cache/tx.pcm";
+ vbuf_rec.rx_filename = VBUFFER_RX_FILE_NAME;//"/cache/rx.pcm";
+
+ }
+
+
+
+
+ vbuf_rec.tx_file = fopen(vbuf_rec.tx_filename , "rb");
+ if (!vbuf_rec.tx_file) {
+ printf("Unable to open file '%s'\n", vbuf_rec.tx_filename);
+ //return -1;
+ }
+
+
+ vbuf_rec.rx_file = fopen(vbuf_rec.rx_filename, "wb");
+ if (!vbuf_rec.rx_file) {
+ printf(stderr, "Unable to create file '%s'\n", vbuf_rec.rx_filename);
+ //fclose(vbuf_rec.tx_file);
+
+ //return -1;
+ }
+ vbuf_rec.rx_filesize = RX_FILE_LEN_MAX;
+ printf("%s : vbuf_rec.rx_filesize(%d) \n",__func__,vbuf_rec.rx_filesize);
+
+ vbuf_rec.rx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.rx_buf) {
+ printf("%s : malloc buf fail,return \n",__func__);
+ goto err;
+ }
+ vbuf_rec.tx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.tx_buf) {
+ free(vbuf_rec.rx_buf);
+ printf("%s : malloc buf fail,return \n",__func__);
+ vbuf_rec.rx_buf = NULL;
+ goto err;
+ }
+ vbuf_rec.buf_size = buf_size;
+
+ vbuf_rec.quit = 0;
+
+ printf("%s : vb open start \n",__func__);
+
+
+ vbuf_rec.fd = voice_buffer_open();
+ if(vbuf_rec.fd <= 0){
+ printf("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
+ ret = -1;
+ goto err;
+
+ }
+ printf("%s :voice_buffer_open end \n",__func__);
+
+ printf("%s :rx tx vb_thread_create start \n",__func__);
+ ret = vb_thread_create ("vb_playback_test",&vbuf_rec.rx_test_thread, vb_rx_test_thread_func,
+ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+ printf("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ vbuf_rec.rx_test_thread = NULL;
+ goto err;
+ }
+
+ printf("%s :rx vb_thread_create end \n",__func__);
+
+ ret = vb_thread_create ( "vbuf_record_test", &vbuf_rec.tx_test_thread, vb_tx_test_thread_func,
+ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+
+ printf("%s :tx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ vbuf_rec.tx_test_thread = NULL;
+ goto err;
+ }
+ printf("%s :tx vb_thread_create end \n",__func__);
+
+ return 0;
+
+err:
+ voice_buffer_stream_test_stop();
+
+ return ret;
+}
+
+
+//Stop stream
+int voice_buffer_stream_test_stop(void)
+{
+ int ret = 0;
+ printf("%s:rx tx thread exit start \n",__func__);
+ if(vbuf_rec.quit == 1) {
+ printf("%s,already stop ,return\n",__func__);
+
+ }
+
+ vbuf_rec.quit = 1;
+ voice_buffer_stop(vbuf_rec.fd);
+ if (vbuf_rec.tx_test_thread)
+ {
+ pthread_join (vbuf_rec.tx_test_thread,NULL);
+ vbuf_rec.tx_test_thread = NULL;
+
+ }
+
+ if (vbuf_rec.rx_test_thread)
+ {
+ pthread_join (vbuf_rec.rx_test_thread,NULL);
+ vbuf_rec.rx_test_thread = NULL;
+ }
+
+ if(vbuf_rec.tx_file != NULL)
+ {
+ fclose(vbuf_rec.tx_file);
+ printf("%s : vb close ,close tx file \n",__func__);
+ vbuf_rec.tx_file = NULL;
+ }
+
+ if(vbuf_rec.rx_file != NULL)
+ {
+
+ fclose(vbuf_rec.rx_file);
+ printf("%s : vb close ,close rx file \n",__func__);
+ vbuf_rec.rx_file = NULL;
+
+ }
+
+ vb_close_fd_release_buf();
+ return 0;
+}
+
+
+static int vb_loop_test_thread_func(void *arg)
+{
+ int ret;
+
+ char* buf = vbuf_rec.rx_buf;
+ int size = vbuf_rec.buf_size;
+
+ //char* buf = vbuf_rec.tx_buf;
+
+ //int size = vbuf_rec.buf_size;
+ int w_size;
+ int r_size;
+
+
+ printf( "%s: start size=%d! \n",__func__,size);
+ memset (buf,0, size);
+
+ while (!vbuf_rec.quit)
+ {
+ rx_optcount ++;
+ VB_INT_OVERFLOW(rx_optcount);
+ if((rx_optcount%1000) == 0){
+ printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+
+ }
+ else if(rx_optcount == 1000000){
+ printf("%s: rx_optcount=%d! \n",__func__,rx_optcount);
+ rx_optcount = 0;
+
+ }
+
+ //read form ps
+ r_size = voice_buffer_read(vbuf_rec.fd, vbuf_rec.rx_buf, size);
+ if(r_size <= 0)
+ {
+ first_rderr_flag++;
+ VB_INT_OVERFLOW(first_rderr_flag);
+ continue ;
+ }
+ else{
+ first_rderr_flag = 0;
+ }
+ memcpy(vbuf_rec.tx_buf,vbuf_rec.rx_buf,size);
+ w_size = voice_buffer_write(vbuf_rec.fd, vbuf_rec.tx_buf, size);
+ if(w_size <= 0)
+ {
+ first_wrerr_flag++;
+
+ VB_INT_OVERFLOW(first_wrerr_flag);
+
+ continue;
+ }
+ else{
+ first_wrerr_flag = 0;
+ }
+
+ }
+
+ return 0;
+}
+
+
+int voice_buffer_stream_loop_test_stop(void);
+
+int voice_buffer_stream_loop_test_start(int fs)
+{
+ int ret = -1;
+ int buf_size = 320;
+ tx_optcount = 0;
+ rx_optcount = 0;
+ int* buf_int;
+
+ int i;
+
+ if(vbuffer_start_flag == 1){
+ printf(" VB already start,return \n");
+
+ return 0;
+ }
+
+ if((vbuf_rec.fd != -1)&&(vbuf_rec.fd != 0)){
+ printf(" VB fd already get, vbuf_rec.fd=%d return \n",vbuf_rec.fd);
+ }
+
+ vbuffer_start_flag = 1;
+
+ if(fs == 8000){
+
+ buf_size = 320;
+ }
+ else if(fs == 16000){
+
+ buf_size = 640;
+ }
+ else
+ {
+ buf_size = 320;
+ }
+ printf("Starting vb stream fs=%d buf_size=%d \n",fs,buf_size);
+
+ vbuf_rec.rx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.rx_buf) {
+ printf("%s : malloc buf fail,return \n",__func__);
+ goto err;
+ }
+ vbuf_rec.tx_buf = (char*) malloc(buf_size);
+ if(!vbuf_rec.tx_buf) {
+ printf("%s : malloc buf fail,return \n",__func__);
+ goto err;
+ }
+ vbuf_rec.buf_size = buf_size;
+
+ vbuf_rec.quit = 0;
+
+ printf("%s : vb open start \n",__func__);
+
+
+ vbuf_rec.fd = voice_buffer_open();
+ if(vbuf_rec.fd <= 0){
+ printf("%s : vb open fail fd=%d,return \n",__func__,vbuf_rec.fd);
+ goto err;
+
+ }
+ printf("%s :loop vb_thread_create start \n",__func__);
+ ret = vb_thread_create ("vb_playback_test",&vbuf_rec.loop_test_thread, vb_loop_test_thread_func,
+ 4*1024,35,NULL);
+ if (ret != 0)
+ {
+ printf("%s :rx vb_thread_create fail ret=%d,return \n",__func__,ret);
+ goto err;
+ }
+
+ printf("%s :rx vb_thread_create end \n",__func__);
+
+ return 0;
+
+err:
+ voice_buffer_stream_loop_test_stop();
+
+ return ret;
+}
+
+int voice_buffer_stream_loop_test_stop(void)
+{
+ int ret = 0;
+ printf("%s:loop thread exit start \n",__func__);
+ if(vbuf_rec.quit == 1) {
+ printf("%s,already stop ,return\n",__func__);
+
+ }
+
+ vbuf_rec.quit = 1;
+ voice_buffer_stop(vbuf_rec.fd);
+ if (vbuf_rec.loop_test_thread)
+ {
+ pthread_join (vbuf_rec.loop_test_thread,NULL);
+ vbuf_rec.tx_test_thread = NULL;
+
+ }
+
+ vb_close_fd_release_buf();
+ return 0;
+}
+
+int voice_buffer_rtp_test_start(int fs)
+{
+ // refer to voice_buffer_stream_test_start(fs);
+ return 0;
+}
+
+
+
+int voice_buffer_rtp_test_stop(void)
+{
+// refer to voice_buffer_stream_loop_test_stop();
+ return 0;
+
+}
+
+void voice_buffer_cmd_proc(char *cmdstr)
+{
+ int ret = 0;
+ char data[VOICE_CMD_MAX_LEN];
+ int cmdstr_len = strlen(cmdstr); //-strlen("\r")
+ int value = 0;
+ int *p_value = &value;
+
+ cmdstr[cmdstr_len] = '\0'; //+strlen("\0")
+
+ ret = sscanf(cmdstr, "%s", data);
+ if(1 != ret){
+ printf("data sscanf failed!(%d)\n", ret);
+ return;
+ }
+ if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_START, strlen(REQ_VOICE_BUFFER_TEST_START))){
+
+ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+ printf("%s,value sscanf failed!(%d)\n",data, ret);
+ return;
+ }
+
+ printf("%s set value %d\n", data, value);
+ ret = voice_buffer_stream_test_start(value);
+
+ printf("%s return ret=%d\n", data, ret);
+
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_TEST_STOP, strlen(REQ_VOICE_BUFFER_TEST_STOP))){
+ ret = voice_buffer_stream_test_stop();
+ printf("%s return %d\n", data, ret);
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_START, strlen(REQ_VOICE_BUFFER_LOOP_TEST_START))){
+
+ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+ printf("%s,value sscanf failed!(%d)\n",data, ret);
+ return;
+ }
+
+ printf("%s set value %d\n", data, value);
+ ret = voice_buffer_stream_loop_test_start(value);
+
+ printf("%s return ret=%d\n", data, ret);
+
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_LOOP_TEST_STOP, strlen(REQ_VOICE_BUFFER_LOOP_TEST_STOP))){
+ printf("voice_buffer_stream_loop_test_stop \n");
+ ret = voice_buffer_stream_loop_test_stop();
+ printf("%s return %d\n", data, ret);
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_START, strlen(REQ_VOICE_BUFFER_RTP_TEST_START))){
+
+ ret = sscanf(cmdstr, "%*s %d", &value);
+ if(1 != ret){
+ printf("%s,value sscanf failed!(%d)\n",data, ret);
+ return;
+ }
+
+ printf("%s set value %d\n", data, value);
+ ret = voice_buffer_rtp_test_start(value);
+
+ printf("%s return ret=%d\n", data, ret);
+
+ }
+ else if(0 == strncmp(data, REQ_VOICE_BUFFER_RTP_TEST_STOP, strlen(REQ_VOICE_BUFFER_RTP_TEST_STOP))){
+ ret = voice_buffer_rtp_test_stop();
+ printf("%s return %d\n", data, ret);
+ }
+ else{
+ printf("Request unknow.\n");
+ printUsage(cmdstr);
+ }
+}
+
+void vb_buffer_stop_all()
+{
+ voice_buffer_stream_loop_test_stop();
+ voice_buffer_stream_test_stop();
+ voice_buffer_rtp_test_stop();
+}
+
+void signal_handle_func(int sig)
+{
+ printf("sig(%d) signal_handle_func exit ",sig);
+
+ vb_buffer_stop_all();
+ exit(0);
+}
+
+int main(int argc, char **argv)
+{
+ char cmdstr[VOICE_CMD_MAX_LEN];
+
+ signal(SIGINT, signal_handle_func);
+ signal(SIGQUIT, signal_handle_func);
+ signal(SIGTERM, signal_handle_func);
+ signal(SIGPIPE, signal_handle_func);
+
+ memset(&vbuf_rec,0,sizeof(vbuf_rec));
+#if 0
+ /*add by hq for faster start @20240906,begin*/
+ if(argc>1)
+ {
+ voice_buffer_cmd_proc(argv[1]);
+ }
+ /*add by hq for faster start @20240906,end*/
+ else
+ {
+#endif
+ while(1){
+ printf("Please input an voice_demo command:\n");
+ if(NULL != fgets(cmdstr, VOICE_CMD_MAX_LEN - 1, stdin)){
+ if(0 == strcmp(EXIT_CMD_STOP, cmdstr) ||
+ 0 == strcmp(EXIT_CMD_Q, cmdstr) ||
+ 0 == strcmp(EXIT_CMD_EXIT, cmdstr)){
+ vb_buffer_stop_all();
+ break;
+ }
+
+ printf("len:%d, cmdstr:%s\n", strlen(cmdstr), cmdstr);
+
+ if(1 >= strlen(cmdstr)){
+ continue;
+ }
+ voice_buffer_cmd_proc(cmdstr);
+ }
+ }
+// }
+
+ printf("voice_demo end\n");
+
+ return 0;
+}
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
new file mode 100755
index 0000000..6a6f960
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/files/makefile
@@ -0,0 +1,47 @@
+SHELL = /bin/sh
+RM = rm -f
+
+LOCAL_CFLAGS := -Wall \
+ -g -Os \
+ -flto \
+ -fpermissive \
+ -fPIC \
+
+ifeq ($(strip $(TARGET_PLATFORM)), T106)
+LOCAL_CFLAGS += -DBINDER_IPC_32BIT=1 -DHAVE_ENDIAN_H -DHAVE_PTHREADS -DHAVE_SYS_UIO_H -DHAVE_POSIX_FILEMAP -DHAVE_STRLCPY -DHAVE_PRCTL -DHAVE_MEMSET16 -DHAVE_MEMSET32 -DANDROID_SMP=0
+endif
+
+LOCAL_CFLAGS += -Werror=implicit-function-declaration
+
+$(warning ################# rock ROOT: $(ROOT),includedir:$(includedir),)
+
+LOCAL_PATH = .
+
+LOCAL_C_INCLUDES = \
+ -I. \
+ -I$(ROOT)$(includedir)/ \
+
+
+
+LOCAL_LIBS := \
+ -L. \
+ -ldl \
+ -lpthread \
+ -lvoice \
+
+SOURCES = $(wildcard *.c)
+
+EXECUTABLE = lynq_vb_demo
+
+OBJECTS=$(SOURCES:.c=.o)
+all: $(EXECUTABLE)
+
+$(EXECUTABLE): $(OBJECTS)
+ $(CC) $(OBJECTS) $(LOCAL_LIBS) $(LOCAL_CFLAGS) $(LOCAL_C_INCLUDES) -o $@
+
+%.o : %.c
+ $(CC) $(LOCAL_C_INCLUDES) $(LOCAL_CFLAGS) $(LOCAL_LIBS) -o $@ -c $<
+
+.PHONY: clean
+clean:
+ $(RM) $(OBJECTS) $(EXECUTABLE)
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
new file mode 100755
index 0000000..b01d3b0
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic-custom/recipes-lynq/lynq-vb-demo/lynq-vb-demo.bb
@@ -0,0 +1,29 @@
+#inherit externalsrc package
+
+DESCRIPTION = "lynq-vb-demo"
+LICENSE = "CLOSED"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=b1e07e8d88e26263e71d3a9e2aa9a2ff"
+DEPENDS += "libvoice"
+SRC_URI = "file://lynq_vb_demo.c \
+ file://makefile \
+"
+
+SRC-DIR = "${S}/../lynq-vb-demo"
+FILES_${PN} += "${bindir}/"
+TARGET_CC_ARCH += "${LDFLAGS}"
+
+S = "${WORKDIR}"
+
+#INHIBIT_PACKAGE_STRIP = "1"
+do_compile () {
+ if test "${PACKAGE_ARCH}" = "cortexa7hf-vfp-vfpv4-neon" || test "${PACKAGE_ARCH}" = "cortexa7hf-neon-vfpv4"; then
+ oe_runmake all ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST} -mhard-float"
+ else
+ oe_runmake all ROOT=${STAGING_DIR_HOST} OFLAGS="--sysroot=${STAGING_DIR_HOST}"
+ fi
+}
+
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/lynq_vb_demo ${D}${bindir}/
+}
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
new file mode 100755
index 0000000..b413ee2
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/libvoice/libvoice.bb
@@ -0,0 +1,51 @@
+DESCRIPTION = "libvoice"
+DEPENDS = "libtinyalsa libnvram libsoftap libsofttimer"
+SECTION = "lib"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://libvoice \
+ "
+
+S = "${WORKDIR}"
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+CFLAGS_append = "-I ${BSPDIR}/zxic_code/zxic_source/zxic_app_open/platform/libtinyalsa/include"
+CFLAGS_append = "-I ${BSPDIR}/zxic_code/zxic_source/linux-5.10/include/linux"
+
+
+CFLAGS_append += "${@bb.utils.contains("CONFIG_VB_TRANSMIT_INTF", "RTP", "-I ${BSPDIR}/zxic_code/zxic_source/zxic_app/librtp/include", "", d)}"
+DEPENDS += "${@bb.utils.contains('CONFIG_VB_TRANSMIT_INTF', 'RTP', 'librtp', '', d)}"
+#编译
+do_compile () {
+ make -C libvoice CONFIG_VB_TRANSMIT_INTF=${CONFIG_VB_TRANSMIT_INTF}
+}
+
+#库和头文件的安装
+do_install () {
+ install -d ${D}${libdir}/
+ install -d ${D}/usr/include
+ install -m 0755 ${S}/libvoice/libvoice.so ${D}${libdir}/
+ install -m 0755 ${S}/libvoice/libvoice.a ${D}${libdir}/
+ install -m 0644 ${S}/libvoice/include/*.h ${D}/usr/include/
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/libvoice/libvoice.so ${ELFS-PATH}/
+}
+
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/libvoice.so
+}
+
+#rootfs包含的文件
+FILES_${PN} += "${libdir}/*.so"
+FILES_${PN}-dbg += "${libdir}/.debug"
+FILES_SOLIBSDEV = ""
+INSANE_SKIP_${PN} = "dev-so"
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
new file mode 100755
index 0000000..69ad466
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/nvserver/nvserver.bb
@@ -0,0 +1,79 @@
+DESCRIPTION = "nvserver"
+#nvserver依赖libnvram库
+DEPENDS = "libmtd libnvram libflags libsd-daemon"
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://nvserver \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://nvserver.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://nvserver.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://nvserver.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append = "${ZXIC_EXTRA_CFLAGS}"
+
+#编译
+do_compile() {
+ make -C nvserver
+}
+
+#库文件的安装
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/nvserver/nvserver ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/nvserver.init ${D}${sysconfdir}/init.d/nvserver
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/nvserver.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/nvserver.sysvinit ${D}${sysconfdir}/init.d/nvserver
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/nvserver ${D}${sysconfdir}/rcS.d/S16nvserver
+ ln -s ../init.d/nvserver ${D}${sysconfdir}/rcS.d/K84nvserver
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/nvserver/nvserver ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/nvserver
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "nvserver.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+RDEPENDS_${PN} = "libmtd libnvram libflags libsd-daemon"
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
new file mode 100755
index 0000000..dd579d3
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/sntp/sntp.bb
@@ -0,0 +1,76 @@
+DESCRIPTION = "sntp"
+#sntp依赖libnvram库
+DEPENDS = "libdebug-info libnvram libsoftap libsofttimer"
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://sntp \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://sntp.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://sntp.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://sntp.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append += "${ZXIC_EXTRA_CFLAGS}"
+#编译
+do_compile() {
+ make -C sntp
+}
+
+#库文件的安装，封库的宏MK_SDK_VERSION
+do_install () {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/sntp/sntp ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/sntp.init ${D}${sysconfdir}/init.d/sntp
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/sntp.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/sntp.sysvinit ${D}${sysconfdir}/init.d/sntp
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/sntp ${D}${sysconfdir}/rcS.d/S22sntp
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/sntp/sntp ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/sntp
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/init.d/sntp","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "sntp.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+RDEPENDS_${PN} = " libdebug-info libnvram libsoftap libsofttimer"
\ No newline at end of file
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
new file mode 100755
index 0000000..61650fa
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-app/zxic-debug/zxic-debug.bb
@@ -0,0 +1,79 @@
+DESCRIPTION = "zxic-debug"
+#zxic-debug依赖libnvram库
+DEPENDS = "libnvram"
+SECTION = "app"
+LICENSE = "zte"
+PV = "1.0.0"
+PR = "r0"
+
+CLASS_COM = " \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'procd', 'openwrt openwrt-services', '', d)} \
+ ${@bb.utils.contains('DISTRO_FEATURES', 'systemd', 'systemd', '', d)} \
+"
+inherit ${CLASS_COM}
+
+#配置code路径信息。
+FILESEXTRAPATHS_prepend :="${APP-OPEN-PATH}/platform:"
+SRC_URI = " \
+ file://zxic_debug \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "file://zxic_debug.init","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "systemd", "file://zxic_debug.service","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "file://zxic_debug.sysvinit","", d)} \
+ "
+
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/zte;md5=c075689d1d1e06d4ab5bbe53623a6808"
+S = "${WORKDIR}"
+
+#引用公用头文件和编译选项。
+include ${BSPDIR}/sources/meta-zxic/conf/app_com.inc
+include ${BSPDIR}/sources/meta-zxic/conf/pub.inc
+CFLAGS_append = "${ZXIC_EXTRA_CFLAGS}"
+
+#编译
+do_compile() {
+ make -C zxic_debug
+}
+
+#库文件的安装
+do_install() {
+ install -d ${D}${bindir}/
+ install -m 0755 ${S}/zxic_debug/zxic_debug ${D}${bindir}/
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','procd','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/zxic_debug.init ${D}${sysconfdir}/init.d/zxic_debug
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ install -d ${D}${systemd_unitdir}/system
+ install -m 0644 ${WORKDIR}/zxic_debug.service ${D}${systemd_unitdir}/system
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','sysvinit','true','false',d)}; then
+ install -Dm 0755 ${WORKDIR}/zxic_debug.sysvinit ${D}${sysconfdir}/init.d/zxic_debug
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/zxic_debug ${D}${sysconfdir}/rcS.d/S90zxic_debug
+ ln -s ../init.d/zxic_debug ${D}${sysconfdir}/rcS.d/K10zxic_debug
+ fi
+
+ #install elfs
+ install -d ${ELFS-PATH}/
+ install -m 0755 ${S}/zxic_debug/zxic_debug ${ELFS-PATH}/
+}
+#清库
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/zxic_debug
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
+
+#rootfs包含的文件
+FILES_${PN} = "\
+ ${bindir}/ \
+ ${@bb.utils.contains("DISTRO_FEATURES", "procd", "${sysconfdir}/","", d)} \
+ ${@bb.utils.contains("DISTRO_FEATURES", "sysvinit", "${sysconfdir}/","", d)} \
+ "
+SYSTEMD_SERVICE_${PN} = "zxic_debug.service"
+SYSTEMD_AUTO_ENABLE_${PN} = "enable"
+
+
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
new file mode 100755
index 0000000..a5a5bf4
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.bb
@@ -0,0 +1,67 @@
+require busybox_1.33.1.inc
+
+SRC_URI = "https://busybox.net/downloads/busybox-${PV}.tar.bz2;name=tarball \
+ file://busybox-1.33.1/busybox-udhcpc-no_deconfig.patch \
+ file://find-touchscreen.sh \
+ file://busybox-cron \
+ file://busybox-httpd \
+ file://busybox-udhcpd \
+ file://default.script \
+ file://simple.script \
+ file://hwclock.sh \
+ file://syslog \
+ file://syslog-startup.conf \
+ file://syslog.conf \
+ file://busybox-syslog.default \
+ file://files-1.33.1/mdev \
+ file://mdev.conf \
+ file://mdev-mount.sh \
+ file://busybox-1.33.1/defconfig \
+ file://busybox-syslog.service.in \
+ file://busybox-klogd.service.in \
+ file://busybox-1.33.1/fail_on_no_media.patch \
+ file://run-ptest \
+ file://inetd.conf \
+ file://inetd \
+ file://login-utilities.cfg \
+ file://recognize_connmand.patch \
+ file://busybox-cross-menuconfig.patch \
+ file://busybox-1.33.1/0001-Use-CC-when-linking-instead-of-LD-and-use-CFLAGS-and.patch \
+ file://busybox-1.33.1/mount-via-label.cfg \
+ file://sha1sum.cfg \
+ file://sha256sum.cfg \
+ file://getopts.cfg \
+ file://resize.cfg \
+ ${@["", "file://init.cfg"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]} \
+ ${@["", "file://rcS.default"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]} \
+ ${@["", "file://mdev.cfg"][(d.getVar('VIRTUAL-RUNTIME_dev_manager') == 'busybox-mdev')]} \
+ file://syslog.cfg \
+ file://unicode.cfg \
+ file://rev.cfg \
+ file://pgrep.cfg \
+ file://rcS \
+ file://rcK \
+ file://makefile-libbb-race.patch \
+ file://busybox-1.33.1/0001-testsuite-check-uudecode-before-using-it.patch \
+ file://0001-testsuite-use-www.example.org-for-wget-test-cases.patch \
+ file://0001-du-l-works-fix-to-use-145-instead-of-144.patch \
+ file://0001-sysctl-ignore-EIO-of-stable_secret-below-proc-sys-ne.patch \
+ file://busybox-1.33.1/0001-gen_build_files-Use-C-locale-when-calling-sed-on-glo.patch \
+ file://busybox-1.33.1/0001-mktemp-add-tmpdir-option.patch \
+ file://busybox-1.33.1/600-dhcpd-fix.patch \
+ file://busybox-1.33.1/0100-zxic-tty-disable-soft-flow-control.patch \
+ file://busybox-1.33.1/700-dhcpd-fix.patch \
+ "
+
+SRC_URI += "file://busybox-1.33.1/010-syslogd-recive-remote-log.patch"
+SRC_URI += "file://busybox-1.33.1/020-syslogd-filesize-and-filenum-parameter-nvcfg.patch"
+#SRC_URI += "file://busybox-1.33.1/022-syslogd-replace-remote-log-facility.patch"
+SRC_URI += "file://busybox-1.33.1/0100-zxic-add-sync-after-chmod.patch"
+SRC_URI += "file://busybox-1.33.1/0101-zxic-bb_get_chunk_from_file-limit-10MB.patch"
+SRC_URI += "file://busybox-1.33.1/0102-zxic-ash-read-etc-profile.patch"
+SRC_URI += "file://busybox-1.33.1/0103-top-short-lived-processes-optimize.patch"
+SRC_URI += "file://busybox-1.33.1/0103-syslogd-data-encryption.patch"
+
+SRC_URI_append_libc-musl = " file://busybox-1.33.1/musl.cfg "
+
+SRC_URI[tarball.sha256sum] = "12cec6bd2b16d8a9446dd16130f2b92982f1819f6e1c5f5887b6db03f5660d28"
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
new file mode 100755
index 0000000..2efbe4d
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/busybox/busybox_1.33.1.inc
@@ -0,0 +1,510 @@
+SUMMARY = "Tiny versions of many common UNIX utilities in a single small executable"
+DESCRIPTION = "BusyBox combines tiny versions of many common UNIX utilities into a single small executable. It provides minimalist replacements for most of the utilities you usually find in GNU fileutils, shellutils, etc. The utilities in BusyBox generally have fewer options than their full-featured GNU cousins; however, the options that are included provide the expected functionality and behave very much like their GNU counterparts. BusyBox provides a fairly complete POSIX environment for any small or embedded system."
+HOMEPAGE = "https://www.busybox.net"
+BUGTRACKER = "https://bugs.busybox.net/"
+
+DEPENDS += "kern-tools-native virtual/crypt libnvram"
+
+# bzip2 applet in busybox is based on lightly-modified bzip2-1.0.4 source
+# the GPL is version 2 only
+LICENSE = "GPLv2 & bzip2-1.0.4"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=de10de48642ab74318e893a61105afbb \
+ file://archival/libarchive/bz/LICENSE;md5=28e3301eae987e8cfe19988e98383dae"
+
+SECTION = "base"
+
+# Whether to split the suid apps into a seperate binary
+BUSYBOX_SPLIT_SUID ?= "1"
+
+export EXTRA_CFLAGS = "${CFLAGS}"
+export EXTRA_LDFLAGS = "${LDFLAGS}"
+
+EXTRA_OEMAKE = "CC='${CC}' LD='${CCLD}' V=1 ARCH=${TARGET_ARCH} CROSS_COMPILE=${TARGET_PREFIX} SKIP_STRIP=y HOSTCC='${BUILD_CC}' HOSTCPP='${BUILD_CPP}'"
+
+PACKAGES =+ "${PN}-httpd ${PN}-udhcpd ${PN}-udhcpc ${PN}-syslog ${PN}-mdev ${PN}-hwclock"
+
+FILES_${PN}-httpd = "${sysconfdir}/init.d/busybox-httpd /srv/www"
+FILES_${PN}-syslog = "${sysconfdir}/init.d/syslog* ${sysconfdir}/syslog-startup.conf* ${sysconfdir}/syslog.conf* ${systemd_unitdir}/system/syslog.service ${sysconfdir}/default/busybox-syslog"
+FILES_${PN}-mdev = "${sysconfdir}/init.d/mdev ${sysconfdir}/mdev.conf ${sysconfdir}/mdev/*"
+FILES_${PN}-udhcpd = "${sysconfdir}/init.d/busybox-udhcpd"
+FILES_${PN}-udhcpc = "${sysconfdir}/udhcpc.d ${datadir}/udhcpc"
+FILES_${PN}-hwclock = "${sysconfdir}/init.d/hwclock.sh"
+
+INITSCRIPT_PACKAGES = "${PN}-httpd ${PN}-syslog ${PN}-udhcpd ${PN}-mdev ${PN}-hwclock"
+
+INITSCRIPT_NAME_${PN}-httpd = "busybox-httpd"
+INITSCRIPT_NAME_${PN}-hwclock = "hwclock.sh"
+INITSCRIPT_NAME_${PN}-mdev = "mdev"
+INITSCRIPT_PARAMS_${PN}-mdev = "start 04 S ."
+INITSCRIPT_NAME_${PN}-syslog = "syslog"
+INITSCRIPT_NAME_${PN}-udhcpd = "busybox-udhcpd"
+
+SYSTEMD_PACKAGES = "${PN}-syslog"
+SYSTEMD_SERVICE_${PN}-syslog = "${@bb.utils.contains('SRC_URI', 'file://syslog.cfg', 'busybox-syslog.service', '', d)}"
+
+RDEPENDS_${PN}-syslog = "busybox"
+CONFFILES_${PN}-syslog = "${sysconfdir}/syslog-startup.conf"
+RCONFLICTS_${PN}-syslog = "rsyslog sysklogd syslog-ng"
+
+CONFFILES_${PN}-mdev = "${sysconfdir}/mdev.conf"
+
+RRECOMMENDS_${PN} = "${PN}-udhcpc"
+
+RDEPENDS_${PN} = "${@["", "busybox-inittab"][(d.getVar('VIRTUAL-RUNTIME_init_manager') == 'busybox')]}"
+
+inherit cml1 systemd update-rc.d ptest
+
+# busybox's unzip test case needs zip command, which busybox itself does not provide
+RDEPENDS_${PN}-ptest = "zip"
+
+# internal helper
+def busybox_cfg(feature, tokens, cnf, rem):
+ if type(tokens) == type(""):
+ tokens = [tokens]
+ rem.extend(['/^[# ]*' + token + '[ =]/d' for token in tokens])
+ if feature:
+ cnf.extend([token + '=y' for token in tokens])
+ else:
+ cnf.extend(['# ' + token + ' is not set' for token in tokens])
+
+# Map distro features to config settings
+def features_to_busybox_settings(d):
+ cnf, rem = ([], [])
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv6', True, False, d), 'CONFIG_FEATURE_IPV6', cnf, rem)
+ busybox_cfg(True, 'CONFIG_LFS', cnf, rem)
+ busybox_cfg(True, 'CONFIG_FDISK_SUPPORT_LARGE_DISKS', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'nls', True, False, d), 'CONFIG_LOCALE_SUPPORT', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv4', True, False, d), 'CONFIG_FEATURE_IFUPDOWN_IPV4', cnf, rem)
+ busybox_cfg(bb.utils.contains('DISTRO_FEATURES', 'ipv6', True, False, d), 'CONFIG_FEATURE_IFUPDOWN_IPV6', cnf, rem)
+ busybox_cfg(bb.utils.contains_any('DISTRO_FEATURES', 'bluetooth wifi', True, False, d), 'CONFIG_RFKILL', cnf, rem)
+ return "\n".join(cnf), "\n".join(rem)
+
+# X, Y = ${@features_to_busybox_settings(d)}
+# unfortunately doesn't seem to work with bitbake, workaround:
+def features_to_busybox_conf(d):
+ cnf, rem = features_to_busybox_settings(d)
+ return cnf
+def features_to_busybox_del(d):
+ cnf, rem = features_to_busybox_settings(d)
+ return rem
+
+configmangle = '/CONFIG_EXTRA_CFLAGS/d; \
+ '
+OE_FEATURES := "${@features_to_busybox_conf(d)}"
+OE_DEL := "${@features_to_busybox_del(d)}"
+DO_IPv4 := "${@bb.utils.contains('DISTRO_FEATURES', 'ipv4', 1, 0, d)}"
+DO_IPv6 := "${@bb.utils.contains('DISTRO_FEATURES', 'ipv6', 1, 0, d)}"
+
+python () {
+ if "${OE_DEL}":
+ d.setVar('configmangle_append', "${OE_DEL}" + "\n")
+ if "${OE_FEATURES}":
+ d.setVar('configmangle_append',
+ "/^### DISTRO FEATURES$/a\\\n%s\n\n" %
+ ("\\n".join((d.expand("${OE_FEATURES}").split("\n")))))
+ d.setVar('configmangle_append',
+ "/^### CROSS$/a\\\n%s\n" %
+ ("\\n".join(["CONFIG_EXTRA_CFLAGS=\"${CFLAGS} ${HOST_CC_ARCH}\""
+ ])
+ ))
+}
+
+do_prepare_config () {
+ if [ "${BUILD_REPRODUCIBLE_BINARIES}" = "1" ]; then
+ export KCONFIG_NOTIMESTAMP=1
+ fi
+ sed -e '/CONFIG_STATIC/d' \
+ < ${WORKDIR}/busybox-1.33.1/defconfig > ${S}/.config
+ echo "# CONFIG_STATIC is not set" >> .config
+ for i in 'CROSS' 'DISTRO FEATURES'; do echo "### $i"; done >> \
+ ${S}/.config
+ sed -i -e '${configmangle}' ${S}/.config
+ if test ${DO_IPv4} -eq 0 && test ${DO_IPv6} -eq 0; then
+ # disable networking applets
+ mv ${S}/.config ${S}/.config.oe-tmp
+ awk 'BEGIN{net=0}
+ /^# Networking Utilities/{net=1}
+ /^#$/{if(net){net=net+1}}
+ {if(net==2&&$0 !~ /^#/&&$1){print("# "$1" is not set")}else{print}}' \
+ ${S}/.config.oe-tmp > ${S}/.config
+ fi
+ sed -i 's/CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -n"/CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="-R -b"/' ${S}/.config
+ if [ -n "${DEBUG_PREFIX_MAP}" ]; then
+ sed -i 's|${DEBUG_PREFIX_MAP}||g' ${S}/.config
+ fi
+}
+
+do_configure () {
+ set -x
+ do_prepare_config
+ merge_config.sh -m .config ${@" ".join(find_cfgs(d))}
+ cml1_do_configure
+}
+
+do_compile() {
+ unset CFLAGS CPPFLAGS CXXFLAGS LDFLAGS
+ if [ "${BUILD_REPRODUCIBLE_BINARIES}" = "1" ]; then
+ export KCONFIG_NOTIMESTAMP=1
+ fi
+ if [ "${BUSYBOX_SPLIT_SUID}" = "1" -a x`grep "CONFIG_FEATURE_INDIVIDUAL=y" .config` = x ]; then
+ # split the .config into two parts, and make two busybox binaries
+ if [ -e .config.orig ]; then
+ # Need to guard again an interrupted do_compile - restore any backup
+ cp .config.orig .config
+ fi
+ cp .config .config.orig
+ oe_runmake busybox.cfg.suid
+ oe_runmake busybox.cfg.nosuid
+
+ # workaround for suid bug 10346
+ if ! grep -q "CONFIG_SH_IS_NONE" busybox.cfg.nosuid; then
+ echo "CONFIG_SH_IS_NONE" >> busybox.cfg.suid
+ fi
+
+ for i in `cat busybox.cfg.suid busybox.cfg.nosuid`; do
+ echo "# $i is not set" >> .config.disable.apps
+ done
+ merge_config.sh -m .config.orig .config.disable.apps
+ cp .config .config.nonapps
+ for s in suid nosuid; do
+ cat busybox.cfg.$s | while read item; do
+ grep -w "$item" .config.orig
+ done > .config.app.$s
+
+ # workaround for suid bug 10346
+ if [ "$s" = "suid" ] ; then
+ sed "s/.*CONFIG_SH_IS_NONE.*$/CONFIG_SH_IS_NONE=y/" -i .config.app.suid
+ fi
+
+ merge_config.sh -m .config.nonapps .config.app.$s
+ oe_runmake busybox_unstripped
+ mv busybox_unstripped busybox.$s
+ oe_runmake busybox.links
+ sort busybox.links > busybox.links.$s
+ rm busybox.links
+ done
+
+ # hard fail if sh is being linked to the suid busybox (detects bug 10346)
+ if grep -q -x "/bin/sh" busybox.links.suid; then
+ bbfatal "busybox suid binary incorrectly provides /bin/sh"
+ fi
+
+ # copy .config.orig back to .config, because the install process may check this file
+ cp .config.orig .config
+ # cleanup
+ rm .config.orig .config.app.suid .config.app.nosuid .config.disable.apps .config.nonapps
+ else
+ oe_runmake busybox_unstripped
+ cp busybox_unstripped busybox
+ oe_runmake busybox.links
+ fi
+}
+
+do_install () {
+ sed -i "s:^/bin/:BASE_BINDIR/:" busybox.links*
+ sed -i "s:^/sbin/:BASE_SBINDIR/:" busybox.links*
+ sed -i "s:^/usr/bin/:BINDIR/:" busybox.links*
+ sed -i "s:^/usr/sbin/:SBINDIR/:" busybox.links*
+
+ # Move arch/link to BINDIR to match coreutils
+ sed -i "s:^BASE_BINDIR/arch:BINDIR/arch:" busybox.links*
+ sed -i "s:^BASE_BINDIR/link:BINDIR/link:" busybox.links*
+
+ sed -i "s:^BASE_BINDIR/:${base_bindir}/:" busybox.links*
+ sed -i "s:^BASE_SBINDIR/:${base_sbindir}/:" busybox.links*
+ sed -i "s:^BINDIR/:${bindir}/:" busybox.links*
+ sed -i "s:^SBINDIR/:${sbindir}/:" busybox.links*
+
+ install -d ${D}${sysconfdir}/init.d
+
+ if ! grep -q "CONFIG_FEATURE_INDIVIDUAL=y" ${B}/.config; then
+ # Install ${base_bindir}/busybox, and the ${base_bindir}/sh link so the postinst script
+ # can run. Let update-alternatives handle the rest.
+ install -d ${D}${base_bindir}
+ if [ "${BUSYBOX_SPLIT_SUID}" = "1" ]; then
+ install -m 4755 ${B}/busybox.suid ${D}${base_bindir}
+ install -m 0755 ${B}/busybox.nosuid ${D}${base_bindir}
+ install -m 0644 ${S}/busybox.links.suid ${D}${sysconfdir}
+ install -m 0644 ${S}/busybox.links.nosuid ${D}${sysconfdir}
+ if grep -q "CONFIG_SH_IS_ASH=y" ${B}/.config; then
+ ln -sf busybox.nosuid ${D}${base_bindir}/sh
+ fi
+ # Keep a default busybox for people who want to invoke busybox directly.
+ # This is also useful for the on device upgrade. Because we want
+ # to use the busybox command in postinst.
+ ln -sf busybox.nosuid ${D}${base_bindir}/busybox
+ else
+ if grep -q "CONFIG_FEATURE_SUID=y" ${B}/.config; then
+ install -m 4755 ${B}/busybox ${D}${base_bindir}
+ else
+ install -m 0755 ${B}/busybox ${D}${base_bindir}
+ fi
+ install -m 0644 ${S}/busybox.links ${D}${sysconfdir}
+ if grep -q "CONFIG_SH_IS_ASH=y" ${B}/.config; then
+ ln -sf busybox ${D}${base_bindir}/sh
+ fi
+ # We make this symlink here to eliminate the error when upgrading together
+ # with busybox-syslog. Without this symlink, the opkg may think of the
+ # busybox.nosuid as obsolete and remove it, resulting in dead links like
+ # ${base_bindir}/sed -> ${base_bindir}/busybox.nosuid. This will make upgrading busybox-syslog fail.
+ # This symlink will be safely deleted in postinst, thus no negative effect.
+ ln -sf busybox ${D}${base_bindir}/busybox.nosuid
+ fi
+ else
+ install -d ${D}${base_bindir} ${D}${bindir} ${D}${libdir}
+ cat busybox.links | while read FILE; do
+ NAME=`basename "$FILE"`
+ install -m 0755 "0_lib/$NAME" "${D}$FILE.${BPN}"
+ done
+ # add suid bit where needed
+ for i in `grep -E "APPLET.*BB_SUID_((MAYBE|REQUIRE))" include/applets.h | grep -v _BB_SUID_DROP | cut -f 3 -d '(' | cut -f 1 -d ','`; do
+ find ${D} -name $i.${BPN} -exec chmod a+s {} \;
+ done
+ install -m 0755 0_lib/libbusybox.so.${PV} ${D}${libdir}/libbusybox.so.${PV}
+ ln -sf sh.${BPN} ${D}${base_bindir}/sh
+ ln -sf ln.${BPN} ${D}${base_bindir}/ln
+ ln -sf test.${BPN} ${D}${bindir}/test
+ if [ -f ${D}/linuxrc.${BPN} ]; then
+ mv ${D}/linuxrc.${BPN} ${D}/linuxrc
+ fi
+ install -m 0644 ${S}/busybox.links ${D}${sysconfdir}
+ fi
+
+ if grep -q "CONFIG_SYSLOGD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/syslog ${D}${sysconfdir}/init.d/syslog
+ install -m 644 ${WORKDIR}/syslog-startup.conf ${D}${sysconfdir}/syslog-startup.conf
+ install -m 644 ${WORKDIR}/syslog.conf ${D}${sysconfdir}/syslog.conf
+ install -d ${D}${sysconfdir}/rcS.d
+ ln -s ../init.d/syslog ${D}${sysconfdir}/rcS.d/S18syslog
+ fi
+ if grep -q "CONFIG_CROND=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-cron ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_HTTPD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-httpd ${D}${sysconfdir}/init.d/
+ install -d ${D}/srv/www
+ fi
+ if grep -q "CONFIG_UDHCPD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/busybox-udhcpd ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_HWCLOCK=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/hwclock.sh ${D}${sysconfdir}/init.d/
+ fi
+ if grep -q "CONFIG_UDHCPC=y" ${B}/.config; then
+ install -d ${D}${sysconfdir}/udhcpc.d
+ install -d ${D}${datadir}/udhcpc
+ install -m 0755 ${WORKDIR}/simple.script ${D}${sysconfdir}/udhcpc.d/50default
+ sed -i "s:/SBIN_DIR/:${base_sbindir}/:" ${D}${sysconfdir}/udhcpc.d/50default
+ install -m 0755 ${WORKDIR}/default.script ${D}${datadir}/udhcpc/default.script
+ fi
+ if grep -q "CONFIG_INETD=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/inetd ${D}${sysconfdir}/init.d/inetd.${BPN}
+ sed -i "s:/usr/sbin/:${sbindir}/:" ${D}${sysconfdir}/init.d/inetd.${BPN}
+ install -m 0644 ${WORKDIR}/inetd.conf ${D}${sysconfdir}/
+ fi
+ if grep -q "CONFIG_MDEV=y" ${B}/.config; then
+ install -m 0755 ${WORKDIR}/files-1.33.1/mdev ${D}${sysconfdir}/init.d/mdev
+ if grep "CONFIG_FEATURE_MDEV_CONF=y" ${B}/.config; then
+ install -m 644 ${WORKDIR}/mdev.conf ${D}${sysconfdir}/mdev.conf
+ install -d ${D}${sysconfdir}/mdev
+ install -m 0755 ${WORKDIR}/find-touchscreen.sh ${D}${sysconfdir}/mdev
+ install -m 0755 ${WORKDIR}/mdev-mount.sh ${D}${sysconfdir}/mdev
+ fi
+ fi
+ if grep -q "CONFIG_INIT=y" ${B}/.config && ${@bb.utils.contains('VIRTUAL-RUNTIME_init_manager','busybox','true','false',d)}; then
+ install -D -m 0755 ${WORKDIR}/rcS ${D}${sysconfdir}/init.d/rcS
+ install -D -m 0755 ${WORKDIR}/rcK ${D}${sysconfdir}/init.d/rcK
+ install -D -m 0755 ${WORKDIR}/rcS.default ${D}${sysconfdir}/default/rcS
+ fi
+
+ if ${@bb.utils.contains('DISTRO_FEATURES','systemd','true','false',d)}; then
+ if grep -q "CONFIG_KLOGD=y" ${B}/.config; then
+ install -d ${D}${systemd_unitdir}/system
+ sed 's,@base_sbindir@,${base_sbindir},g' < ${WORKDIR}/busybox-klogd.service.in \
+ > ${D}${systemd_unitdir}/system/busybox-klogd.service
+ fi
+
+ if grep -q "CONFIG_SYSLOGD=y" ${B}/.config; then
+ install -d ${D}${systemd_unitdir}/system
+ sed 's,@base_sbindir@,${base_sbindir},g' < ${WORKDIR}/busybox-syslog.service.in \
+ > ${D}${systemd_unitdir}/system/busybox-syslog.service
+ if [ ! -e ${D}${systemd_unitdir}/system/busybox-klogd.service ] ; then
+ sed -i '/klog/d' ${D}${systemd_unitdir}/system/busybox-syslog.service
+ fi
+ if [ -f ${WORKDIR}/busybox-syslog.default ] ; then
+ install -d ${D}${sysconfdir}/default
+ install -m 0644 ${WORKDIR}/busybox-syslog.default ${D}${sysconfdir}/default/busybox-syslog
+ fi
+ fi
+ fi
+
+ # Remove the sysvinit specific configuration file for systemd systems to avoid confusion
+ if ${@bb.utils.contains('DISTRO_FEATURES', 'sysvinit', 'false', 'true', d)}; then
+ rm -f ${D}${sysconfdir}/syslog-startup.conf
+ fi
+}
+
+PTEST_BINDIR = "1"
+
+do_install_ptest () {
+ cp -r ${B}/testsuite ${D}${PTEST_PATH}/
+ # These access the internet which is not guaranteed to work on machines running the tests
+ rm -rf ${D}${PTEST_PATH}/testsuite/wget
+ sort ${B}/.config > ${D}${PTEST_PATH}/.config
+ ln -s /bin/busybox ${D}${PTEST_PATH}/busybox
+}
+
+inherit update-alternatives
+
+ALTERNATIVE_PRIORITY = "50"
+
+python do_package_prepend () {
+ # We need to load the full set of busybox provides from the /etc/busybox.links
+ # Use this to see the update-alternatives with the right information
+
+ dvar = d.getVar('D')
+ pn = d.getVar('PN')
+ def set_alternative_vars(links, target):
+ links = d.expand(links)
+ target = d.expand(target)
+ f = open('%s%s' % (dvar, links), 'r')
+ for alt_link_name in f:
+ alt_link_name = alt_link_name.strip()
+ alt_name = os.path.basename(alt_link_name)
+ # Match coreutils
+ if alt_name == '[':
+ alt_name = 'lbracket'
+ if alt_name == 'klogd' or alt_name == 'syslogd':
+ d.appendVar('ALTERNATIVE_%s-syslog' % (pn), ' ' + alt_name)
+ else:
+ d.appendVar('ALTERNATIVE_%s' % (pn), ' ' + alt_name)
+ d.setVarFlag('ALTERNATIVE_LINK_NAME', alt_name, alt_link_name)
+ if os.path.exists('%s%s' % (dvar, target)):
+ d.setVarFlag('ALTERNATIVE_TARGET', alt_name, target)
+ f.close()
+ return
+
+ if os.path.exists('%s/etc/busybox.links' % (dvar)):
+ set_alternative_vars("${sysconfdir}/busybox.links", "${base_bindir}/busybox")
+ else:
+ set_alternative_vars("${sysconfdir}/busybox.links.nosuid", "${base_bindir}/busybox.nosuid")
+ set_alternative_vars("${sysconfdir}/busybox.links.suid", "${base_bindir}/busybox.suid")
+}
+
+# This part of code is dedicated to the on target upgrade problem. It's known
+# that if we don't make appropriate symlinks before update-alternatives calls,
+# there will be errors indicating missing commands such as 'sed'.
+# These symlinks will later be updated by update-alternatives calls.
+# The update-alternatives.bbclass' postinst script runs firstly before other
+# postinst, but this part of code needs run firstly, so add this funtion.
+python populate_packages_updatealternatives_append() {
+ postinst = """
+test -n 2 > /dev/null || alias test='busybox test'
+if test "x$D" = "x"; then
+ # Remove busybox.nosuid if it's a symlink, because this situation indicates
+ # that we're installing or upgrading to a one-binary busybox.
+ if test -h ${base_bindir}/busybox.nosuid; then
+ rm -f ${base_bindir}/busybox.nosuid
+ fi
+ for suffix in "" ".nosuid" ".suid"; do
+ if test -e ${sysconfdir}/busybox.links$suffix; then
+ while read link; do
+ if test ! -e "$link"; then
+ # we can use busybox here because even if we are using splitted busybox
+ # we've made a symlink from /bin/busybox to /bin/busybox.nosuid.
+ busybox rm -f $link
+ busybox ln -s "${base_bindir}/busybox$suffix" $link
+ fi
+ done < ${sysconfdir}/busybox.links$suffix
+ fi
+ done
+fi
+if grep -q "^${base_bindir}/bash$" $D${sysconfdir}/busybox.links*; then
+ grep -q "^${base_bindir}/bash$" $D${sysconfdir}/shells || echo ${base_bindir}/bash >> $D${sysconfdir}/shells
+fi
+
+"""
+ d.prependVar('pkg_postinst_%s' % pkg, postinst)
+}
+
+pkg_postinst_${PN}_prepend () {
+ # Need path to saved utils, but they may have be removed on upgrade of busybox
+ # Only use shell to get paths. Also capture if busybox was saved.
+ BUSYBOX=""
+ if [ "x$D" = "x" ] ; then
+ for busybox_rmdir in /tmp/busyboxrm-*; do
+ if [ "$busybox_rmdir" != '/tmp/busyboxrm-*' ] ; then
+ export PATH=$busybox_rmdir:$PATH
+ if [ -e $busybox_rmdir/busybox* ] ; then
+ BUSYBOX="$busybox_rmdir/busybox*"
+ fi
+ fi
+ done
+ fi
+}
+
+pkg_postinst_${PN}_append () {
+ # If busybox exists in the remove directory it is because it was the only shell left.
+ if [ "x$D" = "x" ] ; then
+ if [ "x$BUSYBOX" != "x" ] ; then
+ update-alternatives --remove sh $BUSYBOX
+ rm -f $BUSYBOX
+ fi
+ fi
+}
+
+pkg_prerm_${PN} () {
+ # This is so you can make busybox commit suicide - removing busybox with no other packages
+ # providing its files, this will make update-alternatives work, but the update-rc.d part
+ # for syslog, httpd and/or udhcpd will fail if there is no other package providing sh
+ tmpdir=`mktemp -d /tmp/busyboxrm-XXXXXX`
+ ln -s ${base_bindir}/busybox $tmpdir/[
+ ln -s ${base_bindir}/busybox $tmpdir/test
+ ln -s ${base_bindir}/busybox $tmpdir/head
+ ln -s ${base_bindir}/busybox $tmpdir/sh
+ ln -s ${base_bindir}/busybox $tmpdir/basename
+ ln -s ${base_bindir}/busybox $tmpdir/echo
+ ln -s ${base_bindir}/busybox $tmpdir/mv
+ ln -s ${base_bindir}/busybox $tmpdir/ln
+ ln -s ${base_bindir}/busybox $tmpdir/dirname
+ ln -s ${base_bindir}/busybox $tmpdir/rm
+ ln -s ${base_bindir}/busybox $tmpdir/sed
+ ln -s ${base_bindir}/busybox $tmpdir/sort
+ ln -s ${base_bindir}/busybox $tmpdir/grep
+ ln -s ${base_bindir}/busybox $tmpdir/tail
+ export PATH=$PATH:$tmpdir
+
+ # If busybox is the shell, we need to save it since its the lowest priority shell
+ # Register saved bitbake as the lowest priority shell possible as back up.
+ if [ -n "$(readlink -f /bin/sh | grep busybox)" ] ; then
+ BUSYBOX=$(readlink -f /bin/sh)
+ cp $BUSYBOX $tmpdir/$(basename $BUSYBOX)
+ update-alternatives --install /bin/sh sh $tmpdir/$(basename $BUSYBOX) 1
+ fi
+}
+
+pkg_postrm_${PN} () {
+ # Add path to remove dir in case we removed our only grep
+ if [ "x$D" = "x" ] ; then
+ for busybox_rmdir in /tmp/busyboxrm-*; do
+ if [ "$busybox_rmdir" != '/tmp/busyboxrm-*' ] ; then
+ export PATH=$busybox_rmdir:$PATH
+ fi
+ done
+ fi
+
+ if grep -q "^${base_bindir}/bash$" $D${sysconfdir}/busybox.links* && [ ! -e $D${base_bindir}/bash ]; then
+ printf "$(grep -v "^${base_bindir}/bash$" $D${sysconfdir}/shells)\n" > $D${sysconfdir}/shells
+ fi
+}
+
+pkg_prerm_${PN}-syslog () {
+ # remove syslog
+ if test "x$D" = "x"; then
+ if test "$1" = "upgrade" -o "$1" = "remove"; then
+ ${sysconfdir}/init.d/syslog stop || :
+ fi
+ fi
+}
+
+RPROVIDES_${PN} += "${@bb.utils.contains('DISTRO_FEATURES', 'usrmerge', '/bin/sh /bin/ash', '', d)}"
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
new file mode 100755
index 0000000..1ea730c
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-core/glibc/glibc_%.bbappend
@@ -0,0 +1,37 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
+
+SRC_URI += " \
+ file://0001-write-log-to-zcat-tool.patch \
+ file://0002-fix-y2038-time_t-unsigned-long.patch \
+"
+
+do_install_append() {
+ install -d ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/ld-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libc-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libthread_db-1.0.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libpthread-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libm-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_hesiod-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_db-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_files-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_compat-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libpcprofile.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnss_dns-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/librt-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libdl-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libmemusage.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libSegFault.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libresolv-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libutil-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libanl-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libnsl-2.31.so ${ELFS-PATH}/
+ cp -rv ${D}${base_libdir}/libBrokenLocale-2.31.so ${ELFS-PATH}/
+}
+
+do_cleanlibs () {
+ rm -fr ${ELFS-PATH}/libc.so
+}
+
+addtask cleanlibs after do_clean before do_cleansstate
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-devtools/python/python3/0001-zxic-y2038-time_t.patch b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-devtools/python/python3/0001-zxic-y2038-time_t.patch
new file mode 100755
index 0000000..6740344
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-devtools/python/python3/0001-zxic-y2038-time_t.patch
@@ -0,0 +1,35 @@
+From 0a7fc505937e81c1ff9ce19f4a0084d4f7040cf3 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?=E5=91=A8=E5=9B=BD=E5=9D=A10318000136?=
+ <zhou.guopo@sanechips.com.cn>
+Date: Mon, 9 Sep 2024 16:02:36 +0800
+Subject: [PATCH] zxic y2038 time_t
+
+---
+ Modules/timemodule.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Modules/timemodule.c b/Modules/timemodule.c
+index 096911d..b34bf54 100644
+--- a/Modules/timemodule.c
++++ b/Modules/timemodule.c
+@@ -1556,7 +1556,7 @@ get_zone(char *zone, int n, struct tm *p)
+ #endif
+ }
+
+-static time_t
++static long
+ get_gmtoff(time_t t, struct tm *p)
+ {
+ #ifdef HAVE_STRUCT_TM_TM_ZONE
+@@ -1630,7 +1630,7 @@ init_timezone(PyObject *m)
+ static const time_t YEAR = (365 * 24 + 6) * 3600;
+ time_t t;
+ struct tm p;
+- time_t janzone_t, julyzone_t;
++ long janzone_t, julyzone_t;
+ char janname[10], julyname[10];
+ t = (time((time_t *)0) / YEAR) * YEAR;
+ _PyTime_localtime(t, &p);
+--
+2.17.1
+
diff --git a/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-devtools/python/python3_3.8.%.bbappend b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-devtools/python/python3_3.8.%.bbappend
new file mode 100755
index 0000000..8c97d91
--- /dev/null
+++ b/patch/17.09_19.00/code/old/esdk/layers/meta-zxic/recipes-devtools/python/python3_3.8.%.bbappend
@@ -0,0 +1,5 @@
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/python3:"
+
+SRC_URI += "file://0001-zxic-y2038-time_t.patch"
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mfd/zx234290-core.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mfd/zx234290-core.c
new file mode 100755
index 0000000..d43085f
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mfd/zx234290-core.c
@@ -0,0 +1,680 @@
+/*
+ * zx234290-core.c -- Device access for ZX234290 PMICs
+ *
+ * Copyright 2016 ZTE Inc.
+ *
+ * Author: yuxiang<yu.xiang5@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/zx234290.h>
+
+#include <linux/debugfs.h>
+#include <asm/uaccess.h>
+
+#include <linux/of_gpio.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/delay.h>
+#include <dma_cfg.h>
+#include <linux/reboot.h>
+
+
+#define USER_RST_TO_NORMAL 1
+
+//#include <mach/peri_cfg.h>
+extern int zx234290_i2c_write_simple(u8 reg, void *src);
+extern int zx234290_i2c_read_simple(u8 reg, void *dest);
+
+//void __iomem * s_poweron_type_addr;
+ unsigned long s_poweron_type_addr;
+
+/*the power on info, boot_reason */
+typedef enum
+{
+ POWER_ON_NORMAL = 0,
+ POWER_ON_FOTA,
+ POWER_ON_CHARGING,
+ POWER_ON_RTC,
+ POWER_ON_RESET,
+ POWER_ON_HDT_TEST,
+ POWER_ON_EXCEPTRESET,
+ POWER_ON_LOCALUPDATE,
+ POWER_ON_BOOST_IN,
+ POWER_ON_AMT,
+ POWER_ON_PRODUCTION,
+ POWER_ON_INVALID,
+}T_ZDrvSys_PowerOn_Type;
+
+static struct resource regulator_resources[] = {
+ {
+ .name = "bulk-error",
+ .start = ZX234290_INT_BUCK_FAUL,
+ .end = ZX234290_INT_BUCK_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "ldo_error",
+ .start = ZX234290_INT_LDO_FAUL,
+ .end = ZX234290_INT_LDO_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource rtc_resources[] = {
+ {
+ .name = "zx234290-rtc-alarm",
+ .start = ZX234290_INT_RTC_ALRM,
+ .end = ZX234290_INT_RTC_ALRM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-min",
+ .start = ZX234290_INT_RTC_MIN,
+ .end = ZX234290_INT_RTC_MIN,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-hour",
+ .start = ZX234290_INT_RTC_HOUR,
+ .end = ZX234290_INT_RTC_HOUR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct resource powerkey_resources[] = {
+ {
+ .name = "zx234290-pwrkey-int",
+ .start = ZX234290_INT_PWRON,
+ .end = ZX234290_INT_PWRON,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+static struct mfd_cell zx234290_cell[] = {
+ {
+ .name = "zx234290-regulators",
+ .num_resources = 2,
+ .resources = ®ulator_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-rtc",
+ .num_resources = 3,
+ .resources = &rtc_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-gpadc",
+ },
+ {
+ .name = "zx234290-powerkey",
+ .num_resources = 1,
+ .resources = &powerkey_resources[0],
+ .id = -1,
+ },
+};
+
+unsigned int boot_reason = POWER_ON_NORMAL;
+struct wakeup_source * adc_wakelock;
+
+unsigned int * get_boot_reason_addr(void)
+{
+ return (unsigned int *)s_poweron_type_addr;
+}
+EXPORT_SYMBOL(get_boot_reason_addr);
+
+static void get_boot_reason(void)
+{
+ //boot_reason = *(unsigned int *)POWERON_TYPE_BASE;
+ if(s_poweron_type_addr){
+ boot_reason = readl(s_poweron_type_addr/*+0xf8*/);
+
+ printk(KERN_INFO "[PMU] get boot_reason = %d from 0x%x.\n",boot_reason,s_poweron_type_addr);
+ }
+ else
+ printk(KERN_INFO "[PMU] boot_reason is unknown.\n");
+}
+
+#if 1
+int zx234290_set_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data |= mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_set_bits);
+
+int zx234290_clear_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data &= ~mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_clear_bits);
+#endif
+
+static inline int zx234290_read(struct zx234290 *zx234290, u8 reg)
+{
+ u8 val;
+ int err;
+
+ err = zx234290->read(zx234290, reg, 1, &val);
+ if (err < 0)
+ return err;
+
+ return val;
+}
+
+static inline int zx234290_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ return zx234290->write(zx234290, reg, 1, &val);
+}
+
+#if 1
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg)
+{
+ int data;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ data = zx234290_read(zx234290, reg);
+ if (data < 0)
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return data;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_read);
+
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290_write(zx234290, reg, val);
+ if (err < 0)
+ dev_err(zx234290->dev, "Write for reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_write);
+#endif
+#if 1
+extern int Zx234290_SetUserReg_PSM(unsigned char data);
+
+void zx29_restart(const char * cmd)
+{
+ /*set reset value = 1*/
+ unsigned char status = ZX234290_USER_RST_TO_NORMAL;
+
+ printk(KERN_INFO"restart:enter reboot :reset to normal\n");
+
+ status = ZX234290_USER_RST_TO_NORMAL;
+ Zx234290_SetUserReg_PSM(status);
+}
+
+
+int pmu_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+
+ printk(" pmu reboot,in user,task is: %s\n", current->comm);
+ zx29_restart((char *) ptr);
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block pmu_reboot_notifier = {
+ .notifier_call = pmu_reboot_event
+};
+
+#endif
+
+
+
+int Zx234290_SetVldo6Onoff(void)
+{
+ int ret = 0;
+ u8 reg_addr=0, reg_val=0;
+ reg_addr = 0x21;
+ ret = zx234290_i2c_read_simple(reg_addr,®_val);
+ if (ret) {
+ return -EIO;
+ }
+ reg_val = reg_val&(~(1<<5));
+ ret = zx234290_i2c_write_simple(reg_addr, ®_val);
+ if (ret) {
+ return -EIO;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(Zx234290_SetVldo6Onoff);
+#if 0
+int zx297510_write_pmu_flag_charging(void)
+{
+ int ret = 0;
+ unsigned char reg = 0;
+ ret = zx234290_i2c_read_simple(0xf, ®);
+ reg = reg|0xff;
+ ret += zx234290_i2c_write_simple(0xf, ®);
+ ret = zx234290_i2c_read_simple(0xe, ®);
+ reg = reg|0x3;
+ ret += zx234290_i2c_write_simple(0xe, ®);
+ return ret;
+}
+#endif
+//static void __iomem* PMU_ADDR_VIR;
+//#define GPIO_PMU_PSHOLD ZX29_GPIO_51
+unsigned int gpio_num_pshold;
+
+void zx234290_pshold_pull_down(void)
+{
+ //PMU_ADDR_VIR = ioremap(0x10d6c0,4);
+ //__raw_writel(0x0,PMU_ADDR_VIR);
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,0);
+ else
+ printk("zx234290_pshold_pull_down error\n");
+}
+
+//extern int zx234290_rtc_disable_timer_alarm();
+EXPORT_SYMBOL(zx234290_pshold_pull_down);
+
+/***********yuwei added at 20170523**************/
+void zx234290_pshold_pull_up(void)
+{
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,1);
+ else
+ printk("zx234290_pshold_pull_up error\n");
+}
+/**************/
+
+static int zx234290_set_softon(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+static int zx234290_set_softon_PSM(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+
+static bool debug_stop_poweroff = false;
+module_param(debug_stop_poweroff, bool, 0644);
+//extern void zx29_restart(char str,const char * cmd);
+static void zx234290_power_off(void)
+{
+ //void __iomem *reset_charging_reg;
+ //reset_charging_reg = ZX29_TOP_VA;
+ //zx234290_rtc_disable_timer_alarm();
+ //Zx234290_SetVldo6Onoff();
+ u8 reg_poweron = 0;
+ int ret;
+
+ if(debug_stop_poweroff )
+ {
+ printk(KERN_INFO"debug_stop_poweroff= 0x%x, for debug, bug_on!!!!\n", debug_stop_poweroff);
+ panic("poweroff");
+ }
+ zx234290_set_softon_PSM(0);
+ zx234290_pshold_pull_down();
+#if 1
+ while(1){
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_STSA, ®_poweron);
+ if (ret) {
+ printk(KERN_INFO"power off pmu i2c read err\n");
+ break;
+ }
+ if((reg_poweron&(1<<ZX234290_STATUSA_POWERON_LSH))== 0)
+ break;
+ }
+ mdelay(50);
+ /*reset to charging*/
+ //zx29_restart(NULL,"drv_key reboot");
+#endif
+}
+
+
+#if defined(CONFIG_DEBUG_FS)
+static ssize_t debugfs_regs_write(struct file *file, const char __user *buf,size_t nbytes, loff_t *ppos)
+{
+ struct zx234290 *zx234290 = file->private_data;
+
+ unsigned int val1, val2;
+ u8 reg, value;
+ int ret;
+ char *kern_buf;
+
+ kern_buf = kzalloc(nbytes, GFP_KERNEL);
+
+ if (!kern_buf) {
+ printk(KERN_INFO "zx234290-core: Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ if (copy_from_user(kern_buf, (void __user *)buf, nbytes)) {
+ kfree(kern_buf);
+ return -ENOMEM;
+ }
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, kern_buf,nbytes);
+
+ ret = sscanf(kern_buf, "%x:%x", &val1, &val2);
+ if (ret < 2 || val1 > ZX234290_MAX_REGISTER ) {
+ printk(KERN_INFO "zx234290-core: failed to read user buf, ret=%d, input 0x%x:0x%x\n",
+ ret, val1, val2);
+ kfree(kern_buf);
+ return -EINVAL;
+ }
+ kfree(kern_buf);
+
+ reg = val1 & 0xff;
+ value = val2 & 0xff;
+ printk(KERN_INFO "%s input %x,%x; reg=%x,value=%x\n", __func__, val1, val2, reg, value);
+ ret = zx234290_i2c_write_simple(reg, &value);
+
+ return ret ? ret : nbytes;
+}
+
+static int debugfs_regs_show(struct seq_file *s, void *v)
+{
+ int i;
+ u8 value[ZX234290_MAX_REGISTER];
+ int ret=0;
+ u8 reg_rtc_ctrl2 = 0;
+
+ printk(KERN_INFO "%s\n", __func__);
+ memset(value, 0, sizeof(value));
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++){
+ ret = zx234290_i2c_read_simple(i, &(value[i]));
+ if(ret){
+ printk(KERN_INFO "%s err=%d, break\n", __func__, ret);
+ seq_printf(s, "%s err=%d, break", __func__, ret);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++) {
+ if((i+1)%9 == 0)
+ seq_printf(s, "\n");
+
+ seq_printf(s, "[0x%x]%02x ", i, value[i]);
+ }
+
+ reg_rtc_ctrl2 = value[ZX234290_REG_ADDR_RTC_CTRL2];
+ seq_printf(s, "\nAF=%d,TF=%d,Alarm %s,Timer %s\n",(reg_rtc_ctrl2&0x8),(reg_rtc_ctrl2&0x4),
+ (reg_rtc_ctrl2&0x2)? "enable":"disable",(reg_rtc_ctrl2&0x1)? "enable":"disable");
+ if(value[ZX234290_REG_ADDR_BUCK_FAULT_STATUS]||value[ZX234290_REG_ADDR_LDO_FAULT_STATUS])
+ seq_printf(s, "ldo or bulk fault!!!!!\n ");
+ else
+ seq_printf(s, "no ldo or bulk fault\n ");
+ if(value[ZX234290_REG_ADDR_TIMER_CTRL]&0x80)
+ seq_printf(s, "timer enable\n ");
+ else
+ seq_printf(s, "timer disable\n ");
+
+
+ return ret;
+}
+
+#define DEBUGFS_FILE_ENTRY(name) \
+static int debugfs_##name##_open(struct inode *inode, struct file *file) \
+{\
+return single_open(file, debugfs_##name##_show, inode->i_private); \
+}\
+\
+static const struct file_operations debugfs_##name##_fops = { \
+.owner= THIS_MODULE, \
+.open= debugfs_##name##_open, \
+.write=debugfs_##name##_write, \
+.read= seq_read, \
+.llseek= seq_lseek, \
+.release= single_release, \
+}
+
+DEBUGFS_FILE_ENTRY(regs);
+
+int zx234290_rtc_settimer(int sec);
+
+static int debugfs_adc_get(void *data, u64 *val)
+{
+ switch ((int)data) {
+ case 0:
+ *val = get_battery_voltage();
+ //zx234290_rtc_settimer(10);
+ break;
+ case 1:
+ *val = get_adc1_voltage();
+ break;
+ case 2:
+ *val = get_adc2_voltage();
+ break;
+ default:
+ *val = -1;
+ break;
+ }
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fops_adc_ro, debugfs_adc_get, NULL, "%llumV\n");
+
+static struct dentry *g_pmu_root;
+
+extern u32 int_irq_times;
+extern u32 int_thread_times;
+
+static void debugfs_pmu_init(struct zx234290 *zx234290)
+{
+ struct dentry *root;
+ struct dentry *node;
+ int i;
+
+ if(!zx234290)
+ return;
+ //create root
+ root = debugfs_create_dir("pmu_zx29", NULL);
+ if (!root){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(root));
+ goto err;
+ }
+ //print regs;
+ node = debugfs_create_file("regs", S_IRUGO | S_IWUGO, root, zx234290, &debugfs_regs_fops);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc0;
+ node = debugfs_create_file("adc0", S_IRUGO, root, 0, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc1;
+ node = debugfs_create_file("adc1", S_IRUGO, root, 1, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc2;
+ node = debugfs_create_file("adc2", S_IRUGO, root, 2, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print u32
+ debugfs_create_u32("irq_cnt", S_IRUGO, root, &int_irq_times);
+
+ //print u32
+ debugfs_create_u32("thread_cnt", S_IRUGO, root, &int_thread_times);
+
+ g_pmu_root = (void *)root;
+ return;
+err:
+ dev_err(zx234290->dev, "debugfs_pmu_init err\n");
+}
+
+#endif
+
+
+int zx234290_device_init(struct zx234290 *zx234290)
+{
+ //struct zx234290_board *pmic_plat_data = zx234290->dev->platform_data;
+ enum of_gpio_flags flags;
+ //struct zx234290_platform_data *init_data;
+ int ret;
+ int irq;
+
+ s_poweron_type_addr = (unsigned long)ioremap(POWERON_TYPE_ADDR,0x800);
+ get_boot_reason();
+ /*
+ init_data = kzalloc(sizeof(struct zx234290_platform_data), GFP_KERNEL);
+ if (init_data == NULL)
+ return -ENOMEM;
+ */
+ mutex_init(&zx234290->io_mutex);
+ dev_set_drvdata(zx234290->dev, zx234290);
+
+ ret = mfd_add_devices(zx234290->dev, -1,
+ zx234290_cell, ARRAY_SIZE(zx234290_cell),
+ NULL,0, 0);
+ if (ret < 0)
+ goto err;
+
+ gpio_num_pshold= of_get_gpio_flags(zx234290->dev->of_node, 0, &flags);
+ if (!gpio_is_valid(gpio_num_pshold)) {
+ pr_info("pmu pshold error\n");
+ }
+ gpio_direction_input(gpio_num_pshold);
+
+ //gpio_num_pshold = pmic_plat_data->pshold_gpio_num;//by yuxiang
+ // gpio_func_pshold= pmic_plat_data->pshold_gpio_func;//by yuxiang
+ if (!pm_power_off)
+ pm_power_off = zx234290_power_off;
+
+#ifdef PSHOLD_PULLUP_IN_POWEROFFCHARGING
+ /* CPE MDL don't control ps_hold pin. */
+ if (boot_reason == POWER_ON_CHARGING) {
+ zx234290_pshold_pull_up();
+ }
+#endif
+/***********PJT added **************/
+ zx234290_get_chip_version();
+ adc_wakelock = wakeup_source_register(NULL, "adc_wake");
+ if (!adc_wakelock)
+ return -ENOMEM;
+
+ //init_data->irq = pmic_plat_data->irq;
+ //init_data->irq_base = pmic_plat_data->irq_base;
+ //irq = gpio_to_irq(pmic_plat_data->irq_gpio_num);
+ ret = zx234290_irq_init(zx234290);
+ if (ret < 0)
+ goto err;
+
+ register_reboot_notifier(&pmu_reboot_notifier);
+
+#if defined(CONFIG_DEBUG_FS)
+ debugfs_pmu_init(zx234290);
+#endif
+ //kfree(init_data);
+ return ret;
+
+err:
+ //kfree(init_data);
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+ return ret;
+}
+
+void zx234290_device_exit(struct zx234290 *zx234290)
+{
+#if defined(CONFIG_DEBUG_FS)
+ if(g_pmu_root){
+ printk(KERN_INFO "zx234290_device_exit:debugfs_remove_recursive \n");
+ debugfs_remove_recursive(g_pmu_root);
+ }
+#endif
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+}
+
+
+MODULE_AUTHOR("yuxiang");
+MODULE_DESCRIPTION("ZX234290 chip family multi-function driver");
+MODULE_LICENSE("GPL");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
new file mode 100755
index 0000000..be7309c
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mmc/core/mmc_ramdump.c
@@ -0,0 +1,680 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2014, ÉîÛÚÊÐÖÐÐËͨѶ΢µç×Ó
+*
+* ÎļþÃû³Æ£º emmc_ramdump.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+//#include <common.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/mfd/zx234290.h>
+#include <linux/stddef.h>
+
+
+#define MMC1_REG_BASE 0x1211000
+#define MATRIX_CRM_REG_BASE 0x1306000
+#define CFG_EMMC_CLK_ENUM 400000
+#define CFG_EMMC_CLK_WORK 50000000
+#define CFG_EMMC_CLK_REF 50000000
+
+#define ZXMCI_FIFO_DEPTH 128
+#define MMC_BLOCK_SIZE 512
+
+#define mci_read(base, reg) \
+ (*(volatile u32*)(base + reg))
+#define mci_write(base, reg, value) \
+ (*(volatile u32*)(base+ reg) = (value))
+
+u8 mmc_data_buf[512]={0};
+//CMD register
+//bit6 1=response from card
+//bit7 1=long response from card
+//bit8 1=check response CRC
+//bit9 1=data transfer expect
+//bit12 1=send stop command at the end of data transfer
+//bit13 1=wait for previous data transfer completion before sending command
+#define R1 ((1 << 6) | (1 << 8))
+#define R2 ((1 << 6) | (1 << 7) | (1 << 8))
+#define R3 (1 << 6)
+#define CF_DATA ((1 << 9) | (1 << 12) | (1 << 13))
+#define CF_DATA_WR ((1 << 9)|(1 << 10) | (1 << 12) | (1 << 13))
+
+
+static u32 mmc_rca;
+static u32 block_addr = 1;
+//extern struct dw_mci *dw_mci_host_ptr[2];
+extern u32 * g_reg_base[2];
+struct mmc_cid
+{
+ u32 psn;
+ u8 oid;
+ u8 mid;
+ u8 prv;
+ u8 mdt;
+ char pnm[7];
+};
+
+// ¸´Î»EMMCʱÖÓ
+static void emmc_clk_reset(void)
+{
+return ;
+#if 0
+ volatile u32 *crm = (u32*)MATRIX_CRM_REG_BASE;
+
+ crm[0x50>>2] &= ~(0x7<<8);//bit8~10 000:26Mhz 001:100Mhz
+
+ crm[0x54>>2] |= 0x03 << 4; // clk enable
+
+ udelay(10);
+
+ crm[0x58>>2] |= 0x01 << 1; // reset release
+#endif
+}
+
+// emmc ·¢ËÍÃüÁî
+static int emmc_cmd(u32 cmd, u32 arg, void *resp, u32 flags)
+{
+
+#define ERR_STATUS (1 << 1 | 1 << 6 | 1 << 8) // bit1:response error
+ // bit6:response CRC error
+ // bit8:response timeout
+ volatile u32 i;
+ u32 cmdreg;
+ u32 *response = resp;
+ u32 response_words = 0;
+ // volatile u32 *emmc = (u32*)MMC1_REG_BASE;
+ u32 reg_val = 0;
+ u32 regs_base = g_reg_base[1];
+
+ //printk("(%s) cmd = %d start\n",__func__,cmd);
+
+ //Clear all raw interrupt status
+ reg_val = mci_read(regs_base,0x44);
+ mci_write(regs_base,0x44,reg_val|((u32)-1));
+
+ cmdreg = cmd & 0x3F;
+ cmdreg |= flags|(1 << 29) | 0x80000000;
+
+ if(flags &(1 << 7))
+ {
+ response_words = 4; // long response expected from card
+ }
+ else if(flags & (1 << 6))
+ {
+ response_words = 1; // response expected from card
+ }
+ //send command
+ reg_val = mci_read(regs_base,0x44);
+ mci_write(regs_base,0x44,reg_val|((u32)-1));
+ mci_write(regs_base,0x28,arg);
+ mci_write(regs_base,0x2C,cmdreg);
+
+ // check command done
+ i= 0;
+ do
+ {
+ udelay(10);
+ if(++i > 1000)
+ {
+ printk("SEND CMD FAILED,CMD = %d,reg= 0x%x\n",cmd,mci_read(regs_base,0x44));
+
+ break;
+ }
+
+ } while(!(mci_read(regs_base,0x44) & (1 << 2)));
+
+ // check error
+ if(mci_read(regs_base,0x44) & ERR_STATUS)
+ {
+
+ printk("SEND CMD ERR,reg_0x44=0x%x\n",mci_read(regs_base,0x44));
+ return -1;
+ }
+
+ if(response == NULL)
+ return 0;
+
+ for(i = 0; i < response_words; i++)
+ {
+ response[i]= mci_read(regs_base,(0x30 + i));
+ }
+
+ return 0;
+}
+
+//¸´Î»ËùÓп¨£¬Ê¹Æä½øÈëIDLE״̬
+static u32 emmc_idle_cards(void)
+{
+ int i;
+ u32 ret;
+ u32 regs_base = g_reg_base[1];
+
+ // Reset and initialize all cards
+ ret = (u32)emmc_cmd(0, 0, NULL, (1 << 15));
+ if(ret)
+ {
+ printk("ENTER IDLE ERR\n");
+ return (int)ret;
+ }
+
+ // wait for 80 clock at least
+ for(i = 0; i < 100; i++)
+ {
+ ret = mci_read(regs_base,0x70);
+ }
+
+ return 0;
+}
+
+//·¢ËÍCMD1
+static inline int mmc_send_op_cond(u32 ocr,u32 *rocr)
+{
+ int i;
+ int ret = 0;
+ u32 resp[4];
+
+ // ÖÁÉÙ1s£¬ÕâÀïÉèÖÃΪ4s
+ for(i = 50000; i > 0; i--)
+ {
+ ret = emmc_cmd(1,ocr,resp,R3);
+ if(ret)
+ break;
+
+ if(ocr == 0)
+ break;
+ if(resp[0] & 0x80000000)
+ break;
+
+ udelay(80);
+
+ ret= -1;
+ }
+
+ if(rocr)
+ *rocr = resp[0];
+
+ return ret;
+}
+
+//ö¾ÙEMMC¿¨
+static u32 ramdump_mmc_init_card(struct mmc_cid *cid, u32 ocr)
+{
+ u32 resp[4];
+ u32 rocr;
+
+ // CMD0
+ emmc_idle_cards();
+
+ // CMD1
+ mmc_send_op_cond(ocr/* | (1 << 30)*/, &rocr);
+
+ if((rocr & 0x80000000) != 0)
+ {
+ if((rocr & 0x40000000) == 0)
+ {
+ block_addr = 0;
+ }
+ else
+ {
+ block_addr = 1;
+ }
+ }
+ else
+ {
+ printk("ERR\n");
+ }
+ // CMD2
+ emmc_cmd(2, 0, resp, R2);
+
+ // CMD3
+ // Set RCA of the card that responded
+
+ mmc_rca = 1 << 16;
+ emmc_cmd(3, mmc_rca, resp, R1);
+
+ return 0;
+}
+
+// card detected numbers
+static inline int emmc_card_present(void)
+{
+ u32 regs_base = g_reg_base[1];
+
+ return ((mci_read(regs_base,0x50) & 0x3FFFFFFF) != 0x01);
+}
+
+// ²ÉÓÃCPU¶ÁÈ¡FIFO£¬½ûÖ¹ÖжÏ
+static inline void emmc_init(void)
+{
+ u32 tmp,cardnums;
+ u32 i = 0;
+ u32 reg_val=0;
+ u32 regs_base = g_reg_base[1];
+
+ mci_read(regs_base,0x00) = (0 << 5)|(1 << 1)|(1 << 0); //½ûÖ¹dma //¸´Î»fifo //¸´Î»¿ØÖÆÆ÷
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00)&3);
+
+ cardnums = mci_read(regs_base,0x70)&0x3E;
+ cardnums = (cardnums >> 1) + 1;
+
+ //ÉèÖÃCTRL¼Ä´æÆ÷£¬¶ÔÓÚMMC-Ver3.3-onlyģʽ£¬ÐèÒªÉèÖÃenable_OD_pullupλ¡£
+ mci_write(regs_base,0x00,0x0);
+
+ //¸øCARD¹©µç
+ mci_write(regs_base,0x04,0x01);
+ //µÈ´ýµçÔ´Îȶ¨
+ udelay(500);
+
+ //ÇåÖжÏ״̬¼Ä´æÆ÷£¬ÒÔ¼°ÉèÖÃINTMSK¼Ä´æÆ÷
+ mci_write(regs_base,0x44,((u32)-1));
+ //ÆÁ±ÎËùÓÐÖжϣ¬¸ß16λÊǶÔÓ¦sdio£¬µÍ16λ¶ÔӦÿ¸ö¿¨
+ mci_write(regs_base,0x24,0x00);
+
+ //ÐÞ¸ÄCARDµÄʱÖÓÔ´¡£ÎÒÃÇÓõÄʱÖÓÀ´Ô´ÊÇclksrc0. 2bit¶ÔÓ¦Ò»¸ö¿¨(32/2=16)
+ mci_write(regs_base,0x0C,0x0);
+
+ //ÉèÖÃHOST IPµÄһЩȱʡ²ÎÊý¡£¶ÔÓ¦TMOUT,DEBNCE,FIFOTH¼Ä´æÆ÷
+ mci_write(regs_base,0x14,((u32)-1)); //data_timeout
+ //response_timeout,ĬÈÏ0x40
+ //·´Ìø¼ÆÊý¼Ä´æÆ÷,25ms
+ mci_write(regs_base,0x64,0xFFFFFF);
+
+ //fifo·§ÖµÎªÄ¬ÈÏ
+ tmp = (2 << 28) |(((ZXMCI_FIFO_DEPTH >> 1)-1) << 16) |((ZXMCI_FIFO_DEPTH >> 1) << 0); //dma multiple transaction size,ÄÚ²¿dma//RX WMARK //TX WMARK
+ mci_write(regs_base,0x4c,tmp);
+
+ //SD¿¨ÉϵçÖ®ºó£¬ÔËÐÐÔÚ1BITģʽ£¬ËùÒÔÈ·±£host¹¤×÷ÔÚ1BITģʽ
+ mci_write(regs_base,0x18,0);
+ mci_write(regs_base,0x100,1);
+
+ //ÉèÖÃCTRL¼Ä´æÆ÷£¬ÔÊÐíÖжÏ
+ mci_write(regs_base,0x00,(0 << 5)|(0 << 4)|(1 << 1));// ½ûÖ¹dma // ½ûֹȫ¾ÖÖжÏ// ¸´Î»fifo
+
+ i= 0;
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("FIFO RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00)& 2);
+}
+//¸üÐÂʱÖÓ
+static int emmc_update_clock_reg_only(void)
+{
+ //Ö»ÐèÒªÖÃλbit21,ÒòΪ²»·¢Ë͵½¿¨£¬ËùÒÔ²»»á²úÉúÖжÏ
+ u32 rintsts;
+ u32 repeat = 0;
+ u32 cmdr = (1 << 21)| (1 << 13) | 0x80000000;
+ u32 regs_base = g_reg_base[1];
+
+ do
+ {
+ mci_write(regs_base,0x2c,cmdr);
+ rintsts = mci_read(regs_base,0x44);
+ repeat++;
+ } while(((rintsts & (1 << 12)) != 0) && (repeat < 10));
+
+ if(repeat >= 10)
+ {
+ printk("HW LOCK ERR\n");
+ return -2;
+ }
+
+ repeat = 0;
+
+ while((mci_read(regs_base,0x2C) & 0x80000000) != 0)
+ {
+ udelay(50);
+ if(++repeat >=1000)
+ {
+ printk("UPDATE CLOCK TIMEOUT\n");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+//ÉèÖÃʱÖÓ
+static inline void emmc_set_clk(u32 clock)
+{
+ u32 clk_div;
+ u32 regs_base = g_reg_base[1];
+
+ //ʱÖӵıà³ÌÁ÷³Ì£¬²Î¿¼IPÊÖ²áP167
+ //È·±£CardûÓÐÔÚ´«ÊäÊý¾Ý
+ //½ûÖ¹ËùÓÐʱÖÓ
+ mci_write(regs_base,0x10,0x0);
+ emmc_update_clock_reg_only();
+ //ÉèÖÃCLKDIV,CLKSRCÁ½¸ö¼Ä´æÆ÷£¬CLKSRC²ÉÓÃĬÈÏÖµ
+ //ÕâÀïÓÃÄ£¿éʱÖÓ2·ÖƵ = 66625000.ÎÒÃǵķÖƵÆ÷¿ÉÒÔ×öµ½2*n(n=255) = 510¸ö·ÖƵ,0=1·ÖƵ
+ //ËùÒÔ×îµÍƵÂÊΪ66625000/510 = 130.637KHz,×î´ó= 66625000.
+ if(clock <= (CFG_EMMC_CLK_REF / 510))
+ {
+ clk_div = 0xff;
+ }
+ else
+ {
+ clk_div = (CFG_EMMC_CLK_REF + clock )/((clock<<1)+1);//ËÄÉáÎåÈë
+ }
+ mci_write(regs_base,0x08,clk_div);
+ emmc_update_clock_reg_only();
+
+ //ÖØÐÂʹÄÜʱÖÓ
+ //»Ö¸´Ê±ÖÓ.¸ß16λ1=µÍ¹¦ºÄģʽ
+ mci_write(regs_base,0x10,0x001);
+ emmc_update_clock_reg_only();
+
+}
+//·¢ËÍEMMC¶ÁÃüÁî
+static s32 zx_mmc_read(u32 src, u8 * dst, u32 size)
+{
+ int ret;
+ u32 resp, data, wordcount, start_addr, fifo_cnt;
+ volatile u32 i= 0;
+ volatile u32 j= 0;
+ u32 *p= (u32 *)dst;
+ u32 regs_base = g_reg_base[1];
+
+ if(size == 0)
+ return -1;
+
+ while((mci_read(regs_base,0x48) & (1 << 9)) != 0)
+ {
+ udelay(10);
+
+ if(++i > 200)
+ break;
+ }
+
+ start_addr = src;
+ data = mci_read(regs_base,0x00) | (1 << 1);
+ mci_write(regs_base,0x00,data);
+ mci_write(regs_base,0x20,size);
+ mci_write(regs_base,0x1C,MMC_BLOCK_SIZE);
+
+ i = 0;
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("FIFO RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00) & 0x02);
+
+
+ if (size > 512)
+ {
+ ret = emmc_cmd(18,start_addr, &resp,(R1 | CF_DATA));
+ if(ret)
+ return -18;
+ }
+ else
+ {
+ ret = emmc_cmd(17,start_addr, &resp,(R1 | CF_DATA));
+ if(ret)
+ return -17;
+ }
+
+ wordcount = 0;
+ do
+ {
+ fifo_cnt =((mci_read(regs_base,0x48) >> 17) & 0x1FFF);
+
+ for(j = 0; j < fifo_cnt; j++)
+ {
+ data = mci_read(regs_base,0x200);
+ *p++= data;
+ wordcount++;
+ }
+
+ } while(wordcount < (size >> 2));
+ udelay(2000);
+
+ return 0;
+
+}
+
+static int zx_mmc_write(u32 blknr, u8 * src_buf, u32 size)
+{
+ int ret;
+ u32 resp, data, wordcount, start_addr, fifo_cnt;
+ volatile u32 i= 0;
+ volatile u32 j= 0;
+ u32 *p= (u32 *)src_buf;
+ u32 regs_base = g_reg_base[1];
+ u32 write_count_per =0;
+
+ if(size == 0)
+ return -1;
+
+ while((mci_read(regs_base,0x48) & (1 << 9)) != 0)
+ {
+ udelay(10);
+
+ if(++i > 200)
+ break;
+ }
+
+ start_addr = blknr;
+ data = mci_read(regs_base,0x00) | (1 << 1);
+ mci_write(regs_base,0x00,data);
+ mci_write(regs_base,0x20,size);
+ mci_write(regs_base,0x1C,MMC_BLOCK_SIZE);
+
+ i = 0;
+ do
+ {
+ udelay(10);
+ if(++i > 100)
+ {
+ printk("FIFO RESET FAILED\n");
+ break;
+ }
+ } while(mci_read(regs_base,0x00) & 0x02);
+
+
+ if (size > 512)
+ {
+
+ ret = emmc_cmd(25,start_addr, &resp,(R1 | CF_DATA_WR));
+ if(ret)
+ return -18;
+ }
+ else
+ {
+
+ ret = emmc_cmd(24,start_addr, &resp,(R1 | CF_DATA_WR));
+ if(ret)
+ return -17;
+ }
+
+ wordcount = 0;
+
+ do
+ {
+ fifo_cnt =((mci_read(regs_base,0x48) >> 17) & 0x1FFF);
+ write_count_per = min(((size-wordcount)>>2),(ZXMCI_FIFO_DEPTH-fifo_cnt));
+
+ for(j = 0; j < write_count_per; j++)
+ {
+ mci_write(regs_base,0x200,*p++);
+ wordcount = wordcount+4;
+ }
+
+ } while(size-wordcount);
+
+ udelay(2000);
+
+ return 0;
+
+}
+
+//ÉèÖöÁÊý¾Ý´óС
+int mmc_bread(u32 start_addr, u32 data_size, void *dst)
+{
+ int ret;
+ u32 src = 0;
+ u32 blk_count;
+ u32 remain = 0;
+
+ if((start_addr%MMC_BLOCK_SIZE)||(data_size==0)||(dst==NULL))
+ return -1;//err start addr
+
+ blk_count = data_size/MMC_BLOCK_SIZE;
+ remain = data_size%MMC_BLOCK_SIZE;
+ if(remain)
+ memset(&mmc_data_buf,0x0,MMC_BLOCK_SIZE);
+
+ if(block_addr == 0)
+ src = start_addr;
+ else
+ src = start_addr/MMC_BLOCK_SIZE;
+
+ if(blk_count){
+ ret= zx_mmc_read(src, (u8 *) dst, blk_count * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("READ ERR\n");
+ return -1;
+ }
+ }
+
+ if(remain){/*transfer remain*/
+
+ ret= zx_mmc_read(src+blk_count, (u8 *)&mmc_data_buf, 1 * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("READ ERR\n");
+ return -1;
+ }
+ memcpy((dst+blk_count * MMC_BLOCK_SIZE),&mmc_data_buf,remain);
+ }
+
+ return data_size;
+}
+
+int mmc_bwrite(u32 start_addr, u32 data_size, void *src_buf)
+{
+ int ret;
+ u32 start_blk = 0;
+ u32 blk_count;
+ u32 remain = 0;
+ u32 resp[4];
+
+ if((start_addr%MMC_BLOCK_SIZE)||(data_size==0)||(src_buf==NULL))
+ return -1;//err start addr
+
+ blk_count = data_size/MMC_BLOCK_SIZE;
+ remain = data_size%MMC_BLOCK_SIZE;
+ if(remain){
+ memset(&mmc_data_buf,0x00,MMC_BLOCK_SIZE);
+ memcpy(&mmc_data_buf,(src_buf+blk_count*MMC_BLOCK_SIZE),remain);
+ }
+
+ if(block_addr == 0)
+ start_blk = start_addr;
+ else
+ start_blk = (start_addr/MMC_BLOCK_SIZE);
+
+ if(blk_count){
+ ret= zx_mmc_write(start_blk, (u8 *)src_buf, blk_count * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("WRITE ERR\n");
+ return -1;
+ }
+
+ resp[0]=0;
+ do{
+ emmc_cmd(13, (1<<16), resp, R1);
+ }while(((resp[0] & 0x00001E00) >> 9)!= 4);
+ }
+
+ if(remain){/*transfer remain*/
+
+ ret= zx_mmc_write((start_blk+blk_count), (u8 *)&mmc_data_buf, 1 * MMC_BLOCK_SIZE);
+ if(ret < 0)
+ {
+ printk("WRITE remain ERR\n");
+ return -1;
+ }
+
+ resp[0]=0;
+ do{
+ emmc_cmd(13, (1<<16), resp, R1);
+ }while(((resp[0] & 0x00001E00) >> 9)!= 4);
+ }
+ return data_size;
+}
+
+
+// ¶Á4KÊý¾Ý,½öÖ§³Öemmc£¬ºóÐø¿ÉÒÔ¿¼ÂÇ×Ô¶¯Ê¶±ð
+int mmc_ramdump_init(void)
+{
+ struct mmc_cid cid;
+ u32 resp[4];
+ u32 ocr;
+ int ret = 0;
+ block_addr = 0;
+
+ //zDrvPmic_SetNormal_Onoff_PSM(VSD1,PM_DISABLE);
+ //mdelay(10);
+ //zDrvPmic_SetNormal_Onoff_PSM(VSD1,PM_ENABLE);
+ // emmc_clk_reset();
+ emmc_init();
+
+ if(!emmc_card_present())
+ {
+ printk("NO EMMC\n");
+ return -1;
+ }
+
+ emmc_set_clk(CFG_EMMC_CLK_ENUM);
+ emmc_idle_cards();
+
+ ret = mmc_send_op_cond(0, &ocr);
+
+ if(!ret)
+ {
+ ramdump_mmc_init_card(&cid, ocr);
+
+ emmc_cmd(9, mmc_rca, resp, R2);
+
+ ret = emmc_cmd(7, mmc_rca, resp, R1);
+
+ if(ret)
+ {
+ return ret;
+ }
+
+ emmc_cmd(16, 512, resp, R1);
+
+ emmc_set_clk(CFG_EMMC_CLK_WORK);
+ }
+
+// mmc_bread(0, 0, 8, (void *)CFG_LOAD_BASE);
+
+ return 0;
+}
+
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mtd/mtdcore.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mtd/mtdcore.c
new file mode 100755
index 0000000..a52a2c8
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/mtd/mtdcore.c
@@ -0,0 +1,2257 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Core registration and callback routines for MTD
+ * drivers and users.
+ *
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
+ * Copyright © 2006 Red Hat UK Limited
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/ioctl.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/proc_fs.h>
+#include <linux/idr.h>
+#include <linux/backing-dev.h>
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/reboot.h>
+#include <linux/leds.h>
+#include <linux/debugfs.h>
+#include <linux/nvmem-provider.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include "mtdcore.h"
+
+struct backing_dev_info *mtd_bdi;
+
+#ifdef CONFIG_PM_SLEEP
+
+static int mtd_cls_suspend(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return mtd ? mtd_suspend(mtd) : 0;
+}
+
+static int mtd_cls_resume(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ if (mtd)
+ mtd_resume(mtd);
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mtd_cls_pm_ops, mtd_cls_suspend, mtd_cls_resume);
+#define MTD_CLS_PM_OPS (&mtd_cls_pm_ops)
+#else
+#define MTD_CLS_PM_OPS NULL
+#endif
+
+static struct class mtd_class = {
+ .name = "mtd",
+ .owner = THIS_MODULE,
+ .pm = MTD_CLS_PM_OPS,
+};
+
+static DEFINE_IDR(mtd_idr);
+
+/* These are exported solely for the purpose of mtd_blkdevs.c. You
+ should not use them for _anything_ else */
+DEFINE_MUTEX(mtd_table_mutex);
+EXPORT_SYMBOL_GPL(mtd_table_mutex);
+
+struct mtd_info *__mtd_next_device(int i)
+{
+ return idr_get_next(&mtd_idr, &i);
+}
+EXPORT_SYMBOL_GPL(__mtd_next_device);
+
+static LIST_HEAD(mtd_notifiers);
+
+
+#define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2)
+
+/* REVISIT once MTD uses the driver model better, whoever allocates
+ * the mtd_info will probably want to use the release() hook...
+ */
+static void mtd_release(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ dev_t index = MTD_DEVT(mtd->index);
+
+ /* remove /dev/mtdXro node */
+ device_destroy(&mtd_class, index + 1);
+}
+
+static ssize_t mtd_type_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ char *type;
+
+ switch (mtd->type) {
+ case MTD_ABSENT:
+ type = "absent";
+ break;
+ case MTD_RAM:
+ type = "ram";
+ break;
+ case MTD_ROM:
+ type = "rom";
+ break;
+ case MTD_NORFLASH:
+ type = "nor";
+ break;
+ case MTD_NANDFLASH:
+ type = "nand";
+ break;
+ case MTD_DATAFLASH:
+ type = "dataflash";
+ break;
+ case MTD_UBIVOLUME:
+ type = "ubi";
+ break;
+ case MTD_MLCNANDFLASH:
+ type = "mlc-nand";
+ break;
+ default:
+ type = "unknown";
+ }
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", type);
+}
+static DEVICE_ATTR(type, S_IRUGO, mtd_type_show, NULL);
+
+static ssize_t mtd_flags_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)mtd->flags);
+}
+static DEVICE_ATTR(flags, S_IRUGO, mtd_flags_show, NULL);
+
+static ssize_t mtd_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%llu\n",
+ (unsigned long long)mtd->size);
+}
+static DEVICE_ATTR(size, S_IRUGO, mtd_size_show, NULL);
+
+static ssize_t mtd_erasesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize);
+}
+static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL);
+
+static ssize_t mtd_writesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->writesize);
+}
+static DEVICE_ATTR(writesize, S_IRUGO, mtd_writesize_show, NULL);
+
+static ssize_t mtd_subpagesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int subpagesize = mtd->writesize >> mtd->subpage_sft;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", subpagesize);
+}
+static DEVICE_ATTR(subpagesize, S_IRUGO, mtd_subpagesize_show, NULL);
+
+static ssize_t mtd_oobsize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->oobsize);
+}
+static DEVICE_ATTR(oobsize, S_IRUGO, mtd_oobsize_show, NULL);
+
+static ssize_t mtd_oobavail_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->oobavail);
+}
+static DEVICE_ATTR(oobavail, S_IRUGO, mtd_oobavail_show, NULL);
+
+static ssize_t mtd_numeraseregions_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->numeraseregions);
+}
+static DEVICE_ATTR(numeraseregions, S_IRUGO, mtd_numeraseregions_show,
+ NULL);
+
+static ssize_t mtd_name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", mtd->name);
+}
+static DEVICE_ATTR(name, S_IRUGO, mtd_name_show, NULL);
+
+static ssize_t mtd_ecc_strength_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_strength);
+}
+static DEVICE_ATTR(ecc_strength, S_IRUGO, mtd_ecc_strength_show, NULL);
+
+static ssize_t mtd_bitflip_threshold_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->bitflip_threshold);
+}
+
+static ssize_t mtd_bitflip_threshold_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int bitflip_threshold;
+ int retval;
+
+ retval = kstrtouint(buf, 0, &bitflip_threshold);
+ if (retval)
+ return retval;
+
+ mtd->bitflip_threshold = bitflip_threshold;
+ return count;
+}
+static DEVICE_ATTR(bitflip_threshold, S_IRUGO | S_IWUSR,
+ mtd_bitflip_threshold_show,
+ mtd_bitflip_threshold_store);
+
+static ssize_t mtd_ecc_step_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_step_size);
+
+}
+static DEVICE_ATTR(ecc_step_size, S_IRUGO, mtd_ecc_step_size_show, NULL);
+
+static ssize_t mtd_ecc_stats_corrected_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->corrected);
+}
+static DEVICE_ATTR(corrected_bits, S_IRUGO,
+ mtd_ecc_stats_corrected_show, NULL);
+
+static ssize_t mtd_ecc_stats_errors_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->failed);
+}
+static DEVICE_ATTR(ecc_failures, S_IRUGO, mtd_ecc_stats_errors_show, NULL);
+
+static ssize_t mtd_badblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->badblocks);
+}
+static DEVICE_ATTR(bad_blocks, S_IRUGO, mtd_badblocks_show, NULL);
+
+static ssize_t mtd_bbtblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->bbtblocks);
+}
+static DEVICE_ATTR(bbt_blocks, S_IRUGO, mtd_bbtblocks_show, NULL);
+
+static struct attribute *mtd_attrs[] = {
+ &dev_attr_type.attr,
+ &dev_attr_flags.attr,
+ &dev_attr_size.attr,
+ &dev_attr_erasesize.attr,
+ &dev_attr_writesize.attr,
+ &dev_attr_subpagesize.attr,
+ &dev_attr_oobsize.attr,
+ &dev_attr_oobavail.attr,
+ &dev_attr_numeraseregions.attr,
+ &dev_attr_name.attr,
+ &dev_attr_ecc_strength.attr,
+ &dev_attr_ecc_step_size.attr,
+ &dev_attr_corrected_bits.attr,
+ &dev_attr_ecc_failures.attr,
+ &dev_attr_bad_blocks.attr,
+ &dev_attr_bbt_blocks.attr,
+ &dev_attr_bitflip_threshold.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(mtd);
+
+static const struct device_type mtd_devtype = {
+ .name = "mtd",
+ .groups = mtd_groups,
+ .release = mtd_release,
+};
+
+static int mtd_partid_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partid);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partid_debug);
+
+static int mtd_partname_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partname);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partname_debug);
+
+static struct dentry *dfs_dir_mtd;
+
+static void mtd_debugfs_populate(struct mtd_info *mtd)
+{
+ struct device *dev = &mtd->dev;
+ struct dentry *root;
+
+ if (IS_ERR_OR_NULL(dfs_dir_mtd))
+ return;
+
+ root = debugfs_create_dir(dev_name(dev), dfs_dir_mtd);
+ mtd->dbg.dfs_dir = root;
+
+ if (mtd->dbg.partid)
+ debugfs_create_file("partid", 0400, root, mtd,
+ &mtd_partid_debug_fops);
+
+ if (mtd->dbg.partname)
+ debugfs_create_file("partname", 0400, root, mtd,
+ &mtd_partname_debug_fops);
+}
+
+#ifndef CONFIG_MMU
+unsigned mtd_mmap_capabilities(struct mtd_info *mtd)
+{
+ switch (mtd->type) {
+ case MTD_RAM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ | NOMMU_MAP_WRITE;
+ case MTD_ROM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ;
+ default:
+ return NOMMU_MAP_COPY;
+ }
+}
+EXPORT_SYMBOL_GPL(mtd_mmap_capabilities);
+#endif
+
+static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
+ void *cmd)
+{
+ struct mtd_info *mtd;
+
+ mtd = container_of(n, struct mtd_info, reboot_notifier);
+ mtd->_reboot(mtd);
+
+ return NOTIFY_DONE;
+}
+
+/**
+ * mtd_wunit_to_pairing_info - get pairing information of a wunit
+ * @mtd: pointer to new MTD device info structure
+ * @wunit: write unit we are interested in
+ * @info: returned pairing information
+ *
+ * Retrieve pairing information associated to the wunit.
+ * This is mainly useful when dealing with MLC/TLC NANDs where pages can be
+ * paired together, and where programming a page may influence the page it is
+ * paired with.
+ * The notion of page is replaced by the term wunit (write-unit) to stay
+ * consistent with the ->writesize field.
+ *
+ * The @wunit argument can be extracted from an absolute offset using
+ * mtd_offset_to_wunit(). @info is filled with the pairing information attached
+ * to @wunit.
+ *
+ * From the pairing info the MTD user can find all the wunits paired with
+ * @wunit using the following loop:
+ *
+ * for (i = 0; i < mtd_pairing_groups(mtd); i++) {
+ * info.pair = i;
+ * mtd_pairing_info_to_wunit(mtd, &info);
+ * ...
+ * }
+ */
+int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
+ struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master);
+
+ if (wunit < 0 || wunit >= npairs)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_info)
+ return master->pairing->get_info(master, wunit, info);
+
+ info->group = 0;
+ info->pair = wunit;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info);
+
+/**
+ * mtd_pairing_info_to_wunit - get wunit from pairing information
+ * @mtd: pointer to new MTD device info structure
+ * @info: pairing information struct
+ *
+ * Returns a positive number representing the wunit associated to the info
+ * struct, or a negative error code.
+ *
+ * This is the reverse of mtd_wunit_to_pairing_info(), and can help one to
+ * iterate over all wunits of a given pair (see mtd_wunit_to_pairing_info()
+ * doc).
+ *
+ * It can also be used to only program the first page of each pair (i.e.
+ * page attached to group 0), which allows one to use an MLC NAND in
+ * software-emulated SLC mode:
+ *
+ * info.group = 0;
+ * npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
+ * for (info.pair = 0; info.pair < npairs; info.pair++) {
+ * wunit = mtd_pairing_info_to_wunit(mtd, &info);
+ * mtd_write(mtd, mtd_wunit_to_offset(mtd, blkoffs, wunit),
+ * mtd->writesize, &retlen, buf + (i * mtd->writesize));
+ * }
+ */
+int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
+ const struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+
+ if (!info || info->pair < 0 || info->pair >= npairs ||
+ info->group < 0 || info->group >= ngroups)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_wunit)
+ return mtd->pairing->get_wunit(master, info);
+
+ return info->pair;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit);
+
+/**
+ * mtd_pairing_groups - get the number of pairing groups
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Returns the number of pairing groups.
+ *
+ * This number is usually equal to the number of bits exposed by a single
+ * cell, and can be used in conjunction with mtd_pairing_info_to_wunit()
+ * to iterate over all pages of a given pair.
+ */
+int mtd_pairing_groups(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->pairing || !master->pairing->ngroups)
+ return 1;
+
+ return master->pairing->ngroups;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_groups);
+
+static int mtd_nvmem_reg_read(void *priv, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct mtd_info *mtd = priv;
+ size_t retlen;
+ int err;
+
+ err = mtd_read(mtd, offset, bytes, &retlen, val);
+ if (err && err != -EUCLEAN)
+ return err;
+
+ return retlen == bytes ? 0 : -EIO;
+}
+
+static int mtd_nvmem_add(struct mtd_info *mtd)
+{
+ struct nvmem_config config = {};
+
+ config.id = -1;
+ config.dev = &mtd->dev;
+ config.name = dev_name(&mtd->dev);
+ config.owner = THIS_MODULE;
+ config.reg_read = mtd_nvmem_reg_read;
+ config.size = mtd->size;
+ config.word_size = 1;
+ config.stride = 1;
+ config.read_only = true;
+ config.root_only = true;
+ config.no_of_node = true;
+ config.priv = mtd;
+
+ mtd->nvmem = nvmem_register(&config);
+ if (IS_ERR(mtd->nvmem)) {
+ /* Just ignore if there is no NVMEM support in the kernel */
+ if (PTR_ERR(mtd->nvmem) == -EOPNOTSUPP) {
+ mtd->nvmem = NULL;
+ } else {
+ dev_err(&mtd->dev, "Failed to register NVMEM device\n");
+ return PTR_ERR(mtd->nvmem);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * add_mtd_device - register an MTD device
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Add a device to the list of MTD devices present in the system, and
+ * notify each currently active MTD 'user' of its arrival. Returns
+ * zero on success or non-zero on failure.
+ */
+
+int add_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_notifier *not;
+ int i, error;
+
+ /*
+ * May occur, for instance, on buggy drivers which call
+ * mtd_device_parse_register() multiple times on the same master MTD,
+ * especially with CONFIG_MTD_PARTITIONED_MASTER=y.
+ */
+ if (WARN_ONCE(mtd->dev.type, "MTD already registered\n"))
+ return -EEXIST;
+
+ BUG_ON(mtd->writesize == 0);
+
+ /*
+ * MTD drivers should implement ->_{write,read}() or
+ * ->_{write,read}_oob(), but not both.
+ */
+ if (WARN_ON((mtd->_write && mtd->_write_oob) ||
+ (mtd->_read && mtd->_read_oob)))
+ return -EINVAL;
+
+ if (WARN_ON((!mtd->erasesize || !master->_erase) &&
+ !(mtd->flags & MTD_NO_ERASE)))
+ return -EINVAL;
+
+ /*
+ * MTD_SLC_ON_MLC_EMULATION can only be set on partitions, when the
+ * master is an MLC NAND and has a proper pairing scheme defined.
+ * We also reject masters that implement ->_writev() for now, because
+ * NAND controller drivers don't implement this hook, and adding the
+ * SLC -> MLC address/length conversion to this path is useless if we
+ * don't have a user.
+ */
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION &&
+ (!mtd_is_partition(mtd) || master->type != MTD_MLCNANDFLASH ||
+ !master->pairing || master->_writev))
+ return -EINVAL;
+
+ mutex_lock(&mtd_table_mutex);
+
+ i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL);
+ if (i < 0) {
+ error = i;
+ goto fail_locked;
+ }
+
+ mtd->index = i;
+ mtd->usecount = 0;
+
+ /* default value if not set by driver */
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ int ngroups = mtd_pairing_groups(master);
+
+ mtd->erasesize /= ngroups;
+ mtd->size = (u64)mtd_div_by_eb(mtd->size, master) *
+ mtd->erasesize;
+ }
+
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+
+ mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+ mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+
+ /* Some chips always power up locked. Unlock them now */
+ if ((mtd->flags & MTD_WRITEABLE) && (mtd->flags & MTD_POWERUP_LOCK)) {
+ error = mtd_unlock(mtd, 0, mtd->size);
+ if (error && error != -EOPNOTSUPP)
+ printk(KERN_WARNING
+ "%s: unlock failed, writes may not work\n",
+ mtd->name);
+ /* Ignore unlock failures? */
+ error = 0;
+ }
+
+ /* Caller should have set dev.parent to match the
+ * physical device, if appropriate.
+ */
+ mtd->dev.type = &mtd_devtype;
+ mtd->dev.class = &mtd_class;
+ mtd->dev.devt = MTD_DEVT(i);
+ dev_set_name(&mtd->dev, "mtd%d", i);
+ dev_set_drvdata(&mtd->dev, mtd);
+ of_node_get(mtd_get_of_node(mtd));
+ error = device_register(&mtd->dev);
+ if (error)
+ goto fail_added;
+
+ /* Add the nvmem provider */
+ error = mtd_nvmem_add(mtd);
+ if (error)
+ goto fail_nvmem_add;
+
+ mtd_debugfs_populate(mtd);
+
+ device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
+ "mtd%dro", i);
+
+ pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name);
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+ /* We _know_ we aren't being removed, because
+ our caller is still holding us here. So none
+ of this try_ nonsense, and no bitching about it
+ either. :) */
+ __module_get(THIS_MODULE);
+ return 0;
+
+fail_nvmem_add:
+ device_unregister(&mtd->dev);
+fail_added:
+ of_node_put(mtd_get_of_node(mtd));
+ idr_remove(&mtd_idr, i);
+fail_locked:
+ mutex_unlock(&mtd_table_mutex);
+ return error;
+}
+
+/**
+ * del_mtd_device - unregister an MTD device
+ * @mtd: pointer to MTD device info structure
+ *
+ * Remove a device from the list of MTD devices present in the system,
+ * and notify each currently active MTD 'user' of its departure.
+ * Returns zero on success or 1 on failure, which currently will happen
+ * if the requested device does not appear to be present in the list.
+ */
+
+int del_mtd_device(struct mtd_info *mtd)
+{
+ int ret;
+ struct mtd_notifier *not;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (idr_find(&mtd_idr, mtd->index) != mtd) {
+ ret = -ENODEV;
+ goto out_error;
+ }
+
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->remove(mtd);
+
+ if (mtd->usecount) {
+ printk(KERN_NOTICE "Removing MTD device #%d (%s) with use count %d\n",
+ mtd->index, mtd->name, mtd->usecount);
+ ret = -EBUSY;
+ } else {
+ debugfs_remove_recursive(mtd->dbg.dfs_dir);
+
+ /* Try to remove the NVMEM provider */
+ if (mtd->nvmem)
+ nvmem_unregister(mtd->nvmem);
+
+ device_unregister(&mtd->dev);
+
+ idr_remove(&mtd_idr, mtd->index);
+ of_node_put(mtd_get_of_node(mtd));
+
+ module_put(THIS_MODULE);
+ ret = 0;
+ }
+
+out_error:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+
+/*
+ * Set a few defaults based on the parent devices, if not provided by the
+ * driver
+ */
+static void mtd_set_dev_defaults(struct mtd_info *mtd)
+{
+ if (mtd->dev.parent) {
+ if (!mtd->owner && mtd->dev.parent->driver)
+ mtd->owner = mtd->dev.parent->driver->owner;
+ if (!mtd->name)
+ mtd->name = dev_name(mtd->dev.parent);
+ } else {
+ pr_debug("mtd device won't show a device symlink in sysfs\n");
+ }
+
+ INIT_LIST_HEAD(&mtd->partitions);
+ mutex_init(&mtd->master.partitions_lock);
+}
+
+/**
+ * mtd_device_parse_register - parse partitions and register an MTD device.
+ *
+ * @mtd: the MTD device to register
+ * @types: the list of MTD partition probes to try, see
+ * 'parse_mtd_partitions()' for more information
+ * @parser_data: MTD partition parser-specific data
+ * @parts: fallback partition information to register, if parsing fails;
+ * only valid if %nr_parts > %0
+ * @nr_parts: the number of partitions in parts, if zero then the full
+ * MTD device is registered if no partition info is found
+ *
+ * This function aggregates MTD partitions parsing (done by
+ * 'parse_mtd_partitions()') and MTD device and partitions registering. It
+ * basically follows the most common pattern found in many MTD drivers:
+ *
+ * * If the MTD_PARTITIONED_MASTER option is set, then the device as a whole is
+ * registered first.
+ * * Then It tries to probe partitions on MTD device @mtd using parsers
+ * specified in @types (if @types is %NULL, then the default list of parsers
+ * is used, see 'parse_mtd_partitions()' for more information). If none are
+ * found this functions tries to fallback to information specified in
+ * @parts/@nr_parts.
+ * * If no partitions were found this function just registers the MTD device
+ * @mtd and exits.
+ *
+ * Returns zero in case of success and a negative error code in case of failure.
+ */
+int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
+ struct mtd_part_parser_data *parser_data,
+ const struct mtd_partition *parts,
+ int nr_parts)
+{
+ int ret;
+
+ mtd_set_dev_defaults(mtd);
+
+ if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) {
+ ret = add_mtd_device(mtd);
+ if (ret)
+ return ret;
+ }
+
+ /* Prefer parsed partitions over driver-provided fallback */
+ ret = parse_mtd_partitions(mtd, types, parser_data);
+ if (ret == -EPROBE_DEFER)
+ goto out;
+
+ if (ret > 0)
+ ret = 0;
+ else if (nr_parts)
+ ret = add_mtd_partitions(mtd, parts, nr_parts);
+ else if (!device_is_registered(&mtd->dev))
+ ret = add_mtd_device(mtd);
+ else
+ ret = 0;
+
+ if (ret)
+ goto out;
+
+ /*
+ * FIXME: some drivers unfortunately call this function more than once.
+ * So we have to check if we've already assigned the reboot notifier.
+ *
+ * Generally, we can make multiple calls work for most cases, but it
+ * does cause problems with parse_mtd_partitions() above (e.g.,
+ * cmdlineparts will register partitions more than once).
+ */
+ WARN_ONCE(mtd->_reboot && mtd->reboot_notifier.notifier_call,
+ "MTD already registered\n");
+ if (mtd->_reboot && !mtd->reboot_notifier.notifier_call) {
+ mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
+ register_reboot_notifier(&mtd->reboot_notifier);
+ }
+
+out:
+ if (ret && device_is_registered(&mtd->dev))
+ del_mtd_device(mtd);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_device_parse_register);
+
+/**
+ * mtd_device_unregister - unregister an existing MTD device.
+ *
+ * @master: the MTD device to unregister. This will unregister both the master
+ * and any partitions if registered.
+ */
+int mtd_device_unregister(struct mtd_info *master)
+{
+ int err;
+
+ if (master->_reboot)
+ unregister_reboot_notifier(&master->reboot_notifier);
+
+ err = del_mtd_partitions(master);
+ if (err)
+ return err;
+
+ if (!device_is_registered(&master->dev))
+ return 0;
+
+ return del_mtd_device(master);
+}
+EXPORT_SYMBOL_GPL(mtd_device_unregister);
+
+/**
+ * register_mtd_user - register a 'user' of MTD devices.
+ * @new: pointer to notifier info structure
+ *
+ * Registers a pair of callbacks function to be called upon addition
+ * or removal of MTD devices. Causes the 'add' callback to be immediately
+ * invoked for each MTD device currently present in the system.
+ */
+void register_mtd_user (struct mtd_notifier *new)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ list_add(&new->list, &mtd_notifiers);
+
+ __module_get(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ new->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+}
+EXPORT_SYMBOL_GPL(register_mtd_user);
+
+/**
+ * unregister_mtd_user - unregister a 'user' of MTD devices.
+ * @old: pointer to notifier info structure
+ *
+ * Removes a callback function pair from the list of 'users' to be
+ * notified upon addition or removal of MTD devices. Causes the
+ * 'remove' callback to be immediately invoked for each MTD device
+ * currently present in the system.
+ */
+int unregister_mtd_user (struct mtd_notifier *old)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ module_put(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ old->remove(mtd);
+
+ list_del(&old->list);
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(unregister_mtd_user);
+
+/**
+ * get_mtd_device - obtain a validated handle for an MTD device
+ * @mtd: last known address of the required MTD device
+ * @num: internal device number of the required MTD device
+ *
+ * Given a number and NULL address, return the num'th entry in the device
+ * table, if any. Given an address and num == -1, search the device table
+ * for a device with that address and return if it's still present. Given
+ * both, return the num'th driver only if its address matches. Return
+ * error code if not.
+ */
+struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num)
+{
+ struct mtd_info *ret = NULL, *other;
+ int err = -ENODEV;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (num == -1) {
+ mtd_for_each_device(other) {
+ if (other == mtd) {
+ ret = mtd;
+ break;
+ }
+ }
+ } else if (num >= 0) {
+ ret = idr_find(&mtd_idr, num);
+ if (mtd && mtd != ret)
+ ret = NULL;
+ }
+
+ if (!ret) {
+ ret = ERR_PTR(err);
+ goto out;
+ }
+
+ err = __get_mtd_device(ret);
+ if (err)
+ ret = ERR_PTR(err);
+out:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(get_mtd_device);
+
+
+int __get_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int err;
+
+ if (!try_module_get(master->owner))
+ return -ENODEV;
+
+ if (master->_get_device) {
+ err = master->_get_device(mtd);
+
+ if (err) {
+ module_put(master->owner);
+ return err;
+ }
+ }
+
+ master->usecount++;
+
+ while (mtd->parent) {
+ mtd->usecount++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__get_mtd_device);
+
+/**
+ * get_mtd_device_nm - obtain a validated handle for an MTD device by
+ * device name
+ * @name: MTD device name to open
+ *
+ * This function returns MTD device description structure in case of
+ * success and an error code in case of failure.
+ */
+struct mtd_info *get_mtd_device_nm(const char *name)
+{
+ int err = -ENODEV;
+ struct mtd_info *mtd = NULL, *other;
+
+ mutex_lock(&mtd_table_mutex);
+
+ mtd_for_each_device(other) {
+ if (!strcmp(name, other->name)) {
+ mtd = other;
+ break;
+ }
+ }
+
+ if (!mtd)
+ goto out_unlock;
+
+ err = __get_mtd_device(mtd);
+ if (err)
+ goto out_unlock;
+
+ mutex_unlock(&mtd_table_mutex);
+ return mtd;
+
+out_unlock:
+ mutex_unlock(&mtd_table_mutex);
+ return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(get_mtd_device_nm);
+
+void put_mtd_device(struct mtd_info *mtd)
+{
+ mutex_lock(&mtd_table_mutex);
+ __put_mtd_device(mtd);
+ mutex_unlock(&mtd_table_mutex);
+
+}
+EXPORT_SYMBOL_GPL(put_mtd_device);
+
+void __put_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ while (mtd->parent) {
+ --mtd->usecount;
+ BUG_ON(mtd->usecount < 0);
+ mtd = mtd->parent;
+ }
+
+ master->usecount--;
+
+ if (master->_put_device)
+ master->_put_device(master);
+
+ module_put(master->owner);
+}
+EXPORT_SYMBOL_GPL(__put_mtd_device);
+
+/*
+ * Erase is an synchronous operation. Device drivers are epected to return a
+ * negative error code if the operation failed and update instr->fail_addr
+ * to point the portion that was not properly erased.
+ */
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ u64 mst_ofs = mtd_get_master_ofs(mtd, 0);
+ struct erase_info adjinstr;
+ int ret;
+
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ adjinstr = *instr;
+
+ if (!mtd->erasesize || !master->_erase)
+ return -ENOTSUPP;
+
+ if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!instr->len)
+ return 0;
+
+ ledtrig_mtd_activity();
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ adjinstr.addr = (loff_t)mtd_div_by_eb(instr->addr, mtd) *
+ master->erasesize;
+ adjinstr.len = ((u64)mtd_div_by_eb(instr->addr + instr->len, mtd) *
+ master->erasesize) -
+ adjinstr.addr;
+ }
+
+ adjinstr.addr += mst_ofs;
+
+ ret = master->_erase(master, &adjinstr);
+
+ if (adjinstr.fail_addr != MTD_FAIL_ADDR_UNKNOWN) {
+ instr->fail_addr = adjinstr.fail_addr - mst_ofs;
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ instr->fail_addr = mtd_div_by_eb(instr->fail_addr,
+ master);
+ instr->fail_addr *= mtd->erasesize;
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_erase);
+
+/*
+ * This stuff for eXecute-In-Place. phys is optional and may be set to NULL.
+ */
+int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ void **virt, resource_size_t *phys)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ *virt = NULL;
+ if (phys)
+ *phys = 0;
+ if (!master->_point)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ from = mtd_get_master_ofs(mtd, from);
+ return master->_point(master, from, len, retlen, virt, phys);
+}
+EXPORT_SYMBOL_GPL(mtd_point);
+
+/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
+int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unpoint)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+ return master->_unpoint(master, mtd_get_master_ofs(mtd, from), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unpoint);
+
+/*
+ * Allow NOMMU mmap() to directly map the device (if not NULL)
+ * - return the address to which the offset maps
+ * - return -ENOSYS to indicate refusal to do the mapping
+ */
+unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len,
+ unsigned long offset, unsigned long flags)
+{
+ size_t retlen;
+ void *virt;
+ int ret;
+
+ ret = mtd_point(mtd, offset, len, &retlen, &virt, NULL);
+ if (ret)
+ return ret;
+ if (retlen != len) {
+ mtd_unpoint(mtd, offset, retlen);
+ return -ENOSYS;
+ }
+ return (unsigned long)virt;
+}
+EXPORT_SYMBOL_GPL(mtd_get_unmapped_area);
+
+static void mtd_update_ecc_stats(struct mtd_info *mtd, struct mtd_info *master,
+ const struct mtd_ecc_stats *old_stats)
+{
+ struct mtd_ecc_stats diff;
+
+ if (master == mtd)
+ return;
+
+ diff = master->ecc_stats;
+ diff.failed -= old_stats->failed;
+ diff.corrected -= old_stats->corrected;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.failed += diff.failed;
+ mtd->ecc_stats.corrected += diff.corrected;
+ mtd = mtd->parent;
+ }
+}
+
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = buf,
+ };
+ int ret;
+
+ ret = mtd_read_oob(mtd, from, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_read);
+
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = (u8 *)buf,
+ };
+ int ret;
+
+ ret = mtd_write_oob(mtd, to, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_write);
+
+/*
+ * In blackbox flight recorder like scenarios we want to make successful writes
+ * in interrupt context. panic_write() is only intended to be called when its
+ * known the kernel is about to panic and we need the write to succeed. Since
+ * the kernel is not going to be running for much longer, this function can
+ * break locks and delay to ensure the write succeeds (but not sleep).
+ */
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_panic_write)
+ return -EOPNOTSUPP;
+ if (to < 0 || to >= mtd->size || len > mtd->size - to)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+ if (!len)
+ return 0;
+ if (!master->oops_panic_write)
+ master->oops_panic_write = true;
+
+ return master->_panic_write(master, mtd_get_master_ofs(mtd, to), len,
+ retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_panic_write);
+
+static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs,
+ struct mtd_oob_ops *ops)
+{
+ /*
+ * Some users are setting ->datbuf or ->oobbuf to NULL, but are leaving
+ * ->len or ->ooblen uninitialized. Force ->len and ->ooblen to 0 in
+ * this case.
+ */
+ if (!ops->datbuf)
+ ops->len = 0;
+
+ if (!ops->oobbuf)
+ ops->ooblen = 0;
+
+ if (offs < 0 || offs + ops->len > mtd->size)
+ return -EINVAL;
+
+ if (ops->ooblen) {
+ size_t maxooblen;
+
+ if (ops->ooboffs >= mtd_oobavail(mtd, ops))
+ return -EINVAL;
+
+ maxooblen = ((size_t)(mtd_div_by_ws(mtd->size, mtd) -
+ mtd_div_by_ws(offs, mtd)) *
+ mtd_oobavail(mtd, ops)) - ops->ooboffs;
+ if (ops->ooblen > maxooblen)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtd_read_oob_std(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ from = mtd_get_master_ofs(mtd, from);
+ if (master->_read_oob)
+ ret = master->_read_oob(master, from, ops);
+ else
+ ret = master->_read(master, from, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_write_oob_std(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ to = mtd_get_master_ofs(mtd, to);
+ if (master->_write_oob)
+ ret = master->_write_oob(master, to, ops);
+ else
+ ret = master->_write(master, to, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_io_emulated_slc(struct mtd_info *mtd, loff_t start, bool read,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+ struct mtd_oob_ops adjops = *ops;
+ unsigned int wunit, oobavail;
+ struct mtd_pairing_info info;
+ int max_bitflips = 0;
+ u32 ebofs, pageofs;
+ loff_t base, pos;
+
+ ebofs = mtd_mod_by_eb(start, mtd);
+ base = (loff_t)mtd_div_by_eb(start, mtd) * master->erasesize;
+ info.group = 0;
+ info.pair = mtd_div_by_ws(ebofs, mtd);
+ pageofs = mtd_mod_by_ws(ebofs, mtd);
+ oobavail = mtd_oobavail(mtd, ops);
+
+ while (ops->retlen < ops->len || ops->oobretlen < ops->ooblen) {
+ int ret;
+
+ if (info.pair >= npairs) {
+ info.pair = 0;
+ base += master->erasesize;
+ }
+
+ wunit = mtd_pairing_info_to_wunit(master, &info);
+ pos = mtd_wunit_to_offset(mtd, base, wunit);
+
+ adjops.len = ops->len - ops->retlen;
+ if (adjops.len > mtd->writesize - pageofs)
+ adjops.len = mtd->writesize - pageofs;
+
+ adjops.ooblen = ops->ooblen - ops->oobretlen;
+ if (adjops.ooblen > oobavail - adjops.ooboffs)
+ adjops.ooblen = oobavail - adjops.ooboffs;
+
+ if (read) {
+ ret = mtd_read_oob_std(mtd, pos + pageofs, &adjops);
+ if (ret > 0)
+ max_bitflips = max(max_bitflips, ret);
+ } else {
+ ret = mtd_write_oob_std(mtd, pos + pageofs, &adjops);
+ }
+
+ if (ret < 0)
+ return ret;
+
+ max_bitflips = max(max_bitflips, ret);
+ ops->retlen += adjops.retlen;
+ ops->oobretlen += adjops.oobretlen;
+ adjops.datbuf += adjops.retlen;
+ adjops.oobbuf += adjops.oobretlen;
+ adjops.ooboffs = 0;
+ pageofs = 0;
+ info.pair++;
+ }
+
+ return max_bitflips;
+}
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_ecc_stats old_stats = master->ecc_stats;
+ int ret_code;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ ret_code = mtd_check_oob_ops(mtd, from, ops);
+ if (ret_code)
+ return ret_code;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_read */
+ if (!master->_read_oob && (!master->_read || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ret_code = mtd_io_emulated_slc(mtd, from, true, ops);
+ else
+ ret_code = mtd_read_oob_std(mtd, from, ops);
+
+ mtd_update_ecc_stats(mtd, master, &old_stats);
+
+ /*
+ * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics
+ * similar to mtd->_read(), returning a non-negative integer
+ * representing max bitflips. In other cases, mtd->_read_oob() may
+ * return -EUCLEAN. In all cases, perform similar logic to mtd_read().
+ */
+ if (unlikely(ret_code < 0))
+ return ret_code;
+ if (mtd->ecc_strength == 0)
+ return 0; /* device lacks ecc */
+ //printk("ecc strength = %d.\n",mtd->ecc_strength);
+ //printk("bitflip_threshold = %d.\n",mtd->bitflip_threshold);
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+ return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0;
+}
+EXPORT_SYMBOL_GPL(mtd_read_oob);
+
+int mtd_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ ret = mtd_check_oob_ops(mtd, to, ops);
+ if (ret)
+ return ret;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_write */
+ if (!master->_write_oob && (!master->_write || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ return mtd_io_emulated_slc(mtd, to, false, ops);
+
+ return mtd_write_oob_std(mtd, to, ops);
+}
+EXPORT_SYMBOL_GPL(mtd_write_oob);
+
+/**
+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section
+ * @mtd: MTD device structure
+ * @section: ECC section. Depending on the layout you may have all the ECC
+ * bytes stored in a single contiguous section, or one section
+ * per ECC chunk (and sometime several sections for a single ECC
+ * ECC chunk)
+ * @oobecc: OOB region struct filled with the appropriate ECC position
+ * information
+ *
+ * This function returns ECC section information in the OOB area. If you want
+ * to get all the ECC bytes information, then you should call
+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobecc, 0, sizeof(*oobecc));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->ecc)
+ return -ENOTSUPP;
+
+ return master->ooblayout->ecc(master, section, oobecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
+
+/**
+ * mtd_ooblayout_free - Get the OOB region definition of a specific free
+ * section
+ * @mtd: MTD device structure
+ * @section: Free section you are interested in. Depending on the layout
+ * you may have all the free bytes stored in a single contiguous
+ * section, or one section per ECC chunk plus an extra section
+ * for the remaining bytes (or other funky layout).
+ * @oobfree: OOB region struct filled with the appropriate free position
+ * information
+ *
+ * This function returns free bytes position in the OOB area. If you want
+ * to get all the free bytes information, then you should call
+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobfree, 0, sizeof(*oobfree));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->free)
+ return -ENOTSUPP;
+
+ return master->ooblayout->free(master, section, oobfree);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
+
+/**
+ * mtd_ooblayout_find_region - Find the region attached to a specific byte
+ * @mtd: mtd info structure
+ * @byte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: used to retrieve the ECC position
+ * @iter: iterator function. Should be either mtd_ooblayout_free or
+ * mtd_ooblayout_ecc depending on the region type you're searching for
+ *
+ * This function returns the section id and oobregion information of a
+ * specific byte. For example, say you want to know where the 4th ECC byte is
+ * stored, you'll use:
+ *
+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc);
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte,
+ int *sectionp, struct mtd_oob_region *oobregion,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ int pos = 0, ret, section = 0;
+
+ memset(oobregion, 0, sizeof(*oobregion));
+
+ while (1) {
+ ret = iter(mtd, section, oobregion);
+ if (ret)
+ return ret;
+
+ if (pos + oobregion->length > byte)
+ break;
+
+ pos += oobregion->length;
+ section++;
+ }
+
+ /*
+ * Adjust region info to make it start at the beginning at the
+ * 'start' ECC byte.
+ */
+ oobregion->offset += byte - pos;
+ oobregion->length -= byte - pos;
+ *sectionp = section;
+
+ return 0;
+}
+
+/**
+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific
+ * ECC byte
+ * @mtd: mtd info structure
+ * @eccbyte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: OOB region information
+ *
+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC
+ * byte.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion)
+{
+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion);
+
+/**
+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @buf: destination buffer to store OOB bytes
+ * @oobbuf: OOB buffer
+ * @start: first byte to retrieve
+ * @nbytes: number of bytes to retrieve
+ * @iter: section iterator
+ *
+ * Extract bytes attached to a specific category (ECC or free)
+ * from the OOB buffer and copy them into buf.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf,
+ const u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(buf, oobbuf + oobregion.offset, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @buf: source buffer to get OOB bytes from
+ * @oobbuf: OOB buffer
+ * @start: first OOB byte to set
+ * @nbytes: number of OOB bytes to set
+ * @iter: section iterator
+ *
+ * Fill the OOB buffer with data provided in buf. The category (ECC or free)
+ * is selected by passing the appropriate iterator.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf,
+ u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(oobbuf + oobregion.offset, buf, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category
+ * @mtd: mtd info structure
+ * @iter: category iterator
+ *
+ * Count the number of bytes in a given category.
+ *
+ * Returns a positive value on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section = 0, ret, nbytes = 0;
+
+ while (1) {
+ ret = iter(mtd, section++, &oobregion);
+ if (ret) {
+ if (ret == -ERANGE)
+ ret = nbytes;
+ break;
+ }
+
+ nbytes += oobregion.length;
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes);
+
+/**
+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get ECC bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes);
+
+/**
+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes);
+
+/**
+ * mtd_ooblayout_set_databytes - set data bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: source buffer to get data bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes);
+
+/**
+ * mtd_ooblayout_count_eccbytes - count the number of ECC bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes);
+
+/*
+ * Method to access the protection register area, present in some flash
+ * devices. The user data is one time programmable but the factory data is read
+ * only.
+ */
+int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_fact_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_fact_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info);
+
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_fact_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_fact_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg);
+
+int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_user_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_user_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_user_prot_info);
+
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_user_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg);
+
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ *retlen = 0;
+ if (!master->_write_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ ret = master->_write_user_prot_reg(master, to, len, retlen, buf);
+ if (ret)
+ return ret;
+
+ /*
+ * If no data could be written at all, we are out of memory and
+ * must return -ENOSPC.
+ */
+ return (*retlen) ? 0 : -ENOSPC;
+}
+EXPORT_SYMBOL_GPL(mtd_write_user_prot_reg);
+
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_lock_user_prot_reg(master, from, len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
+
+/* Chip-supported device locking */
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_lock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock);
+
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unlock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_unlock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unlock);
+
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_is_locked)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_is_locked(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_is_locked);
+
+int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isreserved)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isreserved(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isreserved);
+
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isbad)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isbad(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isbad);
+
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ if (!master->_block_markbad)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ ret = master->_block_markbad(master, mtd_get_master_ofs(mtd, ofs));
+ if (ret)
+ return ret;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.badblocks++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_block_markbad);
+
+/*
+ * default_mtd_writev - the default writev method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+static int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ unsigned long i;
+ size_t totlen = 0, thislen;
+ int ret = 0;
+
+ for (i = 0; i < count; i++) {
+ if (!vecs[i].iov_len)
+ continue;
+ ret = mtd_write(mtd, to, vecs[i].iov_len, &thislen,
+ vecs[i].iov_base);
+ totlen += thislen;
+ if (ret || thislen != vecs[i].iov_len)
+ break;
+ to += vecs[i].iov_len;
+ }
+ *retlen = totlen;
+ return ret;
+}
+
+/*
+ * mtd_writev - the vector-based MTD write method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!master->_writev)
+ return default_mtd_writev(mtd, vecs, count, to, retlen);
+
+ return master->_writev(master, vecs, count,
+ mtd_get_master_ofs(mtd, to), retlen);
+}
+EXPORT_SYMBOL_GPL(mtd_writev);
+
+/**
+ * mtd_kmalloc_up_to - allocate a contiguous buffer up to the specified size
+ * @mtd: mtd device description object pointer
+ * @size: a pointer to the ideal or maximum size of the allocation, points
+ * to the actual allocation size on success.
+ *
+ * This routine attempts to allocate a contiguous kernel buffer up to
+ * the specified size, backing off the size of the request exponentially
+ * until the request succeeds or until the allocation size falls below
+ * the system page size. This attempts to make sure it does not adversely
+ * impact system performance, so when allocating more than one page, we
+ * ask the memory allocator to avoid re-trying, swapping, writing back
+ * or performing I/O.
+ *
+ * Note, this function also makes sure that the allocated buffer is aligned to
+ * the MTD device's min. I/O unit, i.e. the "mtd->writesize" value.
+ *
+ * This is called, for example by mtd_{read,write} and jffs2_scan_medium,
+ * to handle smaller (i.e. degraded) buffer allocations under low- or
+ * fragmented-memory situations where such reduced allocations, from a
+ * requested ideal, are allowed.
+ *
+ * Returns a pointer to the allocated buffer on success; otherwise, NULL.
+ */
+void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size)
+{
+ gfp_t flags = __GFP_NOWARN | __GFP_DIRECT_RECLAIM | __GFP_NORETRY;
+ size_t min_alloc = max_t(size_t, mtd->writesize, PAGE_SIZE);
+ void *kbuf;
+
+ *size = min_t(size_t, *size, KMALLOC_MAX_SIZE);
+
+ while (*size > min_alloc) {
+ kbuf = kmalloc(*size, flags);
+ if (kbuf)
+ return kbuf;
+
+ *size >>= 1;
+ *size = ALIGN(*size, mtd->writesize);
+ }
+
+ /*
+ * For the last resort allocation allow 'kmalloc()' to do all sorts of
+ * things (write-back, dropping caches, etc) by using GFP_KERNEL.
+ */
+ return kmalloc(*size, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(mtd_kmalloc_up_to);
+
+#ifdef CONFIG_PROC_FS
+
+/*====================================================================*/
+/* Support for /proc/mtd */
+
+static int mtd_proc_show(struct seq_file *m, void *v)
+{
+ struct mtd_info *mtd;
+
+ seq_puts(m, "dev: size erasesize name\n");
+ mutex_lock(&mtd_table_mutex);
+ mtd_for_each_device(mtd) {
+ seq_printf(m, "mtd%d: %8.8llx %8.8x \"%s\"\n",
+ mtd->index, (unsigned long long)mtd->size,
+ mtd->erasesize, mtd->name);
+ }
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+#endif /* CONFIG_PROC_FS */
+
+/*====================================================================*/
+/* Init code */
+
+static struct backing_dev_info * __init mtd_bdi_init(char *name)
+{
+ struct backing_dev_info *bdi;
+ int ret;
+
+ bdi = bdi_alloc(NUMA_NO_NODE);
+ if (!bdi)
+ return ERR_PTR(-ENOMEM);
+ bdi->ra_pages = 0;
+ bdi->io_pages = 0;
+
+ /*
+ * We put '-0' suffix to the name to get the same name format as we
+ * used to get. Since this is called only once, we get a unique name.
+ */
+ ret = bdi_register(bdi, "%.28s-0", name);
+ if (ret)
+ bdi_put(bdi);
+
+ return ret ? ERR_PTR(ret) : bdi;
+}
+
+static struct proc_dir_entry *proc_mtd;
+
+static int __init init_mtd(void)
+{
+ int ret;
+
+ ret = class_register(&mtd_class);
+ if (ret)
+ goto err_reg;
+
+ mtd_bdi = mtd_bdi_init("mtd");
+ if (IS_ERR(mtd_bdi)) {
+ ret = PTR_ERR(mtd_bdi);
+ goto err_bdi;
+ }
+
+ proc_mtd = proc_create_single("mtd", 0, NULL, mtd_proc_show);
+
+ ret = init_mtdchar();
+ if (ret)
+ goto out_procfs;
+
+ dfs_dir_mtd = debugfs_create_dir("mtd", NULL);
+
+ return 0;
+
+out_procfs:
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ bdi_put(mtd_bdi);
+err_bdi:
+ class_unregister(&mtd_class);
+err_reg:
+ pr_err("Error registering mtd class or bdi: %d\n", ret);
+ return ret;
+}
+
+static void __exit cleanup_mtd(void)
+{
+ debugfs_remove_recursive(dfs_dir_mtd);
+ cleanup_mtdchar();
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ class_unregister(&mtd_class);
+ bdi_put(mtd_bdi);
+ idr_destroy(&mtd_idr);
+}
+
+module_init(init_mtd);
+module_exit(cleanup_mtd);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
+MODULE_DESCRIPTION("Core MTD registration and access routines");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
new file mode 100755
index 0000000..668d9d9
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
@@ -0,0 +1,2063 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/device.h>
+#include "zx29_gmac.h"
+
+#define gmac_printk(_format, _args...) do{printk(KERN_INFO"gmac," _format "\n",##_args);}while(0)
+
+static u8 zx29_gmac_addr[MAC_ADDR_LENTH] = {0xec,0x1d,0x7f,0xb0,0x2f,0x32};
+static struct tasklet_struct *g_gmac_tasklet = NULL;
+/*struct zx29_gmac_dev *g_gmac_dev = NULL; */ /* no use possible */
+extern void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void* puf);
+extern int gmac_event_init(const char *name);
+static void gmac_hw_deinit(struct net_device *dev);
+//extern void v7_dma_map_area(const void *, size_t, int);
+//extern unsigned long virt_to_phys_ap(unsigned long virt);
+extern void dma_map(const void *addr, size_t len, int flags);
+extern unsigned long virt_to_phys_ap_new(unsigned long virt_addr);
+extern void kobj_gmac_del(struct kobject *kobject);
+
+
+void dump_pkt_trace(unsigned char *data,int len)
+{
+ int i;
+ len = len > 128?128:len;
+ printk("********************\n");
+ for(i=0;i<len;i++){
+ printk("%.2x ",data[i]);
+ if((i&0xf) == 0xf)
+ printk("\n");
+ }
+ printk("\n");
+ printk("********************\n");
+}
+
+static u32 zx29_gmac_get_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+
+ return prv->link.isup;
+}
+
+
+static void gmac_start(void* io)
+{
+ volatile unsigned *gmac = (unsigned*)io;
+
+ mac_int_enable();
+ dma_enable();
+ mac_enable();
+}
+
+static inline int mod_sub(int left, int right, int mod)
+{
+ return (mod - right + left) % mod;
+}
+
+static struct bd_tx *get_txed_bd(struct net_device *ndev)
+{
+ struct bd_tx *d;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int n = priv->txed_bd;
+
+ d = (struct bd_tx *)priv->dma_tx_vir;
+
+ if (n == priv->tx_bd_offset)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER)
+ return 0;
+
+ if (d[n].skb == NULL)
+ return 0;
+
+ priv->txed_bd++;
+ priv->txed_bd %= GMAC_TX_BD_NUM;
+
+ return &d[n];
+}
+
+static inline struct bd_tx *get_tx_bd(struct net_device *ndev)
+{
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+ int n = priv->tx_bd_offset;
+ struct bd_tx *d = (struct bd_tx*)priv->dma_tx_vir;
+
+ if (mod_sub(priv->tx_bd_offset, priv->txed_bd, GMAC_TX_BD_NUM) > GMAC_TX_BD_NUM - 2)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER) {
+ return 0;
+ } else {
+ return &d[n];
+ }
+}
+
+static struct bd_rx *get_rx_bd(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+ int n = prv->rx_bd_offset;
+ struct bd_rx *d = (struct bd_rx*)prv->dma_rx_vir;
+
+ if(d[n].RDES0 & DMA_OWNER)
+ {
+ return 0;
+ }
+ else
+ {
+ return &d[n];
+ }
+}
+
+static void gmac_trig_transmit(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 20) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 6:
+ dma_continue_tx();
+ break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 7:
+ default:
+ break;
+
+ }
+}
+
+static void gmac_trig_receive(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 17) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 4:
+ dma_continue_rx();
+ break;
+ default:
+ break;
+ }
+}
+
+static inline void gmac_update_mac(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned char *mac = (unsigned char*)ndev->dev_addr;
+
+ MAC(0x0044) = mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24;
+ MAC(0x0040) = mac[4] | mac[5] << 8;
+}
+
+static int zx29mii_read(struct mii_bus *bus, int phy_addr, int regnum)
+{
+ unsigned long flags;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 0 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irqsave(&prv->lock,flags);
+ while(mac_mii_is_busy());
+ MAC(0x0010) = val;
+ spin_unlock_irqrestore(&prv->lock,flags);
+
+ while(mac_mii_is_busy());
+
+ return (MAC(0x0014) & 0xFFFF);
+}
+
+static int zx29mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
+{
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 1 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irq(&prv->lock);
+ while(mac_mii_is_busy());
+ MAC(0x0014) = value;
+ MAC(0x0010) = val;
+
+ spin_unlock_irq(&prv->lock);
+
+ while(mac_mii_is_busy());
+
+ return 0;
+}
+
+static int zx29mii_reset(struct mii_bus *bus)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)priv->base_addr;
+
+ gmac_start((void *)priv->base_addr);
+ while (mac_mii_is_busy());
+ return 0;
+}
+
+static inline void zx29_gmac_set_macaddr(struct net_device *ndev)
+{
+ int i = 0;
+#if MAC_ADDR_SET
+ for (i = 0; i < MAC_ADDR_LENTH; i++)
+ ndev->dev_addr[i] = zx29_gmac_addr[i];
+
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ random_ether_addr(ndev->dev_addr);
+#else
+ random_ether_addr(ndev->dev_addr);
+#endif
+}
+
+static void zx29_gmac_tx(struct net_device *ndev)
+{
+ register unsigned status;
+ struct net_device_stats s = ndev->stats;
+ struct bd_tx *tx = get_txed_bd(ndev);
+
+
+ while (tx) {
+ status = tx->TDES0;
+
+ if (tx->TDES0 & ERR_TX_ES) {
+ s.tx_errors++;
+ if(status & ERR_TX_LC) s.tx_carrier_errors++;
+ if(status & ERR_TX_NC) s.tx_carrier_errors++;
+ if(status & ERR_TX_EC) s.tx_window_errors++;
+ if(status & ERR_TX_LATECOL) s.tx_window_errors++;
+ if(status & ERR_TX_UF) s.tx_aborted_errors++;
+ if(status & ERR_TX_ED) s.tx_aborted_errors++;
+ if(status & ERR_TX_JT) s.tx_fifo_errors++;
+ if(status & ERR_TX_FF) s.tx_fifo_errors++;
+
+ printk("%s, status=0x%x, err_cnt=%ld\n", __FUNCTION__,status, s.tx_errors);
+ }
+ dev_kfree_skb_any(tx->skb);
+ tx->skb = NULL;
+ tx = get_txed_bd(ndev);
+
+ }
+
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
+}
+
+static int zx29_gmac_rx(struct net_device *ndev)
+{
+ struct bd_rx *rx;
+ struct sk_buff *skb;
+ struct sk_buff *skb_new;
+ unsigned len;
+ int exhausted = 0;
+
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+
+ rx = get_rx_bd(ndev);
+
+ if(unlikely(!rx)) goto rcv_done;
+
+ while (rx) {
+ if ((rx->RDES0 & ERR_RX_ES) || (rx->RDES0 & ERR_RX_LE)) {
+ ndev->stats.rx_errors++;
+ if(rx->RDES0 & ERR_RX_LE) ndev->stats.rx_length_errors++;
+ if(rx->RDES0 & ERR_RX_OE) ndev->stats.rx_over_errors++;
+ if(rx->RDES0 & ERR_RX_IPC) ndev->stats.rx_frame_errors++;
+ if(rx->RDES0 & ERR_RX_LC) ndev->stats.rx_fifo_errors++;
+ if(rx->RDES0 & ERR_RX_CE) ndev->stats.rx_crc_errors++;
+ } else {
+
+ len = ((rx->RDES0 >> 16) & 0x3FFF) - 4;
+ if(len > (ETH_FRAME_LEN+8)) {
+ ndev->stats.rx_dropped++;
+ goto rx_bd_reset;
+ }
+
+ skb_new = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb_new)) {
+ ndev->stats.rx_dropped++;
+ exhausted++;
+ } else {
+ exhausted = 0;
+ ndev->stats.rx_packets++;
+ ndev->stats.rx_bytes += len;
+
+ dma_sync_single_for_cpu(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_FROM_DEVICE);
+ skb = rx->skb;
+ skb_put(skb, len); /*in fact , use for?*/
+
+// dump_pkt_trace(skb->data, len);
+ skb->protocol = eth_type_trans(skb, ndev);
+ netif_rx(skb);
+
+ skb_reserve(skb_new, NET_IP_ALIGN);
+// rx->dma_buf = virt_to_phys_ap((unsigned long)skb_new->data);
+ rx->dma_buf = virt_to_phys_ap_new((unsigned long)skb_new->data);
+ if(rx->dma_buf == NULL)
+ rx->dma_buf = __pa((unsigned)skb_new->data);
+ rx->skb = skb_new;
+ wmb();
+ dma_sync_single_for_device(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+ }
+ }
+rx_bd_reset:
+ rx->RDES0 = rx->RDES0 | DMA_OWNER;
+ priv->rx_bd_offset++;
+ priv->rx_bd_offset %= GMAC_RX_BD_NUM;
+ wmb();
+
+ if (exhausted >= 10)
+ break;
+ gmac_trig_receive((void*)ndev->base_addr);
+ rx = get_rx_bd(ndev);
+ }
+
+rcv_done:
+
+ gmac_trig_receive((void*)ndev->base_addr);
+
+ return (exhausted > 10);
+}
+
+
+#ifndef GMAC_NO_INT
+static irqreturn_t zx29_gmac_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned * gmac = (unsigned *)ndev->base_addr;
+
+ priv->int_event = MAC(0x1014);
+ MAC(0x1014) = priv->int_event;
+
+ mac_int_disable();
+ tasklet_schedule(&priv->tasklet);
+
+ return IRQ_HANDLED;
+}
+
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int events = prv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX)
+ zx29_gmac_rx(ndev);
+
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_TX | INT_ST_RX));
+
+ mac_int_enable();
+}
+
+#else
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned events = priv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX) {
+ if (zx29_gmac_rx(ndev))
+ break;
+ }
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_RX | INT_ST_TX));
+}
+
+enum hrtimer_restart gmac_timer_callback(struct hrtimer *timer)
+{
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+
+ hrtimer_forward_now(timer, gmac_schdule_time);
+ tasklet_schedule(g_gmac_tasklet);
+ return HRTIMER_RESTART;
+}
+#endif
+
+static inline void zx29_gmac_linkisup(struct net_device *dev, int isup)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+
+ priv->link.duplex = phydev->duplex;
+ priv->link.giga = (phydev->speed == 100);
+ if (priv->link.speed != phydev->speed)
+ priv->link.speed = phydev->speed;
+
+
+ priv->link.isup = isup;
+ if (isup)
+ netif_carrier_on(dev);
+ phy_print_status(phydev);
+}
+
+static void zx29_gmac_adjust_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+ volatile unsigned *gmac = (unsigned *)dev->base_addr;
+
+ if (priv->link.isup &&
+ (!phydev->link ||
+ (priv->link.speed != phydev->speed) ||
+ (priv->link.duplex != phydev->duplex))) {
+ priv->link.isup = 0;
+ netif_tx_disable(dev);
+ if (!phydev->link) {
+ netif_carrier_off(dev);
+ phy_print_status(phydev);
+ }
+ }
+
+ if (!priv->link.isup && phydev->link) {
+ if (priv->link.duplex != phydev->duplex) {
+ if (phydev->duplex)
+ mac_set_full_duplex_mode();
+ else
+ mac_set_half_duplex_mode();
+ }
+
+ if (priv->link.giga != (phydev->speed == 100)) {
+ if (phydev->speed == 100)
+ mac_set_speed_100m_mode();
+ else
+ mac_set_speed_10m_mode();
+ }
+ netif_wake_queue(dev);
+ zx29_gmac_linkisup(dev, 1);
+ }
+
+}
+
+static inline int zx29_gmac_phy_start(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *p = NULL;
+ struct mdio_device *mdio_dev = NULL;
+ int ret = 0;
+
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 start
+ int i = 0;
+ for(i = 0;i <= 5;i++)
+ {
+ if (priv->nports == 1) {
+ p = phy_find_first(priv->mii.bus);
+ } else if (priv->rmii_port < PHY_MAX_ADDR) {
+ mdio_dev = priv->mii.bus->mdio_map[priv->rmii_port];
+ p = container_of(mdio_dev, struct phy_device, mdio);
+ }
+
+ if (!p) {
+ if(i == 5){
+ gpio_direction_output(priv->gpio_power[0], 0);
+#ifdef CONFIG_MDIO_C45
+ gpio_direction_output(priv->gpio_power[1], 0);
+#endif
+ }
+ else
+ continue;
+ printk("%s: no PHY found\n", dev->name);
+ return -ENODEV;
+ }
+ else
+ break;
+ }
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 end
+
+ ret = phy_connect_direct(dev, p, zx29_gmac_adjust_link, PHY_INTERFACE_MODE_RMII); /* phy_start_machine */
+ /* supported and advertising */
+ priv->phydev = p;
+ return 0;
+}
+
+
+static int gmac_init_rx_bd(struct net_device *ndev, struct zx29_gmac_dev *priv)
+{
+ struct sk_buff *skb = NULL;
+ struct bd_rx *rx = (struct bd_rx *)priv->dma_rx_vir;
+ int i = 0;
+
+ priv->rx_bd_offset = 0;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ skb = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb)) {
+ gmac_hw_deinit(ndev);
+ return -1;
+ }
+
+ skb_reserve(skb, NET_IP_ALIGN);
+
+ rx[i].RDES0 |= DMA_OWNER; /* when to change? */
+ rx[i].RDES1 = 0;
+ rx[i].RDES1 = GMAC_FRAME_LEN | 1 << 14;
+ rx[i].dma_buf = __pa((unsigned)skb->data); /* __pa ? */
+ rx[i].next = priv->dma_rx_phy + ((i + 1) << 5); /* why phy? */
+ rx[i].skb = skb;
+#if 0
+ if(i%4 != 0)
+ {
+ rx[i].RDES1 |= 0x80000000;
+ }
+#endif
+ dma_sync_single_for_device(&ndev->dev, rx[i].dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+
+ }
+ rx[GMAC_RX_BD_NUM - 1].next = priv->dma_rx_phy;
+ rx[GMAC_RX_BD_NUM - 1].RDES1 = GMAC_FRAME_LEN | 1 << 14 | 1 << 15;
+
+ return 0;
+}
+
+static void gmac_init_tx_bd(struct zx29_gmac_dev *priv)
+{
+ struct bd_tx *tx = (struct bd_tx *)priv->dma_tx_vir;
+ int i = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ tx[i].TDES0 = (1 << 20 | 1 << 30);
+ tx[i].TDES1 = GMAC_FRAME_LEN;
+ tx[i].next = priv->dma_tx_phy + ((i + 1) << 5);
+ }
+
+ tx[GMAC_TX_BD_NUM - 1].next = priv->dma_tx_phy;
+ tx[GMAC_TX_BD_NUM - 1].TDES0 = 1 << 20 | 1 << 21 | 1 << 30;
+
+}
+
+static void gmac_stop(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ dma_clear_tx_fifo();
+ dma_wait_tx_fifo_cleared();
+}
+
+static void gmac_set_speed_duplex(struct net_device *ndev, int speed, int duplex)
+{
+ unsigned val;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+
+ val = MAC(0x0000) | 1 << 11 | 1 << 14;
+ if (SPEED_10 == speed)
+ val &= ~(1 << 14);
+ if (DUPLEX_HALF == duplex) {
+ val &= (~(1 << 11));
+ val |= (1 << 16);
+ }
+ MAC(0x0000) = val;
+}
+
+static void mac_init(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int i = 0, j = 0, mac_rst = 0;
+ unsigned long long mac_time_start = 0;
+ unsigned long long mac_time_end = 0;
+
+ mac_provide_clock();
+#ifdef __DEAD_LOOP_POLL__
+ mac_reset();
+ mac_set_gmii_mode();
+ mac_wait_reset_finished();
+#else
+ mac_time_start = local_clock();
+ for (i = 0; i < MAC_RESET_NUM; i++) {
+ mac_reset();
+ mac_set_mii_mode();
+ for (j = 0; j < MAC_WAIT_TIME; j++) {
+// printk(".");
+ if (!((MAC(0x1000)) & 1)) {
+ mac_time_end = local_clock();
+ printk("ok:time:%llu ns\n", mac_time_end - mac_time_start);
+ mac_rst = 1;
+ goto mac_reset_option;
+ }
+ udelay(100);
+ }
+ }
+ mac_time_end = local_clock();
+mac_reset_option:
+ if(!mac_rst)
+ printk("gmac reset failed!time:%llu us\n", mac_time_end - mac_time_start);
+#endif
+ while(mac_mii_is_busy());
+}
+
+static void gmac_hw_deinit(struct net_device *ndev)
+{
+ int i;
+ struct bd_rx *rx_bd;
+ struct bd_tx *tx_bd;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ gmac_stop((void *)ndev->base_addr);
+
+ if (priv->dma_rx_phy) {
+ rx_bd = (struct bd_rx *)priv->dma_rx_vir;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ if (rx_bd[i].skb)
+ dev_kfree_skb_any(rx_bd[i].skb);
+ }
+
+ tx_bd = (struct bd_tx *)priv->dma_tx_vir;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ if (tx_bd[i].skb)
+ dev_kfree_skb_any(tx_bd[i].skb);
+ }
+ }
+
+ dma_set_tx_buffer(0); //设置首个BD的缓冲区为0；
+ dma_set_rx_buffer(0);
+
+ priv->rx_bd_offset = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+ priv->dma_rx_phy = 0;
+ priv->dma_rx_vir = 0;
+ priv->dma_tx_phy = 0;
+ priv->dma_tx_vir = 0;
+
+}
+
+static int gmac_hw_init(struct net_device *ndev)
+{
+ int ret = -1;
+ unsigned val;
+
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (priv->dma_rx_phy)
+ gmac_hw_deinit(ndev);
+
+ priv->dma_rx_vir = priv->dma_rx_vir_init;
+ priv->dma_rx_phy = priv->dma_rx_phy_init;
+ priv->dma_tx_vir = priv->dma_rx_vir + GMAC_RX_BUF_LEN;
+ priv->dma_tx_phy = priv->dma_rx_phy + GMAC_RX_BUF_LEN; /* ifconfig up, clear fifo*/
+
+ memset(priv->dma_rx_vir, 0, GMAC_BUF_LEN);
+
+ ret = gmac_init_rx_bd(ndev, priv);
+ if (ret < 0) {
+ printk("hw_net_init,init_rx_bd fail\n");
+ return ret;
+ }
+ gmac_init_tx_bd(priv);
+
+ mac_init(ndev);
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ val = MAC(0x1000);
+ val &= ~(0x3F << 8);
+ val |= (0x10 << 8);
+ MAC(0x1000) = val;
+
+ dma_set_rx_buffer(priv->dma_rx_phy);
+ dma_set_tx_buffer(priv->dma_tx_phy);
+
+ mac_int_clear(0x0001FFFF);
+ while (mac_mii_is_busy());
+
+ gmac_set_speed_duplex(ndev, priv->phydev->speed, priv->phydev->duplex);
+
+ mac_rece_all_data();
+
+ gmac_start((void *)ndev->base_addr);
+ return 0;
+}
+
+static int zx29_gmac_open(struct net_device *ndev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ unsigned long flags;
+ int ret;
+ int err = 0;
+#ifdef GMAC_NO_INT
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time;
+#endif
+ err = phy_read_status(priv->phydev); /*interal, phy drv provide*/
+ if (err < 0)
+ return err;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->link.speed = 0;
+
+ zx29_gmac_linkisup(ndev, priv->phydev->link);
+
+ ret = gmac_hw_init(ndev);
+ if(ret) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+
+ netif_carrier_on(ndev);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ phy_start(priv->phydev);
+
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+ if (priv->timer)
+ hrtimer_start(priv->timer, gmac_schdule_time, HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+
+ printk("TSP zx29 gmac net open\n");
+
+ return 0;
+}
+
+static int zx29_gmac_stop(struct net_device *ndev)
+{
+ unsigned long flags = 0;
+ int ret = 0;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (!priv->stopped) {
+ spin_lock_irqsave(&priv->lock, flags);
+#ifdef GMAC_NO_INT
+ ret = hrtimer_cancel(priv->timer);
+ if (ret < 0) {
+ BUG_ON(1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+#endif
+
+ priv->stopped = 1;
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ phy_stop(priv->phydev);
+ gmac_hw_deinit(ndev);
+
+ memset(&ndev->stats, 0, sizeof(struct net_device_stats));
+ spin_unlock_irqrestore(&priv->lock, flags);
+ printk("TSP zx29 gmac net stop\n");
+ }
+ return 0;
+}
+
+
+static netdev_tx_t zx29_gmac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ unsigned long flags;
+ unsigned len;
+ struct sk_buff *skb_old;
+ struct bd_tx *tx;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (0 == priv->link.isup) {
+ dev_kfree_skb_any(skb);
+ printk("TSP zx29 gmac xmit phy not link\n");
+ return NETDEV_TX_OK; /* ? */
+ }
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if(priv->stopped)
+ {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+
+ printk("zx_net_start_xmit when stopped\n");
+
+ return NETDEV_TX_OK;
+ }
+
+ tx = get_tx_bd(ndev);
+
+ if (!tx) {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ priv->tx_bd_offset++;
+ priv->tx_bd_offset %= GMAC_TX_BD_NUM;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ if(skb->len > ETH_FRAME_LEN + 4) /* why 4*/
+ printk("TSP zx29 gmac start xmit len too long\n");
+
+// v7_dma_map_area(skb->data, skb->len, DMA_TO_DEVICE);
+ dma_map(skb->data, skb->len, DMA_TO_DEVICE);
+ if (NULL == skb)
+ BUG_ON(1);
+
+ len = MIN(skb->len, GMAC_FRAME_LEN - NET_IP_ALIGN);
+
+ tx->TDES0 |= (0x07 << 28);
+// tx->dma_buf = virt_to_phys_ap((unsigned long)skb->data);
+ tx->dma_buf = virt_to_phys_ap_new((unsigned long)skb->data);
+
+ if(tx->dma_buf == NULL)
+ tx->dma_buf = virt_to_phys((unsigned)skb->data);
+ tx->skb = skb;
+
+ tx->TDES1 = len;
+ tx->TDES0 |= DMA_OWNER;
+
+ wmb();
+ ndev->stats.tx_bytes += len;
+ ndev->stats.tx_packets++;
+/* ndev->trans_start = jiffies; */
+
+
+ gmac_trig_transmit((void*)ndev->base_addr);
+// dump_pkt_trace(skb->data, len);
+// printk("[%s]\n", __func__);
+
+ return NETDEV_TX_OK;
+}
+
+static void zx29_gmac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ genphy_update_link(priv->phydev);
+#endif
+ priv->link.isup = priv->phydev->link;
+
+ if (0 == priv->link.isup) {
+ printk("TSP zx29 gmac net timeout phy not link\n"); // PHY 未连接
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ } else {
+ printk("TSP zx29 gmac net timeout phy linked\n");
+ gmac_trig_transmit(ndev);
+ gmac_trig_receive(ndev);
+
+ netif_carrier_on(ndev);
+ netif_wake_queue(ndev);
+/* ndev->trans_start = jiffies; */ /* modify */
+ ndev->stats.tx_errors++;
+ ndev->stats.tx_dropped++;
+ }
+}
+
+void __iomem *base_clk = NULL;
+void __iomem *base_phy_release = NULL;
+
+static int zx29_gmac_phy_disable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+
+ enum of_gpio_flags flags;
+ unsigned long flag;
+ int gpio = 0;
+ int ret = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if (ndev && !priv->stopped) {
+ if (netif_running(ndev)) {
+
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+ printk("[%s] netif_running\n", __func__);
+
+ gpio_direction_output(priv->gpio_power[0], 0);
+
+ gmac_stop((void*)ndev->base_addr);
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+// netif_device_detach(ndev);
+ }
+ pm_relax(&pdev->dev);
+ // printk("[%s] sleep\n");
+ }
+#endif
+ //printk("[%s] exit\n", __func__);
+ return 0;
+}
+
+static int zx29_gmac_phy_enable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ int ret = 0;
+ int status = 0;
+ int islink = 0;
+ unsigned int num= 0;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if(ndev && priv->stopped) {
+ pm_stay_awake(&pdev->dev);
+ if( netif_running(ndev)) {
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+// netif_device_attach(ndev);
+ }
+ }
+#endif
+ return 0;
+}
+
+#define C45_READ 1
+#define C45_WRITE 0
+static int zx29_c22_2_c45(struct phy_device *phydev, int addr, u16 devad, u32 regnum, int rw, int write_val)
+{
+ int val = 0;
+ phy_lock_mdio_bus(phydev);
+ /* Write the desired MMD Devad */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL, devad);
+ /* Write the desired MMD register address */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, regnum);
+ /* Select the Function : DATA with no post increment */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL,
+ devad | MII_MMD_CTRL_NOINCR);
+ /* Read the content of the MMD's selected register */
+ if (rw == C45_READ)
+ val = __mdiobus_read(phydev->mdio.bus, addr, MII_MMD_DATA);
+ else
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, write_val);
+ phy_unlock_mdio_bus(phydev);
+
+ return val;
+}
+
+static int zx29_c45_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
+{
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ u16 val = mii_data->val_in;
+ bool change_autoneg = false;
+ int prtad, devad, reg_num;
+
+ switch (cmd) {
+ case SIOCGMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);//phy id
+ devad = mdio_phy_id_devad(mii_data->phy_id);//dev id / mmd
+ reg_num = mii_data->reg_num;
+ mii_data->val_out = zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_READ, 0);
+ return 0;
+
+ case SIOCSMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);
+ devad = mdio_phy_id_devad(mii_data->phy_id);
+ reg_num = mii_data->reg_num;
+
+ if (prtad == phydev->mdio.addr) {
+ switch (devad) {
+ case MII_BMCR:
+ if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) {
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_DISABLE;
+ if (val & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ if (val & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (val & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else phydev->speed = SPEED_10;
+ }
+ else {
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_ENABLE;
+ }
+ break;
+ case MII_ADVERTISE:
+ mii_adv_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ case MII_CTRL1000:
+ mii_ctrl1000_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+
+ zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_WRITE, val);
+
+ if (prtad == phydev->mdio.addr &&
+ devad == MII_BMCR &&
+ val & BMCR_RESET)
+ return phy_init_hw(phydev);
+
+ if (change_autoneg)
+ return phy_start_aneg(phydev);
+
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int zx29_gmac_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ int is_c45 = mdio_phy_id_is_c45(mii_data->phy_id);
+
+ if (!(netif_running(ndev)))
+ return -EINVAL;
+ if (!priv->phydev)
+ return -EINVAL;
+ if (cmd == SIOCDISABLEPHY)
+ return zx29_gmac_phy_disable(ndev->dev.parent);
+
+ if (cmd == SIOCENABLEPHY)
+ return zx29_gmac_phy_enable(ndev->dev.parent);
+
+ if (is_c45)
+ return zx29_c45_mii_ioctl(priv->phydev, ifr, cmd);
+
+ return phy_mii_ioctl(priv->phydev, ifr, cmd);
+}
+
+static int eth_change_mtu(struct net_device *ndev, int new_mtu)
+{
+ if (new_mtu < 68 || new_mtu > ETH_DATA_LEN)
+ return -EINVAL;
+ ndev->mtu = new_mtu;
+ return 0;
+}
+
+static int zx29_gmac_set_mac_address(struct net_device *ndev, void *p)
+{
+ int ret = eth_mac_addr(ndev, p);
+ if (!ret) {
+ gmac_update_mac(ndev);
+ printk(" zx29 gmac set mac addr ok\n");
+ }
+ return ret;
+}
+
+
+static int zx29_gmac_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ unsigned long flag;
+
+ if(ndev) {
+ if(netif_running(ndev)) {
+// netif_device_detach(ndev);
+// gmac_stop((void*)ndev->base_addr);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ phy_stop(priv->phydev);
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+
+ printk("[%s] netif_running\n", __func__);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gmac_stop((void*)ndev->base_addr);
+#else
+ gmac_stop((void*)ndev->base_addr);
+ gpio_direction_output(priv->gpio_power[0], 0);
+#endif
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+#endif
+ }
+ }
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_sleep_state(&pdev->dev);
+#endif
+ return 0;
+}
+
+static int zx29_gmac_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_default_state(&pdev->dev);
+#endif
+ if(ndev) {
+ if(netif_running(ndev)) {
+// gmac_start((void*)ndev->base_addr);
+// netif_device_attach(ndev);
+// zx29_gmac_phy_enable(dev);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+
+ phy_start(priv->phydev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+#endif
+
+ }
+ }
+ return 0;
+}
+
+static const struct ethtool_ops zx29_gmac_ethtool_ops = {
+ .get_link = zx29_gmac_get_link,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ /* other func */
+};
+
+static const struct net_device_ops zx29_gmac_netdev_ops = {
+ .ndo_open = zx29_gmac_open,
+ .ndo_stop = zx29_gmac_stop,
+ .ndo_start_xmit = zx29_gmac_start_xmit,
+ .ndo_tx_timeout = zx29_gmac_tx_timeout,
+ .ndo_do_ioctl = zx29_gmac_ioctl,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = zx29_gmac_set_mac_address,
+};
+
+
+
+ssize_t show_fun(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ int status = 0;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ printk("MAC(1000) :0x%x\n", MAC(0x1000));
+ printk("MAC(1004) :0x%x\n", MAC(0x1004));
+ printk("MAC(1008) :0x%x\n", MAC(0x1008));
+ printk("MAC(100c) :0x%x\n", MAC(0x100c));
+ printk("MAC(1010) :0x%x\n", MAC(0x1010));
+ printk("MAC(1014) int status:0x%x\n", MAC(0x1014));
+ printk("MAC(1018) :0x%x\n", MAC(0x1018));
+ printk("MAC(101c) :0x%x\n", MAC(0x101c));
+ printk("MAC(0000) :0x%x\n", MAC(0x0000));
+ printk("MAC(0004) :0x%x\n", MAC(0x0004));
+ printk("MAC(0010) :0x%x\n", MAC(0x0010));
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 1);
+ printk("phy status:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 0, 1);
+ printk("phy status port0:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 1, 1);
+ printk("phy status port1:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 2, 1);
+ printk("phy status port2:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 3, 1);
+ printk("phy status port3:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 4, 1);
+ printk("phy status port4:0x%x\n", status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 20);
+ status |= 0x4;
+ mdiobus_write(priv->phydev->mdio.bus, 21, 20, status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 21);
+ printk("phy status loop port:0x%x\n", status);
+
+
+ return 0;
+}
+
+ssize_t store_fun(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ printk("[%s]", __func__);
+ return 1;
+}
+
+
+ssize_t mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x", &rd_wt, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ return count;
+}
+
+
+ssize_t free_mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t free_mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ int phy_addr = 8;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x,%x", &rd_wt, &phy_addr, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, phy_addr, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,phy_addr,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ return count;
+}
+
+extern int debug_on;
+ssize_t debug_on_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if (ret < 1) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input %d\n",
+ ret,val);
+ return count;
+ }
+ debug_on = val;
+ return count;
+}
+
+ssize_t debug_on_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (debug_on)
+ memcpy(buf, "on", 3);
+ else
+ memcpy(buf, "off", 4);
+ return 0;
+}
+
+/*jb.qi add for gamc power down on 20231116 start*/
+
+extern int gmac_power = 1;
+int gmac_power_flag = 0;
+
+ssize_t gmac_power_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if(ret < 1)
+ {
+ printk(KERN_INFO "gmac: failed ti read user buf, ret=%d, input %d\n", ret,val);
+ return count;
+ }
+ gmac_power = val;
+ gpio_direction_output(gmac_power_flag, val);
+ return count;
+}
+
+ssize_t gmac_power_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ if(gmac_power)
+ memcpy(buf, "on",3);
+ else
+ memcpy(buf, "off", 4);
+
+ printk("gmac_power %s\n", buf);
+ return 0;
+
+}
+/*jb.qi add for gamc power down on 20231116 end */
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 start*/
+static int mode_type = -1;
+static int enter_only_one = 0;
+
+ssize_t gmac_master_or_slave_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///read mode_type
+ ret = sscanf(buf, "%d", &mode_type);
+ if (ret < 1) {
+ printk(KERN_ERR "Please enter the number 0-3 to enable the corresponding mode \n"
+ "Enter values in the non-0-3 range to get pattern description \n");
+ return count;
+ }
+
+ ///Judgment model
+ if (mode_type < 0 || mode_type > 3) {
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ return ret ? ret : count;
+ }
+
+ ///Set the Ethernet slave mode
+ if (mode_type == 0) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val & (~BIT(14)));
+ }
+ ///Set the Ethernet master mode
+ else if (mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val | BIT(14));
+ }
+ return count;
+}
+
+ssize_t gmac_master_or_slave_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int len = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///Reentrant prevention
+ if(enter_only_one == 1)
+ {
+ return 0;
+ }
+ enter_only_one = 1;
+
+ ///Read the network master/slave
+ if (mode_type == 0 || mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e) & BIT(14);
+ if(val)
+ memcpy(buf, "Master\n",7);
+ else
+ memcpy(buf, "Slave\n", 6);
+
+ printk(KERN_DEBUG "mode_type %d - gmac_master_or_slave is %s\n", mode_type, buf);
+
+ }
+ ///Obtain the cable quality SQI value
+ else if(mode_type == 2){
+ mmd = 0x1;
+ reg = 0x8B10;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "0x%x\n", val);
+ sprintf(buf, "SQI : 0x%x\n", val);
+ printk(KERN_DEBUG "mode_type %d - SQI is 0x%x", mode_type, val);
+
+ }
+ ///Obtain short circuit, open circuit and normal connection of VCT
+ else if(mode_type == 3){
+ ///--TDR Enable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, BIT(14) | BIT(12));
+ msleep(10);
+ ///--Read VCT
+ mmd = 0x1;
+ reg = 0x8B02;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ printk(KERN_DEBUG "Open status: %s - Short status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ sprintf(buf, "Open status: %s\nShort status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ reg = 0x8B01;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "%sDistance status: 0x%x\n", buf, val);
+ printk(KERN_DEBUG "mode_type %d - Distance status is 0x%x\n", mode_type, val);
+
+ ///--TDR Disable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, 0);
+
+ }
+ ///Get model help information
+ else{
+ sprintf(buf, "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ }
+ enter_only_one = 0;
+ return strlen(buf);
+
+}
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 end */
+
+static DEVICE_ATTR(gmac_test, 0664, show_fun, store_fun);
+static DEVICE_ATTR(mdio_test, 0664, mdio_show, mdio_store);
+static DEVICE_ATTR(free_mdio, 0664, free_mdio_show, free_mdio_store);
+static DEVICE_ATTR(debug_on, 0664, debug_on_show, debug_on_store);
+static DEVICE_ATTR(gmac_power, 0664, gmac_power_show, gmac_power_store);//jb.qi add for gamc power down on 20231116
+static DEVICE_ATTR(gmac_master_or_slave, 0664, gmac_master_or_slave_show, gmac_master_or_slave_store);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+
+static int zx29_gmac_probe(struct platform_device *pdev)
+{
+ struct zx29_gmac_dev *prv = NULL;
+ struct net_device *ndev = alloc_etherdev(sizeof(struct zx29_gmac_dev));
+ volatile unsigned int *gmac = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ int ret = -1;
+ unsigned long i;
+ struct mii_bus *mb;
+ struct resource *iomem;
+ void __iomem *base = NULL;
+ struct pinctrl *pctrl;
+ struct pinctrl_state *state0;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ char board_name[128] = {"init_failed"};
+
+ printk("[%s] #########zx29_gmac_probe begin.\n", __func__);
+ if (!ndev)
+ return -ENOMEM;
+
+ device_create_file(&pdev->dev, &dev_attr_gmac_test);
+ device_create_file(&pdev->dev, &dev_attr_mdio_test);
+ device_create_file(&pdev->dev, &dev_attr_free_mdio);
+ device_create_file(&pdev->dev, &dev_attr_debug_on);
+ device_create_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_create_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+
+ prv = netdev_priv(ndev);
+ memset(prv, 0, sizeof(*prv));
+ prv->stopped = 1;
+
+ pctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(pctrl)) {
+ dev_warn(&pdev->dev, "Failed to get test pins");
+ pctrl = NULL;
+ goto errirq;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ state0 = pinctrl_lookup_state(pctrl, "state0");
+#else
+ state0 = pinctrl_lookup_state(pctrl, "default");
+#endif
+ if (IS_ERR(state0)) {
+ dev_err(&pdev->dev, "TEST: missing state0\n");
+ goto pinctrl_init_end;
+ }
+
+ if (pinctrl_select_state(pctrl, state0) < 0) {
+ dev_err(&pdev->dev, "setting state0 failed\n");
+ goto pinctrl_init_end;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ prv->gpio_power[2] = of_get_gpio_flags(pdev->dev.of_node, 2, &flags);
+ ret = gpio_request(prv->gpio_power[2], "phy_power"); /* gpio 51 */
+ gpio_direction_output(prv->gpio_power[2], 1);
+ mdelay(15);
+#endif
+
+ prv->gpio_power[0] = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
+ ret = gpio_request(prv->gpio_power[0], "gmac_power"); /* gpio 83/124 */
+ gpio_direction_output(prv->gpio_power[0], 1);
+ mdelay(15);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ prv->gpio_power[1] = of_get_gpio_flags(pdev->dev.of_node, 1, &flags);
+ ret = gpio_request(prv->gpio_power[1], "phy_rst"); /* gpio 63 */
+ gpio_direction_output(prv->gpio_power[1], 0);
+ mdelay(10);
+ gpio_direction_output(prv->gpio_power[1], 1);
+ mdelay(15);
+#endif
+
+ SET_NETDEV_DEV(ndev, &pdev->dev); //if not, will panic
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ gmac_power_flag = prv->gpio_power[0];//jb.qi add for gamc power down on 20231116
+ ndev->base_addr = base;/*iomem->start;*/
+ if (!ndev->base_addr)
+ return -ENXIO;
+
+#ifndef GMAC_NO_INT
+ ndev->irq = platform_get_irq(pdev, 0);
+#endif
+ ndev->netdev_ops = &zx29_gmac_netdev_ops;
+ ndev->ethtool_ops = &zx29_gmac_ethtool_ops;
+
+ gmac = (unsigned *)ndev->base_addr;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ spin_lock_init(&prv->lock);
+
+
+/* wake_lock_init(&prv->wake_lock, WAKE_LOCK_SUSPEND, "gmac_pm"); //what replace?
+ wake_lock(&prv->wake_lock); */
+ device_init_wakeup(&pdev->dev, true);
+
+
+ zx29_gmac_set_macaddr(ndev);
+
+#ifndef GMAC_NO_INT
+ ret = request_irq(ndev->irq, zx29_gmac_interrupt, 0, ndev->name, ndev);
+ if (ret) {
+ printk(KERN_ERR "irq request failed: %d\n", ndev->irq);
+ goto errirq;
+ }
+#endif
+
+ ret = register_netdev(ndev);
+ if (ret) {
+ printk(KERN_ERR "error registering device %s\n",
+ ndev->name);
+ goto errdev;
+ }
+
+ of_property_read_u32(np, "port-nums", &prv->nports);
+ of_property_read_u32(np, "rmii-ports", &prv->rmii_port);
+ prv->base_addr = ndev->base_addr;
+
+ prv->netdev = ndev;
+
+ mb = mdiobus_alloc();
+ if (!mb) {
+ printk(KERN_ERR "error allocating mii bus\n");
+ goto errmii;
+ }
+ mb->name = "zx29_gmac_mii";
+ mb->read = zx29mii_read;
+ mb->write = zx29mii_write;
+ mb->reset = zx29mii_reset;
+ mb->priv = prv;
+ snprintf(mb->id, MII_BUS_ID_SIZE, "%s-%x", "zx29_gmac", 0);
+ of_property_read_u32(np, "port-mask", &mb->phy_mask);
+/* mb->irq = &prv->mii.irq[0]; */
+ for (i = 0; i < PHY_MAX_ADDR; i++) {
+ int n = platform_get_irq(pdev, i + 1); /* devtrrr modify */
+ if (n < 0)
+ n = PHY_POLL;
+ prv->mii.irq[i] = n;
+ mb->irq[i] = n;
+ }
+
+ base = devm_platform_ioremap_resource(pdev, 2);
+ gmac_set_clk();
+ base_clk = base;
+
+ base = devm_platform_ioremap_resource(pdev, 1);
+ gmac_phy_release();
+ base_phy_release = base;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ mdelay(500);
+#else
+ mdelay(10); //zw.wang@20240306 modify. Here, the jl3103 is set as an example, and other phy peripherals need to be optimized according to different reset stability times
+#endif
+
+ ret = mdiobus_register(mb);
+ if (ret < 0) {
+ printk("[%s] mdiobus register failed!\n", __func__);
+ goto errmdioregister;
+ }
+
+ prv->mii.bus = mb;
+ ret = zx29_gmac_phy_start(ndev);
+ if (ret)
+ goto errphystart;
+
+ if (!(prv->phydev->phy_id == 0x00000000 || prv->phydev->phy_id == 0xffffffff)) {
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ pm_stay_awake(&pdev->dev);
+#endif
+ strcpy(board_name, "cpe");
+
+ printk("[%s] phy id = 0x%x \n", __func__, prv->phydev->phy_id);
+ printk("set gmac wakelock!\n");
+ } else {
+ strcpy(board_name, "mdl");
+ netif_device_detach(ndev);
+ }
+
+ platform_set_drvdata(pdev, ndev);
+
+ tasklet_init(&prv->tasklet, zx29_gmac_tasklet, (unsigned long)ndev);
+ g_gmac_tasklet = &prv->tasklet;
+
+
+ prv->dma_rx_vir = dma_alloc_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_phy, GFP_KERNEL);
+ if (!prv->dma_rx_vir) { // null, ndev->dev.parent difference?
+ BUG_ON(1);
+ goto errphystart;
+ }
+
+ prv->dma_rx_phy_init = prv->dma_rx_phy;
+ prv->dma_rx_vir_init = prv->dma_rx_vir;
+ prv->dma_tx_phy = prv->dma_rx_phy + GMAC_RX_BUF_LEN;
+ prv->dma_tx_vir = prv->dma_rx_vir + GMAC_RX_BUF_LEN;
+
+#ifdef GMAC_NO_INT
+ sema_init(&prv->sem, 0);
+
+ prv->timer = kzalloc(sizeof(struct hrtimer), GFP_KERNEL);
+ if (!prv->timer) {
+ BUG_ON(1);
+ goto errmalloc;
+ }
+ hrtimer_init(prv->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+
+ prv->timer->function = gmac_timer_callback;
+#endif
+
+ gmac_event_init(board_name);
+/* g_gmac_dev = prv; */ /* no use possible*/
+
+ printk("[%s] probe end\n", __func__);
+ return 0;
+errmalloc:
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_vir, prv->dma_rx_phy);
+
+
+errphystart:
+ mdiobus_unregister(mb);
+
+
+errmdioregister:
+ mdiobus_free(mb);
+
+errmii:
+ unregister_netdev(ndev);
+
+errdev:
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+
+pinctrl_init_end:
+
+errirq:
+ free_netdev(ndev);
+
+ printk("#########zx29_gmac_probe fail.\n");
+ return ret;
+}
+
+static int zx29_gmac_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ volatile unsigned *gmac = NULL;
+ if (ndev) {
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+
+// gpio_direction_output(priv->gpio_power[0], 1);
+// msleep(500);
+ unregister_netdev(ndev);
+
+ phy_disconnect(priv->phydev);
+
+ kobj_gmac_del(NULL);
+
+ mdiobus_unregister(priv->mii.bus);
+ mdiobus_free(priv->mii.bus);
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+ tasklet_disable(&priv->tasklet);
+ tasklet_kill(&priv->tasklet);
+
+ if (priv->dma_rx_vir)
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, priv->dma_rx_vir, priv->dma_rx_phy);
+
+ pm_relax(&pdev->dev);
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ gpio_free(priv->gpio_power[1]);
+#endif
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gpio_free(priv->gpio_power[0]);
+
+ device_remove_file(&pdev->dev, &dev_attr_gmac_test);
+ device_remove_file(&pdev->dev, &dev_attr_mdio_test);
+ device_remove_file(&pdev->dev, &dev_attr_free_mdio);
+ device_remove_file(&pdev->dev, &dev_attr_debug_on);
+ device_remove_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_remove_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+ }
+ return 0;
+}
+
+static struct dev_pm_ops zx29_gmac_pm_ops = {
+ .suspend = zx29_gmac_suspend,
+ .resume = zx29_gmac_resume,
+};
+
+static const struct of_device_id gmac_match_table[] = {
+ {.compatible = "zte, zx29_gmac",},
+};
+
+static struct platform_driver zx29_gmac_driver = {
+ .probe = zx29_gmac_probe,
+ .remove = zx29_gmac_remove,
+ .driver = {
+ .name = "zx29_gmac",
+ .owner = THIS_MODULE,
+ .pm = &zx29_gmac_pm_ops,
+ .of_match_table = gmac_match_table,
+ },
+};
+
+static int __init zx29_gmac_init(void)
+{
+ return platform_driver_register(&zx29_gmac_driver);
+}
+
+static void __exit zx29_gmac_exit(void)
+{
+ printk("[%s] start exit!\n", __func__);
+ platform_driver_unregister(&zx29_gmac_driver);
+}
+
+module_init(zx29_gmac_init);
+module_exit(zx29_gmac_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ZX29 on chip Ethernet driver");
+MODULE_AUTHOR("zhu jianlinag <zhu.jianliang@zte.com.cn>");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
new file mode 100755
index 0000000..750580b
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
@@ -0,0 +1,298 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include "zx29_gmac.h"
+
+extern void v7_dma_map_area(const void *, size_t, int);
+extern unsigned long virt_to_phys_ap(unsigned long virt);
+
+void dma_map(const void * addr, size_t len, int flags)
+{
+ v7_dma_map_area(addr, len, flags);
+}
+EXPORT_SYMBOL(dma_map);
+
+unsigned long virt_to_phys_ap_new(unsigned long virt_addr)
+{
+ return virt_to_phys_ap(virt_addr);
+}
+EXPORT_SYMBOL(virt_to_phys_ap_new);
+
+int debug_on = 0;
+EXPORT_SYMBOL(debug_on);
+
+struct kset *kset_gmac;
+struct kobject *gmackobj = NULL;
+struct kobject *typekobj = NULL;
+char type[8] = { 0 };
+u32 zx29_gmac_plug_state[3] = {0}; /* 0:phy 1:sw_wan 2:sw_lan */
+
+static struct attribute gmac_phy_plug_attr = {
+ .name = "eth_phy_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_wan_plug_attr = {
+ .name = "eth_sw_wan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_lan_plug_attr = {
+ .name = "eth_sw_lan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute board_type = {
+ .name = "type",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute *gmac_status_attrs[] = {
+ &gmac_phy_plug_attr,
+ &gmac_sw_wan_plug_attr,
+ &gmac_sw_lan_plug_attr,
+ &board_type,
+ NULL,
+};
+
+ssize_t kobj_gmac_show(struct kobject *kobject,struct attribute *attr,char *buf)
+{
+ unsigned link =0;
+
+ if(!strcmp(attr->name,"eth_phy_state")) {
+ if(zx29_gmac_plug_state[0] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_wan_state")) {
+ if(zx29_gmac_plug_state[1] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_lan_state")) {
+ if(zx29_gmac_plug_state[2] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if (!strcmp(attr->name,"type")) {
+ sprintf(buf, "%s", type);
+ } else {
+ printk("invalidate attr name.\n");
+ }
+
+ return strlen(buf);
+}
+
+ssize_t kobj_gmac_store(struct kobject *kobject, struct attribute *attr, const char *buf, size_t size)
+{
+ unsigned int value = 0;
+ value = simple_strtoul(buf, NULL, 4);
+ printk("attrname: %s.\n", attr->name);
+ if (!strcmp(attr->name, "eth_phy_state")) {
+ zx29_gmac_plug_state[0] = value;
+ } else if (!strcmp(attr->name,"eth_sw_wan_state")) {
+ zx29_gmac_plug_state[1] = value;
+ } else if (!strcmp(attr->name,"eth_sw_lan_state")) {
+ zx29_gmac_plug_state[2] = value;
+ } else {
+ printk("invalidate attr name.\n");
+ }
+ return size;
+}
+
+static struct sysfs_ops obj_gmac_sysops = {
+ .show = kobj_gmac_show,
+ .store = kobj_gmac_store,
+};
+
+static void kobj_gmac_release(struct kobject *kobject)
+{
+ printk("[gmac kobj_test: release!]\n");
+}
+
+static void kobj_type_release(struct kobject *kobject)
+{
+ printk("[type kobj_test: release!]\n");
+}
+
+
+void kobj_gmac_del(struct kobject *kobject)
+{
+ kset_unregister(kset_gmac);
+
+ kobject_uevent(typekobj, KOBJ_REMOVE);
+ kobject_del(typekobj);
+ kobject_put(typekobj);
+ kfree(typekobj);
+
+ kobject_uevent(gmackobj, KOBJ_REMOVE);
+ kobject_del(gmackobj);
+ kobject_put(gmackobj);
+
+ kfree(gmackobj);
+
+ printk("[gmac kobj_test: delete!]\n");
+}
+EXPORT_SYMBOL(kobj_gmac_del);
+
+static struct kobj_type gmacktype =
+{ .release = kobj_gmac_release,
+ .sysfs_ops = &obj_gmac_sysops,
+ .default_attrs = gmac_status_attrs,
+};
+
+static struct kobj_type typektype =
+{ .release = kobj_type_release,
+// .sysfs_ops = &obj_gmac_sysops,
+// .default_attrs = gmac_status_attrs,
+};
+
+
+static int kset_filter(struct kset *kset,struct kobject *kobj)
+{
+ printk("kset Filter: kobj %s.\n",kobj->name);
+ return 1;
+}
+
+static const char *kset_name(struct kset *kset,struct kobject *kobj)
+{
+ static char buf[20];
+ printk("Name: kobj %s.\n",kobj->name);
+ sprintf(buf,"%s","gmac");
+ return buf;
+}
+
+static int kset_uevent(struct kset *kset, struct kobject *kobj, struct kobj_uevent_env *env)
+{
+ int i = 0;
+ printk("uevent: kobj %s.\n",kobj->name);
+ while (i < env->envp_idx) {
+ printk("%s.\n",env->envp[i]);
+ i++;
+ }
+
+ return 0;
+}
+
+static struct kset_uevent_ops gmac_uevent_ops =
+{
+ .filter = kset_filter,
+ .name = kset_name,
+ .uevent = kset_uevent,
+};
+
+void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void *puf)
+{
+ int rtv = -1;
+ enum kobject_action action = KOBJ_UNBIND;
+ char *envp_phy_ext[] = {"GMACEVENT=gmac_eth_phy",NULL};
+ char *envp_sw_wan_ext[] = {"GMACEVENT=gmac_eth_sw_wan",NULL};
+ char *envp_sw_lan_ext[] = {"GMACEVENT=gmac_eth_sw_lan",NULL};
+
+ switch (notify_type) {
+ case GMAC_ETH_PHY_PLUGIN:
+ printk("gmac eth phy plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[0] = 1;
+ if (gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action, envp_phy_ext);
+ break;
+
+ case GMAC_ETH_PHY_PLUGOUT:
+ printk("gmac eth phy plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[0] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_phy_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGIN:
+ printk("gmac eth switch wan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[1] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGOUT:
+ printk("gmac eth switch wan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[1] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGIN:
+ printk("gmac eth switch lan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[2] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGOUT:
+ printk("gmac eth switch lan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[2] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ default:
+ printk(KERN_WARNING "UNKWON GMAC EVENT \n");
+ break;
+ }
+
+ printk(KERN_WARNING "rtv:%d \n",rtv);
+}
+
+EXPORT_SYMBOL(gmac_event_notify);
+
+int gmac_event_init(const char *name)
+{
+ int ret = 0;
+ /* 创建并注册 kset_p */
+ gmackobj = kzalloc(sizeof(*gmackobj),GFP_KERNEL);
+ if(!gmackobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+ kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(gmackobj, &gmacktype);
+ kobject_add(gmackobj,&kset_gmac->kobj,"%s","gmacconfig");
+ gmackobj->kset = kset_gmac;
+
+ typekobj = kzalloc(sizeof(*typekobj),GFP_KERNEL);
+ if(!typekobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+// kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(typekobj, &typektype);
+ kobject_add(typekobj,&kset_gmac->kobj,"%s",name);
+ typekobj->kset = kset_gmac;
+
+ strcpy(type, name);
+
+ return ret;
+}
+EXPORT_SYMBOL(gmac_event_init);
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/phy/phy_device.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/phy/phy_device.c
new file mode 100755
index 0000000..d9b53ba
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/phy/phy_device.c
@@ -0,0 +1,3113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Framework for finding and configuring PHYs.
+ * Also contains generic PHY driver
+ *
+ * Author: Andy Fleming
+ *
+ * Copyright (c) 2004 Freescale Semiconductor, Inc.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/bitmap.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mdio.h>
+#include <linux/mii.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/phy_led_triggers.h>
+#include <linux/property.h>
+#include <linux/sfp.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+
+MODULE_DESCRIPTION("PHY library");
+MODULE_AUTHOR("Andy Fleming");
+MODULE_LICENSE("GPL");
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_t1_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_fibre_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_all_ports_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_fec_features);
+
+const int phy_basic_ports_array[3] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_ports_array);
+
+const int phy_fibre_port_array[1] = {
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_fibre_port_array);
+
+const int phy_all_ports_features_array[7] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+ ETHTOOL_LINK_MODE_AUI_BIT,
+ ETHTOOL_LINK_MODE_BNC_BIT,
+ ETHTOOL_LINK_MODE_Backplane_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_all_ports_features_array);
+
+const int phy_10_100_features_array[4] = {
+ ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10_100_features_array);
+
+const int phy_basic_t1_features_array[2] = {
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);
+
+const int phy_gbit_features_array[2] = {
+ ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_gbit_features_array);
+
+const int phy_10gbit_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10gbit_features_array);
+
+static const int phy_10gbit_fec_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
+};
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_full_features);
+
+static const int phy_10gbit_full_features_array[] = {
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+
+//status = phy_read_cl(phydev, MII_BMSR);
+static int phy_read_cl(struct phy_device *phydev, u32 regnum)
+{
+ int val = 0;
+
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 1);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0e, regnum);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 0x4000 | 1);
+ val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 0x0e);
+
+ return val;
+}
+
+static void features_init(void)
+{
+ /* 10/100 half/full*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_basic_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_basic_features);
+
+ /* 100 full, TP */
+ linkmode_set_bit_array(phy_basic_t1_features_array,
+ ARRAY_SIZE(phy_basic_t1_features_array),
+ phy_basic_t1_features);
+
+ /* 10/100 half/full + 1000 half/full */
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_features);
+
+ /* 10/100 half/full + 1000 half/full + fibre*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_fibre_port_array,
+ ARRAY_SIZE(phy_fibre_port_array),
+ phy_gbit_fibre_features);
+
+ /* 10/100 half/full + 1000 half/full + TP/MII/FIBRE/AUI/BNC/Backplane*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_all_ports_features);
+
+ /* 10/100 half/full + 1000 half/full + 10G full*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10gbit_features_array,
+ ARRAY_SIZE(phy_10gbit_features_array),
+ phy_10gbit_features);
+
+ /* 10/100/1000/10G full */
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_full_features);
+ linkmode_set_bit_array(phy_10gbit_full_features_array,
+ ARRAY_SIZE(phy_10gbit_full_features_array),
+ phy_10gbit_full_features);
+ /* 10G FEC only */
+ linkmode_set_bit_array(phy_10gbit_fec_features_array,
+ ARRAY_SIZE(phy_10gbit_fec_features_array),
+ phy_10gbit_fec_features);
+}
+
+void phy_device_free(struct phy_device *phydev)
+{
+ put_device(&phydev->mdio.dev);
+}
+EXPORT_SYMBOL(phy_device_free);
+
+static void phy_mdio_device_free(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_free(phydev);
+}
+
+static void phy_device_release(struct device *dev)
+{
+ kfree(to_phy_device(dev));
+}
+
+static void phy_mdio_device_remove(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_remove(phydev);
+}
+
+static struct phy_driver genphy_driver;
+
+static LIST_HEAD(phy_fixup_list);
+static DEFINE_MUTEX(phy_fixup_lock);
+
+static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
+{
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (!drv || !phydrv->suspend)
+ return false;
+
+ /* PHY not attached? May suspend if the PHY has not already been
+ * suspended as part of a prior call to phy_disconnect() ->
+ * phy_detach() -> phy_suspend() because the parent netdev might be the
+ * MDIO bus driver and clock gated at this point.
+ */
+ if (!netdev)
+ goto out;
+
+ if (netdev->wol_enabled)
+ return false;
+
+ /* As long as not all affected network drivers support the
+ * wol_enabled flag, let's check for hints that WoL is enabled.
+ * Don't suspend PHY if the attached netdev parent may wake up.
+ * The parent may point to a PCI device, as in tg3 driver.
+ */
+ if (netdev->dev.parent && device_may_wakeup(netdev->dev.parent))
+ return false;
+
+ /* Also don't suspend PHY if the netdev itself may wakeup. This
+ * is the case for devices w/o underlaying pwr. mgmt. aware bus,
+ * e.g. SoC devices.
+ */
+ if (device_may_wakeup(&netdev->dev))
+ return false;
+
+out:
+ return !phydev->suspended;
+}
+
+static __maybe_unused int mdio_bus_phy_suspend(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ /* We must stop the state machine manually, otherwise it stops out of
+ * control, possibly with the phydev->lock held. Upon resume, netdev
+ * may call phy routines that try to grab the same lock, and that may
+ * lead to a deadlock.
+ */
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_stop_machine(phydev);
+
+ if (!mdio_bus_phy_may_suspend(phydev))
+ return 0;
+
+ phydev->suspended_by_mdio_bus = 1;
+
+ return phy_suspend(phydev);
+}
+
+static __maybe_unused int mdio_bus_phy_resume(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ int ret;
+
+ if (!phydev->suspended_by_mdio_bus)
+ goto no_resume;
+
+ phydev->suspended_by_mdio_bus = 0;
+
+ ret = phy_init_hw(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_resume(phydev);
+ if (ret < 0)
+ return ret;
+no_resume:
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_start_machine(phydev);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mdio_bus_phy_pm_ops, mdio_bus_phy_suspend,
+ mdio_bus_phy_resume);
+
+/**
+ * phy_register_fixup - creates a new phy_fixup and adds it to the list
+ * @bus_id: A string which matches phydev->mdio.dev.bus_id (or PHY_ANY_ID)
+ * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
+ * It can also be PHY_ANY_UID
+ * @phy_uid_mask: Applied to phydev->phy_id and fixup->phy_uid before
+ * comparison
+ * @run: The actual code to be run when a matching PHY is found
+ */
+int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ struct phy_fixup *fixup = kzalloc(sizeof(*fixup), GFP_KERNEL);
+
+ if (!fixup)
+ return -ENOMEM;
+
+ strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id));
+ fixup->phy_uid = phy_uid;
+ fixup->phy_uid_mask = phy_uid_mask;
+ fixup->run = run;
+
+ mutex_lock(&phy_fixup_lock);
+ list_add_tail(&fixup->list, &phy_fixup_list);
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_register_fixup);
+
+/* Registers a fixup to be run on any PHY with the UID in phy_uid */
+int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_uid);
+
+/* Registers a fixup to be run on the PHY with id string bus_id */
+int phy_register_fixup_for_id(const char *bus_id,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_id);
+
+/**
+ * phy_unregister_fixup - remove a phy_fixup from the list
+ * @bus_id: A string matches fixup->bus_id (or PHY_ANY_ID) in phy_fixup_list
+ * @phy_uid: A phy id matches fixup->phy_id (or PHY_ANY_UID) in phy_fixup_list
+ * @phy_uid_mask: Applied to phy_uid and fixup->phy_uid before comparison
+ */
+int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask)
+{
+ struct list_head *pos, *n;
+ struct phy_fixup *fixup;
+ int ret;
+
+ ret = -ENODEV;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_safe(pos, n, &phy_fixup_list) {
+ fixup = list_entry(pos, struct phy_fixup, list);
+
+ if ((!strcmp(fixup->bus_id, bus_id)) &&
+ ((fixup->phy_uid & phy_uid_mask) ==
+ (phy_uid & phy_uid_mask))) {
+ list_del(&fixup->list);
+ kfree(fixup);
+ ret = 0;
+ break;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_unregister_fixup);
+
+/* Unregisters a fixup of any PHY with the UID in phy_uid */
+int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask)
+{
+ return phy_unregister_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_uid);
+
+/* Unregisters a fixup of the PHY with id string bus_id */
+int phy_unregister_fixup_for_id(const char *bus_id)
+{
+ return phy_unregister_fixup(bus_id, PHY_ANY_UID, 0xffffffff);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_id);
+
+/* Returns 1 if fixup matches phydev in bus_id and phy_uid.
+ * Fixups can be set to match any in one or more fields.
+ */
+static int phy_needs_fixup(struct phy_device *phydev, struct phy_fixup *fixup)
+{
+ if (strcmp(fixup->bus_id, phydev_name(phydev)) != 0)
+ if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ return 0;
+
+ if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+ (phydev->phy_id & fixup->phy_uid_mask))
+ if (fixup->phy_uid != PHY_ANY_UID)
+ return 0;
+
+ return 1;
+}
+
+/* Runs any matching fixups for this phydev */
+static int phy_scan_fixups(struct phy_device *phydev)
+{
+ struct phy_fixup *fixup;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_entry(fixup, &phy_fixup_list, list) {
+ if (phy_needs_fixup(phydev, fixup)) {
+ int err = fixup->run(phydev);
+
+ if (err < 0) {
+ mutex_unlock(&phy_fixup_lock);
+ return err;
+ }
+ phydev->has_fixups = true;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+
+static int phy_bus_match(struct device *dev, struct device_driver *drv)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
+ int i;
+
+ if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
+ return 0;
+
+ if (phydrv->match_phy_device)
+ return phydrv->match_phy_device(phydev);
+
+ if (phydev->is_c45) {
+ for (i = 1; i < num_ids; i++) {
+ if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ continue;
+
+ if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->c45_ids.device_ids[i] &
+ phydrv->phy_id_mask))
+ return 1;
+ }
+ return 0;
+ } else {
+ return (phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->phy_id & phydrv->phy_id_mask);
+ }
+}
+
+static ssize_t
+phy_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "0x%.8lx\n", (unsigned long)phydev->phy_id);
+}
+static DEVICE_ATTR_RO(phy_id);
+
+static ssize_t
+phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ const char *mode = NULL;
+
+ if (phy_is_internal(phydev))
+ mode = "internal";
+ else
+ mode = phy_modes(phydev->interface);
+
+ return sprintf(buf, "%s\n", mode);
+}
+static DEVICE_ATTR_RO(phy_interface);
+
+static ssize_t
+phy_has_fixups_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", phydev->has_fixups);
+}
+static DEVICE_ATTR_RO(phy_has_fixups);
+
+static struct attribute *phy_dev_attrs[] = {
+ &dev_attr_phy_id.attr,
+ &dev_attr_phy_interface.attr,
+ &dev_attr_phy_has_fixups.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(phy_dev);
+
+static const struct device_type mdio_bus_phy_type = {
+ .name = "PHY",
+ .groups = phy_dev_groups,
+ .release = phy_device_release,
+ .pm = pm_ptr(&mdio_bus_phy_pm_ops),
+};
+
+static int phy_request_driver_module(struct phy_device *dev, u32 phy_id)
+{
+ int ret;
+
+ ret = request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT,
+ MDIO_ID_ARGS(phy_id));
+ /* We only check for failures in executing the usermode binary,
+ * not whether a PHY driver module exists for the PHY ID.
+ * Accept -ENOENT because this may occur in case no initramfs exists,
+ * then modprobe isn't available.
+ */
+ if (IS_ENABLED(CONFIG_MODULES) && ret < 0 && ret != -ENOENT) {
+ phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n",
+ ret, (unsigned long)phy_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
+ bool is_c45,
+ struct phy_c45_device_ids *c45_ids)
+{
+ struct phy_device *dev;
+ struct mdio_device *mdiodev;
+ int ret = 0;
+
+ /* We allocate the device, and initialize the default values */
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ mdiodev = &dev->mdio;
+ mdiodev->dev.parent = &bus->dev;
+ mdiodev->dev.bus = &mdio_bus_type;
+ mdiodev->dev.type = &mdio_bus_phy_type;
+ mdiodev->bus = bus;
+ mdiodev->bus_match = phy_bus_match;
+ mdiodev->addr = addr;
+ mdiodev->flags = MDIO_DEVICE_FLAG_PHY;
+ mdiodev->device_free = phy_mdio_device_free;
+ mdiodev->device_remove = phy_mdio_device_remove;
+
+ dev->speed = SPEED_UNKNOWN;
+ dev->duplex = DUPLEX_UNKNOWN;
+ dev->pause = 0;
+ dev->asym_pause = 0;
+ dev->link = 0;
+ dev->port = PORT_TP;
+ dev->interface = PHY_INTERFACE_MODE_GMII;
+
+ dev->autoneg = AUTONEG_ENABLE;
+
+ dev->is_c45 = is_c45;
+ dev->phy_id = phy_id;
+ if (c45_ids)
+ dev->c45_ids = *c45_ids;
+ dev->irq = bus->irq[addr];
+
+ dev_set_name(&mdiodev->dev, PHY_ID_FMT, bus->id, addr);
+ device_initialize(&mdiodev->dev);
+
+ dev->state = PHY_DOWN;
+
+ mutex_init(&dev->lock);
+ INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
+
+ /* Request the appropriate module unconditionally; don't
+ * bother trying to do so only if it isn't already loaded,
+ * because that gets complicated. A hotplug event would have
+ * done an unconditional modprobe anyway.
+ * We don't do normal hotplug because it won't work for MDIO
+ * -- because it relies on the device staying around for long
+ * enough for the driver to get loaded. With MDIO, the NIC
+ * driver will get bored and give up as soon as it finds that
+ * there's no driver _already_ loaded.
+ */
+ if (is_c45 && c45_ids) {
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ int i;
+
+ for (i = 1; i < num_ids; i++) {
+ if (c45_ids->device_ids[i] == 0xffffffff)
+ continue;
+
+ ret = phy_request_driver_module(dev,
+ c45_ids->device_ids[i]);
+ if (ret)
+ break;
+ }
+ } else {
+ ret = phy_request_driver_module(dev, phy_id);
+ }
+
+ if (ret) {
+ put_device(&mdiodev->dev);
+ dev = ERR_PTR(ret);
+ }
+
+ return dev;
+}
+EXPORT_SYMBOL(phy_device_create);
+
+/* phy_c45_probe_present - checks to see if a MMD is present in the package
+ * @bus: the target MII bus
+ * @prtad: PHY package address on the MII bus
+ * @devad: PHY device (MMD) address
+ *
+ * Read the MDIO_STAT2 register, and check whether a device is responding
+ * at this address.
+ *
+ * Returns: negative error number on bus access error, zero if no device
+ * is responding, or positive if a device is present.
+ */
+static int phy_c45_probe_present(struct mii_bus *bus, int prtad, int devad)
+{
+ int stat2;
+
+ stat2 = mdiobus_c45_read(bus, prtad, devad, MDIO_STAT2);
+ if (stat2 < 0)
+ return stat2;
+
+ return (stat2 & MDIO_STAT2_DEVPRST) == MDIO_STAT2_DEVPRST_VAL;
+}
+
+/* get_phy_c45_devs_in_pkg - reads a MMD's devices in package registers.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @dev_addr: MMD address in the PHY.
+ * @devices_in_package: where to store the devices in package information.
+ *
+ * Description: reads devices in package registers of a MMD at @dev_addr
+ * from PHY at @addr on @bus.
+ *
+ * Returns: 0 on success, -EIO on failure.
+ */
+static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr,
+ u32 *devices_in_package)
+{
+ int phy_reg;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package |= phy_reg;
+
+ return 0;
+}
+
+/**
+ * get_phy_c45_ids - reads the specified addr for its 802.3-c45 IDs.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @c45_ids: where to store the c45 ID information.
+ *
+ * Read the PHY "devices in package". If this appears to be valid, read
+ * the PHY identifiers for each device. Return the "devices in package"
+ * and identifiers in @c45_ids.
+ *
+ * Returns zero on success, %-EIO on bus access error, or %-ENODEV if
+ * the "devices in package" is invalid.
+ */
+static int get_phy_c45_ids(struct mii_bus *bus, int addr,
+ struct phy_c45_device_ids *c45_ids)
+{
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ u32 devs_in_pkg = 0;
+ int i, ret, phy_reg;
+
+ /* Find first non-zero Devices In package. Device zero is reserved
+ * for 802.3 c45 complied PHYs, so don't probe it at first.
+ */
+ for (i = 1; i < MDIO_MMD_NUM && (devs_in_pkg == 0 ||
+ (devs_in_pkg & 0x1fffffff) == 0x1fffffff); i++) {
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Check that there is a device present at this
+ * address before reading the devices-in-package
+ * register to avoid reading garbage from the PHY.
+ * Some PHYs (88x3310) vendor space is not IEEE802.3
+ * compliant.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return -EIO;
+
+ if (!ret)
+ continue;
+ }
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, i, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+ }
+
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff) {
+ /* If mostly Fs, there is no device there, then let's probe
+ * MMD 0, as some 10G PHYs have zero Devices In package,
+ * e.g. Cortina CS4315/CS4340 PHY.
+ */
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, 0, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+
+ /* no device there, let's get out of here */
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+ }
+
+ /* Now probe Device Identifiers for each device present. */
+ for (i = 1; i < num_ids; i++) {
+ if (!(devs_in_pkg & (1 << i)))
+ continue;
+
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Probe the "Device Present" bits for the vendor MMDs
+ * to ignore these if they do not contain IEEE 802.3
+ * registers.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return ret;
+
+ if (!ret)
+ continue;
+ }
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID1);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID2);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] |= phy_reg;
+ }
+
+ c45_ids->devices_in_package = devs_in_pkg;
+ /* Bit 0 doesn't represent a device, it indicates c22 regs presence */
+ c45_ids->mmds_present = devs_in_pkg & ~BIT(0);
+
+ return 0;
+}
+
+/**
+ * get_phy_c22_id - reads the specified addr for its clause 22 ID.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @phy_id: where to store the ID retrieved.
+ *
+ * Read the 802.3 clause 22 PHY ID from the PHY at @addr on the @bus,
+ * placing it in @phy_id. Return zero on successful read and the ID is
+ * valid, %-EIO on bus access error, or %-ENODEV if no device responds
+ * or invalid ID.
+ */
+static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id)
+{
+ int phy_reg;
+
+ /* Grab the bits from PHYIR1, and put them in the upper half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 2);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id = phy_reg << 16;
+
+ /* Grab the bits from PHYIR2, and put them in the lower half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#ifdef CONFIG_MDIO_C45
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 3);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id |= phy_reg;
+
+#ifdef CONFIG_MDIO_C45
+ printk("[%s] read with c45 phy id:0x%x\n", __func__, *phy_id);
+#else
+ printk("[%s] read with c22 phy id:0x%x\n", __func__, *phy_id);
+#endif
+ /* If the phy_id is mostly Fs, there is no device there */
+ if ((*phy_id & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+
+ return 0;
+}
+
+/**
+ * get_phy_device - reads the specified PHY device and returns its @phy_device
+ * struct
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @is_c45: If true the PHY uses the 802.3 clause 45 protocol
+ *
+ * Probe for a PHY at @addr on @bus.
+ *
+ * When probing for a clause 22 PHY, then read the ID registers. If we find
+ * a valid ID, allocate and return a &struct phy_device.
+ *
+ * When probing for a clause 45 PHY, read the "devices in package" registers.
+ * If the "devices in package" appears valid, read the ID registers for each
+ * MMD, allocate and return a &struct phy_device.
+ *
+ * Returns an allocated &struct phy_device on success, %-ENODEV if there is
+ * no PHY present, or %-EIO on bus access error.
+ */
+struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
+{
+ struct phy_c45_device_ids c45_ids;
+ u32 phy_id = 0;
+ int r;
+
+ c45_ids.devices_in_package = 0;
+ c45_ids.mmds_present = 0;
+ memset(c45_ids.device_ids, 0xff, sizeof(c45_ids.device_ids));
+
+ if (is_c45)
+ r = get_phy_c45_ids(bus, addr, &c45_ids);
+ else
+ r = get_phy_c22_id(bus, addr, &phy_id);
+
+ if (r)
+ return ERR_PTR(r);
+
+ return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids);
+}
+EXPORT_SYMBOL(get_phy_device);
+
+/**
+ * phy_device_register - Register the phy device on the MDIO bus
+ * @phydev: phy_device structure to be added to the MDIO bus
+ */
+int phy_device_register(struct phy_device *phydev)
+{
+ int err;
+
+ err = mdiobus_register_device(&phydev->mdio);
+ if (err)
+ return err;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ /* Run all of the fixups for this PHY */
+ err = phy_scan_fixups(phydev);
+ if (err) {
+ phydev_err(phydev, "failed to initialize\n");
+ goto out;
+ }
+
+ err = device_add(&phydev->mdio.dev);
+ if (err) {
+ phydev_err(phydev, "failed to add\n");
+ goto out;
+ }
+
+ return 0;
+
+ out:
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+ return err;
+}
+EXPORT_SYMBOL(phy_device_register);
+
+/**
+ * phy_device_remove - Remove a previously registered phy device from the MDIO bus
+ * @phydev: phy_device structure to remove
+ *
+ * This doesn't free the phy_device itself, it merely reverses the effects
+ * of phy_device_register(). Use phy_device_free() to free the device
+ * after calling this function.
+ */
+void phy_device_remove(struct phy_device *phydev)
+{
+ if (phydev->mii_ts)
+ unregister_mii_timestamper(phydev->mii_ts);
+
+ device_del(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+}
+EXPORT_SYMBOL(phy_device_remove);
+
+/**
+ * phy_find_first - finds the first PHY device on the bus
+ * @bus: the target MII bus
+ */
+struct phy_device *phy_find_first(struct mii_bus *bus)
+{
+ struct phy_device *phydev;
+ int addr;
+
+ for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+ phydev = mdiobus_get_phy(bus, addr);
+ if (phydev) {
+ printk("[%s] addr:%d\n", __func__, addr);
+ return phydev;
+ }
+ }
+ return NULL;
+}
+EXPORT_SYMBOL(phy_find_first);
+
+static void phy_link_change(struct phy_device *phydev, bool up)
+{
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (up)
+ netif_carrier_on(netdev);
+ else
+ netif_carrier_off(netdev);
+ phydev->adjust_link(netdev);
+ if (phydev->mii_ts && phydev->mii_ts->link_state)
+ phydev->mii_ts->link_state(phydev->mii_ts, phydev);
+}
+
+/**
+ * phy_prepare_link - prepares the PHY layer to monitor link status
+ * @phydev: target phy_device struct
+ * @handler: callback function for link status change notifications
+ *
+ * Description: Tells the PHY infrastructure to handle the
+ * gory details on monitoring link status (whether through
+ * polling or an interrupt), and to call back to the
+ * connected device driver when the link status changes.
+ * If you want to monitor your own link state, don't call
+ * this function.
+ */
+static void phy_prepare_link(struct phy_device *phydev,
+ void (*handler)(struct net_device *))
+{
+ phydev->adjust_link = handler;
+}
+
+/**
+ * phy_connect_direct - connect an ethernet device to a specific phy_device
+ * @dev: the network device to connect
+ * @phydev: the pointer to the phy device
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ */
+int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ int rc;
+
+ if (!dev)
+ return -EINVAL;
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ if (rc)
+ return rc;
+
+ phy_prepare_link(phydev, handler);
+ if (phy_interrupt_is_valid(phydev))
+ phy_request_interrupt(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_connect_direct);
+
+/**
+ * phy_connect - connect an ethernet device to a PHY device
+ * @dev: the network device to connect
+ * @bus_id: the id string of the PHY device to connect
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ *
+ * Description: Convenience function for connecting ethernet
+ * devices to PHY devices. The default behavior is for
+ * the PHY infrastructure to handle everything, and only notify
+ * the connected driver when the link status changes. If you
+ * don't want, or can't use the provided functionality, you may
+ * choose to call only the subset of functions which provide
+ * the desired functionality.
+ */
+struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(&mdio_bus_type, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_connect_direct(dev, phydev, handler, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_connect);
+
+/**
+ * phy_disconnect - disable interrupts, stop state machine, and detach a PHY
+ * device
+ * @phydev: target phy_device struct
+ */
+void phy_disconnect(struct phy_device *phydev)
+{
+ if (phy_is_started(phydev))
+ phy_stop(phydev);
+
+ if (phy_interrupt_is_valid(phydev))
+ phy_free_interrupt(phydev);
+
+ phydev->adjust_link = NULL;
+
+ phy_detach(phydev);
+}
+EXPORT_SYMBOL(phy_disconnect);
+
+/**
+ * phy_poll_reset - Safely wait until a PHY reset has properly completed
+ * @phydev: The PHY device to poll
+ *
+ * Description: According to IEEE 802.3, Section 2, Subsection 22.2.4.1.1, as
+ * published in 2008, a PHY reset may take up to 0.5 seconds. The MII BMCR
+ * register must be polled until the BMCR_RESET bit clears.
+ *
+ * Furthermore, any attempts to write to PHY registers may have no effect
+ * or even generate MDIO bus errors until this is complete.
+ *
+ * Some PHYs (such as the Marvell 88E1111) don't entirely conform to the
+ * standard and do not fully reset after the BMCR_RESET bit is set, and may
+ * even *REQUIRE* a soft-reset to properly restart autonegotiation. In an
+ * effort to support such broken PHYs, this function is separate from the
+ * standard phy_init_hw() which will zero all the other bits in the BMCR
+ * and reapply all driver-specific and board-specific fixups.
+ */
+static int phy_poll_reset(struct phy_device *phydev)
+{
+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
+ int ret, val;
+
+ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+ 50000, 600000, true);
+ if (ret)
+ return ret;
+ /* Some chips (smsc911x) may still need up to another 1ms after the
+ * BMCR_RESET bit is cleared before they are usable.
+ */
+ msleep(1);
+ return 0;
+}
+
+int phy_init_hw(struct phy_device *phydev)
+{
+ int ret = 0;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (!phydev->drv)
+ return 0;
+
+ if (phydev->drv->soft_reset) {
+ ret = phydev->drv->soft_reset(phydev);
+ /* see comment in genphy_soft_reset for an explanation */
+ if (!ret)
+ phydev->suspended = 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ ret = phy_scan_fixups(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->drv->config_init) {
+ ret = phydev->drv->config_init(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (phydev->drv->config_intr) {
+ ret = phydev->drv->config_intr(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_init_hw);
+
+void phy_attached_info(struct phy_device *phydev)
+{
+ phy_attached_print(phydev, NULL);
+}
+EXPORT_SYMBOL(phy_attached_info);
+
+#define ATTACHED_FMT "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%s)"
+char *phy_attached_info_irq(struct phy_device *phydev)
+{
+ char *irq_str;
+ char irq_num[8];
+
+ switch(phydev->irq) {
+ case PHY_POLL:
+ irq_str = "POLL";
+ break;
+ case PHY_IGNORE_INTERRUPT:
+ irq_str = "IGNORE";
+ break;
+ default:
+ snprintf(irq_num, sizeof(irq_num), "%d", phydev->irq);
+ irq_str = irq_num;
+ break;
+ }
+
+ return kasprintf(GFP_KERNEL, "%s", irq_str);
+}
+EXPORT_SYMBOL(phy_attached_info_irq);
+
+void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
+{
+ const char *drv_name = phydev->drv ? phydev->drv->name : "unbound";
+ char *irq_str = phy_attached_info_irq(phydev);
+
+ if (!fmt) {
+ phydev_info(phydev, ATTACHED_FMT "\n",
+ drv_name, phydev_name(phydev),
+ irq_str);
+ } else {
+ va_list ap;
+
+ phydev_info(phydev, ATTACHED_FMT,
+ drv_name, phydev_name(phydev),
+ irq_str);
+
+ va_start(ap, fmt);
+ vprintk(fmt, ap);
+ va_end(ap);
+ }
+ kfree(irq_str);
+}
+EXPORT_SYMBOL(phy_attached_print);
+
+static void phy_sysfs_create_links(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ int err;
+
+ if (!dev)
+ return;
+
+ err = sysfs_create_link(&phydev->mdio.dev.kobj, &dev->dev.kobj,
+ "attached_dev");
+ if (err)
+ return;
+
+ err = sysfs_create_link_nowarn(&dev->dev.kobj,
+ &phydev->mdio.dev.kobj,
+ "phydev");
+ if (err) {
+ dev_err(&dev->dev, "could not add device link to %s err %d\n",
+ kobject_name(&phydev->mdio.dev.kobj),
+ err);
+ /* non-fatal - some net drivers can use one netdevice
+ * with more then one phy
+ */
+ }
+
+ phydev->sysfs_links = true;
+}
+
+static ssize_t
+phy_standalone_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", !phydev->attached_dev);
+}
+static DEVICE_ATTR_RO(phy_standalone);
+
+/**
+ * phy_sfp_attach - attach the SFP bus to the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .attach member.
+ */
+void phy_sfp_attach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = bus;
+ phydev->sfp_bus_attached = true;
+}
+EXPORT_SYMBOL(phy_sfp_attach);
+
+/**
+ * phy_sfp_detach - detach the SFP bus from the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .detach member.
+ */
+void phy_sfp_detach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = NULL;
+ phydev->sfp_bus_attached = false;
+}
+EXPORT_SYMBOL(phy_sfp_detach);
+
+/**
+ * phy_sfp_probe - probe for a SFP cage attached to this PHY device
+ * @phydev: Pointer to phy_device
+ * @ops: SFP's upstream operations
+ */
+int phy_sfp_probe(struct phy_device *phydev,
+ const struct sfp_upstream_ops *ops)
+{
+ struct sfp_bus *bus;
+ int ret = 0;
+
+ if (phydev->mdio.dev.fwnode) {
+ bus = sfp_bus_find_fwnode(phydev->mdio.dev.fwnode);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ phydev->sfp_bus = bus;
+
+ ret = sfp_bus_add_upstream(bus, phydev, ops);
+ sfp_bus_put(bus);
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_sfp_probe);
+
+/**
+ * phy_attach_direct - attach a network device to a given PHY device pointer
+ * @dev: network device to attach
+ * @phydev: Pointer to phy_device to attach
+ * @flags: PHY device's dev_flags
+ * @interface: PHY device's interface
+ *
+ * Description: Called by drivers to attach to a particular PHY
+ * device. The phy_device is found, and properly hooked up
+ * to the phy_driver. If no driver is attached, then a
+ * generic driver is used. The phy_device is given a ptr to
+ * the attaching device, and given a callback for link status
+ * change. The phy_device is returned to the attaching driver.
+ * This function takes a reference on the phy device.
+ */
+int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
+ u32 flags, phy_interface_t interface)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct device *d = &phydev->mdio.dev;
+ struct module *ndev_owner = NULL;
+ bool using_genphy = false;
+ int err;
+
+ /* For Ethernet device drivers that register their own MDIO bus, we
+ * will have bus->owner match ndev_mod, so we do not want to increment
+ * our own module->refcnt here, otherwise we would not be able to
+ * unload later on.
+ */
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner && !try_module_get(bus->owner)) {
+ phydev_err(phydev, "failed to get the bus module\n");
+ return -EIO;
+ }
+
+ get_device(d);
+
+ /* Assume that if there is no driver, that it doesn't
+ * exist, and we should use the genphy driver.
+ */
+ if (!d->driver) {
+ if (phydev->is_c45)
+ d->driver = &genphy_c45_driver.mdiodrv.driver;
+ else
+ d->driver = &genphy_driver.mdiodrv.driver;
+
+ using_genphy = true;
+ }
+
+ if (!try_module_get(d->driver->owner)) {
+ phydev_err(phydev, "failed to get the device driver module\n");
+ err = -EIO;
+ goto error_put_device;
+ }
+
+ if (using_genphy) {
+ err = d->driver->probe(d);
+ if (err >= 0)
+ err = device_bind_driver(d);
+
+ if (err)
+ goto error_module_put;
+ }
+
+ if (phydev->attached_dev) {
+ dev_err(&dev->dev, "PHY already attached\n");
+ err = -EBUSY;
+ goto error;
+ }
+
+ phydev->phy_link_change = phy_link_change;
+ if (dev) {
+ phydev->attached_dev = dev;
+ dev->phydev = phydev;
+
+ if (phydev->sfp_bus_attached)
+ dev->sfp_bus = phydev->sfp_bus;
+ }
+
+ /* Some Ethernet drivers try to connect to a PHY device before
+ * calling register_netdevice() -> netdev_register_kobject() and
+ * does the dev->dev.kobj initialization. Here we only check for
+ * success which indicates that the network device kobject is
+ * ready. Once we do that we still need to keep track of whether
+ * links were successfully set up or not for phy_detach() to
+ * remove them accordingly.
+ */
+ phydev->sysfs_links = false;
+
+ phy_sysfs_create_links(phydev);
+
+ if (!phydev->attached_dev) {
+ err = sysfs_create_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+ if (err)
+ phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n");
+ }
+
+ phydev->dev_flags |= flags;
+
+ phydev->interface = interface;
+
+ phydev->state = PHY_READY;
+
+ /* Port is set to PORT_TP by default and the actual PHY driver will set
+ * it to different value depending on the PHY configuration. If we have
+ * the generic PHY driver we can't figure it out, thus set the old
+ * legacy PORT_MII value.
+ */
+ if (using_genphy)
+ phydev->port = PORT_MII;
+
+ /* Initial carrier state is off as the phy is about to be
+ * (re)initialized.
+ */
+ if (dev)
+ netif_carrier_off(phydev->attached_dev);
+
+ /* Do initial configuration here, now that
+ * we have certain key parameters
+ * (dev_flags and interface)
+ */
+ err = phy_init_hw(phydev);
+ if (err)
+ goto error;
+
+ err = phy_disable_interrupts(phydev);
+ if (err)
+ return err;
+
+ phy_resume(phydev);
+ phy_led_triggers_register(phydev);
+
+ return err;
+
+error:
+ /* phy_detach() does all of the cleanup below */
+ phy_detach(phydev);
+ return err;
+
+error_module_put:
+ module_put(d->driver->owner);
+error_put_device:
+ put_device(d);
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+ return err;
+}
+EXPORT_SYMBOL(phy_attach_direct);
+
+/**
+ * phy_attach - attach a network device to a particular PHY device
+ * @dev: network device to attach
+ * @bus_id: Bus ID of PHY device to attach
+ * @interface: PHY device's interface
+ *
+ * Description: Same as phy_attach_direct() except that a PHY bus_id
+ * string is passed instead of a pointer to a struct phy_device.
+ */
+struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
+ phy_interface_t interface)
+{
+ struct bus_type *bus = &mdio_bus_type;
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(bus, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_attach);
+
+static bool phy_driver_is_genphy_kind(struct phy_device *phydev,
+ struct device_driver *driver)
+{
+ struct device *d = &phydev->mdio.dev;
+ bool ret = false;
+
+ if (!phydev->drv)
+ return ret;
+
+ get_device(d);
+ ret = d->driver == driver;
+ put_device(d);
+
+ return ret;
+}
+
+bool phy_driver_is_genphy(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
+
+bool phy_driver_is_genphy_10g(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_c45_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
+
+/**
+ * phy_package_join - join a common PHY group
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * This joins a PHY group and provides a shared storage for all phydevs in
+ * this group. This is intended to be used for packages which contain
+ * more than one PHY, for example a quad PHY transceiver.
+ *
+ * The addr parameter serves as a cookie which has to have the same value
+ * for all members of one group and as a PHY address to access generic
+ * registers of a PHY package. Usually, one of the PHY addresses of the
+ * different PHYs in the package provides access to these global registers.
+ * The address which is given here, will be used in the phy_package_read()
+ * and phy_package_write() convenience functions. If your PHY doesn't have
+ * global registers you can just pick any of the PHY addresses.
+ *
+ * This will set the shared pointer of the phydev to the shared storage.
+ * If this is the first call for a this cookie the shared storage will be
+ * allocated. If priv_size is non-zero, the given amount of bytes are
+ * allocated for the priv member.
+ *
+ * Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
+ * with the same cookie but a different priv_size is an error.
+ */
+int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct phy_package_shared *shared;
+ int ret;
+
+ if (addr < 0 || addr >= PHY_MAX_ADDR)
+ return -EINVAL;
+
+ mutex_lock(&bus->shared_lock);
+ shared = bus->shared[addr];
+ if (!shared) {
+ ret = -ENOMEM;
+ shared = kzalloc(sizeof(*shared), GFP_KERNEL);
+ if (!shared)
+ goto err_unlock;
+ if (priv_size) {
+ shared->priv = kzalloc(priv_size, GFP_KERNEL);
+ if (!shared->priv)
+ goto err_free;
+ shared->priv_size = priv_size;
+ }
+ shared->addr = addr;
+ refcount_set(&shared->refcnt, 1);
+ bus->shared[addr] = shared;
+ } else {
+ ret = -EINVAL;
+ if (priv_size && priv_size != shared->priv_size)
+ goto err_unlock;
+ refcount_inc(&shared->refcnt);
+ }
+ mutex_unlock(&bus->shared_lock);
+
+ phydev->shared = shared;
+
+ return 0;
+
+err_free:
+ kfree(shared);
+err_unlock:
+ mutex_unlock(&bus->shared_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_package_join);
+
+/**
+ * phy_package_leave - leave a common PHY group
+ * @phydev: target phy_device struct
+ *
+ * This leaves a PHY group created by phy_package_join(). If this phydev
+ * was the last user of the shared data between the group, this data is
+ * freed. Resets the phydev->shared pointer to NULL.
+ */
+void phy_package_leave(struct phy_device *phydev)
+{
+ struct phy_package_shared *shared = phydev->shared;
+ struct mii_bus *bus = phydev->mdio.bus;
+
+ if (!shared)
+ return;
+
+ if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+ bus->shared[shared->addr] = NULL;
+ mutex_unlock(&bus->shared_lock);
+ kfree(shared->priv);
+ kfree(shared);
+ }
+
+ phydev->shared = NULL;
+}
+EXPORT_SYMBOL_GPL(phy_package_leave);
+
+static void devm_phy_package_leave(struct device *dev, void *res)
+{
+ phy_package_leave(*(struct phy_device **)res);
+}
+
+/**
+ * devm_phy_package_join - resource managed phy_package_join()
+ * @dev: device that is registering this PHY package
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * Managed phy_package_join(). Shared storage fetched by this function,
+ * phy_package_leave() is automatically called on driver detach. See
+ * phy_package_join() for more information.
+ */
+int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+ int addr, size_t priv_size)
+{
+ struct phy_device **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_phy_package_leave, sizeof(*ptr),
+ GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = phy_package_join(phydev, addr, priv_size);
+
+ if (!ret) {
+ *ptr = phydev;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_phy_package_join);
+
+/**
+ * phy_detach - detach a PHY device from its network device
+ * @phydev: target phy_device struct
+ *
+ * This detaches the phy device from its network device and the phy
+ * driver, and drops the reference count taken in phy_attach_direct().
+ */
+void phy_detach(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ struct module *ndev_owner = NULL;
+ struct mii_bus *bus;
+
+ if (phydev->sysfs_links) {
+ if (dev)
+ sysfs_remove_link(&dev->dev.kobj, "phydev");
+ sysfs_remove_link(&phydev->mdio.dev.kobj, "attached_dev");
+ }
+
+ if (!phydev->attached_dev)
+ sysfs_remove_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+
+ phy_suspend(phydev);
+ if (dev) {
+ phydev->attached_dev->phydev = NULL;
+ phydev->attached_dev = NULL;
+ }
+ phydev->phylink = NULL;
+
+ phy_led_triggers_unregister(phydev);
+
+ if (phydev->mdio.dev.driver)
+ module_put(phydev->mdio.dev.driver->owner);
+
+ /* If the device had no specific driver before (i.e. - it
+ * was using the generic driver), we unbind the device
+ * from the generic driver so that there's a chance a
+ * real driver could be loaded
+ */
+ if (phy_driver_is_genphy(phydev) ||
+ phy_driver_is_genphy_10g(phydev))
+ device_release_driver(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ /*
+ * The phydev might go away on the put_device() below, so avoid
+ * a use-after-free bug by reading the underlying bus first.
+ */
+ bus = phydev->mdio.bus;
+
+ put_device(&phydev->mdio.dev);
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+}
+EXPORT_SYMBOL(phy_detach);
+
+int phy_suspend(struct phy_device *phydev)
+{
+ struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
+ struct net_device *netdev = phydev->attached_dev;
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ if (phydev->suspended)
+ return 0;
+
+ /* If the device has WOL enabled, we cannot suspend the PHY */
+ phy_ethtool_get_wol(phydev, &wol);
+ if (wol.wolopts || (netdev && netdev->wol_enabled))
+ return -EBUSY;
+
+ if (!phydrv || !phydrv->suspend)
+ return 0;
+
+ ret = phydrv->suspend(phydev);
+ if (!ret)
+ phydev->suspended = true;
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_suspend);
+
+int __phy_resume(struct phy_device *phydev)
+{
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ WARN_ON(!mutex_is_locked(&phydev->lock));
+
+ if (!phydrv || !phydrv->resume)
+ return 0;
+
+ ret = phydrv->resume(phydev);
+ if (!ret)
+ phydev->suspended = false;
+
+ return ret;
+}
+EXPORT_SYMBOL(__phy_resume);
+
+int phy_resume(struct phy_device *phydev)
+{
+ int ret;
+
+ mutex_lock(&phydev->lock);
+ ret = __phy_resume(phydev);
+ mutex_unlock(&phydev->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_resume);
+
+int phy_loopback(struct phy_device *phydev, bool enable)
+{
+ struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver);
+ int ret = 0;
+
+ mutex_lock(&phydev->lock);
+
+ if (enable && phydev->loopback_enabled) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ if (!enable && !phydev->loopback_enabled) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (phydev->drv && phydrv->set_loopback)
+ ret = phydrv->set_loopback(phydev, enable);
+ else
+ ret = -EOPNOTSUPP;
+
+ if (ret)
+ goto out;
+
+ phydev->loopback_enabled = enable;
+
+out:
+ mutex_unlock(&phydev->lock);
+ return ret;
+}
+EXPORT_SYMBOL(phy_loopback);
+
+/**
+ * phy_reset_after_clk_enable - perform a PHY reset if needed
+ * @phydev: target phy_device struct
+ *
+ * Description: Some PHYs are known to need a reset after their refclk was
+ * enabled. This function evaluates the flags and perform the reset if it's
+ * needed. Returns < 0 on error, 0 if the phy wasn't reset and 1 if the phy
+ * was reset.
+ */
+int phy_reset_after_clk_enable(struct phy_device *phydev)
+{
+ if (!phydev || !phydev->drv)
+ return -ENODEV;
+
+ if (phydev->drv->flags & PHY_RST_AFTER_CLK_EN) {
+ phy_device_reset(phydev, 1);
+ phy_device_reset(phydev, 0);
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_reset_after_clk_enable);
+
+/* Generic PHY support and helper functions */
+
+/**
+ * genphy_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed.
+ */
+static int genphy_config_advert(struct phy_device *phydev)
+{
+ int err, bmsr, changed = 0;
+ u32 adv;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
+
+ /* Setup standard advertisement */
+ err = phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_100BASE4 |
+ ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ bmsr = phy_read(phydev, MII_BMSR);
+ if (bmsr < 0)
+ return bmsr;
+
+ /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
+ * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
+ * logical 1.
+ */
+ if (!(bmsr & BMSR_ESTATEN))
+ return changed;
+
+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+
+ err = phy_modify_changed(phydev, MII_CTRL1000,
+ ADVERTISE_1000FULL | ADVERTISE_1000HALF,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ return changed;
+}
+
+/**
+ * genphy_c37_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed. This function is intended
+ * for Clause 37 1000Base-X mode.
+ */
+static int genphy_c37_config_advert(struct phy_device *phydev)
+{
+ u16 adv = 0;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XFULL;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPAUSE;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPSE_ASYM;
+
+ return phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
+ ADVERTISE_1000XHALF | ADVERTISE_1000XPSE_ASYM,
+ adv);
+}
+
+/**
+ * genphy_config_eee_advert - disable unwanted eee mode advertisement
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MDIO_AN_EEE_ADV after disabling unsupported energy
+ * efficent ethernet modes. Returns 0 if the PHY's advertisement hasn't
+ * changed, and 1 if it has changed.
+ */
+int genphy_config_eee_advert(struct phy_device *phydev)
+{
+ int err;
+
+ /* Nothing to disable */
+ if (!phydev->eee_broken_modes)
+ return 0;
+
+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ phydev->eee_broken_modes, 0);
+ /* If the call failed, we assume that EEE is not supported */
+ return err < 0 ? 0 : err;
+}
+EXPORT_SYMBOL(genphy_config_eee_advert);
+
+/**
+ * genphy_setup_forced - configures/forces speed/duplex from @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Configures MII_BMCR to force speed/duplex
+ * to the values in phydev. Assumes that the values are valid.
+ * Please see phy_sanitize_settings().
+ */
+int genphy_setup_forced(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (SPEED_1000 == phydev->speed)
+ ctl |= BMCR_SPEED1000;
+ else if (SPEED_100 == phydev->speed)
+ ctl |= BMCR_SPEED100;
+
+ if (DUPLEX_FULL == phydev->duplex)
+ ctl |= BMCR_FULLDPLX;
+
+ return phy_modify(phydev, MII_BMCR,
+ ~(BMCR_LOOPBACK | BMCR_ISOLATE | BMCR_PDOWN), ctl);
+}
+EXPORT_SYMBOL(genphy_setup_forced);
+
+static int genphy_setup_master_slave(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ if (!phydev->is_gigabit_capable)
+ return 0;
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ ctl |= CTL1000_PREFER_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ break;
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ ctl |= CTL1000_AS_MASTER;
+ fallthrough;
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ ctl |= CTL1000_ENABLE_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_UNKNOWN:
+ case MASTER_SLAVE_CFG_UNSUPPORTED:
+ return 0;
+ default:
+ phydev_warn(phydev, "Unsupported Master/Slave mode\n");
+ return -EOPNOTSUPP;
+ }
+
+ return phy_modify_changed(phydev, MII_CTRL1000,
+ (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
+ CTL1000_PREFER_MASTER), ctl);
+}
+
+static int genphy_read_master_slave(struct phy_device *phydev)
+{
+ int cfg, state;
+ int val;
+
+ if (!phydev->is_gigabit_capable) {
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
+ return 0;
+ }
+
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+
+ val = phy_read(phydev, MII_CTRL1000);
+ if (val < 0)
+ return val;
+
+ if (val & CTL1000_ENABLE_MASTER) {
+ if (val & CTL1000_AS_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_FORCE;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_FORCE;
+ } else {
+ if (val & CTL1000_PREFER_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_PREFERRED;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
+ }
+
+ val = phy_read(phydev, MII_STAT1000);
+ if (val < 0)
+ return val;
+
+ if (val & LPA_1000MSFAIL) {
+ state = MASTER_SLAVE_STATE_ERR;
+ } else if (phydev->link) {
+ /* this bits are valid only for active link */
+ if (val & LPA_1000MSRES)
+ state = MASTER_SLAVE_STATE_MASTER;
+ else
+ state = MASTER_SLAVE_STATE_SLAVE;
+ } else {
+ state = MASTER_SLAVE_STATE_UNKNOWN;
+ }
+
+ phydev->master_slave_get = cfg;
+ phydev->master_slave_state = state;
+
+ return 0;
+}
+
+/**
+ * genphy_restart_aneg - Enable and Restart Autonegotiation
+ * @phydev: target phy_device struct
+ */
+int genphy_restart_aneg(struct phy_device *phydev)
+{
+ /* Don't isolate the PHY if we're negotiating */
+ return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+}
+EXPORT_SYMBOL(genphy_restart_aneg);
+
+/**
+ * genphy_check_and_restart_aneg - Enable and restart auto-negotiation
+ * @phydev: target phy_device struct
+ * @restart: whether aneg restart is requested
+ *
+ * Check, and restart auto-negotiation if needed.
+ */
+int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
+{
+ int ret;
+
+ if (!restart) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+
+ if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
+ restart = true;
+ }
+
+ if (restart)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_check_and_restart_aneg);
+
+/**
+ * __genphy_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ * @changed: whether autoneg is requested
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR.
+ */
+int __genphy_config_aneg(struct phy_device *phydev, bool changed)
+{
+ int err;
+
+ if (genphy_config_eee_advert(phydev))
+ changed = true;
+
+ err = genphy_setup_master_slave(phydev);
+ if (err < 0)
+ return err;
+ else if (err)
+ changed = true;
+
+ if (AUTONEG_ENABLE != phydev->autoneg)
+ return genphy_setup_forced(phydev);
+
+ err = genphy_config_advert(phydev);
+ if (err < 0) /* error */
+ return err;
+ else if (err)
+ changed = true;
+
+ return genphy_check_and_restart_aneg(phydev, changed);
+}
+EXPORT_SYMBOL(__genphy_config_aneg);
+
+/**
+ * genphy_c37_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR. This function is intended
+ * for use with Clause 37 1000Base-X mode.
+ */
+int genphy_c37_config_aneg(struct phy_device *phydev)
+{
+ int err, changed;
+
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return genphy_setup_forced(phydev);
+
+ err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
+ BMCR_SPEED1000);
+ if (err)
+ return err;
+
+ changed = genphy_c37_config_advert(phydev);
+ if (changed < 0) /* error */
+ return changed;
+
+ if (!changed) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ int ctl = phy_read(phydev, MII_BMCR);
+
+ if (ctl < 0)
+ return ctl;
+
+ if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
+ changed = 1; /* do restart aneg */
+ }
+
+ /* Only restart aneg if we are advertising something different
+ * than we were before.
+ */
+ if (changed > 0)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_config_aneg);
+
+/**
+ * genphy_aneg_done - return auto-negotiation status
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the status register and returns 0 either if
+ * auto-negotiation is incomplete, or if there was an error.
+ * Returns BMSR_ANEGCOMPLETE if auto-negotiation is done.
+ */
+int genphy_aneg_done(struct phy_device *phydev)
+{
+ int retval = phy_read(phydev, MII_BMSR);
+
+ return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
+}
+EXPORT_SYMBOL(genphy_aneg_done);
+
+/**
+ * genphy_update_link - update link status in @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Update the value in phydev->link to reflect the
+ * current link value. In order to do this, we need to read
+ * the status register twice, keeping the second value.
+ */
+int genphy_update_link(struct phy_device *phydev)
+{
+ int status = 0, bmcr;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ bmcr = phy_read(phydev, MII_BMCR);
+#endif
+ if (bmcr < 0)
+ return bmcr;
+
+ /* Autoneg is being started, therefore disregard BMSR value and
+ * report link as down.
+ */
+ if (bmcr & BMCR_ANRESTART)
+ goto done;
+
+ /* The link state is latched low so that momentary link
+ * drops can be detected. Do not double-read the status
+ * in polling mode to detect such short link drops except
+ * the link was already down.
+ */
+ if (!phy_polling_mode(phydev) || !phydev->link) {
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+ else if (status & BMSR_LSTATUS)
+ goto done;
+ }
+
+ /* Read link and autonegotiation status */
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+done:
+ phydev->link = status & BMSR_LSTATUS ? 1 : 0;
+ phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0;
+
+ /* Consider the case that autoneg was started and "aneg complete"
+ * bit has been reset, but "link up" bit not yet.
+ */
+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
+ phydev->link = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_update_link);
+
+int genphy_read_lpa(struct phy_device *phydev)
+{
+ int lpa, lpagb;
+
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ if (!phydev->autoneg_complete) {
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ 0);
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
+ return 0;
+ }
+
+ if (phydev->is_gigabit_capable) {
+ lpagb = phy_read(phydev, MII_STAT1000);
+ if (lpagb < 0)
+ return lpagb;
+
+ if (lpagb & LPA_1000MSFAIL) {
+ int adv = phy_read(phydev, MII_CTRL1000);
+
+ if (adv < 0)
+ return adv;
+
+ if (adv & CTL1000_ENABLE_MASTER)
+ phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
+ else
+ phydev_err(phydev, "Master/Slave resolution failed\n");
+ return -ENOLINK;
+ }
+
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ lpagb);
+ }
+
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
+ } else {
+ linkmode_zero(phydev->lp_advertising);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_lpa);
+
+/**
+ * genphy_read_status_fixed - read the link parameters for !aneg mode
+ * @phydev: target phy_device struct
+ *
+ * Read the current duplex and speed state for a PHY operating with
+ * autonegotiation disabled.
+ */
+int genphy_read_status_fixed(struct phy_device *phydev)
+{
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ int bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ int bmcr = phy_read(phydev, MII_BMCR);
+#endif
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (bmcr & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status_fixed);
+
+/**
+ * genphy_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. Start by checking the gigabit possibilities,
+ * then move on to 10/100.
+ */
+int genphy_read_status(struct phy_device *phydev)
+{
+ int err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ err = genphy_read_master_slave(phydev);
+ if (err < 0)
+ return err;
+
+ err = genphy_read_lpa(phydev);
+ if (err < 0)
+ return err;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ err = genphy_read_status_fixed(phydev);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status);
+
+/**
+ * genphy_c37_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. This function is for Clause 37 1000Base-X mode.
+ */
+int genphy_c37_read_status(struct phy_device *phydev)
+{
+ int lpa, err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->lp_advertising, lpa & LPA_LPACK);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XPAUSE);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->lp_advertising,
+ lpa & LPA_1000XPAUSE_ASYM);
+
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ int bmcr = phy_read(phydev, MII_BMCR);
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_read_status);
+
+/**
+ * genphy_soft_reset - software reset the PHY via BMCR_RESET bit
+ * @phydev: target phy_device struct
+ *
+ * Description: Perform a software PHY reset using the standard
+ * BMCR_RESET bit and poll for the reset bit to be cleared.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_soft_reset(struct phy_device *phydev)
+{
+ u16 res = BMCR_RESET;
+ int ret;
+
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ res |= BMCR_ANRESTART;
+
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res);
+ if (ret < 0)
+ return ret;
+
+ /* Clause 22 states that setting bit BMCR_RESET sets control registers
+ * to their default value. Therefore the POWER DOWN bit is supposed to
+ * be cleared after soft reset.
+ */
+ phydev->suspended = 0;
+
+ ret = phy_poll_reset(phydev);
+ if (ret)
+ return ret;
+
+ /* BMCR may be reset to defaults */
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ ret = genphy_setup_forced(phydev);
+
+ return ret;
+}
+EXPORT_SYMBOL(genphy_soft_reset);
+
+/**
+ * genphy_read_abilities - read PHY abilities from Clause 22 registers
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the PHY's abilities and populates
+ * phydev->supported accordingly.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_read_abilities(struct phy_device *phydev)
+{
+ int val;
+
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phydev->supported);
+
+ val = phy_read(phydev, MII_BMSR);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
+ val & BMSR_ANEGCAPABLE);
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
+ val & BMSR_100FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
+ val & BMSR_100HALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
+ val & BMSR_10FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
+ val & BMSR_10HALF);
+
+ if (val & BMSR_ESTATEN) {
+ val = phy_read(phydev, MII_ESTATUS);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_TFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported, val & ESTATUS_1000_THALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_XFULL);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_abilities);
+
+/* This is used for the phy device which doesn't support the MMD extended
+ * register access, but it does have side effect when we are trying to access
+ * the MMD register via indirect method.
+ */
+int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_read_mmd_unsupported);
+
+int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
+ u16 regnum, u16 val)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_write_mmd_unsupported);
+
+int genphy_suspend(struct phy_device *phydev)
+{
+ return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_suspend);
+
+int genphy_resume(struct phy_device *phydev)
+{
+ return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_resume);
+
+int genphy_loopback(struct phy_device *phydev, bool enable)
+{
+ return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
+ enable ? BMCR_LOOPBACK : 0);
+}
+EXPORT_SYMBOL(genphy_loopback);
+
+/**
+ * phy_remove_link_mode - Remove a supported link mode
+ * @phydev: phy_device structure to remove link mode from
+ * @link_mode: Link mode to be removed
+ *
+ * Description: Some MACs don't support all link modes which the PHY
+ * does. e.g. a 1G MAC often does not support 1000Half. Add a helper
+ * to remove a link mode.
+ */
+void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode)
+{
+ linkmode_clear_bit(link_mode, phydev->supported);
+ phy_advertise_supported(phydev);
+}
+EXPORT_SYMBOL(phy_remove_link_mode);
+
+static void phy_copy_pause_bits(unsigned long *dst, unsigned long *src)
+{
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, src));
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, src));
+}
+
+/**
+ * phy_advertise_supported - Advertise all supported modes
+ * @phydev: target phy_device struct
+ *
+ * Description: Called to advertise all supported modes, doesn't touch
+ * pause mode advertising.
+ */
+void phy_advertise_supported(struct phy_device *phydev)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(new);
+
+ linkmode_copy(new, phydev->supported);
+ phy_copy_pause_bits(new, phydev->advertising);
+ linkmode_copy(phydev->advertising, new);
+}
+EXPORT_SYMBOL(phy_advertise_supported);
+
+/**
+ * phy_support_sym_pause - Enable support of symmetrical pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports symmetrical
+ * Pause, but not asym pause.
+ */
+void phy_support_sym_pause(struct phy_device *phydev)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_sym_pause);
+
+/**
+ * phy_support_asym_pause - Enable support of asym pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports Asym Pause.
+ */
+void phy_support_asym_pause(struct phy_device *phydev)
+{
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_asym_pause);
+
+/**
+ * phy_set_sym_pause - Configure symmetric Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ * @autoneg: Auto neg should be used
+ *
+ * Description: Configure advertised Pause support depending on if
+ * receiver pause and pause auto neg is supported. Generally called
+ * from the set_pauseparam .ndo.
+ */
+void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
+ bool autoneg)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
+
+ if (rx && tx && autoneg)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+
+ linkmode_copy(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_set_sym_pause);
+
+/**
+ * phy_set_asym_pause - Configure Pause and Asym Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ *
+ * Description: Configure advertised Pause support depending on if
+ * transmit and receiver pause is supported. If there has been a
+ * change in adverting, trigger a new autoneg. Generally called from
+ * the set_pauseparam .ndo.
+ */
+void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(oldadv);
+
+ linkmode_copy(oldadv, phydev->advertising);
+ linkmode_set_pause(phydev->advertising, tx, rx);
+
+ if (!linkmode_equal(oldadv, phydev->advertising) &&
+ phydev->autoneg)
+ phy_start_aneg(phydev);
+}
+EXPORT_SYMBOL(phy_set_asym_pause);
+
+/**
+ * phy_validate_pause - Test if the PHY/MAC support the pause configuration
+ * @phydev: phy_device struct
+ * @pp: requested pause configuration
+ *
+ * Description: Test if the PHY/MAC combination supports the Pause
+ * configuration the user is requesting. Returns True if it is
+ * supported, false otherwise.
+ */
+bool phy_validate_pause(struct phy_device *phydev,
+ struct ethtool_pauseparam *pp)
+{
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported) && pp->rx_pause)
+ return false;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported) &&
+ pp->rx_pause != pp->tx_pause)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL(phy_validate_pause);
+
+/**
+ * phy_get_pause - resolve negotiated pause modes
+ * @phydev: phy_device struct
+ * @tx_pause: pointer to bool to indicate whether transmit pause should be
+ * enabled.
+ * @rx_pause: pointer to bool to indicate whether receive pause should be
+ * enabled.
+ *
+ * Resolve and return the flow control modes according to the negotiation
+ * result. This includes checking that we are operating in full duplex mode.
+ * See linkmode_resolve_pause() for further details.
+ */
+void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause)
+{
+ if (phydev->duplex != DUPLEX_FULL) {
+ *tx_pause = false;
+ *rx_pause = false;
+ return;
+ }
+
+ return linkmode_resolve_pause(phydev->advertising,
+ phydev->lp_advertising,
+ tx_pause, rx_pause);
+}
+EXPORT_SYMBOL(phy_get_pause);
+
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ s32 int_delay;
+ int ret;
+
+ ret = device_property_read_u32(dev, name, &int_delay);
+ if (ret)
+ return ret;
+
+ return int_delay;
+}
+#else
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ return -EINVAL;
+}
+#endif
+
+/**
+ * phy_get_delay_index - returns the index of the internal delay
+ * @phydev: phy_device struct
+ * @dev: pointer to the devices device struct
+ * @delay_values: array of delays the PHY supports
+ * @size: the size of the delay array
+ * @is_rx: boolean to indicate to get the rx internal delay
+ *
+ * Returns the index within the array of internal delay passed in.
+ * If the device property is not present then the interface type is checked
+ * if the interface defines use of internal delay then a 1 is returned otherwise
+ * a 0 is returned.
+ * The array must be in ascending order. If PHY does not have an ascending order
+ * array then size = 0 and the value of the delay property is returned.
+ * Return -EINVAL if the delay is invalid or cannot be found.
+ */
+s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev,
+ const int *delay_values, int size, bool is_rx)
+{
+ s32 delay;
+ int i;
+
+ if (is_rx) {
+ delay = phy_get_int_delay_property(dev, "rx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ return 1;
+ else
+ return 0;
+ }
+
+ } else {
+ delay = phy_get_int_delay_property(dev, "tx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ return 1;
+ else
+ return 0;
+ }
+ }
+
+ if (delay < 0)
+ return delay;
+
+ if (delay && size == 0)
+ return delay;
+
+ if (delay < delay_values[0] || delay > delay_values[size - 1]) {
+ phydev_err(phydev, "Delay %d is out of range\n", delay);
+ return -EINVAL;
+ }
+
+ if (delay == delay_values[0])
+ return 0;
+
+ for (i = 1; i < size; i++) {
+ if (delay == delay_values[i])
+ return i;
+
+ /* Find an approximate index by looking up the table */
+ if (delay > delay_values[i - 1] &&
+ delay < delay_values[i]) {
+ if (delay - delay_values[i - 1] <
+ delay_values[i] - delay)
+ return i - 1;
+ else
+ return i;
+ }
+ }
+
+ phydev_err(phydev, "error finding internal delay index for %d\n",
+ delay);
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(phy_get_internal_delay);
+
+static bool phy_drv_supports_irq(struct phy_driver *phydrv)
+{
+ return phydrv->config_intr && phydrv->ack_interrupt;
+}
+
+/**
+ * phy_probe - probe and init a PHY device
+ * @dev: device to probe and init
+ *
+ * Description: Take care of setting up the phy_device structure,
+ * set the state to READY (the driver's init function should
+ * set it to STARTING if needed).
+ */
+static int phy_probe(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ int err = 0;
+
+ phydev->drv = phydrv;
+
+ /* Disable the interrupt if the PHY doesn't support it
+ * but the interrupt is still a valid one
+ */
+ if (!phy_drv_supports_irq(phydrv) && phy_interrupt_is_valid(phydev))
+ phydev->irq = PHY_POLL;
+
+ if (phydrv->flags & PHY_IS_INTERNAL)
+ phydev->is_internal = true;
+
+ mutex_lock(&phydev->lock);
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (phydev->drv->probe) {
+ err = phydev->drv->probe(phydev);
+ if (err)
+ goto out;
+ }
+
+ /* Start out supporting everything. Eventually,
+ * a controller will attach, and may modify one
+ * or both of these values
+ */
+ if (phydrv->features) {
+ linkmode_copy(phydev->supported, phydrv->features);
+ } else if (phydrv->get_features) {
+ err = phydrv->get_features(phydev);
+ } else if (phydev->is_c45) {
+ err = genphy_c45_pma_read_abilities(phydev);
+ } else {
+ err = genphy_read_abilities(phydev);
+ }
+
+ if (err)
+ goto out;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported))
+ phydev->autoneg = 0;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+
+ of_set_phy_supported(phydev);
+ phy_advertise_supported(phydev);
+
+ /* Get the EEE modes we want to prohibit. We will ask
+ * the PHY stop advertising these mode later on
+ */
+ of_set_phy_eee_broken(phydev);
+
+ /* The Pause Frame bits indicate that the PHY can support passing
+ * pause frames. During autonegotiation, the PHYs will determine if
+ * they should allow pause frames to pass. The MAC driver should then
+ * use that result to determine whether to enable flow control via
+ * pause frames.
+ *
+ * Normally, PHY drivers should not set the Pause bits, and instead
+ * allow phylib to do that. However, there may be some situations
+ * (e.g. hardware erratum) where the driver wants to set only one
+ * of these bits.
+ */
+ if (!test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported) &&
+ !test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported)) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported);
+ }
+
+ /* Set the state to READY by default */
+ phydev->state = PHY_READY;
+
+out:
+ /* Assert the reset signal */
+ if (err)
+ phy_device_reset(phydev, 1);
+
+ mutex_unlock(&phydev->lock);
+
+ return err;
+}
+
+static int phy_remove(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ cancel_delayed_work_sync(&phydev->state_queue);
+
+ mutex_lock(&phydev->lock);
+ phydev->state = PHY_DOWN;
+ mutex_unlock(&phydev->lock);
+
+ sfp_bus_del_upstream(phydev->sfp_bus);
+ phydev->sfp_bus = NULL;
+
+ if (phydev->drv && phydev->drv->remove)
+ phydev->drv->remove(phydev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ phydev->drv = NULL;
+
+ return 0;
+}
+
+/**
+ * phy_driver_register - register a phy_driver with the PHY layer
+ * @new_driver: new phy_driver to register
+ * @owner: module owning this PHY
+ */
+int phy_driver_register(struct phy_driver *new_driver, struct module *owner)
+{
+ int retval;
+
+ /* Either the features are hard coded, or dynamically
+ * determined. It cannot be both.
+ */
+ if (WARN_ON(new_driver->features && new_driver->get_features)) {
+ pr_err("%s: features and get_features must not both be set\n",
+ new_driver->name);
+ return -EINVAL;
+ }
+
+ new_driver->mdiodrv.flags |= MDIO_DEVICE_IS_PHY;
+ new_driver->mdiodrv.driver.name = new_driver->name;
+ new_driver->mdiodrv.driver.bus = &mdio_bus_type;
+ new_driver->mdiodrv.driver.probe = phy_probe;
+ new_driver->mdiodrv.driver.remove = phy_remove;
+ new_driver->mdiodrv.driver.owner = owner;
+ new_driver->mdiodrv.driver.probe_type = PROBE_FORCE_SYNCHRONOUS;
+
+ retval = driver_register(&new_driver->mdiodrv.driver);
+ if (retval) {
+ pr_err("%s: Error %d in registering driver\n",
+ new_driver->name, retval);
+
+ return retval;
+ }
+
+ pr_debug("%s: Registered new driver\n", new_driver->name);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_driver_register);
+
+int phy_drivers_register(struct phy_driver *new_driver, int n,
+ struct module *owner)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < n; i++) {
+ ret = phy_driver_register(new_driver + i, owner);
+ if (ret) {
+ while (i-- > 0)
+ phy_driver_unregister(new_driver + i);
+ break;
+ }
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_drivers_register);
+
+void phy_driver_unregister(struct phy_driver *drv)
+{
+ driver_unregister(&drv->mdiodrv.driver);
+}
+EXPORT_SYMBOL(phy_driver_unregister);
+
+void phy_drivers_unregister(struct phy_driver *drv, int n)
+{
+ int i;
+
+ for (i = 0; i < n; i++)
+ phy_driver_unregister(drv + i);
+}
+EXPORT_SYMBOL(phy_drivers_unregister);
+
+static struct phy_driver genphy_driver = {
+ .phy_id = 0xffffffff,
+ .phy_id_mask = 0xffffffff,
+ .name = "Generic PHY",
+ .get_features = genphy_read_abilities,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .set_loopback = genphy_loopback,
+};
+
+static const struct ethtool_phy_ops phy_ethtool_phy_ops = {
+ .get_sset_count = phy_ethtool_get_sset_count,
+ .get_strings = phy_ethtool_get_strings,
+ .get_stats = phy_ethtool_get_stats,
+ .start_cable_test = phy_start_cable_test,
+ .start_cable_test_tdr = phy_start_cable_test_tdr,
+};
+
+static int __init phy_init(void)
+{
+ int rc;
+
+ rc = mdio_bus_init();
+ if (rc)
+ return rc;
+
+ ethtool_set_ethtool_phy_ops(&phy_ethtool_phy_ops);
+ features_init();
+
+ rc = phy_driver_register(&genphy_c45_driver, THIS_MODULE);
+ if (rc)
+ goto err_c45;
+
+ rc = phy_driver_register(&genphy_driver, THIS_MODULE);
+ if (rc) {
+ phy_driver_unregister(&genphy_c45_driver);
+err_c45:
+ mdio_bus_exit();
+ }
+
+ return rc;
+}
+
+static void __exit phy_exit(void)
+{
+ phy_driver_unregister(&genphy_c45_driver);
+ phy_driver_unregister(&genphy_driver);
+ mdio_bus_exit();
+ ethtool_set_ethtool_phy_ops(NULL);
+}
+
+subsys_initcall(phy_init);
+module_exit(phy_exit);
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
new file mode 100755
index 0000000..c7da7a4
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/net/zvnet/zvnet_dev.c
@@ -0,0 +1,1372 @@
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include <linux/module.h>
+#include <linux/etherdevice.h>
+#include <net/sock.h>
+#include <uapi/linux/sched/types.h>
+#include "zvnet_dev.h"
+#include "ram_config.h"
+#include <net/netfilter/nf_conntrack.h>
+#include <net/SI/fast_common.h>
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define USE_ZVNET_PACKET
+
+#define WATCHDOG_TIMEO (5*HZ)
+#define XMIT_RETRANS_TIMES 3
+#define ZVNET_SKB_PAD 128
+#define ZVNET_TMP_BUFF_LEN 2048
+#define ZVNET_FREE_BUFF_NUM 256
+#define ZVNET_XMIT_BUFF_NUM 64
+#define ZVNET_XMIT_MAX_QUEUE_NUM 2048
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+//AP´«µÝ¸øCAPµÄÊý¾Ý°üÐÅÏ¢£¬¸ÃÄÚÈÝдÈë¹²ÏíDDR
+struct T_zvnet_rpmsg
+{
+ void *buff;//skb_headÖ¸Õ룬ÓÃÓÚÊÍ·Åʱ´«µÝ¸øºË¼ä£¬ÒÔ±ã¿ìËÙÊÍ·Å;
+ void *head;//ºË¼äÄÜʹÓõĵØÖ·±ß½ç£¬²»ÄÜÔ½½ç£¬·ñÔòÄÚ´æÒç³öÒì³£;ÎïÀíµØÖ·
+ unsigned short data_off;//ºË¼ä´«µÝÀ´µÄÊý¾Ý°üÊ×µØÖ·£¬Ö¸ÏòMACÖ¡Í·;ÎïÀíµØÖ·
+ unsigned short len;//Êý¾Ý°üÓÐЧ³¤¶È£¬Ò»°ãΪMACÖ¡³¤¶È
+ unsigned short end_off;//end offset
+ unsigned char dev;//cid 1->8
+ unsigned char flag;//0ÆÕͨ°ü£¬1¶þ´Îת·¢°ü£¬2¶þ´Îfastת·¢°ü
+};
+struct T_zvnet_pkt_stats
+{
+ unsigned int pkt;
+ unsigned int len;
+};
+//AP´«µÝ¸øCAPµÄCTÐÅÏ¢£¬¸ÃÄÚÈÝдÈë¹²ÏíDDR
+struct T_zvnet_rpmsg_ctstat
+{
+ void *cap_nfct;
+ unsigned char in;
+ unsigned char out;
+ unsigned short flag;
+ struct T_zvnet_pkt_stats pkt[2];
+};
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+struct zvnet_device zvnet_dev[DDR_ZVNET_DEV_MAX];
+int *vir_addr_ap = NULL;
+struct sk_buff_head g_zvnet_skb_queue;
+struct zvnet_channel g_zvnet_chn_info;
+
+#ifdef USE_ZVNET_PACKET
+void *g_zvnet_free_buff[ZVNET_FREE_BUFF_NUM];
+int g_zvnet_free_num;
+spinlock_t g_zvnet_free_lock;
+struct semaphore g_zvnet_free_sem;
+struct semaphore g_zvnet_xmit_sem;
+struct sk_buff_head g_zvnet_skb_xmit_queue;
+
+unsigned int g_wrap_packet_size = 1000;
+module_param(g_wrap_packet_size, int, 0644);
+unsigned int g_wrap_num = 10;
+module_param(g_wrap_num, int, 0644);
+unsigned int g_wrap_timeout = 10;
+module_param(g_wrap_timeout, int, 0644);
+unsigned int g_trace_limit = 0;
+module_param(g_trace_limit, int, 0644);
+#endif
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+extern int (*fast_from_driver)(struct sk_buff *skb, struct net_device* dev);
+extern void v7_dma_map_area(const void *, size_t, int);
+extern void *get_ct_for_ap(struct sk_buff *skb);
+extern void put_ct_for_ap(void *ct);
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+static int zvnet_open(struct net_device *net);
+static int zvnet_close(struct net_device *net);
+static netdev_tx_t zvnet_xmit(struct sk_buff *skb, struct net_device *net);
+static void zvnet_tx_timeout(struct net_device *net, unsigned int txqueue);
+static struct net_device_stats *zvnet_get_stats(struct net_device *net);
+static void v2xnet_init_netdev(struct net_device *net);
+static void zvnet_skb_return (struct zvnet *dev, struct sk_buff *skb);
+static void zvnet_bh (unsigned long param);
+static struct zvnet *v2xnet_dev_init(struct net_device *net, struct zvnet_device *zvnetdev);
+
+static int zvnet_channel_write(struct zvnet_channel *chninfo, void *buf, unsigned int len);
+static int zvnet_channel_read(struct zvnet_channel *chninfo, void *buf, unsigned int len);
+static int zvnet_channel_clear(struct zvnet_channel *chninfo);
+static int zvnet_read_header(struct zvnet_channel *chninfo, struct zvp_header *phzvp);
+static struct sk_buff *zvnet_direct_read_skb(struct zvnet_channel *chninfo);
+static struct sk_buff *zvnet_read_skb(struct zvnet_channel *chninfo, unsigned int tlen, struct zvnet *dev);
+static int zvnet_receive_thread(void *argv);
+static int rpmsgCreateChannel_v2xnet (T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size);
+static int zvnet_createIcpChannel(T_RpMsg_CoreID core_id, T_RpMsg_ChID channel_id, unsigned int channel_size);
+static int zvnet_channel_create(struct zvnet_device *zvnetdev);
+
+/*******************************************************************************
+ * Local function implementations *
+ ******************************************************************************/
+
+unsigned long virt_to_phys_ap(unsigned long virt)
+{
+ if(virt >= (unsigned long)vir_addr_ap && virt <= ((unsigned long)vir_addr_ap+DDR_BASE_LEN_AP))
+ return DDR_BASE_ADDR_AP + (virt - (unsigned long)vir_addr_ap);
+ return NULL;
+}
+
+unsigned long phys_to_virt_ap(unsigned long phys)
+{
+ if(phys >= DDR_BASE_ADDR_AP && phys <= (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP))
+ return (unsigned long)vir_addr_ap + (phys - DDR_BASE_ADDR_AP);
+ return NULL;
+}
+
+/* Started by AICoder, pid:2fa080381bb2e3d14fbc0aa44091291a60d78e35 */
+void check_skb_test(struct sk_buff *skb)
+{
+ if (skb && vir_addr_ap) {
+ struct sk_buff *tmp_skb;
+ if ((skb->capHead && (virt_to_phys_ap(skb->head) == NULL))
+ || ((skb->capHead == NULL) && virt_to_phys_ap(skb->head))) {
+ dump_stack();
+ panic("capHead err");
+ }
+ skb_queue_walk(&g_zvnet_skb_queue, tmp_skb) {
+ if (tmp_skb == skb) {
+ dump_stack();
+ panic("dup free");
+ }
+ }
+ }
+}
+/* Ended by AICoder, pid:2fa080381bb2e3d14fbc0aa44091291a60d78e35 */
+
+/* Started by AICoder, pid:z5702yf8bad07ad1448a083e806dc31250b2418f */
+void zvnet_dump_packet(unsigned char * data, int len, int limit_len)
+{
+ int i = 0;
+ unsigned char *p = data;
+ for(i = 0; i < len && i < limit_len; i+=16)
+ {
+ printk("0x%04x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",i,
+ p[0],p[1],p[2],p[3],p[4],p[5],p[6],p[7],
+ p[8],p[9],p[10],p[11],p[12],p[13],p[14],p[15]);
+ p += 16;
+ }
+}
+/* Ended by AICoder, pid:z5702yf8bad07ad1448a083e806dc31250b2418f */
+
+int zvnet_get_index_by_netdev(struct net_device *net)
+{
+ int i;
+
+ for (i = 0; i < DDR_ZVNET_DEV_MAX; i++) {
+ if(zvnet_dev[i].net == net)
+ return i;
+ }
+ return -1;
+}
+#ifdef USE_ZVNET_PACKET
+void write_free_apbuf_packet(void)
+{
+ int ret,size;
+ unsigned long flags;
+ void *buf[ZVNET_FREE_BUFF_NUM];
+
+ spin_lock_irqsave(&g_zvnet_free_lock, flags);
+ if(g_zvnet_free_num == 0){
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+ return;
+ }
+ size = (g_zvnet_free_num << 2);
+ memcpy(buf, g_zvnet_free_buff, size);
+ g_zvnet_free_num = 0;
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+ {
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = RPMSG_WRITE_INT|RPMSG_WRITE_IRQLOCK};
+ if((size >> 2) > ZVNET_FREE_BUFF_NUM)
+ panic("free packet err");
+ msg.buf = &buf;
+ msg.len = size;
+ zv_info("tofree size=%d", size);
+ ret = zvnetWrite(&msg);
+ if(ret < 0)
+ panic("err, ret:%d!!!!!!", ret);
+ }
+}
+#endif
+//½«CAP²à´«µÝÀ´µÄcapbufÖ¸ÕëдÈëDDR£¬ÒÔICP·½Ê½Í¨ÖªCAP²à
+void write_free_apbuf(void *head)
+{
+#ifdef USE_ZVNET_PACKET
+ unsigned long flags;
+
+ zv_info("g_zvnet_free_num=%d skb=0x%x", g_zvnet_free_num, head);
+ spin_lock_irqsave(&g_zvnet_free_lock, flags);
+ g_zvnet_free_buff[g_zvnet_free_num] = head;
+ g_zvnet_free_num++;
+ if(g_zvnet_free_num == ZVNET_FREE_BUFF_NUM){
+ int size;
+ void *buf[ZVNET_FREE_BUFF_NUM];
+
+ size = (g_zvnet_free_num << 2);
+ memcpy(buf, g_zvnet_free_buff, size);
+ g_zvnet_free_num = 0;
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+ if((size >> 2) > ZVNET_FREE_BUFF_NUM)
+ panic("free packet err");
+ {
+ int ret;
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = RPMSG_WRITE_INT|RPMSG_WRITE_IRQLOCK};
+ msg.buf = &buf;
+ msg.len = size;
+ if(printk_ratelimit())
+ zv_warn("tofree quick size=%d", size);
+ ret = zvnetWrite(&msg);
+ if(ret < 0)
+ panic("err, ret:%d!!!!!!", ret);
+ }
+ return;
+ }
+ if(g_zvnet_free_num > g_wrap_num)
+ up(&g_zvnet_free_sem);
+ if(g_zvnet_free_num > ZVNET_FREE_BUFF_NUM)
+ panic("free_buff err");
+ spin_unlock_irqrestore(&g_zvnet_free_lock, flags);
+#else
+ int ret = 0;
+ long buf = (long)head;
+
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = RPMSG_WRITE_INT,
+ .buf = NULL,
+ .len = 4 };
+ msg.buf = &buf;
+ zv_info("tofree 0x%x", head);
+ ret = zvnetWrite(&msg);
+ if(ret < 0)
+ panic("err, ret:%d!!!!!!", ret);
+#endif
+}
+
+struct sk_buff *skb_build_apbuf(struct T_zvnet_rpmsg *pbuf_temp)
+{
+ struct skb_shared_info *shinfo;
+ struct sk_buff *skb;
+ zv_info("build 0x%x 0x%x %d %d", pbuf_temp->buff, pbuf_temp->head, pbuf_temp->data_off, pbuf_temp->len);
+ if((unsigned long )pbuf_temp->head < DDR_BASE_ADDR_AP || (unsigned long )pbuf_temp->head > (DDR_BASE_ADDR_AP + DDR_BASE_LEN_AP)){
+ zv_err("err 0x%x 0x%x %d %d", pbuf_temp->buff, pbuf_temp->head, pbuf_temp->data_off, pbuf_temp->len);
+ panic("addr is not APBUF mem!!!");
+ return NULL;
+ }
+ skb = kmem_cache_alloc(skbuff_head_cache, GFP_ATOMIC);
+ if (!skb)
+ {
+ write_free_apbuf(pbuf_temp->buff);
+ zv_err("alloc fail");
+ return NULL;
+ }
+ memset(skb, 0, offsetof(struct sk_buff, tail));
+
+ //ÅжÏÊÇ·ñÊÇapbuff
+
+ if(pbuf_temp->dev < 0 || pbuf_temp->dev >= DDR_ZVNET_DEV_MAX)
+ panic("dev index error!!!");
+ skb->head = phys_to_virt_ap((unsigned long )pbuf_temp->head);
+ skb->data = skb->head + pbuf_temp->data_off;
+ skb->capHead = pbuf_temp->buff;
+ //ÐèÒª¿¼ÂÇcacheÐжÔÆë
+ skb->truesize = SKB_TRUESIZE(skb->data - skb->head + pbuf_temp->len);//°´µÀÀíβ²¿»¹ÓпÉÓõÄÄÚ´æ¿Õ¼ä£¬ÔÝʱδ¿¼ÂÇ;SKB_DATA_ALIGN
+
+ refcount_set(&skb->users, 1);
+ skb_reset_tail_pointer(skb);
+ skb->tail += pbuf_temp->len;
+ skb->len = pbuf_temp->len;
+ skb->end = skb->head + pbuf_temp->end_off;
+ skb->mac_header = (typeof(skb->mac_header))~0U;
+ skb->transport_header = (typeof(skb->transport_header))~0U;
+ skb->dev = zvnet_dev[pbuf_temp->dev].net;
+ if(skb->len == 0 || skb->len > 2000)
+ panic("len ERR!!!!!!!!!!\n");
+ v7_dma_map_area(skb->head, sizeof(struct skb_shared_info) + pbuf_temp->end_off, DMA_FROM_DEVICE);
+ if(IFF_NOARP & skb->dev->flags)
+ memcpy(skb->data, skb->dev->dev_addr, 6);
+ atomic_set(&skb_shinfo(skb)->dataref, 1);
+ /* make sure we initialize shinfo sequentially */
+ skb_reset_network_header(skb);
+ skb_set_kcov_handle(skb, kcov_common_handle());
+ if(unlikely(g_trace_limit > 0)){
+ printk("-%s-dump_packet-start-%d\n", skb->dev->name, skb->len);
+ zvnet_dump_packet(skb->data, skb->len, g_trace_limit);
+ printk("-%s-dump_packet-end-\n", skb->dev->name);
+ }
+ return skb;
+}
+
+int eth_change_mtu(struct net_device *dev, int new_mtu)
+{
+ netdev_warn(dev, "%s is deprecated!\n", __func__);
+ dev->mtu = new_mtu;
+ return 0;
+}
+
+/* Started by AICoder, pid:b001dtf2551fd53146790a57201be3321cf0a682 */
+static void skb_debug_test(struct sk_buff *skb)
+{
+ int i;
+ int vcount = skb->len / 10;
+ int rcount = skb->len % 10;
+ char tmp[64] = {0};
+ char strbuf[64] = {0};
+ const unsigned char *data = skb->data;
+
+ zv_info("\n");
+ for (i = 0; i < vcount; i++) {
+ zv_info("%d---%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", i,
+ data[0 + 10 * i], data[1 + 10 * i], data[2 + 10 * i], data[3 + 10 * i],
+ data[4 + 10 * i], data[5 + 10 * i], data[6 + 10 * i], data[7 + 10 * i],
+ data[8 + 10 * i], data[9 + 10 * i]);
+ }
+ if (vcount > 0) {
+ memset(tmp, 0, sizeof(tmp));
+ sprintf(strbuf, "%d---", vcount);
+ char *p = strbuf + strlen(strbuf);
+
+ for (i = 0; i < rcount; i++) {
+ sprintf(p, "%02x,", data[10 * vcount + i]);
+ p += strlen(p);
+ }
+ *(p - 1) = '\0'; // ÒƳý×îºóÒ»¸ö¶ººÅ
+ zv_info("%s ", strbuf);
+ }
+ zv_info("\n");
+}
+/* Ended by AICoder, pid:b001dtf2551fd53146790a57201be3321cf0a682 */
+
+static int zvnet_open(struct net_device *net)
+{
+ struct zvnet *dev = netdev_priv(net);
+
+ if(net->flags & IFF_UP) {
+ zv_dbg("%s has been opened!", dev->net->name);
+ return -EBUSY;
+ }
+ netif_start_queue (net);
+
+ return 0;
+}
+
+static int zvnet_close(struct net_device *net)
+{
+ struct zvnet *dev = netdev_priv(net);
+
+ zv_info("%s", dev->net->name);
+ netif_stop_queue(net);
+ tasklet_kill (&dev->bh);
+
+ return 0;
+}
+#ifdef USE_ZVNET_PACKET
+static void zvnet_xmit_packet(void)
+{
+ int i,j,k,ret,num;
+ unsigned long flags;
+ unsigned long flags1;
+ struct sk_buff *skb, *tmp;
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 20,
+ .flag = RPMSG_WRITE_INT};
+ static struct T_zvnet_rpmsg buff[ZVNET_XMIT_MAX_QUEUE_NUM+1];
+
+ spin_lock_irqsave(&g_zvnet_skb_xmit_queue.lock, flags);
+ if (skb_queue_empty(&g_zvnet_skb_xmit_queue)) {
+ spin_unlock_irqrestore(&g_zvnet_skb_xmit_queue.lock, flags);
+ return;
+ }
+ i = 0;
+ skb_queue_walk_safe(&g_zvnet_skb_xmit_queue, skb, tmp) {
+ //buff[i].buff = skb;
+ buff[i].data_off = skb->data - skb->head;
+ //buff[i].head = virt_to_phys(skb->head);
+ buff[i].len = skb->len;
+ buff[i].end_off = skb->end - skb->head;
+ buff[i].dev = zvnet_get_index_by_netdev(skb->dev);
+ if(skb->capHead){
+ buff[i].buff = skb->capHead;
+#ifdef CONFIG_FASTNAT_MODULE
+ if(skb->isFastnat){
+ buff[i].head = get_ct_for_ap(skb);
+ buff[i].flag = 2;
+ }else
+#endif
+ {
+ buff[i].head = NULL;
+ buff[i].flag = 1;
+ }
+ __skb_unlink(skb, &g_zvnet_skb_xmit_queue);
+ kfree_skb(skb);
+ }else{
+ buff[i].buff = skb;
+ buff[i].head = virt_to_phys(skb->head);
+ buff[i].flag = 0;
+ }
+ i++;
+ zv_info("xmit skb=0x%x i=%d", skb, i);
+ if(i > ZVNET_XMIT_MAX_QUEUE_NUM){
+ panic("qlen:%d!", i);
+ break;
+ }
+ }
+ spin_lock_irqsave(&g_zvnet_skb_queue.lock, flags1);
+ skb_queue_splice_tail_init(&g_zvnet_skb_xmit_queue, &g_zvnet_skb_queue);
+ spin_unlock_irqrestore(&g_zvnet_skb_queue.lock, flags1);
+ spin_unlock_irqrestore(&g_zvnet_skb_xmit_queue.lock, flags);
+ zv_info("g_zvnet_skb_queue.qlen=%d i=%d", g_zvnet_skb_queue.qlen, i);
+ for(j = 0; j < i; j = j + ZVNET_XMIT_BUFF_NUM){
+ if(i <= (j + ZVNET_XMIT_BUFF_NUM)){
+ msg.buf = (void *)&buff[j];
+ msg.len = sizeof(struct T_zvnet_rpmsg)*(i-j);/*±¾´ÎÄÜÈ¡¹â*/
+ ret = zvnetWrite(&msg);
+ }else{
+ msg.buf = (void *)&buff[j];
+ msg.len = sizeof(struct T_zvnet_rpmsg)*ZVNET_XMIT_BUFF_NUM;
+ ret = zvnetWrite(&msg);
+ }
+ zv_info("xmit write ret=%d size=%d i=%d j=%d", ret, msg.len, i, j);
+ if(ret < 0) {
+ if(printk_ratelimit())
+ zv_warn("zvnet_channel_write ret=%d fail.",ret);
+ num = msg.len / sizeof(struct T_zvnet_rpmsg);
+ for(k = j; k < j+num; k++){
+ if(buff[k].flag == 0){
+ skb = (struct sk_buff *)buff[k].buff;
+ skb_unlink(skb, &g_zvnet_skb_queue);
+ skb->isToap = 0;
+ kfree_skb(skb);
+ }else{
+ if(buff[k].head)
+ put_ct_for_ap(buff[k].head);
+ write_free_apbuf(buff[k].buff);
+ }
+ }
+ }
+ }
+}
+#endif
+static netdev_tx_t zvnet_xmit(struct sk_buff *skb, struct net_device *net)
+{
+#ifdef USE_ZVNET_PACKET
+ struct sk_buff *data = NULL;
+
+ //zv_info("g_zvnet_skb_xmit_queue.qlen=%d", g_zvnet_skb_xmit_queue.qlen);
+ if(g_zvnet_skb_xmit_queue.qlen >= ZVNET_XMIT_MAX_QUEUE_NUM){
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ zv_err("write err, qlen:%d!", g_zvnet_skb_xmit_queue.qlen);
+ kfree_skb(skb);
+ return NET_XMIT_SUCCESS;
+ }
+
+ if(unlikely(skb->next//|| skb->capHead || skb_headroom(skb) < NET_SKB_PAD
+ || skb->fclone || skb->cloned || (skb_shinfo(skb)->nr_frags) || skb->sk || (skb->indev == NULL)
+ || (skb_shinfo(skb)->tx_flags & SKBTX_DEV_ZEROCOPY) || (skb_has_frag_list(skb)))){
+ int ret_len = skb->len;
+
+ data = dev_alloc_skb(ret_len + NET_IP_ALIGN);
+ if (unlikely(!data)) {
+ zv_err("dev_alloc_skb fail,len %d",ret_len);
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ kfree_skb(skb);
+ return NET_XMIT_SUCCESS;
+ }
+ skb_put(data,ret_len);
+ skb_reserve(data, NET_IP_ALIGN);
+ memcpy(data->data, skb->data, ret_len);
+ zv_info("ap=0x%x next=0x%x clone=%d nr_frags=%d tx_flags=%d frag_list=0x%x", skb->capHead, skb->next, skb->cloned, (skb_shinfo(skb)->nr_frags), skb_shinfo(skb)->tx_flags, skb_shinfo(skb)->frag_list);
+ kfree_skb(skb);
+ }else{
+ data = skb;
+ }
+ data->dev = net;
+ data->isToap = 1;
+ v7_dma_map_area(data->head, data->end - data->head + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
+ skb_queue_tail(&g_zvnet_skb_xmit_queue, data);
+ if(data->len < g_wrap_packet_size || g_zvnet_skb_xmit_queue.qlen > g_wrap_num)
+ up(&g_zvnet_xmit_sem);
+ net->stats.tx_packets++;
+ net->stats.tx_bytes += skb->len;
+#else
+ struct zvnet *dev = netdev_priv(net);
+ struct zvnet_device *zvnetdev = (struct zvnet_device *)dev->dev_priv;
+ int ret = 0;
+ struct zvp_header hzvp;
+
+ if (!skb) {
+ zv_err("err: skb == 0!");
+ }
+#if 0
+ if (skb->len > ZVNET_TMP_BUFF_LEN) {
+ zv_err("err: skb->len(%d)>%d!", skb->len, ZVNET_TMP_BUFF_LEN);
+ }
+
+send_header:
+ ret = zvnet_channel_write(&(zvnetdev->chn_info), skb->data, skb->len);
+
+ if((ret < 0) && (zvnetdev->retran_times < XMIT_RETRANS_TIMES)) {
+ zvnetdev->retran_times ++;
+ zv_warn("The retran_times is %d.",zvnetdev->retran_times);
+ goto send_header;
+ }
+
+ if (ret >= 0) {
+ net->stats.tx_packets++;
+ net->stats.tx_bytes += skb->len;
+ } else {
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ zv_err("write err, ret:%d!", ret);
+ }
+
+exit:
+ kfree_skb(skb);
+#else
+ struct T_zvnet_rpmsg buff = {0};
+ struct sk_buff *data = NULL;
+ if(unlikely(skb_headroom(skb) < NET_SKB_PAD || skb->capHead || skb->next
+ || skb->fclone || skb->cloned || (skb_shinfo(skb)->nr_frags)
+ || (skb_shinfo(skb)->tx_flags & SKBTX_DEV_ZEROCOPY) || (skb_has_frag_list(skb)))){
+ int ret_len = skb->len;
+
+ data = dev_alloc_skb(ret_len + NET_IP_ALIGN);
+ if (unlikely(!data)) {
+ zv_err("dev_alloc_skb fail,len %d",ret_len);
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ kfree_skb(skb);
+ return NET_XMIT_SUCCESS;
+ }
+ skb_put(data,ret_len);
+ skb_reserve(data, NET_IP_ALIGN);
+ memcpy(data->data, skb->data, ret_len);
+ data->isToap = 1;
+ buff.buff = data;
+ buff.data_off = data->data - data->head;
+ buff.head = virt_to_phys(data->head);
+ buff.len = ret_len;
+ buff.end_off = data->end - data->head;
+ buff.dev = zvnet_get_index_by_netdev(net);
+ zv_info("alloc 0x%x 0x%x %d %d", buff.buff, buff.head, buff.data_off, buff.len);
+ zv_info("ap=0x%x next=0x%x clone=%d nr_frags=%d tx_flags=%d frag_list=0x%x", skb->capHead, skb->next, skb->cloned, (skb_shinfo(skb)->nr_frags), skb_shinfo(skb)->tx_flags, skb_shinfo(skb)->frag_list);
+ v7_dma_map_area(data->head, buff.end_off + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
+ }else{
+ skb->isToap = 1;
+ buff.buff = skb;
+ buff.data_off = skb->data - skb->head;
+ buff.head = virt_to_phys(skb->head);
+ buff.len = skb->len;
+ buff.end_off = skb->end - skb->head;
+ buff.dev = zvnet_get_index_by_netdev(net);
+ zv_info("transfer 0x%x %d 0x%x %d", buff.buff, buff.head, buff.data_off, buff.len);
+ v7_dma_map_area(skb->head, buff.end_off + sizeof(struct skb_shared_info), DMA_TO_DEVICE);
+ }
+send_header:
+ ret = zvnet_channel_write(&g_zvnet_chn_info, &buff, sizeof(struct T_zvnet_rpmsg));
+
+ if((ret < 0) && (zvnetdev->retran_times < XMIT_RETRANS_TIMES)) {
+ zvnetdev->retran_times ++;
+ zv_warn("The retran_times is %d.",zvnetdev->retran_times);
+ goto send_header;
+ }
+
+ if (ret >= 0) {
+ net->stats.tx_packets++;
+ net->stats.tx_bytes += skb->len;
+ if(data){
+ kfree_skb(skb);
+ skb_queue_tail(&g_zvnet_skb_queue, data);
+ }else
+ skb_queue_tail(&g_zvnet_skb_queue, skb);
+ zvnetdev->retran_times = 0;
+ } else {
+ net->stats.tx_errors++;
+ net->stats.tx_dropped++;
+ zv_err("write err, ret:%d!", ret);
+ if(data){
+ data->isToap = 0;
+ kfree_skb(data);
+ }
+ else
+ skb->isToap = 0;
+ kfree_skb(skb);
+ }
+#endif
+#endif
+ return NET_XMIT_SUCCESS;
+}
+
+/* Called by the kernel when transmit times out */
+static void zvnet_tx_timeout(struct net_device *net, unsigned int txqueue)
+{
+ zv_warn("sent timeout!");
+ net->stats.tx_errors++;
+ netif_wake_queue(net);
+}
+
+static struct net_device_stats *zvnet_get_stats(struct net_device *net)
+{
+ return &net->stats;
+}
+
+const struct net_device_ops zvnet_netdev_ops = {
+ .ndo_open = zvnet_open,
+ .ndo_stop = zvnet_close,
+ .ndo_start_xmit = zvnet_xmit,
+ .ndo_tx_timeout = zvnet_tx_timeout,
+ .ndo_get_stats = zvnet_get_stats,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = eth_mac_addr,
+};
+
+static void v2xnet_init_netdev(struct net_device *net)
+{
+ u8 node_id [ETH_ALEN];
+
+ random_ether_addr(node_id);
+ memcpy (net->dev_addr, node_id, sizeof node_id);
+
+ net->netdev_ops = &zvnet_netdev_ops;
+ net->watchdog_timeo = WATCHDOG_TIMEO;
+ net->flags |= IFF_NOARP;
+}
+
+static void zvnet_skb_return (struct zvnet *dev, struct sk_buff *skb)
+{
+ int status;
+
+ //zv_info("enter...");
+
+ //skb->protocol = eth_type_trans(skb, dev->net);
+
+ status = netif_rx (skb);
+ if (status == NET_RX_SUCCESS) {
+ dev->net->stats.rx_packets++;
+ dev->net->stats.rx_bytes += skb->len;
+ } else {
+ dev->net->stats.rx_errors++;
+ zv_err("netif_rx status %d.", status);
+ }
+}
+
+static void zvnet_bh (unsigned long param)
+{
+ struct zvnet *dev = (struct zvnet *)param;
+ struct sk_buff *skb;
+
+ while((skb = skb_dequeue(&dev->rxq)) != NULL) {
+ if (skb->len)
+ zvnet_skb_return(dev, skb);
+ else {
+ dev->net->stats.rx_errors++;
+ dev_kfree_skb (skb);
+ zv_err("drop!!!ddrnet_bh skb len == 0.");
+ }
+ }
+}
+
+static struct zvnet *v2xnet_dev_init(struct net_device *net, struct zvnet_device *zvnetdev)
+{
+ struct zvnet *dev = NULL;
+
+ dev = netdev_priv(net);
+ if(!dev) {
+ zv_err("dev is null.\n");
+ return NULL;
+ }
+
+ dev->net = net;
+ dev->bh.func = zvnet_bh;
+ dev->bh.data = (unsigned long) dev;
+
+ skb_queue_head_init (&dev->rxq);
+
+ dev->dev_priv = zvnetdev;
+
+ return dev;
+}
+
+/*·µ»ØÖµ´óÓÚµÈÓÚ0£¬±íʾдͨµÀ³É¹¦£»Ð¡ÓÚ0±íʾдͨµÀʧ°Ü*/
+static int zvnet_channel_write(struct zvnet_channel *chninfo, void *buf, unsigned int len)
+{
+ T_RpMsg_Msg msg;
+
+ if(NULL == buf) {
+ return -EINVAL;
+ }
+ memset(&msg, 0, sizeof(msg));
+ msg.coreID = chninfo->core_id;
+ msg.chID = chninfo->channel_id;
+ msg.flag |= RPMSG_WRITE_INT; //| RPMSG_WRITE_IRQLOCK;
+ msg.buf = buf;
+ msg.len = len;
+
+ return zvnetWrite(&msg);
+}
+
+/*·µ»ØÖµ´óÓÚ0£¬±íʾ¶ÁȡͨµÀ³É¹¦£»Ð¡ÓÚµÈÓÚ0±íʾͨµÀÊý¾ÝΪ¿Õ»òʧ°Ü*/
+static int zvnet_channel_read(struct zvnet_channel *chninfo, void *buf, unsigned int len)
+{
+ T_RpMsg_Msg msg;
+ int ret = 0;
+
+ if(NULL == buf) {
+ return -EINVAL;
+ }
+
+ memset(&msg, 0, sizeof(msg));
+ msg.coreID = chninfo->core_id;
+ msg.chID = chninfo->channel_id;
+ msg.buf = buf;
+ msg.len = len;
+
+ ret = zvnetRead(&msg);
+ if (ret <= 0) {
+ zv_err("rpm read err=%d!",ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int zvnet_channel_clear(struct zvnet_channel *chninfo)
+{
+ char *tbuf = NULL;
+ unsigned int tlen = chninfo->channel_size/2;
+ int ret = 0;
+
+ tbuf = (char *)kzalloc(tlen,GFP_ATOMIC);
+ if(IS_ERR(tbuf)) {
+ zv_err("kzalloc fail! %d byte.", tlen);
+ return -ENOMEM;
+ }
+ ret = zvnet_channel_read(chninfo, tbuf, tlen);
+ if(ret < 0) {
+ zv_err("zvnet_channel_read fail!");
+ ret = 0;
+ }
+ kfree(tbuf);
+ zv_err("Drop channel data. %d byte.",ret);
+
+ return ret;
+}
+
+static int zvnet_read_header(struct zvnet_channel *chninfo, struct zvp_header *phzvp)
+{
+ return zvnet_channel_read(chninfo, phzvp, sizeof(struct zvp_header));
+}
+
+static struct sk_buff *zvnet_read_skb(struct zvnet_channel *chninfo, unsigned int tlen, struct zvnet *dev)
+{
+ struct sk_buff *skb;
+
+ if(NULL == chninfo || 0 >= tlen || NULL == dev) {
+ return NULL;
+ }
+ skb = dev_alloc_skb(tlen);
+ if (unlikely(!skb)) {
+ zv_err("netdev_alloc_skb fail,len %d",tlen);
+ return NULL;
+ }
+ skb_put(skb,tlen);
+
+ if(zvnet_channel_read(chninfo, (void *)skb->data, tlen) != tlen) {
+ zv_err("zvnet_channel_read fail.\n");
+ kfree_skb(skb);
+ return NULL;
+ }
+
+ zv_info("%s dev receive packet %d byte.",dev->net->name, tlen);
+
+ skb->dev = dev->net;
+
+ return skb;
+}
+
+static struct sk_buff *zvnet_direct_read_skb(struct zvnet_channel *chninfo)
+{
+ struct sk_buff *skb;
+#if 0
+/* Started by AICoder, pid:sd1cfsbc2eu87c41445f09652039f525fa147687 */
+int ret_len = 0;
+struct sk_buff *skb;
+
+ret_len = zvnet_channel_read(chninfo, NULL, 0); // »ñÈ¡ÐèÒª¶ÁÈ¡µÄÊý¾Ý³¤¶È
+if(ret_len <= 0) {
+ zv_err("zvnet_channel_read fail.\n");
+ return NULL;
+}
+
+skb = dev_alloc_skb(ret_len + ZVNET_SKB_PAD);
+if (unlikely(!skb)) {
+ zv_err("netdev_alloc_skb fail,len %d",ret_len);
+ return NULL;
+}
+
+ret_len = zvnet_channel_read(chninfo, skb->data, ret_len); // ¶ÁÈ¡Êý¾Ýµ½skb->data
+if(ret_len <= 0) {
+ kfree_skb(skb); // Èç¹û¶Áȡʧ°Ü£¬ÊÍ·ÅÒÑ·ÖÅäµÄskb
+ zv_err("zvnet_channel_read fail.\n");
+ return NULL;
+}
+
+skb_put(skb,ret_len);
+skb_reserve(skb, ZVNET_SKB_PAD);
+/* Ended by AICoder, pid:sd1cfsbc2eu87c41445f09652039f525fa147687 */
+#else
+ struct T_zvnet_rpmsg buff = {0};
+ int ret_len = 0;
+ ret_len = zvnet_channel_read(chninfo, (void *)&buff, sizeof(struct T_zvnet_rpmsg));
+
+ if(ret_len <= 0) {
+ zv_err("rpm read err=%d", ret_len);
+ msleep(1000);
+ return NULL;
+ }
+ if(ret_len != sizeof(struct T_zvnet_rpmsg)) {
+ panic("err, ret:%d!!!!!!", ret_len);
+ }
+ skb = skb_build_apbuf(&buff);
+ if (unlikely(!skb)) {
+ zv_err("netdev_alloc_skb fail,len %d",ret_len);
+ return NULL;
+ }
+#endif
+ //skb->dev = dev->net;
+ return skb;
+}
+
+static int zvnet_receive_thread(void *argv)
+{
+ //struct zvnet_device *zvnetdev = (struct zvnet_device *)argv;
+ //struct zvnet_channel *chninfo = NULL;
+ struct zvnet *dev = NULL;
+ int index,ret_len,i,num;
+ unsigned long flags;
+ struct sk_buff *skb = NULL;
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 20,
+ .flag = 0};
+ struct T_zvnet_rpmsg buff[ZVNET_XMIT_BUFF_NUM];
+ //struct zvp_header hzvp;
+/*
+ if(IS_ERR(zvnetdev)) {
+ zv_err("The receive thread create fail!");
+ return -EINVAL;
+ }
+ chninfo = &zvnetdev->chn_info;
+ dev = zvnetdev->dev;
+*/
+ while(1) {
+/*
+ if(unlikely(!(zvnetdev->net->flags & IFF_UP))) {
+ msleep(1000);
+ continue;
+ }
+*/
+ //memset(&hzvp, 0, sizeof(hzvp));
+#ifdef USE_ZVNET_PACKET
+ //ret_len = zvnet_channel_read(&g_zvnet_chn_info, (void *)buff, sizeof(struct T_zvnet_rpmsg)*ZVNET_XMIT_BUFF_NUM);
+ msg.buf = (void *)(buff); // Êý¾Ý
+ msg.len = sizeof(struct T_zvnet_rpmsg)*ZVNET_XMIT_BUFF_NUM;// ¶ÁÈ¡µÄ³¤¶È
+ ret_len = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+ zv_info("zvnetRead ret=%d", ret_len);
+ if(ret_len <= 0) {
+ zv_err("rpm read err=%d", ret_len);
+ msleep(1000);
+ continue;
+ }
+ if((ret_len % sizeof(struct T_zvnet_rpmsg)) != 0) {
+ panic("err, ret:%d!!!!!!", ret_len);
+ }
+ num = ret_len / sizeof(struct T_zvnet_rpmsg);
+ for(i = 0; i < num; i++){
+ skb = skb_build_apbuf(&buff[i]);
+ if (unlikely(!skb)) {
+ zv_err("skb_build_apbuf fail,len=%d i=%d",ret_len,i);
+ continue;
+ }
+ if(unlikely(!(skb->dev->flags & IFF_UP))) {
+ if(printk_ratelimit())
+ zv_err("drop!!!%s is down.", skb->dev->name);
+ dev_kfree_skb (skb);
+ continue;
+ }
+ skb->protocol = eth_type_trans(skb, skb->dev);
+ if (fast_from_driver && fast_from_driver(skb, skb->dev))
+ {
+ continue;
+ }
+ index = zvnet_get_index_by_netdev(skb->dev);
+ if(index < 0)
+ panic("");
+ dev = zvnet_dev[index].dev;
+ spin_lock_irqsave(&dev->rxq.lock, flags);
+ __skb_queue_tail(&dev->rxq, skb);
+ spin_unlock_irqrestore(&dev->rxq.lock, flags);
+ tasklet_schedule(&dev->bh);
+ }
+#else
+ if(0 != (skb = zvnet_direct_read_skb(&g_zvnet_chn_info))) {
+ //skb_debug_test(skb);
+ if(unlikely(!(skb->dev->flags & IFF_UP))) {
+ zv_err("drop!!!%s is down.", skb->dev->name);
+ dev_kfree_skb (skb);
+ continue;
+ }
+ skb->protocol = eth_type_trans(skb, skb->dev);
+#if 1
+ if (fast_from_driver && fast_from_driver(skb, skb->dev))
+ {
+ continue;
+ }
+#endif
+ index = zvnet_get_index_by_netdev(skb->dev);
+ if(index < 0)
+ panic("");
+ dev = zvnet_dev[index].dev;
+ spin_lock_irqsave(&dev->rxq.lock, flags);
+ __skb_queue_tail(&dev->rxq, skb);
+ spin_unlock_irqrestore(&dev->rxq.lock, flags);
+ tasklet_schedule(&dev->bh);
+ }
+ else {
+ zv_err("zvnet_read_header fail.");
+ msleep(1000);
+ }
+#endif
+ }
+
+ zv_err("The receive thread exit!");
+ return 0;
+}
+
+static int rpmsgCreateChannel_v2xnet (T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
+{
+ return zvnetCreateChannel (dstCoreID, chID, size);
+}
+
+static int zvnet_createIcpChannel(T_RpMsg_CoreID core_id, T_RpMsg_ChID channel_id, unsigned int channel_size)
+{
+ int retval;
+
+ retval = rpmsgCreateChannel_v2xnet (core_id, channel_id, channel_size);
+ if(retval != RPMSG_SUCCESS && retval != RPMSG_CHANNEL_ALREADY_EXIST)
+ goto out;
+
+ return retval;
+
+out:
+ zv_err("could not create channel.");
+ return retval;
+}
+/*
+static int zvnet_channel_create(struct zvnet_device *zvnetdev)
+{
+ struct task_struct *th = NULL;
+ int retval = 0;
+ struct zvnet_channel *chninfo = NULL;
+
+ if (IS_ERR(zvnetdev)) {
+ return -EINVAL;
+ }
+ chninfo = &(zvnetdev->chn_info);
+ retval = zvnet_createIcpChannel(chninfo->core_id, chninfo->channel_id, chninfo->channel_size);
+ if(retval < 0) {
+ zv_err("Create IcpChannel fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_receive_thread, (void *)zvnetdev, "zvnet-recv%d", chninfo->channel_id);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start receive thread.");
+ return PTR_ERR(th);
+ }
+ chninfo->rcv_thread = th;
+
+ return 0;
+}
+*/
+static int zvnet_release_thread(void * nouse)
+{
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 29,
+ .flag = 0};
+ void *buff[ZVNET_FREE_BUFF_NUM];
+ int i,num,retval;
+ struct sk_buff *skb;
+ struct sched_param param = { .sched_priority = 1 };
+ param.sched_priority = 37;
+ sched_setscheduler(current, SCHED_FIFO, ¶m);
+
+ while(1) {
+ zv_info("g_zvnet_skb_queue.qlen=%d", g_zvnet_skb_queue.qlen);
+#ifdef USE_ZVNET_PACKET
+ msg.buf = (unsigned char *)(buff); // Êý¾Ý
+ msg.len = 4*ZVNET_FREE_BUFF_NUM;// ¶ÁÈ¡µÄ³¤¶È
+ retval = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+ zv_info("free read ret=%d", retval);
+ if (retval <= 0) {
+ zv_err("rpm read err=%d", retval);
+ msleep(1000);
+ continue;
+ }
+ if((retval%4) != 0) {
+ panic("err, ret:%d!!!!!!", retval);
+ }
+ num = retval>>2;
+ for(i = 0; i < num; i++){
+ skb = (struct sk_buff *)buff[i];
+ zv_info("free 0x%x", skb);
+ if (skb == NULL || skb->next == NULL || skb->prev == NULL) {
+ panic("rpm read=%d i=%d NULL", retval, i);
+ continue;
+ }
+ skb_unlink(skb, &g_zvnet_skb_queue);
+ if(skb->isToap != 1)
+ panic("");
+ skb->isToap = 0;
+ kfree_skb(skb);
+ }
+#else
+ void *buff;
+ msg.coreID = CORE_PS0;
+ msg.chID = 29;
+ msg.buf = (unsigned char *)(&buff); // Êý¾Ý
+ msg.len = 4;// ¶ÁÈ¡µÄ³¤¶È
+ //msg.flag |= RPMSG_READ_POLL;
+
+ retval = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+ if (retval <= 0) {
+ zv_err("no msg or threand exited");
+ msleep(1000);
+ continue;
+ }
+ if(retval != 4) {
+ panic("err, ret:%d!!!!!!", retval);
+ }
+ zv_info("free 0x%x", buff);
+ skb = (struct sk_buff *)buff;
+ skb_unlink(skb, &g_zvnet_skb_queue);
+ if(skb->isToap != 1)
+ panic("");
+ skb->isToap = 0;
+ kfree_skb(skb);
+#endif
+ }
+ zv_err("The realse thread exit!");
+ return 0;
+}
+#ifdef USE_ZVNET_PACKET
+static int zvnet_xmit_warp_thread(void * nouse)
+{
+ while(1) {
+ down_timeout(&g_zvnet_xmit_sem, msecs_to_jiffies(g_wrap_timeout));
+ zvnet_xmit_packet();
+ }
+ zv_err("The xmit warp thread exit!");
+ return 0;
+}
+
+static int zvnet_free_warp_thread(void * nouse)
+{
+ while(1) {
+ down_timeout(&g_zvnet_free_sem, msecs_to_jiffies(g_wrap_timeout));
+ write_free_apbuf_packet();
+ }
+ zv_err("The free warp thread exit!");
+ return 0;
+}
+#endif
+
+static int zvnet_update_thread(void * nouse)
+{
+ T_RpMsg_Msg msg = { .coreID = CORE_PS0,
+ .chID = 21,
+ .flag = 0};
+ int ret_len = 0;
+ struct nf_conn *ct;
+ fast_entry_t *entry;
+ struct net_device *in;
+ struct net_device *out;
+
+ while(1) {
+ struct T_zvnet_rpmsg_ctstat buff = {0};
+ msg.buf = (void *)(&buff); // Êý¾Ý
+ msg.len = sizeof(struct T_zvnet_rpmsg_ctstat);// ¶ÁÈ¡µÄ³¤¶È
+ ret_len = zvnetRead(&msg); // ¶ÁÈ¡»·ÐζÓÁÐÖÐÒ»¸ö½Úµã£¬
+
+ if(ret_len <= 0) {
+ zv_err("rpm read err=%d", ret_len);
+ msleep(1000);
+ continue;
+ }
+ if(ret_len != sizeof(struct T_zvnet_rpmsg_ctstat)) {
+ panic("err, ret:%d!!!!!!", ret_len);
+ }
+ ct = (struct nf_conn *)buff.cap_nfct;
+ WARN_ON(atomic_read(&ct->ct_general.use) == 0);
+ if(buff.flag){
+ if(!(buff.pkt[0].pkt || buff.pkt[0].len || buff.pkt[1].pkt || buff.pkt[1].len))
+ continue;
+ BUG_ON(buff.in <= 0 || buff.out <= 0);
+ in = zvnet_dev[buff.in-1].net;
+ out = zvnet_dev[buff.out-1].net;
+ if(buff.pkt[0].pkt && buff.pkt[0].len){
+ zv_info("nf_update %x %s %s %d %d", buff.cap_nfct, ct->indev[0]->name, ct->outdev[0]->name, buff.in, buff.out);
+ in->stats.rx_packets += buff.pkt[0].pkt;
+ in->stats.rx_bytes += buff.pkt[0].len;
+ out->stats.tx_packets += buff.pkt[0].pkt;
+ out->stats.tx_bytes += buff.pkt[0].len;
+ }
+ if(buff.pkt[1].pkt && buff.pkt[1].len){
+ zv_info("nf_update %x %s %s %d %d", buff.cap_nfct, ct->indev[1]->name, ct->outdev[1]->name, buff.out, buff.in);
+ out->stats.rx_packets += buff.pkt[1].pkt;
+ out->stats.rx_bytes += buff.pkt[1].len;
+ in->stats.tx_packets += buff.pkt[1].pkt;
+ in->stats.tx_bytes += buff.pkt[1].len;
+ }
+ spin_lock_bh(&fast_fw_spinlock);
+ /*¸üÐÂÁ´½Ó³¬Ê±*/
+ if (IPPROTO_TCP == nf_ct_protonum(ct))
+ {
+ ct->timeout = jiffies + tcp_timeouts[ct->proto.tcp.state];
+ }else if (IPPROTO_UDP == nf_ct_protonum(ct)){
+ /*udp*/
+ if (test_bit(IPS_SEEN_REPLY_BIT, &ct->status)){
+ ct->timeout = jiffies + fast_udp_timeout_stream;
+ }else{
+ ct->timeout = jiffies + fast_udp_timeout;
+ }
+ }
+ entry = (fast_entry_t *)ct->fast_entry;
+ if(entry){
+ WARN_ON(entry->ct != ct);
+ mod_timer(&entry->timeout, ct->timeout);
+ }
+ ct->packet_info[IP_CT_DIR_ORIGINAL].bytes += buff.pkt[IP_CT_DIR_ORIGINAL].len;
+ ct->packet_info[IP_CT_DIR_ORIGINAL].packets += buff.pkt[IP_CT_DIR_ORIGINAL].pkt;
+ ct->packet_info[IP_CT_DIR_REPLY].bytes += buff.pkt[IP_CT_DIR_REPLY].len;
+ ct->packet_info[IP_CT_DIR_REPLY].packets += buff.pkt[IP_CT_DIR_REPLY].pkt;
+ if(ct->indev[0] && is_vlan_dev(ct->indev[0])){
+ struct net_device *tmp = vlan_dev_real_dev(ct->indev[0]);
+ struct vlan_pcpu_stats *stats = this_cpu_ptr(vlan_dev_priv(ct->indev[0])->vlan_pcpu_stats);
+
+ if(tmp == in){
+/* Started by AICoder, pid:tbef0151bf4135d1479d0a5d108c870bc756e858 */
+u64_stats_update_begin(&stats->syncp);
+stats->rx_packets += buff.pkt[0].pkt;
+stats->rx_bytes += buff.pkt[0].len;
+stats->tx_packets += buff.pkt[1].pkt;
+stats->tx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:tbef0151bf4135d1479d0a5d108c870bc756e858 */
+ }else if(tmp == out){
+/* Started by AICoder, pid:y34f7id6bcs049f144f10bb8a05c9703b196635b */
+u64_stats_update_begin(&stats->syncp);
+stats->tx_packets += buff.pkt[0].pkt;
+stats->tx_bytes += buff.pkt[0].len;
+stats->rx_packets += buff.pkt[1].pkt;
+stats->rx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:y34f7id6bcs049f144f10bb8a05c9703b196635b */
+ }else
+ zv_err("nf_update0 %s->%s!=%s-%s", in->name, out->name, tmp->name, ct->indev[0]->name);
+ }
+ if(ct->indev[1] && is_vlan_dev(ct->indev[1])){
+ struct net_device *tmp = vlan_dev_real_dev(ct->indev[1]);
+ struct vlan_pcpu_stats *stats = this_cpu_ptr(vlan_dev_priv(ct->indev[1])->vlan_pcpu_stats);
+
+ if(tmp == in){
+/* Started by AICoder, pid:8bef0t51bfu135d1479d0a5d108c870bc756e858 */
+u64_stats_update_begin(&stats->syncp);
+stats->rx_packets += buff.pkt[0].pkt;
+stats->rx_bytes += buff.pkt[0].len;
+stats->tx_packets += buff.pkt[1].pkt;
+stats->tx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:8bef0t51bfu135d1479d0a5d108c870bc756e858 */
+ }else if(tmp == out){
+/* Started by AICoder, pid:934f7zd6bcl049f144f10bb8a05c9703b196635b */
+u64_stats_update_begin(&stats->syncp);
+stats->tx_packets += buff.pkt[0].pkt;
+stats->tx_bytes += buff.pkt[0].len;
+stats->rx_packets += buff.pkt[1].pkt;
+stats->rx_bytes += buff.pkt[1].len;
+u64_stats_update_end(&stats->syncp);
+/* Ended by AICoder, pid:934f7zd6bcl049f144f10bb8a05c9703b196635b */
+ }else
+ zv_err("nf_update1 %s->%s!=%s-%s", in->name, out->name, tmp->name, ct->indev[1]->name);
+ }
+ spin_unlock_bh(&fast_fw_spinlock);
+ zv_info("nf_update %x %d %d %d %d", buff.cap_nfct, buff.pkt[0].pkt, buff.pkt[0].len, buff.pkt[1].pkt, buff.pkt[1].len);
+ }else{
+ zv_info("nf_put %x", buff.cap_nfct);
+ WRITE_ONCE(ct->timeout, nfct_time_stamp);
+ nf_conntrack_put(buff.cap_nfct);
+ }
+ }
+ zv_err("The update thread exit!");
+ return 0;
+}
+
+/*******************************************************************************
+ * Global function implementations *
+ ******************************************************************************/
+static int __init zvnet_init(void)
+{
+ int i;
+ int err = -ENOMEM;
+ struct zvnet *dev = NULL;
+ struct net_device *net = NULL;
+ struct zvnet_device *zvnetdev = NULL;
+
+#ifdef USE_ZVNET_PACKET
+ skb_queue_head_init(&g_zvnet_skb_xmit_queue);
+ spin_lock_init(&g_zvnet_free_lock);
+ sema_init(&g_zvnet_free_sem, 0);
+ sema_init(&g_zvnet_xmit_sem, 0);
+#endif
+ skb_queue_head_init(&g_zvnet_skb_queue);
+ g_zvnet_chn_info.core_id = CORE_PS0;
+ g_zvnet_chn_info.channel_id = ICP_CHN_ZVNET1;
+ g_zvnet_chn_info.channel_size = ICP_CHANNEL_SIZE;
+ for (i = 0; i < DDR_ZVNET_DEV_MAX; i++) {
+ zvnetdev = &zvnet_dev[i];
+ memset(zvnetdev, 0, sizeof(struct zvnet_device));
+ net = alloc_etherdev(sizeof(struct zvnet));
+ if (!net) {
+ zv_err("could not allocate device.\n");
+ return err;
+ }
+
+ //net->needed_headroom += ZVNET_SKB_PAD;//NET_SKB_PAD;
+ sprintf(net->name, "%s%d", ZVNET_IFNAME_PREFIX, i);
+ dev = v2xnet_dev_init(net, zvnetdev);
+ v2xnet_init_netdev(net);
+ if(0 == i || i > 8){
+ net->flags = (net->flags & (~IFF_NOARP));
+ }
+ err = register_netdev(net);
+ if (err) {
+ zv_err("register_netdev error:%d :%d\n",err,i);
+ return err;
+ }
+ zvnetdev->dev = dev;
+ zvnetdev->net = net;
+/*
+ zvnetdev->chn_info.core_id = CAP_ID;
+ zvnetdev->chn_info.channel_id = ICP_CHN_ZVNET1 + i;//zvnet_collect[i];
+ zvnetdev->chn_info.channel_size = ICP_CHANNEL_SIZE;
+ err = zvnet_channel_create(zvnetdev);
+ if(0 != err) {
+ zv_err("zvnet_channel_create error:%d :%d\n",err,i);
+ goto out_unregister_netdev;
+ }
+*/
+ }
+ {
+ struct task_struct *th = NULL;
+ int retval = 0;
+ retval = zvnet_createIcpChannel(CORE_PS0, 21, 64);
+ if(retval < 0) {
+ zv_err("Create IcpChannel channel_21 fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_update_thread, 0, "zvnet-update%d", 21);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start update thread.");
+ return PTR_ERR(th);
+ }
+ retval = zvnet_createIcpChannel(CORE_PS0, 20, ICP_CHANNEL_SIZE);
+ if(retval < 0) {
+ zv_err("Create IcpChannel channel_20 fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_receive_thread, 0, "zvnet-recv%d", 20);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start receive thread.");
+ return PTR_ERR(th);
+ }
+ g_zvnet_chn_info.rcv_thread = th;
+
+ retval = zvnet_createIcpChannel(CORE_PS0, 29, ICP_CHANNEL_SIZE);
+ if(retval < 0) {
+ zv_err("Create IcpChannel channel_29 fail.");
+ return retval;
+ }
+
+ th = kthread_run(zvnet_release_thread, 0, "zvnet-free%d", 29);
+ if (IS_ERR(th)) {
+ zv_err("Unable to start release thread.");
+ return PTR_ERR(th);
+ }
+#ifdef USE_ZVNET_PACKET
+ th = kthread_run(zvnet_xmit_warp_thread, 0, "zvnet-xmit-wrap");
+ if (IS_ERR(th)) {
+ zv_err("Unable to start xmit_warp thread.");
+ return PTR_ERR(th);
+ }
+
+ th = kthread_run(zvnet_free_warp_thread, 0, "zvnet-free-wrap");
+ if (IS_ERR(th)) {
+ zv_err("Unable to start free_warp thread.");
+ return PTR_ERR(th);
+ }
+#endif
+ vir_addr_ap = ioremap_cache(DDR_BASE_ADDR_AP, DDR_BASE_LEN_AP);
+ zv_warn("vir_addr_ap vir=0x%x phy=0x%x len=0x%x", vir_addr_ap, DDR_BASE_ADDR_AP, DDR_BASE_LEN_AP);
+ if(vir_addr_ap == NULL)
+ {
+ zv_err("AP mmap failed.\n");
+ return -1;
+ }
+
+ }
+ zv_dbg("success.\n");
+ return 0;
+
+}
+
+static void __exit zvnet_exit(void)
+{
+ int i;
+ struct net_device *net;
+
+ for (i = 0; i < DDR_ZVNET_DEV_MAX; i++) {
+ net = zvnet_dev[i].net;
+ unregister_netdev(net);
+ free_netdev(net);
+ zvnet_dev[i].net = NULL;
+ }
+ zv_warn("success.\n");
+}
+
+late_initcall(zvnet_init);
+module_exit(zvnet_exit);
+
+MODULE_AUTHOR("ZXIC");
+MODULE_DESCRIPTION("ZXIC CAP LAN NET DEVICE");
+MODULE_LICENSE("GPL");
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
new file mode 100755
index 0000000..3c5ba58
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/soc/sc/rpmsg/zx29_icp.c
@@ -0,0 +1,492 @@
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/syscore_ops.h>
+#include <linux/gpio.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/sc/common.h>
+#include <linux/soc/sc/spinlock.h>
+#include <pub_debug_info.h>
+
+#include "icp_dev.h"
+#include "zx29_icp.h"
+#include "icp_rpmsg.h"
+
+static icp_callback_fn _icp_fn;
+static T_HalIcp_Reg *icp_ap2m0_reg;
+static T_HalIcp_Reg *icp_ap2ps_reg;
+
+static inline T_HalIcp_Reg *icp_get_reg(T_ZDrvRpMsg_ActorID actor_id)
+{
+ if (CORE_M0 == actor_id )
+ return icp_ap2m0_reg;
+ else if (CORE_PS0 == actor_id )
+ return icp_ap2ps_reg;
+ else
+ BUG();
+}
+
+/*******************************************************************************
+* Function: icp_set_int
+* Description: This function is used for generating icp interrupt to inform remote cpu;
+* Parameters:
+* Input:
+ actorID: id of remote cpu
+ chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+static int icp_set_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
+ return -EINVAL;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ icp_reg->control.low_word = (1<<chID);
+ else
+ icp_reg->control.high_word = (1<<(chID-32));
+
+ return 0;
+}
+
+/*******************************************************************************
+* Function: icp_clear_int
+* Description: This function is used for clear icp interrupt from remote cpu;
+* Parameters:
+* Input:
+ actorID: id of remote cpu
+ chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+static void icp_clear_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ icp_reg->clear.low_word = (1<<chID);
+ else
+ icp_reg->clear.high_word = (1<<(chID-32)) ;
+}
+
+/*******************************************************************************
+* Function: icp_get_int
+* Description: This function is used for get icp interrupt from remote cpu;
+* Parameters:
+* Input:
+* actorID: id of remote cpu
+* chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+T_HalIcp_Dword icp_get_int(T_ZDrvRpMsg_ActorID actorID)
+{
+ T_HalIcp_Dword IcpState;
+ T_HalIcp_Reg *icp_reg;
+
+ if (actorID >= CORE_MAXID)
+ {
+ IcpState.high_word = 0;
+ IcpState.low_word = 0;
+
+ return IcpState;
+ }
+
+ icp_reg = icp_get_reg(actorID);
+
+ IcpState.high_word = icp_reg->state.high_word;
+ IcpState.low_word = icp_reg->state.low_word;
+
+ return IcpState;
+}
+
+/*******************************************************************************
+* Function: icp_get_int_state
+* Description: This function is used for get the state of icp interruptting of remote cpu;
+* Parameters:
+* Input:
+ actorID: id of remote cpu
+ chID: id of channel
+* Output:None
+*
+* Returns:None
+*
+*
+* Others:
+********************************************************************************/
+static int icp_get_int_state(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ {
+ if(icp_reg->in_state.low_word & (0x1<<chID))
+ return true;
+ }
+ else
+ {
+ if(icp_reg->in_state.high_word & (0x1<<(chID-32)))
+ return true;
+ }
+
+ return false;
+}
+
+/*******************************************************************************
+* Function: icp_mask_int
+* Description: This function is used for Mask interrupt of channel;
+* Parameters:
+* Input:
+* Output:
+*
+* Returns: NONE
+*
+*
+* Others:
+********************************************************************************/
+static int icp_mask_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
+ return -EINVAL;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID<32)
+ icp_reg->mask.low_word |= (0x1<<chID);
+ else
+ icp_reg->mask.high_word |= (0x1<<(chID-32));
+
+ return 0;
+}
+
+/*******************************************************************************
+* Function: icp_unmask_int
+* Description: This function is used for unmask interrupt of channel;
+* Parameters:
+* Input:
+* Output:
+*
+* Returns:
+* NONE
+*
+*
+* Others:
+********************************************************************************/
+static int icp_unmask_int(T_ZDrvRpMsg_ActorID actorID, T_ZDrvRpMsg_ChID chID)
+{
+ T_HalIcp_Reg *icp_reg;
+
+ if ((actorID >= CORE_MAXID) || (chID >= CHANNEL_MAXID(actorID)))
+ return -EINVAL;
+
+ icp_reg = icp_get_reg(actorID);
+
+ if(chID < 32)
+ icp_reg->mask.low_word &= ~(0x1<<chID);
+ else
+ icp_reg->mask.high_word &= ~(0x1<<(chID-32));
+
+ return 0;
+}
+
+int icp_int_count = 0;
+#ifdef CONFIG_ZX29_WATCHDOG
+extern void zx_wdt_icp_wake(void);
+#endif
+irqreturn_t icp_isr(int irq, void *data)
+{
+ icp_msg _icp_msg;
+ T_HalIcp_Dword IcpState;
+ unsigned int i;
+
+ _icp_msg.src_id = (unsigned int)data;
+
+ IcpState = icp_get_int(_icp_msg.src_id);
+
+ for(i=0; i<CHANNEL_MAXID(_icp_msg.src_id); i++)
+ {
+ if((((i<32)&&((IcpState.low_word>>i) & 0x1))||((i>=32)&&((IcpState.high_word>>(i-32)) & 0x1)))) {
+ _icp_msg.event_id = i;
+ #ifdef CONFIG_ZX29_WATCHDOG
+ if((CORE_M0 == _icp_msg.src_id)&&(2 == i))
+ zx_wdt_icp_wake();
+ #endif
+ if(_icp_fn)
+ _icp_fn(&_icp_msg);
+
+ icp_clear_int(_icp_msg.src_id, i);
+ }
+ }
+
+ icp_int_count ++;
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * for loopback test
+ */
+void fake_icp_isr(T_RpMsg_CoreID src_core, T_RpMsg_CoreID dest_core, T_RpMsg_ChID ch)
+{
+ icp_msg _icp_msg;
+ unsigned int i;
+
+ _icp_msg.src_id = src_core;
+ _icp_msg.dest_core = dest_core;
+ _icp_msg.event_id = ch;
+
+ if(_icp_fn)
+ _icp_fn(&_icp_msg);
+}
+
+/*
+ * for get wake state
+ */
+void icp_get_int_info(T_ZDrvRpMsg_ActorID actorID, unsigned int *high_word, unsigned int *low_word)
+{
+ T_HalIcp_Dword IcpState;
+
+ IcpState = icp_get_int(actorID);
+
+ *high_word = IcpState.high_word;
+ *low_word = IcpState.low_word;
+}
+
+static const char * const ps_channel_info[64] = {
+ [0] = "drv test",
+ [2] = "Power Management",
+ [3] = "ADB agent",
+ [4] = "USB app config",
+ [5] = "USB kernel config",
+ [6] = "audio",
+ [7] = "console switch",
+ [8] = "NV",
+ [9] = "debug",
+ [10] = "ramdump",
+ [11] = "tee common",
+ [12] = "tee RPC",
+ [13] = "ap2cap message queue",
+ [14] = "cap2ap message queue",
+ [15] = "AMT framework",
+ [16] = "APP rsvd 16",
+ [17] = "APP rsvd 17",
+ [18] = "APP rsvd 18",
+ [19] = "APP rsvd 19",
+ [20] = "zvnet 20",
+ [21] = "zvnet 21",
+ [22] = "zvnet 22",
+ [23] = "zvnet 23",
+ [24] = "zvnet 24",
+ [25] = "zvnet 25",
+ [26] = "zvnet 26",
+ [27] = "zvnet 27",
+ [28] = "zvnet 28",
+ [29] = "free skb",
+ [30] = "ttygs0",
+ [31] = "ttygs1",
+ [32] = "socket ipc",
+ [33] = "binder ipc",
+ [34] = "at channel 34",
+ [35] = "at channel 35",
+ [36] = "at channel 36",
+ [37] = "at channel 37",
+ [38] = "at channel 38",
+ [39] = "at channel 39",
+ [40] = "at channel 40",
+ [41] = "voice buffer",
+};
+
+void show_icp_state(T_ZDrvRpMsg_ActorID actorID)
+{
+ unsigned int hw, lw;
+ int i;
+
+ if (actorID != CORE_PS0)
+ return;
+
+ icp_get_int_info(actorID, &hw, &lw);
+ pr_info("[SLP] icpwake: 0x%x 0x%x\n", hw, lw);
+ sc_debug_info_record(MODULE_ID_CAP_PM, " icpwake: 0x%x 0x%x\n", hw, lw);
+
+ for (i=0; i<32; i++)
+ if (lw&BIT(i))
+ pr_info("[SLP] icpwake: channel(%d) function(%s)\n", i, ps_channel_info[i] ? ps_channel_info[i] : "NA");
+
+ for (i=0; i<32; i++)
+ if (hw&BIT(i))
+ pr_info("[SLP] icpwake: channel(%d) function(%s)\n", i+32, ps_channel_info[i+32] ? ps_channel_info[i+32] : "NA");
+}
+
+static void icp_register_callback(icp_callback_fn cb)
+{
+ _icp_fn = cb;
+}
+
+static int icp_send_message(unsigned int core_id, icp_msg *icp_msg)
+{
+ if(!icp_msg || icp_msg->dest_core > CORE_MAXID )
+ return -EINVAL;
+
+ if(icp_get_int_state(icp_msg->dest_core, icp_msg->event_id)==false)
+ {
+ icp_set_int(icp_msg->dest_core, icp_msg->event_id);
+ }
+
+ return 0;
+}
+
+static t_icpdev_ops zx29_icp_ops = {
+ .register_callback = icp_register_callback,
+ .send_message = icp_send_message,
+ .mask_int = icp_mask_int,
+ .unmask_int = icp_unmask_int,
+ .set_int = icp_set_int,
+};
+
+static int icp_ap2ps_init(struct device *dev)
+{
+ void __iomem *reg_base;
+ unsigned int irq;
+ int ret;
+ struct device_node *np = dev->of_node;
+
+ reg_base = of_iomap(np, 0);
+ if ( !reg_base ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_MEM\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2ps_reg = (T_HalIcp_Reg *)reg_base;
+
+ irq = irq_of_parse_and_map(np, 0);
+ if( !irq ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_IRQ\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2ps_reg->mask.high_word = 0xffffffff;
+ icp_ap2ps_reg->mask.low_word = 0xffffffff;
+
+ ret = request_irq(irq, icp_isr, 0, "zx_icp", CORE_PS0);
+ if (ret)
+ {
+ pr_err("%s: [ICP]register irq failed\n", __func__);
+ return ret;
+ }
+
+ enable_irq_wake(irq);
+
+ icpdev_register_ops(&zx29_icp_ops);
+
+ rpmsgInit(CORE_PS0, np);
+/*
+ dev->id = CORE_PS0;
+ ret = icp_rpmsg_device_register(dev);
+*/
+ pr_info("%s: ok! irq(%d) icp_address(%llx \n", __func__, irq, reg_base );
+
+ return ret;
+}
+
+static int icp_ap2m0_init(struct device *dev)
+{
+ void __iomem *reg_base;
+ unsigned int irq;
+ int ret;
+ struct device_node *np = dev->of_node;
+
+ pr_info("%s: enter \n", __func__);
+
+ reg_base = of_iomap(np, 0);
+ if ( !reg_base ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_MEM\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2m0_reg = (T_HalIcp_Reg *)reg_base;
+
+ irq = irq_of_parse_and_map(np, 0);
+ if( !irq ){
+ pr_err("%s: [ICP]Cannot get IORESOURCE_IRQ\n", __func__);
+ return -ENOENT;
+ }
+
+ icp_ap2m0_reg->mask.high_word = 0xffffffff;
+ icp_ap2m0_reg->mask.low_word = 0xffffffff;
+
+ ret = request_irq(irq, icp_isr, 0, "zx_icp", CORE_M0);
+ if (ret)
+ {
+ pr_err("%s: [ICP]register irq failed\n", __func__);
+ return ret;
+ }
+
+ enable_irq_wake(irq);
+
+ icpdev_register_ops(&zx29_icp_ops);
+
+ rpmsgInit(CORE_M0, np);
+
+ pr_info("%s: ok! irq(%d) icp_address(%llx \n", __func__, irq, reg_base );
+
+ return 0;
+}
+
+static const struct of_device_id zx29_icp_dt_ids[] = {
+ { .compatible = "zte,zx29-icp-ap2m0", .data = &icp_ap2m0_init },
+ { .compatible = "zte,zx29-icp-ap2ps", .data = &icp_ap2ps_init },
+ { /* sentinel */ }
+};
+
+static int zx29_icp_probe(struct platform_device *pdev)
+{
+ int (*init_fn)(struct device *dev);
+
+ init_fn = of_device_get_match_data(&pdev->dev);
+ if (!init_fn) {
+ dev_err(&pdev->dev, "Error: No device match found\n");
+ return -ENODEV;
+ }
+
+ return init_fn(&pdev->dev);
+}
+
+static struct platform_driver zx29_icp_driver = {
+ .driver = {
+ .name = "zx29-icp",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(zx29_icp_dt_ids),
+ },
+ .probe = zx29_icp_probe,
+};
+
+builtin_platform_driver(zx29_icp_driver)
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
new file mode 100755
index 0000000..b29437a
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/drivers/tty/serial/zx29_uart.c
@@ -0,0 +1,4510 @@
+/****************************************************************************/
+/*
+ * zx29_uart.c sanchips
+ *
+ * (C) Copyright 2003-2007, gaowei
+ * (C) Copyright 2003-2007, sanchips
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/****************************************************************************/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <linux/printk.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <linux/sched/clock.h>
+#include <linux/soc/zte/spinlock.h>
+
+#if 0
+#include <mach/gpio_def.h>
+#include <mach/irqs.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/debug.h>
+#include <mach/iomap.h>
+#include <mach/dma.h>
+#include <mach/dma_cfg.h>
+#endif
+//#include <linux/wakelock.h>
+#include <linux/kthread.h>
+#include <linux/semaphore.h>
+
+#include <linux/dma/zx-dma.h>
+//#include "../../dma/zte/zx298501_dma.h"
+
+#include "zx29_uart.h"
+#include <linux/soc/zte/rpmsg.h>
+#include <linux/soc/sc/drv_idle.h>
+#include "pub_debug_info.h"
+//#include <linux/soc/zte/pm/drv_idle.h>
+//#include <mach/pcu.h>
+//#define DEBUG_UART
+
+#ifdef DEBUG_UART
+#pragma GCC optimize("O0")
+#endif
+
+#define UART_WCLK_NAME "uartclk"
+#define UART_APBCLK_NAME "apb_pclk"
+
+#define CONFIG_SERIAL_ZX29_DMA 1
+
+
+extern bool xp2xp_Ap2CpIsApWakeup(void);
+extern int xp2xp_enable_4line(void);
+
+extern signed int zx29_dma_stop(unsigned int channel_id);
+extern signed int zx29_dma_get_transfer_num(unsigned int channel_id);
+
+
+
+char uart_names[5][12] = {
+ "zx29_uart.0",
+ "zx29_uart.1",
+ "zx29_uart.2",
+ "zx29_uart.3",
+ "zx29_uart.4"
+};
+
+#if CONFIG_SERIAL_ZX29_DMA
+#define ZX29_DMA_BUFFER_SIZE PAGE_SIZE
+#define UART_DMA_RX_MAX_COUNT 2
+//#define RX_DMA_TIMEOUT (HZ / 10)//60
+#define RX_DMA_TIMEOUT (HZ / 100)
+#define RX_DMA_WORK 1
+struct zx29_sgbuf {
+ struct scatterlist sg;
+ dma_addr_t dma_addr;
+ char *buf;
+};
+
+struct zx29_dmarx_data {
+ struct dma_chan *chan;
+ struct completion complete;
+ dma_channel_def rx_def[UART_DMA_RX_MAX_COUNT];
+ u32 rx_index;
+ bool use_buf_b;
+ struct zx29_sgbuf sgbuf_a;
+ struct zx29_sgbuf sgbuf_b;
+ dma_cookie_t cookie;
+ bool running;
+ atomic_t count;
+ bool used;
+};
+
+struct zx29_dmatx_data {
+ struct dma_chan *chan;
+ struct completion complete;
+ dma_channel_def tx_def;
+ struct scatterlist sg;
+ char *buf;
+ bool queued;
+ atomic_t count;
+};
+#define UART_DEBUG_RECORDER_BYTE 0
+#define UART_DMA_CYCLE_RX_CONFIG_COUNT 5
+struct zx29_dma_cycle_data{
+ int id;
+ int flg_enter_th;
+ int flg_enter_to;
+ char flg_overrun;
+ char flg_pe;
+ char flg_be;
+ char flg_fe;
+ char from_resume;
+ unsigned long cnt_callback_total;
+ unsigned long cnt_th_total;
+ int cnt_callback;
+ int cnt_th;
+ struct zx29_sgbuf sgbuf[UART_DMA_CYCLE_RX_CONFIG_COUNT];
+ dma_channel_def rxdef[UART_DMA_CYCLE_RX_CONFIG_COUNT];
+ bool enter_throttle;
+ bool from_unthrottle;
+ bool used;
+ unsigned int cnt_throttle;
+ unsigned int cnt_unthrottle;
+};
+struct zx29_dma_cycle_data uart_dma_cycle[6];
+#endif
+
+
+
+#define UART_NUM 5
+int g_uart_overrun[5];
+ktime_t g_hr_interval;
+
+
+int g_cons_id_cmdline;
+EXPORT_SYMBOL(g_cons_id_cmdline);
+
+#ifdef DEBUG_CONSOLE
+#undef DEBUG_CONSOLE
+#endif
+#define DEBUG_CONSOLE g_cons_id_cmdline
+/****************************************************************************/
+
+/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
+ * name, but it is legally reserved for the 8250 driver. */
+#define SERIAL_zx29_MAJOR TTY_MAJOR
+#define SERIAL_MINOR_START 64
+
+#define UART_PORT_AUTOBAUD_ON 1
+#define UART_PORT_AUTOBAUD_OFF 0
+#define UART_PORT_AUTOBAUD_BYTE 2
+#define UART_AT_SENDOK_NUM 6
+#define UART_AUTOBAUD_LEVEL 5
+#define UART_AUTOBAUD_CHECKBYTE 4
+#define UART_AUTOBAUD_RATE 115200
+#define UART1_AUTOBAUD_RATE 921600
+
+
+unsigned char uart_port_autobaud_buffer[UART_PORT_AUTOBAUD_BYTE] = {0};
+unsigned char uart_port_autobaud_gtflag = 0 ;
+unsigned char uart_port_autobaud_suflag = 0 ;
+unsigned char g_console_open_flag = 1;
+
+
+unsigned char UART_AT_send_ok[UART_AT_SENDOK_NUM] =
+ {
+ 0x0d,0x0a,0x4F,0x4B,0x0d,0x0a
+ };
+
+unsigned char UART_baud_check[UART_AUTOBAUD_LEVEL][UART_AUTOBAUD_CHECKBYTE]=
+ {
+ {0x61,0x74,0x41,0x54},{0x06,0x9e,0x06,0x98},{0x1c,0x80,0x1c,0x00},
+ {0xe0,0x00,0xe0,0x00},{0x00,0x00,0x00,0x00},
+ };
+unsigned int UART_baud[UART_AUTOBAUD_LEVEL] =
+ {
+ 115200,57600,38400,19200,9600
+ };
+unsigned int UART_termios_cflag[UART_AUTOBAUD_LEVEL] =
+ {
+ B115200,B57600,B38400,B19200,B9600
+ };
+
+#ifdef CONFIG_SERIAL_CORE_CONSOLE
+#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
+#else
+#define uart_console(port) (0)
+#endif
+
+/****************************************************************************/
+/*
+ * Local per-uart structure.
+ */
+struct zx29_uart_port
+{
+ struct uart_port port;
+ unsigned int sigs; /* Local copy of line sigs */
+ unsigned int old_status;
+ unsigned char imr; /* Local interrupt mask reg mirror */
+#if CONFIG_SERIAL_ZX29_DMA
+ unsigned char dmacr; /* DMA reg*/
+#endif
+ bool rts_state;
+ bool autorts; /* hardware flow control */
+ struct clk *wclk; /* uart work clock */
+ struct clk *busclk; /* uart apb clock */
+ bool autobaud;
+ bool autobaud_state;
+ unsigned int baudrate;
+ bool uartwake;
+
+ int irq;
+ int irq_state;
+ int rxd_irq;
+ struct tasklet_struct write_wakeup;
+ bool rxd_wakeup;
+ int rxd_int_depth;
+ bool enter_suspend;
+#if CONFIG_SERIAL_ZX29_DMA
+ /* DMA stuff */
+ bool using_tx_dma;
+ bool using_rx_dma;
+ struct zx29_dmarx_data dmarx;
+ struct zx29_dmatx_data dmatx;
+ struct timer_list rx_dma_timer;
+ struct hrtimer rx_dma_hrtimer;
+ struct task_struct *dma_compl_th;
+ struct semaphore sema;
+ struct semaphore sema_cyclic;
+ bool port_close;
+ bool work_state;
+ size_t pre_pending;
+ struct zx29_sgbuf *sg2tty;
+ size_t sg2tty_len;
+ struct zx29_sgbuf *curr_sg;
+ int enable_ctsrts;
+ int enable_wakeup;
+
+ struct notifier_block wakeup_notifier;
+
+#endif
+ //means application decide close and release DMA &wakelock
+ int app_ctrl;
+ int sleep_state;
+ //if app_ctrl is set or using kernel control sleep,set this flag
+ int uart_power_mode;
+};
+
+
+
+static struct zx29_uart_port zx29_uart_ports[UART_NUM];
+
+#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
+typedef struct __UART_STATIC{
+ int cnt;
+ char head[16];
+ unsigned long long s_time;
+ int func_step;
+ unsigned int fr;
+ unsigned int ris;
+}uart_static;
+#define STATIC_UART_ID 0
+#define UART_STATIC_COUNT 512
+#define UART_STATIC_NUM 4
+uart_static g_uart_static[UART_STATIC_NUM][UART_STATIC_COUNT] = {0};
+int g_uart_static_cnt[UART_STATIC_NUM] = {0};
+void test_uart_static(int uart_id, char *buf, unsigned int cnt, int steps)
+{
+ //if(uart_id != STATIC_UART_ID)
+ // return;
+ if(buf){
+ if(cnt >= 16){
+ memcpy(g_uart_static[uart_id][g_uart_static_cnt[uart_id]].head, buf, 16);
+ }else{
+ memcpy(g_uart_static[uart_id][g_uart_static_cnt[uart_id]].head, buf, cnt);
+ }
+ }
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].cnt = cnt;
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].s_time = local_clock();
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].func_step = steps;
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].fr = UART_GET_FR(&zx29_uart_ports[uart_id].port);
+ g_uart_static[uart_id][g_uart_static_cnt[uart_id]].ris = UART_GET_RIS(&zx29_uart_ports[uart_id].port);
+
+ if(++g_uart_static_cnt[uart_id] >= UART_STATIC_COUNT)
+ g_uart_static_cnt[uart_id] = 0;
+}
+
+
+
+
+#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
+void zx29_uart_stop_rx(struct uart_port *port);
+
+#if CONFIG_SERIAL_ZX29_DMA
+static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup);
+static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup);
+static bool zx29_dma_tx_irq(struct zx29_uart_port *zup);
+static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup);
+void uart_dma_rx_callback(void *data);
+void uart_dma_rx_callback_use_dma_cyclic(void * data);
+static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
+ //u32 pending, bool use_buf_b,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ bool readfifo, unsigned long *flags);
+static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup);
+static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup);
+static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup);
+static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup);
+static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup);
+
+static void zx29_uart_rx_dma_chars(struct zx29_uart_port *zup, unsigned long *flags);
+dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup);
+
+#if RX_DMA_WORK
+static void zx29_uart_rx_timeout_chars(struct zx29_uart_port *zup, unsigned long *flags);
+static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup);
+
+static void zx29_uart_rt_dma(struct zx29_uart_port *zup, unsigned long *flags);
+static void uart_dma_cycle_deinit(struct zx29_uart_port *zup);
+#endif
+#endif
+
+
+
+/*******************************************************************************
+* Function: uart_wakeup_callback.
+* Description: uart_wakeup_callback.
+* Parameters:
+* Input:val:means wakeup or sleep notify to other device
+*
+* Output:v:means devices been called return result
+*
+* Returns:
+*
+* Others:
+********************************************************************************/
+int uart_wakeup_callback(struct notifier_block * nb, unsigned long val, void * v)
+{
+ int *call_result = (int *)v;
+ unsigned long flags = 0;
+ struct zx29_uart_port *zup = container_of(nb, struct zx29_uart_port, wakeup_notifier);
+
+ if(!zup || zup->port_close){
+ *call_result |= 0;
+ return 0;
+ }
+ struct platform_device *pdev = zup->port.private_data;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ if(val == 1){//wakeup
+ zup->sleep_state = 0;
+ pm_stay_awake(&pdev->dev);
+ zx29_uart_rx_dma_chars(zup, &flags);
+
+ }else{//sleep
+ zup->sleep_state = 1;
+ zx29_uart_stop_rx(&zup->port);
+ pm_relax(&pdev->dev);
+
+ }
+ *call_result |= 0;
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return 0;
+}
+
+int zx29_get_sleep_state(int uart_index)
+{
+ if(uart_index < 0 || uart_index > 2){
+ printk("invalid uart index\n");
+ return -1;
+ }
+
+ return zx29_uart_ports[uart_index].sleep_state;
+}
+EXPORT_SYMBOL_GPL(zx29_get_sleep_state);
+
+void zx29_set_sleep_state(int state, int uart_index)
+{
+ if(uart_index < 0 || uart_index > 2){
+ printk("invalid uart index\n");
+ return ;
+ }
+ printk(" uart %d, state change to:%d\n", uart_index, state);
+ zx29_uart_ports[uart_index].sleep_state = (state ? 1: 0);
+}
+EXPORT_SYMBOL_GPL(zx29_set_sleep_state);
+
+static ssize_t sleep_state_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "\n wakeup_enable = %d\n",zx29_uart_ports[pdev->id].sleep_state);
+}
+
+static ssize_t sleep_state_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ flag = simple_strtoul(buf, NULL, 16);
+ //pdata->uart_wakeup_enable = flag;
+ zx29_uart_ports[pdev->id].sleep_state = (flag ? 1: 0);
+ return count;
+}
+
+DEVICE_ATTR(sleep_state, S_IRUGO | S_IWUSR, sleep_state_show,
+ sleep_state_store);
+//bool uart_dma_filter_fn (struct dma_chan *chan, void *param)
+//{
+// dma_peripheral_id peri_id = (dma_peripheral_id) param;
+// if (chan->chan_id == (unsigned int)peri_id){
+// printk("uart_dma_filter_fn, peri_id:%d, ok\n", peri_id);
+// return true;
+// }
+// chan->private = param;
+//
+// return false;
+//}
+static void zx29_uart_console_putc(struct uart_port *port, int c);
+void zx29_uart_putc(struct uart_port *port, int c);
+
+#if CONFIG_SERIAL_ZX29_DMA
+void uart_mod_timer(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ unsigned long t_delay = 0;
+ t_delay = msecs_to_jiffies(RX_DMA_TIMEOUT);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ //printk("uart_mod_timer, delay %d jiffies\n", t_delay);
+ mod_timer(&(zup->rx_dma_timer), jiffies + t_delay);
+
+ spin_lock_irqsave(&zup->port.lock, *flags);
+}
+#endif
+/**
+* Show the console_input attribute.
+*/
+static ssize_t console_input_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "\n console_input = %d\n",g_console_open_flag);
+}
+
+/**
+ * Store the console_input attribure.
+ * 0: disable console input function,only out put log
+ * 1: able console input, can input commands
+ */
+static ssize_t console_input_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ flag = simple_strtoul(buf, NULL, 16);
+ g_console_open_flag = flag;
+
+ return count;
+}
+
+DEVICE_ATTR(console_input, S_IRUGO | S_IWUSR, console_input_show,
+ console_input_store);
+
+static ssize_t ctsrts_input_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ if(pdev->id < 0 || pdev->id >= UART_NUM){
+ printk("ctsrts_input_store, invalid uart id, return error\n");
+ return 0;
+ }
+// return sprintf(buf, "\n ctsrts_input = %d\n",pdata->uart_ctsrtsuse);
+return sprintf(buf, "\n uart %d ctsrts_input = %d\n", pdev->id, zx29_uart_ports[pdev->id].enable_ctsrts);
+
+}
+
+static ssize_t ctsrts_input_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+
+ if(pdev->id != 0){
+ printk("ctsrts_input_store, invalid uart id, only uart support hardware control\n");
+ }
+ flag = simple_strtoul(buf, NULL, 16);
+ zx29_uart_ports[pdev->id].enable_ctsrts = flag;
+
+ return count;
+}
+
+DEVICE_ATTR(ctsrts_input, S_IRUGO | S_IWUSR, ctsrts_input_show,
+ ctsrts_input_store);
+
+static ssize_t wakeup_enable_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "\n wakeup_enable = %d\n",1);
+}
+
+static ssize_t wakeup_enable_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ if(pdev->id != 4){
+ printk("\nctsrts_input_store, invalid uart id, only lp_uart(uart 4) support wakeup\n");
+ }
+ flag = simple_strtoul(buf, NULL, 16);
+ zx29_uart_ports[pdev->id].enable_wakeup = flag;
+
+ return count;
+}
+
+DEVICE_ATTR(wakeup_enable, S_IRUGO | S_IWUSR, wakeup_enable_show,
+ wakeup_enable_store);
+
+static ssize_t app_ctrl_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "%d\n",zx29_uart_ports[pdev->id].app_ctrl);
+}
+
+static ssize_t app_ctrl_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ flag = simple_strtoul(buf, NULL, 16);
+ // pdata->uart_wakeup_enable = flag;
+ zx29_uart_ports[pdev->id].app_ctrl = (flag == 0) ? 0 : 1;
+
+ return count;
+}
+DEVICE_ATTR(app_ctrl, S_IRUGO | S_IWUSR, app_ctrl_show,
+ app_ctrl_store);
+
+int rxd_wake_cnt = 0;
+static ssize_t statics_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+
+ return sprintf(buf, "\n RX:%u,TX:%u,OE:%u,brk:%u,FE:%u,PE:%u ,rxd_wake_cnt:%d\n",
+ zx29_uart_ports[pdev->id].port.icount.rx,
+ zx29_uart_ports[pdev->id].port.icount.tx,
+ zx29_uart_ports[pdev->id].port.icount.overrun,
+ zx29_uart_ports[pdev->id].port.icount.brk,
+ zx29_uart_ports[pdev->id].port.icount.frame,
+ zx29_uart_ports[pdev->id].port.icount.parity,
+ rxd_wake_cnt
+ );
+}
+DEVICE_ATTR(statics, S_IRUGO, statics_show, NULL);
+#define VEHICLE_USE_ONE_UART_LOG 1
+#if VEHICLE_USE_ONE_UART_LOG
+#define ICP_CORE_ID_PS CORE_PS0
+#define ICP_CORE_ID_CAP 1
+#define ICP_CHANNEL_CONSOLE_UART 7
+#define ICP_MSG_LEN_CONSOLE_UART 2
+#define ICP_BUFFERSIZE_CONSOLE_TOGGLE 16
+#define SYMB_PS_CORE_ID ICP_CORE_ID_PS
+#define SYMB_CAP_CORE_ID ICP_CORE_ID_CAP
+#define SYMB_WHAT_CORE_ID 3
+#define ENABLE_CURRENT_CONSOLE_UART 1
+#define DISABLE_CURRENT_CONSOLE_UART 0
+#define ENABLE_TOGGLE 1
+#define DISABLE_TOGGLE 0
+unsigned char g_core_id_occupy_uart = 0;
+unsigned char g_cap_uart_toggle = 0;
+static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id);
+static void restart_current_cons_uart(void)
+{
+ struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
+ struct uart_port *port = &zup->port;
+ enable_irq(port->irq);
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ spin_lock(&zup->port.lock);
+ tasklet_schedule(&zup->write_wakeup);
+ spin_unlock(&zup->port.lock);
+}
+static void forbid_current_cons_uart(void)
+{
+ struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
+ struct uart_port *port = &zup->port;
+ disable_irq(port->irq);
+ g_core_id_occupy_uart = SYMB_PS_CORE_ID;
+}
+static void process_ps2cap_rpmsg(char *arr)
+{
+ if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == ENABLE_CURRENT_CONSOLE_UART)){
+ restart_current_cons_uart();
+ }else if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == DISABLE_CURRENT_CONSOLE_UART)){
+ printk("current console uart not enable.\n");
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_PS_CORE_ID)){
+ g_core_id_occupy_uart = SYMB_PS_CORE_ID;
+ forbid_current_cons_uart();
+ }else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_CAP_CORE_ID)){
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }
+ else{
+ printk("%s error!!\n",__func__);
+ }
+}
+static void icp_callback_ps2cap(void *buf, unsigned int len)
+{
+ char *arr_ps2cap;
+ if (len==0){
+ printk("%s empty.\n", __func__);
+ return ;
+ }
+ arr_ps2cap = (char *)buf;
+ process_ps2cap_rpmsg(arr_ps2cap);
+}
+static void echo_to_change_other_uart(uint32_t val)
+{
+ int ret;
+ if(val > ENABLE_TOGGLE)
+ {
+ printk("echo para error!!!\n");
+ return;
+ }
+ char arr[2] = {0};
+ arr[0] = SYMB_PS_CORE_ID;
+ arr[1] = val;
+ T_RpMsg_Msg icp_msg;
+ icp_msg.coreID = CORE_PS0;
+ icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
+ icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
+ icp_msg.buf = arr;
+ icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
+ ret = rpmsgWrite(&icp_msg);
+ if(ret == 0){
+ if(val == ENABLE_TOGGLE)
+ g_core_id_occupy_uart = SYMB_PS_CORE_ID;
+ else if(val == DISABLE_TOGGLE)
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }else
+ printk("echo_to_change_ohter_uart fail.\n");
+}
+static ssize_t console_uart_toggle_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "\n console_uart_toggle_show %d. \n", g_cap_uart_toggle);
+}
+static ssize_t console_uart_toggle_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ flag = simple_strtoul(buf, NULL, 16);
+ if(flag == ENABLE_TOGGLE){
+ g_cap_uart_toggle = 1;
+ forbid_current_cons_uart();
+ echo_to_change_other_uart(flag);
+ }else if(flag == DISABLE_TOGGLE){
+ g_cap_uart_toggle = 0;
+ g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
+ }
+ return count;
+}
+DEVICE_ATTR(console_uart_toggle, S_IRUGO | S_IWUSR, console_uart_toggle_show,
+ console_uart_toggle_store);
+static void notify_occupy_uart_coreid_to_other(void)
+{
+ char arr[2] = {0};
+ arr[0] = SYMB_WHAT_CORE_ID;
+ arr[1] = g_core_id_occupy_uart;
+ T_RpMsg_Msg icp_msg;
+ icp_msg.coreID = CORE_AP;
+ icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
+ icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
+ icp_msg.buf = arr;
+ icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
+ rpmsgWrite(&icp_msg);
+}
+static ssize_t coreid_occupy_uart_show(struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "\n core %d occupy cons uart now! \n",g_core_id_occupy_uart);
+}
+static ssize_t coreid_occupy_uart_store(struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t flag = 0;
+ flag = simple_strtoul(buf, NULL, 16);
+ g_core_id_occupy_uart = flag;
+ if(flag == SYMB_CAP_CORE_ID){
+ g_cap_uart_toggle = 0;
+ }else if(SYMB_PS_CORE_ID){
+ g_cap_uart_toggle = 1;
+ }
+ return count;
+}
+DEVICE_ATTR(coreid_occupy_uart, S_IRUGO | S_IWUSR, coreid_occupy_uart_show,
+ coreid_occupy_uart_store);
+#endif
+
+//extern int (*pm_callback_fn)(void);
+#ifdef CONFIG_CPU_IDLE
+typedef int (*pm_callback_fn)(void);
+extern int zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb);
+
+extern void disable_irq_nosync(unsigned int irq);
+extern void enable_irq(unsigned int irq);
+
+void uart_rxd_int_disable(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->rxd_int_depth++;
+}
+EXPORT_SYMBOL(uart_rxd_int_disable);
+
+int uart_0_pm_enter(void)
+{
+ struct zx29_uart_port *zup = &zx29_uart_ports[0];
+
+ //zDrvInt_UnmaskIrq(UART0_RXD_INT);
+ if(zup->irq_state == 0 || zup->imr== 0)
+ return 0;
+
+ //pcu_int_clear(PCU_UART0_RXD_INT);
+ if(!zup->rxd_int_depth){
+ //enable_irq(UART0_RXD_INT);
+ zup->rxd_int_depth++;
+ }
+ return 0;
+}
+
+int uart_0_pm_exit(void)
+{
+
+ return 0;
+}
+#endif
+/****************************************************************************/
+
+static int zx29_sgbuf_init(struct dma_chan *chan, struct zx29_sgbuf *sg,
+ enum dma_data_direction dir)
+{
+ dma_addr_t dma_addr;
+
+ sg->buf = dma_alloc_coherent(chan->device->dev,
+ ZX29_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
+ if (!sg->buf){
+ printk("zx29_sgbuf_init fail, no mem\n");
+ return -ENOMEM;
+ }
+ sg_init_table(&sg->sg, 1);
+ sg_set_page(&sg->sg, phys_to_page(dma_addr),
+ ZX29_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
+ sg_dma_address(&sg->sg) = dma_addr;
+ sg_dma_len(&sg->sg) = ZX29_DMA_BUFFER_SIZE;
+ sg->dma_addr = dma_addr;
+ return 0;
+}
+
+static void zx29_sgbuf_free(struct dma_chan *chan, struct zx29_sgbuf *sg,
+ enum dma_data_direction dir)
+{
+ if (sg->buf) {
+ dma_free_coherent(chan->device->dev,
+ ZX29_DMA_BUFFER_SIZE, sg->buf,
+ sg_dma_address(&sg->sg));
+ sg->dma_addr = NULL;
+ }
+}
+
+
+/****************************************************************************/
+static unsigned int zx29_uart_tx_empty(struct uart_port *port)
+{
+ return (UART_GET_FR(port)&(UART_FR_TXBUSY|UART_FR_TXFF)) ? 0 : TIOCSER_TEMT;
+}
+
+/****************************************************************************/
+static void zx29_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ unsigned int control = 0;
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->sigs = mctrl;
+ control = UART_GET_CR(&zup->port);
+ if(mctrl & TIOCM_DTR)
+ control |= UART_CR_DTR;
+ else
+ control &= ~ UART_CR_DTR;
+
+ if(mctrl & TIOCM_RTS)
+ control |= UART_CR_RTS;
+ else
+ control &= ~UART_CR_RTS;
+
+ if(mctrl & TIOCM_LOOP)
+ control |= UART_CR_LBE;
+ else
+ control &= ~UART_CR_LBE;
+
+ /* We need to disable auto-RTS if we want to turn RTS off */
+ if (zup->autorts) {
+ if (mctrl & TIOCM_RTS)
+ control |= UART_CR_RTSEN;
+ else
+ control &= ~UART_CR_RTSEN;
+ }
+ UART_PUT_CR(port, control);
+}
+
+/****************************************************************************/
+static unsigned int zx29_uart_get_mctrl(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned int mctrl = 0;
+ unsigned int uart_flag = 0;
+
+ uart_flag = UART_GET_FR(port);
+
+ mctrl = (uart_flag&UART_FR_CTS) ?TIOCM_CTS : 0;
+ mctrl |= (zup->sigs & TIOCM_RTS);
+ mctrl |= (uart_flag&UART_FR_DCD) ? TIOCM_CD : 0;
+ mctrl |= (uart_flag&UART_FR_DSR) ? TIOCM_DSR : 0;
+ mctrl |= (uart_flag&UART_FR_RI) ? TIOCM_RI : 0;
+
+ return mctrl;
+}
+
+/****************************************************************************/
+static void zx29_uart_start_tx(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned int control = 0;
+ unsigned int reg_bak[10] = {0};
+ struct circ_buf *xmit = &zup->port.state->xmit;
+ int count = 0;
+#if VEHICLE_USE_ONE_UART_LOG
+ if((port->line == DEBUG_CONSOLE))
+ {
+ if(g_core_id_occupy_uart == SYMB_PS_CORE_ID){
+ #if 1
+ count = uart_circ_chars_pending(xmit);
+ while(count-- > 0)
+ {
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ if (uart_circ_empty(xmit))
+ break;
+ }
+ #endif
+ return;
+ }
+ count = uart_circ_chars_pending(xmit);
+ while(count-- > 0)
+ {
+ zx29_uart_console_putc(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit)){
+ break;
+ }
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ {
+ spin_lock(&zup->port.lock);
+ tasklet_schedule(&zup->write_wakeup);
+ spin_unlock(&zup->port.lock);
+ return;
+ }
+ return;
+ }
+else
+#endif
+{
+ if(!(UART_GET_RIS(port)&UART_TXIS) && (UART_GET_FR(port) & UART_FR_TXFE))
+ {
+ if(!(UART_GET_RIS(port)&UART_TXIS))
+ {
+ count = uart_circ_chars_pending(xmit);
+ if(count >= zup->port.fifosize)
+ count = 15;//sent data more than TX ifls, TXIS will coming soon
+ if(count != 0){
+ do {
+ zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit) || (UART_GET_RIS(port)&UART_TXIS))
+ break;
+ } while (--count > 0);
+ }
+ }
+
+ }
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ if(!uart_console(port))
+ {
+ if (!zx29_dma_tx_start(zup))
+ {
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+ if(!(UART_GET_RIS(port)&UART_TXIS)){
+ if((UART_GET_FR(port) & UART_FR_TXFF))
+ return;
+ count = uart_circ_chars_pending(xmit);
+ while (count > 0) {
+ UART_PUT_CHAR(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit) || (UART_GET_RIS(port)&UART_TXIS) ||
+ (UART_GET_FR(port) & UART_FR_TXFF))
+ break;
+ }
+ }
+ }
+ }
+ else
+ {
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+ }
+#else
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+#endif
+}
+
+static void uart_write_wakeup_task(unsigned long _port)
+{
+ struct uart_port *port = (void *)_port;
+struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ struct platform_device *pdev=port->private_data;
+ //printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
+
+ if(zup->rxd_wakeup){
+ //rxd wake
+ printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
+ pm_wakeup_dev_event(&pdev->dev, 5000, false);
+ disable_irq(zup->rxd_irq);
+ zup->rxd_wakeup = false;
+ } else {
+ uart_write_wakeup(port);
+ }
+
+}
+
+#if CONFIG_SERIAL_ZX29_DMA
+#if UART_DEBUG_RECORDER_BYTE
+#define UART_DRIVER_DEBUG_COUNT (4*1024*1024)
+u32 cnt_uart_driver_debug = 0;
+u8 uart_driver_debug[UART_DRIVER_DEBUG_COUNT]={};
+void uart_debug(char *debug_buf, u32 count){
+ if(cnt_uart_driver_debug > (UART_DRIVER_DEBUG_COUNT-1)){
+ cnt_uart_driver_debug = 0;
+ }else{
+ memcpy(uart_driver_debug+cnt_uart_driver_debug,debug_buf,count);
+ cnt_uart_driver_debug = cnt_uart_driver_debug+count;
+ }
+}
+#endif
+int dma_complete_thread_use_dma_cyclic(void *ptr)
+{
+ unsigned long flags;
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)ptr;
+ size_t pending;
+ int dma_count = 0;
+ struct device *dev = NULL;
+ dev = zup->dmarx.chan->device->dev;
+ int uart_id = zup->port.line;
+ while(down_interruptible(&zup->sema_cyclic) == 0)
+ {
+ if(uart_dma_cycle[zup->port.line].cnt_callback > 0)
+ uart_id = zup->port.line;
+ else if(uart_dma_cycle[zup->port.line+3].cnt_callback > 0)
+ uart_id = zup->port.line + 3;
+
+ if(zup->port_close || !uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th].dma_addr)
+ break;
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ uart_dma_cycle[uart_id].cnt_th_total++;
+ uart_dma_cycle[uart_id].cnt_th++;
+ zup->sg2tty = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
+ zup->sg2tty_len = 4096;
+ pending = zup->sg2tty_len;
+ if(uart_dma_cycle[uart_id].flg_be || uart_dma_cycle[uart_id].flg_fe|| uart_dma_cycle[uart_id].flg_pe){
+ printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
+ zup->port.icount.brk,zup->port.icount.parity);
+ uart_dma_cycle[uart_id].flg_be = 0;
+ uart_dma_cycle[uart_id].flg_fe = 0;
+ uart_dma_cycle[uart_id].flg_pe = 0;
+ }
+ dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ zup->sg2tty->buf, pending);
+ test_uart_static(zup->port.line, zup->sg2tty->buf, uart_dma_cycle[zup->port.line].used, 27);
+#if UART_DEBUG_RECORDER_BYTE
+ uart_debug(zup->sg2tty->buf, pending);
+#endif
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock_irqsave(&zup->port.lock, flags);
+ dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ uart_dma_cycle[uart_id].flg_enter_th = (uart_dma_cycle[uart_id].flg_enter_th+1)%UART_DMA_CYCLE_RX_CONFIG_COUNT;
+ uart_dma_cycle[uart_id].cnt_callback--;
+ if(!hrtimer_active(&zup->rx_dma_hrtimer))
+ hrtimer_restart(&zup->rx_dma_hrtimer);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ }
+ return 0;
+}
+int dma_complete_thread(void *ptr)
+{
+ unsigned long flags;
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)ptr;
+
+ size_t pending;
+ struct dma_tx_state state;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ bool lastbuf;
+ int dma_count = 0;
+ struct zx29_sgbuf *sgbuf = NULL;
+ struct device *dev = NULL;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ dev = zup->dmarx.chan->device->dev;
+
+ while(down_interruptible(&zup->sema) == 0)
+ {
+ if(zup->port_close)
+ break;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ // tty = zup->port.state->port.tty;
+ if(!zup->sg2tty)
+ panic("dma_complete_thread, buffer 2 tty is invalid\n");
+ // dev = zup->dmarx.chan->device->dev;
+ pending = zup->sg2tty_len;
+ if(zx29_dma_rx_running(zup)){
+
+ test_uart_static(zup->port.line, NULL, 0, 10);
+ //uart_mod_timer(zup, &flags);
+ if(!hrtimer_active(&zup->rx_dma_hrtimer))
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ }
+ /* Pick everything from the DMA first */
+ if (pending) {
+ /* Sync in buffer */
+ dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+ //BUG();
+
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ zup->sg2tty->buf, pending);
+ test_uart_static(zup->port.line, zup->sg2tty->buf, pending, 11);
+ tty_flip_buffer_push(&zup->port.state->port);
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ /* Return buffer to device */
+ dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
+
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->port.icount.rx += dma_count;
+
+ //if(zup->port.line == 0)
+ //printk("yanming dma_complete_thread, dma2tty:%d\n", dma_count);
+ if (dma_count < pending){
+ sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d couldn't insert all characters \n",zup->port.line);
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+
+
+ }
+#if 0
+ zup->work_state = false;
+ zup->pre_pending = 0;
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+#endif
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ }
+
+ return 0;
+}
+#endif
+
+/****************************************************************************/
+static void zx29_uart_stop_tx(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->imr &= ~UART_TXIM;
+ UART_PUT_IMSC(port, zup->imr);
+#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
+ if((port->line == DEBUG_CONSOLE) && uart_tx_stopped(port))
+ {
+ //uart_write_wakeup(port);
+ tasklet_schedule(&zup->write_wakeup);
+ }
+#endif
+
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_tx_stop(zup);
+#endif
+
+ zx_cpuidle_set_free(IDLE_FLAG_UART);
+
+}
+
+/****************************************************************************/
+void zx29_uart_stop_rx(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+
+ zup->imr &= ~(UART_RXIM|UART_RTIM|UART_FEIM|UART_PEIM|UART_BEIM|UART_OEIM);
+ UART_PUT_IMSC(port, zup->imr);
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_rx_stop(zup);
+#endif
+}
+
+/****************************************************************************/
+static void zx29_uart_break_ctl(struct uart_port *port, int break_state)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ unsigned int lcr_h;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ lcr_h = UART_GET_LCRH(port);
+ if (break_state == -1)
+ lcr_h |= UART_LCRH_BRK;
+ else
+ lcr_h &= ~UART_LCRH_BRK;
+ UART_PUT_LCRH(port, lcr_h);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+}
+
+/****************************************************************************/
+static void zx29_uart_enable_ms(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ zup->imr |= UART_RIMIM|UART_CTSMIM|UART_DCDMIM|UART_DSRMIM;
+ UART_PUT_IMSC(port, zup->imr);
+}
+
+/****************************************************************************/
+/*--------------------------------------------------------------------
+ * Reads up to 256 characters from the FIFO or until it's empty and
+ * inserts them into the TTY layer. Returns the number of characters
+ * read from the FIFO.
+ --------------------------------------------------------------------*/
+static int zx29_uart_fifo_to_tty(struct zx29_uart_port *zup)
+{
+ struct uart_port *port = &zup->port;
+ u32 status, ch, i = 0;
+ unsigned int flag, max_count = 256;
+ int fifotaken = 0;
+ u8 uart_poll_char[16] ={0};
+
+ while (max_count--) {
+ status = UART_GET_FR(port);
+ if (status & UART_FR_RXFE)
+ break;
+
+ /* Take chars from the FIFO and update status */
+ ch = UART_GET_CHAR(port) | UART_DUMMY_DR_RX;
+
+#if 0
+ if(g_console_open_flag == 0 &&
+ port->line == DEBUG_CONSOLE){
+ if((ch&0xff) == 't'){
+ memset(uart_poll_char, 0, sizeof(uart_poll_char));
+ uart_poll_char[0] = 't';
+ i = 0;
+ printk("ch = %c i = %d\n",ch,i);
+ }else if ((ch&0xff) == 'y' && (i == 1)){
+ uart_poll_char[1] = 'y';
+ printk("ch = %c i = %d\n",ch,i);
+ }else if ((ch&0xff) == 'o' && (i == 2)){
+ uart_poll_char[2] = 'o';
+ printk("ch = %c i = %d\n",ch,i);
+ }else if ((ch&0xff) == 'p' && (i == 3)){
+ uart_poll_char[3] = 'p';
+ printk("ch = %c i = %d\n",ch,i);
+
+ }else if ((ch&0xff) == 'e' && (i == 4)){
+ uart_poll_char[4] = 'e';
+ printk("ch = %c i = %d\n",ch,i);
+
+ }else if ((ch&0xff) == 'n' && (i == 5)){
+ uart_poll_char[5] = 'n';
+ printk("ch = %c i = %d\n",ch,i);
+ g_console_open_flag = 1;
+ printk("ch = %c i = %d,g_console_open_flag:%d\n",ch,i,g_console_open_flag);
+ }else {
+ i = 10;
+ }
+ i++;
+ }
+#endif
+ flag = TTY_NORMAL;
+ if(zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
+ {
+ if(zup->port.icount.rx < UART_PORT_AUTOBAUD_BYTE)
+ {
+ uart_port_autobaud_buffer[zup->port.icount.rx] = ch;
+ }
+ else
+ {
+ uart_port_autobaud_gtflag = 1 ;
+ }
+ }
+ zup->port.icount.rx++;
+ if(zup->autobaud_state == UART_PORT_AUTOBAUD_OFF)
+ {
+ if(fifotaken < 16){
+ uart_poll_char[fifotaken] = ch & 0xFF;
+ }
+ fifotaken++;
+
+ if (unlikely(ch & UART_DR_ERROR)) {
+ if (ch & UART_DR_BE) {
+ ch &= ~(UART_DR_FE | UART_DR_PE);
+ zup->port.icount.brk++;
+ if (uart_handle_break(&zup->port))
+ continue;
+ } else if (ch & UART_DR_PE)
+ zup->port.icount.parity++;
+ else if (ch & UART_DR_FE)
+ zup->port.icount.frame++;
+ else if (ch & UART_DR_OE){
+ zup->port.icount.overrun++;
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ ch &= zup->port.read_status_mask;
+
+ if (ch & UART_DR_BE)
+ flag = TTY_BREAK;
+ else if (ch & UART_DR_PE)
+ flag = TTY_PARITY;
+ else if (ch & UART_DR_FE)
+ flag = TTY_FRAME;
+ }
+
+ if (uart_handle_sysrq_char(&zup->port, ch & 255))
+ continue;
+ if(g_console_open_flag || port->line != DEBUG_CONSOLE){
+ uart_insert_char(&zup->port, ch, UART_DR_OE, ch, flag);
+ }
+ }
+ }
+
+ test_uart_static(zup->port.line, uart_poll_char, fifotaken, 3);
+
+ return fifotaken;
+}
+
+/****************************************************************************/
+static void zx29_uart_rx_chars(struct zx29_uart_port *zup)
+{
+ unsigned long flags;
+
+ //struct tty_struct *tty = zup->port.state->port.tty;
+
+ zx29_uart_fifo_to_tty(zup);
+ spin_unlock(&zup->port.lock);
+
+ tty_flip_buffer_push(&zup->port.state->port);
+
+#if CONFIG_SERIAL_ZX29_DMA
+ if(!uart_console(&zup->port)){//console doesn't use dma rcv data
+ if (zx29_dma_rx_available(zup)) {
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ dev_dbg(zup->port.dev, "could not trigger RX DMA job "
+ "fall back to interrupt mode again\n");
+ zup->imr |= UART_RXIM;
+ } else{
+ zup->imr &= ~UART_RXIM;
+ }
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }
+ }
+#endif
+RX_END:
+ spin_lock(&zup->port.lock);
+
+}
+
+/****************************************************************************/
+static void zx29_uart_tx_chars(struct zx29_uart_port *zup)
+{
+ struct circ_buf *xmit = &zup->port.state->xmit;
+ unsigned long flags;
+ int count;
+
+ if (zup->port.x_char) {
+ UART_PUT_CHAR(&zup->port, zup->port.x_char);
+ zup->port.icount.tx++;
+ zup->port.x_char = 0;
+ return;
+ }
+ if (uart_circ_empty(xmit) || uart_tx_stopped(&zup->port)) {
+ zx29_uart_stop_tx(&zup->port);
+ return;
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ /* If we are using DMA mode, try to send some characters. */
+ if(!uart_console(&(zup->port)))
+ {
+ if (zx29_dma_tx_irq(zup))
+ return;
+ }
+#endif
+ count = zup->port.fifosize >> 1;
+ do {
+ zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+ } while (--count > 0);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ {
+ spin_unlock(&zup->port.lock);
+ //uart_write_wakeup(&zup->port);
+ tasklet_schedule(&zup->write_wakeup);
+ spin_lock(&zup->port.lock);
+ }
+
+ if (uart_circ_empty(xmit))
+ zx29_uart_stop_tx(&zup->port);
+}
+
+#if CONFIG_SERIAL_ZX29_DMA
+
+dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup)
+{
+ struct uart_port *port = &zup->port;
+ if(port->line < UART0 || port->line > UART4){
+ printk("get_rx_dma_peripheral_id,fail, invalid port->line:%d\n", port->line);
+ }
+ if(port->line == UART0){
+ return DMA_CH_UART0_RX;
+ } else if(port->line == UART1){
+ return DMA_CH_UART1_RX;
+ }else if(port->line == UART2){
+ return DMA_CH_UART2_RX;
+ }
+// else if(port->line == UART3){
+// return DMA_CH_UART3_RX;
+// }else if(port->line == UART4){
+// return DMA_CH_UART4_RX;
+// }
+
+ return DMA_CH_NUM;
+}
+
+/*
+ * We received a transmit interrupt without a pending X-char but with
+ * pending characters.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * false if we want to use PIO to transmit
+ * true if we queued a DMA buffer
+ */
+static bool zx29_dma_tx_irq(struct zx29_uart_port *zup)
+{
+ if (!zup->using_tx_dma)
+ return false;
+
+ /*
+ * If we already have a TX buffer queued, but received a
+ * TX interrupt, it will be because we've just sent an X-char.
+ * Ensure the TX DMA is enabled and the TX IRQ is disabled.
+ */
+ if (zup->dmatx.queued) {
+ zup->dmacr |= UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ zup->imr &= ~UART_TXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ return true;
+ }
+
+ /*
+ * We don't have a TX buffer queued, so try to queue one.
+ * If we successfully queued a buffer, mask the TX IRQ.
+ */
+ if (zx29_uart_dma_tx_chars(zup) > 0) {
+ zup->imr &= ~UART_TXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ return true;
+ }
+ return false;
+}
+
+
+/*
+ * Stop the DMA transmit (eg, due to received XOFF).
+ * Locking: called with port lock held and IRQs disabled.
+ */
+static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup)
+{
+ if (zup->dmatx.queued) {
+ zup->dmacr &= ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ }
+}
+
+
+/*
+ * Try to start a DMA transmit, or in the case of an XON/OFF
+ * character queued for send, try to get that character out ASAP.
+ * Locking: called with port lock held and IRQs disabled.
+ * Returns:
+ * false if we want the TX IRQ to be enabled
+ * true if we have a buffer queued
+ */
+static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup)
+{
+ u16 dmacr;
+
+ if (!zup->using_tx_dma)
+ return false;
+
+ if (!zup->port.x_char) {
+ /* no X-char, try to push chars out in DMA mode */
+ bool ret = true;
+
+ if (!zup->dmatx.queued) {
+ if (zx29_uart_dma_tx_chars(zup) > 0) {
+ zup->imr &= ~UART_TXIM;
+ ret = true;
+ } else {
+ zup->imr |= UART_TXIM;
+ ret = false;
+ }
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ } else if (!(zup->dmacr & UART_TXDMAE)) {
+ zup->dmacr |= UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ }
+ return ret;
+ }
+
+ /*
+ * We have an X-char to send. Disable DMA to prevent it loading
+ * the TX fifo, and then see if we can stuff it into the FIFO.
+ */
+ dmacr = zup->dmacr;
+ zup->dmacr &= ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+
+ if (UART_GET_FR(&zup->port) & UART_FR_TXFF) {
+ /*
+ * No space in the FIFO, so enable the transmit interrupt
+ * so we know when there is space. Note that once we've
+ * loaded the character, we should just re-enable DMA.
+ */
+ return false;
+ }
+
+ UART_PUT_CHAR(&zup->port, zup->port.x_char);
+ //writew(uap->port.x_char, uap->port.membase + UART01x_DR);
+ zup->port.icount.tx++;
+ zup->port.x_char = 0;
+
+ /* Success - restore the DMA state */
+ zup->dmacr = dmacr;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ //writew(dmacr, uap->port.membase + UART011_DMACR);
+
+ return true;
+}
+
+/****************************************************************************/
+
+//#if CONFIG_SERIAL_ZX29_DMA
+/*
+ * Flush the transmit buffer.
+ * Locking: called with port lock held and IRQs disabled.
+ */
+static void zx29_dma_flush_buffer(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)port;
+ if (!zup->using_tx_dma)
+ return;
+
+ /* Avoid deadlock with the DMA engine callback */
+ //dmaengine_terminate_all(zup->dmatx.chan);
+ if (zup->dmatx.queued) {
+
+ //printk(KERN_INFO "zx29_dma_flush_buffer enter[%s][%d] Port[%d]\n",__func__,__LINE__,port->line);
+ dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
+ DMA_TO_DEVICE);
+ zup->dmatx.queued = false;
+ zup->dmacr &= ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ }
+}
+
+static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup)
+{
+ struct dma_chan *rxchan = zup->dmarx.chan;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_async_tx_descriptor *desc;
+ struct zx29_sgbuf *sgbuf;
+
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ if (!rxchan)
+ {
+ printk("[%s][%d]\n",__func__,__LINE__);
+ return -EIO;
+ }
+
+ /* Start the RX DMA job */
+
+ sgbuf = zup->dmarx.use_buf_b ?
+ &zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
+ /*
+
+ sgbuf = zup->dmarx.use_buf_b ?
+ &zup->dmarx.sgbuf_a : &zup->dmarx.sgbuf_b;
+ */
+ zup->dmarx.rx_def[zup->dmarx.rx_index].link_addr=0;
+ zup->dmarx.rx_def[zup->dmarx.rx_index].dest_addr=(unsigned int)(sgbuf->dma_addr);
+ zup->dmarx.rx_def[zup->dmarx.rx_index].count=ZX29_DMA_BUFFER_SIZE;//fifo or max buffer?
+ wmb();
+
+ dmaengine_slave_config(rxchan, (struct dma_slave_config*)&zup->dmarx.rx_def[zup->dmarx.rx_index]);
+ desc = rxchan->device->device_prep_interleaved_dma(rxchan,NULL,0);
+
+
+ /*
+ * If the DMA engine is busy and cannot prepare a
+ * channel, no big deal, the driver will fall back
+ * to interrupt mode as a result of this error code.
+ */
+ if (!desc) {
+ printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
+ sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d ERROR DESC \n",zup->port.line);
+ zup->dmarx.running = false;
+ dmaengine_terminate_all(rxchan);
+ //zx29_dma_force_stop(rx_id);
+ return -EBUSY;
+ }
+
+ /* Some data to go along to the callback */
+ desc->callback = uart_dma_rx_callback;
+ desc->callback_param = zup;
+ zup->curr_sg = sgbuf;
+ wmb();
+
+ dmarx->cookie = dmaengine_submit(desc);
+ dma_async_issue_pending(rxchan);
+ atomic_inc(&zup->dmarx.count);
+ zup->dmarx.rx_index = (zup->dmarx.rx_index +1)%UART_DMA_RX_MAX_COUNT;
+ zup->dmacr |= UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ zup->dmarx.running = true;
+ zup->dmarx.used = true;
+ zup->imr &= ~(UART_RXIM | UART_RTIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+
+
+ return 0;
+}
+static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup)
+{
+ struct dma_chan *rxchan = zup->dmarx.chan;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_async_tx_descriptor *desc;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ int uart_id = zup->port.line;
+ if (!rxchan)
+ {
+ printk("[%s][%d]\n",__func__,__LINE__);
+ return -EIO;
+ }
+
+ if(uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+
+ dmaengine_slave_config(rxchan, (struct dma_slave_config*)&uart_dma_cycle[uart_id].rxdef);
+ desc = rxchan->device->device_prep_dma_cyclic(rxchan,NULL,(ZX29_DMA_BUFFER_SIZE *5) , ZX29_DMA_BUFFER_SIZE,0,0);
+ if (!desc) {
+ printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
+ zup->dmarx.running = false;
+ dmaengine_terminate_all(rxchan);
+ return -EBUSY;
+ }
+ desc->callback = uart_dma_rx_callback_use_dma_cyclic;
+ desc->callback_param = zup;
+ wmb();
+ dmarx->cookie = dmaengine_submit(desc);
+ dma_async_issue_pending(rxchan);
+ zup->dmacr |= UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ uart_dma_cycle[uart_id].flg_enter_th = 0;
+ if(uart_dma_cycle[zup->port.line].used){
+ uart_dma_cycle[zup->port.line].used = false;
+ uart_dma_cycle[zup->port.line+3].used = true;
+ }else{
+ uart_dma_cycle[zup->port.line].used = true;
+ uart_dma_cycle[zup->port.line+3].used = false;
+ }
+
+ zup->dmarx.running = true;
+ zup->dmarx.used = true;
+ zup->imr &= ~(UART_RXIM | UART_RTIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ return 0;
+}
+
+void uart_dma_rx_callback(void *data)
+{
+ unsigned long flags;
+
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)data;
+ int uart_id = zup->port.line;
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ struct device *dev = NULL;
+// struct dma_tx_state state;
+ unsigned int ris_status;
+
+ bool lastbuf;
+ int dma_count = 0;
+ struct zx29_sgbuf *sgbuf = zup->curr_sg;
+ size_t pending;
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 4;
+ test_uart_static(zup->port.line, NULL, 0, 20);
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ zx29_dma_stop(rx_id);
+
+ dev = zup->dmarx.chan->device->dev;
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+
+ //spin_lock_irqsave(&zup->port.lock, flags);
+ zup->sg2tty = sgbuf;
+// rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ zup->sg2tty_len = zup->sg2tty->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //zx29_dma_force_stop(rx_id);
+ // dmaengine_terminate_all(rxchan);
+ dmarx->use_buf_b = ! dmarx->use_buf_b;
+ wmb();
+ //BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
+ /* Then we terminate the transfer - we now know our residue */
+ //dmaengine_terminate_all(rxchan);
+
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ test_uart_static(zup->port.line, NULL, 0, 9);
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+
+ up(&zup->sema);
+}
+
+void uart_dma_rx_callback_use_dma_cyclic(void *data)
+{
+ unsigned long flags;
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)data;
+ unsigned int ris_status;
+ int uart_id = zup->port.line;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ if(!uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+ uart_dma_cycle[uart_id].cnt_callback_total++;
+ uart_dma_cycle[uart_id].cnt_callback++;
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ uart_dma_cycle[uart_id].flg_overrun = 1;
+ }
+ if(ris_status & UART_BEIS){
+ uart_dma_cycle[uart_id].flg_be = 1;
+ zup->port.icount.brk++;
+ }
+ if(ris_status & UART_PEIS){
+ uart_dma_cycle[uart_id].flg_pe = 1;
+ zup->port.icount.parity++;
+ }
+ if(ris_status & UART_FEIS){
+ uart_dma_cycle[uart_id].flg_fe = 1;
+ zup->port.icount.frame++;
+ }
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 26);
+ up(&zup->sema_cyclic);
+}
+static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup)
+{
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ //zx29_dma_force_stop(rx_id);
+ //dmaengine_terminate_all(zup->dmarx.chan);
+ /* FIXME. Just disable the DMA enable */
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+#if 0
+ //do we need check data received?
+ if(zup->pre_pending){
+ printk("pre_pending :%d\n ", zup->pre_pending);
+ }
+#endif
+ zup->curr_sg = NULL;
+}
+
+static void zx29_dma_remove(struct zx29_uart_port *zup)
+{
+ /* TODO: remove the initcall if it has not yet executed */
+ if (zup->dmatx.chan)
+ dma_release_channel(zup->dmatx.chan);
+ if (zup->dmarx.chan)
+ dma_release_channel(zup->dmarx.chan);
+}
+
+
+static void zx29_dma_shutdown(struct zx29_uart_port *zup)
+{
+ unsigned long flags;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+
+ if (!(zup->using_tx_dma || zup->using_rx_dma))
+ return;
+ /* Disable RX and TX DMA */
+ while(UART_GET_FR(&zup->port) & (UART_FR_TXBUSY | UART_FR_TXBUSY))
+ barrier();
+
+ spin_lock_irqsave(&zup->port.lock, flags);
+ //zx29_dma_force_stop(rx_id);
+ // dmaengine_terminate_all(zup->dmarx.chan);
+ zup->dmacr &= ~(UART_DMAONERR | UART_RXDMAE | UART_TXDMAE);
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->curr_sg = NULL;
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ if (zup->using_tx_dma) {
+ /* In theory, this should already be done by zx29_dma_flush_buffer */
+ dmaengine_terminate_all(zup->dmatx.chan);
+ if (zup->dmatx.queued) {
+ dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
+ DMA_TO_DEVICE);
+ zup->dmatx.queued = false;
+ }
+ if(!zup->dmatx.buf)
+ kfree(zup->dmatx.buf);
+ zup->dmatx.buf = NULL;
+ zup->using_tx_dma = false;
+ }
+ if (zup->using_rx_dma) {
+ //dmaengine_terminate_all(zup->dmarx.chan);
+ /* Clean up the RX DMA */
+ if(!zup->uart_power_mode){
+ zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a, DMA_FROM_DEVICE);
+ zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_b, DMA_FROM_DEVICE);
+ }else if(zup->uart_power_mode == 1){
+ uart_dma_cycle_deinit(zup);
+ }else
+ printk("uart%d dma shutdown fail.\n",zup->port.line);
+ zup->using_rx_dma = false;
+ zup->dmarx.used = false;
+ zup->dmarx.running = false;
+ zup->dmarx.use_buf_b = false;
+ zup->dmarx.rx_index = 0;
+ }
+ zup->pre_pending = 0;
+ zup->work_state = false;
+
+}
+
+static void zx29_shutdown_channel(struct zx29_uart_port *zup,
+ unsigned int lcrh)
+{
+ unsigned long val;
+
+ val = UART_GET_LCRH(&zup->port);
+ val &= ~(UART_LCRH_BRK | UART_LCRH_FEN);
+ UART_PUT_LCRH(&zup->port, val);
+}
+
+
+static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma;
+}
+
+static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma && zup->dmarx.running;
+}
+
+static inline bool zx29_dma_rx_used(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma && zup->dmarx.used;
+}
+
+static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup)
+{
+ return zup->using_rx_dma && zup->work_state;
+}
+
+
+void uart_dma_tx_callback(void *data)
+{
+ struct zx29_uart_port *zup = data;
+ struct zx29_dmatx_data *dmatx = &zup->dmatx;
+
+ unsigned long flags;
+ u16 dmacr;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ if (zup->dmatx.queued)
+ dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
+ DMA_TO_DEVICE);
+
+ dmacr = zup->dmacr;
+ zup->dmacr = dmacr & ~UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+
+ /*
+ * If TX DMA was disabled, it means that we've stopped the DMA for
+ * some reason (eg, XOFF received, or we want to send an X-char.)
+ *
+ * Note: we need to be careful here of a potential race between DMA
+ * and the rest of the driver - if the driver disables TX DMA while
+ * a TX buffer completing, we must update the tx queued status to
+ * get further refills (hence we check dmacr).
+ */
+ if (!(dmacr & UART_TXDMAE) || uart_tx_stopped(&zup->port) ||
+ uart_circ_empty(&zup->port.state->xmit)) {
+ zup->dmatx.queued = false;
+
+
+ zx_cpuidle_set_free(IDLE_FLAG_UART);
+
+
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ return;
+ }
+
+ if (zx29_uart_dma_tx_chars(zup) <= 0) {
+ /*
+ * We didn't queue a DMA buffer for some reason, but we
+ * have data pending to be sent. Re-enable the TX IRQ.
+ */
+ zup->imr |= UART_TXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+}
+
+static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup)
+{
+ struct zx29_dmatx_data *dmatx = &zup->dmatx;
+ struct dma_chan *tx_chan = dmatx->chan;
+ struct dma_device *dma_dev = tx_chan->device;
+ struct dma_async_tx_descriptor *desc;
+ struct circ_buf *xmit = &zup->port.state->xmit;
+ unsigned int count;
+
+ /*
+ * Try to avoid the overhead involved in using DMA if the
+ * transaction fits in the first half of the FIFO, by using
+ * the standard interrupt handling. This ensures that we
+ * issue a uart_write_wakeup() at the appropriate time.
+ */
+
+ count = uart_circ_chars_pending(xmit);
+ if (count < (16 >> 1)) {
+ zup->dmatx.queued = false;
+ return 0;
+ }
+
+ if (xmit->tail < xmit->head)
+ memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
+ else {
+ size_t first = UART_XMIT_SIZE - xmit->tail;
+ size_t second ;//= xmit->head;
+
+ if (first > count)
+ first = count;
+ second = count - first;
+ memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
+ if (second)
+ memcpy(&dmatx->buf[first], &xmit->buf[0], second);
+ }
+ dmatx->sg.length = count;
+
+ if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
+ zup->dmatx.queued = false;
+ dev_dbg(zup->port.dev, "unable to map TX DMA\n");
+ return -EBUSY;
+ }
+
+
+ zup->dmatx.tx_def.link_addr=0;
+ zup->dmatx.tx_def.src_addr=(unsigned int)(dmatx->sg.dma_address);
+ zup->dmatx.tx_def.count=count;
+ wmb();
+ dmaengine_slave_config(tx_chan, (struct dma_slave_config*)&zup->dmatx.tx_def);
+ desc = tx_chan->device->device_prep_interleaved_dma(tx_chan,NULL,0);
+
+ if (!desc) {
+ printk(KERN_INFO "!!!!!ERROR TX DESC[%s][%d]\n",__func__,__LINE__);
+ dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
+ zup->dmatx.queued = false;
+ /*
+ * If DMA cannot be used right now, we complete this
+ * transaction via IRQ and let the TTY layer retry.
+ */
+ dev_dbg(zup->port.dev, "TX DMA busy\n");
+ return -EBUSY;
+ }
+ desc->callback = (dma_async_tx_callback)uart_dma_tx_callback;
+ desc->callback_param = (void *)zup;
+ dmaengine_submit(desc);
+ dma_async_issue_pending(tx_chan);
+ atomic_inc(&zup->dmatx.count);
+ zup->dmacr |= UART_TXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zup->dmatx.queued = true;
+
+ /*
+ * Now we know that DMA will fire, so advance the ring buffer
+ * with the stuff we just dispatched.
+ */
+ xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+ zup->port.icount.tx += count;
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ //uart_write_wakeup(&zup->port);
+ tasklet_schedule(&zup->write_wakeup);
+
+ return 1;
+}
+
+static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
+ //u32 pending, bool use_buf_b,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ bool readfifo, unsigned long *flags)
+{
+ struct tty_struct *tty = zup->port.state->port.tty;
+#if 0
+ struct zx29_sgbuf *sgbuf = use_buf_b ?
+ &zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
+#endif
+ struct device *dev = zup->dmarx.chan->device->dev;
+ int dma_count = 0;
+ u32 fifotaken = 0; /* only used for vdbg() */
+ //unsigned long flags;
+
+ /* Pick everything from the DMA first */
+ if (pending) {
+ /* Sync in buffer */
+
+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+
+ /*
+ * First take all chars in the DMA pipe, then look in the FIFO.
+ * Note that tty_insert_flip_buf() tries to take as many chars
+ * as it can.
+ */
+
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ sgbuf->buf, pending);
+
+ test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ /* Return buffer to device */
+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+
+ /*
+ * Only continue with trying to read the FIFO if all DMA chars have
+ * been taken first.
+ */
+ //if (dma_count == pending && readfifo) {
+ if (readfifo) {
+ /* Clear any error flags */
+ //UART_PUT_ICR(&zup->port,UART_OEIC | UART_BEIC | UART_PEIC | UART_FEIC);
+ /*
+ * If we read all the DMA'd characters, and we had an
+ * incomplete buffer, that could be due to an rx error, or
+ * maybe we just timed out. Read any pending chars and check
+ * the error status.
+ *
+ * Error conditions will only occur in the FIFO, these will
+ * trigger an immediate interrupt and stop the DMA job, so we
+ * will always find the error in the FIFO, never in the DMA
+ * buffer.
+ */
+ test_uart_static(zup->port.line, NULL, 0, 7);
+ fifotaken = zx29_uart_fifo_to_tty(zup);
+ }
+ if((pending > 0) || (fifotaken > 0)) {
+ spin_unlock(&zup->port.lock);
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock(&zup->port.lock);
+ }
+}
+static void zx29_uart_deal_dma_fifo_rx_chars_cyclic(struct zx29_uart_port *zup,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ unsigned long *flags, char *fifo_buf, int fifo_len)
+{
+ struct tty_struct *tty = zup->port.state->port.tty;
+ struct device *dev = zup->dmarx.chan->device->dev;
+ int dma_count = 0;
+ int fifo_count = 0;
+ u32 fifotaken = 0; /* only used for vdbg() */
+ if ((pending) && (pending != 4096)) {
+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ sgbuf->buf, pending);
+ test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
+#if UART_DEBUG_RECORDER_BYTE
+ uart_debug(sgbuf->buf, pending);
+#endif
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+ if(fifo_len){
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ fifo_count = tty_insert_flip_string(&zup->port.state->port,
+ fifo_buf, fifo_len);
+ test_uart_static(zup->port.line, fifo_buf, fifo_len, 50);
+#if UART_DEBUG_RECORDER_BYTE
+ uart_debug(fifo_buf, fifo_len);
+#endif
+ fifo_buf[0] = '\0';
+ fifo_buf[1] = '\0';
+ fifo_buf[2] = '\0';
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ }
+ zup->port.icount.rx += fifo_count;
+ if(((pending) && (pending != 4096)) || (fifo_len > 0)){
+ spin_unlock(&zup->port.lock);
+ tty_flip_buffer_push(&zup->port.state->port);
+ test_uart_static(zup->port.line, NULL, (fifo_count+dma_count), 51);
+ spin_lock(&zup->port.lock);
+ }
+}
+
+static void zx29_uart_deal_dma_fifo_rx_chars(struct zx29_uart_port *zup,
+ u32 pending, struct zx29_sgbuf *sgbuf,
+ unsigned long *flags, char *fifo_buf, int fifo_len)
+{
+ struct tty_struct *tty = zup->port.state->port.tty;
+
+ struct device *dev = zup->dmarx.chan->device->dev;
+ int dma_count = 0;
+ int fifo_count = 0;
+ u32 fifotaken = 0; /* only used for vdbg() */
+ if (pending) {
+ dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ dma_count = tty_insert_flip_string(&zup->port.state->port,
+ sgbuf->buf, pending);
+ test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
+ spin_unlock_irqrestore(&zup->port.lock, *flags);
+ zup->port.icount.rx += dma_count;
+ if (dma_count < pending)
+ dev_info(zup->port.dev,
+ "couldn't insert all characters (TTY is full?)\n");
+ }
+
+ if(fifo_len){
+ //printk("qq >> fifo len %d.\n",fifo_len);
+ fifo_count = tty_insert_flip_string(&zup->port.state->port,
+ fifo_buf, fifo_len);
+ //printk("qq >>fifo count %d,buf is %x %x %x .\n",fifo_count, fifo_buf[0],fifo_buf[1],fifo_buf[2]);
+ fifo_buf[0] = '\0';
+ fifo_buf[1] = '\0';
+ fifo_buf[2] = '\0';
+ //memset(fifo_buf, '\0', 4);
+ }
+
+ zup->port.icount.rx += fifo_count;
+ test_uart_static(zup->port.line, fifo_buf, fifo_count, 18);
+ if(pending > 0 || (fifo_len > 0)){
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock_irqsave(&zup->port.lock, *flags);
+ }
+}
+
+#if 0
+static void zx29_dma_rx_irq(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ struct zx29_sgbuf *sgbuf = dmarx->use_buf_b ?
+ &dmarx->sgbuf_b : &dmarx->sgbuf_a;
+ size_t pending;
+ struct dma_tx_state state;
+ enum dma_status dmastat;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+
+ uint32_t ris_status = UART_GET_RIS(&zup->port);
+ //printk("rx irq\n");
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+
+ if(zx29_dma_rx_running(zup)){
+ /*
+ * Pause the transfer so we can trust the current counter,
+ * do this before we pause the block, else we may
+ * overflow the FIFO.
+ */
+ // if(zx29_dma_stop(rx_id))
+ // printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ //zx29_dma_force_stop(rx_id);
+ //dmaengine_terminate_all(rxchan);
+
+ //dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
+
+ /* Disable RX DMA - incoming data will wait in the FIFO */
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
+ BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
+ /* Then we terminate the transfer - we now know our residue */
+ //dmaengine_terminate_all(rxchan);
+
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ /*
+ * This will take the chars we have so far and insert
+ * into the framework.
+ */
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, false, flags);
+ }
+
+ /* Switch buffer & re-trigger DMA job */
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("uart%d could not retrigger RX DMA job\n",zup->port.line);
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ }
+#if RX_DMA_WORK
+ //printk("add timer\n");
+ else{
+ // mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
+ uart_mod_timer(zup, flags);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+#endif
+
+}
+#endif
+/****************************************************************************/
+static void zx29_uart_rx_dma_chars(struct zx29_uart_port *zup, unsigned long *flags)
+{
+
+ struct tty_struct *tty = zup->port.state->port.tty;
+ //zx29_uart_fifo_to_tty(zup);
+// spin_unlock(&zup->port.lock);
+ if (zx29_dma_rx_available(zup)) {
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM | UART_RTIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }
+#if RX_DMA_WORK
+//printk("add timer\n");
+ else{
+ //mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
+ uart_mod_timer(zup, flags);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+#endif
+ }
+
+ //tty_flip_buffer_push(tty);
+ //spin_lock(&zup->port.lock);
+}
+
+
+/****************************************************************************/
+static void zx29_uart_rx_timeout_chars(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ int rt_cnt = 0;
+// unsigned long flags;
+
+ int fr = UART_GET_FR(&zup->port);
+ //printk("rx_timeout_chars\n");
+
+ rt_cnt = zx29_uart_fifo_to_tty(zup);
+ if(rt_cnt){
+ if(g_console_open_flag == 1 || zup->port.line != DEBUG_CONSOLE){
+ spin_unlock(&zup->port.lock);
+ tty_flip_buffer_push(&zup->port.state->port);
+ spin_lock(&zup->port.lock);
+ }
+ }
+}
+
+static void zx29_uart_rt_dma(struct zx29_uart_port *zup, unsigned long *flags)
+{
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ struct zx29_sgbuf *sgbuf = zup->curr_sg;
+ size_t pending;
+ struct dma_tx_state state;
+ enum dma_status dmastat;
+
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ uint32_t ris_status = UART_GET_RIS(&zup->port);
+
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //printk("---zx29_uart_rt_dma, pending:%d, residue:%d\n", pending, state.residue);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ // if(!uart_console(&zup->port))
+ //BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+
+ if(zx29_dma_rx_running(zup)){
+ /*
+ * Pause the transfer so we can trust the current counter,
+ * do this before we pause the block, else we may
+ * overflow the FIFO.
+ */
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ //printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
+ //dmastat = rxchan->device->device_tx_status(rxchan,
+ // dmarx->cookie, &state);
+ // dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
+
+ //zx29_dma_force_stop(rx_id);
+ //dmaengine_terminate_all(rxchan);
+
+ /* Disable RX DMA - incoming data will wait in the FIFO */
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ zup->curr_sg = zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
+
+ //printk("---zx29_uart_rt_dma, after stop pending:%d, residue:%d\n", pending, state.residue);
+ BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
+ /* Then we terminate the transfer - we now know our residue */
+ //dmaengine_terminate_all(rxchan);
+
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ wmb();
+ /*
+ * This will take the chars we have so far and insert
+ * into the framework.
+ */
+ test_uart_static(zup->port.line, NULL, 0, 5);
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, flags);
+ }
+
+#if 0
+//printk("rt dma\n");
+ /* Switch buffer & re-trigger DMA job */
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("zx29_dma_rx_trigger_dma fail,uart:%d\n", zup->port.line);
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ }
+#if RX_DMA_WORK
+ //printk("add timer\n");
+ else{
+ //mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
+ uart_mod_timer(zup, flags);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ zup->dmarx.used = true;
+ }
+#endif
+
+#endif
+
+}
+char g_fifo_residue_buf[5][4];
+char g_fifo_residue_all[5][20];
+unsigned char g_fifo_cnt[5];
+static void zx29_uart_rx_dma_timeout(struct timer_list *t)
+{
+ struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_timer);
+
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ static bool dma_timeout_flag = false;
+ size_t pending, tmp_len;
+ uint32_t ris_status = 0;
+ int cancel_timer = 0;
+ int sg_idx = (dmarx->use_buf_b ? 1 : 0);
+
+ unsigned long flags;
+ struct zx29_sgbuf *sgbuf = NULL;
+ int uart_id = zup->port.line;
+ if(!zx29_dma_rx_running(zup))
+ //printk("---uart_rx_dma_timeout enter, dma stopped\n");
+ return;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ if(zup->port_close || (zup->curr_sg == NULL)){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return;
+ }
+ //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
+ if(zup->sg2tty) {//dma complete now, later check again
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 14);
+ mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ return;
+ }
+ sgbuf = zup->curr_sg;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ //printk("---uart_rx_dma_timeout enter,sg.length:%d, pending:%d, state.residue:%d\n", sgbuf->sg.length, pending, state.residue);
+ if(pending == zup->pre_pending){
+ int fr = UART_GET_FR(&zup->port);
+ //if RXBUSY,means data come again
+
+ if((fr & UART_FR_RXBUSY)){
+
+ uart_mod_timer(zup, &flags);
+ test_uart_static(zup->port.line, NULL, 0, 12);
+ goto deal_end;
+
+ }
+
+ ris_status = UART_GET_RIS(&zup->port);
+
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 1;
+ test_uart_static(zup->port.line, NULL, 0, 19);
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(tmp_len != pending){
+ pending = tmp_len;
+ }
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ wmb();
+ if(zup->uart_power_mode){
+ int i;
+ for(i= 0;i < 3;i++){
+ fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXFE) == 0){
+ g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+ else
+ break;
+ }
+ if(i){
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+
+ //zup->sg2tty = sgbuf;
+ //when app ctrl sleep ,always start dma receive
+ if(zup->sleep_state == 0){
+ //now start dma again
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ uart_mod_timer(zup, &flags);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ }
+ if(pending || (i > 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
+ }
+
+ }else{
+ //for normal mode, dma start only on rx busy after timeout came
+ if(pending || (( fr & UART_FR_RXFE) == 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
+ }
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ zup->pre_pending = 0;
+ zup->work_state = false;
+ if((UART_GET_RIS(&zup->port) & (UART_RXIS | UART_RTIS)) ||
+ (UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
+ zup->imr &= ~(UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ uart_mod_timer(zup, &flags);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
+ }
+ }
+
+ }
+deal_end:
+
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ }else{
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ zup->pre_pending = pending;
+ mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ //uart_mod_timer(zup, &flags);
+ }
+
+
+}
+enum hrtimer_restart zx29_uart_rx_dma_hrtimeout(struct hrtimer *t)
+{
+ struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ static bool dma_timeout_flag = false;
+ size_t pending, tmp_len;
+ uint32_t ris_status = 0;
+ int cancel_timer = 0;
+ int sg_idx = (dmarx->use_buf_b ? 1 : 0);
+ int uart_id = zup->port.line;
+ unsigned long flags;
+ struct zx29_sgbuf *sgbuf = NULL;
+ if(!zx29_dma_rx_running(zup))
+ return HRTIMER_NORESTART;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ if(zup->port_close || (zup->curr_sg == NULL)){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_NORESTART;
+ }
+ if(zup->sg2tty) {//dma complete now, later check again
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 14);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ if(zup->enter_suspend){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 15);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ sgbuf = zup->curr_sg;
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if((pending == zup->pre_pending)) {
+ int fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXBUSY)){
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, 0, 12);
+ goto deal_end;
+ }
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 1;
+ test_uart_static(zup->port.line, NULL, 0, 19);
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ }
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(tmp_len != pending){
+ pending = tmp_len;
+ }
+ dmarx->use_buf_b = !dmarx->use_buf_b;
+ wmb();
+ if(zup->uart_power_mode){
+ int i;
+ for(i= 0;i < 3;i++){
+ fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXFE) == 0){
+ g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+ else
+ break;
+ }
+ if(i){
+ g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
+ if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
+ }
+ if(zup->sleep_state == 0){
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ }
+ if(pending || (i > 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
+ }
+ }else{
+ if(pending || (( fr & UART_FR_RXFE) == 0)){
+ test_uart_static(zup->port.line, NULL, 0, 13);
+ zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
+ printk("at pending %d.\n",pending);
+ }
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ zup->pre_pending = 0;
+ zup->work_state = false;
+ if((UART_GET_RIS(&zup->port) & (UART_RXIS | UART_RTIS)) ||
+ (UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
+ zup->imr &= ~(UART_RXIM);
+ UART_PUT_IMSC(&zup->port, zup->imr);
+ if (zx29_dma_rx_trigger_dma(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
+ }
+ }
+ }
+deal_end:
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_RESTART;
+ }else{
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ zup->pre_pending = pending;
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
+ return HRTIMER_RESTART;
+ }
+}
+enum hrtimer_restart zx29_uart_rx_dma_hrtimeout_cyclic(struct hrtimer *t)
+{
+ struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
+ struct zx29_dmarx_data *dmarx = &zup->dmarx;
+ struct dma_chan *rxchan = dmarx->chan;
+ size_t pending, tmp_len;
+ uint32_t ris_status = 0;
+ unsigned long flags;
+ struct zx29_sgbuf *sgbuf = NULL;
+ int uart_id = zup->port.line;
+
+
+ if(!zx29_dma_rx_running(zup))
+ return HRTIMER_NORESTART;
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+
+ if((uart_dma_cycle[zup->port.line].cnt_callback > 0) || (uart_dma_cycle[zup->port.line+3].cnt_callback > 0)){
+ test_uart_static(zup->port.line, NULL, uart_dma_cycle[zup->port.line].used, 46);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_NORESTART;
+ }
+
+ if(!uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+
+ sgbuf = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
+ if(zup->port_close || (sgbuf == NULL)){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_NORESTART;
+ }
+ if(zup->sema_cyclic.count > 0){
+ printk("uart has th not deal.\n");
+ //test_uart_static(zup->port.line, NULL, uart_id, 11);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+
+ if((zup->sg2tty)){//dma not complete now, later check again
+ printk("dmath_cyclic not end.\n");
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 14);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ if(zup->enter_suspend || uart_dma_cycle[uart_id].enter_throttle){
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ test_uart_static(zup->port.line, NULL, 0, 15);
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ return HRTIMER_RESTART;
+ }
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(((pending == zup->pre_pending) && pending) || uart_dma_cycle[uart_id].from_resume
+ || uart_dma_cycle[uart_id].from_unthrottle){
+ uart_dma_cycle[uart_id].from_resume = 0;
+ uart_dma_cycle[uart_id].from_unthrottle = false;
+#if 0
+ if(uart_dma_cycle[uart_id].flg_enter_th == 0)
+ uart_dma_cycle[uart_id].flg_enter_to = 4;
+ else
+ uart_dma_cycle[uart_id].flg_enter_to = uart_dma_cycle[uart_id].flg_enter_th - 1;
+ struct zx29_sgbuf *sgbuf_tmp = NULL;
+ sgbuf_tmp = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_to];
+ test_uart_static(zup->port.line, NULL, 0, 61);
+ if (sgbuf->sg.dma_address != (zx29_dma_cur_dst(rx_id)&0xfffff000)){
+ if(sgbuf_tmp->sg.dma_address != ((zx29_dma_cur_dst(rx_id)&0xfffff000)-0x1000)){
+ printk("uart lose dma isr enter self resume.\n");
+ up(&zup->sema_cyclic);
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+ return;
+ }
+ }
+ #endif
+ int fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXBUSY)){
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, 0, 12);
+ goto deal_end;
+ }
+ ris_status = UART_GET_RIS(&zup->port);
+ if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
+ if(ris_status & UART_OEIS){
+ zup->port.icount.overrun++;
+ uart_dma_cycle[uart_id].flg_overrun = 1;
+ }
+ if(ris_status & UART_BEIS)
+ zup->port.icount.brk++;
+ if(ris_status & UART_PEIS)
+ zup->port.icount.parity++;
+ if(ris_status & UART_FEIS)
+ zup->port.icount.frame++;
+ UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
+ printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
+ zup->port.icount.brk,zup->port.icount.parity);
+ }
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ dmaengine_terminate_all(rxchan);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
+ if(tmp_len != pending){
+ pending = tmp_len;
+ //test_uart_static(zup->port.line, NULL, tmp_len, 48);
+ }
+ wmb();
+ int i = 0;
+ for(i= 0;i < 3;i++){
+ fr = UART_GET_FR(&zup->port);
+ if((fr & UART_FR_RXFE) == 0){
+ g_fifo_residue_buf[zup->port.line][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
+ g_fifo_residue_all[zup->port.line][g_fifo_cnt[zup->port.line]++] = g_fifo_residue_buf[zup->port.line][i];
+ if(g_fifo_cnt[zup->port.line] >= 20) g_fifo_cnt[zup->port.line] = 0;
+ }
+ else
+ break;
+ }
+ if(i){
+ g_fifo_residue_all[zup->port.line][g_fifo_cnt[zup->port.line]++]=i;
+ if(g_fifo_cnt[zup->port.line] >= 20) g_fifo_cnt[zup->port.line] = 0;
+ }
+ if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, (pending+i), 49);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ }
+ if((pending && (pending != 4096)) || (i > 0)){
+ zx29_uart_deal_dma_fifo_rx_chars_cyclic(zup, pending, sgbuf, &flags, g_fifo_residue_buf[zup->port.line],i);
+ }
+ uart_dma_cycle[uart_id].cnt_th = 0;
+ uart_dma_cycle[uart_id].cnt_callback=0;
+deal_end:
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return HRTIMER_RESTART;
+ }else{
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ zup->pre_pending = pending;
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
+ return HRTIMER_RESTART;
+ }
+}
+#endif
+
+
+static void zx29_uart_modem_status(struct zx29_uart_port *zup)
+{
+ unsigned int status, delta;
+
+ status = UART_GET_FR(&zup->port)& UART_FR_MODEM_ANY;
+
+ delta = status ^ zup->old_status;
+ zup->old_status = status;
+
+ if (!delta)
+ return;
+
+ if (delta & UART_FR_DCD)
+ uart_handle_dcd_change(&zup->port, status & UART_FR_DCD);
+
+ if (delta & UART_FR_DSR)
+ zup->port.icount.dsr++;
+
+ if (delta & UART_FR_CTS)
+ uart_handle_cts_change(&zup->port, status & UART_FR_CTS);
+
+ wake_up_interruptible(&zup->port.state->port.delta_msr_wait);
+}
+
+/****************************************************************************/
+static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id)
+{
+ struct uart_port *port = (struct uart_port *)dev_id;
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ unsigned int status,ris, pass_counter = 256;
+ int handled = 0;
+ int uart_id = zup->port.line;
+ spin_lock_irqsave(&zup->port.lock, flags);
+ status = UART_GET_MIS(port) & zup->imr;
+ ris = UART_GET_RIS(port);
+ if (status) {
+ do {
+ UART_PUT_ICR(port,(status & ~(UART_TXIS|UART_RTIS|UART_RXIS)));
+ if(uart_console(&zup->port)){
+ if (status & (UART_RTIS|UART_RXIS))
+ zx29_uart_rx_chars(zup);
+ }else{
+#ifdef CONFIG_CPU_IDLE
+ zup->rxd_int_depth = 0;
+#endif
+ if (status & (UART_RXIS)){
+#if CONFIG_SERIAL_ZX29_DMA
+ if(ris & UART_OEIS){
+ zup->port.icount.overrun++;
+ g_uart_overrun[uart_id] = 8;
+ test_uart_static(zup->port.line, NULL, 0, 21);
+ //if(!uart_console(&zup->port))
+ // BUG_ON(1);
+ }
+ if (zx29_dma_rx_used(zup)){
+ UART_PUT_ICR(port,UART_RXIS);
+ if(!(zup->imr & UART_RTIM)){
+ zup->imr |= UART_RTIM;
+ UART_PUT_IMSC(port,zup->imr);
+ }
+
+ test_uart_static(port->line, NULL, 0, 8);
+ uart_mod_timer(zup, &flags);
+
+ }else{
+ test_uart_static(port->line, NULL, 0, 1);
+
+ zup->imr &= ~UART_RXIM;
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ zx29_uart_rx_dma_chars(zup, &flags);
+
+ zup->dmarx.used = true;
+ //when RX&RT comes both, we trigger dma and add timer,so clear RT,waiting the timer
+ if(status & (UART_RTIS))
+ status &= ~UART_RTIS;
+ }
+#else
+ zx29_uart_rx_chars(zup);
+#endif
+ }
+
+ if (status & (UART_RTIS)){
+#if CONFIG_SERIAL_ZX29_DMA
+ if(!zx29_dma_rx_running(zup)){
+ test_uart_static(port->line, NULL, 0, 2);
+ zx29_uart_rx_timeout_chars(zup, &flags);
+ }else{
+ UART_PUT_ICR(port, UART_RTIS);
+ test_uart_static(port->line, NULL, 0, 4);
+ zx29_uart_rt_dma(zup, &flags);
+ }
+#else
+ zx29_uart_rx_chars(zup);
+#endif
+ }
+ }
+
+ if (status & (UART_DSRMIS|UART_DCDMIS|UART_CTSMIS|UART_RIMIS))
+ zx29_uart_modem_status(zup);
+
+ if (status & UART_TXIS)
+ zx29_uart_tx_chars(zup);
+
+ if (pass_counter-- == 0)
+ break;
+
+ status = UART_GET_MIS(port);
+ } while (status != 0);
+ handled = IRQ_HANDLED;
+ }
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+
+ return IRQ_RETVAL(handled);
+}
+
+#if CONFIG_SERIAL_ZX29_DMA
+extern bool zx29_dma_filter_fn(struct dma_chan *chan, void *param);
+static void uart_dma_init(struct zx29_uart_port *zup)
+{
+ int i=0;
+ struct dma_chan *chan = NULL;
+
+ atomic_set(&zup->dmarx.count, 1);
+ atomic_set(&zup->dmatx.count, 1);
+#if 1
+ if(zup->port.line == UART0)
+ {
+ zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART0_BASE +zx29_UART_DR);
+ }
+ else if(zup->port.line == UART1)
+ {
+ zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART1_BASE+zx29_UART_DR);
+ }
+ else if(zup->port.line == UART2)
+ {
+ zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART2_BASE+zx29_UART_DR);
+ }
+
+ zup->dmatx.tx_def.dma_control.tran_mode = TRAN_MEM_TO_PERI;
+ zup->dmatx.tx_def.dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ zup->dmatx.tx_def.dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmatx.tx_def.dma_control.src_burst_len = DMA_BURST_LEN_4;
+ zup->dmatx.tx_def.dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmatx.tx_def.dma_control.dest_burst_len = DMA_BURST_LEN_4;
+
+ dma_cap_mask_t mask;
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ if(zup->port.line == UART0)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_TX);
+ }
+ else if(zup->port.line == UART1)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_TX);
+ }
+ else if(zup->port.line == UART2)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_TX);
+ }
+ if(!chan){
+ printk("UART%d DMA TX channel request fail.\n", zup->port.line);
+ return;
+ }
+ zup->dmatx.chan = chan;
+
+
+
+ for(i=0;i<UART_DMA_RX_MAX_COUNT;i++)
+ {
+ if(zup->port.line == UART0)
+ {
+ zup->dmarx.rx_def[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
+ }
+ else if(zup->port.line == UART1)
+ {
+ zup->dmarx.rx_def[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
+ }
+ else if(zup->port.line == UART2)
+ {
+ zup->dmarx.rx_def[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
+ }
+
+ zup->dmarx.rx_def[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
+ zup->dmarx.rx_def[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ zup->dmarx.rx_def[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmarx.rx_def[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
+ zup->dmarx.rx_def[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ zup->dmarx.rx_def[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
+ }
+
+ zup->dmarx.rx_index = 0;
+ chan = NULL;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ if(zup->port.line == UART0)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_RX);
+ }
+ else if(zup->port.line == UART1)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_RX);
+ }
+ else if(zup->port.line == UART2)
+ {
+ chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_RX);
+ }
+ if(!chan){
+ printk("UART%d DMA RX channel request fail.\n", zup->port.line);
+ return;
+ }
+ zup->dmarx.chan = chan;
+#endif
+}
+
+static int uart_dma_cycle_init(struct zx29_uart_port *zup)
+{
+ int ret;
+ int uart_id = zup->port.line;
+ uart_dma_cycle[uart_id].id = zup->port.line;
+ int i,j;
+ for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
+ if(ret){
+ printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", zup->port.line, ret);
+ for(j=0;j<i;j++){
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[j],DMA_FROM_DEVICE);
+ }
+ return -1;
+ }
+
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[i],DMA_FROM_DEVICE);
+ if(ret){
+ printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", (zup->port.line+3), ret);
+ for(j=0;j<i;j++){
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[j],DMA_FROM_DEVICE);
+ }
+ return -1;
+ }
+ }
+ for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
+ if(zup->port.line == UART0){
+ uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id].used = false;
+ uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id+3].used = false;
+ }
+ else if(zup->port.line == UART1){
+ uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id].used = false;
+ uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id+3].used = false;
+ }
+ else if(zup->port.line == UART2){
+ uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id].used = false;
+ uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
+ uart_dma_cycle[uart_id+3].used = false;
+ }
+ uart_dma_cycle[uart_id].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id].sgbuf[i].dma_addr);
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ uart_dma_cycle[uart_id].rxdef[i].link_addr = 1;
+
+ uart_dma_cycle[uart_id+3].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id+3].sgbuf[i].dma_addr);
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id+3].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
+ uart_dma_cycle[uart_id+3].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
+ uart_dma_cycle[uart_id+3].rxdef[i].link_addr = 1;
+
+ }
+ return 0;
+}
+static void uart_dma_cycle_deinit(struct zx29_uart_port *zup)
+{
+ int i;
+ int uart_id = zup->port.line;
+ for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
+ zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[i],DMA_FROM_DEVICE);
+ }
+ memset(uart_dma_cycle[uart_id].rxdef, 0, sizeof(uart_dma_cycle[uart_id].rxdef));
+ memset(uart_dma_cycle[uart_id+3].rxdef, 0, sizeof(uart_dma_cycle[uart_id+3].rxdef));
+}
+static void uart_dma_startup(struct zx29_uart_port *zup)
+{
+ int ret = 0;
+ if (!zup->dmatx.chan)
+ {
+ printk("tx_chan is error[%s][%d]\n",__func__,__LINE__);
+ return;
+ }
+
+ zup->dmatx.buf = kmalloc(ZX29_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
+ if (!zup->dmatx.buf) {
+ printk("tx_buf is error[%s][%d]\n",__func__,__LINE__);
+ return;
+ }
+
+ sg_init_one(&zup->dmatx.sg, zup->dmatx.buf, ZX29_DMA_BUFFER_SIZE);
+
+ /* The DMA buffer is now the FIFO the TTY subsystem can use */
+ zup->port.fifosize = 16;//ZX29_DMA_BUFFER_SIZE;
+ zup->using_tx_dma = true;
+
+ if(!zup->uart_power_mode)
+ {
+ if (!zup->dmarx.chan)
+ {
+ printk(KERN_INFO "[%s][%d]uart_%d rx_chan is error\n",__func__,__LINE__, zup->port.line);
+ goto skip_rx;
+ }
+
+ /* Allocate and map DMA RX buffers */
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
+ DMA_FROM_DEVICE);
+ if (ret) {
+ printk(KERN_INFO "[%s][%d] uart_%d rx_buf_a is error\n",__func__,__LINE__, zup->port.line);
+ //dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
+ // "RX buffer A", ret);
+ goto skip_rx;
+ }
+
+ ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_b,
+ DMA_FROM_DEVICE);
+ if (ret) {
+ printk( "failed to init DMA uart: %d RX buffer B ,ret:%d\n", zup->port.line, ret);
+ zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
+ DMA_FROM_DEVICE);
+ goto skip_rx;
+ }
+
+ zup->using_rx_dma = true;
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->curr_sg = NULL;
+#if RX_DMA_WORK
+ timer_setup(&(zup->rx_dma_timer), zx29_uart_rx_dma_timeout, 0);
+ hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout;
+ g_hr_interval = ktime_set(0, 1500000);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ zup->dmarx.use_buf_b = false;
+ zup->dmarx.rx_index = 0;
+
+ zup->pre_pending = 0;
+ zup->work_state = false;
+
+ zup->dma_compl_th = kthread_run(dma_complete_thread, zup, "uart_dma_compl");
+ BUG_ON(IS_ERR(zup->dma_compl_th));
+#endif
+
+skip_rx:
+
+ /* Turn on DMA error (RX/TX will be enabled on demand) */
+ printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
+ zup->dmacr &= ~UART_DMAONERR;
+ //zup->dmacr |= UART_DMAONERR;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ if(zup->uart_power_mode){
+ if (zup->using_rx_dma) {
+ //printk(KERN_INFO "[%s][%d]\n",__func__,__LINE__);
+ if (zx29_dma_rx_trigger_dma(zup)){
+ dev_dbg(zup->port.dev, "could not trigger initial "
+ "RX DMA job, fall back to interrupt mode\n");
+ }else{
+ mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+ }
+ }
+ }
+ else if(zup->uart_power_mode == 1)
+ {
+ ret = uart_dma_cycle_init(zup);
+ if(ret){
+ printk("uart%d dma cycle init failed,ret %d.\n",zup->port.line,ret);
+ return;
+ }
+ zup->using_rx_dma = true;
+ zup->sg2tty = NULL;
+ zup->sg2tty_len = 0;
+ zup->curr_sg = NULL;
+#if RX_DMA_WORK
+ hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout_cyclic;
+ g_hr_interval = ktime_set(0, 1500000);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ zup->dmarx.use_buf_b = false;
+ zup->dmarx.rx_index = 0;
+ zup->pre_pending = 0;
+ zup->work_state = false;
+ sema_init(&zup->sema_cyclic, 0);
+ zup->dma_compl_th = kthread_run(dma_complete_thread_use_dma_cyclic, zup, "uart_dma_th_cyc");
+ BUG_ON(IS_ERR(zup->dma_compl_th));
+#endif
+ printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
+ zup->dmacr &= ~UART_DMAONERR;
+ UART_PUT_DMACR(&zup->port, zup->dmacr);
+ if(zup->uart_power_mode){
+ if (zup->using_rx_dma) {
+ if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)){
+ dev_dbg(zup->port.dev, "could not trigger initial "
+ "RX DMA job, fall back to interrupt mode\n");
+ }else{
+ hrtimer_start(&zup->rx_dma_hrtimer, g_hr_interval, HRTIMER_MODE_REL);
+ //mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
+ zup->pre_pending = 0;
+ zup->work_state = true;
+ }
+ }
+ }
+ }else
+ printk("uart%d power mode set error,dma dont startup.\n",zup->port.line);
+}
+
+
+#endif
+
+static irqreturn_t zx29_uart_rxd_irq(int irq, void *dev_id)
+{
+ struct zx29_uart_port *zup = (struct zx29_uart_port *)dev_id;
+
+ rxd_wake_cnt++;
+ zup->rxd_wakeup = true;
+ tasklet_schedule(&zup->write_wakeup);
+ zup->rxd_int_depth = 0;
+ return IRQ_HANDLED;//IRQ_RETVAL(retval);
+}
+
+/****************************************************************************/
+static int zx29_uart_startup(struct uart_port *port)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags = 0;
+ unsigned long control = 0;
+ int retval = 0;
+ struct platform_device *pdev=port->private_data;
+// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ int i = 0,j = 0,iflag = 0;
+ struct tty_struct *tty = port->state->port.tty;
+ unsigned int ibrd, fbrd,lcr_h, old_cr;
+ int ret=0;
+ printk("-----zx29_uart_startup, port:%d\n", port->line);
+ #if 0//def CONFIG_ARCH_ZX297520V3_WATCH
+
+ if(port->line == 0)
+ {
+ gpio_free(pdata->uart_txd.gpionum);
+ gpio_free(pdata->uart_rxd.gpionum);
+ //printk("gpio_free err err!\n");
+ }
+
+ wmb();
+
+ #endif
+ if(DEBUG_CONSOLE != pdev->id){
+ char temp_buf[TASK_COMM_LEN]= {0};
+ int th_ctrl = 0;
+ if((strlen(get_task_comm(temp_buf,get_current())) > 0) && (strcmp(get_task_comm(temp_buf,get_current()),"at_ctl") != 0))
+ th_ctrl = 1;
+
+ //app ctrl or kernel ctrl set this
+ int kernel_ctrl = xp2xp_enable_4line();
+ zup->uart_power_mode = (kernel_ctrl | zup->app_ctrl | th_ctrl);
+ printk("zx29_uart%d open task is %s,power_mode is %d.\n",pdev->id, get_task_comm(temp_buf,get_current()),zup->uart_power_mode);
+ if(zup->uart_power_mode){
+ //pm_stay_awake(&pdev->dev);
+ }
+ }
+ //when open, clear last statistic info
+ port->icount.brk = port->icount.buf_overrun = port->icount.frame = 0;
+ port->icount.overrun = port->icount.parity = port->icount.rng = 0;
+ port->icount.rx = port->icount.tx = 0;
+ /*
+ *enable uart clock
+ *if uart is used for console, don't need do these, these was done before
+ */
+ if (DEBUG_CONSOLE != port->line) {
+ /* config uart apb_clk */
+ clk_prepare_enable(zup->busclk);
+ /* enable uart work clock */
+ clk_prepare_enable(zup->wclk);
+ }
+
+ /* Clear all pending error and receive interrupts */
+ UART_PUT_ICR(port, 0xfff);
+
+ /* Allocate the IRQ */
+ retval = request_irq(port->irq, zx29_uart_interrupt, 0, "uart-zx29", zup);
+ if (retval){
+ printk("[UART]unable to attach zx29 UART %d "
+ "interrupt vector=%d\n", port->line, port->irq);
+ return retval;
+ }
+
+ /* set interrupt fifo level RX:1/2 Full, TX:1/2 Full */
+#if 0//CONFIG_SERIAL_ZX29_DMA
+ UART_PUT_IFLS(port, UART_IFLS_RX2_8|UART_IFLS_TX6_8);
+#else
+ UART_PUT_IFLS(port, UART_IFLS_RX2_8|UART_IFLS_TX4_8);
+#endif
+
+#if 0
+ /* Provoke TX FIFO interrupt into asserting. */
+ control = UART_CR_UARTEN | UART_CR_TXE | UART_CR_LBE;
+ UART_PUT_CR(port, control);
+ UART_PUT_FBRD(port, 0);
+ UART_PUT_IBRD(port, 1);
+ UART_PUT_LCRH(port, 0);
+ UART_PUT_CHAR(port, 0);
+ while (UART_GET_FR(port) & UART_FR_TXBUSY)
+ barrier();
+#endif
+ control = UART_CR_UARTEN | UART_CR_RXE | UART_CR_TXE;
+ //console & lp_uart don't need dma
+ if ((DEBUG_CONSOLE != port->line) && (port->line != 4)) {
+#if CONFIG_SERIAL_ZX29_DMA
+ UART_PUT_DMACR(port, UART_TXDMAE | UART_RXDMAE);
+ uart_dma_startup(zup);
+#endif
+ }
+
+ tasklet_init(&zup->write_wakeup, uart_write_wakeup_task, (unsigned long) port);
+ if((pdev->id == 0) && (zup->irq_state == 0) && (zup->uart_power_mode == 0)){
+ ret = request_irq(zup->rxd_irq,
+ zx29_uart_rxd_irq,
+ 0,
+ "uart0_rxd_wake",
+ zup);
+ if(ret<0){
+ panic("request uart0 rxd wake irq fail\n");
+ }
+ printk("--------rxd wake up interrupt ok\n");
+ enable_irq_wake(zup->rxd_irq);
+ zup->irq_state = 1;
+ zup->rxd_int_depth = 1;
+ }
+#if 0
+ /*configure gpio pin to UART*/
+ if((pdata->uart_use)/*&&(port->line == UART0 )*/)
+ {
+ retval=gpio_request(pdata->uart_rxd.gpionum,pdata->uart_rxd.gpioname);
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_txd.gpioname);
+ if(retval)
+ BUG();
+ /*uart rxd*/
+ zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
+ if(pdata->uart_rxd.gpionum == ZX29_GPIO_121 ) {
+ //pull up gpio121
+ *(volatile unsigned int *)0xf843c82c |= 0xf0;
+ }
+ /*uart txd*/
+ zx29_gpio_config(pdata->uart_txd.gpionum, pdata->uart_txd.gpiofnc);
+#ifdef CONFIG_ARCH_ZX297520V3
+ if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 0)){
+ zup->irq = platform_get_irq_byname(pdev, "zx29_uart_rxd_wakeup");
+ printk(KERN_INFO"zx29_uart_startup,irq:%d,%s.%d\n",zup->irq,pdata->uart_cts.gpioname,zup->irq_state);
+ if(zup->irq >= 0){
+
+ pcu_int_set_type(PCU_UART0_RXD_INT, IRQF_TRIGGER_FALLING);
+ pcu_int_clear(PCU_UART0_RXD_INT);
+ ret = request_irq(zup->irq, zx29_uart_rxd_irq,
+ IRQF_ONESHOT , "uart_rxd_irq",
+ zup);
+ printk(KERN_INFO"zx29_uart_startup, retval:%d\n",ret);
+ irq_set_irq_wake(zup->irq,1);
+#ifdef CONFIG_CPU_IDLE
+ zup->rxd_int_depth = rxd_wake_cnt = 0;
+ zx_pm_register_callback(uart_0_pm_enter, uart_0_pm_exit);
+ disable_irq_nosync(UART0_RXD_INT);
+#endif
+ zup->irq_state = 1;
+ }else{
+ printk("uart_startup, request wake irq fail:%d\n",zup->irq);
+ }
+ }
+#endif
+ if(pdata->uart_ctsrtsuse)
+ {
+ retval=gpio_request(pdata->uart_cts.gpionum,pdata->uart_cts.gpioname);
+ if(retval)
+ BUG();
+
+ retval=gpio_request(pdata->uart_rts.gpionum,pdata->uart_rts.gpioname);
+ if(retval)
+ BUG();
+/*uart cts*/
+ zx29_gpio_config(pdata->uart_cts.gpionum, pdata->uart_cts.gpiofnc);
+/*uart rts*/
+ zx29_gpio_config(pdata->uart_rts.gpionum, pdata->uart_rts.gpiofnc);
+
+ control |= (UART_CR_RTSEN |UART_CR_CTSEN );
+ control |= UART_CR_RTS; //wl write1 for allow send
+ }
+ zup->autobaud = pdata->uart_abauduse ;
+ }
+#if 0
+ if((pdata->uart_use)&&(port->line == UART1 ))
+ {
+ retval=gpio_request(pdata->uart_rx.gpionum,pdata->uart_rx.gpioname);
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_tx.gpioname);
+ if(retval)
+ BUG();
+/*uart rxd*/
+ zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
+/*uart txd*/
+ zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
+
+ if(pdata->uart_ctsrtsuse)
+ {
+ retval=gpio_request(pdata->uart_ctsnum,"uart1_cts");
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_rtsnum,"uart1_rts");
+ if(retval)
+ BUG();
+/*uart cts*/
+ zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
+/*uart rts*/
+ zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
+
+ control |= (UART_CR_RTSEN |UART_CR_CTSEN );
+ control |= UART_CR_RTS; //wl write1 for allow send
+ }
+ zup->autobaud = pdata->uart_abauduse;
+ }
+ if((pdata->uart_use)&&(port->line == UART2 ))
+ {
+ retval=gpio_request(pdata->uart_rxdnum,"uart2_rxd");
+ if(retval)
+ BUG();
+ retval=gpio_request(pdata->uart_txdnum,"uart2_txd");
+ if(retval)
+ BUG();
+
+/*uart rxd*/
+ zx29_gpio_config(pdata->uart_rxdnum, pdata->uart_rxdfnc);
+ if(pdata->uart_rxdnum == ZX29_GPIO_121 ) {
+ //pull up gpio121
+ *(volatile unsigned int *)0xf843c82c |= 0xf0;
+ }
+/*uart txd*/
+ zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
+
+ if(pdata->uart_ctsrtsuse)
+ {
+ retval=gpio_request(pdata->uart_ctsnum,"uart2_cts");
+ if(retval)
+ BUG();
+
+ retval=gpio_request(pdata->uart_rtsnum,"uart2_rts");
+ if(retval)
+ BUG();
+/*uart cts*/
+ zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
+/*uart rts*/
+ zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
+
+ control |= (UART_CR_RTSEN |UART_CR_CTSEN );
+ control |= UART_CR_RTS; //wl write1 for allow send
+ }
+ zup->autobaud = pdata->uart_abauduse ;
+ }
+#endif
+#endif
+ zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
+ UART_PUT_CR(port, control);
+
+ /*
+ * Finally, enable interrupts, only timeouts when using DMA
+ * if initial RX DMA job failed, start in interrupt mode
+ * as well.
+ */
+ spin_lock_irqsave(&zup->port.lock, flags);
+ /* Clear out any spuriously appearing RX interrupts */
+ UART_PUT_ICR(port, (UART_RTIS | UART_RXIS));
+ //when dma not running,set UART_RTIM | UART_RXIM
+ if(!zx29_dma_rx_running(zup)){
+ zup->imr = UART_RTIM | UART_RXIM;
+ UART_PUT_IMSC(port, zup->imr);
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ zup->port_close = false;
+#endif
+ spin_unlock_irqrestore(&zup->port.lock, flags);
+
+
+ return 0;
+}
+
+/****************************************************************************/
+static void zx29_uart_shutdown(struct uart_port *port)
+{
+ printk("zx29_uart%d_shutdown.\n",port->line);
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ uint32_t val;
+ int retval = 0;
+ struct platform_device *pdev=port->private_data;
+ //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+#if CONFIG_SERIAL_ZX29_DMA
+ zup->port_close = true;
+ if(zup->uart_power_mode)
+ up(&zup->sema_cyclic);
+ else
+ up(&zup->sema);
+#endif
+ int ret;
+ tasklet_kill(&zup->write_wakeup);
+#if RX_DMA_WORK
+ if(zx29_dma_rx_work_scheduled(zup)){
+ ret = del_timer_sync(&(zup->rx_dma_timer));
+ ret = hrtimer_cancel(&zup->rx_dma_hrtimer);
+ zup->work_state = 0;
+ }
+#endif
+ /* Disable and clear all interrupts now */
+ spin_lock_irqsave(&port->lock, flags);
+ zup->imr = 0;
+ UART_PUT_IMSC(port, zup->imr);
+ UART_PUT_ICR(port, 0xFFFF);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_shutdown(zup);
+#endif
+ /* Free the interrupt */
+ free_irq(zup->port.irq, zup);
+
+ /* Disable UART transmitter and receiver */
+ zup->autorts = false;
+ val = UART_GET_CR(port);
+ if (val & UART_CR_RTS) {
+ zup->rts_state = true;
+ val = UART_CR_RTS;
+ } else
+ zup->rts_state = false;
+ val = UART_CR_UARTEN | UART_CR_TXE;
+ UART_PUT_CR(port, val);
+
+ /* disable break condition and fifos */
+ val = UART_GET_LCRH(port);
+ val &= ~(UART_LCRH_BRK | UART_LCRH_FEN);
+ UART_PUT_LCRH(port, val);
+ if(zup->uart_power_mode){
+ //pm_relax(&pdev->dev);
+ zup->app_ctrl = 0;
+ zup->uart_power_mode = 0;
+ }
+
+ if((pdev->id == 0) && (zup->irq_state == 1) && (zup->uart_power_mode == 0)){
+ free_irq(zup->rxd_irq, zup);
+ disable_irq_wake(zup->rxd_irq);
+ zup->irq_state = 0;
+ }
+
+#if 0
+ if(pdata->uart_use)
+ {
+ if(pdata->uart_ctsrtsuse)
+ {
+ gpio_free(pdata->uart_cts.gpionum);
+ gpio_free(pdata->uart_rts.gpionum);
+ }
+#ifdef CONFIG_ARCH_ZX297520V3
+ if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 1)){
+ printk(KERN_INFO"zx29_uart_shutdown,irq:%d,%s\n",zup->irq,pdata->uart_cts.gpioname);
+ if(zup->irq){
+ free_irq(zup->irq, zup);
+ pcu_int_clear(PCU_UART0_RXD_INT);
+ irq_set_irq_wake(zup->irq, 0);
+ zup->irq_state = 0;
+ zup->rxd_int_depth = 0;
+ }
+ }
+#endif
+ gpio_free(pdata->uart_rxd.gpionum);
+ gpio_free(pdata->uart_txd.gpionum);
+
+#ifdef CONFIG_ARCH_ZX297520V3_WATCH
+ if(port->line == 0)
+ {
+ retval = gpio_request(pdata->uart_txd.gpionum, pdata->uart_txd.gpioname);
+ if(retval)
+ {
+ BUG();
+ }
+ zx29_gpio_config(pdata->uart_txd.gpionum, GPIO30_GPIO30);
+ gpio_direction_input(pdata->uart_txd.gpionum);
+
+ retval = gpio_request(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpioname);
+ if(retval)
+ {
+ BUG();
+ }
+ zx29_gpio_config(pdata->uart_rxd.gpionum, GPIO29_GPIO29);
+ gpio_direction_input(pdata->uart_rxd.gpionum);
+ }
+#endif
+
+ }
+#endif
+ /* Shutdown uart clock */
+}
+
+/****************************************************************************/
+static void zx29_uart_set_termios(struct uart_port *port, struct ktermios *termios,
+ struct ktermios *old)
+{
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned int lcr_h, old_cr;
+ unsigned long flags;
+ unsigned int baud, ibrd, fbrd,j;
+
+ //temple change,using setting from cmm script
+ //if(port->line == DEBUG_CONSOLE)
+ //return;
+
+ /* Set baud rate */
+ /* Ask the core to calculate the divisor for us. */
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ printk("uart port %d baud is %d.\n",port->line,baud);
+
+ //this should not hapend
+ if(baud == 0)
+ BUG_ON(1);
+ zup->baudrate = baud;
+ ibrd = port->uartclk / (baud<<4);
+ fbrd = ((port->uartclk % (baud<<4) )*8 + baud)/(2*baud);
+ UART_PUT_FBRD(port, fbrd);
+ UART_PUT_IBRD(port, ibrd);
+
+printk("-------zx29_uart_set_termios,line:%d, new baud:%d, uartclk:%d,ibrd:%d, fbrd:%d \n", port->line,
+ baud, port->uartclk, ibrd, fbrd);
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ lcr_h = UART_LCRH_WLEN_5;
+ break;
+ case CS6:
+ lcr_h = UART_LCRH_WLEN_6;
+ break;
+ case CS7:
+ lcr_h = UART_LCRH_WLEN_7;
+ break;
+ default: // CS8
+ lcr_h = UART_LCRH_WLEN_8;
+ break;
+ }
+ if (termios->c_cflag & CSTOPB)
+ lcr_h |= UART_LCRH_STP2;
+ if (termios->c_cflag & PARENB) {
+ lcr_h |= UART_LCRH_PEN;
+ if (!(termios->c_cflag & PARODD))
+ lcr_h |= UART_LCRH_EPS;
+ }
+ if (port->fifosize > 1)
+ lcr_h |= UART_LCRH_FEN;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /*
+ * Update the per-port timeout.
+ */
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ port->read_status_mask = UART_DR_OE | 255;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= UART_DR_FE | UART_DR_PE;
+ if (termios->c_iflag & (BRKINT | PARMRK))
+ port->read_status_mask |= UART_DR_BE;
+
+ /*
+ * Characters to ignore
+ */
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART_DR_FE | UART_DR_PE;
+ if (termios->c_iflag & IGNBRK) {
+ port->ignore_status_mask |= UART_DR_BE;
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns too (for real raw support).
+ */
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= UART_DR_OE;
+ }
+
+ /*
+ * Ignore all characters if CREAD is not set.
+ */
+ if ((termios->c_cflag & CREAD) == 0)
+ port->ignore_status_mask |= UART_DUMMY_DR_RX;
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ zx29_uart_enable_ms(port);
+
+ /* first, disable everything */
+ old_cr = UART_GET_CR(port);
+ UART_PUT_CR(port, 0);
+
+ if (termios->c_cflag & CRTSCTS) {
+ if (old_cr & UART_CR_RTS)
+ old_cr |= UART_CR_RTSEN;
+
+ old_cr |= UART_CR_CTSEN;
+ port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
+ zup->autorts = true;
+ } else {
+ old_cr &= ~(UART_CR_CTSEN | UART_CR_RTSEN);
+ zup->autorts = false;
+ port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
+ }
+
+ /*
+ * ----------v----------v----------v----------v-----
+ * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
+ * ----------^----------^----------^----------^-----
+ */
+ UART_PUT_LCRH(port, lcr_h);
+ UART_PUT_CR(port, old_cr);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+ if( zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
+ {
+ msleep(50);
+ zup->port.icount.rx = 0;
+
+ for( j = 0; j<UART_AT_SENDOK_NUM; j++)
+ {
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(&zup->port, UART_AT_send_ok[j]);
+ }
+
+ zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
+ }
+}
+
+/****************************************************************************/
+static const char *zx29_uart_type(struct uart_port *port)
+{
+ return (port->type == PORT_ZX29) ? "zx29_UART" : NULL;
+}
+
+/****************************************************************************/
+
+static int zx29_uart_request_port(struct uart_port *port)
+{
+ /* UARTs always present */
+// return request_mem_region(port->mapbase, SZ_4K, "uart-zx29")!= NULL ? 0 : -EBUSY;
+ return 0;
+}
+
+/****************************************************************************/
+static void zx29_uart_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE) {
+ port->type = PORT_ZX29;
+ zx29_uart_request_port(port);
+ }
+}
+
+/****************************************************************************/
+
+static void zx29_uart_release_port(struct uart_port *port)
+{
+// release_mem_region(port->mapbase, SZ_4K);
+}
+
+/****************************************************************************/
+
+static int zx29_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+ if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ZX29))
+ return -EINVAL;
+ return 0;
+}
+
+
+void zx29_uart_putc(struct uart_port *port, int c)
+{
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, c);
+}
+
+
+#ifdef CONFIG_CONSOLE_POLL
+/****************************************************************************/
+static int zx29_get_poll_char(struct uart_port *port)
+{
+ if (UART_GET_FR(port) & UART_FR_RXFE)
+ return NO_POLL_CHAR;
+
+ return UART_PUT_CHAR(port);
+}
+
+/****************************************************************************/
+static void zx29_put_poll_char(struct uart_port *port, unsigned char ch)
+{
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, ch);
+}
+#endif /* CONFIG_CONSOLE_POLL */
+extern int tty_buffer_space_avail(struct tty_port *port);
+static void zx29_uart_throttle_rx(struct uart_port *port)
+{
+ test_uart_static(port->line, NULL, 0, 80);
+ unsigned long flags;
+ int uart_id = port->line;
+
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
+ spin_lock_irqsave(&port->lock, flags);
+ if(!uart_dma_cycle[port->line].used)
+ uart_id = uart_id + 3;
+ if(!tty_buffer_space_avail(&port->state->port)){
+ zx29_dma_stop(DMA_CH_UART0_RX);
+ uart_dma_cycle[uart_id].enter_throttle = true;
+ uart_dma_cycle[uart_id].cnt_throttle++;
+ }
+ spin_unlock_irqrestore(&port->lock, flags);
+ #if 0
+ while(zx29_dma_get_transfer_num(rx_id) != 4096)
+ msleep(1);
+ spin_lock_irqsave(&port->lock, flags);
+ zup->dmacr &= ~UART_RXDMAE;
+ UART_PUT_DMACR(&zup->port,zup->dmacr);
+ zx29_dma_stop(rx_id);
+ zup->dmarx.running = false;
+ zup->dmarx.used = false;
+ uart_dma_cycle[port->line].enter_throttle = true;
+ spin_unlock_irqrestore(&port->lock, flags);
+ #endif
+}
+static void zx29_uart_unthrottle_rx(struct uart_port *port)
+{
+ test_uart_static(port->line, NULL, 0, 81);
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+ unsigned long flags;
+ int uart_id = port->line;
+ spin_lock_irqsave(&port->lock, flags);
+ if(!uart_dma_cycle[port->line].used)
+ uart_id = uart_id + 3;
+ uart_dma_cycle[uart_id].enter_throttle = false;
+ uart_dma_cycle[uart_id].from_unthrottle = true;
+ uart_dma_cycle[uart_id].cnt_unthrottle++;
+ #if 0
+ if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
+ printk("rx_dma_chars RXDMA start fail\n");
+ zup->imr |= (UART_RTIM|UART_RXIM);
+ UART_PUT_IMSC(&zup->port,zup->imr);
+ }else{
+ hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
+ zup->pre_pending = 0;
+ zup->dmarx.used = true;
+ zup->work_state = true;
+ UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
+ }
+ #endif
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/****************************************************************************/
+/*
+ * Define the basic serial functions we support.
+ */
+static const struct uart_ops zx29_uart_ops = {
+ .tx_empty = zx29_uart_tx_empty,
+ .set_mctrl = zx29_uart_set_mctrl,
+ .get_mctrl = zx29_uart_get_mctrl,
+ .start_tx = zx29_uart_start_tx,
+ .stop_tx = zx29_uart_stop_tx,
+ .stop_rx = zx29_uart_stop_rx,
+ .throttle = zx29_uart_throttle_rx,
+ .unthrottle = zx29_uart_unthrottle_rx,
+ .enable_ms = zx29_uart_enable_ms,
+ .break_ctl = zx29_uart_break_ctl,
+ .startup = zx29_uart_startup,
+ .shutdown = zx29_uart_shutdown,
+ .set_termios = zx29_uart_set_termios,
+#if CONFIG_SERIAL_ZX29_DMA
+ .flush_buffer = zx29_dma_flush_buffer,
+#endif
+ .type = zx29_uart_type,
+ .request_port = zx29_uart_request_port,
+ .release_port = zx29_uart_release_port,
+ .config_port = zx29_uart_config_port,
+ .verify_port = zx29_uart_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+ .poll_get_char = zx29_get_poll_char,
+ .poll_put_char = zx29_put_poll_char,
+#endif
+
+};
+
+
+/****************************************************************************/
+static int zx29_init_ports(struct zx29_uart_port *zx29_port,
+ struct platform_device *pdev)
+{
+ int ret = 0;
+ struct uart_port *port=&zx29_port->port;
+ unsigned int offset=(unsigned int)(pdev->id);
+ struct device_node *np = pdev->dev.of_node;
+ unsigned int baud, ibrd, fbrd;
+
+ struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ //struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+ if(!regs){
+ dev_err(&pdev->dev, "zx29_init_ports, get resource fail,\n");
+ return -ENODEV;
+ }
+/*get apb clock*/
+ zx29_port->busclk = devm_clk_get(&pdev->dev, UART_APBCLK_NAME);
+ if (IS_ERR(zx29_port->busclk)) {
+ ret = PTR_ERR(zx29_port->busclk);
+ printk("failed to get zx29_port->busclk: %d\n", ret);
+ return ret;
+ }
+
+ /*get work clock*/
+ zx29_port->wclk = devm_clk_get(&pdev->dev, UART_WCLK_NAME);
+
+ if (IS_ERR(zx29_port->wclk)) {
+ ret = PTR_ERR(zx29_port->wclk);
+ printk("failed to get zx29_port->wclk: %d\n", ret);
+ return ret;
+ }
+ if(offset == 0){
+ clk_set_rate(zx29_port->wclk, 104 * 1000000);
+ }
+ port->line = offset;
+ port->type = PORT_ZX29;
+ port->fifosize = UART_TXFIFO_SIZE;
+ //port->iotype = UPIO_MEM;
+ //port->irq = irq->start;
+ port->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+ if(pdev->id == 0){
+ zx29_port->rxd_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
+ }
+ //port->membase = devm_ioremap_nocache(&pdev->dev, regs->start,
+ // resource_size(regs));
+ port->membase = devm_platform_ioremap_resource(pdev, 0);
+
+ if (!port->membase)
+ return -ENODEV;
+ port->mapbase = regs->start;
+ port->mapsize = resource_size(regs);
+
+ //port->flags = UPF_BOOT_AUTOCONF;
+ port->ops = &zx29_uart_ops;
+ port->uartclk = clk_get_rate(zx29_port->wclk);
+
+ port->private_data = pdev;
+ //here is temple def
+ if(port->uartclk == 0){
+ printk("---zx29_init_ports, uartclk hard set to 26M\n");
+ port->uartclk = 26000000;
+ }
+ printk("---zx29_init_ports, line:%d, irq:%d, membase:%08x, uartclk:%d\n", port->line, port->irq, port->membase, port->uartclk);
+ /*
+ * just configure clock,
+ * actually pin configuration is needed, but now gpio driver is not OK
+ * use bootloader default configuration
+ */
+ if(DEBUG_CONSOLE == pdev->id){
+ /* config uart apb_clk */
+ clk_prepare_enable(zx29_port->busclk);
+
+ /* enable uart work clock */
+ clk_prepare_enable(zx29_port->wclk);
+ }
+ return 0;
+}
+
+
+#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
+
+#if VEHICLE_USE_ONE_UART_LOG
+static void zx29_uart_console_putc(struct uart_port *port, int c)
+{
+ if(g_core_id_occupy_uart == SYMB_PS_CORE_ID)
+ return;
+ int ret = soft_spin_lock_printf(UART_SFLOCK);
+ if(ret)
+ return;
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, c);
+ soft_spin_unlock(UART_SFLOCK);
+}
+#else
+static void zx29_uart_console_putc(struct uart_port *port, int c)
+{
+ while (UART_GET_FR(port) & UART_FR_TXFF)
+ barrier();
+ UART_PUT_CHAR(port, c);
+}
+
+#endif
+
+
+
+/****************************************************************************/
+static void zx29_uart_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct uart_port *port = &zx29_uart_ports[co->index].port;
+
+ //spin_lock(&port->lock);
+ for (; (count); count--, s++) {
+ zx29_uart_console_putc(port, *s);
+ if (*s == '\n')
+ zx29_uart_console_putc(port, '\r');
+ }
+
+ //spin_unlock(&port->lock);
+}
+
+/***************************************************************************
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ ****************************************************************************/
+static void __init zx29_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits)
+{
+ if (UART_GET_CR(port) & UART_CR_UARTEN) {
+ unsigned int lcr_h, ibrd, fbrd;
+
+ lcr_h = UART_GET_LCRH(port);
+ *parity = 'n';
+ if (lcr_h & UART_LCRH_PEN) {
+ if (lcr_h & UART_LCRH_EPS)
+ *parity = 'e';
+ else
+ *parity = 'o';
+ }
+ if ((lcr_h & 0x60) == UART_LCRH_WLEN_7)
+ *bits = 7;
+ else
+ *bits = 8;
+
+ ibrd = UART_GET_IBRD(port);
+ fbrd = UART_GET_FBRD(port);
+
+ *baud = port->uartclk * 8 / (16*8 * ibrd + 2*fbrd-1);
+ }
+}
+
+/****************************************************************************/
+static int __init zx29_uart_console_setup(struct console *co, char *options)
+{
+ printk("zx29_uart_console_setup.\n");
+ struct uart_port *port;
+ int baud = 115200;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+ unsigned int uart_cr = 0;
+
+ if ((co->index < 0) || (co->index >= zx29_MAXPORTS))
+ co->index = CONFIG_UART_CONSOLE_ID;
+
+ port = &zx29_uart_ports[co->index].port;
+ if (port->membase == NULL)
+ return -ENODEV;
+
+ uart_cr = UART_GET_CR(port);
+ uart_cr |= UART_CR_UARTEN | UART_CR_TXE;
+ UART_PUT_CR(port,uart_cr);
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ else
+ zx29_console_get_options(port, &baud, &parity, &bits);
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+/****************************************************************************/
+
+static struct uart_driver zx29_uart_driver;
+int zx29_get_console_index(void)
+{
+#if 0
+ int dev_cnt = zx29_device_table_num;
+ int idx = 0;
+ struct platform_device *pdev = NULL;
+ for(idx = 0; idx < dev_cnt; idx++)
+ {
+ pdev = zx29_device_table[idx];
+ if(strcmp(pdev->name,"zx29_uart") == 0 && pdev->id == CONFIG_UART_CONSOLE_ID)
+ return idx;
+ }
+#endif
+ return CONFIG_UART_CONSOLE_ID;
+ //return -1;
+}
+static struct console zx29_uart_console = {
+ .name = "ttyS",
+ .write = zx29_uart_console_write,
+ .device = uart_console_device,
+ .setup = zx29_uart_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &zx29_uart_driver,
+};
+static int __init zx29_uart_console_init(void)
+{
+ int console_dev_id = zx29_get_console_index();
+
+ if(console_dev_id < 0){
+ printk("console init fail, uart config fail, console_dev_id is: %d", console_dev_id);
+ return -1;
+ }
+ //zx29_init_ports(&zx29_uart_ports[DEBUG_CONSOLE], zx29_device_table[console_dev_id]);
+ register_console(&zx29_uart_console);
+ pr_info("[UART]register_console: zx29 console registered!\n");
+
+ return 0;
+}
+
+//console_initcall(zx29_uart_console_init);
+
+#define zx29_UART_CONSOLE (&zx29_uart_console)
+
+
+static void zx29_uart_early_write(struct console *con, const char *s, unsigned n)
+{
+ struct earlycon_device *dev = con->data;
+
+ uart_console_write(&dev->port, s, n, zx29_uart_console_putc);
+}
+
+static int __init zx29_uart_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ if (!device->port.membase)
+ return -ENODEV;
+
+ device->con->write = zx29_uart_early_write;
+
+ return 0;
+}
+
+OF_EARLYCON_DECLARE(zx29_uart, "zxic,zx29-uart", zx29_uart_early_console_setup);
+#else
+#define zx29_UART_CONSOLE NULL
+#endif /* CONFIG_zx29_UART_CONSOLE */
+static void zx29_uart_pin_ctrl(struct platform_device *pdev)
+{
+ struct pinctrl *pin_ctrl;
+ struct pinctrl_state *state0;
+ pin_ctrl = devm_pinctrl_get(&pdev->dev);
+ switch(pdev->id){
+ case 0:
+ printk("zx29_uart %d use default pinctrl.",pdev->id);
+ break;
+ case 1:
+ printk("zx29_uart %d use default pinctrl.",pdev->id);
+ break;
+
+ case 2:
+ if(IS_ERR(pin_ctrl)){
+ dev_warn(&pdev->dev, "fail to get uart2 pins.");
+ pin_ctrl = NULL;
+ return;
+ }
+ state0 = pinctrl_lookup_state(pin_ctrl, "default");
+ if(IS_ERR(state0)){
+ dev_err(&pdev->dev, "uart2 pinstate get fail.\n");
+ }
+ if(pinctrl_select_state(pin_ctrl, state0)){
+ dev_err(&pdev->dev, "uart2 select pinstate fail.\n");
+ }
+ break;
+ }
+}
+
+/*
+ * Define the zx29 UART driver structure.
+ */
+static struct uart_driver zx29_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = "zx29_uart",
+ .dev_name = "ttyS",
+ .major = SERIAL_zx29_MAJOR,
+ .minor = SERIAL_MINOR_START,
+ .nr = zx29_MAXPORTS,
+ .cons = zx29_UART_CONSOLE,
+};
+
+unsigned char uart_wakelock_name[zx29_MAXPORTS][20]={{0}};
+/****************************************************************************/
+
+
+#ifdef CONFIG_PM_SLEEP
+static int zx29_uart_suspend(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_uart_port *zup = dev_get_drvdata(dev);
+ unsigned int flags;
+ if (!zup)
+ return -EINVAL;
+ if(zup->port.line == UART1)
+ return 0;
+#if 1
+ pinctrl_pm_select_sleep_state(dev);
+#endif
+
+ printk("zx29_uart%d suspend.\n",zup->port.line);
+
+ raw_spin_lock_irqsave(&zup->port.lock, flags);
+ zup->enter_suspend = 1;
+ if(zup->port.line == UART2){
+ zx29_dma_stop(DMA_CH_UART2_RX);
+ zx29_dma_stop(DMA_CH_UART2_TX);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+ return 0;
+ }
+
+ zx29_dma_stop(DMA_CH_UART0_RX);
+ zx29_dma_stop(DMA_CH_UART0_TX);
+ raw_spin_unlock_irqrestore(&zup->port.lock, flags);
+#if 0
+ ret = irq_set_irq_type(unsigned int irq, unsigned int type);
+
+#endif
+ //pcu_int_clear(PCU_UART0_RXD_INT);
+ if(zup->irq_state && (zup->rxd_int_depth == 0)){
+ struct irq_data *data_rxd;
+ data_rxd= irq_get_irq_data(zup->rxd_irq);
+ if(data_rxd){
+ if(irqd_irq_disabled(data_rxd))
+ enable_irq(zup->rxd_irq);
+ }
+ zup->rxd_int_depth = 1;
+ }
+
+ return 0;
+}
+
+static int zx29_uart_resume(struct device *dev)
+{
+ struct zx29_uart_port *zup = dev_get_drvdata(dev);
+
+ if (!zup)
+ return -EINVAL;
+ int uart_id = zup->port.line;
+ if(!uart_dma_cycle[zup->port.line].used)
+ uart_id = uart_id + 3;
+ if(zup->port.line == UART1)
+ return 0;
+#if 1
+ pinctrl_pm_select_default_state(dev);
+#endif
+
+ printk("zx29_uart%d resume.\n",zup->port.line);
+
+ zup->enter_suspend = 0;
+ uart_dma_cycle[uart_id].from_resume = 1;
+ return 0;
+}
+
+
+#endif
+
+static SIMPLE_DEV_PM_OPS(zx29_uart_dev_pm_ops, zx29_uart_suspend, zx29_uart_resume);
+
+
+
+static int zx29_uart_probe(struct platform_device *pdev)
+{
+ int ret=0;
+ int error;
+ char wakelock_name[20];
+ struct device_node *np = pdev->dev.of_node;
+ ret = of_alias_get_id(np, "uart");
+
+ if(ret < 0){
+ printk("-----zx29_uart_probe,of_alias_get_id fail ret:%d\n", ret);
+ return -ENODEV;
+ }
+ pdev->id = ret;
+ printk("-----zx29_uart_probe,ret:%d\n", ret);
+ // struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
+ struct zx29_uart_port *port = &zx29_uart_ports[pdev->id];
+
+
+#if 0//def CONFIG_SERIAL_ZX29_UART_CONSOLE
+ if(DEBUG_CONSOLE != pdev->id){
+ ret = zx29_init_ports(port,pdev);
+ }
+#else
+ ret = zx29_init_ports(port,pdev);
+
+#endif
+ if(ret < 0){
+ printk("-----zx29_uart_probe,zx29_init_ports fail ret:%d\n", ret);
+ }
+ zx29_uart_pin_ctrl(pdev);
+#if CONFIG_SERIAL_ZX29_DMA
+ if((DEBUG_CONSOLE != pdev->id ) && (pdev->id != 4))
+ {
+ uart_dma_init(port);
+ printk(KERN_INFO "[%s][%d]UART_%d DMA is OPENED\n",__func__,__LINE__,pdev->id);
+ }
+#endif
+ ret = 0;
+ ret=uart_add_one_port(&zx29_uart_driver, &port->port);
+
+ if(ret)
+ {
+#if CONFIG_SERIAL_ZX29_DMA
+ zx29_dma_remove(port);
+#endif
+ return ret;
+ }
+#if CONFIG_SERIAL_ZX29_DMA
+ sema_init(&port->sema, 0);
+#endif
+
+ platform_set_drvdata(pdev, port);
+
+ if(pdev->id == DEBUG_CONSOLE){
+ //g_console_open_flag = pdata->uart_input_enable ? pdata->uart_input_enable : 0;
+ error = device_create_file(&pdev->dev, &dev_attr_console_input);
+#if VEHICLE_USE_ONE_UART_LOG
+ error = device_create_file(&pdev->dev, &dev_attr_console_uart_toggle);
+ error = device_create_file(&pdev->dev, &dev_attr_coreid_occupy_uart);
+ int ret;
+ ret = rpmsgCreateChannel(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, ICP_BUFFERSIZE_CONSOLE_TOGGLE);
+ if(ret){
+ printk("linux5 request icp channel for uart fail %d.\n",ret);
+ }
+ rpmsgRegCallBack(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, icp_callback_ps2cap);
+#endif
+ }
+
+ if(pdev->id != DEBUG_CONSOLE){
+ error = device_create_file(&pdev->dev, &dev_attr_ctsrts_input);
+ error = device_create_file(&pdev->dev, &dev_attr_wakeup_enable);
+ error = device_create_file(&pdev->dev, &dev_attr_sleep_state);
+ error = device_create_file(&pdev->dev, &dev_attr_app_ctrl);
+
+ }
+ error = device_create_file(&pdev->dev, &dev_attr_statics);
+ device_init_wakeup(&pdev->dev, true);
+/*
+ strcpy(wakelock_name, "uart_wakelock_x");
+ wakelock_name[14] = '0' + pdev->id;
+ strcpy(uart_wakelock_name[pdev->id], wakelock_name);
+ wake_lock_init(&(port->port.port_wakelock),WAKE_LOCK_SUSPEND,uart_wakelock_name[pdev->id]);
+*/
+
+ printk(KERN_INFO "TSP zx29 UART_%d probe OK\n",pdev->id);
+ return 0;
+}
+
+/****************************************************************************/
+static int /*__devexit*/ zx29_uart_remove(struct platform_device *pdev)
+{
+ struct uart_port *port = NULL;
+#if CONFIG_SERIAL_ZX29_DMA
+ struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
+#endif
+ int i;
+ if(pdev->id == DEBUG_CONSOLE){
+ device_remove_file(&pdev->dev, &dev_attr_console_input);
+ }
+
+ if(pdev->id != DEBUG_CONSOLE){
+ device_remove_file(&pdev->dev, &dev_attr_ctsrts_input);
+ device_remove_file(&pdev->dev, &dev_attr_wakeup_enable);
+ }
+
+ for (i = 0; (i < zx29_MAXPORTS); i++) {
+ port = &zx29_uart_ports[i].port;
+ if (port){
+ uart_remove_one_port(&zx29_uart_driver, port);
+
+
+#if CONFIG_SERIAL_ZX29_DMA
+ zup=container_of(port,struct zx29_uart_port,port);
+ zx29_dma_remove(zup);
+
+#endif
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id zx29_uart_of_match[] = {
+ { .compatible = "zxic,zx29-uart"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_uart_of_match);
+
+static struct platform_driver zx29_uart_platform_driver = {
+ .probe = zx29_uart_probe,
+ //.remove = __devexit_p(zx29_uart_remove),
+ .remove = zx29_uart_remove,
+ .driver = {
+ .name = "zx29_uart",
+ .pm = &zx29_uart_dev_pm_ops,
+ .of_match_table = of_match_ptr(zx29_uart_of_match),
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init zx29_uart_init(void)
+{
+ int rc;
+
+ rc = uart_register_driver(&zx29_uart_driver);
+ if (rc)
+ return rc;
+ rc = platform_driver_register(&zx29_uart_platform_driver);
+ if (rc){
+ uart_unregister_driver(&zx29_uart_driver);
+ return rc;
+ }
+
+ printk(KERN_INFO "zx29 UART driver registered\n");
+
+ return 0;
+}
+
+static void __exit zx29_uart_exit(void)
+{
+#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
+ unregister_console(&zx29_uart_console);
+#endif
+ platform_driver_unregister(&zx29_uart_platform_driver);
+ uart_unregister_driver(&zx29_uart_driver);
+}
+//arch_initcall(zx29_uart_init);
+
+//subsys_initcall(zx29_uart_init);
+module_init(zx29_uart_init);
+module_exit(zx29_uart_exit);
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/include/linux/mfd/zx234290.h b/patch/17.09_19.00/code/old/upstream/linux-5.10/include/linux/mfd/zx234290.h
new file mode 100755
index 0000000..ea89815
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/include/linux/mfd/zx234290.h
@@ -0,0 +1,1130 @@
+/*
+ * zx234290.h -- ZTE ZX234290
+ *
+ * Copyright 2016 ZTE Corporation.
+ *
+ * Author: yuxiang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_ZX234290_H
+#define __LINUX_MFD_ZX234290_H
+
+#include <linux/mutex.h>
+
+#define zx234290_rails(_name) "zx234290_"#_name
+
+#define u8 unsigned char
+
+/* LDOs */
+#define ZX234290_REG_LDO1 0
+#define ZX234290_REG_LDO2 1
+#define ZX234290_REG_LDO3 2
+#define ZX234290_REG_LDO4 3
+#define ZX234290_REG_LDO5 4
+#define ZX234290_REG_LDO6 5
+#define ZX234290_REG_LDO7 6
+#define ZX234290_REG_LDO8 7
+
+#define ZX234290_REG_LDO9 8
+#define ZX234290_REG_LDO10 9
+#define ZX234290_REG_LDO11 10
+
+/* DCDC's */
+#define ZX234290_REG_DCDC0 11
+#define ZX234290_REG_DCDC1 12
+#define ZX234290_REG_DCDC2 13
+#define ZX234290_REG_DCDC3 14
+#define ZX234290_REG_DCDC4 15
+
+/* ZX regulator type list */
+#ifndef ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_INT_LDO_FAUL 0
+#define ZX234290_INT_BUCK_FAUL 1
+#endif
+
+#define ZX234290_INT_EOADC 2 /* xxxx x100 */
+#define ZX234290_INT_PWRON_SHORT 3
+#define ZX234290_INT_PWRON_LONG 4
+#define ZX234290_INT_PWRON 5
+
+#define ZX234290_INT_RTC_ALRM 8
+#define ZX234290_INT_BATT_DET 10
+#define ZX234290_INT_RTC_MIN 11
+#define ZX234290_INT_RTC_HOUR 12
+
+#define ZX234290_NUM_IRQ 13
+
+#ifdef ZX234290_PWR_FAUL_PROCESS
+int zx234290_register_client(struct notifier_block *nb);
+int zx234290_unregister_client(struct notifier_block *nb);
+int zx234290_notifier_call_chain(unsigned long val, void *v);
+#endif
+
+#if 0
+/* External controls requests */
+enum zx234290_ext_control {
+ PWR_REQ_INPUT_NONE = 0x00000000,
+ PWR_REQ_INPUT_PREQ1 = 0x00000001,
+ PWR_REQ_INPUT_PREQ2 = 0x00000002,
+ PWR_REQ_INPUT_PREQ3 = 0x00000004,
+ PWR_OFF_ON_SLEEP = 0x00000008,
+ PWR_ON_ON_SLEEP = 0x00000010,
+};
+#endif
+
+#if 0
+typedef enum
+{
+ RESET_TO_NORMAL, /*reset to idle*/
+ RESET_TO_CHARGER, /*reset to charger*/
+ RESET_TO_ALRAM, /*reset to alarm*/
+ RESET_TO_EXCEPTRESET,
+ MAX_RESET_TYPE,
+} T_ZDrvSys_RESET_TYPE;
+#endif
+
+typedef enum _T_ZDrvPmic_Enable{
+ PM_DISABLE = 0,
+ PM_ENABLE,
+ PM_ENABLE_NOT_SUPPORT = -100,
+ PM_ENABLE_MAX_STATUS = -255
+} T_ZDrvPmic_Enable;
+
+typedef enum _T_ZDrvPmic_NrmMode{
+ PM_NRMMODE_AUTO = 0,
+ PM_NRMMODE_PFM,
+ PM_NRMMODE_PWM,
+ PM_NRMMODE_NOT_SUPPORT = -100,
+ PM_NRMMODE_MAX_STATUS = -255
+}T_ZDrvPmic_NrmMode;
+
+typedef enum _T_ZDrvPmic_SlpMode{
+ PM_SLPMODE_AUTO_NORMAL = 0, //auto in dcdc, normal in ldo
+ PM_SLPMODE_ECO_NRMV, //normal voltage
+ PM_SLPMODE_ECO_SLPV, //sleep voltage
+ PM_SLPMODE_OFF, //OFF
+ PM_SLPMODE_NOT_SUPPORT = -100,
+ PM_SLPMODE_MAX_STATUS = -255
+}T_ZDrvPmic_SlpMode;
+
+//consumer
+typedef enum _T_ZDrvPmic_Regulator{
+ VCORE0 = 0,
+ VCORE1,
+ VDDR,
+ VMMC,
+ VSD0,
+ VSD1,
+ VIO_LO,
+ VIO_HI,
+ VUSB_0V9,
+ VUSB_3V3,
+ VPLL_LO,
+ VPLL_HI,
+ VSIM1,
+ VSIM2,
+ VRF_LO,
+ VRF_HI,
+ VRF_SW,
+ VPA,
+ VCTCXO1,
+ VCTCXO2,
+ VSSBUF,
+ VRTC,
+} T_ZDrvPmic_Regulator;
+
+typedef enum _T_ZDrvPmic_Vcore{
+ PM_VOLT_0_6750 = 0,
+ PM_VOLT_0_6875 ,
+ PM_VOLT_0_7000 ,
+ PM_VOLT_0_7125 ,
+ PM_VOLT_0_7250 = 0x04,
+ PM_VOLT_0_7375 ,
+ PM_VOLT_0_7500 ,
+ PM_VOLT_0_7625 ,
+ PM_VOLT_0_7750 = 0x08 ,
+ PM_VOLT_0_7875 ,
+ PM_VOLT_0_8000 ,
+ PM_VOLT_0_8125 ,
+ PM_VOLT_0_8250 = 0x0c,
+ PM_VOLT_0_8375 ,
+ PM_VOLT_0_8500 ,
+ PM_VOLT_0_8625 ,
+ PM_VOLT_0_8750 = 0x10 ,
+ PM_VOLT_0_8875 ,
+ PM_VOLT_0_9000 ,
+ PM_VOLT_0_9125 ,
+ PM_VOLT_0_9250 = 0x14,
+ PM_VOLT_0_9375 ,
+ PM_VOLT_0_9500 ,
+ PM_VOLT_0_9625 ,
+ PM_VOLT_0_9750 = 0x18 ,
+ PM_VOLT_0_9875 ,
+ PM_VOLT_1_0000 ,
+ PM_VOLT_1_0125 ,
+ PM_VOLT_1_0250 = 0x1c,
+ PM_VOLT_1_0375 ,
+ PM_VOLT_1_0500 ,
+ PM_VOLT_1_0625 ,
+ PM_VOLT_1_0750 = 0x20 ,
+ PM_VOLT_1_0875 ,
+ PM_VOLT_1_1000 ,
+ PM_VOLT_1_1125 ,
+ PM_VOLT_1_1250 = 0x24,
+ PM_VOLT_1_1375 ,
+ PM_VOLT_1_1500 ,
+ PM_VOLT_1_1625 ,
+ PM_VOLT_1_1750 = 0x28 ,
+ PM_VOLT_1_1875 ,
+ PM_VOLT_1_2000 ,
+ PM_VOLT_1_2125 ,
+ PM_VOLT_1_2250 = 0x2c,
+ PM_VOLT_1_2375 ,
+ PM_VOLT_1_2500 = 0x2e,
+ PM_VOLT_1_2625 ,
+ PM_VOLT_1_2750 = 0x30 ,
+ PM_VOLT_1_2875 ,
+ PM_VOLT_1_3000 ,
+ PM_VOLT_1_3125 ,
+ PM_VOLT_1_3250 = 0x34,
+ PM_VOLT_1_3375 ,
+ PM_VOLT_1_3500 ,
+ PM_VOLT_1_3625 ,
+ PM_VOLT_1_3750 = 0x38 ,
+ PM_VOLT_1_3875 ,
+ PM_VOLT_1_4000 ,
+ PM_VOLT_1_4125 ,
+ PM_VOLT_1_4250 = 0x3c,
+ PM_VOLT_1_4375 ,
+ PM_VOLT_1_4500 ,
+ PM_VOLT_1_4625 ,
+ PM_VOLT_1_4750 = 0x40 ,
+ PM_VOLT_1_4875 ,
+ PM_VOLT_1_5000 ,
+ PM_VOLT_1_5125 ,
+ PM_VOLT_1_5250 = 0x44,
+ PM_VOLT_1_5375 ,
+ PM_VOLT_1_5500 ,
+ PM_VOLT_1_5625 ,
+ PM_VOLT_1_5750 = 0x48,
+ PM_VOLT_1_5875 ,
+ PM_VOLT_1_6000 ,
+ PM_VOLT_1_6125 ,
+ PM_VOLT_1_6250 = 0x4c,
+ PM_VOLT_1_6375 ,
+ PM_VOLT_1_6500 ,
+ PM_VOLT_1_6625 ,
+ PM_VOLT_1_6750 = 0x50,
+ PM_VOLT_1_6875 ,
+ PM_VOLT_1_7000 ,
+ PM_VOLT_1_7125 ,
+ PM_VOLT_1_7250 = 0x54,
+ PM_VOLT_1_7375 ,
+ PM_VOLT_1_7500 ,
+ PM_VOLT_1_7625 ,
+ PM_VOLT_1_7750 = 0x58,
+ PM_VOLT_1_7875 ,
+ PM_VOLT_1_8000 ,
+ PM_VOLT_1_8125 ,
+ PM_VOLT_1_8250 = 0x5c,
+ PM_VOLT_1_8375 ,
+ PM_VOLT_1_8500 ,
+ PM_VOLT_1_8625 ,
+ PM_VOLT_1_8750 = 0x60 ,
+ PM_VOLT_1_8875 ,
+ PM_VOLT_1_9000 ,
+ PM_VOLT_1_9125 ,
+ PM_VOLT_1_9250 = 0x64,
+ PM_VOLT_1_9375 ,
+ PM_VOLT_1_9500 ,
+ PM_VOLT_1_9625 ,
+ PM_VOLT_1_9750 = 0x68,
+ PM_VOLT_1_9875 ,
+ PM_VOLT_2_0000 ,
+ PM_VOLT_2_0125 ,
+ PM_VOLT_2_0250 = 0x6c,
+ PM_VOLT_2_0375 ,
+ PM_VOLT_2_0500 ,
+ PM_VOLT_2_0625 ,
+ PM_VOLT_2_0750 = 0x70,
+ PM_VOLT_2_0875 ,
+ PM_VOLT_2_1000 ,
+ PM_VOLT_2_1125 ,
+ PM_VOLT_2_1250 = 0x74,
+ PM_VOLT_2_1375 ,
+ PM_VOLT_2_1500 ,
+ PM_VOLT_2_1625 ,
+ PM_VOLT_2_1750 = 0x78 ,
+ PM_VOLT_2_1875 ,
+ PM_VOLT_2_2000 ,
+ PM_VOLT_2_2125 ,
+ PM_VOLT_2_2250 = 0x7c,
+ PM_VOLT_2_2375 ,
+ PM_VOLT_2_2500 ,
+ PM_VOLT_2_2625 ,
+ PM_VOLT_2_2750 = 0x80,
+ PM_VOLT_2_2875 ,
+ PM_VOLT_2_3000 ,
+ PM_VOLT_2_3125 ,
+ PM_VOLT_2_3250 = 0x84,
+ PM_VOLT_2_3375 ,
+ PM_VOLT_2_3500 ,
+ PM_VOLT_2_3625 ,
+ PM_VOLT_2_3750 = 0x88 ,
+ PM_VOLT_2_3875 ,
+ PM_VOLT_2_4000 ,
+ PM_VOLT_2_4125 ,
+ PM_VOLT_2_4250 = 0x8c,
+ PM_VOLT_2_4375 ,
+ PM_VOLT_2_4500 ,
+ PM_VOLT_2_4625 ,
+ PM_VOLT_2_4750 = 0x90,
+ PM_VOLT_2_4875 ,
+ PM_VOLT_2_5000 ,
+ PM_VOLT_2_5125 ,
+ PM_VOLT_2_5250 = 0x94,
+ PM_VOLT_2_5375 ,
+ PM_VOLT_2_5500 ,
+ PM_VOLT_2_5625 ,
+ PM_VOLT_2_5750 = 0x98 ,
+ PM_VOLT_2_5875 ,
+ PM_VOLT_2_6000 ,
+ PM_VOLT_2_6125 ,
+ PM_VOLT_2_6250 = 0x9c,
+ PM_VOLT_2_6375 ,
+ PM_VOLT_2_6500 ,
+ PM_VOLT_2_6625 ,
+ PM_VOLT_2_6750 = 0xa0,
+ PM_VOLT_2_6875 ,
+ PM_VOLT_2_7000 ,
+ PM_VOLT_2_7125 ,
+ PM_VOLT_2_7250 = 0xa4,
+ PM_VOLT_2_7375 ,
+ PM_VOLT_2_7500 ,
+ PM_VOLT_2_7625 ,
+ PM_VOLT_2_7750 = 0xa8,
+ PM_VOLT_2_7875 ,
+ PM_VOLT_2_8000 ,
+ PM_VOLT_2_8125 ,
+ PM_VOLT_2_8250 = 0xac,
+ PM_VOLT_2_8375 ,
+ PM_VOLT_2_8500 ,
+ PM_VOLT_2_8625 ,
+ PM_VOLT_2_8750 = 0xb0,
+ PM_VOLT_2_8875 ,
+ PM_VOLT_2_9000 ,
+ PM_VOLT_2_9125 ,
+ PM_VOLT_2_9250 = 0xb4,
+ PM_VOLT_2_9375 ,
+ PM_VOLT_2_9500 ,
+ PM_VOLT_2_9625 ,
+ PM_VOLT_2_9750 = 0xb8,
+ PM_VOLT_2_9875 ,
+ PM_VOLT_3_0000 ,
+ PM_VOLT_3_0125 ,
+ PM_VOLT_3_0250 = 0xbc,
+ PM_VOLT_3_0375 ,
+ PM_VOLT_3_0500 ,
+ PM_VOLT_3_0625 ,
+ PM_VOLT_3_0750 = 0xc0 ,
+ PM_VOLT_3_0875 ,
+ PM_VOLT_3_1000 ,
+ PM_VOLT_3_1125 ,
+ PM_VOLT_3_1250 = 0xc4,
+ PM_VOLT_3_1375 ,
+ PM_VOLT_3_1500 ,
+ PM_VOLT_3_1625 ,
+ PM_VOLT_3_1750 = 0xc8 ,
+ PM_VOLT_3_1875 ,
+ PM_VOLT_3_2000 ,
+ PM_VOLT_3_2125 ,
+ PM_VOLT_3_2250 = 0xcc,
+ PM_VOLT_3_2375 ,
+ PM_VOLT_3_2500 ,
+ PM_VOLT_3_2625 ,
+ PM_VOLT_3_2750 = 0xd0 ,
+ PM_VOLT_3_2875 ,
+ PM_VOLT_3_3000 ,
+ PM_VOLT_3_3125 ,
+ PM_VOLT_3_3250 = 0xd4,
+ PM_VOLT_3_3375 ,
+ PM_VOLT_3_3500 ,
+ PM_VOLT_3_3625 ,
+ PM_VOLT_3_3750 = 0xd8 ,
+ PM_VOLT_3_3875 ,
+
+ PM_VOLT_NOT_SUPPORT = -100,
+ PM_VOLT_MAX_STATUS = -255,
+ } T_ZDrvPmic_Voltage;
+
+
+
+
+/**
+ * struct zx234290 - zx234290 sub-driver chip access routines
+ */
+
+struct zx234290 {
+ struct device *dev;
+ /* for read/write acces */
+ struct mutex io_mutex;
+
+ /* For device IO interfaces: I2C or SPI */
+ void *control_data;
+
+ int (*read)(struct zx234290 *zx234290, u8 reg, int size, void *dest);
+ int (*write)(struct zx234290 *zx234290, u8 reg, int size, void *src);
+
+ /* Client devices */
+ struct zx234290_regulator *regulator;
+
+ /* GPIO Handling */
+
+ /* IRQ Handling */
+ struct mutex irq_lock;
+ int chip_irq;
+ int irq_base;
+ struct irq_domain * irq_domain;
+ int irq_num;
+ unsigned int irq_mask;
+};
+int zx234290_i2c_read_simple(u8 reg, void *dest);
+int zx234290_i2c_write_simple(u8 reg, void *src);
+int zx234290_i2c_read_simple_PSM(u8 reg, void *dest);
+int zx234290_i2c_write_simple_PSM(u8 reg, void *src);
+
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg);
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val);
+int zx234290_device_init(struct zx234290 *zx234290);
+void zx234290_device_exit(struct zx234290 *zx234290);
+
+
+/*regulator defines*/
+#if 1
+/*
+ * List of registers for ZX234290
+*/
+
+/////////////////////////////////////////////////
+/*slave address 0x12*/
+/////////////////////////////////////////////////
+#define ZX234290_I2C_SLAVE_ADDR0 (0x12)
+
+ /* interrupt and mask */
+#define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */
+#define ZX234290_REG_ADDR_INTB 0x01
+#define ZX234290_REG_ADDR_INTA_MASK 0x02
+#define ZX234290_REG_ADDR_INTB_MASK 0x03
+
+ /* interrupt status */
+#define ZX234290_REG_ADDR_STSA 0x04
+#define ZX234290_REG_ADDR_STSB 0x05
+#define ZX234290_REG_ADDR_STS_STARTUP 0x06
+
+ /* adc & softon select */
+#define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/
+
+ /* bucks normal voltage and sleep voltage */
+#define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/
+#define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D
+
+ /* bucks mode */
+#define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/
+#define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/
+#define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */
+
+ /* ldo normal voltage */
+#define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */
+#define ZX234290_REG_ADDR_LDO34_VOL 0x13
+#define ZX234290_REG_ADDR_LDO56_VOL 0x14
+#define ZX234290_REG_ADDR_LDO78_VOL 0x15
+#define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */
+#define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/
+
+
+#define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */
+
+ /* ldo sleep voltage */
+#define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/
+#define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */
+#define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/
+#define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */
+#define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */
+
+ /* ldo mode */
+#define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/
+#define ZX234290_REG_ADDR_LDO5678_MODE 0x1F
+#define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */
+
+ /* ldo enable */
+#define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */
+#define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/
+
+ /* adc code */
+#define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/
+#define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/
+#define ZX234290_REG_ADDR_ADC1_MSB 0x25
+#define ZX234290_REG_ADDR_ADC1_LSB 0x26
+#define ZX234290_REG_ADDR_ADC2_MSB 0x27
+#define ZX234290_REG_ADDR_ADC2_LSB 0x28
+
+ /* sink control */
+#define ZX234297_REG_ADDR_SINK_CONTROL 0x29
+
+ /* rtc */
+#define ZX234290_REG_ADDR_RTC_CTRL1 0x30
+#define ZX234290_REG_ADDR_RTC_CTRL2 0x31
+
+ /* date and time */
+#define ZX234290_REG_ADDR_SECONDS 0x32
+#define ZX234290_REG_ADDR_MINUTES 0x33
+#define ZX234290_REG_ADDR_HOURS 0x34
+#define ZX234290_REG_ADDR_DAY 0x35
+#define ZX234290_REG_ADDR_WEEK 0x36
+#define ZX234290_REG_ADDR_MONTH 0x37
+#define ZX234290_REG_ADDR_YEAR 0x38
+
+ /* alarm */
+#define ZX234290_REG_ADDR_ALARM_MINUTE 0x39
+#define ZX234290_REG_ADDR_ALARM_HOUR 0x3A
+#define ZX234290_REG_ADDR_ALARM_DAY 0x3B
+#define ZX234290_REG_ADDR_ALARM_WEEK 0x3C
+#define ZX234290_REG_ADDR_ALARM_SECOND 0x3D
+
+#define ZX234290_REG_ADDR_TIMER_CTRL 0x3E
+#define ZX234290_REG_ADDR_TIMER_CNT 0x3F
+
+ /* enable ldo output discharge resistance */
+#define ZX234290_REG_ADDR_EN_DISCH1 0x40
+#define ZX234290_REG_ADDR_EN_DISCH2 0x41
+
+ /* power key control */
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43
+
+#define ZX234290_REG_ADDR_VERSION 0x44
+
+ /*fault status*/
+#define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45
+#define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46
+
+#define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47
+#define ZX234290_REG_ADDR_LDO_INT_MASK 0x48
+
+#define ZX234290_REG_ADDR_USER_RESERVED 0x50
+#define ZX234290_REG_ADDR_GMT_TESTING 0xf1
+
+#define ZX234290_MAX_REGISTER 0x51 //yuxiang ?
+
+/*0x04 status A*/
+#define ZX234290_STATUSA_POWERON_LSH (5)
+#define ZX234290_STATUSA_POWERON_WID (1)
+#define ZX234290_STATUSA_EOCADC_LSH (2)
+#define ZX234290_STATUSA_EOCADC_WID (1)
+
+/* 0x06 STATUS REG -- STARTUP */
+#define ZX234290_SYSPOR_STATUS_PWRON_STARTUP (0x1 << 0) /* PWR ON button */
+#define ZX234290_SYSPOR_STATUS_RTC_ALARM_STARTUP (0x1 << 1)
+#define ZX234290_SYSPOR_STATUS_PSHOLD_STARTUP (0x1 << 2)
+#define ZX234290_SYSPOR_STATUS_PWRONLLP_STARTUP (0x1 << 3)
+
+/* discharger */
+#define ZX234290_DISCHG1_LSB_LSH (0)
+#define ZX234290_DISCHG1_LSB_WID (4)
+
+#define ZX234290_DISCHG1_MSB_LSH (5)
+#define ZX234290_DISCHG1_MSB_WID (2)
+
+#define ZX234290_DISCHG2_LSH (0)
+#define ZX234290_DISCHG2_WID (8)
+
+
+/* BUCK VOLTAGE */
+#define ZX234290_BUCK01_VSEL_LSH (0)
+#define ZX234290_BUCK01_VSEL_WID (6)
+
+/* BUCK SLEEP VOLTAGE */
+#define ZX234290_BUCK01_SLEEP_VSEL_LSH (0)
+#define ZX234290_BUCK01_SLEEP_VSEL_WID (6)
+
+/* BUCKS MODE CTROL */
+#define ZX234290_REGULATOR_MODE_WID (2)
+
+#define ZX234290_BUCK0_SLPMODE_LSH (0)
+#define ZX234290_BUCK0_NRMMODE_LSH (2)
+#define ZX234290_BUCK1_SLPMODE_LSH (4)
+#define ZX234290_BUCK1_NRMMODE_LSH (6) /*[7:6]*/
+#define ZX234290_BUCK2_SLPMODE_LSH (0)
+#define ZX234290_BUCK2_NRMMODE_LSH (2)
+#define ZX234290_BUCK3_SLPMODE_LSH (4)
+#define ZX234290_BUCK3_NRMMODE_LSH (6)
+#define ZX234290_BUCK4_SLPMODE_LSH (0)
+#define ZX234290_BUCK4_NRMMODE_LSH (2)
+
+/* LDO MODE, ONLY SLEEP MODE */
+#define ZX234290_LDO1_SLPMODE_LSH (0)
+#define ZX234290_LDO2_SLPMODE_LSH (2)
+#define ZX234290_LDO3_SLPMODE_LSH (4)
+#define ZX234290_LDO4_SLPMODE_LSH (6)
+#define ZX234290_LDO5_SLPMODE_LSH (0)
+#define ZX234290_LDO6_SLPMODE_LSH (2)
+#define ZX234290_LDO7_SLPMODE_LSH (4)
+#define ZX234290_LDO8_SLPMODE_LSH (6)
+#define ZX234290_LDO9_SLPMODE_LSH (2)
+#define ZX234290_LDO10_SLPMODE_LSH (4)
+//#define ZX234290_LDO11_SLPMODE_LSH (6)
+
+/* LDO VOLTAGE SELECT */
+#define ZX234290_LDO_VSEL_WID (4)
+
+#define ZX234290_LDO1_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_VSEL_LSH (0)
+#define ZX234290_LDO4_VSEL_LSH (4)
+#define ZX234290_LDO5_VSEL_LSH (0)
+#define ZX234290_LDO6_VSEL_LSH (4)
+#define ZX234290_LDO7_VSEL_LSH (0)
+#define ZX234290_LDO8_VSEL_LSH (4)
+#define ZX234290_LDO9_VSEL_LSH (4)
+#define ZX234290_LDO10_VSEL_LSH (0)
+#define ZX234290_LDO11_VSEL_LSH (0) /* [3:0] */
+
+#define ZX234290_VORTC_VSEL_WID (2)
+#define ZX234290_VORTC_VSEL_LSH (4) /* [5][4] */
+#define ZX234290_LDO5_VSEL_WID (2) /* [1][0]*/
+
+
+/* LDO SLEEP VOLTAGE */
+#define ZX234290_BUCK2_VSEL_WID (5)
+
+#define ZX234290_BUCK2_VSEL_LSH (0)
+
+#define ZX234290_LDO1_SLP_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_SLP_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_SLP_VSEL_LSH (0)
+#define ZX234290_LDO7_SLP_VSEL_LSH (0)
+#define ZX234290_LDO8_SLP_VSEL_LSH (0)
+#define ZX234290_LDO11_SLP_VSEL_LSH (0) /* [3:0] */
+
+/* ENABLE 0x21-0x22 */
+#define ZX234290_LDOS_ON_WID (1)
+
+#define ZX234290_LDO1_ON_LSH (0)
+#define ZX234290_LDO2_ON_LSH (1)
+#define ZX234290_LDO3_ON_LSH (2)
+#define ZX234290_LDO4_ON_LSH (3)
+#define ZX234290_LDO5_ON_LSH (4)
+#define ZX234290_LDO6_ON_LSH (5)
+#define ZX234290_LDO7_ON_LSH (6)
+#define ZX234290_LDO8_ON_LSH (7)
+
+#define ZX234290_LDO9_ON_LSH (1)
+#define ZX234297_LDO9_ON_LSH (0)
+#define ZX234290_LDO10_ON_LSH (2)
+#define ZX234297_LDO10_ON_LSH (1)
+#define ZX234290_BUCK1_ON_LSH (4)
+#define ZX234290_BUCK2_ON_LSH (5)
+#define ZX234290_BUCK3_ON_LSH (6)
+#define ZX234290_BUCK4_ON_LSH (7)
+
+/* LONG PRESSED TIME */
+#define ZX234290_PWRON_TIME_LSH (0)
+#define ZX234290_PWRON_TIME_WID (2)
+#define ZX234290_PWRON_LONGPRESS_EN_LSH (2)
+#define ZX234290_PWRON_LONGPRESS_EN_WID (1)
+#define ZX234290_PWRON_LLP_TODO_LSH (3) /* LLP long long pressed */
+#define ZX234290_PWRON_LLP_TODO_WID (1)
+
+/* sys ctrol 0x07 */
+#define ZX234290_SINK1_EN_LSH (0)
+#define ZX234290_SINK1_EN_WID (1)
+#define ZX234290_SINK2_EN_LSH (1)
+#define ZX234290_SINK2_EN_WID (1)
+#define ZX234290_ADC1_EN_LSH (4)
+#define ZX234290_ADC1_EN_WID (1)
+#define ZX234290_ADC2_EN_LSH (3)
+#define ZX234290_ADC2_EN_WID (1)
+#define ZX234290_ADC_START_LSH (5)
+#define ZX234290_ADC_START_WID (1)
+#define ZX234290_SOFTON_LSH (7)
+
+/* 0x08 */
+#define ZX234290_SINK2_CURSEL_LSH (0)
+#define ZX234290_SINK2_CURSEL_WID (4)
+/* 0x09 */
+#define ZX234290_SINK1_CURSEL_LSH (0)
+#define ZX234290_SINK1_CURSEL_WID (4)
+
+/* 0x20 */
+#define ZX234297_SINK1_SLP_MODE_LSH (6)
+#define ZX234297_SINK2_SLP_MODE_LSH (7)
+#define ZX234297_SINK_SLP_MODE_WID (1)
+/* 0x22 */
+#define ZX234297_SINK1_ON_LSH (2)
+#define ZX234297_SINK2_ON_LSH (3)
+#define ZX234297_SINK_ON_WID (1)
+/* 0x29 */
+#define ZX234297_SINK1_CURRENT_LSH (0)
+#define ZX234297_SINK2_CURRENT_LSH (4)
+#define ZX234297_SINK_CURRENT_WID (4)
+
+#define ZX234290_LDO_RSTERR_LSH (0)
+#define ZX234290_LDO_RSTERR_WID (1)
+
+#endif /* end of ZX234290 */
+
+#define ZX234290_BITFVAL(var, lsh) ( (var) << (lsh) )
+#define ZX234290_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) )
+#define ZX234290_BITFEXT(var, wid, lsh) ((var & ZX234290_BITFMASK(wid, lsh)) >> (lsh))
+
+/* VBA - BUCK1 6bit */
+typedef enum _T_ZDrvZx234290_VbuckA
+{
+ VBUCKA_0_675 = 0x00,
+ VBUCKA_0_700 = 0x02,
+ VBUCKA_0_750 = 0x06,
+ VBUCKA_0_800 = 0x0a,
+ VBUCKA_0_850 = 0x0e,
+ VBUCKA_0_900 = 0x12,/*default*/
+ VBUCKA_0_950 = 0x16,
+ VBUCKA_1_000 = 0x1a,
+ VBUCKA_1_050 = 0x1e,
+ VBUCKA_1_100 = 0x22,
+ VBUCKA_1_150 = 0x26,
+ VBUCKA_1_200 = 0x2a,
+ VBUCKA_1_250 = 0x2e,
+
+ VBUCKA_MAX
+
+}T_ZDrvZx234290_VbuckA;
+
+/* VBC - BUCK2 */
+typedef enum _T_ZDrvZx234290_VbuckC
+{
+ VBUCKC_0_850 = 0x00,
+ VBUCKC_0_900 = 0x02,
+ VBUCKC_0_950 = 0x04,
+ VBUCKC_1_000 = 0x06,
+ VBUCKC_1_050 = 0x08,
+ VBUCKC_1_100 = 0x0a,
+ VBUCKC_1_150 = 0x0c,
+ VBUCKC_1_200 = 0x0e,/*default*/
+ VBUCKC_1_250 = 0x10,
+ VBUCKC_1_300 = 0x12,
+ VBUCKC_1_350 = 0x14,
+ VBUCKC_1_400 = 0x16,
+ VBUCKC_1_450 = 0x18,
+ VBUCKC_1_500 = 0x1a,
+ VBUCKC_1_550 = 0x1c,
+ VBUCKC_1_600 = 0x1e,
+
+ VBUCKC_MAX
+
+}T_ZDrvZx234290_VbuckC;
+
+/* VLA - ldo1/9/10 */
+typedef enum _T_ZDrvZx234290_VldoA
+{
+ VLDOA_0_725 = 0,
+ VLDOA_0_750 = 1,
+ VLDOA_0_775 = 2,
+ VLDOA_0_800 = 3,
+ VLDOA_0_825 = 4,
+ VLDOA_0_850 = 5,
+ VLDOA_0_875 = 6,
+ VLDOA_0_900 = 7,
+ VLDOA_0_925 = 8,
+ VLDOA_0_950 = 9,
+ VLDOA_0_975 = 10,
+ VLDOA_1_000 = 11,
+ VLDOA_1_025 = 12,
+ VLDOA_1_050 = 13,
+ VLDOA_1_075 = 14,
+ VLDOA_1_100 = 15,
+
+ VLDOA_MAX
+
+}T_ZDrvZx234290_VldoA;
+
+/* VLB - ldo5 2bit */
+typedef enum _T_ZDrvZx234290_VldoB
+{
+ VLDOB_3_300 = 0,
+ VLDOB_3_150 = 1,
+ VLDOB_3_000 = 2,
+ VLDOB_1_800 = 3, /* 11 */
+
+ VLDOB_MAX
+
+}T_ZDrvZx234290_VldoB;
+
+/* VLC - ldo2/ldo3 */
+typedef enum _T_ZDrvZx234290_VldoC
+{
+ VLDOC_0_750 = 0,
+ VLDOC_0_800 = 1,
+ VLDOC_0_850 = 2,
+ VLDOC_0_900 = 3,
+ VLDOC_0_950 = 4,
+ VLDOC_1_000 = 5,
+ VLDOC_1_050 = 6,
+ VLDOC_1_100 = 7,
+ VLDOC_1_200 = 8,
+ VLDOC_1_500 = 9,
+ VLDOC_1_800 = 10,
+ VLDOC_2_000 = 11,
+ VLDOC_2_500 = 12,
+ VLDOC_2_800 = 13,
+ VLDOC_3_000 = 14,
+ VLDOC_3_300 = 15,
+
+ VLDOC_MAX
+
+}T_ZDrvZx234290_VldoC;
+
+/* VLD - ldo4/6/7/8 */
+typedef enum _T_ZDrvZx234290_VldoD
+{
+ VLDOD_1_400 = 0,
+ VLDOD_1_500 = 1,
+ VLDOD_1_600 = 2,
+ VLDOD_1_800 = 3,
+ VLDOD_1_850 = 4,
+ VLDOD_2_000 = 5,
+ VLDOD_2_050 = 6,
+ VLDOD_2_500 = 7,
+ VLDOD_2_550 = 8,
+ VLDOD_2_700 = 9,
+ VLDOD_2_750 = 10,
+ VLDOD_2_800 = 11,
+ VLDOD_2_850 = 12,
+ VLDOD_2_900 = 13,
+ VLDOD_2_950 = 14,
+ VLDOD_3_000 = 15,
+
+ VLDOD_MAX
+
+}T_ZDrvZx234290_VldoD;
+
+/* VORTC 2bit */
+typedef enum _T_ZDrvZx234290_VldoE
+{
+ VLDOE_1_800 = 0,
+ VLDOE_2_500 = 1,
+ VLDOE_3_000 = 2,
+ VLDOE_3_300 = 3, /* 11 */
+
+ VLDOE_MAX
+
+}T_ZDrvZx234290_VldoE;
+
+/* VLF - ldo10 */
+typedef enum _T_ZDrvZx234297_VldoF
+{
+ VLDOF_0_800 = 0,
+ VLDOF_0_850 = 1,
+ VLDOF_0_900 = 2,
+ VLDOF_0_950 = 3,
+
+ VLDOF_1_000 = 4,
+ VLDOF_1_050 = 5,
+ VLDOF_1_100 = 6,
+ VLDOF_1_200 = 7,
+
+ VLDOF_1_300 = 8,
+ VLDOF_1_400 = 9,
+ VLDOF_1_500 = 10,
+ VLDOF_1_800 = 11,
+
+ VLDOF_2_500 = 12,
+ VLDOF_2_800 = 13,
+ VLDOF_3_000 = 14,
+ VLDOF_3_300 = 15,
+
+ VLDOF_MAX
+
+}T_ZDrvZx234297_VldoF;
+
+/* BUCK3/4 EXTERNAL ADJUSTABLE */
+
+typedef enum _T_ZDrvZx234290_LDO_ENABLE
+{
+ LDO_ENABLE_OFF = 0, /* 00 */
+ LDO_ENABLE_ON = 1, /* 10 */
+
+ LDO_AVTICE_MAX
+}T_ZDrvZx234290_LDO_ENABLE;
+
+
+/*
+ ¹ØÓÚ BUCKSµÄģʽ£¬·ÖΪÕý³£Ä£Ê½Óë˯Ãßģʽ£¬ Õý³£Ä£Ê½Ö»¹Ø×¢PFM/PWM£¬²»¹Ø×¢¿ª¹Ø¡£
+ ˯Ãßģʽ¹Ø×¢PFM/PWM/ECO/OFF/NRM£¬Ó¦¸Ã½âÊÍΪ ˯ÃßģʽµÄ״̬²»½ö¹Ø×¢PWM/PFM£¬
+ ¶øÇÒ¹Ø×¢´ò¿ª¹Ø±Õ£¬³ýÁËOFF£¬ÆäËû¶¼ÊÇÔÚ¿ª×ŵÄÇé¿öϵÄģʽ£»¶øĬÈÏ¿ªµÄÇé¿öÔòÊÇ
+ NRMMODE£¬µçѹÓÃ˯Ãßµçѹ£»
+ ¶øLDOSµÄ˯Ãßģʽ£¬Ò»ÑùÓëÕý³£Ä£Ê½²»Ïà¸É¡£ÆäÒ²ÓÐNRM/ECO/OFFÕ⼸ÖÖ״̬
+*/
+
+/* BUCK1/2/3/4 NORMAL MODE */
+typedef enum _T_ZDrvZx234290_BUCK_NRMMODE
+{
+ BUCK_NRM_AUTO_WITH_ECO = 0, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRM_FORCE_PWM = 2, /* 10 FORCE PWM */
+ BUCK_NRM_AUTO_WITHOUT_ECO = 3, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRMMODE_MAX
+}T_ZDrvZx234290_BUCK_NRMMODE;
+
+/* BUCK1 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK1_SLPMODE
+{
+ BUCK1_SLP_AUTO_WITHOUT_ECO = 0, /* 00/11 AUTO PWM/PFM */
+ BUCK1_SLP_AUTO_ECO = 1, /*BUCK1_SLP_AUTO_ECO_VOLT output voltage configred by FBDC1[5:0]*/
+ BUCK1_SLP_AUTO_ECO_SLP = 2, /* output voltage configred by FBDC1_SLP[5:0]*/
+ BUCK1_SLP_SHUTDOWN = 3, /* 11 OFF */
+ BUCK1_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK1_SLPMODE;
+
+/* BUCK2/3/4 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK234_SLPMODE
+{
+ BUCK234_SLP_AUTO_WITHOUT_ECO = 0, /* 00 AUTO PWM/PFM without eco*/
+ BUCK234_SLP_ECO_WITH_ECO = 1, /* 01Óë10¾ùÊÇ ECO */
+ BUCK234_SLP_SHUTDOWN = 3, /* 11 OFF */
+
+ BUCK234_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK234_SLPMODE;
+
+/* LDO1/2/3/7/8/9/10 SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOA_SLPMODE
+{
+ LDOA_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT_SLP = 2, /* VOLDOx_SLP[3:0] */
+ LDOA_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOA_SLPMODE_MAX
+}T_ZDrvZx234290_LDOA_SLPMODE;
+
+/* LDO4/5/6/ SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOB_SLPMODE
+{
+ LDOB_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOB_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOB_SLP_NRM_MODE_VOLT = 2, /* VOLDOx[3:0] */
+ LDOB_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOB_SLPMODE_MAX
+}T_ZDrvZx234290_LDOB_SLPMODE;
+
+typedef enum _T_ZDrvZx234290_LdoDischarger
+{
+ DISCHARGER_LDO_9 = 0,
+ DISCHARGER_LDO_10,
+ DISCHARGER_LDO_X, /*not support*/
+ DISCHARGER_BUCK_4,
+ DISCHARGER_BUCK_3,
+ DISCHARGER_BUCK_2,
+ DISCHARGER_BUCK_1,
+ DISCHARGER_BUCK_X, /*not support*/
+
+ DISCHARGER_LDO_1,
+ DISCHARGER_LDO_2,
+ DISCHARGER_LDO_3,
+ DISCHARGER_LDO_4,
+ DISCHARGER_LDO_5,
+ DISCHARGER_LDO_6,
+ DISCHARGER_LDO_7,
+ DISCHARGER_LDO_8,
+
+ DISCHARGER_MAX
+}T_ZDrvZx234290_LdoDischarger;
+
+typedef enum _T_ZDrvZx234290_DISCHARGER_ENABLE
+{
+ DISCHARGER_DISBALE = 0, /* 00 */
+ DISCHARGER_ENABLE = 1, /* 10 */
+
+ DISCHARGER_ENABLE_MAX
+}T_ZDrvZx234290_DISCHARGER_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LdoList
+{
+ LDOLIST_BUCK_1 = 0,
+ LDOLIST_BUCK_2,
+ LDOLIST_BUCK_3,
+ LDOLIST_BUCK_4,
+ LDOLIST_LDO_1,
+ LDOLIST_LDO_2,
+ LDOLIST_LDO_3,
+
+ LDOLIST_LDO_4,
+ LDOLIST_LDO_5,
+ LDOLIST_LDO_6,//default off
+ LDOLIST_LDO_7,
+ LDOLIST_LDO_8,
+ LDOLIST_LDO_9,//default off
+ LDOLIST_LDO_10,
+ LDOLIST_LDO_RTC,
+
+ LDOLIST_MAX
+}T_ZDrvZx234290_LdoList;
+
+typedef enum _T_ZDrvZx234297_SINK
+{
+ ZX234297_SINK1 = 0, /* 00 */
+ ZX234297_SINK2 = 1, /* 10 */
+
+ ZX234297_SINK_MAX
+}T_ZDrvZx234297_SINK;
+
+typedef enum _T_ZDrvZx234297_SINK_SLPMODE
+{
+ SLPMODE_NORMAL = 0, /* 00 */
+ SLPMODE_SHUTDOWN = 1, /* 10 */
+
+ SLPMODE_MAX
+}T_ZDrvZx234297_SINK_SLPMODE;
+
+typedef enum _T_ZDrvZx234297_SINK_CURRENT
+{
+ SINK_CURRENT_5MA,
+ SINK_CURRENT_10MA,
+ SINK_CURRENT_15MA,
+ SINK_CURRENT_20MA,
+ SINK_CURRENT_30MA,
+ SINK_CURRENT_40MA,
+ SINK_CURRENT_50MA,
+ SINK_CURRENT_60MA,
+ SINK_CURRENT_70MA,
+ SINK_CURRENT_80MA,
+ SINK_CURRENT_90MA,
+ SINK_CURRENT_100MA,
+ SINK_CURRENT_110MA,
+ SINK_CURRENT_120MA,
+
+ SINK_CURRENT_MAX
+}T_ZDrvZx234297_SINK_CURRENT;
+
+typedef enum _T_ZDrvZx234290_ResetType
+{
+#if 0
+ ZX234290_USER_RST_UNDEFINE = 0,
+ ZX234290_USER_RST_TO_NORMAL = 1,
+ ZX234290_USER_RST_TO_CHARGER = 2,
+ ZX234290_USER_RST_TO_ALARM = 3,
+#else
+ ZX234290_USER_RST_UNDEFINE = 3,
+ ZX234290_USER_RST_TO_NORMAL = 0,
+ ZX234290_USER_RST_TO_CHARGER = 1,
+ ZX234290_USER_RST_TO_ALARM = 2,
+#endif
+ ZX234290_USER_RST_TO_EXCEPT = 4,
+
+ ZX234290_USER_RST_MAX
+}T_ZDrvZx234290_ResetType;
+
+
+int zx234290_get_chip_version(void);
+int zx234290_irq_init(struct zx234290 *zx234290);
+
+int zx234290_set_buck1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_buck1_onoff(void);
+int zx234290_set_buck1_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+T_ZDrvZx234290_BUCK_NRMMODE zx234290_get_buck1_active_mode(void);
+int zx234290_set_buck1_voltage(T_ZDrvZx234290_VbuckA vol);
+T_ZDrvZx234290_VbuckA zx234290_get_buck1_voltage(void);
+int zx234290_set_buck1_sleep_mode(T_ZDrvZx234290_BUCK1_SLPMODE status);
+T_ZDrvZx234290_BUCK1_SLPMODE zx234290_get_buck1_sleep_mode(void);
+int zx234290_set_buck1_sleep_voltage(T_ZDrvZx234290_VbuckA vol);
+
+int zx234290_set_buck2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck2_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck2_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+int zx234290_set_buck3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck3_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck3_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+int zx234290_set_buck4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck4_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck4_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+
+int zx234290_set_ldo1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo1_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo1_onoff(void);
+int zx234290_set_ldo1_voltage(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA zx234290_get_ldo1_voltage(void);
+int zx234290_set_ldo1_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo1_sleep_mode(void);
+
+
+int zx234290_set_ldo2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo2_onoff(void);
+int zx234290_set_ldo2_voltage(T_ZDrvZx234290_VldoC vol);
+T_ZDrvZx234290_VldoC zx234290_get_ldo2_voltage(void);
+int zx234290_set_ldo2_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo2_sleep_mode(void);
+
+int zx234290_set_ldo3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo3_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo4_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+
+
+int zx234290_set_ldo5_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo5_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo5_onoff(void);
+int zx234290_set_ldo5_voltage(T_ZDrvZx234290_VldoB vol);
+T_ZDrvZx234290_VldoB zx234290_get_ldo5_voltage(void);
+int zx234290_set_ldo5_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo5_sleep_mode(void);
+
+int zx234290_set_ldo6_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo6_onoff(void);
+int zx234290_set_ldo6_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo6_voltage(void);
+int zx234290_set_ldo6_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo6_sleep_mode(void);
+
+int zx234290_set_ldo7_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo7_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo8_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo8_onoff(void);
+int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo8_voltage(void);
+int zx234290_set_ldo8_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo8_sleep_mode(void);
+int zx234290_set_ldo9_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo9_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo10_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo10_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo10_onoff(void);
+T_ZDrvZx234297_VldoF zx234290_get_ldo10_voltageF(void);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo10_sleep_mode(void);
+int zx234297_set_ldo10_voltageF(T_ZDrvZx234297_VldoF vol);
+
+int zDrvPmic_SetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Onoff_PSM(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_SetSleep_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_GetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable* enable);
+int zDrvPmic_GetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int* voltage);
+
+
+/*adc fun*/
+uint get_battery_voltage(void);
+uint get_adc1_voltage(void);
+uint get_adc2_voltage(void);
+
+
+#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/include/linux/mmc/mmc_func.h b/patch/17.09_19.00/code/old/upstream/linux-5.10/include/linux/mmc/mmc_func.h
new file mode 100755
index 0000000..b2636ab
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/include/linux/mmc/mmc_func.h
@@ -0,0 +1,37 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2014, ÉîÛÚÊÐÖÐÐËͨѶ΢µç×Ó
+*
+* ÎļþÃû³Æ£º emmc_ramdump.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+
+
+#ifndef LINUX_MMC_MMC_FUNC_H
+#define LINUX_MMC_MMC_FUNC_H
+
+#include <linux/types.h>
+
+int mmc_ramdump_init(void);
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file stored;
+*/
+int mmc_bwrite(u32 start_addr, u32 data_size, void *src_buf);
+
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file will store;
+*/
+
+int mmc_bread(u32 start_addr, u32 data_size, void *dst);
+
+#endif /* LINUX_MMC_MMC_FUNC_H */
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
new file mode 100755
index 0000000..bcb6a53
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
@@ -0,0 +1,457 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_client_cap.c
+* Îļþ±êʶ: ramdump_client_cap.c
+* ÄÚÈÝÕªÒª: ramdump cap¿Í»§¶ËÒì³£ËÀ»úÏÖ³¡Êý¾Ýµ¼³öʵÏÖ
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2019/10/10 V1.0 Create 00130574 ´´½¨
+*
+*******************************************************************************/
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_arch.h"
+#include <linux/module.h>
+#include <linux/soc/zte/rpmsg.h>
+#include "ram_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* ³£Á¿¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* º¯ÊýÉùÃ÷ *
+*******************************************************************************/
+extern void ramdump_register_callbacks(void);
+extern unsigned char *ramdump_phy_to_vir(unsigned long phy, unsigned long size);
+extern void ramdump_shared_mem_init(void);
+extern void ramdump_data_transfer_to_device(void);
+extern void ramdump_oss_data_trans_init(void);
+extern unsigned char *ramdump_export_flag_base;
+
+/*******************************************************************************
+* ¾Ö²¿¾²Ì¬±äÁ¿¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_ON_DEFAULT_VAL (1)
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿¶¨Òå *
+*******************************************************************************/
+/*
+ * run time control dump or not, use ( echo "0" > ramdump_on ) to close ramdump
+ */
+int sysctl_ramdump_on_panic = RAMDUMP_ON_DEFAULT_VAL;
+int ramdump_cap_init_flag = -1;
+int ramdump_count = 0;
+int ramdump_server_exp_core = RAMDUMP_FALSE;
+#ifdef CONFIG_RAMDUMP_USER
+unsigned int sysctl_ramdump_on_user = 1;
+#endif
+unsigned int ramdump_export_mode = 0xFF;
+/* Cmm file content */
+unsigned char *ramdump_cap_cmm_buf = NULL;
+/* err log file */
+unsigned char *ramdump_cap_error_log = NULL;
+unsigned int *cap_ddr_len_base = NULL;
+unsigned int sysctl_ramdump_emmc_size = 0x0;
+unsigned int sysctl_ramdump_emmc_start_addr = 0xFFFF;
+
+static struct ctl_table cfg_ramdump_array[] = {
+#ifdef CONFIG_RAMDUMP_USER
+ {
+ .procname = "sysctl_ramdump_on_user",
+ .data = &sysctl_ramdump_on_user,
+ .maxlen = sizeof(sysctl_ramdump_on_user),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ .extra1 = SYSCTL_ZERO,
+ .extra2 = SYSCTL_ONE,
+ },
+#endif
+ {
+ .procname = "ramdump_start_addr",
+ .data = &sysctl_ramdump_emmc_start_addr,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ },
+ {
+ .procname = "ramdump_emmc_size",
+ .data = &sysctl_ramdump_emmc_size,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_doulongvec_minmax,
+ },
+
+ { }
+};
+
+static struct ctl_table sysctl_ramdump_table[] = {
+ {
+ .procname = "ramdump_ap",
+ .mode = 0555,
+ .child = cfg_ramdump_array,
+ },
+ { }
+};
+
+/*******************************************************************************
+* ¾Ö²¿º¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_handle
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) buf: icp msg addr
+* len: icp msg len
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp msg handle, common entry
+*******************************************************************************/
+static void ramdump_cap_icp_handle(void *buf, unsigned int len)
+{
+ ramdump_msg_t *icp_msg = (ramdump_msg_t *)buf;
+
+ ramdump_server_exp_core = RAMDUMP_SUCCESS;
+
+ switch(icp_msg->msg_id)
+ {
+ case RAMDUMP_MSG_EXCEPT:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+
+ default:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_create_channel
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ size: icp channel size
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_create_channel(T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
+{
+ return rpmsgCreateChannel(dstCoreID, chID, size);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_regcallback
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ callback:icp callback fun
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_regcallback (T_RpMsg_CoreID coreID, unsigned int chID, T_RpMsg_Callback callback)
+{
+ return rpmsgRegCallBack(coreID, chID, callback);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init_sysctl_table
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ×¢²ásysctlÃüÁÓû§Ì¬Ê¹ÓÃsysctl¿ØÖÆramdump´æ´¢µØÖ·
+*******************************************************************************/
+void ramdump_init_sysctl_table(void)
+{
+ register_sysctl_table(sysctl_ramdump_table);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp init
+*******************************************************************************/
+static int ramdump_cap_icp_init(void)
+{
+ int ret = 0;
+
+ ret = ramdump_cap_icp_create_channel(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ RAMDUMP_CHANNEL_SIZE);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ ret = ramdump_cap_icp_regcallback(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ ramdump_cap_icp_handle);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_notify_server_panic
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for cap notify ramdump server to panic
+*******************************************************************************/
+static int ramdump_notify_server_panic(void)
+{
+ int ret = 0;
+ T_RpMsg_Msg rpMsg = {0};
+ ramdump_msg_t ramdumpMsg = {0};
+
+ ramdumpMsg.msg_id = RAMDUMP_MSG_EXCEPT;
+ ramdumpMsg.cpu_id = CORE_AP;
+
+ rpMsg.coreID = RAMDUMP_SERVER_AP;
+ rpMsg.chID = RAMDUMP_CHANNEL;
+ rpMsg.flag = RPMSG_WRITE_INT | RPMSG_WRITE_IRQLOCK;
+ rpMsg.len = sizeof(ramdump_msg_t);
+ rpMsg.buf = &ramdumpMsg;
+
+ ret = rpmsgWrite(&rpMsg);
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_store_ram_conf
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) mem: addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: unsigend char*: changed addr
+* ÆäËü˵Ã÷: This function is used to store ram conf
+*******************************************************************************/
+static unsigned char *ramdump_cap_store_ram_conf(unsigned char *mem)
+{
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_ddr.bin",
+ (unsigned int)DDR_BASE_CAP_ADDR_PA,
+ (unsigned int)(DDR_BASE_CAP_ADDR_PA + *cap_ddr_len_base - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap.cmm",
+ (unsigned int)RAMDUMP_CAP_CMM_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_CMM_BUF_ADDR + RAMDUMP_CAP_CMM_BUF_LEN_REAL - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_err_log.txt",
+ (unsigned int)RAMDUMP_CAP_LOG_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_LOG_BUF_ADDR + RAMDUMP_CAP_LOG_BUF_LEN - 1));
+ return mem;
+}
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_cmm_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for server to generate cmm scripts
+*******************************************************************************/
+static void ramdump_cap_cmm_create(void)
+{
+ unsigned char *pcmm_buf = ramdump_cap_cmm_buf;
+
+ memset(ramdump_cap_cmm_buf, 0, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+
+ // store the cmm BEGIN
+ pcmm_buf += sprintf(pcmm_buf, "ENTRY &ramdump_dir\n");
+
+ // store procmodes regs
+ pcmm_buf = ramdump_arch_store_modes_regs(pcmm_buf);
+
+ // store ram config
+ pcmm_buf = ramdump_cap_store_ram_conf(pcmm_buf);
+
+ // store memory map control regs
+ pcmm_buf = ramdump_arch_store_mm_regs(pcmm_buf);
+
+ // store end symbol
+ pcmm_buf += sprintf(pcmm_buf, "ENDDO\n");
+
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_trans_cap_error_log_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to create err log file
+*******************************************************************************/
+static void ramdump_cap_error_log_create(void)
+{
+ unsigned char *buf = ramdump_cap_error_log;
+
+ memset(ramdump_cap_error_log, 0, RAMDUMP_CAP_LOG_BUF_LEN);
+ buf += sprintf(buf, "dump at core%d,", smp_processor_id());
+ if (current->mm != NULL)
+ buf += sprintf(buf, "in user,task is: %s\n", current->comm);
+ else
+ buf += sprintf(buf, "in kernel,task is: %s\n", current->comm);
+
+ if (ramdump_server_exp_core)
+ buf += sprintf(buf, "recv dumpinfo from ap\n");
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_ram_conf_table_add
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) ram_name: dump ram name
+ ram_start: dump ram start(virtual addr)
+ ram_size: dump ram size
+ ram_virt: dump ram virt addr
+ ram_flag: dump ram flag(copy/exter/callback)
+ ram_extra: dump ram extra access addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to add dump ram conf into public table
+*******************************************************************************/
+void ramdump_ram_conf_table_add(
+ char *ram_name,
+ unsigned long ram_phy,
+ unsigned long ram_size,
+ unsigned long ram_virt,
+ unsigned long ram_flag,
+ unsigned long ram_extra)
+{
+}
+void ramdump_init_cmm_buf(void)
+{
+ /* Cmm file content */
+ ramdump_cap_cmm_buf = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_CMM_BUF_ADDR, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+ /* err log file */
+ ramdump_cap_error_log = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_LOG_BUF_ADDR, RAMDUMP_CAP_LOG_BUF_LEN);
+ cap_ddr_len_base = (unsigned int *)ramdump_phy_to_vir((unsigned long)IRAM_BASE_ADDR_BOOT_DDR, sizeof(unsigned long));
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: RAMDUMP_SUCCESS or RAMDUMP_FAILED
+* ÆäËü˵Ã÷: This function is used for ramdump init
+*******************************************************************************/
+int __init ramdump_init(void)
+{
+ int ret = 0;
+ ramdump_printf("Ramdump cap init start!!!!!\n");
+
+ if (ramdump_cap_init_flag == RAMDUMP_TRUE)
+ return RAMDUMP_SUCCESS;
+ ramdump_printf("Ramdump cap init rpmsg start!!!!!\n");
+ ret = ramdump_cap_icp_init();
+ if (ret != RAMDUMP_ICP_SUCCESS)
+ return ret;
+
+ ramdump_register_callbacks();
+
+ ramdump_init_cmm_buf();
+
+ ramdump_init_sysctl_table();
+
+ ramdump_shared_mem_init();
+ ramdump_oss_data_trans_init();
+
+ ramdump_printf("Ramdump cap init success!\n");
+ ramdump_cap_init_flag = RAMDUMP_TRUE;
+
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_entry
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump entry
+*******************************************************************************/
+void ramdump_entry (void)
+{
+ unsigned long flags;
+ if (sysctl_ramdump_on_panic == false)
+ return;
+
+ /*
+ * we need lock the irq, this can`t be interrupt.
+ */
+ ramdump_irq_lock(flags);
+
+ if (!ramdump_cap_init_flag)
+ while(true); /* endless circle */
+
+ if (++ramdump_count > 1)
+ while(true); /* endless circle */
+
+ /*
+ * save all regs first.
+ */
+ ramdump_arch_save_all_regs();
+ // generate error log
+ ramdump_cap_error_log_create();
+
+ //Éú³Écmm½Å±¾µÄµ¼³öÅäÖÃ
+ ramdump_cap_cmm_create();
+
+ /* notify client ramdump */
+ ramdump_notify_server_panic();
+
+ ramdump_arch_clean_caches();
+ ramdump_export_mode = *(unsigned int *)ramdump_export_flag_base;
+
+ if((ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ || (ramdump_export_mode == RAMDUMP_MODE_SPINAND))
+ ramdump_data_transfer_to_device();
+
+ while(true)
+ ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
new file mode 100755
index 0000000..f3e91e9
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_device_trans.c
@@ -0,0 +1,754 @@
+/**
+ * @file oss_ramdump_osa.c
+ * @brief Implementation of Ramdump os adapt
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Qing Wang <wang.qing@sanechips.com.cn>
+ * @ingroup si_ap_oss_ramdump_id
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "ramdump.h"
+#include <linux/lzo.h>
+#include "ramdump_compress.h"
+#ifdef CONFIG_RAMDUMP_EMMC
+#include "ramdump_emmc.h"
+#endif
+#ifdef CONFIG_MTD_SPI_NAND
+#include "ramdump_spinand.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Extern function declarations *
+*******************************************************************************/
+extern unsigned char *ramdump_phy_to_vir(unsigned long phy, unsigned long size);
+extern int dump_printk_text(char *buffer, unsigned long len);
+
+/*******************************************************************************
+* Extern variable declarations *
+*******************************************************************************/
+extern unsigned int ramdump_compress_flag;
+extern unsigned char *ramdump_log_buf;
+extern unsigned int ramdump_export_mode;
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+/*Ö¸ÁîÖ¡³¤¶È */
+#define RAMDUMP_INTERACTIVE_DATA_LEN 40
+#define RAMDUMP_INTERACTIVE_ARRAY_LEN 10
+
+/* ramdump ºÍ ¹²ÏíÄÚ´æ½»»¥ÃüÁîÔ¼¶¨ */
+/*ͬ²½ÇëÇó*/
+#define RAMDUMP_PC_INTERACTIVE_REQ 1
+/*ͬ²½ÇëÇóÓ¦´ð,´«ÊäramdumpµÄÎļþÊýÄ¿*/
+#define RAMDUMP_TRANS_SERVER_INTERACTIVE_RSP 2
+/*ÇëÇó´«µÝÖ¸¶¨Îļþ±àºÅµÄÎļþÐÅÏ¢*/
+#define RAMDUMP_PC_FILE_INFO_READ_REQ 3
+/*ÇëÇó´«µÝÖ¸¶¨Îļþ±àºÅµÄÎļþÐÅÏ¢µÄÓ¦´ð£¬´«ÊäÎļþÃû¼°´óС*/
+#define RAMDUMP_TRANS_SERVER_FILE_INFO_READ_RSP 4
+/*ÇëÇó¶ÁÈ¡Ö¸¶¨Îļþ±àºÅµÄÎļþÄÚÈÝ*/
+#define RAMDUMP_PC_FILE_DATA_TRANS_REQ 5
+/*ÇëÇó¶ÁÈ¡Ö¸¶¨Îļþ±àºÅµÄÎļþÄÚÈݵÄÓ¦´ð£¬´«ÊäÎļþÄÚÈÝ*/
+#define RAMDUMP_TRANS_SERVER_FILE_DATA_TRANS_RSP 6
+/*´«Êä½áÊø*/
+#define RAMDUMP_PC_FILE_TRANS_DONE_REQ 7
+/*´«Êä½áÊøÓ¦´ð*/
+#define RAMDUMP_TRANS_SERVER_FILE_TRANS_DONE_RSP 8
+
+/* ´íÎóÀàÐÍ */
+/*Ö¸Áî´íÎó*/
+#define RAMDUMP_INTERACTIVE_CMD_ERROR 9
+/*ÇëÇó´«µÝÖ¸¶¨Îļþ±àºÅ´í*/
+#define RAMDUMP_FILE_NUMBER_ERROR 10
+/*ÇëÇó´«µÝÖ¸¶¨ÎļþλÖôóС´í*/
+#define RAMDUMP_FILE_SIZE_ERROR 11
+
+#define RAMDUMP_DELAY_MS_COUNT (2500)
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+/*
+ * struct TRANS WITH AP
+ */
+
+/* trans_server rsp pc, interactive msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int file_num;
+} ramdump_trans_server_interactive_req;
+
+/* trans_server rsp pc, file info msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ char file_name[RAMDUMP_RAMCONF_FILENAME_MAXLEN];
+ unsigned int file_size;
+} ramdump_trans_server_file_info_req;
+
+/* pc req trans_server, file info msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int file_id;
+} ramdump_pc_file_info_rsp;
+
+/* trans_server rsp pc, trans data msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int buf_addr;
+ unsigned int buf_left_size;
+} ramdump_trans_server_data_trans_req;
+
+/* pc req trans_server, trans data msg struct */
+typedef struct
+{
+ unsigned int cmd;
+ unsigned int file_id; /* Îļþ±àºÅ */
+ unsigned int offset; /* offsetΪÊý¾ÝÆ«ÒÆ */
+ unsigned int length; /* lengthΪÊý¾Ý³¤¶È */
+} ramdump_pc_trans_data_rsp;
+
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+char *ramdump_log_buf_region = NULL;
+unsigned int ramdump_log_buf_len = 0;
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+unsigned char *ramdump_shared_mem_base = NULL;
+unsigned char *ramdump_export_flag_base = NULL;
+int ramdump_file_num = 0;
+ramdump_file_t ramdump_device_fp = {0};
+ramdump_file_t ramdump_spinand_fp = {0};
+ramdump_file_t *g_ramdump_dev_fp;
+unsigned int ramdump_device_file_cnt = 0;
+unsigned char *ramdump_log_buf = NULL; /* ¸´ÓÃramdump´æ´¢µÄ128KB(Æ«ÒÆ16KB) */
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+static inline void ramdump_wait_delay( unsigned long ms)
+{
+ volatile int j = 0;
+ for (j = 0; j < 10000; j++);
+}
+/*******************************************************************************
+ * extern function implementations *
+ ******************************************************************************/
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_data_trans_write
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump to trans dump data to PC
+*******************************************************************************/
+int ramdump_oss_data_trans_write(unsigned char *buffer, unsigned int size)
+{
+ int ret;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ if (size > (RAMDUMP_SHARED_MEM_LEN- roundup(sizeof(ramdump_shmem_t), RAMDUMP_SHMEM_ALIGN_SIZE)));
+ ret = -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 1)){
+ memcpy(msg->buf, buffer, size);
+ msg->size = size;
+ msg->core_flag = 0;
+ msg->rw_flag = 2;
+ ret = size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_data_trans_read
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump to trans dump data to PC
+*******************************************************************************/
+int ramdump_oss_data_trans_read(unsigned char *buffer, unsigned int size)
+{
+ int ret;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ if (size > (RAMDUMP_SHARED_MEM_LEN - roundup(sizeof(ramdump_shmem_t), RAMDUMP_SHMEM_ALIGN_SIZE)))
+ ret = -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+ if (size < msg->size)
+ return -1;
+ memcpy(buffer, msg->buf, msg->size);
+ msg->size = size;
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+ ret = size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_data_trans_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for map ramdump_shared_mem_base
+*******************************************************************************/
+void ramdump_oss_data_trans_init(void)
+{
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ memset(msg, 0, sizeof(ramdump_shmem_t));
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for init fp head
+*******************************************************************************/
+int ramdump_device_init(void)
+{
+ int ret = 0;
+
+ ramdump_lzo_init();
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_init(&ramdump_device_fp);
+#endif
+ g_ramdump_dev_fp = &ramdump_device_fp;
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ret = ramdump_spinand_init(&ramdump_spinand_fp);
+#endif
+ g_ramdump_dev_fp = &ramdump_spinand_fp;
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_close
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for print close msg
+*******************************************************************************/
+void ramdump_device_close(void)
+{
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ramdump_emmc_close(&ramdump_device_fp);
+#endif
+ }
+ else if (ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ramdump_spinand_close(&ramdump_spinand_fp);
+#endif
+ }
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_fill_header
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý)
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump file header
+*******************************************************************************/
+int ramdump_fill_header(char *file_name, unsigned int file_size, ramdump_file_t *fp, unsigned int offset)
+{
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, file_name, RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+ fp->file_fp[ramdump_device_file_cnt].offset = offset;
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_file
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write file infomation
+*******************************************************************************/
+int ramdump_device_write_file(ramdump_trans_server_file_info_req *server_to_cap)
+{
+ int ret = -1;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ if (ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
+ return -1;
+
+ ret = ramdump_fill_header(server_to_cap->file_name,
+ server_to_cap->file_size,
+ &ramdump_device_fp,
+ ramdump_emmc_offset);
+#endif
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ if (ramdump_spinand_offset >= RAMDUMP_SPINAND_LEN)
+ return -1;
+
+ ret = ramdump_fill_header(server_to_cap->file_name,
+ server_to_cap->file_size,
+ &ramdump_spinand_fp,
+ ramdump_spinand_offset);
+#endif
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_file
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) fp£º Îļþ¾ä±ú
+* (´«³ö²ÎÊý) file_size Îļþ´óС
+* ·µ »Ø Öµ: ³É¹¦·µ»Ø0£¬Ê§°Ü·µ»Ø-1
+* ÆäËü˵Ã÷: This function is used for write file infomation
+*******************************************************************************/
+int ramdump_device_modify_file_size(ssize_t file_size)
+{
+ int ret = -1;
+ ramdump_file_t *fp = g_ramdump_dev_fp;
+
+ if(fp)
+ {
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+ }
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_file_head
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write file head
+*******************************************************************************/
+int ramdump_device_write_file_head(void)
+{
+ int ret = -1;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_write_file_head(&ramdump_device_fp);
+#endif
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ret = ramdump_spinand_write_file_head(&ramdump_spinand_fp);
+#endif
+ }
+ return ret;
+}
+
+int ramdump_do_write_log_txt(ramdump_file_t *fp)
+{
+ int ret = -1;
+ size_t dst_len = 0;
+ size_t send_len = 0;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+ char *buf = NULL;
+
+ memset(ramdump_log_buf, 0, RAMDUMP_LOG_BUF);
+ ret = dump_printk_text(ramdump_log_buf, RAMDUMP_LOG_BUF);
+ if(ret < 0){
+ printk("ramdump printk log buf failed!!\n");
+ return ret;
+ }
+ if (ramdump_compress_flag == 1){
+ ret = ramdump_lzo_compress(ramdump_log_buf, RAMDUMP_LOG_BUF, msg->buf, &dst_len);
+ buf = msg->buf;
+ }
+ if (ret != LZO_E_OK){
+ dst_len = RAMDUMP_LOG_BUF;
+ buf = ramdump_log_buf;
+ }
+ fp->file_num += 1;
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, "cap_log_buf.txt", RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+
+ if (fp == &ramdump_device_fp)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ fp->file_fp[ramdump_device_file_cnt].size = roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ ret = mmc_bwrite(RAMDUMP_EMMC_ADDR + ramdump_emmc_offset, dst_len, buf);
+ ramdump_emmc_write_file_head(fp);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+#endif
+ }
+ else if (fp == &ramdump_spinand_fp)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ send_len = roundup(dst_len, RAMDUMP_FLASH_ALIGN_SIZE);
+ fp->file_fp[ramdump_device_file_cnt].size = send_len;
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_spinand_offset;
+ ret = write_data(RAMDUMP_SPINAND_ADDR + ramdump_spinand_offset, send_len, buf);
+ ramdump_spinand_offset = ramdump_spinand_offset + send_len;
+#endif
+ }
+ else
+ {
+ printk("ramdump_do_write_logbuf error fp!\n");
+ return -1;
+ }
+ ramdump_device_file_cnt += 1;
+ return ret;
+}
+
+int ramdump_do_write_logbuf(ramdump_file_t *fp)
+{
+ char *buf = NULL;
+ int ret = -1;
+ size_t dst_len = 0;
+ size_t send_len = 0;
+ ramdump_shmem_t *msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+
+ if(!fp)
+ {
+ printk("ramdump_do_write_logbuf error: fp is Null\n");
+ return -1;
+ }
+
+ ramdump_log_buf_region = log_buf_addr_get();
+ ramdump_log_buf_len = log_buf_len_get();
+
+ if (ramdump_compress_flag == 1){
+ ret = ramdump_lzo_compress(ramdump_log_buf_region, ramdump_log_buf_len, msg->buf, &dst_len);
+ buf = msg->buf;
+ }
+ if (ret != LZO_E_OK){
+ dst_len = ramdump_log_buf_len;
+ buf = ramdump_log_buf_region;
+ }
+
+ fp->file_num += 1;
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, "cap_log_buf.bin", RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+
+ if (fp == &ramdump_device_fp)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ fp->file_fp[ramdump_device_file_cnt].size = roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+ ret = mmc_bwrite(RAMDUMP_EMMC_ADDR + ramdump_emmc_offset, dst_len, buf);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ ramdump_emmc_write_file_head(fp);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(dst_len, RAMDUMP_EMMC_ALIGN_SIZE);
+#endif
+ }
+ else if (fp == &ramdump_spinand_fp)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ send_len = roundup(dst_len, RAMDUMP_FLASH_ALIGN_SIZE);
+ fp->file_fp[ramdump_device_file_cnt].size = send_len;
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_spinand_offset;
+ ret = write_data(RAMDUMP_SPINAND_ADDR + ramdump_spinand_offset, send_len, buf);
+ ramdump_spinand_offset = ramdump_spinand_offset + send_len;
+#endif
+ }
+ else
+ {
+ printk("ramdump_do_write_logbuf error fp!\n");
+ return -1;
+ }
+
+ ramdump_device_file_cnt += 1;
+ ramdump_do_write_log_txt(fp);
+
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_logbuf
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write cap logbuf
+*******************************************************************************/
+int ramdump_device_write_logbuf(void)
+{
+ int ret = -1;
+
+ ret = ramdump_do_write_logbuf(g_ramdump_dev_fp);
+ if (ret < 0)
+ ramdump_printf("device memory trans file:cap_log_buf error!!!\n");
+ else
+ ramdump_printf("device memory trans file:cap_log_buf success!!!\n");
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_device_write_data
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for write data
+*******************************************************************************/
+int ramdump_device_write_data(ramdump_shmem_t *msg, unsigned int size, ssize_t *dstlen)
+{
+ int ret = 0;
+
+ if(ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ {
+#ifdef CONFIG_RAMDUMP_EMMC
+ ret = ramdump_emmc_write_data(msg, &ramdump_device_fp, size);
+ if(ret < 0)
+ *dstlen = 0;
+ else
+ *dstlen += roundup(ret, RAMDUMP_EMMC_ALIGN_SIZE);
+#endif
+ }
+ else if(ramdump_export_mode == RAMDUMP_MODE_SPINAND)
+ {
+#ifdef CONFIG_MTD_SPI_NAND
+ ret = ramdump_spinand_write_data(msg, &ramdump_spinand_fp, size);
+ if(ret < 0)
+ *dstlen = 0;
+ else
+ *dstlen += ret;
+#endif
+ }
+ else
+ return 0;
+ return ret;
+}
+
+/*******************************************************************************
+ * Global function implementations *
+ ******************************************************************************/
+void ramdump_shared_mem_init(void)
+{
+ ramdump_shared_mem_base = ramdump_phy_to_vir((unsigned long)RAMDUMP_SHARED_MEM_BASE, (unsigned long)RAMDUMP_MEM_LEN);
+ ramdump_export_flag_base = ramdump_phy_to_vir((unsigned long)IRAM_BASE_ADDR_RAMDUMP_MODE, sizeof(unsigned long));
+ ramdump_log_buf = ramdump_shared_mem_base + 0x4000;
+ ramdump_flash_alloc_transbuf();
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_data_transfer_to_device
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump to trans dump data to ap
+*******************************************************************************/
+void ramdump_data_transfer_to_device(void)
+{
+ int data_trans_max;
+ int file_cnt = 0;
+ int file_size = 0;
+ int file_offset = 0;
+ int file_left_size = 0;
+ int file_trans_size = 0;
+ int error_cmd = 0;
+ int ret = 0;
+ ssize_t file_dstlen = 0;
+
+ unsigned int req_buf[RAMDUMP_INTERACTIVE_ARRAY_LEN] = {0};
+ ramdump_trans_server_interactive_req cap_to_server_msg = {0};
+
+ /* interactive begin */
+ if(ramdump_device_init() < 0)
+ return;
+
+ ramdump_device_write_logbuf();
+ data_trans_max = RAMDUMP_SHARED_MEM_LEN - roundup(sizeof(ramdump_shmem_t), RAMDUMP_SHMEM_ALIGN_SIZE) - RAMDUMP_COMPRESS_OUT_LEN;
+ cap_to_server_msg.cmd = RAMDUMP_PC_INTERACTIVE_REQ;
+ ramdump_oss_data_trans_write((unsigned char*)(&cap_to_server_msg), sizeof(cap_to_server_msg));
+
+ for(;;)
+ {
+ ramdump_oss_data_trans_read((unsigned char *)req_buf, RAMDUMP_INTERACTIVE_DATA_LEN);
+ switch (*(unsigned int *)req_buf)
+ {
+ case RAMDUMP_TRANS_SERVER_INTERACTIVE_RSP:
+ {
+ ramdump_pc_file_info_rsp cap_to_server_msg ={0};
+ ramdump_trans_server_interactive_req *server_to_cap_msg = (ramdump_trans_server_interactive_req *)req_buf;
+ /* data from server to cap */
+ ramdump_file_num = server_to_cap_msg->file_num;
+ ramdump_device_fp.file_num += ramdump_file_num;
+ ramdump_spinand_fp.file_num += ramdump_file_num;
+
+ /* data from cap to server */
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_INFO_READ_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+ sizeof(cap_to_server_msg));
+
+ break;
+ }
+ case RAMDUMP_TRANS_SERVER_FILE_INFO_READ_RSP:
+ {
+ ramdump_pc_trans_data_rsp cap_to_server_msg = {0};
+ ramdump_trans_server_file_info_req *server_to_cap_msg = (ramdump_trans_server_file_info_req *)req_buf;
+ /* data from server to cap */
+ /*device memory file create*/
+ if(ramdump_device_write_file(server_to_cap_msg) == -1){
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
+ ramdump_device_write_file_head();//±£Ö¤³ö´íÇ°¼¸¸öÎļþ¾ùд¶Ô¡£
+ ramdump_printf("ramdump write emmc file error!\n");
+ }
+ file_size = server_to_cap_msg->file_size;
+ file_offset = 0;
+ file_left_size = file_size;
+ /* data from cap to server */
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_DATA_TRANS_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+ cap_to_server_msg.offset = file_offset;
+ if (file_size >= data_trans_max)
+ cap_to_server_msg.length = data_trans_max;
+ else
+ cap_to_server_msg.length = file_size;
+ file_trans_size = cap_to_server_msg.length;
+ file_left_size = file_left_size - cap_to_server_msg.length;
+ file_offset = file_offset + cap_to_server_msg.length;
+ printk("device memory trans file:%s !!!\n", server_to_cap_msg->file_name);
+ /* interactive data trans */
+ ramdump_oss_data_trans_write(
+ (unsigned char*)(&cap_to_server_msg),
+ sizeof(cap_to_server_msg));
+
+ break;
+ }
+ case RAMDUMP_TRANS_SERVER_FILE_DATA_TRANS_RSP:
+ {
+ int write_len = 0;
+ ramdump_pc_trans_data_rsp cap_to_server_msg = {0};
+ /* data from server to cap */
+ ramdump_shmem_t *server_to_cap_msg = (ramdump_shmem_t *)ramdump_shared_mem_base;
+ server_to_cap_msg->core_flag = 0;
+ /*data from cap to emmc*/
+
+ write_len = ramdump_device_write_data(server_to_cap_msg, file_left_size, &file_dstlen);
+ if(write_len < 0)
+ {
+ ramdump_printf("ramdump write emmc data error!\n");
+ }
+
+ /*ÅжÏÊ£Óà´óС*/
+ if (file_left_size == 0)
+ {
+ file_cnt++;
+ if (file_cnt == ramdump_file_num)
+ {
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_TRANS_DONE_REQ;
+ }
+ else
+ {
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_INFO_READ_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+ }
+ ramdump_device_modify_file_size(file_dstlen);
+ file_dstlen = 0;
+ ramdump_device_file_cnt++;
+ }
+ else
+ {
+ /* data from cap to server */
+ if (file_left_size >= data_trans_max)
+ cap_to_server_msg.length = data_trans_max;
+ else
+ cap_to_server_msg.length = file_left_size;
+ cap_to_server_msg.cmd = RAMDUMP_PC_FILE_DATA_TRANS_REQ;
+ cap_to_server_msg.file_id = file_cnt;
+ cap_to_server_msg.offset = file_offset;
+ file_left_size = file_left_size - cap_to_server_msg.length;
+ file_offset= file_offset + cap_to_server_msg.length;
+ }
+
+ ramdump_oss_data_trans_write((unsigned char *)(&cap_to_server_msg), sizeof(cap_to_server_msg));
+ continue;
+ }
+ case RAMDUMP_TRANS_SERVER_FILE_TRANS_DONE_RSP:
+ {
+ ramdump_device_close();
+ return;
+ }
+ default:
+ {
+ error_cmd = RAMDUMP_INTERACTIVE_CMD_ERROR;
+ ramdump_printf("ramdump trans emmc error:%d!\n", error_cmd);
+ /* interactive data trans */
+ break;
+ }
+ }
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
new file mode 100755
index 0000000..0c28f27
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
@@ -0,0 +1,170 @@
+/**
+ * @file oss_ramdump_osa.c
+ * @brief Implementation of Ramdump os adapt
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Qing Wang <wang.qing@sanechips.com.cn>
+ * @ingroup si_ap_oss_ramdump_id
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_emmc.h"
+#include "ram_config.h"
+#include "ramdump_compress.h"
+#include <linux/lzo.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Extern function declarations *
+*******************************************************************************/
+
+/*******************************************************************************
+* Extern variable declarations *
+*******************************************************************************/
+extern unsigned char *ramdump_shared_mem_base;
+extern unsigned char *ramdump_emmc_flag_base;
+extern unsigned int ramdump_compress_flag;
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define RAMDUMP_DELAY_MS_COUNT (2500)
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+unsigned int ramdump_emmc_size = 0;
+volatile unsigned int ramdump_emmc_offset = 0;
+extern unsigned int ramdump_device_file_cnt;
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+static inline void ramdump_wait_delay( unsigned long ms)
+{
+ volatile int j = 0;
+ for (j = 0; j < 10000; j++);
+}
+
+/*******************************************************************************
+ * Local function implementations *
+ ******************************************************************************/
+int ramdump_emmc_init(ramdump_file_t *fp)
+{
+ fp->magic = 0x2A2A2A2A;
+ ramdump_emmc_offset = roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE);
+
+ if(RAMDUMP_TRANS_EMMC_LEN > ramdump_emmc_offset)
+ {
+ ramdump_emmc_size = RAMDUMP_TRANS_EMMC_LEN - ramdump_emmc_offset;
+ }
+ else
+ {
+ printk("[ramdump] emmc start addr is %ld, emmc size= %ld, error: size smaller than ramdump file header, return!\n", sysctl_ramdump_emmc_start_addr, sysctl_ramdump_emmc_size);
+ return -1;
+ }
+
+ if(mmc_ramdump_init()){
+ ramdump_printf("EMMC init failed! No ramdump data trans to emmc!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp)
+{
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+ if (ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
+ return -1;
+
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, file_name, RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+}
+
+int ramdump_emmc_write_file_head(ramdump_file_t *fp)
+{
+ int ret = -1;
+ mmc_bwrite(RAMDUMP_EMMC_ADDR, roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE), fp);
+ return ret;
+}
+
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size)
+{
+ int ret = 0;
+ unsigned int buffer = RAMDUMP_EMMC_ADDR + ramdump_emmc_offset;
+
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+ if(msg->size >= (ramdump_emmc_size - fp->file_fp[ramdump_device_file_cnt].offset))
+ return -1;
+ ret = mmc_bwrite(buffer, msg->size, msg->buf);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(msg->size, RAMDUMP_EMMC_ALIGN_SIZE);
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+ ret = msg->size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+int ramdump_emmc_read(char *buffer, ramdump_shmem_t *msg, unsigned int size)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+void ramdump_emmc_close(ramdump_file_t *fp)
+{
+ fp->file_size = ramdump_emmc_offset;
+ ramdump_emmc_write_file_head(fp);
+ ramdump_printf("ramdump trans emmc finished!\n");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
new file mode 100755
index 0000000..1028ab2
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_emmc.h
+* Îļþ±êʶ: ramdump_emmc.h
+* ÄÚÈÝÕªÒª: ramdump emmcÍ·Îļþ
+* ʹÓ÷½·¨: #include "ramdump_emmc.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2016/3/10 V1.0 Create ÕÔ¾ü¿ü ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAMDUMP_EMMC_H
+#define _RAMDUMP_EMMC_H
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include <linux/mmc/mmc_func.h>
+
+/*******************************************************************************
+* Íⲿ±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+extern unsigned int sysctl_ramdump_emmc_start_addr;
+extern unsigned int sysctl_ramdump_emmc_size;
+extern volatile unsigned int ramdump_emmc_offset;
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_EMMC_ADDR (sysctl_ramdump_emmc_start_addr * 512)
+#define RAMDUMP_TRANS_EMMC_LEN (sysctl_ramdump_emmc_size * 512)
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+/**
+ * @brief ramdump_emmc_init .
+ *
+ * @param void.
+ *
+ * @return int.
+ * @retval standard error
+ * @note This function is used for ramdump init
+ */
+int ramdump_emmc_init(ramdump_file_t *fp);
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp);
+int ramdump_emmc_write_file_head(ramdump_file_t *fp);
+int ramdump_emmc_modify_file_size(ramdump_file_t *fp, unsigned int file_size);
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size);
+int ramdump_emmc_write_logbuf(ramdump_file_t *fp);
+void ramdump_emmc_close(ramdump_file_t *fp);
+int ramdump_emmc_write_log_txt(ramdump_file_t *fp);
+
+/*******************************************************************************
+* ÄÚÁªº¯ÊýʵÏÖ *
+*******************************************************************************/
+
+#endif //#ifndef _RAMDUMP_EMMC_H
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/tracker.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/tracker.c
new file mode 100755
index 0000000..6f7e1ab
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/kernel/tracker.c
@@ -0,0 +1,459 @@
+/*
+ * tracker.c - System accounting over taskstats interface
+ *
+ * Copyright (C) Jay Lan, <jlan@sgi.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/export.h>
+#include <linux/sched/clock.h>
+#include "ram_config.h"
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define _OS_LINUX 1
+
+#if defined(_OS_TOS)
+# define OS_STATISTIC_IRAM_BASE (IRAM_BASE_ADDR_OS_STATISTIC_PSCPU)
+# define OS_STATISTIC_TIME zDrvTimer_Stamp()
+#elif defined(_OS_LINUX)
+# define OS_STATISTIC_IRAM_BASE g_zxic_trace_apcpu_addr //(IRAM_BASE_ADDR_OS_STATISTIC_APCPU)
+# define OS_STATISTIC_TIME (cpu_clock(0)>>10)
+#else
+# error "unknown os"
+#endif
+
+
+
+#define OS_IRAM_STATISTIC_CNT (5)
+#define OS_IRAM_STATISTIC_NAME_LEN (16)
+#define OS_DDR_STATISTIC_CNT (1000)
+
+#define OS_IRAM_THREAD_SWAPIN (OS_STATISTIC_IRAM_BASE)
+#define OS_IRAM_IRQ_START (OS_IRAM_THREAD_SWAPIN + sizeof(t_os_iram_thread_statistic))
+#define OS_IRAM_IRQ_END (OS_IRAM_IRQ_START + sizeof(t_os_iram_statistic))
+
+#if defined(_OS_TOS)
+#define OS_IRAM_DSR_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_DSR_END (OS_IRAM_DSR_START + sizeof(t_os_iram_statistic))
+#elif defined(_OS_LINUX)
+#define OS_IRAM_SOFTIRQ_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_SOFTIRQ_END (OS_IRAM_SOFTIRQ_START + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_START (OS_IRAM_SOFTIRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_END (OS_IRAM_TIMER_START + sizeof(t_os_iram_statistic))
+#endif
+
+#define os_statistic_check() *((volatile unsigned long *)OS_STATISTIC_IRAM_BASE)
+#define os_statistic_enabled() g_os_statistic_enable
+
+/*******************************************************************************
+* Êý¾Ý½á¹¹¶¨Òå *
+*******************************************************************************/
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned char name[OS_IRAM_STATISTIC_NAME_LEN];
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_thread_statistic;
+
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_statistic;
+
+typedef struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_DDR_STATISTIC_CNT];
+}t_os_ddr_statistic;
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ *
+*******************************************************************************/
+#if defined(_OS_LINUX)
+volatile static char *g_zxic_trace_apcpu_addr;
+#endif
+
+volatile static int g_os_statistic_enable;
+volatile static unsigned int g_os_statistic_cnt;
+
+volatile static t_os_iram_thread_statistic *g_os_iram_swapin_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_iram_statistic *g_os_iram_dsr_start_statistic;
+static t_os_iram_statistic *g_os_iram_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_iram_statistic *g_os_iram_softirq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_softirq_end_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_end_statistic;
+#endif
+
+volatile static t_os_ddr_statistic *g_os_ddr_swapin_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_ddr_statistic *g_os_ddr_dsr_start_statistic;
+static t_os_ddr_statistic *g_os_ddr_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_end_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_end_statistic;
+#endif
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+void os_statistic_enable(void);
+/*******************************************************************************
+* ¾Ö²¿º¯Êý *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_statistic *iram;
+
+ iram = (t_os_iram_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+ iram->statistics[index].data1 = (unsigned int)data;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: Ï̹߳켣ͳ¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_thread_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_thread_statistic *iram;
+
+ iram = (t_os_iram_thread_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+#if defined(_OS_TOS)
+ strncpy((char *)(iram->statistics[index].name), cyg_thread_get_name((cyg_handle_t)data), OS_IRAM_STATISTIC_NAME_LEN - 1);
+#elif defined(_OS_LINUX)
+ strncpy((char *)(iram->statistics[index].name), ((struct task_struct *)data)->comm, OS_IRAM_STATISTIC_NAME_LEN - 1);
+#else
+# error "unkown os"
+#endif
+ iram->statistics[index].name[OS_IRAM_STATISTIC_NAME_LEN - 1] = 0;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_ddr(void *ddr_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_ddr_statistic *ddr;
+
+ ddr = (t_os_ddr_statistic *)ddr_addr;
+
+ index = ddr->index;
+ if (index >= OS_DDR_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+ ddr->statistics[index].data1 = (unsigned int)data;
+ ddr->statistics[index].data2 = time;
+ index++;
+
+ ddr->index = index;
+ ddr->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_info_update(void)
+{
+ g_os_statistic_cnt++;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¶¨Ê±Æ÷»Øµ÷¹³×Ó
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý)
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static int os_statistic_delayed_work_timer_fn(unsigned long data)
+{
+ int sec = 0;
+ msleep(20000);
+ while(!os_statistic_check())
+ {
+ //³¬¹ý40s£¬Ö±½ÓÍ˳ö
+ if(sec >= 4)
+ return 0;
+ msleep(10000);
+ sec++;
+ }
+ os_statistic_enable();
+ return 0;
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ʹÄܹ켣ͳ¼Æ¹¦ÄÜ
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) address: ¼Ç¼µ½IRAMÖеĵØÖ·
+ size: IRAM¿Õ¼ä´óС
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+void os_statistic_enable(void)
+{
+#if defined(_OS_TOS)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_dsr_start_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_START;
+ g_os_iram_dsr_end_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+#elif defined(_OS_LINUX)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_softirq_start_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_START;
+ g_os_iram_softirq_end_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_END;
+ g_os_iram_timer_start_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_START;
+ g_os_iram_timer_end_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+
+#else
+# error "unkown os"
+#endif
+ if ((unsigned int )g_os_iram_timer_end_statistic - (unsigned int )g_os_iram_swapin_statistic > (unsigned int )IRAM_BASE_LEN_OS_STATISTIC_PSCPU )
+ {
+ BUG();
+ }
+ g_os_statistic_enable = 1;
+}
+EXPORT_SYMBOL(os_statistic_enable);
+
+void zxic_trace_task_switch(struct task_struct *next)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_thread_in_iram(g_os_iram_swapin_statistic, next, time);
+ os_statistic_in_ddr(g_os_ddr_swapin_statistic, next, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_enter(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_start_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_start_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_exit(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_end_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_end_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_enter(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_start_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_start_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_exit(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_end_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_end_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_enter(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_start_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_start_statistic, func, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_exit(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_end_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_end_statistic, func, time);
+ os_statistic_info_update();
+}
+
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+int __init zxic_enable_tracer(void)
+{
+ struct timer_list timer;
+ struct task_struct *task;
+
+#ifdef IRAM_BASE_ADDR_VA
+ g_zxic_trace_apcpu_addr = IRAM_BASE_ADDR_OS_STATISTIC_PSCPU;
+#else
+ g_zxic_trace_apcpu_addr = ioremap(IRAM_BASE_ADDR_OS_STATISTIC_PSCPU, IRAM_BASE_LEN_OS_STATISTIC_PSCPU);
+#endif
+
+ /*
+ init_timer(&timer);
+ timer.expires = jiffies + 40*HZ;//msecs_to_jiffies(40*1000);//ÑÓ³Ù40Ãë
+ timer.data = 0;
+ timer.function = os_statistic_delayed_work_timer_fn;
+ setup_timer(&timer, os_statistic_delayed_work_timer_fn, 0);
+ add_timer(&timer);
+ */
+ //task = kthread_create(os_statistic_delayed_work_timer_fn, 0, "g_zxic_trace_sync_thread", 0);
+ //wake_up_process(task);
+ os_statistic_enable();
+ return 0x0;
+}
+module_init(zxic_enable_tracer);
+
+
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
new file mode 100755
index 0000000..f730067
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
@@ -0,0 +1,2041 @@
+/*
+ * zx297520v3_es8312.c -- zx29-ak4940 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/ak4940.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0xac
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ak4940_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "ak4940.1-0012",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, voice_platform),
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, dummy),
+
+},
+
+#if 0
+
+ [AUDIO_DL_MEDIA] = {
+ .name = "ak4940",
+ .stream_name = "MultiMedia",
+ .nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940, media_platform),
+ },
+
+ [AUDIO_DL_VOICE] = {
+
+ .name = "voice_call",
+ .stream_name = "voice",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ },
+ [AUDIO_DL_2G_AND_3G_VOICE] = {
+
+ .name = "voice_2g_3g",
+ .stream_name = "voice_2g_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice_2g_3g, ak4940, voice_audio),
+
+ },
+ [AUDIO_DL_VP_LOOP] = {
+
+ .name = "loop_test",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "snd-soc-dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops2,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ }, .stream_name = "loop_voice",
+
+ [AUDIO_DL_3G_VOICE] = {
+
+ .name = "voice_3g", // 3g nb,wb
+ .stream_name = "voice_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, voice_audio),
+
+ }
+#endif
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ak4940_of_match[] = {
+ { .compatible = "zxic,zx29_ak4940", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ak4940_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<15);
+ val |= 0x1<<15;; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+
+ val &= 0xfffffff8;
+ val |= 0x00000001;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ak4940_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_ak4940";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_ak4940",
+ .of_match_table = of_match_ptr(zx29_ak4940_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ak4940");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
new file mode 100755
index 0000000..1a8cf3e
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
@@ -0,0 +1,1346 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-dummycodec ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+ unsigned int armRegBit = 0;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x1;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ //if (ret < 0){
+ // print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ // return ret;
+ // }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ti3100_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0012", "tlv320aic31xx-hifi")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_dummycodec_of_match[] = {
+ { .compatible = "zxic,zx29_dummycodec", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_dummycodec_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+
+
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+ board->name = "zx29_dummycodec";
+ board->dev = &pdev->dev;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_dummycodec_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ //platform_set_drvdata(pdev, board);
+
+
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_dummycodec",
+ .of_match_table = of_match_ptr(zx29_dummycodec_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-dummycodec");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
new file mode 100755
index 0000000..1204542
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_es83xx.c
@@ -0,0 +1,1361 @@
+/*
+ * zx29_es83xx.c -- zx29-es83xx ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifdef CONFIG_SND_SOC_ES8311
+
+#include "../codecs/es8311.h"
+#endif
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+//#define NAU_CLK_ID 0
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+/* System Clock Source */
+enum {
+ CODEC_SCLK_MCLK,
+ CODEC_SCLK_PLL,
+};
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+ static int zx29_hw_params_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret =-EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8311_MCLK_PIN,params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+ static int zx29_hw_params_lp_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret =-EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ static int zx29_hw_params_voice_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret =-EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8311_MCLK_PIN,params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_tdm,
+#else
+ .hw_params = zx29_hw_params,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_lp_tdm,
+#else
+ .hw_params = zx29_hw_params_lp,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_voice_tdm,
+#else
+ .hw_params = zx29_hw_params_voice,
+#endif
+ //.prepare = zx29_prepare2,
+ };
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+ //static struct zx298501_nau8810_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(cpu_tdm, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1412000.tdm")));
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("es8311.1-0018", "ES8311 HiFi")));
+
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("es8374.1-001a", "es8374-hifi")));
+#else
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("es8311.1-0018", "es8311-hifi")));
+
+#endif
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(media_platform_tdm, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1412000.tdm")));
+
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, dummy_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+#endif
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, codec, media_platform),
+#endif
+},
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, dummy),
+
+},
+
+};
+
+
+
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef CONFIG_USE_TOP_TDM
+#else
+ #ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+ #endif
+#endif
+};
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+static const struct of_device_id zx29_codec_of_match[] = {
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+ { .compatible = "zxic,zx29_es8311", .data = &zx29_platform_data },
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+ { .compatible = "zxic,zx29_es8374", .data = &zx29_platform_data },
+#else
+ { .compatible = "zxic,zx29_es8311", .data = &zx29_platform_data },
+
+#endif
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_codec_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+ int ret = 0;
+ printk("%s start \n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: board name(%s)!\n", __func__,info->name);
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+#ifdef CONFIG_USE_TOP_TDM
+ //#if 1 //CONFIG_USE_PIN_I2S0
+ #if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+
+ #elif defined(CONFIG_USE_PIN_I2S1)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+ #endif
+
+#else
+
+ //#if 1 //CONFIG_USE_PIN_I2S0
+ #if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+
+ #elif defined(CONFIG_USE_TOP_I2S1)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+ #endif
+#endif
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+#if defined(CONFIG_USE_TOP_I2S0)
+ dev_info(dev, "%s: top_i2s0 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+
+
+#elif defined(CONFIG_USE_TOP_I2S1)
+ dev_info(dev, "%s: top_i2s1 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s1_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#elif defined(CONFIG_USE_TOP_TDM)
+ dev_info(dev, "%s: top_tdm pinctrl sel!!\n", __func__);
+ s = pinctrl_lookup_state(p, "top_tdm");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "toptdm_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#else
+ dev_info(dev, "%s: default top_i2s pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#endif
+ if(info != NULL){
+
+ info->p = p;
+ info->s = s;
+ info->s_sleep = s_sleep;
+ }
+//yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment start
+ ret = pinctrl_select_state(p, s_sleep);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+
+int zx29_i2s_config_default_pin(void)
+{
+ struct zx29_board_data *info = s_board;
+ int ret;
+
+ if (!info || !info->p || !info->s)
+ return -ENODEV;
+
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ pr_err(" %s select state failure %d!!\n", __func__, ret);
+ }
+
+ return ret;
+}
+
+int zx29_i2s_config_sleep_pin(void)
+{
+ struct zx29_board_data *info = s_board;
+ int ret;
+
+ if (!info || !info->p || !info->s_sleep)
+ return -ENODEV;
+
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ pr_err(" %s select state failure %d!!\n", __func__, ret);
+ }
+
+ return ret;
+}
+//yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment end
+
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
+#ifdef CONFIG_USE_TOP_TDM
+#else
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+ }
+#endif
+/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
+
+ id = of_match_device(of_match_ptr(zx29_codec_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+ board->name = "zx29_es8311";
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+ board->name = "zx29_es8374";
+#else
+ board->name = "zx29_es8311";
+
+#endif
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+#ifdef CONFIG_PM
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(&pdev->dev);
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(&pdev->dev);
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start![8311]\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(dev);
+ if((info->p != NULL)&&(info->s_sleep != NULL)){
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl sleep end!\n", __func__);
+ }
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(dev);
+ if((info->p != NULL)&&(info->s != NULL)){
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl active end!\n", __func__);
+ }
+
+
+ return snd_soc_resume(dev);
+
+}
+
+#else
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+
+
+ return snd_soc_resume(dev);
+
+}
+
+
+#endif
+
+struct dev_pm_ops zx29_snd_soc_pm_ops = {
+ .suspend = zx29_snd_soc_suspend,
+ .resume = zx29_snd_soc_resume,
+};
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+#if defined(CONFIG_SND_SOC_ZX29_ES8311)
+ .name = "zx29_es8311",
+#elif defined(CONFIG_SND_SOC_ZX29_ES8374)
+ .name = "zx29_es8374",
+
+#else
+ .name = "zx29_es8311",
+#endif
+ .of_match_table = of_match_ptr(zx29_codec_of_match),
+ .pm = &zx29_snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-es83xx");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
new file mode 100755
index 0000000..ea874ee
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
@@ -0,0 +1,2012 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/max9867.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define CODEC_CLK_ID 0
+#define CODEC_SCLK_MCLK_ID 0
+#define CODEC_SCLK_PLL_ID 1
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ #if 0
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+ #endif
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(max9867_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("max9867.1-001a", "max9867-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, max9867_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_max9867_of_match[] = {
+ { .compatible = "zxic,zx29_max9867", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_max9867_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p,*p2;
+ struct pinctrl_state *s,*s2;
+ int ret = 0;
+ printk("%s start n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s0 end!\n", __func__);
+ /*
+ p2 = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+ */
+
+ s2 = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ ret = pinctrl_select_state(p, s2);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s1 end!\n", __func__);
+
+
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_max9867_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_max9867";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static void zx29_audio_shutdown(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ;
+}
+static int zx29_audio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_max9867",
+ .of_match_table = of_match_ptr(zx29_max9867_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ .shutdown = zx29_audio_shutdown,
+ .suspend = zx29_audio_suspend,
+ .resume = zx29_audio_resume,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-max9867");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
new file mode 100755
index 0000000..1e5777d
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
@@ -0,0 +1,2325 @@
+/*
+ * zx297520v3_nau8810.c -- zx297520v3-nau8810 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/nau8810.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define NAU_CLK_ID 0
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+ static int zx29_hw_params_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_tdm,
+#else
+ .hw_params = zx29_hw_params,
+#endif
+
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_lp_tdm,
+#else
+ .hw_params = zx29_hw_params_lp,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_voice_tdm,
+#else
+ .hw_params = zx29_hw_params_voice,
+#endif
+
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx29_nau8810",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to nau8810 */
+#define ZX29_CODEC_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_codec_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(cpu_tdm, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1412000.tdm")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(nau8810, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-0012", "nau8810-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(nau8810_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-001a", "nau8810-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+
+ SND_SOC_DAILINK_DEF(media_platform_tdm, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1412000.tdm")));
+
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, dummy_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+#endif
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, nau8810_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, nau8810_codec, media_platform),
+#endif
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_nau8810_of_match[] = {
+ { .compatible = "zxic,zx29_nau8810", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_nau8810_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+ int ret = 0;
+ printk("%s start \n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: board name(%s)!\n", __func__,info->name);
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#elif defined(CONFIG_USE_TOP_I2S1)//defined(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+#if defined(CONFIG_USE_TOP_I2S0)
+ dev_info(dev, "%s: top_i2s0 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+
+
+#elif defined(CONFIG_USE_TOP_I2S1)
+ dev_info(dev, "%s: top_i2s1 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s1_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#elif defined(CONFIG_USE_TOP_TDM)
+ dev_info(dev, "%s: top_tdm pinctrl sel!!\n", __func__);
+ s = pinctrl_lookup_state(p, "top_tdm");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "toptdm_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#else
+ dev_info(dev, "%s: default top_i2s pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#endif
+ if(info != NULL){
+
+ info->p = p;
+ info->s = s;
+ info->s_sleep = s_sleep;
+ }
+
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+/*
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+*/
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_nau8810_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_nau8810";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+
+#ifdef CONFIG_PM
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(&pdev->dev);
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(&pdev->dev);
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(dev);
+ if((info->p != NULL)&&(info->s_sleep != NULL)){
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl sleep end!\n", __func__);
+ }
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(dev);
+ if((info->p != NULL)&&(info->s != NULL)){
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl active end!\n", __func__);
+ }
+
+
+ return snd_soc_resume(dev);
+
+}
+
+#else
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+
+
+ return snd_soc_resume(dev);
+
+}
+
+
+#endif
+
+
+struct dev_pm_ops zx29_snd_soc_pm_ops = {
+ .suspend = zx29_snd_soc_suspend,
+ .resume = zx29_snd_soc_resume,
+ .freeze = snd_soc_suspend,
+ .thaw = snd_soc_resume,
+ .poweroff = snd_soc_poweroff,
+ .restore = snd_soc_resume,
+};
+
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_nau8810",
+ .of_match_table = of_match_ptr(zx29_nau8810_of_match),
+ //.pm = &snd_soc_pm_ops,
+ .pm = &zx29_snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_nau8810_snd_device, &zx29xx_nau8810, sizeof(zx29xx_nau8810));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-nau8810");
diff --git a/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
new file mode 100755
index 0000000..9959350
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
@@ -0,0 +1,2011 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/tlv320aic31xx.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_TI3100_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_TI3100_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018", "tlv320aic3x-hifi")));
+
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+#else
+
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+
+#endif
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, codec, dummy),
+ SND_SOC_DAILINK_REG(voice_cpu, codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ti3100_of_match[] = {
+ { .compatible = "zxic,zx29_ti3100", .data = &zx29_platform_data },
+ { .compatible = "zxic,zx29_ti3104", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ti3100_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ti3100_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ board->name = "zx29_ti3104";
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ board->name = "zx29_ti3100";
+#else
+ board->name = "zx29_ti3100";
+
+#endif
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ .name = "zx29_ti3104",
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ .name = "zx29_ti3100",
+#else
+ .name = "zx29_ti3100",
+
+#endif
+ .of_match_table = of_match_ptr(zx29_ti3100_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ti3100");
diff --git a/patch/17.09_19.00/code/old/upstream/pub/include/infra/pub_debug_info.h b/patch/17.09_19.00/code/old/upstream/pub/include/infra/pub_debug_info.h
new file mode 100755
index 0000000..95a480f
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/pub/include/infra/pub_debug_info.h
@@ -0,0 +1,48 @@
+#ifndef _PUB_DEBUG_INFO_H_
+#define _PUB_DEBUG_INFO_H_
+
+#include <stdarg.h>
+
+#define DEBUG_INFO_DEV_PATH "/dev/debug_info"
+
+/* AP²àºÍCAP²àµÄPS\KERNEL\DRIVER\FS\APP ÒÔSTART~ENDΪÇø¼ä£¬¸÷²¿·ÖÔ¤ÁôÁË100¸öID */
+
+#define MODULE_ID_PS_NAS ("ps_nas")
+#define MODULE_ID_PS_RRC ("ps_rrc")
+#define MODULE_ID_PS_L2 ("ps_l2")
+#define MODULE_ID_PS_UICC ("ps_uicc")
+#define MODULE_ID_AP_USB ("ap_usb")
+#define MODULE_ID_AP_REBOOT ("ap_reboot")
+#define MODULE_ID_AP_TSC ("ap_tsc")
+#define MODULE_ID_AP_PSM ("ap_psm")
+#define MODULE_ID_AP_NAND ("ap_nand")
+#define MODULE_ID_AP_MMC ("ap_mmc")
+#define MODULE_ID_AP_WIFI ("ap_wifi")
+
+
+#define MODULE_ID_CAP_USB ("cap_usb")
+#define MODULE_ID_CAP_TSC ("cap_tsc")
+#define MODULE_ID_CAP_PSM ("cap_psm")
+#define MODULE_ID_CAP_NAND ("cap_nand")
+#define MODULE_ID_CAP_SPI ("cap_spi")
+#define MODULE_ID_CAP_MMC ("cap_mmc")
+#define MODULE_ID_CAP_UART ("cap_uart")
+#define MODULE_ID_CAP_PM ("cap_pm")
+
+
+#define MODULE_ID_AP_JFFS2 ("ap_jffs2")
+#define MODULE_ID_AP_FOTA ("ap_fota")
+#define MODULE_ID_AP_FS_CHECK ("ap_fs_check")
+
+#define MODULE_ID_CAP_FOTA ("cap_fota")
+#define MODULE_ID_CAP_FS_CHECK ("cap_fs_check")
+
+#if defined(_USE_ZXIC_DEBUG_INFO)
+int sc_debug_info_vrecord(char *id, const char *format, va_list args);
+int sc_debug_info_record(char *id, const char *format, ...);
+#else
+static inline int sc_debug_info_vrecord(char *id, const char *format, va_list args) { return 0; }
+static inline int sc_debug_info_record(char *id, const char *format, ...) { return 0; }
+#endif
+
+#endif
\ No newline at end of file
diff --git a/patch/17.09_19.00/code/old/upstream/pub/include/ps_phy/atipsevent.h b/patch/17.09_19.00/code/old/upstream/pub/include/ps_phy/atipsevent.h
new file mode 100755
index 0000000..92e71e6
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/pub/include/ps_phy/atipsevent.h
@@ -0,0 +1,1678 @@
+/*****************************************************************
+*°æ±¾ËùÓÐ (C)2016ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
+*Ä£¿éÃû:
+*ÎļþÃû:atipsevent.h
+*ʵÏÖ¹¦ÄÜ:ATIÏà¹ØÏûÏ¢ºÅ
+*°æ±¾:V1.0
+*****************************************************************/
+#ifndef ZPS_ATI_PSECENT_DEF_H
+#define ZPS_ATI_PSECENT_DEF_H
+
+/*ÐÒéÕ»×Óϵͳ, ÓÉÓÚºÍSDL½ø³Ì»¥Í¨£¬ÆäʼþºÅ¶¨ÒåΪ16룬¹ÊÐÒéջʼþºÅ½öµÍ16λÓÐЧ£¬²»Ê¹Óøß16λ*/
+#define EVENT_PS_BASE (DWORD)0x0000A000
+#define EVENT_PS_END (DWORD)(EVENT_PS_BASE + 0x00005f3f)
+
+/**************************************************PS msg range start (5530)********************************************************/
+/*UICC¶ÔÍâÏûÏ¢·¶Î§(200)*/
+#define AP_UICC_EVENT_BASE (DWORD)EVENT_PS_BASE
+#define AP_UICC_RSP_EVENT (DWORD)(AP_UICC_EVENT_BASE + 100)
+#define AP_UICC_EVENT_END (DWORD)(AP_UICC_RSP_EVENT + 99)
+
+/*MMIA¶ÔÍâÏûÏ¢·¶Î§(1625)*/
+#define AP_MMIA_EVENT_BASE (DWORD)(AP_UICC_EVENT_END + 1)
+
+#define AP_MMIA_EVENT_MM_BASE (DWORD)AP_MMIA_EVENT_BASE
+#define AP_MMIA_MM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_MM_BASE + 100)
+#define AP_MMIA_EVENT_MM_END (DWORD)(AP_MMIA_MM_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_CC_BASE (DWORD)(AP_MMIA_EVENT_MM_END + 1)
+#define AP_MMIA_CC_RSP_EVENT (DWORD)(AP_MMIA_EVENT_CC_BASE + 100)
+#define AP_MMIA_EVENT_CC_END (DWORD)(AP_MMIA_CC_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_SMS_BASE (DWORD)(AP_MMIA_EVENT_CC_END + 1)
+#define AP_MMIA_SMS_RSP_EVENT (DWORD)(AP_MMIA_EVENT_SMS_BASE + 100)
+#define AP_MMIA_EVENT_SMS_END (DWORD)(AP_MMIA_SMS_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_SS_BASE (DWORD)(AP_MMIA_EVENT_SMS_END + 1)
+#define AP_MMIA_SS_RSP_EVENT (DWORD)(AP_MMIA_EVENT_SS_BASE + 50)
+#define AP_MMIA_EVENT_SS_END (DWORD)(AP_MMIA_SS_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_SM_BASE (DWORD)(AP_MMIA_EVENT_SS_END + 1)
+#define AP_MMIA_SM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_SM_BASE + 100)
+#define AP_MMIA_EVENT_SM_END (DWORD)(AP_MMIA_SM_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_ESM_BASE (DWORD)(AP_MMIA_EVENT_SM_END + 1)
+#define AP_MMIA_ESM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_ESM_BASE + 50)
+#define AP_MMIA_EVENT_ESM_END (DWORD)(AP_MMIA_ESM_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_UICC_BASE (DWORD)(AP_MMIA_EVENT_ESM_END + 1)
+#define AP_MMIA_UICC_RSP_EVENT (DWORD)(AP_MMIA_EVENT_UICC_BASE + 100)
+#define AP_MMIA_EVENT_UICC_END (DWORD)(AP_MMIA_UICC_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_USAT_BASE (DWORD)(AP_MMIA_EVENT_UICC_END + 1)
+#define AP_MMIA_USAT_RSP_EVENT (DWORD)(AP_MMIA_EVENT_USAT_BASE + 5)
+#define AP_MMIA_EVENT_USAT_END (DWORD)(AP_MMIA_USAT_RSP_EVENT + 4)
+
+#define AP_MMIA_EVENT_CBS_BASE (DWORD)(AP_MMIA_EVENT_USAT_END + 1)
+#define AP_MMIA_CBS_RSP_EVENT (DWORD)(AP_MMIA_EVENT_CBS_BASE + 5)
+#define AP_MMIA_EVENT_CBS_END (DWORD)(AP_MMIA_CBS_RSP_EVENT + 9)
+
+#define AP_MMIA_EVENT_PB_BASE (DWORD)(AP_MMIA_EVENT_CBS_END + 1)
+#define AP_MMIA_PB_RSP_EVENT (DWORD)(AP_MMIA_EVENT_PB_BASE + 100)
+#define AP_MMIA_EVENT_PB_END (DWORD)(AP_MMIA_PB_RSP_EVENT + 99)
+
+#define AP_MMIA_EVENT_EM_BASE (DWORD)(AP_MMIA_EVENT_PB_END + 1)
+#define AP_MMIA_EM_RSP_EVENT (DWORD)(AP_MMIA_EVENT_EM_BASE + 50)
+#define AP_MMIA_EVENT_EM_END (DWORD)(AP_MMIA_EM_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_OTHER_BASE (DWORD)(AP_MMIA_EVENT_EM_END + 1)
+#define AP_MMIA_OTHER_RSP_EVENT (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 50)
+#define AP_MMIA_EVENT_OTHER_END (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 49)
+
+#define AP_MMIA_EVENT_END (DWORD)AP_MMIA_EVENT_OTHER_END
+
+
+/*ATIÓëPDIÏûÏ¢·¶Î§(20)*/
+#define ATI_PDI_EVENT_BASE (DWORD)(EVENT_PS_BASE + 1850)
+#define ATI_PDI_RSP_EVENT (DWORD)(ATI_PDI_EVENT_BASE + 10)
+#define ATI_PDI_EVENT_END (DWORD)(ATI_PDI_RSP_EVENT + 9)
+
+/*ATIÓëCSDÏûÏ¢·¶Î§(10)*/
+#define ATI_CSD_EVENT_BASE (DWORD)(ATI_PDI_EVENT_END + 1)
+#define ATI_CSD_RSP_EVENT (DWORD)(ATI_CSD_EVENT_BASE + 5)
+#define ATI_CSD_EVENT_END (DWORD)(ATI_CSD_RSP_EVENT + 4)
+
+/*MMIAÓëUMM/CC/SS/SMS/SM/UICC/ESM/ASÏûÏ¢·¶Î§(690)*/
+#define MMIA_NAS_EVENT_BASE (DWORD)(EVENT_PS_BASE + 1880)
+
+#define MMIA_UMM_EVENT_BASE (DWORD)MMIA_NAS_EVENT_BASE
+#define MMIA_UMM_RSP_EVENT (DWORD)(MMIA_UMM_EVENT_BASE + 50)
+#define MMIA_UMM_EVENT_END (DWORD)(MMIA_UMM_RSP_EVENT + 49)
+
+#define MMIA_CC_EVENT_BASE (DWORD)(MMIA_UMM_EVENT_END + 1)
+#define MMIA_CC_RSP_EVENT (DWORD)(MMIA_CC_EVENT_BASE + 50)
+#define MMIA_CC_EVENT_END (DWORD)(MMIA_CC_RSP_EVENT + 49)
+
+#define MMIA_SMS_EVENT_BASE (DWORD)(MMIA_CC_EVENT_END + 1)
+#define MMIA_SMS_RSP_EVENT (DWORD)(MMIA_SMS_EVENT_BASE + 50)
+#define MMIA_SMS_EVENT_END (DWORD)(MMIA_SMS_RSP_EVENT + 49)
+
+#define MMIA_SS_EVENT_BASE (DWORD)(MMIA_SMS_EVENT_END + 1)
+#define MMIA_SS_RSP_EVENT (DWORD)(MMIA_SS_EVENT_BASE + 50)
+#define MMIA_SS_EVENT_END (DWORD)(MMIA_SS_RSP_EVENT + 49)
+
+#define MMIA_SM_EVENT_BASE (DWORD)(MMIA_SS_EVENT_END + 1)
+#define MMIA_SM_RSP_EVENT (DWORD)(MMIA_SM_EVENT_BASE + 50)
+#define MMIA_SM_EVENT_END (DWORD)(MMIA_SM_RSP_EVENT + 49)
+
+#define MMIA_ESM_EVENT_BASE (DWORD)(MMIA_SM_EVENT_END + 1)
+#define MMIA_ESM_RSP_EVENT (DWORD)(MMIA_ESM_EVENT_BASE + 15)
+#define MMIA_ESM_EVENT_END (DWORD)(MMIA_ESM_RSP_EVENT + 14)
+
+#define MMIA_CBS_EVENT_BASE (DWORD)(MMIA_ESM_EVENT_END + 1)
+#define MMIA_CBS_RSP_EVENT (DWORD)(MMIA_CBS_EVENT_BASE + 15)
+#define MMIA_CBS_EVENT_END (DWORD)(MMIA_CBS_RSP_EVENT + 14)
+
+#define MMIA_SNDCP_EVENT_BASE (DWORD)(MMIA_CBS_EVENT_END + 1)
+#define MMIA_SNDCP_RSP_EVENT (DWORD)(MMIA_SNDCP_EVENT_BASE + 15)
+#define MMIA_SNDCP_EVENT_END (DWORD)(MMIA_SNDCP_RSP_EVENT + 14)
+
+#define MMIA_NAS_EVENT_END (DWORD)MMIA_SNDCP_EVENT_END
+
+#define MMIA_AS_EVENT_BASE (DWORD)(MMIA_NAS_EVENT_END + 1)
+#define MMIA_AS_RSP_EVENT (DWORD)(MMIA_AS_EVENT_BASE + 50)
+#define MMIA_AS_EVENT_END (DWORD)(MMIA_AS_RSP_EVENT + 49)
+
+/*** ÔSIG_CODE.HÖÐÒÆÖ²¹ýÀ´µÄÏûÏ¢(660) ***/
+#define EVENT_PS_GSM_NORMAL_BASE (DWORD)(EVENT_PS_BASE + 4300)
+
+#define LAPDM_EVENT_BASE (DWORD)EVENT_PS_GSM_NORMAL_BASE
+#define LAPDM_EVENT_END (DWORD)(LAPDM_EVENT_BASE + 19)
+
+#define GRR_EVENT_BASE (DWORD)(LAPDM_EVENT_END + 1)
+#define GRR_EVENT_END (DWORD)(GRR_EVENT_BASE + 199)
+
+#define GMAC_EVENT_BASE (DWORD)(GRR_EVENT_END + 1)
+#define GMAC_EVENT_END (DWORD)(GMAC_EVENT_BASE + 69)
+
+#define GRLC_EVENT_BASE (DWORD)(GMAC_EVENT_END + 1)
+#define GRLC_EVENT_END (DWORD)(GRLC_EVENT_BASE + 69)
+
+#define GLLC_EVENT_BASE (DWORD)(GRLC_EVENT_END + 1)
+#define GLLC_EVENT_END (DWORD)(GLLC_EVENT_BASE + 49)
+
+#define SNDCP_EVENT_BASE (DWORD)(GLLC_EVENT_END + 1)
+#define SNDCP_EVENT_END (DWORD)(SNDCP_EVENT_BASE + 49)
+
+#define GRRC_EVENT_BASE (DWORD)(SNDCP_EVENT_END + 1)
+#define GRRC_EVENT_END (DWORD)(GRRC_EVENT_BASE + 49)
+
+#define GSMA_EVENT_BASE (DWORD)(GRRC_EVENT_END + 1)
+#define GSMA_EVENT_END (DWORD)(GSMA_EVENT_BASE + 149)
+
+#define EVENT_PS_GSM_NORMAL_END (DWORD)GSMA_EVENT_END
+
+/*ATI¶¨Ê±Æ÷ÏûÏ¢·¶Î§*/
+#define TIMER_EVENT_BASE (DWORD)(EVENT_PS_BASE + 5000)
+
+#define MMIA_TIMER_EVENT_BASE (DWORD)TIMER_EVENT_BASE
+#define MMIA_TIMER_EVENT_END (DWORD)(MMIA_TIMER_EVENT_BASE + 19)
+
+/**************************************************TOOLS & ROADTEST msg range start********************************************************/
+/*±ê×¼ÐÅÁîʼþºÅ·¶Î§(100)*/
+#define STANDARD_SIG_EVENT_BASE (DWORD)(EVENT_PS_BASE + 7000)
+#define STANDARD_SIG_EVENT_END (DWORD)(STANDARD_SIG_EVENT_BASE + 99)
+
+/*·²âÈí¼þʼþºÅ·¶Î§(800)*/
+#define PS_ROADTEST_EVENT_BASE (DWORD)(EVENT_PS_BASE + 7100)
+#define PS_ROADTEST_RSP_EVENT (DWORD)(PS_ROADTEST_EVENT_BASE + 200)
+#define PS_ROADTEST_EVENT_END (DWORD)(PS_ROADTEST_RSP_EVENT + 599)
+
+/*LTE BTrunkʼþºÅ·¶Î§*/
+#define EVENT_PS_LTE_BTRUNK_BASE (DWORD)(EVENT_PS_BASE + 15000)
+#define EVENT_PS_LTE_BTRUNK_END (DWORD)(EVENT_PS_BASE + 16383)
+/**************************************************TOOLS & ROADTEST msg range end***********************************************************/
+
+/**************************************************PS test msg range start********************************************************/
+/*ÐÒéÕ»ÄÚ²âÊÔÏûÏ¢·¶Î§(130)*/
+#define PRI_TEST_EVENT_BASE (DWORD)(PS_ROADTEST_EVENT_END + 1)
+#define PRI_TEST_EVENT_END (DWORD)(PRI_TEST_EVENT_BASE + 19)
+
+#define TAF_TEST_EVENT_BASE (DWORD)(PRI_TEST_EVENT_END + 1)
+#define TAF_TEST_EVENT_END (DWORD)(TAF_TEST_EVENT_BASE + 9)
+
+#define TC_EVENT_BASE (DWORD)(TAF_TEST_EVENT_END + 1)
+#define TC_EVENT_END (DWORD)(TC_EVENT_BASE + 29)
+
+#define NCBS_EVENT_BASE (DWORD)(TC_EVENT_END + 1)
+#define NCBS_EVENT_END (DWORD)(NCBS_EVENT_BASE + 19)
+
+#define USIR_TEST_EVENT_BASE (DWORD)(NCBS_EVENT_END + 1)
+#define USIR_TEST_EVENT_END (DWORD)(USIR_TEST_EVENT_BASE + 9)
+
+#define NURLC_EVENT_BASE (DWORD)(USIR_TEST_EVENT_END + 1)
+#define NURLC_EVENT_END (DWORD)(NURLC_EVENT_BASE + 19)
+
+#define NUMAC_EVENT_BASE (DWORD)(NURLC_EVENT_END + 1)
+#define NUMAC_EVENT_END (DWORD)(NUMAC_EVENT_BASE + 9)
+
+#define NPDCP_EVENT_BASE (DWORD)(NUMAC_EVENT_END + 1)
+#define NPDCP_EVENT_END (DWORD)(NPDCP_EVENT_BASE + 9)
+
+/*GSM²âÊÔ½ø³ÌÏûÏ¢·¶Î§(300)*/
+#define EVENT_PS_GSM_SIMU_BASE (DWORD)(NPDCP_EVENT_END + 1)
+#define L1SIMU_EVENT_BASE (DWORD)EVENT_PS_GSM_SIMU_BASE
+#define L1SIMU_EVENT_END (DWORD)(L1SIMU_EVENT_BASE + 49)
+
+#define NLAPDM_EVENT_BASE (DWORD)(L1SIMU_EVENT_END + 1)
+#define NLAPDM_EVENT_END (DWORD)(NLAPDM_EVENT_BASE + 49)
+
+#define NGMAC_EVENT_BASE (DWORD)(NLAPDM_EVENT_END + 1)
+#define NGMAC_EVENT_END (DWORD)(NGMAC_EVENT_BASE + 99)
+
+#define NLLC_EVENT_BASE (DWORD)(NGMAC_EVENT_END + 1)
+#define NLLC_EVENT_END (DWORD)(NLLC_EVENT_BASE + 49)
+
+#define NRLC_EVENT_BASE (DWORD)(NLLC_EVENT_END + 1)
+#define NRLC_EVENT_END (DWORD)(NRLC_EVENT_BASE + 49)
+
+#define EVENT_PS_GSM_SIMU_END (DWORD)NRLC_EVENT_END
+
+/*GSM AS¶ÔµÈ²ãÐÅÁî¸ú×ÙʼþºÅ·¶Î§¶¨Òå(100)*/
+#define SIGTRACE_EVENT_BASE (DWORD)(EVENT_PS_GSM_SIMU_END + 1)
+
+/*L1GÐÅÁî¸ú×ÙʼþºÅ·¶Î§¶¨Òå(50)*/
+#define L1G_ST_EVENT_BASE (DWORD)(SIGTRACE_EVENT_BASE + 100)
+#define L1G_ST_EVENT_END (DWORD)(L1G_ST_EVENT_BASE + 49)
+
+#define SIGTRACE_EVENT_END (DWORD)L1G_ST_EVENT_END
+
+/*GRRº¯Êý¸ú×ÙÏûÏ¢·¶Î§(100)*/
+#define GSM_FUNC_EVENT_BASE (DWORD)(SIGTRACE_EVENT_END + 1)
+#define GRR_FUNC_EVENT_BASE (DWORD)GSM_FUNC_EVENT_BASE
+#define GRR_FUNC_EVENT_END (DWORD)(GRR_FUNC_EVENT_BASE + 99)
+
+/*º¯ÊýÐÅÁî¸ú×ÙÏûÏ¢·¶Î§(60)*/
+#define FUNC_EVENT_BASE (DWORD)(GRR_FUNC_EVENT_END + 1)
+#define URRC_FUNC_EVENT_BASE (DWORD)FUNC_EVENT_BASE
+#define URRC_FUNC_EVENT_END (DWORD)(URRC_FUNC_EVENT_BASE + 49)
+
+#define TAF_FUNC_EVENT_BASE (DWORD)(URRC_FUNC_EVENT_END + 1)
+#define TAF_FUNC_EVENT_END (DWORD)(TAF_FUNC_EVENT_BASE + 9)
+#define FUNC_EVENT_END (DWORD)TAF_FUNC_EVENT_END
+
+/*È«¾Ö±äÁ¿»ñȡʼþºÅ·¶Î§¶¨Òå(150)*/
+#define GVAR_EVENT_BASE (DWORD)(FUNC_EVENT_END + 1)
+#define GVAR_EVENT_END (DWORD)(GVAR_EVENT_BASE + 149)
+/* ========================================================================
+ UICC¶ÔÍâÌṩÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_UICC_INIT_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 0)
+#define AP_UICC_VERIFY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 1)
+#define AP_UICC_READ_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 2)
+#define AP_UICC_UPDATE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 3)
+#define AP_UICC_AUTH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 4)
+#define AP_UICC_PWROFF_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 5)
+#define AP_UICC_PIN_REMAIN_NUM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 6)
+#define AP_UICC_USAT_ENVELOP_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 7)
+#define AP_UICC_USAT_TERMNL_RSP_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 8)
+#define AP_UICC_USAT_TERMNL_PROF_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 9)
+#define AP_UICC_PIN_ENABLE_QUERY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 10)
+#define AP_UICC_PIN_STAT_QUERY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 11)
+#define AP_UICC_PIN_APPL_SET_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 12)
+#define AP_UICC_PIN_APPL_READ_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 13)
+#define AP_UICC_CARD_MODE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 14)
+#define AP_UICC_WRITE_ITEM_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 15)
+#define AP_UICC_UPDATE_ITEM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 16)
+#define AP_UICC_VERIFY_PIN2_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 17)
+#define AP_UICC_ZPUK_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 18)
+#define AP_UICC_INCREASE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 19)
+#define AP_UICC_RESET_ACM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 20)
+#define AP_UICC_UNBLOCK_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 21)
+#define AP_UICC_CHANGE_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 22)
+#define AP_UICC_FACILITY_PIN_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 23)
+#define AP_UICC_REFRESH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 24)
+#define AP_UICC_DEACTEND_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 25)
+#define AP_UICC_FILECHANGEEND_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 26)
+#define AP_UICC_TO_READ_CARD_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 27)
+#define AP_UICC_CSIM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 28)
+#define AP_UICC_AP_PWROFF_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 29)
+#define AP_UICC_CCHO_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 30)
+#define AP_UICC_CCHC_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 31)
+#define AP_UICC_CGLA_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 32)
+#define AP_UICC_CRSM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 33)
+#define AP_UICC_MOVECARD_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 34)
+#define AP_UICC_INSERTCARD_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 35)
+#define AP_UICC_GET_INFO_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 36)
+#define AP_UICC_EFSTATUS_QUERY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 37)
+#define AP_UICC_EFSTATUS_MODIFY_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 38)
+#define AP_UICC_PREPERSONREC_SEARCH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 39)
+#define AP_UICC_PB_SEARCH_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 40)
+#define AP_UICC_READ_TO_PSDEV_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 45)
+#define AP_UICC_GET_REC_NUM_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 46)
+#define AP_UICC_AIR_AUTH_RSP_IND_EV (DWORD)(AP_UICC_EVENT_BASE + 47)
+#define AP_UICC_READ_EID_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 48)
+#define AP_UICC_READ_REC_DIRECT_REQ_EV (DWORD)(AP_UICC_EVENT_BASE + 50)
+
+#define AP_UICC_INIT_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 0)
+#define AP_UICC_UICCOK_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 1)
+#define AP_UICC_INIT_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 2)
+#define AP_UICC_SLOT_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 3)
+#define AP_UICC_READ_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 4)
+#define AP_UICC_UPDATE_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 5)
+#define AP_UICC_AUTH_RSP_EV (DWORD)(AP_UICC_RSP_EVENT + 6)
+#define AP_UICC_AUTH_FAIL_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 7)
+#define AP_UICC_NOCARD_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 8)
+#define AP_UICC_PIN_REMAIN_NUM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 9)
+#define AP_UICC_USAT_ENVELOP_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 10)
+#define AP_UICC_USAT_COMMON_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 11)
+#define AP_UICC_USAT_PROV_CMD_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 12)
+#define AP_UICC_PIN_ENABLE_QUERY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 13)
+#define AP_UICC_PIN_STAT_QUERY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 14)
+#define AP_UICC_PIN_APPL_SET_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 15)
+#define AP_UICC_PIN_APPL_READ_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 16)
+#define AP_UICC_CARD_MODE_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 17)
+#define AP_UICC_PWROFF_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 18)
+#define AP_UICC_COMMON_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 19)
+#define AP_UICC_UICC_UNSYNC_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 20)
+#define AP_UICC_NO_PROC_NOTIFY_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 21)
+#define AP_UICC_CARD_LOCK_STATUS_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 22)
+#define AP_UICC_PWROFF_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 23)
+#define AP_UICC_UPDATE_ITEM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 24)
+#define AP_UICC_VERIFY_PIN2_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 25)
+#define AP_UICC_INCREASE_ACM_FAIL_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 26)
+#define AP_UICC_FILECHANGE_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 27)
+#define AP_UICC_CSIM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 28)
+#define AP_UICC_ATR_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 29)
+#define AP_UICC_CCHO_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 30)
+#define AP_UICC_CGLA_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 31)
+#define AP_UICC_CRSM_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 32)
+#define AP_UICC_USAT_FETCH_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 33)
+#define AP_UICC_GET_INFO_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 34)
+#define AP_UICC_EFSTATUS_QUERY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 35)
+#define AP_UICC_EFSTATUS_MODIFY_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 36)
+#define AP_UICC_PREPERSNREC_SRCH_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 37)
+#define AP_UICC_PB_SEARCH_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 38) /* ·ÖÅäÁË50ÌõÏûÏ¢Çø¼ä£¬ÒÑÓÃÁË39¸ö */
+#define AP_UICC_REFRESH_HAPPEN_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 39)
+#define AP_UICC_AIR_AUTH_REQ_IND_EV (DWORD)(AP_UICC_RSP_EVENT + 40)
+#define AP_UICC_READ_EID_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 41)
+#define AP_UICC_CCHC_CNF_EV (DWORD)(AP_UICC_RSP_EVENT + 42)
+#define AP_UICC_LOC_STAT_IND (DWORD)(AP_UICC_RSP_EVENT + 43)
+
+/* ========================================================================
+ MMIA¶ÔÍâÌṩÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* ========================================================================
+ AP-MMIA MMÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_CREG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 0)
+#define AP_MMIA_CREG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 1)
+#define AP_MMIA_COPS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 2)
+#define AP_MMIA_COPS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 3)
+#define AP_MMIA_COPS_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 4)
+#define AP_MMIA_CGATT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 5)
+#define AP_MMIA_CGATT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 6)
+#define AP_MMIA_CGREG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 7)
+#define AP_MMIA_CGREG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 8)
+#define AP_MMIA_CFUN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 9)
+#define AP_MMIA_CFUN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 10)
+#define AP_MMIA_CPLS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 11)
+#define AP_MMIA_CPLS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 12)
+#define AP_MMIA_CPOL_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 13)
+#define AP_MMIA_CPOL_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 14)
+#define AP_MMIA_CPOL_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 15)
+#define AP_MMIA_ZMMI_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 16)
+#define AP_MMIA_ZMMI_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 17)
+#define AP_MMIA_MODE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 18)
+#define AP_MMIA_ZATT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 19)
+#define AP_MMIA_ZATT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 20)
+#define AP_MMIA_ZGAAT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 21)
+#define AP_MMIA_ZGAAT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 22)
+#define AP_MMIA_SYSINFO_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 23)
+#define AP_MMIA_ZACT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 24)
+#define AP_MMIA_ZACT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 25)
+#define AP_MMIA_MODE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 26)
+#define AP_MMIA_SYSCONFIG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 27)
+#define AP_MMIA_SYSCONFIG_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 28)
+#define AP_MMIA_CEREG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 29)
+#define AP_MMIA_CEREG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 30)
+#define AP_MMIA_ZCSG_SEL_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 31)
+#define AP_MMIA_ZCSG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 32)
+#define AP_MMIA_ZCSG_LIST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 33)
+#define AP_MMIA_CEMODE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 34)
+#define AP_MMIA_CEMODE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 35)
+#define AP_MMIA_ZEACT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 36)
+#define AP_MMIA_ZEACT_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 37)
+#define AP_MMIA_CVMOD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 38)
+#define AP_MMIA_CVMOD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 39)
+#define AP_MMIA_CS_SRV_RSP_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 40)
+#define AP_MMIA_LTEBGPLMN_TESTREQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 41)
+#define AP_MMIA_SMSOVERIPNET_SETREQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 42)
+#define AP_MMIA_SMSOVERIPNET_QUERYREQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 43)
+#define AP_MMIA_FPLMN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 44)
+#define AP_MMIA_FPLMN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 45)
+#define AP_MMIA_FPLMN_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_MM_BASE + 46)
+
+#define AP_MMIA_CREG_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 0)
+#define AP_MMIA_CGREG_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 1)
+#define AP_MMIA_ZMMI_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 2)
+#define AP_MMIA_COPS_TEST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 3)
+#define AP_MMIA_CGATT_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 4)
+#define AP_MMIA_CPOL_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 5)
+#define AP_MMIA_ZATT_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 6)
+#define AP_MMIA_MODE_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 7)
+#define AP_MMIA_ZACT_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 8)
+#define AP_MMIA_SYSCONFIG_READ_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 9)
+#define AP_MMIA_CEREG_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 10)
+#define AP_MMIA_ZCSG_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 11)
+#define AP_MMIA_ZCSG_LIST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 12)
+#define AP_MMIA_CEMODE_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 13)
+#define AP_MMIA_CVMOD_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 14)
+#define AP_MMIA_CS_SRV_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 15)
+#define AP_MMIA_LTEBGPLMN_TESTCNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 16)
+#define AP_MMIA_IMSVOPS_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 17)
+#define AP_MMIA_FPLMN_QUERY_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 18)
+#define AP_MMIA_FPLMN_TEST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 19)
+#define AP_MMIA_EMERBER_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 20)
+#define AP_MMIA_EMERNUM_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 21)
+#define AP_MMIA_PSCFGSTART_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 22)
+#define AP_MMIA_PSCFGEND_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 23)
+#define AP_MMIA_USER_CARD_SEL_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 24)
+#define AP_MMIA_ZCOPS_TEST_CNF_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 25)
+#define AP_MMIA_TIMEZONE_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 26)
+#define AP_MMIA_ZULRTIND_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 27)
+#define AP_MMIA_ZPSABNORMAL_IND_EV (DWORD)(AP_MMIA_MM_RSP_EVENT + 28)
+/* ========================================================================
+ AP-MMIA CCÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_CC_SETUP_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 0)
+#define AP_MMIA_CC_ANSWER_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 1)
+#define AP_MMIA_CC_MODIFY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 2)
+#define AP_MMIA_CC_STATE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 3)
+#define AP_MMIA_CC_DISC_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 4)
+#define AP_MMIA_CC_DTMF_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 5)
+#define AP_MMIA_CC_CHLD_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 6)
+#define AP_MMIA_CC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 7)
+#define AP_MMIA_CC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 8)
+#define AP_MMIA_DS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 9)
+#define AP_MMIA_DS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 10)
+#define AP_MMIA_MOD_TO_MULTMEDIA_RSP_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 11)
+#define AP_MMIA_CC_MTC_RSP_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 12)
+#define AP_MMIA_DSCI_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 13)
+#define AP_MMIA_DSCI_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 14)
+#define AP_MMIA_CAOC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 15)
+#define AP_MMIA_CAOC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 16)
+#define AP_MMIA_CACM_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 17)
+#define AP_MMIA_CAMM_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 18)
+#define AP_MMIA_CPUC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 19)
+#define AP_MMIA_CCWE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 20)
+#define AP_MMIA_CACM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 21)
+#define AP_MMIA_CAMM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 22)
+#define AP_MMIA_CPUC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 23)
+#define AP_MMIA_CCWE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 24)
+#define AP_MMIA_CALL_LINE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 25)
+#define AP_MMIA_CALL_LINE_QRY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 26)
+
+#define AP_MMIA_CC_CBST_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 27)
+#define AP_MMIA_CC_CBST_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 28)
+#define AP_MMIA_CC_CCUG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 29)
+#define AP_MMIA_CC_CCUG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 30)
+#define AP_MMIA_CC_CMOD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 31)
+#define AP_MMIA_CC_CMOD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 32)
+#define AP_MMIA_CC_CR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 33)
+#define AP_MMIA_CC_CR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 34)
+#define AP_MMIA_CC_CRC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 35)
+#define AP_MMIA_CC_CRC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 36)
+#define AP_MMIA_CC_CSNS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 37)
+#define AP_MMIA_CC_CSNS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 38)
+#define AP_MMIA_CC_CSSN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 39)
+#define AP_MMIA_CC_CSSN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 40)
+#define AP_MMIA_CC_FCLASS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 41)
+#define AP_MMIA_CC_FCLASS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 42)
+#define AP_MMIA_SS_CHSN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 43)
+#define AP_MMIA_SS_CHSN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 44)
+#define AP_MMIA_SS_CRLP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 45)
+#define AP_MMIA_SS_CRLP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 46)
+#define AP_MMIA_SS_ETBM_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 47)
+#define AP_MMIA_SS_ETBM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CC_BASE + 48)
+
+#define AP_MMIA_CC_SETUP_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 0)
+#define AP_MMIA_CC_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 1)
+#define AP_MMIA_CC_ANSWER_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 2)
+#define AP_MMIA_CC_MODIFY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 3)
+#define AP_MMIA_CC_STATE_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 4)
+#define AP_MMIA_CC_DISC_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 5)
+#define AP_MMIA_DS_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 6)
+#define AP_MMIA_COLP_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 7)
+#define AP_MMIA_CR_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 8)
+#define AP_MMIA_MT_CALL_SS_NOTIFY_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 9)
+#define AP_MMIA_CLIP_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 10)
+#define AP_MMIA_CC_PROC_INFO_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 11)
+#define AP_MMIA_RING_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 12)
+#define AP_MMIA_CRING_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 13)
+#define AP_MMIA_CCWA_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 14)
+#define AP_MMIA_MO_CALL_SS_NOTIFY_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 15)
+#define AP_MMIA_MOD_TO_MULTMEDIA_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 16)
+#define AP_MMIA_CONN_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 17)
+#define AP_MMIA_ORIG_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 18)
+#define AP_MMIA_CONF_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 19)
+#define AP_MMIA_CEND_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 20)
+#define AP_MMIA_CALL_STATE_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 21)
+#define AP_MMIA_DSCI_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 22)
+#define AP_MMIA_CAOC_SET_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 23)
+#define AP_MMIA_CPUC_QUERY_CNF_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 24)
+#define AP_MMIA_CCCM_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 25)
+#define AP_MMIA_CCWV_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 26)
+#define AP_MMIA_REDIALEND_IND_EV (DWORD)(AP_MMIA_CC_RSP_EVENT + 27)
+
+/* ========================================================================
+ AP-MMIA SMSÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_SMS_TCMGS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 0)
+#define AP_MMIA_SMS_CMSS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 1)
+#define AP_MMIA_SMS_TCMGW_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 2)
+#define AP_MMIA_SMS_CMGD_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 3)
+#define AP_MMIA_SMS_TCMGC_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 4)
+#define AP_MMIA_SMS_CMMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 5)
+#define AP_MMIA_SMS_CNMI_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 6)
+#define AP_MMIA_SMS_CMGL_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 7)
+#define AP_MMIA_SMS_CMGR_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 8)
+#define AP_MMIA_SMS_TCNMA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 9)
+#define AP_MMIA_SMS_CGSMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 10)
+#define AP_MMIA_SMS_CSMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 11)
+#define AP_MMIA_SMS_CPMS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 12)
+#define AP_MMIA_SMS_CMGF_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 13)
+#define AP_MMIA_SMS_CSCA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 14)
+#define AP_MMIA_SMS_TCSMP_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 15)
+#define AP_MMIA_SMS_TCSDH_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 16)
+#define AP_MMIA_SMS_PCMGS_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 17)
+#define AP_MMIA_SMS_PCMGW_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 18)
+#define AP_MMIA_SMS_PCMGC_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 19)
+#define AP_MMIA_SMS_PCNMA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 20)
+#define AP_MMIA_SMS_CPMS_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 21)
+#define AP_MMIA_SMS_ZMENA_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 22)
+#define AP_MMIA_SMS_QUERY_MODE_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 23)
+#define AP_MMIA_SMS_QUERY_MAX_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 24)
+#define AP_MMIA_SMS_CNMA_QUERY_MODE_REQ_EV (DWORD)(AP_MMIA_EVENT_SMS_BASE + 25)
+
+#define AP_MMIA_SMS_TCMGS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 0)
+#define AP_MMIA_SMS_TCMSS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 1)
+#define AP_MMIA_SMS_CMGW_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 2)
+#define AP_MMIA_SMS_TCMGC_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 3)
+#define AP_MMIA_SMS_STORE_REC_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 4)
+#define AP_MMIA_SMS_TCMT_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 5)
+#define AP_MMIA_SMS_TCDS_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 6)
+#define AP_MMIA_SMS_TDELI_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 7)
+#define AP_MMIA_SMS_TSUB_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 8)
+#define AP_MMIA_SMS_TSTAT_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 9)
+#define AP_MMIA_SMS_TCOM_LIST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 10)
+#define AP_MMIA_SMS_TDELI_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 11)
+#define AP_MMIA_SMS_TSUB_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 12)
+#define AP_MMIA_SMS_TSTAT_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 13)
+#define AP_MMIA_SMS_TCOM_READ_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 14)
+#define AP_MMIA_SMS_CPMS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 15)
+#define AP_MMIA_SMS_PCMGS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 16)
+#define AP_MMIA_SMS_PCMSS_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 17)
+#define AP_MMIA_SMS_PCMGC_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 18)
+#define AP_MMIA_SMS_PCMTIND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 19)
+#define AP_MMIA_SMS_PCDSIND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 20)
+#define AP_MMIA_SMS_PCMGL_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 21)
+#define AP_MMIA_SMS_PCMGR_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 22)
+#define AP_MMIA_SMS_CPMS_TEST_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 23)
+#define AP_MMIA_SMS_QUERY_MAX_INDEX_CNF_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 24)
+#define AP_MMIA_SMS_SAVE_FAILURE_IND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 25)
+#define AP_MMIA_SMS_ZCMTIND_EV (DWORD)(AP_MMIA_SMS_RSP_EVENT + 26)
+
+/* ========================================================================
+ AP-MMIA SSÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_CLCK_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 0)
+#define AP_MMIA_CPWD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 1)
+#define AP_MMIA_CLIP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 2)
+#define AP_MMIA_CLIP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 3)
+#define AP_MMIA_CLIR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 4)
+#define AP_MMIA_CLIR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 5)
+#define AP_MMIA_COLP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 6)
+#define AP_MMIA_COLP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 7)
+#define AP_MMIA_CCFC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 8)
+#define AP_MMIA_CCWA_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 9)
+#define AP_MMIA_CCWA_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 10)
+#define AP_MMIA_CUSD_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 11)
+#define AP_MMIA_CUSD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 12)
+#define AP_MMIA_COLR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 13)
+#define AP_MMIA_CNAP_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 14)
+#define AP_MMIA_CNAP_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SS_BASE + 15)
+
+#define AP_MMIA_CLCK_STATUS_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 0)
+#define AP_MMIA_CLIP_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 1)
+#define AP_MMIA_CLIR_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 2)
+#define AP_MMIA_COLP_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 3)
+#define AP_MMIA_CCFC_STATUS_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 4)
+#define AP_MMIA_CCWA_STATUS_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 5)
+#define AP_MMIA_CCWA_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 6)
+#define AP_MMIA_CUSD_IND_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 7)
+#define AP_MMIA_COLR_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 8)
+#define AP_MMIA_CNAP_QUERY_CNF_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 9)
+#define AP_MMIA_CNAP_IND_EV (DWORD)(AP_MMIA_SS_RSP_EVENT + 10)
+
+/* ========================================================================
+ AP-MMIA SMÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_SM_PARAM_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 0)
+#define AP_MMIA_SM_PARAM_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 1)
+#define AP_MMIA_SM_PDP_STATUS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 2)
+#define AP_MMIA_SM_ACTIVED_CID_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 3)
+#define AP_MMIA_SM_DEF_CID_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 4)
+#define AP_MMIA_SM_PDP_ADDR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 5)
+#define AP_MMIA_SM_NEG_QOS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 6)
+#define AP_MMIA_SM_NEG_EQOS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 7)
+#define AP_MMIA_SM_ACT_DEACT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 8)
+#define AP_MMIA_SM_MOD_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 9)
+#define AP_MMIA_SM_DATA_STATE_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 10)
+#define AP_MMIA_SM_MT_ACT_ANS_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 11)
+#define AP_MMIA_SM_CPSB_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 12)
+#define AP_MMIA_SM_CGCONTRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 13)
+#define AP_MMIA_SM_CGSCONTRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 14)
+#define AP_MMIA_SM_CGTFTRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 15)
+#define AP_MMIA_SM_CGDEL_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 16)
+#define AP_MMIA_SM_ZGACT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 17)
+/* ÒÔÉÏΪATÃüÁî¶ÔÓ¦ÏûÏ¢*/
+#define AP_MMIA_SM_GET_PCO_RSP_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 18)
+#define AP_MMIA_SM_IP_PDP_ACT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 19)
+#define AP_MMIA_SM_OPEN_CHNL_RSP_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 20)
+#define AP_MMIA_SM_IDLE_CHNL_QUERY_RSP_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 21)
+#define AP_MMIA_DISCONNECT_REQ_EV (DWORD)(AP_MMIA_EVENT_SM_BASE + 22)
+
+
+#define AP_MMIA_SM_PDP_STATUS_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 0)
+#define AP_MMIA_SM_ACTIVED_CID_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 1)
+#define AP_MMIA_SM_PDP_ADDR_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 2)
+#define AP_MMIA_SM_NEG_QOS_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 3)
+#define AP_MMIA_SM_NEG_EQOS_QUERY_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 4)
+#define AP_MMIA_SM_NO_CARRIER_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 5)
+#define AP_MMIA_SM_ACT_DEACT_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 6)
+#define AP_MMIA_SM_MOD_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 7)
+#define AP_MMIA_SM_MT_ACTIVATE_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 8)
+#define AP_MMIA_SM_CGEV_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 9)
+#define AP_MMIA_SM_IP_PDP_ACT_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 10)
+#define AP_MMIA_SM_CLOSE_CHNL_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 11)
+#define AP_MMIA_SM_QUERY_IDLE_CHNL_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 12)
+#define AP_MMIA_SM_GET_PCO_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 13)
+#define AP_MMIA_SM_CONNECT_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 14)
+#define AP_MMIA_SM_CPSB_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 15)
+#define AP_MMIA_SM_CGCONTRDP_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 16)
+#define AP_MMIA_SM_CGSCONTRDP_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 17)
+#define AP_MMIA_SM_CGTFTRDP_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 18)
+#define AP_MMIA_SM_CGDEL_CNF_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 19)
+#define AP_MMIA_SM_DEACT_IND_EV (DWORD)(AP_MMIA_SM_RSP_EVENT + 20)
+
+/* ========================================================================
+ AP-MMIA ESMÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_ESM_CGETFADS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 0)
+#define AP_MMIA_ESM_TFAD_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 1)
+#define AP_MMIA_ESM_CGATFT_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 2)
+#define AP_MMIA_ESM_BEARER_MOD_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 3)
+#define AP_MMIA_ESM_EBR_MOD_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 4)
+#define AP_MMIA_CGEQOSRDP_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 5) /*only for R7&R5*/
+#define AP_MMIA_ESM_TFAD_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 6)
+#define AP_MMIA_CGEQOS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 7) /*only for R7&R5*/
+#define AP_MMIA_CGEQOS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_ESM_BASE + 8) /*only for R7&R5*/
+
+#define AP_MMIA_ESM_BEARER_ACT_IND_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 0)
+#define AP_MMIA_ESM_BEARER_DEACT_IND_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 1)
+#define AP_MMIA_ESM_BEARER_MOD_IND_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 2)
+#define AP_MMIA_ESM_TFAD_READ_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 3)
+#define AP_MMIA_ESM_CGATFT_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 4)
+#define AP_MMIA_ESM_BEARER_MOD_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 5)
+#define AP_MMIA_ESM_BEARER_MOD_REJ_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 6)
+#define AP_MMIA_ESM_EBRMOD_QUERY_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 7)
+#define AP_MMIA_CGEQOSRDP_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 8) /*only for R7&R5*/
+#define AP_MMIA_ESM_TFADTEST_CNF_EV (DWORD)(AP_MMIA_ESM_RSP_EVENT + 9)
+
+/* ========================================================================
+ AP-MMIA UICCÏà¹Ø²¿·ÖÏûÏ¢ºÅ
+======================================================================== */
+#define AP_MMIA_UICC_INIT_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 0)
+#define AP_MMIA_CPIN_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 1)
+#define AP_MMIA_PIN_REMAIN_NUM_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 2)
+#define AP_MMIA_CPBS_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 3)
+#define AP_MMIA_CPBS_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 4)
+#define AP_MMIA_CPBR_EXE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 5)
+#define AP_MMIA_CPBR_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 6)
+#define AP_MMIA_CPBF_EXE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 7)
+#define AP_MMIA_CPBF_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 8)
+#define AP_MMIA_CPBW_EXE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 9)
+#define AP_MMIA_CPBW_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 10)
+#define AP_MMIA_UICC_COMMAND_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 11)
+#define AP_MMIA_PIN_APPL_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 12)
+#define AP_MMIA_PIN_APPL_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 13)
+#define AP_MMIA_CARD_MODE_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 14)
+#define AP_MMIA_CPIN_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 15)
+#define AP_MMIA_CPBS_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 16)
+#define AP_MMIA_SCPBR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 17)
+#define AP_MMIA_SCPBR_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 18)
+#define AP_MMIA_SCPBW_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 19)
+#define AP_MMIA_SCPBW_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 20)
+#define AP_MMIA_CNUM_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 21)
+#define AP_MMIA_ZIMG_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 22)
+#define AP_MMIA_ZGIIDF_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 23)
+#define AP_MMIA_ZPUK_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 24)
+#define AP_MMIA_CPBW_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 25)
+#define AP_MMIA_ZCPBQ_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 26)
+#define AP_MMIA_ZCPBQ_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 27)
+#define AP_MMIA_ZEER_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 28)
+#define AP_MMIA_MB_AUTH_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 29)
+#define AP_MMIA_MB_CELL_ID_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 30)
+#define AP_MMIA_PSEUDO_FR_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 31)
+#define AP_MMIA_PSEUDO_FR_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 32)
+#define AP_MMIA_REFRESH_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 33)
+#define AP_MMIA_CARD_SRV_LIST_QRY_REQ_EV (DWORD)(AP_MMIA_EVENT_UICC_BASE + 34)
+
+#define AP_MMIA_UICC_INIT_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 0)
+#define AP_MMIA_UICC_OKIND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 1)
+#define AP_MMIA_UICC_INTI_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 2)
+#define AP_MMIA_UICC_SLOT_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 3)
+#define AP_MMIA_PIN_REMAI_NNUM_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 4)
+#define AP_MMIA_CPBS_QUERY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 5)
+#define AP_MMIA_CPBR_EXE_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 6)
+#define AP_MMIA_CPBR_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 7)
+#define AP_MMIA_CPBF_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 8)
+#define AP_MMIA_CPBW_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 9)
+#define AP_MMIA_PIN_APPL_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 10)
+#define AP_MMIA_PIN_APPL_READ_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 11)
+#define AP_MMIA_CARD_MODE_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 12)
+#define AP_MMIA_CPIN_READ_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 13)
+#define AP_MMIA_CPBR_SET_END_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 14)
+#define AP_MMIA_CPBS_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 15)
+#define AP_MMIA_SCPBR_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 16)
+#define AP_MMIA_SCPBR_SET_END_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 17)
+#define AP_MMIA_SCPBR_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 18)
+#define AP_MMIA_SCPBW_TEST_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 19)
+#define AP_MMIA_CNUM_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 20)
+#define AP_MMIA_ZIMG_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 21)
+#define AP_MMIA_ZGIIDF_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 22)
+#define AP_MMIA_CPBW_EXE_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 23)
+#define AP_MMIA_ZCPBQ_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 24)
+#define AP_MMIA_ZCPBQ_QUERY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 25)
+#define AP_MMIA_ZEER_READ_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 26)
+#define AP_MMIA_MB_AUTH_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 27)
+#define AP_MMIA_PSEUDO_FR_QUERY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 28)
+#define AP_MMIA_CARD_SRV_LIST_QRY_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 29)
+#define AP_MMIA_ICCID_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 30)
+#define AP_MMIA_ZCFIS_SET_CNF_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 31)
+#define AP_MMIA_ZISIMINIT_IND_EV (DWORD)(AP_MMIA_UICC_RSP_EVENT + 32)
+#define AP_MMIA_COPN_EXE_CNF (DWORD)(AP_MMIA_UICC_RSP_EVENT + 33)
+#define AP_MMIA_COPN_END_CNF (DWORD)(AP_MMIA_UICC_RSP_EVENT + 34)
+
+/* ========================================================================
+ AP-MMIA USATÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_USAT_ENVELOP_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 0)
+#define AP_MMIA_USAT_TERMNL_RSP_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 1)
+#define AP_MMIA_USAT_TERMNL_PROF_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 2)
+#define AP_MMIA_USAT_LOC_INFO_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 3)
+#define AP_MMIA_USAT_TO_READ_CARD_REQ_EV (DWORD)(AP_MMIA_EVENT_USAT_BASE + 4)
+
+#define AP_MMIA_USAT_ENVELOP_CNF_EV (DWORD)(AP_MMIA_USAT_RSP_EVENT + 0)
+#define AP_MMIA_USAT_PROV_CMD_IND_EV (DWORD)(AP_MMIA_USAT_RSP_EVENT + 1)
+#define AP_MMIA_USAT_NOPROC_NOTIFY_IND_EV (DWORD)(AP_MMIA_USAT_RSP_EVENT + 2)
+
+/* ========================================================================
+ AP-MMIA CBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_CBS_CSCB_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 0)
+#define AP_MMIA_CBS_CSCB_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 1)
+#define AP_MMIA_CBS_SAVING_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 2)
+#define AP_MMIA_CBS_RESTORE_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_CBS_BASE + 3)
+
+#define AP_MMIA_CBS_TCBM_IND_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 0)
+#define AP_MMIA_CBS_PCBM_IND_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 1)
+#define AP_MMIA_CBS_TCBM_LIST_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 2)
+#define AP_MMIA_CBS_PCBM_LIST_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 3)
+#define AP_MMIA_CBS_TCBM_READ_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 4)
+#define AP_MMIA_CBS_PCBM_READ_CNF_EV (DWORD)(AP_MMIA_CBS_RSP_EVENT + 5)
+
+/* ========================================================================
+ AP-MMIA PB(´æ´¢¹ÜÀí)ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_SM_SAVE_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 0)
+#define AP_MMIA_SM_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 1)
+#define AP_MMIA_SM_LIST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 2)
+#define AP_MMIA_SM_DELETE_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 3)
+#define AP_MMIA_SM_MEM_AVAIL_RSP_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 4)
+#define AP_MMIA_PB_FIND_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 5)
+#define AP_MMIA_PB_FIND_TEXT_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 6)
+#define AP_MMIA_PB_EDIT_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 7)
+#define AP_MMIA_PB_STORAGE_STATUS_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 8)
+#define AP_MMIA_PB_PREF_MSG_STO_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 9)
+#define AP_MMIA_PB_PREF_MSG_STO_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 10)
+#define AP_MMIA_PB_TPMR_UPDATE_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 11)
+#define AP_MMIA_PB_MEM_CAPA_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 12)
+#define AP_MMIA_PB_MT_PARA_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 13)
+#define AP_MMIA_PB_EMER_NUM_LIST_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 14)
+#define AP_MMIA_PB_STO_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 15)
+#define AP_MMIA_PB_STO_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 16)
+#define AP_MMIA_PB_QUERY_SMS_MAX_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 17)
+#define AP_MMIA_PB_S_FIND_INDEX_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 18)
+#define AP_MMIA_PB_S_EDIT_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 19)
+#define AP_MMIA_PB_C_NUM_REQ (DWORD)(AP_MMIA_EVENT_PB_BASE + 20)
+#define AP_MMIA_PB_CLCK_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 21)
+#define AP_MMIA_PB_SCPBR_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 22)
+#define AP_MMIA_PB_SCPBW_TEST_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 23)
+#define AP_MMIA_PB_UICC_OK_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 24)
+#define AP_MMIA_PB_CPBR_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 25)
+#define AP_MMIA_PB_CPBF_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 26)
+#define AP_MMIA_PB_SCPBR_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 27)
+#define AP_MMIA_PB_CMGL_IND_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 28)
+#define AP_MMIA_PB_CPBW_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 29)
+#define AP_MMIA_PB_READ_CAPA_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 30)
+#define AP_MMIA_PB_READ_SET_NUM_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 31)
+#define AP_MMIA_PB_READ_LAST_EXT_ERR_REQ_EV (DWORD)(AP_MMIA_EVENT_PB_BASE + 32)
+
+#define AP_MMIA_SM_SAVE_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 0)
+#define AP_MMIA_SM_READ_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 1)
+#define AP_MMIA_SM_LIST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 2)
+#define AP_MMIA_SM_DELETE_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 3)
+#define AP_MMIA_SM_MEM_AVAIL_IND_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 4)
+#define AP_MMIA_PB_FIND_INDEX_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 5)
+#define AP_MMIA_PB_FIND_TEXT_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 6)
+#define AP_MMIA_PB_EDIT_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 7)
+#define AP_MMIA_PB_STORAGE_STATUS_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 8)
+#define AP_MMIA_PB_FIND_INDEX_END_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 9)
+#define AP_MMIA_PB_PREF_MSG_STO_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 10)
+#define AP_MMIA_PB_PREF_MSG_STO_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 11)
+#define AP_MMIA_PB_COMMON_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 12)
+#define AP_MMIA_PB_INIT_COMP_IND_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 13)
+#define AP_MMIA_PB_STO_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 14)
+#define AP_MMIA_PB_QUERY_SMS_MAX_INDEX_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 15)
+#define AP_MMIA_PB_S_FIND_INDEX_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 16)
+#define AP_MMIA_PB_S_FIND_INDEX_END_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 17)
+#define AP_MMIA_PB_S_EDIT_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 18)
+#define AP_MMIA_PB_SCPBR_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 19)
+#define AP_MMIA_PB_SCPBW_TEST_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 20)
+#define AP_MMIA_PB_C_NUM_CNF (DWORD)(AP_MMIA_PB_RSP_EVENT + 21)
+#define AP_MMIA_PB_CLCK_STATUS_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 22)
+#define AP_MMIA_PB_CHG_INDEX_IND_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 23)
+#define AP_MMIA_PB_CPBW_QUERY_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 24)
+#define AP_MMIA_PB_READ_CAPA_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 25)
+#define AP_MMIA_PB_READ_SET_NUM_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 26)
+#define AP_MMIA_PB_READ_LAST_EXT_ERR_CNF_EV (DWORD)(AP_MMIA_PB_RSP_EVENT + 27)
+
+/* ========================================================================
+ AP-MMIA ¹¤³ÌģʽºÍÏúÁ¿Í³¼ÆÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_EM_CELL_INFO_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 0)
+#define AP_MMIA_EM_CELL_INFO_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 1)
+#define AP_MMIA_EM_LOCK_CELL_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 2)
+#define AP_MMIA_EM_HO_INFO_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 3)
+#define AP_MMIA_EM_HO_INFO_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 4)
+#define AP_MMIA_SELL_STAT_SWITCH_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 5)
+#define AP_MMIA_SELL_STAT_SWITCH_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 6)
+#define AP_MMIA_SELL_STAT_UDPINFO_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 7)
+#define AP_MMIA_SELL_STAT_TEST_SEND_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 8)
+#define AP_MMIA_SELL_STAT_DOMAIN_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 9)
+#define AP_MMIA_SELL_STAT_DOMAIN_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 10)
+#define AP_MMIA_SELL_STAT_CRC_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 11)
+#define AP_MMIA_SELL_STAT_CRC_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 12)
+#define AP_MMIA_SELL_STAT_DEBUG_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 13)
+#define AP_MMIA_SELL_STAT_DEBUG_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 14)
+#define AP_MMIA_SELL_STAT_PORT_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 15)
+#define AP_MMIA_SELL_STAT_PORT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 16)
+#define AP_MMIA_SELL_STAT_TRI_TYPE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 17)
+#define AP_MMIA_SELL_STAT_DNS_CNT_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_EM_BASE + 18)
+
+
+#define AP_MMIA_EM_CELL_INFO_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 0)
+#define AP_MMIA_EM_HO_INFO_IND_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 1)
+#define AP_MMIA_EM_HO_INFO_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 2)
+#define AP_MMIA_SELL_STAT_SWITCH_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 3)
+#define AP_MMIA_SELL_STAT_UDPINFO_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 4)
+#define AP_MMIA_SELL_STAT_DOMAIN_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 5)
+#define AP_MMIA_SELL_STAT_CRC_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 6)
+#define AP_MMIA_SELL_STAT_DEBUG_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 7)
+#define AP_MMIA_SELL_STAT_PORT_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 8)
+#define AP_MMIA_SELL_STAT_TRI_TYPE_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 9)
+#define AP_MMIA_SELL_STAT_DNS_CNT_QUERY_CNF_EV (DWORD)(AP_MMIA_EM_RSP_EVENT + 10)
+
+/* ========================================================================
+ AP-MMIA ÐźÅÇ¿¶ÈÖ÷¶¯Éϱ¨ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define AP_MMIA_RXLEV_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 0)
+#define AP_MMIA_ZRPT_RXLEV_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 1)
+#define AP_MMIA_ZRPT_RXLEV_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 2)
+#define AP_MMIA_QUERY_IMSI_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 3)
+#define AP_MMIA_QUERY_IMEI_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 4)
+#define AP_MMIA_ABORT_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 5)
+#define AP_MMIA_CAUSE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 6)
+#define AP_MMIA_SPN_READ_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 7)
+#define AP_MMIA_ZETWS_PRIMARY_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 8)
+#define AP_MMIA_ZETWS_PRIMARY_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 9)
+#define AP_MMIA_ZETWS_SECONDARY_SET_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 10)
+#define AP_MMIA_ZETWS_SECONDARY_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 11)
+#define AP_MMIA_SET_IMSI_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 12)
+#define AP_MMIA_AUTO_START_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 13)
+#define AP_MMIA_CHNEL_STATE_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 14)
+#define AP_MMIA_ZOPERLTEBAND_QUERY_REQ_EV (DWORD)(AP_MMIA_EVENT_OTHER_BASE + 15)
+
+
+#define AP_MMIA_RXLEV_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 0)
+#define AP_MMIA_ZRPT_RXLEVIND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 1)
+#define AP_MMIA_ZRPT_RXLEV_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 2)
+#define AP_MMIA_QUERY_IMSI_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 3)
+#define AP_MMIA_QUERY_IMEI_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 4)
+#define AP_MMIA_COMMON_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 5)
+#define AP_MMIA_CAUSE_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 6)
+#define AP_MMIA_ZPBIC_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 7)
+#define AP_MMIA_SPN_READ_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 8)
+#define AP_MMIA_ZETWS_PRIMARY_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 9)
+#define AP_MMIA_ZETWS_SECONDARY_QUERY_CNF_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 10)
+#define AP_MMIA_ZETWS_PRIMARY_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 11)
+#define AP_MMIA_ZETWS_SECONDARY_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 12)
+#define AP_MMIA_CHG_INDEX_IND_EV (DWORD)(AP_MMIA_OTHER_RSP_EVENT + 13)
+
+/* ========================================================================
+ MMIA-UMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_UMM_SEARCH_PLMN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 0)
+#define MMIA_UMM_PLMN_LIST_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 1)
+#define MMIA_UMM_ACTIVE_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 2)
+#define MMIA_UMM_RF_CTRL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 3)
+#define MMIA_UMM_ABORT_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 4)
+#define MMIA_UMM_EM_LOCK_CELL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 5)
+#define MMIA_UMM_CSG_SEL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 6)
+#define MMIA_UMM_CURRENT_CSG_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 7)
+#define MMIA_UMM_CSG_LIST_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 8)
+#define MMIA_UMM_SYSCONFIG_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 9)
+#define MMIA_UMM_CGATT_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 10)
+#define MMIA_UMM_ZATT_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 11)
+#define MMIA_UMM_EPS_MODE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 12)
+#define MMIA_UMM_EPS_MODE_SET_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 13)
+#define MMIA_UMM_SET_LTE_ACT_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 14)
+#define MMIA_UMM_CS_SRV_CNF_EV (DWORD)(MMIA_UMM_EVENT_BASE + 15)
+#define MMIA_UMM_IMS_REGISTER_STATES_EV (DWORD)(MMIA_UMM_EVENT_BASE + 16)
+#define MMIA_UMM_VOICE_MODE_SET_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 17)
+#define MMIA_UMM_VOICE_MODE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 18)
+#define MMIA_UMM_SYSCONFIG_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 19)
+#define MMIA_UMM_SMSOVERIPNET_SETREQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 20)
+#define Z_TD_LTE_CELL_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 21)
+#define MMIA_UMM_PS_CONTEXT_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 22)
+#define MMIA_UMM_PS_CONTEXT_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 23)
+#define MMIA_UMM_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 24)
+#define MMIA_UMM_UPDATE_OPERPLMN_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 25)
+#define MMIA_UMM_CS_CALL_START_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 26)
+#define MMIA_UMM_CS_CALL_END_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 27)
+#define MMIA_UMM_XCELLINFO_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 28)
+#define MMIA_UMM_LASTCID_APNMODIFY_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 29)
+#define MMIA_UMM_CSVOICE_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 30)
+#define MMIA_UMM_CARDSWITCH_CMP_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 31)
+#define MMIA_UMM_ECALLSPT_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 32)
+#define MMIA_UMM_ECALLONLY_QUERY_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 33)
+#define MMIA_UMM_FREQ_SCAN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 34)
+#define MMIA_UMM_FAST_FREQ_SCAN_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 35)
+#define MMIA_UMM_IMSAIRREL_REQ_EV (DWORD)(MMIA_UMM_EVENT_BASE + 36)
+#define MMIA_UMM_SOFTPOWER_STATUS_IND_EV (DWORD)(MMIA_UMM_EVENT_BASE + 37)
+
+
+#define MMIA_UMM_PLMN_INFO_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 0)
+#define MMIA_UMM_PLMN_LIST_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 1)
+#define MMIA_UMM_ACTIVE_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 2)
+#define MMIA_UMM_MM_INFO_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 3)
+#define MMIA_UMM_RF_CTRL_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 4)
+#define MMIA_UMM_EM_LOCK_CELL_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 5)
+#define MMIA_UMM_CSG_SEL_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 6)
+#define MMIA_UMM_CURRENT_CSG_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 7)
+#define MMIA_UMM_CSG_LIST_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 8)
+#define MMIA_UMM_COMMON_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 9)
+#define MMIA_UMM_CGATT_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 10)
+#define MMIA_UMM_ZATT_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 11)
+#define MMIA_UMM_EPS_MODE_SET_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 12)
+#define MMIA_UMM_EPS_MODE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 13)
+#define MMIA_UMM_SEARCH_PLMN_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 14)
+#define MMIA_UMM_CS_SRV_IND_Ev (DWORD)(MMIA_UMM_RSP_EVENT + 15)
+#define MMIA_UMM_VOICE_MODE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 16)
+#define MMIA_UMM_SYSCONFIG_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 17)
+#define MMIA_UMM_NOTIFY_PS_STATE_EV (DWORD)(MMIA_UMM_RSP_EVENT + 18)
+#define MMIA_UMM_SUBMODE_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 19)
+#define MMIA_UMM_SRVCC_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 20)
+#define MMIA_UMM_PS_CONTEXT_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 21)
+#define MMIA_UMM_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 22)
+#define MMIA_UMM_UPDATE_DUALPSSYSCONFIG_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 23)
+#define MMIA_UMM_IMSNOTSUPPORT_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 24)
+#define MMIA_UMM_PLMNLIST_BANDINFO_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 25)
+#define MMIA_UMM_XCELLINFO_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 26)
+#define MMIA_UMM_CSVOICE_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 27)
+#define MMIA_UMM_SCAN_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 28)
+#define MMIA_UMM_CARDSWITCH_REQ_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 29)
+#define MMIA_UMM_ECALLSPT_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 30)
+#define MMIA_UMM_ECALLONLY_QUERY_CNF_EV (DWORD)(MMIA_UMM_RSP_EVENT + 31)
+#define MMIA_UMM_CAUSE_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 32)
+#define MMIA_UMM_T10DEREG_IND_EV (DWORD)(MMIA_UMM_RSP_EVENT + 33)
+/* ========================================================================
+ MMIA£CCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_CC_MOC_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 0)
+#define MMIA_CC_MTC_RSP_EV (DWORD)(MMIA_CC_EVENT_BASE + 1)
+#define MMIA_CC_ANS_MODE_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 2)
+#define MMIA_CC_MODIFY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 3)
+#define MMIA_CC_DIS_MODE_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 4)
+#define MMIA_CC_DTMF_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 5)
+#define MMIA_CC_CHLD_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 6)
+#define MMIA_CC_STATE_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 7)
+#define MMIA_CC_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 8)
+#define MMIA_CC_CSTA_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 9)
+#define MMIA_CC_CSTA_SET_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 10)
+#define MMIA_CC_MODE_TO_MULTMEDIA_RSP_EV (DWORD)(MMIA_CC_EVENT_BASE + 11)
+#define MMIA_CC_CCM_QUERY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 12)
+#define MMIA_CC_ABORT_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 13)
+#define MMIA_CC_STATE_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 14)
+#define MMIA_CC_OPEN_VOICECHNL_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 15)
+#define MMIA_CC_SRVCC_NOTOPEN_VOICECHNL_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 16)
+#define MMIA_CC_T9TIMER_SET_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 17)
+#define MMIA_CC_T9TIMER_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 18)
+#define MMIA_CC_VOICEMODE_QRY_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 19)
+#define MMIA_CC_RESETIVS_REQ_EV (DWORD)(MMIA_CC_EVENT_BASE + 20)
+
+#define MMIA_CC_MOC_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 0)
+#define MMIA_CC_MTC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 1)
+#define MMIA_CC_ANS_MODE_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 2)
+#define MMIA_CC_MODIFY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 3)
+#define MMIA_CC_DISC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 4)
+#define MMIA_CC_NOTIFY_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 5)
+#define MMIA_CC_AOC_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 6)
+#define MMIA_CC_SS_NOTIFY_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 7)
+#define MMIA_CC_STATE_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 8)
+#define MMIA_CC_COMMON_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 9)
+#define MMIA_CC_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 10)
+#define MMIA_CC_PROC_INFO_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 11)
+#define MMIA_CC_CSTA_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 12)
+#define MMIA_CC_MODE_TO_MULTMEDIAIND_EV (DWORD)(MMIA_CC_RSP_EVENT + 13)
+#define MMIA_CC_DISC_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 14)
+#define MMIA_CC_CALL_STATE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 15)
+#define MMIA_CC_OPEN_VOICE_CHNL_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 16)
+#define MMIA_CC_CLOSE_VOICE_CHNL_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 17)
+#define MMIA_CC_CCM_QUERY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 18)
+#define MMIA_CC_CCWV_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 19)
+#define MMIA_CC_NOTIFY_AOC_TIMER_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 20)
+#define MMIA_CC_CNAP_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 21)
+#define MMIA_CC_DUALPSCFG_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 22)
+#define MMIA_CC_STOP_LOCALVOICE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 23)
+#define MMIA_CC_CHLD_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 24)
+#define MMIA_CC_DTMF_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 25)
+#define MMIA_CC_CSTA_SET_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 26)
+#define MMIA_CC_START_LOCALVOICE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 27)
+#define MMIA_CC_ZECALL_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 28)
+#define MMIA_CC_CECN_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 29)
+#define MMIA_CC_ECALL_WORKSTATE_IND_EV (DWORD)(MMIA_CC_RSP_EVENT + 30)
+#define MMIA_CC_T9TIMER_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 31)
+#define MMIA_CC_CALLBACK_EVENT_EV (DWORD)(MMIA_CC_RSP_EVENT + 32)
+#define MMIA_CC_VOICEMODE_QRY_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 33)
+#define MMIA_CC_RESETIVS_CNF_EV (DWORD)(MMIA_CC_RSP_EVENT + 34)
+
+/* ========================================================================
+ MMIA£SMSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_SMS_SUBMIT_SEND_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 0)
+#define MMIA_SMS_COMMAND_SEND_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 1)
+#define MMIA_SMS_REC_RSP_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 2)
+#define MMIA_SMS_MEM_AVAIL_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 3)
+#define MMIA_SMS_STORE_REPORT_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 4)
+#define MMIA_SMS_ABORT_MO_REQ_EV (DWORD)(MMIA_SMS_EVENT_BASE + 5)
+
+#define MMIA_SMS_MSG_SEND_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 0)
+#define MMIA_SMS_DELIVER_REC_IND_EV (DWORD)(MMIA_SMS_RSP_EVENT + 1)
+#define MMIA_SMS_STATUS_REC_IND_EV (DWORD)(MMIA_SMS_RSP_EVENT + 2)
+#define MMIA_SMS_REC_RSP_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 3)
+#define MMIA_SMS_MMS_DISABLE_IND_EV (DWORD)(MMIA_SMS_RSP_EVENT + 4)
+#define MMIA_SMS_MEM_AVAIL_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 5)
+#define MMIA_SMS_COMMON_CNF_EV (DWORD)(MMIA_SMS_RSP_EVENT + 6)
+
+/* ========================================================================
+ MMIA£SSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_SS_CLCK_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 0)
+#define MMIA_SS_CPWD_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 1)
+#define MMIA_SS_CLIP_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 2)
+#define MMIA_SS_CLIR_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 3)
+#define MMIA_SS_COLP_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 4)
+#define MMIA_SS_COLR_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 5)
+#define MMIA_SS_CCFC_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 6)
+#define MMIA_SS_CCWA_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 7)
+#define MMIA_SS_CUSD_SET_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 8)
+#define MMIA_SS_ABORT_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 9)
+#define MMIA_SS_USSD_CANCEL_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 10)
+#define MMIA_SS_CNAP_READ_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 11)
+#define MMIA_SS_MOLR_ENABLE_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 12)
+#define MMIA_SS_MOLR_DISABLE_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 13)
+#define MMIA_SS_MTLR_ANS_REQ_EV (DWORD)(MMIA_SS_EVENT_BASE + 14)
+
+#define MMIA_SS_COMMON_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 0)
+#define MMIA_SS_CLCK_QUERY_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 1)
+#define MMIA_SS_CLIP_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 2)
+#define MMIA_SS_CLIR_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 3)
+#define MMIA_SS_COLP_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 4)
+#define MMIA_SS_COLR_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 5)
+#define MMIA_SS_CCFC_QUERY_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 6)
+#define MMIA_SS_CCWA_QUERY_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 7)
+#define MMIA_SS_CUSD_MT_IND_EV (DWORD)(MMIA_SS_RSP_EVENT + 8)
+#define MMIA_SS_CNAP_READ_CNF_EV (DWORD)(MMIA_SS_RSP_EVENT + 9)
+#define MMIA_SS_MOLR_RES_IND_EV (DWORD)(MMIA_SS_RSP_EVENT + 10)
+#define MMIA_SS_MTLOCIREQ_NOTIFY_IND_EV (DWORD)(MMIA_SS_RSP_EVENT + 11)
+/* ========================================================================
+ MMIA£SMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_SM_NEG_QOS_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 0)
+#define MMIA_SM_NEG_EQOS_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 1)
+#define MMIA_SM_ACTIVATED_CID_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 2)
+#define MMIA_SM_PDP_STATUS_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 3)
+#define MMIA_SM_PDP_ADDR_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 4)
+#define MMIA_SM_PDP_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 5)
+#define MMIA_SM_PDP_ACTIVATE_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 6)
+#define MMIA_SM_PDP_DEACTIVATE_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 7)
+#define MMIA_SM_PDP_MODIFY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 8)
+#define MMIA_SM_DATA_STATE_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 9)
+#define MMIA_SM_MT_ACT_ANS_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 10)
+#define MMIA_SM_CPSB_QUERY_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 11)
+#define MMIA_SM_CGCONTRDP_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 12)
+#define MMIA_SM_CGSCONTRDP_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 13)
+#define MMIA_SM_CGTFTRDP_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 14)
+
+/* ÒÔÉÏÏûÏ¢ÓжÔÓ¦µÄATÃüÁî */
+#define MMIA_SM_ABORT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 15)
+#define MMIA_SM_IP_PDP_ACT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 16)
+#define MMIA_SM_IDLE_CHNL_QUERY_RSP_EV (DWORD)(MMIA_SM_EVENT_BASE + 17)
+#define MMIA_SM_GET_PCO_RSP_EV (DWORD)(MMIA_SM_EVENT_BASE + 18)
+#define MMIA_SM_DISCONNECT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 19)
+#define MMIA_SM_CONTEXT_REQ_EV (DWORD)(MMIA_SM_EVENT_BASE + 20)
+#define MMIA_SM_CONTEXT_IND_EV (DWORD)(MMIA_SM_EVENT_BASE + 21)
+
+#define MMIA_SM_NEG_QOS_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 0)
+#define MMIA_SM_NEG_EQOS_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 1)
+#define MMIA_SM_ACTIVATED_CID_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 2)
+#define MMIA_SM_PDP_STATUS_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 3)
+#define MMIA_SM_PDP_ADDR_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 4)
+#define MMIA_SM_PDP_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 5)
+#define MMIA_SM_PDP_ACTIVATE_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 6)
+#define MMIA_SM_PDP_DEACTIVATE_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 7)
+#define MMIA_SM_PDP_MODIFY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 8)
+#define MMIA_SM_PDP_ACTIVATE_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 9)
+#define MMIA_SM_CGEV_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 10)
+#define MMIA_SM_IP_PDP_ACT_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 11)
+#define MMIA_SM_CLOSE_CHNL_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 12)
+#define MMIA_SM_IDLE_CHNL_QUERY_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 13)
+#define MMIA_SM_GET_PCO_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 14)
+#define MMIA_SM_COMMON_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 15)
+#define MMIA_SM_CONNECT_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 16)
+#define MMIA_SM_NO_CARRIER_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 17)
+#define MMIA_SM_CID_DEACT_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 18)
+#define MMIA_SM_CPSB_QUERY_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 19)
+#define MMIA_SM_CPSB_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 20)
+#define MMIA_SM_CGCONTRDP_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 21)
+#define MMIA_SM_CGSCONTRDP_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 22)
+#define MMIA_SM_CGTFTRDP_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 23)
+#define MMIA_SM_NOTIFICATION_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 24)
+#define MMIA_SM_MT_ACT_ANS_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 25)
+#define MMIA_SM_CONTEXT_CNF_EV (DWORD)(MMIA_SM_RSP_EVENT + 26)
+#define MMIA_SM_MSISDN_IND_EV (DWORD)(MMIA_SM_RSP_EVENT + 27)
+
+/* ========================================================================
+ ESM- MMIAÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_ESM_MT_EPS_BEARER_ACT_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 0) /*only for R7&R5*/
+#define MMIA_ESM_EPS_BEARER_MOD_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 1)
+#define MMIA_ESM_EBR_MOD_QUERY_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 2)
+#define MMIA_ESM_EPS_QOS_QUERY_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 3) /*only for R7&R5*/
+#define MMIA_ESM_CGATFT_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 4)
+#define MMIA_ESM_ABORT_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 5) /*only for R7&R5*/
+#ifdef BTRUNK_SUPPORT
+#define PTT_MMIA_ESM_TAUTYPE_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 6) /*¼¯ÈºÌí¼Ó*/
+#endif
+#define MMIA_ESM_PDP_CAUSE_QUERY_REQ_EV (DWORD)(MMIA_ESM_EVENT_BASE + 7)
+
+#define MMIA_ESM_EPS_BEARER_ACT_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 0)
+#define MMIA_ESM_EPS_BEARER_DEACT_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 1)
+#define MMIA_ESM_EPS_BEARER_MOD_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 2)
+#define MMIA_ESM_MT_EPS_BEARER_ACT_IND_EV (DWORD)(MMIA_ESM_RSP_EVENT + 3) /*only for R7&R5*/
+#define MMIA_ESM_EPS_BEARER_MOD_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 4)
+#define MMIA_ESM_EPS_BEARER_MOD_REJ_EV (DWORD)(MMIA_ESM_RSP_EVENT + 5)
+#define MMIA_ESM_EBR_MOD_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 6)
+#define MMIA_ESM_EPS_QOS_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 7) /*only for R7&R5*/
+#define MMIA_ESM_CGATFT_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 8)
+#define MMIA_ESM_PDP_ADDR_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 9) /*only for R7&R5*/
+#ifdef BTRUNK_SUPPORT
+#define PTT_MMIA_ESM_TAUTYPE_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 10) /*¼¯ÈºÌí¼Ó*/
+#endif
+#define MMIA_ESM_PDP_CAUSE_QUERY_CNF_EV (DWORD)(MMIA_ESM_RSP_EVENT + 11)
+
+/* ========================================================================
+ MMIA£CBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_CBS_ACTIVATE_REQ_EV (DWORD)(MMIA_CBS_EVENT_BASE + 0)
+
+#define MMIA_CBS_ACTIVATE_CNF_EV (DWORD)(MMIA_CBS_RSP_EVENT + 0)
+#define MMIA_CBS_DATA_IND_EV (DWORD)(MMIA_CBS_RSP_EVENT + 1)
+
+/* ========================================================================
+ MMIA£ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_AS_EM_CELL_INFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 0)
+#define MMIA_AS_EM_HO_INFO_REQ (DWORD)(MMIA_AS_EVENT_BASE + 1)
+#define MMIA_AS_EM_CELLRESORCCOCOUNT_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 2)
+#define MMIA_AS_RPT_RXLEV_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 3)
+#define MMIA_AS_QUERY_RXLEV_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 4)
+#define MMIA_PDI_SELL_STAT_START_SEND_PACKET_IND_EV (DWORD)(MMIA_AS_EVENT_BASE + 5)
+#define MMIA_PDI_SELL_STAT_ABORT_IND_EV (DWORD)(MMIA_AS_EVENT_BASE + 6)
+#define MMIA_EUCSR_LTEINFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 7)
+#define MMIA_L1E_ZEPCG_REQ (DWORD)(MMIA_AS_EVENT_BASE + 8)
+#define MMIA_AS_B39_INFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 9)
+#define MMIA_AS_RSSI_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 10)
+#define MMIA_AS_SINR_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 11)
+#define MMIA_AS_QUERY_EM_CELL_INFO_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 12)
+#define MMIA_AS_TMGI_ACTIVATE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 13)
+#define MMIA_AS_TMGI_DEACTIVATE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 14)
+#define MMIA_AS_SAI_LIST_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 15)
+#define MMIA_AS_TMGI_LIST_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 16)
+#define MMIA_AS_TMGI_LIST_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 17)
+#define MMIA_AS_MBMS_PREFERENCE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 18)
+#define MMIA_AS_TMGI_LIST_REPORT_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 19)
+#define MMIA_AS_SAI_LIST_REPORT_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 20)
+#define MMIA_AS_NW_TIME_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 21)
+#define MMIA_AS_QUERY_CESQ_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 22)
+#define MMIA_AS_EM_LTE_HO_SET_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 23)
+#define MMIA_AS_EM_LTE_HO_SET_QUERY_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 24)
+#define MMIA_L1W_ZWPCG_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 25)
+#define MMIA_L1T_ZTPCG_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 26)
+#define MMIA_GRR_ZGPCG_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 27)
+#define MMIA_AS_QUERY_ZCSQ_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 28)
+#define MMIA_AS_LBS_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 29)
+#define MMIA_AS_IMS_DATA_DELETE_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 30)
+#define MMIA_AS_CARD_SWITCH_REQ_EV (DWORD)(MMIA_AS_EVENT_BASE + 31)
+#define MMIA_AS_CARD_SWITCH_IND_EV (DWORD)(MMIA_AS_EVENT_BASE + 32)
+
+#define MMIA_AS_EM_UCELL_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 0)
+#define MMIA_AS_EM_UHO_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 1)
+#define MMIA_AS_RPT_RXLEV_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 2)
+#define MMIA_AS_QUERY_RXLEV_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 3)
+#define MMIA_EUSIR_ETWS_PRIMARY_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 4)
+#define MMIA_EUSIR_ETWS_SECONDARY_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 5)
+#define MMIA_AS_EM_EUCELL_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 6)
+#define MMIA_EUCSR_LTEINFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 7)
+#define MMIA_L1E_ZEPCG_CNF (DWORD)(MMIA_AS_RSP_EVENT + 8)
+#define MMIA_AS_B39_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 9)
+#define AS_EM_CELL_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 10)
+#define MMIA_AS_RSSI_QUERY_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 11)
+#define MMIA_AS_SINR_QUERY_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 12)
+#define MMIA_AS_QUERY_EM_UCELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 13)
+#define MMIA_AS_QUERY_EM_EUCELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 14)
+#define RR_QUERY_EM_CELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 15)
+#define AS_QUERY_EM_CELL_INFO_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 16)
+#define MMIA_AS_TMGI_ACTIVATE_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 17)
+#define MMIA_AS_TMGI_DEACTIVATE_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 18)
+#define MMIA_AS_SAI_LIST_QUERY_RESP_EV (DWORD)(MMIA_AS_RSP_EVENT + 19)
+#define MMIA_AS_SAI_LIST_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 20)
+#define MMIA_AS_TMGI_LIST_QUERY_RESP_EV (DWORD)(MMIA_AS_RSP_EVENT + 21)
+#define MMIA_AS_TMGI_LIST_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 22)
+#define MMIA_AS_MBMS_SERVICE_SUSPEND_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 23)
+#define MMIA_AS_MBMS_SERVICE_RESUME_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 24)
+#define MMIA_AS_COMMON_CFG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 25)
+#define MMIA_AS_NW_TIME_QUERY_RESP_EV (DWORD)(MMIA_AS_RSP_EVENT + 26)
+#define ATI_EUCSR_HIGHT_CALL_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 27)
+#define MMIA_AS_QUERY_CESQ_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 28)
+#define ATI_EUCSR_BUSY_ALERTING_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 29)
+#define MMIA_ASC_LTE_LOSTCOVERAGE_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 30)
+#define MMIA_AS_EM_LTE_HO_INFO_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 31)
+#define MMIA_AS_EM_LTE_HO_SET_QUERY_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 32)
+#define MMIA_L1W_ZWPCG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 33)
+#define MMIA_L1T_ZTPCG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 34)
+#define MMIA_GRR_ZGPCG_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 35)
+#define MMIA_AS_QUERY_ZCSQ_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 36)
+#define MMIA_AS_LBS_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 37)
+#define MMIA_AS_UL_PARAM_IND_EV (DWORD)(MMIA_AS_RSP_EVENT + 38)
+#define MMIA_AS_CARD_SWITCH_CNF_EV (DWORD)(MMIA_AS_RSP_EVENT + 39)
+/* ========================================================================
+ PDI - ATI ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ATI_PDI_DATA_REQ_EV (DWORD)(ATI_PDI_EVENT_BASE + 0)
+#define ATI_PDI_DATA_IND_EV (DWORD)(ATI_PDI_EVENT_BASE + 1)
+#define PSI_PDI_DATA_IND_EV (DWORD)(ATI_PDI_EVENT_BASE + 2)
+
+/* ========================================================================
+ CSD - ATI ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ATI_CSD_DATA_IND_EV (DWORD)(ATI_CSD_EVENT_BASE + 0)
+
+#define ATI_CSD_FLOW_CTRL_ON_EV (DWORD)(ATI_CSD_RSP_EVENT + 0)
+#define ATI_CSD_FLOW_CTRL_OFF_EV (DWORD)(ATI_CSD_RSP_EVENT + 1)
+
+/*È«¾Ö±äÁ¿ÉèÖᢻñÈ¡ÏûÏ¢¶¨Òå*/
+#define GVAR_MMIA_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 0)
+#define GVAR_MMIA_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 1)
+
+#define GVAR_UMM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 2)
+#define GVAR_UMM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 3)
+
+#define GVAR_MM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 4)
+#define GVAR_MM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 5)
+
+#define GVAR_GMM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 6)
+#define GVAR_GMM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 7)
+
+#define GVAR_UICCMNG_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 8)
+#define GVAR_UICCMNG_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 9)
+
+#define GVAR_CC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 10)
+#define GVAR_CC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 11)
+
+#define GVAR_SM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 12)
+#define GVAR_SM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 13)
+
+#define GVAR_SMS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 14)
+#define GVAR_SMS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 15)
+
+#define GVAR_SS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 16)
+#define GVAR_SS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 17)
+
+#define GVAR_DS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 18)
+#define GVAR_DS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 19)
+#define GVAR_RA_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 20)
+#define GVAR_RA_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 21)
+#define GVAR_RLP_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 22)
+#define GVAR_RLP_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 23)
+
+#define GVAR_CBS_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 24)
+#define GVAR_CBS_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 25)
+
+#define GVAR_URRC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 26)
+#define GVAR_URRC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 27)
+
+#define GVAR_UMTC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 28)
+#define GVAR_UMTC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 29)
+
+#define GVAR_UCER_CONTEXT_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 30)
+#define GVAR_UCER_CONTEXT_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 31)
+#define GVAR_UCER_SECURITY_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 32)
+#define GVAR_UCER_SECURITY_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 33)
+
+#define GVAR_UCSR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 34)
+#define GVAR_UCSR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 35)
+
+#define GVAR_USIR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 36)
+#define GVAR_USIR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 37)
+
+#define GVAR_UMCR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 38)
+#define GVAR_UMCR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 39)
+
+#define GVAR_URBC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 40)
+#define GVAR_URBC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 41)
+
+#define GVAR_UCMR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 42)
+#define GVAR_UCMR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 43)
+
+#define GVAR_URLC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 44)
+#define GVAR_URLC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 45)
+
+#define GVAR_UMAC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 46)
+#define GVAR_UMAC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 47)
+#define GVAR_PDCP_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 48)
+#define GVAR_PDCP_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 49)
+#define GVAR_RABM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 50)
+#define GVAR_RABM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 51)
+
+#define GVAR_PDI_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 52)
+#define GVAR_PDI_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 53)
+
+#define GVAR_SCI_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 54)
+#define GVAR_SCI_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 55)
+
+#define GVAR_GSMA_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 56)
+#define GVAR_GSMA_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 57)
+
+#define GVAR_UICC_DEV_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 58)
+#define GVAR_UICC_DEV_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 59)
+
+#define GVAR_ATMEM_DEV_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 60)
+#define GVAR_ATMEM_DEV_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 61)
+
+#define GVAR_NV_DEV_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 62)
+#define GVAR_NV_DEV_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 63)
+
+#define GVAR_ASC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 64)
+#define GVAR_ASC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 65)
+
+#define GVAR_EMM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 66)
+#define GVAR_EMM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 67)
+
+#define GVAR_ESM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 68)
+#define GVAR_ESM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 69)
+
+/*WCDMA GVAR_EVENT_BASE=150*/
+#define GVAR_WRRC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 70)
+#define GVAR_WRRC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 71)
+
+#define GVAR_WMTC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 72)
+#define GVAR_WMTC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 73)
+
+#define GVAR_WCER_CONTEXT_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 74)
+#define GVAR_WCER_CONTEXT_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 75)
+#define GVAR_WCER_SECURITY_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 76)
+#define GVAR_WCER_SECURITY_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 77)
+
+#define GVAR_WCSR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 78)
+#define GVAR_WCSR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 79)
+
+#define GVAR_WSIR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 80)
+#define GVAR_WSIR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 81)
+
+#define GVAR_WMCR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 82)
+#define GVAR_WMCR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 83)
+
+#define GVAR_WRBC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 84)
+#define GVAR_WRBC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 85)
+
+#define GVAR_WCMR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 86)
+#define GVAR_WCMR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 87)
+
+#define GVAR_WRLC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 88)
+#define GVAR_WRLC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 89)
+
+#define GVAR_WMAC_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 90)
+#define GVAR_WMAC_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 91)
+
+#define GVAR_ECSR_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 92)
+#define GVAR_ECSR_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 93)
+
+#define GVAR_ECER_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 94)
+#define GVAR_ECER_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 95)
+
+#define GVAR_STM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 96)
+#define GVAR_STM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 97)
+#define GVAR_TSM_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 98)
+#define GVAR_TSM_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 99)
+
+#define GVAR_LPP_GET_REQ_EV (DWORD)(GVAR_EVENT_BASE + 100)
+#define GVAR_LPP_GET_CNF_EV (DWORD)(GVAR_EVENT_BASE + 101)
+
+
+#define RRAT_RXSTAT_IND (DWORD)(GRR_EVENT_BASE + 140)
+#define RRMI_RXSTAT_IND (DWORD)(GRR_EVENT_BASE + 141)
+#define RR_EM_HO_INFO_IND (DWORD)(GRR_EVENT_BASE + 142)
+#define RR_EM_CELL_INFO_IND (DWORD)(GRR_EVENT_BASE + 143)
+#define ERRC_CELL_CHANGE_CNF_EV (DWORD)(GRR_EVENT_BASE + 144)
+#define ERRC_CELL_CHANGE_REJ_EV (DWORD)(GRR_EVENT_BASE + 145)
+#define ERRC_RESEL_CNF_EV (DWORD)(GRR_EVENT_BASE + 146)
+#define ERRC_RESEL_REJ_EV (DWORD)(GRR_EVENT_BASE + 147)
+#define ERRC_CELL_SEARCH_CNF_EV (DWORD)(GRR_EVENT_BASE + 148)
+#define ERRC_CELL_SEARCH_REJ_EV (DWORD)(GRR_EVENT_BASE + 149)
+#define URRC_PSHO_CNF_EV (DWORD)(GRR_EVENT_BASE + 150)
+#define URRC_PSHO_REJ_EV (DWORD)(GRR_EVENT_BASE + 151)
+#define ERRC_PSHO_CNF_EV (DWORD)(GRR_EVENT_BASE + 152)
+#define ERRC_PSHO_REJ_EV (DWORD)(GRR_EVENT_BASE + 153)
+#define RR_PSHO_REQ_EV (DWORD)(GRR_EVENT_BASE + 154)
+#define MAC_GRR_PSHO_CNF_EV (DWORD)(GRR_EVENT_BASE + 155)
+#define MAC_GRR_PSHO_REJ_EV (DWORD)(GRR_EVENT_BASE + 156)
+#define MAC_GRR_PSHO_RETURN_CNF_EV (DWORD)(GRR_EVENT_BASE + 157)
+#define MAC_GRR_PSHO_RETURN_FAIL_EV (DWORD)(GRR_EVENT_BASE + 158)
+#define MAC_GRR_PSHO_DEACT_CNF_EV (DWORD)(GRR_EVENT_BASE + 159)
+#define Z_RRMI_INTER_RAT_NCELL_IND_EV (DWORD)(GRR_EVENT_BASE + 160)
+#define RR_XCELLINFO_REQ (DWORD)(GRR_EVENT_BASE + 161)
+#define RR_XCELLINFO_ABORT_REQ (DWORD)(GRR_EVENT_BASE + 162)
+
+/* START OF RRC */
+#define LLC_RRC_DATA_REQ (DWORD)(GRRC_EVENT_BASE + 0)
+#define RR_EM_HO_INFO_REQ (DWORD)(GRRC_EVENT_BASE + 1)
+#define RR_ABORT_REQ (DWORD)(GRRC_EVENT_BASE + 2)
+#define RR_DATA_REQ (DWORD)(GRRC_EVENT_BASE + 3)
+#define RR_HO_START_INFO (DWORD)(GRRC_EVENT_BASE + 4)
+#define GRR_RRC_CLASSMARK_IND (DWORD)(GRRC_EVENT_BASE + 5)
+#define GRR_RRC_UPDATE_PARAM_REQ (DWORD)(GRRC_EVENT_BASE + 6)
+#define GRR_RRC_ASSIGN_REQ (DWORD)(GRRC_EVENT_BASE + 7)
+#define GRR_RRC_EST_REQ (DWORD)(GRRC_EVENT_BASE + 8)
+#define GRR_RRC_ERROR_IND (DWORD)(GRRC_EVENT_BASE + 9)
+#define GRR_RRC_DEACT_REQ (DWORD)(GRRC_EVENT_BASE + 10)
+#define GRR_RRC_RXSTAT_REQ (DWORD)(GRRC_EVENT_BASE + 11)
+#define GRR_RRC_TESTPARAM_REQ (DWORD)(GRRC_EVENT_BASE + 12)
+#define GRR_RRC_MN_MEAS_REQ (DWORD)(GRRC_EVENT_BASE + 13)
+#define GRR_RRC_RRAT_RXSTAT_REQ (DWORD)(GRRC_EVENT_BASE + 14)
+#define GRR_RRC_RRL_DATA_REQ (DWORD)(GRRC_EVENT_BASE + 15)
+#define GRR_RRC_DTM_REQ (DWORD)(GRRC_EVENT_BASE + 16)
+#define GRR_RRC_PDCH_COMPLETE_IND (DWORD)(GRRC_EVENT_BASE + 17)
+#define GRR_RRC_REL_PS_CNF (DWORD)(GRRC_EVENT_BASE + 18)
+#define GRR_RRC_REL_PS_IND (DWORD)(GRRC_EVENT_BASE + 19)
+#define DL_UNIT_DATA_IND (DWORD)(GRRC_EVENT_BASE + 20)
+#define DL_DATA_IND (DWORD)(GRRC_EVENT_BASE + 21)
+#define DL_DATA_REJ (DWORD)(GRRC_EVENT_BASE + 22)
+#define DL_ESTABLISH_IND (DWORD)(GRRC_EVENT_BASE + 23)
+#define DL_ESTABLISH_CON (DWORD)(GRRC_EVENT_BASE + 24)
+#define DL_IRAT_HO_CON (DWORD)(GRRC_EVENT_BASE + 25)
+#define DL_RELEASE_IND (DWORD)(GRRC_EVENT_BASE + 26)
+#define DL_RELEASE_CON (DWORD)(GRRC_EVENT_BASE + 27)
+#define DL_SUSPEND_CON (DWORD)(GRRC_EVENT_BASE + 28)
+#define MDL_ERROR_IND (DWORD)(GRRC_EVENT_BASE + 29)
+#define URRC_HO_INFO_RES (DWORD)(GRRC_EVENT_BASE + 30)
+#define URRC_HO_CNF (DWORD)(GRRC_EVENT_BASE + 31)
+#define URRC_HO_REJ (DWORD)(GRRC_EVENT_BASE + 32)
+#define RR_HO_REQ (DWORD)(GRRC_EVENT_BASE + 33)
+#define RR_VSD_INFO (DWORD)(GRRC_EVENT_BASE + 34)
+#define DL_SENDCMP_IND_EV (DWORD)(GRRC_EVENT_BASE + 35)
+#define GRR_RRC_POWEROFF_IND_EV (DWORD)(GRRC_EVENT_BASE + 36)
+#define T3110 (DWORD)(GRRC_EVENT_BASE + 37)
+#define T3124 (DWORD)(GRRC_EVENT_BASE + 38)
+#define GRRC_T3230_EV (DWORD)(GRRC_EVENT_BASE + 39) // R9 UPDATE
+#define T3148 (DWORD)(GRRC_EVENT_BASE + 40)
+
+ /* END OF RRC */
+
+/* START OF GRR */
+#define RRMN_MEAS_RESULTS_REQ (DWORD)(GRR_EVENT_BASE + 0)
+#define RR_TESTPARAM_REQ (DWORD)(GRR_EVENT_BASE + 1)
+#define RR_EM_CELL_INFO_REQ (DWORD)(GRR_EVENT_BASE + 2)
+#define RR_ACT_REQ (DWORD)(GRR_EVENT_BASE + 3)
+#define RR_CELL_PARAMETER_REQ (DWORD)(GRR_EVENT_BASE + 4)
+#define RR_CLASSMARK_IND (DWORD)(GRR_EVENT_BASE + 5)
+#define RR_DEACT_REQ (DWORD)(GRR_EVENT_BASE + 6)
+#define RR_HPLMN_ACT_REQ (DWORD)(GRR_EVENT_BASE + 7)
+#define RR_PCH_PREFERENCE_REQ (DWORD)(GRR_EVENT_BASE + 8)
+#define RR_PLMN_ABORT_REQ (DWORD)(GRR_EVENT_BASE + 9)
+#define RR_PLMN_REQ (DWORD)(GRR_EVENT_BASE + 10)
+#define RR_UPDATE_PLMN_REQ (DWORD)(GRR_EVENT_BASE + 11)
+#define RR_INACTIVE_REQ (DWORD)(GRR_EVENT_BASE + 12)
+#define RR_HPLMN_ABORT_REQ (DWORD)(GRR_EVENT_BASE + 13)
+#define RR_EST_REQ (DWORD)(GRR_EVENT_BASE + 14)
+#define RR_UPDATE_PARAM_REQ (DWORD)(GRR_EVENT_BASE + 15)
+#define GMMRR_ASSIGN_REQ (DWORD)(GRR_EVENT_BASE + 16)
+#define GMMRR_INFO_REQ (DWORD)(GRR_EVENT_BASE + 17)
+#define GMMRR_RELEASE_REQ (DWORD)(GRR_EVENT_BASE + 18)
+#define RR_TEST_COUNT_REQ (DWORD)(GRR_EVENT_BASE + 19)
+#define RRMI_START_RXSTAT_REQ (DWORD)(GRR_EVENT_BASE + 20)
+#define RRMI_END_RXSTAT_REQ (DWORD)(GRR_EVENT_BASE + 21)
+#define RRL_RR_DATA_REQ (DWORD)(GRR_EVENT_BASE + 22)
+#define RRC_GRR_EST_CNF (DWORD)(GRR_EVENT_BASE + 23)
+#define RRC_GRR_EST_FAIL (DWORD)(GRR_EVENT_BASE + 24)
+#define RRC_GRR_CHN_REL_IND (DWORD)(GRR_EVENT_BASE + 25)
+#define RRC_GRR_DEACT_CNF (DWORD)(GRR_EVENT_BASE + 26)
+#define RRC_GRR_TESTPARAM_CNF (DWORD)(GRR_EVENT_BASE + 27)
+#define RRC_GRR_MN_MEAS_CNF (DWORD)(GRR_EVENT_BASE + 28)
+#define RRC_GRR_RRAT_RXSTAT_IND (DWORD)(GRR_EVENT_BASE + 29)
+#define RRC_GRR_RRL_DATA_IND (DWORD)(GRR_EVENT_BASE + 30)
+#define RRC_GRR_RRL_ABORT_EVENT_IND (DWORD)(GRR_EVENT_BASE + 31)
+#define RRC_GRR_DTM_CNF (DWORD)(GRR_EVENT_BASE + 32)
+#define RRC_GRR_DTM_IND (DWORD)(GRR_EVENT_BASE + 33)
+#define RRC_GRR_DTM_ASS_IND (DWORD)(GRR_EVENT_BASE + 34)
+#define RRC_GRR_DTM_REJ (DWORD)(GRR_EVENT_BASE + 35)
+#define RRC_GRR_PKT_NOTI_IND (DWORD)(GRR_EVENT_BASE + 36)
+#define RRC_GRR_REL_PS_REQ (DWORD)(GRR_EVENT_BASE + 37)
+#define RRC_GRR_CONNECTED_IND (DWORD)(GRR_EVENT_BASE + 38)
+#define RRC_GRR_HO_TO_UTRAN_IND (DWORD)(GRR_EVENT_BASE + 39)
+#define RLC_GRR_ACCESS_REQ (DWORD)(GRR_EVENT_BASE + 40)
+#define RLC_GRR_UPLINK_PDCH_IND (DWORD)(GRR_EVENT_BASE + 41)
+#define RLC_GRR_REL_PDCH_CNF (DWORD)(GRR_EVENT_BASE + 42)
+#define RLC_GRR_UPLINK_PDCH_REL_IND (DWORD)(GRR_EVENT_BASE + 43)
+#define RLC_GRR_STATUS_IND (DWORD)(GRR_EVENT_BASE + 44)
+#define RLC_GRR_UPLINK_PDCH_EST_IND (DWORD)(GRR_EVENT_BASE + 45)
+#define RLC_GRR_TESTPARAM_IND (DWORD)(GRR_EVENT_BASE + 46)
+#define MAC_GRR_DOWNLINK_PDCH_IND (DWORD)(GRR_EVENT_BASE + 47)
+#define MAC_GRR_DOWNLINK_PDCH_REL_IND (DWORD)(GRR_EVENT_BASE + 48)
+#define MAC_GRR_POLLING_CNF (DWORD)(GRR_EVENT_BASE + 49)
+#define MAC_GRR_CIRCUIT_CNF (DWORD)(GRR_EVENT_BASE + 50)
+#define MAC_GRR_CIRCUIT_FAIL (DWORD)(GRR_EVENT_BASE + 51)
+#define MAC_GRR_CIRCUIT_ABORT_CNF (DWORD)(GRR_EVENT_BASE + 52)
+#define MAC_GRR_DATA_IND (DWORD)(GRR_EVENT_BASE + 53)
+#define MAC_GRR_FREQ_UPDATE_REQ (DWORD)(GRR_EVENT_BASE + 54)
+#define MAC_GRR_DEACT_CNF (DWORD)(GRR_EVENT_BASE + 55)
+#define MAC_GRR_IDLE_CHN_REQ (DWORD)(GRR_EVENT_BASE + 56)
+#define MAC_GRR_PERS_LEVEL_IND (DWORD)(GRR_EVENT_BASE + 57)
+#define MAC_GRR_START_TIMER (DWORD)(GRR_EVENT_BASE + 58)
+#define MAC_GRR_STOP_TIMER (DWORD)(GRR_EVENT_BASE + 59)
+#define MAC_GRR_TESTPARAM_IND (DWORD)(GRR_EVENT_BASE + 60)
+#define MAC_GRR_SUSPEND_CNF (DWORD)(GRR_EVENT_BASE + 61)
+#define MAC_GRR_PDCH_FAIL_IND (DWORD)(GRR_EVENT_BASE + 62)
+#define RRAT_RXSTAT_REQ (DWORD)(GRR_EVENT_BASE + 63)
+#define RRAT_CHANGE_REL_REQ (DWORD)(GRR_EVENT_BASE + 64)
+#define RR_CELL_CHANGE_REQ (DWORD)(GRR_EVENT_BASE + 65)
+#define URRC_CELL_CHANGE_CNF (DWORD)(GRR_EVENT_BASE + 66)
+#define URRC_CELL_CHANGE_REJ (DWORD)(GRR_EVENT_BASE + 67)
+#define URRC_RESEL_REJ (DWORD)(GRR_EVENT_BASE + 68)
+#define URRC_RESEL_CNF (DWORD)(GRR_EVENT_BASE + 69)
+#define URRC_SET_INACTIVE_CNF (DWORD)(GRR_EVENT_BASE + 70)
+#define RR_SET_INACTIVE_REQ (DWORD)(GRR_EVENT_BASE + 71)
+#define URRC_ABORT_READ_PREDEF_CNF (DWORD)(GRR_EVENT_BASE + 72)/*WCDMAÏÂʹÓÃ*/
+#define URRC_L1_RSRC_CNF (DWORD)(GRR_EVENT_BASE + 73)
+#define URRC_L1_RSRC_REJ (DWORD)(GRR_EVENT_BASE + 74)
+#define RR_L1_RSRC_REQ (DWORD)(GRR_EVENT_BASE + 75)
+#define RR_L1_RSRC_FREE_IND (DWORD)(GRR_EVENT_BASE + 76)
+#define RR_CELL_SEARCH_REQ (DWORD)(GRR_EVENT_BASE + 77)
+#define URRC_READ_PREDEF_CONF_CNF (DWORD)(GRR_EVENT_BASE + 78)/*WCDMAÏÂʹÓÃ*/
+#define URRC_CELL_RESEL_PARAM_IND (DWORD)(GRR_EVENT_BASE + 79)
+#define URRC_CELL_SEARCH_CNF (DWORD)(GRR_EVENT_BASE + 80)
+#define URRC_CELL_SEARCH_REJ (DWORD)(GRR_EVENT_BASE + 81)
+#define RR_RESEL_REQ (DWORD)(GRR_EVENT_BASE + 82)
+/* ========================================================================
+ MMIA¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MMIA_EM_HO_INFO_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 0)
+#define MMIA_SELL_STAT_ONE_PDP_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 1)
+#define MMIA_SELL_STAT_SUM_PDP_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 2)
+#define MMIA_SELL_STAT_REG_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 3)
+#define MMIA_AOC_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 4)
+#define MMIA_ZGDT_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 5)
+#define MMIA_SOFTRESET_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 6)
+#define MMIA_ZULRTIND_EXPIRY_EV (DWORD)(MMIA_TIMER_EVENT_BASE + 7)
+
+/*´¥·¢ÏûÏ¢*/
+#define MSGTRACEPS_CELL_DISPLAY_REQ_EV (DWORD)(PS_ROADTEST_EVENT_BASE + 0)
+#define ROADTEST_UEINFO_REQ_EV (DWORD)(PS_ROADTEST_EVENT_BASE + 1)
+#define MSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV (DWORD)(PS_ROADTEST_EVENT_BASE + 2)
+
+/*WCDMA PS_ROADTEST_RSP_EVENT =300*/
+#define AT_INFO_RECEIVED_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 18)
+#define AT_INFO_SENT_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 19)
+#define WRLC_UL_DATAPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 20)
+#define WRLC_DL_DATAPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 21)
+#define WRLC_UL_CTRLPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 22)
+#define WRLC_DL_CTRLPDU_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 23)
+#define PDCP2WRLC_DATA_IND_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 24)
+#define PDCP2WRLC_DATA_REQ_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 25)
+#define WMAC_UL_UPA_TB_INFO_TRACE_EV (DWORD)(PS_ROADTEST_RSP_EVENT + 26)
+
+#ifdef BTRUNK_SUPPORT
+/**************************************************PS LTE BTrunk msg range start********************************************************/
+/* ATI --> TSM */
+#define ATI_TSM_REG_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 1)
+#define ATI_TSM_CALL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 2)
+#define ATI_TSM_CALLCONFIRM_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 3)
+#define ATI_TSM_CALLCONNECT_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 4)
+#define ATI_TSM_CALLRLS_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 5)
+#define ATI_TSM_FLOOR_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 6)
+#define ATI_TSM_FLOORRLS_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 7)
+#define ATI_TSM_STUNINFO_QUERY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 8)
+#define ATI_TSM_GROUPINFO_QUERY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 9)
+#define ATI_TSM_SCANGROUPINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 10)
+#define ATI_TSM_SCANSWITCH_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 11)
+#define ATI_TSM_SHAKEHAND_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 12)
+#define ATI_TSM_SHORT_DATA_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 13)
+#define ATI_TSM_LOCATINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 14)
+#define ATI_TSM_SETABILITY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 15)
+#define ATI_TSM_CALLFORWARD_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 16)
+#define ATI_TSM_CALLMODIFY_RSP_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 17)
+#define ATI_TSM_CALLMODIFY_REJ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 18)
+
+/* TSM --> ATI */
+#define ATI_TSM_FLOORGRT_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 25)
+#define ATI_TSM_FLOORRLS_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 26)
+#define ATI_TSM_FLOORRLS_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 27)
+#define ATI_TSM_FLOORREJ_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 28)
+#define ATI_TSM_FLOORWAIT_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 29)
+#define ATI_TSM_FLOORINFORM_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 30)
+#define ATI_TSM_STUNINFO_QUERY_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 31)
+#define ATI_TSM_STUNINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 32)
+#define ATI_TSM_GROUPINFO_QUERY_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 33)
+#define ATI_TSM_GROUPINFO_UPDATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 34)
+#define ATI_TSM_GROUPCALL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 35)
+#define ATI_TSM_SCANGROUPINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 36)
+#define ATI_TSM_SHAKEHAND_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 37)
+#define ATI_TSM_SHORT_DATA_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 38)
+#define ATI_TSM_LOCATINFO_TYPE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 39)
+#define ATI_TSM_FALLBACK_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 40)
+#define ATI_TSM_REG_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 41)
+#define ATI_TSM_REGSTATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 42)
+#define ATI_TSM_CALL_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 43)
+#define ATI_TSM_CALLRLS_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 44)
+#define ATI_TSM_CALL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 45)
+#define ATI_TSM_CALLPROCEED_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 46)
+#define ATI_TSM_CALLALERTING_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 47)
+#define ATI_TSM_CALLCONNECTACK_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 48)
+#define ATI_TSM_CALLRLS_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 49)
+#define ATI_TSM_SPEAKINGTIMEROUT_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 50)
+#define ATI_TSM_VIDEOSOURCE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 51)
+#define ATI_TSM_SCANGROUPINFO_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 52)
+#define ATI_TSM_SRSTATUS_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 53)
+#define ATI_TSM_CALLHOLD_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 54)
+#define ATI_TSM_PTTBEAR_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 55)
+#define ATI_TSM_BUSY_ALERTING_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 56)
+#define ATI_TSM_CALLFORWARD_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 57)
+#define ATI_TSM_CALLMODIFY_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 58)
+#define ATI_TSM_CALLMODIFY_ACK_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 59)
+#define ATI_TSM_REGEXTINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 60)
+#endif
+#endif
+
diff --git a/patch/17.09_19.00/code/old/upstream/pub/include/ps_phy/psevent.h b/patch/17.09_19.00/code/old/upstream/pub/include/ps_phy/psevent.h
new file mode 100755
index 0000000..d1fbdf8
--- /dev/null
+++ b/patch/17.09_19.00/code/old/upstream/pub/include/ps_phy/psevent.h
@@ -0,0 +1,5172 @@
+/*****************************************************************************
+ *°æ±¾ËùÓÐ (C)2007ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
+ * Ä£¿éÃû £ºPUB
+ * ÎļþÃû £ºpsEvent.h
+ * Îļþ±êʶ£º
+ * Ïà¹ØÎļþ£º
+ * ʵÏÖ¹¦ÄÜ£ºÐÒéÕ»Èí¼þʼþºÅ¶¨Òå
+ * ×÷Õß £º
+ * °æ±¾ £º
+ * Íê³ÉÈÕÆÚ£º
+ * ÆäËü˵Ã÷£º
+ *
+ * Ð޸ļǼºÅ ÈÕÆÚ ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+ 1 2008.02.23 ½ºè 1)ÐÒéÕ»ÐèÒªºÍCOMNEON´úÂ뻥ͨ£¬ÆäʼþºÅ¶¨ÒåΪ16λ¡£¹ÊÏÞÖÆÐÒéջʼþºÅÓÐЧ·¶Î§ÎªµÍ16λ¡£
+ 2 2008.05.14 ½ºè 1)Ôö¼ÓÁËSCIÓëURRC/CCÖ®¼äµÄʼþºÅ¶¨Òå
+ 3 2008.05.15 ½ºè 1)Ôö¼ÓÁËCCÓëURRC¼äµÄʼþºÅ¶¨Òå:GMMAS_CALLTYPENOTIFYREQ_EV
+ 4 2008.05.19 ½ºè 1Ôö¼ÓTAFÓëL1G¼äµÄʼþºÅ¶¨Òå
+ 5 2008.05.29 ½ºè 1)Ôö¼ÓGSM²âÊÔÄ£¿é¼äʼþºÅ
+ 6 2008.06.05 ½ºè 1)Ôö¼ÓGVAR_SCI_GETREQ_EV¡¢GVAR_SCI_GETCNF_EV¡¢CSCI_CONFIGREL_EV
+ 7 2008.06.12 ½ºè 1)Ôö¼ÓATIÓëCSD¼äµÄʼþºÅ¶¨Òå
+ 8 2008.06.12 ½ºè 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁË£º
+ LLGMM_USERDATAPRESENT_EV;
+ GMMAS_ASSIGNREQ_EV¡¢GMMAS_INFOREQ_EV¡¢GMMAS_SUSPENDIND_EV
+ CPDI_SENDDATAIND_EV£»
+ SM_PDCP_RATACTIND_EV¡¢SM_PDCP_RATACTRSP_EV¡¢SM_PDCP_RATDEACTIND_EV¡¢
+ SM_PDCP_RATSEQIND_EV¡¢SM_PDCP_RATSEQRSP_EV¡¢SM_PDCP_READYIND_EV£»
+ SNSM_RATDEACTRSP_EV£»
+ UMMAS_PLMNLISTREJ_EV¡¢UMMAS_PCHPRE_REQ¡¢UMMAS_ABORTHPPLMNREQ_EV¡¢
+ UMMAS_UPDATEPARAMREQ_EV¡¢UMMAS_INACTIVEREQ_EV¡¢UMMAS_INACTIVECNF_EV¡¢
+ UMMAS_RATCHNIND_EV¡¢UMMAS_HOSTARTIND_EV¡¢UMMAS_CCOSTARTIND_EV
+ 9 2008.06.14 ½ºè 1)Ôö¼ÓTOOL_NGMAC_PMO_REQ_EV¡¢TOOL_NGMAC_PSI_REQ_EV¶¨Òå
+ 2)¸üÃû£ºUMMAS_PCHPRE_REQ £½¡·UMMAS_PCHPREREQ_EV
+ 10 2008.06.16 ËïÒÔÀ× 1)Ôö¼ÓSNDCP-SMÖ®¼äʼþºÅ
+ 2)Ôö¼ÓGSMA²âÊÔʼþºÅ:GVAR_GSMA_GETREQ_EV¡¢GVAR_GSMA_GETCNF_EV
+ 11 2008.06.17 ÕÅÅô³Ì 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁËURRC-GRR¡¢URRCÄÚ²¿¡¢URRC-PHYÖ®¼äʼþºÅ
+ 12 2008.06.18 ÕÅÅô³Ì 1)Ôö¼ÓUMMAS_TRYHPPLMNCNF_EV
+ 13 2008.06.18 ½ºè 1)ÐÞ¸ÄÁËURRC-GRRÖ®¼äʼþºÅÃû³Æ
+ 14 2008.06.19 ÍõÀò 1)Ôö¼ÓSNSM_READYIND_EV,ɾ³ýSNSM_RATDEACTRSP_EV
+ 15 2008.06.20 ËïȪ 1)Ôö¼ÓTOOL_L1SIMU_DCCHFAIL_CFG_EV
+ 16 2008.06.20 ÕÅÅô³Ì 1)Ôö¼ÓURRCGRR_CAMPONCELLCNF_EV¡¢URRCGRR_CAMPONCELLIND_EV
+ 17 2008.06.30 Ç®¿¡ 1)Ôö¼ÓNGMACʼþºÅ:
+ TOOL_NGMAC_ULTBF_EST_CFG_EV ¡¢TOOL_NGMAC_DLTBF_EST_CFG_EV
+ TOOL_NGMAC_ULTBF_REL_CFG_EV ¡¢TOOL_NGMAC_DLTBF_REL_CFG_EV
+ TOOL_NGMAC_PKTTSRECFG_REQ_EV ¡¢TOOL_NGMAC_PKTTBFREL_REQ_EV
+ TOOL_NGMAC_PKTPDCHREL_REQ_EV ¡¢TOOL_NGMAC_PKTCCC_REQ_EV
+ TOOL_NGMAC_PKTCCO_REQ_EV ¡¢TOOL_NGMAC_PKTNCD_REQ_EV
+ TOOL_NGMAC_PKTPOLL_REQ_EV ¡¢TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV
+ TOOL_NGMAC_PKTPRACHPARA_REQ_EV ¡¢TOOL_NGMAC_PKTSCD_REQ_EV
+ TOOL_NGMAC_PKTQUENOTI_REQ_EV ¡¢TOOL_NGMAC_PKTACCREJ_REQ_EV
+ NGMAC_TOOL_PKTMEARPT_EV¡¢NGMAC_TOOL_PKTMOBTBFSTA_EV
+ NGMAC_TOOL_PKTPSISTA_EV ¡¢NGMAC_TOOL_PKTPAUSE_EV
+ NGMAC_TOOL_PKTEMEARPT_EV ¡¢NGMAC_TOOL_PKTADDMSRAC_EV
+ NGMAC_TOOL_PKTCCN_EV ¡¢NGMAC_TOOL_PKTSISTA_EV
+ 2)Ôö¼ÓNGRLCʼþºÅ:
+ TOOL_NGRLC_ULTBF_EST_CFG_EV ¡¢TOOL_NRLC_PUAN_REQ_EV
+ TOOL_NGRLC_DLTBF_CFG_EV ¡¢NGRLC_TOOL_DLTBF_HALF_IND_EV
+ NGRLC_TOOL_DLTBF_FINAL_IND_EV ¡¢NGRLC_TOOL_ULTBF_HALF_IND_EV
+ NGRLC_TOOL_ULTBF_FINAL_IND_EV ¡¢TOOL_NGRLC_ULTBF_REL_EV
+ NGRLC_TOOL_ULTBF_FAI_IND_EV
+ 3)À©Õ¹ÁËNGMACʼþ·¶Î§£º50-¡·100
+ 18 2008.07.02 ½¯Õ×´º 1)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄǰ׺°´AP-MMIAʼþºÅǰ׺
+ 2)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄ·¶Î§ÓÉÔÀ´µÄMMIA-NASÒƵ½AP-MMIA
+ 19 2008.07.03 ½ºè 1)Ôö¼ÓÉèÖÃNUMAC¡¢NURLCÓ¦´ð¿ØÖÆÏûÏ¢:
+ TEST_URLCACKCTRL_UTRAN_EV¡¢TEST_UMACACKCTRL_UTRAN_EV
+ 20 2008.07.19 ½ºè 1)Ôö¼ÓTOOL_L1SIMU_SYSINFOFAIL_CFG_EV¡¢
+ GMAC_GET_BLOCKS_EV¡¢GMAC_ACK_BLOCKS_EV¡¢TOOL_NGMAC_PKTPGREQ_REQ_EV
+ 2)ÐÞ¸ÄNGRLCʼþºÅ¶¨Òå
+ 21 2008.07.22 ½ºè 1)Ôö¼ÓGSMÄ£ÄâʼþºÅ·¶Î§ºê¶¨Ò壺EVENT_PS_GSM_SIMU_BEGIN/EVENT_PS_GSM_SIMU_END
+ 22 2008.07.25 ÅËÀÚ 1)Ôö¼ÓÓëTCÏà¹ØʼþºÅ¶¨Òå
+ 23 2008.08.13 ½ºè 1)Ôö¼ÓÁËUMCR-GPHYÖ®¼äµÄʼþºÅ·¶Î§¶¨Òå
+ 2)½«UMCRÓëGSM²âÁ¿Ïà¹ØʼþºÅ¶¨ÒåÒÆÈëUMCR-GPHY·¶Î§ÄÚ
+ 3)Ôö¼ÓÁËURRAÄ£¿éµÄ¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 24 2008.08.14 ÕÅÅô³Ì 1)Ôö¼ÓÁËURRC-GRR¼äURRCGRR_HOINFOCNF_EV¡¢URRCGRR_HOINFOIND_EV
+ 2)Ôö¼ÓÁ˺¯ÊýÐÅÁî¸ú×ÙʼþºÅ·¶Î§ºÍURRCÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+ 25 2008.08.15 ÌÀÔ±¦ 1)Ôö¼ÓURRCINTRA_RADIOLINKFAIL_IND_EVÏûÏ¢
+ 26 2008.08.18 ÍõÀò 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_RXLEVREQ_CFG_EV
+ L1SIMU_TOOL_SYNCREQ_CFG_EV
+ L1SIMU_TOOL_SYSREQ_CFG_EV
+ L1SIMU_TOOL_IDLEMODEREQ_CFG_EV
+ L1SIMU_TOOL_NCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_SCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_MEAS_REPORT_CFG_EV
+ L1SIMU_TOOL_DLTBFRELIND_EV
+ L1SIMU_TOOL_ULTBFRELIND_EV
+ 2)Ôö¼ÓNGMACʼþºÅ£ºTOOL_NGMAC_CTRLBLOCK_REQ_EV
+ ʯ×ÚÀ¤ 1)Ôö¼ÓURRAÓëTD PHYÖ®¼äʼþºÅ¶¨Òå
+ 2)Ôö¼ÓL1G-GSMAÖ®¼äʼþºÅ¶¨Òå
+ ×ÞÑÞ 1)Ôö¼ÓGMMAS_CCSYNCIND_GSM_EVʼþºÅ
+ ÕŽ¡ 1)Ôö¼ÓNLAPDMºÍTRSÖ®¼äÓÃÓÚ²»Í¬SAPI¼äÏûÏ¢·¢ËͺÍÒì³£²âÊÔµÄʼþºÅ¶¨Òå
+ NLAPDM_L2_DATA_IND_EV
+ NLAPDM_TOOL_SABM_IND_EV
+ TOOL_NLAPDM_UA_RSP_EV
+ NLAPDM_TOOL_SABM_COR_IND_EV
+ TOOL_NLAPDM_UA_COR_RSP_EV
+ TOOL_NLAPDM_EXCEPT_DATA_EV
+ NLAPDM_TOOL_I_IND_EV
+ ׿Խ 1)Ôö¼ÓURRC_FUNC_SUSPENDMEASREQ_EV
+ 27 2008.08.20 ʯ×ÚÀ¤ 1)Ôö¼ÓL1GÐÅÁî¸ú×ÙʼþºÅ¶¨Ò壺L1G_ST_....
+ 2)Ôö¼ÓURRA-GPHYʼþºÅ·¶Î§¶¨Òå
+ 28 2008.08.30 ½ª²¨ 1)ÓÉÓÚ´¦Àí¸ÕפÁôijСÇø1SÄÚ²»ÄܶԲâÁ¿¸üºÃµÄСÇø½øÐÐÖØÑ¡£¬Ôö¼ÓUCSR_TCAMP1S_EXPIRY_EV
+ Ç®¿¡ 2)Ôö¼ÓGSMÐÅÁî¸ú×ÙʼþºÅ¶¨Òå¡£
+ 29 2008.09.03 ½ºè 1)L1G_GSMA_EVENT_BASE/L1G_GSMA_EVENT_END ÐÞ¸ÄΪ£ºL1G_DM_EVENT_BASE/L1G_DM_EVENT_END
+ 2)L1GË«Ä£ÏûϢǰ׺¸ü¸ÄΪ£ºL1G_DM_
+ 3)Ôö¼ÓÁËL1G_DM_TDD_CELL_MEAS_REQ
+ 4)Ôö¼ÓÁËL1SIMU_TOOL_TAFIND_EV¡¢L1SIMU_TOOL_TAFREQ_EV
+ 30 2008.09.16 ÍõÀò 1)Ôö¼Ó3Gʱ,UMMÏòRBCÅäÖÃÑ°ºôµÄÇëÇóʼþºÅ£º
+ UMMAS_PAGEREQ_EV
+ 31 2008.09.19 ½ºè 1)SDLÈÎÎñºÍÆÕͨÈÎÎñ¼äÏûÏ¢¶¨ÒåͳһÔÚSIG_CODE.HÖУ¬ÏÂÁкêÃû±»ÒÆ×ߣº
+ L1G_DM_DEACT_UMTS_REQ¡¢L1G_DM_DEACT_GSM_CNF
+ L1G_DM_TDD_CELL_MEAS_REQ¡¢L1G_UTRAN_MEAS_PERIOD_IND
+ 2)ɾ³ýÁË£º
+ L1G_DM_EVENT_BASE¡¢L1G_DM_EVENT_END
+ P_GSM_INACT_TIME_REQ_EV¡¢P_ABORT_GSM_GAP_REQ_EV¡¢P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ 32 2008.09.22 ÍõС½ø 1)Ôö¼ÓAP_MMIA_SMSABORTMOREQ_EV¡¢MMIASMS_ABORTMOREQ_EV
+ 33 2008.10.10 ÍõÀò 1)Ôö¼ÓUMMAS_PWRONREQ_EV
+ 34 2008.10.15 Íõ¾´Ò¢ 1)Ôö¼ÓNGMACʼþºÅ:
+ NGMAC_TOOL_CCF_IND_EV
+ 35 2008.10.24 ʯ×ÚÀ¤ 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV¡¢
+ L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV
+ 36 2008.11.05 ½ºè 1)ÐÞ¸ÄËùÓÐZ_ǰ׺Ϊ
+ 37 2008.11.13 ÍõÀò 1)Ôö¼ÓGMM_TPOWEROFF_EXPIRY_EV:2G¹Ø»ú¼à¿ØÈ¥»îÁ÷³Ì¶¨Ê±Æ÷
+ 38 2008.11.17 ÑîÎÄÇ¿ 1)È¡ÏûÏûÏ¢NGRLC_START_TIMER_EV(²»ÔÙʹÓÃ)
+ 2)Ôö¼Ó ÏûÏ¢NGRLC_TOOL_DLTBF_FAI_IND_EV¡¢TOOL_NGRLC_BEGINTESTMODE_EV¡¢NGRLC_TOOL_PDANNOTIFY_EV
+ 39 2008.11.27 ¸ßÏè 1)Ôö¼ÓCUMAC_GETTVBOCMPIND_EV£¬ÒÔ֪ͨUMCRÄ£¿é²ÉÑùÍê³É£¬¿ÉÒÔ½øÐÐÏà¹ØÆÀ¹ÀºÍ±¨¸æ¡£
+ ΤÓñÕä 1)Ôö¼ÓP_GSM_MEAS_DONE_REQ_EV
+ 40 2008.11.28 ׿Խ 1)ɾ³ýÁËMAC²âÁ¿²¿·ÖÐÅÁî¸ú×ÙÏûÏ¢URRC_FUNC_SUSPENDMEASREQ_EV,URRC_FUNC_TVMEASREQ_EV,URRC_FUNC_QUAMEASREQ_EV,URRC_FUNC_UEINTERMEASREQ_EV,
+ URRC_FUNC_RESUMEMEASREQ_EV,URRC_FUNC_MACRPT_EV,URRC_FUNC_TVDISTRIBUTE_EV,URRC_FUNC_QUADISTRIBUTE_EV,URRC_FUNC_UEINTERDISTRIBUTE_EV
+ 41 2008.12.10 ½¯Õ×´º 1)Ôö¼ÓUMMAS_ABORTCNF_EV
+ 42 2008.12.29 ½ºè 1)Ϊ֧³Ö½Å±¾¿ØÖÆCSDÒµÎñ£¬Ôö¼ÓTEST_TAFDATAIND_UTRAN_EV
+ ¸ßÏè148725 1)ÐÞ¸ÄSM¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 2)Ôö¼ÓMMIASM_PDPAUTOACTIND_EV
+ 43 2008.12.31 ×ÞÑÞ 1)Ôö¼ÓÁËCC¶¨Ê±Æ÷ʼþºÅ £ºCC_TMMCONN_EXPIRY_EV ¼à¿ØMMÁ¬½ÓµÄ½¨Á¢
+ 44 2009.02.10 ÑîÔÊ 1)Ôö¼ÓÁËMMÄ£¿é¶¨Ê±Æ÷ÏûÏ¢£ºMM_T3231_EXPIRY_EV¡¢MM_T3232_EXPIRY_EV
+ 45 2009.02.12 ½ºè 1)TAFÓëL1GÏûÏ¢¶¨ÒåÒÆÈëSIG_CODE.H£¬É¾³ýTAF_L1GÏûÏ¢·¶Î§
+ 2)Ôö¼ÓTAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢£ºTAF_FUNC_L1GDATAREQ_EV
+ 46 2009.02.16 ÍõС½ø 1)UMMÐÂÔöATÃüÁIMSI¼¤»îÈ¥»îÇëÇ󡢶ÔÁ½¸öÓòͬʱ½øÐÐÈ¥»îµÄÇëÇó¡¢ÉèÖÃGPRS×Ô¶¯¸½×ÅÇëÇó£¬
+ Ôö¼ÓÏûÏ¢¶¨Ò壺AP_MMIA_ZATTSETREQ_EV¡¢AP_MMIA_ZATTQUERYREQ_EV¡¢
+ AP_MMIA_ZGAATSETREQ_EV¡¢AP_MMIA_ZGAATQUERYREQ_EV¡¢
+ AP_MMIA_ZATTQUERYCNF_EV¡¢AP_MMIA_ZGAATQUERYCNF_EV
+ 47 2009.02.19 Ëﳤ½ 1)MM/GMM/CC£RRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºGMMAS_CSRABRELIND_EV;
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_ABORTCFGREQ_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_ACTTIMENOTIFY_REQ_EV£»
+ 48 2009.02.21 ×ÞÑÞ 1)Ö§³ÖMODIFY¹ý³Ì£¬Ôö¼ÓCCÓëTAFʼþºÅ¶¨Ò壺
+ CCTAF_PEND_REQ_EV¡¢CCTAF_RESUME_REQ_EV¡¢CCTAF_MODIFYBC_REQ_EV¡¢CCTAF_MODIFYBC_CNF_EV
+ 2)Ôö¼ÓCC¶¨Ê±Æ÷ʼþºÅ¶¨Ò壺
+ CC_TRELTAF_EXPIRY_EV
+ CC_TCONNTAF_EXPIRY_EV
+ CC_TSYNCIND_EXPIRY_EV
+ CC_TMODIFYBC_EXPIRY_EV
+ 49 2009.02.24 ½»¶ 1)Ϊ֧³ÖUSAT¹¦ÄÜ£¬Ôö¼ÓMMIAÓëATI/UICCÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_USAT_ENVELOPREQ_EV
+ AP_MMIA_USAT_ENVELOPCNF_EV
+ AP_MMIA_USAT_TERMNLRSPREQ_EV
+ AP_MMIA_USAT_TERMNLPROFREQ_EV
+ AP_MMIA_USAT_PROCMDIND_EV
+ AP_UICC_USAT_ENVELOPREQ_EV
+ AP_UICC_USAT_ENVELOPCNF_EV
+ AP_UICC_USAT_TERMNLRSPREQ_EV
+ AP_UICC_USAT_TERMNLPROFREQ_EV
+ AP_UICC_USAT_COMMONCNF_EV
+ AP_UICC_USAT_PROVCMDIND_EV
+ 50 2009.03.05 ÍõС½ø 1)UICCNOCARDIND²»ÔÙÉϱ¨¸øATI£¬ËùÒÔɾ³ýAP_MMIA_UICCNOCARDIND_EV
+ 51 2009.03.10 ½ºè Ôö¼ÓÖ§³ÖCBS¹¦ÄÜ
+ 1)Ôö¼ÓMMIA-ATI¡¢MMIA-CBSÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_CBS_CSCBSETREQ_EV
+ AP_MMIA_CBS_CSCBREADREQ_EV
+ AP_MMIA_CBS_SAVINGSETREQ_EV
+ AP_MMIA_CBS_RESTORESETREQ_EV
+ AP_MMIA_CBS_CSCBREADCNF_EV
+ AP_MMIA_CBS_TCBMIND_EV
+ AP_MMIA_CBS_PCBMIND_EV
+ AP_MMIA_CBS_TCBMLISTCNF_EV
+ AP_MMIA_CBS_PCBMLISTCNF_EV
+ AP_MMIA_CBS_TCBMREADCNF_EV
+ AP_MMIA_CBS_PCBMREADCNF_EV
+ MMIACBS_ACTIVATEREQ_EV
+ MMIACBS_ACTIVATECNF_EV
+ MMIACBS_DATAIND_EV
+ 2)CBSÏà¹ØATÃüÁî¶ÔÓ¦ÏûÏ¢´ÓAP-MMIA SMS²¿·Ö¶¨ÒåÖÐɾ³ý£º
+ AP_MMIA_SMSCSCBREQ_EV
+ AP_MMIA_SMSCSASREQ_EV
+ AP_MMIA_SMSCRESREQ_EV
+ AP_MMIA_SMSTCBMIND_EV
+ AP_MMIA_SMSTCBMREADCNF_EV
+ AP_MMIA_SMSCSCBCNF_EV
+ AP_MMIA_SMSCSASCNF_EV
+ AP_MMIA_SMSCRESCNF_EV
+ AP_MMIA_SMSTCBMLISTCNF_EV
+ 3)CBSÓëURBCµÄÖ®¼äµÄʼþºÅ¶¨Òå:
+ CBSAS_NODRXREQ_EV
+ CBSAS_DRXRSVREQ_EV
+ CBSAS_STOPREQ_EV
+ CBSAS_PCHCELLINFOIND_EV
+ 4)CBSÓëUMMÖ®¼äµÄʼþºÅ¶¨ÒåµÄ¶¨Òå:
+ UMMCBS_STARTREQ_EV
+ UMMCBS_STOPREQ_EV
+ UMMCBS_CELLINFOIND_EV
+ 5)CBS¶¨Ê±Æ÷ÏûϢʼþºÅµÄ¶¨Òå:
+ CBS_TSCHEDCHECK_EXPIRY_EV
+ 6)Ôö¼ÓURBCÓëURLCÖ®¼ä½Ó¿Ú¶¨Ò壺
+ CURLC_CBSRBCONFIGREQ_EV
+ 7)Ôö¼ÓURBCÓëPHYÖ®¼ä½Ó¿Ú¶¨Ò壺
+ P_CBS_NODRX_REQ_EV
+ P_CBS_DRX_REQ_EV
+ P_ADD_MODIFY_CBS_REQ_EV
+ P_STOP_CBS_REQ_EV
+ 52 2009.03.20 ÍõС½ø 1)Ôö¼ÓÖ§³ÖATÃüÁ+ZUSTAT,+ZURDY,+ZUSLOT,+ZPINSTAT
+ AP_MMIA_UICCCOMMANDREQ_EV
+ AP_MMIA_UICCCOMMANDQUERYCNF_EV
+ 53 2009.03.23 ÍõС½ø 1)Ôö¼ÓÏûÏ¢£º
+ AP_MMIA_USAT_LOCINFOCNF_EV
+ AP_MMIA_USAT_LOCINFOREQ_EV
+ 54 2009.03.31 ½»¶ 1)Ôö¼ÓÖ§³Ö¹¤³Ìģʽ£º
+ AP_MMIA_EM_CELLINFOREQ_EV
+ AP_MMIA_EM_CELLINFOQUERYREQ_EV
+ AP_MMIA_EM_LOCKCELLREQ_EV
+ AP_MMIA_EM_HOINFOREQ_EV
+ AP_MMIA_EM_HOINFOQUERYREQ_EV
+ AP_MMIA_EM_CELLINFOIND_EV
+ AP_MMIA_EM_CELLINFOQUERYCNF_EV
+ AP_MMIA_EM_HOINFOIND_EV
+ AP_MMIA_EM_HOINFOQUERYCNF_EV
+ MMIAUMM_EM_LOCKCELLREQ_EV
+ MMIAUMM_EM_LOCKCELLCNF_EV
+ MMIAAS_EM_CELLINFOREQ_EV
+ MMIAAS_EM_HOINFO_REQ
+ MMIAAS_EM_UCELLINFOIND_EV
+ MMIAAS_EM_UHOINFOIND_EV
+ UMMAS_LOCKCELLREQ_EV
+ UMMAS_UNLOCKCELLREQ_EV
+ UMMAS_LOCKCELLCNF_EV
+ MMIA_EM_HOINFO_EXPIRY_EV
+ UMCR_EM_CELLINFO_EXPIRY_EV
+ 55 2009.04.02 ΤÓñÕä 1)ÐÞ¸ÄÐźÅÇ¿¶ÈÉϱ¨·½Ê½£¬Ôö¼Ó£º
+ AP_MMIA_RXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVQUERYREQ_EV
+ AP_MMIA_RXLEVCNF_EV
+ AP_MMIA_ZRPTRXLEVIND_EV
+ AP_MMIA_ZRPTRXLEVQUERYCNF_EV
+ MMIAAS_RPTRXLEV_REQ_EV
+ MMIAAS_QUERYRXLEV_REQ_EV
+ MMIAAS_RPTRXLEV_IND_EV
+ MMIAAS_QUERYRXLEV_IND_EV
+ ɾ³ý:
+ MMIAMCR_RPTPRDREQ_EV
+ MMIAMCR_RSSIIND_EV
+ AP_MMIA_CSQEXEREQ_EV
+ AP_MMIA_ZSQSETREQ_EV
+ AP_MMIA_ZSQQUERYREQ_EV
+ AP_MMIA_ZSQIND_EV
+ AP_MMIA_CSQEXECNF_EV
+ AP_MMIA_ZSQQUERYCNF_EV
+ 56 2009.04.13 ½ºè 1)ΪÔö¼ÓL1GÓëPHYÖ®¼ä˫ģʼþºÅ¶¨Ò壺
+ P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ P_GSM_INACT_TIME_REQ_EV
+ P_ABORT_GSM_GAP_REQ_EV
+ 2)ºô½ÐÐÅÏ¢Éϱ¨£º
+ AP_MMIA_CCPROCINFOIND_EV
+ MMIACC_PROCINFOIND_EV
+ 3)Ϊ±ÜÃⲻͬ½á¹¹¶ÔӦͬÃûÏûÏ¢£¬Ôö¼Ó£º
+ TEST_UURLCDATAIND_UTRAN_EV
+ TEST_UURLCCONFIGREQ_UTRAN_EV
+ 57 2009.05.08 ½ª²¨ 1)Ôö¼ÓUMCRͬUCSRÖ®¼ä֪ͨÁÚÇø¸ü¸ÄµÄURRCÄÚ²¿Ê¼þºÅ:
+ URRCINTRA_NEIBCELLCHGIND_EV
+ 58 2009.05.11 ½ª²¨ 1)ɾ³ýUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CAMPONCELLREQ_EV
+ URRCGRR_CAMPONCELLCNF_EV
+ URRCGRR_CAMPONCELLIND_EV
+ URRCGRR_CAMPONCELLRSP_EV
+ 2)Ôö¼ÓUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CELLRESELREQ_EV
+ URRCGRR_ANYCELLRESELREQ_EV
+ URRCGRR_CELLRESELIND_EV
+ URRCGRR_CELLRESELREJ_EV
+
+ 59 2009.05.19 ½¯Õ×´º 1)Ôö¼ÓUMMͬGSMAÖ®¼äµÄʼþºÅ
+ UMMAS_GSMSRVNOTIFYREQ_EV
+ 60 2009.05.20 Ëﳤ½ 1)URLC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCURLC_CONFIGCNF_EV£»
+ ɾ³ýÏûÏ¢ºÅCURLC_STOPREQ_EV£»
+ 2)URRC/CC£SCIÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCSCI_CONFIGCNF_EV£»
+ 3)PDCP£URRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCPDCP_CONFIGCNF_EV£»
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_FACHCFGREQ_EV£»
+ URRCINTRA_FACHCFGIND_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_CONTINUEREQ_EV£»
+
+ 61 2009.5.22 ËïÒÔÀ× 1)Ôö¼ÓGSMA¶¨Ê±Æ÷µÄʼþºÅ¶¨Òå
+ GSMA_PROCTIMER_EXPIRY_EV
+ GSMA_INACTTIMER_EXPIRY_EV
+
+ 62 2009.06.04 ʷѧºì 1)PDCP£URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£º
+ CPDCP_RELOCREJ_EV
+ CPDCP_RELOCCOMPIND_EV
+ CPDCP_RELOCFAILIND_EV
+ CPDCP_DLPDUSIZECHANGEREQ_EV
+ CPDCP_DLPDUSIZECHANGECNF_EV
+ CPDCP_ROHCTARGETMODEREQ_EV
+ 2)PDCP£URRC ÏûÏ¢ºÅ¶¨Òåɾ³ý£º
+ CPDCP_RELOCCOMPREQ_EV
+
+ 63 2009.06.22 ΤÓñÕä 1)ÐÂÔöMACUL->MACDLÏûÏ¢£º
+ CUMAC_NOTIFYDLPERIODREPORTREQ_EV
+ 2)ɾ³ýÒÔÏÂÏûÏ¢£º
+ CUMAC_MEASRELREQ_EV
+ CUMAC_MEASREPORTIND_EV
+ CUMAC_PERIODMEASDELNOTIFYREQ_EV
+ CUMAC_GETTVBOCMPIND_EV
+ 3)ÐÂÔöRRCÓëUMAC½Ó¿ÚÏûÏ¢£º
+ CUMAC_TRAFFICMEASREQ_EV
+ CUMAC_QUANLITYMEASREQ_EV
+ CUMAC_INTERNALMEASREQ_EV
+ CUMAC_TVMEASRELREQ_EV
+ CUMAC_QMEASRELREQ_EV
+ CUMAC_UEMEASRELREQ_EV
+ CUMAC_TVMEASRESUMEREQ_EV
+ CUMAC_TVMEASSUSPENDREQ_EV
+ CUMAC_DLMEASSUSPENDREQ_EV
+ CUMAC_DLMEASRESUMEREQ_EV
+ CUMAC_ADDTVMEASREPORTREQ_EV
+ CUMAC_ADDQMEASREPORTREQ_EV
+ CUMAC_ADDUEMEASREPORTREQ_EV
+
+65 2009.06.23 ÑîÔÊ 1)Ôö¼ÓGMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ GMM_TWSPN_EXPIRY_EV
+ GMM_TWCRS_EXPIRY_EV
+ GMM_TWTRG_EXPIRY_EV
+
+66 2009.06.24 ½ºè 1)ÐÞ¸ÄTEST_GVAR_XXXΪGVAR_XXX
+ 2)ÖØÐÂÕûÀíÁ˲âÊÔÏûϢʼþ¶¨Ò巶Χ
+ 3)Ôö¼ÓÁËNCBSÏà¹ØÏûÏ¢¶¨Ò壺£¨½ªéª£©
+ TEST_UCBSSCHEDCFG_UTRAN_EV
+ TEST_UCBSDATAREQ_UTRAN_EV
+ TEST_UCBSOUTPUTEND_UTRAN_EV
+ TEST_UCBSUMAC_TFSCFG_UTRAN_EV
+ TEST_UCBSUMAC_SFNINFO_UTRAN_EV
+ TEST_UURLCDATACNF_UTRAN_EV
+ TOOL_L1SIMU_CBSBLK_START_EV
+ TOOL_L1SIMU_CBSFSTBLK_REQ_EV
+ TOOL_L1SIMU_CBSOTHERBLK_REQ_EV
+
+67 2009.06.29 QIANJUN155488 1)Ôö¼ÓÓû§ÃæÐÅÁî¸ú×ÙαÏûÏ¢¶¨Òå
+ ATIPDI_DATAREQ_TRACE_EV
+ UPDI_DATAREQ_TRACE_EV
+ SN_DATA_REQ_TRACE
+ SN_UNITDATA_REQ_TRACE
+ LL_DATA_REQ_TRACE
+ LL_UNITDATA_REQ_TRACE
+ LLC_GET_NEXT_PDU_TRACE_EV
+ GMAC_GET_BLOCKS_TRACE_EV
+ GMAC_ACK_BLOCKS_TRACE_EV
+ PDCP_UPDATA_TRACE_EV
+ URLC_GETBO_TRACE_EV
+ URLC_SENDPDU_TRACE_EV
+ UMAC_TFCSEL_TRACE_EV
+ PH_MAC_DATA_IND_TRACE
+ PH_RLC_DATA_IND_TRACE
+ MAC_RLC_DATA_IND_TRACE
+ RLC_DATA_IND_TRACE
+ RLC_UNITDATA_IND_TRACE
+ LL_DATA_IND_TRACE
+ LL_UNITDATA_IND_TRACE
+ SN_DATA_IND_TRACE
+ SN_UNITDATA_IND_TRACE
+ UPDI_DATAIND_TRACE_EV
+ ATIPDI_DATAIND_TRACE_EV
+ UUMAC_DATAIND_TRACE_EV
+ PDCP_DOWNDATA_TRACE_EV
+ TAF_COUNTER_TRACE_EV
+ TAF_RLP_XID_ULFRAME_TRACE_EV
+ TAF_RLP_XID_DLFRAME_TRACE_EV
+ TAF_RLP_SABM_ULFRAME_TRACE_EV
+ TAF_RLP_SABM_DLFRAME_TRACE_EV
+ TAF_RLP_UA_ULFRAME_TRACE_EV
+ TAF_RLP_UA_DLFRAME_TRACE_EV
+ TAF_RLP_DISC_ULFRAME_TRACE_EV
+ TAF_RLP_DISC_DLFRAME_TRACE_EV
+ TAF_RLP_DM_ULFRAME_TRACE_EV
+ TAF_RLP_DM_DLFRAME_TRACE_EV
+ TAFL1G_DATA_IND_TRACE_EV
+ TAFL1G_DATA_REQ_TRACE_EV
+ TAF_FUNC_UURLCDATAIND_EV
+ TAF_FUNC_UURLCDATAREQ_EV
+68 2009.7.2 ½»¶ 1)Ϊ֧³ÖÖÐÒÆËæEÐÐATÃüÁÔö¼ÓÏÂÁÐÏûÏ¢£º
+ AP_UICC_PINENABLEQUERYREQ_EV
+ AP_UICC_PINENABLEQUERYCNF_EV
+ AP_UICC_PINSTATQUREYREQ_EV
+ AP_UICC_PINSTATQUREYCNF_EV
+ AP_UICC_CARDMODEREQ_EV
+ AP_UICC_CARDMODECNF_EV
+ AP_MMIA_SETPINAPPLREQ_EV
+ AP_MMIA_SETPINAPPLCNF_EV
+ AP_MMIA_PINAPPLREADREQ_EV
+ AP_MMIA_PINAPPLREADCNF_EV
+ AP_MMIA_CPINREQ_EV
+ AP_MMIA_CPINREADREQ_EV
+ AP_MMIA_CPINREADCNF_EV
+ AP_MMIA_CARDMODEREQ_EV
+ AP_MMIA_CARDMODECNF_EV
+ AP_MMIA_MODEREQ_EV
+ AP_MMIA_MODECNF_EV
+69 2009.7.15 ½ºè 1)Òƶ¯L1G_ST_EVENT·¶Î§µ½SIGTRACE_EVENT·¶Î§ÄÚ
+ 2)Ôö¼ÓGVAR_CBS_GETREQ_EV¡¢GVAR_CBS_GETCNF_EV
+70 2009.7.17 Áõµ¤ 1)Ôö¼ÓURRC-URLCµÄʼþºÅ:
+ CURLC_SETDATANOTIFYMODE_EV
+ CURLC_PCHULDATATRREQ_EV
+71 2009.7.21 ½»¶ 1)ɾ³ý£º
+ AP_MMIA_ZBDMDSETREQ_EV
+ AP_MMIA_ZBDMDQUERYREQ_EV
+ AP_MMIA_ZBDMDQUERYCNF_EV
+ 2)ÐÂÔö£º
+ AP_MMIA_ZACTSETREQ_EV
+ AP_MMIA_ZACTQUERYREQ_EV
+ AP_MMIA_ZACTQUERYCNF_EV
+ AP_MMIA_MODEQRYREQ_EV
+ AP_MMIA_MODEQRYCNF_EV
+ AP_MMIA_MODESETREQ_EV
+72 2009.7.23 ÍõÀò 1)Ôö¼Ó£¬UMCRÔÚ½øÈë·ÉÐÐģʽʱ£¬Í¨ÖªURRCA½øÈë¿ÕÏеÄÏûÏ¢£º
+ P_GSM_MEAS_TONULL_REQ_EV
+73 2009.7.28 ΤÓñÕä 1)Ö§³ÖÈý°æÐб꣬Ôö¼ÓURRCÄÚ²¿Ê¼þºÅURBC-UMCR: URRCINTRA_DRXCHGIND_EV
+ Ôö¼ÓUMCR-URRCAµÄʼþºÅ: P_GSM_MEAS_DRX_CHANGE_REQ_EV
+74 2009.7.28 ʷѧºì 1)Ôö¼ÓNPDCP_EVENT_BASE¡¢NPDCP_EVENT_END
+ 2)Ôö¼ÓNPDCPʼþºÅ£º
+ CPDCP_CONFIGREQ_UTRAN_EV
+ CPDCP_RELEASEREQ_UTRAN_EV
+ NPDCP_DATAREQ_UTRAN_EV
+ NPDCP_DATAIND_UTRAN_EV
+ TEST_NPDCP_DATAERRIND_UTRAN_EV
+ TEST_NPDCP_DATACNF_UTRAN_EV
+75 2009.8.11 ÍõÀò CC/SM/SS²¿·ÖÓëATIÓÅ»¯½Ó¿ÚÐÞ¸Ä
+ 1)Ôö¼ÓºÍÐÞ¸ÄCCÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ Ôö¼Ó£ºAP_MMIA_CCQUERYREQ_EV/AP_MMIA_RINGIND_EV/AP_MMIA_CRINGIND_EV/AP_MMIA_CCWAIND_EV
+ AP_MMIA_MOCALLSSNOTIFY_EV/AP_MMIA_MTCALLSSNOTIFY_EV/AP_MMIA_CCQUERYCNF_EV/AP_MMIA_CLIPIND_EV
+ AP_MMIA_CRIND_EV/AP_MMIA_CCSETREQ_EV/AP_MMIA_COLPIND_EV/MMIACC_CSTAQUERYREQ_EV
+ MMIACC_CSTASETREQ_EV/MMIACC_CSTAQUERYCNF_EV/AP_MMIA_MODTOMULTMEDIARSP_EV
+ AP_MMIA_MODTOMULTMEDIAIND_EV/MMIACC_MODTOMULTMEDIARSP_EV/MMIACC_MODTOMULTMEDIAIND_EV
+ ɾ³ý£ºAP_MMIA_CRLPSETREQ_EV/AP_MMIA_CRLPQUERYREQ_EV/AP_MMIA_CHSNSETREQ_EV/AP_MMIA_CHSNQUERYREQ_EV
+ AP_MMIA_ETBMSETREQ_EV/AP_MMIA_ETBMQUERYREQ_EV
+ AP_MMIA_CCSETREQ_EV/AP_MMIA_CCSETUPIND_EV/AP_MMIA_CCCOMMANDCNF_EV/AP_MMIA_SSNOTIFYIND_EV
+ AP_MMIA_CHSNQUERYCNF_EV/AP_MMIA_DSQUERYCNF_EV/AP_MMIA_ETBMQUERYCNF_EV/AP_MMIA_CRLPQUERYCNF_EV
+ AP_MMIA_CCCAUSEQUERYREQ_EV/AP_MMIA_CCCAUSEQUERYCNF_EV
+
+ 2)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£º AP_MMIA_SMQUERYREQ_EV¡¢AP_MMIA_SMHANDLEREQ_EV¡¢AP_MMIA_SMANSREQ_EV
+ AP_MMIA_SMPDPADDRREQ_EV¡¢AP_MMIA_SMNEGQOSREQ_EV¡¢AP_MMIA_SMMODEMMOREQ_EV¡¢
+ AP_MMIA_SMMODEMANSREQ_EV¡¢AP_MMIA_SMCAUSEREQ_EV¡¢AP_MMIA_SMCANCELREQ_EV¡¢
+ AP_MMIA_SMQUERYPDPINFOREQ_EV¡¢AP_MMIA_SMQUERYCNF_EV¡¢AP_MMIA_SMHANDLECNF_EV¡¢
+ AP_MMIA_SMANSCNF_EV¡¢AP_MMIA_SMPDPADDRCNF_EV¡¢AP_MMIA_SMNEGQOSCNF_EV¡¢
+ AP_MMIA_SMMODEMMOCNF_EV¡¢AP_MMIA_SMMODEMANSCNF_EV¡¢AP_MMIA_SMCAUSECNF_EV¡¢
+ AP_MMIA_SMMTDEACTIVATEIND_EV¡¢AP_MMIA_SML2PIND_EV¡¢AP_MMIA_SMQUERYPDPINFOCNF_EV
+ Ôö¼Ó£ºAP_MMIA_SMREADREQ_EV¡¢AP_MMIA_SMQUERYPDPSTATUSREQ_EV¡¢AP_MMIA_SMQUERYACTCIDREQ_EV¡¢
+ AP_MMIA_SMQUERYDEFCIDREQ_EV¡¢AP_MMIA_SMQUERYPDPADDRREQ_EV¡¢AP_MMIA_SMQUERYNEGQOSREQ_EV¡¢
+ AP_MMIA_SMQUERYNEGEQOSREQ_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV¡¢AP_MMIA_SMACTDEACTREQ_EV¡¢
+ AP_MMIA_SMMODREQ_EV¡¢AP_MMIA_SMMTACTANSREQ_EV¡¢AP_MMIA_SMIPPDPACTREQ_EV¡¢
+ AP_MMIA_SMOPENCHRSP_EV¡¢AP_MMIA_SMQUERYIDLECHRSP_EV¡¢AP_MMIA_SMGETPCORSP_EV¡¢
+ AP_MMIA_SMQUERYPDPSTATUSCNF_EV¡¢AP_MMIA_SMQUERYACTCIDCNF_EV¡¢AP_MMIA_SMQUERYDEFCIDCNF_EV¡¢
+ AP_MMIA_SMQUERYPDPADDRCNF_EV¡¢AP_MMIA_SMQUERYNEGQOSCNF_EV¡¢AP_MMIA_SMQUERYNEGEQOSCNF_EV¡¢
+ AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMACTDEACTCNF_EV¡¢AP_MMIA_SMMODCNF_EV¡¢
+ AP_MMIA_SMCGEVIND_EV¡¢AP_MMIA_SMIPPDPACTCNF_EV¡¢AP_MMIA_SMOPENCHIND_EV¡¢
+ AP_MMIA_SMCLOSECHIND_EV¡¢AP_MMIA_SMQUERYIDLECHIND_EV¡¢AP_MMIA_SMGETPCOIND_EV¡¢
+ AP_MMIA_SMCONNECTIND_EV¡¢AP_MMIA_SMNOCARRIERCNF_EV
+
+ 3)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£ºAP_MMIA_CAAPTESTREQ_EV/AP_MMIA_CFCSQUERYREQ_EV/AP_MMIA_CPPSEXEREQ_EV/AP_MMIA_CFCSTESTREQ_EV
+ AP_MMIA_CAAPQUERYREQ_EV/AP_MMIA_CPPSEXECNF_EV/AP_MMIA_CFCSQUERYCNF_EV/AP_MMIA_CFCSTESTCNF_EV
+ Ôö¼Ó£ºAP_MMIA_COLRQUERYREQ_EV/AP_MMIA_COLRQUERYCNF_EV
+ ÆÁ±ÎÔÝδʵÏÖ¹¦ÄܵÄʼþºÅ£ºAP_MMIA_CAEMLPPSETREQ_EV /AP_MMIA_CAEMLPPQUERYREQ_EV /AP_MMIA_CFCSSETREQ_EV
+ AP_MMIA_CAAPSETREQ_EV/AP_MMIA_CAEMLPPQUERYCNF_EV /AP_MMIA_CAAPQUERYCNF_EV
+ AP_MMIA_CAAPTESTCNF_EV
+
+ 4)Ôö¼ÓIMEI/IMSI²éѯºÍ֤ʵµÄÏûϢʼþºÅ AP_MMIAÖ®¼ä
+ AP_MMIA_QUERYIMSIREQ_EV/AP_MMIA_QUERYIMEIREQ_EV/AP_MMIA_QUERYIMSICNF_EV/AP_MMIA_QUERYIMEICNF_EV
+
+ 5)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯µÄʼþºÅ MMIASSÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ Ôö¼Ó:MMIASS_COLRREADREQ_EV/MMIASS_ABORTREQ_EV/MMIASS_COMMONCNF_EV/SS_WAIT_TIMER_EXPIRY_EV
+ MMIASS_CUSDMTIND_EV
+
+ ɾ³ý:MMIASS_CAEMLPPSETREQ_EV/MMIASS_CAEMLPPREADREQ_EV/MMIASS_CPWDSETCNF_EV/MMIASS_CCFCSETCNF_EV
+ MMIASS_CCWASETCNF_EV/MMIASS_CAEMLPPSETCNF_EV/MMIASS_CAEMLPPREADCNF_EV/MMIASS_FORWARDCHECK_IND_EV
+ SS_T5000_EXPIRY_EV/MMIASS_CUSDUNSCNF_EV
+
+ 6)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯µÄʼþºÅ MMIASMÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ ɾ³ý:
+ MMIASM_PDPSTATUSREQ_EV¡¢MMIASM_NEGQOSREQ_EV¡¢MMIASM_PDPADDRREQ_EV¡¢
+ MMIASM_CAUSEREQ_EV¡¢MMIASM_PDPACTREJ_EV¡¢MMIASM_QUERYPDPINFOREQ_EV¡¢
+ MMIASM_PDPDEACTIVATEIND_EV¡¢MMIASM_PDPSTATUSCNF_EV¡¢MMIASM_NEGQOSCNF_EV¡¢
+ MMIASM_PDPADDRCNF_EV¡¢MMIASM_CAUSECNF_EV¡¢MMIASM_QUERYPDPINFOCNF_EV
+ SM_ATHRELEASE_EXPIRY_EV¡¢AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV
+ Ôö¼Ó:
+ MMIASM_QUERYNEGQOSREQ_EV¡¢MMIASM_QUERYNEGEQOSREQ_EV¡¢MMIASM_QUERYACTCIDREQ_EV¡¢
+ MMIASM_QUERYPDPSTATUSREQ_EV¡¢MMIASM_QUERYPDPADDRREQ_EV¡¢MMIASM_QUERYPDPCAUSEREQ_EV¡¢
+ MMIASM_MTACTANSREQ_EV¡¢MMIASM_IPPDPACTREQ_EV¡¢MMIASM_OPENCHRSP_EV¡¢
+ MMIASM_QUERYIDLECHRSP_EV¡¢MMIASM_GETPCORSP_EV¡¢MMIASM_QUERYNEGQOSCNF_EV¡¢
+ MMIASM_QUERYNEGEQOSCNF_EV¡¢MMIASM_QUERYACTCIDCNF_EV¡¢MMIASM_QUERYPDPSTATUSCNF_EV¡¢
+ MMIASM_QUERYPDPADDRCNF_EV¡¢MMIASM_QUERYPDPCAUSECNF_EV¡¢MMIASM_CGEVIND_EV¡¢
+ MMIASM_IPPDPACTCNF_EV¡¢MMIASM_OPENCHIND_EV¡¢MMIASM_CLOSECHIND_EV¡¢
+ MMIASM_QUERYIDLECHIND_EV¡¢MMIASM_GETPCOIND_EV¡¢MMIASM_COMMONCNF_EV¡¢
+ MMIASM_CONNECTIND_EV¡¢MMIASM_NOCARRIERCNF_EV
+ SM_AUTOANSMTACT_EXPIRY_EV
+ 7)Ôö¼ÓAP_MMIA_CAUSEQUERYREQ_EV, AP_MMIA_CAUSEQUERYCNF_EV
+ ɾ³ýAP_MMIA_SMSABORTMOREQ_EV/AP_MMIA_ABORTSEARCHPLMNREQ_EV
+
+76 2009.9.10 ºÎ½¨Î° 1)Ôö¼ÓLTEÖÆʽÏÂÏà¹ØµÄʼþºÅ
+ ½»¶ 2)½«AP_MMIA_EVENT_UICC_ENDºêÖµÔö¼Ó1
+
+77 2009.9.16 ÓÈ±ó ½«SIG_CODE.HÖÐÔÀ´²¿·ÖSDLÏûÏ¢£¨ÕâЩÏûÏ¢µÄÔ´ºÍÄ¿Ç°Ä£¿é¶¼¸ÄΪÁËÆÕͨÈÎÎñ£©µÄ¶¨Ò壬¸ÄΪÆÕͨÈÎÎñÏûÏ¢µÄ¶¨Òå
+
+78 2009.9.27 ÍõС½ø ΪʵÏÖ´æ´¢¹ÜÀí¹¦ÄÜÔö¼ÓÈçÏÂÏûÏ¢:
+ AP_MMIA_SMSCPMSTESTREQ_EV,AP_MMIA_SMSZMENAREQ_EV,AP_MMIA_SMSCPMSTESTCNF_EV,
+ AP_MMIA_CPBSTESTREQ_EV,AP_MMIA_CPBRSETENDCNF_EV,AP_MMIA_CPBSTESTCNF_EV,
+ AP_MMIA_PBPREFMSGSTOREQ_EV,AP_MMIA_PBPREFMSGSTOTESTREQ_EV,AP_MMIA_PBTPMRUPDATEREQ_EV,
+ AP_MMIA_PBMEMCAPAREQ_EV,AP_MMIA_PBMTPARAIND_EV,AP_MMIA_PBEMERNUMLISTIND_EV,
+ AP_MMIA_PBSTOSETREQ_EV,AP_MMIA_PBSTOTESTREQ_EV,AP_MMIA_PBFINDINDEXENDCNF_EV,
+ AP_MMIA_PBPREFMSGSTOCNF_EV,AP_MMIA_PBPREFMSGSTOTESTCNF_EV,AP_MMIA_PBCOMMONCNF_EV ,
+ AP_MMIA_PBINITCMPLTIND_EV,AP_MMIA_ZPBICIND_EV,
+
+79 2009.9.28 ΤÓñÕä ±ÜÃâ3GÖ÷ģʽÏ£¬¸ø³öGAPºó£¬ÓÖ·¢ÆðËæ»ú½ÓÈë¹ý³Ì¶øµ¼ÖµÄÉäƵͬÇÀ¶øÔö¼ÓµÄÏûÏ¢:
+ CUMAC_URRCAMEASSUSPENDREQ_EV
+ CUMAC_URRCAMEASRESUMEREQ_EV
+ P_GSM_RACH_ACTIVE_CNF_EV
+80 2009.9.28 ½ª²¨ Ôö¼ÓUSIRÖÜÆÚÐÔ½ÓÊÕϵͳÐÅÏ¢µÄ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ:
+ USIR_TIMER_R_EXPIRY_EV
+
+81 2009.9.28 ³Â¹â»ª 1)AP-MMIA SMSÏûÏ¢ºÅ¶¨Ò壬Ôö¼Ó
+ AP_MMIA_CPMSTESTREQ_EV
+ AP_MMIA_CPMSTESTCNF_EV
+ AP_MMIA_SMSZPBICIND_EV
+82 2009.9.28 ½¯Õ×´º 1)Ôö¼ÓUMM/GSMA½Ó¿ÚÏûÏ¢UMMAS_TBFRELEASEIND_EV
+ 2)Ôö¼ÓUMM¶¨Ê±Æ÷ÏûÏ¢UMM_TLIST_EXPIRY_EV
+
+83 2009.9.28 ½»¶ 1¡¢Ôö¼Ó»ñÈ¡PSDEVÊý¾ÝʼþºÅ
+ GVAR_UICC_DEV_GETREQ_EV
+ GVAR_UICC_DEV_GETCNF_EV
+ 2¡¢Ôö¼Ó¹Ø¿¨È·ÈÏÏûÏ¢£ºAP_UICC_PWROFFCNF_EV
+ 3¡¢È¡Ïû¹Ø¿¨¶¨Ê±Æ÷ÏûÏ¢£ºUICC_TIMER_EXPIRY_EV
+84 2009.9.29 ½»¶ 1¡¢Ôö¼ÓPBʼþºÅ
+ AP_MMIA_PBSTOTESTCNF_EV
+85 2009.9.30 ʯ×ÚÀ¤ 1¡¢AP-MMIA¼äʼþºÅÒÑʹÓÃÁË510¸ö£¬ÐèÔö¼ÓAP_MMIA_EVENT_BASEµÄ¿Õ¼ä£¬´Ó500£>600
+
+86 2009.10.19 ÑîÔÊ 1¡¢ Ôö¼ÓMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺 MM_TWRRR_EXPIRY_EV
+87 2009.10.27 Ç®¿¡ 1)Ϊ֧³ÖEGPRS,Ôö¼Ó2GÍø²àÄ£ÄâʼþºÅNGMAC_NGRLC_EPDAN_IND_EV,
+ NGRLC_NGRLC_PUAN_REQ_EV,NGRLC_FILL_DATA_QUEUE_REQ_EV,L1SIMU_NGRLC_DATA_IND_EV
+88 2009.10.27 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+89 2009.11.09 ÑîÔÊ 1¡¢Ôö¼ÓÁËMMIAºÍUMMÖ®¼äÔö¼ÓSYSCONFIGÏà¹ØÏûÏ¢ºê¶¨Ò壺
+ MMIAUMM_SYSCONFIGREQ_EV¡¢MMIAUMM_COMMONCNF_EV£»
+ 2¡¢Ôö¼ÓÁËUMMºÍASÖ®¼äϵͳÅäÖÃÏûÏ¢ºê¶¨Ò壺
+ UMMAS_UPDATESYSCONFIGREQ_EV ¡£
+90 2009.11.12 ½ª²¨/Ëﳤ½ ×Óϵͳ·½°¸ÐÞ¸Ä
+ 1.USIR_TBCCHMOD_EXPIRY_EV,UCSR_TBARGSMCELL_EXPIRY_EV
+ 2.URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨ÒåÖÐÔö¼ÓÏûÏ¢ºÅ:
+ URRC_FUNC_RELSCCPCHSTOPMACREQ_EV
+ URRC_FUNC_RESUMEFACHCFGREQ_EV
+91 2009.11.17 ³Â¹â»ª
+ MMIA£SMSÏûÏ¢ºÅ¶¨ÒåÖÐÐÂÔö£ºMMIASMS_COMMONCNF_EV
+
+92 2009.11.17 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+93 2009.11.18 ÑîÎÄÇ¿ Ôö¼ÓEDGEÖ§³ÖµÄÏà¹ØʼþºÅ:
+ TOOL_NGRLC_MODE_CFG_REQ_EV£¬NGRLC_TOOL_UL_DATABLOCK_IND_EV £¬
+ TOOL_NGRLC_DUMMYBLOCK_REQ_EV £¬DOWNLINK_DUMMY_BLOCK_REQ_EV£¬
+ TOOL_NGRLC_DOWNLINKBLOCK_REQ_EV
+94 2009.12.14 ÑîÔÊ Ôö¼Ó¼à¿ØÑ°ºôµÄ¶¨Ê±Æ÷ÏûÏ¢ºÅ:(CQNJ00137720)
+ GMM_TPAGE_EXPIRY_EV, MM_TWPGR_EXPIRY_EV;
+
+95 2009.12.16 ÍõС½ø 1)Ôö¼ÓËæEÐÐÏà¹ØʼþºÅ:
+ MMIACC_CLOSEVOICECHNLIND_EV,MMIACC_OPENVOICECHNLIND_EV,AP_MMIA_PBSFINDINDEXCNF_EV
+ AP_MMIA_PBSFINDINDEXENDCNF_EV,AP_MMIA_PBSEDITCNF_EV,AP_MMIA_PBSCPBRTESTCNF_EV,
+ AP_MMIA_PBSCPBWTESTCNF_EV,AP_MMIA_PBCNUM_CNF,AP_MMIA_PBCLCKSTATUSCNF_EV
+ AP_MMIA_PBSFINDINDEXREQ_EV,AP_MMIA_PBSEDITREQ_EV,AP_MMIA_PBCNUM_REQ
+ AP_MMIA_PBCLCKSETREQ_EV,AP_MMIA_PBSCPBRTESTREQ_EV,AP_MMIA_PBSCPBWTESTREQ_EV
+ AP_MMIA_PBUICCOKIND_EV,AP_MMIA_SCPBRSETCNF_EV ,AP_MMIA_SCPBRSETENDCNF_EV
+ AP_MMIA_SCPBRTESTCNF_EV,AP_MMIA_SCPBWTESTCNF_EV ,AP_MMIA_CNUMCNF_EV
+ AP_MMIA_SCPBRSETREQ_EV ,AP_MMIA_SCPBRTESTREQ_EV,AP_MMIA_SCPBWTESTREQ_EV
+ AP_MMIA_SCPBWSETREQ_EV ,AP_MMIA_CNUMREQ_EV ,AP_UICC_CRSM_CNF_EV
+ AP_UICC_COMMONCNF_EV,
+ 2)ÐÞ¸ÄPB,UICCʼþºÅ·¶Î§Öµ:
+ AP_MMIA_PB_RSP_EVENT,AP_MMIA_EVENT_PB_END
+ AP_MMIA_EVENT_UICC_END,AP_UICC_EVENT_END
+
+96 2009.12.07 ³ÂÎÄ Ôö¼Ó¶ÁдIMEIµÄʼþºÅTEST_SET_NV_DATA_IMEI_EV
+ Ôö¼ÓCRSMÃüÁîʼþºÅAP_UICC_CRSM_REQ_EV
+ Ôö¼ÓUICCÄ£¿éµÄͨÓÃʼþºÅ AP_UICC_COMMONCNF_EV
+
+97 2010.01.05 ΤÓñÕä Ôö¼ÓURRCINTRA_GETSERVCELLINFO_EV,ÒÔ±ãÔÚMSGTRACEÖÐÏÔʾʵʱСÇøÐÅÏ¢
+
+98 2010.01.08 Ëïºóɽ Ôö¼ÓPDIµãµÆºÍÏúÁ¿Í³¼Æ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ PDI_SWITCHLEDTIMER_EXPIRY_EV£¬
+ PDI_WAITDNSACKTIMER_EXPIRY_EV£¬
+ PDI_WAITZSSACKTIMER_EXPIRY_EV£¬
+
+99 2010.01.09 ÍõС½ø 1)Ôö¼ÓÏúÁ¿Í³¼ÆÏà¹ØʼþºÅ:
+ AP_MMIA_SELL_STAT_SWITCHSETREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYREQ_EV,AP_MMIA_SELL_STAT_UDPINFOQUERYREQ_EV
+ AP_MMIA_SELL_STAT_TESTSENDREQ_EV,AP_MMIA_SELL_STAT_DOMAINSETREQ_EV,AP_MMIA_SELL_STAT_DOMAINQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_CRCSETREQ_EV,AP_MMIA_SELL_STAT_CRCQUERYREQ_EV,AP_MMIA_SELL_STAT_DEBUGSETREQ_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYREQ_EV,AP_MMIA_SELL_STAT_PORTSETREQ_EV,AP_MMIA_SELL_STAT_PORTQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_TRITYPEQUERYREQ_EV,AP_MMIA_SELL_STAT_DNSCNTQUERYREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_UDPINFOQUERYCNF_EV,AP_MMIA_SELL_STAT_DOMAINQUERYCNF_EV,AP_MMIA_SELL_STAT_CRCQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYCNF_EV,AP_MMIA_SELL_STAT_PORTQUERYCNF_EV,AP_MMIA_SELL_STAT_TRITYPEQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DNSCNTQUERYCNF_EV,MMIASM_CIDDEACTIND_EV,MMIAPDI_SELLSTAT_STARTSENDPACKETIND_EV,
+ MMIAPDI_SELLSTAT_ABORTIND_EV,MMIA_SELLSTAT_ONEPDP_EXPIRY_EV,MMIA_SELLSTAT_SUMPDP_EXPIRY_EV,
+ MMIA_SELLSTAT_REG_EXPIRY_EV
+ ÐÞ¸ÄAP_MMIA_UICC_RSP_EVENT£¬AP_MMIA_EM_RSP_EVENT
+ 2) Ôö¼ÓZIMGE,ZGIIDFʼþºÅ
+ AP_MMIA_ZIMGREQ_EV,AP_MMIA_ZGIIDFREQ_EV,AP_MMIA_ZIMGCNF_EV,AP_MMIA_ZGIIDFCNF_EV
+ 3)´æ´¢ÁоÙÏûÏ¢µÄ֪ͨÏûÏ¢
+ AP_MMIA_PBCPBRIND_EV,AP_MMIA_PBCPBFIND_EV,AP_MMIA_PBSCPBRIND_EV,AP_MMIA_PBCMGLIND_EV
+
+100 2010.01.21 ʯ×ÚÀ¤ ½«UMCR-UPHY¸ÄΪUMACÉÏÏÂÐÐÁ½¶Î£¬Í¬Ê±½«ÏÂÁÐÏûÏ¢IDµÄ»ùµØÖ·¶¨Òå´ÓUMCR-UPHY¸ÄΪUMAC_DL-UPHY£º
+ P_QUALITY_MEAS_REQ_EV
+ P_UE_INTERNAL_MEAS_REQ_EV
+ P_QUALITY_MEAS_IND_EV
+ P_UE_INTERNAL_MEAS_IND_EV
+
+101 2010.02.05 ³ÂÎÄ Ôö¼ÓUICCʼþºÅ
+ UICC_CARDDETECT_EXPIRY_EV
+ AP_UICC_UICCUNSYNCIND_EV
+
+102 2010.02.20 ÕÅÅô³Ì Ôö¼ÓL1TʼþºÅ
+ P_ABORT_FREQ_SCAN_CNF_EV,P_ABORT_CELL_SEARCH_CNF_EV,P_BCH_RELEASE_CNF_EV,
+ P_CAMPON_A_CELL_CNF_EV,P_CHECK_RF_IND_EV£¨´¦ÀíÉäƵ³åÍ»£©,P_DPCH_CFG_FINAL_EV£¨¸ÃÏûÏ¢²»·¢µ½DPRAM£©,
+ P_DPCH_REL_CNF_EV,P_REL_SCCPCH_CNF_EV,P_STOP_PAGING_CNF_EV,P_STOP_CBS_CNF_EV
+ P_REL_HSDPA_CNF_EV,P_REL_HSUPA_CNF_EV,P_ACTIVE_IND_EV£¨´¦Àí¼¤»îʱ¼äµ½£©
+ P_RACH_PRCEDURE_CNF_EV,P_ERUCCH_PRCEDURE_CNF_EV
+
+103 2010.02.20 YANGYUN ÐÞ¸ÄÖÆʽ¼äÖØÑ¡£¬Ìí¼ÓʼþºÅ£º
+ UMMAS_CELLRESSTARTIND_EV
+
+104 2010.03.09 ʯ×ÚÀ¤ ÐÞ¸ÄL1TµÄÈýÌõÏûÏ¢ID£º
+ P_DPCH_CFG_FINAL_EV¸ÄΪP_L1_RESOURCE_CFG_FINAL_EV
+ P_RACH_PRCEDURE_CNF_EV¸ÄΪP_RACH_PROCEDURE_CNF_EV
+ P_ERUCCH_PRCEDURE_CNF_EV¸ÄΪP_ERUCCH_PROCEDURE_CNF_EV
+
+101 2010 .03.11 ׿Խ/ºÎ« Ôö¼ÓÏûÏ¢£º
+ URRCINTRA_GETNCELLINFO_EV
+ MSGTRACEPS_CELLDISPLAYREQ_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+
+102 2010 .03.12 ËïȪ Ôö¼ÓÏûÏ¢£º
+ MMIASS_USSDCANCELREQ_EV
+
+103 2010 .03.17 ³Â¹â»ª Ôö¼ÓSMS¶¨Ê±Æ÷ʼþºÅ£º
+ SMS_TWSI_EXPIRY_EV
+
+104 2010.3.30 ×ÞÑÞ Ôö¼Ó2GÏÂTCHÊÍ·ÅʱGSMAÉϱ¨¸øCCµÄÏûÏ¢
+ GMMAS_CCTCHRELIND_GSM_EV
+
+105 2010 .04.04 ½ª²¨ ÐÞ¸ÄÁбí¹ý³Ìʱ³¤Ïà¹ØÐÞ¸Ä
+ ½«PS_UMMAS_ABORTPLMNREQ_EV ÐÞ¸ÄΪ UMMAS_STOPPLMNLISTREQ_EV
+ ½«UMMAS_ABORTCNF_EV ÐÞ¸ÄΪ UMMAS_ABORTHPPLMNCNF_EV
+ Ôö¼Ó³¬Ê±ÏûÏ¢: UMM_TPLMNLIST_EXPIRY_EV
+
+106 2010 .04.06 ½ª²¨ Ôö¼ÓURRCÄÚ²¿Ê¼þºÅ£º
+ URRCINTRA_SENDBUFESTREQ_EV
+ URRCINTRA_ABORTCCOREQ_EV
+
+107 2010 .04.13 ½ª²¨ Ð޸ı»BAR´¦ÀíÏà¹Ø£¬Ôö¼ÓÁ½¸öʼþºÅ
+ URRCINTRA_BARRESUMEIND_EV
+ UCSR_TBARFREQ_EXPIRY_EV
+
+108 2010 .04.23 ½»¶ ÐÞ¸ÄSUBMODE,Ôö¼ÓʼþºÅ
+ MMIAAS_SUBMODEIND_EV
+
+ 109 2010 .04.24 ËÕá° Ôö¼ÓUMAC-ULÏòUMAC-DL֪ͨÏÂÐÐÅäÖõı仯
+ CUMAC_ACTDLCFG_EV
+
+110 2010.04.29 ½¯Õ×´º Ôö¼ÓUMM¶ÔMMIAËÑÍøÇëÇóµÄ»Ø¸´£¬Ê¼þºÅ
+ MMIAUMM_SEARCHPLMNCNF_EV
+
+111 2010.04.30 ½¯Õ×´º ɾ³ý UMM_TPROC_EXPIRY_EV
+ Ôö¼Ó UMM_TUICCINIT_EXPIRY_EV
+ UMM_TCAMP_EXPIRY_EV
+ UMM_TDETACH_EXPIRY_EV
+
+ 112 2010 .05.04 ʯ×ÚÀ¤ Ôö¼ÓR7Ö§³Ö
+
+ 113 2010.05.14 Éòº® Ôö¼ÓGSMA֪ͨUCSR2GפÁô³É¹¦µÄָʾ
+ URRCGRR_GSMCAMPSUCCIND_EV
+
+ 114 2010.05.20 ʯ×ÚÀ¤ UICCÏûÏ¢ÒѾ³¬³öÔÓеÄÇø¼ä£¬Õ¼ÓÃÁËÆäËûÄ£¿éµÄÏûÏ¢Çø¼ä£¬µ÷ÕûUICCµÄÏûÏ¢Çø¼ä
+
+115 2010.05.22 ÑîÔÊ Ôö¼ÓCS¡¢PS¸½×Å״̬²éѯÏûÏ¢
+ MMIAUMM_CGATTQUERYREQ_EV
+ MMIAUMM_ZATTQUERYREQ_EV
+ MMIAUMM_CGATTQUERYCNF_EV
+ MMIAUMM_ZATTQUERYCNF_EV
+
+116 2010.05.25 ÑîÔÊ Ôö¼ÓUMM֪ͨGMMÖÆʽ¸ü¸Ä³É¹¦ÏûÏ¢
+ UMM_RATCHNIND_EV
+
+ 117 2010 .05.24 ÍõС½ø Ôö¼ÓAP_MMIA_ESMTFADTESTREQ_EV
+ AP_MMIA_ESMTFADTESTCNF_EV
+
+ 118 2010 .05.29 ³ÂÎÄ Ôö¼Ó£º
+ AP_UICC_ACTIVEORDEACTIVEFILEREQ_EV¡¢AP_UICC_ACTIVEORDEACTIVEFILECNF_EV
+
+119 2010.06.07 ʯ×ÚÀ¤ ÐÞ¸ÄÉϱ¨MSGTRACE·þÎñСÇøºÍÁÚÇøµÄ·½Ê½
+ Ôö¼Ó£ºMSGTRACEPS_SCELLINFOIND_EV£¨·þÎñСÇøÐÅÏ¢£©¡¢MSGTRACEPS_NCELLINFOIND_EV£¨ÁÚÇøÐÅÏ¢£©
+ ɾ³ýÔÓеÄÏûÏ¢£º
+ URRCINTRA_GETSERVCELLINFO_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+ URRCINTRA_GETNCELLINFO_EV
+
+120 2010.06.08 ÍõС½ø ΪUSATÃüÁîÔÚ90 00ʱÔö¼ÓÖ÷¶¯Éϱ¨ÏûÏ¢
+ AP_UICC_NOPROCNOTIFYIND_EV, AP_MMIA_USAT_NOPROCNOTIFYIND_EV
+
+121 2010.06.08 ʯ×ÚÀ¤ ½«RRAT_RXSTAT_IND¡¢RRMI_RXSTAT_IND¡¢RR_EM_HO_INFO_IND¡¢RR_EM_CELL_INFO_IND
+ ÒƵ½PSEVENT.HÖÐÈ¥
+121 2010.07.02 ÍõÀò£¨Ó¦¸ßÏè148604ÒªÇóÐ޸ģ© Ôö¼Ó
+ P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV¡¢
+
+122 2010.07.08 ʯ×ÚÀ¤ ½«P_RESEL_GSMCELL_START_REQ_EV¡¢P_RESEL_GSMCELL_START_CNF_EVÌ滻Ϊ
+ P_TD_RF_REL_REQ_EV¡¢P_TD_RF_REL_CNF_EV
+ ½«P_RESEL_GSMCELL_SUCC_REQ_EV¡¢P_RESEL_GSMCELL_SUCC_CNF_EVºÍ
+ P_TD_CLOSE_REQ_EV¡¢P_TD_CLOSE_IND_EVÌ滻Ϊ
+ P_TD_RESET_REQ_EV¡¢P_TD_RESET_CNF_EV
+ ÐÂÔöP_TD_RF_RESUME_REQ¡¢P_ABORT_GSM_GAP_CNF_EV
+
+123 2010.07.08 ¸ßÏè È¥³ýÏûÏ¢¶¨ÒåP_INTER_FREQ_BLIND_MEAS_IND_EV
+
+124 2010 .07.10 ¹Ë±¦³É Ôö¼Ó£º
+ SM_PDCP_HCMODIND_EV
+
+125 2010.07.10 ΤÓñÕä Ôö¼ÓRRCÄÚ²¿Ê¼þºÅ£ºURRCINTRA_CHANGECAMPONTYPE_EV CSR֪ͨ
+ MCR ÈÎÒâפÁôתºÏÊÊפÁô»òÕßÊǺÏÊÊתÈÎÒâ
+
+126 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ MMIAESM_ABORTREQ_EV
+
+127 2010.07.10 ÕÔÕñ»Ôɾ³ýÏûÏ¢MMIAESM_MTEPSBEARERACT_CNF_EV
+
+128 2010.07.10 ÍõС½øÔö¼Ó £º
+ AP_UICC_EFSTATUSQUERYREQ_EV, AP_UICC_EFSTATUSMODIFYREQ_EV
+ AP_UICC_EFSTATUSQUERYCNF_EV,AP_UICC_EFSTATUSMODIFYCNF_EV
+
+129 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ AP_MMIA_PBCHGINDEXIND_EV
+ AP_MMIA_CHGINDEXIND_EV
+
+130 2010.07.10 ÕÔÕñ»ÔΪ×Û²âÔö¼ÓÏûÏ¢AP_MMIA_AUTOSTARTREQ_EV
+
+131 2010.08.18 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢AP_MMIA_CGEQOSSETREQ_EV¡¢AP_MMIA_CGEQOSQUERYREQ_EV
+ AP_MMIA_CGEQOSQUERYCNF_EV¡¢AP_MMIA_CGEQOSRDPREQ_EV
+ AP_MMIA_CGEQOSRDPCNF_EV¡¢MMIAESM_QUERYPDPADDRCNF_EV
+ ɾ³ýÏûÏ¢MMIAESM_ABORTREQ_EV¡¢AP_MMIA_ESMQOSQUERYREQ_EVºÍAP_MMIA_ESMQOSQUERYCNF_EV
+ µ÷ÕûMMIAºÍATIÏûÏ¢Çø¼ä
+
+132 2010.08.26 ÑîÔÊ Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATELTEACT_EV¡¢MMIAUMM_SETLTEACT_REQ_EV
+
+133 2010.09.13 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_MMIA_ZEACTSETREQ_EV¡¢AP_MMIA_ZEACTREADREQ_EVºÍ
+ AP_MMIA_ZEACTREADCNF_EV
+
+134 2010.09.14 ³Â¹â»ª Ôö¼ÓÏûÏ¢GMMAS_SAPI3RELIND_EV
+
+135 2010.09.25 ÍõС½ø ½â¾ö֪ͨSTMËø¿¨ºÍ½âËø£¬Ôö¼ÓÏûÏ¢AP_UICC_CARDLOCKSTATUSIND_EV
+
+136 2010.09.27 ÀîÎľ² Ôö¼Ó¡¢µ÷ÕûLTEÏà¹ØÏûÏ¢
+
+137 2010.10.18 Ëﳤ½ È¥µôÏûÏ¢ºÅ£ºP_CBS_NODRX_REQ_EV¡¢ P_CBS_DRX_REQ_EVµÄ¶¨Ò壻
+ ºóÃæµÄÏûÏ¢µÄʼþºÅͬʱǰÒÆ£¬ÓУºP_ADD_MODIFY_CBS_REQ_EV¡¢P_STOP_CBS_REQ_EV¡¢P_L1_RESOURCE_CFG_FINAL_EV¡¢
+ P_ADD_HSUPA_REQ_EV¡¢P_REL_HSUPA_REQ_EV¡¢P_PLCCH_ADD_MODIFY_REQ_EV
+
+137 2010.10.28 ΤÓñÕä Ôö¼ÓÏûÏ¢UMCR_TBSIC_EXPIRY_EVÖ§³ÖTD϶ÔGSMСÇøͬ²½ÐÅÏ¢µÄÓÐЧÆÚά»¤
+138 2010.10.29 ÁõÒí Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATESCANUEBANDFG_EV¡¢UMMAS_SCANUEBANDIND_EV
+ ɾ³ýÏûÏ¢£ºUCSR_TFREQSCAN_EXPIRY_EV
+
+139 2010.11.05 YANGYUN Ôö¼ÓUMM_CELLNOCHANGEIND_EV
+
+140 2010.11.15 YANGYUN Ôö¼Ó CM_RRCRELIND_EVÏûÏ¢
+
+141 2010.11.29 ÀîÎľ² ÐÞ¸ÄESM_EPDCP_EVENT_BASEµÄºê¶¨Òå
+
+142 2010.11.30 ÍõС½ø ½â¾ö¿¨³õʼ»¯¹ý³ÌÖйػú»ØÏÔ´íÎóÎÊÌ⣬Ôö¼ÓÏûÏ¢ AP_UICC_PWROFFIND_EV
+ PSDEVÐ޸ķ½°¸£¬Ôö¼ÓÏûÏ¢ AP_UICC_WRITEITEMIND_EV,AP_UICC_UPDATEITEMREQ_EV,AP_UICC_UPDATEITEMCNF_EV
+
+143 2010.12.1 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢GVAR_ATMEM_DEV_GETREQ_EV¡¢GVAR_ATMEM_DEV_GETCNF_EV¡¢GVAR_NV_DEV_GETREQ_EV¡¢
+ GVAR_NV_DEV_GETCNF_EV
+
+144 2010.12.15 ʷѧºì ɾ³ýROHCµÄ¶¨Ê±Æ÷ÏûÏ¢ROHC_FO2IRTIMER_EXPIRY_EV¡¢ROHC_SO2IRTIMER_EXPIRY_EV£¬
+ Ôö¼ÓÒ»¸öÓÉSO¡¢FOµ½IRµÄ¶¨Ê±Æ÷ÏûÏ¢£ºROHC_IRTIMER_EXPIRY_EV
+
+145 2010.12.30 Ëﳤ½ µ¥¶ÀµÄСÇø¸üйý³Ì£¬ÊÕµ½Á½ÌõTI²»Í¬µÄCUCÏûÏ¢µÄ´¦Àí£¬Ðèɾ³ý£º
+ URRCINTRA_ABORTCFGREQ_EV
+
+146 2010.12.31 ׿±Ø²¨ CQNJ00240340 PSEVENT.HÖÐÓÐЩʼþºÅ¶¨ÒåËæ×Å°æ±¾µÄÑݽøÒѾ²»ÔÙʹÓÃ
+
+147 2010.12.31 ÍõС½ø ΪÔö¼Ó¿¨SEARCH¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢ AP_UICC_PREPERSONRECSEARCHREQ_EV,AP_UICC_PREPERSNRECSRCHCNF_EV
+
+148 2011.1.28 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢MMIASM_DISCONNECTREQ_EV¡¢AP_MMIA_DISCONNECTREQ_EV
+
+149 2011.1.30 ׿±Ø²¨ EC 614000686090 ½«MMIA£SMÏûÏ¢ºÅ¶¨Òå°´ÊÇ·ñ
+ ¶ÔÓ¦ATÃüÁî·ÖÀ࣬µ÷ÕûMMIASM_ABORTREQ_EVµÈ3ÌõÏûÏ¢µÄÈ¡Öµ
+150 2011.2.11 ÍõС½ø Ôö¼ÓÏûÏ¢AP_UICC_VERIFYPIN2REQ_EV£¬AP_UICC_VERIFYPIN2CNF_EV
+
+151 2011.01.25 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢
+ AP_MMIA_CAOCSETREQ_EV ¡¢AP_MMIA_CAOCQRYREQ_EV¡¢AP_MMIA_CACMQRYREQ_EV¡¢AP_MMIA_CAMMQRYREQ_EV
+ AP_MMIA_CPUCQRYREQ_EV¡¢AP_MMIA_CCWEQRYREQ_EV¡¢AP_MMIA_CACMSETREQ_EV¡¢AP_MMIA_CAMMSETREQ_EV
+ AP_MMIA_CPUCSETREQ_EV¡¢AP_MMIA_CCWESETREQ_EV¡¢AP_MMIA_CAOCSETCNF_EV¡¢AP_MMIA_CAOCQRYCNF_EV
+ AP_MMIA_CACMQRYCNF_EV¡¢AP_MMIA_CAMMQRYCNF_EV¡¢AP_MMIA_CPUCQRYCNF_EV¡¢AP_MMIA_CCWEQRYCNF_EV
+ AP_MMIA_CCCMIND_EV¡¢AP_MMIA_CCWVIND_EV¡¢MMIACC_CCMQUERYREQ_EV¡¢MMIACC_CCMQUERYCNF_EV
+ MMIACC_CCWVIND_EV¡¢MMIACC_NOTIFYAOCTIMERIND_EV
+
+152 2011.03.01 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_UICC_ZPUKREQ_EV¡¢AP_MMIA_ZPUKREQ_EV
+
+153 2011.3.2 ÍõС½ø Ôö¼Ó¼Æ·Ñ¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢AP_UICC_INCREASEACMFAILIND_EV£¬
+ AP_UICC_INCREASEREQ_EV£¬AP_UICC_RESETACMREQ_EV
+ ¼Æ·Ñ¹¦ÄÜYUZHIMING²¹³ä CC_TACMUPD_EXPIRY_EV ,CC_TCDUR_EXPIRY_EV
+
+154 2011.3.10 ZHANGCHONG ͬ²½LTEÐÞ¸Ä
+
+155 2011.3.16 ʯ×ÚÀ¤ ÃüÃûÐÞ¸Ä
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼ÓGSM PS HOÏûÏ¢id
+ 2£©Ôö¼Ó¶àÄ£Ïà¹ØÏûÏ¢idºÍASCÏà¹ØÏûÏ¢
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼Ó¿ìËÙ˯ÃßÏûÏ¢CPDCP_SCRI_IND_EV/CPDCP_ULDATA_TRANSFER_REQ_EV
+
+157 2011.04.02 ÕÔÕñ»Ô
+ 1) ΪR9Éý¼¶Ôö¼ÓÏûÏ¢
+
+158 2011.04.23 ÕÔÕñ»Ô
+ Õë¶ÔUICCÓÅ»¯£¬É¾³ýÎÞÓõÄÏûÏ¢AP_MMIA_UICC_INFO_REQ_EV ¡¢
+ AP_MMIA_UICC_INFO_CNF_EV¡¢AP_MMIA_PIN_STATE_IND_EV
+
+159 2011.05.03 ÕÔÕñ»ÔΪ3GÃûƬ¼ÐÔö¼ÓÏûÏ¢AP_MMIA_ZCPBQ_SET_REQ_EV¡¢AP_MMIA_ZCPBQ_QUERY_REQ_EV
+ AP_MMIA_ZEER_READ_REQ_EV¡¢AP_MMIA_ZCPBQ_SET_CNF_EV¡¢AP_MMIA_ZCPBQ_QUERY_CNF_EV
+ AP_MMIA_ZEER_READ_CNF_EV¡¢AP_MMIA_PB_READ_CAPA_REQ_EV¡¢AP_MMIA_PB_READ_SET_NUM_REQ_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_REQ_EV¡¢AP_MMIA_PB_READ_CAPA_CNF_EV¡¢AP_MMIA_PB_READ_SET_NUM_CNF_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_CNF_EV
+160 2011.05.31 ʷѧºì
+ Ôö¼ÓROHCv2¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¶Î,Ôö¼ÓROHCv2_T_IR_EXPIRY_EVÏûÏ¢ºÅ
+
+161 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼Ó´¦Àí+ZIMIµÄÏûÏ¢AP_MMIA_SET_IMSI_REQ_EV
+
+162 2011.06.16 ËÎÑÇÅô
+ Ôö¼ÓGMM¼à¿ØMSÖ÷¶¯ÇëÇóÊÍ·ÅÁ´½Ó¶¨Ê±Æ÷Z_GMM_Twrel³¬Ê±µÄÏûÏ¢GMM_T_WREL_EXPIRY_EV
+ EC614000821119£ºGMMÄ£¿éÊÍ·ÅRRCÁ¬½ÓÔö¼ÓÎÕÊÖ¹ý³Ì£¬Ôö¼Ó¶¨Ê±Æ÷Twrel¼à¿Ø´Ë¹ý³Ì£¬Í¬Ê±ÐèÒªÔö¼Ó¶¨Ê±Æ÷³¬Ê±ÏûÏ¢
+163 2011.06.20 ¹ù·å
+ EC614000815619£ºCM²ãÔÚUMM»»Íø¹ý³ÌÖÐÓÐÒµÎñÁ÷³Ì£¬²»¶ÏµÄ·¢ÆðCM_EST£»Í¨¹ý¶¨Ê±Æ÷À´¿ØÖÆÖØ·¢´ÎÊý
+
+ 164 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼ÓÏûÏ¢AP_MMIA_CS_SRV_IND_EV
+
+165 2011.06.30 Ëﳤ½Ôö¼ÓPA+Éý¼¶ÐÞ¸Ä
+ 1£©URBC_UPHY_RSP_EVENTÓëURBC_UPHY_EVENT_BASEÖ®¼äµÄÆ«ÒÆÓÉ20±äΪ30£»
+ 2£©Ôö¼ÓÏûÏ¢ºÅCSCI_UNRECOVER_ERR_EV£¬URRC_EFACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_REQ_EV£¬CUMAC_HSPA_EPCH_CFG_REQ_EV£¬
+ CUMAC_UPDATE_ERNTI_REQ_EV£¬CUMAC_FACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_CNF_EV£¬P_HSPA_PLUS_FACH_REQ_EV£¬P_HSPA_PLUS_PCH_REQ_EV
+ P_HSPA_PLUS_FACH_REL_REQ_EV£¬P_HSPA_PLUS_PCH_REL_REQ_EV£¬P_EFACH_UPDATE_RNTI_REQ_EV£¬P_CELL_RESEL_REQ_EV£¬P_CELL_RESEL_CNF_EV£¬P_SYNC_CMD_RESP_EV,
+ P_HSPA_PLUS_FACH_REL_CNF_EV,P_HSPA_PLUS_FACH_REL_CNF_EV
+ 3£©P_DL_DPCH_SETUP_MODIFY_CNF_EV¸ÄÃûΪP_DL_RL_SETUP_MODIFY_CNF_EV
+
+ 166 2011.7.1 ¹Ë±¦³ÉÔö¼ÓÄ£ÄâPSIÏûÏ¢SIMULPSI_CONFIG_EV
+
+ 167 2011.7.7 ÕÔÕñ»ÔÔö¼Ó¶ÔCSÑ°ºôµÄÓ¦´ðÏûÏ¢AP_MMIA_CS_SRV_RSP_EV
+ 168 2011.7.15 ÕÅÅô³ÌÔö¼ÓÖ§³ÖLTE±³¾°ËÑË÷¹¦ÄÜÐÂÔöµÄʼþºÅ
+ AP_MMIA_BGPLMNSEL_SETREQ_EV¡¢AP_MMIA_BGPLMNSEL_QUERYCNF_EV¡¢AP_MMIA_BGPLMNSEL_QUERYREQ_EV
+ MMIA_UMM_BGPLMNSEL_REQ_EV
+ UMM_ASC_TRY_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_CNF_EV¡¢UMM_ASC_TRY_BGPLMN_REJ_EV¡¢UMM_ASC_TRY_BGPLMN_CNF_EV
+ ASC_LTE_TRY_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_CNF_EV¡¢ASC_LTE_TRY_BGPLMN_REJ_EV¡¢ASC_LTE_TRY_BGPLMN_CNF_EV
+169 2011.7.18 Ëﳤ½ Õë¶Ô614000878724 ɾ³ýÈçÏÂÏûÏ¢ºÅ
+ AS_LTE_TD_CSHO_REQ_EV¡¢AS_LTE_TD_CSHO_CNF_EV¡¢AS_LTE_TD_CSHO_REJ_EV
+170 2011.7.28 ½ª²¨ Õë¶Ô614000920283 Ôö¼ÓÈçÏÂÏûÏ¢ºÅ
+ ASC_LTE_LOCK_CELL_REQ_EV¡¢ASC_LTE_UNLOCK_CELL_REQ_EV¡¢ASC_LTE_LOCK_CELL_CNF_EV
+171 2011.8.2 ÅËÀÚ Ôö¼ÓÏûÏ¢ºÅUURLC_PDCP_DATA_IND_EV
+172 2011.8.2 Ëﳤ½ ÏûÏ¢ºÅ¶¨ÒåÖظ´ÁË£¬ÐèҪɾ³ýÏûÏ¢ºÅCUMAC_RESEL_REQ_EV£¬CUMAC_RESEL_IND_EV
+173 2011.8.15 ³Â¹â»ªÔö¼ÓCBSÏûÏ¢ºÅCBS_ASC_CMAS_NOTIFY_IND_EV
+174 2011.8.17 ¿µÊé½ÜÔö¼ÓCSGÏûÏ¢ºÅEURRC_CSG_PROXIMITY_IND_EV
+175 2011.8.23 ¿µÊé½Üɾ³ýLTE_P_SWITCH_RF_REQ_EV,LTE_P_START_PAGING_REQ_EV,LTE_P_SWITCH_RF_CNF_EV
+ Ôö¼ÓLTE_P_SLEEP_TIME_IND_EV£¬LTE_P_WAKEUP_REQ_EV
+176 2011.8.23 ÕÔÕñ»ÔΪCMMB/×¼FR/Refresh/·þÎñÁбí/CCOͳ¼ÆÔö¼ÓÏûÏ¢AP_MMIA_MB_AUTH_REQ_EV¡¢
+ AP_MMIA_MB_CELL_ID_REQ_EV¡¢AP_MMIA_PSEUDO_FR_SET_REQ_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_REQ_EV¡¢
+ AP_MMIA_REFRESH_REQ_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_REQ_EV¡¢AP_MMIA_MB_AUTH_CNF_EV ¡¢
+ AP_MMIA_MB_CELL_ID_CNF_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_CNF_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_CNF_EV¡¢
+ MSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV
+177 2011.8.24 ΤÓñÕäÔö¼Ólte gap±¨¸æ¸øtrs
+178 2011.8.25 ÑîÔÊÔö¼ÓESM_EMM_EMERGENCY_PDN_ONLY_IND_EV,EMM_ESM_DETACH_NORMAL_IND_EV
+179 2011.8.25 ÑÔö¼ÓESM_UMM_LOCAL_DEACT_IND_EV
+180 2011.8.25 ׿±Ø²¨Ôö¼ÓCM_SM_DEACT_NON_EMERGENCY_EV
+181 2011.8.29 ½ª²¨Ôö¼ÓMSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV¡¢MSGTRACEPS_CELLRESORCCO_IND_EV¡¢MMIA_AS_EM_CELLRESORCCOCOUNT_REQ_EV¡¢
+ ASC_LTE_CMAS_NOTIFY_IND_EV¡¢EUSIR_T_ETWS_EXPIRY_EV¡¢EUSIR_T_CMAS_EXPIRY_EV
+ ÐÞ¸ÄEURRC_ETWS_INFO_EV Ϊ EURRC_WARNING_NOTIFY_INFO_EV
+182 2011.8.29 ÓȺ£Ó¢ refresh Ôö¼Ó AP_UICC_REFRESH_REQ_EV AP_UICC_DEACTEND_IND_EV AP_UICC_FILECHANGEEND_IND_EV AP_UICC_FILECHANGE_IND_EV
+183 2011.9.15 ½ª²¨Ôö¼ÓEURRC_SI_END_FOR_HO_EV
+184 2011.9.15 ÍõÖ¾Ôö¼ÓENBRRC_PROXIMITY_RPT_EV
+185 2011.9.16 Ðì¿¡Ôö¼ÓGRRº¯Êý½Ó¿Ú
+186 2011.9.16 Ëﳤ½ÉêÇëÔö¼ÓENBRRC_UE_INFO_REQ_EV¡¢ENBRRC_UE_INFO_RSP_EV
+187 2011.9.26 ð¿¡µ÷ÕûGRR¶¨Ê±Æ÷ÏûÏ¢ºÅ·¶Î§
+
+188 2011.10.12 lh ɾ³ýÁÚÇøÉϱ¨ºÍ·þÎñСÇøÉϱ¨ÏûÏ¢½Ó¿Ú£¬Ôö¼ÓLTEСÇøÐÅÏ¢Éϱ¨Ê¼þºÅ
+189 2011.10.18 ÕÔÕñ»ÔΪLTE±³¾°ËÑË÷Ôö¼ÓÏûÏ¢AP_MMIA_LTEBGPLMN_TESTREQ_EVºÍAP_MMIA_LTEBGPLMN_TESTCNF_EV
+
+190 2011.10.19 ºÎ«Ôö¼Ó¶¨Ê±Æ÷ʼþºÅT_DISABLE_UMTS_MEAS_EV,T_DISABLE_LTE_MEAS_EV
+191 2011.11.3 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SMSOVERIPNET_SETREQ_EV¡¢AP_MMIA_SMSOVERIPNET_QUERYREQ_EV
+ AP_MMIA_SMSOVERIPNET_QUERYCNF_EV¡¢MMIA_UMM_SMSOVERIPNET_SETREQ_EV
+ EC614001128873
+
+192 2011.11.4 ÕÔÕñ»ÔÔö¼ÓËæeÐа汾IccIdµÄÉϱ¨ºÍ»ú¿¨»¥ËøÐèÇó:
+ Ôö¼ÓÏûÏ¢ZPS_ApUicc_ToReadCardReq_Ev¡¢ZPS_ApMmia_Iccid_Ind_EV¡¢ZPS_ApMmia_USAT_ToReadCardReq_Ev
+
+193 2011.11.4 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SM_DEACT_IND_EV, EC614001103133
+194 2011.11.22 ÓȺ£Ó¢Ôö¼ÓTEST_SET_NV_DATA_SPCLFUNC_EV £¬EC 614001151291
+
+195 2011.12.2 ÁºÐ¡º®Ôö¼ÓÏûÏ¢AP_MMIA_CALL_LINE_SET_REQ_EV¡¢AP_MMIA_CALL_LINE_QRY_REQ_EVºÍAP_MMIA_CALL_LINE_QUERY_CNF_EV 614001181454
+ R9 U115¸£ÖÝ°æ±¾Ò»»úË«ºÅÐèÇó ºÏÈë
+
+196 2011.12.26 EC617001225651,MMIAÔö¼ÓUE InfoµÄÉϱ¨,ÕÔÕñ»ÔÔö¼ÓÏûÏ¢ROADTEST_UEINFO_REQ_EV¡¢ROADTEST_UEINFO_CNF_EV
+197 2011.12.27 ËÎÑÇÅôÐÂÔöPDCP(RABM)֪ͨGMM¹ØÓÚRABÐÅÏ¢
+
+198 2012.1.5 EC617001233064Ôö¼ÓÄ£ÄâPDI·¢Ë͸øGSMAµÄÏûÏ¢PDI_GSM_DATA_REQ_EV
+199 2012.1.11 ¹Ë±¦³ÉÐÂÔöÈýÌõÏûÏ¢ÓÃÓÚÓû§ÃæÌØÊâÐÅÁî¸ú×Ù
+200 2012.03.12 ΤÓñÕä Ôö¼ÓÏûÏ¢P_DETECT_CELL_INFO_IND_EV
+201 2012.03.27 ³ÂΰÐÂÔöLTE_P_DLSCH_DATA_TRACE_EVºÍLTE_P_ULSCH_DATA_TRACE_EVÓÃÓÚEPHYºÍEUMAC¼äµÄÉÏÏÂÐÐÊý¾ÝÐÅÁî¸ú×Ù
+
+202 2012.04.16 ºÎ«ÐÂÔöGRR_RRC_POWEROFF_IND_EVÏûÏ¢ÓÃÀ´Í¨ÖªGRRC(Èí)¹Ø»ú
+203 2012.05.08 Ëﳤ½ÐÂÔöASC_TD_LOSTCOV_CAMP_SUCC_IND_EVÏûÏ¢ÓÃÓÚÆäËüÖÆʽ¶ªÊ§¸²¸ÇÖØÑ¡µ½TD³É¹¦ºó£¬ASC֪ͨUCER±íʾ¿çÖÆʽÖØÑ¡³É¹¦¡£
+204 2012.05.10 ³ÂΰÐÂÔöLTE_P_MAC_SR_REQ_EVÓÃÓÚTMTÐÅÁî¸ú×ÙSRµÄ·¢ËÍ
+205 2012.05.10 Ëﳤ½ÐÂÔöP_UL_PHY_CH_CTRL_REQ_EvÏûÏ¢ÓÃÓÚ½øÐÐUl-DTXÅäÖÃ?
+206 2012.07.15 ÁºÐ¡º®ÐÂÔöMMIA_EUCSR_LTEINFO_REQ_EVµÈÏûÏ¢ÓÃÓÚatÃüÁîÉϱ¨×ÓÖ¡ÅäÖÃÐÅÏ¢
+207 2012.08.02 ÍõС½ø EC617001662142£¬ Ôö¼Ó
+ AP_UICC_CCHO_REQ_EV,AP_UICC_CCHC_REQ_EV,AP_UICC_CGLA_REQ_EV,AP_UICC_CRSM_REQ_EV,
+ AP_UICC_CCHO_CNF_EV,AP_UICC_CGLA_CNF_EV,AP_UICC_CRSM_CNF_EV,AP_UICC_USAT_FETCH_IND_EV,
+208 2012.11.06 W GROUPÐ޸ģºÐÞ¸Äpsenent end,ÔÚÔÀ´µÄ»ù´¡ÉÏÔö¼ÓÁË8000.W·ÇÎïÀí²ãÏûϢλÓÚLTEÏûÏ¢Ö®ºó£¬ÔÚ16384--end
+ WµÄÎïÀí²ãÏûÏ¢·ÅÔÚps+6500---ps+7000µÄµØ·½£¬¶ÔÓÚTW¹²ÓÃÏûÏ¢²ÉÓÃÐÞ¸ÄÃüÃûµÄ·½Ê½TD¸ÄΪUTRA
+209 2012.11.21 ÍõС½ø EC617001860117£¬ ÖÇÄÜ»úÈȲå°ÎÐèÇó£¬Ôö¼ÓÏûÏ¢
+ AP_UICC_MOVECARD_IND_EV AP_UICC_INSERTCARD_IND_EV
+210 2013.10.18 ΤÓñÕäÔö¼ÓATIÓëASµÄÏûÏ¢MMIA_AS_B39_INFO_IND_EV(EUMCR,UMCR->ATI)ºÍMMIA_AS_B39_INFO_REQ_EV(ATI->GRR)
+ *****************************************************************************/
+#ifndef Z_EVENTDEF_H
+#define Z_EVENTDEF_H
+
+#include "atipsevent.h"
+
+/*=====================================================================================================================
+ ÏûÏ¢Çø¼ä£º
+
+ ||______________________|__________UPHY__________|_____________________|_____________________||
+ PS_BASE UPHY_BASE(+6K) UPHY_BASE(+6.5K) PS_LTE_BASE(+10K) PS_END(PS_LTE_END)
+ =====================================================================================================================*/
+
+/*GSM SDLÏûϢʼþºÅ·¶Î§£¬¾ßÌåµÄGSMʼþºÅ¶¨ÒåÔÚSIG_CODE.HÖУ¬½öÔÚpstestÖÐʹÓÃ*/
+#define EVENT_PS_GSM_SDL_BASE (DWORD)0x00010000
+#define EVENT_PS_GSM_SDL_END (DWORD)0xff7d0003
+
+/*LTEʼþºÅ·¶Î§*/
+#define EVENT_PS_LTE_BASE (DWORD)(EVENT_PS_BASE + 10000)
+#define EVENT_PS_LTE_END (DWORD)(EVENT_PS_BASE + 16383)
+
+/*WCDMAʼþºÅ·¶Î§*/
+#define EVENT_PS_W_BASE (DWORD)(EVENT_PS_BASE + 16384)
+#define EVENT_PS_W_END (DWORD)EVENT_PS_END
+/**************************************************PHY msg base-end start********************************************************/
+/*Õⲿ·ÖID²»ÄÜËæÒâÐ޸ģ¬»áÓ°Ïì½Ó¿ÚÖеÄmsgidµÄÖµ£¬´Ó¶øʹÎïÀí²ãµ¼ÖÂÎóÅÐÏûÏ¢*/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define PS_UPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6000)
+/*ÐÒéÕ»ÓëWCDMAÎïÀí²ãÏûÏ¢·¶Î§.TDÓëWÎïÀí²ãÏûÏ¢·¶Î§¹Ì¶¨ÔÚ6000µ½7000.ÆäÖÐÇ°500ÓÃÓÚTD£¬ºó500ÓÃÓÚW*/
+#define PS_WPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6500)
+
+/*ÐÒéÕ»ÓëLTEÎïÀí²ãÏûÏ¢·¶Î§£¬±£Ö¤ÎïÀí²ãºÍÐÒéÕ»IDÆðʼֵµÍ8λȫÁ㣬±£Ö¤Ç¿ÖÆת»»ÎªBYTEΪÕý³£Öµ*/
+#define LTE_PS_EUPHY_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 2544)
+#define LTE_PS_EUPHY_RSP_EVENT (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 60)
+#define LTE_PS_EUPHY_EVENT_END (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 120)
+/**************************************************PHY msg base-end end********************************************************/
+
+/*UMM¡¢MM¡¢GMMÄÚ²¿ÏûÏ¢·¶Î§(50)*/
+#define UMM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2570)
+#define UMM_EVENT_END (DWORD)(UMM_EVENT_BASE + 49)
+
+/*SS/SMS/SM/CC/PDCPÓëMM/GMMµÄÏûÏ¢·¶Î§(50)*/
+#define CM_MM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2620)
+#define CM_MM_EVENT_END (DWORD)(CM_MM_EVENT_BASE + 49)
+
+/*UMMºÍASCµÄÏûÏ¢·¶Î§ (100)*/
+#define UMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2670)
+#define UMM_ASC_RSP_EVENT (DWORD)(UMM_ASC_EVENT_BASE + 50)
+#define UMM_ASC_EVENT_END (DWORD)(UMM_ASC_EVENT_BASE + 99)
+
+/*GMMºÍASCµÄÏûÏ¢·¶Î§(100) */
+#define GMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2770)
+#define GMM_ASC_RSP_EVENT (DWORD)(GMM_ASC_EVENT_BASE + 50)
+#define GMM_ASC_EVENT_END (DWORD)(GMM_ASC_EVENT_BASE + 99)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_UAS_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2870)
+#define ASC_UAS_RSP_EVENT (DWORD)(ASC_UAS_EVENT_BASE + 50)
+#define ASC_UAS_EVENT_END (DWORD)(ASC_UAS_EVENT_BASE + 99)
+
+/*ASCºÍGSM ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_GAS_EVENT_BASE (DWORD)(ASC_UAS_EVENT_END + 1)
+#define ASC_GAS_RSP_EVENT (DWORD)(ASC_GAS_EVENT_BASE + 50)
+#define ASC_GAS_EVENT_END (DWORD)(ASC_GAS_EVENT_BASE + 99)
+
+/*ASCºÍLTE ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_EUAS_EVENT_BASE (DWORD)(ASC_GAS_EVENT_END + 1)
+#define ASC_EUAS_RSP_EVENT (DWORD)(ASC_EUAS_EVENT_BASE + 50)
+#define ASC_EUAS_EVENT_END (DWORD)(ASC_EUAS_EVENT_BASE + 99)
+
+/*ASCºÍ¸÷AS¹«¹²µÄÏûÏ¢·¶Î§(100) */
+#define ASC_AS_EVENT_BASE (DWORD)(ASC_EUAS_EVENT_END + 1)
+#define ASC_AS_EVENT_END (DWORD)(ASC_AS_EVENT_BASE + 149)
+
+/*CBSºÍRRCµÄÏûÏ¢·¶Î§(30)*/
+#define CBS_RRC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 3320)
+#define CBS_RRC_RSP_EVENT (DWORD)(CBS_RRC_EVENT_BASE + 20)
+#define CBS_RRC_EVENT_END (DWORD)(CBS_RRC_EVENT_BASE + 29)
+
+/*GMMºÍSNDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_SNDCP_EVENT_BASE (DWORD)(CBS_RRC_EVENT_END + 1)
+#define GMM_SNDCP_EVENT_END (DWORD)(GMM_SNDCP_EVENT_BASE + 24)
+
+/*GMMºÍPDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_PDCP_EVENT_BASE (DWORD)(GMM_SNDCP_EVENT_END + 1)
+#define GMM_PDCP_EVENT_END (DWORD)(GMM_PDCP_EVENT_BASE + 24)
+
+/*SMºÍPDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_PDCP_EVENT_BASE (DWORD)(GMM_PDCP_EVENT_END + 1)
+#define SM_PDCP_RSP_EVENT (DWORD)(SM_PDCP_EVENT_BASE + 25)
+#define SM_PDCP_EVNET_END (DWORD)(SM_PDCP_EVENT_BASE + 49)
+
+/*SMºÍSNDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_SNDCP_EVENT_BASE (DWORD)(SM_PDCP_EVNET_END + 1)
+#define SM_SNDCP_RSP_EVENT (DWORD)(SM_SNDCP_EVENT_BASE + 20)
+#define SM_SNDCP_EVENT_END (DWORD)(SM_SNDCP_EVENT_BASE + 49)
+
+/*PDIºÍGSMAµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_GSMA_EVENT_BASE (DWORD)(SM_SNDCP_EVENT_END + 1)
+#define PDI_GSMA_RSP_EVENT (DWORD)(PDI_GSMA_EVENT_BASE + 10)
+#define PDI_GSMA_EVENT_END (DWORD)(PDI_GSMA_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_PDCP_EVENT_BASE (DWORD)(PDI_GSMA_EVENT_END + 1)
+#define PDI_PDCP_RSP_EVENT (DWORD)(PDI_PDCP_EVENT_BASE + 10)
+#define PDI_PDCP_EVENT_END (DWORD)(PDI_PDCP_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_URLC_EVENT_BASE (DWORD)(PDI_PDCP_EVENT_END + 1)
+#define PDCP_URLC_EVENT_END (DWORD)(PDCP_URLC_EVENT_BASE + 9)
+
+/*TAFºÍCCÏûÏ¢·¶Î§(50)*/
+#define CC_TAF_EVENT_BASE (DWORD)(PDCP_URLC_EVENT_END + 1)
+#define CC_TAF_EVENT_END (DWORD)(CC_TAF_EVENT_BASE + 49)
+
+/*UMMºÍCBSÏûÏ¢·¶Î§(50)*/
+#define UMM_CBS_EVENT_BASE (DWORD)(CC_TAF_EVENT_END + 1)
+#define UMM_CBS_RSP_EVENT (DWORD)(UMM_CBS_EVENT_BASE + 20)
+#define UMM_CBS_EVENT_END (DWORD)(UMM_CBS_EVENT_BASE + 49)
+
+/*SCIºÍURRC/CCÏûÏ¢·¶Î§(30)*/
+#define AP_SCI_EVENT_BASE (DWORD)(UMM_CBS_EVENT_END + 1)
+#define AP_SCI_EVENT_END (DWORD)(AP_SCI_EVENT_BASE + 29)
+
+/*URLCºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define URLC_URRC_EVENT_BASE (DWORD)(AP_SCI_EVENT_END + 1)
+#define URLC_URRC_RSP_EVENT (DWORD)(URLC_URRC_EVENT_BASE + 30)
+#define URLC_URRC_EVENT_END (DWORD)(URLC_URRC_EVENT_BASE + 59)
+
+/*UMACºÍURRCµÄÏûÏ¢·¶Î§(70)*/
+#define UMAC_URRC_EVENT_BASE (DWORD)(URLC_URRC_EVENT_END + 1)
+#define UMAC_URRC_RSP_EVENT (DWORD)(UMAC_URRC_EVENT_BASE + 40)
+#define UMAC_URRC_EVENT_END (DWORD)(UMAC_URRC_EVENT_BASE + 69)
+
+/*UMAC-UL/DLºÍUMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define UMAC_UMAC_EVENT_BASE (DWORD)(UMAC_URRC_EVENT_END + 1)
+#define UMAC_UMAC_EVENT_END (DWORD)(UMAC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1T_URRC_EVENT_BASE (DWORD)(UMAC_UMAC_EVENT_END + 1)
+#define L1T_URRC_RSP_EVENT (DWORD)(L1T_URRC_EVENT_BASE + 30)
+#define L1T_URRC_EVENT_END (DWORD)(L1T_URRC_EVENT_BASE + 59)
+
+/*PDCPºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_URRC_EVENT_BASE (DWORD)(L1T_URRC_EVENT_END + 1)
+#define PDCP_URRC_RSP_EVENT (DWORD)(PDCP_URRC_EVENT_BASE + 30)
+#define PDCP_URRC_EVENT_END (DWORD)(PDCP_URRC_EVENT_BASE + 59)
+
+/*URLCºÍUMACµÄÏûÏ¢·¶Î§(20)*/
+#define URLC_UMAC_EVENT_BASE (DWORD)(PDCP_URRC_EVENT_END + 1)
+#define URLC_UMAC_EVENT_END (DWORD)(URLC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍUMACµÄÏûÏ¢·¶Î§(10)*/
+#define UMAC_L1T_EVENT_BASE (DWORD)(URLC_UMAC_EVENT_END + 1)
+#define UMAC_L1T_EVENT_END (DWORD)(UMAC_L1T_EVENT_BASE + 9)
+
+/*URRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define URRC_EVENT_BASE (DWORD)(UMAC_L1T_EVENT_END + 1)
+#define URRC_EVENT_END (DWORD)(URRC_EVENT_BASE + 99)
+
+/*L1TÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1T_EVENT_BASE (DWORD)(URRC_EVENT_END + 1)
+#define L1T_EVENT_END (DWORD)(L1T_EVENT_BASE + 19)
+
+/*ÎïÀí²ãÊÊÅä²ãÖ®¼äL1T/L1EÏûÏ¢·¶Î§(30)£¨²»°üº¬L1G£¬ÓëL1G½»»¥µÄÏûϢȫ²¿ÊÇSDLÏûÏ¢£¬¶¨ÒåÔÚsig_code.hÖУ©*/
+#define L1A_EVENT_BASE (DWORD)(L1T_EVENT_END + 1)
+#define L1A_EVENT_END (DWORD)(L1A_EVENT_BASE + 29)
+
+/*ÐÒéÕ»ÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§(530)*/
+#define UMM_TIMER_EVENT_BASE (DWORD)(MMIA_TIMER_EVENT_END + 1)
+#define UMM_TIMER_EVENT_END (DWORD)(UMM_TIMER_EVENT_BASE + 49)
+
+#define MM_TIMER_EVENT_BASE (DWORD)(UMM_TIMER_EVENT_END + 1)
+#define MM_TIMER_EVENT_END (DWORD)(MM_TIMER_EVENT_BASE + 29)
+
+#define GMM_TIMER_EVENT_BASE (DWORD)(MM_TIMER_EVENT_END + 1)
+#define GMM_TIMER_EVENT_END (DWORD)(GMM_TIMER_EVENT_BASE + 29)
+
+#define CC_TIMER_EVENT_BASE (DWORD)(GMM_TIMER_EVENT_END + 1)
+#define CC_TIMER_EVENT_END (DWORD)(CC_TIMER_EVENT_BASE + 49)
+
+#define SMS_TIMER_EVENT_BASE (DWORD)(CC_TIMER_EVENT_END + 1)
+#define SMS_TIMER_EVENT_END (DWORD)(SMS_TIMER_EVENT_BASE + 19)
+
+#define SM_TIMER_EVENT_BASE (DWORD)(SMS_TIMER_EVENT_END + 1)
+#define SM_TIMER_EVENT_END (DWORD)(SM_TIMER_EVENT_BASE + 19)
+
+#define SS_TIMER_EVENT_BASE (DWORD)(SM_TIMER_EVENT_END + 1)
+#define SS_TIMER_EVENT_END (DWORD)(SS_TIMER_EVENT_BASE + 9)
+
+#define CBS_TIMER_EVENT_BASE (DWORD)(SS_TIMER_EVENT_END + 1)
+#define CBS_TIMER_EVENT_END (DWORD)(CBS_TIMER_EVENT_BASE + 9)
+
+#define UICC_TIMER_EVENT_BASE (DWORD)(CBS_TIMER_EVENT_END + 1)
+#define UICC_TIMER_EVENT_END (DWORD)(UICC_TIMER_EVENT_BASE + 19)
+
+#define URRC_TIMER_EVENT_BASE (DWORD)(UICC_TIMER_EVENT_END + 1)
+#define URRC_TIMER_EVENT_END (DWORD)(URRC_TIMER_EVENT_BASE + 79)
+
+#define URLC_TIMER_EVENT_BASE (DWORD)(URRC_TIMER_EVENT_END + 1)
+#define URLC_TIMER_EVENT_END (DWORD)(URLC_TIMER_EVENT_BASE + 19)
+
+#define UMAC_TIMER_EVENT_BASE (DWORD)(URLC_TIMER_EVENT_END + 1)
+#define UMAC_TIMER_EVENT_END (DWORD)(UMAC_TIMER_EVENT_BASE + 19)
+
+#define L1T_TIMER_EVENT_BASE (DWORD)(UMAC_TIMER_EVENT_END + 1)
+#define L1T_TIMER_EVENT_END (DWORD)(L1T_TIMER_EVENT_BASE + 19)
+
+#define PDCP_TIMER_EVENT_BASE (DWORD)(L1T_TIMER_EVENT_END + 1)
+#define PDCP_TIMER_EVENT_END (DWORD)(PDCP_TIMER_EVENT_BASE + 9)
+
+#define ROHCv1_TIMER_EVENT_BASE (DWORD)(PDCP_TIMER_EVENT_END + 1)
+#define ROHCv1_TIMER_EVENT_END (DWORD)(ROHCv1_TIMER_EVENT_BASE + 19)
+
+#define TAF_TIMER_EVENT_BASE (DWORD)(ROHCv1_TIMER_EVENT_END + 1)
+#define TAF_TIMER_EVENT_END (DWORD)(TAF_TIMER_EVENT_BASE + 19)
+
+#define GSMA_TIMER_EVENT_BASE (DWORD)(TAF_TIMER_EVENT_END + 1)
+#define GSMA_TIMER_EVENT_END (DWORD)(GSMA_TIMER_EVENT_BASE + 19)
+
+#define PDI_TIMER_EVENT_BASE (DWORD)(GSMA_TIMER_EVENT_END + 1)
+#define PDI_TIMER_EVENT_END (DWORD)(PDI_TIMER_EVENT_BASE + 19)
+
+#define ROHCv2_TIMER_EVENT_BASE (DWORD)(PDI_TIMER_EVENT_END + 1)
+#define ROHCv2_TIMER_EVENT_END (DWORD)(ROHCv2_TIMER_EVENT_BASE + 19)
+
+#define SCI_TIMER_EVENT_BASE (DWORD)(ROHCv2_TIMER_EVENT_END + 1)
+#define SCI_TIMER_EVENT_END (DWORD)(SCI_TIMER_EVENT_BASE + 9)
+
+#define STM_TIMER_EVENT_BASE (DWORD)(SCI_TIMER_EVENT_END + 1)
+#define STM_TIMER_EVENT_END (DWORD)(STM_TIMER_EVENT_BASE + 9)
+
+#define USAT_TIMER_EVENT_BASE (DWORD)(STM_TIMER_EVENT_END + 1)
+#define USAT_TIMER_EVENT_END (DWORD)(USAT_TIMER_EVENT_BASE + 9)
+
+#define TIMER_EVENT_END (DWORD)USAT_TIMER_EVENT_END
+
+/**************************************************PS msg range end********************************************************/
+
+/**************************************************UPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§(300)*/
+#define USIR_UPHY_EVENT_BASE (DWORD)PS_UPHY_EVENT_BASE
+#define USIR_UPHY_RSP_EVENT (DWORD)(USIR_UPHY_EVENT_BASE + 20)
+#define USIR_UPHY_EVENT_END (DWORD)(USIR_UPHY_EVENT_BASE + 49)
+
+#define UCSR_UPHY_EVENT_BASE (DWORD)(USIR_UPHY_EVENT_END + 1)
+#define UCSR_UPHY_RSP_EVENT (DWORD)(UCSR_UPHY_EVENT_BASE + 20)
+#define UCSR_UPHY_EVENT_END (DWORD)(UCSR_UPHY_EVENT_BASE + 49)
+
+#define UMCR_UPHY_EVENT_BASE (DWORD)(UCSR_UPHY_EVENT_END + 1)
+#define UMCR_UPHY_RSP_EVENT (DWORD)(UMCR_UPHY_EVENT_BASE + 20)
+#define UMCR_UPHY_EVENT_END (DWORD)(UMCR_UPHY_EVENT_BASE + 49)
+
+#define URBC_UPHY_EVENT_BASE (DWORD)(UMCR_UPHY_EVENT_END + 1)
+#define URBC_UPHY_RSP_EVENT (DWORD)(URBC_UPHY_EVENT_BASE + 30)
+#define URBC_UPHY_EVENT_END (DWORD)(URBC_UPHY_EVENT_BASE + 49)
+
+#define UMAC_UL_UPHY_EVENT_BASE (DWORD)(URBC_UPHY_EVENT_END + 1)
+#define UMAC_UL_UPHY_EVENT_END (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 19)
+
+#define UMAC_DL_UPHY_EVENT_BASE (DWORD)(UMAC_UL_UPHY_EVENT_END + 1)
+#define UMAC_DL_UPHY_EVENT_END (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 29)
+
+/*L1TÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1T_UPHY_EVENT_BASE (DWORD)(UMAC_DL_UPHY_EVENT_END + 1)
+#define L1T_UPHY_RSP_EVENT (DWORD)(L1T_UPHY_EVENT_BASE + 20)
+#define L1T_UPHY_EVENT_END (DWORD)(L1T_UPHY_EVENT_BASE + 49)
+
+#define PS_UPHY_EVENT_END (DWORD)L1T_UPHY_EVENT_END
+/**************************************************WPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define WSIR_WPHY_EVENT_BASE (DWORD)PS_WPHY_EVENT_BASE
+#define WSIR_WPHY_RSP_EVENT (DWORD)(WSIR_WPHY_EVENT_BASE + 20)
+#define WSIR_WPHY_EVENT_END (DWORD)(WSIR_WPHY_EVENT_BASE + 49)
+
+#define WCSR_WPHY_EVENT_BASE (DWORD)(WSIR_WPHY_EVENT_END + 1)
+#define WCSR_WPHY_RSP_EVENT (DWORD)(WCSR_WPHY_EVENT_BASE + 20)
+#define WCSR_WPHY_EVENT_END (DWORD)(WCSR_WPHY_EVENT_BASE + 49)
+
+#define WMCR_WPHY_EVENT_BASE (DWORD)(WCSR_WPHY_EVENT_END + 1)
+#define WMCR_WPHY_RSP_EVENT (DWORD)(WMCR_WPHY_EVENT_BASE + 20)
+#define WMCR_WPHY_EVENT_END (DWORD)(WMCR_WPHY_EVENT_BASE + 49)
+
+#define WRBC_WPHY_EVENT_BASE (DWORD)(WMCR_WPHY_EVENT_END + 1)
+#define WRBC_WPHY_RSP_EVENT (DWORD)(WRBC_WPHY_EVENT_BASE + 30)
+#define WRBC_WPHY_EVENT_END (DWORD)(WRBC_WPHY_EVENT_BASE + 49)
+
+#define WMAC_UL_WPHY_EVENT_BASE (DWORD)(WRBC_WPHY_EVENT_END + 1)
+#define WMAC_UL_WPHY_EVENT_END (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 19)
+
+#define WMAC_DL_WPHY_EVENT_BASE (DWORD)(WMAC_UL_WPHY_EVENT_END + 1)
+#define WMAC_DL_WPHY_EVENT_END (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 29)
+
+/*L1WÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1W_WPHY_EVENT_BASE (DWORD)(WMAC_DL_WPHY_EVENT_END + 1)
+#define L1W_WPHY_RSP_EVENT (DWORD)(L1W_WPHY_EVENT_BASE + 20)
+#define L1W_WPHY_EVENT_END (DWORD)(L1W_WPHY_EVENT_BASE + 49)
+
+#define PS_WPHY_EVENT_END (DWORD)L1W_WPHY_EVENT_END
+/**************************************************WPHY msg range end********************************************************/
+
+/**************************************************PS LTE msg range start********************************************************/
+/*EMMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EMM_TIMER_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1)
+#define EMM_TIMER_EVENT_END (DWORD)(EMM_TIMER_EVENT_BASE + 19)
+
+/*ESMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define ESM_TIMER_EVENT_BASE (DWORD)(EMM_TIMER_EVENT_END + 1)
+#define ESM_TIMER_EVENT_END (DWORD)(ESM_TIMER_EVENT_BASE + 19)
+
+/*EUPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EPDCP_TIMER_EVENT_BASE (DWORD)(ESM_TIMER_EVENT_END + 1)
+#define EPDCP_TIMER_EVENT_END (DWORD)(EPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EURLC_TIMER_EVENT_BASE (DWORD)(EPDCP_TIMER_EVENT_END + 1)
+#define EURLC_TIMER_EVENT_END (DWORD)(EURLC_TIMER_EVENT_BASE + 9)
+
+/*EUMACÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EUMAC_TIMER_EVENT_BASE (DWORD)(EURLC_TIMER_EVENT_END + 1)
+#define EUMAC_TIMER_EVENT_END (DWORD)(EUMAC_TIMER_EVENT_BASE + 9)
+
+/*EURRCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define EURRC_TIMER_EVENT_BASE (DWORD)(EUMAC_TIMER_EVENT_END + 1)
+
+/*EUCER×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCER_TIMER_EVENT_BASE (DWORD)(EURRC_TIMER_EVENT_BASE + 1)
+#define EUCER_TIMER_EVENT_END (DWORD)(EUCER_TIMER_EVENT_BASE + 19)
+
+/*EUMCR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUMCR_TIMER_EVENT_BASE (DWORD)(EUCER_TIMER_EVENT_END + 1)
+#define EUMCR_TIMER_EVENT_END (DWORD)(EUMCR_TIMER_EVENT_BASE + 19)
+
+/*EUCSR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCSR_TIMER_EVENT_BASE (DWORD)(EUMCR_TIMER_EVENT_END + 1)
+#define EUCSR_TIMER_EVENT_END (DWORD)(EUCSR_TIMER_EVENT_BASE + 19)
+
+/*EUSIR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUSIR_TIMER_EVENT_BASE (DWORD)(EUCSR_TIMER_EVENT_END + 1)
+#define EUSIR_TIMER_EVENT_END (DWORD)(EUSIR_TIMER_EVENT_BASE + 19)
+
+#define EURRC_TIMER_EVENT_END (DWORD)EUSIR_TIMER_EVENT_END
+
+/*EMMºÍUMMÄ£¿é¼äµÄÏûÏ¢IDºÅ*/
+#define EMM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 200)
+#define EMM_UMM_RSP_EVENT (DWORD)(EMM_UMM_EVENT_BASE + 19)
+#define EMM_UMM_EVENT_END (DWORD)(EMM_UMM_EVENT_BASE + 29)
+
+/*UMMºÍEPDCPÄ£¿éÖ®¼äµÄÏûÏ¢ID */
+#define UMM_EPDCP_EVENT_BASE (DWORD)(EMM_UMM_EVENT_END + 1)
+#define UMM_EPDCP_RSP_EVENT (DWORD)(UMM_EPDCP_EVENT_BASE + 9)
+#define UMM_EPDCP_EVENT_END (DWORD)(UMM_EPDCP_EVENT_BASE + 19)
+
+/* CM²ãºÍESMÄ£¿é¼äÏûÏ¢IDºÅ(ÐÂÔö)*/
+#define CM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 260)
+#define CM_ESM_RSP_EVENT (DWORD)(CM_ESM_EVENT_BASE + 9)
+#define CM_ESM_EVENT_END (DWORD)(CM_ESM_EVENT_BASE + 19)
+
+/* CM²ãºÍEMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define CM_EMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 280)
+#define CM_EMM_RSP_EVENT (DWORD)(CM_EMM_EVENT_BASE + 9)
+#define CM_EMM_EVENT_END (DWORD)(CM_EMM_EVENT_BASE + 19)
+
+/* EMMºÍESMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_EMM_EVENT_BASE (DWORD)(CM_EMM_EVENT_END + 1)
+#define ESM_EMM_RSP_EVENT (DWORD)(ESM_EMM_EVENT_BASE + 19)
+#define ESM_EMM_EVENT_END (DWORD)(ESM_EMM_EVENT_BASE + 29)
+
+/*EMMºÍERRC(CER)Ä£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_ASC_EVENT_BASE (DWORD)(ESM_EMM_EVENT_END + 1)
+#define EMM_ASC_RSP_EVENT (DWORD)(EMM_ASC_EVENT_BASE + 19)
+#define EMM_ASC_EVENT_END (DWORD)(EMM_ASC_EVENT_BASE + 49)
+
+/*EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_EPDCP_EVENT_BASE (DWORD)(EMM_ASC_EVENT_END + 1)
+#define EMM_EPDCP_RSP_EVENT (DWORD)(EMM_EPDCP_EVENT_BASE + 9)
+#define EMM_EPDCP_EVENT_END (DWORD)(EMM_EPDCP_EVENT_BASE + 19)
+
+/*ESMºÍUMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 400)
+#define ESM_UMM_RSP_EVENT (DWORD)(ESM_UMM_EVENT_BASE + 19)
+#define ESM_UMM_EVENT_END (DWORD)(ESM_UMM_EVENT_BASE + 29)
+
+
+/* ESMºÍPDCP Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define ESM_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 430)
+#define ESM_EPDCP_RSP_EVENT (DWORD)(ESM_EPDCP_EVENT_BASE + 9)
+#define ESM_EPDCP_EVENT_END (DWORD)(ESM_EPDCP_EVENT_BASE + 19)
+
+/*EURRCºÍEPDCPÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 450)
+#define EURRC_EPDCP_RSP_EVENT (DWORD)(EURRC_EPDCP_EVENT_BASE + 25)
+#define EURRC_EPDCP_EVENT_END (DWORD)(EURRC_EPDCP_EVENT_BASE + 49)
+
+/*EURRCºÍEURLCÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EURLC_EVENT_BASE (DWORD)(EURRC_EPDCP_EVENT_END + 1)
+#define EURRC_EURLC_RSP_EVENT (DWORD)(EURRC_EURLC_EVENT_BASE + 19)
+#define EURRC_EURLC_EVENT_END (DWORD)(EURRC_EURLC_EVENT_BASE + 29)
+
+/*EURRCºÍEUMACÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EUMAC_EVENT_BASE (DWORD)(EURRC_EURLC_EVENT_END + 1)
+#define EURRC_EUMAC_RSP_EVENT (DWORD)(EURRC_EUMAC_EVENT_BASE + 25)
+#define EURRC_EUMAC_EVENT_END (DWORD)(EURRC_EUMAC_EVENT_BASE + 49)
+
+/*EURRCºÍMEL2Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_MEL2_EVENT_BASE (DWORD)(EURRC_EUMAC_EVENT_END + 1)
+#define EURRC_MEL2_RSP_EVENT (DWORD)(EURRC_MEL2_EVENT_BASE + 4)
+#define EURRC_MEL2_EVENT_END (DWORD)(EURRC_MEL2_EVENT_BASE + 6)
+
+/*SMºÍESMÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define SM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 750) /*Added:KangShuJie*/
+#define SM_ESM_RSP_EVENT (DWORD)(SM_ESM_EVENT_BASE + 25) /*Added:KangShuJie*/
+#define SM_ESM_EVENT_END (DWORD)(SM_ESM_EVENT_BASE + 49) /*Added:KangShuJie*/
+
+/*EURRCÄÚ²¿ÏûϢʼþID*/
+#define EURRC_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1000)
+#define EURRC_EVENT_END (DWORD)(EURRC_EVENT_BASE + 54)
+
+#define EUPDCP_EURLC_EVENT_BASE (DWORD)(EURRC_EVENT_END + 1)
+#define EUPDCP_EURLC_EVENT_END (DWORD)(EUPDCP_EURLC_EVENT_BASE + 4)
+
+/*EURRCºÍL1EÄ£¿éÖ®¼äÏûϢʼþ*/
+#define EURRC_L1E_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1200)
+#define EURRC_L1E_RSP_EVENT (DWORD)(EURRC_L1E_EVENT_BASE + 20)
+#define EURRC_L1E_EVENT_END (DWORD)(EURRC_L1E_EVENT_BASE + 39)
+
+
+#define EUDBG_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1400)
+#define EUDBG_EVENT_END (DWORD)(EUDBG_EVENT_BASE + 19)
+
+#define LPP_ECID_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1450)
+#define LPP_ECID_EVENT_END (DWORD)(EVENT_PS_LTE_BASE + 1499)
+
+/* LTE¼¯³É²âÊÔ¼ÓÈëµÄ²âÊÔÄ£¿éʹÓõÄÏûÏ¢ */
+#define TRS_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1500)
+#define TRS_ESM_RSP_EVENT (DWORD)(TRS_ESM_EVENT_BASE + 9)
+#define TRS_ESM_EVENT_END (DWORD)(TRS_ESM_EVENT_BASE + 29)
+
+#define TRS_EMM_EVENT_BASE (DWORD)(TRS_ESM_EVENT_END + 1)
+#define TRS_EMM_RSP_EVENT (DWORD)(TRS_EMM_EVENT_BASE + 5)
+#define TRS_EMM_EVENT_END (DWORD)(TRS_EMM_EVENT_BASE + 29)
+
+#define ENB_EMM_ESM_EVENT_BASE (DWORD)(TRS_EMM_EVENT_END + 1)
+#define ENB_EMM_ESM_RSP_EVENT (DWORD)(ENB_EMM_ESM_EVENT_BASE + 9)
+#define ENB_EMM_ESM_EVENT_END (DWORD)(ENB_EMM_ESM_EVENT_BASE + 19)
+
+#define ENB_RRC_EMM_EVENT_BASE (DWORD)(ENB_EMM_ESM_EVENT_END + 1)
+#define ENB_RRC_EMM_RSP_EVENT (DWORD)(ENB_RRC_EMM_EVENT_BASE + 9)
+#define ENB_RRC_EMM_EVENT_END (DWORD)(ENB_RRC_EMM_EVENT_BASE + 19)
+
+#define ENB_RRC_EVENT_BASE (DWORD)(ENB_RRC_EMM_EVENT_END + 1)
+#define ENB_RRC_RSP_EVENT (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENB_RRC_EVENT_END (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+/* LTE ¼¯³É²âÊÔÊý¾ÝÃæÔö¼ÓµÄÏûÏ¢ÆðʼºêADD BY LIUZHIPENG AT 09-12-28 */
+
+#define ENRRC_ENPDCP_EVENT_BASE (DWORD)(ENB_RRC_EVENT_END + 1)
+#define ENRRC_ENPDCP_RSP_EVENT (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 20)
+#define ENRRC_ENPDCP_EVENT_END (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 44)
+/* EDCP Ó²¼þ¼ÓËÙ½Ó¿ÚÏûÏ¢ */
+#define PS_ENDCP_EVENT_BASE (DWORD)(ENRRC_ENPDCP_EVENT_END + 1)
+#define PS_ENDCP_RSP_EVENT (DWORD)(PS_ENDCP_EVENT_BASE + 9)
+#define PS_ENDCP_EVENT_END (DWORD)(PS_ENDCP_EVENT_BASE + 19)
+
+/* ENPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENPDCP_TIMER_EVENT_BASE (DWORD)(PS_ENDCP_EVENT_END + 1)
+#define ENPDCP_TIMER_EVENT_END (DWORD)(ENPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENRLC_TIMER_EVENT_BASE (DWORD)(ENPDCP_TIMER_EVENT_END + 1)
+#define ENRLC_TIMER_EVENT_END (DWORD)(ENRLC_TIMER_EVENT_BASE + 9)
+
+/* ENRRCÓëENRLCµÄÏûÏ¢¿Õ¼ä */
+#define ENRRC_ENRLC_EVENT_BASE (DWORD)(ENRLC_TIMER_EVENT_END + 1)
+#define ENRRC_ENRLC_RSP_EVENT (DWORD)(ENRRC_ENRLC_EVENT_BASE + 9)
+#define ENRRC_ENRLC_EVENT_END (DWORD)(ENRRC_ENRLC_EVENT_BASE + 19)
+/* ENMACÓëEPHYµÄÏûÏ¢¿Õ¼ä*/
+#define ENMAC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENRLC_EVENT_END + 1)
+#define ENMAC_EPHY_RSP_EVENT (DWORD)(ENMAC_EPHY_EVENT_BASE + 9)
+#define ENMAC_EPHY_EVENT_END (DWORD)(ENMAC_EPHY_EVENT_BASE + 19)
+
+#define ENRRC_ENMAC_EVENT_BASE (DWORD)(ENMAC_EPHY_EVENT_END + 1)
+#define ENRRC_ENMAC_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 9)
+#define ENRRC_ENMAC_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 19)
+
+#define ENRRC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENMAC_EVENT_END + 1)
+#define ENRRC_EPHY_RSP_EVENT (DWORD)(ENRRC_EPHY_EVENT_BASE + 9)
+#define ENRRC_EPHY_EVENT_END (DWORD)(ENRRC_EPHY_EVENT_BASE + 19)
+
+#define TRS_EPHY_EVENT_BASE (DWORD)(ENRRC_EPHY_EVENT_END + 1)
+#define TRS_EPHY_RSP_EVENT (DWORD)(TRS_EPHY_EVENT_BASE + 10)
+#define TRS_EPHY_EVENT_END (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+
+#define TRS_ENMAC_EVENT_BASE (DWORD)(TRS_EPHY_EVENT_END + 1)
+#define TRS_ENMAC_RSP_EVENT (DWORD)(TRS_ENMAC_EVENT_BASE + 10)
+#define TRS_ENMAC_EVENT_END (DWORD)(TRS_ENMAC_EVENT_BASE + 19)
+
+#define ENPDI_ENPDCP_EVENT_BASE (DWORD)(TRS_ENMAC_EVENT_END + 1)
+#define ENPDI_ENPDCP_RSP_EVENT (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 10)
+#define ENPDI_ENPDCP_EVENT_END (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 19)
+
+#define TRS_SIMULPDI_EVENT_BASE (DWORD)(ENPDI_ENPDCP_EVENT_END + 1)
+#define TRS_SIMULPDI_RSP_EVENT (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define TRS_SIMULPDI_EVENT_END (DWORD)(TRS_SIMULPDI_EVENT_BASE + 19)
+
+#define TRS_SIMULENPDI_EVENT_BASE (DWORD)(TRS_SIMULPDI_EVENT_END + 1)
+#define TRS_SIMULENPDI_RSP_EVENT (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define TRS_SIMULENPDI_EVENT_END (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 19)
+
+/* =========================================================================
+ TRS --ΪÁËGCF²âÊÔ¶ø¶¨Òå2010/3/3 SHIFANGMING
+=========================================================================*/
+#define LTE_GCF_TRS_EVENT_BASE (DWORD)(TRS_SIMULENPDI_EVENT_END + 1)
+#define LTE_GCF_TRS_RSP_EVENT (DWORD)(LTE_GCF_TRS_EVENT_BASE + 10)
+#define LTE_GCF_TRS_EVENT_END (DWORD)(LTE_GCF_TRS_EVENT_BASE + 19)
+
+#define LTE_GCF_TIMER_EVENT_BASE (DWORD)(LTE_GCF_TRS_EVENT_END + 1)
+#define LTE_GCF_TIMER_EVENT_END (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 19)
+
+
+/*TRSºÍENRLCÄ£¿éÖ®¼äµÄÏûϢʼþ2010/3/1 LIUHUAN*/
+#define TRS_ENRLC_EVENT_BASE (DWORD)(LTE_GCF_TIMER_EVENT_END + 1)
+#define TRS_ENRLC_RSP_EVENT (DWORD)(TRS_ENRLC_EVENT_BASE + 10)
+#define TRS_ENRLC_EVENT_END (DWORD)(TRS_ENRLC_EVENT_BASE + 19)
+
+#define ENPDCP_ENRLC_EVENT_BASE (DWORD)(TRS_ENRLC_EVENT_END + 1)
+#define ENPDCP_ENRLC_EVENT_END (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 9)
+
+//--ENMEL2ÏûϢʼþ
+#define ENMEL2_EVENT_BASE (DWORD)(ENPDCP_ENRLC_EVENT_END + 1)
+#define ENMEL2_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5)
+#define ENMEL2_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6)
+/**************************************************PS LTE msg range end********************************************************/
+
+
+/**************************************************PS W msg range start********************************************************/
+
+/*WRLCºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_WRLC_EVENT_BASE (DWORD)(EVENT_PS_W_BASE + 1)
+#define PDCP_WRLC_EVENT_END (DWORD)(PDCP_WRLC_EVENT_BASE + 9)
+
+
+/*WRLCºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define WRLC_WRRC_EVENT_BASE (DWORD)(PDCP_WRLC_EVENT_END + 1)
+#define WRLC_WRRC_RSP_EVENT (DWORD)(WRLC_WRRC_EVENT_BASE + 30)
+#define WRLC_WRRC_EVENT_END (DWORD)(WRLC_WRRC_EVENT_BASE + 59)
+
+/*WMACºÍWRRCµÄÏûÏ¢·¶Î§(70)*/
+#define WMAC_WRRC_EVENT_BASE (DWORD)(WRLC_WRRC_EVENT_END + 1)
+#define WMAC_WRRC_RSP_EVENT (DWORD)(WMAC_WRRC_EVENT_BASE + 40)
+#define WMAC_WRRC_EVENT_END (DWORD)(WMAC_WRRC_EVENT_BASE + 69)
+
+/*WMAC-UL/DLºÍWMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define WMAC_WMAC_EVENT_BASE (DWORD)(WMAC_WRRC_EVENT_END + 1)
+#define WMAC_WMAC_EVENT_END (DWORD)(WMAC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1W_WRRC_EVENT_BASE (DWORD)(WMAC_WMAC_EVENT_END + 1)
+#define L1W_WRRC_RSP_EVENT (DWORD)(L1W_WRRC_EVENT_BASE + 30)
+#define L1W_WRRC_EVENT_END (DWORD)(L1W_WRRC_EVENT_BASE + 59)
+
+/*PDCPºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_WRRC_EVENT_BASE (DWORD)(L1W_WRRC_EVENT_END + 1)
+#define PDCP_WRRC_RSP_EVENT (DWORD)(PDCP_WRRC_EVENT_BASE + 30)
+#define PDCP_WRRC_EVENT_END (DWORD)(PDCP_WRRC_EVENT_BASE + 59)
+
+/*WRLCºÍWMACµÄÏûÏ¢·¶Î§(20)*/
+#define WRLC_WMAC_EVENT_BASE (DWORD)(PDCP_WRRC_EVENT_END + 1)
+#define WRLC_WMAC_EVENT_END (DWORD)(WRLC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWMACµÄÏûÏ¢·¶Î§(10)*/
+#define WMAC_L1W_EVENT_BASE (DWORD)(WRLC_WMAC_EVENT_END + 1)
+#define WMAC_L1W_EVENT_END (DWORD)(WMAC_L1W_EVENT_BASE + 9)
+
+/*WRRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define WRRC_EVENT_BASE (DWORD)(WMAC_L1W_EVENT_END + 1)
+#define WRRC_EVENT_END (DWORD)(WRRC_EVENT_BASE + 99)
+
+/*L1WÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1W_EVENT_BASE (DWORD)(WRRC_EVENT_END + 1)
+#define L1W_EVENT_END (DWORD)(L1W_EVENT_BASE + 19)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_WAS_EVENT_BASE (DWORD)(L1W_EVENT_END + 1)
+#define ASC_WAS_RSP_EVENT (DWORD)(ASC_WAS_EVENT_BASE + 50)
+#define ASC_WAS_EVENT_END (DWORD)(ASC_WAS_EVENT_BASE + 99)
+
+/*WÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§140()*/
+
+#define WRRC_TIMER_EVENT_BASE (DWORD)(ASC_WAS_EVENT_END + 1)
+#define WRRC_TIMER_EVENT_END (DWORD)(WRRC_TIMER_EVENT_BASE + 79)
+
+#define WRLC_TIMER_EVENT_BASE (DWORD)(WRRC_TIMER_EVENT_END + 1)
+#define WRLC_TIMER_EVENT_END (DWORD)(WRLC_TIMER_EVENT_BASE + 19)
+
+#define WMAC_TIMER_EVENT_BASE (DWORD)(WRLC_TIMER_EVENT_END + 1)
+#define WMAC_TIMER_EVENT_END (DWORD)(WMAC_TIMER_EVENT_BASE + 19)
+
+#define L1W_TIMER_EVENT_BASE (DWORD)(WMAC_TIMER_EVENT_END + 1)
+#define L1W_TIMER_EVENT_END (DWORD)(L1W_TIMER_EVENT_BASE + 19)
+
+/*W²âÊÔÏûÏ¢·¶Î§(40)*/
+
+#define WSIR_TEST_EVENT_BASE (DWORD)(L1W_TIMER_EVENT_END + 1)
+#define WSIR_TEST_EVENT_END (DWORD)(WSIR_TEST_EVENT_BASE + 9)
+
+#define NWRLC_EVENT_BASE (DWORD)(WSIR_TEST_EVENT_END + 1)
+#define NWRLC_EVENT_END (DWORD)(NWRLC_EVENT_BASE + 19)
+
+#define NWMAC_EVENT_BASE (DWORD)(NWRLC_EVENT_END + 1)
+#define NWMAC_EVENT_END (DWORD)(NWMAC_EVENT_BASE + 9)
+
+/*º¯ÊýÐÅÁî¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define WRRC_FUNC_EVENT_BASE (DWORD)(NWMAC_EVENT_END + 1)
+#define WRRC_FUNC_EVENT_END (DWORD)(WRRC_FUNC_EVENT_BASE + 49)
+
+/*º¯Êý·µ»ØÖµ¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define RRC_FUNC_TRACE_BASE (DWORD)(WRRC_FUNC_EVENT_END + 1)
+#define RRC_FUNC_TRACE_END (DWORD)(RRC_FUNC_TRACE_BASE + 49)
+
+/**************************************************PS W msg range end********************************************************/
+/* ========================================================================
+ CM-MM/GMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 0)
+#define CM_EST_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 1)
+#define CM_REL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 2)
+#define CM_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 3)
+#define CM_CANCEL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 4)
+#define CM_REEST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 5)
+#define CM_CMSRV_IND_EV (DWORD)(CM_MM_EVENT_BASE + 6)
+#define CM_IN_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 7)
+#define CM_OUT_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 8)
+#define CM_DATA_IND_EV (DWORD)(CM_MM_EVENT_BASE + 9)
+#define CM_RATCHG_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 10)
+#define CM_RATCHG_END_IND_EV (DWORD)(CM_MM_EVENT_BASE + 11)
+#define CM_RRC_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 12)
+#define CM_SRVCC_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 13)
+#define CM_SRVCC_SUCC_IND_EV (DWORD)(CM_MM_EVENT_BASE + 14)
+#define CM_SRVCC_FAIL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 15)
+#define CM_SM_ONLY_ONE_EPDNCON_EV (DWORD)(CM_MM_EVENT_BASE + 16)
+#define CM_ESM_DETACH_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 17)
+#define CM_SM_DEACT_NON_EMERGENCY_EV (DWORD)(CM_MM_EVENT_BASE + 18)
+#define CC_UMM_RETURN_IMS_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 19)
+#define UMM_CC_RETURN_IMS_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 20)
+/*IVSÏ߳̽ÓÊÕÏûÏ¢*/
+#define IVS_DL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 21)
+#define CC_IVS_RESET_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 22)
+#define CC_IVS_MSD_IND_EV (DWORD)(CM_MM_EVENT_BASE + 23)
+/*IVS·¢¸øCC*/
+#define IVS_CC_MSD_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 24)
+#define IVS_CC_MSD_STATE_IND_EV (DWORD)(CM_MM_EVENT_BASE + 25)
+
+#define PSAP_UL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 26)
+
+/* ========================================================================
+ UMM£MM/GMM/EMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 0)
+#define UMM_DETACH_REQ_EV (DWORD)(UMM_EVENT_BASE + 1)
+#define UMM_PENDING_REQ_EV (DWORD)(UMM_EVENT_BASE + 2)
+#define UMM_RESUME_REQ_EV (DWORD)(UMM_EVENT_BASE + 3)
+#define UMM_ABORT_REQ_EV (DWORD)(UMM_EVENT_BASE + 4)
+#define UMM_EMERGENCY_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 5)
+#define UMM_CSEST_REQ_EV (DWORD)(UMM_EVENT_BASE + 6)
+#define UMM_PAGE_IND_EV (DWORD)(UMM_EVENT_BASE + 7)
+#define UMM_CCO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 8)
+#define UMM_HO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 9)
+#define UMM_CELL_RESEL_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 10)
+#define UMM_LU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 11)
+#define UMM_FAIL_IND_EV (DWORD)(UMM_EVENT_BASE + 12)
+#define UMM_RU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 13)
+#define UMM_DETACH_IND_EV (DWORD)(UMM_EVENT_BASE + 14)
+#define UMM_DETACH_CNF_EV (DWORD)(UMM_EVENT_BASE + 15)
+#define UMM_MM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 16)
+#define UMM_GMM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 17)
+#define UMM_EMERGENCY_T3412_EXPIRY_IND_EV (DWORD)(UMM_EVENT_BASE + 18)
+#define UMM_CELL_NO_CHG_IND_EV (DWORD)(UMM_EVENT_BASE + 19)
+#define UMM_CS_EST_REJ_EV (DWORD)(UMM_EVENT_BASE + 20)
+#define UMM_CS_SRV_NOTIFY_IND_EV (DWORD)(UMM_EVENT_BASE + 21)
+#define UMM_CCO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 22)
+#define UMM_HO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 23)
+#define UMM_CELL_RESEL_END_IND_EV (DWORD)(UMM_EVENT_BASE + 24)
+#define UMM_ATTACH_STATE_SYNC_REQ_EV (DWORD)(UMM_EVENT_BASE + 25)
+#define UMM_CHECK_REL_RRC_REQ_EV (DWORD)(UMM_EVENT_BASE + 26)
+#define UMM_PS_CONTEXT_IND_EV (DWORD)(UMM_EVENT_BASE + 27)
+#define UMM_START_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 28)
+#define UMM_STOP_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 29)
+#define UMM_POWEROFF_IND_RV (DWORD)(UMM_EVENT_BASE + 30)
+#define UMM_SWITCH_CARD_END_EV (DWORD)(UMM_EVENT_BASE + 31)
+/* ========================================================================
+ UMM£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_ASC_CAMPON_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 0)
+#define UMM_ASC_CAMPON_ANYCELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 1)
+#define UMM_ASC_UPDATE_PLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 2)
+#define UMM_ASC_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 3)
+#define UMM_ASC_SWITCH_RADIO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 4)
+#define UMM_ASC_TRY_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 5)
+#define UMM_ASC_STOP_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 6)
+#define UMM_ASC_PCH_PRE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 7)
+#define UMM_ASC_ABORT_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 8)
+#define UMM_ASC_UPDATE_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 9)
+#define UMM_ASC_INACTIVE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 10)
+#define UMM_ASC_PAGE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 11)
+#define UMM_ASC_LOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 12)
+#define UMM_ASC_UNLOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 13)
+#define UMM_ASC_GSM_SRV_NOTIFY_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 14)
+#define UMM_ASC_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 15)
+#define UMM_ASC_UPDATE_SYSCONFIG_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 16)
+#define UMM_ASC_UPDATE_LTE_ACT_EV (DWORD)(UMM_ASC_EVENT_BASE + 17)
+#define UMM_ASC_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(UMM_ASC_EVENT_BASE + 18)
+#define UMM_ASC_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 19)
+#define UMM_ASC_STOP_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 20)
+#define UMM_ASC_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 21)
+#define UMM_ASC_SYS_CAMP_LTESUBACT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 22)
+#define UMM_ASC_DELFORBIDDENLAILIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 23)
+#define UMM_ASC_HPPLMN_END_IND_EV (DWORD)(UMM_ASC_EVENT_BASE + 24)
+#define UMM_ASC_XCELLINFO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 25)
+#define UMM_ASC_XCELLINFO_ABORT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 26)
+#define UMM_ASC_UPDATE_ECALLMODE_EV (DWORD)(UMM_ASC_EVENT_BASE + 27)
+
+#define UMM_ASC_CELL_INFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 0)
+#define UMM_ASC_NOCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 1)
+#define UMM_ASC_PLMN_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 2)
+#define UMM_ASC_SWITCH_RADIO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 3)
+#define UMM_ASC_CNINFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 4)
+#define UMM_ASC_TRY_HPPLMN_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 5)
+#define UMM_ASC_PLMN_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 6)
+#define UMM_ASC_INACTIVE_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 7)
+#define UMM_ASC_HO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 9)
+#define UMM_ASC_CCO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 10)
+#define UMM_ASC_CELL_RESEL_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 11)
+#define UMM_ASC_HO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 12)
+#define UMM_ASC_CCO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 13)
+#define UMM_ASC_CELL_RESEL_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 14)
+#define UMM_ASC_TRY_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 15)
+#define UMM_ASC_ABORT_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 16)
+#define UMM_ASC_LOCK_CELL_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 17)
+#define UMM_ASC_CSG_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 18)
+#define UMM_ASC_CSG_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 19)
+#define UMM_ASC_TBF_RELEASE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 20)
+#define UMM_ASC_SCAN_UE_BAND_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 21)
+#define UMM_ASC_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(UMM_ASC_RSP_EVENT + 22)
+#define UMM_ASC_CELL_UPDATE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 23) /*GRR֪ͨUMM×öСÇø¸üÐÂ*/
+#define UMM_ASC_RECONST_PSRES_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 24)
+#define UMM_ASC_SUBMODE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 25)
+#define UMM_ASC_CELL_LOST_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 26)
+#define UMM_ASC_CELL_RECOVERAGE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 27)
+#define UMM_ASC_XCELLINFO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 28)
+#define UMM_ASC_XCELLINFO_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 29)
+#define UMM_ASC_NEIGCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 30)
+#define UMM_ASC_SCAN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 31)
+/* ========================================================================
+ MM/GMM/CC£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_ASC_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 0)
+#define GMM_ASC_REL_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 1)
+#define GMM_ASC_DATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 2)
+#define GMM_ASC_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 3)
+#define GMM_ASC_GRR_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 4)
+#define GMM_ASC_GRR_INFO_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 5)
+#define GMM_ASC_LL_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 6)
+#define GMM_ASC_LL_TRIGGER_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 7)
+#define GMM_ASC_LL_SUSPEND_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 8)
+#define GMM_ASC_LL_RESUME_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 9)
+#define GMM_ASC_LL_UNITDATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 10)
+#define GMM_ASC_CLEAN_PEND_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 11)
+
+#define GMM_ASC_EST_CNF_EV (DWORD)(GMM_ASC_RSP_EVENT + 0)
+#define GMM_ASC_EST_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 1)
+#define GMM_ASC_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 2)
+#define GMM_ASC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 3)
+#define GMM_ASC_CCSYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 4)
+#define GMM_ASC_PAGE_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 5)
+#define GMM_ASC_DATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 6)
+#define GMM_ASC_SUSPEND_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 7)
+#define GMM_ASC_GSM_CC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 8)
+#define GMM_ASC_CS_RAB_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 9)
+#define GMM_ASC_GSM_CC_TCH_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 10)
+#define GMM_ASC_SAPI3_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 11)
+#define GMM_ASC_SRVCC_START_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 12)
+#define GMM_ASC_SRVCC_END_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 13)
+#define GMM_ASC_LL_UNITDATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 14)
+#define GMM_ASC_LL_TRIGGER_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 15)
+#define GMM_ASC_LL_STATUS_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 16)
+#define GMM_ASC_LL_USER_DATA_PRESENT_EV (DWORD)(GMM_ASC_RSP_EVENT + 17)
+#define GMM_ASC_GSM_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 18)
+#define GMM_ASC_UTRA_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 19)/*WCDMA*//*¶ÔÓ¦AS²ãµÄASC_TD_CURR_BEAR_IND_EVºÍASC_W_CURR_BEAR_IND_EV*/
+#define GMM_ASC_PSHO_INFO_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 20) /*LLC֪ͨGMMÇл»Ïà¹Ø¼ÓÃÜËã·¨ ASC£>GMM*/
+#define GMM_ASC_SEND_CMP_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 21)
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* ========================================================================
+ ASC£TD ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->UCSR*/
+#define ASC_TD_SWITCH_RADIO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 0)
+#define ASC_TD_CAMPON_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 1)
+#define ASC_TD_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 2)
+#define ASC_TD_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 3)
+#define ASC_TD_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 4)
+#define ASC_TD_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 5)
+#define ASC_TD_TRY_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 6)
+#define ASC_TD_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 7)
+#define ASC_TD_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_UAS_EVENT_BASE + 8)
+#define ASC_TD_IRAT_CAMPON_REJ_EV (DWORD)(ASC_UAS_EVENT_BASE + 9)
+#define ASC_TD_IRAT_CAMPON_CNF_EV (DWORD)(ASC_UAS_EVENT_BASE + 10)
+#define ASC_TD_ABORT_RSP_EV (DWORD)(ASC_UAS_EVENT_BASE + 11)
+
+/*NAS->ASC->AS*/
+#define ASC_TD_LOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 12)
+#define ASC_TD_UNLOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 13)
+#define ASC_TD_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 14)
+#define ASC_TD_DATA_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 15)
+#define ASC_TD_REL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 16)
+#define ASC_TD_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 17)
+#define ASC_TD_PAGE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 18)
+#define ASC_TD_INACTIVE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 19)
+#define ASC_TD_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 20)
+#define ASC_TD_NO_DRX_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 21)
+#define ASC_TD_DRX_RSV_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 22)
+#define ASC_TD_STOP_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 23)
+#define ASC_TD_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 24)
+#define ASC_TD_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 25)
+#define ASC_TD_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 26)
+#define ASC_TD_XCELLINFO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 27)
+#define ASC_TD_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 28)
+
+/*UCSR->ASC */
+#define ASC_TD_SWITCH_RADIO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 0)
+#define ASC_TD_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 1)
+#define ASC_TD_IRAT_CAMPON_REQ_EV (DWORD)(ASC_UAS_RSP_EVENT + 2)
+#define ASC_TD_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 3)
+#define ASC_TD_TRY_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 4)
+
+#define ASC_TD_NOCELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 5)
+#define ASC_TD_PLMN_LIST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 6)
+#define ASC_TD_PLMN_LIST_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 7)
+#define ASC_TD_TRY_HPPLMN_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 8)
+#define ASC_TD_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 9)
+#define ASC_TD_ABORT_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 10)
+#define ASC_TD_SUBMODE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 11)
+#define ASC_TD_LOCK_CELL_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 12)
+#define ASC_TD_SCAN_UE_BAND_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 13)
+
+/*UCSR->ASC or UCER->ASC*/
+#define ASC_TD_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_UAS_RSP_EVENT + 14)
+#define ASC_TD_INACTIVE_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 15)
+#define ASC_TD_EST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 16)
+#define ASC_TD_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 17)
+#define ASC_TD_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 18)
+#define ASC_TD_PAGING_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 19)
+#define ASC_TD_SYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 20)
+#define ASC_TD_PCH_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 21)
+#define ASC_TD_UURLC_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 22)
+#define ASC_TD_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 23)
+#define ASC_TD_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 24)
+#define ASC_TD_SRVCC_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 25)
+#define ASC_TD_SRVCC_END_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 26)
+#define ASC_TD_CCSYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 27)
+#define ASC_TD_CS_RAB_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 28)
+#define ASC_TD_CNINFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 29)
+
+/* URBC->ASC */
+#define ASC_TD_CURR_BEAR_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 30)
+#define ASC_TD_RECONST_PSRES_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 31)
+#define ASC_TD_CELL_LOST_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 32)
+#define ASC_TD_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 33)
+
+/*UCSR->ASC add*/
+#define ASC_TD_XCELLINFO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 34)
+#define ASC_TD_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 35)
+#define ASC_TD_XCELLINFO_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 36)
+
+/* ========================================================================
+ ASC£WCDMA ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->WCSR*/
+#define ASC_W_SWITCH_RADIO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 0)
+#define ASC_W_CAMPON_CELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 1)
+#define ASC_W_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 2)
+#define ASC_W_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 3)
+#define ASC_W_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 4)
+#define ASC_W_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 5)
+#define ASC_W_TRY_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 6)
+#define ASC_W_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 7)
+#define ASC_W_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_WAS_EVENT_BASE + 8)
+#define ASC_W_IRAT_CAMPON_REJ_EV (DWORD)(ASC_WAS_EVENT_BASE + 9)
+#define ASC_W_IRAT_CAMPON_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 10)
+#define ASC_W_ABORT_RSP_EV (DWORD)(ASC_WAS_EVENT_BASE + 11)
+#define ASC_W_IRAT_INACTIVE_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 12)
+
+/*NAS->ASC->AS*/
+#define ASC_W_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 13)
+#define ASC_W_DATA_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 14)
+#define ASC_W_REL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 15)
+#define ASC_W_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 16)
+#define ASC_W_PAGE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 17)
+#define ASC_W_INACTIVE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 18)
+#define ASC_W_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 19)
+#define ASC_W_NO_DRX_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 20)
+#define ASC_W_DRX_RSV_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 21)
+#define ASC_W_STOP_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 22)
+#define ASC_W_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 23)
+#define ASC_W_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 24)
+#define ASC_W_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 25)
+#define ASC_W_XCELLINFO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 26)
+#define ASC_W_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 27)
+
+/*WCSR->ASC */
+#define ASC_W_SWITCH_RADIO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 0)
+#define ASC_W_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 1)
+#define ASC_W_IRAT_CAMPON_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 2)
+#define ASC_W_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 3)
+#define ASC_W_TRY_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 4)
+#define ASC_W_IRAT_INACTIVE_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 5)
+
+#define ASC_W_NOCELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 6)
+#define ASC_W_PLMN_LIST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 7)
+#define ASC_W_PLMN_LIST_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 8)
+#define ASC_W_TRY_HPPLMN_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 9)
+#define ASC_W_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 10)
+#define ASC_W_ABORT_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 11)
+#define ASC_W_SUBMODE_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 12)
+#define ASC_W_SCAN_UE_BAND_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 13)
+
+/*WCSR->ASC or WCER->ASC*/
+#define ASC_W_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_WAS_RSP_EVENT + 14)
+#define ASC_W_INACTIVE_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 15)
+#define ASC_W_EST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 16)
+#define ASC_W_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 17)
+#define ASC_W_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 18)
+#define ASC_W_PAGING_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 19)
+#define ASC_W_SYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 20)
+#define ASC_W_PCH_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 21)
+#define ASC_W_UURLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 22)
+#define ASC_W_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 23)
+#define ASC_W_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 24)
+#define ASC_W_SRVCC_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 25)
+#define ASC_W_SRVCC_END_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 26)
+#define ASC_W_CCSYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 27)
+#define ASC_W_CS_RAB_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 28)
+#define ASC_W_CNINFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 29)
+/* WRBC->ASC */
+#define ASC_W_CURR_BEAR_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 30)
+#define ASC_W_RECONST_PSRES_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 31)
+/*WCDMA*/
+#define ASC_W_UWRLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 32)
+/*WCSR/UCSR -> ASC*/
+#define ASC_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 33)
+#define ASC_UTRA_RESEL_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 34)
+#define ASC_UTRA_COMPLETE_EV (DWORD)(ASC_WAS_RSP_EVENT + 35)
+#define ASC_W_XCELLINFO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 36)
+#define ASC_W_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 37)
+#define ASC_W_XCELLINFO_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 38)
+
+/* ========================================================================
+ ASC£GSM ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->GSMAÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 0)
+#define ASC_GSM_CAMPON_CELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 1)
+#define ASC_GSM_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 2)
+#define ASC_GSM_INACTIVE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 3)
+#define ASC_GSM_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 4)
+#define ASC_GSM_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 5)
+#define ASC_GSM_TRY_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 6)
+#define ASC_GSM_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 7)
+#define ASC_GSM_UPDATE_PARAM_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 8)
+#define ASC_GSM_UPDATE_EPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 9)
+#define ASC_GSM_GSM_SRV_NOTIFY_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 10)
+#define ASC_GSM_PCHPRE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 11)
+#define ASC_GSM_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 12)
+#define ASC_GSM_EST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 13)
+#define ASC_GSM_DATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 14)
+#define ASC_GSM_REL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 15)
+#define ASC_GSM_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 16)
+#define ASC_GSM_INFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 17)
+#define ASC_GSM_ABORT_RSP_EV (DWORD)(ASC_GAS_EVENT_BASE + 18)
+
+/*ASC->GSMAµÄ,GSMAÊÊÅäLLCµÄÏûϢʼþºÅ*/
+#define ASC_LLC_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 19)
+#define ASC_LLC_TRIGGER_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 20)
+#define ASC_LLC_SUSPEND_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 21)
+#define ASC_LLC_RESUME_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 22)
+#define ASC_LLC_UNITDATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 23)
+#define ASC_SNP_GMM_SEQ_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 24)
+
+//ÁÚÇøÐÅÏ¢»ñÈ¡ÏûÏ¢
+#define ASC_GSM_XCELLINFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 25)
+#define ASC_GSM_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 26)
+
+/*GSMA->ASCÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 0)
+#define ASC_GSM_CELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 1)
+#define ASC_GSM_NOCELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 2)
+#define ASC_GSM_INACTIVE_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 3)
+#define ASC_GSM_PLMN_LIST_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 4)
+#define ASC_GSM_PLMN_LIST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 5)
+#define ASC_GSM_ABORT_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 6)
+#define ASC_GSM_TRY_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 7)
+#define ASC_GSM_TRY_HPPLMN_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 8)
+#define ASC_GSM_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 9)
+#define ASC_GSM_CELL_UPDATE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 10)
+#define ASC_GSM_SUBMODE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 11)
+#define ASC_GSM_EST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 12)
+#define ASC_GSM_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 13)
+#define ASC_GSM_SYNC_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 14)
+#define ASC_GSM_CCSYNC_IND_GSM_EV (DWORD)(ASC_GAS_RSP_EVENT + 15)
+#define ASC_GSM_SUSPEND_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 16)
+#define ASC_GSM_PAGE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 17)
+#define ASC_GSM_EST_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 18)
+#define ASC_GSM_DATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 19)
+#define ASC_GSM_SAPI3_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 20)
+#define ASC_GSM_CCTCH_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 21)
+#define ASC_GSM_TBF_RELEASE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 22)
+#define ASC_GSM_UTRA_CSHO_ENDIND_EV (DWORD)(ASC_GAS_RSP_EVENT + 23)
+
+#define ASC_LLC_UNITDATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 24)
+#define ASC_LLC_TRIGGER_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 25)
+#define ASC_LLC_STATUS_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 26)
+#define ASC_LLC_USER_DATA_PRESENT_EV (DWORD)(ASC_GAS_RSP_EVENT + 27)
+#define ASC_LLC_PSHO_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 28)
+
+/*GSMA->ASC->CBS (ASC͸´«)*/
+#define ASC_GSM_ETWS_NOTIFY_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 29)
+/*AS_GSM_LTE_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_REDIRECT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 30)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_RESEL_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 31)
+
+/*GSMA->ASC->SM (ASC͸´«)*/
+#define ASC_GSM_CURR_BEAR_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 32)
+#define ASC_SNP_GMM_SEQ_RSP_EV (DWORD)(ASC_GAS_RSP_EVENT + 33)
+
+/*GSMA->ASC->SMS (ASC͸´«)*/
+#define ASC_GSM_SEND_CMP_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 34)
+
+#define ASC_GSM_XCELLINFO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 35)
+#define ASC_GSM_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 36)
+#define ASC_GSM_XCELLINFO_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 37)
+
+/* ========================================================================
+ ASC£LTE ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC-->EURRC*/
+#define ASC_LTE_SWITCH_RADIO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 0)
+#define ASC_LTE_CAMPON_CELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 1)
+#define ASC_LTE_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 2)
+#define ASC_LTE_UPDATE_PLMN_FTAI_IND_EV (DWORD)(ASC_EUAS_EVENT_BASE + 3)
+#define ASC_LTE_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 4)
+#define ASC_LTE_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 5)
+#define ASC_LTE_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 6)
+#define ASC_LTE_STOP_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 7)
+#define ASC_LTE_TRY_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 8)
+#define ASC_LTE_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 9)
+#define ASC_LTE_EST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 10)
+#define ASC_LTE_EST_ABT_EV (DWORD)(ASC_EUAS_EVENT_BASE + 11)
+#define ASC_LTE_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 12)
+#define ASC_LTE_KENB_RSP_EV (DWORD)(ASC_EUAS_EVENT_BASE + 13)
+#define ASC_LTE_REL_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 14)
+#define ASC_LTE_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 15)
+#define ASC_LTE_INACTIVE_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 16)
+#define ASC_LTE_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_EUAS_EVENT_BASE + 17)
+#define ASC_LTE_DETACH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 18)
+#define ASC_LTE_GROUP_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 19)
+#define ASC_LTE_SCANSWITCH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 20)
+#define ASC_LTE_XCELLINFO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 21)
+#define ASC_LTE_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 22)
+#define ASC_LTE_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 23)
+
+/* EURRC->ASC */
+#define ASC_LTE_SWITCH_RADIO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 0)
+#define ASC_LTE_CELL_INFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 1)
+#define ASC_LTE_NOCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 2)
+#define ASC_LTE_PAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 3)
+#define ASC_LTE_PLMN_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 4)
+#define ASC_LTE_PLMN_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 5)
+#define ASC_LTE_CSG_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 6)
+#define ASC_LTE_CSG_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 7)
+#define ASC_LTE_TRY_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 8)
+#define ASC_LTE_TRY_HPPLMN_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 9)
+#define ASC_LTE_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 10)
+#define ASC_LTE_ABORT_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 11)
+#define ASC_LTE_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 13)
+#define ASC_LTE_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 14)
+#define ASC_LTE_DATA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 15)
+#define ASC_LTE_EST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 16)
+#define ASC_LTE_EST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 17)
+#define ASC_LTE_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 18)
+#define ASC_LTE_ABA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 19)
+#define ASC_LTE_DRB_SETUP_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 20)
+#define ASC_LTE_TRANS_FAIL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 21)
+#define ASC_LTE_KENB_REQ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 22)
+#define ASC_LTE_UE_INFO_CHANGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 23)
+#define ASC_LTE_DATA_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 24)
+#define ASC_LTE_SEC_PARA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 25)
+#define ASC_LTE_INACTIVE_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 26)
+#define ASC_LTE_ABORT_RSP_EV (DWORD)(ASC_EUAS_RSP_EVENT + 27)
+/*AS_LTE_TD_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_REDIRECT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 28)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_RESEL_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 29)
+#define ASC_LTE_SRVCC_START_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 30)
+#define ASC_LTE_SRVCC_END_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 31)
+#define ASC_LTE_CMAS_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 32)
+#define ASC_LTE_SCAN_UE_BAND_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 33)
+#define ASC_LTE_CELL_LOST_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 34)
+#define ASC_LTE_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 35)
+#define ASC_LTE_GROUP_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 36)
+#define ASC_LTE_TGCCH_MSG_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 37)
+#define ASC_LTE_SCANGROUPINFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 38)
+#define ASC_LTE_SET_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 39)
+#define ASC_LTE_REL_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 40)
+#define ASC_LTE_XCELLINFO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 41)
+#define ASC_LTE_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 42)
+#define ASC_LTE_XCELLINFO_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 43)
+#define ASC_LTE_NEIGCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 44)
+#define ASC_LTE_SCAN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 45)
+/* ========================================================================
+ ASC£¸÷AS¹«¹²ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*LTE->UTRAÖØÑ¡*/
+#define AS_LTE_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 0)
+#define AS_LTE_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 1)
+#define AS_LTE_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 2)
+
+/*LTE->UTRAÖض¨Ïò*/
+#define AS_LTE_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 3)
+#define AS_LTE_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 4)
+#define AS_LTE_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 5)
+
+/*LTE->UTRA PSÇл»*/
+#define AS_LTE_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 6)
+#define AS_LTE_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 7)
+#define AS_LTE_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 8)
+
+/*LTE->GSMÖØÑ¡*/
+#define AS_LTE_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 9)
+#define AS_LTE_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 10)
+#define AS_LTE_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 11)
+
+/*LTE->GSMÖض¨Ïò*/
+#define AS_LTE_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 12)
+#define AS_LTE_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 13)
+#define AS_LTE_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 14)
+
+/*LTE->TD CSÇл»*/
+#define AS_LTE_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 15)
+#define AS_LTE_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 16)
+#define AS_LTE_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 17)
+
+/*LTE->GSM CCO*/
+#define AS_LTE_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 18)
+#define AS_LTE_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 19)
+#define AS_LTE_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 20)
+
+/*LTE->GSM PSÇл»*/
+#define AS_LTE_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 21)
+#define AS_LTE_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 22)
+#define AS_LTE_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 23)
+
+/*UTRA->LTEÖØÑ¡*/
+#define AS_UTRA_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 24)
+#define AS_UTRA_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 25)
+#define AS_UTRA_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 26)
+
+/*UTRA->LTEÖض¨Ïò*/
+#define AS_UTRA_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 27)
+#define AS_UTRA_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 28)
+#define AS_UTRA_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 29)
+
+/*UTRA->LTE PSÇл»*/
+#define AS_UTRA_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 30)
+#define AS_UTRA_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 31)
+#define AS_UTRA_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 32)
+
+/*UTRA->GSMÖØÑ¡*/
+#define AS_UTRA_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 33)
+#define AS_UTRA_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 34)
+#define AS_UTRA_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 35)
+
+/*UTRA>GSMÖض¨Ïò*/
+#define AS_UTRA_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 36)
+#define AS_UTRA_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 37)
+#define AS_UTRA_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 38)
+
+/*UTRA->GSM CSÇл»*/
+#define AS_UTRA_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 39)
+#define AS_UTRA_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 40)
+#define AS_UTRA_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 41)
+
+/*UTRA->GSM CCO*/
+#define AS_UTRA_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 42)
+#define AS_UTRA_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 43)
+#define AS_UTRA_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 44)
+
+/*UTRA->GSM PSÇл»*/
+#define AS_UTRA_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 45)
+#define AS_UTRA_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 46)
+#define AS_UTRA_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 47)
+
+/*UTRA->GSM Êý¾Ý°áÒÆ*/
+#define AS_UTRA_GSM_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 48)
+
+/*GSM->LTEÖØÑ¡*/
+#define AS_GSM_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 49)
+#define AS_GSM_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 50)
+#define AS_GSM_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 51)
+
+/*GSM->LTEÖض¨Ïò*/
+#define AS_GSM_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 52)
+#define AS_GSM_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 53)
+#define AS_GSM_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 54)
+
+/*GSM->LTE PSÇл»*/
+#define AS_GSM_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 55)
+#define AS_GSM_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 56)
+#define AS_GSM_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 57)
+
+/*GSM->LTE CCO*/
+#define AS_GSM_LTE_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 58)
+#define AS_GSM_LTE_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 59)
+#define AS_GSM_LTE_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 60)
+
+/*GSM->UTRAÖØÑ¡*/
+#define AS_GSM_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 61)
+#define AS_GSM_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 62)
+#define AS_GSM_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 63)
+
+/*GSM->UTRAÖض¨Ïò*/
+#define AS_GSM_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 64)
+#define AS_GSM_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 65)
+#define AS_GSM_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 66)
+
+/*GSM->UTRA CSÇл»*/
+#define AS_GSM_UTRA_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 67)
+#define AS_GSM_UTRA_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 68)
+#define AS_GSM_UTRA_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 69)
+
+/*GSM->UTRA PSÇл»*/
+#define AS_GSM_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 70)
+#define AS_GSM_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 71)
+#define AS_GSM_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 72)
+
+/*GSM->UTRA CCO*/
+#define AS_GSM_UTRA_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 73)
+#define AS_GSM_UTRA_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 74)
+#define AS_GSM_UTRA_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 75)
+
+/*GSM->UTRA Êý¾Ý°áÒÆ*/
+#define AS_GSM_UTRA_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 76)
+/*WCDMA PREDEF*/
+#define AS_GSM_UTRA_READ_PREDEF_CONF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 77)
+#define AS_GSM_UTRA_READ_PREDEF_CONF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 78)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 79)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 80)
+
+
+/*NAS->ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_UPDATE_SYSCONFIG_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 81)
+#define AS_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 82)
+
+/*ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_L1_RSRC_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 83)
+#define AS_L1_RSRC_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 84)
+#define AS_L1_RSRC_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 85)
+#define AS_L1_RSRC_FREE_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 86)
+
+/*.(UCSR EUCSR GSMA)AS->ASC*/
+#define AS_IRAT_CCO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 87)
+#define AS_IRAT_HO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 88)
+#define AS_IRAT_CELL_RESEL_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 89)
+
+#define AS_LTE_GSM_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 90)
+#define AS_LTE_GSM_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 91)
+#define AS_LTE_GSM_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 92)
+#define AS_LTE_GSM_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 93)
+
+#define AS_LTE_UTRA_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 94)
+#define AS_LTE_UTRA_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 95)
+#define AS_LTE_UTRA_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 96)
+#define AS_LTE_UTRA_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 97)
+
+#define AS_LTE_TD_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 98)
+#define AS_LTE_W_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 99)
+
+/* ========================================================================
+ CBS£ASCÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_ASC_NO_DRX_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 0)
+#define CBS_ASC_DRX_RSV_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 1)
+#define CBS_ASC_STOP_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 2)
+
+#define CBS_ASC_PCH_CELL_INFO_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 0)
+#define CBS_ASC_UURLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 1)
+#define CBS_ASC_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 2)
+#define CBS_ASC_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 3)
+#define CBS_ASC_CMAS_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 4)
+/*WCDMA*/
+#define CBS_ASC_UWRLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ GMM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_GMM_SEQ_IND_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 0)
+#define SNP_GMM_SEQ_RSP_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ GMM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDCP_GMM_NW_REL_ANYRB_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 0)
+#define GMM_PDCP_RB_CHG_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ SM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_SM_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 0)
+#define SNP_SM_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 1)
+#define SNP_SM_MOD_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 2)
+#define SNP_SM_RAT_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 3)
+#define SNP_SM_RAT_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 4)
+#define SNP_SM_RAT_SEQ_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 5)
+#define SNP_SM_RAT_CHG_COMP_EV (DWORD)(SM_SNDCP_EVENT_BASE + 6)
+
+#define SNP_SM_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 0)
+#define SNP_SM_MOD_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 1)
+#define SNP_SM_STATUS_REQ_EV (DWORD)(SM_SNDCP_RSP_EVENT + 2)
+#define SNP_SM_RAT_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 3)
+#define SNP_SM_RAT_SEQ_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 4)
+#define SNP_SM_RAT_DEACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 5)
+
+/* ========================================================================
+ TAF£CCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_TAF_CONNECT_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 0)
+#define CC_TAF_CONNECT_CNF_EV (DWORD)(CC_TAF_EVENT_BASE + 1)
+#define CC_TAF_CONNECT_CNF_NEG_EV (DWORD)(CC_TAF_EVENT_BASE + 2)
+#define CC_TAF_RELEASE_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 3)
+#define CC_TAF_RELEASE_IND_EV (DWORD)(CC_TAF_EVENT_BASE + 4)
+#define CC_TAF_PEND_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 5)
+#define CC_TAF_RESUME_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS-UMMÖ®¼äµÄÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define UMM_CBS_START_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 0)
+#define UMM_CBS_STOP_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 1)
+
+#define UMM_CBS_CELL_INFO_IND_EV (DWORD)(UMM_CBS_RSP_EVENT + 0)
+
+/* ========================================================================
+ URRC/CC£SCIÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CSCI_CONFIG_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 0)
+#define CSCI_CDEC_CTRL_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 1)
+#define CSCI_CONFIG_REL_EV (DWORD)(AP_SCI_EVENT_BASE + 2)
+#define CSCI_CONFIG_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 3)
+#define CSCI_UNRECOVER_ERR_EV (DWORD)(AP_SCI_EVENT_BASE + 4)
+#define CSCI_CDEC_CTRL_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 5)
+
+/* ========================================================================
+ URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_READ_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 0)
+#define URRC_READ_SYSINFO_IND_EV (DWORD)(URRC_EVENT_BASE + 1)
+#define URRC_READ_SYSINFO_REJ_EV (DWORD)(URRC_EVENT_BASE + 2)
+#define URRC_STOP_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 3)
+#define URRC_READ_DYN_SIB_REQ_EV (DWORD)(URRC_EVENT_BASE + 4)
+#define URRC_READ_DYN_SIB_CNF_EV (DWORD)(URRC_EVENT_BASE + 5)
+#define URRC_SIB_MODIFIED_IND_EV (DWORD)(URRC_EVENT_BASE + 6)
+#define URRC_CELLUPDATE_REQ_EV (DWORD)(URRC_EVENT_BASE + 7)
+#define URRC_CELL_RESEL_REQ_EV (DWORD)(URRC_EVENT_BASE + 8)
+#define URRC_CELL_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 9)
+#define URRC_REL_CONN_REQ_EV (DWORD)(URRC_EVENT_BASE + 10)
+#define URRC_RESUME_CELL_REQ_EV (DWORD)(URRC_EVENT_BASE + 11)
+#define URRC_RPLMN_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 12)
+#define URRC_RESOURE_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 13)
+#define URRC_RESOURCE_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 14)
+#define URRC_UPDATE_EPLMN_REQ_EV (DWORD)(URRC_EVENT_BASE + 15)
+#define URRC_HIGH_MOBILITY_IND (DWORD)(URRC_EVENT_BASE + 16)
+#define URRC_HO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 17)
+#define URRC_HO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 18)
+#define URRC_HO_TO_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 19)
+#define URRC_HO_TO_UTRAN_CNF_EV (DWORD)(URRC_EVENT_BASE + 20)
+#define URRC_HO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 21)
+#define URRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 22)
+#define URRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 23)
+#define URRC_CCO_TO_UTRAN_IND_EV (DWORD)(URRC_EVENT_BASE + 24)
+#define URRC_CCO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 25)
+#define URRC_RADIO_LINK_FAIL_IND_EV (DWORD)(URRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define URRC_NEIBCELL_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 27)
+#define URRC_FACH_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 28)
+#define URRC_FACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 29)
+#define URRC_DRX_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 30)
+#define URRC_SEND_BUF_EST_REQ_EV (DWORD)(URRC_EVENT_BASE + 31)
+#define URRC_ABORT_RATCHG_REQ_EV (DWORD)(URRC_EVENT_BASE + 32)
+#define URRC_BAR_RESUME_IND_EV (DWORD)(URRC_EVENT_BASE + 33)
+#define URRC_CHG_CAMPON_TYPE_EV (DWORD)(URRC_EVENT_BASE + 34)
+#define URRC_GET_RF_REQ_EV (DWORD)(URRC_EVENT_BASE + 35) /*USIR->UCSR*/
+#define URRC_GET_RF_CNF_EV (DWORD)(URRC_EVENT_BASE + 36) /*UCSR->USIR*/
+#define URRC_SYSINFO_CONTAINER_IND_EV (DWORD)(URRC_EVENT_BASE + 37) /*UCSR->USIR*/
+#define URRC_ETWS_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 38)
+#define URRC_ETWS_CFG_END_EV (DWORD)(URRC_EVENT_BASE + 39)
+#define URRC_ETWS_CONTINUE_REQ_EV (DWORD)(URRC_EVENT_BASE + 40)
+#define URRC_DRX_CHANGE_IND_EV (DWORD)(URRC_EVENT_BASE + 41) /*URBC->UMCR*/
+#define URRC_EFACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 42)/*UCMR->URBC*/
+#define URRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(URRC_EVENT_BASE + 43)
+#define URRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(URRC_EVENT_BASE + 44)
+#define URRC_OUT_OF_SYNC_EV (DWORD)(URRC_EVENT_BASE + 45)
+#define URRC_RESUME_IN_SYNC_EV (DWORD)(URRC_EVENT_BASE + 46)
+#define URRC_LBS_MEAS_IND (DWORD)(URRC_EVENT_BASE + 47)
+/* ========================================================================
+ URLC - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CURLC_CONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 0)
+#define CURLC_RELEASE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 1)
+#define CURLC_LOOP_TEST_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 2)
+#define CURLC_SUSPEND_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 3)
+#define CURLC_RESUME_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 4)
+#define CURLC_CONTINUE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 5)
+#define UURLC_DATA_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 6)
+#define CURLC_CBS_RBCONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 7)
+#define CURLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(URLC_URRC_EVENT_BASE + 8)
+
+#define CURLC_SUSPEND_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 0)
+#define CURLC_LOOP_TEST_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 1)
+#define UURLC_DATA_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 2)
+#define CURLC_STATUS_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 3)
+#define UURLC_DATA_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 4)
+#define CURLC_CONFIG_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 5)
+#define CURLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(URLC_URRC_RSP_EVENT + 6)
+
+/* ========================================================================
+ UMAC - URRC/UMAC - UMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 0)
+#define CUMAC_RACH_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 1)
+#define CUMAC_RNTI_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 2)
+#define CUMAC_HS_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 3)
+#define CUMAC_HS_RESET_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 4)
+#define CUMAC_TFC_CTRL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 5)
+#define CUMAC_CONFIG_ABORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 6)
+#define CUMAC_ASC_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 7)
+#define CUMAC_DEL_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 8)
+#define CUMAC_TV_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 9)
+#define CUMAC_Q_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 10)
+#define CUMAC_UE_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 11)
+#define CUMAC_TV_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 12)
+#define CUMAC_Q_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 13)
+#define CUMAC_UE_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 14)
+#define CUMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 15)
+#define CUMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 16)
+#define CUMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 17)
+#define CUMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 18)
+#define CUMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 19)
+#define CUMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 20)
+#define CUMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 21)
+#define CUMAC_CRC_RESULT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 22)
+#define CUMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 23)
+#define CUMAC_CONTINUE_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 24)
+#define CUMAC_IDLE_PERIOD_EV (DWORD)(UMAC_URRC_EVENT_BASE + 25)
+#define CUMAC_CELL_RESEL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 26)
+#define CUMAC_HSPA_EPCH_CFG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 27)
+#define CUMAC_UPDATE_ERNTI_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 28)
+
+#define CUMAC_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 0)
+#define UUMAC_PCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 1)
+#define UUMAC_BCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 2)
+#define CUMAC_CONFIG_CHG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 3)
+#define CUMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 4)
+#define CUMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 5)
+#define CUMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 6)
+#define CUMAC_TV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 7)
+#define CUMAC_Q_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 8)
+#define CUMAC_UE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 9)
+#define CUMAC_ERUCCH_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 10)
+#define CUMAC_FACH_CFG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 11)
+#define CUMAC_CELL_RESEL_CNF_EV (DWORD)(UMAC_URRC_RSP_EVENT + 12)
+/* ========================================================================
+ UMAC - UL/DL - UMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(UMAC_UMAC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1T - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_GSM_MEAS_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 0)
+#define L1T_GSM_BSIC_VERIFY_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 1)
+#define L1T_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 3)
+#define L1T_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 4)
+#define L1T_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 5)
+#define L1T_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 6)
+#define L1T_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 7)
+#define L1T_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 8)
+#define L1T_TD_GET_RF_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 9)
+#define L1T_PLMN_END_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 10)
+#define L1T_IRAT_RSRC_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 11)
+
+#define L1T_GSM_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 0)
+#define L1T_TD_GET_RF_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 1)
+#define L1T_IRAT_RSRC_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 2)
+#define L1T_LTE_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDCP - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 1)
+#define CPDCP_RELOC_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 2)
+#define CPDCP_RELOC_COMP_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 3)
+#define CPDCP_RELOC_FAIL_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 4)
+#define CPDCP_DL_PDU_SIZE_CHG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 5)
+#define CPDCP_ROHC_TARGET_MODE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 6)
+#define CPDCP_SCRI_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 7)
+#define CPDCP_FD_MONITOR_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 8)
+#define CPDCP_FD_NO_DATA_CNF_EV (DWORD)(PDCP_URRC_EVENT_BASE + 9)
+
+
+#define CPDCP_RELOC_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 0)
+#define CPDCP_CONFIG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 1)
+#define CPDCP_RELOC_REJ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 2)
+#define CPDCP_DL_PDU_SIZE_CHG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 3)
+#define CPDCP_DATA_TRANSFER_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 4)
+#define CPDCP_FD_NO_DATA_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 5)
+
+
+/* ========================================================================
+ URLC - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UUMAC_DATA_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 0)
+#define CUMAC_HS_RESET_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 2)
+#define UURLC_DL_CTRL_PDU_REQ_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 3)
+#define UURLC_MAKE_AMDPDU_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ISR_FRAME_IND_EV (DWORD)(UMAC_L1T_EVENT_BASE + 0)
+
+/* ========================================================================
+ SM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_PDCP_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 0)
+#define SM_PDCP_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 1)
+#define SM_PDCP_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 2)
+#define SM_PDCP_ACT_ALREADY_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 3)
+#define SM_PDCP_RAT_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 4)
+#define SM_PDCP_RAT_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 5)
+#define SM_PDCP_RAT_SEQ_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 6)
+#define SM_PDCP_HC_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 7)
+#define SM_PDCP_RAT_CHG_COMP_EV (DWORD)(SM_PDCP_EVENT_BASE + 8)
+#define SM_PDCP_MODIFY_CNF_EV (DWORD)(SM_PDCP_EVENT_BASE + 9)
+
+#define SM_PDCP_STATUS_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 0)
+#define SM_PDCP_RAT_ACT_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 1)
+#define SM_PDCP_RAT_SEQ_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 2)
+#define SM_PDCP_MODIFY_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDI - GSMA ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDI_GSM_DATA_REQ_EV (DWORD)(PDI_GSMA_EVENT_BASE + 0)
+
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UPDI_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 0)
+#define UPDI_DATA_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 1)
+#define CPDI_NOT_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 2)
+#define CPDI_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 3)
+#define PDI_EPDCP_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 4)
+
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UURLC_PDCP_DATA_REQ_EV (DWORD)(PDCP_URLC_EVENT_BASE + 0)
+#define UURLC_PDCP_DATA_IND_EV (DWORD)(PDCP_URLC_EVENT_BASE + 1)
+/* ========================================================================
+ PDCP - RLC ÏûÏ¢ºÅ¶¨Òå(²Î¿¼RLC - RRC)
+======================================================================== */
+
+
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_BCH_READ_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 1)
+#define P_BCH_OPEN_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 2)
+#define P_BCH_RELEASE_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 3)
+
+#define P_SFN_DECODE_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 1)
+#define P_BCH_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 2)
+#define P_BCH_OPEN_REJ_EV (DWORD)(USIR_UPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ UCSR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_FREQUENCY_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 1)
+#define P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 2)
+#define P_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 3)
+#define P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 4)
+#define P_CAMPON_A_CELL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 5)
+#define P_TD_REL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 6)
+#define P_TD_RESET_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 7)
+#define P_TD_SLEEP_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 8)
+#define P_TD_SET_IRAT_MODE_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 9)
+
+#define P_FREQUENCY_SCAN_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 1)
+#define P_CELL_SEARCH_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 2)
+#define P_TD_RESET_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 3)
+#define P_TD_REL_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMCR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 1)
+#define P_INTER_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 2)
+#define P_MEAS_REL_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 5)
+#define P_FMO_INFO_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 6)
+
+#define P_INTRA_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 1)
+#define P_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 2)
+#define P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 3)
+#define P_DETECT_CELL_INFO_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 4)
+#define P_SERVCELL_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 7)
+/* ========================================================================
+ URBC - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 1)
+#define P_DL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 2)
+#define P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 3)
+#define P_UL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 4)
+#define P_DL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 5)
+#define P_UL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 6)
+#define P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 7)
+#define P_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 8)
+#define P_STOP_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 9)
+#define P_ADD_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 10)
+#define P_REL_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 11)
+#define P_REL_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 12)
+#define P_ADD_MODIFY_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 13)
+#define P_STOP_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 14)
+#define P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(URBC_UPHY_EVENT_BASE + 15)
+#define P_ADD_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 16)
+#define P_REL_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 17)
+#define P_PLCCH_ADD_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 18)
+#define P_HSPA_PLUS_FACH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 19)
+#define P_HSPA_PLUS_PCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 20)
+#define P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 21)
+#define P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 22)
+#define P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 23)
+#define P_UL_PHY_CH_CTRL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 24)
+
+#define P_DL_RL_SETUP_MODIFY_CNF_EV (DWORD)(URBC_UPHY_RSP_EVENT + 1)
+#define P_IN_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 2)
+#define P_OUT_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 3)
+#define P_UL_ESTABLISH_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMAC_UL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_RACH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 0)
+#define P_DL_DATA_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 1)
+#define P_TFC_POWER_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 2)
+#define P_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 3)
+#define P_UL_DATA_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 4)
+#define P_ABORT_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 5)
+#define P_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 6)
+#define P_ERUCCH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 7)
+#define P_ABORT_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 8)
+#define P_SET_AGCH_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 9)
+#define P_CELL_RESEL_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 10)
+#define P_CELL_RESEL_CNF_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 11)
+#define P_SYNC_CMD_RESP_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 12)
+/* ========================================================================
+ UMAC_DL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_QUALITY_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 0)
+#define P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 1)
+#define P_QUALITY_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 2)
+#define P_UE_INTERNAL_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1T - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G_L1T_GSM_INACT_TIME_IND_EV*/
+#define P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G_L1T_ABORT_GSM_GAP_REQ_EV*/
+#define P_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 3)
+#define P_CARD2_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 4) /*T_zTD_P_card2_gap_req*/
+#define P_CARD2_GAP_REL_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 5) /*T_zTD_P_card2_gap_rel_req*/
+#define P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 6) /*T_zTD_P_card2_stop_gap_req*/
+#define P_CARD1_SUSPEND_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 7) /*T_zTD_P_card1_suspend_req*/
+#define P_CARD1_RESUME_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 8) /*T_zTD_P_card1_resume_req*/
+#define P_TD_ZTPCG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 9)
+
+#define P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 1)
+#define P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 2)
+#define P_BCH_RELEASE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 3)
+#define P_CAMPON_A_CELL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 4)
+#define P_DPCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 5)
+#define P_REL_SCCPCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 6)
+#define P_STOP_PAGING_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 7)
+#define P_STOP_CBS_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 8)
+#define P_REL_HSDPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 9)
+#define P_REL_HSUPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 10)
+#define P_RACH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 11)
+#define P_ERUCCH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 12)
+#define P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 13)
+#define P_UMTS_TIMER_SNAPSHOT_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 14)
+#define P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 15)
+#define P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 16)
+#define P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 17)
+#define P_CARD2_GAP_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 18) /*T_zTD_P_card2_gap_ind*/
+#define P_CARD2_GAP_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 19) /*T_zTD_P_card2_gap_rel_cnf*/
+#define P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 20) /*T_zTD_P_card2_stop_gap_cnf*/
+#define P_CARD1_SUSPEND_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 21) /*T_zTD_P_card1_suspend_cnf*/
+#define P_TD_ZTPCG_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 22)
+
+/* ========================================================================
+ L1T ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_CHECK_RF_IND_EV (DWORD)(L1T_EVENT_BASE + 1)
+#define P_ACTIVE_IND_EV (DWORD)(L1T_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_DONE_REQ_EV (DWORD)(L1T_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1E/L1Gµ÷L1T º¯ÊýÉèÖÃÖ÷¸¨Ä£Ê½µÄº¯ÊýÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_FUNC_SET_MODE_REQ_EV (DWORD)(L1T_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T/L1E/L1WÖ®¼äÏûÏ¢ºÅ¶¨Òå(ÎïÀí²ãÊÊÅä²ãL1A)
+======================================================================== */
+#define L1_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 0)
+#define L1_GET_RF_CNF_EV (DWORD)(L1A_EVENT_BASE + 1)
+#define UTRAN_IRAT_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 2)
+#define UTRAN_BLIND_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 3)
+/*WCDMA*/
+#define L1A_FUNC_SET_MODE_REQ_EV (DWORD)(L1A_EVENT_BASE + 4)
+#define L1A_TD_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 5)/*TDÏòÖ÷ÖÆʽҪÉäƵÇëÇóÏûÏ¢*/
+#define L1A_GET_RF_FROM_TD_CNF_EV (DWORD)(L1A_EVENT_BASE + 6)/*TDÈóöÉäƵºó¸øÆäËûÖÆʽµÄ»Ø¸´ÏûÏ¢*/
+#define L1A_W_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 7)
+#define L1A_GET_RF_FROM_W_CNF_EV (DWORD)(L1A_EVENT_BASE + 8)
+#define L1A_LTE_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 9)
+#define L1A_GET_RF_FROM_LTE_CNF_EV (DWORD)(L1A_EVENT_BASE + 10)
+/*w¸¨Ä£Ï²âÁ¿Éϱ¨¹²ÓÃW_P_INTER_FREQ_MEAS_IND_EV*/
+/*** ÔSIG_CODE.HÖÐÒÆÖ²¹ýÀ´µÄÏûÏ¢ ***/
+ /* START OF DLL */
+#define L2_CONNECT_IND (DWORD)(LAPDM_EVENT_BASE + 0)
+#define L2_DATA_IND (DWORD)(LAPDM_EVENT_BASE + 1)
+#define DL_UNIT_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 2)
+#define DL_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 3)
+#define DL_ESTABLISH_REQ (DWORD)(LAPDM_EVENT_BASE + 4)
+#define DL_IRAT_HO_REQ (DWORD)(LAPDM_EVENT_BASE + 5)
+#define DL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 6)
+#define DL_RECONNECT_REQ (DWORD)(LAPDM_EVENT_BASE + 7)
+#define DL_RESUME_REQ (DWORD)(LAPDM_EVENT_BASE + 8)
+#define DL_SUSPEND_REQ (DWORD)(LAPDM_EVENT_BASE + 9)
+#define MDL_CONFIG (DWORD)(LAPDM_EVENT_BASE + 10)
+#define MDL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 11)
+#define PH_START_T200 (DWORD)(LAPDM_EVENT_BASE + 12)
+#define T200 (DWORD)(LAPDM_EVENT_BASE + 13)
+ /* END OF DLL */
+
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äBEGIN**************************/
+#define T_SI2N_AVAIL (DWORD)(GRR_EVENT_BASE + 83)
+#define T3206 (DWORD)(GRR_EVENT_BASE + 84)
+#define T3208 (DWORD)(GRR_EVENT_BASE + 85)
+#define T3210 (DWORD)(GRR_EVENT_BASE + 86)
+#define T_NCELL_VALID_TIMER (DWORD)(GRR_EVENT_BASE + 87)
+#define T_P_SI_STATUS_TIMER (DWORD)(GRR_EVENT_BASE + 88)
+#define T_CELL_SUPERVISION (DWORD)(GRR_EVENT_BASE + 89)
+#define T_PENALTY_0 (DWORD)(GRR_EVENT_BASE + 90)
+#define T_PENALTY_1 (DWORD)(GRR_EVENT_BASE + 91)
+#define T_PENALTY_2 (DWORD)(GRR_EVENT_BASE + 92)
+#define T_PENALTY_3 (DWORD)(GRR_EVENT_BASE + 93)
+#define T_PENALTY_4 (DWORD)(GRR_EVENT_BASE + 94)
+#define T_PENALTY_5 (DWORD)(GRR_EVENT_BASE + 95)
+#define T_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 96)
+#define T_RESELECTION_DELAY (DWORD)(GRR_EVENT_BASE + 97)
+#define T_SCELL_RESEL_DELAY (DWORD)(GRR_EVENT_BASE + 98)
+#define T_SYS_INFO_READ (DWORD)(GRR_EVENT_BASE + 99)
+#define T_PSI_CYCLE (DWORD)(GRR_EVENT_BASE + 100)
+#define T_NCELL_SI_READ (DWORD)(GRR_EVENT_BASE + 101)
+#define T_CALL_REEST_TIMEOUT (DWORD)(GRR_EVENT_BASE + 102)
+#define T3122 (DWORD)(GRR_EVENT_BASE + 103)
+#define T3142 (DWORD)(GRR_EVENT_BASE + 104)
+#define T3172 (DWORD)(GRR_EVENT_BASE + 105)
+#define T3200 (DWORD)(GRR_EVENT_BASE + 106)
+#define T_SYS_INFO_VALID (DWORD)(GRR_EVENT_BASE + 107)
+#define T_RXLEV_VALID (DWORD)(GRR_EVENT_BASE + 108)
+#define T_BETTER_C2 (DWORD)(GRR_EVENT_BASE + 109)
+#define T_SYNC_READ (DWORD)(GRR_EVENT_BASE + 110)
+#define T_NON_DRX (DWORD)(GRR_EVENT_BASE + 111)
+#define T_MONITOR_OLD_SCELL (DWORD)(GRR_EVENT_BASE + 112)
+#define T_TWO_IA_SUPERVISION (DWORD)(GRR_EVENT_BASE + 113)
+#define T_SENT_MEAS_REPORT (DWORD)(GRR_EVENT_BASE + 114)
+#define T_PSI_UNSOLICITED (DWORD)(GRR_EVENT_BASE + 115)
+#define T_ABN_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 116)
+#define T_ABN_CELL_RESEL_SCELL (DWORD)(GRR_EVENT_BASE + 117)
+#define T_TESTPARAM (DWORD)(GRR_EVENT_BASE + 118)
+#define T_CELL_BARRED_TIMER (DWORD)(GRR_EVENT_BASE + 119)
+#define T_CELL_SEL_IND (DWORD)(GRR_EVENT_BASE + 120)
+#define T3218 (DWORD)(GRR_EVENT_BASE + 121)
+#define T309 (DWORD)(GRR_EVENT_BASE + 122)
+#define T_BETTER_UTRAN (DWORD)(GRR_EVENT_BASE + 123)
+#define T_IR_WAIT_TIMER (DWORD)(GRR_EVENT_BASE + 124)
+#define T_IR_CELL_INVALID_TIMER (DWORD)(GRR_EVENT_BASE + 125)
+#define T3232_EV (DWORD)(GRR_EVENT_BASE + 126)
+#define T_RESELECTION_EV (DWORD)(GRR_EVENT_BASE + 127)
+#define T3230_EV (DWORD)(GRR_EVENT_BASE + 128)
+#define T_DISABLE_UMTS_MEAS_EV (DWORD)(GRR_EVENT_BASE + 129)
+#define T_DISABLE_LTE_MEAS_EV (DWORD)(GRR_EVENT_BASE + 130)
+
+#define T_IR_READ_PREDEF_CONF_TIMER (DWORD)(GRR_EVENT_BASE + 139)//¸ø¶¨Ê±Æ÷ÏûÏ¢ºÅÔ¤Áô10¸ö
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äEND*****************************/
+ /* END OF GRR */
+
+ /* START OF MAC */
+#define MAC_PDCH_REL_REQ (DWORD)(GMAC_EVENT_BASE + 0)
+#define MAC_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 1)
+#define RLC_MAC_TLLI_ASSIGN_REQ (DWORD)(GMAC_EVENT_BASE + 2)
+#define RLC_MAC_UPLINK_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 3)
+#define RLC_MAC_REL_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 4)
+#define RLC_MAC_DEACT_CNF (DWORD)(GMAC_EVENT_BASE + 5)
+#define RLC_MAC_CTRL_BLOCK_REQ (DWORD)(GMAC_EVENT_BASE + 6)
+#define GRR_MAC_CLASSMARK_IND (DWORD)(GMAC_EVENT_BASE + 7)
+#define GRR_MAC_UPDATE_PARAM_REQ (DWORD)(GMAC_EVENT_BASE + 8)
+#define GRR_MAC_FREQ_UPDATE_REQ (DWORD)(GMAC_EVENT_BASE + 9)
+#define GRR_MAC_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 10)
+#define GRR_MAC_POLLING_REQ (DWORD)(GMAC_EVENT_BASE + 11)
+#define GRR_MAC_CIRCUIT_REQ (DWORD)(GMAC_EVENT_BASE + 12)
+#define GRR_MAC_CIRCUIT_ABORT_REQ (DWORD)(GMAC_EVENT_BASE + 13)
+#define GRR_MAC_DEACT_REQ (DWORD)(GMAC_EVENT_BASE + 14)
+#define GRR_MAC_IDLE_CHN_CNF (DWORD)(GMAC_EVENT_BASE + 15)
+#define GRR_MAC_CELL_CHANGE_IND (DWORD)(GMAC_EVENT_BASE + 16)
+#define GRR_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 17)
+#define GRR_MAC_STOP_TIMER (DWORD)(GMAC_EVENT_BASE + 18)
+#define GRR_MAC_TESTPARAM_REQ (DWORD)(GMAC_EVENT_BASE + 19)
+#define GRR_MAC_SUSPEND_REQ (DWORD)(GMAC_EVENT_BASE + 20)
+#define T3126 (DWORD)(GMAC_EVENT_BASE + 21)
+#define T3146 (DWORD)(GMAC_EVENT_BASE + 22)
+#define T3162 (DWORD)(GMAC_EVENT_BASE + 23)
+#define T3164 (DWORD)(GMAC_EVENT_BASE + 24)
+#define T3166 (DWORD)(GMAC_EVENT_BASE + 25)
+#define T3168_MAC (DWORD)(GMAC_EVENT_BASE + 26)
+#define T3170 (DWORD)(GMAC_EVENT_BASE + 27)
+#define T3174 (DWORD)(GMAC_EVENT_BASE + 28)
+#define T3176 (DWORD)(GMAC_EVENT_BASE + 29)
+#define T3180 (DWORD)(GMAC_EVENT_BASE + 30)
+#define T3184 (DWORD)(GMAC_EVENT_BASE + 31)
+#define T3186 (DWORD)(GMAC_EVENT_BASE + 32)
+#define T3190 (DWORD)(GMAC_EVENT_BASE + 33)
+#define T3192 (DWORD)(GMAC_EVENT_BASE + 34)
+#define T_SINGLE_DL_BLOCK (DWORD)(GMAC_EVENT_BASE + 35)
+#define XPOLLING_RESPONSE (DWORD)(GMAC_EVENT_BASE + 36)
+#define XBLOCK_DL_RELEASE (DWORD)(GMAC_EVENT_BASE + 37)
+#define XBLOCK_UL_RELEASE (DWORD)(GMAC_EVENT_BASE + 38)
+#define GRR_MAC_T3218_EXP_EV (DWORD)(GMAC_EVENT_BASE + 39)
+#define GRR_MAC_PSHO_REQ_EV (DWORD)(GMAC_EVENT_BASE + 40)
+#define GRR_MAC_PSHO_RETURN_REQ_EV (DWORD)(GMAC_EVENT_BASE + 41)
+#define GRR_MAC_PSHO_DEACT_REQ_EV (DWORD)(GMAC_EVENT_BASE + 42)
+#define GMAC_T3216_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 43)
+#define GMAC_T_MULTI_DL_BLOCK_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 44)
+#define GMAC_T3200_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 45)
+
+ /* END OF MAC */
+
+ /* START OF RLC */
+#define RLC_WAKE_UP (DWORD)(GRLC_EVENT_BASE + 0)
+#define RLC_FILL_DATA_QUEUE (DWORD)(GRLC_EVENT_BASE + 1)
+#define RLC_START_TIMER_T3182 (DWORD)(GRLC_EVENT_BASE + 2)
+#define RLC_START_TIMER_T3168 (DWORD)(GRLC_EVENT_BASE + 3)
+#define RLC_FILL_GPRS_TEST_MODE (DWORD)(GRLC_EVENT_BASE + 4)
+#define RLC_UNEXPECTED_INPUT_RECEIVED (DWORD)(GRLC_EVENT_BASE + 5)
+#define RLC_UPL_DEBUG (DWORD)(GRLC_EVENT_BASE + 6)
+#define OM_RLC_TEST_MODE_REQ (DWORD)(GRLC_EVENT_BASE + 7)
+#define GRR_RLC_SUSPEND_REQ (DWORD)(GRLC_EVENT_BASE + 8)
+#define GRR_RLC_RESUME_REQ (DWORD)(GRLC_EVENT_BASE + 9)
+#define GRR_RLC_UPDATE_PARAM_REQ (DWORD)(GRLC_EVENT_BASE + 10)
+#define GRR_RLC_ACCESS_CNF (DWORD)(GRLC_EVENT_BASE + 11)
+#define GRR_RLC_ACCESS_REJ (DWORD)(GRLC_EVENT_BASE + 12)
+#define GRR_RLC_REL_PDCH_REQ (DWORD)(GRLC_EVENT_BASE + 13)
+#define GRR_RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 14)
+#define GRR_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 15)
+#define GRR_RLC_TBF_FAILURE (DWORD)(GRLC_EVENT_BASE + 16)
+#define GRR_RLC_TESTPARAM_REQ (DWORD)(GRLC_EVENT_BASE + 17)
+#define RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 18)
+#define RLC_UNITDATA_REQ (DWORD)(GRLC_EVENT_BASE + 19)
+#define RLC_CLEAR_QUEUE_REQ (DWORD)(GRLC_EVENT_BASE + 20)
+#define LL_RLC_RESUME_MM_REQ (DWORD)(GRLC_EVENT_BASE + 21)
+#define LL_RLC_RESUME_ALL_REQ (DWORD)(GRLC_EVENT_BASE + 22)
+#define RLC_ASSIGN_REQ (DWORD)(GRLC_EVENT_BASE + 23)
+#define RLC_RESET_REQ (DWORD)(GRLC_EVENT_BASE + 24)
+#define MAC_RLC_UPLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 25)
+#define MAC_RLC_UPLINK_PDCH_FAIL (DWORD)(GRLC_EVENT_BASE + 26)
+#define MAC_RLC_REL_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 27)
+#define MAC_RLC_UPLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 28)
+#define MAC_RLC_UPLINK_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 29)
+#define MAC_RLC_DOWNLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 30)
+#define MAC_RLC_DATA_IND (DWORD)(GRLC_EVENT_BASE + 31)
+#define MAC_RLC_UPLINK_DATA_IND (DWORD)(GRLC_EVENT_BASE + 32)
+#define MAC_RLC_ERROR_IND (DWORD)(GRLC_EVENT_BASE + 33)
+#define MAC_RLC_DEACT_REQ (DWORD)(GRLC_EVENT_BASE + 34)
+#define MAC_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 35)
+#define MAC_RLC_TLLI_IND (DWORD)(GRLC_EVENT_BASE + 36)
+#define MAC_RLC_DOWNLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 37)
+#define UPL_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 38)
+#define PTBF_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 39)
+#define T3168 (DWORD)(GRLC_EVENT_BASE + 40)
+#define T3182 (DWORD)(GRLC_EVENT_BASE + 41)
+#define RLC_ENG_MODE_TIMER (DWORD)(GRLC_EVENT_BASE + 42)
+#define GRR_RLC_PSHO_REQ_EV (DWORD)(GRLC_EVENT_BASE + 43)
+#define GRR_RLC_PSHO_SUCC_EV (DWORD)(GRLC_EVENT_BASE + 44)
+#define GRR_RLC_PSHO_FAIL_EV (DWORD)(GRLC_EVENT_BASE + 45)
+
+ /* END OF RLC */
+
+ /* START OF SNP */
+#define SN_DL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 0)
+#define SN_UL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 1)
+#define SN_NPDU_DEL_REQ (DWORD)(SNDCP_EVENT_BASE + 2)
+#define SN_NPDU_AVAIL_REQ (DWORD)(SNDCP_EVENT_BASE + 3)
+#define SN_DATA_REQ (DWORD)(SNDCP_EVENT_BASE + 4)
+#define SN_UNITDATA_REQ (DWORD)(SNDCP_EVENT_BASE + 5)
+#define SN_IR_UL_SUSPEND_RSP (DWORD)(SNDCP_EVENT_BASE + 6)
+#define SN_XID_REQ (DWORD)(SNDCP_EVENT_BASE + 7)
+#define SNSM_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 8)
+#define SNSM_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 9)
+#define SNSM_ASSIGN_IND (DWORD)(SNDCP_EVENT_BASE + 10)
+#define SNSM_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 11)
+#define SNSM_MODIFY_IND (DWORD)(SNDCP_EVENT_BASE + 12)
+#define SNSM_IR_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 13)
+#define SNSM_IR_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 14)
+#define SNSM_IR_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 15)
+#define SNPDU_AVAIL_IND (DWORD)(SNDCP_EVENT_BASE + 16)
+#define SNPDU_DEL_CNF (DWORD)(SNDCP_EVENT_BASE + 17)
+#define SNPDU_DEL_IND (DWORD)(SNDCP_EVENT_BASE + 18)
+#define LL_ESTABLISH_CNF (DWORD)(SNDCP_EVENT_BASE + 19)
+#define LL_ESTABLISH_IND (DWORD)(SNDCP_EVENT_BASE + 20)
+#define LL_RELEASE_CNF (DWORD)(SNDCP_EVENT_BASE + 21)
+#define LL_RELEASE_IND (DWORD)(SNDCP_EVENT_BASE + 22)
+#define LL_STATUS_IND (DWORD)(SNDCP_EVENT_BASE + 23)
+#define LL_RESET_IND (DWORD)(SNDCP_EVENT_BASE + 24)
+#define LL_RESET_PSHO_IND (DWORD)(SNDCP_EVENT_BASE + 25)
+#define LL_DATA_CNF (DWORD)(SNDCP_EVENT_BASE + 26)
+#define LL_XID_CNF (DWORD)(SNDCP_EVENT_BASE + 27)
+#define LL_XID_IND (DWORD)(SNDCP_EVENT_BASE + 28)
+#define LL_DATA_IND (DWORD)(SNDCP_EVENT_BASE + 29)
+#define LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 30)
+#define TIME_REEST (DWORD)(SNDCP_EVENT_BASE + 31)
+#define TIME_LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 32)
+#define TIME_UACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 33)
+#define TIME_ACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 34)
+ /* END OF SNP */
+
+ /* START OF GSMA */
+#define LLSMS_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 0)
+#define SN_NPDU_DEL_IND (DWORD)(GSMA_EVENT_BASE + 1)
+#define SN_NPDU_AVAIL_IND (DWORD)(GSMA_EVENT_BASE + 2)
+#define SN_DATA_IND (DWORD)(GSMA_EVENT_BASE + 3)
+#define SN_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 4)
+#define SN_IR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 5)
+#define SN_IR_TO_UMTS_IND (DWORD)(GSMA_EVENT_BASE + 6)
+#define RR_TESTPARAM_IND (DWORD)(GSMA_EVENT_BASE + 7)
+#define RR_ABORT_IND (DWORD)(GSMA_EVENT_BASE + 8)
+#define RR_ACT_CNF (DWORD)(GSMA_EVENT_BASE + 9)
+#define RR_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 10)
+#define RR_ACT_FAIL (DWORD)(GSMA_EVENT_BASE + 11)
+#define RR_CELL_PARAMETER_IND (DWORD)(GSMA_EVENT_BASE + 12)
+#define RR_ACT_IND (DWORD)(GSMA_EVENT_BASE + 13)
+#define RR_DEACT_CNF (DWORD)(GSMA_EVENT_BASE + 14)
+#define RR_PLMN_CNF (DWORD)(GSMA_EVENT_BASE + 15)
+#define RR_PLMN_REJ (DWORD)(GSMA_EVENT_BASE + 16)
+#define RR_PLMN_IND (DWORD)(GSMA_EVENT_BASE + 17)
+#define RR_PLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 18)
+#define RR_REL_IND (DWORD)(GSMA_EVENT_BASE + 19)
+#define RR_TBF_EST_IND (DWORD)(GSMA_EVENT_BASE + 20)
+#define RR_TBF_REL_IND (DWORD)(GSMA_EVENT_BASE + 21)
+#define RR_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 22)
+#define RR_HPLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 23)
+#define RR_HPLMN_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 24)
+#define RR_EST_CNF (DWORD)(GSMA_EVENT_BASE + 25)
+#define RR_EST_IND (DWORD)(GSMA_EVENT_BASE + 26)
+#define RR_CELL_IND (DWORD)(GSMA_EVENT_BASE + 27)
+#define RR_DATA_IND (DWORD)(GSMA_EVENT_BASE + 28)
+#define RR_SYNC_IND (DWORD)(GSMA_EVENT_BASE + 29)
+#define GMMRR_PAGE_IND (DWORD)(GSMA_EVENT_BASE + 30)
+#define GMMRR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 31)
+#define GMMRR_CELL_UPDATE_IND (DWORD)(GSMA_EVENT_BASE + 32)
+#define RR_DATA_REJ (DWORD)(GSMA_EVENT_BASE + 33)
+#define RR_EST_REJ (DWORD)(GSMA_EVENT_BASE + 34)
+#define RR_HO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 35)
+#define RR_HO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 36)
+#define RR_HO_START_IND (DWORD)(GSMA_EVENT_BASE + 37)
+#define RR_IRAT_RESEL_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 38)
+#define RR_IRAT_RESEL_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 39)
+#define RR_IRAT_RESEL_START_IND (DWORD)(GSMA_EVENT_BASE + 40)
+#define RR_CCO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 41)
+#define RR_CCO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 42)
+#define RR_CCO_START_IND (DWORD)(GSMA_EVENT_BASE + 43)
+#define RR_RAT_CHN_IND (DWORD)(GSMA_EVENT_BASE + 44)
+#define RR_TEST_COUNT_CNF (DWORD)(GSMA_EVENT_BASE + 45)
+#define LLGMM_STATUS_IND (DWORD)(GSMA_EVENT_BASE + 46)
+#define LLGMM_TRIGGER_IND (DWORD)(GSMA_EVENT_BASE + 47)
+#define LLGMM_USER_DATA_PRESENT (DWORD)(GSMA_EVENT_BASE + 48)
+#define LLGMM_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 49)
+#define RR_START_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 50)
+#define RR_END_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 51)
+#define RR_ADD_CELL_RESEL_INFO_IND (DWORD)(GSMA_EVENT_BASE + 52)
+#define RLC_BLOCK_INFO_IND (DWORD)(GSMA_EVENT_BASE + 53)
+#define RRMN_MEAS_RESULTS_CNF (DWORD)(GSMA_EVENT_BASE + 54)
+#define MNRR_CIPHERING_IND (DWORD)(GSMA_EVENT_BASE + 55)
+#define SN_XID_CNF (DWORD)(GSMA_EVENT_BASE + 56)
+#define RR_RRL_DATA_IND (DWORD)(GSMA_EVENT_BASE + 57)
+#define RR_RRL_ABORT_EVENT_IND (DWORD)(GSMA_EVENT_BASE + 58)
+#define RR_RRL_CLASSMARK_IND (DWORD)(GSMA_EVENT_BASE + 59)
+#define SNSM_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 60)
+#define SNSM_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 61)
+#define SNSM_MODIFY_RSP (DWORD)(GSMA_EVENT_BASE + 62)
+#define SNSM_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 63)
+#define SNSM_STATUS_REQ (DWORD)(GSMA_EVENT_BASE + 64)
+#define SNSM_IR_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 65)
+#define SNSM_IR_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 66)
+#define SNSM_IR_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 67)
+#define URRC_RESEL_REQ (DWORD)(GSMA_EVENT_BASE + 68)
+#define URRC_SET_INACTIVE_REQ (DWORD)(GSMA_EVENT_BASE + 69)
+#define RR_SET_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 70)
+#define URRC_READ_PREDEF_CONF_REQ (DWORD)(GSMA_EVENT_BASE + 71)/*WCDMAÏÂʹÓÃ*/
+#define URRC_ABORT_READ_PREDEF_REQ (DWORD)(GSMA_EVENT_BASE + 72)/*WCDMAÏÂʹÓÃ*/
+#define URRC_L1_RSRC_REQ (DWORD)(GSMA_EVENT_BASE + 73)
+#define URRC_L1_RSRC_FREE_IND (DWORD)(GSMA_EVENT_BASE + 74)
+#define RR_L1_RSRC_CNF (DWORD)(GSMA_EVENT_BASE + 75)
+#define RR_L1_RSRC_REJ (DWORD)(GSMA_EVENT_BASE + 76)
+#define RR_CELL_SEARCH_CNF (DWORD)(GSMA_EVENT_BASE + 77)
+#define RR_CELL_SEARCH_REJ (DWORD)(GSMA_EVENT_BASE + 78)
+#define URRC_CELL_SEARCH_REQ (DWORD)(GSMA_EVENT_BASE + 79)
+#define URRC_HO_INFO_REQ (DWORD)(GSMA_EVENT_BASE + 80)
+#define URRC_HO_REQ (DWORD)(GSMA_EVENT_BASE + 81)
+#define URRC_VSD_INFO (DWORD)(GSMA_EVENT_BASE + 82)
+#define RR_HO_CNF (DWORD)(GSMA_EVENT_BASE + 83)
+#define RR_HO_REJ (DWORD)(GSMA_EVENT_BASE + 84)
+#define URRC_CELL_CHANGE_REQ (DWORD)(GSMA_EVENT_BASE + 85)
+#define RR_CELL_CHANGE_CNF (DWORD)(GSMA_EVENT_BASE + 86)
+#define RR_CELL_CHANGE_REJ (DWORD)(GSMA_EVENT_BASE + 87)
+#define RR_RESEL_CNF (DWORD)(GSMA_EVENT_BASE + 88)
+#define RR_RESEL_REJ (DWORD)(GSMA_EVENT_BASE + 89)
+
+#define ERRC_RESEL_REQ_EV (DWORD)(GSMA_EVENT_BASE + 90)
+#define ERRC_CELL_SEARCH_REQ_EV (DWORD)(GSMA_EVENT_BASE + 91)
+#define RR_IRAT_PSHO_START_IND_EV (DWORD)(GSMA_EVENT_BASE + 92)
+#define RR_IRAT_PSHO_COMPLETE_IND_EV (DWORD)(GSMA_EVENT_BASE + 93)
+#define RR_IRAT_PSHO_FAIL_IND_EV (DWORD)(GSMA_EVENT_BASE + 94)
+#define URRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 95)
+#define ERRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 96)
+#define RR_PSHO_CNF_EV (DWORD)(GSMA_EVENT_BASE + 97)
+#define RR_PSHO_REJ_EV (DWORD)(GSMA_EVENT_BASE + 98)
+#define ERRC_CELL_CHANGE_REQ_EV (DWORD)(GSMA_EVENT_BASE + 99)
+#define RR_ETWS_DATA_IND_EV (DWORD)(GSMA_EVENT_BASE + 100)
+#define LLGMM_PSHO_IND_EV (DWORD)(GSMA_EVENT_BASE + 101)
+#define RLC_SM_CURR_BEAR_IND_EV (DWORD)(GSMA_EVENT_BASE + 102)
+#define RR_SENDCMP_IND_EV (DWORD)(GSMA_EVENT_BASE + 103)
+#define RR_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 104)
+#define RR_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 105)
+#define RR_ABORT_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 106)
+#define RR_ABORT_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 107)
+#define RR_XCELLINFO_CNF (DWORD)(GSMA_EVENT_BASE + 108)
+#define RR_XCELLINFO_REJ (DWORD)(GSMA_EVENT_BASE + 109)
+#define RR_XCELLINFO_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 110)
+
+
+ /* START OF LLC */
+#define LLC_START_TIMER_T200 (DWORD)(GLLC_EVENT_BASE + 0)
+#define LLC_START_TIMER_T201 (DWORD)(GLLC_EVENT_BASE + 1)
+#define LLSMS_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 2)
+#define LLGMM_ASSIGN_REQ (DWORD)(GLLC_EVENT_BASE + 3)
+#define LLGMM_RESUME_REQ (DWORD)(GLLC_EVENT_BASE + 4)
+#define LLGMM_SUSPEND_REQ (DWORD)(GLLC_EVENT_BASE + 5)
+#define LLGMM_TRIGGER_REQ (DWORD)(GLLC_EVENT_BASE + 6)
+#define LLGMM_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 7)
+#define LLGMM_CELL_NOTIFICATION_REQ (DWORD)(GLLC_EVENT_BASE + 8)
+#define SNPDU_AVAIL_REQ (DWORD)(GLLC_EVENT_BASE + 9)
+#define SNPDU_DEL_REQ (DWORD)(GLLC_EVENT_BASE + 10)
+#define SNPDU_DEL_RSP (DWORD)(GLLC_EVENT_BASE + 11)
+#define LL_CONFIG_REQ (DWORD)(GLLC_EVENT_BASE + 12)
+#define LL_ESTABLISH_REQ (DWORD)(GLLC_EVENT_BASE + 13)
+#define LL_ESTABLISH_RSP (DWORD)(GLLC_EVENT_BASE + 14)
+#define LL_RELEASE_REQ (DWORD)(GLLC_EVENT_BASE + 15)
+#define LL_DATA_REQ (DWORD)(GLLC_EVENT_BASE + 16)
+#define LL_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 17)
+#define LL_XID_REQ (DWORD)(GLLC_EVENT_BASE + 18)
+#define LL_XID_RSP (DWORD)(GLLC_EVENT_BASE + 19)
+#define GRR_LLC_PSHO_SUCCESS_IND (DWORD)(GLLC_EVENT_BASE + 20)
+#define RRC_LLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 21)
+#define RLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND (DWORD)(GLLC_EVENT_BASE + 23)
+#define RLC_DATA_CNF (DWORD)(GLLC_EVENT_BASE + 24)
+#define RLC_UNITDATA_CNF (DWORD)(GLLC_EVENT_BASE + 25)
+#define RLC_CLEAR_QUEUE_CNF (DWORD)(GLLC_EVENT_BASE + 26)
+#define RLC_CLEAR_QUEUE_IND (DWORD)(GLLC_EVENT_BASE + 27)
+#define RLC_DATA_BUFF_IND (DWORD)(GLLC_EVENT_BASE + 28)
+#define LLC_T200 (DWORD)(GLLC_EVENT_BASE + 29)
+#define T201 (DWORD)(GLLC_EVENT_BASE + 30)
+#define LLC_T100_EV (DWORD)(GLLC_EVENT_BASE + 31)
+ /* END OF LLC */
+
+/* ========================================================================
+ MM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MM_T3210_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 0)
+#define MM_T3211_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 1)
+#define MM_T3212_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 2)
+#define MM_T3213_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 3)
+#define MM_T3214_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 4)
+#define MM_T3216_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 5)
+#define MM_T3218_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 6)
+#define MM_T3220_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 7)
+#define MM_T3221_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 8)
+#define MM_T3230_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 9)
+#define MM_T3240_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 10)
+#define MM_T3241_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 11)
+#define MM_T3225_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 12)
+#define MM_T3222_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 13)
+#define MM_T3231_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 14)
+#define MM_T3232_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 15)
+#define MM_TWRRR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 16)
+#define MM_TWPGR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 17)
+#define MM_TCCSRV_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 18)
+
+/* ========================================================================
+ GMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_T_READY_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 0)
+#define GMM_T3310_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 1)
+#define GMM_T3330_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 2)
+#define GMM_T3317_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 3)
+#define GMM_T3321_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 4)
+#define GMM_T3316_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 5)
+#define GMM_T3318_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 6)
+#define GMM_T3320_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 7)
+#define GMM_T_WRRC_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 8)
+#define GMM_T_WRRR_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 9)
+#define GMM_T_POWER_OFF_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 10)
+#define GMM_T_WSPN_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 11)
+#define GMM_T_WCRS_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 12)
+#define GMM_T_WTRG_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 13)
+#define GMM_T_PAGE_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 14)
+#define GMM_T3319_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 15)
+#define GMM_T_WREL_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 16)/*EC614000821119*/
+/* ========================================================================
+ UMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_T3212_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 0)
+#define UMM_T3311_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 1)
+#define UMM_T3302_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 2)
+#define UMM_T3312_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 3)
+#define UMM_T_NOCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 4)
+#define UMM_T_LIMIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 5)
+#define UMM_T_DELLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 6)
+#define UMM_T_SHHPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 7)
+#define UMM_T_UICCINIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 8) /* ¼àÊÓ¿¨³õʼ»¯¶¨Ê±Æ÷ */
+#define UMM_T_CAMPON_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 9) /* ¼àÊÓפÁô¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_DETACH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 10) /* ¼àÊӹػúÈ¥»î¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_LIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 11) /* ÖØÊÔPLMNÁÐ±í¶¨Ê±Æ÷ */
+#define UMM_T_PLMNLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 12) /* Áбí¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T3411_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 13)
+#define UMM_T3402_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 14)
+#define UMM_T3412_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 15)
+#define UMM_T3442_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 16)
+#define UMM_T_PROC_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 17)
+#define UMM_T_FOCSGLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 18)
+#define UMM_T3323_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 19)
+#define UMM_T3423_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 20)
+#define UMM_TBGSEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 21) /*LTE±³¾°ËÑË÷ÖÜÆÚ¶¨Ê±Æ÷*/
+#define UMM_T_IMSREG_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 22)
+#define UMM_T_NORMALFAILPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 23)
+#define UMM_T_ENABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 24)
+#define UMM_T_DISABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 25)
+#define UMM_T_LOOPTIME_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 26)
+#define UMM_T_DISFRESEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 27)
+#define UMM_T_RESETCAUSEPAR_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 28)
+#define UMM_T_SWITCHCARD_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 29)
+#define UMM_T_ARREARS_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 30)
+#define UMM_TSEARCHECALLCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 31)
+#define UMM_TECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 32)
+#define UMM_TTESTECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 33)
+#define UMM_T_IMSREL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 34)
+/* ========================================================================
+ CC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_T303_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 0)
+#define CC_T305_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 1)
+#define CC_T308_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 2)
+#define CC_T310_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 3)
+#define CC_T313_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 4)
+#define CC_T335_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 5) /*CCBS*/
+#define CC_T332_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 6)
+#define CC_T323_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 7)
+#define CC_T336_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 8)
+#define CC_T337_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 9)
+
+/* ADD A TIMER FOR CALL CONFIRM MESSAGE */
+#define CC_T_CALLCNF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 10)
+
+/* ADD TIMER FOR AOC */
+#define CC_T_ACMUPD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 11)
+#define CC_T_CDUR_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 12)
+
+#define CC_T_HOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 13)
+#define CC_T_RETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 14)
+
+#define CC_T_MPTYBUILD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 15)
+#define CC_T_MPTYHOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 16)
+#define CC_T_MPTYRETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 17)
+#define CC_T_MPTYSPLIT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 18)
+
+#define CC_T322_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 19)
+#define CC_T_SUPPER_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 20)
+#define CC_T_MMCONN_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 21)
+
+#define CC_T_RELTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 22)
+#define CC_T_CONNTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 23)
+#define CC_T_SYNCIND_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 24)
+#define CC_T_MODIFYBC_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 25)
+#define CC_T_DTMFDURA_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 26)
+#define CC_T_MMCONNRETRY_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 27)
+#define CC_T_ALLOWEDCALL_TIME_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 28)
+#define CC_T_ECT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 29)
+#define CC_T_T2_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 30)
+#define CC_T_T5_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 31)
+#define CC_T_T6_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 32)
+#define CC_T_T7_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 33)
+#define CC_T_TIDLE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 34)
+#define CC_T_T9_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 35)
+
+/* ========================================================================
+ SMS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SMS_TR1M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 0) /* FOR MO SM.*/
+#define SMS_TRAM_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 1) /* FOR MO SM.*/
+#define SMS_TC1M_MO_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 2) /* FOR MO SM.*/
+#define SMS_TMMS_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 3) /* FOR MO SM.*/
+#define SMS_TR2M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 4) /* FOR MT SM.*/
+#define SMS_TC1M_MT_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 5) /* FOR MT SM.*/
+/* ========================================================================
+ SS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SS_T_WAIT_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 0)
+#define SS_T_MOLRTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 1)
+#define SS_T_MOLRINTERTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 2)
+#ifdef _USE_SIG_TRACE
+#define SS_DL_L3FACILITY_EV (DWORD)(SS_TIMER_EVENT_BASE + 3)
+#define SS_DL_L3MTREG_EV (DWORD)(SS_TIMER_EVENT_BASE + 4)
+#define SS_DL_L3RELCOMP_EV (DWORD)(SS_TIMER_EVENT_BASE + 5)
+#endif
+
+
+/* ========================================================================
+ SM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_T3380_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 0)
+#define SM_T3381_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 1)
+#define SM_T3390_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 2)
+#define SM_T_CMEST_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 3)
+#define SM_T_PDPHANDLE_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 4)
+#define SM_T_APPANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 5)
+#define SM_T_AUTOANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS¶¨Ê±Æ÷ ÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_T_SCHEDCHECK_EXPIRY_EV (DWORD)(CBS_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ UICC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UICC_CARD_DETECT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 0)
+#define UICC_CARD_USAT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ URRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define USIR_T_BCH_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 0)
+#define USIR_T_SIB7_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 1)
+#define USIR_T_VTSIB_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 2)
+#define USIR_T_R_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 3)
+#define USIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 4)
+#define UCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 5)
+#define UCSR_T_HYSTX_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 6)
+#define UCSR_T_PROTECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 7)
+#define UCSR_T_NCELL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 8)
+#define UCSR_T_OOS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 9)
+#define UCSR_T_CAMP1S_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define UCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 11)
+#define UCSR_T_REDIRECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 12)
+#define UMCR_T_RESELECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 13)
+#define UMCR_T_PERIOD_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 14)
+#define UMCR_T_TRIGGER_EV (DWORD)(URRC_TIMER_EVENT_BASE + 15)
+#define UMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 16)
+#define UCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 17)
+#define UCER_T_ETWS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 18)
+#define UCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 19)
+#define URRC_T300_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 20)
+#define URRC_T302_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 21)
+#define URRC_T304_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 22)
+#define URRC_T305_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 23)
+#define URRC_T307_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 24)
+#define URRC_T308_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 25)
+#define URRC_T309_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 26)
+#define URRC_T312_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 27)
+#define URRC_T313_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 28)
+#define URRC_T314_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 29)
+#define URRC_T315_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 30)
+#define URRC_T316_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 31)
+#define URRC_T319_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 32)
+#define URRC_T320_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 33)
+#define UMCR_T322_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 34)
+#define URRC_T323_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 35)
+#define URRC_T325_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 36)
+#define URRC_T_WAIT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 37)
+#define UCSR_T_LBS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 38)
+
+/* ========================================================================
+ UPDCP¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDCP_T_RABREEST_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 0)
+#define PDCP_T_SNSYNC_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 1)
+#define PDCP_T_DATAMONITOR_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ URLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define URLC_T_DISCARD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 0)
+#define URLC_T_POLL_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 1)
+#define URLC_T_POLLPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 2)
+#define URLC_T_POLLPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 3)
+#define URLC_T_STATUSPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 4)
+#define URLC_T_STATUSPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 5)
+#define URLC_T_RESET_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 6)
+#define URLC_T_MRW_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ UMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define UMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 0)
+#define UMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 1)
+#define UMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 2)
+#define UMAC_T_RACHPROC_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 3)
+#define UMAC_T_HSTIMER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 4)
+#define UMAC_T_RESET_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 5)
+
+
+/* ========================================================================
+ L1T¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define L1T_T_BSIC_EXPIRY_EV (DWORD)(L1T_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ TAF¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define TAF_T_PROC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 0)
+#define TAF_T_DISC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 1)
+#define TAF_T_RA_TSYNC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 2)
+#define TAF_T_RA_TSYNCEND_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 3)
+#define TAF_T_RA_TSBFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 4)
+#define TAF_T_RA_TXFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 5)
+#define TAF_T_RLP_TRCVR_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 6)
+#define TAF_T_RLP_TRCVS_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 7)
+#define TAF_T_RLP_TTEST_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 8)
+#define TAF_T_RLP_TXID_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 9)
+#define TAF_T_RLP_T_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ GSMA¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ ROHCv1¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 0)
+#define ROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 1)
+#define ENROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 2)
+#define ENROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 3)
+#define ROHCv1_T_NACK_FDBK_CNT_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ ROHCv2¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 0)
+#define ENROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ PDI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDI_T_SWITCHLED_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 0)
+#define PDI_T_WAITDNSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 1)
+#define PDI_T_WAITZSSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 2)
+#define PDI_T_WAIT_BUF_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 3)
+#define PDI_LOOPB_TIMER_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 4)
+
+/* ========================================================================
+ SCI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define SCI_T_VOICE_FRAME_EXPIRY_EV (DWORD)(SCI_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ STM¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define STM_MEMAVAILD_EXPIRY_EV (DWORD)(STM_TIMER_EVENT_BASE + 0)
+
+/*========================================================================
+USAT¶¨Ê±Æ÷¶¨Òå
+========================================================================*/
+#define USAT_TIMERMNG_TIMER1_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 0)
+#define USAT_TIMERMNG_TIMER2_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 1)
+#define USAT_TIMERMNG_TIMER3_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 2)
+#define USAT_TIMERMNG_TIMER4_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 3)
+#define USAT_TIMERMNG_TIMER5_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 4)
+#define USAT_TIMERMNG_TIMER6_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 5)
+#define USAT_TIMERMNG_TIMER7_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 6)
+#define USAT_TIMERMNG_TIMER8_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ È«¾ÖÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define FOR_TEST_TEMP_EV (DWORD)(PRI_TEST_EVENT_BASE + 0)
+#define TEST_SET_UICC_RLT_EV (DWORD)(PRI_TEST_EVENT_BASE + 1)
+#define TEST_SET_UICC_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 2)
+#define TEST_SET_NV_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 3)
+#define TEST_SET_NV_DATA_IMEI_EV (DWORD)(PRI_TEST_EVENT_BASE + 4)
+#define TEST_SET_NV_DATA_SPCLFUNC_EV (DWORD)(PRI_TEST_EVENT_BASE + 5)
+#define TEST_SET_COMP_IND_EV (DWORD)(PRI_TEST_EVENT_BASE + 6)
+/* ========================================================================
+ Ä£ÄâTAFÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_TAFDATAIND_UTRAN_EV (DWORD)(TAF_TEST_EVENT_BASE + 0)
+
+/* ========================================================================
+ USIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_BIGSIB_IND_EV (DWORD)(USIR_TEST_EVENT_BASE + 0)
+#define TEST_USIR_DECSIB_EV (DWORD)(USIR_TEST_EVENT_BASE + 1)
+
+/* ========================================================================
+ NURLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UURLC_DATA_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 0)
+#define TEST_UURLC_DATA_IND_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 1)
+#define TEST_CURLC_CONFIG_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 2)
+#define TEST_URLC_ACK_CTRL_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NPDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 1)
+#define NPDCP_DATA_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 2)
+#define NPDCP_DATA_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 3)
+#define TEST_NPDCP_DATA_ERR_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 4)
+#define TEST_NPDCP_DATA_CNF_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 5)
+
+/* ========================================================================
+ NUMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UMAC_ACK_CTRL_UTRAN_EV (DWORD)(NUMAC_EVENT_BASE + 0)
+#define TEST_UMAC_HSUPA_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 1)
+#define TEST_UMAC_HSUPA_CFG_EV (DWORD)(NUMAC_EVENT_BASE + 2)
+#define TEST_UMAC_HSUPA_SIINFO_EV (DWORD)(NUMAC_EVENT_BASE + 3)
+#define TEST_UMAC_HSUPA_HEADER_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 4)
+#define TEST_UMAC_NOTIFY_DATA_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 5)
+#define TEST_UMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 6)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UCBS_SCHED_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 0)
+#define TEST_UCBS_DATA_REQ_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 1)
+#define TEST_UCBS_OUTPUT_END_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 2)
+#define TEST_UCBS_UMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 3)
+#define TEST_UCBS_UMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 4)
+#define TEST_UURLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 5)
+/*WCDMA NCBS_EVENT_BASE=20 */
+#define TEST_UWRLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 6)
+#define TEST_UCBS_WMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 7)
+#define TEST_UCBS_WMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 8)
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TC_ACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 0)
+#define TC_ACTIVE_TEST_CNF_EV (DWORD)(TC_EVENT_BASE + 1)
+#define TC_DEACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 2)
+#define TC_CLOSE_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 3)
+#define TC_CLOSE_LOOP_CNF_EV (DWORD)(TC_EVENT_BASE + 4)
+#define TC_CLOSE_LOOP_REQ_URLC_EV (DWORD)(TC_EVENT_BASE + 5)
+#define TC_OPEN_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 6)
+/*wcdma TC_EVENT_BASE=30*/
+#define TC_CLOSE_LOOP_REQ_WRLC_EV (DWORD)(TC_EVENT_BASE + 7)
+//lte TC_EVERNT
+#define EMM_TC_TEST_CONTROL_REQ_EV (DWORD)(TC_EVENT_BASE + 8)
+#define TC_EMM_TEST_CONTROL_CNF_EV (DWORD)(TC_EVENT_BASE + 9)
+#define TC_PDI_OPEN_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 10)
+#define TC_PDI_CLOSE_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 11)
+/* ========================================================================
+ L1SIMUÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1SIMU_START_EV (DWORD)(L1SIMU_EVENT_BASE + 0) /*Æô¶¯L1_SIMUÄ£¿é*/
+#define L1SIMU_NGMAC_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 1) /*L1_SIMU·¢ËÍÊý¾Ýµ½MAC_N*/
+#define L1SIMU_DLLN_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 2) /*L1_SIMU·¢ËÍÊý¾Ýµ½LAPDM*/
+#define TOOL_L1SIMU_CELL_MEAS_INFO_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 3) /*¹¤¾ß·¢ËÍFCBSBÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_SYSINFO_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 4) /*¹¤¾ß·¢ËÍϵͳÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_PAGING_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 5) /*¹¤¾ß·¢ËÍÑ°ºôÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_DCCH_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 6)
+#define TOOL_L1SIMU_DCCH_REL_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 7)
+#define L1SIMU_DLLN_CONNECT_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 8)
+#define L1SIMU_FRAME_INT_EV (DWORD)(L1SIMU_EVENT_BASE + 9)
+#define TOOL_L1SIMU_SYNC_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 10)
+#define TOOL_L1SIMU_SYSINFO_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 11)
+#define L1SIMU_DLLN_DATA_SENT_CMP_EV (DWORD)(L1SIMU_EVENT_BASE + 12) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define TOOL_L1SIMU_DCCH_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 13) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define TOOL_L1SIMU_SYSINFO_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 14)
+#define L1SIMU_TOOL_RXLEV_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 15)
+#define L1SIMU_TOOL_SYNCREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 16)
+#define L1SIMU_TOOL_SYSREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 17)
+#define L1SIMU_TOOL_IDLE_MODE_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 18)
+#define L1SIMU_TOOL_NCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 19) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define L1SIMU_TOOL_SCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 20) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define L1SIMU_TOOL_MEAS_REPORT_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 21)
+#define L1SIMU_TOOL_DL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 22)
+#define L1SIMU_TOOL_UL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 23)
+#define L1SIMU_TOOL_TAF_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 24)
+#define L1SIMU_TOOL_TAF_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 25)
+#define L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 26)
+#define L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 27)
+#define TOOL_L1SIMU_CBS_BLK_START_EV (DWORD)(L1SIMU_EVENT_BASE + 28)
+#define TOOL_L1SIMU_CBS_FST_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 29)
+#define TOOL_L1SIMU_CBS_OTHER_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 30)
+#define L1SIMU_TOOL_PSHOREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 31)
+#define L1SIMU_TOOL_DEACTIATE_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 32)
+#define TOOL_L1SIMU_ABNORMAL_TA_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 33)
+#define L1SIMU_TOOL_L1G_L1E_GSM_INACT_TIME_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 34)
+#define L1SIMU_TOOL_L1G_L1E_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 35)
+#define L1SIMU_TOOL_L1G_L1E_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 36)
+#define L1SIMU_TOOL_CHANNEL_ASSIGN_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 37)
+#define L1SIMU_TOOL_CHANNEL_TYPE_INFO_EV (DWORD)(L1SIMU_EVENT_BASE + 38)
+
+/* ========================================================================
+ NLAPDMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLAPDM_UNIT_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 0) /*¹¤¾ßÏòLADPN·¢ËÍ·ÇÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_UNIT_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 1) /*LADPNÏò¹¤¾ßÉÏ´«·ÇÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 2) /*¹¤¾ßÏòLADPN·¢ËÍÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 3) /*LADPNÏò¹¤¾ßÉÏ´«È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_ESTABLISH_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 4) /*¹¤¾ßÏòLADPN·¢Ëͽ¨Á´ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 5) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 6) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´È·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_SUSPEND_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 7) /*LADPNÏò¹¤¾ß·¢Ë͹ÒÆðÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_RECONNECT_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 8) /*¹¤¾ßÏòLADPN·¢ËÍÖØÁ¬ÇëÇóÏûÏ¢*/
+#define TOOL_NLAPDM_RELEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 9) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 10) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 11) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_MDL_CONFIG_EV (DWORD)(NLAPDM_EVENT_BASE + 12) /*¹¤¾ßÏòLADPN·¢ËͳõʼÅäÖÃÏûÏ¢*/
+#define NLAPDM_TOOL_MDL_ERROR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 13) /*LADPNÏò¹¤¾ß·¢ËÍ´íÎ󱨸æ*/
+#define TOOL_NLAPDM_MDL_REALEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 14) /*¹¤¾ß·¢ÆðÒì³£±¾µØÊÍ·ÅÏûÏ¢*/
+#define NLAPDM_L2_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 15) /*SAPI0·¢ËÍÏûÏ¢µ½SAPI3*/
+#define NLAPDM_TOOL_SABM_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 16) /*NLAPDMÏò¹¤¾ß·¢ËÍÆÕͨ½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 17) /*¹¤¾ßÏòNLAPDM·¢ËÍÆÕͨ½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define NLAPDM_TOOL_SABM_COR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 18) /*NLAPDMÏò¹¤¾ß·¢ËͳåÍ»½â¾ö½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_COR_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 19) /*¹¤¾ßÏòNLAPDM·¢ËͳåÍ»½â¾ö½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define TOOL_NLAPDM_EXCEPT_DATA_EV (DWORD)(NLAPDM_EVENT_BASE + 20) /*¹¤¾ßÏòNLAPDM·¢ËÍÒì³£Êý¾ÝÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_I_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 21) /*NLAPDMÏò¹¤¾ß·¢ËÍÈ·ÈÏÊý¾ÝÉϱ¨Ö¸Ê¾ÏûÏ¢*/
+
+
+/* ========================================================================
+ NGMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NGMAC_START_EV (DWORD)(NGMAC_EVENT_BASE + 0) /*NGMACÄ£¿éÆô¶¯*/
+#define NGMAC_NGRLC_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 1) /*NGMAC¸øNGRLC·¢ËÍPDANÏûÏ¢*/
+#define NGMAC_NGRLC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 2) /*NGMAC¸øNGRLC·¢ËÍUPLINKÊý¾Ý¿é*/
+#define NGRLC_NGMAC_PUAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 3) /*NGRLC¸øNGMAC·¢ËÍPUANµÄ²ÎÊý*/
+#define NGMAC_NGRLC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 4) /*NGMAC֪ͨNGRLCÊÍ·ÅUPLINK TBF*/
+#define NGRLC_NGMAC_FBI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 5) /*RLC·ÇÈ·ÈÏģʽ£¬NGRLC֪ͨNGMAC×îÖÕ¿éÒÑ·¢³ö£¬NGMACµÈ´ýPCA*/
+#define NGMAC_NGRLC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 6) /*RLC·ÇÈ·ÈÏģʽ£¬NGMAC֪ͨNGRLCÊÍ·ÅTBF*/
+#define NGRLC_NGMAC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 7) /*RLCÈ·ÈÏģʽ£¬NGRLC֪ͨNGMACÊÍ·ÅDOWNLINK TBF*/
+#define NGRLC_NGMAC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 8) /*NGRLC֪ͨNGMACÒì³£ÊÍ·ÅUPLINK TBF*/
+#define NGMAC_NGRLC_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 9) /*NGMAC֪ͨNGRLC DOWNLINK_TBFÒѾÍêÈ«µÃµ½È·ÈÏ*/
+#define TOOL_NGMAC_PUA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 10) /*TOOL¸øNGMAC·¢ËÍPUA*/
+#define NGMAC_TOOL_PRR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 11) /*NGMAC¸øTOOL·¢ËÍPRR£¬Çé¿ö°üÀ¨£ºIDLE̬½¨Á¢µÄUPLINK TBF¡¢ULONULµÄTBF¡¢ULONDLµÄTBF*/
+#define NGMAC_TOOL_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 12) /*NGMAC¸øTOOL·¢ËÍPDANÏûÏ¢£¬½öÔÚÐèÒª½¨Á¢ULONDL TBFʱ²Å·¢*/
+#define TOOL_NGMAC_PUAN_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 13) /*TOOL¸øNGMAC·¢ËÍPUAN£¬½öÔÚ±àÂ뷽ʽ¡¢´°¿Ú´óС¡¢RESEGMENTµÈ¸Ä±äʱ²Å·¢*/
+#define TOOL_NGMAC_PDA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 14) /*TOOL¸øNGMAC·¢ËÍPDA*/
+#define NGMAC_TOOL_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 15) /*NGMAC¸øTOOL·¢ËÍPCA£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR8_IND_EV (DWORD)(NGMAC_EVENT_BASE + 16) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR11_IND_EV (DWORD)(NGMAC_EVENT_BASE + 17) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_CR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 18) /*NGMAC¸øTOOL·¢ËÍCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 19) /*NGMAC֪ͨTOOLÊÍ·ÅDOWNLINK TBF*/
+#define NGMAC_TOOL_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 20) /*NGMAC֪ͨTOOLÊÍ·ÅUPLINK TBF*/
+#define NGMAC_TOOL_TLLI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 21) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬NGMAC¸øTOOLÇëÇóCONT_RES_TLLI*/
+#define TOOL_NGMAC_TLLI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 22) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬TOOL¸øNGMAC·¢ËÍCONT_RES_TLLI*/
+#define TOOL_NGMAC_IMM_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 23) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨*/
+#define TOOL_NGMAC_IMM_EX_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 24) /*TOOL¸øNGMAC·¢ËÍÀ©Õ¹Á¢¼´É趨*/
+#define TOOL_NGMAC_IMM_REJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 25) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨¾Ü¾ø*/
+#define L1_NGMAC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 26) /*L1_SIMU°Ñ´ÓL1G½ÓÊÕµ½µÄÉÏÐÐÊý¾Ý·¢Ë͵½MAC_N*/
+#define NGMAC_NGMAC_TMS_FBI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 27) /*FBI¶¨Ê±Æ÷³¬Ê±*/
+#define NGMAC_NGMAC_TMS_FAI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 28) /*FAI¶¨Ê±Æ÷³¬Ê±*/
+#define TOOL_NGMAC_PMO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 29) /*TOOL¸øNGMAC·¢ËÍPMO*/
+#define TOOL_NGMAC_PSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 30) /*TOOL¸øNGMAC·¢ËÍPSI*/
+#define NGMAC_TOOL_MSACC_IND_EV (DWORD)(NGMAC_EVENT_BASE + 31) /*NGMACÏòTOOLÇëÇóUPLINK TBF½¨Á¢»òÇëÇó½¨Á¢RRÁ¬½Ó*/
+#define TOOL_NGMAC_ULTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 32) /*TOOLÅäÖÃNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 33) /*TOOLÅäÖÃNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_ULTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 34) /*TOOLÊÍ·ÅNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 35) /*TOOLÊÍ·ÅNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PKTTSRECFG_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 36) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TIMESLOT_RECONFIGUREµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTTBFREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 37) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TBF_RELEASEµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTPDCHREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 38) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_PDCH_RELEASEÏûÏ¢*/
+#define TOOL_NGMAC_PKTCCC_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 39) /*TOOLÒªÇóNGMAC·¢ËÍPACKET CELL CHANGE CONTINUE*/
+#define TOOL_NGMAC_PKTCCO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 40) /*TOOLÇëÇóNGMAC·¢ËÍPACKET CELL CHANGE ORDER*/
+#define TOOL_NGMAC_PKTNCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 41) /*TOOLÇëÇóNGMAC·¢ËÍPACKET NEIGHBOUR CELL DATA*/
+#define TOOL_NGMAC_PKTPOLL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 42) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POLLING REQUEST*/
+#define TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 43) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POWER CTRL/TA*/
+#define TOOL_NGMAC_PKTPRACHPARA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 44) /*TOOLÇëÇóNGMAC·¢ËÍPACKET PRACH PARAMETERS*/
+#define TOOL_NGMAC_PKTSCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 45) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVE CELL DATA*/
+#define TOOL_NGMAC_PKTQUENOTI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 46) /*TOOLÇëÇóNGMAC·¢ËÍPACKET QUEUING NOTIFICATION*/
+#define TOOL_NGMAC_PKTACCREJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 47) /*TOOLÇëÇóNGMAC·¢ËÍ·Ö×é½ÓÈë¾Ü¾ø*/
+#define NGMAC_TOOL_PKTMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 48) /*NGMAC½ÓÊÕµ½MS PACKET MEAS REPORT ºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTMOBTBFSTA_EV (DWORD)(NGMAC_EVENT_BASE + 49) /*NGMAC½ÓÊÕµ½MS PACKET MOBILE TBF STATUSºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTPSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 50) /*NGMAC½ÓÊÕµ½MS PACKET PSI STATUSºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTPAUSE_EV (DWORD)(NGMAC_EVENT_BASE + 51) /*NGMAC½ÓÊÕµ½MS PACKET PAUSEºó·¢ËÍÏûÏ¢µ½TOOL*/
+#define NGMAC_TOOL_PKTEMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 52) /*NGMAC½ÓÊÕµ½MS PACKET ENHANCED MEAS REPORTºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTADDMSRAC_EV (DWORD)(NGMAC_EVENT_BASE + 53) /*NGMAC½ÓÊÕµ½MS PACKET ADDITION MS RACºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTCCN_EV (DWORD)(NGMAC_EVENT_BASE + 54) /*NGMAC½ÓÊÕµ½MS PACKET CELL CHANGE NOTIFICATIONºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 55) /*NGMAC½ÓÊÕµ½MS PACKET SI STATUSºó·¢Ë͵½¹¤¾ß*/
+#define GMAC_GET_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 56) /*GMAC·¢ËÍÉÏÐÐÊý¾Ýʱµ÷Óú¯ÊýMAC_GET_BLOCKS,ΪÔö¼ÓTRACEÌí¼ÓµÄʼþºÅ*/
+#define GMAC_ACK_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 57) /*L1Gµ÷ÓÃMAC_ACK_BLOCKSʱΪÔö¼ÓÐÅÁî¸ú×Ù¶øÔö¼ÓµÄʼþºÅ*/
+#define TOOL_NGMAC_PKTPGREQ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 58)
+#define TOOL_NGMAC_CTRLBLOCK_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 59)
+#define NGMAC_TOOL_CCF_IND_EV (DWORD)(NGMAC_EVENT_BASE + 60) /*NGMACÏòTOOL·¢Ë͵ÄPACKET CELL CHANGE FAILUREÏûÏ¢*/
+#define NGMAC_NGRLC_EPDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 61) /*NGMAC¸øNGRLC·¢ËÍEPDANÏûÏ¢*/
+#define TOOL_NGMAC_PSHOCMD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 62) /*TOOLÇëÇóNGMAC·¢ËÍPs Handover Command*/
+#define TOOL_NGMAC_PPI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 63) /*TOOLÇëÇóNGMAC·¢ËÍPacket Physical Information*/
+#define TOOL_NGMAC_PSHO_ULTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 64) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_DLTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 65) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_RETURN_EV (DWORD)(NGMAC_EVENT_BASE + 66) /*TOOL ֪ͨNGMAC ×ÊÔ´»ØÍË*/
+#define TOOL_NGMAC_PSHO_REL_EV (DWORD)(NGMAC_EVENT_BASE + 67) /*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGMAC_TOOL_PSHO_ACC_EV (DWORD)(NGMAC_EVENT_BASE + 68) /*NGMACÏòTOOLÇëÇóPacket Physical Information*/
+#define TOOL_NGMAC_PKTSCELLSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 69) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVING CELL SI*/
+#define TOOL_NGMAC_PKTAPPINF_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 70) /*TOOLÇëÇóNGMAC·¢ËÍPACKET APPLICATION INFORMATION*/
+
+
+/* ========================================================================
+ NLLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLLC_START_EV (DWORD)(NLLC_EVENT_BASE + 0) /*NLLCÄ£¿éÆô¶¯*/
+#define NLLC_NRLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 1) /*֪ͨNRLCÒÔ·ÇÈ·ÈÏģʽ´«ÊäLLC-PDU*/
+#define NRLC_NLLC_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 2) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸öÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define NRLC_NLLC_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 3) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸ö·ÇÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define TOOL_NLLC_ASSIGN_REQ_EV (DWORD)(NLLC_EVENT_BASE + 4) /*¹¤¾ß֪ͨ NLLCÓÐеļÓÃÜËã·¨ºÍ²ÎÊý£¬ÒÔ¼°·ÖÅäTLLI*/
+#define TOOL_NLLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 5) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÓÃÎÞÓ¦´ð´«Êä*/
+#define NLLC_TOOL_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 6) /*NLLC²ãÏòÉϲ㴫ËÍÒÔ·ÇÈ·ÈÏģʽ½ÓÊÕµ½µÄL3_PDU*/
+#define TOOL_NLLC_DATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 7) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÈ·ÈÏ´«Êä*/
+#define NLLC_TOOL_FRMR_RSP_EV (DWORD)(NLLC_EVENT_BASE + 8) /*ÊÕµ½¾Ü¾øÖ¡*/
+#define NLLC_TOOL_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 9) /*NLLCÏòÉϲ㴫ËͽÓÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_DATA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 10) /*¹¤¾ß²àÏìÓ¦ÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_ESTABLISH_REQ_EV (DWORD)(NLLC_EVENT_BASE + 11) /*ÓÃÓÚΪNLLC²ãÖÐÒ»¸öSAPI½¨Á¢»òÖؽ¨ABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_ESTABLISH_RSP_EV (DWORD)(NLLC_EVENT_BASE + 12) /*ÉϲãÔÚ½ÓÊÕµ½LL_ESTABLISHָʾÔÓïÖ®ºóʹÓÃ.Ö÷ÒªÊÇÐÉÌXID²ÎÊý*/
+#define NLLC_TOOL_UA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 13) /*ÊÕµ½UA·µ»Ø*/
+#define NLLC_TOOL_ESTABLISH_IND_EV (DWORD)(NLLC_EVENT_BASE + 14) /*ÓÃÓÚ֪ͨÉϲã²ã¶ÔNLLC²ãÖеÄÒ»¸öSAPIÒѾ½¨Á¢»òÒѾÖؽ¨ÆðÁËABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_RELEASE_REQ_EV (DWORD)(NLLC_EVENT_BASE + 15) /*ÓÃÓÚÊÍ·ÅΪNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽ*/
+#define NLLC_TOOL_DM_RSP_EV (DWORD)(NLLC_EVENT_BASE + 16) /*ÊÕµ½DM·µ»Ø*/
+#define NLLC_TOOL_RELEASE_IND_EV (DWORD)(NLLC_EVENT_BASE + 17) /*ÓÃÓÚָʾNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽÒѱ»ÊÍ·Å*/
+#define TOOL_NLLC_RELEASE_RSP_EV (DWORD)(NLLC_EVENT_BASE + 18) /*ÓÃÓÚ¹¤¾ß֪ͨNLLC·µ»Ø³É¹¦ÊÍ·ÅÏìÓ¦*/
+#define TOOL_NLLC_XID_REQ_EV (DWORD)(NLLC_EVENT_BASE + 19) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÇëÇó*/
+#define TOOL_NLLC_XID_RSP_EV (DWORD)(NLLC_EVENT_BASE + 20) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÏìÓ¦*/
+#define NLLC_TOOL_XID_CNF_EV (DWORD)(NLLC_EVENT_BASE + 21) /*ÓÃÓÚÈ·ÈÏÉϲãXID²ÎÊýÐÉÌÍê³É*/
+#define NLLC_TOOL_XID_IND_EV (DWORD)(NLLC_EVENT_BASE + 22) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐXID²ÎÊýÐèÒªÐÉÌ*/
+#define NLLC_TOOL_NULL_IND_EV (DWORD)(NLLC_EVENT_BASE + 23) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐNULLÖ¡*/
+
+
+/* ========================================================================
+ NRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NRLC_DATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 0)
+#define NRLC_UNITDATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 1)
+#define NRLC_ASSIGN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 2)
+#define TOOL_NGRLC_ULTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 3)
+#define TOOL_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 4)
+#define TOOL_NGRLC_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 5)
+#define NGRLC_TOOL_DLTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 6)
+#define NGRLC_TOOL_DLTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 7)
+#define NGRLC_TOOL_ULTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 8)
+#define NGRLC_TOOL_ULTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 9)
+#define TOOL_NGRLC_ULTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 10)
+#define NGRLC_TOOL_ULTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 11)
+#define TOOL_NGRLC_DLTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 12)
+#define TOOL_NGRLC_DLTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 13)
+#define TOOL_NGRLC_EXTBF_ON_EV (DWORD)(NRLC_EVENT_BASE + 14)
+#define TOOL_NGRLC_EXTBF_OFF_EV (DWORD)(NRLC_EVENT_BASE + 15)
+#define NGRLC_TOOL_DLTBF_TRIGGER_IND_EV (DWORD)(NRLC_EVENT_BASE + 16)
+#define NGRLC_START_TIMER_EV (DWORD)(NRLC_EVENT_BASE + 17) /*ÄÚ²¿ÏûÏ¢£¬ÆäËûÄ£¿é²»»áʹÓÃ*/
+#define NGRLC_TOOL_DLTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 18)
+#define TOOL_NGRLC_BEGINTEST_MODE_EV (DWORD)(NRLC_EVENT_BASE + 19)
+#define NGRLC_TOOL_PDANNOTIFY_EV (DWORD)(NRLC_EVENT_BASE + 20)
+#define NGRLC_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 21)
+#define NGRLC_FILL_DATA_QUEUE_REQ_EV (DWORD)(NRLC_EVENT_BASE + 22)
+#define L1SIMU_NGRLC_DATA_IND_EV (DWORD)(NRLC_EVENT_BASE + 23)
+#define TOOL_NGRLC_MODE_CFG_REQ_EV (DWORD)(NRLC_EVENT_BASE + 24)
+#define NGRLC_TOOL_UL_DATA_BLOCK_IND_EV (DWORD)(NRLC_EVENT_BASE + 25)
+#define TOOL_NGRLC_DUMMYBLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 26)
+#define DOWNLINK_DUMMY_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 27)
+#define TOOL_NGRLC_DOWNLINK_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 28)
+#define TOOL_NGRLC_PSHO_ULTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 29)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 30)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_RETURN_EV (DWORD)(NRLC_EVENT_BASE + 31)/*TOOL ֪ͨNGRLC ×ÊÔ´»ØÍË*/
+#define TOOL_NGRLC_PSHO_REL_EV (DWORD)(NRLC_EVENT_BASE + 32)/*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGRLC_TOOL_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 33)/*NGRLC ֪ͨTOOL PSHO ³É¹¦*/
+#define NGRLC_NGMAC_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 34)/*NGRLC ֪ͨNGMAC PSHO ³É¹¦*/
+/* ========================================================================
+ URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 0)
+#define URRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 1)
+#define URRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 2)
+#define URRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 3)
+#define URRC_FUNC_ENTER_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 4)
+#define URRC_FUNC_READ_SIB_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 5)
+#define URRC_FUNC_READ_SIB_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 6)
+#define URRC_FUNC_SER_CELL_IND_EV (DWORD)(URRC_FUNC_EVENT_BASE + 7)
+#define URRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 8)
+#define URRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 9)
+#define URRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 10)
+#define URRC_FUNC_START_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 11)
+#define URRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 12)
+#define URRC_FUNC_PAGING_TYPE1_EV (DWORD)(URRC_FUNC_EVENT_BASE + 13)
+#define URRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 14)
+#define URRC_FUNC_GET_UE_CAP_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 15)
+#define URRC_FUNC_CFG_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 16)
+#define URRC_FUNC_CFG_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 17)
+#define URRC_FUNC_REL_FACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 18)
+#define URRC_FUNC_REL_FACH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 19)
+#define URRC_FUNC_REL_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 20)
+#define URRC_FUNC_REL_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 21)
+#define URRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 22)
+#define URRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 23)
+#define URRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 24)
+#define URRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 25)
+#define URRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 26)
+#define URRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(URRC_FUNC_EVENT_BASE + 27)
+#define URRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(URRC_FUNC_EVENT_BASE + 28)
+#define URRC_FUNC_STOP_SYSINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 29)
+#define URRC_FUNC_READ_CGIINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 30)
+#define URRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 31)
+#define URRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 32)
+
+/* ========================================================================
+ TAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TAF_FUNC_L1G_DATA_REQ_EV (DWORD)(TAF_FUNC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1GÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1G_ST_MEAS_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 0)
+#define L1G_ST_MEAS_IND_EV (DWORD)(L1G_ST_EVENT_BASE + 1)
+#define L1G_ST_FCB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 2)
+#define L1G_ST_FCB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 3)
+#define L1G_ST_SYNC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 4)
+#define L1G_ST_BSIC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 5)
+#define L1G_ST_SB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 6)
+#define L1G_ST_RX_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 7)
+#define L1G_ST_RX_EQU_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 8)
+#define L1G_ST_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 9)
+#define L1G_ST_RACH_EV (DWORD)(L1G_ST_EVENT_BASE + 10)
+#define L1G_ST_SDCCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 11)
+#define L1G_ST_SACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 12)
+#define L1G_ST_SACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 13)
+#define L1G_ST_FACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 14)
+#define L1G_ST_FACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 15)
+#define L1G_ST_DS_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 16)
+#define L1G_ST_DS_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 17)
+#define L1G_ST_TCH_CTRL_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 18)
+
+/* ========================================================================
+ GRRº¯Êý¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GRR_FUNC_SUSPEND_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 0)
+#define GRR_FUNC_RESUME_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 1)
+#define GRR_FUNC_SUSPEND_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 2)
+#define GRR_FUNC_RESUME_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 3)
+#define GRR_FUNC_IDLE_MODE_SETTING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 4)
+#define GRR_FUNC_LIST_HANDLING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 5)
+#define GRR_FUNC_SCELL_UPDATE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 6)
+#define GRR_FUNC_INIT_SCELL_PARAM_EV (DWORD)(GRR_FUNC_EVENT_BASE + 7)
+#define GRR_FUNC_INIT_GRR_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 8)
+#define GRR_FUNC_INIT_GRR_SCELL_TMP_EV (DWORD)(GRR_FUNC_EVENT_BASE + 9)
+#define GRR_FUNC_INIT_MI_EV (DWORD)(GRR_FUNC_EVENT_BASE + 10)
+#define GRR_FUNC_SI2QUATER_COMPLETE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 11)
+#define GRR_FUNC_CELL_SEL_BCCH_ALL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 12)
+#define GRR_FUNC_CELL_SEL_BCCH_MIN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 13)
+#define GRR_FUNC_RESET_SYSINFO_EV (DWORD)(GRR_FUNC_EVENT_BASE + 14)
+#define GRR_FUNC_STORE_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 15)
+#define GRR_FUNC_STORE_MODIFY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 16)
+#define GRR_FUNC_COPY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 17)
+#define GRR_FUNC_INDIVID_PRIORITY_CHANGE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 18)
+#define GRR_FUNC_GET_QSEARCH_EV (DWORD)(GRR_FUNC_EVENT_BASE + 19)
+#define GRR_FUNC_COPY_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 20)
+
+
+/* ========================================================================
+ αÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GAS_ST_CTRL_BLOCK_TLV_EV (DWORD)(SIGTRACE_EVENT_BASE + 0) /*GRRÏûÏ¢¶ÔµÈ²ãÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_UL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 1) /*GMAC¶ÔµÈ²ãÉÏÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 2) /*GMAC¶ÔµÈ²ãÏÂÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_SEG_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 3) /*GMAC¶ÔµÈ²ãÏÂÐзֶÎÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DLL_READ_DCCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 4)
+#define GAS_ST_DLL_READ_SACCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 5)
+#define ATI_PDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 6)
+#define UPDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 7)
+#define SN_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 8)
+#define SN_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 9)
+#define LL_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 10)
+#define LL_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 11)
+#define LLC_GET_NEXT_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 12)
+#define GMAC_GET_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 13)
+#define GMAC_ACK_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 14)
+#define PDCP_RLC_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 15)
+#define URLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 16)
+#define URLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 17)
+#define UMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 18)
+#define PH_MAC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 19)
+#define PH_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 20)
+#define MAC_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 21)
+#define RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 23)
+#define LL_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 24)
+#define LL_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 25)
+#define SN_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 26)
+#define SN_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 27)
+#define UPDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 28)
+#define ATI_PDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 29)
+#define UUMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 30)
+#define PDCP_RLC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 31)
+#define TAF_COUNTER_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 32)
+#define TAF_RLP_XID_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 33)
+#define TAF_RLP_XID_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 34)
+#define TAF_RLP_SABM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 35)
+#define TAF_RLP_SABM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 36)
+#define TAF_RLP_UA_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 37)
+#define TAF_RLP_UA_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 38)
+#define TAF_RLP_DISC_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 39)
+#define TAF_RLP_DISC_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 40)
+#define TAF_RLP_DM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 41)
+#define TAF_RLP_DM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 42)
+#define TAFL1G_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 43)
+#define TAFL1G_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 44)
+#define TAF_FUNC_UURLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 45)
+#define TAF_FUNC_UURLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 46)
+#define PDI_PDCP_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 47)
+#define PDCP_DATA_BACK_PDI_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 48)
+/*WCDMA(SIGIRACE=100)*/
+#define WRLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 49)
+#define WRLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 50)
+#define WMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 51)
+#define UWMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 52)
+#define TAF_FUNC_UWRLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 53)
+#define TAF_FUNC_UWRLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 54)
+#define WMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 55)
+#define WMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 56)
+#define EUMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 57)
+#define EUMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 58)
+#define EUMAC_HOLD_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 59)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ EMM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_T3410_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 0)
+#define EMM_T3416_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 1)
+#define EMM_T3417_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 2)
+#define EMM_T3418_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 3)
+#define EMM_T3420_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 4)
+#define EMM_T3421_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 5)
+#define EMM_T3430_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 6)
+#define EMM_T3440_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 7)
+#define EMM_T_POWEROFF_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 8)
+#define EMM_T3417EXT_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 9)
+#define EMM_T_WAITRELIND_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ ESM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_TIMER3480_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 0)
+#define ESM_TIMER3481_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 1)
+#define ESM_TIMER3482_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 2)
+#define ESM_TIMER3492_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 3)
+#define ESM_T_MTACTANSWER_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 4)
+#define ESM_T_WAITINGATH_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 5)
+#define ESM_T_PTIBUF_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 6)
+#define ESM_T_CMEST_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ EPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_T_DISCARD_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 0)
+#define EPDCP_T_DELAYMODEB_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 1)
+#define EPDCP_T_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ EURLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURLC_T_POLL_RETRANSMIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 0)
+#define EURLC_T_STATUS_PROHIBIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 1)
+#define EURLC_T_REORDERING_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 2)
+#define EUL2LOG_T_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 3)
+
+/* ========================================================================
+ EUMAC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMAC_T_EXPIRY_EV (DWORD)(EUMAC_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ EUCER×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_T300_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 0)
+#define EURRC_T301_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 1)
+#define EURRC_T302_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 2)
+#define EURRC_T303_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 3)
+#define EURRC_T304_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 4)
+#define EURRC_T305_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 5)
+#define EURRC_T310_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 6)
+#define EURRC_T311_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 7)
+#define EURRC_T60MS_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 8)
+#define EURRC_T3174_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 9)
+#define EURRC_VARRLF_VALID_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 10)
+#define EURRC_T306_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 11)
+#define EURRC_MCCH_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 12)
+#define EURRC_1SECOND_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 13)
+#define EURRC_TGPAGING_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 14)
+#define EURRC_PERIDOSTATUSREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 15)
+#define EURRC_SELFHOREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 16)
+#define EURRC_SINGLEUSEREXIT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 17)
+
+/* ========================================================================
+ EUMCR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMCR_T320_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 0)
+#define EUMCR_T321_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 1)
+#define EUMCR_T_REMAIN_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 2)
+#define EUMCR_T_LEAVE_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 3)
+#define EUMCR_T_HYSTNORMAL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 4)
+#define EUMCR_T_PROXIMITY_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 5)
+#define EUMCR_T_CELLINFO_REPORT_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 6)
+#define EUMCR_T_RESEL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 7)
+#define EUMCR_T_MDT_LOG_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 8)
+#define EUMCR_T330_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 9)
+#define EUMCR_T_48HOURS_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 10)
+#define EUMCR_T_LISTEN_HANDOVER_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 11)
+#define EUMCR_T_MONITOR_PERIOD_CHG_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 12)
+#define EUMCR_T_MONITOR_HO_EXPIR_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 13)
+/* ========================================================================
+ EUCSR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUCSR_T_SI_MODI_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 0)
+#define EUCSR_T_ABORT_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 1)
+#define EUCSR_T_FREQ_SCAN_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 2)
+#define EUCSR_T_CELL_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 3)
+#define EUCSR_T_PLMN_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 4)
+#define EUCSR_T_CSG_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 5)
+#define EUCSR_T_3HOUR_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 6)
+#define EUCSR_T_OOS_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 7)
+#define EUCSR_T_SWITCH_RADIO_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 8)
+#define EUCSR_T_REDIRECT_TO_LTE_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 9)
+#define EUCSR_T_SYNC_BARREDLIST_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 10)
+#define EUCSR_T_WAIT_RESEL_TO_UTRA_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 11)
+#define EUCSR_T_REDIRECT_TO_LTE_OP_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 12)
+#define EUCSR_T_LISTEN_RESEL_SUCC_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 13)
+#define EUCSR_T_LBS_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 14)
+#define EUCSR_T_ECID_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 15)
+
+
+/* ========================================================================
+ EUSIR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUSIR_T_SIB1GUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 0)
+#define EUSIR_T_SIMSGGUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 1)
+#define EUSIR_T_ETWS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 2)
+#define EUSIR_T_CMAS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 3)
+#define EUSIR_T_SIBVALID_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ EMMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_TU_SUCC_IND_EV (DWORD)(EMM_UMM_EVENT_BASE + 0)
+
+#define UMM_CONFIG_REQ_EV (DWORD)(EMM_UMM_RSP_EVENT + 0)
+
+/* ========================================================================
+ UMMºÍEPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_UMM_EST_REJ_EV (DWORD)(UMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_UMM_EST_REQ_EV (DWORD)(UMM_EPDCP_RSP_EVENT + 0)
+
+/* ========================================================================
+ CM²ãºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EMM_DATA_REQ_EV (DWORD)(CM_EMM_EVENT_BASE + 0)
+/* ========================================================================
+ ESMºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESM->EMM*/
+#define ESM_EMM_DEFAULT_ACT_REJ_EV (DWORD)(ESM_EMM_EVENT_BASE + 0)
+#define ESM_EMM_EMERGENCY_PDN_EST_SUCC_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 1)
+#define ESM_EMM_EMERGENCY_PDN_ONLY_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 2)
+
+/* EMM->ESM*/
+#define ESM_EMM_DATA_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 0)
+#define ESM_EMM_ATTACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 1)
+#define ESM_EMM_ATTACH_REJ_EV (DWORD)(ESM_EMM_RSP_EVENT + 2)
+#define ESM_EMM_CONTEXT_STATUS_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 3)
+#define ESM_EMM_DETACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 4)
+#define ESM_EMM_DETACH_EMERGENCY_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 5)
+#define EMM_ESM_DETACH_NORMAL_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 6)
+
+/* ========================================================================
+ EMMºÍASC(ERRC(CER))Ä£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_ASC_EST_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 1)
+#define EMM_ASC_EST_ABT_EV (DWORD)(EMM_ASC_EVENT_BASE + 2)
+#define EMM_ASC_REL_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 3)
+#define EMM_ASC_KENB_RSP_EV (DWORD)(EMM_ASC_EVENT_BASE + 4)
+#define EMM_ASC_REL_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 5)
+#define EMM_ASC_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 6)
+#define EMM_ASC_DETACH_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 7)
+
+/* EURRC->ASC */
+#define EMM_ASC_DATA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 0)
+#define EMM_ASC_EST_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 1)
+#define EMM_ASC_EST_REJ_EV (DWORD)(EMM_ASC_RSP_EVENT + 2)
+#define EMM_ASC_REL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 3)
+#define EMM_ASC_ABA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 4)
+#define EMM_ASC_DRB_SETUP_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 5)
+#define EMM_ASC_TRANS_FAIL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 6)
+#define EMM_ASC_KENB_REQ_EV (DWORD)(EMM_ASC_RSP_EVENT + 7)
+#define EMM_ASC_UE_INFO_CHANGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 8)
+#define EMM_ASC_DATA_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 9)
+#define EMM_ASC_PAGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 10)
+#define EMM_ASC_SEC_PARA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 11)
+/* ========================================================================
+ EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EPDCP_EMM_EST_REJ_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_EMM_BAR_ALLEVIATE_NOTIFY_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 1)
+/* ========================================================================
+ ESMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESMºÍUMMÄ£¿éÖ®¼äµÄÏûϢʼþºÅ--
+* 1.CM_EST_REQ_EV£¬
+* 2.CM_EST_CNF_EV£¬
+* 3.CM_RELIND_EVÑØÓÃÒÔÇ°90AµÄ½Ó¿Ú*/
+/*ESM->UMM*/
+#define ESM_UMM_DETACH_REQ_EV (DWORD)(ESM_UMM_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_UMM_LOCAL_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 1)
+
+/* ========================================================================
+ SMºÍESMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*SM->ESM*/
+#define SM_ESM_DATA_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 0) /*Added:KangShuJie*/
+#define SM_ESM_RAT_ACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define SM_ESM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define SM_ESM_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 3) /*Added:KangShuJie*/
+/*ESM->SM*/
+#define ESM_SM_DATA_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 0) /*Added:KangShuJie*/
+#define ESM_SM_RAT_ACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 1) /*Added:KangShuJie*/
+#define ESM_SM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 2) /*Added:KangShuJie*/
+#define ESM_SM_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 3) /*Added:KangShuJie*/
+
+
+/* ========================================================================
+ ESMºÍEPDCP*Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_EPDCP_DEACTIVATE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_MOVE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_DEL_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define ESM_EPDCP_DIAL_IND_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 3)
+#define DEL_USER_PLANE_BUFFER_DATA_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 4)
+
+#define ESM_EPDCP_LOCAL_DEACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 0)
+#define ESM_EPDCP_RAT_SEQ_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 1)
+#define ESM_EPDCP_RAT_ACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 2)
+#define ESM_EPDCP_RAT_CHANGE_COMP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 3) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_SEQ_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 4) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_ACT_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 5) /*Added:KangShuJie*/
+#define EPDCP_ESM_STATUS_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 6) /*Added:KangShuJie*/
+#define ESM_EPDCP_CURR_BEAR_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 7)
+
+/* ========================================================================
+ EURRCºÍEPDCPÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 0)
+#define EURRC_EPDCP_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 1)
+#define EURRC_EPDCP_DATA_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 2)
+#define EURRC_EPDCP_REESTABLISH_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 3)
+#define EURRC_EPDCP_RELEASE_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 4)
+#define EURRC_EPDCP_RESUME_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 5)
+#define EURRC_EPDCP_SUSPEND_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 6)
+#define EURRC_EPDCP_DECIPHER_AND_INT_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 7)
+#define EURRC_EPDCP_HO_SUCC_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 8)
+#define EURRC_EPDCP_HO_FAIL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 9)
+#define EURRC_EPDCP_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 10)/*Added:KangShuJie*/
+#define EURRC_EPDCP_SMC_END_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 11)
+#define EURRC_EPDCP_TRUNKING_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 12)
+#define EURRC_EPDCP_CELL_RESEL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 13)
+
+
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 0)
+#define EURRC_EPDCP_DATA_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 1)
+#define EURRC_EPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 2)
+#define EURRC_EPDCP_CONFIG_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 3)
+#define EURRC_EPDCP_DATA_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 4)
+#define EURRC_EPDCP_REESTABLISH_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 5)
+#define EURRC_EPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 6)
+/* ========================================================================
+ EURRCºÍEURLCÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EURLC_CONFIG_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EURLC_RELEASE_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+
+#define EURRC_EURLC_CONFIG_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EL2_EURRC_RADIOLINK_FAIL_IND_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EURRC_EL2_TRUNKCH_ERROR_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 3)
+/* ========================================================================
+ EURRCºÍEUMACÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EURRC_EUMAC_CCCH_DATA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_COMM_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_DEDI_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_REL_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 3) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESET_MAC_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 4) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESUME_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 5) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_SUSPEND_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 6) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 7) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_HO_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 8)
+#define EURRC_EUMAC_REL_DEDI_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 11)
+#define EURRC_EUMAC_GRNTI_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 12)
+#define EURRC_EUMAC_SR_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 13)
+#define EURRC_EUMAC_LISTENINGCFG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 14)
+
+#define EUMAC_EURRC_CCCH_DATA_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_PROBLEM_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_SUCC_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_HO_CNF_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 3)
+#define EUMAC_EURRC_PUCCH_SRS_REL_REQ (DWORD)(EURRC_EUMAC_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define EURLC_EPDCP_UM_DATA_CNF_EV (DWORD)(EUPDCP_EURLC_EVENT_BASE + 0)
+
+/* ========================================================================
+ EURRCºÍMEL2Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EUMAC_MCH_CONFIG_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 0)
+#define EURRC_EUMAC_MCH_REL_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 1)
+#define MEL2_DMA_COMPLETE_IND (DWORD)(EURRC_MEL2_EVENT_BASE + 2)
+#define EUMAC_EURRC_MCCH_DATA_IND_EV (DWORD)(EURRC_MEL2_RSP_EVENT + 0)
+
+/* ========================================================================
+ EURRCÄÚ²¿ÏûϢʼþºÅ¶¨Òå
+======================================================================== */
+/*EUCER-EUMCR*/
+#define EURRC_MCR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 0)
+#define EURRC_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 1)
+#define EURRC_IDLE_INFO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 2)
+
+#define EURRC_SCELL_UNSUITABLE_IND_EV (DWORD)(EURRC_EVENT_BASE + 3)
+#define EURRC_CER_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 4)
+
+/*EUCER-EUCSR*/
+#define EURRC_CSR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 5)
+#define EURRC_CELL_INFO2NAS_EV (DWORD)(EURRC_EVENT_BASE + 6)
+#define EURRC_BARRED_CELL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 7)
+#define EURRC_REL_EPHY_CNF_EV (DWORD)(EURRC_EVENT_BASE + 8)
+
+#define EURRC_CER_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 9)
+#define EURRC_CELL_SEL_SUCC_IND_EV (DWORD)(EURRC_EVENT_BASE + 10)
+#define EUCER_TRS_TEST_IND_EV (DWORD)(EURRC_EVENT_BASE + 11)
+#define EURRC_REL_EPHY_REQ_EV (DWORD)(EURRC_EVENT_BASE + 12)
+/*EUCER-EUSIR*/
+
+#define EURRC_CER_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 13)
+
+/*EUCSR-EUMCR*/
+#define EURRC_CELL_RESEL_REJ_EV (DWORD)(EURRC_EVENT_BASE + 14)
+#define EURRC_PLMN_SEL_IND_EV (DWORD)(EURRC_EVENT_BASE + 15)
+#define EURRC_MCR_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 16)
+
+#define EURRC_CELL_RESEL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 17)
+#define EURRC_CSR_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 18)
+/*EUCSR-EUSIR*/
+
+#define EURRC_READ_SI_REQ_EV (DWORD)(EURRC_EVENT_BASE + 19)
+#define EURRC_ABORT_SI_READ_REQ_EV (DWORD)(EURRC_EVENT_BASE + 20)
+
+#define EURRC_CSR_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 21)
+#define EURRC_CSG_IND_EV (DWORD)(EURRC_EVENT_BASE + 22)
+#define EURRC_WARNING_NOTIFY_INFO_EV (DWORD)(EURRC_EVENT_BASE + 23)
+
+/*EUCSR-EUCER*/
+#define EURRC_CER_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 24)
+
+
+/*UMCR-EUSIR*/
+ /*UMCR-EUSIR ͬEURRC_READSI_REQ_EV
+ EURRC_ABORTSIREAD_REQ_EV */
+
+#define EURRC_MCR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 25)
+#define EURRC_CGI_CNF_EV (DWORD)(EURRC_EVENT_BASE + 26)
+#define EURRC_GET_RF_REQ_EV (DWORD)(EURRC_EVENT_BASE + 27)
+#define EURRC_GET_RF_CNF_EV (DWORD)(EURRC_EVENT_BASE + 28)
+#define EURRC_CSG_PROXIMITY_IND_EV (DWORD)(EURRC_EVENT_BASE + 29)
+#define EURRC_SI_END_FOR_HO_EV (DWORD)(EURRC_EVENT_BASE + 30)
+#define EURRC_MDT_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 31)
+#define EURRC_MCR_CGI_PEND_REQ_EV (DWORD)(EURRC_EVENT_BASE + 32)
+#define EURRC_MCR_CGI_PEND_CNF_EV (DWORD)(EURRC_EVENT_BASE + 33)
+#define EURRC_INTEREST_FREQ_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 34)
+#define EURRC_CER_SELFHO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 35)
+#define EURRC_NETWORK_TIME_INFO_IND_EV (DWORD)(EURRC_EVENT_BASE + 36)
+#define EURRC_RRC_STATE_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 37)
+#define EURRC_EUCER_RESUME_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 38)
+#define EURRC_EUCER_ABORT_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 39)
+#define EURRC_CSR_XCELL_IND_EV (DWORD)(EURRC_EVENT_BASE + 40)
+#define EURRC_EUMCR_START_MEAS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 41)
+#define EURRC_CSR_RESEL_START_EV (DWORD)(EURRC_EVENT_BASE + 42)
+#define EURRC_CSR_RESEL_END_EV (DWORD)(EURRC_EVENT_BASE + 43)
+#define EURRC_CSR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 44)
+//LBS
+#define EURRC_CELL_MEAS_IND_EV (DWORD)(EURRC_EVENT_BASE + 45)
+#define EURRC_EUMCR_START_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 46)
+#define EURRC_EUMCR_STOP_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 47)
+#define EURRC_EUCER_UE_INFO_RLF_9E0_EV (DWORD)(EURRC_EVENT_BASE + 48)
+#define EURRC_EUCER_UE_CAPA_LTE_9D0_EV (DWORD)(EURRC_EVENT_BASE + 49)
+#define EURRC_MEAS_GAP_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 50)
+#define EURRC_CER_REL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 51)
+
+
+/*EURRC<->L1E*/
+#define EURRC_L1E_MEAS_SUSPEND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 0)
+#define EURRC_L1E_MEAS_RESUME_EV (DWORD)(EURRC_L1E_EVENT_BASE + 1)
+#define EURRC_L1E_GSM_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 2)
+#define EURRC_L1E_UTRA_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 3)
+#define EURRC_L1E_GSM_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 4)
+#define EURRC_L1E_TD_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 5)
+#define EURRC_L1E_RESOURCE_REL_EV (DWORD)(EURRC_L1E_EVENT_BASE + 6)
+#define EURRC_L1E_RESOURCE_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 7)
+#define EURRC_L1E_SI_END_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 8)
+#define EURRC_L1E_GET_RF_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 9)
+#define EURRC_L1E_STATE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 10)
+#define EURRC_L1E_TRACE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 11)
+#define EURRC_L1E_W_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 12)
+#define EURRC_L1E_IRAT_CGI_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 13)
+#define EURRC_L1E_IRAT_CGI_END_EV (DWORD)(EURRC_L1E_EVENT_BASE + 14)
+
+#define L1E_EURRC_RESOURCE_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 0)
+#define L1E_EURRC_GSM_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 1)
+#define L1E_EURRC_TD_LIST_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 2)
+#define L1E_EURRC_TD_BLIND_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 3)
+#define EURRC_L1E_GET_RF_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 4)
+#define L1E_EURRC_W_MEAS_RLT_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 5)
+/* ========================================================================
+ LTEÐÒéÕ»ºÍÎïÀí²ãÏûϢʼþÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* PS -> EPHY MSG ID */
+#define LTE_P_FREQ_SCAN_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 0)
+#define LTE_P_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 1)
+#define LTE_P_READ_SIB1_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 2)
+#define LTE_P_SCHED_SI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 3)
+#define LTE_P_ABORT_SI_READ_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 4)
+#define LTE_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 5)
+#define LTE_P_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 6)
+#define LTE_P_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 7)
+#define LTE_P_MEAS_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 8)
+#define LTE_P_ABORT_MEAS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 9)
+#define LTE_P_EARFCN_BAND_INFO_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 10)
+#define LTE_P_COMMON_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 11)
+#define LTE_P_DEDICATED_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 12)
+#define LTE_P_HANDOVER_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 13)
+#define LTE_P_MAC_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 14)
+#define LTE_P_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 15)
+#define LTE_P_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 16)
+#define LTE_P_ABORT_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 17)
+#define LTE_P_TA_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 18)
+#define LTE_P_DRX_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 19)
+#define LTE_P_TA_TIMER_STOP_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 20)
+#define LTE_P_FREQ_LIST_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 21)
+#define LTE_P_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 22)
+#define LTE_P_ABORT_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 23)
+#define LTE_P_IRAT_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 24)
+#define LTE_P_IDLE_PERIOD_REP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 25)
+#define LTE_P_SET_MODE_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 26)
+#define LTE_P_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 27)
+#define LTE_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 28)
+#define LTE_P_WAKEUP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 29)
+#define ZPS_LTE_ZEPCG_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 30)
+#define LTE_P_GRNTI_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 31)
+#define LTE_P_BTRUNK_TTCH_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 32)
+#define LTE_P_DEDICATECD_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 33)
+#define LTE_P_BTRUNK_CONFIG_REL_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 34)
+#define LTE_P_ACT_DEACT_SCELL_CTRL_ELEMNT_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 35)
+#define LTE_P_MCCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 36)
+#define LTE_P_MTCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 37)
+#define LTE_P_MTCH_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 38)
+#define LTE_P_PMCH_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 39)
+#define LTE_P_MSI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 40)
+#define LTE_P_CARD2_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 41) /*T_zLTE_P_card2_gap_req*/
+#define LTE_P_CARD2_GAP_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 42) /*T_zLTE_P_card2_gap_rel_req*/
+#define LTE_P_CARD2_STOP_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 43) /*T_zLTE_P_card2_stop_gap_req*/
+#define LTE_P_CARD1_SUSPEND_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 44) /*T_zLTE_P_card1_suspend_req*/
+#define LTE_P_CARD1_RESUME_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 45) /*T_zLTE_P_card1_resume_req*/
+#define LTE_P_MEAS_PERIOD_CHG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 46)
+#define LTE_P_AMT_MSG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 47)
+#define LTE_P_RPI_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 48)
+#define LTE_P_RPI_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 49)
+#define LTE_P_OTDOA_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 50)
+#define LTE_P_OTDOA_MEAS_ABORT_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 51)
+#define ZPS_LTE_CARD_SWITCH_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 52)
+
+
+
+/* EPHY -> PS MSG ID */
+#define LTE_P_SI_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 0)
+#define LTE_P_PBCH_READ_FAIL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 1)
+#define LTE_P_FREQ_SCAN_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 2)
+#define LTE_P_CELL_SEARCH_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 3)
+#define LTE_P_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 4)
+#define LTE_P_INTRA_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 5)
+#define LTE_P_INTER_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 6)
+#define LTE_P_DRX_STATE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 7)
+#define LTE_P_HANDOVER_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 8)
+#define LTE_P_OUT_OF_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 9)
+#define LTE_P_RECOVERY_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 10)
+#define LTE_P_PUCCH_SRS_REL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 11)
+#define LTE_P_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 12)
+#define LTE_P_ACCESS_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 13)
+#define LTE_P_EUMAC_INIT_RA_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 14)
+#define LTE_P_RA_RESPONSE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 15)
+#define LTE_P_DLSCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 16)
+#define LTE_P_IRAT_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 17)
+#define LTE_P_ABORT_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 18)
+#define LTE_P_RESET_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 19)
+#define LTE_P_INACTIVE_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 20)
+#define LTE_P_SLEEP_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 21)
+#define ZPS_LTE_ZEPCG_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 22)
+#define LTE_P_EMBMS_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 23)
+#define LTE_P_ULGRANT_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 24)
+#define LTE_P_OTDOA_MEAS_RLT_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 25)
+#define LTE_P_C0_SAVE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 26)
+#define LTE_P_BTRUNK_CQI_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 27)
+#define LTE_P_LISTENINGHO_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 28)
+#define LTE_P_BTRUNK_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 29)
+#define EPDCP_EDCP_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 30)
+#define EURLC_EMAC_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 31)
+#define LTE_P_CARD2_GAP_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 32) /*T_zLTE_P_card2_gap_ind*/
+#define LTE_P_CARD2_GAP_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 33)
+#define LTE_P_CARD2_STOP_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 34)
+#define LTE_P_CARD1_SUSPEND_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 35)
+#define LTE_P_PHYWAKEUPPS_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 36)
+#define LTE_P_ICP_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 37)
+#define LTE_P_AMT_MSG_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 38)
+#define ZPS_LTE_CARD_SWITCH_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 39)
+
+
+#if 0
+#define LTE_P_RF_ERR_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 40)
+#endif
+
+
+/* ========================================================================
+ LTEÐÒéÕ»ºÍTRSÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TRS_ESM_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 0)
+#define TRS_ESM_L3TC_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 1)
+#define TRS_ESM_ACT_DED_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 0)
+#define TRS_ESM_ACT_DED_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 1)
+#define TRS_ESM_ACT_DEF_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 2)
+#define TRS_ESM_ACT_DEF_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 3)
+#define TRS_ESM_BR_ALLOC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 4)
+#define TRS_ESM_BR_MOD_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 5)
+#define TRS_ESM_DEACT_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 6)
+#define TRS_ESM_ESMINFO_RSP_EV (DWORD)(TRS_ESM_RSP_EVENT + 7)
+#define TRS_ESM_ESMSTATUS_EV (DWORD)(TRS_ESM_RSP_EVENT + 8)
+#define TRS_ESM_MOD_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 9)
+#define TRS_ESM_MOD_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 10)
+#define TRS_ESM_PDN_CON_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 11)
+#define TRS_ESM_PDN_DISC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 12)
+#define TRS_ESM_L3TC_CLOSE_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 13)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 14)
+#define TRS_ESM_L3TC_ACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 15)
+#define TRS_ESM_L3TC_DEACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 16)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMBMSPACKETCNT_RESP_EV (DWORD)(TRS_ESM_RSP_EVENT + 17)
+/* TRS -> MME_EMM */
+#define TRS_EMM_DATA_REQ_EV (DWORD)(TRS_EMM_EVENT_BASE + 0)
+#define TRS_EMM_MAPPED_SEC_PARAM_Ev (DWORD)(TRS_EMM_EVENT_BASE + 1)
+#define TRS_EMM_PS_HO_FROM_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 2)
+#define TRS_EMM_PS_HO_TO_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 3)
+/* MME_EMM ->TRS */
+#define ENB_TRS_ESM_CMD_EV (DWORD)(TRS_EMM_RSP_EVENT + 0)
+#define TRS_EMM_L3MSG_ATTACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 1)
+#define TRS_EMM_L3MSG_ATTACH_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 2)
+#define TRS_EMM_L3MSG_AUTH_FAIL_EV (DWORD)(TRS_EMM_RSP_EVENT + 3)
+#define TRS_EMM_L3MSG_AUTH_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 4)
+#define TRS_EMM_L3MSG_AUTH_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 5)
+#define TRS_EMM_L3MSG_DETACH_APT_EV (DWORD)(TRS_EMM_RSP_EVENT + 6)
+#define TRS_EMM_L3MSG_DETACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 7)
+#define TRS_EMM_L3MSG_ULNAS_TRANS_EV (DWORD)(TRS_EMM_RSP_EVENT + 8)
+#define TRS_EMM_L3MSG_SERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 9)
+#define TRS_EMM_L3MSG_EXSERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 10)
+#define TRS_EMM_L3MSG_GUTI_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 11)
+#define TRS_EMM_L3MSG_IDNT_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 12)
+#define TRS_EMM_L3MSG_SMC_COM_EV (DWORD)(TRS_EMM_RSP_EVENT + 13)
+#define TRS_EMM_L3MSG_SMC_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 14)
+#define TRS_EMM_L3MSG_TAU_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 15)
+#define TRS_EMM_L3MSG_TAU_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 16)
+#define TRS_EMM_L3MSG_EMMSTATUS_EV (DWORD)(TRS_EMM_RSP_EVENT + 17)
+#define TRS_EMM_DATA_IND_EV (DWORD)(TRS_EMM_RSP_EVENT + 18)
+
+#define ENB_EMM_ESM_DATA_REQ_EV (DWORD)(ENB_EMM_ESM_EVENT_BASE + 0)
+#define ENB_EMM_ESM_DATA_IND_EV (DWORD)(ENB_EMM_ESM_RSP_EVENT + 0)
+/* MME_EMM -> ENBRRC */
+#define ENB_RRC_EMM_DATA_REQ_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 0)
+#define ENB_RRC_EMM_DLSQN_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 1)
+/* ENBRRC -> MME_EMM */
+#define ENB_RRC_EMM_DATA_IND_EV (DWORD)(ENB_RRC_EMM_RSP_EVENT + 0)
+
+
+/* ÆäËüLTE²âÊÔÄ£¿éÏûÏ¢IDºêÌí¼Ó´¦*/
+#define ENBRRC_RRC_CONN_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 0)
+#define ENBRRC_RRC_CONN_SETUP_EV (DWORD)(ENB_RRC_EVENT_BASE + 1)
+#define ENBRRC_RRC_CONN_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 2)
+#define ENBRRC_RRC_CONN_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 3)
+#define ENBRRC_SEC_MODE_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 4)
+#define ENBRRC_SEC_MODE_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 5)
+#define ENBRRC_SEC_MODE_FAIL_EV (DWORD)(ENB_RRC_EVENT_BASE + 6)
+#define ENBRRC_RRC_CONN_RECONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 7)
+#define ENBRRC_RRC_CONN_RECONFIG_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 8)
+#define ENBRRC_RRC_CONN_REEST_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 9)
+#define ENBRRC_RRC_CONN_REEST_EV (DWORD)(ENB_RRC_EVENT_BASE + 10)
+#define ENBRRC_RRC_CONN_REEST_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 11)
+#define ENBRRC_RRC_CONN_REEST_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 12)
+#define ENBRRC_RRC_CONN_REL_EV (DWORD)(ENB_RRC_EVENT_BASE + 13)
+#define ENBRRC_UE_CAP_ENQUIRY_EV (DWORD)(ENB_RRC_EVENT_BASE + 14)
+#define ENBRRC_UE_CAP_INFO_EV (DWORD)(ENB_RRC_EVENT_BASE + 15)
+#define ENBRRC_UE_MEAS_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 16)
+#define ENB_NASRRC_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 17)
+#define ENB_NASRRC_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 18)
+#define TRS_EPHY_UE_MEAS_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 19)
+#define TRS_EPHY_UE_CER_HO_REQ_CTL_EV (DWORD)(ENB_RRC_EVENT_BASE + 20)
+#define ENBRRC_COUNTER_CHECK_SUCC_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 21)
+#define ENBRRC_COUNTER_CHECK_FAIL_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 22)
+#define ENBRRC_MOBILITY_FROM_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 23)
+#define ENBRRC_START_HO_FROM_EUTRA_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 24)
+#define ENBRRC_START_HO_TO_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENBRRC_PROXIMITY_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 26)
+#define ENBRRC_UE_INFO_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 27)
+#define ENBRRC_UE_INFO_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 28)
+#define ENBRRC_MBSFN_AREA_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 29)
+#define ENBRRC_MBMS_COUNTING_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 30)
+#define ENBRRC_TDLINFO_TRANS_EV (DWORD)(ENB_RRC_EVENT_BASE + 31)
+#define ENBRRC_GROUPCALL_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 32)
+#define ENBRRC_GROUPCALL_RELEASE_EV (DWORD)(ENB_RRC_EVENT_BASE + 33)
+#define ENRRC_NEIGHBOURINFO_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+
+#define ENRRC_ENPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 0)
+#define ENRRC_ENPDCP_CONFIG_CIPHER_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 1)
+#define ENRRC_ENPDCP_CONFIG_INTEGRITY_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 2)
+#define ENRRC_ENPDCP_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 3)
+#define ENRRC_ENPDCP_DATA_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 4)
+#define ENRRC_ENPDCP_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 5)
+#define ENRRC_ENPDCP_RELEASE_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 6)
+#define ENRRC_ENPDCP_RESUME_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 7)
+#define ENRRC_ENPDCP_SUSPEND_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 8)
+#define ENRRC_ENPDCP_DECIPHER_AND_INTCHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 9)
+#define ENRRC_ENPDCP_SEC_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 10)
+
+#define ENRRCENPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 0)
+#define ENRRCENPDCP_DATA_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 1)
+#define ENRRCENPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 2)
+#define ENRRCENPDCP_CONFIG_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 3)
+#define ENRRCENPDCP_DATAC_NF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 4)
+#define ENRRCENPDCP_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 5)
+#define ENRRCENPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 6)
+#define ENRRCENPDCP_ENABLE_UL_DECIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 7)
+#define ENRRCENPDCP_COUNTER_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 8)
+#define ENRRCENPDCP_MDT_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 9)
+
+#define ENPDCP_EDCP_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 0)
+#define ENRLC_ENMAC_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 1)
+/* ========================================================================
+ ENPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDCP_DISCARDTIMER_EV (DWORD)(ENPDCP_TIMER_EVENT_BASE + 0)
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDI_DATA_REQ_EV (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 0)
+
+#define ENPDI_DATA_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 0)
+#define ENPDI_NOT_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 1)
+#define ENPDI_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 2)
+
+
+/* ========================================================================
+ TRS ÏûÏ¢ºÅ¶¨ÒåΪGCF ²âÊÔ¶øÌí¼Ó2010/3/8 SHIFANGMING
+======================================================================== */
+
+#define LTE_GCF_STARTCHECK_REQ_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 0)
+#define LTE_GCF_CHECKPASS_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 1)
+#define LTE_GCF_CHECKFAIL_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 2)
+
+#define LTE_GCF_CHECK_TIMER_EV (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ ENRLC - TRS ÏûÏ¢ºÅ¶¨Òå2010/3/1 LIUHUAN
+======================================================================== */
+#define TRS_ENRLC_UMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 0)
+#define TRS_ENRLC_AMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 1)
+#define TRS_ENRLC_SDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 2)
+#define TRS_ENRLC_AUTOACK_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ PDI - TRS ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SIMULATI_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 0)
+#define SIMULATI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 1)
+#define SIMULATI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 2)
+#define SIMULATI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 3)
+#define SIMULATI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 4)
+#define SIMULATI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 5)
+#define SIMULATI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 6)
+#define SIMULATI_DATA_IND_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 7)
+#define SIMULPSI_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 8)
+#define SIMULATI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 9)
+#define SIMULATI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define SIMULATI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 11)
+#define SIMULATI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 12)
+#define SIMULATI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 13)
+
+#define SIMULENPDI_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 0)
+#define SIMULENPDI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 1)
+#define SIMULENPDI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 2)
+#define SIMULENPDI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 3)
+#define SIMULENPDI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 4)
+#define SIMULENPDI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 5)
+#define SIMULENPDI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 6)
+#define SIMULENPDI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 7)
+#define SIMULENPDI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 8)
+#define SIMULENPDI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 9)
+#define SIMULENPDI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define SIMULENPDI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 11)
+/* ========================================================================
+ ENRRCÓëENRLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRRC_ENRLC_CONFIG_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 0)
+#define ENRRC_ENRLC_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 1)
+#define ENRRC_ENRLC_RELEASE_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 2)
+
+#define ENRLC_ENRRC_CONFIG_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 0)
+#define ENRLC_ENRRC_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 1)
+#define ENRLC_ENRRC_RETX_FAIL_IND_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 2)
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define ENRLC_ENPDCP_UMDATA_CNF_EV (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 0)
+
+
+/* ========================================================================
+ ENRLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRLC_REORDERING_TIMER_EV (DWORD)(ENRLC_TIMER_EVENT_BASE + 0)
+/*EPHY--->ENMAC*/
+#define EPHY_ENMAC_DATA_IND_EV (DWORD)(ENMAC_EPHY_RSP_EVENT + 0) /*EUMAC·¢Ë͵ÄÊý¾Ýµ½´ï*/
+
+/***************************************************** ¶ÔÓ¦UE²àRRC Ïà¹ØÏûÏ¢ *********** Êý¾ÝÃæÕâÀïÓ¦¸Ã²»ÐèÒªÕâЩÏûÏ¢ ÕâÀïµÄ¶¨ÒåÊÇÒÔ·ÀÍòÒ» ******************************************************/
+#define ENMAC_CCCH_DATA_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 0) /*RRC²àÇëÇóCCCHÊý¾Ý*/
+#define ENMAC_COMM_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 1) /*RRC²à·¢ËÍͨÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_DEDI_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 2) /*RRC²à·¢ËÍרÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_REL_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 3) /*RRC²àÇëÇóMACÊÍ·Å×ÊÔ´¡¢Í˳öÁ¬½Ó̬*/
+#define ENMAC_RESET_MAC_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 4) /*RRC²àÇëÇóMAC RESET*/
+#define ENMAC_RESUME_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5) /*RRC²àÇëÇó»Ö¸´RB*/
+#define ENMAC_SUSPEND_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6) /*RRC²àÇëÇóÔÝÍ£RB*/
+#define ENMAC_ACTIVE_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 7)
+
+
+
+#define ENMAC_CCCH_DATA_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 0) /*MAC¸æÖªRRC CCCH Êý¾Ýµ½´ï*/
+#define ENMAC_RA_PROBLEM_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 1) /*MAC¸æÖªRRC RA ÖØ´«´ÎÊý¹ý¶à*/
+#define ENMAC_RA_SUCCESS_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 2) /*MAC¸æÖªRRC RA ³É¹¦*/
+
+/*TRS--->EPHY*/
+#define EPHY_TIMER_INTERUPT_EV (DWORD)(TRS_EPHY_EVENT_BASE + 1) /* ×ÓÖ¡Öжϴ¥·¢ÏûÏ¢ */
+#define TRS_EPHY_DUPLICATE_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 2) /*TRSÏòEPHY·¢ËÍÖظ´·¢ËÍÊý¾ÝµÄÅäÖÃÏûÏ¢*/
+#define EPHY_DL_RARESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 3) /*TRSÏòEPHY·¢ËÍ RA³É¹¦Óë·ñµÄÅäÖà */
+#define EPHY_DL_CRRESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 4) /*TRSÏòEPHY·¢ËÍ CR³É¹¦Óë·ñµÄÅäÖà */
+#define TRS_EPHY_DISCARD_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 5) /*TRSÏòEPHY·¢ËÍ ¶ª°üµÄÅäÖà */
+#define TRS_EPHY_GRANT_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 6) /*TRSÏòEPHY·¢ËÍ ÊÚȨµÄÅäÖòÎÊý */
+#define TRS_EPHY_DISORDER_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 7) /*TRSÏòEPHY·¢ËÍÂÒÐò·¢Ë͵ÄÅäÖÃÏûÏ¢*/
+
+#define EPHY_ULGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 8) /*¼¤·¢ÉÏÐÐ×éÖ¡*/
+#define EPHY_DLGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 9) /*¼¤·¢ÏÂÐÐ×éÖ¡*/
+#define EPHY_GRANTARRAYCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 10) /*ÅäÖÃÉÏÏÂÐÐÊÜȨÊý×é*/
+#define EPHY_IDLE_PERIOD_REP_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 11) /*ÅäÖÿÕÏÐʱ¼ä*/
+#define EPHY_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 12) /*¹¤¾ß¶ÔEPHYµÄÅäÖÃ*/
+/* C# adaptor·¢Ë͵½ephyµÄÏûÏ¢£¬ÁÙʱ´æ·ÅÔÚÕâÀï*/
+#define TRS_FREQ_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 13)
+#define TRS_CELL_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 14)
+#define TRS_CELL_DEL_IND (DWORD)(TRS_EPHY_EVENT_BASE + 15)
+#define TRS_CELL_MOD_IND (DWORD)(TRS_EPHY_EVENT_BASE + 16)
+#define TRS_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 17) // ÉèÖÃC#ģʽ£¬0 - auto £¬ 1- manual
+#define TRS_MSG_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 18) // ÉèÖÃij¸öÏûÏ¢µÄģʽ£¬×Ô¶¯»òÊÖ¶¯
+#define EPHY_CELLINFOCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+#define EPHY_EXTGRANTCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 20)
+/*TRS--->ENMAC*/
+#define TRS_ENMAC_TA_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 1) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà TAÃüÁîÏûÏ¢ Я´øWORDÊý¾Ý£¬Îª0ʱ²»×éTA£¬·Ç0ʱ£¬Ê¹ÓøÃÖµ×éTA*/
+#define TRS_ENMAC_DRX_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 2) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà DRXÃüÁî ÏûÏ¢*/
+#define TRS_ENMAC_CCCH_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 3) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡CCCCHÊý¾Ý*/
+#define TRS_ENMAC_CRID_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 4) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡¾ºÕù½â¾öÉí·ÝÊý¾Ý£¬BIT0Ϊ1£¬
+ BIT1Ϊ0ʱ×éÖ¡·ÇÆ¥ÅäÊý¾Ý£¬ BIT0Ϊ1£¬BIT1Ϊ1ʱ£¬×éÖ¡ÕýÈ·Éí·ÝÊý¾Ý*/
+#define TRS_ENMAC_BACKOFF_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 5) /*Я´øBYTEÊý¾Ý Ôݶ¨*/
+
+#define ENMAC_MCCH_DATA_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 0 )
+#define ENRRC_ENMEL2_REL_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 1)
+#define TRS_ENMEL2_RLC_SDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 2)
+#define TRS_ENMEL2_RLC_PDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 3)
+#define TRS_ENMEL2_MSI_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 4)
+#define EUDBG_EMM_PLAIN_DL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 4)
+#define EUDBG_SEND_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 5)
+#define EUDBG_RECV_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 6)
+#define EUDBG_AM_SEND_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 7)
+#define EUDBG_AM_RECV_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 8)
+#define LTE_P_DLSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 9)
+#define LTE_P_ULSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 10)
+#define LTE_P_MAC_SR_REQ_EV (DWORD)(EUDBG_EVENT_BASE + 11)
+#define LTE_EL2_THROUGHPUT_IND_EV (DWORD)(EUDBG_EVENT_BASE + 12)
+#define LTE_EL2_STATE_IND_EV (DWORD)(EUDBG_EVENT_BASE + 13)
+#define EUDBG_EMM_PLAIN_UL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 14)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå END
+======================================================================== */
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ BEGIN
+======================================================================== */
+
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ END
+======================================================================== */
+/* ========================================================================
+ WÏà¹ØʼþºÅ START
+======================================================================== */
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRC£SCIÏûÏ¢ºÅ¶¨Òå W ÓëTD¹²ÓÃ
+======================================================================== */
+
+/* ========================================================================
+ WRRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_READ_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 0)
+#define WRRC_READ_SYSINFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 1)
+#define WRRC_READ_SYSINFO_REJ_EV (DWORD)(WRRC_EVENT_BASE + 2)
+#define WRRC_STOP_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 3)
+#define WRRC_READ_DYN_SIB_REQ_EV (DWORD)(WRRC_EVENT_BASE + 4)
+#define WRRC_READ_DYN_SIB_CNF_EV (DWORD)(WRRC_EVENT_BASE + 5)
+#define WRRC_SIB_MODIFIED_IND_EV (DWORD)(WRRC_EVENT_BASE + 6)
+#define WRRC_CELLUPDATE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 7)
+#define WRRC_CELL_RESEL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 8)
+#define WRRC_CELL_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 9)
+#define WRRC_REL_CONN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 10)
+#define WRRC_RESUME_CELL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 11)
+#define WRRC_RPLMN_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 12)
+#define WRRC_RESOURE_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 13)
+#define WRRC_RESOURCE_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 14)
+#define WRRC_UPDATE_EPLMN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 15)
+#define WRRC_HIGH_MOBILITY_IND (DWORD)(WRRC_EVENT_BASE + 16)
+#define WRRC_HO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 17)
+#define WRRC_HO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 18)
+#define WRRC_HO_TO_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 19)
+#define WRRC_HO_TO_UTRAN_CNF_EV (DWORD)(WRRC_EVENT_BASE + 20)
+#define WRRC_HO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 21)
+#define WRRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 22)
+#define WRRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 23)
+#define WRRC_CCO_TO_UTRAN_IND_EV (DWORD)(WRRC_EVENT_BASE + 24)
+#define WRRC_CCO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 25)
+#define WRRC_RADIO_LINK_FAIL_IND_EV (DWORD)(WRRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define WRRC_NEIBCELL_CHG_IND_EV (DWORD)(WRRC_EVENT_BASE + 27)
+#define WRRC_FACH_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 28)
+#define WRRC_FACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 29)
+#define WRRC_DRX_CHANGE_IND_EV (DWORD)(WRRC_EVENT_BASE + 30)
+#define WRRC_SEND_BUF_EST_REQ_EV (DWORD)(WRRC_EVENT_BASE + 31)
+#define WRRC_ABORT_RATCHG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 32)
+#define WRRC_CHG_CAMPON_TYPE_EV (DWORD)(WRRC_EVENT_BASE + 33)
+#define WRRC_GET_RF_REQ_EV (DWORD)(WRRC_EVENT_BASE + 34) /*WSIR->WCSR*/
+#define WRRC_GET_RF_CNF_EV (DWORD)(WRRC_EVENT_BASE + 35) /*WCSR->WSIR*/
+#define WRRC_SYSINFO_CONTAINER_IND_EV (DWORD)(WRRC_EVENT_BASE + 36) /*WCSR->WSIR*/
+#define WRRC_ETWS_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 37)
+#define WRRC_ETWS_CFG_END_EV (DWORD)(WRRC_EVENT_BASE + 38)
+#define WRRC_ETWS_CONTINUE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 39)
+#define WRRC_EFACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 40) /*WCMR->WRBC*/
+#define WRRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(WRRC_EVENT_BASE + 41)
+#define WRRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(WRRC_EVENT_BASE + 42)
+/* ========================================================================
+ WRLC - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWRLC_CONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 0)
+#define CWRLC_RELEASE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 1)
+#define CWRLC_SUSPEND_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 2)
+#define CWRLC_RESUME_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 3)
+#define CWRLC_CONTINUE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 4)
+#define UWRLC_DATA_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 5)
+#define CWRLC_CBS_RBCONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 6)
+#define CWRLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 7)
+
+#define CWRLC_SUSPEND_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 0)
+#define UWRLC_DATA_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 1)
+#define CWRLC_STATUS_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 2)
+#define UWRLC_DATA_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 3)
+#define CWRLC_CONFIG_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 4)
+#define CWRLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ WMAC - WRRC/WMAC - WMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWMAC_ASC_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 0)
+#define CWMAC_RACH_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 1)
+#define CWMAC_TFC_CTRL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 2)
+#define CWMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 3)
+#define CWMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 4)
+#define CWMAC_CONTINUE_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 5)
+#define CWMAC_DEL_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 6)
+#define CWMAC_RNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 7)
+#define CWMAC_ERNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 8)
+#define CWMAC_HS_RESET_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 9)
+#define CWMAC_SRB_DELAY_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 10)
+#define CWMAC_TV_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 11)
+#define CWMAC_Q_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 12)
+#define CWMAC_UE_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 13)
+#define CWMAC_TV_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 14)
+#define CWMAC_Q_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 15)
+#define CWMAC_UE_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 16)
+#define CWMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 17)
+#define CWMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 18)
+#define CWMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 19)
+#define CWMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 20)
+#define CWMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 21)
+#define CWMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 22)
+#define CWMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 23)
+#define CWMAC_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 24)
+#define CWMAC_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 25)
+
+#define CWMAC_CONFIG_CHG_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 0)
+#define CWMAC_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 1)
+#define CWMAC_EFACH_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 2)
+#define UWMAC_PCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 3)
+#define UWMAC_BCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 4)
+#define CWMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 5)
+#define CWMAC_TV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 6)
+#define CWMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 7)
+#define CWMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 8)
+#define CWMAC_Q_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 9)
+#define CWMAC_UE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 10)
+#define CWMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 11)
+/* ========================================================================
+ WMAC - UL/DL - WMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+
+/* ========================================================================
+ L1W - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1W_GSM_MEAS_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 0)
+#define L1W_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 1)
+#define L1W_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 2)
+#define L1W_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 3)
+#define L1W_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 4)
+#define L1W_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 5)
+#define L1W_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 6)
+#define L1W_GET_RF_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 7)
+#define L1W_PLMN_END_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 8)
+#define L1W_IRAT_RSRC_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 9)
+#define L1W_CM_CONFIG_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 10)
+#define L1W_CM_FALLBACK_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 11)
+#define L1W_WRRC_LEAVE3G_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 12)
+
+#define L1W_GSM_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 0)
+#define L1W_GET_RF_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 1)
+#define L1W_IRAT_RSRC_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 2)
+#define L1W_LTE_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 3)
+#define L1W_CM_FALLBACK_IND (DWORD)(L1W_WRRC_RSP_EVENT + 4)
+#define L1W_CM_OVERLAP_IND (DWORD)(L1W_WRRC_RSP_EVENT + 5)
+#define L1W_CM_INFO_IND (DWORD)(L1W_WRRC_RSP_EVENT + 6)
+/* ========================================================================
+ PDCP - WRRC ÏûÏ¢ºÅ¶¨Òå(PDCPʼþºÅ¹²ÓÃ)
+======================================================================== */
+
+/* ========================================================================
+ WRLC -WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ L1W - WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WISR_FRAME_IND_EV (DWORD)(WMAC_L1W_EVENT_BASE + 0)
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define UWRLC_PDCP_DATA_IND_EV (DWORD)(PDCP_WRLC_EVENT_BASE + 0)
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_BCH_READ_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 0)
+#define W_P_BCH_OPEN_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 1)
+#define W_P_BCH_RELEASE_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 2)
+
+#define W_P_BCH_IND_EV (DWORD)(WSIR_WPHY_RSP_EVENT + 0)
+/* ========================================================================
+ WCSR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_FREQUENCY_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 0)
+#define W_P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 1)
+#define W_P_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 2)
+#define W_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 3)
+#define W_P_CAMPON_A_CELL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 4)
+#define W_P_REL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 5)
+#define W_P_RESET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 6)
+#define W_P_SET_IRAT_MODE_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 7)
+#define W_P_RPI_SET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 8)
+#define W_P_RPI_CFG_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 9)
+
+
+#define W_P_FREQUENCY_SCAN_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 0)
+#define W_P_CELL_SEARCH_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 1)
+#define W_P_RESET_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 2)
+#define W_P_REL_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ WMCR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 0)
+#define W_P_INTER_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 1)
+#define W_P_FMO_INFO_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 2)
+#define W_P_MEAS_REL_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 3)
+
+#define W_P_INTRA_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 1)
+#define W_P_INTER_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 2)
+#define W_P_SERVCELL_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 3)
+
+
+/* ========================================================================
+ WRBC - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 0)
+#define W_P_DL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 1)
+#define W_P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 2)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 3)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_ABORT_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 4)
+#define W_P_UL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 5)
+#define W_P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 6)
+#define W_P_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 7)
+#define W_P_STOP_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 8)
+#define W_P_ADD_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 9)
+#define W_P_REL_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 10)
+#define W_P_REL_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 11)
+#define W_P_ADD_MODIFY_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 12)
+#define W_P_STOP_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 13)
+#define W_P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 14)
+#define W_P_ADD_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 15)
+#define W_P_REL_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 16)
+#define W_P_HSPA_PLUS_FACH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 17)
+#define W_P_HSPA_PLUS_PCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 18)
+#define W_P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 19)
+#define W_P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 20)
+#define W_P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 21)
+#define W_P_ADD_PRACH_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 22)
+#define W_P_DL_FDPCH_SETUP_MODIFY_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 23)
+
+
+#define W_P_IN_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 0)
+#define W_P_OUT_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 1)
+#define W_P_DPCH_SETUP_MODIFY_CNF (DWORD)(WRBC_WPHY_RSP_EVENT + 2)
+#define W_P_HSSCCH_ORDER_IND (DWORD)(WRBC_WPHY_RSP_EVENT + 3)
+
+
+
+/* ========================================================================
+ WMAC_UL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_RACH_PROCEDURE_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 0)
+#define W_P_RACH_PROCEDURE_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 1)
+#define W_P_EFACH_NO_DATA_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 2)
+#define W_P_ETFC_PARAM_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 3)
+#define W_P_POST_VERFY_FAIL_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 4)
+#define W_P_MAC_DTX_CYCLE_INFO_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 5)
+#define W_P_TFCI_CM_INFO_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 6)
+/* ========================================================================
+ WMAC_DL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 0)
+#define W_P_UE_INTERNAL_MEAS_IND_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 1)
+
+/* ========================================================================
+ L1W - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define W_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G L1W_GSM_INACT_TIME_IND_EV*/
+#define W_P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G L1W_ABORT_GSM_GAP_REQ_EV*/
+#define W_P_COMPRESS_MODE_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 3)
+#define W_P_CARD2_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 4) /*T_zW_P_card2_gap_req*/
+#define W_P_CARD2_GAP_REL_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 5) /*T_zW_P_card2_gap_rel_req*/
+#define W_P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 6) /*T_zW_P_card2_stop_gap_req*/
+#define W_P_CARD1_SUSPEND_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 7) /*T_zW_P_card1_suspend_req*/
+#define W_P_CARD1_RESUME_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 8) /*T_zW_P_card1_resume_req*/
+#define W_P_ZWPCG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 9)
+
+#define W_P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 0)
+#define W_P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 1)
+#define W_P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 2)
+#define W_P_BCH_RELEASE_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 3)
+#define W_P_CAMPON_A_CELL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 4)
+#define W_P_DPCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 5)
+#define W_P_REL_SCCPCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 6)
+#define W_P_STOP_PAGING_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 7)
+#define W_P_STOP_CBS_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 8)
+#define W_P_REL_HSDPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 9)
+#define W_P_REL_HSUPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 10)
+#define W_P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 11)
+#define W_P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 12)
+#define W_P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 13)
+#define W_P_CARD2_GAP_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 14) /*T_zW_P_card2_gap_ind*/
+#define W_P_CARD2_GAP_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 15) /*T_zW_P_card2_gap_rel_cnf*/
+#define W_P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 16) /*T_zW_P_card2_stop_gap_cnf*/
+#define W_P_CARD1_SUSPEND_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 17) /*T_zW_P_card1_suspend_cnf*/
+#define W_P_ZWPCG_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 18)
+
+
+/* ========================================================================
+ L1W ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_CHECK_RF_IND_EV (DWORD)(L1W_EVENT_BASE + 0)
+#define W_P_ACTIVE_IND_EV (DWORD)(L1W_EVENT_BASE + 1)
+#define L1W_MEAS_TIMESTAMP_IND_EV (DWORD)(L1W_EVENT_BASE + 2)
+#define L1W_MEAS_TICKTRACE_IND_EV (DWORD)(L1W_EVENT_BASE + 3)
+
+/* ========================================================================
+ WRRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WSIR_T_BCH_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 0)
+#define WSIR_T_SIB7_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 1)
+#define WSIR_T_VTSIB_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 2)
+#define WSIR_T_R_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 3)
+#define WSIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 4)
+#define WCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 5)
+#define WCSR_T_HYSTX_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 6)
+#define WCSR_T_PROTECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 7)
+#define WCSR_T_NCELL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 8)
+#define WCSR_T_OOS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 9)
+#define WCSR_T_CAMP1S_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define WCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 11)
+#define WCSR_T_REDIRECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 12)
+#define WMCR_T_RESELECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 13)
+#define WMCR_T_PERIOD_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 14)
+#define WMCR_T_TRIGGER_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 15)
+#define WMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 16)
+#define WCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 17)
+#define WCER_T_ETWS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 18)
+#define WCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 19)
+#define WRRC_T300_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 20)
+#define WRRC_T302_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 21)
+#define WRRC_T304_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 22)
+#define WRRC_T305_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 23)
+#define WRRC_T307_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 24)
+#define WRRC_T308_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 25)
+#define WRRC_T309_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 26)
+#define WRRC_T312_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 27)
+#define WRRC_T313_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 28)
+#define WRRC_T314_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 29)
+#define WRRC_T315_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 30)
+#define WRRC_T316_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 31)
+#define WRRC_T319_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 32)
+#define WRRC_T320_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 33)
+#define WMCR_T322_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 34)
+#define WRRC_T323_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 35)
+#define WRRC_T325_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 36)
+#define WRRC_T_WAIT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 37)
+
+/* ========================================================================
+ WPDCP¶¨Ê±Æ÷¶¨Òå(wÎÞÐÂÔö£¬Í¬TD)
+======================================================================== */
+
+
+/* ========================================================================
+ WRLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WRLC_T_DISCARD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 0)
+#define WRLC_T_POLL_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 1)
+#define WRLC_T_POLLPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 2)
+#define WRLC_T_POLLPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 3)
+#define WRLC_T_STATUSPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 4)
+#define WRLC_T_STATUSPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 5)
+#define WRLC_T_RESET_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 6)
+#define WRLC_T_MRW_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ WMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 0)
+#define WMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 1)
+#define WMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 2)
+#define WMAC_T_HSTIMER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 3)
+#define WMAC_T_RESET_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 4)
+#define WMAC_T_BO1_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 5)
+#define WMAC_T_TB_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 6)
+#define WMAC_T_AG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 7)
+#define WMAC_T_RG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 8)
+#define WMAC_T_SING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 9)
+#define WMAC_T_SIG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ L1W¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+/* ========================================================================
+ WSIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_WSIR_DECSIB_EV (DWORD)(WSIR_TEST_EVENT_BASE + 0)
+/* ========================================================================
+ NWRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UWRLC_DATA_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 0)
+#define TEST_UWRLC_DATA_IND_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 1)
+#define TEST_CWRLC_CONFIG_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 2)
+#define TEST_WRLC_ACK_CTRL_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NWMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_WMAC_ACK_CTRL_UTRAN_EV (DWORD)(NWMAC_EVENT_BASE + 0)
+#define TEST_WMAC_HSUPA_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 1)
+#define TEST_WMAC_HSUPA_CFG_EV (DWORD)(NWMAC_EVENT_BASE + 2)
+#define TEST_WMAC_HSUPA_SIINFO_EV (DWORD)(NWMAC_EVENT_BASE + 3)
+#define TEST_WMAC_HSUPA_HEADER_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 4)
+#define TEST_WMAC_NOTIFY_DATA_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 5)
+#define TEST_WMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 6)
+#define TEST_WMAC_CRC_RESULT_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 7)
+#define TEST_UWMAC_DATA_IND_EV (DWORD)(NWMAC_EVENT_BASE + 8)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 0)
+#define WRRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 1)
+#define WRRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 2)
+#define WRRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 3)
+#define WRRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 4)
+#define WRRC_FUNC_READ_SIB_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 5)
+#define WRRC_FUNC_READ_SIB_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 6)
+#define WRRC_FUNC_SER_CELL_IND_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 7)
+#define WRRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 8)
+#define WRRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 9)
+#define WRRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 10)
+#define WRRC_FUNC_START_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 11)
+#define WRRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 12)
+#define WRRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 13)
+#define WRRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 14)
+#define WRRC_FUNC_STOP_SYSINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 15)
+#define WRRC_FUNC_CFG_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 16)
+#define WRRC_FUNC_CFG_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 17)
+#define WRRC_FUNC_REL_FACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 18)
+#define WRRC_FUNC_REL_FACH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 19)
+#define WRRC_FUNC_REL_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 20)
+#define WRRC_FUNC_REL_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 21)
+#define WRRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 22)
+#define WRRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 23)
+#define WRRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 24)
+#define WRRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 25)
+#define WRRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 26)
+#define WRRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 27)
+#define WRRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 28)
+#define WRRC_FUNC_READ_CGIINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 29)
+/* ========================================================================
+ RRCº¯ÊýÖµ¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define RRC_FUNC_GET_TICK_COUNT_EV (DWORD)(RRC_FUNC_TRACE_BASE + 0)
+#define RRC_FUNC_GET_NV_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 1)
+#define RRC_FUNC_GET_UICC_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 2)
+#define RRC_FUNC_GET_PLMN_TYPE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 3)
+#define RRC_FUNC_GET_3A_THREOLD_EV (DWORD)(RRC_FUNC_TRACE_BASE + 4)
+#define RRC_FUNC_GET_PSLOCI_INFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 5)
+#define RRC_FUNC_GET_COUNTC_EV (DWORD)(RRC_FUNC_TRACE_BASE + 6)
+#define RRC_FUNC_GET_MASTER_MODE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 7)
+#define RRC_FUNC_GET_SFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 8)
+#define RRC_FUNC_GET_CFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 9)
+#define RRC_FUNC_GET_AMDLPDU_SIZE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 10)
+#define RRC_FUNC_GET_SIB7_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 11)
+#define RRC_FUNC_GET_VTSIB_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 12)
+/*´òÓ¡µ±Ç°ÊÇ·ñÓÐNASÐÅÁîÕýÔÚ½øÐÐ*/
+#define RRC_FUNC_NAS_SIGNAL_PROC_EXIST_EV (DWORD)(RRC_FUNC_TRACE_BASE + 13)
+#define RRC_FUNC_GET_SRB2_UL_ACT_TIME_EV (DWORD)(RRC_FUNC_TRACE_BASE + 14)
+#define RRC_FUNC_GET_SRB2_MAX_HFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 15)
+//as comÖеÄbarÐÅÏ¢ÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define AS_FUNC_CLEARBARFREQINFO (DWORD)(RRC_FUNC_TRACE_BASE + 50)
+#define AS_FUNC_ADDTDFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 51)
+#define AS_FUNC_DELTDFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 52)
+#define AS_FUNC_CLEARBARCELLINFO (DWORD)(RRC_FUNC_TRACE_BASE + 53)
+#define AS_FUNC_ADDTDCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 54)
+#define AS_FUNC_ADDGSMCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 55)
+#define AS_FUNC_ADDWFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 56)
+#define AS_FUNC_DELWFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 57)
+#define AS_FUNC_ADDWCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 58)
+#define AS_FUNC_GETDEDIPRIOINFO (DWORD)(RRC_FUNC_TRACE_BASE + 59)
+#define AS_FUNC_GETBARINFO (DWORD)(RRC_FUNC_TRACE_BASE + 60)
+#define AS_FUNC_SETFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 61)
+#define AS_FUNC_CLEARFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 62)
+//EUSIRÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define EURRC_EUSIR_SIB1_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 63)
+#define EURRC_EUSIR_SIB2_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 64)
+#define EURRC_EUSIR_SIB5_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 65)
+/* ========================================================================
+WÏà¹ØʼþºÅ END
+======================================================================== */
+#ifdef BTRUNK_SUPPORT
+/* ESM --> TSM */
+#define TSM_ESM_DIALED_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 60)
+#define TSM_ESM_BEARER_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 61)
+
+/* TSM --> ESM */
+#define TSM_ESM_SYN_BEARSTATE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 62)
+
+
+/* TSM --> EMM */
+#define TSM_EST_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 70)
+#define TSM_EMM_DATA_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 71)
+#define TSM_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 72)
+#define TSM_LOCATIONINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 73)
+#define TSM_UMM_DETACHLTE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 74)
+
+
+/* EMM/UMM --> TSM */
+#define TSM_EST_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 80)
+#define TSM_REL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 81)
+#define TSM_EMM_ATTACHSTATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 82)
+#define TSM_EMM_DATA_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 83)
+#define TSM_UMM_PTTINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 84)
+#define TSM_EMM_LOCATIONINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 85)
+
+/*TSM->ASC*/
+#define TSM_ASC_GROUP_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 90)
+#define TSM_ASC_SCANSWITCH_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 91)
+
+/*ASC->TSM*/
+#define TSM_ASC_TGCCH_MSG_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 100)
+#define TSM_ASC_SCANGROUPINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 101)
+#define TSM_ASC_SET_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 102)
+#define TSM_ASC_REL_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 103)
+#define TSM_ASC_REL_GROUP_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 104)
+
+
+/* ========================================================================
+ TSM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TSM_TIMER_BASE (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 300)
+#define TSM_TCMEST_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 1)
+#define TSM_T8001_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 2)
+#define TSM_T8003_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 3)
+#define TSM_T8005_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 4)
+#define TSM_T8006_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 5)
+#define TSM_T8011_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 6)
+#define TSM_T8012_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 7)
+#define TSM_T8014_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 8)
+#define TSM_T8016_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 9)
+#define TSM_T8018_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 10)
+#define TSM_T8020_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 11)
+#define TSM_TPERIOD_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 12)
+#define TSM_TGPS_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 13)
+#define TSM_T8123_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 14)
+#define TSM_TREGRETRY_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 15)
+#define TSM_TCONFIRM_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 16)
+#define TSM_T8125_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 17)
+#define TSM_T8026_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 18)
+/**************************************************PS LTE BTRUNK msg range end********************************************************/
+#endif
+
+/* LPP-ECIDʼþºÅ¶¨Ò壬¹²¼Æ50¸ö */
+
+/* LPP --> ASC */
+#define LPP_ASC_ECID_MEAS_START_EV (DWORD)(LPP_ECID_EVENT_BASE + 0)
+#define LPP_ASC_ECID_MEAS_ABORT_EV (DWORD)(LPP_ASC_ECID_MEAS_START_EV + 1)
+/* LPP --> EURRC */
+#define ASC_EUCSR_ECID_MEAS_START_EV (DWORD)(LPP_ASC_ECID_MEAS_ABORT_EV + 1)
+#define ASC_EUCSR_ECID_MEAS_ABORT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_START_EV + 1)
+/* EURRC --> ASC */
+#define EURRC_ASC_ECID_MEAS_RESULT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_ABORT_EV + 1)
+/* ASC --> LPP */
+#define ASC_LPP_ECID_MEAS_RESULT_EV (DWORD)(EURRC_ASC_ECID_MEAS_RESULT_EV + 1)
+/* SS --> LPP */
+#define SS_LPP_MOLR_START_IND_EV (DWORD)(ASC_LPP_ECID_MEAS_RESULT_EV + 1)
+#define SS_LPP_MOLR_END_IND_EV (DWORD)(SS_LPP_MOLR_START_IND_EV + 1)
+#define SS_LPP_MTLR_START_IND_EV (DWORD)(SS_LPP_MOLR_END_IND_EV + 1)
+#define SS_LPP_MTLR_END_IND_EV (DWORD)(SS_LPP_MTLR_START_IND_EV + 1)
+/* UMM -->LPP */
+#define UMM_LPP_CELLCHG_IND_EV (DWORD)(SS_LPP_MTLR_END_IND_EV + 1)
+/* LPP TIMER EXPIRY EVENT */
+#define LPP_TRIRPT_TIMER_EXP_EV (DWORD)(UMM_LPP_CELLCHG_IND_EV + 1)
+#define LPP_RETRANS_TIMER_EXP_EV (DWORD)(LPP_TRIRPT_TIMER_EXP_EV + 1)
+#define LPP_MSG_TRACE_LOG_EV (DWORD)(LPP_RETRANS_TIMER_EXP_EV + 1)
+
+#endif /* PS_EVENTDEF_H */
+