[Feature][T106_eSDK]T106-V2.01.01.02P56U06.AP.15.11_CAP.15.11(SDK4.6)diff_17.02(SDK4.7)
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I9dc02273b59a074828ab3eeaa84306415b153138
diff --git a/upstream/linux-5.10/include/linux/soc/sc/spinlock.h b/upstream/linux-5.10/include/linux/soc/sc/spinlock.h
new file mode 100755
index 0000000..eb5e7b7
--- /dev/null
+++ b/upstream/linux-5.10/include/linux/soc/sc/spinlock.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2015 ZTE-TSP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SPINLOCK_H
+#define _SPINLOCK_H
+
+
+/****************************************************************************
+* Include files
+****************************************************************************/
+//#include <spinlock_com.h>
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+/****************************************************************************
+* Types
+****************************************************************************/
+
+
+#define SPINLOCK_IOC_MAGIC 'S'
+
+/*ioctl cmd usd by device*/
+#define SPINLOCK_GET_STATUS _IOWR(SPINLOCK_IOC_MAGIC, 1, char *)
+
+
+
+typedef enum
+{
+ CORE_ID_PS=210,
+ CORE_ID_PHY=211,
+ CORE_ID_ZSP=212,
+ CORE_ID_M0=213,
+ CORE_ID_AP=214,
+ CORE_ID_NUM = 215
+} zte_coreid;
+/* ±êʶӲ¼þËø*/
+typedef enum
+{
+ PCU_HWLOCK = 0,/*PCU*/
+ CLK_HWLOCK = 1,/*Clock*/
+ REGLOCK_HWLOCK,
+ SOFTLOCK_HWLOCK,
+ HWLOCK_NUM
+} emhw_lock_id;
+
+/* ±êʶÈí¼þËø*/
+typedef enum
+{
+ I2C0_SFLOCK = 0,/*i2c0*/
+ I2C1_SFLOCK = 1,/*i2c1*/
+ I2C2_SFLOCK = 2,/*pmic-i2c*/
+ NAND_SFLOCK = 3,/*NAND*/
+ SD0_SFLOCK, /*for sd0*/
+ SD1_SFLOCK, /*for sd1*/
+ ADC_SFLOCK, /*for adc*/
+ UART_SFLOCK,
+ PMIC_SFLOCK,
+ SFLOCK_ID9,
+ SFLOCK_ID10,
+ SFLOCK_ID11,
+ SFLOCK_ID12,
+ SFLOCK_ID13,
+ SFLOCK_ID14,
+ SFLOCK_ID15,
+ SFLOCK_ID16,
+ SFLOCK_ID17,
+ SFLOCK_ID18,
+ SFLOCK_ID19,
+ SFLOCK_ID20,
+ SFLOCK_ID21,
+ SFLOCK_ID22,
+ SFLOCK_ID23,
+ SFLOCK_ID24,
+ SFLOCK_ID25,
+ SFLOCK_ID26,
+ SFLOCK_ID27,
+ SFLOCK_ID28,
+ SFLOCK_ID29,
+ SFLOCK_ID30,
+ REG_SFLOCK = 31,/*REG*/
+ SFLOCK_NUM
+} emsf_lock_id;
+
+
+void hw_spin_lock(u32 hwid);
+void hw_spin_unlock(u32 hwid);
+void soft_spin_lock(u32 sfid);
+void soft_spin_unlock(u32 sfid);
+void reg_spin_lock(void);
+void reg_spin_unlock(void);
+void soft_spin_lock_psm(emsf_lock_id sfid);
+void soft_spin_unlock_psm(emsf_lock_id sfid);
+
+void zx_spinlock_init(void __iomem *spinlock_base);
+int soft_spin_lock_printf(emsf_lock_id sfid);
+
+#endif/* _SPINLOCK_H */
+