[Feature][T106_eSDK]17.09(SDK4.8)diff_19.00(SDK5.0)
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I768f6d42285f04acf919b9f8f6cd34af460c3ef4
diff --git a/Uboot/boot/common/src/uboot/arch/arm/lib/bootm.c b/Uboot/boot/common/src/uboot/arch/arm/lib/bootm.c
new file mode 100755
index 0000000..914259d
--- /dev/null
+++ b/Uboot/boot/common/src/uboot/arch/arm/lib/bootm.c
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+#include <fdt.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <bootimg.h>
+#include <load_image.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <asm/arch/efuse.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+static void setup_start_tag (bd_t *bd);
+
+# ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags (bd_t *bd);
+# endif
+static void setup_commandline_tag (bd_t *bd, char *commandline);
+
+# ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag (bd_t *bd, ulong initrd_start,
+ ulong initrd_end);
+# endif
+static void setup_end_tag (bd_t *bd);
+
+static struct tag *params;
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+static ulong get_sp(void);
+#if defined(CONFIG_OF_LIBFDT)
+static int bootm_linux_fdt(int machid, bootm_headers_t *images);
+#endif
+extern int rd_offset ;
+extern int rd_size;
+extern unsigned int g_sys_kernel_sdram_size;
+extern unsigned char g_ddr_size_flag;
+
+#define reg32(addr) (*(volatile unsigned long *)(addr))
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp;
+
+ /*
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
+ */
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+ /* adjust sp by 1K to be safe */
+ sp -= 1024;
+ lmb_reserve(lmb, sp,
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp);
+}
+
+static void announce_and_cleanup(void)
+{
+ printf("\nStarting kernel ...\n");
+
+#ifdef CONFIG_USB_DEVICE
+ {
+ extern void udc_disconnect(void);
+ udc_disconnect();
+ }
+#endif
+ cleanup_before_linux();
+}
+
+//#ifdef CONFIG_ZX297520V3E_WATCH_CAP
+#if defined(CONFIG_ZX297520V3E_WATCH_CAP) || defined (CONFIG_ZX297520V3E_VEHICLE_DC) || defined (CONFIG_ZX297520V3E_VEHICLE_DC_REF)
+#define SYS_CPUCAP_PARAM_ADDR 0x10200C
+extern uint32_t arm_cpucap_ep;
+void set_cpucap_tag(int arch, uint parameter)
+{
+ uint32_t cap_tag_addr = 0;
+
+ cap_tag_addr = arm_cpucap_ep - 0x8000 + 0x100;
+
+ writel(0x0, SYS_CPUCAP_PARAM_ADDR);
+ writel(arch, SYS_CPUCAP_PARAM_ADDR+0x4);
+ writel(cap_tag_addr, SYS_CPUCAP_PARAM_ADDR+0x8);
+
+ memcpy(cap_tag_addr, parameter, 0x800);
+}
+#endif
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv ("bootargs");
+#endif
+
+ if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+ {
+ return 1;
+ }
+
+
+ s = getenv ("machid");
+ if (s)
+ {
+ machid = simple_strtoul (s, NULL, 16);
+ printf ("Using machid 0x%x from environment\n", machid);
+ }
+
+ show_boot_progress (15);
+
+#ifdef CONFIG_OF_LIBFDT
+#if 0
+ if (images->ft_len)
+ {
+ debug("start device tree...\n");
+ //return bootm_linux_fdt(machid, images);
+ bootm_linux_fdt(machid, images);
+ }
+#endif
+#if defined(CONFIG_ZX297520V3E_VEHICLE_DC) || defined(CONFIG_ZX297520V3E_VEHICLE_DC_REF)
+ debug("start device tree...\n");
+ bootm_linux_fdt(machid, images);
+ //fdt_chosen(images->ft_addr, 1);
+#endif
+
+#endif
+
+ kernel_entry = (void (*)(int, int, uint))images->ep;
+
+ debug ("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+ setup_start_tag (bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag (¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag (¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags (bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag (bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (images->rd_start && images->rd_end)
+ setup_initrd_tag (bd, images->rd_start, images->rd_end);
+#endif
+ setup_end_tag(bd);
+#endif
+
+//#ifdef CONFIG_ZX297520V3E_WATCH_CAP
+#if defined(CONFIG_ZX297520V3E_WATCH_CAP) || defined (CONFIG_ZX297520V3E_VEHICLE_DC) || defined (CONFIG_ZX297520V3E_VEHICLE_DC_REF)
+ memset(ICP_CAP_BUF_ADDR, 0, ICP_CAP_BUF_LEN);
+ memset(IRAM_BASE_ADDR_SYS_TRACE, 0, IRAM_BASE_LEN_SYS_TRACE);
+ if(!read_fota_update_flag())
+ {
+ cap_poweron();
+ set_cpucap_tag(machid, bd->bi_boot_params);
+ start_cpucap_cores();
+ }
+#endif
+ printf("===chiid=0x%x,boot_params=0x%x\n", machid, bd->bi_boot_params);
+ announce_and_cleanup();
+ kernel_entry(0, machid, bd->bi_boot_params);
+
+ /* does not return */
+ return 1;
+}
+
+//add by zhouqi
+int do_booti_linux( boot_img_hdr *hdr )
+{
+ bd_t *bd = gd->bd;
+ char *s;
+ int machid = bd->bi_arch_number;
+ void (*kernel_entry)(int zero, int arch, uint params);
+
+#ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv ("bootargs");
+#endif
+
+ s = getenv ("machid");
+ if (s) {
+ machid = simple_strtoul (s, NULL, 16);
+ printf ("Using machid 0x%x from environment\n", machid);
+ }
+
+ show_boot_progress (15);
+
+#ifdef CONFIG_OF_LIBFDT
+ //if (images->ft_len)
+ //return bootm_linux_fdt(machid, images);
+#endif
+
+ kernel_entry = (void (*)(int, int, uint))hdr->kernel_addr;
+
+ debug ("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+ setup_start_tag (bd);
+#ifdef CONFIG_SERIAL_TAG
+ setup_serial_tag (¶ms);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ setup_revision_tag (¶ms);
+#endif
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+ setup_memory_tags (bd);
+#endif
+#ifdef CONFIG_CMDLINE_TAG
+ setup_commandline_tag (bd, commandline);
+#endif
+#ifdef CONFIG_INITRD_TAG
+ if (hdr->ramdisk_size)
+ setup_initrd_tag (bd, hdr->ramdisk_addr, hdr->ramdisk_size + hdr->ramdisk_addr);
+#endif
+ setup_end_tag(bd);
+#endif
+
+ announce_and_cleanup();
+
+ kernel_entry(0, machid, bd->bi_boot_params);
+ /* does not return */
+
+ return 1;
+}
+
+
+#if defined(CONFIG_OF_LIBFDT)
+static int fixup_memory_node(void *blob)
+{
+ bd_t *bd = gd->bd;
+ int bank;
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ //start[bank] = bd->bi_dram[bank].start;
+ //size[bank] = bd->bi_dram[bank].size;
+ start[bank] = DDR_BASE_ADDR_CAP;
+ if(g_ddr_size_flag == CHIP_DDR_IS_128M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = DDR_BASE_LEN_CAP;
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_256M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP + 0x8000000;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = (DDR_BASE_LEN_CAP + 0x8000000);
+ }
+ else if(g_ddr_size_flag == CHIP_DDR_IS_512M)
+ {
+ size[bank] = DDR_BASE_LEN_CAP + 0x18000000;
+ reg32(IRAM_BASE_ADDR_BOOT_DDR) = (DDR_BASE_LEN_CAP + 0x18000000);
+ }
+ else
+ {
+ debug("ddr size is error.\n");
+ return 0;
+ }
+ }
+ debug("size is 0x%llx\n",size[0]);
+ return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+
+static int bootm_linux_fdt(int machid, bootm_headers_t *images)
+{
+ ulong rd_len;
+ void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ ulong *initrd_start = &images->initrd_start;
+ ulong *initrd_end = &images->initrd_end;
+ struct lmb *lmb = &images->lmb;
+ int ret;
+
+ kernel_entry = (void (*)(int, int, void *))images->ep;
+
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ rd_len = images->rd_end - images->rd_start;
+ ret = boot_ramdisk_high(lmb, images->rd_start, rd_len,
+ initrd_start, initrd_end);
+ if (ret)
+ return ret;
+
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return ret;
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) kernel_entry);
+
+ fdt_chosen(*of_flat_tree, 1);
+
+ fixup_memory_node(*of_flat_tree);
+
+#if 0
+ fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
+
+ announce_and_cleanup();
+
+ kernel_entry(0, machid, *of_flat_tree);
+ /* does not return */
+#endif
+ return 1;
+}
+#endif
+
+#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
+ defined (CONFIG_SERIAL_TAG) || \
+ defined (CONFIG_REVISION_TAG)
+static void setup_start_tag (bd_t *bd)
+{
+ params = (struct tag *) bd->bi_boot_params;
+
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size (tag_core);
+
+ params->u.core.flags = 0x1;//0;
+ params->u.core.pagesize =0x1000; //0;
+ params->u.core.rootdev = 0x0;//0;
+
+ params = tag_next (params);
+}
+
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+static void setup_memory_tags (bd_t *bd)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size (tag_mem32);
+
+ /* modify by zhouqi 2013/06/27 */
+ params->u.mem.start = read_sys_ddr_kernel_start();
+ params->u.mem.size = g_sys_kernel_sdram_size; //CONFIG_SYS_SDRAM_A9_SIZE;
+
+ params = tag_next (params);
+ }
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS */
+
+
+static void setup_commandline_tag (bd_t *bd, char *commandline)
+{
+ char *p;
+
+ if (!commandline)
+ return;
+
+ /* eat leading white space */
+ for (p = commandline; *p == ' '; p++);
+
+ /* skip non-existent command lines so the kernel will still
+ * use its default command line.
+ */
+ if (*p == '\0')
+ return;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof (struct tag_header) + strlen (p) + 1 + 4) >> 2;
+
+ strcpy (params->u.cmdline.cmdline, p);
+
+ params = tag_next (params);
+}
+
+
+#ifdef CONFIG_INITRD_TAG
+static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end)
+{
+ /* an ATAG_INITRD node tells the kernel where the compressed
+ * ramdisk can be found. ATAG_RDIMG is a better name, actually.
+ */
+ params->hdr.tag = ATAG_INITRD2;
+ params->hdr.size = tag_size (tag_initrd);
+
+ params->u.initrd.start = rd_offset;//initrd_start;
+ params->u.initrd.size =rd_size;//initrd_end - initrd_start;
+
+
+ params = tag_next (params);
+}
+#endif /* CONFIG_INITRD_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+void setup_serial_tag (struct tag **tmp)
+{
+ struct tag *params = *tmp;
+ struct tag_serialnr serialnr;
+ void get_board_serial(struct tag_serialnr *serialnr);
+
+ get_board_serial(&serialnr);
+ params->hdr.tag = ATAG_SERIAL;
+ params->hdr.size = tag_size (tag_serialnr);
+ params->u.serialnr.low = serialnr.low;
+ params->u.serialnr.high= serialnr.high;
+ params = tag_next (params);
+ *tmp = params;
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+void setup_revision_tag(struct tag **in_params)
+{
+ u32 rev = 0;
+ u32 get_board_rev(void);
+
+ rev = get_board_rev();
+ params->hdr.tag = ATAG_REVISION;
+ params->hdr.size = tag_size (tag_revision);
+ params->u.revision.rev = rev;
+ params = tag_next (params);
+}
+#endif /* CONFIG_REVISION_TAG */
+
+static void setup_end_tag (bd_t *bd)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
diff --git a/Uboot/boot/common/src/uboot/drivers/power/zx234290.c b/Uboot/boot/common/src/uboot/drivers/power/zx234290.c
new file mode 100755
index 0000000..6e82f81
--- /dev/null
+++ b/Uboot/boot/common/src/uboot/drivers/power/zx234290.c
@@ -0,0 +1,938 @@
+/*********************************************************************
+ Copyright 2016 by ZIXC Corporation.
+*
+* FileName:: zx234290.c
+* File Mark:
+* Description:
+* Others:
+* Version:
+* Author:
+* Date:
+
+* History 1:
+* Date:
+* Version:
+* Author:
+* Modification:
+* History 2:
+**********************************************************************/
+
+#include <common.h>
+#include <errno.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <boot_mode.h>
+#include <i2c.h>
+#include <drvs_gpio.h>
+#include <power.h>
+#include <zx234290.h>
+#include <zx234502.h>
+#include <watchdog.h>
+
+int zx234290_write_flag(UINT8 val);
+
+#define PIN_PSHOLD_NUM GPIO24
+#define GPIO_PSHOLD_FUNC_SEL GPIO24_GPIO24
+
+static boot_reason_t s_boot_reason = UNKNOWN_BOOT_REASON;
+unsigned int g_pmu_type = PMU_TYPE_MAX;
+
+/*******************************************************************************
+ * Function: zx234290_i2c_read_reg
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_i2c_read_reg(ushort reg, uchar *val)
+{
+ return i2c_read(0, ZX234290_I2C_SLAVE_ADDR, reg, 8, val, 1);
+}
+
+/*******************************************************************************
+ * Function: zx234290_i2c_write_reg
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_i2c_write_reg(ushort reg, uchar *val)
+{
+ return i2c_write(0, ZX234290_I2C_SLAVE_ADDR, reg, 8, val, 1);
+}
+
+int zx234290_reset_flag(void)
+{
+#if 0
+ int ret = 0;
+ int val = 0;
+
+ /*
+ int val = 0xff;
+ ret = zx234290_i2c_write_reg(0x0f,&val);
+ */
+ ret = zx234290_i2c_read_reg(BUCK_MODE_CONTROL0, &val);
+ val &= (~0x30);
+ ret += zx234290_i2c_write_reg(BUCK_MODE_CONTROL0, &val);
+
+ return ret;
+#else
+ return zx234290_write_flag(ZX234290_USER_RST_UNDEFINE);
+#endif
+}
+
+int zx234290_write_flag(UINT8 val)
+{
+#if 0
+ int ret = 0;
+ int tmp = 0;
+
+ if(val > 3)
+ {
+ return -1;
+ }
+ ret = zx234290_i2c_read_reg(BUCK_MODE_CONTROL0, &tmp);
+ tmp &= (~0x30);
+ tmp |= (val<<4);
+ ret += zx234290_i2c_write_reg(BUCK_MODE_CONTROL0, &tmp);
+
+ return ret;
+#else
+ int ret = 0;
+ uchar tmp = 0;
+
+ /*
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_USER_RESERVED, &tmp);
+ tmp &= ~(0x03<<2);
+ tmp |= (val<<2);
+ */
+ tmp = val;
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_USER, &tmp);
+
+ return ret;
+#endif
+}
+
+
+void zx234290_set_rtc_alarm_off(void)
+{
+ int ret = 0;
+ uchar tmp = 0;
+
+ //set alarm active bit 1 disable
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_MINUTE, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_MINUTE, &tmp);
+
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_HOUR, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_HOUR, &tmp);
+
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_DAY, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_DAY, &tmp);
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_WEEK, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_WEEK, &tmp);
+
+
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_ADDR_ALARM_SECOND, &tmp);
+ tmp |= (1<<ZX234290_RTC_AlARM_ACTIVATED_LSH);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_ADDR_ALARM_SECOND, &tmp);
+
+ /*disable AIE bit && AF*/
+ ret |= zx234290_i2c_read_reg(ZX234290_REG_RTC_CONTROL2, &tmp);
+ tmp &= ~(RTC_CONTROL2_AIE|RTC_CONTROL2_AF);
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_RTC_CONTROL2, &tmp);
+
+ if(ret)
+ printf( "[%s] fail ret=%d...\n", __FUNCTION__, ret);
+
+}
+/*******************************************************************************
+ * Function: zx234290_get_boot_reason
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_get_boot_reason(boot_reason_t *boot_reason)
+{
+ if (boot_reason == NULL)
+ {
+ return -1;
+ }
+
+ if(s_boot_reason == UNKNOWN_BOOT_REASON)
+ {
+ return -EIO;
+ }
+ *boot_reason = s_boot_reason;
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_get_boot_reason
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+static int zx234290_get_boot_reason_prev(void)
+{
+ int ret = 0;
+ uchar reg_user = ZX234290_USER_RST_UNDEFINE;
+ uchar reg_start = 0;
+ uchar reg_write = 0;
+
+ /* ¶Á²¢ÇåSTART_UP_STATUS */
+ ret = zx234290_i2c_read_reg(START_UP_STATUS, ®_start);
+ if( ret != 0 )
+ {
+ return -EIO;
+ }
+ printf( " [%s][START_UP_STATUS = 0x%X] ...\n", __FUNCTION__, reg_start);
+ (*(volatile unsigned long *)(START_UP_STATUS_BASE))=reg_start;
+
+ /* ¶Á²¢ÇåZX234290_REG_USER */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_USER, ®_user);
+ if(reg_user != ZX234290_USER_RST_UNDEFINE)
+ {
+ reg_write = ZX234290_USER_RST_UNDEFINE; /* write back the reset value */
+
+ ret |= zx234290_i2c_write_reg(ZX234290_REG_USER, ®_write);
+ }
+ if ( ret != 0 )
+ {
+ return -EIO;
+ }
+ printf( " [%s][USER_RESERVED = 0x%X] ...\n", __FUNCTION__, reg_user);
+ (*(volatile unsigned long *)(USER_RESERVED_BASE)) =reg_user;
+
+ /* 1. Õý³£¿ª»ú¼ì²â */
+ if( reg_start & PWR_ON_START_UP )
+ /* ϵͳÖØÆô,Èç¹ûZX234290_REG_USER²»Îª³õÖµ£¬ÔòΪÖØÆô */
+ {
+ s_boot_reason = RB_POWER_KEY;
+ return 0;
+ }
+ else if( reg_start & PS_HOLD_START_UP )
+ {
+ s_boot_reason = RB_USB_INSERT;
+
+ /* ZX234290_REG_USERΪÉϵ縴λֵ»ò·Ç·¨Öµ */
+ return 0;
+ }
+ else if( reg_start & RTC_ALARM_START_UP )
+ /* 2. Õý³£¿ª»ú¼ì²â */
+ {
+ uchar rtc_ctrl2 = 0xF0;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_RTC_CONTROL2, &rtc_ctrl2);
+ printf( " [%s][RTC_CONTROL2 = 0x%X]\n", __FUNCTION__, rtc_ctrl2);
+
+ if (rtc_ctrl2 & RTC_CONTROL2_AF) {
+ s_boot_reason = RB_RTC;
+ zx234290_set_rtc_alarm_off();
+ } else if (rtc_ctrl2 & RTC_CONTROL2_TF) {
+ s_boot_reason = RB_RESET_NOMAL;
+ }
+
+ return ret;
+ }
+ else if( reg_start & LLP_RESTART_UP )
+ {
+ s_boot_reason = RB_POWER_KEY_LONG;
+ return 0;
+ }
+ /* reg_startΪ0£¬¼´reg_start¶ÁÇåÖ®ºóδµôµç£¬¼´ÏµÍ³ÖØÆô */
+
+ /* 2. ÖØÆô¼ì²â */
+
+ /* ϵͳÖØÆô,Èç¹ûZX234290_REG_USER²»Îª³õÖµ£¬ÔòΪÖØÆô */
+ switch (reg_user)
+ {
+ case ZX234290_USER_RST_TO_NORMAL:
+ {
+ s_boot_reason = RB_RESET_NOMAL;
+ return 0;
+ }
+
+ case ZX234290_USER_RST_TO_CHARGER:
+ {
+ s_boot_reason = RB_RESET_USB_OFF;
+ return 0;
+ }
+
+ case ZX234290_USER_RST_TO_ALARM:
+ {
+ s_boot_reason = RB_RESET_ALARM;
+ return 0;
+ }
+
+ /* ZX234290_REG_USERΪÉϵ縴λֵ»ò·Ç·¨Öµ */
+ default:
+ {
+ if ((reg_user & 0xF0) == ZX234290_WDT_RST_FLAG) {
+ s_boot_reason = reg_user;
+ return 0;
+ }
+ break;
+ }
+ }
+
+ s_boot_reason = RB_USB_INSERT;
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_ps_hold_pull_on
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_ps_hold_pull_on(void)
+{
+ zDrvGpio_PullUpDown(PIN_PSHOLD_NUM, 0);
+ //gpio_set_reuse(PS_HOLD_PIN, 0);
+ zDrvGpio_SetFunc(PIN_PSHOLD_NUM,GPIO_PSHOLD_FUNC_SEL);
+ zDrvGpio_SetDirection(PIN_PSHOLD_NUM,GPIO_IN); //set output;v3 gpio24(pshold) direction is reverse
+ zDrvGpio_SetOutputValue(PIN_PSHOLD_NUM,GPIO_HIGH);
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_ps_hold_pull_off
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_ps_hold_pull_off(void)
+{
+ zDrvGpio_PullUpDown(PIN_PSHOLD_NUM, 0);
+ //gpio_set_reuse(PS_HOLD_PIN, 0);
+ //gpio_direction_output(PS_HOLD_PIN, GPIO_LOW);
+ zDrvGpio_SetFunc(PIN_PSHOLD_NUM,GPIO_PSHOLD_FUNC_SEL);
+ zDrvGpio_SetDirection(PIN_PSHOLD_NUM,GPIO_IN); //set output;v3 gpio24(pshold) direction is reverse
+ zDrvGpio_SetOutputValue(PIN_PSHOLD_NUM,GPIO_LOW);
+ return 0;
+}
+
+/*******************************************************************************
+ * Function: zx234290_power_off
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int zx234290_power_off(void)
+{
+ return zx234290_ps_hold_pull_off();
+}
+
+/*******************************************************************************
+ * Function:
+ * Description:
+ * Parameters:
+ * Input:
+ *
+ * Output:
+ *
+ * Returns:
+ *
+ *
+ * Others:
+ ********************************************************************************/
+int pmu_init(void)
+{
+ int ret = 0;
+ uchar reg_val = 0;
+ uchar reg_val1 = 0;
+ struct pmu_opt pmu = {NULL};
+
+ /* GPIO init */
+ //gpio_set_reuse(PS_HOLD_PIN, 0x0);
+ //gpio_direction_output(PS_HOLD_PIN,GPIO_LOW);
+
+ // gpio_set_reuse(POWER_KEY_PIN,0x0);
+ // gpio_direction_input(POWER_KEY_PIN);
+
+ // gpio_noaction(POWER_KEY_PIN);
+
+ /* register pmu opt */
+ pmu.read_reg = zx234290_i2c_read_reg;
+ pmu.write_reg = zx234290_i2c_write_reg;
+ pmu.get_boot_reason = zx234290_get_boot_reason;
+ pmu.ps_hold_pull_on = pmu_pull_on_ps_hold;
+ pmu.ps_hold_pull_off = pmu_pull_off_ps_hold;
+ pmu.power_off = zx234290_power_off;
+ ret = register_pmu_opt(&pmu);
+ if( ret != 0 )
+ {
+ return -EIO;
+ }
+
+ ret = zx234290_get_boot_reason_prev();
+ ret +=zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL,®_val);
+ ret +=zx234290_i2c_read_reg(ZX234290_REG_ADDR_TYPE,®_val1);
+ if(reg_val==0x7f){//means 296G C
+ reg_val = 0xff;//define to 296
+ ret+=zx234290_i2c_write_reg(ZX234297_REG_ADDR_SINK_CONTROL,®_val);
+ }
+
+ if (ret != SUCCESS)
+ {
+ printf( "[%s]set 0x29 error ret=0x%x!\n", __FUNCTION__,ret);
+ return ret;
+ }
+
+ if(0xff == reg_val)//296&296G
+ {
+ if(0==reg_val1)
+ g_pmu_type = PMU_TYPE_296G;
+ else
+ g_pmu_type = PMU_TYPE_296;
+ }
+ else//297
+ {
+ if(0==reg_val1)
+ g_pmu_type = PMU_TYPE_296H;
+ else
+ g_pmu_type = PMU_TYPE_297;
+ }
+ return ret;
+}
+
+/* ================================================================================
+ * pmu_init:
+ */
+int pmu_pull_off_ps_hold(void)
+{
+ return zx234290_ps_hold_pull_off();
+}
+
+/* ================================================================================
+ * pmu_init:
+ */
+int pmu_pull_on_ps_hold(void)
+{
+ return zx234290_ps_hold_pull_on();
+}
+
+/* ================================================================================
+ * system_power_off:
+ */
+void system_power_off(void)
+{
+ zx234290_power_off();
+}
+
+int zx234290_get_adc2_voltage(void)
+{
+ int nTempAdc = 0, ret = -1;
+ int adcReadInt = -1;
+ int msb=0, lsb=0;
+ int num;
+ uchar status_a=0;
+ uchar adcEnable = 0x28;
+ uchar sys_ctrl;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ sys_ctrl = (sys_ctrl & (1 << 7)) | adcEnable;
+
+ /*enable adc*/
+#if 0
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL,&sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+#else
+ for(num=1; num <= 50; num++)
+ {
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ udelay((100000/3000)*5); /* delay 5ms */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_STSA, &status_a);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ if(status_a & 0x04)
+ {
+ printf( "adc2 get adc,break num =%d ...\n", num);
+ break;
+ }
+ }
+#endif
+ udelay((100000/3000)*20); /* delay 20ms */
+
+ /*read adc*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC2MSB, &msb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC2LSB, &lsb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ /*clear int*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_INTA, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret =zx234290_i2c_read_reg(ZX234290_REG_INTB, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ nTempAdc = ((msb<<4)|(lsb>>4));
+
+ nTempAdc = (int)((double)(5000-0)*(nTempAdc)/4096);
+
+ return nTempAdc;
+}
+
+int zx234290_get_adc1_voltage(void) /*read adc1*/
+{
+ int nTempAdc = 0,adcEnable = 0,ret = -1;
+ int adcReadInt = -1;
+ int msb=0, lsb=0;
+ int num;
+ uchar status_a=0;
+ adcEnable = 0x30; /*read adc1*/
+ uchar sys_ctrl;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ sys_ctrl = (sys_ctrl & (1 << 7)) | adcEnable;
+
+ /*enable adc*/
+#if 0
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL,&sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+#else
+ for(num=1; num <= 50; num++)
+ {
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ udelay((100000/3000)*5); /* delay 5ms */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_STSA, &status_a);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ if(status_a & 0x04)
+ {
+ printf( "adc1 get adc,break num =%d ...\n", num);
+ break;
+ }
+ }
+#endif
+
+ udelay((100000/3000)*20); /* delay 20ms */
+
+ /*read adc*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1MSB, &msb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1LSB, &lsb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ /*clear int*/
+ ret = zx234290_i2c_read_reg(ZX234290_REG_INTA, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret =zx234290_i2c_read_reg(ZX234290_REG_INTB, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ nTempAdc = ((msb<<4)|(lsb>>4));
+
+ nTempAdc = (int)((double)(5000-0)*(nTempAdc)/4096);
+
+ return nTempAdc;
+}
+
+int zx234290_get_vbat_voltage(void)
+{
+ int nTempAdc = 0,adcEnable = 0,ret = -1;
+ int adcReadInt = -1;
+ int msb=0, lsb=0;
+ int num;
+ uchar status_a=0;
+ //adcEnable = 0x30;
+ adcEnable = 0x20;
+ uchar sys_ctrl;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ sys_ctrl = (sys_ctrl & (1 << 7)) | adcEnable;
+
+#if 0
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL,&sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+#else
+ for(num=1; num <= 50; num++)
+ {
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, &sys_ctrl);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ udelay((100000/3000)*5); /* delay 5ms */
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_STSA, &status_a);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ if(status_a & 0x04)
+ {
+ printf( "vbat get adc,break num =%d ...\n", num);
+ break;
+ }
+ }
+#endif
+ //ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1MSB, &msb);
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_VBATMSB, &msb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ //ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_ADC1LSB, &lsb);
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADC_VBATLSB, &lsb);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_INTA, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret =zx234290_i2c_read_reg(ZX234290_REG_INTB, &adcReadInt);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ nTempAdc = ((msb<<4)|(lsb>>4));
+ nTempAdc = (int)((double)(5000-0)*(nTempAdc)/4096);
+ return nTempAdc;
+}
+
+int zx234290_set_llp_enable(void)
+{
+ int ret = -1;
+ ushort reg=ZX234290_REG_ADDR_PWRON;
+ uchar val=0x05;
+
+ ret = zx234290_i2c_write_reg(reg, &val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ return ret;
+}
+
+/*get the poweron key state 0x1<<5: poweron press 0:poweron up*/
+int zx234290_get_poweron_state(void)
+{
+ int val = 0,ret = -1;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(STATUS_A,®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ val = reg&STATUS_PWR_ON;
+ return val;
+}
+
+/* get the rtc_alarm status: bit0 in reg 0x05 */
+int zx234290_get_rtc_state(void)
+{
+ int val = 0,ret = -1;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(STATUS_B, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ val = reg & STATUS_RTC_ALARM;
+ return val;
+}
+
+/* Set or clear SoftOn bit in ZX234290_REG_SYS_CTRL */
+int zx234290_set_softon(int on)
+{
+ uchar reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_SYS_CTRL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ if ((reg >> 7) != on) {
+ reg ^= (0x01<<7);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_SYS_CTRL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ }
+ return 0;
+}
+
+/*set ldo8 SD VOL*/
+int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol)
+{
+ int ret = 0;
+ unsigned char reg_addr=0, reg_val=0;
+
+ if(vol > VLDOD_MAX)
+ {
+ return -EINVAL;
+ }
+ reg_addr = ZX234290_REG_ADDR_LDO78_VOL;
+ ret = zx234290_i2c_read_reg(reg_addr,®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg_val &= ~(0xf<<ZX234290_LDO8_VSEL_LSH);
+ reg_val |= (vol<<ZX234290_LDO8_VSEL_LSH);
+
+ ret = zx234290_i2c_write_reg(reg_addr, ®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int zx234290_set_ldo8_sleep_voltage(T_ZDrvZx234290_VldoD vol)
+{
+ int ret = 0;
+ unsigned char reg_addr=0, reg_val=0;
+
+ if(vol > VLDOD_MAX)
+ {
+ return -EINVAL;
+ }
+ reg_addr = ZX234290_REG_ADDR_LDO78_VOL;
+ ret = zx234290_i2c_read_reg(reg_addr,®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg_val &= ~(0xf<<ZX234290_LDO8_SLP_VSEL_LSH);
+ reg_val |= (vol<<ZX234290_LDO8_SLP_VSEL_LSH);
+
+ ret = zx234290_i2c_write_reg(reg_addr, ®_val);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
+/* clear SoftOn bit in ZX234290_REG_SYS_CTRL bit7 */
+int zx234290_ldo8_enable(int enable)
+{
+ int ret = -1;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(ZX234290_REG_LDO_EN1, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg &= ~(0x01<<7);
+ reg |= (enable<<7);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_LDO_EN1, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ return 0;
+}
+int zx234290_set_sink(T_ZX234290_SINK sink_num, int is_on, T_ZX234297_SINK_CURRENT sink_current)
+{
+ int ret = 0;
+ unsigned char lsh_on, lsh_current;
+ uchar reg = 0;
+
+ ret = zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ if(0xff==reg){
+ printf("pmu zx234296 no sink\n");
+ return SUCCESS;
+ }
+ if (sink_num == SINK_1) {
+ lsh_on = ZX234297_SINK1_ON_LSH;
+ lsh_current = ZX234297_SINK1_CURRENT_LSH;
+ } else if (sink_num == SINK_2) {
+ lsh_on = ZX234297_SINK2_ON_LSH;
+ lsh_current = ZX234297_SINK2_CURRENT_LSH;
+ } else
+ return -EINVAL;
+
+ if (is_on) {
+ if (sink_current >= SINK_CURRENT_MAX)
+ sink_current = SINK_CURRENT_120MA;
+
+ ret = zx234290_i2c_read_reg(ZX234297_REG_ADDR_SINK_CONTROL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg &= ~(0xf<<lsh_current);
+ reg |= (sink_current<<lsh_current);
+ ret = zx234290_i2c_write_reg(ZX234297_REG_ADDR_SINK_CONTROL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ }
+
+ is_on = !!is_on;
+ ret = zx234290_i2c_read_reg(ZX234290_REG_ADDR_LDO_EN2, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ reg &= ~(0x1<<lsh_on);
+ reg |= (is_on<<lsh_on);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_ADDR_LDO_EN2, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+#if 0
+int zx234290_SetVldo8(Zx234290_VldoD vol)
+{
+ int reg = 0,val = 0,ret = -1;
+ ret = zx234290_i2c_read_reg(ZX234290_REG_LD78_VOL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ BOOT_PRINTF(UBOOT_ERR, "********First REG0x15=0x%x!!!\n",reg);
+ reg &= 0xf;/*00001111*/
+ reg |= (vol<<4);
+ ret = zx234290_i2c_write_reg(ZX234290_REG_LD78_VOL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ ret = zx234290_i2c_read_reg(ZX234290_REG_LD78_VOL, ®);
+ if (ret != SUCCESS)
+ {
+ return -EIO;
+ }
+ BOOT_PRINTF(UBOOT_ERR, "********Last REG0x15=0x%x!!!\n",reg);
+ return 0;
+}
+
+#endif
+
+
diff --git a/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
new file mode 100755
index 0000000..c3de9f3
--- /dev/null
+++ b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.bin
Binary files differ
diff --git a/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
new file mode 100755
index 0000000..4a7e274
--- /dev/null
+++ b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy.map
@@ -0,0 +1,14691 @@
+Mapfile generated by: ZView-4.1.0-Windows
+Archive member included because of file (symbol)
+
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o (_odo_zsp_do_int)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o (_create_process)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o (_odo_panic)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_sys)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_main)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_process_entry)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o) (_send)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_start_zcos)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o) (_odo_go_search)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o) (_alloc)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o) (_odo_arch_init_interrupts)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_ZSP_DCacheUseDCFGRDescribe)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_ZSP_DCacheEnableNCSRAM)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o) (___zsp_dc_mba)
+T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor_addr.o)
+ T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o) (___zsp_dc_mba_value)
+T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o) (_odo_pool_list)
+T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_TIMER0_ISR)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_BspTimerInit1)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_DrvPhyTimer1Init)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_L1_SysErrHnd)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o (_LoadStaticIDNCSRAM)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_L1_SysEntry)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_g_atHookInfo)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_dwMacroSupport_ZX7520_PHY_SP_PS)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_w_assert)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_InitComAtNv)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_save_zsp880_reg)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_L1_DrvL2CacheTcmEnable)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_L1_DrvCacheDisable)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_DrvDmaInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_zDrvRpMsg_CreateChannel)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1_LpmLatchInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o) (_g_dwPHY_USE_PSM)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_LpcDrvChangeCpuPhyFreq)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_tL1IratLpCtrl)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_aeClkSelToCpuFreq)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_PhyPowerOffSaveContext)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_PhyPowerOff)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_L1_DrvWDTFeedDog)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_printk)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_iomemcpy_32)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o) (_L1_DrvL1CacheInit)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o) (_g_atDmaRegCh)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(dmc_zsp_0x140_lp.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_dei_handler_lp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheDsc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheDisableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheEnableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_ZSP_ICacheFlush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheLoadNCSRAM)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_ICacheUseICFGRDescribe)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_ICacheNonCacheableDisable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheDisableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheEnableAllWays)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_poweroff.o) (_ZSP_DCacheFlush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_ZSP_DCacheLoadNCSRAM)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheClean)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheSetWriteThruRegion)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteAllocateEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteThruEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheWriteThruDisable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheNonCacheableEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o) (_ZSP_DCacheExtraNonCacheableEnable)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor_addr.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(ic_descriptor.o) (___zsp_ic_mba_value)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_g_L1wPriTaskPid)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_g_tL1wNvBb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_BchTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DevMeasGetPreSyncInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_HspaTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DevRtxRxPchCfgReq)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_L1w_DevRfSleepInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevPcPilotIntInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o) (_g_tL1wHsdpaDbgInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_wL1wLessCfgIdx)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DrvDpramRxWriteClearData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_g_tUlRfTbl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevTxGetDchState)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o) (_L1W_DevHsupaInitMacro)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_eDivState)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_DlsTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o) (_TAB_L1W_HSDPA_HSDPCCH_ACK_CODING)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_wPiAiAfcIntCnt)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o) (_L1w_DevCsrIntInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (_tPcCalcDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (_g_awL1wEngTempBuffer)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_g_tTxTrchInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRxSccpchDtrParam)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o) (_L1w_DevHsdpaCqiCalcPos)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o) (_L1w_DevRtxRxDecodePcch)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o) (_g_eL1wHsupaTaskType)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_L1w_DevRtxRxIntDataInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o) (_g_tL1wDchDlsPsrReq)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_L1w_DevHsupaIsEfachActive)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_bIsWUsePsm)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_tAfcErrorPrint)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o) (_g_atL1wTpuRegNtFixedEventInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_atDevBchAfcdb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRxInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o) (_L1w_DevRtxRxDsReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_atRfcDcLog)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DrvGetPiAiEnPara)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvLpcModemIntCtrl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_URegLpmTime1CtrlCmd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_g_awL1wRamUtrData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o) (_L1_DrvCsrInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_L1w_DrvSetTop01GdtrHdtrBitSet)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o) (_g_atL1wTpuIntStaticNtPara)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_dRfcSpiReadData)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o) (_g_tRegTpuReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_L1w_DrvTxReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o) (_g_atL1wDrvMeasResultInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o) (_g_tRegPsrWinPosCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_g_bL1wHsdschConfigFlg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o) (_g_tL1wEutrParaConf)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvDpramIsEmpty)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o) (_g_tRegTxReg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_L1w_DrvRxInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_top.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_g_wL1wTop00SoftReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_L1w_DrvDtrSetCsServiceFlg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_L1w_DrvBchReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o) (_g_tRegCsrFpgaVersion)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o) (_L1w_DrvUtrReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_uL1wRegIcSubFrameHead)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_L1w_DrvRfcAbbCsfHpfCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o) (_g_tRegRxRakeChipLvl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o) (_L1w_DrvPsrStartPosCfg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o) (_g_atBandInfoTX)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o) (_g_tRegMeasBufOffline)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o) (_g_tRegPiAiEnble)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_TxCfgOver)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_L1w_SchedMainTask)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_g_tL1wRachProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_L1w_SchMeasQueryCellInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (_g_tL1wCtrlDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCs1ProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o) (_g_tServCellDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o) (_g_tL1wMeasProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_L1w_SchedHsupaGetUpaSchedDb)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCmProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_sc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o) (_L1w_SchedCs1SetStrategy)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_g_tL1wResCtrl)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wBchProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_amt.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_g_tL1wAmtProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wCs0ProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wHspaProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFachProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_page.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wPageProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_dch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wDchProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o) (_L1w_SchedHsdpaFachActive)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wGapProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_efach.o) (_g_tL1wHsdpaProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o) (_L1w_SchedHspaEraInd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFmoProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o) (_g_tL1wFSProcInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o) (_L1w_MathFloatAdd)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o) (_L1w_DevHsupaCalcSubFrmBitmap)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o) (_L1w_DevPcHspaReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o) (_L1w_DevTxRaInit)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o) (_L1w_DevRtxRmReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_L1w_DevHsdpaSendPcTtiInfo)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o) (_g_bL1wHsdpaDmaBusy)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o) (_L1w_DevPcRachReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o) (_g_atL1wHsupaDlCmPattern)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o) (_g_tRegRtxDtrReg)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o) (_g_uRegBchTxdMode)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o) (_L1w_DrvDmaReset)
+T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o) (_L1w_SchedHsdpaPchCfgPSCmd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_g_L1LteAPriTaskPid)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_NVInit)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_etmtlog_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_LTE_TPU_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_ecsi_CSIAThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_edls_PDschIsr)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o) (_wPchUseSibFlag)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_erfc_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_wCNT)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_epbch_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_zPHY_edls_tDlsCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_atCqiCommonInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_t_zPHY_Dls2UlsDciValue)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_ptRxp_Ops)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_t_zPHY_eula_CtrlBlock)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o) (_g_tL1lLpCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_zPHY_erfc_SupSampleRateSet)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_ZPHY_ecsrm_tMeasState)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o) (_g_zPHY_ecsrm_bHalfFrame)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_UL_CSI_CombThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_Tx2Rx2_NL2_PMICalc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o) (_g_tRxpCirCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_aswOutdata)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_SumLOGNoSqrt_RICalc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o) (_g_tLteA1DlaRxCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_EDFE_SYSTEM_INFO)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eula_Entry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_t_zPHY_DlaCb)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eula_ProInitial)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_Int_dwDFEIntType_agc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_eulpc_GetConfigParas)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (_g_awL1lEngTempBuffer)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o) (_zEasn1p_DcT_zEurrc_PCCH_Message)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_zPHY_edla_PdcchBlindDetectProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (_Asm_CqiSinglePort_TX1_RX1_NL1)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_g_bIsRarNewTrans)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_ACP405_AFC_DIFF)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_DevDlsDecodeDciF1A)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_gadwCsiRsPosCalculated)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_zPHY_eulpc_PucchPowCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_g_ac_zPHY_edls_TddSubframeType)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_DrvDdtrResetCfg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o) (_zPHY_DrvTopIntAbleBitSet)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_L1L_TpuDrvReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_g_tzPHY_eulpc_At2UlPc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o) (_g_zPHY_tLpcPwrDomainState)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_eltx_SoftReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_zPHY_ecsrm_MeasHwReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_adw_Drv_Rx_FixFirCoeff_16QAM)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_elutr_SoftReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o) (_L1e_DrvRxMimoReset)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_L1e_DrvMimoCaRstCfg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_zPHY_erfc_atCurrentSFConfig)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o) (_g_atzPHY_erfc_atRFABBMainSyncEvent)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_g_zPHY_erfc_cTddOrFddSel)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_cAGCCalMode)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o) (_g_CsrGapInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o) (_zPHY_erapc_ThreadEntry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_g_awAgcNoBalance)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_g_wSibPrintCtrlCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o) (_g_L1e_tDlRfcCfgInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_g_L1e_ConnIntraRptCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_zPHY_emc_ProPhyStateCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_g_zPHY_erapc_tCtrlBlock)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_zPHY_ecsrc_SatAdd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_g_zPHY_ecsrc_tMulmInactiveTimeInd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_g_RxOpenPara)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o) (_EventHandler)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_L1e_SchedMbmsInit)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_g_zPHY_emc_bDrxActvieFlag)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_zPHY_emc_ProRadioLink_SetFIUpdateInd)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_gtAmtCellSyncProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_g_sbFixTaAutoAdjFlg)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o) (_g_tHandoverReq)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_g_wPreSyncInterval)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o) (_zPHY_ecscMeas_LogMeasConfigReq)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o) (_L1e_LogDlDlsDciDetInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_zPHY_ecsc_LogMibReqCellInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o) (_zPHY_ecsm_LogMeasHwInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o) (_zPHY_ecsccs_LogRSStart)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_L1e_LogDlRxMbsfnCirInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_emulm_LogCsrSlaveStateChange)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o) (_L1e_logCmnMbmsMbsfnSubfListInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_L1e_csrs_LogSetFtErrorList)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o) (_zPHY_ecsm_LogBlackCell)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_zPHY_Float2Fixpoint)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o) (_g_zPHY_SID)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_L1l_CmnAssert)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o) (_zPHY_eula_PucchSrsRelease)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_adw_zPHY_Rx_NormalSfnTypeValue)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_at_zPHY_NxtHiQuadPosTab)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_wNotSyncAgcIntCnt)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_zPHY_eulpc_SrsPowCtrl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o) (_zPHY_euls_Entry)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (_g_aswTwf)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o) (_g_tzPHY_ecsrs_FSPara)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o) (_zPHY_euls_ReleaseSPSMode)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetPssStartInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_g_ai_zPHY_Tdd_MiTab)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o) (_zPHY_eula_PuschAckProcess)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o) (_zPHY_eulpc_UlsRelativePuscchPowCtrlProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (_g_zPHY_edfe_wRxLog2Dagc0)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o) (_zEasn1p_per_dcOctStr)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_G_EULPC_RARTPCVAL)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetCfoStartInfo)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o) (_zPHY_edla_PcfichProc)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_zPHY_ecsrs_GetNearValidTime)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o) (_g_atEcsrSearchPeakdatabase)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o) (_g_ptTi_Ctl)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o) (_g_CsrDrvCfgInfor)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1_ref.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (_GainValueConfig_TDD)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o) (_L1e_FS_LogAddSearchResult)
+T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o) (_zPHY_ecsrs_ListAdd)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_s_create_pool)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_create_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o) (_current_process)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o) (_delay)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_free_buf)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o) (_get_pri)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o) (_get_ticks)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_g_pcZcosVersion)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o) (_kill_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o) (_receive)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o) (_s_alloc_nil)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o) (_sender)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (_set_pri)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_signal_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_start)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o) (_zcos_sysd_init)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o) (_tick)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o) (_wait_sem)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_odo_hunt_find_name)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_restore)
+T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_send_w_s)
+T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o) (_zDrvEfuse_IsSpe)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(32.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___modhi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___addsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(compare_IEEE.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___lthf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convert.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___floatunshihf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convertqi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___floatqihf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(div.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o) (___divqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Div.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___divsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(divzi3_v2.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o) (___divzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(errno.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o) (_ierrno)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ftou.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o) (___ieee754_ftou)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o) (_memcmp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy16.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o) (___memcpy16)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o) (_memcpy)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memset.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o) (_memset)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mod.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o) (___modqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(modzi3_v2.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o) (___modzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Mul.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___mulsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pnan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o) (___ieee754_propagate_nan)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o) (_sprintf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strchr.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strchr)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcmp.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o) (_strcmp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strcpy.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strcpy)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(strlen.o)
+ T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o) (_strlen)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Sub.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o) (___subsf3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udiv.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (___udivqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(udivzi3_v2.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___udivzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(umod.o)
+ T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o) (___umodqi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(umodzi3_v2.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o) (___umodzi3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(vsprintf.o)
+ T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o) (_vsprintf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o) (___adddf3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___fixsfhi.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___fixsfhi)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatsisf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o) (___floatsisf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatunsisf.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___floatunsisf)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___gesf2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___gesf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___gtsf2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o) (___gtsf2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (___muldf3_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_packFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_packFloat64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_addFloat64Sigs.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o) (_staticFunc_addFloat64Sigs)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeFloat64Subnormal.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_normalizeFloat64Subnormal)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeRoundAndPackFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___floatsisf.o) (_staticFunc_normalizeRoundAndPackFloat64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_propagateFloat64NaN)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_roundAndPackFloat64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_staticFunc_roundAndPackFloat64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_subFloat64Sigs.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___adddf3_v2.o) (_staticFunc_subFloat64Sigs)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___subdf3_v2.o)
+ T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o) (_(short, bool __restrict, double, float, _v2))
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(sprintf.o) (__vfsprintf_sdsp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrli3.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (___lshrli3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrzi3.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(lshrli3.o) (___lshrzi3)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mul64To128.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___muldf3_v2.o) (_mul64To128)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(shift64RightJamming.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_addFloat64Sigs.o) (_shift64RightJamming_v2)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_data.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_roundAndPackFloat64.o) (_float_rounding_mode)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_extractFloat64Exp.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat___fixsfhi.o) (_extractFloat64Exp)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_float64_is_nan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o) (_float64_is_nan)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_float64_is_signaling_nan.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_propagateFloat64NaN.o) (_float64_is_signaling_nan)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_countLeadingZeros64.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(zoftfloat_staticFunc_normalizeFloat64Subnormal.o) (_staticFunc_countLeadingZeros64)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(atoi.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (_atoi)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ctype.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (___ctype)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (_fputc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fwrite_8bit.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(low_level.o) (_fwrite_8bit)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o) (__zsim_fputc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fwrite_8bit.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fwrite_8bit.o) (__zsim_fwrite_8bit)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fflush.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fputc.o) (_fflush)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pr_routines.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o) (___zsim_fputc)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fputc.o) (_ZSPgetUserDevice)
+C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(_zsim_fwrite.o)
+ C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(fflush.o) (__zsim_fwrite)
+
+Allocating common symbols
+Common symbol size file
+
+_g_awSyncMsgBuff 0x2ee0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_tL1wDevDbHsdpaCfgReqB
+ 0x7c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_zPHY_edfe_wAgcEnEventFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_L1l_LpmCaliIdx 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_ThreadIntraCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_dwOffsetDelta 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_atDevBchAfcdb 0x7a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_dwL1lPreHookEntry
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_g_tTempDCOffsetComp
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_atL1wCellType 0xc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_wLastBand 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+_g_tL1wDevDbUlDpchCfgReqA
+ 0x3d6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_atEcsrSearchPeakdatabase
+ 0xf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_tL1lCallStackInfo
+ 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+_g_eTxCalibrationStep
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+_g_tL1wCmCfnN0123Bitmap
+ 0x5a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_tL1wDevDbHsdpaCfgReqA
+ 0x7c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_awPSeqCellIDDiv30
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_zPHY_erfc_tempDac
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_dL1wDprICPSSFN 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+_g_zPHY_bDdtrWorkFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+_g_wAdrIcCellState 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+_g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+_g_awFHopSeq4SubBands
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_tRfRxOffsetCfgInfo
+ 0x5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_tTTIBundlingDB 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_adL1wTpuTaskID 0x1a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+_g_tLteAmtCellSyncPara
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_edfe_wRxLinDagc1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_tWUpaStdlogStatisitcInfo
+ 0xe T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+_g_tWcdmaUserNv 0xbec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+_g_dwTpcPrintCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_tUEIdInfo 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+_g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_atL1RfSegInfo 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_EUL_SrsStatisticsInfo
+ 0x158 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_awL1wStandardMsgRpt
+ 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+_g_atL1wTpuRegRtVarEventInfo
+ 0x235 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+_g_zPHY_edfe_swAgcMeanPwr1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_swPrintProNoInt 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+_g_tL1wDevMeasInfo 0x3eb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+_g_tTimerCnt 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_zPHY_euls_tTpcCommands
+ 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+_g_zPHY_emc_tCommonConfigReq
+ 0x96 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_CsContext 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_g_tzPHY_ecsrs_FSPara
+ 0xd91 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+_g_wRLMATQInFlg 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_erfc_TempStartRecordFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_awMbmsClusterNum
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+_gL1l_MissLogInfo 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_g_zPHY_ecsrm_wNextIntFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+_g_adw_zPHY_erfc_profile_DB
+ 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+_g_sdRLMATQIn 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_emc_wSIDataBufSel
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_g_zPHY_ecsrc_wPiPeriod
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_dwOffsetFlag 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
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+_g_wLayerNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+_g_wSssHwRestartCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_slot0_nRBNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_wCsrs_RX_Sib1_Read_Flag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_tUlReportBlerInfo
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_zPHY_edfe_tRxAgcBalance
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_gtLteRfcRpiPwrCtl 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_tWUpaDlDebugInfo
+ 0x6b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+_g_tHsdpaResetInfo 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+_g_zPHY_ecsrc_swBackupCFOFreqOffset
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_erfc_tpu 0x60 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+_g_tIqMappingCon 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_awCsiRsCheCfgVal
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_tRfcTmpReadInfo 0x5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+_g_w_FirstFlgSet 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_zPHY_AMT_SrvCellRsrp
+ 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_LtePhySleepCnt
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_g_zPHY_edfe_wAgcDagcGain
+ 0x1f0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_g_L1e_mulm_40msGapCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_l1wATSetAPCFlag 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+_g_zPHY_erfc_RfStateMap
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_PchBlerInfo_2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_EDL_AT_INFO 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_tDchAscPara 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+_g_wTpuNtRegLpcSave
+ 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+_g_FreqScanData 0x86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_zPHY_edfe_tMbsfnAgcInfo
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_TotalPuschNumTB0 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_EUL_wPrachPowerIdx
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+_g_Next2SubFrameDrxActiveSidFlag
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+_g_tL1wCmInfoForN4N9
+ 0xca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_ThreadCfoCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_aiInitSequence 0x200 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+_g_ThreadInterCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_sL1wUlAdujstFlag
+ 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_tWDevDbHspaPlusFachCfgReq
+ 0x544 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+_g_awMaxLayerNum 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+_g_at_zPHY_erfc_atReloadData
+ 0x40 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+_g_ThreadMulmCs 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+_g_pSemId_TXIntPulse
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+_g_L1e_ConnIntraRptCnt
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_TmtLogCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_edfe_tMbsfnAgcGain
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+_tPcInfoDb 0x146 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_awFHopSeq3SubBands_Scell
+ 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_pSemId_INTH2 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+_g_zPHY_emulm_tMulmIdlePeriodReqFlag
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_tL1wAddionCtrl 0x1a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+_g_PchTiCfgInd_2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_zPHY_emc_tRadioLinkCtrlInfo
+ 0xf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+_g_zPHY_emulm_tMulmAfcPara
+ 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_wRfSegNum 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+_g_dOldUlTiming 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_atRfcOpen 0x3a0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+_g_zPHY_erfc_dwConFr33RefClk
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+_g_tL1wDpaRlReqInfo
+ 0x2f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+_g_awTempMeanPower0
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_eRfcRamState 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+_g_atMeasSpsrInfo 0x3c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+_g_t_zPHY_etx_RarUlGrant
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+_g_zPHY_ecsrc_atSlaveMeasInfo
+ 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_emulm_tFilterMeas
+ 0x621 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_zPHY_emc_tReleaseCtrlParam
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_dwFdt10MsCnt 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_erfc_Meas0SubfDef
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+_g_wCNT 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+_g_zPHY_sdwRxAnt1OffsetValue
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+_gdwTmtFlowCount 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_emc_tReadSib1Req
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+_ps2phy_chinfo 0x300 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_tzPHY_eulpc_PowerCtrlParas
+ 0x13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+_g_adwDebug 0xc8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+_g_EUL_PrachStatisticsInfo
+ 0xd9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_dwCalibration_amp
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+_g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_emc_tRaMsgHoldFlag
+ 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_zPHY_edfe_wRxLog2Dagc0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+_g_L1l_MrtrAfterSleep
+ 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+_gIramHookCnt 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+_g_DbgMibPerStat 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_zPHY_AMT_Frequency
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+_g_zPHY_Int_dwDFEIntType_agc
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+_g_tRtxPcPrachMessageInfo
+ 0x13 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+_gt_zPHY_Rx_CsiRsExistInd
+ 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+_g_L1e_wSiTimingNeibState
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+_g_atL1wDrvMeasResultInfo
+ 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+_g_tL1wPsCmConfigBuffer
+ 0x7e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+_g_sdAtCtl_ApcOffsetTime
+ 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+_g_wL1lRemainLen 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+_gRpMsgReadMutex 0x100 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+_g_awL1eRxDrsAccNum
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+_g_zPHY_edfe_wAgcdBGain1
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+_g_L1e_tDlRfcCfgInfo
+ 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+_g_L1eTempAdc 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_g_zPHY_ecsrc_tMulmIratMeasConfig
+ 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+_g_wCsiWorkFlg 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+_g_L1e_tMibRfcBackUp
+ 0xb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+_g_TpuCfgOver 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+_g_L1e_Csrc_bCellSearchPbch
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+_tMprTest 0xcb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+_g_dwUlHarqFailCount
+ 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+_g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+INCSRAM 0x00000000 0x00008000
+//OLINCSRAM 0x00000000 0x00000000
+DNCSRAM 0x00010000 0x00007000
+OLDNSCRAM 0x00015400 0x00001c00
+HEAP_STACK 0x00017000 0x00001000
+IRAM 0x41000000 0x00008000
+IRAM1 0x00080800 0x00000600
+DDR 0x10000000 0x00180000
+L2_CODE_TCM_STA 0x30060000 0x00004000
+L2_CODE_TCM_DYN 0x30064000 0x00004000
+L2_DATA_TCM_STA 0x30068000 0x00004000
+L2_DATA_TCM_DYN 0x3006c000 0x00004000
+DMA_REG 0x00980000 0x00001000
+ICP_REG 0x0098101c 0x00000030
+ICP_REG_M0 0x009810f4 0x00000030
+ICU_REG 0x00400800 0x00001000
+UART_REG 0x00a00800 0x00001000
+SLOTBUF_LTE_REG 0x7e010140 0x00000008
+TOP_REG 0x7e080000 0x00000800
+TPU_REG 0x7e080800 0x00001800
+RFC_REG 0x7e082000 0x00002800
+//DFE_RX_REG 0x7e084000 0x00000400
+//DFE_TX_REG 0x7e084400 0x00000400
+CSR_REG 0x7e084800 0x00000a00
+MEAS_REG 0x7e085200 0x00000e00
+CSR_FULLSCAN_REG 0x7e086000 0x00000200
+BCH_REG 0x7e086200 0x00000600
+PSR_REG 0x7e086800 0x00000100
+TX_REG 0x7e087000 0x00000200
+UTR_REG 0x7e087600 0x00000200
+EUTR_REG 0x7e087c00 0x00000400
+//RAKE_REG 0x7e088000 0x00000000
+RX_REG1 0x7e088000 0x00000800
+RX_REG2 0x7e088800 0x00000800
+RX_REG3 0x7e089000 0x00000800
+RX_REG4 0x7e089800 0x00000800
+GDTR_REG 0x7e08a000 0x00002000
+EAGCH_REG 0x7e08c000 0x00000400
+ADR_REG 0x7e08c400 0x00000200
+IC_REG 0x7e08c600 0x00001a00
+HDTR_REG 0x7e08e000 0x00000400
+HSSCCH_REG 0x7e08e400 0x00000400
+PICH_REG 0x7e08e800 0x00000200
+SLOTBUF_REG 0x7e08f000 0x00000200
+HDTR_LESS_REG 0x7e08f400 0x00000c00
+CSR_RAM 0x7c080000 0x00000400
+MEAS_RAM 0x7c080400 0x00000200
+BCH_RAM 0x7c080600 0x00007a00
+PSR_DATA_RAM 0x7c088000 0x00000400
+TX_RAM0 0x7c08e000 0x00002000
+TX_RAM1 0x7c090000 0x00002000
+UTR_RAM 0x7c092000 0x00004000
+EUTR_RAM 0x7c096000 0x00002000
+RX_RAM1 0x7c09a000 0x00000140
+RX_RAM2 0x7c09a140 0x00000040
+RX_RAM3 0x7c09a180 0x00000040
+RX_RAM4 0x7c09a1c0 0x00000100
+RX_RAM5 0x7c09a240 0x000005c0
+RX_RAM6 0x7c09a800 0x00000400
+RX_RAM7 0x7c09ac00 0x00000020
+RX_RAM8 0x7c09ac20 0x000013e0
+RX_RAM9 0x7c09c000 0x00000800
+RX_RAM10 0x7c09c800 0x00001000
+RX_RAM15 0x7c09d800 0x00000100
+RX_RAM16 0x7c09d900 0x00000300
+RX_RAM17 0x7c09dc00 0x00000040
+RX_RAM18 0x7c09dc40 0x00000040
+RX_RAM19 0x7c09dc80 0x00000040
+RX_RAM20 0x7c09dcc0 0x00000040
+RX_RAM21 0x7c09dd00 0x00000040
+RX_RAM22 0x7c09dd40 0x00000040
+RX_RAM23 0x7c09dd80 0x00000040
+RX_RAM24 0x7c09ddc0 0x00000140
+RX_RAM25 0x7c09df00 0x00000020
+RX_RAM26 0x7c09df20 0x000020e0
+GDTR_RAM 0x7c0a0000 0x00000400
+ADR_RAM 0x7c0b0000 0x00010000
+HDTR_RAM 0x7c0c0000 0x00008000
+PIAI_RAM 0x7c0c8000 0x00000100
+SLOTBUF_RAM 0x7c0e0000 0x00008000
+SLEEP_REG 0x0009a300 0x00000040
+RFFE_REG 0x7c250000 0x00000208
+SPI_REG 0x7c250208 0x00000010
+TD_TOP_REG 0x7e100000 0x00000080
+TD_TPU_REG 0x7e100400 0x00000040
+TD_AFC_REG 0x7e100800 0x00000400
+TD_CSR_REG 0x7e100c00 0x00000400
+TD_DST_REG 0x7e101000 0x00000080
+TD_RX_REG 0x7e101400 0x00000200
+TD_GDTR_REG 0x7e101800 0x00000100
+TD_HDTR_REG 0x7e101c00 0x00000040
+TD_UTR_REG 0x7e102000 0x00000079
+TD_ULC_REG 0x7e102079 0x00000187
+TD_HSUPA_REG 0x7e102200 0x00000080
+TD_DM_RDB_REG 0x7e103000 0x00000010
+TD_RFC_REG 0x7e104000 0x00005000
+TD_TFCI_REG 0x7e103400 0x00000020
+TD_SLEEP_REG 0x0009a200 0x00000080
+TD_PSLPM_REG 0x0009a280 0x00000080
+TD_VITERBI_REG 0x7e103400 0x00000020
+TD_CSR_DPRAM_MEM 0x7c100400 0x00000800
+TD_DST_DPRAM_MEM 0x7c104000 0x00000400
+TD_DST_DPRAM_INTERF_MEM 0x7c104800 0x00000400
+TD_UL_DPRAM_MEM 0x7c108000 0x00000400
+TD_HSUPA_MEM 0x7c10a000 0x00002000
+TD_RX_DPRAM_MEM2 0x7c10c000 0x00001000
+TD_GDTR_DPRAM_MEM 0x7c114000 0x00004000
+//TD_GDTR_DPRAM_TEST_MEM 0x7c118000 0x00004000
+TD_HDTR_DPRAM_MEM 0x7c11c000 0x00004400
+DST_SLOT_BUF 0x7c122000 0x00008000
+*default* 0x00000000 0xffffffff
+RAKE_REG 0x00000000 0xffffffff
+
+Linker script and memory map
+
+START GROUP
+LOAD T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a
+LOAD T:/cp/phy/rtos/zcos/os_krn/libczspfft.a
+LOAD T:/cp/phy/rtos/zcos/os_krn/libzspcache.a
+LOAD T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a
+LOAD T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libm.a
+LOAD T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a
+LOAD T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a
+LOAD /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+LOAD T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+END GROUP
+LOAD C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a
+ 0x10000000 . = 0x10000000
+
+.text 0x10000000 0xa7b05
+ 0x10000000 _stext = .
+ *(.ddr_vectors)
+ .ddr_vectors 0x10000000 0x8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ *(.text)
+ .text 0x10000008 0x83 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ 0x10000008 0x80 __start
+ 0x10000088 0x3 __finished
+ .text 0x1000008b 0xe3 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ 0x1000008b 0x2e _L1_DrvIcuIntStart
+ 0x100000b9 0x1b _L1_DrvIcuIntMask
+ 0x100000d4 0x1a _L1_DrvIcuIntUnMask
+ 0x100000ee 0x27 _ICU_ISR
+ 0x10000115 0x2 _L1_DrvIcuError
+ 0x10000117 0x57 _L1_DrvIcuInit
+ .text 0x1000016e 0xbe T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ 0x1000016e 0x5 _L1_DrvIntInit
+ 0x10000173 0x5 _L1_DrvIntMaskAll
+ 0x10000178 0x27 _L1_DrvIntMask
+ 0x1000019f 0x26 _L1_DrvIntUnMask
+ 0x100001c5 0x67 _L1_DrvInstallIsr
+ .text 0x1000022c 0x19a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ 0x1000022c 0xc8 _odo_create_process
+ 0x100002f4 0x72 _s_create_process
+ 0x10000366 0x60 _create_process
+ .text 0x100003c6 0x8d T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x100003c6 0x54 _odo_error
+ 0x1000041a 0x5 _error
+ 0x1000041f 0x5 _error2
+ 0x10000424 0x20 _odo_panic
+ 0x10000444 0x3 _odo_panic2
+ 0x10000447 0x9 _odo_panic_nonfatal
+ 0x10000450 0x3 _odo_panic_nonfatal2
+ .text 0x10000453 0x179 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x10000453 0x31 _creat_pcb
+ 0x10000484 0x8e _odo_init_os_stage2
+ 0x10000512 0x4d _creat_idlepcb
+ 0x1000055f 0x6d _odo_init_os
+ .text 0x100005cc 0xc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ 0x100005cc 0xc _main
+ .text 0x100005d8 0xf7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ 0x100005d8 0x21 _odo_process_entry
+ 0x100005f9 0x3f _odo_alloc_pcb
+ 0x10000638 0x20 _odo_init_process
+ 0x10000658 0x77 _odo_init_pcb
+ .text 0x100006cf 0xa4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ 0x100006cf 0xa4 _send
+ .text 0x10000773 0x26 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ 0x10000773 0x26 _start_zcos
+ .text 0x10000799 0xee T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ 0x10000799 0x1e _odo_go_search
+ 0x100007b7 0x6b _odo_do_swap
+ 0x10000822 0x2d _odo_wait
+ 0x1000084f 0x38 _odo_swap_if_necessary
+ .text 0x10000887 0x90 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ 0x10000887 0x90 _alloc
+ .text 0x10000917 0x94 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ 0x10000917 0x1b _update_mask_list
+ 0x10000932 0x8 _odo_arch_init_interrupts
+ 0x1000093a 0x5c _odo_arch_create_osint
+ 0x10000996 0x15 _odo_arch_init
+ .text 0x100009ab 0x16 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ 0x100009ab 0x16 _ZSP_DCacheUseDCFGRDescribe
+ .text 0x100009c1 0xa T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_enable_ncsram.o)
+ 0x100009c1 0xa _ZSP_DCacheEnableNCSRAM
+ .text 0x100009cb 0x104 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x100009cb 0x5b _odo_config_init_pools
+ 0x10000a26 0x44 _odo_config_start_handler1
+ 0x10000a6a 0x65 _odo_config_start_handler2
+ .text 0x10000acf 0x23 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ 0x10000acf 0x5 _L1_TIMER0_ISR
+ 0x10000ad4 0x1e _L1_SysIdleTask
+ .text 0x10000af2 0x6e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ 0x10000af2 0x1b _BspTimerInit1
+ 0x10000b0d 0xd _BspTimerInit2
+ 0x10000b1a 0x1b _BspTimerGet
+ 0x10000b35 0x1c _BspTimerCallbackReg
+ 0x10000b51 0xf _Timer0_ISR
+ .text 0x10000b60 0xf5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ 0x10000b60 0x4d _L1_DrvTimer
+ 0x10000bad 0x6 _L1_DrvTimerStop
+ 0x10000bb3 0x42 _L1_DrvPhyTimer1Init
+ 0x10000bf5 0x1e _L1_DrvSwDelay
+ 0x10000c13 0x6 _L1_DrvGetTimeCnt
+ 0x10000c19 0x10 _L1_DrvCalcTimeElapse
+ 0x10000c29 0x10 _L1_DrvTimer0Init
+ 0x10000c39 0xf _L1_DrvTimer1Init
+ 0x10000c48 0x6 _TIMER0_INT
+ 0x10000c4e 0x7 _TIMER1_INT
+ .text 0x10000c55 0x2cc T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x10000c55 0x1a _L1_SysSendRamDumpIcp
+ 0x10000c6f 0x1e9 _ramdump_client_cmm_create_sde
+ 0x10000e58 0x36 _L1_SysErrHnd
+ 0x10000e8e 0x42 _RAMDUMP_ICP_ISR
+ 0x10000ed0 0x33 _L1_AllocHookDebug
+ 0x10000f03 0x1e _L1_FreeHookDebug
+ .text 0x10000f21 0x1ed T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ 0x10000f21 0x90 _LoadStaticIDNCSRAM
+ 0x10000fb1 0xd _CpyDdrBetweenL2Tcm
+ 0x10000fbe 0x6c _FirstLoadL2Tcm
+ 0x1000102a 0x1 _DynamicLoadL2CodeTcm
+ 0x1000102b 0x4f _CopyBackL2TcmData
+ 0x1000107a 0x94 _UpdateL2TcmDynamic
+ .text 0x1000110e 0x215 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ 0x1000110e 0x105 _L1_InitMacro
+ 0x10001213 0x110 _L1_SysEntry
+ .text 0x10001323 0x63 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x10001323 0x1a __ASSERT
+ 0x1000133d 0x35 __AllocMsg
+ 0x10001372 0xb _ZSP_DelayChip
+ 0x1000137d 0x7 _ZSP_delay_clock
+ 0x10001384 0x2 _erfc_tpu_state
+ .text 0x10001386 0x132f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x10001386 0x11 _phy_memcpy
+ 0x10001397 0x1 _TD_WD_L1_Init
+ 0x10001398 0x22 _L1_RfcSscConfig
+ 0x100013ba 0xa _L1_RfcSscClkEnDisable
+ 0x100013c4 0x59 _L1_RfcSpiWriteSleep
+ 0x1000141d 0x59 _L1_RfcAbbSpiWriteSleep
+ 0x10001476 0x8 _L1_RfcGetSpiRdDataSleep
+ 0x1000147e 0x10 _L1_RfcMipiRffeWrite
+ 0x1000148e 0x44 _L1_RfcMipiInit
+ 0x100014d2 0x16 _L1_RfcDcxoTempDacInit
+ 0x100014e8 0x1b _L1_RfcDcxoTempDacBSearch
+ 0x10001503 0x36 _L1_RfcDcxoGetTempFromDac
+ 0x10001539 0x30 _L1_RfcDcxoGetTempDegree
+ 0x10001569 0x1a _L1_Rf220TxOff
+ 0x10001583 0x1a _L1_Rf220TxOn
+ 0x1000159d 0x12 _L1_Rf220A1IsoOn
+ 0x100015af 0x12 _L1_Rf220A1IsoOff
+ 0x100015c1 0x17 _L1_Abb128TxOff
+ 0x100015d8 0x18 _L1_Abb128TxOn
+ 0x100015f0 0x1 _L1_Rf220GsmWakeUpOn
+ 0x100015f1 0x1 _L1_Rf220GsmWakeUpOff
+ 0x100015f2 0x8 _L1_Abb128WakeUpOff
+ 0x100015fa 0x9 _L1_Abb128WakeUpOn
+ 0x10001603 0x12 _L1_Abb128ResetOff
+ 0x10001615 0x30 _L1_Abb128ResetOn
+ 0x10001645 0x8 _L1_AbbIsoEnOff
+ 0x1000164d 0x9 _L1_AbbIsoEnOn
+ 0x10001656 0x1b9 _L1_Abb128DRXFilterCnfLTE20
+ 0x1000180f 0x1b4 _L1_Abb128DRXFilterCnfLTE15
+ 0x100019c3 0x1b4 _L1_Abb128DRXFilterCnfLTE10
+ 0x10001b77 0x1b4 _L1_Abb128DRXFilterCnfLTE5
+ 0x10001d2b 0x1c2 _L1_Abb128DRXFilterCnfLTE3
+ 0x10001eed 0x1a2 _L1_Abb128DRXFilterCnfLTE1_4
+ 0x1000208f 0x197 _L1_Abb128DRXFilterCnfWcdma
+ 0x10002226 0x1ad _L1_Abb128DRXFilterCnfTdscdma
+ 0x100023d3 0xac _L1_Abb128DRXFilterCnfHpf
+ 0x1000247f 0x20 _L1_RfGpioPinMuxReCfg
+ 0x1000249f 0x8 _L1_Rfc_IratShare_Lock
+ 0x100024a7 0xa _L1_Rfc_IratShare_UnLock
+ 0x100024b1 0x13 _L1_AbbClkEnCtrl
+ 0x100024c4 0xbc _L1_RfcIdleToSleepForLp
+ 0x10002580 0x135 _L1_RfcSleepToIdleForLp
+ .text 0x100026b5 0xa0 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x100026b5 0x75 _w_assert
+ 0x1000272a 0x15 _delay_ms
+ 0x1000273f 0x16 _delay_10us
+ .text 0x10002755 0x9cb T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x10002755 0x25 _L1_InitComAtNv
+ 0x1000277a 0x79 _L1_MmcPrioLteReset
+ 0x100027f3 0x74 _L1_MmcPrioLteMaster
+ 0x10002867 0x79 _L1_MmcPrioLteSlave
+ 0x100028e0 0x5 _L1_MmcPrioLteSlaveInFsPostPro
+ 0x100028e5 0x5 _L1_MmcPrioLteSlaveOutFsPostPro
+ 0x100028ea 0x17 _L1_MmcPrioLteEIcp
+ 0x10002901 0x17 _L1_MmcPrioLteEIcpRestore
+ 0x10002918 0x5 _L1_MmcPrioLteSleep
+ 0x1000291d 0x5 _L1_MmcPrioLteWakeup
+ 0x10002922 0x49 _L1_MmcPrioWReset
+ 0x1000296b 0x49 _L1_MmcPrioWMaster
+ 0x100029b4 0x49 _L1_MmcPrioWSlave
+ 0x100029fd 0x5 _L1_MmcPrioWSleep
+ 0x10002a02 0x5 _L1_MmcPrioWWakeup
+ 0x10002a07 0x7 _L1_MmcSetResetPrio
+ 0x10002a0e 0x2f _L1_MmcGetLteStamp
+ 0x10002a3d 0x34 _L1_MmcGetWStamp
+ 0x10002a71 0x34 _L1_MmcGetTdsStamp
+ 0x10002aa5 0x39 _L1_MmcGetGsmStamp
+ 0x10002ade 0x20 _L1_MmcTimeTransLte2Ms
+ 0x10002afe 0x2b _L1_MmcTimeTransW2Ms
+ 0x10002b29 0x2a _L1_MmcTimeTransTds2Ms
+ 0x10002b53 0x28 _L1_MmcTimeTransGsm2Ms
+ 0x10002b7b 0x1d _L1_MmcTimeTransMs2Lte
+ 0x10002b98 0x20 _L1_MmcTimeTransMs2W
+ 0x10002bb8 0x1f _L1_MmcTimeTransMs2Tds
+ 0x10002bd7 0x32 _L1_MmcTimeTransMs2Gsm
+ 0x10002c09 0x17 _L1_MmcTimeTransLte2W
+ 0x10002c20 0x17 _L1_MmcTimeTransLte2Tds
+ 0x10002c37 0x17 _L1_MmcTimeTransLte2Gsm
+ 0x10002c4e 0x17 _L1_MmcTimeTransW2Lte
+ 0x10002c65 0x17 _L1_MmcTimeTransW2Gsm
+ 0x10002c7c 0x17 _L1_MmcTimeTransTds2Lte
+ 0x10002c93 0x17 _L1_MmcTimeTransTds2Gsm
+ 0x10002caa 0x17 _L1_MmcTimeTransGsm2Lte
+ 0x10002cc1 0x17 _L1_MmcTimeTransGsm2W
+ 0x10002cd8 0x17 _L1_MmcTimeTransGsm2Tds
+ 0x10002cef 0x4e _L1_MmcPosTransLte2Gsm
+ 0x10002d3d 0x49 _L1_MmcPosTransGsm2Lte
+ 0x10002d86 0x47 _L1_MmcPosTransW2Gsm
+ 0x10002dcd 0x38 _L1_MmcPosTransGsm2W
+ 0x10002e05 0x47 _L1_MmcPosTransTds2Gsm
+ 0x10002e4c 0x31 _L1_MmcPosTransGsm2Tds
+ 0x10002e7d 0x34 _L1_MmcLteTimePlus
+ 0x10002eb1 0x27 _L1_MmcWTimePlus
+ 0x10002ed8 0x27 _L1_MmcTdsTimePlus
+ 0x10002eff 0x33 _L1_MmcGsmTimePlus
+ 0x10002f32 0x6e _L1_MmcLteTimeMinus
+ 0x10002fa0 0x5c _L1_MmcWTimeMinus
+ 0x10002ffc 0x53 _L1_MmcTdsTimeMinus
+ 0x1000304f 0xa3 _L1_MmcGsmTimeMinus
+ 0x100030f2 0x2e _L1_MMcGsmPosMove
+ .text 0x10003120 0x24b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ 0x10003120 0x25 _L1_DrvL2CachePrefetchCfg
+ 0x10003145 0xa _L1_DrvL2CachePowerModeCfg
+ 0x1000314f 0x41 _L1_DrvL2CacheGetInfo
+ 0x10003190 0x4d _L1_DrvL2CacheEnable
+ 0x100031dd 0x18 _L1_DrvL2CacheDisable
+ 0x100031f5 0x11 _L1_DrvL2CacheSync
+ 0x10003206 0x27 _L1_DrvL2CacheClean
+ 0x1000322d 0x27 _L1_DrvL2CacheInv
+ 0x10003254 0x27 _L1_DrvL2CacheCleanInv
+ 0x1000327b 0x1d _L1_DrvL2CacheCleanByWay
+ 0x10003298 0x1d _L1_DrvL2CacheInvByWay
+ 0x100032b5 0x1d _L1_DrvL2CacheCleanInvByWay
+ 0x100032d2 0xd _L1_DrvL2CacheIntEnable
+ 0x100032df 0xe _L1_DrvL2CacheIntDisable
+ 0x100032ed 0xa _L1_DrvL2CacheGetMaskIntStatus
+ 0x100032f7 0xa _L1_DrvL2CacheClearIntStatus
+ 0x10003301 0x1e _L1_DrvL2CacheCfgEventCounter
+ 0x1000331f 0xa _L1_DrvL2CacheEventCounterEnable
+ 0x10003329 0x9 _L1_DrvL2CacheEventCounterDisable
+ 0x10003332 0x13 _L1_DrvL2CacheGetEventCounterVal
+ 0x10003345 0x1a _L1_DrvL2CacheTcmEnable
+ 0x1000335f 0xc _L1_DrvL2CacheTcmDisable
+ .text 0x1000336b 0x98 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ 0x1000336b 0x1b _L1_DrvCacheDisable
+ 0x10003386 0x3b _L1_DrvCacheEnable
+ 0x100033c1 0x24 _L1_DrvCacheWb
+ 0x100033e5 0x1e _L1_DrvCacheWbAll
+ .text 0x10003403 0x179 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ 0x10003403 0xb _L1_DrvDmaReset
+ 0x1000340e 0x15 _L1_DrvDmaCfg
+ 0x10003423 0x41 _L1_DrvDmaClear
+ 0x10003464 0x2 _L1_DrvDmaError
+ 0x10003466 0x41 _L1_DrvDmaInit
+ 0x100034a7 0x21 _L1_DrvDmaStart
+ 0x100034c8 0x26 _L1_DrvDmaIsr
+ 0x100034ee 0x4e _L1_DrvDmaCfgChParam
+ 0x1000353c 0x33 _L1_DrvDmaCfgLLI
+ 0x1000356f 0xd _L1_DrvDmaTcEnd
+ .text 0x1000357c 0x101a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x1000357c 0x1 _RPMSG_ERR
+ 0x1000357d 0x3e _rpMsg_MaskInt
+ 0x100035bb 0x40 _rpMsg_UnmaskInt
+ 0x100035fb 0x39 _rpMsg_GetIntState
+ 0x10003634 0x38 _rpMsg_ClearState
+ 0x1000366c 0xd2 _rpMsg_SetInt
+ 0x1000373e 0x184 _rpMsg_DispatchMsg
+ 0x100038c2 0xcc _zDrvRpMsg_CreateChannel
+ 0x1000398e 0x32 _zDrvRpMsg_RegCallBack
+ 0x100039c0 0xfa _zDrvRpMsg_Write
+ 0x10003aba 0x107 _zDrvRpMsg_WriteWithId
+ 0x10003bc1 0xd7 _zDrvRpMsg_WriteLockIrq
+ 0x10003c98 0x146 _zDrvRpMsg_Read
+ 0x10003dde 0x146 _zDrvRpMsg_ReadWithId
+ 0x10003f24 0xe1 _zDrvRpMsg_ReadWithIdLockIrq
+ 0x10004005 0xd8 _zDrvRpMsg_ReadLockIrq
+ 0x100040dd 0x23 _zDrvRpMsg_ChIsEmpty
+ 0x10004100 0x23 _zDrvRpMsg_WriteChIsEmpty
+ 0x10004123 0xd4 _zDrvRpMsg_CreateBlock
+ 0x100041f7 0xe _zDrvRpMsg_GetWriteAddrCnt
+ 0x10004205 0xa2 _zDrvRpMsg_GetWriteAddr
+ 0x100042a7 0xc8 _zDrvRpMsg_WriteUpdate
+ 0x1000436f 0xc4 _zDrvRpMsg_GetReadAddr
+ 0x10004433 0xbf _zDrvRpMsg_ReadUpdate
+ 0x100044f2 0xa4 _zDrvRpMsg_Initiate
+ .text 0x10004596 0x96 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ 0x10004596 0x1 _L1_Comm_SocTopInit
+ 0x10004597 0x1 _delay_1us
+ 0x10004598 0x26 _L1_LpmLatchInit
+ 0x100045be 0x8 _L1_RmHarqRamWcdmaCfg
+ 0x100045c6 0x8 _L1_RmHarqRamTdCfg
+ 0x100045ce 0x9 _L1_RmHarqRam3GRel
+ 0x100045d7 0x9 _L1e_RmHarqRamLteModeClkSelCfg
+ 0x100045e0 0xd _L1_TurboModeSel
+ 0x100045ed 0x1f _L1_WdTdIpSel
+ 0x1000460c 0x1f _L1_WdTdShareRamModeSel
+ 0x1000462b 0x1 _L1_PhyLteModemSel
+ .text 0x1000462c 0x878 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x1000464a 0x6e _L1_AtCmdCtrlLpcFuncs
+ 0x100046b8 0x2c _L1_InitSleepMacro
+ 0x100046e4 0x18 _L1_PhyModeExistInit
+ 0x100046fc 0x46 _L1_SocNoPsmInit
+ 0x10004742 0x14b _L1_SocLpcInit
+ 0x1000488d 0x71 _L1_PcuLpmCalibrationCfg
+ 0x100048fe 0x9 _L1_SocGetApCpuFreq
+ 0x10004907 0x9 _L1_SocGetPsCpuFreq
+ 0x10004910 0x10 _L1_SocGetCurCpuFreq
+ 0x10004920 0x10 _L1_SocGetCurAxiFreq
+ 0x10004930 0x2 _L1_SocGetCurDdrFreq
+ 0x10004932 0x2 _L1_SocDdrDfs
+ 0x10004934 0x17 _L1_SocResCpuExpUpdate
+ 0x1000494b 0x18 _L1_SocResAxiExpUpdate
+ 0x10004963 0x18 _L1_SocResVolExpUpdate
+ 0x1000497b 0x18 _L1_SocResDdrExpUpdate
+ 0x10004993 0x4e _L1_SocResGetExpCurrent
+ 0x100049e1 0xec _L1_SocAdjust
+ 0x10004acd 0x3d7 _L1_LpcTask
+ .text 0x10004ea4 0x20c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x10004ea4 0x10 _L1_LpcDrvChangeCpuPhyFreq
+ 0x10004eb4 0x12 _L1_SetPhyDeepSleepTime2Pcu
+ 0x10004ec6 0x1 _L1_DrvPcu2TpuClkCfg
+ 0x10004ec7 0x1 _L1_DrvPcuCalibrationCfg
+ 0x10004ec8 0x8 _L1_TdlpmClkEn
+ 0x10004ed0 0xa _L1_PhyAxiClkEn
+ 0x10004eda 0x4b _L1_RmModClkEn1
+ 0x10004f25 0x1 _L1_MatrixAxiAutoEn
+ 0x10004f26 0x3d _L1_CpuPhyWakeIntClear
+ 0x10004f63 0x1 _L1_DrvLpcIram1PhyInit
+ 0x10004f64 0x50 _L1_DrvLpcIramFlgInit
+ 0x10004fb4 0x8 _L1_SetPhyDeepSleepFlag
+ 0x10004fbc 0x13 _L1_L2CacheConfigLpMode
+ 0x10004fcf 0x9 _L1_PcuPhyPoweroffIntStart
+ 0x10004fd8 0x9 _L1_CrmSetZspAxiClkEn
+ 0x10004fe1 0x1 _L1_CopyRestartData
+ 0x10004fe2 0x1 _L1_PhyLowPowerInit
+ 0x10004fe3 0x8 _L1_DrvLpcRegLock
+ 0x10004feb 0xa _L1_DrvLpcRegUnLock
+ 0x10004ff5 0x8 _L1_DrvLpcSoftHwLock
+ 0x10004ffd 0xc _L1_DrvLpcSoftHwUnLock
+ 0x10005009 0x4e _L1_DrvLpcSpinSoftLockPsm
+ 0x10005057 0x4a _L1_DrvLpcSpinSoftUnlockPsm
+ 0x100050a1 0xf _L1_DrvLpcSpinSoftlockInit
+ .text 0x100050b0 0x2a4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x100050b2 0x37 _L1_IratSetMode
+ 0x100050e9 0x14 _L1_IratGetMode
+ 0x100050fd 0x13 _L1_IratRfProPcuShareDevInit
+ 0x10005110 0x11 _L1_IratRfProPcuShareDev
+ 0x10005121 0x1f _L1_IratRfIdleToSleep
+ 0x10005140 0x1d _L1_IratRfSleepToIdle
+ 0x1000515d 0x14 _L1_IratRfCfgFlgSet
+ 0x10005171 0x13 _L1_IratIsTdRfCfgNeed
+ 0x10005184 0x13 _L1_IratIsWdRfCfgNeed
+ 0x10005197 0x5b _L1_IratSetSlaveShortGapFlg
+ 0x100051f2 0xd _L1_IratSetGapRptIramFlg
+ 0x100051ff 0xf _L1_IratIsSharePwr
+ 0x1000520e 0x3a _L1_IratPwrCtrl
+ 0x10005248 0x5d _L1_IratLpcInit
+ 0x100052a5 0x2e _L1_IratLpcSleep
+ 0x100052d3 0xc _L1_IratLpcWakeup
+ 0x100052df 0x2b _L1_IratLpcSetCalibrationFlag
+ 0x1000530a 0x1d _L1_IratLpcGetCalibrationFlag
+ 0x10005327 0x18 _L1_IratLpcSetCalibrationTime
+ 0x1000533f 0x15 _L1_IratLpcGetCalibrationTime
+ .text 0x10005354 0x466 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x10005354 0x1 _L1_SysModClkSelInit
+ 0x10005355 0x10 _L1_PhyTimerClkDis
+ 0x10005365 0x11 _L1_Dma1ClkEn
+ 0x10005376 0x65 _L1_MatrixModemClkEn
+ 0x100053db 0xa _L1_DrvPhyCoreAcsCfg
+ 0x100053e5 0x1 _L1_DrvPwrTopRegCtrl
+ 0x100053e6 0x12 _L1_DrvPwrDomainIsOn
+ 0x100053f8 0x61 _L1_DrvPwrCtrl
+ 0x10005459 0x30 _L1_DrvLtePwr1Ctrl
+ 0x10005489 0x4 _L1_Drv3GSyncPwrCtrl
+ 0x1000548d 0x4 _L1_Drv3GDpaPwrCtrl
+ 0x10005491 0x1b _L1_DrvDpll245mClkCtrl
+ 0x100054ac 0x67 _L1_Dpll1Cfg
+ 0x10005513 0x74 _L1_Dpll2Cfg
+ 0x10005587 0x3c _L1_DpllCfg
+ 0x100055c3 0xad _L1_CpuPhyWakeIntInit
+ 0x10005670 0x2e _L1_PcuConfigPhyLpMode
+ 0x1000569e 0x19 _L1_PhyMgClkGating
+ 0x100056b7 0xd _L1_CpuPhyLpSvtAddr
+ 0x100056c4 0x36 _L1_DrvSetSharePwrUsedFlg
+ 0x100056fa 0x19 _L1_DrvGetSharePwrIsUsed
+ 0x10005713 0x18 _L1_DrvPhyComPwrUsedFlgInit
+ 0x1000572b 0x45 _L1_DrvSharePwrCtrl
+ 0x10005770 0x3f _L1_DrvLpcPwrCtrl
+ 0x100057af 0xb _L1_DrvLpcDdrPort1Ctrl
+ .text 0x100057ba 0x34f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_cpu_save_restore.o)
+ 0x100057ba 0x40 _L1_PhyDmaCfg
+ 0x100057fa 0xa _L1_SaveMgCrm
+ 0x10005804 0xa _L1_RestoreMgCrm
+ 0x1000580e 0xa _L1_SaveL2tcmByDma
+ 0x10005818 0xa _L1_RestoreL2tcmByDma
+ 0x10005822 0x33 _L1_SaveIcu
+ 0x10005855 0x33 _L1_RestoreIcu
+ 0x10005888 0x6 _L1_SaveInt
+ 0x1000588e 0x8 _L1_RestoreInt
+ 0x10005896 0x3 _L1_SaveSmodeReg
+ 0x10005899 0x3 _L1_RestoreSmodeReg
+ 0x1000589c 0x7d _L1_SavePl310
+ 0x10005919 0x87 _L1_RestorePl310
+ 0x100059a0 0x9f _L1_PhyPowerOffSaveContext
+ 0x10005a3f 0xca _L1_PhyPowerOffRestoreContext
+ .text 0x10005b09 0xf5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_wdt.o)
+ 0x10005b09 0x25 _L1_DrvWDTFeedDog
+ 0x10005b2e 0x4c _L1_DrvWDTInit
+ 0x10005b7a 0x50 _L1_DrvM02PhyIcpIsr
+ 0x10005bca 0x34 _L1_WdtTask
+ .text 0x10005bfe 0x66 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_uart.o)
+ 0x10005bfe 0x1a _serial_puts
+ 0x10005c18 0x4c _printk
+ .text 0x10005c64 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(iomemcpy_32.o)
+ 0x10005c6a 0x14 _iomemcpy_32
+ .text 0x10005c7e 0x2a1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l1cache.o)
+ 0x10005c7e 0x81 _L1_DrvL1CacheInit
+ 0x10005cff 0x46 _ZSP_DCacheSetExtraNonCacheableRegion_Ext
+ 0x10005d45 0x1b _ZSP_DCacheExtraNonCacheableEnable_Ext
+ 0x10005d60 0x1b _ZSP_DCacheExtraNonCacheableDisable_Ext
+ 0x10005d7b 0x35 _ZSP_DCacheExtraBufferableAndNonCacheableEnable_Ext
+ 0x10005db0 0x35 _ZSP_DCacheExtraBufferableAndNonCacheableDisable_Ext
+ 0x10005de5 0x13 _L1Cache_set_ramclk_gate
+ 0x10005df8 0xd _L1Cache_set_superfetch
+ 0x10005e05 0x15 _L1_DrvL1CacheEnableI
+ 0x10005e1a 0x15 _L1_DrvL1CacheEnableD
+ 0x10005e2f 0x8 _L1_DrvL1CacheEnable
+ 0x10005e37 0xf _L1_DrvL1CacheDisableI
+ 0x10005e46 0x26 _L1_DrvL1CacheDisableD
+ 0x10005e6c 0x8 _L1_DrvL1CacheDisable
+ 0x10005e74 0x21 _L1_DrvL1CacheCleanD
+ 0x10005e95 0x21 _L1_DrvL1CacheFlushD
+ 0x10005eb6 0x21 _L1_DrvL1CacheFlushI
+ 0x10005ed7 0x2d _L1_DrvL1CacheFlush
+ 0x10005f04 0x1b _L1_DrvL1CacheSetWT
+ .text 0x10005f1f 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_disableall.o)
+ 0x10005f1f 0x17 _ZSP_ICacheDisableAllWays
+ .text 0x10005f36 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enable.o)
+ 0x10005f36 0x17 _ZSP_ICacheEnable
+ .text 0x10005f4d 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_enableall.o)
+ 0x10005f4d 0x16 _ZSP_ICacheEnableAllWays
+ .text 0x10005f63 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_flush.o)
+ 0x10005f63 0x25 _ZSP_ICacheFlush
+ .text 0x10005f88 0x36 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_loadtcm.o)
+ 0x10005f88 0x36 _ZSP_ICacheLoadNCSRAM
+ .text 0x10005fbe 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_use_dcfgr_describe.o)
+ 0x10005fbe 0x16 _ZSP_ICacheUseICFGRDescribe
+ .text 0x10005fd4 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(idc_noncacheable_disable.o)
+ 0x10005fd4 0x12 _ZSP_ICacheNonCacheableDisable
+ .text 0x10005fe6 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_disableall.o)
+ 0x10005fe6 0x17 _ZSP_DCacheDisableAllWays
+ .text 0x10005ffd 0x16 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_enableall.o)
+ 0x10005ffd 0x16 _ZSP_DCacheEnableAllWays
+ .text 0x10006013 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_flush.o)
+ 0x10006013 0x25 _ZSP_DCacheFlush
+ .text 0x10006038 0x22 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_loadtcm.o)
+ 0x10006038 0x22 _ZSP_DCacheLoadNCSRAM
+ .text 0x1000605a 0x25 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_clean.o)
+ 0x1000605a 0x25 _ZSP_DCacheClean
+ .text 0x1000607f 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_setwritethruregion.o)
+ 0x1000607f 0x15 _ZSP_DCacheSetWriteThruRegion
+ .text 0x10006094 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writeallocate_enable.o)
+ 0x10006094 0x12 _ZSP_DCacheWriteAllocateEnable
+ .text 0x100060a6 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_enable.o)
+ 0x100060a6 0x12 _ZSP_DCacheWriteThruEnable
+ .text 0x100060b8 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_writethru_disable.o)
+ 0x100060b8 0x12 _ZSP_DCacheWriteThruDisable
+ .text 0x100060ca 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_noncacheable_enable.o)
+ 0x100060ca 0x12 _ZSP_DCacheNonCacheableEnable
+ .text 0x100060dc 0x13 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libzspcache.a(dc_extranoncacheable_enable.o)
+ 0x100060dc 0x13 _ZSP_DCacheExtraNonCacheableEnable
+ .text 0x100060ef 0x142 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x100060ef 0x54 _L1w_TaskPrioEng
+ 0x10006143 0xee _L1w_ModemDrvInit
+ .text 0x10006231 0x8e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x10006231 0x46 _L1w_AtNvInit
+ 0x10006277 0x48 _L1w_NvDataInit
+ .text 0x100062bf 0x13d5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_bch.o)
+ 0x100062bf 0x2e _L1w_DevBchBchSchedReq
+ 0x100062ed 0x2c _L1w_DevBchAfcSupplyReq
+ 0x10006319 0x26 _L1w_DevBchAfcLockCnf
+ 0x1000633f 0x2e _L1w_DevBchIntInd
+ 0x1000636d 0x3f _L1w_BchTask
+ 0x100063ac 0x45 _L1w_DevBchTimeDecrease
+ 0x100063f1 0xa _L1w_DevBchClearAfcInfo
+ 0x100063fb 0x1d _L1w_DevBchPiSymbol2Float
+ 0x10006418 0x53 _L1w_DevBchPiReset
+ 0x1000646b 0x3e _L1w_DevBchReset
+ 0x100064a9 0x35 _L1w_DevBchInit
+ 0x100064de 0x1f _L1w_DevBchTpuIntHandle
+ 0x100064fd 0x82 _L1w_DevBchPichSched
+ 0x1000657f 0x222 _L1w_DevBchPichRxCfg
+ 0x100067a1 0x97 _L1w_DevBchBchSched
+ 0x10006838 0x1b4 _L1w_DevBchBchRxCfg
+ 0x100069ec 0xa8 _L1w_DevBchAfcSupply
+ 0x10006a94 0xca _L1w_DevBchCpichRxCfg
+ 0x10006b5e 0x23 _L1w_DevBchAfcLockHandle
+ 0x10006b81 0x57 _L1w_DevBchPichIntHandle
+ 0x10006bd8 0xf8 _L1w_DevBchBchIntHandle
+ 0x10006cd0 0x80 _L1w_DevBchCpichIntHandle
+ 0x10006d50 0x24 _L1w_DevBchTimeConflict
+ 0x10006d74 0x56 _L1w_DevBchCalcFingerAdj
+ 0x10006dca 0x32 _L1w_DevBchCalcFingerBound
+ 0x10006dfc 0x6c _L1w_DevBchAddTpuEvent
+ 0x10006e68 0x7e _L1w_DevBchBchAfcProc
+ 0x10006ee6 0x54 _L1w_DevBchPichAfcProc
+ 0x10006f3a 0x14d _L1w_DevBchAdjustFinger
+ 0x10007087 0x2d _L1w_DevBchCpichIntMask
+ 0x100070b4 0x16 _L1w_DevBchClearAfcData
+ 0x100070ca 0xf _L1w_DevBchReadSfnResult
+ 0x100070d9 0x5c _L1w_DevBchFindBchRxCfgBuf
+ 0x10007135 0x5c _L1w_DevBchRtCfgTimeValid
+ 0x10007191 0x49 _L1w_DevBchPichIntPostProc
+ 0x100071da 0x15 _L1w_DevBchCalcFingerDist
+ 0x100071ef 0xc7 _L1w_DevBchSigProc
+ 0x100072b6 0x3a _L1w_DevBchCalcChipDist
+ 0x100072f0 0x25 _L1w_DevBchStopBchDecode
+ 0x10007315 0x7b _L1w_DevBchSetIQRotate
+ 0x10007390 0x26 _L1w_DevBchNCellAfcFeedback
+ 0x100073b6 0x60 _L1w_DevBchCaclRtSfnOffset
+ 0x10007416 0xcf _L1w_DevBchFingerManage
+ 0x100074e5 0x42 _L1w_DevBchFingerUpdate
+ 0x10007527 0x21 _L1w_DevBchStopBchDecodeReq
+ 0x10007548 0xe6 _L1w_DevBchPiaiAfcHandle
+ 0x1000762e 0x66 _L1w_DevBchFilterFinger
+ .text 0x10007694 0x2301 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x10007694 0x41 _L1w_DevMeasInit
+ 0x100076d5 0x41 _L1w_DevMeasReset
+ 0x10007716 0xd _L1w_DevMeasJudgeBufStateFull
+ 0x10007723 0xe _L1w_DevMeasJudgeBufState
+ 0x10007731 0x2cc _L1w_DevMeasConfigHw
+ 0x100079fd 0x40 _L1w_DevMeasCpichMeasCnf
+ 0x10007a3d 0x139 _L1w_DevMeasSideSupres
+ 0x10007b76 0x94 _L1w_DevMeasPathDetct
+ 0x10007c0a 0xd2 _L1w_DevMeasDeleteSttdDetctCell
+ 0x10007cdc 0xc1 _L1w_DevMeasSttdDetct
+ 0x10007d9d 0x4f _L1w_DevMeasCalcFingerPeakSum
+ 0x10007dec 0x5f _L1w_DevMeasCalcSearchWindowSum
+ 0x10007e4b 0x29 _L1w_DevMeasSortFirstFinger
+ 0x10007e74 0xd _L1w_DevMeasIsSearchWindowPath
+ 0x10007e81 0x25 _L1w_DevMeasSelNewWindow
+ 0x10007ea6 0xa8 _L1w_DevMeasSelWinFinInfo
+ 0x10007f4e 0xbe _L1w_DevMeasAdrWindowUpdate
+ 0x1000800c 0x104 _L1w_DevMeasTimeAdjust
+ 0x10008110 0x5f _L1w_DevMeasLOG10Cal
+ 0x1000816f 0x146 _L1w_DevMeasCalRssi
+ 0x100082b5 0x17a _L1w_DevMeasSaveCnfCellInfo
+ 0x1000842f 0x35 _L1w_DevMeasEcIoClaib
+ 0x10008464 0x104 _L1w_DevMeasGetRscpNew
+ 0x10008568 0xc0 _L1w_DevMeasGetRscp
+ 0x10008628 0x249 _L1w_DevMeasCalRscp1New
+ 0x10008871 0x2dd _L1w_DevMeasCalRscp1
+ 0x10008b4e 0xed _L1w_DevMeasPreSyncFingerCmp
+ 0x10008c3b 0xee _L1w_DevMeasAddPreSyncFingernew
+ 0x10008d29 0x14d _L1w_DevMeasAddPreSyncFinger
+ 0x10008e76 0x2f _L1w_DevMeasSetPreSyncInfo
+ 0x10008ea5 0x4 _L1w_DevMeasPreSyncHandler
+ 0x10008ea9 0x134 _L1w_DevMeasRscpHandler
+ 0x10008fdd 0x25 _L1w_DevMeasIntMissHandle
+ 0x10009002 0xb2 _L1w_DevMeasGetTpuEvtTim
+ 0x100090b4 0x50 _L1w_DevMeasSetAbnormalIntInfo
+ 0x10009104 0x1b6 _L1w_DevMeasReqProc
+ 0x100092ba 0x216 _L1w_DevMeasIntProc
+ 0x100094d0 0x62 _L1w_DevMeasTpuHandler
+ 0x10009532 0x48 _L1w_DevMeasIntInd
+ 0x1000957a 0x33 _L1w_DevMeasGetPreSyncInfo
+ 0x100095ad 0xf _L1w_DevMeasCheckWorkSt
+ 0x100095bc 0xe7 _L1w_DevMeasSetAgcStartTime
+ 0x100096a3 0x3e _L1w_DevMeasAgcTrans
+ 0x100096e1 0x2d _L1w_DevMeasSetAgc
+ 0x1000970e 0x18 _L1w_DevMeasOfflinedataStartTime
+ 0x10009726 0xc _L1w_DevMeasGetOfflinedataEndtTime
+ 0x10009732 0x2d _L1w_DevMeasOfflinedataSavedReq
+ 0x1000975f 0xe7 _L1w_DevMeasCfgOfflineData
+ 0x10009846 0x15 _L1w_DevMeasSaveAgcValue
+ 0x1000985b 0x16 _L1w_DevMeasSaveAgcStartTime
+ 0x10009871 0x63 _L1w_DevMeasJugeIsSaveAgcInfo
+ 0x100098d4 0xe _L1w_DevMeasClearOfflineDataInfo
+ 0x100098e2 0xb3 _L1w_MeasTask
+ .text 0x10009995 0x2bc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x10009995 0x8 _L1w_DevHsdpaActiveFlgGet
+ 0x1000999d 0x8 _L1w_DevHsdpaActiveFlgSet
+ 0x100099a5 0x8 _L1w_DevHsdpaHdtrUseTurboFlgGet
+ 0x100099ad 0x8 _L1w_DevHsdpaHdtrUseTurboFlgSet
+ 0x100099b5 0x8 _L1w_DevHsdpaGetAgcDownFlg
+ 0x100099bd 0x7 _L1w_DevHspaFachSetEdchActive
+ 0x100099c4 0x7 _L1w_DevHspaFachGetEdchActive
+ 0x100099cb 0x18 _L1w_DevHspaFachSubFrmInt
+ 0x100099e3 0x47 _L1w_DevHspaReset
+ 0x10009a2a 0x3e _L1w_DevHspaInit
+ 0x10009a68 0x18 _L1w_DevHspaCmnMsgProc
+ 0x10009a80 0x3c _L1w_DevHsupaFachMsgProc
+ 0x10009abc 0x4a _L1w_DevHsdpaFachMsgProc
+ 0x10009b06 0x5e _L1w_DevHsupaMsgProc
+ 0x10009b64 0x83 _L1w_DevHsdpaMsgProc
+ 0x10009be7 0x6a _L1w_HspaTask
+ .text 0x10009c51 0x951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx.o)
+ 0x10009c51 0x15 _L1w_DevRtxReset
+ 0x10009c66 0xf _L1w_DevRtxInit
+ 0x10009c75 0x44 _L1w_DevRtxInitCfgMsgHandle
+ 0x10009cb9 0x1 _L1w_DevRtxTxRfOperate
+ 0x10009cba 0x95 _L1w_DevRtxRxCfgTpuIntHandle
+ 0x10009d4f 0xce _L1w_DevRtxTpuIntUlRfHandle
+ 0x10009e1d 0xfa _L1w_DevRtxTpuIntHandle
+ 0x10009f17 0x24 _L1w_DevRtxResetInd
+ 0x10009f3b 0x24 _L1w_DevRtxInitInd
+ 0x10009f5f 0x21 _L1w_DevRtxTxPrachAbortReq
+ 0x10009f80 0x1 _L1w_DevRtxTxDpcchOfHspaCfgReq
+ 0x10009f81 0x48 _L1w_DevRtxUlRfCtrlSendReq
+ 0x10009fc9 0x2c _L1w_DevRtxRxFingerCfgReq
+ 0x10009ff5 0x32 _L1w_DevRtxRxPchCfgReq
+ 0x1000a027 0x21 _L1w_DevRtxRxAichRelReq
+ 0x1000a048 0x31 _L1w_DevRtxRxFachCfgReq
+ 0x1000a079 0x21 _L1w_DevRtxRxFachRelReq
+ 0x1000a09a 0x2f _L1w_DevRtxRxDlCmCfgReq
+ 0x1000a0c9 0x21 _L1w_DevRtxRxDlCmAbortReq
+ 0x1000a0ea 0x2d _L1w_DevRtxRxHsscchCfgReq
+ 0x1000a117 0x2f _L1w_DevRtxRxEagchCfgReq
+ 0x1000a146 0x21 _L1w_DevRtxRxEagchRelReq
+ 0x1000a167 0x35 _L1w_DevRtxRxDrxUpdateReq
+ 0x1000a19c 0x2a _L1w_DevRtxRxPlusCpichCfgReq
+ 0x1000a1c6 0x26 _L1w_DevRtxRxPlusCpichRelReq
+ 0x1000a1ec 0x2e _L1w_DevRtxRxRgHiCfgReq
+ 0x1000a21a 0x21 _L1w_DevRtxRxRgHiRelReq
+ 0x1000a23b 0x21 _L1w_DevRtxTxTimingAdjustInd
+ 0x1000a25c 0x19 _L1w_DevRtxRxTpcPilotIntInd
+ 0x1000a275 0x18 _L1w_DevRtxRxHwTpcPlIntInd
+ 0x1000a28d 0x2f _L1w_DevRtxRxHwPiAiIntInd
+ 0x1000a2bc 0x9 _L1w_DevRtxRxHwRakeIntInd
+ 0x1000a2c5 0x1a _L1w_DevRtxRxHwDtrIntInd
+ 0x1000a2df 0x22 _L1w_DevRtxRxPichIntInd
+ 0x1000a301 0x22 _L1w_DevRtxRxAichIntInd
+ 0x1000a323 0x102 _L1w_DevRtxRxTpcIntInd
+ 0x1000a425 0x3e _L1w_DevRtxRxTpcIntReq
+ 0x1000a463 0x66 _L1w_DevRtxRxPilotIntInd
+ 0x1000a4c9 0x21 _L1w_DevRtxRxTfciIntInd
+ 0x1000a4ea 0x22 _L1w_DevRtxRxTtiIntInd
+ 0x1000a50c 0x21 _L1w_DevRtxRxAgchFactorIntInd
+ 0x1000a52d 0x1 _L1w_DevRtxErrHandle
+ 0x1000a52e 0x6 _L1w_DevRtxInfoGet
+ 0x1000a534 0x6e _L1w_RtxTask
+ .text 0x1000a5a2 0x152c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x1000a5a2 0x49 _L1w_DevRfcAtSetDebug
+ 0x1000a5eb 0x5 _L1w_DevRfcGetAfcHz
+ 0x1000a5f0 0x1 _L1w_DevRfcRbdpRegCfg
+ 0x1000a5f1 0x6a _L1w_DevRfcReadMrtr
+ 0x1000a65b 0x2a _L1w_DevRfSleepInfo
+ 0x1000a685 0xc7 _L1w_DevRfcReset
+ 0x1000a74c 0x29 _L1w_DevRfcInit
+ 0x1000a775 0x8f _L1w_NvDataCheck
+ 0x1000a804 0x24 _L1w_DevRfcResetCnf
+ 0x1000a828 0x24 _L1w_DevRfcInitCnf
+ 0x1000a84c 0x53 _L1w_DevRfcSchedOpenReq
+ 0x1000a89f 0x23 _L1w_DevRestoreReq
+ 0x1000a8c2 0x2e _L1w_DevRfcIntInd
+ 0x1000a8f0 0x34 _L1w_DevRfcDpaInfoCtrl
+ 0x1000a924 0x30 _L1w_DevRfcAntExchange
+ 0x1000a954 0x2c _L1w_DevRfcAntSel
+ 0x1000a980 0x5e _L1w_DevRfcDiversityCtrl
+ 0x1000a9de 0x35 _L1w_DevRfcChgeInfoCtrlTx
+ 0x1000aa13 0x82 _L1w_DevRfcNotchHandle
+ 0x1000aa95 0xfd _L1w_DevRfcChgeInfoCtrlRx
+ 0x1000ab92 0x21 _L1W_DevRfcWaitForRfClose
+ 0x1000abb3 0xa6 _L1W_DevRfcSoltCtrlRfClose
+ 0x1000ac59 0x71 _L1w_DevRfcSlotCtrl
+ 0x1000acca 0xc6 _L1w_DevRfcFdtTrigCtrl
+ 0x1000ad90 0x56 _L1w_DevRfcFdtGetAgc
+ 0x1000ade6 0xbc _L1w_DevRfcFdtFreqCtrl
+ 0x1000aea2 0x67 _L1w_DevRfcFdtApcCwPaHighCtrl
+ 0x1000af09 0x6e _L1w_DevRfcFdtApcCwPaLowCtrl
+ 0x1000af77 0x67 _L1w_DevRfcFdtStartCtrl
+ 0x1000afde 0x91 _L1w_DevRfcNstTRXOpenCtrl
+ 0x1000b06f 0x42 _L1w_DevRfcNstTRXCloseCtrl
+ 0x1000b0b1 0x6a _L1w_DevRfcNstTRXFreqChge
+ 0x1000b11b 0x52 _L1w_DevRfcAmtCtrl
+ 0x1000b16d 0x46 _L1w_DevRfcAgcRefPowLogUpdate
+ 0x1000b1b3 0x29 _L1w_DevRfcIntTimeLogUpdate
+ 0x1000b1dc 0x19 _L1w_DevRfcMrtrConfLogUpdate
+ 0x1000b1f5 0x91 _L1w_DevRfcAgcRxStateLogUpdate
+ 0x1000b286 0x8 _L1w_DevRfcTempDacToIram
+ 0x1000b28e 0x31 _L1w_DevRfcIntLogUpdate
+ 0x1000b2bf 0x25 _L1w_DevRfcIntAgcDcCalc
+ 0x1000b2e4 0x2f _L1w_DevRfcIntNotchCfg
+ 0x1000b313 0x48 _L1w_DevRfc_RpiCfg
+ 0x1000b35b 0x18 _L1w_DevRfc_RpiSet
+ 0x1000b373 0x56 _L1w_DevRfc_RpiPwrCtrl
+ 0x1000b3c9 0x5e _L1w_DevRfcIntAgcDcSet
+ 0x1000b427 0x25 _L1w_DevRfcIntAfcSet
+ 0x1000b44c 0x63 _L1w_DevRfcRfRegReadCtrl
+ 0x1000b4af 0x2b _L1w_DevRfcSleepStatusSet
+ 0x1000b4da 0x6b _L1w_DevRfcIntProc
+ 0x1000b545 0x45 _L1w_DevRfcSetTxBandMaxPwr
+ 0x1000b58a 0x8f _L1w_DevRfcTxPowerSet
+ 0x1000b619 0x3f _L1w_DevRfcAfcHz2PPM
+ 0x1000b658 0x4d _L1w_DevRfcPpm2Hz
+ 0x1000b6a5 0x50 _L1w_DevRfcAfcUpdate
+ 0x1000b6f5 0x1c _L1w_DevRfcOpenCtrl
+ 0x1000b711 0x33 _L1w_DevRfcReusedReSourceRestore
+ 0x1000b744 0x1 _L1w_DevRfcTxTestMode
+ 0x1000b745 0x389 _L1w_RfcTask
+ .text 0x1000bace 0x1c63 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x1000bace 0x1f _L1w_DevPcDpchReset
+ 0x1000baed 0x1 _L1w_DevPcDpchInit
+ 0x1000baee 0x94 _L1w_DevPcDpcchPowerFilter
+ 0x1000bb82 0x38 _L1w_DevPcDeltaPilotPro
+ 0x1000bbba 0x28 _L1w_DevPcPowerItpPro
+ 0x1000bbe2 0x1c _L1w_DevPcGapTpcJudge
+ 0x1000bbfe 0x4b _L1w_DevPcCmPowerPro
+ 0x1000bc49 0x60 _L1w_DevPcDpcchPowerCalc
+ 0x1000bca9 0x40 _L1w_DevPcDeltaPilotPowerCalc
+ 0x1000bce9 0x3c _L1w_DevPcDeltaResumeCalc
+ 0x1000bd25 0x3c _L1w_DevPcRppPowerCalc
+ 0x1000bd61 0x59 _L1w_DevPcGetDeltaPilotCalcMode
+ 0x1000bdba 0x2a _L1w_DevPcSigmaLastCalc
+ 0x1000bde4 0xe0 _L1w_DevPcAjCalc
+ 0x1000bec4 0x5d _L1w_DevPcFindNearBeltaC
+ 0x1000bf21 0x6b _L1w_DevPcFindNearBeltaD
+ 0x1000bf8c 0x47 _L1w_DevPcAjToBelta
+ 0x1000bfd3 0x11 _L1w_DevPcDpchCurTfciBeltaCD
+ 0x1000bfe4 0x1f5 _L1w_DevPcBeltaCBeltaDCalc
+ 0x1000c1d9 0xf0 _L1w_DevPcBeltaCBeltaDUpdate
+ 0x1000c2c9 0xcc _L1w_DevPcSecCmBetalUpd
+ 0x1000c395 0x18 _L1w_DlIlpc_reset
+ 0x1000c3ad 0x8 _L1w_Olpc_reset
+ 0x1000c3b5 0x10 _L1w_DevPcOlpcCntReset
+ 0x1000c3c5 0xf _L1w_DevPcTpcGenReset
+ 0x1000c3d4 0xc _L1w_DevPcWindupReset
+ 0x1000c3e0 0x42 _L1w_DevPcDlSirCmAdjust
+ 0x1000c422 0x90 _L1w_DevPcDlSirTargetCalc
+ 0x1000c4b2 0xec _L1w_DevPcFdpchSirCal
+ 0x1000c59e 0x111 _L1w_DevPcDpchSirCal
+ 0x1000c6af 0x49 _L1w_DevPcDlWindUpMode
+ 0x1000c6f8 0x3c _L1w_DevPcSirSfAdjust
+ 0x1000c734 0x95 _L1w_DevPcTpcGenDpcMode1
+ 0x1000c7c9 0xd4 _L1w_DevPcDlTpcCmdGen
+ 0x1000c89d 0x26 _L1w_DevFdpchRscpCalc
+ 0x1000c8c3 0x37 _L1w_DevDpchParaECal
+ 0x1000c8fa 0x88 _L1w_DevDpchRscpCalc
+ 0x1000c982 0x9a _L1w_DevPcPilotIntInd
+ 0x1000ca1c 0x75 _L1w_DevPcRlsSetStaticAndSirThJudge
+ 0x1000ca91 0xb2 _L1w_DevPcSetTpcSoftBit
+ 0x1000cb43 0xc5 _L1w_DevPcTpcCombine
+ 0x1000cc08 0x14 _L1w_DevPcTpcSingleRlPca1Calc
+ 0x1000cc1c 0x11 _L1w_DevPcTpcSingleRlPca2Calc
+ 0x1000cc2d 0x89 _L1w_DevPcTpcMultiRlsPca1Calc
+ 0x1000ccb6 0x51 _L1w_DevPcTpcMultiRlsPca2Calc
+ 0x1000cd07 0x46 _L1w_DevPcTpcSingleRlCombine
+ 0x1000cd4d 0x4d _L1w_DevPcTpcMultiRlCombine
+ 0x1000cd9a 0x7e _L1w_DevPcTpcMultiRlsCombine
+ 0x1000ce18 0x18 _L1w_DevPcSirReset
+ 0x1000ce30 0x5 _L1w_DevPcBetalSeqalCal
+ 0x1000ce35 0x58 _L1w_DevPcCurSlotPowCalc
+ 0x1000ce8d 0x1f _L1w_DevPcIsOverPwr
+ 0x1000ceac 0x2a _L1w_DevPcSerachTfci
+ 0x1000ced6 0x31 _L1w_DevPcCurSlotOverPowProc
+ 0x1000cf07 0x40 _L1w_DevPcMaxPowerUpdate
+ 0x1000cf47 0xf _L1w_DevPcUlTfcOverEstCmp
+ 0x1000cf56 0xe9 _L1w_DevPcUlTfcOverEstRlt
+ 0x1000d03f 0x22 _L1w_DevPcUphFrmAvrCalc
+ 0x1000d061 0x5 _L1w_DevPcUphMapRep
+ 0x1000d066 0x32 _L1w_DevPcUphResult
+ 0x1000d098 0x8 _L1w_DevPcGetUphValue
+ 0x1000d0a0 0xab _L1w_DevPcUphProc
+ 0x1000d14b 0x91 _L1w_DevPcCfgInfoUpd
+ 0x1000d1dc 0x83 _L1w_DevPcDchInfoGet
+ 0x1000d25f 0x1e _L1w_DevDchOlpcBlerTargetMapping
+ 0x1000d27d 0x8f _L1w_DevPcDchOlpcThParamGet
+ 0x1000d30c 0x59 _L1w_DevPcEfachBeltacCal
+ 0x1000d365 0x104 _L1w_DevPcDchStartReqHandle
+ 0x1000d469 0x1a _L1w_DevPcUldpchTfciInfoHandle
+ 0x1000d483 0x27 _L1w_DevPcFDpchOutLoopAdj
+ 0x1000d4aa 0x55 _L1w_DevPcDpchOutLoopAdj
+ 0x1000d4ff 0x69 _L1w_DevPcDlRefTrchSel
+ 0x1000d568 0x68 _L1w_DevPcOlpcInit
+ 0x1000d5d0 0x3f _L1w_DevPcDtrBlerInfoHandle
+ 0x1000d60f 0x14 _L1w_DevPcTpcBerCal
+ 0x1000d623 0x27 _L1w_DevPcRlsTpcBerPro
+ 0x1000d64a 0x7e _L1w_DevPcMutlRlsTpcBerCal
+ 0x1000d6c8 0x33 _L1w_DevPcTpcBerCtr
+ 0x1000d6fb 0x36 _L1w_DevPcOlpcCtrl
+ .text 0x1000d731 0x1bca T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x1000d731 0x64 _L1w_DevHsdpaStartPc
+ 0x1000d795 0x27 _L1w_DevHspdaHwReset
+ 0x1000d7bc 0x1b _L1w_DevHsdpaHwInit
+ 0x1000d7d7 0xa3 _L1w_DevHsdpaReset
+ 0x1000d87a 0x1 _L1w_DevHsdpaNvInit
+ 0x1000d87b 0x10d _L1w_DevHsdpaParaInit
+ 0x1000d988 0x187 _L1w_DevHsdpaRegTpuEvent
+ 0x1000db0f 0x1ac _L1w_DevHsdpaCfgProc
+ 0x1000dcbb 0x6e _L1w_DevHsdpaRelProc
+ 0x1000dd29 0xc4 _L1w_DevHsdpaIcSymModProc
+ 0x1000dded 0xa1 _L1w_DevHsdpaAdrCirIntProc
+ 0x1000de8e 0xeb _L1w_DevHsdpaAdrCpichIntProc
+ 0x1000df79 0x30 _L1w_DevHsdpaHsscchPart1IntProc
+ 0x1000dfa9 0x4d _L1w_DevHsdpaHsscchPart2IntProc
+ 0x1000dff6 0x30 _L1w_DevHsdpaHdtrIntProc
+ 0x1000e026 0x3a _L1w_DevHsdpaCfn2SfnTime
+ 0x1000e060 0x37 _L1w_DevHsdpaOrderActProc
+ 0x1000e097 0x152 _L1w_DevHsdpaDchTpuProc
+ 0x1000e1e9 0x42f _L1w_DevHsdpaTpuTraceLog
+ 0x1000e618 0xfb _L1w_DevHsdpaIsJudgechangjing3
+ 0x1000e713 0xe0 _L1w_DevHsdpaTpuProc
+ 0x1000e7f3 0xb4 _L1w_DevHsdpaCompareCellInfo
+ 0x1000e8a7 0x173 _L1w_DevHsdpaIsJudgePsrOver512
+ 0x1000ea1a 0x105 _L1w_DevHsdpaPsrOver512
+ 0x1000eb1f 0x2a _L1w_DevHsdpaPsrFingerOldDaNew
+ 0x1000eb49 0x2a _L1w_DevHsdpaPsrFingerNewXiaoOld
+ 0x1000eb73 0xea _L1w_DevHsdpaPsrIschangjing3
+ 0x1000ec5d 0x1d0 _L1w_DevHsdpaTxTpuProc
+ 0x1000ee2d 0x56 _L1w_DevHsdpaPsrUpdateProc
+ 0x1000ee83 0x3f _L1w_DevHsdpaCmUpdateProc
+ 0x1000eec2 0x4a _L1w_DevHsdpaCfgReq
+ 0x1000ef0c 0x29 _L1w_DevHsdpaRelReq
+ 0x1000ef35 0x29 _L1w_DevHsdpaIcSymModIntInd
+ 0x1000ef5e 0x29 _L1w_DevHsdpaAdrCirIntInd
+ 0x1000ef87 0x29 _L1w_DevHsdpaAdrCpichIntInd
+ 0x1000efb0 0x29 _L1w_DevHsdpaHsscchPart1IntInd
+ 0x1000efd9 0x29 _L1w_DevHsdpaHsscchPart2IntInd
+ 0x1000f002 0x29 _L1w_DevHsdpaHdtrIntInd
+ 0x1000f02b 0x3b _L1w_DevDlsHsdpaPsrUpdateReq
+ 0x1000f066 0x35 _L1w_DevHsdpaCmUpdateReq
+ 0x1000f09b 0x3b _L1w_DevHsdpaHsscchOrdInd
+ 0x1000f0d6 0x4c _L1w_DevHsdpaFachCfgReq
+ 0x1000f122 0x26 _L1w_DevHsdpaFachRelReq
+ 0x1000f148 0x29 _L1w_DevHsdpaFachRcvReq
+ 0x1000f171 0x26 _L1w_DevHsdpaFachHrntiUpdateReq
+ 0x1000f197 0x21 _L1w_DevHsdpaFachDataInd
+ 0x1000f1b8 0x4b _L1w_DevHsdpaPchCfgReq
+ 0x1000f203 0x21 _L1w_DevHsdpaPchRelReq
+ 0x1000f224 0x26 _L1w_DevHsdpaRtxPiInd
+ 0x1000f24a 0x28 _L1w_DevHsdpaDmaIntInd
+ 0x1000f272 0x39 _L1w_DevHsdpaDataDmaCpy
+ 0x1000f2ab 0x24 _L1w_DevHsdpaCurTime2SfnTime
+ 0x1000f2cf 0x2c _L1w_DevHsdpaGetCurSfnTime
+ .text 0x1000f2fb 0x16ff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x1000f2fb 0x20 _L1w_DevHsdpaLessIsAct
+ 0x1000f31b 0xa5 _L1w_DevHsdpaLessParaInit
+ 0x1000f3c0 0x2f _L1w_DevHsdpaLessOrdIndProc
+ 0x1000f3ef 0x33 _L1w_DevHsdpaLessTimeRcd
+ 0x1000f422 0x5f _L1w_DevHsdpaLessCfgTraceLog
+ 0x1000f481 0xc _L1w_DevHsdpaLessCfgAllTb
+ 0x1000f48d 0x23 _L1w_DevHsdpaLessFindIdleHarq
+ 0x1000f4b0 0x231 _L1w_DevHsdpaPart2Type2Proc
+ 0x1000f6e1 0xc5 _L1w_DevHsdpaDchLessProc
+ 0x1000f7a6 0x7e _L1w_DevHsdpaPart2LessProc
+ 0x1000f824 0x23 _L1w_DevHsdpaIsLessValid
+ 0x1000f847 0x18 _L1w_DevHsdpaLessFindHsdschTti
+ 0x1000f85f 0x1c9 _L1w_DevHsdpaDchLessHdtrIntProc
+ 0x1000fa28 0x24 _L1w_DevHsdpaLessHdtrIntProc
+ 0x1000fa4c 0x6b _L1w_DevHsdpaPchSaveAdrInitCfg
+ 0x1000fab7 0x51 _L1w_DevHsdpaPchSaveHsscchInitCfg
+ 0x1000fb08 0x7d _L1w_DevHsdpaPchRxInitRcvProc
+ 0x1000fb85 0xae _L1w_DevHsdpaPchSaveLessPara
+ 0x1000fc33 0x8e _L1w_DevHsdpaPchSaveAdrSubFrmCfg
+ 0x1000fcc1 0x42 _L1w_DevHsdpaPchSaveIcPsrCfg
+ 0x1000fd03 0x9a _L1w_DevHsdpaPchRxSubFrmProc
+ 0x1000fd9d 0x5f _L1w_DevHsdpaPchCfgProc
+ 0x1000fdfc 0x2d _L1w_DevHsdpaPchRelProc
+ 0x1000fe29 0x18 _L1w_DevHsdpaPchTpuProc
+ 0x1000fe41 0x62 _L1w_DevHsdpaPchSavePart1IntCfg
+ 0x1000fea3 0x66 _L1w_DevHsdpaPchPart2Type1Proc
+ 0x1000ff09 0x12d _L1w_DevHsdpaPchHdtrIntProc
+ 0x10010036 0x92 _L1w_DevHsdpaPchLessProc
+ 0x100100c8 0x16d _L1w_DevHsdpaPchLessHdtrIntProc
+ 0x10010235 0xa1 _L1w_DevHsdpaRtxPiIndProc
+ 0x100102d6 0x71 _L1w_DevHsdpaFachStartPc
+ 0x10010347 0x4e _L1w_DevHsdpaFachSaveHsdpcchAckCfg
+ 0x10010395 0x5c _L1w_DevHsdpaFachSaveHsdpcchCqiCfg
+ 0x100103f1 0x4d _L1w_DevHsdpaFachCqiSendCtrl
+ 0x1001043e 0x6e _L1w_DevHsdpaFachSaveAdrInitCfg
+ 0x100104ac 0x4a _L1w_DevHsdpaFachSaveHsscchInitCfg
+ 0x100104f6 0x52 _L1w_DevHsdpaFachRxInitRcvProc
+ 0x10010548 0x2e _L1w_DevHsdpaFachTxInitSendProc
+ 0x10010576 0x81 _L1w_DevHsdpaFachSaveAdrSubFrmCfg
+ 0x100105f7 0x83 _L1w_DevHsdpaFachRxSubFrmProc
+ 0x1001067a 0x56 _L1w_DevHsdpaFachTxSubFrmProc
+ 0x100106d0 0x68 _L1w_DevHsdpaFachCfgProc
+ 0x10010738 0x44 _L1w_DevHsdpaFachRelProc
+ 0x1001077c 0x22 _L1w_DevHsdpaFachTpuProc
+ 0x1001079e 0x2e _L1w_DevHsdpaFachSavePart1IntCfg
+ 0x100107cc 0x131 _L1w_DevHsdpaFachHdtrIntProc
+ 0x100108fd 0x3c _L1w_DevHsdpaFachRcvProc
+ 0x10010939 0x28 _L1w_DevHsdpaFachHrntiUpdateProc
+ 0x10010961 0x79 _L1w_DevHsdpaFachEdchIndProc
+ 0x100109da 0x20 _L1w_DevHsdpaFachSetHsdpcchFlg
+ .text 0x100109fa 0x1019 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_cfg.o)
+ 0x100109fa 0x60 _L1w_DevRtxRxFingerCfg
+ 0x10010a5a 0xe2 _L1w_DevRtxRxCpichCfg
+ 0x10010b3c 0x4f _L1w_DevRtxRxPichCfg
+ 0x10010b8b 0x12 _L1w_DevRtxRxPichRel
+ 0x10010b9d 0x50 _L1w_DevRtxRxPchCfg
+ 0x10010bed 0x24 _L1w_DevRtxRxPchRel
+ 0x10010c11 0x2f _L1w_DevRtxRxAichRakeCfg
+ 0x10010c40 0x26 _L1w_DevRtxRxAichCfg
+ 0x10010c66 0x5 _L1w_DevRtxRxAichRel
+ 0x10010c6b 0x2e _L1w_DevRtxRxFachRakeCfg
+ 0x10010c99 0x46 _L1w_DevRtxRxFachCfg
+ 0x10010cdf 0x21 _L1w_DevRtxRxFachRel
+ 0x10010d00 0xa5 _L1w_DevRtxRxDlDpchRakeCfg
+ 0x10010da5 0x40 _L1w_DevRtxRxDlDpchCfg
+ 0x10010de5 0x26 _L1w_DrvDpramRxWriteClearData
+ 0x10010e0b 0x39 _L1w_DevRtxRxDlDpchRel
+ 0x10010e44 0x16d _L1w_DevRtxRxDlCmSlotCfg
+ 0x10010fb1 0xe5 _L1w_DevRtxRxDlCmSlotRel
+ 0x10011096 0x63 _L1w_DevRtxRxDlCmCfgTpuIntHandle
+ 0x100110f9 0x1ff _L1w_DevRtxRxDlCmCfg
+ 0x100112f8 0x6f _L1w_DevRtxRxFdpchRakeCfg
+ 0x10011367 0x3d _L1w_DevRtxRxFdpchCfg
+ 0x100113a4 0x5 _L1w_DevRtxRxFdpchRel
+ 0x100113a9 0x34 _L1w_DevRtxRxHsscchRakeCfg
+ 0x100113dd 0x39 _L1w_DevRtxRxHsscchCfg
+ 0x10011416 0x5 _L1w_DevRtxRxHsscchRel
+ 0x1001141b 0x38 _L1w_DevRtxRxEagchRakeCfg
+ 0x10011453 0x34 _L1w_DevRtxRxEagchCfg
+ 0x10011487 0xf _L1w_DevRtxRxEagchRel
+ 0x10011496 0xbc _L1w_DevRtxRxRgHiRakeCfg
+ 0x10011552 0x4b _L1w_DevRtxRxRgHiCfg
+ 0x1001159d 0x5 _L1w_DevRtxRxRgHiRel
+ 0x100115a2 0x6b _L1w_DevRtxRxCctrchCfgHandle
+ 0x1001160d 0x11b _L1w_DevRtxRxCfgHandle
+ 0x10011728 0x2f _L1w_DevRtxRxDlTpcPlCfg
+ 0x10011757 0x7e _L1w_DevRtxRxIntFingerCfg
+ 0x100117d5 0x69 _L1w_DevRtxRxIntCfg
+ 0x1001183e 0x6e _L1w_DevRtxRxDpchSlotForm
+ 0x100118ac 0x71 _L1w_DevRtxRxSccpchSlotForm
+ 0x1001191d 0x5a _L1w_DevRtxRxComparaSlotForm
+ 0x10011977 0x34 _L1w_DevRtxRxCmASlotForm
+ 0x100119ab 0x34 _L1w_DevRtxRxCmBSlotForm
+ 0x100119df 0x34 _L1w_DevRtxRxNormalSlotForm
+ .text 0x10011a13 0x92c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x10011a13 0x13 _L1w_DevRtxTimeCmp
+ 0x10011a26 0x2d _L1w_DevRtxUlRfcReq
+ 0x10011a53 0x37 _L1w_DevRtxUlRfTblInit
+ 0x10011a8a 0x2f _L1w_DevRtxUlRfGetNodeFromUnusedQ
+ 0x10011ab9 0x17 _L1w_DevRtxUlRfPutNode2UnusedQ
+ 0x10011ad0 0x31 _L1w_DevRtxUlRfQueueInsert
+ 0x10011b01 0x41 _L1w_DevRtxUlRfQueueGet
+ 0x10011b42 0xf _L1w_DevRtxUlRfQueueSearch
+ 0x10011b51 0x67 _L1w_DevRtxUlRfStartSched
+ 0x10011bb8 0x262 _L1w_DevRtxUlRfCtrlReq
+ 0x10011e1a 0x1de _L1w_DevRtxUlRfSchedPick
+ 0x10011ff8 0x81 _L1w_DevRtxUlRfSchedLink
+ 0x10012079 0x12f _L1w_DevRtxUlRfSchedMerge
+ 0x100121a8 0x18a _L1w_DevRtxUlRfSched
+ 0x10012332 0xd _L1w_DevRtxUlRfStopSched
+ .text 0x1001233f 0xf38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x1001233f 0x7 _L1w_DevTxGetDchState
+ 0x10012346 0x11 _L1w_DevTxGetRfCtrlPara
+ 0x10012357 0x15 _L1w_DevTxDchReset
+ 0x1001236c 0x39 _L1w_DevTxOpenRfc
+ 0x100123a5 0x39 _L1w_DevTxCloseRfc
+ 0x100123de 0x68 _L1w_DevTxCmRfcCfg
+ 0x10012446 0x50 _L1w_DevTxNormalSlotForm
+ 0x10012496 0x5e _L1w_DevTxCmSlotForm
+ 0x100124f4 0x1c _L1w_DevTxCalcCmPliot
+ 0x10012510 0x39 _L1w_DevTxGetUlMaxMinTti
+ 0x10012549 0x10e _L1w_DevTxGetDchParam
+ 0x10012657 0x75 _L1w_DevTxUlCmTfciAnalysis
+ 0x100126cc 0x29 _L1w_DevTxHsupaTransInd
+ 0x100126f5 0x16b _L1w_DevTxDchToPcStart
+ 0x10012860 0x26 _L1w_DevTxDchToPcStop
+ 0x10012886 0x64 _L1w_DevTxDchCmParaToPc
+ 0x100128ea 0x27 _L1w_DevTxDpcchPreambleToPc
+ 0x10012911 0x2a _L1w_DevTxDpdchTfciToPc
+ 0x1001293b 0x177 _L1w_DevTxDataUpdate
+ 0x10012ab2 0x55 _L1w_DevTxGetUtrPara
+ 0x10012b07 0x115 _L1w_DevTxDchUtrCfg
+ 0x10012c1c 0x77 _L1w_DevTxDchCmProc
+ 0x10012c93 0x154 _L1w_DevTxDchSendCfg
+ 0x10012de7 0xad _L1w_DevTxDchPreambleSendProc
+ 0x10012e94 0x29 _L1w_DevTxDchPostVerifyFailProc
+ 0x10012ebd 0x94 _L1w_DevTxDchPreambleIntHandle
+ 0x10012f51 0xd9 _L1w_DevTxDpchSendCndCheck
+ 0x1001302a 0x59 _L1w_DevTxDpchIntHandle
+ 0x10013083 0x54 _L1w_DevTxDchTpuIntHandle
+ 0x100130d7 0x65 _L1w_DevTxDchRelMsgHandle
+ 0x1001313c 0x8b _L1w_DevTxCmCfgMsgHandle
+ 0x100131c7 0xb0 _L1w_DevTxDchCfgMsgHandle
+ .text 0x10013277 0x6e4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x10013277 0xf _L1W_DevHsupaInitMacro
+ 0x10013286 0xc _L1W_DevHsupaCalCBNum
+ 0x10013292 0x21 _L1W_DevHsupaCalcCBLength
+ 0x100132b3 0xa _L1W_DevHsupaCalInterleavingRow
+ 0x100132bd 0x3a _L1W_DevHsupaCalCodeBlockConf
+ 0x100132f7 0x1c _L1w_DevHsupaCalMaxNej
+ 0x10013313 0x99 _L1W_DevHsupaCalSfOneEtfc
+ 0x100133ac 0xfd _L1W_DevHsupaCalAllSFConf
+ 0x100134a9 0x12a _L1W_DevHsupaCalSFConf
+ 0x100135d3 0x94 _L1W_DevHsupaCalRmRv
+ 0x10013667 0x9b _L1W_DevHsupaCalRmPara
+ 0x10013702 0x41 _L1W_DevHsupaCalChannelCodeConf
+ 0x10013743 0x7a _L1W_DevHsupaCalInterleavingConf
+ 0x100137bd 0x37 _L1W_DevHsupaReTransBitmapTtiTen
+ 0x100137f4 0x6b _L1W_DevHsupaCalEtxBitmap
+ 0x1001385f 0x48 _L1W_DevHsupaCalEUTRConf
+ 0x100138a7 0x6e _L1W_DevHsupaCalETXConf
+ 0x10013915 0x46 _L1W_DevHsupaCalULConf
+ .text 0x1001395b 0x1358 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x1001395b 0xb _L1w_DevRfcCtrlDbChgeInfoSet
+ 0x10013966 0xf _L1w_DevRfcCtrlDbChgeInfoInit
+ 0x10013975 0x2 _L1w_DevRfcCtrlDbSlotEndSet
+ 0x10013977 0x17 _L1w_DevRfcCtrlDbSlotInfoInit
+ 0x1001398e 0x61 _L1w_DevRfcCtrlDbInit
+ 0x100139ef 0x10 _L1w_DevRfcCtrlDbInitAll
+ 0x100139ff 0x37 _L1w_DevRfcCtrlDbTimeContCheck
+ 0x10013a36 0x33 _L1w_DevRfcCtrlDbSlotChgeInfoWr
+ 0x10013a69 0x16 _L1w_DevRfcCtrlDbGetDbInd
+ 0x10013a7f 0x35 _L1w_DevRfcCtrlDbFrameChgeInfoWr
+ 0x10013ab4 0x2d _L1w_DevRfcCtrlDbGetSegLen
+ 0x10013ae1 0x9f _L1w_DevRfcCtrlDbSlotEndUpdate
+ 0x10013b80 0x5c _L1w_DevRfcCtrlDbCtrlInfoUpdate
+ 0x10013bdc 0x117 _L1w_DevRfcCtrlDbSchedUpdate
+ 0x10013cf3 0x9c _L1w_DevRfcCtrlDbStPo2Chge
+ 0x10013d8f 0x6d _L1w_DevRfcCtrlDbStPo1Chge
+ 0x10013dfc 0x93 _L1w_DevRfcCtrlDbStPi2Chge
+ 0x10013e8f 0x27 _L1w_DevRfcCtrlDbStPi1Chge
+ 0x10013eb6 0x63 _L1w_DevRfcCtrlDbStPi0Chge
+ 0x10013f19 0x49 _L1w_DevRfcCtrlDbStartInsert
+ 0x10013f62 0xeb _L1w_DevRfcCtrlDbEndPo2Chge
+ 0x1001404d 0x5d _L1w_DevRfcCtrlDbEndPo1Chge
+ 0x100140aa 0xf _L1w_DevRfcCtrlDbEndPo0Chge
+ 0x100140b9 0x3f _L1w_DevRfcCtrlDbEndInsert
+ 0x100140f8 0xf9 _L1w_DevRfcCtrlDbDrvOpenUpdate
+ 0x100141f1 0xd _L1w_DevRfcCtrlDbGetAdr
+ 0x100141fe 0x4a _L1w_DevRfcCtrlDbChgeInfoHandle
+ 0x10014248 0x10e _L1w_DevRfcCtrlDbGetSlotChgeInfo
+ 0x10014356 0x39 _L1w_DevRfcAgcDbInit
+ 0x1001438f 0x29 _L1w_DevRfcAfcDbInit
+ 0x100143b8 0x14 _L1w_DevRfcAgcDbFreqSearch
+ 0x100143cc 0xe _L1w_DevRfcAgcDbSetFreqChgeFlag
+ 0x100143da 0x21 _L1w_DevRfcAgcDbFindOldestPos
+ 0x100143fb 0x58 _L1w_DevRfcAgcDbFindFreqPos
+ 0x10014453 0x21 _L1w_DevRfcAgcDbGetFreqInd
+ 0x10014474 0x35 _L1w_DevRfcAgcDbFastAgcCond
+ 0x100144a9 0xd0 _L1w_DevRfcAgcDbAgcSet
+ 0x10014579 0x3b _L1w_DevRfcAgcDbLockInfoUpdate
+ 0x100145b4 0x3a _L1w_DevRfcAgcCalcInfoUpdateCmn
+ 0x100145ee 0x2e _L1w_DevRfcAgcCalcInfoUpdateDpa
+ 0x1001461c 0x58 _L1w_DevRfcAgcDbAgcStepCtrl
+ 0x10014674 0x48 _L1w_DevRfcAgcDbAgcUpdate
+ 0x100146bc 0x6e _L1w_DevRfcAgcDbAgcCalcSingleCh
+ 0x1001472a 0x37 _L1w_DevRfcAgcDbAfterFastAgcSet
+ 0x10014761 0x38 _L1w_DevRfcAgcDbFastAgcValUpdate
+ 0x10014799 0x60 _L1w_DevRfcAgcDb2RMainChAdjCond
+ 0x100147f9 0x6b _L1w_DevRfcAgcDb2RAgcHandle
+ 0x10014864 0x124 _L1w_DevRfcAgcDbAgcCalc
+ 0x10014988 0x1c _L1w_DevRfcAgcDbAgcEstEn
+ 0x100149a4 0x3d _L1w_DevRfcAfcDbAfcSet
+ 0x100149e1 0x13 _L1w_DevRfcAfcDbGetAfcDbVal
+ 0x100149f4 0x1e _L1w_DevRfcSetRefFreq
+ 0x10014a12 0x43 _L1w_DevRfcAgcDbGetFreqAgcInfo
+ 0x10014a55 0x62 _L1w_DevRfcAgcDbGetRssi
+ 0x10014ab7 0x9e _L1w_DevRfcAgcDbGetMeanpwr
+ 0x10014b55 0x35 _L1w_DevRfcAgcDbAuxChInitSet
+ 0x10014b8a 0x42 _L1w_DevRfcAgcDbGetTableInd
+ 0x10014bcc 0x7a _L1w_DevRfcAgcDbFdtAgcInit
+ 0x10014c46 0x43 _L1w_DevRfcAgcDbNstAgcInit
+ 0x10014c89 0x15 _L1w_DevRfcAgcDbTxChgeInfoWr
+ 0x10014c9e 0x15 _L1w_DevRfcAgcDbRxChgeInfoWr
+ .text 0x10014cb3 0x2cb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls.o)
+ 0x10014cb3 0x26 _L1w_DevDlsSendIntMsg
+ 0x10014cd9 0x24 _L1w_DevDlsSendCnf
+ 0x10014cfd 0xf _L1w_DevDlsReset
+ 0x10014d0c 0xf _L1w_DevDlsInit
+ 0x10014d1b 0x263 _L1w_DlsTask
+ .text 0x10014f7e 0x12a5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x10014f7e 0x89 _L1w_DevHsdpaSubFrmIsInCm
+ 0x10015007 0x78 _L1w_DevHsdpaCalcTimingInfo
+ 0x1001507f 0x2d _L1w_DevHsdpaCalcAckNackPos
+ 0x100150ac 0x52 _L1w_DevHsdpaCalcTbSizeByTbs
+ 0x100150fe 0x23 _L1w_DevHsdpaCalcTbSizeByTbsIdx
+ 0x10015121 0xd _L1w_DevHsdpaCalcRvB
+ 0x1001512e 0x3a _L1w_DevHsdpaCalcCodeBlockPara
+ 0x10015168 0x25 _L1w_DevHsdpaCalc1stRmPara
+ 0x1001518d 0x37 _L1w_DevHsdpaCalc2ndRmEini
+ 0x100151c4 0xf9 _L1w_DevHsdpaCalcRmPara
+ 0x100152bd 0x9f _L1w_DevHsdpaCalcVelcity
+ 0x1001535c 0xd _L1w_DevHsdpaCalcSymPower
+ 0x10015369 0x79 _L1w_DevHsdpaCalcFingerMaskStep1
+ 0x100153e2 0xba _L1w_DevHsdpaCalcFingerMaskStep2
+ 0x1001549c 0x45 _L1w_DevHsdpaCalcFingerMaskStep3
+ 0x100154e1 0x5d _L1w_DevHsdpaCalcAntFingerMask
+ 0x1001553e 0x11f _L1w_DevHsdpaFingerMaskBufUpdate
+ 0x1001565d 0x8c _L1w_DevHsdpaCalcFingerMask
+ 0x100156e9 0xb8 _L1w_DevHsdpaSnrLowRstJudge
+ 0x100157a1 0x1b0 _L1w_DevHsdpaCalcNoiseSinr
+ 0x10015951 0x47 _L1w_DevHsdpaCalcNoiseFactor
+ 0x10015998 0xc3 _L1w_DevHsdpaCalcCirPower
+ 0x10015a5b 0xba _L1w_DevHsdpaCalcEqNoise
+ 0x10015b15 0x34 _L1w_DevHsdpaCalcNoise
+ 0x10015b49 0x2d _L1w_DevHsdpaIsExceedFinWin
+ 0x10015b76 0x6b _L1w_DevHsdpaPsrFingerFilter
+ 0x10015be1 0x56 _L1w_DevHsdpaCalcFrameHeadPos
+ 0x10015c37 0x87 _L1w_DevHsdpaCalcIntraCellSfnOffset
+ 0x10015cbe 0xfc _L1w_DevHsdpaCalcFingerSort
+ 0x10015dba 0x24 _L1w_DevHsdpaCalcJudgeResetFlg
+ 0x10015dde 0x27c _L1w_DevHsdpaCalcCellFingerSort
+ 0x1001605a 0x1b _L1w_DevHsdpaCalcAntChe4xPos
+ 0x10016075 0xef _L1w_DevHsdpaCalcChe4xPos
+ 0x10016164 0xbf _L1w_DevHsdpaCalcAdrPsrInfo
+ .text 0x10016223 0x3d4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_comm_int.o)
+ 0x10016223 0x3f _L1w_DevDrvAllIntClear
+ 0x10016262 0x54 _L1w_DevDrvRestoreAllInt
+ 0x100162b6 0x9e _L1W_TPU_RAKE_ISR
+ 0x10016354 0x70 _L1W_RAKE_DFE_RFC_ISR
+ 0x100163c4 0xac _L1W_TPU_CSR_ADR_HSSCCH_ISR
+ 0x10016470 0x89 _L1W_CSR_DTR_PSR_ISR
+ 0x100164f9 0x27 _L1w_DevCommGetTop19IntStatus
+ 0x10016520 0x26 _L1W_ICP_UPA_DATA_ISR
+ 0x10016546 0x5c _L1W_ICP_SLEEP_WAKEUP_ISR
+ 0x100165a2 0x1c _L1W_EDCP_ISR
+ 0x100165be 0x39 _L1_W_LPM_T3_ISR
+ .text 0x100165f7 0x2265 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x100165f7 0x8 _L1w_DevCsrSetStep1Clk
+ 0x100165ff 0x8 _L1w_DevCsrGetStep1Clk
+ 0x10016607 0x6 _L1w_DevGetPeakThreshold
+ 0x1001660d 0x1 _L1w_DevGetFsThreshold
+ 0x1001660e 0x1e _L1w_DevCsrStep1Cmp
+ 0x1001662c 0xa _L1w_DevCsrF2W
+ 0x10016636 0xf _L1w_DevCsrW2F
+ 0x10016645 0x15 _L1w_DevCsrCompare
+ 0x1001665a 0x87 _L1w_DevCsrComputeWin
+ 0x100166e1 0x2a _L1w_DevCsrInitReq
+ 0x1001670b 0x98 _L1w_DevCsrStep1Req
+ 0x100167a3 0x75 _L1w_DevCsrFsReq
+ 0x10016818 0x27 _L1w_DevCsrResetCnf
+ 0x1001683f 0x27 _L1w_DevCsrInitCnf
+ 0x10016866 0x65 _L1w_DevCsrStep1Cnf
+ 0x100168cb 0x4f _L1w_DevCsrFsCnf
+ 0x1001691a 0x2d _L1w_DevCsrIntInd
+ 0x10016947 0x5d _L1w_DevCsrStep1CalConfigIndex4_1
+ 0x100169a4 0x3d _L1w_DevCsrSaveDateMrtr
+ 0x100169e1 0x138 _L1w_DevCsrIcCfg
+ 0x10016b19 0xe _L1w_DevCsrSetFsAbort
+ 0x10016b27 0x1ac _L1w_DevCsrStep1Abort
+ 0x10016cd3 0x272 _L1w_DevCsrStep1Pro
+ 0x10016f45 0xa _L1w_DevCsrClrFsSt
+ 0x10016f4f 0x7d _L1w_DevCsrFsPro
+ 0x10016fcc 0xbf _L1w_DevCsrPeakFilter
+ 0x1001708b 0xb8 _L1w_DevCsrPeakSearch
+ 0x10017143 0x95 _L1w_DevCsrFsReqCfg
+ 0x100171d8 0x113 _L1w_DevCsrIcFilter
+ 0x100172eb 0x1312 _L1w_DevCsrStep1Int
+ 0x100185fd 0x125 _L1w_DevCsrFsInt
+ 0x10018722 0x1a _L1w_DevCsrStep1IsBusy
+ 0x1001873c 0x13 _L1w_DevCsrReset
+ 0x1001874f 0x10 _L1w_DevCsrStFsSt
+ 0x1001875f 0xfd _L1w_CsrTask
+ .text 0x1001885c 0x220d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x1001885c 0x30 _L1w_DevPcWord64ToFloat
+ 0x1001888c 0x40 _L1w_DevPcFloatToWord
+ 0x100188cc 0x2e _L1w_PcLog2FindTable
+ 0x100188fa 0x80 _L1w_DevPcFloatSirAndBlerToWord32
+ 0x1001897a 0x28 _L1w_DevPcDiv
+ 0x100189a2 0x71 _L1w_DevPcLog10
+ 0x10018a13 0xe6 _L1w_DevPc10xPower10expOld
+ 0x10018af9 0x2c _L1w_DevPc10xPower10exp
+ 0x10018b25 0x65 _L1w_DevSirBlerPcDiv
+ 0x10018b8a 0x38 _L1w_DevPcFloatAdd
+ 0x10018bc2 0x3b _L1w_DevPcUlAlphaDiv
+ 0x10018bfd 0x62 _L1w_DevPcPowerLimit
+ 0x10018c5f 0x86 _L1w_DevPcSumBeltaIQmap
+ 0x10018ce5 0x81 _L1w_DevPcCalcSquareBetaHs
+ 0x10018d66 0x22 _L1w_DevPcP1P2LogCalc
+ 0x10018d88 0x19 _L1w_DevPcP1P2Calc
+ 0x10018da1 0xd _L1w_DevPcBetalRatioProc
+ 0x10018dae 0x9d _L1w_DevPcCodeRatioCalc
+ 0x10018e4b 0x14 _L1w_DevPcGetTxpowerForMeas
+ 0x10018e5f 0x99 _L1w_DevPcConfigTxReg
+ 0x10018ef8 0x92 _L1w_DevPcTtiUpdDpaBeta
+ 0x10018f8a 0xe4 _L1w_DevPcTtiUpdEdchBeta
+ 0x1001906e 0x23 _L1w_DevPcNoDpdchPro
+ 0x10019091 0xb5 _L1w_DevPcTtiUpdDpchBeta
+ 0x10019146 0x35 _L1w_DevPcBetaEdAllSquareCalc
+ 0x1001917b 0xc _L1w_DevPcSumSquareCalc
+ 0x10019187 0x56 _L1w_DevPcSquareCalc
+ 0x100191dd 0x110 _L1w_DevPcIQMap
+ 0x100192ed 0x1b _L1w_DevPcRangeAdjust
+ 0x10019308 0x32 _L1w_DevPcCalcCm
+ 0x1001933a 0x146 _L1w_DevPcMprCalPro
+ 0x10019480 0x2f _L1w_DevPcMprAdjust
+ 0x100194af 0x39 _L1w_DevPcMprCalCtrl
+ 0x100194e8 0x116 _L1w_DevPcCodeRatioAndTotalPowerCalc
+ 0x100195fe 0x33 _L1w_DevPcPwrValadjust
+ 0x10019631 0x94 _L1w_DevPcGainTorAdjust
+ 0x100196c5 0x89 _L1w_DevPcCalPvalue
+ 0x1001974e 0x3f _L1w_DevPcGaintorHalf
+ 0x1001978d 0x4b _L1w_DevPcMaxPwrSetProc
+ 0x100197d8 0x178 _L1w_DevPcTxAndRfSet
+ 0x10019950 0x54 _L1w_DevPcTpuCallBack
+ 0x100199a4 0x1d _L1w_DevPcRegFrmTpu
+ 0x100199c1 0x88 _L1w_DevPcUlRegTpu
+ 0x10019a49 0x1c _L1w_DevPcIsBeltaEdAllEquReduce
+ 0x10019a65 0xff _L1w_DevPcSetLastBelta
+ 0x10019b64 0x25 _L1w_DevPcPmaxReLimt
+ 0x10019b89 0x7d _L1w_DevPcPmaxReCalc
+ 0x10019c06 0x2d _L1w_DevPcBeltaReCalcBeltaEdReducedMin
+ 0x10019c33 0x43 _L1w_DevPcBeltaReCalcEtfciBoost
+ 0x10019c76 0x97 _L1w_DevPcBeltaReCalc
+ 0x10019d0d 0x21 _L1w_DevPcMaxPowerLimit
+ 0x10019d2e 0x14 _L1w_DevPcMinPowerLimit
+ 0x10019d42 0xe0 _L1w_DevPcCMInfoUpdate
+ 0x10019e22 0x46 _L1w_DevPcFrmEventHandle
+ 0x10019e68 0x51 _L1w_DevPcPreCalc
+ 0x10019eb9 0x63 _L1w_DevPcStopHandle
+ 0x10019f1c 0xdd _L1w_DevPc3SymbolIntHandle
+ 0x10019ff9 0x4d _L1w_DevPcGaintorCalc
+ 0x1001a046 0x46 _L1w_DevPcTpuTpcSlotHandle
+ 0x1001a08c 0x1c _L1w_DevPcSlotModeGet
+ 0x1001a0a8 0x15 _L1w_DevPcDlGapPatternJudge
+ 0x1001a0bd 0x9 _L1w_DevPcWriteCmBitMap
+ 0x1001a0c6 0xa _L1w_DevPcIsUlCmFrm
+ 0x1001a0d0 0x15 _L1w_DevPcIsCmFrmOnlyGap
+ 0x1001a0e5 0x2d _L1w_DevPcIsCmFrm
+ 0x1001a112 0x7a _L1w_DevPcSlotModeSet
+ 0x1001a18c 0x2d _L1w_DevPcUlCmInfoHandle
+ 0x1001a1b9 0x24 _L1w_DevPcDlCmInfoHandle
+ 0x1001a1dd 0x48 _L1w_DevPcCmStopHandle
+ 0x1001a225 0x12 _L1w_DevPcCmStopReqHandle
+ 0x1001a237 0x32 _L1w_DevPcStopReqHandle
+ 0x1001a269 0x11c _L1w_DevPcWriteSubFrmIntInfo
+ 0x1001a385 0x74 _L1w_DevPcReset
+ 0x1001a3f9 0xcb _L1w_DevPcInit
+ 0x1001a4c4 0x7b _L1w_DevPcOutSyncEng
+ 0x1001a53f 0xef _L1w_DevPcEngPrintf
+ 0x1001a62e 0x63 _L1w_DevPcWriteDpramMsg
+ 0x1001a691 0x27 _L1w_DevPcResetCnf
+ 0x1001a6b8 0x27 _L1w_DevPcInitCnf
+ 0x1001a6df 0x2c _L1w_DevRtxPcPrachStartReq
+ 0x1001a70b 0x28 _L1w_DevRtxPcPrachPreambleReq
+ 0x1001a733 0x30 _L1w_DevRtxPcPrachMessageReq
+ 0x1001a763 0x39 _L1w_DevRtxPcDchStartReq
+ 0x1001a79c 0x2c _L1w_DevRtxPcUlDpchCmInfoReq
+ 0x1001a7c8 0x2c _L1w_DevRtxPcDlDpchCmInfoReq
+ 0x1001a7f4 0x29 _L1w_DevRtxPcDpchCmStopReq
+ 0x1001a81d 0x2e _L1w_DevRtxPcBlerReq
+ 0x1001a84b 0x2d _L1w_DevHsdpaPcStartReq
+ 0x1001a878 0x28 _L1w_DevHsdpaPcTtiReq
+ 0x1001a8a0 0x21 _L1w_DevHsdpaPcStoptReq
+ 0x1001a8c1 0x11 _L1w_DevDchPcSetPara
+ 0x1001a8d2 0x2a _L1w_DevHsupaPcStartReq
+ 0x1001a8fc 0x2d _L1w_DevHsupaPcTtiReq
+ 0x1001a929 0x21 _L1w_DevHsupaPcStopReq
+ 0x1001a94a 0x11f _L1w_PcTask
+ .text 0x1001aa69 0x29a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x1001aa69 0x1 _L1w_DevEngInitAddr
+ 0x1001aa6a 0x19 _L1w_EngTaskInit
+ 0x1001aa83 0x7 _L1w_DevEngSetFlag
+ 0x1001aa8a 0x12 _L1w_log_track_init
+ 0x1001aa9c 0x8e _L1w_DevEngDisplay
+ 0x1001ab2a 0x46 _L1w_EngTrace
+ 0x1001ab70 0xaa _L1w_DevEngLogHeaderUpdate
+ 0x1001ac1a 0xc6 _L1w_DevEngWriteDataToBuffer
+ 0x1001ace0 0x22 _L1w_DevEngCopyMem2Dpram
+ 0x1001ad02 0x1 _L1w_DevEngUartTransmit
+ .text 0x1001ad03 0xde T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx.o)
+ 0x1001ad03 0x9 _L1w_DevTxFirstTpuIntSet
+ 0x1001ad0c 0xc _L1w_DevTxFirstTpuIntDelete
+ 0x1001ad18 0x82 _L1w_DevRtxTxCfgMsgHandle
+ 0x1001ad9a 0x16 _L1w_DevTxTpuIntHandle
+ 0x1001adb0 0x15 _L1w_DevRtxTxReset
+ 0x1001adc5 0x1c _L1w_DevRtxTxInit
+ .text 0x1001ade1 0x1cc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x1001ade1 0x6b _L1w_DevRtxRxBlindAnalyse
+ 0x1001ae4c 0x77 _L1w_DevRtxRxTfcParaCalc
+ 0x1001aec3 0xd5 _L1w_DevRtxRxJudgeCsRam
+ 0x1001af98 0x115 _L1w_DevRtxRxTrchParaCalc
+ 0x1001b0ad 0x33 _L1w_DevRtxRxDtrCtfcSort
+ 0x1001b0e0 0x81 _L1w_DevRtxRxSccpchDtrParam
+ 0x1001b161 0x3b _L1w_DevRtxRxJudgeRrm
+ 0x1001b19c 0x2f _L1w_DevRtxRxV3BlindTbs49Change
+ 0x1001b1cb 0x25 _L1w_DevRtxRxV3BlindTbsChange
+ 0x1001b1f0 0xc4 _L1w_DevRtxRxV3BlindTfcPatch
+ 0x1001b2b4 0xd2 _L1w_DevRtxRxDpchDtrParam
+ 0x1001b386 0x11 _L1w_DevRtxRxTtiModeGet
+ 0x1001b397 0xe _L1w_DevRtxRxCrcModeGet
+ 0x1001b3a5 0x16 _L1w_DevRtxRxCodingGet
+ 0x1001b3bb 0x89 _L1w_DevRtxRxTrchInfoCfg
+ 0x1001b444 0x51 _L1w_DevRtxRxDpchDtrCmCfg
+ 0x1001b495 0x74 _L1w_DevRtxRxDlDpchDtrCfg
+ 0x1001b509 0x6d _L1w_DevRtxRxDlSccpchDtrCfg
+ 0x1001b576 0x36 _L1w_DevRtxRxAgchDtrCfg
+ 0x1001b5ac 0x83 _L1w_DevRtxRxAgchCmDtrCfg
+ 0x1001b62f 0x45 _L1w_DevRtxRxCfgABUpdate
+ 0x1001b674 0x34 _L1w_DevRtxRxDeilBaseSort
+ 0x1001b6a8 0x9f _L1w_DevRtxRxTfciS2Cfg
+ 0x1001b747 0xb1 _L1w_DevRtxRxTfcAnalyse
+ 0x1001b7f8 0x58 _L1w_DevRtxRxBlindGuidCfg
+ 0x1001b850 0x37 _L1w_DevRtxRxPn9BerCheckStart
+ 0x1001b887 0xa1 _L1w_DevRtxRxPn9Get244Bit
+ 0x1001b928 0x42 _L1w_DevRtxRxPn9BerRltReport
+ 0x1001b96a 0xc5 _L1w_DevRtxRxPn9DataCheck
+ 0x1001ba2f 0x81 _L1w_DevRtxRxAllBlindHandle
+ 0x1001bab0 0xda _L1w_DevRtxRxBlindDtrCfg
+ 0x1001bb8a 0x17a _L1w_DevRtxRxBlindCrcHandle
+ 0x1001bd04 0xc3 _L1w_DevRtxRxBlindDataHandle
+ 0x1001bdc7 0x21 _L1w_DevRtxRxBlindStateCheck
+ 0x1001bde8 0xeb _L1w_DevRtxRxBlindTfcAnalyse
+ 0x1001bed3 0x3a _L1w_DevRtxRxTfcDataCmpHandle
+ 0x1001bf0d 0x38 _L1w_DevRtxRxTfciFWHT
+ 0x1001bf45 0x126 _L1w_DevRtxRxTfciCoding
+ 0x1001c06b 0x1f1 _L1w_DevRtxRxTfciIntHandle
+ 0x1001c25c 0x18 _L1w_DevRtxRxGetGsmVal
+ 0x1001c274 0x76 _L1w_DevRtxRxCmpPchUeId
+ 0x1001c2ea 0x55 _L1w_DevRtxRxPchUeIdHandle
+ 0x1001c33f 0x114 _L1w_DevRtxRxTtiBlindHandle
+ 0x1001c453 0xab _L1w_DevRtxRxTrchCrcStatic
+ 0x1001c4fe 0xbd _L1w_DevRtxRxTtiCrcStatic
+ 0x1001c5bb 0xb _L1w_DevRtxRxTtiCrcStatForAfc
+ 0x1001c5c6 0x63 _L1w_DevRtxRxTtiTrchInfoHandle
+ 0x1001c629 0x8d _L1w_DevRtxRxTtiBdTrchInfoHandle
+ 0x1001c6b6 0x64 _L1w_DevRtxRxNoBdTtiHandle
+ 0x1001c71a 0x54 _L1w_DevRtxRxBlindTtiHandle
+ 0x1001c76e 0x49 _L1w_DevRtxRxPchTtiHandle
+ 0x1001c7b7 0x68 _L1w_DevRtxRxTtiIntAfterHandle
+ 0x1001c81f 0x25e _L1w_DevRtxRxTtiIntHandle
+ 0x1001ca7d 0x24 _L1w_DevRtxRxDtrRel
+ .text 0x1001caa1 0x5db T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_cqi.o)
+ 0x1001caa1 0x8b _L1w_DevHsdpaCqiCalcPos
+ 0x1001cb2c 0x1b1 _L1w_DevHsdpaCalcCqiSnr
+ 0x1001ccdd 0x6b _L1w_DevHsdpaSnrLimitAdj
+ 0x1001cd48 0xbf _L1w_DevHsdpaCqiSnrAdj
+ 0x1001ce07 0x68 _L1w_DevHsdpaCalcSnrVal
+ 0x1001ce6f 0x20d _L1w_DevHsdpaSnrMapToCqiVal
+ .text 0x1001d07c 0x2f5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_pcch.o)
+ 0x1001d07c 0x5b _L1w_DevRtxRxPcchBitRead
+ 0x1001d0d7 0x3e _L1w_DevRtxRxImsiGsm
+ 0x1001d115 0x2f _L1w_DevRtxRxTmsiGsm
+ 0x1001d144 0x2f _L1w_DevRtxRxPTmsiGsm
+ 0x1001d173 0xf _L1w_DevRtxRxImsiDs41
+ 0x1001d182 0xf _L1w_DevRtxRxTmsiDs41
+ 0x1001d191 0x3d _L1w_DevRtxRxPagRecCnId
+ 0x1001d1ce 0x44 _L1w_DevRtxRxPagRecUtranId
+ 0x1001d212 0x4e _L1w_DevRtxRxPagRec2UtranSingUeId
+ 0x1001d260 0x28 _L1w_DevRtxRxPagRec2UtranGrpId
+ 0x1001d288 0x28 _L1w_DevRtxRxPagingRecList
+ 0x1001d2b0 0x28 _L1w_DevRtxRxPagingRec2ListR5
+ 0x1001d2d8 0x12 _L1w_DevRtxRxPagingV590ExtIE
+ 0x1001d2ea 0x10 _L1w_DevRtxRxPagingV860ExtIE
+ 0x1001d2fa 0x47 _L1w_DevRtxRxPagingType1
+ 0x1001d341 0x19 _L1w_DevRtxRxPcchMsgType
+ 0x1001d35a 0x17 _L1w_DevRtxRxDecodePcch
+ .text 0x1001d371 0x18da T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x1001d371 0x22 _L1w_HspaCalcMod
+ 0x1001d393 0xb _L1w_DevHsupaEdchReadyInit
+ 0x1001d39e 0x11 _L1w_DevHsupaInitUlDataInfo
+ 0x1001d3af 0x18 _L1w_DevHsupaUlReset
+ 0x1001d3c7 0x5c _L1w_DevHsupaParaInit
+ 0x1001d423 0x45 _L1w_DevHsupaInit
+ 0x1001d468 0x15 _L1w_DevHsupaHwRel
+ 0x1001d47d 0x8f _L1w_DevHsupaReset
+ 0x1001d50c 0x5f _L1w_DevHsupaGetDlChanInfo
+ 0x1001d56b 0x34 _L1w_DevHsupaCalcDisEagchEdch
+ 0x1001d59f 0x10 _L1w_DevHsupaCalcDisEhichEdch
+ 0x1001d5af 0x21 _L1w_DevHsupaCalcDisErgchEdch
+ 0x1001d5d0 0x1a _L1w_DevHsupaCalcInitNo
+ 0x1001d5ea 0x3a _L1w_DevHsupaCalcInitSwNo
+ 0x1001d624 0x64 _L1w_DevHsupaCalcIscpSlotId
+ 0x1001d688 0x9a _L1w_DevHsupaCalcDlChanInitNo
+ 0x1001d722 0x5e _L1w_DevHsupaConfigReq
+ 0x1001d780 0x2b _L1w_DevHsupaCpEdpdchInfo
+ 0x1001d7ab 0x3d _L1w_DevHsupaCpErntiInfo
+ 0x1001d7e8 0x65 _L1w_DevHsupaCpRxEagchCfg
+ 0x1001d84d 0x42 _L1w_DevHsupaRtxEagchCfg
+ 0x1001d88f 0x8 _L1w_DevHsupaGetErgchFrameType
+ 0x1001d897 0x7e _L1w_DevHsupaCpRxRgHiCfg
+ 0x1001d915 0x77 _L1w_DevHsupaRtxRgHiCfg
+ 0x1001d98c 0x23 _L1w_DevHsupaRtxCfg
+ 0x1001d9af 0xca _L1w_DevHsupaCpDlRcvInfo
+ 0x1001da79 0x20 _L1w_DevHsupaCfgTxInit
+ 0x1001da99 0x22 _L1w_DevHsupaEagchInt2Ps
+ 0x1001dabb 0x97 _L1w_DevHsupaCalAgRgHiIntNo
+ 0x1001db52 0x4f _L1w_DevHsupaNorm2TpuBase
+ 0x1001dba1 0x79 _L1w_DevHsupaFachNt2CfnTime
+ 0x1001dc1a 0x84 _L1w_DevHsupaSaveTpuTime
+ 0x1001dc9e 0x2d _L1w_DevHsupaCalcSwTtiCntIntOff
+ 0x1001dccb 0x73 _L1w_DevHsupaGetCfnTime
+ 0x1001dd3e 0x25 _L1w_DevHsupaCalcSwTtiCntIntOn
+ 0x1001dd63 0x114 _L1w_DevHsupaEagchIntProc
+ 0x1001de77 0x18 _L1w_DevHsupaEagchIntInd
+ 0x1001de8f 0x4c _L1w_DevHuspaSaveAG
+ 0x1001dedb 0x12 _L1w_DevHuspaUpaTransFlgToMac
+ 0x1001deed 0x1c _L1w_DevHuspaGrantHarqToMac
+ 0x1001df09 0xb9 _L1w_DevHsupaReportPsStatistic
+ 0x1001dfc2 0x65 _L1w_DevHsupaStdlogThroughput
+ 0x1001e027 0x82 _L1w_DevHsupaStdlogPacketInfo
+ 0x1001e0a9 0x40 _L1w_DevHsupaReportToMac
+ 0x1001e0e9 0x71 _L1w_DevHsupaRptHarqFlag
+ 0x1001e15a 0x5b _L1w_DevHsupaDchIsMacTrans
+ 0x1001e1b5 0x14 _L1w_DevHsupaFachIsMacTrans
+ 0x1001e1c9 0x22 _L1w_DevHsupaIsMacTrans
+ 0x1001e1eb 0x37 _L1w_DevHsupaPcCfg
+ 0x1001e222 0x1 _L1w_DevHsupaAgRgHiIndCallBack
+ 0x1001e223 0x3a _L1w_DevHsupaAddTpu
+ 0x1001e25d 0x9 _L1w_DevHsupaGetPhyMinSfMaxChan
+ 0x1001e266 0x9e _L1w_DevHsupaDisplayCfgInfo
+ 0x1001e304 0x6a _L1w_DevHsupaSaveStdlogPacket
+ 0x1001e36e 0x35 _L1w_DevHsupaCfgToPsrInd
+ 0x1001e3a3 0x125 _L1w_DevHsupaConfigProc
+ 0x1001e4c8 0x2c _L1w_DevHsupaIcpIntInd
+ 0x1001e4f4 0x2c _L1w_DevHsupaEdcpIntInd
+ 0x1001e520 0x59 _L1w_DevHsupaIcpIntProc
+ 0x1001e579 0xea _L1w_DevHsupaEdcpIntProc
+ 0x1001e663 0x26 _L1w_DevHsupaCfgPcTti
+ 0x1001e689 0x2c _L1w_DevHsupaEtxIntInd
+ 0x1001e6b5 0x2d _L1w_DevHsupaCalcNtx1Info
+ 0x1001e6e2 0x23 _L1w_DevHsupaCmInfoClr
+ 0x1001e705 0xf1 _L1w_DevHsupaEtxIntProc
+ 0x1001e7f6 0x21 _L1w_DevHsupaRelReq
+ 0x1001e817 0xf _L1w_DevHsupaRtxRelReq
+ 0x1001e826 0x4e _L1w_DevHsupaReleaseProc
+ 0x1001e874 0xc _L1w_DevHsupaIfHarqIdValid
+ 0x1001e880 0x66 _L1w_DevHsupaTestCurFrameNum
+ 0x1001e8e6 0x37 _L1w_DevHsupaCalcEdchCfn
+ 0x1001e91d 0x2a _L1w_DevHsupaGetCurFrameNum
+ 0x1001e947 0x2d _L1w_DevHsupaCalcNextTtiFrameNum
+ 0x1001e974 0x2b _L1w_DevHsupaCmPatternUpdateReq
+ 0x1001e99f 0x5c _L1w_DevHsupaCalcDlCm
+ 0x1001e9fb 0x69 _L1w_DevHsupaCmPatternUpdateProc
+ 0x1001ea64 0x31 _L1w_DevHsupaCalChLen
+ 0x1001ea95 0x7 _L1w_DevHsupaSetHsdschCfg
+ 0x1001ea9c 0x77 _L1w_DevHsupaActive
+ 0x1001eb13 0xf1 _L1w_DevHsupaTpuProc
+ 0x1001ec04 0x3b _L1w_DevHsupaTransIndProc
+ 0x1001ec3f 0xc _L1w_DevHsupaIsDchActive
+ .text 0x1001ec4b 0x18b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_int.o)
+ 0x1001ec4b 0xb _L1w_DevRtxRxIntDataInit
+ 0x1001ec56 0x13 _L1w_DevRtxRxIntReset
+ 0x1001ec69 0x12 _L1w_DevRtxRxFix2Sword32
+ 0x1001ec7b 0x13 _L1w_DevRtxRxFix2Sword16
+ 0x1001ec8e 0x6e _L1w_DevRtxRxRcvFingerSlotwt
+ 0x1001ecfc 0x38 _L1w_DevRtxRxRcvFingerAfc
+ 0x1001ed34 0x5b _L1w_DevRtxRxRcvFingerNoise
+ 0x1001ed8f 0x27 _L1w_DevRtxRxCalcFingerIscp
+ 0x1001edb6 0x9c _L1w_DevRtxRxRcvOffLInePiResult
+ 0x1001ee52 0x88 _L1w_DevRtxRxRcvPiData
+ 0x1001eeda 0xcc _L1w_DevRtxRxPichIntHandle
+ 0x1001efa6 0x25 _L1w_DevRtxRxGetBuffIdx
+ 0x1001efcb 0xb2 _L1w_DevRtxRxRcvAiData
+ 0x1001f07d 0xdd _L1w_DevRtxRxCalcAiCpichPower
+ 0x1001f15a 0x51 _L1w_DevRtxRxCalcAiCpichPrIIR
+ 0x1001f1ab 0x10 _L1w_DevRtxRxGetAiDeltaPac
+ 0x1001f1bb 0x31 _L1w_DevRtxRxCalcAiThreshold
+ 0x1001f1ec 0x24 _L1w_DevRtxRxCalcAiSignCorr
+ 0x1001f210 0x26 _L1w_DevRtxRxCalcAiVal
+ 0x1001f236 0x26 _L1w_DevRtxRxAiDataPreHandle
+ 0x1001f25c 0x2e _L1w_DevRtxRxEAiResCfgMap
+ 0x1001f28a 0x4b _L1w_DevRtxRxNewCalcAiVal
+ 0x1001f2d5 0x5e _L1w_DevRtxRxNewEAiCalc
+ 0x1001f333 0x122 _L1w_DevRtxRxNewAichIntHandle
+ 0x1001f455 0x2b _L1w_DevRtxRxCalcFbiFingerPr
+ 0x1001f480 0x34 _L1w_DevRtxRxCalcFbiRlPr
+ 0x1001f4b4 0xed _L1w_DevRtxRxCalcFbiTotalPr
+ 0x1001f5a1 0x23 _L1w_DevRtxRxCalcFbiValue
+ 0x1001f5c4 0xc6 _L1w_DevRtxRxCalcFbi
+ 0x1001f68a 0x4a _L1w_DevRtxRxIntParaUpdate
+ 0x1001f6d4 0x6 _L1w_DevRtxRxGetTpcIData
+ 0x1001f6da 0x5 _L1w_DevRtxRxGetTpcQData
+ 0x1001f6df 0x6 _L1w_DevRtxRxGetTpcIExp
+ 0x1001f6e5 0x5 _L1w_DevRtxRxGetTpcQExp
+ 0x1001f6ea 0x58 _L1w_DevRtxRxDchTpcSirCalc
+ 0x1001f742 0xcf _L1w_DevRtxRxDchTpcIntHandle
+ 0x1001f811 0x9 _L1w_DevRtxRxDchPilotIntHandle
+ 0x1001f81a 0x6f _L1w_DevRtxRxFdpchTpcIntHandle
+ 0x1001f889 0x46 _L1w_DevRtxRxTpcIntHandle
+ 0x1001f8cf 0x4c _L1w_DevRtxRxFactorCheck
+ 0x1001f91b 0x84 _L1w_DevRtxRxFactorDataGet
+ 0x1001f99f 0x44 _L1w_DevRtxRxFactorHandle
+ 0x1001f9e3 0x61 _L1w_DevRtxRxAgchFactorHandle
+ 0x1001fa44 0x50 _L1w_DevRtxRxSccpchFactorCalc
+ 0x1001fa94 0x13b _L1w_DevRtxRxPchFactorHandle
+ 0x1001fbcf 0x109 _L1w_DevRtxRxFachFactorHandle
+ 0x1001fcd8 0x2f _L1w_DevRtxRxCalcIscp
+ 0x1001fd07 0x1dd _L1w_DevRtxRxFingerDataHandle
+ 0x1001fee4 0x8a _L1w_DevRtxRxNoiseDataCheck
+ 0x1001ff6e 0x67 _L1w_DevRtxRxSetAfcInfo
+ 0x1001ffd5 0x119 _L1w_DevRtxRxCpich2ndFingerPrint
+ 0x100200ee 0xf3 _L1w_DevRtxRxCpichTpuIntPrint
+ 0x100201e1 0xea _L1w_DevRtxRxCpichTpuIntAllPrint
+ 0x100202cb 0x5a _L1w_DevRtxRxCpichTpuIntIscpErrPrint
+ 0x10020325 0x45 _L1w_DevRtxRxCpichTpuIntUpaParaUpdate
+ 0x1002036a 0x167 _L1w_DevRtxRxCpichTpuIntHandle
+ 0x100204d1 0x1 _L1w_DevRtxRxPilotIntHandle
+ 0x100204d2 0x2c _L1w_DevRtxRxIntHandle
+ .text 0x100204fe 0x3556 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x100204fe 0x5 _L1w_DevDlsPsrReset
+ 0x10020503 0xb8 _L1w_DevDlsintialGlobalVariable
+ 0x100205bb 0x30 _L1w_DevDlsPsrIntialHardWare
+ 0x100205eb 0x8 _L1w_DevDlsPsrIntial
+ 0x100205f3 0xd _L1w_DevDlsSaveOldUlTiming
+ 0x10020600 0x64 _L1w_DevDlsStop
+ 0x10020664 0x3a _L1w_DevPsrIntEventProc
+ 0x1002069e 0x35 _L1w_DevPsrSendTimingInfoToL1s
+ 0x100206d3 0x3d _L1w_DevPsrAddTpuFixedEvent
+ 0x10020710 0x27 _L1w_DevPsrDchStopReq
+ 0x10020737 0x39 _L1w_DevPsrMeasStartReq
+ 0x10020770 0x12d _L1w_DevPsrDchJudgeNcellSave
+ 0x1002089d 0x177 _L1w_DevPsrSetRlNcellFlag
+ 0x10020a14 0x36 _L1w_DevPsrEfachStartReq
+ 0x10020a4a 0x32 _L1w_DevPsrEfachFdpchOffsetReq
+ 0x10020a7c 0x22 _L1w_DevPsrEfachStopReq
+ 0x10020a9e 0x25 _L1w_DevPsrFmoStopReq
+ 0x10020ac3 0x3b _L1w_DevDlsPsrHsdpaReq
+ 0x10020afe 0x32 _L1w_DevPsrDchUpaExistReq
+ 0x10020b30 0x6c _L1w_DevPsrEfachUlDpcchFBConfig
+ 0x10020b9c 0x54 _L1w_DevPsrUlDpcchFBConfig
+ 0x10020bf0 0x1 _L1w_DevPsrCommParaCfg
+ 0x10020bf1 0x3c _L1w_DevPsrSaveCmInfo
+ 0x10020c2d 0x21 _L1w_DevPsrTransDpchCm2Cpich
+ 0x10020c4e 0xa8 _L1w_DevPsrRtxFirstFingerConfigS
+ 0x10020cf6 0x196 _L1w_DevPsrSelectMasterRl
+ 0x10020e8c 0x6c _L1w_DevPsrSaveLastTimingTrace
+ 0x10020ef8 0x110 _L1w_DevPsrDchSelectUpaCell
+ 0x10021008 0x160 _L1w_DevPsrDchConfigHardware
+ 0x10021168 0xf8 _L1w_DevPsrDchReqConfig
+ 0x10021260 0xfa _L1w_DevPsrHardWorkTimeConfig
+ 0x1002135a 0x53 _L1w_DevPsrRlPosAndCodeConfig
+ 0x100213ad 0xc8 _L1w_DevPsrFachReqConfig
+ 0x10021475 0x29 _L1w_DevDlsCalcHandOverNtAdjPos
+ 0x1002149e 0x2f _L1w_DevDlsCalcAdjPos
+ 0x100214cd 0x1d9 _L1w_DevDlsCalcRegConfigTimingAndReport
+ 0x100216a6 0x15a _L1w_DevDlsCalcRlTimingAndReport
+ 0x10021800 0x58 _L1w_DevDlsPsrUpdateULInfo
+ 0x10021858 0x125 _L1w_DevDlsFachTimingMaintain
+ 0x1002197d 0x1c _L1w_DevDlsTimingMaintain
+ 0x10021999 0x34 _L1w_DevDlsDchJudgeAdustSpeed
+ 0x100219cd 0x42 _L1w_DevDlsDchTimingMaintain
+ 0x10021a0f 0x48 _L1w_DevDlsPsrSelectDpaId
+ 0x10021a57 0x63 _L1w_DevDlsPsrChangeDpaIdCell
+ 0x10021aba 0xc8 _L1w_DevDlsPsrGetAntNumAndJudgeConfig
+ 0x10021b82 0xa _L1w_DevDlsPsrClearCopyFingernfo
+ 0x10021b8c 0x3a _L1w_DevDlsPsrDpaIsChangjing1
+ 0x10021bc6 0x11a _L1w_DevDlsPsrJudgeFingerOver512
+ 0x10021ce0 0x2df _L1w_DevDlsPsrWholeHandleS
+ 0x10021fbf 0x24 _L1w_DevPsrTpuIntHandle
+ 0x10021fe3 0x4a _L1w_DevPsrRlCpichTimingAdujst
+ 0x1002202d 0x5b _L1w_DevPsrSoftHandOverTimingAdj
+ 0x10022088 0x5a _L1w_DevPsrIsCmCfgBug
+ 0x100220e2 0x66 _L1w_DevPsrCmHandle
+ 0x10022148 0x50 _L1w_DevPsrCalcRlsTxRxTimeDiff
+ 0x10022198 0x9a _L1w_DevPsrTimingAdj
+ 0x10022232 0x182 _L1w_DevPsrUpdateRlPos
+ 0x100223b4 0x53 _L1w_DevPsrFmoHandle
+ 0x10022407 0x170 _L1w_DevPsrRdPeakInfoS
+ 0x10022577 0xaf _L1w_DevDlsPsrSidelobeSurp
+ 0x10022626 0x10 _L1w_DevDlsPsrFingerSidelobeSurp
+ 0x10022636 0xb2 _L1w_DevDlsPsrCorasePathDetect
+ 0x100226e8 0x3d _L1w_DevDlsPsrFindStrongFiger
+ 0x10022725 0x46 _L1w_DevDlsPsrUpdateFigerTable
+ 0x1002276b 0x152 _L1w_DevDlsPsrStrongFigerPathDetect
+ 0x100228bd 0x149 _L1w_DevDlsPsrPathDect
+ 0x10022a06 0x3b _L1w_DevPsrRssiNormal
+ 0x10022a41 0x99 _L1w_DevDlsPsrUpdateFingerPos
+ 0x10022ada 0x12 _L1w_DevDlsPsrCalcMrtrDiff
+ 0x10022aec 0x23 _L1w_DevDlsPsrCalcMrtrAver
+ 0x10022b0f 0x31 _L1w_DevDlsPsrSortMinRange
+ 0x10022b40 0x31 _L1w_DevDlsPsrSortMinRange1
+ 0x10022b71 0x70 _L1w_DevDlsPsrSynProtect
+ 0x10022be1 0x24 _L1w_DevPsrBackWardProtect
+ 0x10022c05 0x26 _L1w_DevPsrForwardProtect
+ 0x10022c2b 0x19b _L1w_DevDlsPsrFingerPeakUpdate
+ 0x10022dc6 0x18 _L1w_DevPsrSortMinValue
+ 0x10022dde 0x18 _L1w_DevDlsPsrSortMaxValue
+ 0x10022df6 0x14c _L1w_DevPsrCandidatefingerUpdate
+ 0x10022f42 0xb3 _L1w_DevDlsPsrFingerPeakSelect
+ 0x10022ff5 0x72 _L1w_DevDlsPsrCalcDpchTiming
+ 0x10023067 0x2f _L1w_DevPsrFinPeakNormal
+ 0x10023096 0x38 _L1w_DevPsrAntFinPeakNormal
+ 0x100230ce 0x3b _L1w_DevDlsPsrSelectValidFinger
+ 0x10023109 0x98 _L1w_DevDlsPsrCalcDpchBaseTiming
+ 0x100231a1 0x47 _L1w_DevDlsPsrSortRtxFinger
+ 0x100231e8 0xb _L1w_DevPsrGetDchStartPsrFlag
+ 0x100231f3 0x150 _L1w_DevDlsPsrSelectRtxFinger
+ 0x10023343 0x93 _L1w_DevDlsPsrSelectNcellFinger
+ 0x100233d6 0xc8 _L1w_DevDlsPsrSortDpaFirst
+ 0x1002349e 0xf6 _L1w_DevDlsPsrNewFingerMapping
+ 0x10023594 0xd4 _L1w_DevDlsPsrAdrWindowUpdateS
+ 0x10023668 0xc _L1w_DevDlsPsrSendAdrFingerInfoS
+ 0x10023674 0xd0 _L1w_DevPsrSelSeaWindowFinInfoS
+ 0x10023744 0x47 _L1w_DevPsrSelNewSearchWindowS
+ 0x1002378b 0x21 _L1w_DevPsrIsSearchWindowPath
+ 0x100237ac 0x28 _L1w_DevPsrCalcSearchWindowSum
+ 0x100237d4 0x15 _L1w_DevDlsPsrCalcFingerPeakSum
+ 0x100237e9 0x38 _L1w_DevPsrSortFirstFinger
+ 0x10023821 0x23 _L1w_DevDlscalcPosOff
+ 0x10023844 0x1e3 _L1w_DevDlsChangedMasterRlTiming
+ 0x10023a27 0x13 _L1w_DevDlsPsrFingerCmp
+ 0x10023a3a 0x12 _L1w_DevDlsPsrFingerLessThan
+ 0x10023a4c 0x8 _TestZero
+ .text 0x10023a54 0x5c1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_plus.o)
+ 0x10023a54 0x8 _L1w_DevHsupaFachFdpchOffset
+ 0x10023a5c 0xb _L1w_DevHsupaIsEfachActive
+ 0x10023a67 0x35 _L1w_DevHsupaRtxEdchResInd
+ 0x10023a9c 0x16 _L1w_DevHsupaFachToPsrInd
+ 0x10023ab2 0x52 _L1w_DevHsupaFachConfigReq
+ 0x10023b04 0x3c _L1w_DevHsupaFachCpErntiInfo
+ 0x10023b40 0xa5 _L1w_DevHsupaFachConfigProc
+ 0x10023be5 0x21 _L1w_DevHsupaFachRelReq
+ 0x10023c06 0x46 _L1w_DevHsupaFachRelProc
+ 0x10023c4c 0x26 _L1w_DevHsupaErntiUpdateReq
+ 0x10023c72 0x24 _L1w_DevHsupaErntiUpdateProc
+ 0x10023c96 0x21 _L1w_DevHsupaFachNoDataReq
+ 0x10023cb7 0x7e _L1w_DevHsupaFachNoDataProc
+ 0x10023d35 0x96 _L1w_DevHsupaFachGetRgHiChanInfo
+ 0x10023dcb 0x4a _L1w_DevHsupaFachCfn2NetTime
+ 0x10023e15 0x9b _L1w_DevHsupaFachAddTpu2ms
+ 0x10023eb0 0x6b _L1w_DevHsupaFachAddTpu10ms
+ 0x10023f1b 0x22 _L1w_DevHsupaFachAddTpu
+ 0x10023f3d 0xe _L1w_DevHsupaFachIsMacInitTrans
+ 0x10023f4b 0x1d _L1w_DevHsupaFachAddTpuSubInt
+ 0x10023f68 0x88 _L1w_DevHsupaFachEdchResProc
+ 0x10023ff0 0x25 _L1w_DevHsupaFachReset
+ .text 0x10024015 0x182d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x10024015 0x21 _L1w_SetWmodeLpcMacroValue
+ 0x10024036 0x8 _L1w_DevSleepSetCfunFlg
+ 0x1002403e 0x13 _L1w_PosCmp
+ 0x10024051 0x1c _L1w_DevLpcDvfs
+ 0x1002406d 0x2b _L1W_DevSleepLpmInspectInit
+ 0x10024098 0x87 _L1w_DevUeTurnOn3sNoLpc
+ 0x1002411f 0xe _l1w_DevLpcSetAdjLpmFrmIntFlg
+ 0x1002412d 0xe _l1w_DevLpcGetAdjLpmFrmIntFlg
+ 0x1002413b 0xf _L1w_DevLpcSetSleepSubSt
+ 0x1002414a 0x10 _L1w_DevLpcGetSleepFlg
+ 0x1002415a 0x85 _L1w_DevLpcDpaRecover
+ 0x100241df 0x1f _L1w_DevLpcDrxRecover
+ 0x100241fe 0x93 _L1w_DevLpcClkDevCtrl
+ 0x10024291 0x3d _l1w_DevLpcClkInit
+ 0x100242ce 0x9e _L1w_DevLpcPwrDevCtrl
+ 0x1002436c 0x2d _l1w_DevLpcPwrInit
+ 0x10024399 0x7d _L1w_DevSleepNoLpc
+ 0x10024416 0xa2 _L1w_DevLpcLpmIntCheck
+ 0x100244b8 0x124 _L1w_DevLpcSendIcp
+ 0x100245dc 0x10 _L1w_DevLpcGetWakeUpType
+ 0x100245ec 0x2f _L1w_LpcRegionJudge
+ 0x1002461b 0x4a _L1w_DevLpcSerIdleLen
+ 0x10024665 0x6 _L1w_LpcGetLpcDbAddress
+ 0x1002466b 0x23 _L1w_LpcCalcLen
+ 0x1002468e 0x46 _L1w_LpcPosMove
+ 0x100246d4 0xb5 _L1w_DevLpcCalPreSyncInfo
+ 0x10024789 0x43 _L1w_DevLpcIsPiPchOffsetLen
+ 0x100247cc 0x1ac _L1w_SchedGapGetSleepEnLen
+ 0x10024978 0x77 _L1w_DevLpcCalSleepInfo
+ 0x100249ef 0x7b _L1W_DevLpcGetWSleepLen
+ 0x10024a6a 0x92 _L1w_DevLpcUpdateWakeFlg
+ 0x10024afc 0x14e _L1w_DevLpcSyncWkUpOpenRf
+ 0x10024c4a 0xa _L1w_DevSleepGetPiEndPos
+ 0x10024c54 0x7d _L1W_LPNoSleepAPeriod
+ 0x10024cd1 0x8f _L1W_DevLpcPwrPrintInfo
+ 0x10024d60 0x18 _L1w_DevSleepCloseIsAbleSleep
+ 0x10024d78 0x2a9 _L1W_DevSleepLpmInspect
+ 0x10025021 0x4f _L1w_DevLpcWakeTimeCheck
+ 0x10025070 0x9 _L1W_LPNoSleepEndSsfnInit
+ 0x10025079 0x5e _L1W_LPDataInit
+ 0x100250d7 0x71 _L1W_LPInit
+ 0x10025148 0x37 _L1W_LpcCfgSocWkupInt
+ 0x1002517f 0x1b _L1W_LpcDisSocWkupInt
+ 0x1002519a 0x16 _L1W_WakeupIsr
+ 0x100251b0 0x8 _L1W_GetNtSsfn
+ 0x100251b8 0x4 _L1w_DevSleepPreSyncPiOffset
+ 0x100251bc 0xd _L1W_DevSleepQueryAllowbit
+ 0x100251c9 0x335 _L1W_ModemLpcSleep
+ 0x100254fe 0x344 _L1W_ModemLpcWakeup
+ .text 0x10025842 0x1519 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x10025842 0x39 _L1w_DevDlsAfcReset
+ 0x1002587b 0x19 _L1w_DevDlsAfcInit
+ 0x10025894 0x56 _L1w_DevAfcBchCorrCalEachSlot
+ 0x100258ea 0x23 _L1w_DevAfcNormalToAfc
+ 0x1002590d 0x20 _L1w_DevAfcToNormal
+ 0x1002592d 0xf _L1w_DevAfcFormatCheck
+ 0x1002593c 0x6 _L1w_DevAfcSubFunc1ForAdd
+ 0x10025942 0x27 _L1w_DevAfcSubFunc2ForAdd
+ 0x10025969 0x75 _L1w_DevAfcAdd
+ 0x100259de 0x60 _L1w_DevAfcDiv
+ 0x10025a3e 0x24 _L1w_DevAfcMultip
+ 0x10025a62 0xf _L1w_DevAfcCompABS
+ 0x10025a71 0xfe _L1w_DevAfcCalcPhaseErr
+ 0x10025b6f 0x36 _L1w_DevAfcCalcFreqcenErr
+ 0x10025ba5 0x1c _L1w_DevAfcLockCheck
+ 0x10025bc1 0xa6 _L1w_DevAfcBchFoePostProc
+ 0x10025c67 0x44 _L1w_DevDlsAfcResultValid
+ 0x10025cab 0x31 _L1w_DevAfcFoeAdjResultLim
+ 0x10025cdc 0x42 _L1w_DevAfcFoeResultLimit
+ 0x10025d1e 0x1c _L1w_DevAfcIQFilterProc
+ 0x10025d3a 0x72 _L1w_DevAfcForBchProc
+ 0x10025dac 0x26 _L1w_DevAfcStateTransfer
+ 0x10025dd2 0x64 _L1w_DevAfcRxFoePostProc
+ 0x10025e36 0x13 _L1w_DevAfcCalcFingerPower
+ 0x10025e49 0xab _L1w_DevAfcFingerFoeAdp
+ 0x10025ef4 0x7b _L1w_DevAfcFingerSortByPeak
+ 0x10025f6f 0x27b _L1w_DevAfcForRxProc
+ 0x100261ea 0x27 _L1w_DevAfcSendFreqMsgToL1s
+ 0x10026211 0x29 _L1w_DevAfcBchReq
+ 0x1002623a 0x2c _L1w_DevAfcRxReq
+ 0x10026266 0x26 _L1w_DevAfcRxCrcFlagReq
+ 0x1002628c 0x28 _L1w_DevAfcStateChangeReq
+ 0x100262b4 0x97 _L1w_DevAfcRxDataAccu
+ 0x1002634b 0xa _L1w_DevAfcVcoTimeSet
+ 0x10026355 0xb5 _L1w_DevAfcCalcParam
+ 0x1002640a 0xd _L1w_DevAfcIsInStableSt
+ 0x10026417 0x11 _L1w_DevAfcRxCrcFlagProc
+ 0x10026428 0x37 _L1w_DevAfcLockHandle
+ 0x1002645f 0x4d _L1w_DevAfcNeedAdj
+ 0x100264ac 0x72 _L1w_DevAfcSaveStableVco
+ 0x1002651e 0x21 _L1w_DevAfcMasteStChange
+ 0x1002653f 0x11 _L1w_DevAfcGetRxCrc
+ 0x10026550 0x31 _L1w_DevAfcGetAfcCellEcIo
+ 0x10026581 0x43 _L1w_DevAfcRxDataReqProc
+ 0x100265c4 0x52 _L1w_DevAfcGetNCellAfcPt
+ 0x10026616 0xa _L1w_DevAfcGetSystemAfc
+ 0x10026620 0xb _L1w_DevAfcGetNCellAbsAfc
+ 0x1002662b 0x1b _L1w_DevAfcGetNCellRelativeAfc
+ 0x10026646 0x58 _L1w_DevAfcUpdateNCellAfc
+ 0x1002669e 0x8 _L1w_DevAfcSetWorkCellInfo
+ 0x100266a6 0xa _L1w_DevAfcGetWorkCellInfo
+ 0x100266b0 0x50 _L1w_DevAfcIsSystemAfc
+ 0x10026700 0xa2 _L1w_DevAfcNcellAfcPostProc
+ 0x100267a2 0x3 _L1w_DevAfcSetNCellAbsAfc
+ 0x100267a5 0xa5 _L1w_DevAfcRlsAloneProc
+ 0x1002684a 0x131 _L1w_DevAfcCalcRlOwnFoe
+ 0x1002697b 0xf _L1w_DevAfcClearNcellAfc
+ 0x1002698a 0x1e _L1w_DevAfcCalcFilterPara
+ 0x100269a8 0x66 _L1w_DevAfcDpaIqRotateProc
+ 0x10026a0e 0x1d _L1w_DevAfcNcellAdjLimit
+ 0x10026a2b 0xc _L1w_DevAfcNormDiffValue
+ 0x10026a37 0x11 _L1w_DevAfcSaveDpaInfo
+ 0x10026a48 0x38 _L1w_DevAfcSetDpaIqRotate
+ 0x10026a80 0x4f _L1w_DevAfcCalcSlotWeight
+ 0x10026acf 0x15 _L1w_DevAfcInitNcellData
+ 0x10026ae4 0x2e _L1w_DevAfcNcellUpByEcIo
+ 0x10026b12 0x1f _L1w_DevAfcRestartReq
+ 0x10026b31 0x22 _L1w_DevAfcRestartLockCheck
+ 0x10026b53 0x29 _L1w_DevAfcWriteBackVco
+ 0x10026b7c 0x4f _L1w_DevAfcSaveWMode
+ 0x10026bcb 0xa7 _L1w_DevAfcSlaveAfcMangement
+ 0x10026c72 0x15 _L1w_DevAfcLimitSlaveVco
+ 0x10026c87 0x15 _L1w_CleanSlaveAfcIRAMBuf
+ 0x10026c9c 0x32 _L1w_WriteMasterAfcInfo
+ 0x10026cce 0x20 _L1w_ReadMasterAfcInfo
+ 0x10026cee 0x6d _L1w_DevChangeAndUpdateAfc
+ .text 0x10026d5b 0xf2e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x10026d5b 0x129 _L1w_DevTpuRt1SampleCompst
+ 0x10026e84 0x77 _L1w_DevTpuReset
+ 0x10026efb 0x10 _L1w_DevTpuTaskIdTransForm
+ 0x10026f0b 0x5e _L1w_DevTpuAddFixedEvent
+ 0x10026f69 0x1a _L1w_DevTpuAddFixedCycleEvent
+ 0x10026f83 0x15 _L1w_DevTpuDelFixedCycleEvent
+ 0x10026f98 0x21 _L1w_DevTpuUpdateVarNtEvent
+ 0x10026fb9 0x20 _L1w_DevTpuUpdateVarRtEvent
+ 0x10026fd9 0xfd _L1w_DevTpuAddVarNtEvent
+ 0x100270d6 0xdf _L1w_DevTpuAddVarRtEvent
+ 0x100271b5 0x46 _L1w_DevTpuDelFixedEvent
+ 0x100271fb 0x62 _L1w_DevTpuDelVarNtEvent
+ 0x1002725d 0x3e _L1w_DevTpuDelVarRtEvent
+ 0x1002729b 0x65 _L1w_DevTpuGetRealTime
+ 0x10027300 0x8e _L1w_DevTpuGetRtForWakeUp
+ 0x1002738e 0x50 _L1w_DevTpuGetNetTime
+ 0x100273de 0xa4 _L1w_DevTpuGetAllTime
+ 0x10027482 0x80 _L1w_DevTpuNtFixedEventProc
+ 0x10027502 0xdd _L1w_DevTpuNtVarEventProc
+ 0x100275df 0xf6 _L1w_DevTpuRtEventProc
+ 0x100276d5 0x59 _L1w_DevTpuMacroAdjust
+ 0x1002772e 0x56 _L1w_DevTpuMicroAdjust
+ 0x10027784 0x1a _L1w_DevTpuMicroAdjustForSleep
+ 0x1002779e 0x56 _L1w_DevTpuMicroAdjSetPreSyncFlag
+ 0x100277f4 0x5 _L1w_DevTpuAdjEventProc
+ 0x100277f9 0xb _L1w_DevTpuSetDoff
+ 0x10027804 0x7 _L1w_DevTpuGetDoff
+ 0x1002780b 0xa _L1w_DevTpuSfn2Cfn
+ 0x10027815 0x25 _L1w_DevTpuCfn2Sfn
+ 0x1002783a 0x1b _L1w_DevTpuGetNtSSFN
+ 0x10027855 0x1c _L1w_DevTpuGetRtSSFN
+ 0x10027871 0x17 _L1w_DevTpuGetSSFN
+ 0x10027888 0xe _L1w_DevTpuGetCurCFN
+ 0x10027896 0x7 _L1w_DevTpuSfn2Ssfn
+ 0x1002789d 0x7 _L1w_DevTpuCfn2Ssfn
+ 0x100278a4 0x27 _L1w_DevTpuRt2Nt
+ 0x100278cb 0x69 _L1w_DevTpuAddCnt
+ 0x10027934 0x34 _L1w_DevTpuCalNt2RtOffset
+ 0x10027968 0x2c _L1w_DevTpuMicroSsfnJumpPatch
+ 0x10027994 0x7a _L1w_DevTpuCheckMicroSsfnJump
+ 0x10027a0e 0x21 _L1w_DevTpuMicroSsfnJumpPro
+ 0x10027a2f 0x77 _L1w_DevTpuCheckMicroSsfnBack
+ 0x10027aa6 0x1f _L1w_DevTpuMicroSsfnBackPro
+ 0x10027ac5 0x32 _L1w_DevTpuNtSSfnCfnUpdate
+ 0x10027af7 0x14 _L1w_DevTpuRtSSfnUpdate
+ 0x10027b0b 0x32 _L1w_DevTpuCalcNtUpdateTime
+ 0x10027b3d 0x31 _L1w_DevTpuCalcRtUpdateTime
+ 0x10027b6e 0x1e _L1w_DevTpuBase2Norm
+ 0x10027b8c 0x43 _L1w_DevTpuNorm2Base
+ 0x10027bcf 0x17 _L1w_DevTpuCalRt2NtOffset
+ 0x10027be6 0x27 _L1w_DevTpuNt2Rt
+ 0x10027c0d 0x7c _L1w_DevTpuSubCnt
+ .text 0x10027c89 0x9a4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x10027c89 0x6 _L1w_DevDbAfcAddrGet
+ 0x10027c8f 0x6 _L1w_DevDbIscpAddrGet
+ 0x10027c95 0x6f _L1w_DevDbRtxUpaRlIscpReport
+ 0x10027d04 0xa _L1w_DevDbRtxPcRlIscpReport
+ 0x10027d0e 0x7 _L1w_DevDbSetHsdpaInd
+ 0x10027d15 0xb _L1w_DevDbReSetHsdpaInd
+ 0x10027d20 0x3d _L1w_DevDbUpdateHsdpaInd
+ 0x10027d5d 0x6 _L1w_DevDbGetHsdpaInd
+ 0x10027d63 0x26 _L1w_DevDbRtxRxSirSet
+ 0x10027d89 0x26 _L1w_DevDbRtxRxSirGet
+ 0x10027daf 0x2d _L1w_DevDbBchWriteAfcData
+ 0x10027ddc 0x34 _L1w_DevAfcReadDataFromBch
+ 0x10027e10 0x3a9 _L1w_DevDlsAfcReadDataFromRx
+ 0x100281b9 0x43 _L1w_DevDbGetInitXValue
+ 0x100281fc 0x42 _L1w_DevDbGetInitYValue
+ 0x1002823e 0x1e _L1w_DevDbGetInitValue
+ 0x1002825c 0x45 _L1w_DevDbCodingPara
+ 0x100282a1 0x43 _L1w_DevDbTrchTtiMap
+ 0x100282e4 0x28 _L1w_DevDbTrchMaxMinTti
+ 0x1002830c 0x7 _L1w_DevDbTrchMaxTtiGet
+ 0x10028313 0x8 _L1w_DevDbTrchMinTtiGet
+ 0x1002831b 0x6 _L1w_DevDbGetPichCfg
+ 0x10028321 0x6 _L1w_DevDbGetPchCfg
+ 0x10028327 0x6 _L1w_DevDbGetFachCfg
+ 0x1002832d 0x6 _L1w_DevDbGetDldpchCfg
+ 0x10028333 0x6 _L1w_DevDbGetFdpchCfg
+ 0x10028339 0x32 _L1w_DevDbGetSchCodeGrp
+ 0x1002836b 0x3a _L1w_DevDbSaveCirData
+ 0x100283a5 0xb _L1w_DevDbClearCirData
+ 0x100283b0 0x6 _L1w_DevDbGetCirDataAddr
+ 0x100283b6 0x6 _L1w_DevDbGetFingerMaskBufAddr
+ 0x100283bc 0x1b _L1w_DevDbRtxReportToMac
+ 0x100283d7 0x21 _L1w_DevDbHspaReportToMac
+ 0x100283f8 0x1d _L1w_DevDbSetHsdpaToMacInfo
+ 0x10028415 0x21 _L1w_DevDbSetHsupaToMacInfo
+ 0x10028436 0xb _L1w_DevDbClrHspaToMacInfo
+ 0x10028441 0x1 _L1w_DevDbPcReportToMac
+ 0x10028442 0x9 _L1w_SchedResIsBand8Freq
+ 0x1002844b 0x15 _L1w_DevDbGetAiSignSeries
+ 0x10028460 0x27 _L1w_DevDbPiValHandle
+ 0x10028487 0x26 _L1w_DevDbCalcPiVal
+ 0x100284ad 0x1c _L1w_DevRtxRxPiAiFloatAdd
+ 0x100284c9 0x6 _L1w_DevDbGetHspaPlusFachPsCmd
+ 0x100284cf 0x12 _L1w_DevDbPsSubFrmInt
+ 0x100284e1 0x24 _L1w_DevDbSubFrmInt
+ 0x10028505 0xe _L1w_DevDbSetHarqFlag
+ 0x10028513 0xc _L1w_DevDbInitHsdpaAntSwitchInfo
+ 0x1002851f 0x7 _L1w_DevDbSetHsdpaAntSwitchFlg
+ 0x10028526 0x7 _L1w_DevDbGetHsdpaAntSwitchFlg
+ 0x1002852d 0x8 _L1w_DevDbSetHsdpaAntNum
+ 0x10028535 0x8 _L1w_DevDbGetHsdpaAntNum
+ 0x1002853d 0x1a _L1w_DevDbHsdpaJudge2Rto1R
+ 0x10028557 0x1c _L1w_DevDbHsdpaJudge1Rto2R
+ 0x10028573 0x9 _L1w_DevDbAddHsscchCnt
+ 0x1002857c 0x17 _L1w_DevDbHsscchSchedCnt
+ 0x10028593 0x9 _L1w_DevDbAddHsscchCorrectCnt
+ 0x1002859c 0xa _L1w_DevDbAddHsscchErrorCnt
+ 0x100285a6 0x9 _L1w_DevDbClearHsscchErrorCnt
+ 0x100285af 0xa _L1w_DevDbAddSnrHighCnt
+ 0x100285b9 0x9 _L1w_DevDbClearSnrHighCnt
+ 0x100285c2 0xa _L1w_DevDbAddSnrLowCnt
+ 0x100285cc 0x9 _L1w_DevDbClearSnrLowCnt
+ 0x100285d5 0xd _L1w_DevDbSet1R2RState
+ 0x100285e2 0xc _L1w_DevDbSetLas1R2RState
+ 0x100285ee 0x11 _L1w_DevDbIs1RTo2R
+ 0x100285ff 0x7 _L1w_DevDbGet1R2RState
+ 0x10028606 0xb _L1w_DevDbGet1R2RAntNum
+ 0x10028611 0x7 _L1w_DevSetSystemAntNum
+ 0x10028618 0x7 _L1w_DevGetSystemAntNum
+ 0x1002861f 0x7 _L1w_DevDbSetTxPower
+ 0x10028626 0x7 _L1w_DevDbGetTxPower
+ .text 0x1002862d 0x1833 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x1002862d 0xf _L1w_DevRtxRxInit
+ 0x1002863c 0x29 _L1w_DevRtxRxReset
+ 0x10028665 0x87 _L1w_DevRtxRxAddTpuEvent
+ 0x100286ec 0x36 _L1w_DevRtxRxDelTpuEvent
+ 0x10028722 0x1c _L1w_DevRtxRxDelFactorTpuInt
+ 0x1002873e 0x80 _L1w_DevRtxRxSwapFinger
+ 0x100287be 0x10f _L1w_DevRtxRxFingerSort
+ 0x100288cd 0x72 _L1w_DevRtxRxFingerSelect
+ 0x1002893f 0x75 _L1w_DevRtxRxFingerMsgHandle
+ 0x100289b4 0x27 _L1w_DevRtxOfflinePichRelHanlde
+ 0x100289db 0x38 _L1w_DevRtxSetPchCfgState
+ 0x10028a13 0x65 _L1w_DevRtxRxPchCfgReqHandle
+ 0x10028a78 0x5f _L1w_DevRtxRxCompareConfigTime
+ 0x10028ad7 0x1a1 _L1w_DevRtxRxOffLinePichCfg
+ 0x10028c78 0xcd _L1w_DevRtxRxPichCfgMsgHandle
+ 0x10028d45 0x3e _L1w_DevRtxRxPichRelMsgHandle
+ 0x10028d83 0x187 _L1w_DevRtxRxPchCfgMsgHandle
+ 0x10028f0a 0x26 _L1w_DevRtxRxPchRelMsgHandle
+ 0x10028f30 0x157 _L1w_DevRtxRxAichCfgMsgHandle
+ 0x10029087 0x38 _L1w_DevRtxRxAichRelMsgHandle
+ 0x100290bf 0x123 _L1w_DevRtxRxFachCfgMsgHandle
+ 0x100291e2 0x38 _L1w_DevRtxRxFachRelMsgHandle
+ 0x1002921a 0x219 _L1w_DevRtxRxDlDpchCfgMsgHandle
+ 0x10029433 0x36 _L1w_DevRtxRxDlDpchRelMsgHandle
+ 0x10029469 0x119 _L1w_DevRtxRxFdpchCfgMsgHandle
+ 0x10029582 0x87 _L1w_DevRtxRxPlusCpCfgMsgHandle
+ 0x10029609 0x38 _L1w_DevRtxRxFdpchRelMsgHandle
+ 0x10029641 0x3 _L1w_DevRtxRxPlusFachTpuHandle
+ 0x10029644 0x1cc _L1w_DevRtxRxPlusFachCfg
+ 0x10029810 0x15b _L1w_DevRtxRxCmCfgMsgHandle
+ 0x1002996b 0x26 _L1w_DevRtxRxCmAbortMsgHandle
+ 0x10029991 0x5a _L1w_DevRtxRxHsscchCfgMsgHandle
+ 0x100299eb 0x51 _L1w_DevRtxRxEagchCfgMsgHandle
+ 0x10029a3c 0x9 _L1w_DevRtxRxEagchRelMsgHandle
+ 0x10029a45 0x63 _L1w_DevRtxRxRgHiCfgMsgHandle
+ 0x10029aa8 0x9 _L1w_DevRtxRxRgHiRelMsgHandle
+ 0x10029ab1 0x45 _L1w_DevRtxRxDrxMsgHandle
+ 0x10029af6 0x12e _L1w_DevRtxRxMsgHandle
+ 0x10029c24 0x6 _L1w_DevRtxRxTrchInfoGet
+ 0x10029c2a 0x16 _L1w_DevRtxRxTurboUse
+ 0x10029c40 0xed _L1w_DevRtxRxDlStatEng
+ 0x10029d2d 0x6 _L1w_DevRtxRxDpchPhyInfoGet
+ 0x10029d33 0x6 _L1w_DevRtxRxIntCfgParaGet
+ 0x10029d39 0xf _L1w_DevRtxRxDrxSlotCheck
+ 0x10029d48 0x28 _L1w_DevRtxRxCmSlotCheck
+ 0x10029d70 0x8c _L1w_DevRtxRxCpCmSlotCheck
+ 0x10029dfc 0x19 _L1w_DevRtxRxGetSlotId
+ 0x10029e15 0xa _L1w_DevRtxRxDrxSlotClr
+ 0x10029e1f 0x6 _L1w_DevRtxRxTpcInfoGet
+ 0x10029e25 0x6 _L1w_DevRtxRxSccpchPhyInfoGet
+ 0x10029e2b 0x6 _L1w_DevRtxRxAgchPhyInfoGet
+ 0x10029e31 0x6 _L1w_DevRtxRxCfgInfoGet
+ 0x10029e37 0xd _L1w_DevRtxRxCfgRlCntGet
+ 0x10029e44 0x1c _L1w_DevRtxRxRlPrimSrcGet
+ .text 0x10029e60 0x516 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_ds.o)
+ 0x10029e60 0xd _L1w_DevRtxRxDsReset
+ 0x10029e6d 0x25 _L1w_DevRtxDsMsgHandle
+ 0x10029e92 0x72 _L1w_DevRtxDsStageHandle
+ 0x10029f04 0x84 _L1w_DevRtxDsStart
+ 0x10029f88 0x9 _L1w_DevRtxDsStop
+ 0x10029f91 0x3d _L1w_DevRtxDsCrcCalc
+ 0x10029fce 0x62 _L1w_DevRtxDsStep1Handle
+ 0x1002a030 0x7c _L1w_DevRtxDsQosStep1
+ 0x1002a0ac 0x41 _L1w_DevRtxDsStep2Handle
+ 0x1002a0ed 0xcc _L1w_DevRtxDsQosStep2
+ 0x1002a1b9 0x2a _L1w_DevRtxRxDsPostInd
+ 0x1002a1e3 0x3d _L1w_DevRtxDsInsyncInd
+ 0x1002a220 0x41 _L1w_DevRtxDsOutsyncInd
+ 0x1002a261 0x19 _L1w_DevRtxRxDsIsCrcExist
+ 0x1002a27a 0x1f _L1w_DevRtxRxDsIsCrcOk
+ 0x1002a299 0x16 _L1w_DevRtxRxDsCurTtiParaClr
+ 0x1002a2af 0x16 _L1w_DevRtxRxDsLast20CrcFalse
+ 0x1002a2c5 0xb _L1w_DevRtxRxDsIsPostOk
+ 0x1002a2d0 0x14 _L1w_DevRtxRxDsIsN312Ok
+ 0x1002a2e4 0x31 _L1w_DevRtxRxDsSetTpcData
+ 0x1002a315 0x1d _L1w_DevRtxRxDsGetSyncSt
+ 0x1002a332 0x44 _L1w_DevRtxRxDsUlSendState
+ .text 0x1002a376 0x37c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x1002a376 0xe _L1w_DrvRfcSingedDataMaxLimit
+ 0x1002a384 0xc _L1w_DrvRfcUnSingedDataMaxLimit
+ 0x1002a390 0x26 _L1w_DrvRfcS16ToFastFloat
+ 0x1002a3b6 0x3e _L1w_DrvRfcS16FastFloatDiv
+ 0x1002a3f4 0xd _L1w_DrvRfcFastFloatToS16
+ 0x1002a401 0x3e _L1w_DrvRfcAgcgain2ManExp
+ 0x1002a43f 0x71 _L1w_DrvRfcDcCalcSingleCh
+ 0x1002a4b0 0x29 _L1w_DrvRfcDcCalc
+ 0x1002a4d9 0x37 _L1w_DrvRfcDcSet
+ 0x1002a510 0x1c _L1w_DevRfcDcEstEn
+ 0x1002a52c 0xac _L1w_DrvRfcIQCalcSingleCh
+ 0x1002a5d8 0x2e _L1w_DrvRfcIQSet
+ 0x1002a606 0x11 _L1w_DrvRfcIQCalc
+ 0x1002a617 0x4f _L1w_DrvRfcDagcCalc
+ 0x1002a666 0x8c _L1w_DrvRfcDagcSet
+ .text 0x1002a6f2 0x421 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_piai.o)
+ 0x1002a6f2 0xa _L1w_DrvPIAIClkGateEnable
+ 0x1002a6fc 0xa _L1w_DrvPIAIClkGateDisable
+ 0x1002a706 0x10 _L1w_DrvPIAISttdCfg
+ 0x1002a716 0xc _L1w_DrvAiOnLineEn
+ 0x1002a722 0xa _L1w_DrvAIonLineDisable
+ 0x1002a72c 0xc _L1w_DrvPIAfcoffLineEnable
+ 0x1002a738 0x12 _L1w_DrvPIAfcoffLineDisable
+ 0x1002a74a 0xf _L1w_DrvPiAfcIntModeCfg
+ 0x1002a759 0xe _L1w_DrvGetPiAiEnPara
+ 0x1002a767 0x9 _L1w_DrvGetPiAiIntMode
+ 0x1002a770 0xe _L1w_DrvGetConfigState
+ 0x1002a77e 0xf _L1w_DrvPiAIFirOrderCfg
+ 0x1002a78d 0x21 _L1w_DrvPiSysmbolLenCfg
+ 0x1002a7ae 0x9 _L1w_DrvAlphaCfg
+ 0x1002a7b7 0xa _L1w_DrvAfcCompensateEnable
+ 0x1002a7c1 0xa _L1w_DrvAfcCompensateDisable
+ 0x1002a7cb 0x14 _L1w_DrvAfcRotateParaCfg
+ 0x1002a7df 0xd _L1w_DrvPiAiFingerParaCfg
+ 0x1002a7ec 0x16 _L1w_DrvPiOffsetCfg
+ 0x1002a802 0x23 _L1w_DrvPiAiOvsfCfg
+ 0x1002a825 0xf _L1w_DrvAfcBestFingerIndexCfg
+ 0x1002a834 0x16 _L1w_DrvAiSeqIndexCfg
+ 0x1002a84a 0xa _L1w_DrvPiAiCfgOver
+ 0x1002a854 0x15 _L1w_DrvReadCpichPower
+ 0x1002a869 0xd _L1w_DrvReadAiResult
+ 0x1002a876 0x3b _L1w_DrvReadConfigTime
+ 0x1002a8b1 0x3e _L1w_DrvSetConfigTime
+ 0x1002a8ef 0x1f _L1w_DrvPiAiReadCpichRam
+ 0x1002a90e 0xa _L1w_DrvPiAiReadAiSymbolRam
+ 0x1002a918 0x1b _L1w_DrvPiAiReadSymbolRam
+ 0x1002a933 0xa _L1w_DrvEAiReadAmRam
+ 0x1002a93d 0x18 _L1w_DrvAiReadAmRam
+ 0x1002a955 0xff _L1w_DrvPiAiAichCfg
+ 0x1002aa54 0x12 _L1w_DrvPiAiAichRel
+ 0x1002aa66 0x82 _L1w_DrvOffPichCfg
+ 0x1002aae8 0x2b _L1w_DrvOffPichRel
+ .text 0x1002ab13 0x2b7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_sleep.o)
+ 0x1002ab13 0x9 _L1w_DrvSleepLpmCtrPwrOn
+ 0x1002ab1c 0x1c _L1w_DrvLpcModemIntCtrl
+ 0x1002ab38 0x3d _L1w_DrvLpcLpmConfPosCal
+ 0x1002ab75 0x38 _L1W_DrvLpcCfgSocWkupInt
+ 0x1002abad 0x15 _L1W_DrvLpcCfgModemWkupInt
+ 0x1002abc2 0xe _L1w_DrvLpcModemWakeUpIntCtrl
+ 0x1002abd0 0xe _L1w_DrvLpcSocWakeUpIntCtrl
+ 0x1002abde 0x17 _L1w_DrvLpcLpmSoftReset
+ 0x1002abf5 0x1a _L1w_DrvLpcClearInt
+ 0x1002ac0f 0xe _L1w_DrvLpcLpmSfIntCtrl
+ 0x1002ac1d 0x9 _L1w_DrvLpcIsLpmSfIntEn
+ 0x1002ac26 0x8c _L1w_DrvLpcSetLpmFrmInt
+ 0x1002acb2 0x2b _L1w_DrvLpcSetLpmAdjustFactor
+ 0x1002acdd 0x87 _L1w_DrvLpcLpmIntPwrCtrl
+ 0x1002ad64 0x1f _L1w_DrvLpcGetWNtTimeFromLpm
+ 0x1002ad83 0x2a _L1w_DrvLpcIcpSendForPsm
+ 0x1002adad 0xe _L1w_DrvLpcSetCampOnFlg
+ 0x1002adbb 0x8 _L1w_DrvLpcSetSleepFlag
+ 0x1002adc3 0x7 _L1w_DrvLpcGetSleepFlag
+ .text 0x1002adca 0x39d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_csr.o)
+ 0x1002adca 0x1c _L1_DrvCsrInit
+ 0x1002ade6 0x30 _L1_DrvCsrReset
+ 0x1002ae16 0x1c _L1w_DevCsrStep1Reset
+ 0x1002ae32 0x5f _L1w_DrvCsrTopCfg
+ 0x1002ae91 0x82 _L1w_DrvCsrSlotSyncCfg
+ 0x1002af13 0x4b _L1w_DrvCsrIcCfg
+ 0x1002af5e 0x1 _L1w_DrvCsrFrameSyncCfg2A
+ 0x1002af5f 0x1 _L1w_DrvCsrFrameSyncCfg2B
+ 0x1002af60 0x1 _L1w_DrvCsrScrambleSrchCfg
+ 0x1002af61 0x66 _L1w_DrvCsrFullscanKscCfg
+ 0x1002afc7 0x44 _L1w_DrvCsrFullscanUnKscCfg
+ 0x1002b00b 0x83 _L1w_DrvCsrFullscanCfg
+ 0x1002b08e 0x94 _L1w_DrvCsrReadSlotSync
+ 0x1002b122 0x1 _L1w_DrvCsrStep1ReadMaxPos
+ 0x1002b123 0x1 _L1w_DrvCsrReadFrameSync2A
+ 0x1002b124 0x1 _L1w_DrvCsrReadFrameSync2B
+ 0x1002b125 0x1d _L1w_DrvCsrCmpFloat
+ 0x1002b142 0x1 _L1w_DrvCsrReadScrambleCode
+ 0x1002b143 0x24 _L1w_DrvCsrReadFs
+ .text 0x1002b167 0x306 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x1002b167 0x9 _L1w_DrvSetTop01GdtrHdtrBitSet
+ 0x1002b170 0xa _L1w_DrvSetTop01GdtrHdtrBitclr
+ 0x1002b17a 0x9 _L1w_DrvSetTopEDmaIntBypassBitSet
+ 0x1002b183 0xa _L1w_DrvSetTopEDmaIntBypassBitclr
+ 0x1002b18d 0x1c _L1w_DrvResetTopViterbi
+ 0x1002b1a9 0x6 _L1w_DrvGetTop0OSoftResetRegAddr
+ 0x1002b1af 0x9 _L1w_DrvTop00SoftResetBitSet
+ 0x1002b1b8 0xa _L1w_DrvTop00SoftResetBitClr
+ 0x1002b1c2 0x9 _L1w_DrvTop10TpuRakeIntMaskBitSet
+ 0x1002b1cb 0xa _L1w_DrvTop10TpuRakeIntMaskBitClr
+ 0x1002b1d5 0x9 _L1w_DrvTop11RakeDfeRfcIntMaskBitSet
+ 0x1002b1de 0xa _L1w_DrvTop11RakeDfeRfcIntMaskBitClr
+ 0x1002b1e8 0x9 _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitSet
+ 0x1002b1f1 0xa _L1w_DrvTop12TpuCsrAdrHsscchIntMaskBitClr
+ 0x1002b1fb 0x9 _L1w_DrvTop13CsrDtrPsrIntMaskBitSet
+ 0x1002b204 0xa _L1w_DrvTop13CsrDtrPsrIntMaskBitClr
+ 0x1002b20e 0x9 _L1w_DrvTop14TpuRakeIntStateMaskBitSet
+ 0x1002b217 0xa _L1w_DrvTop14TpuRakeIntStateMaskBitClr
+ 0x1002b221 0x9 _L1w_DrvTop15RakeDfeRfcIntStateMaskBitSet
+ 0x1002b22a 0xa _L1w_DrvTop15RakeDfeRfcIntStateMaskBitClr
+ 0x1002b234 0x9 _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitSet
+ 0x1002b23d 0xa _L1w_DrvTop16TpuCsrAdrHsscchIntStateMaskBitClr
+ 0x1002b247 0x9 _L1w_DrvTop17CsrDtrPsrIntStateMaskBitSet
+ 0x1002b250 0xa _L1w_DrvTop17CsrDtrPsrIntStateMaskBitClr
+ 0x1002b25a 0xe _L1w_DrvTopCsrDtrPsrIntOpen
+ 0x1002b268 0xe _L1w_DrvTopCsrDtrPsrIntClose
+ 0x1002b276 0x8 _L1w_DrvTopGetTop10High16b
+ 0x1002b27e 0x7 _L1w_DrvTopGetTop10Low16b
+ 0x1002b285 0x8 _L1w_DrvTopGetTop14High16b
+ 0x1002b28d 0x7 _L1w_DrvTopGetTop14Low16b
+ 0x1002b294 0x7 _L1w_DrvTopGetTop11Low16b
+ 0x1002b29b 0x7 _L1w_DrvTopGetTop15Low16b
+ 0x1002b2a2 0x9 _L1w_DrvTopLpcOpenGateClk
+ 0x1002b2ab 0xa _L1w_DrvTopLpcCloseGateClk
+ 0x1002b2b5 0xb _L1w_DrvTopClkIsOpen
+ 0x1002b2c0 0x13 _L1W_DrvTopLpcRegSave
+ 0x1002b2d3 0x23 _L1W_DrvTopLpcRegRestore
+ 0x1002b2f6 0x26 _L1w_DrvMcuIntMask
+ 0x1002b31c 0x26 _L1w_DrvMcuIntUnmask
+ 0x1002b342 0xa _L1w_DrvMcuIntIreqClr
+ 0x1002b34c 0x5f _L1w_DrvTopIntMask
+ 0x1002b3ab 0x4f _L1w_DrvTopIntMaskRestore
+ 0x1002b3fa 0x1a _L1w_DrvTopIntClr
+ 0x1002b414 0x59 _L1w_DrvTopIntEng
+ .text 0x1002b46d 0x20d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x1002b46d 0x25 _L1w_DrvTpuSoftResetCfg
+ 0x1002b492 0x39 _L1w_DrvTpuReset
+ 0x1002b4cb 0x28 _L1w_DrvTpuInit
+ 0x1002b4f3 0x39 _L1w_DrvTpuNTIntEnable
+ 0x1002b52c 0x3a _L1w_DrvTpuNTIntDisable
+ 0x1002b566 0x14 _L1w_DrvTpuRTIntEnable
+ 0x1002b57a 0x15 _L1w_DrvTpuRTIntDisable
+ 0x1002b58f 0x11 _L1w_DrvTpuLatchTimeCfg
+ 0x1002b5a0 0x8 _L1w_DrvTpuRdNTTiming
+ 0x1002b5a8 0x8 _L1w_DrvTpuRdRTTiming
+ 0x1002b5b0 0x11 _L1w_DrvTpuNTIntParaCfg
+ 0x1002b5c1 0x11 _L1w_DrvTpuRTIntParaCfg
+ 0x1002b5d2 0xa _L1w_DrvTpuMacroIntDisble
+ 0x1002b5dc 0x7 _L1w_DrvTpuMicroAdjParaCfg
+ 0x1002b5e3 0x8 _L1w_DrvTpuGetNT2RtOffset
+ 0x1002b5eb 0x8 _L1w_DrvTpuGetNTssfn
+ 0x1002b5f3 0x8 _L1w_DrvTpuGetRTssfn
+ 0x1002b5fb 0x32 _L1w_DrvTpuMacroAdjParaCfg
+ 0x1002b62d 0x28 _L1W_DrvTpuLpcRegRestore
+ 0x1002b655 0x25 _L1W_DrvTpuLpcRegSave
+ .text 0x1002b67a 0x431 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tx.o)
+ 0x1002b67a 0x26 _L1w_DrvTxReset
+ 0x1002b6a0 0xb _L1w_DrvTxClear
+ 0x1002b6ab 0x16 _L1w_DrvTxDpxchEnCfg
+ 0x1002b6c1 0x10 _L1w_DrvTxRamLpEnCfg
+ 0x1002b6d1 0x10 _L1w_DrvTxScramFixRotateEnCfg
+ 0x1002b6e1 0x10 _L1w_DrvTxModeTypeCfg
+ 0x1002b6f1 0x10 _L1w_DrvTxGateClkDisableCfg
+ 0x1002b701 0x2b _L1w_DrvTxDpxchOffsetCfg
+ 0x1002b72c 0x31 _L1w_DrvTxPreamblePhchCfg
+ 0x1002b75d 0xa _L1w_DrvTxPreamblePhchDisable
+ 0x1002b767 0x2d _L1w_DrvTxPrachPhchCfg
+ 0x1002b794 0xa _L1w_DrvTxPrachPhchEnable
+ 0x1002b79e 0xa _L1w_DrvTxPrachPhchDisable
+ 0x1002b7a8 0x10 _L1w_DrvTxSampleTxRegTimeCfg
+ 0x1002b7b8 0x10 _L1w_DrvTxDpcchFbiCfg
+ 0x1002b7c8 0x16 _L1w_DrvTxDpcchTpcCfg
+ 0x1002b7de 0x43 _L1w_DrvTxDpxchPhchCfg
+ 0x1002b821 0x30 _L1w_DrvTxPrachSpreaderCfg
+ 0x1002b851 0x22 _L1w_DrvTxScramblerCfg
+ 0x1002b873 0x2a _L1w_DrvTxDpxchOrPrachPwrCfg
+ 0x1002b89d 0x18 _L1w_DrvTxHsDpcchPwrCfg
+ 0x1002b8b5 0x18 _L1w_DrvTxEdpcchPwrCfg
+ 0x1002b8cd 0x49 _L1w_DrvTxEdpdchPwrCfg
+ 0x1002b916 0xc _L1w_DrvTxPreamblePwrCfg
+ 0x1002b922 0x111 _L1_DrvTxRfcTest
+ 0x1002ba33 0x13 _L1w_DrvGetTxDpxchOffset
+ 0x1002ba46 0x39 _L1w_DrvTxCordicAdjustCfg
+ 0x1002ba7f 0x9 _L1w_DrvTxCordicDisable
+ 0x1002ba88 0x23 _L1w_DrvTxCordicEnable
+ .text 0x1002baab 0x381 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x1002baab 0x27 _L1w_DrvMeasReset
+ 0x1002bad2 0x57 _L1w_DrvMeasCfgCellCode
+ 0x1002bb29 0x19 _L1w_DrvMeasParaOverCfg
+ 0x1002bb42 0x6e _L1w_DrvMeasCfgSpsrStartTime
+ 0x1002bbb0 0x8 _L1w_DrvMeasCfgClkGating
+ 0x1002bbb8 0x60 _L1w_DrvMeasReadResult
+ 0x1002bc18 0x1a _L1w_DrvMeasReadAgc
+ 0x1002bc32 0xa _L1w_DrvMeasReadSpsrIntSeqNum
+ 0x1002bc3c 0x5f _L1w_DrvMeasCompareConfigTime
+ 0x1002bc9b 0x14 _L1w_DrvMeasReadSpsrstatus
+ 0x1002bcaf 0x8 _L1w_DrvMeasOffLineRamparaCfg
+ 0x1002bcb7 0x8 _L1w_DrvMeasOffLineRamMrtrCfg
+ 0x1002bcbf 0x9 _L1w_DrvMeasMeasBufUpdateCfg
+ 0x1002bcc8 0x8 _L1w_DrvMeasWorkModeCfg
+ 0x1002bcd0 0x8 _L1w_DrvMeasOnLineStartSpsrCfg
+ 0x1002bcd8 0xe _L1w_DrvMeasOnLineGetSpsrCfg
+ 0x1002bce6 0x10 _L1w_DrvMeasOnLineAgc0paraCfg
+ 0x1002bcf6 0x10 _L1w_DrvMeasOnLineAgc1paraCfg
+ 0x1002bd06 0x35 _L1w_DrvMeasOnLineAgc0StartMrtrCfg
+ 0x1002bd3b 0x35 _L1w_DrvMeasOnLineAgc1StartMrtrCfg
+ 0x1002bd70 0x4f _L1w_DrvMeasFrameBoundaryCfg
+ 0x1002bdbf 0x2d _L1w_DrvMeasSpsrParaCfg
+ 0x1002bdec 0x1c _L1w_DrvMeasCellSttdModeCfg
+ 0x1002be08 0xa _L1w_DrvMeasClkGatingCfg
+ 0x1002be12 0x9 _L1w_DrvMeasSoftPatternCfg
+ 0x1002be1b 0x9 _L1w_DrvMeasPatternModeCfg
+ 0x1002be24 0x8 _L1w_DrvMeasCfgOfflineSpsrStartTime
+ .text 0x1002be2c 0x55d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsupa.o)
+ 0x1002be2c 0x22 _L1w_DrvHsupaEutrEnable
+ 0x1002be4e 0xa _L1w_DrvHsupaEutrDisable
+ 0x1002be58 0xe _L1w_DrvHsupaEutrSoftRst
+ 0x1002be66 0x13 _L1w_DrvHsupaEutrHarqRamMode
+ 0x1002be79 0x10 _L1w_DrvHsupaEutrHarqId
+ 0x1002be89 0xb _L1w_DrvHsupaEutrTtiTwoFlg
+ 0x1002be94 0xb _L1w_DrvHsupaEutrTbSize
+ 0x1002be9f 0x47 _L1w_DrvHsupaEutrCodeSize
+ 0x1002bee6 0x3e _L1w_DrvHsupaEutrPhchPara
+ 0x1002bf24 0x2d _L1w_DrvHsupaEutrRmSysPara
+ 0x1002bf51 0x2d _L1w_DrvHsupaEutrRmP1Para
+ 0x1002bf7e 0x2d _L1w_DrvHsupaEutrRmP2Para
+ 0x1002bfab 0x55 _L1w_DrvHsupaEutrInterPara
+ 0x1002c000 0x60 _L1w_DrvHsupaEutrConfig
+ 0x1002c060 0xb _L1w_DrvHsupaEutrReadHarqStatus
+ 0x1002c06b 0x23 _L1w_DrvHsupaEtxEnable
+ 0x1002c08e 0x12 _L1w_DrvHsupaEtxDisable
+ 0x1002c0a0 0x19 _L1w_DrvHsupaEtxCfgTti
+ 0x1002c0b9 0x2a _L1w_DrvHsupaCfgEtxInt
+ 0x1002c0e3 0x12 _L1w_DrvHsupaTopEtxIntEnable
+ 0x1002c0f5 0xb _L1w_DrvHsupaEtxDisInt
+ 0x1002c100 0x1b _L1w_DrvHsupaTopMaskEtxInt
+ 0x1002c11b 0x31 _L1w_DrvHsupaRakeReadRgHi
+ 0x1002c14c 0xa _L1w_DrvHsupaCalLogTwo
+ 0x1002c156 0x42 _L1w_DrvHsupaEtxInterPara
+ 0x1002c198 0x34 _L1w_DrvHsupaEtxChCfgReg2
+ 0x1002c1cc 0x54 _L1w_DrvHsupaEtxEdpxchPara
+ 0x1002c220 0x25 _L1w_DrvHsupaEtxSpreadReg
+ 0x1002c245 0x29 _L1w_DrvHsupaEtxConf
+ 0x1002c26e 0xb _L1w_DrvHsupaEtxReadTtiCnt
+ 0x1002c279 0x20 _L1w_DrvHsupaTopGetIntState
+ 0x1002c299 0x1 _L1w_DrvHsupaTopMaskEutrInt
+ 0x1002c29a 0xf _L1w_DrvHsupaTopMaskRgHiState
+ 0x1002c2a9 0xf _L1w_DrvHsupaTopMaskRgHiInt
+ 0x1002c2b8 0x17 _L1w_DevHsupaTopMaskAgInt
+ 0x1002c2cf 0x2 _L1w_DrvHsupaTopMaskRgchHichInt
+ 0x1002c2d1 0x23 _L1w_DrvHsupaMaskInt
+ 0x1002c2f4 0x2d _L1w_DrvHsupaTopEagchRst
+ 0x1002c321 0x7 _L1w_DrvHsupaRdAgIntStateMask
+ 0x1002c328 0x7 _L1w_DrvHsupaWtAgIntStateMask
+ 0x1002c32f 0x7 _L1w_DrvHsupaRdAgIntEnable
+ 0x1002c336 0x7 _L1w_DrvHsupaWtAgIntEnable
+ 0x1002c33d 0x7 _L1w_DrvHsupaRdRgHiIntStateMask
+ 0x1002c344 0x7 _L1w_DrvHsupaWtRgHiIntStateMask
+ 0x1002c34b 0x7 _L1w_DrvHsupaRdRgHiIntEnable
+ 0x1002c352 0x7 _L1w_DrvHsupaWtRgHiIntEnable
+ 0x1002c359 0x17 _L1w_DrvHsupaEnableAgInt
+ 0x1002c370 0x13 _L1w_DrvHsupaPcEtxEdpdchDisable
+ 0x1002c383 0x6 _L1w_DrvEutrGetRamAddr
+ .text 0x1002c389 0x506 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x1002c389 0x1 _L1w_DrvDpramEngDisplay
+ 0x1002c38a 0x4a _L1w_DrvDpramStructInit
+ 0x1002c3d4 0x25 _L1w_DrvDpramIsEmpty
+ 0x1002c3f9 0x42 _L1w_DrvDpramReadMsg
+ 0x1002c43b 0x1 _L1w_DrvDpramUpdateMsgPos
+ 0x1002c43c 0x5 _L1w_DrvDpramQueMemRead
+ 0x1002c441 0x37 _L1w_DrvDpramWriteMsg
+ 0x1002c478 0x23 _L1w_DrvDpramGetRdDataPtr
+ 0x1002c49b 0x1f _L1w_DrvDpramUpdateRdDataPos
+ 0x1002c4ba 0x24 _L1w_DrvDpramTxReadClearData
+ 0x1002c4de 0x31 _L1w_DrvDpramGetWrDataPtr
+ 0x1002c50f 0x8 _L1w_DrvDpramGetWrCnt
+ 0x1002c517 0x2c _L1w_DrvDpramUpdateWrDataPos
+ 0x1002c543 0x1a _L1w_DrvICPSendForPsSched
+ 0x1002c55d 0xa _L1w_DrvDpramIsD2AEmpty
+ 0x1002c567 0xa _L1w_DrvDpramSleepCheck
+ 0x1002c571 0x8 _L1w_DrvDpramWriteSfnDpramFlg
+ 0x1002c579 0x7 _L1w_DrvDpramWriteDoff2Dpram
+ 0x1002c580 0x7 _L1w_DrvDpramReadEdcpIntState
+ 0x1002c587 0xa _L1w_DrvDpramClrEdcpIntState
+ 0x1002c591 0x7 _L1w_DrvDpramClrIcpIntState
+ 0x1002c598 0xa _L1w_DrvDpramMaskIcpInt
+ 0x1002c5a2 0x9 _L1w_DrvDpramDemaskIcpInt
+ 0x1002c5ab 0x49 _L1w_DrvDpramPrintLog
+ 0x1002c5f4 0x104 _L1w_DrvDpramUpdateTpu
+ 0x1002c6f8 0x26 _L1w_DrvDpramWriteGrantHarq
+ 0x1002c71e 0x26 _L1w_DrvDpramWriteUlPower
+ 0x1002c744 0x41 _L1w_DrvDpramGetEutrCtrlInfo
+ 0x1002c785 0xa _L1w_DrvDpramSetRachDchTransFlg
+ 0x1002c78f 0xa _L1w_DrvDpramGetRachDchTransFlg
+ 0x1002c799 0x20 _L1w_DrvDpramSetUpaTransInfo
+ 0x1002c7b9 0x1f _L1w_DrvDpramGetGrantMonitorReq
+ 0x1002c7d8 0xe _L1w_DrvDpramHsupaSetActiveInfos
+ 0x1002c7e6 0xa _L1w_DrvDpramSetCmPattern
+ 0x1002c7f0 0x9 _L1w_DrvDpramSetUph
+ 0x1002c7f9 0x2f _L1w_DrvDpramWriteEtfcRestrictInfo
+ 0x1002c828 0x3e _L1w_DrvDpramWriteCmNtrInfo
+ 0x1002c866 0x29 _L1w_DrvDpramGetEdchHarqId
+ .text 0x1002c88f 0x1984 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x1002c88f 0x81 _L1w_DrvRxTpcPlCombTimeInit
+ 0x1002c910 0x83 _L1w_DrvRxInit
+ 0x1002c993 0x50 _L1w_DrvRxReset
+ 0x1002c9e3 0x2c _L1w_DrvRxSoftReset
+ 0x1002ca0f 0x35 _L1w_DrvRxCalcExp2
+ 0x1002ca44 0xe _L1w_DrvRxFingerCfg
+ 0x1002ca52 0x2c _L1w_DrvRxSetTfciIntTime
+ 0x1002ca7e 0x8 _L1w_DrvRxGetTfciIntTime
+ 0x1002ca86 0x191 _L1w_DrvRxCpichCfg
+ 0x1002cc17 0x16 _L1w_DrvRxCpichRel
+ 0x1002cc2d 0x109 _L1w_DrvRxPichCfg
+ 0x1002cd36 0x3a _L1w_DrvRxPichRel
+ 0x1002cd70 0x123 _L1w_DrvRxAichCfg
+ 0x1002ce93 0x3a _L1w_DrvRxAichRel
+ 0x1002cecd 0x11d _L1w_DrvRxPchCfg
+ 0x1002cfea 0x11 _L1w_DrvRxPchRel
+ 0x1002cffb 0x126 _L1w_DrvRxFachCfg
+ 0x1002d121 0x3b _L1w_DrvRxFachRel
+ 0x1002d15c 0x10e _L1w_DrvRxDlDpchCodeCfg
+ 0x1002d26a 0x33 _L1w_DrvRxDlTpcPilotCfg
+ 0x1002d29d 0x29 _L1w_DrvRxFdpchTpcCfg
+ 0x1002d2c6 0xa4 _L1w_DrvRxDlDpchCfg
+ 0x1002d36a 0x6f _L1w_DrvRxDlDpchRel
+ 0x1002d3d9 0x31 _L1w_DrvRxDlFbiCfg
+ 0x1002d40a 0x15b _L1w_DrvRxFdpchCfg
+ 0x1002d565 0x3b _L1w_DrvRxFdpchRel
+ 0x1002d5a0 0x16a _L1w_DrvRxHsscchCfg
+ 0x1002d70a 0x65 _L1w_DrvRxHsscchRel
+ 0x1002d76f 0x103 _L1w_DrvRxEagchCfg
+ 0x1002d872 0x40 _L1w_DrvRxEagchRel
+ 0x1002d8b2 0x333 _L1w_DrvRxRgHiCfg
+ 0x1002dbe5 0x3c _L1w_DrvRxRgHiRel
+ 0x1002dc21 0x15 _L1w_DrvRxEdchTtiCfg
+ 0x1002dc36 0x5b _L1w_DrvRxRgHichPostCmCfg
+ 0x1002dc91 0x10 _L1w_DrvRxDpchFactorCfg
+ 0x1002dca1 0xf _L1w_DrvRxAgchFactorCfg
+ 0x1002dcb0 0x77 _L1w_DrvRxDlCmCfnCfg
+ 0x1002dd27 0x8c _L1w_DrvRxDlCmSymbCfg
+ 0x1002ddb3 0x64 _L1w_DrvRxDlCmPostCfg
+ 0x1002de17 0x1f _L1w_DrvRxDlCmSymbRel
+ 0x1002de36 0x16 _L1w_DrvRxDlCmPostRel
+ 0x1002de4c 0x24 _L1w_DrvRxRakeCpChangRel
+ 0x1002de70 0x8e _L1w_DrvRxRakeChipCfg
+ 0x1002defe 0x119 _L1w_DrvRxRakeSymbCfg
+ 0x1002e017 0x4a _L1w_DrvRxRakePostCfg
+ 0x1002e061 0x18 _L1w_DrvRxRakeCfg
+ 0x1002e079 0xc _L1w_DrvRxSymbCpichStRead
+ 0x1002e085 0xc _L1w_DrvRxSymbPilotStRead
+ 0x1002e091 0x9 _L1w_DrvRxCombPiAiIntRead
+ 0x1002e09a 0x9 _L1w_DrvRxCombPilotIntRead
+ 0x1002e0a3 0x9 _L1w_DrvRxCombTpcIntRead
+ 0x1002e0ac 0x15 _L1w_DrvRxCombTpcPlStIntRead
+ 0x1002e0c1 0x8 _L1w_DrvRxCombFdpchIntRead
+ 0x1002e0c9 0xa _L1w_DrvRxCombDpchFactorDataRead
+ 0x1002e0d3 0xa _L1w_DrvRxCombAgchFactorDataRead
+ 0x1002e0dd 0x27 _L1w_DrvRxRamPiAiRead
+ 0x1002e104 0xa _L1w_DrvRxRamDpchPilotRead
+ 0x1002e10e 0xa _L1w_DrvRxRamDpchTpcRead
+ 0x1002e118 0x43 _L1w_DrvRxRamFdpchTpcRead
+ 0x1002e15b 0x15 _L1w_DrvRxRamSlotwtRead
+ 0x1002e170 0x15 _L1w_DrvRxRamNoiseRead
+ 0x1002e185 0x1f _L1w_DrvRxRamRawCpichRead
+ 0x1002e1a4 0x15 _L1w_DrvRxRamAfcRead
+ 0x1002e1b9 0x1c _L1w_DrvRxRamRawPilotRead
+ 0x1002e1d5 0x1f _L1w_DrvRxRgchIntInfoRead
+ 0x1002e1f4 0x1f _L1w_DrvRxHichIntInfoRead
+ .text 0x1002e213 0xa62 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dtr.o)
+ 0x1002e213 0x11 _L1w_DrvDtrBitReverse
+ 0x1002e224 0xa _L1w_DrvDtrTurboInit
+ 0x1002e22e 0x1d _L1w_DrvDtrTurboReset
+ 0x1002e24b 0x11 _L1w_DrvDtrSetCsServiceFlg
+ 0x1002e25c 0x3b _L1w_DrvDtrReset
+ 0x1002e297 0x5e _L1w_DrvDtrInit
+ 0x1002e2f5 0x3e _L1w_DrvDtrTrchCmCfg
+ 0x1002e333 0x4c _L1w_DrvDtrTrchSlotFormCfg
+ 0x1002e37f 0x171 _L1w_DrvDtrTrchTfciS1Cfg
+ 0x1002e4f0 0x24 _L1w_DrvDtrTrchTfciS1Clear
+ 0x1002e514 0xb _L1w_DrvDtrTrchCfnSet
+ 0x1002e51f 0xa _L1w_DrvDtrTrchCfnGet
+ 0x1002e529 0xf _L1w_DrvDtrTrchRegRel
+ 0x1002e538 0xa _L1w_DrvDtrTrchTfciS2Update
+ 0x1002e542 0xa _L1w_DrvDtrTrchDemultiplexUpdate
+ 0x1002e54c 0x9f _L1w_DrvDtrS1CfgPrint
+ 0x1002e5eb 0x1d7 _L1w_DrvDtrS2CfgPrint
+ 0x1002e7c2 0xb0 _L1w_DrvDtrTrchTfciS2Cfg
+ 0x1002e872 0xb _L1w_DrvDtrTrchTfciS2Clear
+ 0x1002e87d 0x42 _L1w_DrvDtrTrchBlindS1Cfg
+ 0x1002e8bf 0xa5 _L1w_DrvDtrTrchBlindGuidCfg
+ 0x1002e964 0xc _L1w_DrvDtrTrchBlindGuidUpdate
+ 0x1002e970 0xa _L1w_DrvDtrTrchTfciRead
+ 0x1002e97a 0x2d _L1w_DrvDtrTrchTfciDataReadV3
+ 0x1002e9a7 0x30 _L1w_DrvDtrTrchBlindRead
+ 0x1002e9d7 0x6 _L1w_DrvDtrTrchBlindDataAddrGet
+ 0x1002e9dd 0x24 _L1w_DrvDtrTrchDecodeInfoRead
+ 0x1002ea01 0x6 _L1w_DrvDtrTrchDecodeAddrGet
+ 0x1002ea07 0x1bb _L1w_DrvDtrTrchDecodeDataRead
+ 0x1002ebc2 0x61 _L1w_DrvDtrEagchCfg
+ 0x1002ec23 0xe _L1w_DrvDtrEagchCmCfg
+ 0x1002ec31 0x9 _L1w_DrvDtrEagchRel
+ 0x1002ec3a 0x3b _L1w_DrvDtrAgchIntDataRead
+ .text 0x1002ec75 0x572 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_bch.o)
+ 0x1002ec75 0x2d _L1w_DrvBchInit
+ 0x1002eca2 0xe _L1w_DrvBchReset
+ 0x1002ecb0 0x2d _L1w_DrvBchRecover
+ 0x1002ecdd 0xd _L1w_DrvBchSetFingerAdjust
+ 0x1002ecea 0xe _L1w_DrvBchGeViterbiOut
+ 0x1002ecf8 0x56 _L1w_DrvBchGePichSymbol
+ 0x1002ed4e 0xa _L1w_DrvBchGeCrcResult
+ 0x1002ed58 0x2b _L1w_DrvBchGeCpichOut
+ 0x1002ed83 0xf8 _L1w_DrvBchBchRxCfg
+ 0x1002ee7b 0xcd _L1w_DrvBchPichRxCfg
+ 0x1002ef48 0x9b _L1w_DrvBchCpichRxCfg
+ 0x1002efe3 0xc _L1w_DrvBchSetFingerEn
+ 0x1002efef 0xc _L1w_DrvBchSetRuntime
+ 0x1002effb 0xe _L1w_DrvBchGetFingerPos
+ 0x1002f009 0x10 _L1w_DrvBchSetS5TestMode
+ 0x1002f019 0xa _L1w_DrvBchSetTxdMode
+ 0x1002f023 0x7 _L1w_DrvBchSetBchPichSel
+ 0x1002f02a 0x7 _L1w_DrvBchSetTtiSync
+ 0x1002f031 0x7 _L1w_DrvBchSetWindowTh
+ 0x1002f038 0x7 _L1w_DrvBchSetPichOvsfk
+ 0x1002f03f 0xc _L1w_DrvBchSetContexSel
+ 0x1002f04b 0xd _L1w_DrvBchSetFingerPos
+ 0x1002f058 0x19 _L1w_DrvBchSetScramCode
+ 0x1002f071 0x16 _L1w_DrvBchSetStartMode
+ 0x1002f087 0xc _L1w_DrvBchSetPiAfcNum
+ 0x1002f093 0x31 _L1w_DrvBchSetPiPos
+ 0x1002f0c4 0xe _L1w_DrvBchGetFingerSt
+ 0x1002f0d2 0xd _L1w_DrvBchHasInvalidSymbol
+ 0x1002f0df 0xe _L1w_DrvBchGetBufIndex
+ 0x1002f0ed 0xe _L1w_DrvBchGetSlotIndex
+ 0x1002f0fb 0xe _L1w_DrvBchGetBurstPattern
+ 0x1002f109 0xa _L1w_DrvBchGeTotalSt
+ 0x1002f113 0x16 _L1w_DrvBchIsHwBusy
+ 0x1002f129 0x13 _L1w_DrvBchSetIQSel
+ 0x1002f13c 0x12 _L1w_DrvBchSetRotatePara
+ 0x1002f14e 0x21 _L1w_DrvBchSetRotateEn
+ 0x1002f16f 0xf _L1w_DrvBchSetRotateGateCtrl
+ 0x1002f17e 0xb _L1w_DrvBchIsIqRotateEn
+ 0x1002f189 0x36 _L1w_DrvBchStopIqRotate
+ 0x1002f1bf 0x12 _L1w_DrvBchSetFingerAnt
+ 0x1002f1d1 0x16 _L1w_DrvBchSetAdjFingerInfo
+ .text 0x1002f1e7 0x2f1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_utr.o)
+ 0x1002f1e7 0xc _L1w_DrvUtrLogTwo
+ 0x1002f1f3 0x31 _L1w_DrvUtrReset
+ 0x1002f224 0x1c _L1w_DrvUtrRamSoftReset
+ 0x1002f240 0x3 _L1w_DrvUtrInit
+ 0x1002f243 0xac _L1w_DrvUtrDchConfig
+ 0x1002f2ef 0x32 _L1w_DrvUtrRachConfig
+ 0x1002f321 0xa _L1w_DrvUtrEnable
+ 0x1002f32b 0xe _L1w_DrvUtrClose
+ 0x1002f339 0x8 _L1w_DrvUtrGetRamAddr
+ 0x1002f341 0x5f _L1w_DrvUtrTbAndCbConfig
+ 0x1002f3a0 0xac _L1w_DrvUtrRMConfig
+ 0x1002f44c 0x2d _L1w_DrvUtrGetCrcMode
+ 0x1002f479 0x20 _L1w_DrvUtrGetCodingType
+ 0x1002f499 0x1a _L1w_DrvUtrClearRmPara
+ 0x1002f4b3 0xc _L1w_DrvUtrRegClear
+ 0x1002f4bf 0x11 _L1w_DrvUtrGetRamData
+ 0x1002f4d0 0x8 _L1_DrvUtrGetInterlv1RamState
+ .text 0x1002f4d8 0x1dda T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_zx220a1.o)
+ 0x1002f4d8 0x5e _L1w_DrvRfcApcTableSel
+ 0x1002f536 0x1d2 _L1w_DrvRfcAbbCsfHpfCfg
+ 0x1002f708 0x5 _L1w_DrvRfcCalcIntFreq
+ 0x1002f70d 0x29 _L1w_DrvRfcCalcFracFreq
+ 0x1002f736 0x51 _L1w_DrvRfcGetFreqData
+ 0x1002f787 0x19 _L1w_DrvRfcGetBandData
+ 0x1002f7a0 0x9d _L1w_DrvRfcFreqSetTx
+ 0x1002f83d 0x12a _L1w_DrvRfcFreqSetRx
+ 0x1002f967 0x84 _L1w_DrvRfcGetBandNvIndex
+ 0x1002f9eb 0x79 _L1w_DrvRfcAuxRxCtrlSet
+ 0x1002fa64 0x1c _L1w_DrvRfcAuxRxIdleSet
+ 0x1002fa80 0x20 _L1w_DrvRfcRegReadBackSet
+ 0x1002faa0 0x1 _L1w_DrvRfcChSel
+ 0x1002faa1 0x1 _L1w_DrvRfcTransceiverInit
+ 0x1002faa2 0x2e _L1w_DrvRfcAgcSet
+ 0x1002fad0 0x2f _L1w_DrvRfcApcTableFreqSel
+ 0x1002faff 0xbc _L1w_DrvRfcApcSet
+ 0x1002fbbb 0x2d _L1w_DrvRfcFreqCompGetNvIdx
+ 0x1002fbe8 0x7c _L1w_DrvRfcApcFreqComp
+ 0x1002fc64 0x38 _L1w_DrvRfcApcTmpComp
+ 0x1002fc9c 0x100 _L1w_DrvRfcApcCalibTableCheck
+ 0x1002fd9c 0x4f _L1w_DrvRfcApcDefaultTableCheck
+ 0x1002fdeb 0x77 _L1w_DrvRfcAgcFreqComp
+ 0x1002fe62 0x71 _L1w_DrvRfcAgcCalibTableCheck
+ 0x1002fed3 0x46 _L1w_DrvRfcAgcDefaultTableCheck
+ 0x1002ff19 0x2a _L1w_DrvRfcRxNotchEn
+ 0x1002ff43 0x2a _L1w_DrvRfcRxNotchDisEn
+ 0x1002ff6d 0x2b _L1w_DrvRfcAntExChangeSelEn
+ 0x1002ff98 0x2b _L1w_DrvRfcAntOriginSelEn
+ 0x1002ffc3 0x2a _L1w_DrvRfcRxStartDivEn
+ 0x1002ffed 0x2b _L1w_DrvRfcRxStopDivEn
+ 0x10030018 0x2a _L1w_DrvRfcAuxRxSwCtrlEn
+ 0x10030042 0x2b _L1w_DrvRfcAuxRxSwIdleEn
+ 0x1003006d 0x38 _L1w_DrvRfcIdleToTxEn
+ 0x100300a5 0x36 _L1w_DrvRfcTxToRxTxEn
+ 0x100300db 0x3a _L1w_DrvRfcTxToIdleEn
+ 0x10030115 0x36 _L1w_DrvRfcRxTxToTxEn
+ 0x1003014b 0x36 _L1w_DrvRfcIdleToRxEn
+ 0x10030181 0x38 _L1w_DrvRfcRxToRxTxEn
+ 0x100301b9 0x2b _L1w_DrvRfcSwAllIdleEn
+ 0x100301e4 0x40 _L1w_DrvRfcRxToIdleEn
+ 0x10030224 0x2d _L1w_DrvRfcRxTxToRxEn
+ 0x10030251 0x37 _L1w_DrvRfcRxFreqChangeEn
+ 0x10030288 0x38 _L1w_DrvRfcTxFreqChangeEn
+ 0x100302c0 0x32 _L1w_DrvRfcIdleToTxHandle
+ 0x100302f2 0x48 _L1w_DrvRfcTxToIdleHandle
+ 0x1003033a 0x45 _L1w_DrvRfcIdleToRxHandle
+ 0x1003037f 0x55 _L1w_DrvRfcRxToIdleHandle
+ 0x100303d4 0x53 _L1w_DrvRfcRxFreqChangeHandle
+ 0x10030427 0xd _L1w_DrvRfcTxFreqChangeHandle
+ 0x10030434 0x41 _L1w_DrvRfcSlotCtrlDiv
+ 0x10030475 0x2a _L1w_DrvRfcSlotCtrlAntSel
+ 0x1003049f 0x29 _L1w_DrvRfcAgcEstEn
+ 0x100304c8 0x29 _L1w_DrvRfcAgcSetEn
+ 0x100304f1 0x35 _L1w_DrvRfcApcEn
+ 0x10030526 0x3c _L1w_DrvRfcAfcSetEn
+ 0x10030562 0x29 _L1w_DrvRfcDcEstEn
+ 0x1003058b 0x29 _L1w_DrvRfcDcSetEn
+ 0x100305b4 0x29 _L1w_DrvRfcRegReadBackEn
+ 0x100305dd 0x29 _L1w_DrvRfcStartAuxAdcEn
+ 0x10030606 0x29 _L1w_DrvRfcStopAuxAdcEn
+ 0x1003062f 0x1c _L1w_DrvRfcDcxoAuxAdcStart
+ 0x1003064b 0x1d _L1w_DrvRfcDcxoAuxAdcStop
+ 0x10030668 0x1f _L1w_DrvRfcAuxAdcCtrlEn
+ 0x10030687 0x41 _L1w_DrvRfcAbbCsfWriteEn
+ 0x100306c8 0x33 _L1w_DrvRfcCtrlRamTxInit
+ 0x100306fb 0x33 _L1w_DrvRfcCtrlRamRx0Init
+ 0x1003072e 0x204 _L1w_DrvRfcCtrlRamSwitchNvInit
+ 0x10030932 0xea _L1w_DrvRfcCtrlRamPaNvInit
+ 0x10030a1c 0x8 _L1w_DrvRfcCtrlRamNvEventInit
+ 0x10030a24 0x38 _L1w_DrvRfcFastAgcCwTableInit
+ 0x10030a5c 0x4c _L1w_DrvRfcFastAgcRamInit
+ 0x10030aa8 0xda _L1w_DrvRfcOpenTx
+ 0x10030b82 0xf7 _L1w_DrvRfcOpenRx
+ 0x10030c79 0xa _L1w_DrvRfcDiversityCtrl
+ 0x10030c83 0x12 _L1w_DrvRfcAfcCw2Hz
+ 0x10030c95 0x6a _L1w_DrvRfcRfRegRead
+ 0x10030cff 0xce _L1w_DrvRfcAllRegReadBack
+ 0x10030dcd 0x54 _L1w_DrvRfcGetDCXOTmp
+ 0x10030e21 0x3b _L1w_DrvRfcReadTmp
+ 0x10030e5c 0x15 _L1w_DrvRfcAptWrite
+ 0x10030e71 0x21 _L1w_DrvRfcDcocWrite
+ 0x10030e92 0x18 _L1w_DrvRfcAgcWrite
+ 0x10030eaa 0x8d _L1w_DrvRfcCloseTx
+ 0x10030f37 0x6d _L1w_DrvRfcCloseRx
+ 0x10030fa4 0x7e _L1w_DrvRfcDirFreqSetTx
+ 0x10031022 0x7c _L1w_DrvRfcDirFreqSetRx
+ 0x1003109e 0x32 _L1w_DrvRfcPowerApcSet
+ 0x100310d0 0x43 _L1w_DrvRfcIndexApcSet
+ 0x10031113 0x177 _L1w_DrvRfcFdtTxApcSet
+ 0x1003128a 0x22 _L1w_DrvRfcHdtGetTxApcTable
+ 0x100312ac 0x6 _L1w_DrvRfcHdtGetRxAgcTable
+ .text 0x100312b2 0xb8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_psr.o)
+ 0x100312b2 0x8 _L1w_DrvPsrStartPosCfg
+ 0x100312ba 0xb _L1w_DrvPsrRlMrtrPosMrtrConfig
+ 0x100312c5 0xb _L1w_DrvPsrSrcAndChanCodeCfg
+ 0x100312d0 0x8 _L1w_DrvPsrClkGatePassCfg
+ 0x100312d8 0x9 _L1w_DrvPsrPilotPatternCfg
+ 0x100312e1 0x8 _L1w_DrvPsrCmModeCfg
+ 0x100312e9 0x9 _L1w_DrvPsrRlPosStartCfgOver
+ 0x100312f2 0x9 _L1w_DrvPsrSuspendCfg
+ 0x100312fb 0x12 _L1w_DrvPsrTopMaskIntCfg
+ 0x1003130d 0x1c _L1w_DrvPsrResetCfg
+ 0x10031329 0x8 _L1w_DrvPsrPeriodCfg
+ 0x10031331 0x8 _L1w_DrvPsrDoubleAntOpencfg
+ 0x10031339 0x8 _L1w_DrvPsrStartWinPosCfg
+ 0x10031341 0x8 _L1w_DrvPsrRlOpenCloseCfg
+ 0x10031349 0x8 _L1w_DrvPsrMasterRlCfg
+ 0x10031351 0x8 _L1w_DrvPsrSttdCfg
+ 0x10031359 0x8 _L1w_DrvPsrIntInfoCfg
+ 0x10031361 0x9 _L1w_DrvPsrCmOverCfg
+ .text 0x1003136a 0xaff T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x1003136a 0x3c _L1w_DrvRfcGetFreqOffset
+ 0x100313a6 0x17 _L1w_DrvRfcNextSlotGet
+ 0x100313bd 0x16 _L1w_DrvRfcPreSlotGet
+ 0x100313d3 0x20 _L1w_DrvRfcFindSlot
+ 0x100313f3 0x8 _L1w_DrvRfcGetTxFirDlyNum
+ 0x100313fb 0x31 _L1w_DrvRfcSpiWrite
+ 0x1003142c 0x31 _L1w_DrvRfcAbbSpiWrite
+ 0x1003145d 0x12 _L1w_DrvRfcGpioWrite
+ 0x1003146f 0x14 _L1w_DrvRfcRffeWrite
+ 0x10031483 0x38 _L1w_DrvRfcFindBandNumFromTable
+ 0x100314bb 0x41 _L1w_DrvRfcGetFreqBand
+ 0x100314fc 0x22 _L1w_DrvRfcRxDfeIntfCfg
+ 0x1003151e 0x2f _L1w_DrvRfcPaModeSel
+ 0x1003154d 0x25 _L1w_DrvRfcGetPaCtrlData
+ 0x10031572 0x1a _L1w_DrvRfcGetPaIdleData
+ 0x1003158c 0x2a _L1w_DrvRfcGetApcCtrlWord
+ 0x100315b6 0xa3 _L1w_DrvRfcGetTxPowerCtrlWord
+ 0x10031659 0x14 _L1w_DrvRfcPaCtrl
+ 0x1003166d 0x25 _L1w_DrvRfcGetAgcCtrlWord
+ 0x10031692 0x27 _L1w_DrvRfcGetAfcDacCtrlWord
+ 0x100316b9 0x2c _L1w_DrvRfcDCXOGetTempDegree
+ 0x100316e5 0xb _L1w_DrvRfcAfcSet
+ 0x100316f0 0x1a _L1w_DrvRfcGetTxSwData
+ 0x1003170a 0x29 _L1w_DrvRfcGetRxSwData
+ 0x10031733 0x1a _L1w_DrvRfcGetTxSwIdleData
+ 0x1003174d 0x29 _L1w_DrvRfcGetRxSwIdleData
+ 0x10031776 0x1a _L1w_DrvRfcGetSwAllIdleData
+ 0x10031790 0x27 _L1w_DrvRfcSwitchPaCwWr
+ 0x100317b7 0x37 _L1w_DrvRfcSwitchCtrl
+ 0x100317ee 0x55 _L1w_DrvRfcSwPaIdleNvGet
+ 0x10031843 0x12 _L1w_DrvRfcGetCfgMrtr
+ 0x10031855 0x54 _L1w_DrvRfcTuEventMrtrWr
+ 0x100318a9 0x21 _L1w_DrvRfcTuEventCtrlDataWr
+ 0x100318ca 0x54 _L1w_DrvRfcTuEventEn
+ 0x1003191e 0x27 _L1w_DrvRfcCtrlRamFmtDataWr
+ 0x10031945 0x28 _L1w_DrvRfcCtrlRamFmtInfoWr
+ 0x1003196d 0x20 _L1w_DrvRfcCtrlRamDataTypeWr
+ 0x1003198d 0x40 _L1w_DrvRfcCtrlRamEn
+ 0x100319cd 0xe _L1w_DrvRfcAgcRamDataWr
+ 0x100319db 0x1c _L1w_DrvRfcFastAgcEn
+ 0x100319f7 0x1a _L1w_DrvRfcFastAgcDisEn
+ 0x10031a11 0x15 _L1w_DrvRfcIntCfg
+ 0x10031a26 0x15 _L1w_DrvRfcSpiFormatCfg
+ 0x10031a3b 0x9 _L1w_DrvRfcRffeFormatCfg
+ 0x10031a44 0x2 _L1w_DrvRfcRbdpCfg
+ 0x10031a46 0x1c _L1w_DrvRfcDagcCfg
+ 0x10031a62 0x13 _L1w_DrvRfcDcCfg
+ 0x10031a75 0xd _L1w_DrvRfcFcCordicCfg
+ 0x10031a82 0x1a _L1w_DrvRfcNotchCordicCfg
+ 0x10031a9c 0x21 _L1w_DrvRfcReadNotchCordicAVal
+ 0x10031abd 0xb8 _L1w_DrvRfcNotchRegCfg
+ 0x10031b75 0x52 _L1w_DrvRfcFastAgcCfg
+ 0x10031bc7 0x4f _L1w_DrvRfcCtrlRamEventInit
+ 0x10031c16 0x84 _L1w_DrvRfcAbbCsfCtrlRamInit
+ 0x10031c9a 0x21 _L1w_DrvRfcEventTableInit
+ 0x10031cbb 0x41 _L1w_DrvRfcReset
+ 0x10031cfc 0x8f _L1w_DrvRfcGsmIntNotchCalc
+ 0x10031d8b 0x73 _L1w_DrvRfcInit
+ 0x10031dfe 0x9 _L1w_DrvRfcDfeTxInit
+ 0x10031e07 0x30 _L1w_DrvRfcTxTone
+ 0x10031e37 0x28 _L1w_DrvRfcAfcCwSet
+ 0x10031e5f 0x1 _L1w_DrvRfcAfcCwGet
+ 0x10031e60 0x9 _L1w_DrvRfcRestore
+ .text 0x10031e69 0x1594 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x10031e69 0x38 _L1w_DrvHsdpaIcReset
+ 0x10031ea1 0x2f _L1w_DrvHsdpaIcTpuCfgOver
+ 0x10031ed0 0x30 _L1w_DrvHsdpaIcTxTpuCfgOver
+ 0x10031f00 0x28 _L1w_DrvHsdpaIcInit
+ 0x10031f28 0x12 _L1w_DrvHsdpaIcIntOpen
+ 0x10031f3a 0x12 _L1w_DrvHsdpaIcIntMask
+ 0x10031f4c 0x17 _L1w_DrvHsdpaIcEnable
+ 0x10031f63 0x18 _L1w_DrvHsdpaIcStaticCfg
+ 0x10031f7b 0x273 _L1w_DrvHsdpaIcTpuAntPsrCfg
+ 0x100321ee 0x1d8 _L1w_DrvHsdpaIcTxTpuAntPsrCfg
+ 0x100323c6 0xa9 _L1w_DrvHsdpaIcTpuSubFrmCfg
+ 0x1003246f 0x97 _L1w_DrvHsdpaIcTxTpuSubFrmCfg
+ 0x10032506 0x69 _L1w_DrvHsdpaIcModeEnableCfg
+ 0x1003256f 0x5b _L1w_DrvHsdpaIcLambdaCfg
+ 0x100325ca 0x5b _L1w_DrvHsdpaIcSymModulusRead
+ 0x10032625 0x34 _L1w_DrvHsdpaAdrReset
+ 0x10032659 0x18 _L1w_DrvHsdpaAdrInit
+ 0x10032671 0x12 _L1w_DrvHsdpaAdrIntOpen
+ 0x10032683 0x12 _L1w_DrvHsdpaAdrIntMask
+ 0x10032695 0xd6 _L1w_DrvHsdpaAdrStaticCfg
+ 0x1003276b 0x83 _L1w_DrvHsdpaAdrInitRcvCfg
+ 0x100327ee 0x4b _L1w_DrvHsdpaAdrFcCfg
+ 0x10032839 0x10 _L1w_DrvHsdpaAdrEnableCfg
+ 0x10032849 0x172 _L1w_DrvHsdpaAdrSubFrmCfg
+ 0x100329bb 0x10 _L1w_DrvHsdpaAdrHsscchCfg
+ 0x100329cb 0x2e _L1w_DrvHsdpaAdrHsdschCfg
+ 0x100329f9 0xa _L1w_DrvHsdpaAdrDisable
+ 0x10032a03 0x2d _L1w_DrvHsdpaAdrCltd1Cfg
+ 0x10032a30 0x74 _L1w_DrvHsdpaAdrCirIntRead
+ 0x10032aa4 0x11 _L1w_DrvHsdpaAdrGetCirDataAddr
+ 0x10032ab5 0x20 _L1w_DrvHsdpaAdrCpichIntRead
+ 0x10032ad5 0x2e _L1w_DrvHsdpaHsscchReset
+ 0x10032b03 0x21 _L1w_DrvHsdpaHsscchInit
+ 0x10032b24 0x12 _L1w_DrvHsdpaHsscchIntOpen
+ 0x10032b36 0x12 _L1w_DrvHsdpaHsscchIntMask
+ 0x10032b48 0x11 _L1w_DrvHsdpaHsscchStaticCfg
+ 0x10032b59 0x65 _L1w_DrvHsdpaHsscchInitRcvCfg
+ 0x10032bbe 0x2d _L1w_DrvHsdpaHsscchPart1Cfg
+ 0x10032beb 0x3b _L1w_DrvHsdpaHsscchPart2Cfg
+ 0x10032c26 0x1b _L1w_DrvHsdpaHsscchDisable
+ 0x10032c41 0xeb _L1w_DrvHsdpaHsscchPart1IntRead
+ 0x10032d2c 0x31 _L1w_DrvHsdpaHsscchPart2IntRead
+ 0x10032d5d 0x30 _L1w_DrvHsdpaHdtrReset
+ 0x10032d8d 0x1a _L1w_DrvHdtrTurboReset
+ 0x10032da7 0x1b _L1w_DrvHdtrLessTurboReset
+ 0x10032dc2 0x2e _L1w_DrvHsdpaHdtrInit
+ 0x10032df0 0x12 _L1w_DrvHsdpaHdtrIntOpen
+ 0x10032e02 0x12 _L1w_DrvHsdpaHdtrIntMask
+ 0x10032e14 0x25 _L1w_DrvHsdpaHdtrStaticCfg
+ 0x10032e39 0xa _L1w_DrvHsdpaHdtrInitRcvCfg
+ 0x10032e43 0x3b _L1w_DrvHsdpaHdtrDemoduleCfg
+ 0x10032e7e 0x183 _L1w_DrvHsdpaHdtrDecodeCfg
+ 0x10033001 0x83 _L1w_DrvHsdpaHdtrHwCfg
+ 0x10033084 0xa _L1w_DrvHsdpaHdtrGetCurCfgSubFrm
+ 0x1003308e 0x76 _L1w_DrvHsdpaHdtrIntRead
+ 0x10033104 0x6 _L1w_DrvHsdpaHdtrGetRamDataAddr
+ 0x1003310a 0x3b _L1w_DrvHsdpaHsdpcchInitSendCfg
+ 0x10033145 0x39 _L1w_DrvHsdpaHsdpcchAckNackCfg
+ 0x1003317e 0x3c _L1w_DrvHsdpaHsdpcchCqiPciCfg
+ 0x100331ba 0x10 _L1w_DrvHsdpaHsdpcchCqiPciCfgEn
+ 0x100331ca 0x10 _L1w_DrvHsdpaHsdpcchDisable
+ 0x100331da 0x19 _L1w_DrvHsdpaLessStaticCfg
+ 0x100331f3 0x20a _L1w_DrvHsdpaLessCfgAllTb
+ .text 0x100333fd 0x2951 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x100333fd 0x2f _L1W_SEND_RST_REQ
+ 0x1003342c 0x2f _L1W_SEND_INIT_REQ
+ 0x1003345b 0x1d _L1W_RegTpuTS0IntEvent
+ 0x10033478 0xc _L1W_ResetTpu
+ 0x10033484 0x18d _L1W_Reset
+ 0x10033611 0x125 _L1W_Init
+ 0x10033736 0x35 _L1w_SchedMeasRelease
+ 0x1003376b 0x120 _L1W_W_Release
+ 0x1003388b 0x1c _L1W_SetSecSchedId
+ 0x100338a7 0x8 _L1W_CampOnSetFlag
+ 0x100338af 0x75 _L1W_CampOnOrReconfig
+ 0x10033924 0xad _L1W_DchIn1R2RCtrl
+ 0x100339d1 0x1e _L1W_Only1RCtrl
+ 0x100339ef 0xa9 _L1W_Sch1R2RAntCtrl
+ 0x10033a98 0xd8 _L1w_TpuAdjScByDchCfgScene
+ 0x10033b70 0xa8 _L1W_DlDpchReconfig
+ 0x10033c18 0x1c _L1W_DchRelTpuAdj
+ 0x10033c34 0x6e _L1w_AmtFsmProc
+ 0x10033ca2 0x89 _L1w_AmtNSTSetUlDpchParm
+ 0x10033d2b 0x72 _L1w_AmtNSTSetDlDpchParm
+ 0x10033d9d 0x5b _L1W_WRelDelayHandle
+ 0x10033df8 0x4af _L1W_PSCommonMsgCtrl
+ 0x100342a7 0x5 _L1w_HsupaSubIntCallBack
+ 0x100342ac 0x111 _L1W_ReadPSMsg
+ 0x100343bd 0x1d _L1W_RegTpuSubFrmIntEvent
+ 0x100343da 0x42 _L1W_SubFrmSchedStateCtrl
+ 0x1003441c 0x1b _L1W_InnerCmd
+ 0x10034437 0x55 _L1W_ActiveProcHandler
+ 0x1003448c 0x1f _L1W_ProcSend2PS
+ 0x100344ab 0x34 _L1W_ProcAftSchedHandler
+ 0x100344df 0x26f _L1W_RfDevCtrl
+ 0x1003474e 0xa3 _L1W_DlsDevCtrl
+ 0x100347f1 0x64 _L1W_SlaveSetRFStartEnd
+ 0x10034855 0x9e _L1W_CommonDevCtrl
+ 0x100348f3 0x1ce _L1W_BeforeTpuAdjHandler
+ 0x10034ac1 0x19f _L1W_StateChanging
+ 0x10034c60 0x8d _L1W_NorSubFrmIntHandle
+ 0x10034ced 0x150 _L1W_FrameInt
+ 0x10034e3d 0x29 _L1w_SchedResBaseOffUpdate
+ 0x10034e66 0x1a1 _L1W_PichIntHandle
+ 0x10035007 0xe3 _L1W_PreSyncSleepSched
+ 0x100350ea 0x583 _L1W_DevIntHandle
+ 0x1003566d 0x1bd _L1W_DevMeasResultHnd
+ 0x1003582a 0x18d _L1W_DevResultProc
+ 0x100359b7 0x1c2 _L1w_MainTs0Log
+ 0x10035b79 0x12 _L1w_MainSetCloseLog
+ 0x10035b8b 0x3a _L1w_SchedAntSet
+ 0x10035bc5 0x189 _L1w_SchedMainTask
+ .text 0x10035d4e 0x7c7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_rach.o)
+ 0x10035d4e 0x36 _L1w_SchedRachProcInit
+ 0x10035d84 0x14 _L1w_SchedRachProcReset
+ 0x10035d98 0x9c _L1w_SchedRachProcRanSelSig
+ 0x10035e34 0x52 _L1w_SchedRachFindAvailableAS
+ 0x10035e86 0xab _L1w_SchedRachNeedDeleteRtFrameEndAichSlot
+ 0x10035f31 0x170 _L1w_SchedRachProcRanSelAS
+ 0x100360a1 0x49 _L1w_SchedRachProcActive
+ 0x100360ea 0x2f _L1w_SchedRachProcDeactive
+ 0x10036119 0xce _L1w_SchedRachConfigRtx
+ 0x100361e7 0xb9 _L1w_SchedRachProcPSCmd
+ 0x100362a0 0x33 _L1w_SchedRachProcL1Cmd
+ 0x100362d3 0x2e _L1w_SchedRachProcPreSched
+ 0x10036301 0x4d _L1w_SchedRachProcCfgHandle
+ 0x1003634e 0x27 _L1w_SchedRachAiResultHandle
+ 0x10036375 0xea _L1w_SchedRachProcSched
+ 0x1003645f 0x28 _L1w_SchedRachProcSend2PS
+ 0x10036487 0x36 _L1w_SchedRachProcL1InnerReq
+ 0x100364bd 0x9 _L1w_SchedRachProcL1InnerAbort
+ 0x100364c6 0x8 _L1w_SchedRachProcDevFachEnable
+ 0x100364ce 0x1b _L1W_SchedRachProcConfigCheck
+ 0x100364e9 0x2c _L1w_SchedRachProcIsNextFmo
+ .text 0x10036515 0x1181 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ 0x10036515 0xd _L1w_SchMeasDbInit
+ 0x10036522 0x30 _L1w_SchMeasU16Filter
+ 0x10036552 0x17 _L1w_SchMeasFingerPosOffset
+ 0x10036569 0x74 _L1w_SchMeasChooseFilterFinger
+ 0x100365dd 0xc8 _L1w_SchMeasDbUpdPreSyncInfo
+ 0x100366a5 0x1d _L1w_SchedMeasReturnCsrSlot
+ 0x100366c2 0x27f _L1w_SchMeasDbSaveSyncCelReslt
+ 0x10036941 0xbb _L1w_SchedMeasSetInnerReq
+ 0x100369fc 0x91 _L1w_SchedMeasSetInnerResult
+ 0x10036a8d 0x17 _L1w_SchedMeasClearInnerDb
+ 0x10036aa4 0x37 _L1w_SchedMeasGetInnerResult
+ 0x10036adb 0x15 _L1w_SchedMeasQueryInnerSt
+ 0x10036af0 0x12 _L1w_SchedMeasGetAfcCel
+ 0x10036b02 0x25 _L1w_SchedMeasGetInnerCelInfo
+ 0x10036b27 0x14f _L1w_SchedMeasGetInnerFreq
+ 0x10036c76 0x13d _L1w_SchedMeasSaveCsResult
+ 0x10036db3 0x9a _L1w_SchedMeasQuerySyncInfo
+ 0x10036e4d 0xc0 _L1w_SchedMeasSyncSetFreq
+ 0x10036f0d 0x48 _L1w_SchedMeasGetScellResult
+ 0x10036f55 0x2db _L1w_SchedMeasGetIntraResult
+ 0x10037230 0x1a _L1w_SchedMeasFilterRscp
+ 0x1003724a 0x2a4 _L1w_SchedMeasGetInterResult
+ 0x100374ee 0xbf _L1w_SchMeasQueryCellInfo
+ 0x100375ad 0x3a _L1w_SchMeasAdjustSfn
+ 0x100375e7 0x4e _L1w_SchMeasSetCellSfnInfo
+ 0x10037635 0x37 _L1w_SchMeasSetCellSttdInfo
+ 0x1003766c 0x2a _L1w_SchMeasGetUeInternalRssi
+ .text 0x10037696 0x8b4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ 0x10037696 0x30 _L1W_RegisterProcedure
+ 0x100376c6 0x49 _L1W_SetIcsStateProcs
+ 0x1003770f 0x68 _L1W_SetIdleStateProcs
+ 0x10037777 0x40 _L1W_SetPageStateProcs
+ 0x100377b7 0x50 _L1W_SetFachStateProcs
+ 0x10037807 0x50 _L1W_SetEFachStateProcs
+ 0x10037857 0x48 _L1W_SetDchStateProcs
+ 0x1003789f 0x14 _L1W_SetAmtHdtStateProcs
+ 0x100378b3 0x14 _L1W_SetAmtFdtStateProcs
+ 0x100378c7 0x40 _L1W_SetAmtThCalibStateProcs
+ 0x10037907 0x40 _L1W_SetAmtNstStateProcs
+ 0x10037947 0x32 _L1W_SetWSlaveModeProcs
+ 0x10037979 0x1 _L1W_SetCloseStateProcs
+ 0x1003797a 0xb _L1W_GetDchActState
+ 0x10037985 0x6f _L1W_NotifyFSM
+ 0x100379f4 0x142 _L1W_WMasteStateCtrl
+ 0x10037b36 0xc0 _L1W_ModeCtrl
+ 0x10037bf6 0x4d _L1W_L1StateCtrl
+ 0x10037c43 0x87 _L1W_SetProc
+ 0x10037cca 0x42 _L1W_GetPriId
+ 0x10037d0c 0x97 _L1w_SetMasterState
+ 0x10037da3 0x30 _L1w_ResetCountForLog
+ 0x10037dd3 0x1b _L1w_AddSlaveStateCntForLog
+ 0x10037dee 0x3a _L1w_AddMasterStateCntForLog
+ 0x10037e28 0xb4 _L1w_CheckMsgToAddProcCntForLog
+ 0x10037edc 0xa _L1w_SetDLULTimingForLog
+ 0x10037ee6 0x64 _L1w_PrintStandLog
+ .text 0x10037f4a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_inter_cs.o)
+ 0x10037f4a 0x8 _L1w_SchedCs1ProcGetFreq
+ 0x10037f52 0x7 _L1w_SchedCs1ProcGetCsProcState
+ 0x10037f59 0x6 _L1w_Cs1GetInnerInfo
+ 0x10037f5f 0x12 _L1w_SchedCs1ProcInit
+ 0x10037f71 0x21 _L1_SchedCs1ProcReset
+ 0x10037f92 0x22 _L1w_Cs1WriteFullscanResult
+ 0x10037fb4 0x17 _L1w_SchedCs1AbortInnerReq
+ 0x10037fcb 0xf _L1w_Cs1GetInnerReqByActReason
+ 0x10037fda 0x2 _L1w_SchedCs1ProcPSCmd
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+ 0x1004851f 0x2b1 _L1w_SchedHsdpaPSCmd
+ 0x100487d0 0x24d _L1w_SchedHsdpaPreSched
+ 0x10048a1d 0x5a _L1w_SchedHsdpaSched
+ 0x10048a77 0x40 _L1w_SchedHsdpaSend2PS
+ 0x10048ab7 0x1c _L1w_SchedHsdpaReset
+ 0x10048ad3 0xc _L1w_SchedHsdpaInit
+ 0x10048adf 0x3e _L1w_SchedHsdpaDevOrderIndProc
+ 0x10048b1d 0x53 _L1w_SchedHsdpaHsscchOrder
+ 0x10048b70 0x6 _L1w_SchedHsdpaGetSchedDb
+ 0x10048b76 0x32 _L1w_SchedHsdpaInnerRel
+ .text 0x10048ba8 0x2ae T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa_efach.o)
+ 0x10048ba8 0xb _L1w_SchedHspaEraInd
+ 0x10048bb3 0x3a _L1w_SchedHsupaEraStart
+ 0x10048bed 0xb8 _L1w_SchedHsupaFachActive
+ 0x10048ca5 0x11 _L1w_SchedHsupaFachRel
+ 0x10048cb6 0xa _L1w_SchedHsupaErntiUpdateConfig
+ 0x10048cc0 0xee _L1w_SchedHsupaFachPreSched
+ 0x10048dae 0x26 _L1w_SchedHsupaNoDataPSCmd
+ 0x10048dd4 0x2d _L1w_SchedHsupaFachSched
+ 0x10048e01 0x26 _L1w_SchedHsupaEraSend2PS
+ 0x10048e27 0x2f _L1w_SchedHsupaFachSend2PS
+ .text 0x10048e56 0x341 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fmo.o)
+ 0x10048e56 0x8 _L1w_SchedFmoProcActive
+ 0x10048e5e 0x20 _L1w_SchedFmoProcDeactive
+ 0x10048e7e 0x5e _L1w_SchedFmoCalcInfo
+ 0x10048edc 0x45 _L1w_SchedFmoInfoSend2Psr
+ 0x10048f21 0x46 _L1w_SchedFmoProcForbidFmo
+ 0x10048f67 0x26 _L1w_SchedFmoProcGetFmoInfo
+ 0x10048f8d 0xf _L1w_SchedFmoProcGetFmoPeriod
+ 0x10048f9c 0x2 _L1w_SchedFmoProcReset
+ 0x10048f9e 0x12 _L1w_SchedFmoProcInit
+ 0x10048fb0 0x35 _L1w_SchedFmoProcPSCmd
+ 0x10048fe5 0x1b2 _L1w_SchedFmoProcSched
+ .text 0x10049197 0xce5 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ 0x10049197 0x7 _L1w_SchedFsProcGetFsProcState
+ 0x1004919e 0x5 _L1w_SchedFsPscThreshold
+ 0x100491a3 0x23 _l1w_FsRemoveFreq
+ 0x100491c6 0xaf _L1w_FsInit
+ 0x10049275 0x59 _L1w_FsInsertCoarseResult
+ 0x100492ce 0x4a _L1w_FsCalcRssi
+ 0x10049318 0x39 _L1w_FsFilterFineFreq
+ 0x10049351 0xaf _L1w_SchedFsProcBandCrossFilter
+ 0x10049400 0x32 _L1w_FsSetFineFreq
+ 0x10049432 0x64 _L1w_FsGetByRangeIndex
+ 0x10049496 0x63 _L1w_FsGetNextCoarseFreq
+ 0x100494f9 0x2a _L1w_FsGetNextPscFreq
+ 0x10049523 0x27 _L1w_FsGetNextFineFreq
+ 0x1004954a 0x4f _L1w_FsInsertFineResult
+ 0x10049599 0x28 _L1w_SchedFsProcReset
+ 0x100495c1 0x18 _L1w_SchedFsProcInit
+ 0x100495d9 0x30 _L1w_SchedFsProcSchedInit
+ 0x10049609 0xa9 _L1w_SchedfsResQueryGap
+ 0x100496b2 0x88 _L1w_SchedFsProcJudgeEnd
+ 0x1004973a 0x42 _L1w_SchedFsProcSetRes
+ 0x1004977c 0x4f _L1w_SchedFsProcUpdResEnd
+ 0x100497cb 0x4c _L1w_SchedFsProcSetCoarseFreq
+ 0x10049817 0x58 _L1w_SchedFsProcGetRssi
+ 0x1004986f 0x3d _L1w_SchedFsProcCalcCoarseRssi
+ 0x100498ac 0x4d _L1w_SchedFsProcSchedSetFineFreq
+ 0x100498f9 0x60 _L1w_SchedFsProcCalcFineRssi
+ 0x10049959 0xbe _L1w_SchedFsProcSchedSetPscFreq
+ 0x10049a17 0xdd _L1w_SchedFsProcCalcPscRssi
+ 0x10049af4 0x4e _L1w_SchedFsProcSetPscFineInfo
+ 0x10049b42 0x110 _L1w_SchedFsProcSchedCalcPscAndRssi
+ 0x10049c52 0x3c _L1w_SchedFsProcPreSchedHandler
+ 0x10049c8e 0x43 _L1w_SchedFsProcSched
+ 0x10049cd1 0x3c _L1w_SchedFsProcActive
+ 0x10049d0d 0x8 _L1w_SchedFsProcDeactive
+ 0x10049d15 0x64 _L1w_SchedFsProcPSCmd
+ 0x10049d79 0x2c _L1w_FreqScanFineRssiCmp
+ 0x10049da5 0xd7 _L1w_SchedFsProcSend2PS
+ .text 0x10049e7c 0x4eb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_math.o)
+ 0x10049e7c 0x7e _L1w_MathWord2Float
+ 0x10049efa 0x82 _L1w_MathDword2Float
+ 0x10049f7c 0x2a _L1w_MathFloatDiv
+ 0x10049fa6 0x27 _L1w_MathDivEx
+ 0x10049fcd 0x34 _L1w_MathFloatAdd
+ 0x1004a001 0x5c _L1w_MathFloatSub
+ 0x1004a05d 0x2e _L1w_MathFloatMul
+ 0x1004a08b 0x52 _L1w_MathFloatCmp
+ 0x1004a0dd 0x38 _L1w_MathCalcExp2
+ 0x1004a115 0xb0 _L1w_MathLog
+ 0x1004a1c5 0x187 _L1w_MathQuickSort
+ 0x1004a34c 0x11 _L1w_BitReverse
+ 0x1004a35d 0xa _L1w_GetNonZeroBitNum
+ .text 0x1004a367 0x539 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_tx.o)
+ 0x1004a367 0x21 _L1w_DevHsupaSetEdpdchReadyTrue
+ 0x1004a388 0x1f _L1w_DevHsupaCalcSubFrmBitmap
+ 0x1004a3a7 0x9 _L1w_DevHsupaIfSubfrmGap
+ 0x1004a3b0 0x105 _L1w_DevHsupaIsEdchReady
+ 0x1004a4b5 0x3e _L1w_DevHsupaCalcHarqId
+ 0x1004a4f3 0x48 _L1w_DevHsupaEdchDataPrint
+ 0x1004a53b 0x3e _L1w_DevHsupaGetTransFlg
+ 0x1004a579 0x24 _L1w_DevHsupaIsNextTtiReady
+ 0x1004a59d 0x13a _L1w_DevHsupaSendDataProc
+ 0x1004a6d7 0x33 _L1w_DevHsupaTxProc
+ 0x1004a70a 0x24 _L1w_DevHsupaSetEhichRcvInf
+ 0x1004a72e 0x20 _L1w_DevHsupaClrEhichRcvInf
+ 0x1004a74e 0xa _L1w_DevHsupaSearchEhichRcvInf
+ 0x1004a758 0xb _L1w_DevHsupaEhichRcvInfReset
+ 0x1004a763 0xc _L1w_DevHsupaEhichRcvInfInit
+ 0x1004a76f 0xe6 _L1w_DevHsupaIcpIntEdchDataProc
+ 0x1004a855 0x4b _L1w_DevHsupaCpPcTtiInfo
+ .text 0x1004a8a0 0x2a8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_hspa.o)
+ 0x1004a8a0 0x25 _L1w_DevPcHspaReset
+ 0x1004a8c5 0x1b _L1w_DevPcHspaInit
+ 0x1004a8e0 0x44 _L1w_DevPcHsdpaBeltaHsCalc
+ 0x1004a924 0x76 _L1w_DevPcHsdpaBeltaHsCmUpdate
+ 0x1004a99a 0x1 _L1w_DevPcHsEdchBeltaObtain
+ 0x1004a99b 0x2b _L1w_DevPcHsdpaStartReqHandle
+ 0x1004a9c6 0x34 _L1w_DevPcGetCurDpaSubFrm
+ 0x1004a9fa 0x83 _L1w_DevPcHsdpaTtiInfoHandle
+ 0x1004aa7d 0x69 _L1w_DevPcHsupaStartReqHandle
+ 0x1004aae6 0x62 _L1w_DevPcHsupaTtiInfoHandle
+ .text 0x1004ab48 0xee3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x1004ab48 0x26 _L1w_DevTxRachIndToL1s
+ 0x1004ab6e 0xc _L1w_DevTxRaInit
+ 0x1004ab7a 0x35 _L1w_DevTxSendPcRaCfgMsg
+ 0x1004abaf 0x13 _L1w_DevTxUtrTrchParamCalc
+ 0x1004abc2 0x19 _L1w_DevTxUtrTbCbParamCalc
+ 0x1004abdb 0x29 _L1w_DevTxUtrRmParamCalc
+ 0x1004ac04 0xf6 _L1w_DevTxRaUtrCfg
+ 0x1004acfa 0x91 _L1w_DevTxRachTpuIntParaCalc
+ 0x1004ad8b 0x118 _L1w_DevTxRachMessageFactor
+ 0x1004aea3 0x11b _L1w_DevTxRachCfg
+ 0x1004afbe 0x42 _L1w_DevTxRachRel
+ 0x1004b000 0x8a _L1w_DevTxRachCfgMsgHandle
+ 0x1004b08a 0x22 _L1w_DevTxRachAbortMsgHandle
+ 0x1004b0ac 0x98 _L1w_DevTxPreamblePowerCtrl
+ 0x1004b144 0x96 _L1w_DevTxAichCfg
+ 0x1004b1da 0x86 _L1w_DevTxPreambleCfg
+ 0x1004b260 0xd8 _L1w_DevTxPrachPowerCtrl
+ 0x1004b338 0xc8 _L1w_DevTxPrachCfg
+ 0x1004b400 0x8f _L1w_DevTxRaIntPreHandle
+ 0x1004b48f 0x95 _L1w_DevTxRaIntAichHandle
+ 0x1004b524 0x64 _L1w_DevTxRaIntSendPrachHandle
+ 0x1004b588 0x5e _L1w_DevTxRaIntHandle
+ 0x1004b5e6 0x1a _L1w_DevTxPrachClose
+ 0x1004b600 0xbc _L1w_DevTxAichIsAck
+ 0x1004b6bc 0x3e _L1w_DevTxAichIsNack
+ 0x1004b6fa 0x106 _L1w_DevTxAichIsNoAck
+ 0x1004b800 0x77 _L1w_DevPrachInfoLogPrintf
+ 0x1004b877 0xb7 _L1w_DevTxEraDpcchCfg
+ 0x1004b92e 0x56 _L1w_DevTxEraDpcchRel
+ 0x1004b984 0xa7 _L1w_DevTxPiAiAichIntHandle
+ .text 0x1004ba2b 0xfa4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ 0x1004ba2b 0xb _L1w_DevRtxRmReset
+ 0x1004ba36 0x9 _L1w_DevRmGetExp
+ 0x1004ba3f 0x37 _L1w_DevRmCeil
+ 0x1004ba76 0x11 _L1w_DevRmCalcGcd
+ 0x1004ba87 0xad _L1w_DevRmGetSf
+ 0x1004bb34 0x37 _L1w_DevRmRachTfciAnalysis
+ 0x1004bb6b 0x5a _L1w_DevRmUlTfciAnalysis
+ 0x1004bbc5 0x78 _L1w_DevRmDlTfciAnalysis
+ 0x1004bc3d 0x59 _L1w_DevRmCalcCbPara
+ 0x1004bc96 0x63 _L1w_DevRmCalcBitsOfTrch
+ 0x1004bcf9 0x79 _L1w_DevRmCalcRmNi
+ 0x1004bd72 0x90 _L1w_DevRmCalcUlDeltaNi
+ 0x1004be02 0x121 _L1w_DevRmCalcDeltaNi
+ 0x1004bf23 0x45 _L1w_DevRmCalcUlNdataj
+ 0x1004bf68 0xa3 _L1w_DevRmCalcUlUncodeRm
+ 0x1004c00b 0x73 _L1w_DevRmCalcTurboS
+ 0x1004c07e 0xa6 _L1w_DevRmCalcUlTurboRm
+ 0x1004c124 0x65 _L1w_DevRmCalcUlTrchRmPara
+ 0x1004c189 0x46 _L1w_DevRmCalcUlRmPara
+ 0x1004c1cf 0x8a _L1w_DevRmCalcDlNimax
+ 0x1004c259 0x1f _L1w_DevRmCalcDlDeltaNimax
+ 0x1004c278 0xbd _L1w_DevRmCalcDlRmTfcNMax
+ 0x1004c335 0x97 _L1w_DevRmCalcDlRmDeltaNiTti
+ 0x1004c3cc 0x67 _L1w_DevRmCalcDlRmNiMax
+ 0x1004c433 0xfb _L1w_DevRmCalcDlTfcDeltaNijTti
+ 0x1004c52e 0x8f _L1w_DevRmCalcDlDeltaNijTti
+ 0x1004c5bd 0x63 _L1w_DevRmCalcDlUncodeRm
+ 0x1004c620 0x99 _L1w_DevRmCalcDlTurboRm
+ 0x1004c6b9 0x3f _L1w_DevRmCalcDlTrchRmPara
+ 0x1004c6f8 0x54 _L1w_DevRmCalcDlRmPara
+ 0x1004c74c 0x4c _L1w_DevRmSaveUlDchPara
+ 0x1004c798 0x4a _L1w_DevRmSaveDlTrchPara
+ 0x1004c7e2 0x34 _L1w_DevRmSaveRachPara
+ 0x1004c816 0xb5 _L1w_DevRmCalcRmPara
+ 0x1004c8cb 0x74 _L1w_DevRmCalcUlRmNi
+ 0x1004c93f 0x25 _L1w_DevRmCalcUlCmRes
+ 0x1004c964 0x6b _L1w_DevRmCalcTfcRes
+ .text 0x1004c9cf 0x3fc T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_tx.o)
+ 0x1004c9cf 0x23 _L1w_DevHsdpaSendPcTtiInfo
+ 0x1004c9f2 0x1f _L1w_DevHsdpaHarqAckBufferShift
+ 0x1004ca11 0x68 _L1w_DevHsdpaSetHarqBufPrePost
+ 0x1004ca79 0x2a _L1w_DevHsdpaSetHarqBufAckNack
+ 0x1004caa3 0x2f _L1w_DevHsdpaInitCqiInfo
+ 0x1004cad2 0xe2 _L1w_DevHsdpaCqiSendProc
+ 0x1004cbb4 0x4b _L1w_DevHsdpaSnrCalcCtrl
+ 0x1004cbff 0x81 _L1w_DevHsdpaCqiSendCtrl
+ 0x1004cc80 0x3c _L1w_DevHsdpaSaveHsdpcchInitCfg
+ 0x1004ccbc 0x4a _L1w_DevHsdpaSaveHsdpcchAckCfg
+ 0x1004cd06 0x49 _L1w_DevHsdpaSaveHsdpcchCqiCfg
+ 0x1004cd4f 0x2a _L1w_DevHsdpaTxInitSendProc
+ 0x1004cd79 0x52 _L1w_DevHsdpaTxSubFrmProc
+ .text 0x1004cdcb 0x1a89 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x1004cdcb 0x9a _L1w_DevHsdpaInitHarqInfo
+ 0x1004ce65 0x45 _L1w_DevHsdpaInitAdrPsrInfo
+ 0x1004ceaa 0x10 _L1w_DevHsdpaGenChMask
+ 0x1004ceba 0x28 _L1w_DevHsdpaIsHdtrValid
+ 0x1004cee2 0x1a _L1w_DevHsdpaSaveDemoduleCfg
+ 0x1004cefc 0x5f _L1w_DevHsdpaSaveDecodeCfg
+ 0x1004cf5b 0x181 _L1w_DevHsdpaTpuSaveIcPsrCfg
+ 0x1004d0dc 0xea _L1w_DevHsdpaTpuCalcCfgPara
+ 0x1004d1c6 0x153 _L1w_DevHsdpaTxTpuSaveIcPsrCfg
+ 0x1004d319 0xdc _L1w_DevHsdpaTxTpuCalcCfgPara
+ 0x1004d3f5 0x92 _L1w_DevHsdpaTpuSaveScrCodePara
+ 0x1004d487 0x93 _L1w_DevHsdpaTxTpuSaveScrCodePara
+ 0x1004d51a 0x151 _L1w_DevHsdpaSaveAdrIcSubFrmPara
+ 0x1004d66b 0x6e _L1w_DevHsdpaSaveAdrInitRcvCfg
+ 0x1004d6d9 0x47 _L1w_DevHsdpaSaveHsscchInitCfg
+ 0x1004d720 0xa5 _L1w_DevHsdpaSaveAdrSubFrmCfg
+ 0x1004d7c5 0x15 _L1w_DevHsdpaIsPart1Valid
+ 0x1004d7da 0x109 _L1w_DevHsdpaPart1Filter
+ 0x1004d8e3 0x96 _L1w_DevHsdpaDchSavePart1IntCfg
+ 0x1004d979 0x2b2 _L1w_DevHsdpaSavePart1IntCfg
+ 0x1004dc2b 0x97 _L1w_DevHsdpaHsscchTypeAnalyse
+ 0x1004dcc2 0x16 _L1w_DevHsdpaIsNeedAckNack
+ 0x1004dcd8 0x149 _L1w_DevHsdpaDchPart2Type1Proc
+ 0x1004de21 0x7e _L1w_DevHsdpaSaveHdtrHwCfg
+ 0x1004de9f 0x4e _L1w_DevHsdpaSaveHdtrCfgPara
+ 0x1004deed 0x2d _L1w_DevHsdpaHdtrCfg
+ 0x1004df1a 0x3e _L1w_DevHsdpaCalcShiftFactor
+ 0x1004df58 0x13e _L1w_DevHsdpaPart2Type1Proc
+ 0x1004e096 0x35 _L1w_DevHsdpaHsscchOrderProc
+ 0x1004e0cb 0x119 _L1w_DevHsdpaPart2IntTraceLog
+ 0x1004e1e4 0x15d _L1w_DevHsdpaDchHdtrIntProc
+ 0x1004e341 0x3c _L1w_DevHsdpaRxParaInit
+ 0x1004e37d 0x5d _L1w_DevHsdpaRxInitRcvProc
+ 0x1004e3da 0x5f _L1w_DevHsdpaRxIcRstFirstCfg
+ 0x1004e439 0xb9 _L1w_DevHsdpaRxSubFrmProc
+ 0x1004e4f2 0xd3 _L1w_DevHsdpaRxPart1IntProc
+ 0x1004e5c5 0x142 _L1w_DevHsdpaRxPart2IntProc
+ 0x1004e707 0x4e _L1w_DevHsdpaRxMacHeadAnalyse
+ 0x1004e755 0xcc _L1w_DevHsdpaRxHdtrIntProc
+ 0x1004e821 0x33 _L1w_DevHsdpaRxThDataUpdate
+ .text 0x1004e854 0x297 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x1004e854 0x1c _L1w_DevPcRachReset
+ 0x1004e870 0x1c _L1w_DevPcRachInit
+ 0x1004e88c 0x9b _L1w_DevPcPrachBeltaCalc
+ 0x1004e927 0x7 _L1w_DevPcPrachPreamblePowerEngGet
+ 0x1004e92e 0x7b _L1w_DevPcPrachPreamblePowerCtrl
+ 0x1004e9a9 0xf6 _L1w_DevPcPrachMessagePowerCtrl
+ 0x1004ea9f 0x34 _L1w_DevPcPrachStartReqHandle
+ 0x1004ead3 0x6 _L1w_DevPcPrachPreambleReqHandle
+ 0x1004ead9 0x12 _L1w_DevPcPrachMessageReqHandle
+ .text 0x1004eaeb 0xeba T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x1004eaeb 0x3a _L1w_HsupaCalcLowLim
+ 0x1004eb25 0x48 _L1w_HsupaFlt2Fix
+ 0x1004eb6d 0x21 _L1w_DevHsupaCalcHiFrameOffset
+ 0x1004eb8e 0xf _L1w_DevHsupaCalcRgFrameOffset
+ 0x1004eb9d 0x46 _L1w_DevHsupaCalcRgHiFrmOffset
+ 0x1004ebe3 0x1f _L1w_DevHsupaIsTtiCntValid
+ 0x1004ec02 0x14 _L1w_DevHsupaCalcTtiCntMod
+ 0x1004ec16 0x26 _L1w_DevHsupaIsDlChanFrontByTx
+ 0x1004ec3c 0x3e _L1w_DevHsupaReadRgHi
+ 0x1004ec7a 0x20 _L1w_DevHsupaLookUpTtiCm
+ 0x1004ec9a 0x15a _L1w_DevHsupaIsRgHiCm
+ 0x1004edf4 0x15c _L1w_DevHsupaReadAllRgHiInfo
+ 0x1004ef50 0x2 _L1w_DevHsupaReadHarqGrant
+ 0x1004ef52 0x91 _L1w_DevHsupaHiCombine
+ 0x1004efe3 0x90 _L1w_DevHsupaRgCombine
+ 0x1004f073 0xaf _L1w_DevHsupaIscpSlotCombine
+ 0x1004f122 0x87 _L1w_DevHsupaHiDecisonParam
+ 0x1004f1a9 0x46 _L1w_DevHsupaNackConfirm
+ 0x1004f1ef 0xa5 _L1w_DevHsupaSingleHiDecision
+ 0x1004f294 0xb2 _L1w_DevHsupaSingleRgDecision
+ 0x1004f346 0x14 _L1w_DevHsupaMulHiNsrlsDecision
+ 0x1004f35a 0x73 _L1w_DevHsupaMulRgNsrlsDecision
+ 0x1004f3cd 0x30 _L1w_DevHsupaTtiCnt2HarqId
+ 0x1004f3fd 0x84 _L1w_DevHsupaNsrlsHiCombDecis
+ 0x1004f481 0x47 _L1w_DevHsupaSrlsHICombDecis
+ 0x1004f4c8 0x4d _L1w_DevHsupaSrlsRGCombDecis
+ 0x1004f515 0x75 _L1w_DevHsupaGetRlIscp
+ 0x1004f58a 0xee _L1w_DevHsupaReadAllIscpInfo
+ 0x1004f678 0x39 _L1w_DevHsupaSingleHiCombDec
+ 0x1004f6b1 0x61 _L1w_DevHsupaHiCombAndDecision
+ 0x1004f712 0x3d _L1w_DevHsupaSingleRgCombDecis
+ 0x1004f74f 0x75 _L1w_DevHsupaNsrlsRGDecision
+ 0x1004f7c4 0x51 _L1w_DevHsupaRgIndProc
+ 0x1004f815 0x91 _L1w_DevHsupaCalcDisDlChanEdch
+ 0x1004f8a6 0xff _L1w_DevHsupaSetHarqInfo
+ .text 0x1004f9a5 0x4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dma.o)
+ 0x1004f9a5 0x1 _L1w_DrvDmaReset
+ 0x1004f9a6 0x1 _L1w_DrvDmaInit
+ 0x1004f9a7 0x1 _L1w_DrvDmaSingleMemcpy
+ 0x1004f9a8 0x1 _L1W_DMA_ISR
+ .text 0x1004f9a9 0x165 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa_epch.o)
+ 0x1004f9a9 0xd5 _L1w_SchedHsdpaPchCfgPSCmd
+ 0x1004fa7e 0x43 _L1w_SchedHsdpaPchRelPSCmd
+ 0x1004fac1 0x14 _L1w_SchedHsdpaPchPreSched
+ 0x1004fad5 0x1 _L1w_SchedHsdpaPchSched
+ 0x1004fad6 0x38 _L1w_SchedHsdpaPchSend2PS
+ .text 0x1004fb0e 0x12d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x1004fb0e 0x86 _zPHY_ModemOsProcessInit
+ 0x1004fb94 0x38 _zPHY_HwInit
+ 0x1004fbcc 0x1 _zPHY_FpgaPlatTopInit
+ 0x1004fbcd 0x5 _zPHY_ChipTopRegInit
+ 0x1004fbd2 0x69 _zPHY_LteaInit
+ .text 0x1004fc3b 0x210 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x1004fc3b 0xe _zPHY_NVInit_PreInit
+ 0x1004fc49 0x4b _zPHY_NVLteCopy
+ 0x1004fc94 0xd0 _zPHY_NVInit
+ 0x1004fd64 0x8 _L1e_CmnNvGetUeCategory
+ 0x1004fd6c 0x8 _L1e_CmnNvGetDlMimoCapability
+ 0x1004fd74 0xa _L1e_CmnNvGetRxAntNum
+ 0x1004fd7e 0xf _L1e_CmnNvGetRxRsrpInterval
+ 0x1004fd8d 0xf _L1e_CmnNvGetRxAntThreshold
+ 0x1004fd9c 0xa _L1e_CmnNvGetRxN1Timer
+ 0x1004fda6 0xa _L1e_CmnNvGetRxN2Timer
+ 0x1004fdb0 0x8 _L1e_CmnNvGetLteTempDetectEn
+ 0x1004fdb8 0x8 _L1e_CmnNvGetLteTxPwrBackoffEn
+ 0x1004fdc0 0x8 _L1e_CmnNvGetLteRxRateLimitEn
+ 0x1004fdc8 0x9 _L1e_CmnNvGetLteCqiThdParam
+ 0x1004fdd1 0xa _L1e_CmnNvGetLteRxTiAlgoCtrl
+ 0x1004fddb 0x11 _l1e_CmnZTERfSPIWrite
+ 0x1004fdec 0x20 _l1e_CmnZTERfSPIRead
+ 0x1004fe0c 0x3f _zPHY_erfc_TempReadPa
+ .text 0x1004fe4b 0xd86 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x1004fe4b 0x1 _zPHY_ErrorHandle
+ 0x1004fe4c 0x14 _zPHY_GetErrorName
+ 0x1004fe60 0x102 _zPHY_etmtlog_ThreadEntry
+ 0x1004ff62 0x5c _zPHY_VersionInfo
+ 0x1004ffbe 0x41 _L1e_CmnLogUpdateAbsSfn
+ 0x1004ffff 0xc6 _L1e_CmnLogClearVariableVal
+ 0x100500c5 0x1c8 _L1e_CmnLogDlTbCrcAndThroughPut
+ 0x1005028d 0x3b _L1e_CmnLogStatDlFlowByCc
+ 0x100502c8 0x11 _L1e_CmnLogStatDlThroughPut
+ 0x100502d9 0x45 _L1e_CmnLogDlDdtrCfgTimes
+ 0x1005031e 0x45 _L1e_CmnLogDlDdtrIntTimes
+ 0x10050363 0x86 _L1e_CmnLogStatDlRntiApplyCnt
+ 0x100503e9 0x52 _L1e_CmnLogStatPcfichChannel
+ 0x1005043b 0x15c _L1e_CmnLogStatPhichChannel
+ 0x10050597 0x2a9 _L1e_CmnLogStatPdcchChannel
+ 0x10050840 0xa _L1e_CmnLogStatDlCtrlChMonitor
+ 0x1005084a 0x9e _L1e_CmnLogStatDciDecodeInfo
+ 0x100508e8 0x42 _L1e_CmnLogGetRxTxBitmap
+ 0x1005092a 0x94 _L1e_CmnLogGetCalcSinrValByCc
+ 0x100509be 0x3 _L1e_CmnLogGetCalcSinrVal
+ 0x100509c1 0x24 _L1e_CmnLogStatUlFlowByCc
+ 0x100509e5 0x37 _L1e_CmnLogStatUlThroughPut
+ 0x10050a1c 0x1d _zPHY_GetUlQmMcs
+ 0x10050a39 0x2f _zPHY_GetDlQmMcs
+ 0x10050a68 0xa _zPHY_GetDlSinr
+ 0x10050a72 0x1d _zPHY_GetUlHarqNack
+ 0x10050a8f 0x22 _zPHY_GetDlHarqNack
+ 0x10050ab1 0xf _zPHY_GetDlThrougput
+ 0x10050ac0 0xf _zPHY_GetUlThrougput
+ 0x10050acf 0x1a _zPHY_UlResidualBlerCount
+ 0x10050ae9 0xd _zPHY_AtGetPowerHeadroom
+ 0x10050af6 0x9 _zPHY_AtGetPcmax
+ 0x10050aff 0x26 _zPHY_AtGetRsrpDbm
+ 0x10050b25 0x2a _zPHY_AtGetRssiDbm
+ 0x10050b4f 0x42 _zPHY_AtGetResidualBlerByCc
+ 0x10050b91 0x26 _zPHY_AtGetResidualBler
+ 0x10050bb7 0x1a _zPHY_AtClearVariableVal
+ .text 0x10050bd1 0xbb9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x10050bd1 0x117 _zPHY_Tpu_ExtraCheck
+ 0x10050ce8 0x2a _L1L_TpuAdjCnfMsg
+ 0x10050d12 0x293 _L1L_TpuCpModeSwitchProc
+ 0x10050fa5 0x40 _L1L_TpuDevFixedIntRegister
+ 0x10050fe5 0x3d _L1L_TpuDevTimerUnRegister
+ 0x10051022 0x63 _L1L_TpuMicroAdj
+ 0x10051085 0x7 _L1L_TpuDevMsgDelayMsgTimerRegister
+ 0x1005108c 0x6 _L1L_TpuDevMsgDelayCBTimerRegister
+ 0x10051092 0x15 _L1L_TpuDevRelativeMsgTimerRegister
+ 0x100510a7 0x13 _L1L_TpuDevRelativeCBTimerRegister
+ 0x100510ba 0x36 _L1L_TpuDevMrtrTimeTypeMsgTimerRegister
+ 0x100510f0 0x35 _L1L_TpuDevMrtrTimeTypeCBTimerRegister
+ 0x10051125 0x20 _L1L_TpuSuperSlotGet
+ 0x10051145 0x21 _L1L_TpuMrtrFormat
+ 0x10051166 0x1c _L1L_TpuLocalMrtr2FreeMrtr
+ 0x10051182 0x1c _L1L_TpuFreeMrtr2LocalMrtr
+ 0x1005119e 0xb4 _L1L_TpuProUpdateLocalMRTR
+ 0x10051252 0xa _L1L_TpuTimeSub
+ 0x1005125c 0x13 _L1L_TpuTimeAdd
+ 0x1005126f 0x4d _L1L_TpuTs2Time
+ 0x100512bc 0x17 _L1L_TpuTime2Ts
+ 0x100512d3 0x34 _L1L_TpuMrtrAdd
+ 0x10051307 0x40 _L1L_TpuMrtrSub
+ 0x10051347 0x443 _zPHY_LTE_TPU_ThreadEntry
+ .text 0x1005178a 0x677 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x1005178a 0x40 _zPHY_ecsi_HNoDMA
+ 0x100517ca 0x1 _zPHY_ecsi_PCellCSI_En
+ 0x100517cb 0x1 _zPHY_ecsi_SCellCSI_En
+ 0x100517cc 0x49 _zPHY_ecsi_Init
+ 0x10051815 0x2c _zPHY_ecsi_PCellCommParmUpdate
+ 0x10051841 0x9b _zPHY_ecsi_PCellDediParmUpdate
+ 0x100518dc 0xb7 _zPHY_ecsi_PCellHOParmUpdate
+ 0x10051993 0xd3 _zPHY_ecsi_MsgResponse
+ 0x10051a66 0x2d _zPHY_ecsi_ctrl_GetNodeTXAttennaNum
+ 0x10051a93 0x8c _zPHY_ecsi_CbResSetGet
+ 0x10051b1f 0x2c _zPHY_ecsi_PerCqiParaGet
+ 0x10051b4b 0x23 _zPHY_ecsi_CqiRowAParaCalc
+ 0x10051b6e 0x5c _zPHY_ecsi_PcellCsiRepParaDediGet
+ 0x10051bca 0x3f _zPHY_ecsi_ScellCsiRepParaDediGet
+ 0x10051c09 0x12 _zPHY_ecsi_CsiRsParaGet
+ 0x10051c1b 0x28 _zPHY_ecsi_CSITimeUpdate
+ 0x10051c43 0xac _zPHY_ecsi_FlowPrint
+ 0x10051cef 0x1 _zPHY_ecsi2dl_CHECfg
+ 0x10051cf0 0xab _zPHY_ecsi_Start
+ 0x10051d9b 0x66 _zPHY_ecsi_CSIAThreadEntry
+ .text 0x10051e01 0x104d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x10051e01 0x26 _L1e_DevDlsGetTbCrc
+ 0x10051e27 0x16 _L1e_DevDlsGetTbCbCrc
+ 0x10051e3d 0x9c _L1e_DevDlsSetDlHarqFlag
+ 0x10051ed9 0x43 _L1e_DevDlsGetDdtrWorkSf
+ 0x10051f1c 0x89 _zPHY_edls_ProCwCrcGeneration
+ 0x10051fa5 0xfa _zPHY_edls_ProTddCwCrcFeedback
+ 0x1005209f 0x56 _zPHY_edls_ProFddCwCrcFeedback
+ 0x100520f5 0x115 _zPHY_edls_ProHarqFeedbackInfo
+ 0x1005220a 0x11e _zPHY_edls_ProDdtrHbitInt
+ 0x10052328 0xb3 _zPHY_edls_ProDdtrIntDtch
+ 0x100523db 0xa2 _zPHY_edls_ProDdtrIntSibPch
+ 0x1005247d 0x64 _L1e_DbgDlsDecPchInfo
+ 0x100524e1 0x2d _L1e_DevDlsPageMatch
+ 0x1005250e 0x5e _L1e_DevDlsPchMessagePro
+ 0x1005256c 0x5b _L1e_DevDlsPchReportInd
+ 0x100525c7 0x56 _zPHY_edls_ProPchDataProc
+ 0x1005261d 0x48 _zPHY_edls_ProSibDataProc
+ 0x10052665 0x5b _zPHY_edls_ProPchStatAndPrint
+ 0x100526c0 0x53 _zPHY_edls_ProSibStatAndPrint
+ 0x10052713 0x75 _zEumacdl_CrExist
+ 0x10052788 0x285 _L1e_DevDlsCfgMacPduCtrlInfo
+ 0x10052a0d 0x32 _L1e_DevDlsReportMacPdu
+ 0x10052a3f 0x1dc _zPHY_edls_ProDschIntThread
+ 0x10052c1b 0x5c _zPHY_edls_ProMsg2RaRntiMacPdu
+ 0x10052c77 0x36 _zPHY_edls_PDschIsr
+ 0x10052cad 0x7f _L1e_DbgDlsAckNakRptInfo
+ 0x10052d2c 0x122 _L1e_DbgDlsDecStatInfo
+ .text 0x10052e4e 0x6f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x10052e4e 0x51 _zPHY_edls_ProPdcchIntThread
+ 0x10052e9f 0x44 _zPHY_edls_ProMsg4CRntiPdcch
+ 0x10052ee3 0x6a _zPHY_edls_DciIsr
+ 0x10052f4d 0xc _zPHY_edls_ProSetVoLteTime
+ 0x10052f59 0x23 _zLtePsPhy_RemoteMalloc
+ 0x10052f7c 0x35 _zPHY_edls_ProStoreSpsInfo
+ 0x10052fb1 0x17 _L1e_DevDlsRstRxRbBmpReg
+ 0x10052fc8 0x42 _L1e_DevDlsRefSenCntPro
+ 0x1005300a 0x72 _L1e_DevDlsRefSenPro
+ 0x1005307c 0xf _L1e_DevDlsBfInd
+ 0x1005308b 0x39 _zPHY_edls_DdtrHwIdleState
+ 0x100530c4 0x25 _L1x_DevDlsInOutJudge
+ 0x100530e9 0x4e _L1e_DbgDlsCommDecInfo
+ 0x10053137 0xce _L1e_DbgDlsDciInfo
+ 0x10053205 0x51 _L1e_DbgDlsDecErr
+ 0x10053256 0x1 _L1e_DbgDlsValidRptInfo
+ 0x10053257 0x58 _zPHY_edls_ProDbgSpsDciDetInfo
+ 0x100532af 0x291 _zPHY_edls_DbgHarqDdrClose
+ .text 0x10053540 0x2d58 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x10053540 0x3a _zPHY_erfc_ProSetRamSFNumForLargeAdj
+ 0x1005357a 0x46 _zPHY_erfc_ProGetMeas0RamNum
+ 0x100535c0 0x37 _zPHY_erfc_ProGetTxRamNum
+ 0x100535f7 0x34 _zPHY_erfc_ProGetNextSubFrameOffset
+ 0x1005362b 0x96 _zPHY_erfc_SupLteTxEnableCtrl
+ 0x100536c1 0xc _zPHY_erfc_ProSpecSubfrmCheck
+ 0x100536cd 0x23 _zPHY_erfc_ProTxSendCtrl
+ 0x100536f0 0x25 _zPHY_erfc_SupDFESubframeStartCtl
+ 0x10053715 0x311 _zPHY_erfc_ProRamCtrl
+ 0x10053a26 0x1 _zPHY_erfc_ProPrintProcess
+ 0x10053a27 0x27 _zPHY_erfc_ProNotchProCtrl
+ 0x10053a4e 0x10 _zPHY_erfc_ProGetFreqBandNum
+ 0x10053a5e 0x238 _zPHY_erfc_TDDProRFABB_RxToRx
+ 0x10053c96 0xe1 _zPHY_erfc_TDDProRFABB_RxToIdle
+ 0x10053d77 0x4c _zPHY_erfc_TDDProRFABB_RxToTx
+ 0x10053dc3 0x31 _zPHY_erfc_TDDProRFABB_IdleToTx
+ 0x10053df4 0x2ee _zPHY_erfc_TDDProRFABB_IdleToRx
+ 0x100540e2 0x1 _zPHY_erfc_TDDProRFABB_IdleToIdle
+ 0x100540e3 0x30 _zPHY_erfc_TDDProRFABB_TxToIdle
+ 0x10054113 0x108 _zPHY_erfc_TDDProRFABB_TxToRx
+ 0x1005421b 0x1 _zPHY_erfc_TDDProRFABB_TxToTx
+ 0x1005421c 0x58 _zPHY_erfc_ATSetAndReadRfReg
+ 0x10054274 0x534 _zPHY_erfc_ProRFABBCtrl
+ 0x100547a8 0xa07 _zPHY_erfc_ProRFABBCtrl_FDD
+ 0x100551af 0x5b _zPHY_erfc_Pro_IFTempNeedFix
+ 0x1005520a 0x343 _zPHY_erfc_ProRFCWork
+ 0x1005554d 0x58 _zPHY_erfc_ProRxOffsetAutoCtrl
+ 0x100555a5 0x10 _zPHY_erfc_ProTAOffsetAutoCtrl
+ 0x100555b5 0x3b8 _zPHY_erfc_ProTxAndRxOffsetCtrl
+ 0x1005596d 0xe _zPHY_erfc_ProRFSDInit
+ 0x1005597b 0xa _zPHY_erfc_ProRFCSA_CSRConfig
+ 0x10055985 0xe _zPHY_erfc_ProRFCSA_RXConfig
+ 0x10055993 0xa _zPHY_erfc_ProRFCSA_TXConfig
+ 0x1005599d 0x95 _zPHY_erfc_ProRFSDAndRFCSAInit
+ 0x10055a32 0x4b _zPHY_erfc_RpiCfg
+ 0x10055a7d 0x1d _zPHY_erfc_RpiSet
+ 0x10055a9a 0x5d _zPHY_erfc_RpiPwrCtrl
+ 0x10055af7 0x72 _zPHY_erfc_ProRFCSAInit
+ 0x10055b69 0x6f _zPHY_erfc_ProRFCInit
+ 0x10055bd8 0x54 _zPHY_erfc_ProRFCInitPointer
+ 0x10055c2c 0x18d _zPHY_erfc_ProRfsdCheck_FDD
+ 0x10055db9 0x3f _zPHY_erfc_CheckNextSccRfcToIdle
+ 0x10055df8 0x17 _zPHY_erfc_ProGetRFCCurrentState
+ 0x10055e0f 0x1e2 _zPHY_erfc_ThreadEntry
+ 0x10055ff1 0x16 _zPHY_erfc_GetRfcMeasStatus
+ 0x10056007 0x19 _zPHY_erfc_TjpAlgorithm
+ 0x10056020 0x3d _zPHY_erfc_CalcMeasSubfNum
+ 0x1005605d 0x3f _zPHY_erfc_CalcSyncSubfNum
+ 0x1005609c 0x1a _zPHY_erfc_IntraFrameTimeComp
+ 0x100560b6 0x1 _zPHY_erfc_ProCleanHWTable
+ 0x100560b7 0x47 _zPHY_erfc_LTXTxTaConfig
+ 0x100560fe 0x36 _zPHY_erfc_ProCopyTxPccParaToScc
+ 0x10056134 0x1 _zPHY_erfc_RXTX_PathTest
+ 0x10056135 0x27 _zPHY_erfc_MainSlave_InterSwitch
+ 0x1005615c 0x5b _zPHY_erfc_GetTxTabAdjust
+ 0x100561b7 0xa _zPHY_erfc_GetFixDlDelay
+ 0x100561c1 0xd _L1l_DevRfcRxOffsetGet
+ 0x100561ce 0xd _L1l_DevRfcTaTimingGet
+ 0x100561db 0x9 _L1l_DevRfcRatModeSet
+ 0x100561e4 0xc _L1l_DevRfcTmpReadEn
+ 0x100561f0 0x9a _L1l_DevRfcTmpReadCtrl
+ 0x1005628a 0x7 _L1l_DevRfcSetOffsetFlag
+ 0x10056291 0x7 _L1l_DevRfcGetOffsetFlag
+ .text 0x10056298 0x2c1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x10056298 0xf _zPHY_eCSI_Calc_MultiPmiAddr_Init
+ 0x100562a7 0x8 _OSMemCopy16
+ 0x100562af 0x6 _OSMemCopy32
+ 0x100562b5 0x23 _IsTM9_PMIRIEn_CSIRS_2_4
+ 0x100562d8 0x16 _IsTM8_PMIRIEn
+ 0x100562ee 0x1a _zPHY_eCSI_Calc_Sort
+ 0x10056308 0x27 _zPHY_eCSI_Calc_MaxM
+ 0x1005632f 0x16 _zPHY_eCSI_Calc_CapMaxVal
+ 0x10056345 0x20 _zPHY_eCSI_Calc_GetSubbandIdx
+ 0x10056365 0x6c _zPHY_eCSI_Calc_eesm
+ 0x100563d1 0x59 _zPHY_eRLM_Calc_eesm
+ 0x1005642a 0x161 _zPHY_eCSI_Calc_LookupCqiTable
+ 0x1005658b 0x47 _zPHY_eCSI_Calc_WideTotalCapCalc
+ 0x100565d2 0x33 _zPHY_eCSI_Calc_WideTotalCapCalc_PerRI
+ 0x10056605 0x8e _zPHY_eCSI_Calc_WideHigh2UESubCap
+ 0x10056693 0x10c _zPHY_eCSI_Calc_BPMI
+ 0x1005679f 0x3e _zPHY_eCSI_Calc_SPMI
+ 0x100567dd 0x185 _zPHY_eCSI_Calc_RI_TM3
+ 0x10056962 0x127 _zPHY_eCSI_Calc_WPMI_TM4_LastRI
+ 0x10056a89 0x2d0 _zPHY_eCSI_Calc_RI_WPMI_TM4
+ 0x10056d59 0xe5 _zPHY_eCSI_Adjust_RI_PMI
+ 0x10056e3e 0x2e4 _zPHY_eCSI_Calc_RI_PMI
+ 0x10057122 0xd6 _zPHY_eCSI_Calc_WbCQICalc
+ 0x100571f8 0x98 _zPHY_eCSI_Calc_NoPmiGetMsbIdx
+ 0x10057290 0x82 _zPHY_eCSI_Calc_MsbCqiCalc
+ 0x10057312 0xc1 _zPHY_eCSI_Calc_SbCqiCalc
+ 0x100573d3 0x16 _zPHY_eCSI_Calc_Curr_SBSize_Get
+ 0x100573e9 0xcf _zPHY_eCSI_Calc_BpCqiCalc
+ 0x100574b8 0x6d _zPHY_eCSI_Calc_AperSbCqiUpDown
+ 0x10057525 0xb7 _zPHY_eCSI_Calc_AperCQI
+ 0x100575dc 0x9e _zPHY_eCSI_Calc_PerCQI
+ 0x1005767a 0x33 _zPHY_eCSI_Calc_Radio_Monitor
+ 0x100576ad 0x19 _zPHY_eCSI_Calc_BitReversal
+ 0x100576c6 0xf _zPHY_eCSI_Calc_GetPmiBitNum
+ 0x100576d5 0x13 _zPHY_eCSI_Calc_GetMSubbandDifferentCqiValue
+ 0x100576e8 0xf _zPHY_eCSI_Calc_GetSubbandDifferentCqiValue
+ 0x100576f7 0x30 _zPHY_eCSI_CalcMSubbandPosition
+ 0x10057727 0x18 _zPHY_eCSI_FindDiffCQI
+ 0x1005773f 0x297 _zPHY_eCSI_PER_BagPack
+ 0x100579d6 0x5ea _zPHY_eCSI_APER_BagPack
+ 0x10057fc0 0x29 _zPHY_eCSI_PER_PmiBitLen_Estimate
+ 0x10057fe9 0x52 _zPHY_eCSI_APER_PmiBitLen_Estimate
+ 0x1005803b 0x1d _zPHY_ecqi_GetLookTableSNR
+ 0x10058058 0x70 _zPHY_ecsi_Calc_Pow10_inDiv10
+ 0x100580c8 0x3e _zPHY_ecsi_Calc_Get_InvRow_feedA
+ 0x10058106 0x49 _zPHY_ecqi_Calc_Get_InvRowB_lin
+ 0x1005814f 0x243 _zPHY_ecqi_Calc_CSIRltPrint
+ 0x10058392 0x8e _zPHY_eCSI_Calc_ParaInitInDedi
+ 0x10058420 0x211 _zPHY_ecqi_SnrConv
+ 0x10058631 0x1 _zPHY_ecqi_CQISnrPrint
+ 0x10058632 0x1 _zPHY_ecqi_RlmSnrPrint
+ 0x10058633 0x1 _zPHY_ecqi_RiCapPrint
+ 0x10058634 0x60 _zPHY_ecqi_CQIFilter
+ 0x10058694 0x88 _zPHY_ecqi_Sqrt
+ 0x1005871c 0x126 _zPHY_ecsi_Calc_EstiFormatTransform
+ 0x10058842 0x11 _zPHY_ecsi_Calc_LTE_RICapFollowHw0
+ 0x10058853 0x12 _zPHY_ecsi_Calc_LTE_RICapFollowHw1
+ 0x10058865 0x16 _zPHY_ecsi_Calc_LTE_RICapFollowHw2
+ 0x1005887b 0x1c _zPHY_ecsi_Calc_LTE_RICapFollowHw4
+ 0x10058897 0x149 _zPHY_ecsi_Calc_LTE_RICloseLoop
+ 0x100589e0 0x18b _zPHY_ecsi_Calc_LTE_RIOpenLoop
+ 0x10058b6b 0x90 _zPHY_ecsi_Calc_LTE_2Tx2Rx2LWbPMI
+ 0x10058bfb 0xb1 _zPHY_ecsi_Calc_LTE_PeriodWBPmi
+ 0x10058cac 0x79 _zPHY_ecsi_Calc_LTE_GetCQICalcFunc
+ 0x10058d25 0xab _zPHY_ecsi_Calc_LTE_GetCQISNR
+ 0x10058dd0 0x16 _zPHY_ecsi_Calc_LTE_PerCQISNRCalc
+ 0x10058de6 0x94 _zPHY_ecsi_Calc_LTE_AperCQISNRCalc
+ 0x10058e7a 0x3b _zPHY_ecsi_Calc_LTE_RLMSNRCalc
+ .text 0x10058eb5 0x1592 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x10058eb5 0x1b _zPHY_Dl_HwReset
+ 0x10058ed0 0x2a0 _zPHY_epbch_ThreadEntry
+ 0x10059170 0x9a _L1e_Bch_UpdateRxRegs
+ 0x1005920a 0xa _L1e_Bch_ResetProc
+ 0x10059214 0x19 _L1e_Bch_ClkPowerCtrl
+ 0x1005922d 0x2e _L1e_Bch_JudgeSlavePbch
+ 0x1005925b 0x6 _L1e_Bch_GetMaxAntCnt
+ 0x10059261 0x1b _L1e_Bch_BwValid
+ 0x1005927c 0x10 _L1e_Bch_AntValid
+ 0x1005928c 0x7 _L1e_Bch_FrmTyeValid
+ 0x10059293 0x7 _L1e_Bch_SpecPatValid
+ 0x1005929a 0x8e _L1e_Bch_UpdateDb
+ 0x10059328 0x72 _L1e_Bch_CellSync
+ 0x1005939a 0x2b _L1e_Bch_UpRxCtrlOps
+ 0x100593c5 0x8 _L1e_Bch_ClrSyncOps
+ 0x100593cd 0x7 _L1e_Bch_QuerySyncOps
+ 0x100593d4 0x45 _L1e_Bch_PreDecProc
+ 0x10059419 0x3f _L1e_Bch_UpRxState
+ 0x10059458 0x2d _L1e_Bch_InitAllGVar
+ 0x10059485 0x2a _L1e_Bch_AddSpecTpuEvt
+ 0x100594af 0x2d _L1e_Bch_DelAllTpuEvt
+ 0x100594dc 0x1d _L1e_Bch_DelSpecTpuEvt
+ 0x100594f9 0x1a _L1e_Bch_QueryTpuEvt
+ 0x10059513 0x31 _L1e_Bch_CalStartAddr
+ 0x10059544 0x1b _L1e_Bch_GetTpuOffset
+ 0x1005955f 0x43 _L1e_Bch_CalBodryDis
+ 0x100595a2 0x1c _L1e_Bch_RegRxNewFrmEvt
+ 0x100595be 0x1 _L1e_Bch_SaveRfcSyncTable
+ 0x100595bf 0x5e _L1e_Bch_UpRfcCfg
+ 0x1005961d 0x39 _L1e_Bch_RegTpuAdjEvt
+ 0x10059656 0x86 _L1e_Bch_InitBchRegFile
+ 0x100596dc 0x72 _L1e_Bch_GenRxRsScrm
+ 0x1005974e 0xc9 _L1e_Bch_InitRxRegFile
+ 0x10059817 0x6e _L1e_Bch_GetSfnOffset
+ 0x10059885 0x5d _L1e_Bch_StopMibProc
+ 0x100598e2 0x64 _L1e_Bch_Decode
+ 0x10059946 0x89 _L1e_Bch_RltReport
+ 0x100599cf 0x11 _L1e_Bch_StartMib
+ 0x100599e0 0xe _L1e_Bch_GetMibIntCnt
+ 0x100599ee 0x2b _L1e_Bch_ModifyParaForBldDetect
+ 0x10059a19 0x2a _L1e_Bch_StartAnr
+ 0x10059a43 0x45 _L1e_Bch_AnrDecPorc
+ 0x10059a88 0xa7 _L1e_Bch_FrmIntCheck
+ 0x10059b2f 0xc _L1e_Bch_FristBchFrm
+ 0x10059b3b 0xe2 _L1e_Bch_NewFrmDecPorc
+ 0x10059c1d 0x1a _L1e_Bch_EnableSF0RxRcv
+ 0x10059c37 0x9a _L1e_Bch_AdjTpuTime
+ 0x10059cd1 0x18 _L1e_Bch_GetMibResult
+ 0x10059ce9 0x14 _L1e_Bch_CalcInitFrm
+ 0x10059cfd 0x1c _L1e_Bch_MibInfoCheck
+ 0x10059d19 0x3a _L1e_Bch_HandleCrcResult
+ 0x10059d53 0x18 _L1e_Bch_NxtBranchCtrl
+ 0x10059d6b 0xf0 _L1e_Bch_StartNxtDecode
+ 0x10059e5b 0x66 _L1e_Bch_DecideNxtDecode
+ 0x10059ec1 0x5c _L1e_Bch_IntHandle
+ 0x10059f1d 0x49 _L1e_Bch_SaveDlapara
+ 0x10059f66 0x47 _L1e_Bch_ResumeDlapara
+ 0x10059fad 0x53 _L1e_Bch_GetNCellRsNullInd
+ 0x1005a000 0x2e _L1e_Bch_GetNCellRsNullValid
+ 0x1005a02e 0x17 _L1e_Bch_WriteIntraMeasResult
+ 0x1005a045 0x90 _L1e_Bch_GetIntraMeasResult
+ 0x1005a0d5 0x6f _L1e_Bch_SortIntraMeasResult
+ 0x1005a144 0x8 _L1e_Bch_GetMibProc
+ 0x1005a14c 0x6d _L1e_Bch_Performance
+ 0x1005a1b9 0x17 _L1e_Bch_ErrorMoniter
+ 0x1005a1d0 0xc4 _L1e_Bch_RxRsrpMoniter
+ 0x1005a294 0x38 _L1e_Bch_MibReqMonitor
+ 0x1005a2cc 0x59 _L1e_Bch_RfcTpuMonitor
+ 0x1005a325 0x67 _L1e_Bch_IntRptMonitor
+ 0x1005a38c 0x6c _L1e_Bch_CrcRltMonitor
+ 0x1005a3f8 0x32 _L1e_Bch_RxParaMonitor
+ 0x1005a42a 0x1d _L1e_Bch_SerPbchRead
+ .text 0x1005a447 0x9e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x1005a447 0x7b _zPHY_edls_DlHarqReport
+ 0x1005a4c2 0x35 _zPHY_edls_ProDlHarqInit
+ 0x1005a4f7 0x6d _zPHY_edls_ProGvInit
+ 0x1005a564 0x8c _zPHY_edls_ProCommDlschParaInit
+ 0x1005a5f0 0x42 _zPHY_edls_ProSwInit
+ 0x1005a632 0xc _zPHY_edls_ProMcReleaseMsg
+ 0x1005a63e 0x4c _zPHY_edls_ProMsg4AckFeedback
+ 0x1005a68a 0xc _zPHY_edls_ProMcResetMsg
+ 0x1005a696 0x23 _zPHY_edls_ProMcMacResetMsg
+ 0x1005a6b9 0x27 _zPHY_edls_CheckHarqGroupNum
+ 0x1005a6e0 0x116 _zPHY_edls_ThreadEntry
+ 0x1005a7f6 0x4a _zPHY_edls_ProCommDlschParaCal
+ 0x1005a840 0x1 _L1e_DevDlsDdtrAxiReset
+ 0x1005a841 0x1 _L1e_DevDlsProcAxiReset
+ 0x1005a842 0xbe _L1e_DevDlsUeRacpParamInit
+ 0x1005a900 0x4b _L1e_DevDlsDecoderInit
+ 0x1005a94b 0x3e _L1e_DevDlsHarqHwInit
+ 0x1005a989 0x6c _L1e_DevDlsDdtrHwInit
+ 0x1005a9f5 0x17 _L1e_DevDlsRxTMIndCfg
+ 0x1005aa0c 0x1f _L1e_DevDlsSpsParamCfg
+ 0x1005aa2b 0x45 _L1e_DevDlsCsiRsParamCfg
+ 0x1005aa70 0x6d _L1e_DevDlsProcCommonMsg
+ 0x1005aadd 0x5e _L1e_DevDlsProcDedicatedMsg
+ 0x1005ab3b 0xa5 _L1e_DevDlsProcHandoverMsg
+ 0x1005abe0 0x8 _zPHY_edls_ProSetSpsMode
+ 0x1005abe8 0x8 _zPHY_edls_ProGetSpsMode
+ 0x1005abf0 0xe _L1e_DevDlsSetTimeInfo
+ 0x1005abfe 0xd _L1e_DevDlsSetCellParam1
+ 0x1005ac0b 0xd _L1e_DevDlsSetCellparam2
+ 0x1005ac18 0xd _L1e_DevDlsSetRntiInfo
+ 0x1005ac25 0xf _L1e_DevDlsGetTimeInfo
+ 0x1005ac34 0x1a _L1e_DevDlsGetCellParam1
+ 0x1005ac4e 0x1a _L1e_DevDlsGetCellParam2
+ 0x1005ac68 0x1a _L1e_DevDlsGetRntiInfo
+ 0x1005ac82 0x19 _L1e_DevDlsSetDciF1aPld
+ 0x1005ac9b 0x10 _L1e_DevDlsSetDciF1cPld
+ 0x1005acab 0x10 _L1e_DevDlsSetDciFxxPld
+ 0x1005acbb 0xe _L1e_DevDlsSetDciCifSize
+ 0x1005acc9 0xe _L1e_DevDlsSetDciRaHeaderSize
+ 0x1005acd7 0x10 _L1e_DevDlsSetDciRbaSize
+ 0x1005ace7 0xe _L1e_DevDlsSetDciHarqIdSize
+ 0x1005acf5 0xe _L1e_DevDlsSetDciDaiSize
+ 0x1005ad03 0xe _L1e_DevDlsSetDciTpmiSize
+ 0x1005ad11 0xe _L1e_DevDlsSetDciScidSize
+ 0x1005ad1f 0xe _L1e_DevDlsSetDciSrsReqSize
+ 0x1005ad2d 0x1a _L1e_DevDlsGetDciF1aPld
+ 0x1005ad47 0x10 _L1e_DevDlsGetDciF1cPld
+ 0x1005ad57 0x10 _L1e_DevDlsGetDciFxxPld
+ 0x1005ad67 0xd _L1e_DevDlsGetDciCifSize
+ 0x1005ad74 0xd _L1e_DevDlsGetDciRaHeaderSize
+ 0x1005ad81 0x11 _L1e_DevDlsGetDciRbaSize
+ 0x1005ad92 0xd _L1e_DevDlsGetDciHarqIdSize
+ 0x1005ad9f 0xd _L1e_DevDlsGetDciDaiSize
+ 0x1005adac 0xd _L1e_DevDlsGetDciTpmiSize
+ 0x1005adb9 0xd _L1e_DevDlsGetDciScidSize
+ 0x1005adc6 0xd _L1e_DevDlsGetDciSrsReqSize
+ 0x1005add3 0x8 _L1e_DevDlsDdtrUpdateCntCbInit
+ 0x1005addb 0xc _L1e_DevDlsDdtrUpdateCntInc
+ 0x1005ade7 0xc _L1e_DevDlsDdtrUpdateCntClr
+ 0x1005adf3 0x9 _L1e_DevDlsGetDdtrCcUpdateCnt
+ 0x1005adfc 0x7 _L1e_DevDlsGetDdtrUpdateCnt
+ 0x1005ae03 0x7 _L1e_DevDlsSetMsg4RaConflictCnt
+ 0x1005ae0a 0x7 _L1e_DevDlsGetMsg4RaConflictCnt
+ 0x1005ae11 0x9 _L1e_DevDlsMsg4RaConflictCntDec
+ 0x1005ae1a 0x8 _L1e_DevDlsMsg4RaConflictCntClr
+ 0x1005ae22 0x8 _L1e_DevDlsGetTransMode
+ .text 0x1005ae2a 0xbf2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x1005ae2a 0x69 _zPHY_ecsi_ctrl_Init
+ 0x1005ae93 0x80 _zPHY_ecsi_StaticBandParaUpdata
+ 0x1005af13 0x28 _zPHY_ecsi_ctrl_PeriodParaUpdate
+ 0x1005af3b 0x7a _zPHY_ecsi_ctrl_AperiodParaUpdate
+ 0x1005afb5 0x7d _zPHY_ecsi_ctrl_AperRepJudge
+ 0x1005b032 0x3f _zPHY_ecsi_ctrl_GetSubbandIdx
+ 0x1005b071 0x51 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcTDD
+ 0x1005b0c2 0x57 _zPHY_ecsi_ctrl_CqiPmiConfigIndexCalcFDD
+ 0x1005b119 0x32 _zPHY_ecsi_ctrl_RiConfigIndexCalc
+ 0x1005b14b 0x6b _zPHY_ecsi_ctrl_GetPeriodPara
+ 0x1005b1b6 0x14a _zPHY_ecsi_ctrl_GetPeriodRepType
+ 0x1005b300 0xcb _zPHY_ecsi_ctrl_LastRIInit
+ 0x1005b3cb 0x4a _zPHY_ecsi_ctrl_GetMaxLayerNum
+ 0x1005b415 0x71 _zPHY_ecsi_ctrl_SecondCfg
+ 0x1005b486 0x8 _zPHY_ecsi_ctrl_SentCqiRlmProMsg
+ 0x1005b48e 0xc _zPHY_ecsi_ctrl_RlmProEn
+ 0x1005b49a 0x87 _zPHY_ecsi_ctrl_FirIntPrint
+ 0x1005b521 0xa9 _zPHY_ecsi_ctrl_FdBkFirst_IntIsr
+ 0x1005b5ca 0x1e _zPHY_ecsi_ctrl_FdBkSecond_IntIsr
+ 0x1005b5e8 0x1b _zPHY_ecsi_ctrl_FdBk_IntIsr
+ 0x1005b603 0x5c _zPHY_ecsi_ctrl_First_GetEnStep1
+ 0x1005b65f 0x69 _zPHY_ecsi_ctrl_FdBkFirCfgAper
+ 0x1005b6c8 0xbd _zPHY_ecsi_ctrl_FdBkFirCfgPer
+ 0x1005b785 0xcd _zPHY_ecsi_ctrl_First_FdBkCfg
+ 0x1005b852 0x3a _zPHY_ecsi_ctrl_ULGetCSI_Callback
+ 0x1005b88c 0x71 _zPHY_ecsi_Ctrl_CqiRlmCalc
+ 0x1005b8fd 0x2f _zPHY_ecsi_ctrl_PreBagPack
+ 0x1005b92c 0x33 _zPHY_ecsi_ctrl_FindPreDlSfn
+ 0x1005b95f 0xbd _zPHY_ecsi_ctrl_DrxRfZspCtrl
+ .text 0x1005ba1c 0x1ab3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x1005ba1c 0x7 _L1e_DevRxGetAveSinr
+ 0x1005ba23 0x1d _zPHY_erxp_convert_RbNum_to_BWIdx
+ 0x1005ba40 0x7 _L1e_DevRxCirSetIdleAccessReqInd
+ 0x1005ba47 0x7 _L1e_DevRxCirGetIdleAccessReqInd
+ 0x1005ba4e 0x1b2 _zPHY_erxph_ThreadEntry
+ 0x1005bc00 0x173 _L1e_DevRxPowerPrepare
+ 0x1005bd73 0x55 _L1e_DevRxGetSnrFilterFactor
+ 0x1005bdc8 0xa0 _zPHY_erxp_PowerFilterInit
+ 0x1005be68 0x97 _zPHY_erxp_ProPowerFilter
+ 0x1005beff 0x149 _zPHY_erxp_ProSnrMake
+ 0x1005c048 0x64 _zPHY_erxp_ProSnrDB
+ 0x1005c0ac 0x54 _zPHY_erxp_ProLog2
+ 0x1005c100 0x19e _L1e_DevRxProcPwrNbnb
+ 0x1005c29e 0x8a _L1e_DevRxCalcRsrpPwr
+ 0x1005c328 0x36 _L1e_DevRxProcSnrPwrFilter
+ 0x1005c35e 0x50 _L1e_DevRxCalcLinearSnr
+ 0x1005c3ae 0x3e _L1e_DevRxCalcLinearSinr
+ 0x1005c3ec 0x5c _L1e_DevRxConvertSnrDbValue
+ 0x1005c448 0x88 _L1e_DevRxCalcAveSnr
+ 0x1005c4d0 0xa _L1e_DevRxGetAveSnr
+ 0x1005c4da 0xa _L1e_DevRxGetNeiAveSnr
+ 0x1005c4e4 0x14 _L1e_DevRxCalSign
+ 0x1005c4f8 0xa6 _L1e_DevRxCalcMod
+ 0x1005c59e 0x6e _L1e_DevRxDbgMsgRxCrsPwr
+ 0x1005c60c 0x91 _L1e_DevRxDbgMsgRxDrsPwr
+ 0x1005c69d 0x5d _L1e_DevRxDbgMsgRxSnrInfo
+ 0x1005c6fa 0x81 _L1e_DevRxDbgMsgSyncInfo
+ 0x1005c77b 0x48 _L1e_LogDevRxMbsfnCsiInfo
+ 0x1005c7c3 0x54 _L1e_DevRxDbgMsgRxHResult
+ 0x1005c817 0x54 _L1e_DevRxDbgMsgRxPrbN0
+ 0x1005c86b 0x17 _L1e_DevRxExpInfo
+ 0x1005c882 0x1c _L1e_DevRxRssiRead
+ 0x1005c89e 0x2b _L1e_DevRxRspRead
+ 0x1005c8c9 0x25 _L1e_DevRxRsrpRead
+ 0x1005c8ee 0x43 _L1e_DevRxN0Read
+ 0x1005c931 0x15 _L1e_DevRxMrsN0Read
+ 0x1005c946 0x7a _L1e_DevRxGetRxLogInfo
+ 0x1005c9c0 0x20 _L1e_DevRxGetDfeAgcGain
+ 0x1005c9e0 0x14 _L1e_DevRxGetRxAntNum
+ 0x1005c9f4 0x7 _L1e_DevRxSetSingleAntInd
+ 0x1005c9fb 0x7 _L1e_DevRxGetSingleAntInd
+ 0x1005ca02 0x9 _L1e_DevRxSetNbNbSinrCalInd
+ 0x1005ca0b 0x9 _L1e_DevRxGetNbNbSinrCalInd
+ 0x1005ca14 0x9 _L1e_DevRxSetDrsAccNum
+ 0x1005ca1d 0x9 _L1e_DevRxGetDrsAccNum
+ 0x1005ca26 0x9 _L1e_DevRxSetBfDagcFlag
+ 0x1005ca2f 0x9 _L1e_DevRxGetBfDagcFlag
+ 0x1005ca38 0x5f _L1e_DevRxProcBfDagcFlag
+ 0x1005ca97 0x7 _L1e_DevRxPrintCtrlCfg
+ 0x1005ca9e 0x7 _L1e_DevRxPrintCtrlGet
+ 0x1005caa5 0x9 _L1e_DevRxPrintCtrlCnt
+ 0x1005caae 0x22c _L1e_DevRxCalcCsi
+ 0x1005ccda 0x11c _L1e_DevRxCsiLog
+ 0x1005cdf6 0xe _L1e_DevRxSetAntChangeInd
+ 0x1005ce04 0xd _L1e_DevRxGetAntChangeInd
+ 0x1005ce11 0xb4 _zPHY_erxp_RX_DFE_UERS
+ 0x1005cec5 0x10 _zPHY_erxp_RX_SNR
+ 0x1005ced5 0xe _L1e_DevRxSetCfoWorkInd
+ 0x1005cee3 0xd _L1e_DevRxGetCfoWorkInd
+ 0x1005cef0 0x1f _L1e_DevRxSetSinrInd
+ 0x1005cf0f 0x10 _L1e_DevRxGetSinrInd
+ 0x1005cf1f 0x2b _L1e_DevRxGetLowSinrInd
+ 0x1005cf4a 0x11 _L1e_DevReadSnr
+ 0x1005cf5b 0x8 _L1e_DevRxClearFilterInd
+ 0x1005cf63 0x42 _L1e_DevGetNeiBorCellMaxSnr
+ 0x1005cfa5 0x7 _L1e_DevRxGetCellComponState
+ 0x1005cfac 0x7 _L1e_DevRxSetCellComponState
+ 0x1005cfb3 0x7 _L1e_DevRxSetAdaptAntProcInd
+ 0x1005cfba 0x7 _L1e_DevRxGetAdaptAntProcInd
+ 0x1005cfc1 0xaa _L1e_DevRxAdaptAntProc
+ 0x1005d06b 0x44 _L1e_DevRxAdaptAntResult
+ 0x1005d0af 0x3a _L1e_DevRxAdaptAntUpdate
+ 0x1005d0e9 0x36 _L1e_DevRxAdaptSinrAcc
+ 0x1005d11f 0x101 _L1e_DevRxAdaptCalSinr
+ 0x1005d220 0x34 _L1e_DevRxAdaptAgcGainAcc
+ 0x1005d254 0x10 _L1e_DevRxAdaptGetAveResult
+ 0x1005d264 0x8 _L1e_DevRxAdaptGetRsrpRange
+ 0x1005d26c 0x58 _L1e_DevRxAdaptSetRsrpInterval
+ 0x1005d2c4 0x13 _L1e_DevRxClrAdaptAntInfo
+ 0x1005d2d7 0xa _L1e_DevRxAdaptBetaUpdate
+ 0x1005d2e1 0x26 _L1e_DevRxAdaptJudge
+ 0x1005d307 0xa _L1e_DevRxIncN1Timer
+ 0x1005d311 0x8 _L1e_DevRxGetN1Timer
+ 0x1005d319 0x9 _L1e_DevRxClrN1Timer
+ 0x1005d322 0x8 _L1e_DevRxSetN1StartInd
+ 0x1005d32a 0x8 _L1e_DevRxGetN1StartInd
+ 0x1005d332 0xa _L1e_DevRxIncN2Timer
+ 0x1005d33c 0x9 _L1e_DevRxClrN2Timer
+ 0x1005d345 0x8 _L1e_DevRxGetN2Timer
+ 0x1005d34d 0x8 _L1e_DevRxSetN2StartInd
+ 0x1005d355 0x8 _L1e_DevRxGetN2StartInd
+ 0x1005d35d 0x8 _L1e_DevRxSetAdaptStartInd
+ 0x1005d365 0xa _L1e_DevRxGetDLTimer
+ 0x1005d36f 0x8 _L1e_DevRxGetAdaptStartInd
+ 0x1005d377 0x8 _L1e_DevRxGetAdaptResult
+ 0x1005d37f 0x8 _L1e_DevRxSetAdaptResult
+ 0x1005d387 0x8 _L1e_DevRxSetAdaptChangeInd
+ 0x1005d38f 0x8 _L1e_DevRxGetAdaptChangeInd
+ 0x1005d397 0x64 _L1e_DevRxDbgAdptAntInfo
+ 0x1005d3fb 0x6f _L1e_DevRxDbgAdptchangeInfo
+ 0x1005d46a 0x65 _L1e_DevRxAntInfoGetForTool
+ .text 0x1005d4cf 0x1c42 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x1005d4cf 0x69 _zPHY_LteaSysInfoPrint
+ 0x1005d538 0x1d _L1L_elpc_Dvfs
+ 0x1005d555 0x107 _zPHY_elpc_LtePhyTaskStateInfo
+ 0x1005d65c 0x9 _zPHY_elpc_SetCfunFlg
+ 0x1005d665 0x42 _zPHY_elpc_SetLteCamonFlag
+ 0x1005d6a7 0x22 _zPHY_elpc_SetLteConnectFlag
+ 0x1005d6c9 0x28 _zPHY_elpc_SetIratGapReportFlag
+ 0x1005d6f1 0x19 _L11_DrvLpcModemIntCtrl
+ 0x1005d70a 0xe _zPHY_elpc_SetlLtePhySleepFlag
+ 0x1005d718 0x1f _zPHY_elpc_LteIdleTaskStateCtrl
+ 0x1005d737 0x264 _zPHY_elpc_UpdateLteSubFrameNum
+ 0x1005d99b 0x24 _L1L_UpdateAwakeTimer
+ 0x1005d9bf 0x1e _L1L_SetAwakeTimer
+ 0x1005d9dd 0xc _L1L_IsAwakeTimerEnable
+ 0x1005d9e9 0x38 _zPHY_elpc_ProKeepAwakeTimer
+ 0x1005da21 0x87 _zPHY_elpc_ProSleepTimer
+ 0x1005daa8 0x2 _L1_TdSleepInfoPrint
+ 0x1005daaa 0x18 _zPHY_eLpc_GetLpm32KCALIPara
+ 0x1005dac2 0x269 _L1_CpuPhySleepInfo
+ 0x1005dd2b 0x34 _L1L_PrintPwrCtrlInfo
+ 0x1005dd5f 0x29 _L1L_PrintModemClkCtrlInfo
+ 0x1005dd88 0x8e _zPHY_elpc_LpmCalibrationLog
+ 0x1005de16 0x50 _zPHY_elpc_GetLpmCaliIdx
+ 0x1005de66 0x7e _zPHY_elpc_LpmCalibrationProc
+ 0x1005dee4 0x11 _zPHY_elpc_LpmCalibrationParaUpdate
+ 0x1005def5 0x40 _zPHY_eLpc_RecordTpuMrtrForCaliTest
+ 0x1005df35 0xf _zPHY_elpc_IsRfStateIdle
+ 0x1005df44 0x1 _zPHY_elpc_RficSccSleepCtrl
+ 0x1005df45 0x63 _zPHY_eLpc_Lpm32KCALIInfor
+ 0x1005dfa8 0xf1 _zPHY_eLpc_PintCpuAxiFreq
+ 0x1005e099 0x17 _zPHY_eLpc_PrintIcpResult
+ 0x1005e0b0 0x19b _zPHY_eLpc_ChipCfgInfor
+ 0x1005e24b 0x8e _zPHY_eLpc_TimeSysInfo
+ 0x1005e2d9 0x4b4 _zPHY_elpc_CaliTempCompensate
+ 0x1005e78d 0xb _L1L_eLpc_AsynMsgProc
+ 0x1005e798 0x2c1 _L1L_elpc_WakeupMsgFlow
+ 0x1005ea59 0x23a _L1L_elpc_LpmWakeupFlow
+ 0x1005ec93 0x94 _L1L_LPInit
+ 0x1005ed27 0x2 _zPHY_elpc_Init
+ 0x1005ed29 0x6d _L1L_LpcCfgSocWkupInt
+ 0x1005ed96 0x14 _L1L_LpcDisSocWkupInt
+ 0x1005edaa 0x15 _L1L_WakeupIsr
+ 0x1005edbf 0x2b4 _L1L_ModemLpcSleep
+ 0x1005f073 0x9e _L1L_ModemLpcWakeup
+ .text 0x1005f111 0xfa8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x1005f113 0x3d _zPHY_erfc_DrvCheckNVBandWithRFBand
+ 0x1005f150 0x3b _zPHY_erfc_FindNVBandWithRFBand
+ 0x1005f18b 0x3e _zPHY_erfc_DrvCheckTpCompNV
+ 0x1005f1c9 0x2a _zPHY_erfc_SupBinarySearchNv
+ 0x1005f1f3 0xad _zPHY_erfc_SupSampleRateSet
+ 0x1005f2a0 0x82 _zPHY_erfc_SupNVBandIndexInit
+ 0x1005f322 0x1b _zPHY_erfc_SupGlobalVarInit
+ 0x1005f33d 0x18e _zPHY_erfc_InitTableByDma
+ 0x1005f4cb 0x1 _zPHY_erfc_SupIntTxTable
+ 0x1005f4cc 0x129 _zPHY_erfc_SupIntRFC
+ 0x1005f5f5 0x1e _zPHY_erfc_SupBinarySearchAdc
+ 0x1005f613 0x39 _zPHY_erfc_SupCalcDiffpower
+ 0x1005f64c 0x38 _zPHY_erfc_SupCalcDiffpower7510ACP
+ 0x1005f684 0x36 _zPHY_erfc_SupEventRxoffsetEn
+ 0x1005f6ba 0x1c _zPHY_erfc_SupTxSymbSend
+ 0x1005f6d6 0xa _zPHY_erfc_SupTxFclkCtrl
+ 0x1005f6e0 0x2e _zPHY_erfc_SupDFEFrontEsti
+ 0x1005f70e 0x11 _zPHY_erfc_SupDFEpath0RxControl
+ 0x1005f71f 0x1a _zPHY_erfc_SupDFERxDAGC0estiControl
+ 0x1005f739 0x27 _zPHY_erfc_SupDFERxRemovCpControl
+ 0x1005f760 0x11 _zPHY_erfc_SupDFEpath1Meas0Control
+ 0x1005f771 0x1f5 _zPHY_erfc_SupDFEMeas0RemovCpControl
+ 0x1005f966 0x66 _zPHY_erfc_SupDFEMeas0eICICControl
+ 0x1005f9cc 0x21 _zPHY_erfc_SupDFEpath2CellSearchControl
+ 0x1005f9ed 0x2b _zPHY_erfc_SupDFECellSearchDAGC2estiControl
+ 0x1005fa18 0x1 _zPHY_erfc_SupDFEMeas0DAGC1estiControl
+ 0x1005fa19 0x3a _zPHY_erfc_SupDFESubframeStart
+ 0x1005fa53 0x14 _zPHY_erfc_SupDFEFrameStart
+ 0x1005fa67 0x1 _zPHY_erfc_SupSetTDDFDD
+ 0x1005fa68 0x24 _zPHY_erfc_SupEnterLowPower
+ 0x1005fa8c 0x296 _zPHY_erfc_SupLeaveLowPower
+ 0x1005fd22 0x1 _zPHY_erfc_SupRfGPIOOpen
+ 0x1005fd23 0x41 _zPHY_erfc_SupRfRxOpen
+ 0x1005fd64 0x1 _zPHY_erfc_SupRfGPIOClose
+ 0x1005fd65 0x1 _zPHY_erfc_SupRfRxClose
+ 0x1005fd66 0x23 _zPHY_erfc_SupRfEnterLightSleep
+ 0x1005fd89 0x26 _zPHY_erfc_SupRfEnterDeepSleep
+ 0x1005fdaf 0x22 _zPHY_erfc_SupRfLeaveLightSleep
+ 0x1005fdd1 0x23 _zPHY_erfc_SupRfLeaveDeepSleep
+ 0x1005fdf4 0x2c _zPHY_erfc_SupRfLeaveSleep
+ 0x1005fe20 0x24 _zPHY_erfc_SupRfWakeUpRxOpen
+ 0x1005fe44 0x1e _zPHY_erfc_SupRfRxCloseSleep
+ 0x1005fe62 0x4d _zPHY_erfc_SupGetUserNVBandIndex
+ 0x1005feaf 0x3a _zPHY_erfc_SupGetCaliNVBandIndex
+ 0x1005fee9 0x6f _zPHY_erfc_SupNotchEn
+ 0x1005ff58 0xa _zPHY_erfc_SupWriteTempCompDacToIram
+ 0x1005ff62 0x157 _zPHY_erfc_SupGetRBESF
+ .text 0x100600b9 0x5f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x100600b9 0x12 _zPHY_ecsrm_ProReset
+ 0x100600cb 0x17 _zPHY_ecsrm_InitialGlobalVar
+ 0x100600e2 0x55 _zPHY_ecsrm_IsBlackCell
+ 0x10060137 0x88 _zPHY_ecsrm_BuffGetEveryRfcOpenTime
+ 0x100601bf 0xe3 _zPHY_ecsrm_GetRfcOpenTime
+ 0x100602a2 0xba _zPHY_ecsrm_GetRfcOpenTimeFddIdle
+ 0x1006035c 0x8 _zPHY_ecsrm_SetDdMode
+ 0x10060364 0x94 _zPHY_ecsrm_CfgRfcData
+ 0x100603f8 0x2 _zPHY_ecsrm_OnReset
+ 0x100603fa 0x4a _zPHY_ecsrm_OnSearchMeasStart
+ 0x10060444 0x12 _zPHY_ecsrm_OnSearchMeasReset
+ 0x10060456 0x21 _zEcsm_PreEvent
+ 0x10060477 0x38 _L1e_csrm_SfProc
+ 0x100604af 0x1fe _zPHY_ecsrm_WriteRfcEventTabNew
+ .text 0x100606ad 0x1edb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x100606ad 0x3d _zPHY_ecsrm_AveMeasResult
+ 0x100606ea 0x18 _zPHY_ecsrm_AveValLog
+ 0x10060702 0x8 _zPHY_ecsrm_CalSint16ResVal
+ 0x1006070a 0x2 _zPHY_ecsrm_PointToInt
+ 0x1006070c 0x21 _zPHY_ecsrm_CalApproValLog
+ 0x1006072d 0x8 _zPHY_ecsrm_ClearMeasResult
+ 0x10060735 0xd _zPHY_ecsrm_InitialMeasCommPara
+ 0x10060742 0x9 _zPHY_ecsrm_RegistPeriodSfInt
+ 0x1006074b 0xc _L1e_csrm_ClearCurCellInfo
+ 0x10060757 0xfa _zPHY_ecsrm_JudgeMeasState
+ 0x10060851 0x1f _zPHY_escrm_GetFbRelatn
+ 0x10060870 0x2b _zPHY_ecsrm_GetRsNumLogIndex
+ 0x1006089b 0x34 _zPHY_ecsrm_CalModVal
+ 0x100608cf 0x59 _zPHY_ecsrm_Q8log2
+ 0x10060928 0x3c _zPHY_ecsrm_Logarithm
+ 0x10060964 0x3b _zPHY_ecsrm_GetAntAgcCsrm
+ 0x1006099f 0x17 _zPHY_ecsrm_CfgDfeBandCsr
+ 0x100609b6 0x3b _zPHY_ecsrm_GetAntAgcRx
+ 0x100609f1 0x119 _zPHY_ecsrm_ReadRsrpNvInfo
+ 0x10060b0a 0x19 _zPHY_ecsrm_CalLog
+ 0x10060b23 0x25 _zPHY_ecsrm_ReadCaliNvPoint
+ 0x10060b48 0x26 _zPHY_ecsrm_WriteMeasResult
+ 0x10060b6e 0xa4 _zPHY_ecsrm_CalRsrpOffset
+ 0x10060c12 0x1ee _zPHY_ecsrm_CalRsrpRssi
+ 0x10060e00 0xe6 _zPHY_ecsrm_CalRsrpForRx
+ 0x10060ee6 0x18 _zPHY_ecsrm_ReadRealOffet
+ 0x10060efe 0xf1 _zPHY_ecsrm_CalSinr
+ 0x10060fef 0x9 _zPHY_ecrsm_DelAllTpuInt
+ 0x10060ff8 0x2e _zPHY_ecsrm_Buffer_TDDMode
+ 0x10061026 0x36 _zPHY_ecsrm_Idle_Buffer_FddMode
+ 0x1006105c 0x29 _zPHY_ecsrm_Idle_FddMode
+ 0x10061085 0x2c _zPHY_ecsrm_Idle_FddScheInAny
+ 0x100610b1 0x31 _zPHY_ecsrm_Idle_FddReadInAny
+ 0x100610e2 0x26 _zPHY_ecsrm_ClearMeasCellInfo
+ 0x10061108 0x40 _zPHY_ecsrm_ClearBuffInfo
+ 0x10061148 0x34 _zPHY_ecsrm_half_FrameBoundrySub
+ 0x1006117c 0x25 _zPHY_ecsrm_BuffSlaveHFS
+ 0x100611a1 0x44 _zPHY_ecsrm_BuffSlaveMaxBdySub
+ 0x100611e5 0x13 _zPHY_ecsrm_GetCurrCellId
+ 0x100611f8 0x97 _zPHY_ecsrm_UpdateResIntoDbNew
+ 0x1006128f 0x2e _zPHY_ecsrm_ClearMeasResultNew
+ 0x100612bd 0x5d _zPHY_ecsrm_UpdateMeasResultNew
+ 0x1006131a 0x2a _zPHY_ecsrm_Half_Frame_Bdy_Sub
+ 0x10061344 0x25 _zPHY_ecsrm_GetBuffSlaveOpenSfNum
+ 0x10061369 0x3d _zPHY_ecsrm_GetBuffMeasSfNum
+ 0x100613a6 0x2c _zPHY_ecsrm_GetMeasSfNum
+ 0x100613d2 0x10a _zPHY_ecsrm_CalRsrpNew
+ 0x100614dc 0x29 _zPHY_ecsrm_GetNextSchTime
+ 0x10061505 0x1c _zPHY_ecsrm_ClearMeasSch
+ 0x10061521 0x6a _zPHY_ecsrm_DiscardMeas
+ 0x1006158b 0x81 _GetMeasInfo
+ 0x1006160c 0x50 _SetMeasAgeInfo
+ 0x1006165c 0xbf _zPHY_ecsrm_MeasGetCell
+ 0x1006171b 0x10e _zPHY_ecsrm_GetCsrmRegParaNew
+ 0x10061829 0x69 _zPHY_ecsrm_GetDFEBuffFbRelatn
+ 0x10061892 0xc8 _zPHY_ecsrm_GetDFEBuffRegPara
+ 0x1006195a 0xb7 _zPHY_ecsrm_GetDFECellMeasPara_FDD
+ 0x10061a11 0xf7 _zPHY_ecsrm_GetDFECellMeasPara_TDD
+ 0x10061b08 0x97 _zPHY_ecsrm_HandleCsrHWNormalNew
+ 0x10061b9f 0x12 _zPHY_ecsrm_Need_Wait_Cnditon
+ 0x10061bb1 0x9d _zPHY_ecsrm_Wait_MeasPeriodProc
+ 0x10061c4e 0x9a _zPHY_ecsrm_HandleMeasResultNormalNew
+ 0x10061ce8 0x123 _zPHY_ecsrm_MeasSeekToWorkTime
+ 0x10061e0b 0xb _zPHY_ecsrm_OnMeasStart
+ 0x10061e16 0x4a _zPHY_ecsrm_MulmGapCheck
+ 0x10061e60 0x162 _zPHY_ecsrm_MeasConfigHw
+ 0x10061fc2 0xc0 _zPHY_ecsrm_MeasReadResult
+ 0x10062082 0x23 _zPHY_ecsrm_BufferScene
+ 0x100620a5 0x32 _zPHY_ecsrm_CsrFingerSort
+ 0x100620d7 0x4 _zPHY_ecsrc_RemoveMrtrFrame
+ 0x100620db 0x58 _zPHY_ecsrm_half_FrameBoundryCenter
+ 0x10062133 0x4e _zPHY_ecsrm_GetBdyMeasCell
+ 0x10062181 0x215 _zPHY_ecsrm_GetMeasmodeAndCell
+ 0x10062396 0x10 _zPHY_ecsrm_GetMeasCellEarfcn
+ 0x100623a6 0xd3 _eL1_CalCellCfgCont
+ 0x10062479 0x2c _zPHY_ecsrm_GetSF0SF5
+ 0x100624a5 0x2d _zPHY_ecsrm_BeforeBufferMeas
+ 0x100624d2 0x95 _zPHY_ecsrm_MeasNextCell
+ 0x10062567 0x7 _zPHY_ecsrm_SetCaIndex
+ 0x1006256e 0x10 _zPHY_ecsrm_MeasNeedPrimary
+ 0x1006257e 0xa _l1e_csrm_GetMeasFalg
+ .text 0x10062588 0x31e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x10062588 0x1c1 _zPHY_UL_CSI_CombThreadEntry
+ 0x10062749 0x15d _zPHY_DLA_ULSL_CombThreadEntry
+ .text 0x100628a6 0x1861 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x100628a6 0x27 _L1e_DevRxFssSetModIdx
+ 0x100628cd 0xcd _zPHY_eMBMS_CirSearchWinPos_Calc
+ 0x1006299a 0x27 _L1e_DevRxDoubleAntCheckOnlyOneValid
+ 0x100629c1 0x3d _L1e_DevCirPreSyncAcc
+ 0x100629fe 0x5e _L1e_DevCirPreSyncProtect
+ 0x10062a5c 0x43 _zPHY_erxp_CirProc
+ 0x10062a9f 0x25 _zPHY_erxp_CirAdjBorderOfSubframe
+ 0x10062ac4 0x9 _zPHY_eCir_PccPdsch_DmaCallback
+ 0x10062acd 0x9 _zPHY_eCir_SccPdsch_DmaCallback
+ 0x10062ad6 0x9 _zPHY_eCir_PccEicic_DmaCallback
+ 0x10062adf 0x8 _L1e_DevRxSetMbsfnCirIntInt
+ 0x10062ae7 0x1a _L1e_DevRxMbmsCirIntProc
+ 0x10062b01 0x44 _L1e_DevRxFssMainAntFlagSet
+ 0x10062b45 0xd _L1e_DevRxFssMainAntFlagGet
+ 0x10062b52 0xe _L1e_DevRxRefSenDecodeCnt
+ 0x10062b60 0xd _L1e_DevRxRefSenDecodeCntGet
+ 0x10062b6d 0xd _L1e_DevRxRefSenDecodeCntClr
+ 0x10062b7a 0xe _L1e_DevRxRefSenCnt
+ 0x10062b88 0xd _L1e_DevRxRefSenCntGet
+ 0x10062b95 0xd _L1e_DevRxRefSenCntClr
+ 0x10062ba2 0xe _L1e_DevRxRefSenIndCfg
+ 0x10062bb0 0xd _L1e_DevRxRefSenIndGet
+ 0x10062bbd 0x16 _L1e_devRxMrsFIUpdateIndSet
+ 0x10062bd3 0x16 _L1e_devRxMrsBetaUpdateIndSet
+ 0x10062be9 0x18 _L1e_devRxMrsFIUpdateIndGet
+ 0x10062c01 0x18 _L1e_devRxMrsBetaUpdateIndGet
+ 0x10062c19 0x23 _L1e_devRxMrsFIDataAddrGet
+ 0x10062c3c 0x19 _L1e_devRxMrsBetaGet
+ 0x10062c55 0x93e _zPHY_eMBMS_CirInitFftSeq
+ 0x10063593 0xa8 _zPHY_ecir_SW_DynFiRegUdate
+ 0x1006363b 0x135 _zPhy_eMBMS_cir_nomarlize_fir_coeff
+ 0x10063770 0x16a _zPHY_ecir_Apply_Triangle_Window
+ 0x100638da 0xcb _zPhy_ecir_CalcBeta_R01
+ 0x100639a5 0x95 _zPHY_erxp_BchNormalCirCtrl
+ 0x10063a3a 0x23 _zPHY_erxp_CirCfgForBch
+ 0x10063a5d 0x577 _L1e_DevRxCirCtrlCfg
+ 0x10063fd4 0x63 _L1e_DevRxSetRxOffsetAdjTiMode
+ 0x10064037 0x7 _zPHY_ecir_CellChangeSet
+ 0x1006403e 0xc9 _zPHY_ecir_CellChangeGet
+ *fill* 0x10064107 0x80000001 00
+ .text 0x10064108 0x203 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x10064108 0xc4 _zPHY_ecir_Fft256
+ 0x100641cc 0xb _zPhy_ecir_continuous_add
+ 0x100641d7 0x17 _zPhy_ecir_search_max_value
+ 0x100641ee 0xa _zPhy_ecir_acquire_fir_coeff
+ 0x100641f8 0x35 _zPhy_eMBMS_cir_midify_nosieEff
+ 0x1006422d 0x2d _zPhy_ecir_generet_fir_coeff
+ 0x1006425a 0x37 _zPhy_ecir_midify_nosieEff
+ 0x10064291 0x7a _Asm_CIR_FIRCoeffNorm
+ .text 0x1006430b 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x1006430b 0x9 _L1e_DevRxSetRsrpIntInd
+ 0x10064314 0x9 _L1e_DevRxGetRsrpIntInd
+ 0x1006431d 0x1f _L1e_DevRxSetServingCellInd
+ 0x1006433c 0x10b _zPHY_erxp_Cfo_Isr
+ 0x10064447 0x44 _L1e_DevCFOPreSyncAcc
+ 0x1006448b 0x4e _L1e_DevCfoFilterCoeffAdapt
+ 0x100644d9 0x1e _L1e_DevCfoCfgTempRead
+ 0x100644f7 0x59 _L1e_DevSetCfoCoeffK
+ 0x10064550 0xfb _L1e_DevGetCfoCoeffK
+ 0x1006464b 0xa _L1e_DevRxRsrpFilterFlagInit
+ 0x10064655 0x3f _L1e_DevRxGetRsrpFilterCoeff
+ 0x10064694 0x116 _zPHY_erxp_CalRsrpFilter
+ 0x100647aa 0x92 _zPHY_erxp_RsrpFilter
+ 0x1006483c 0xd _L1e_DevRxGetFastCfoConvergenceCnt
+ 0x10064849 0xe _L1e_DevRxSetFastCfoConvergenceCnt
+ 0x10064857 0xe _L1e_DevRxDecreaseFastCfoCnt
+ .text 0x10064865 0x200d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x10064865 0x249 _zPHY_edfe_SupInitDFE
+ 0x10064aae 0x24 _zPHY_edfe_WriteSnrTh
+ 0x10064ad2 0x71 _zPHY_edfe_DCOffsetCal
+ 0x10064b43 0xea _zPHY_edfe_SupNormalHandleDCOffset
+ 0x10064c2d 0xa9 _zPHY_edfe_IQImbaCal
+ 0x10064cd6 0x77 _zPHY_edfe_SupHandleIQImba
+ 0x10064d4d 0x51 _zPHY_edfe_NormalNotSyncAgcIntHandle
+ 0x10064d9e 0x8 _zPHY_edfe_SupInt0Handle
+ 0x10064da6 0x14 _zPHY_edfe_SupInt1Handle
+ 0x10064dba 0x15 _zPHY_edfe_SupInt2Handle
+ 0x10064dcf 0x39 _zPHY_edfe_ProDfeInt
+ 0x10064e08 0x27 _zPHY_edfe_ConfigRXBandwidth
+ 0x10064e2f 0x22 _zPHY_edfe_ConfigCSRMBandwidth
+ 0x10064e51 0x7d _zPHY_edfe_CompesateCFO
+ 0x10064ece 0x72 _zPHY_edfe_CalMeasTotalAGCGain
+ 0x10064f40 0x4c _zPHY_edfe_TotalAGCCsrm
+ 0x10064f8c 0x4c _zPHY_edfe_TotalAGCRx
+ 0x10064fd8 0x2e _zPHY_edfe_SupResetDfeForRelease
+ 0x10065006 0xe _zPHY_edfe_RegsTpuIntForDfe
+ 0x10065014 0x91 _zPHY_edfe_RegsTpuIntForDfeCtrl
+ 0x100650a5 0x1ab _zPHY_edfe_SupDfeIntCheckCtrl
+ 0x10065250 0xb4 _zPHY_edfe_PlmnSaveServCellAgcAndDagc
+ 0x10065304 0x26 _zPHY_edfe_PlmnResumeServCellAgcAndDagc
+ 0x1006532a 0x76 _zPHY_edfe_PlmnBackUpAgcPara
+ 0x100653a0 0x20 _zPHY_edfe_PlmnResumeAgcAndAfc
+ 0x100653c0 0xa _zPHY_edfe_ClearPlmnAgcPara
+ 0x100653ca 0x1ed _zPHY_edfe_SupNotSyncAGCInitCtrl
+ 0x100655b7 0x17e _zPHY_edfe_TMTPrintForFreqScan
+ 0x10065735 0x8d _zPHY_edfe_ConfigAgcWorkState
+ 0x100657c2 0x1b5 _zPHY_edfe_ConfigAgcCalcPara
+ 0x10065977 0xf6 _zPHY_edfe_SupInitAgcDagcGainDB
+ 0x10065a6d 0x5c _zPHY_edfe_SupHandleRxDagcInt
+ 0x10065ac9 0x1b0 _zPHY_edfe_SupHandleAgcInt
+ 0x10065c79 0x43 _zPHY_edfe_StateChangeSetAgcGain
+ 0x10065cbc 0x12a _zPHY_edfe_GetTotalAGCGainOpt
+ 0x10065de6 0x67 _zPHY_edfe_SupCsrcDagcLoseDataCtrl
+ 0x10065e4d 0xbe _zPHY_edfe_PhySlaveDfeIntCtrlOpt
+ 0x10065f0b 0x2c _zPHY_edfe_TotalSubFramePwr
+ 0x10065f37 0x21 _zPHY_edfe_CSRSetFSNewState
+ 0x10065f58 0x48 _zPHY_edfe_CSRSetAGCGain
+ 0x10065fa0 0xfa _zPHY_edfe_SupFSNewSetRF
+ 0x1006609a 0x2d _zPHY_edfe_SupNotSyncAgcIntHandle
+ 0x100660c7 0x72 _zPHY_edfe_FSDCOffsetCal
+ 0x10066139 0x17 _zPHY_edfe_FSDCOffsetClear
+ 0x10066150 0x86 _zPHY_edfe_SupFSHandleDCOffset
+ 0x100661d6 0x12 _zPHY_edfe_SupHandleDCOffset
+ 0x100661e8 0xa9 _zPHY_edfe_SupSingAntNVControl
+ 0x10066291 0x9 _zPHY_edfe_ConfigSingAnt
+ 0x1006629a 0x86 _zPHY_edfe_SupCalAGCGainBalance
+ 0x10066320 0xfa _L1l_DevDfeNotchDbInit
+ 0x1006641a 0x3 _L1l_DevRfcNotchDbReset
+ 0x1006641d 0x14 _L1l_DevDfeNotchAgcGainSave
+ 0x10066431 0x4c _L11_DevDfeNotchBwAndSampRateGet
+ 0x1006647d 0x186 _L1l_DevDfeNotchStartJudge
+ 0x10066603 0xd3 _L1l_DevDfeNotchEvtGet
+ 0x100666d6 0xb7 _L1l_DevDfeNotchRegSet
+ 0x1006678d 0xc7 _L1l_DevDfeNotchProc
+ 0x10066854 0xb _L1l_DevRfcSemiStaticAgcConvCheck
+ 0x1006685f 0x13 _L1l_DevRfcAgcValGet
+ .text 0x10066872 0x1f9a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x10066872 0xfc _zPHY_eula_Entry
+ 0x1006696e 0xf9 _zPHY_eula_TpuInt1MsgPro
+ 0x10066a67 0x9e _zPHY_eula_TpuInt2MsgPro
+ 0x10066b05 0x58e _zPHY_eula_TPU_INT1_process
+ 0x10067093 0x360 _zPHY_eula_TPU_INT2_process
+ 0x100673f3 0x98 _zPHY_eula_ResetDB
+ 0x1006748b 0x17 _zPHY_eula_ResetReqPro
+ 0x100674a2 0x2d4 _zPHY_eula_HandoverReqPro
+ 0x10067776 0x160 _zPHY_eula_Release
+ 0x100678d6 0xd7 _zPHY_eula_MACReset
+ 0x100679ad 0x12d _zPHY_eula_ComCfgReqPro
+ 0x10067ada 0x16d _zPHY_eula_CommRelatedParasCalc
+ 0x10067c47 0x156 _zPHY_eula_DediCfgReqPro
+ 0x10067d9d 0x51 _zPHY_eula_GetScellInfo
+ 0x10067dee 0xca _zPHY_eula_DediRelatedParasCalc
+ 0x10067eb8 0x169 _zPHY_eula_PSGenAllWithCellID
+ 0x10068021 0x5c _zPHY_eula_FuncHopCalculation
+ 0x1006807d 0x5c _zPHY_eula_FuncHopCalculation_Scell
+ 0x100680d9 0x35 _zPHY_eula_UlBandSampleCoeffCfg
+ 0x1006810e 0x46 _zPHY_eula_SetSampleAndFFT
+ 0x10068154 0x15 _zPHY_eula_GetSysTimeInfo
+ 0x10068169 0x13 _zPHY_eula_GetChannelType
+ 0x1006817c 0x29 _zPHY_eula_GetHarqProcessId
+ 0x100681a5 0xe _zPHY_eula_CheckPuschInGap
+ 0x100681b3 0x52 _zPHY_eula_HarqNewTransNoData
+ 0x10068205 0xb0 _zPHY_eula_UL_Conflict_GAP
+ 0x100682b5 0x6b _zPHY_eula_HarqSendDataCopy
+ 0x10068320 0x18 _zPHY_eula_TXInt_Pulse_Isr
+ 0x10068338 0x13 _zPHY_eula_Isr
+ 0x1006834b 0x91 _zPHY_eula_lpcHwRestoreBackupCtrl
+ 0x100683dc 0x2e6 _zPHY_eula_AMTCalcPara
+ 0x100686c2 0x106 _zPHY_amt_Lte_Tx_Create_CommonMsg
+ 0x100687c8 0x44 _zPHY_PrintLocalMrtr
+ .text 0x1006880c 0x121f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x1006880c 0x1a7 _zPHY_edla_Entry
+ 0x100689b3 0x3e _L1e_Dla_UpBchNormalPara
+ 0x100689f1 0x1f7 _zPHY_edla_CdtrCfgProc
+ 0x10068be8 0x1a2 _zPHY_edla_GetSiRnti
+ 0x10068d8a 0x6a _zPHY_edla_QueryDb
+ 0x10068df4 0x1e _zPHY_edla_ProCalYk
+ 0x10068e12 0x1a9 _zPHY_edla_GetRntiInfo
+ 0x10068fbb 0xa8 _zPHY_edla_GetCellInfo
+ 0x10069063 0x20 _zPHY_edla_GetVcInfo
+ 0x10069083 0x1a _zPHY_edla_ErrorTmGuard
+ 0x1006909d 0x2c _zPHY_edla_SetDefaultTM
+ 0x100690c9 0x2e _zPHY_edla_GetTimingInfo
+ 0x100690f7 0x31 _L1e_DevDlaGetPhichMi
+ 0x10069128 0x1b _zPHY_edla_CommRegParaProc
+ 0x10069143 0xbe _zPHY_edla_CdtrCfgCaApply
+ 0x10069201 0x24 _zPHY_edla_CdtrCfgApply
+ 0x10069225 0xf7 _zPHY_edla_InfoCaPrepare
+ 0x1006931c 0x9 _zPHY_edla_InfoPrepare
+ 0x10069325 0x4a _zPHY_edla_IndInfoCaSet
+ 0x1006936f 0x9 _zPHY_edla_IndInfoSet
+ 0x10069378 0x46 _zPHY_edla_ResetDcb
+ 0x100693be 0x3e _zPHY_edla_Init
+ 0x100693fc 0x1e _zPHY_edla_HwInit
+ 0x1006941a 0x1c _zPHY_edla_CacheCtrlReset
+ 0x10069436 0x3b _zPHY_edla_SaveWorkCachePara
+ 0x10069471 0x1a _zPHY_edla_UpdateRBGSize
+ 0x1006948b 0x3d _zPHY_edla_UpdateNGap1
+ 0x100694c8 0x15 _zPHY_edla_UpdateNrbStep
+ 0x100694dd 0x8 _zPHY_edla_ResetCommonInfo
+ 0x100694e5 0xfc _zPHY_edla_UpdateCommonInfo
+ 0x100695e1 0x55 _zPHY_edla_ProCommReqMsg
+ 0x10069636 0x60 _zPHY_edla_ProDediReqMsg
+ 0x10069696 0x56 _zPHY_edla_ProHoReqMsg
+ 0x100696ec 0x24 _zPHY_edla_HoReqEx
+ 0x10069710 0xd _zPHY_edla_LteAmtUpdateEarfcnInfo
+ 0x1006971d 0xb _L1e_DevRxInitLpConvergeCb
+ 0x10069728 0xf _L1e_DevRxSetLpConvergeInd
+ 0x10069737 0x10 _L1e_DevRxGetLpConvergeInd
+ 0x10069747 0x10 _L1e_DevRxSetWorkTimer
+ 0x10069757 0x10 _L1e_DevRxGetWorkTimer
+ 0x10069767 0x13 _L1e_DevRxIncWorkTimer
+ 0x1006977a 0x27 _zPHY_edla_DebugPrint
+ 0x100697a1 0x43 _zPHY_edla_ProDbgMsgRecvCommMsg
+ 0x100697e4 0x43 _zPHY_edla_ProDbgMsgRecvHOMsg
+ 0x10069827 0x43 _zPHY_edla_ProDbgMsgRstRelMacRstMsg
+ 0x1006986a 0x52 _zPHY_edla_ProDbgStateSwitchPrint
+ 0x100698bc 0x3a _zPHY_edla_ProDbgMsgFuncRetErr
+ 0x100698f6 0x77 _zPHY_edla_ProDlCtrlChStatInfoMonitor
+ 0x1006996d 0x25 _zPHY_edla_ProDlCtrlChDecodeMonitor
+ 0x10069992 0x1 _zPHY_edla_ProDlCtrlChConfigMonitor
+ 0x10069993 0x4e _zPHY_edla_PlmnReflashDlaConfig
+ 0x100699e1 0x1a _L1e_DevRxLpcHwRecover
+ 0x100699fb 0x17 _L1e_DevDlaSetDlWorkIndBmp
+ 0x10069a12 0xc _L1e_DevDlaGetDlWorkIndBmp
+ 0x10069a1e 0xd _L1e_DevDlaGetDlBandWidth
+ .text 0x10069a2b 0x2ed3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x10069a2b 0x1cd _zPHY_eula_ProInitial
+ 0x10069bf8 0x68 _zPHY_eula_RegistLutrSymb
+ 0x10069c60 0x130 _zPHY_eula_UlDataSendCtrlInfoProcess
+ 0x10069d90 0x26a _zPHY_eula_LtxParas_ACKMultiplexing
+ 0x10069ffa 0xec _zPHY_eula_LutrLtxParas_RIMultiplexing
+ 0x1006a0e6 0xb _zPHY_eula_CalcInterMatrixColNumber
+ 0x1006a0f1 0x93 _zPHY_eula_CalcRMOutputParas
+ 0x1006a184 0x8 _zPHY_eula_CalcRMOutputParasForPuschWithoutData
+ 0x1006a18c 0xd0 _zPHY_eula_SchdPhichRecInSad
+ 0x1006a25c 0x65 _zPHY_eula_DeterMineHWChanType
+ 0x1006a2c1 0x194 _zPHY_eula_LTXParasCalc
+ 0x1006a455 0x2c _zPHY_eula_LtxParas_wNRsZcDmrs
+ 0x1006a481 0x21 _zPHY_eula_LargestPrimeNumber
+ 0x1006a4a2 0x28 _zPHY_eula_LtxParas_DmrsOCC
+ 0x1006a4ca 0x71 _zPHY_eula_LtxParas_adwQDivNRsZcDmrs
+ 0x1006a53b 0x28 _zPHY_eula_LtxParas_awNcscell
+ 0x1006a563 0x16 _zPHY_eula_LtxParas_acUPucch
+ 0x1006a579 0x113 _zPHY_eula_LtxParas_PucchFormat1Spec
+ 0x1006a68c 0x232 _zPHY_eula_LtxParas_PucchFormat3Spec
+ 0x1006a8be 0x13 _zPHY_eula_LtxParas_dwX2Cinit
+ 0x1006a8d1 0x3e _zPHY_eula_LtxParas_awNcs2
+ 0x1006a90f 0x9e _zPHY_eula_LtxParas_ResMappingPucch
+ 0x1006a9ad 0x14 _zPHY_eula_711712ClosePsmStub
+ 0x1006a9c1 0x46c _zPHY_eula_RfcConfigure
+ 0x1006ae2d 0xe7 _zPHY_eula_LutrRegConfigure
+ 0x1006af14 0x3da _zPHY_eula_LtxConfigure
+ 0x1006b2ee 0x63 _zPHY_eula_LTXTxTaConfig
+ 0x1006b351 0x50 _zPHY_eula_LTXTimingFirstFlag
+ 0x1006b3a1 0x53 _zPHY_eula_LTXTimingLastFlag
+ 0x1006b3f4 0x17 _zPHY_eula_ResetSrInfo
+ 0x1006b40b 0x100 _zPHY_eula_SetPuchFilterCoeff1
+ 0x1006b50b 0x66 _zPHY_eula_SetPrachFilterCoeff2
+ 0x1006b571 0x34 _zPHY_eula_SetPucchScale
+ 0x1006b5a5 0xf _zPHY_eula_GetCsiInfo
+ 0x1006b5b4 0x2 _zPHY_eula_FDDGetHarqAckInfo
+ 0x1006b5b6 0x25 _zPHY_euls_GetPucchHarqAckInfo
+ 0x1006b5db 0x83 _zPHY_eula_GetPucchHarqAckLen
+ 0x1006b65e 0xf7 _zPHY_eula_PucchUciProcess
+ 0x1006b755 0x2bc _zPHY_eula_TDD_PucchAckProcess
+ 0x1006ba11 0x1a _zPHY_eula_FDD_PucchAckProcess
+ 0x1006ba2b 0x70 _zPHY_eula_PucchCSI
+ 0x1006ba9b 0x271 _zPHY_eula_PucchAckParasCalc
+ 0x1006bd0c 0x34 _zPHY_eula_PucchN1pucchCalc
+ 0x1006bd40 0xaa _zPHY_eula_FDD_PucchAckParasCalc
+ 0x1006bdea 0x25 _zPHY_eula_PSGeneration
+ 0x1006be0f 0x7a _zPHY_eula_SrProcess
+ 0x1006be89 0x566 _zPHY_eula_LtxStub
+ 0x1006c3ef 0x213 _zPHY_eula_LutrStub
+ 0x1006c602 0x15a _zPHY_eula_UlTwoAntenHWChanTypeDeterm
+ 0x1006c75c 0xc _zPHY_eula_TATimerStop
+ 0x1006c768 0x25 _zPHY_eula_PucchTwoAntenActivedDetermine
+ 0x1006c78d 0x12f _zPHY_eula_NextAckParasProcess
+ 0x1006c8bc 0x3b _zPHY_eula_GetTQCfgFlg
+ 0x1006c8f7 0x7 _zPHY_eula_PucchAntennaSelect
+ .text 0x1006c8fe 0x38e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x1006c8fe 0x2d _zPHY_eintc_IntDispatchProcess_ICP
+ 0x1006c92b 0x47 _zPHY_eintc_EnableInt
+ 0x1006c972 0x50 _zPHY_eintc_ClearInt
+ 0x1006c9c2 0x1c _L1l_DrvTopIntClr
+ 0x1006c9de 0x46 _zPHY_eintc_InthInit
+ 0x1006ca24 0x1a _L1_LTE_LPM_T1_ISR
+ 0x1006ca3e 0x1 _zPHY_eintc_NullIsr
+ 0x1006ca3f 0xd _zPHY_DMA_CallBack_M
+ 0x1006ca4c 0xd _zPHY_DMA_CallBack_S
+ 0x1006ca59 0xd _zPHY_DMA_CallBack_CSILte
+ 0x1006ca66 0xd _L1e_DevCmnIntPbchIntProc
+ 0x1006ca73 0x36 _L1e_DevCmnIntCfoIntProc
+ 0x1006caa9 0x1c _L1e_DevCmnIntCrsCirIntProc
+ 0x1006cac5 0x31 _L1e_DevCmnIntCdtrIntProc
+ 0x1006caf6 0x24 _L1e_DevCmnIntDdtrIntProc
+ 0x1006cb1a 0x39 _L1e_CmnCheCqiInt
+ 0x1006cb53 0xe _L1e_CmnTpuSubFrameInt
+ 0x1006cb61 0x7 _L1e_CmnTpuAdjInt
+ 0x1006cb68 0xb _L1e_CmnTxPulseInt
+ 0x1006cb73 0x2d _L1e_CmnPdcchIntPcc
+ 0x1006cba0 0x3d _L1e_CmnDfeInt
+ 0x1006cbdd 0x2f _L1e_CmnDfeDcInt
+ 0x1006cc0c 0x2c _L1e_CmnPdcchPccInt
+ 0x1006cc38 0xd _L1e_CmnCsrDebugInt
+ 0x1006cc45 0xd _L1e_CmnPbchInt
+ 0x1006cc52 0xf _L1e_CmnPdschPccCirInt
+ 0x1006cc61 0x1e _L1e_CmnDdtrPccInt
+ 0x1006cc7f 0xd _L1e_CmnPbchIcInt
+ .text 0x1006cc8c 0x1419 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ 0x1006cc8c 0x1e9 _zPHY_eulpc_GetConfigParas
+ 0x1006ce75 0x46 _zPHY_eulpc_InitialProc
+ 0x1006cebb 0x3a _zPHY_eulpc_DeltaTcEUtraBandNoDeterm
+ 0x1006cef5 0x278 _zPHY_eulpc_SingleCarrierMprDeterm
+ 0x1006d16d 0x4e9 _zPHY_eulpc_NoCaAMprDeterm
+ 0x1006d656 0x82 _zPHY_eulpc_PcmaxCalc
+ 0x1006d6d8 0x132 _zPHY_eulpc_PucchTpcProc
+ 0x1006d80a 0x104 _zPHY_eulpc_PuschTpcProc
+ 0x1006d90e 0x44 _zPHY_eulpc_RarTpcProc
+ 0x1006d952 0x6d _zPHY_eulpc_PowCtrlConfigParasCalc
+ 0x1006d9bf 0x96 _zPHY_eulpc_TpcCommandsProc
+ 0x1006da55 0x110 _zPHY_eulpc_CloseLoopPowCtrlProc
+ 0x1006db65 0xb2 _zPHY_eulpc_Type1PhrCalc
+ 0x1006dc17 0x27 _zPHY_eulpc_PhrCalcProc
+ 0x1006dc3e 0xb7 _zPHY_eulpc_Sqrt
+ 0x1006dcf5 0x10d _zPHY_eulpc_PowScaleValCalc
+ 0x1006de02 0x37 _zPHY_eulpc_LinearValToPowDB
+ 0x1006de39 0x142 _zPHY_eulpc_UlaRelativeProc
+ 0x1006df7b 0x29 _zPHY_eulpc_UlPowerStub
+ 0x1006dfa4 0x1c _zPHY_eulpc_ReSetParameters
+ 0x1006dfc0 0xba _zPHY_eulpc_TempMaxPowerBackoff
+ 0x1006e07a 0x2b _zPHY_eulpc_GetLatestPower
+ .text 0x1006e0a5 0x134 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x1006e0a5 0x9 _L1l_DevEngInitAddr
+ 0x1006e0ae 0x12 _L1l_log_track_init
+ 0x1006e0c0 0x46 _L1l_DevEngTrace
+ 0x1006e106 0xd1 _L1l_DevEngWriteDataToBuffer
+ 0x1006e1d7 0x1 _L1l_DevEngUartTransmit
+ 0x1006e1d8 0x1 _L1l_DevEngSwapHook
+ .text 0x1006e1d9 0x35a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_pagedec.o)
+ 0x1006e1d9 0x38 _zEasn1p_DcT_zEurrc_OctString
+ 0x1006e211 0x46 _zEasn1p_DcT_zEurrc_S_TMSI
+ 0x1006e257 0x5b _zEasn1p_DcT_zEurrc_IMSI
+ 0x1006e2b2 0x42 _zEasn1p_DcT_zEurrc_PagingUE_Identity
+ 0x1006e2f4 0x56 _zEasn1p_DcT_zEurrc_PagingRecord
+ 0x1006e34a 0x4a _zEasn1p_DcT_zEurrc_PagingRecordList
+ 0x1006e394 0x4e _zEasn1p_DcT_zEurrc_Paging_v920_IEs
+ 0x1006e3e2 0x49 _zEasn1p_DcT_zEurrc_Paging_v890_IEs
+ 0x1006e42b 0x8f _zEasn1p_DcT_zEurrc_Paging
+ 0x1006e4ba 0x36 _zEasn1p_DcT_zEurrc_PCCH_MessageType_c1
+ 0x1006e4f0 0x3a _zEasn1p_DcT_zEurrc_PCCH_MessageType
+ 0x1006e52a 0x9 _zEasn1p_DcT_zEurrc_PCCH_Message
+ .text 0x1006e533 0xe7e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ 0x1006e533 0x27 _L1e_DevDlaCalcTotRegNum
+ 0x1006e55a 0x75 _L1e_DevDlaCalcSearchSpace
+ 0x1006e5cf 0xdd _L1e_DevDlaProcPdcchSearchSpace
+ 0x1006e6ac 0x11c _zPHY_edla_PdcchBldRntiEnRegProc
+ 0x1006e7c8 0x6f _zPHY_edla_PdcchBldPayLoadRegProc
+ 0x1006e837 0x82 _zPHY_edla_PdcchBlindDetectCaProc
+ 0x1006e8b9 0xd _zPHY_edla_PdcchBlindDetectProc
+ 0x1006e8c6 0x20 _zPHY_edla_GetBandWidthIdx
+ 0x1006e8e6 0x1c _zPHY_edla_GetAmbitiousBits
+ 0x1006e902 0x8c _zPHY_edla_PreDciInfo
+ 0x1006e98e 0x20d _zPHY_edla_GetDciSize
+ 0x1006eb9b 0x809 _zPHY_edla_PdcchDemappingCaProc
+ 0x1006f3a4 0xd _zPHY_edla_PdcchDemappingProc
+ .text 0x1006f3b1 0xb64 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x1006f3b1 0xa0 _zPHY_erfc_SupACP405ToRx
+ 0x1006f451 0x6f _zPHY_erfc_SupACP405ToIdle
+ 0x1006f4c0 0x7f _zPHY_erfc_SupACP405ToTx
+ 0x1006f53f 0x82 _zPHY_erfc_SupACP405ToRxTx
+ 0x1006f5c1 0x1 _zPHY_erfc_SupACP405McroWriteAGC
+ 0x1006f5c2 0x1c _zPHY_erfc_SupGetRealWorkFreq
+ 0x1006f5de 0x46 _zPHY_erfc_ATAptPointAdjust
+ 0x1006f624 0x22 _zPHY_erfc_TxPowerAdjust
+ 0x1006f646 0xb7 _zPHY_erfc_SupGetPATuRegInfo
+ 0x1006f6fd 0x87 _zPHY_erfc_ProTxTempCompensate
+ 0x1006f784 0x1d3 _zPHY_erfc_SupAPCControl
+ 0x1006f957 0x6f _zPHY_erfc_SupClosePA
+ 0x1006f9c6 0x1 _zPHY_erfc_SupAptReload
+ 0x1006f9c7 0x139 _L1l_DevRfcAfcFreqOffsetSet
+ 0x1006fb00 0xd8 _zPHY_erfc_SupAfcEventSet
+ 0x1006fbd8 0x43 _zPHY_erfc_SupFreqOffseToDacValue
+ 0x1006fc1b 0x55 _zPHY_erfc_SupDacValueToFreqOffset
+ 0x1006fc70 0x36 _zPHY_erfc_SupBandNumToVcxoBitPerHz
+ 0x1006fca6 0x55 _zPHY_erfc_SupAfcVxcoInitWord
+ 0x1006fcfb 0x44 _L1l_DevRfcAfcFreqOffsetGet
+ 0x1006fd3f 0x2e _zPHY_erfc_DCXOCordicCfg
+ 0x1006fd6d 0x35 _zPHY_erfc_DCXOAfcInit
+ 0x1006fda2 0xa _zPHY_erfc_DCXOAfcParaSet
+ 0x1006fdac 0xd7 _zPHY_erfc_DCXOAfcParaGet
+ 0x1006fe83 0x92 _zPHY_erfc_DCXOAfcCtrl
+ .text 0x1006ff15 0x45e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x1006ff15 0x20 _zPHY_edls_AdaJudgePdschTrans
+ 0x1006ff35 0x7a _zPHY_edls_AdaDecodePdcchOrder
+ 0x1006ffaf 0x89 _zPHY_edls_AdaDecodeDciF1C
+ 0x10070038 0x71 _zPHY_edls_AdaCalSiRntiNdiRv
+ 0x100700a9 0x72 _zPHY_edls_AdaCalSibDecodeParas
+ 0x1007011b 0x5e _zPHY_edls_AdaRbDmpType0Bw25Rb
+ 0x10070179 0x56 _zPHY_edls_AdaRbDmpType0Bw15Rb
+ 0x100701cf 0x46 _zPHY_edls_AdaRbDmpType0Bw6Rb
+ 0x10070215 0x26 _L1e_DevDlsGetMLSMTbs
+ 0x1007023b 0x1f _L1e_DevDlsTbsBinarySearch
+ 0x1007025a 0x25 _L1e_DevDlsCalcRmCtrlParam
+ 0x1007027f 0xe9 _zPHY_edls_AdaCalRarDecodeParas
+ 0x10070368 0xb _L1e_DevDlsCalcRmBbClk
+ .text 0x10070373 0xf0b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x10070373 0x7 _L1e_DevRxGetPrevRxStatus
+ 0x1007037a 0x7 _L1e_DevRxGetCurrRxStatus
+ 0x10070381 0xc _L1e_DevRxSwitchPrevStatus
+ 0x1007038d 0x9 _L1e_DevRxSetCurrRxStatus
+ 0x10070396 0xa6 _zPHY_edla_PageSubFrmJudge
+ 0x1007043c 0x17 _zPHY_edla_RxVshiftConfig
+ 0x10070453 0xde _L1e_DevRxSfTypeCfg
+ 0x10070531 0x18 _L1e_DevRxRsN0FactorCtrl
+ 0x10070549 0x17c _L1e_DevRxCRsN0ModeCtrl
+ 0x100706c5 0x7e _L1e_DevRxProcRsCinit
+ 0x10070743 0x5d _zPHY_edla_RxBandTxRxPortConfig
+ 0x100707a0 0x113 _zPHY_edla_RxPhichMatrixConfig
+ 0x100708b3 0xf _zPHY_edla_RxCtrlChannelMimoModeConfig
+ 0x100708c2 0x6 _zPHY_edla_RxCalIndicatorConfig
+ 0x100708c8 0x44 _zPHY_edla_RxCarrierInfoConfig
+ 0x1007090c 0x85 _zPHY_edla_CheProc
+ 0x10070991 0xb _zPHY_edla_RxRbDemappingProc
+ 0x1007099c 0x25c _zPHY_edla_RbDemappingSubProc
+ 0x10070bf8 0x20 _zPHY_edla_WriteRxRbDemapRegFile
+ 0x10070c18 0x2b _L1e_DevRxNormalN0ModCfg
+ 0x10070c43 0x25 _L1e_DevRxNCellRsNullCfg
+ 0x10070c68 0x9 _L1e_DevRxSetCirTiCtlFlg
+ 0x10070c71 0x9 _L1e_DevRxGetCirTiCtlFlg
+ 0x10070c7a 0x70 _L1e_DevRxSinrLowInd
+ 0x10070cea 0x53 _L1e_DevNSIOT_8242_Ind
+ 0x10070d3d 0x41 _L1e_DevRxSinrTiCloseInd
+ 0x10070d7e 0x7 _L1e_DevRxCrsIIRIndSet
+ 0x10070d85 0x7 _L1e_DevRxCrsIIRIndGet
+ 0x10070d8c 0x8f _L1e_DevRxCrsIIRCfg
+ 0x10070e1b 0x5d _L1e_DevRxSnrModeTiAdptProc
+ 0x10070e78 0x1c _L1e_DevRxSetTiAlgoMode
+ 0x10070e94 0x9 _L1e_DevRxGetNCellRsNullEnInd
+ 0x10070e9d 0x9 _L1e_DevRxSetNCellRsNullEnInd
+ 0x10070ea6 0x59 _L1e_DevRxTempPro
+ 0x10070eff 0x25b _zPHY_edla_RxRegCfgApply
+ 0x1007115a 0x30 _L1e_DrvRxAgcCalandConfig
+ 0x1007118a 0xf4 _L1e_DbgRxCtrlInfo
+ .text 0x1007127e 0x25e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pucch.o)
+ 0x10071280 0x217 _zPHY_eulpc_PucchPowCtrl
+ 0x10071497 0x45 _zPHY_eulpc_HNcqiNharqNsrCalc
+ .text 0x100714dc 0x287 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_ddtr.o)
+ 0x100714dc 0x8 _L1e_DrvDdtrResetCfg
+ 0x100714e4 0x8 _L1e_DrvDdtrResetGet
+ 0x100714ec 0x7 _L1e_DrvDtrScaleResetCfg
+ 0x100714f3 0x8 _L1e_DrvDtrScaleEnCfg
+ 0x100714fb 0xb _L1e_DrvDtrScaleDtchEnCfg
+ 0x10071506 0x19 _L1e_DrvDtrScaleReset
+ 0x1007151f 0x8 _L1e_DrvDdtrModeCfg
+ 0x10071527 0x8 _L1e_DrvDdtrTurboLpCtrlRegCfg
+ 0x1007152f 0x8 _L1e_DrvDdtrSubfNumCfg
+ 0x10071537 0x8 _L1e_DrvDdtrHarqCtrlCfg
+ 0x1007153f 0x8 _L1e_DrvDdtrHarqIramCtrlCfg
+ 0x10071547 0xb _L1e_DrvDdtrHarqPriorityCfg
+ 0x10071552 0x8 _L1e_DrvDdtrHarqBurstCtrlCfg
+ 0x1007155a 0x8 _L1e_DrvDdtrIntTimerCfg
+ 0x10071562 0x8 _L1e_DrvDdtrLpCtrlCfg
+ 0x1007156a 0x8 _L1e_DrvDdtrUpdateCfg
+ 0x10071572 0xd _L1e_DrvDdtrTbCrcRead
+ 0x1007157f 0x9 _L1e_DrvDdtrSibPchCrcRead
+ 0x10071588 0x9 _L1e_DrvDdtrSubfNumRead
+ 0x10071591 0x9 _L1e_DrvDdtrIdleStateRead
+ 0x1007159a 0x9 _L1e_DrvDdtrErrorIndRead
+ 0x100715a3 0x1 _L1e_DrvDdtrTurboLpCtrlCfg
+ 0x100715a4 0xb _L1e_DrvDdtrPdschEnCfg
+ 0x100715af 0xb _L1e_DrvDdtrPdschEnRead
+ 0x100715ba 0xb _L1e_DrvDdtrSwapFlagCfg
+ 0x100715c5 0xb _L1e_DrvDdtrSwapFlagGet
+ 0x100715d0 0xe _L1e_DrvDdtrCwCinitCfg
+ 0x100715de 0xb _L1e_DrvDdtrTurboCtrlCfg
+ 0x100715e9 0xb _L1e_DrvDdtrPchBchTurboCtrlCfg
+ 0x100715f4 0x5d _L1e_DrvDdtrTbParamCfg
+ 0x10071651 0x8 _L1e_DrvDdtrPchCinitCfg
+ 0x10071659 0x11 _L1e_DrvDdtrPchParamCfg
+ 0x1007166a 0x8 _L1e_DrvDdtrSibCinitCfg
+ 0x10071672 0x11 _L1e_DrvDdtrSibParamCfg
+ 0x10071683 0x1d _L1e_DrvDdtrTurboReset
+ 0x100716a0 0x9 _L1e_DrvDdtrGetAxiInfo
+ 0x100716a9 0x39 _L1e_DrvDdtrPatchCfg
+ 0x100716e2 0x8 _L1e_DrvDdtrDbgGetDdtrMode
+ 0x100716ea 0x8 _L1e_DrvDdtrDbgGetTopErrInd
+ 0x100716f2 0x8 _L1e_DrvDdtrDbgGetAxiInfo
+ 0x100716fa 0x8 _L1e_DrvDdtrDbgGetIdleState
+ 0x10071702 0x8 _L1e_DrvDdtrDbgGetSubfNum
+ 0x1007170a 0xb _L1e_DrvDdtrDbgGetTurboCtrl
+ 0x10071715 0xb _L1e_DrvDdtrDbgGetTbCbCrc
+ 0x10071720 0xa _L1e_DrvDdtrGetDbgMontor1
+ 0x1007172a 0xa _L1e_DrvDdtrGetDbgMontor2
+ 0x10071734 0xf _L1e_DrvDdtrDbgSelCfg
+ 0x10071743 0x8 _L1e_DrvDdtrDbgSelCfgread
+ 0x1007174b 0x8 _L1e_DrvDdtrDbgSelCfgread0
+ 0x10071753 0x8 _L1e_DrvDdtrDbgSelCfgread1
+ 0x1007175b 0x8 _L1e_DrvDdtrDbgSelCfgread2
+ .text 0x10071763 0x454 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x10071763 0x1c _zPHY_DrvTopIntAbleBitSet
+ 0x1007177f 0x1f _zPHY_DrvTopIntMaskBitSet
+ 0x1007179e 0xc _zPHY_DrvTopIntMaskRegWR
+ 0x100717aa 0xc _zPHY_DrvTopIntMaskRegRD
+ 0x100717b6 0xc _zPHY_DrvGetTopIntStaus
+ 0x100717c2 0xc _zPHY_DrvGetTopIntVec
+ 0x100717ce 0xc _zPHY_DrvTopIntClear
+ 0x100717da 0x1f _zPHY_DrvTopIntEnable
+ 0x100717f9 0x5a _zPHY_eintc_IntRegPrint
+ 0x10071853 0x2c _zPHY_DrvTopIntReg_Print
+ 0x1007187f 0x1 _zPHY_DrvModemTopClkGate
+ 0x10071880 0x1 _zPHY_DrvModemTopClkSel
+ 0x10071881 0x11 _zPHY_LteModemTopClkCfg
+ 0x10071892 0x1b _zPHY_ResetModemHw
+ 0x100718ad 0x33 _zPHY_LteaModemTopCfgBackup
+ 0x100718e0 0x4a _zPHY_LteaModemTopCfgRecover
+ 0x1007192a 0x9 _zPHY_DrvTop_Reg_Set
+ 0x10071933 0x9 _zPHY_DrvTop_IntReg_Set
+ 0x1007193c 0x9 _zPHY_DrvTop_IntReg_Get
+ 0x10071945 0x28 _L1l_DrvMcuIntMask
+ 0x1007196d 0x28 _L1l_DrvMcuIntUnmask
+ 0x10071995 0xa _L1l_DrvMcuIntIreqClr
+ 0x1007199f 0x3a _L1l_DrvTopIntMask
+ 0x100719d9 0x39 _L1l_DrvTopIntRestore
+ 0x10071a12 0x48 _L1l_DrvTopIntEng
+ 0x10071a5a 0x1 _zPHY_DrvTOP_DFE_ClkPrintf
+ 0x10071a5b 0x1 _zPHY_DrvTOP_CSR_ClkPrintf
+ 0x10071a5c 0x7 _zPHY_DrvTOP_GetHarkRamSel
+ 0x10071a63 0x7 _zPHY_DrvTOP_GetTDHarkRamSel
+ 0x10071a6a 0x1 _zPHY_DrvTOP_Ddtr_ClkAndLpramPrintf
+ 0x10071a6b 0x37 _zPHY_DrvLteaPwrClkCtrl
+ 0x10071aa2 0x6 _zPHY_DrvPhyLteModemSel
+ 0x10071aa8 0x7 _zPHY_DrvRmHarqRamLteModeClkSelCfg
+ 0x10071aaf 0x5 _zPHY_DrvTurboModeSel
+ 0x10071ab4 0x58 _zPHY_DrvLteTpuClkSet
+ 0x10071b0c 0xe _zPHY_DrvLteTpuClkInit
+ 0x10071b1a 0x19 _zPHY_DrvChipTopRegInit
+ 0x10071b33 0x8 _zPHY_DrvTopCLKRegPOWGAT
+ 0x10071b3b 0x9 _zPHY_DrvTopCLKReg2m1SCfg
+ 0x10071b44 0x9 _zPHY_DrvTopCLKRegRfcCfg
+ 0x10071b4d 0xb _zPHY_DrvTop_RFInitReg_Set
+ 0x10071b58 0x5f _zPHY_DMA_Cfg
+ .text 0x10071bb7 0x2b6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x10071bb7 0x58 _L1L_TpuDrvReset
+ 0x10071c0f 0x33 _L1L_TpuDrvSuspend
+ 0x10071c42 0x3f _L1L_TpuDrvResume
+ 0x10071c81 0x7 _L1L_TpuDrvCpModeGet
+ 0x10071c88 0x46 _L1L_TpuDrvCpModeSet
+ 0x10071cce 0x1c _L1L_TpuDrvLocalMrtrGet
+ 0x10071cea 0x1c _L1L_TpuDrvMrtrGet
+ 0x10071d06 0xe _L1L_TpuDrvMrtrOffsetGet
+ 0x10071d14 0x47 _L1L_TpuDrvTpuRegister
+ 0x10071d5b 0x1b _L1L_TpuDrvMicroAdj
+ 0x10071d76 0x6 _L1L_TpuDrvMacroAdj
+ 0x10071d7c 0x20 _L1L_TpuDrvHwBackup
+ 0x10071d9c 0xb _L1L_TPUDrvCPModeGet
+ 0x10071da7 0xb _L1L_TPUDrvCPModeSet
+ 0x10071db2 0xa _L1L_TPUDrvMrtrOffGet
+ 0x10071dbc 0x8 _L1L_TPUDrvMrtrOffSet
+ 0x10071dc4 0x8 _L1L_TPUDrvAdjTimeSet
+ 0x10071dcc 0xc _L1L_TPUDrvCPMrtrOffStore
+ 0x10071dd8 0xa _L1L_TPUDrvMRTRTransfer
+ 0x10071de2 0x8 _L1L_TPUDrvLocalMrtrGet
+ 0x10071dea 0x8 _L1L_TPUDrvMrtrGet
+ 0x10071df2 0xb _L1L_TPUDrvHWResetCfg
+ 0x10071dfd 0xf _L1L_TpuDrvRAMCtrl
+ 0x10071e0c 0x8 _L1L_TPUDrvInttoArmIndexGet
+ 0x10071e14 0x9 _L1L_TpuDrvIntECTRamSel
+ 0x10071e1d 0x50 _L1L_TPUDrvIntECTInit
+ .text 0x10071e6d 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x10071e6d 0xea _zPHY_emc_DlDataReport
+ 0x10071f57 0x27 _zPHY_emc_RdUlDataSendCtrlInfo
+ 0x10071f7e 0x20 _zPHY_emc_wrUlReportBlerInfo
+ 0x10071f9e 0x53 _zPHY_emc_WrUlSchedInfo
+ 0x10071ff1 0x25 _zPHY_emc_InitRpMsgCh
+ 0x10072016 0x8 _zPHY_emc_MaskRpMsgCh
+ 0x1007201e 0x8 _zPHY_emc_UnMaskRpMsgCh
+ 0x10072026 0x9 _L1e_DrvGetIramTempCtrlBit
+ 0x1007202f 0x12 _L1e_DrvGetLteTempCtrlLimitInd
+ 0x10072041 0xa _L1e_DrvGetDlSibPduCrcBaseAddr
+ 0x1007204b 0xb _L1e_DrvGetDlSibPduDataBaseAddr
+ 0x10072056 0xa _L1e_DrvGetDlPchPduCrcBaseAddr
+ 0x10072060 0xb _L1e_DrvGetDlPchPduDataBaseAddr
+ 0x1007206b 0xa _L1e_DrvGetDlRarPduCrcBaseAddr
+ 0x10072075 0xb _L1e_DrvGetDlRarPduDataBaseAddr
+ 0x10072080 0x17 _L1e_DrvGetDlMacPduHarqBaseAddr
+ 0x10072097 0xb _L1e_DrvGetDlMacPduCrcBaseAddr
+ 0x100720a2 0xd _L1e_DrvSetIslandAddr
+ .text 0x100720af 0x57c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x100720af 0x7 _zPHY_elpc_DrvDelay
+ 0x100720b6 0x85 _L1l_DrvLpcGetSleepLen
+ 0x1007213b 0x32 _L1l_DrvLpcGetRemainCaliTime
+ 0x1007216d 0x8c _zPHY_elpc_LpmTimerCtrl
+ 0x100721f9 0x26 _L1_LTE_GetLpmTimerIsEn
+ 0x1007221f 0x4 _L1L_DrvLpcSocWakeUpIntCtrl
+ 0x10072223 0x1d _L1L_DrvLpcModemWakeUpIntCtrl
+ 0x10072240 0x1b _L1L_DrvLpcCfgSocWkupInt
+ 0x1007225b 0x23 _L1L_DrvLpcCfgModemWkupInt
+ 0x1007227e 0x16 _L1l_DrvLpcGetLpmNT
+ 0x10072294 0x4b _L1l_DrvLpcWaitLpmMrtrChange
+ 0x100722df 0x19 _zPHY_elpc_DrvLpmCaliCfg
+ 0x100722f8 0x10 _zPHY_elpc_DrvPdLteaCsrBackup
+ 0x10072308 0x6 _zPHY_elpc_DrvPdLteaTxBackup
+ 0x1007230e 0x1e _zPHY_elpc_DrvPdLteaCsrRecover
+ 0x1007232c 0x6 _zPHY_elpc_DrvPdLteaTxRecover
+ 0x10072332 0x11 _zPHY_elpc_DrvPdLteaRfcDfeBackup
+ 0x10072343 0x16 _zPHY_elpc_DrvPdLteaRfcDfeRecover
+ 0x10072359 0x5 _zPHY_elpc_DrvPdLteaRxRecover
+ 0x1007235e 0xf _zPHY_elpc_DrvPdLteaMimoCdtrRecover
+ 0x1007236d 0x5 _zPHY_elpc_DrvPdLteaDdtrHarqRecover
+ 0x10072372 0x19 _zPHY_elpc_DrvPdLteaStdbyCtrl
+ 0x1007238b 0x47 _zPHY_elpc_DrvPdHwIsBusy
+ 0x100723d2 0x1a _zPHY_elpc_DrvLteaPwrScenarioCtrlLog
+ 0x100723ec 0x37 _zPHY_elpc_DrvLteaPwrHwBackup
+ 0x10072423 0x12e _zPHY_elpc_DrvLteaPwrScenarioCtrl
+ 0x10072551 0xc1 _zPHY_elpc_DrvLteaPwrCtrl
+ 0x10072612 0x19 _zPHY_eLpc_DrvClearLteaModemInt
+ .text 0x1007262b 0x802 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ 0x1007262b 0x24 _zPHY_eltx_SoftReset
+ 0x1007264f 0x10 _zPHY_eltx_GetHWVersion
+ 0x1007265f 0x10 _zPHY_eltx_GetStatus
+ 0x1007266f 0x42 _zPHY_eltx_Clk_En
+ 0x100726b1 0xa _zPHY_eltx_SetCPType
+ 0x100726bb 0x12 _zPHY_eltx_SetChannelType
+ 0x100726cd 0x27 _zPHY_eltx_SetSysBandwidth
+ 0x100726f4 0xc _zPHY_eltx_SetTxTa
+ 0x10072700 0x9 _zPHY_eltx_SetPortSel
+ 0x10072709 0x14 _zPHY_eltx_SetFirstSfFlag
+ 0x1007271d 0xf _zPHY_eltx_SetConsecutiveSFLast
+ 0x1007272c 0x1e _zPHY_eltx_SetFirstLastMode
+ 0x1007274a 0xa _zPHY_eltx_SetSendMode
+ 0x10072754 0xe _zPHY_eltx_SetAbbSampleRate
+ 0x10072762 0x14 _zPHY_eltx_SetInterMatrixInfo
+ 0x10072776 0xc _zPHY_eltx_SetPuschScreamblePara
+ 0x10072782 0xe _zPHY_eltx_SetPuschModulationMode
+ 0x10072790 0xc _zPHY_eltx_SetPuschDFTPointNumber
+ 0x1007279c 0x9 _zPHY_eltx_SetPrecodingCodeBook
+ 0x100727a5 0x19 _zPHY_eltx_SetAckRiInfo
+ 0x100727be 0x4c _zPHY_eltx_SetRiMultiplexingInfo
+ 0x1007280a 0x77 _zPHY_eltx_SetAckMultiplexingInfo
+ 0x10072881 0xc _zPHY_eltx_SetPucchScreambleCint
+ 0x1007288d 0x24 _zPHY_eltx_SetPucchHarqAckinfo
+ 0x100728b1 0x1c _zPHY_eltx_SetPucchCqiInfo
+ 0x100728cd 0xe _zPHY_eltx_SetPucchFmt
+ 0x100728db 0x20 _zPHY_eltx_SetPucchCommonReg
+ 0x100728fb 0x20 _zPHY_eltx_SetPucchZCParas
+ 0x1007291b 0x7f _zPHY_eltx_SetPucchNcsParas
+ 0x1007299a 0x72 _zPHY_eltx_SetPuschDmrsParas
+ 0x10072a0c 0x68 _zPHY_eltx_SetSrsParas
+ 0x10072a74 0x3c _zPHY_eltx_SetPrachParas
+ 0x10072ab0 0x3e _zPHY_eltx_SetScale
+ 0x10072aee 0x2b _zPHY_eltx_SetPuschReMappingParas
+ 0x10072b19 0x1c _zPHY_eltx_SetPucchReMappingParas
+ 0x10072b35 0x4b _zPHY_eltx_TxCalibrationPreIQOrDC
+ 0x10072b80 0x4b _zPHY_eltx_SetTxCalibrationParas
+ 0x10072bcb 0x19 _zPHY_eltx_SetFilter1Coeff
+ 0x10072be4 0x19 _zPHY_eltx_SetFilter2Coeff
+ 0x10072bfd 0x19 _zPHY_eltx_SetFilter3Coeff
+ 0x10072c16 0xc _zPHY_eltx_SetByPass
+ 0x10072c22 0x9 _zPHY_eltx_SetFiFO
+ 0x10072c2b 0xb _zPHY_eltx_SetAntPhaseClkDelay
+ 0x10072c36 0xc _zPHY_eltx_SetAntFrameDlyNum
+ 0x10072c42 0x2 _zPHY_eltx_SetPucchFormat3Paras
+ 0x10072c44 0xe _zPHY_eltx_Enable
+ 0x10072c52 0x9 _zPHY_eltx_SetDebugMode
+ 0x10072c5b 0x9 _zPHY_eltx_SetDebugBusSel
+ 0x10072c64 0x9 _zPHY_eula_SetTXIntPulse
+ 0x10072c6d 0xa _zPHY_eltx_SetLTXIntSymbol
+ 0x10072c77 0x30 _zPHY_eltx_SetPRS1Paras
+ 0x10072ca7 0x31 _zPHY_eltx_GetPRS1Result
+ 0x10072cd8 0x30 _zPHY_eltx_SetPRS2Paras
+ 0x10072d08 0x2f _zPHY_eltx_GetPRS2Result
+ 0x10072d37 0x62 _zPHY_eula_TxRFCDBB_Interface
+ 0x10072d99 0x9 _zPHY_eula_SetTxDmaConfig
+ 0x10072da2 0xb _zPHY_eula_SetLtxFreqCompBypass
+ 0x10072dad 0xb _zPHY_eula_SetLtxFreqCompTheta
+ 0x10072db8 0xb _zPHY_eula_SetLtxFreqCompTheta0
+ 0x10072dc3 0x48 _zPHY_eula_TxFreqCompValGet
+ 0x10072e0b 0x11 _zPHY_eula_TxCordicInit
+ 0x10072e1c 0x11 _zPHY_eula_TxCordicCfg
+ .text 0x10072e2d 0x165 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ 0x10072e2d 0x19 _zPHY_ecsrm_MeasHwReset
+ 0x10072e46 0x77 _zPHY_ecsrm_MeasHwConfig
+ 0x10072ebd 0x79 _zPHY_ecsrm_MeasResultRead
+ 0x10072f36 0x45 _zPHY_ecsrm_GetMeasDoneFlag
+ 0x10072f7b 0xb _zPHY_ecsrm_GetRspCnt
+ 0x10072f86 0xc _zPHY_ecsrm_ClearMeasDoneFlag
+ .text 0x10072f92 0x8de T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x10072f92 0x1b _L1e_DrvRxResetHW
+ 0x10072fad 0xd1 _L1e_DrvRxCcRegInit
+ 0x1007307e 0x92 _L1e_DrvRxPccRegInit
+ 0x10073110 0x30 _L1e_DrvRxWriteRamCosWinCoeff
+ 0x10073140 0x10 _L1e_DrvRxTransformFirCoeff
+ 0x10073150 0x1c _L1e_DrvRxInitMrsFirCoeff
+ 0x1007316c 0x61 _L1e_DrvRxWriteRamFICoeff
+ 0x100731cd 0x14 _zPHY_Drv_Rx_HwInit
+ 0x100731e1 0x18 _L1e_DrvRxWritePcfichPosRegFile
+ 0x100731f9 0x19 _zPHY_Drv_Rx_WritePhichPosRegFile
+ 0x10073212 0x1 _zPHY_Drv_Rx_ClkPrintf
+ 0x10073213 0x8 _L1e_DrvRxGateCtrlRead
+ 0x1007321b 0x8 _L1e_DrvRxClkSwitch0Cfg
+ 0x10073223 0x8 _L1e_DrvRxClkSwitch0Read
+ 0x1007322b 0x8 _L1e_DrvRxPort5PatchCfg
+ 0x10073233 0x8 _L1e_DrvRxPccCsiCheTimeRead
+ 0x1007323b 0x8 _L1e_DrvRxPbchCtrlCfg
+ 0x10073243 0x8 _L1e_DrvRxPbchCtrlRead
+ 0x1007324b 0x8 _L1e_DrvRxCarrierInfoCfg
+ 0x10073253 0x8 _L1e_DrvRxCarrierInfoRead
+ 0x1007325b 0xb _L1e_DrvRxRxModeCfg
+ 0x10073266 0xb _L1e_DrvRxRxModeRead
+ 0x10073271 0xb _L1e_DrvRxRatModeCfg
+ 0x1007327c 0xb _L1e_DrvRxCpModeCfg
+ 0x10073287 0xb _L1e_DrvRxCpModeRead
+ 0x10073292 0xb _L1e_DrvRxVshiftCfg
+ 0x1007329d 0xb _L1e_DrvRxVshiftRead
+ 0x100732a8 0xe _L1e_DrvRxPcfichRegPosCfg
+ 0x100732b6 0xe _L1e_DrvRxPhichRegPosCfg
+ 0x100732c4 0x18 _L1e_DrvRxCellInfoCfg
+ 0x100732dc 0xb _L1e_DrvRxCellInfoRead
+ 0x100732e7 0xe _L1e_DrvRxSfnTypeCfg
+ 0x100732f5 0xe _L1e_DrvRxSfnTypeRead
+ 0x10073303 0x13 _L1e_DrvRxTmIndCfg
+ 0x10073316 0xb _L1e_DrvRxMbsfnCfiCfg
+ 0x10073321 0xb _L1e_DrvRxMbsfnTm9IndCfg
+ 0x1007332c 0xb _L1e_DrvRxCirAccCtrlCfg
+ 0x10073337 0xb _L1e_DrvRxCirAccCtrlRead
+ 0x10073342 0xb _L1e_DrvRxMrsCirAccCtrlCfg
+ 0x1007334d 0xb _L1e_DrvRxMrsCirAccCtrlRead
+ 0x10073358 0xb _L1e_DrvRxN0FgtFactorlCfg
+ 0x10073363 0x8 _L1e_DrvRxN0FgtFactorRead
+ 0x1007336b 0xb _L1e_DrvRxN0ModeCfg
+ 0x10073376 0xb _L1e_DrvRxN0ModeRead
+ 0x10073381 0xb _L1e_DrvRxSwN0ValCfg
+ 0x1007338c 0xb _L1e_DrvRxSwN0ValRead
+ 0x10073397 0xb _L1e_DrvRxMbsfnN0FgtCfg
+ 0x100733a2 0xb _L1e_DrvRxMbsfnN0FgtRead
+ 0x100733ad 0xb _L1e_DrvRxEicicModeCfg
+ 0x100733b8 0xb _L1e_DrvRxEicicModeRead
+ 0x100733c3 0xb _L1e_DrvRxBniCtrlCfg
+ 0x100733ce 0x1 _L1e_DrvRxNbnbCtrlCfg
+ 0x100733cf 0x2 _L1e_DrvRxNbnbCtrlRead
+ 0x100733d1 0xb _L1e_DrvRxCchModuModeCfg
+ 0x100733dc 0xb _L1e_DrvRxCchModuModeRead
+ 0x100733e7 0xb _L1e_DrvRxCchPcVolCfg
+ 0x100733f2 0xb _L1e_DrvRxCchPcPowCfg
+ 0x100733fd 0xb _L1e_DrvRxCsiRsCfg
+ 0x10073408 0xb _L1e_DrvRxHijRptModeCfg
+ 0x10073413 0xb _L1e_DrvRxTiCrsRptModeCfg
+ 0x1007341e 0xb _L1e_DrvRxTiCrsRptModeRead
+ 0x10073429 0xb _L1e_DrvRxPhichMatrixCfg
+ 0x10073434 0xb _L1e_DrvRxCchWorkModeCfg
+ 0x1007343f 0xb _L1e_DrvRxTiModeCfg
+ 0x1007344a 0xb _L1e_DrvRxTiModeRead
+ 0x10073455 0x10 _L1e_DrvRxAgcBalanceCfg
+ 0x10073465 0xe _L1e_DrvRxAgcBalanceRead
+ 0x10073473 0xb _L1e_DrvRxZpCsiBmpCfg
+ 0x1007347e 0xe _L1e_DrvRxZpCsiPosCfg
+ 0x1007348c 0xe _L1e_DrvRxCrsCinitCfg
+ 0x1007349a 0xe _L1e_DrvRxCrsCinitRead
+ 0x100734a8 0xe _L1e_DrvRxCsiRsCinitCfg
+ 0x100734b6 0xb _L1e_DrvRxRsParamCfg
+ 0x100734c1 0xe _L1e_DrvRxIcCrsCinitCfg
+ 0x100734cf 0xb _L1e_DrvRxIcRsParamCfg
+ 0x100734da 0x26 _L1e_DrvRxN0BetaCfg
+ 0x10073500 0x27 _L1e_DrvRxN0BetaRead
+ 0x10073527 0xb _L1e_DrvRxSwFirUpdateCfg
+ 0x10073532 0x8 _L1e_DrvRxFixFirUpdateCfg
+ 0x1007353a 0xb _L1e_DrvRxDrsGenStateCfg
+ 0x10073545 0xb _L1e_DrvRxDrsCinitCfg
+ 0x10073550 0xb _L1e_DrvRxDrsParamCfg
+ 0x1007355b 0xb _L1e_DrvRxRbBmpValidCfg
+ 0x10073566 0x13 _L1e_DrvRxRbBmpCfg
+ 0x10073579 0xb _L1e_DrvRxPrbBundlingBmpCfg
+ 0x10073584 0xb _L1e_DrvRxCsiRsDelCtrlCfg
+ 0x1007358f 0xb _L1e_DrvRxCsiRsDelCtrlRead
+ 0x1007359a 0xb _L1e_DrvRxPdschModuModeCfg
+ 0x100735a5 0xb _L1e_DrvRxPdschModuModeRead
+ 0x100735b0 0xb _L1e_DrvRxPdschMimoModeCfg
+ 0x100735bb 0xb _L1e_DrvRxPdschMimoModeRead
+ 0x100735c6 0xb _L1e_DrvRxPdschRbMaskCfg
+ 0x100735d1 0xb _L1e_DrvRxPdschTpmiCfg
+ 0x100735dc 0x10 _L1e_DrvRxDchPcVolCfg
+ 0x100735ec 0x10 _L1e_DrvRxDchPcPowCfg
+ 0x100735fc 0xb _L1e_DrvRxPcEnCfg
+ 0x10073607 0xb _L1e_DrvRxPort7IndCfg
+ 0x10073612 0xb _L1e_DrvRxMimoAlgoCfg
+ 0x1007361d 0xb _L1e_DrvRxBfAlgoCfg
+ 0x10073628 0xb _L1e_DrvRxPdschValidCfg
+ 0x10073633 0x13 _L1e_DrvRxCrsRssiRead
+ 0x10073646 0x13 _L1e_DrvRxCrsRspRead
+ 0x10073659 0x16 _L1e_DrvRxCrsRsrpRead
+ 0x1007366f 0xb _L1e_DrvRxCfoPhaseRead
+ 0x1007367a 0x13 _L1e_DrvRxMbsfnRssiRead
+ 0x1007368d 0x13 _L1e_DrvRxMbsfnRspRead
+ 0x100736a0 0x13 _L1e_DrvRxMbsfnRsrpRead
+ 0x100736b3 0x1c _L1e_DrvRxN0Read
+ 0x100736cf 0x1e _L1e_DrvRxCirPeakPosRead
+ 0x100736ed 0x22 _L1e_DrvRxDrsRsrpRead
+ 0x1007370f 0x24 _L1e_DrvRxDrsRspRead
+ 0x10073733 0xb _L1e_DrvRxDrsAccNumRead
+ 0x1007373e 0xc _L1e_DrvRxGetGenStateInd
+ 0x1007374a 0x6 _L1e_DrvRx_CqiHRx0
+ 0x10073750 0x6 _L1e_DrvRx_CqiNo0
+ 0x10073756 0x6 _L1e_DrvRx_R
+ 0x1007375c 0xd _L1e_DrvRxTpmiRamCfg
+ 0x10073769 0xd _L1e_DrvRxFirFixRamCfg
+ 0x10073776 0x6 _L1e_DrvRxFirFixRamRec
+ 0x1007377c 0x16 _L1e_DrvRxFirDynRamCfg
+ 0x10073792 0x1 _L1e_DrvRxFftBitmapRamCfg
+ 0x10073793 0x1 _L1e_DrvRxTiAptRamRead
+ 0x10073794 0x28 _L1e_DrvRxCirRamDataRead
+ 0x100737bc 0xb4 _L1e_DrvRxDbgLogRxCheReg
+ .text 0x10073870 0x209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ 0x10073870 0x1d _zPHY_elutr_SoftReset
+ 0x1007388d 0x12 _zPHY_elutr_GetHWVersion
+ 0x1007389f 0x1f _zPHY_elutr_HarqRam_Harness
+ 0x100738be 0x2b _zPHY_elutr_HarqRam_NoHarness
+ 0x100738e9 0x3a _zPHY_elutr_Clk_En
+ 0x10073923 0xe _zPHY_elutr_Enable
+ 0x10073931 0x9 _zPHY_elutr_GetHWStatus
+ 0x1007393a 0x13 _zPHY_elutr_CommonReg
+ 0x1007394d 0xc _zPHY_elutr_Modulation
+ 0x10073959 0xc _zPHY_elutr_SetTBLength
+ 0x10073965 0x24 _zPHY_elutr_SetTBSegParas
+ 0x10073989 0x1a _zPHY_elutr_SetTurboParas
+ 0x100739a3 0x25 _zPHY_elutr_SetRateMatchParas
+ 0x100739c8 0xc _zPHY_elutr_SetInterMatrixColNumber
+ 0x100739d4 0x24 _zPHY_elutr_SetPuschAckParas
+ 0x100739f8 0xe _zPHY_elutr_SetPuschAckUpdate
+ 0x10073a06 0x15 _zPHY_elutr_SetPuschRiParas
+ 0x10073a1b 0xe _zPHY_elutr_SetPuschRiUpdate
+ 0x10073a29 0x25 _zPHY_elutr_SetPuschCqiParas
+ 0x10073a4e 0xc _zPHY_elutr_SetPuschSubCarrierNumber
+ 0x10073a5a 0x1f _zPHY_elutr_SetRiMultiplexingInfo
+ .text 0x10073a79 0x22a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ 0x10073a79 0x1b _L1e_DrvRxMimoReset
+ 0x10073a94 0x19 _L1e_DrvPbchCdtrViterbiReset
+ 0x10073aad 0x1b _L1e_DrvPbchHWReset
+ 0x10073ac8 0x2 _L1e_DrvPbchInit
+ 0x10073aca 0x6a _L1e_DrvPbchConfigPbchReg
+ 0x10073b34 0xde _L1e_DrvPbchConfigRxReg
+ 0x10073c12 0x22 _L1e_DrvPbchGenRxSubFrmHead
+ 0x10073c34 0x23 _L1e_DrvPbchScGeneration
+ 0x10073c57 0x8 _L1e_DrvPbchCdtrViterbiClkRead
+ 0x10073c5f 0x8 _L1e_DrvPbchResultRead
+ 0x10073c67 0x8 _L1e_DrvPbchAntSfnRead
+ 0x10073c6f 0x8 _L1e_DrvPbchStateRead
+ 0x10073c77 0x9 _L1e_DrvPbchCdtrViterbiCtrl
+ 0x10073c80 0x9 _L1e_DrvPbchCdtrVtbRamLpCtrl
+ 0x10073c89 0x8 _L1e_DrvPbchLpcCfg
+ 0x10073c91 0x9 _L1e_DrvCdtrlkEn
+ 0x10073c9a 0x9 _L1e_DrvPbchClkEn
+ .text 0x10073ca3 0x36f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ 0x10073ca3 0x7 _L1e_DrvMimoCaRstCfg
+ 0x10073caa 0xb _L1e_DrvMimoIrcModeCfg
+ 0x10073cb5 0xb _L1e_DrvMimoIrcModeRead
+ 0x10073cc0 0x8 _L1e_DrvMimoUpdateCfg
+ 0x10073cc8 0x8 _L1e_DrvMimoUpdateRead
+ 0x10073cd0 0x8 _L1e_DrvCdtrResetCfg
+ 0x10073cd8 0x1b _L1e_DrvCdtrHwReset
+ 0x10073cf3 0x19 _L1e_DrvMimoReset
+ 0x10073d0c 0x43 _L1e_DrvCdtrHwInit
+ 0x10073d4f 0x8 _L1e_DrvCdtrTopClkSelCfg
+ 0x10073d57 0x26 _L1e_DrvCdtrTopRegCfg
+ 0x10073d7d 0x9 _L1e_DrvCdtrLpcCtrl
+ 0x10073d86 0x1b _L1e_DrvCdtrPcfichRegCfg
+ 0x10073da1 0x3b _L1e_DrvCdtrPhichRegCfg
+ 0x10073ddc 0x93 _L1e_DrvCdtrPdcchBldRegCfg
+ 0x10073e6f 0x54 _L1e_DrvCdtrPdcchDmpRegCfg
+ 0x10073ec3 0xb _L1e_DrvCdtrPhichNumCfg
+ 0x10073ece 0xb _L1e_DrvCdtrCchEnableCfg
+ 0x10073ed9 0xc _L1e_DrvCdtrRntiEnRead
+ 0x10073ee5 0xc _L1e_DrvCdtrCfiValueRead
+ 0x10073ef1 0xc _L1e_DrvCdtrHiNumRead
+ 0x10073efd 0xf _L1e_DrvCdtrHiValueRead
+ 0x10073f0c 0xc _L1e_DrvCdtrDciPld1Read
+ 0x10073f18 0xc _L1e_DrvCdtrDciPld2Read
+ 0x10073f24 0x1d _L1e_DrvCdtrDciRead
+ 0x10073f41 0x17 _L1e_DrvCdtrDciInfoRead
+ 0x10073f58 0xc _L1e_DrvCdtrDciValidRead
+ 0x10073f64 0xc _L1e_DrvCdtrUePortRead
+ 0x10073f70 0x8 _L1e_DrvCdtrDbgGetIntType
+ 0x10073f78 0xb _L1e_DrvCdtrDbgGetDlDciInfo
+ 0x10073f83 0x11 _L1e_DrvCdtrDbgGetDlDciFlag
+ 0x10073f94 0x11 _L1e_DrvCdtrDbgGetSiDciFlag
+ 0x10073fa5 0x11 _L1e_DrvCdtrDbgGetPmDciFlag
+ 0x10073fb6 0x11 _L1e_DrvCdtrDbgGetRaDciFlag
+ 0x10073fc7 0x4b _L1e_DrvCdtrPdcchBmpRamCfg
+ .text 0x10074012 0x7f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x10074012 0x38 _zPHY_erfc_DrvGetSubFrameAddr
+ 0x1007404a 0xd1 _zPHY_erfc_DrvRealwokEventEn
+ 0x1007411b 0x62 _zPHY_erfc_DrvInitAllEventEnArray
+ 0x1007417d 0x186 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg
+ 0x10074303 0x1 _zPHY_erfc_DrvWriteAllEventEnArrayToHwReg_Slave
+ 0x10074304 0x87 _zPHY_erfc_DrvAFCEventEn
+ 0x1007438b 0x10 _zPHY_erfc_DrvSpiWrite
+ 0x1007439b 0x59 _zPHY_erfc_DrvSetAgcSpiReg
+ 0x100743f4 0xa _zPHY_erfc_DrvRbdp_RxIQInvert
+ 0x100743fe 0xa _zPHY_erfc_DrvRbdp_TxIQInvert
+ 0x10074408 0x1 _zPHY_erfc_DrvRbdpModeCfg
+ 0x10074409 0x1 _zPHY_erfc_DrvTopRBDPGPIOConfig
+ 0x1007440a 0x1 _zPHY_erfc_DrvTopSSCConfig
+ 0x1007440b 0xa _zPHY_erfc_DrvMasterModeTopGPIOConfig
+ 0x10074415 0x1 _zPHY_erfc_DrvEventRamLeaveLP
+ 0x10074416 0x50 _zPHY_erfc_DrvRfcRegInit
+ 0x10074466 0x1 _zPHY_erfc_DrvRfcRegInit_Slave
+ 0x10074467 0x91 _zPHY_erfc_DrvRFEventRamInit
+ 0x100744f8 0x1b _zPHY_erfc_DrvSoftwareReset
+ 0x10074513 0x18 _zPHY_erfc_DrvResetHw
+ 0x1007452b 0xe _zPHY_erfc_DrvWriteCmdEvent
+ 0x10074539 0xe _zPHY_erfc_DrvDBBEventSet
+ 0x10074547 0x6 _zPHY_erfc_GetDfeSampleRateAddr
+ 0x1007454d 0x2c _zPHY_erfc_GetRfcShadowEventTableAddr
+ 0x10074579 0x33 _zPHY_erfc_GetRfcEventTableAddr
+ 0x100745ac 0x33 _zPHY_erfc_GetRfcBackupDDREventTableAddr
+ 0x100745df 0x30 _zPHY_erfc_DrvGetRamState
+ 0x1007460f 0x85 _zPHY_erfc_DrvEvtTabStart
+ 0x10074694 0x12 _zPHY_erfc_DrvGPIOEventSet
+ 0x100746a6 0xb _zPHY_erfc_DrvOpenfilter0
+ 0x100746b1 0xb _zPHY_erfc_DrvClosefilter0
+ 0x100746bc 0xb _zPHY_erfc_DrvOpenfilter1
+ 0x100746c7 0xb _zPHY_erfc_DrvClosefilter1
+ 0x100746d2 0xe _zPHY_erfc_DrvOpenfilter2
+ 0x100746e0 0xb _zPHY_erfc_DrvClosefilter2
+ 0x100746eb 0x10 _zPHY_erfc_DrvDfeRXBandWidthEn
+ 0x100746fb 0x10 _zPHY_erfc_DrvDfeMeas0BandWidthEn
+ 0x1007470b 0xb _zPHY_erfc_DrvGetfilter2State
+ 0x10074716 0x7 _zPHY_erfc_DrvGetfilterState
+ 0x1007471d 0x7 _zPHY_erfc_DrvGetSpiReadData
+ 0x10074724 0x7 _zPHY_erfc_DrvGetMipiReadData
+ 0x1007472b 0x9 _zPHY_erfc_DrvSetRxRemovCpOffset
+ 0x10074734 0x54 _zPHY_erfc_DrvEvtSetTableOffset
+ 0x10074788 0x9 _zPHY_erfc_DrvEnTxCalibration
+ 0x10074791 0x1 _zPHY_erfc_DrvSlaveModeTopGPIOConfig
+ 0x10074792 0xb _zPHY_erfc_DrvRfcRXBandWidthEn
+ 0x1007479d 0xb _zPHY_erfc_DrvRfcMeas0BandWidthEn
+ 0x100747a8 0x1a _zPHY_erfc_DrvInitTuRamTxEnReg
+ 0x100747c2 0x25 _zPHY_erfc_DrvInitTuRamTxTable
+ 0x100747e7 0x23 _zPHY_erfc_DrvInitTuRegTxTable
+ .text 0x1007480a 0x1ae0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x1007480a 0xcb _sin_wave_test_dfe
+ 0x100748d5 0x5a _zPHY_erfc_DrvRfcRffeWrite
+ 0x1007492f 0x7a _zPHY_erfc_MIPI_Config
+ 0x100749a9 0x1 _zPHY_erfc_DrvRfcRffeSwitchInit
+ 0x100749aa 0x9f _zPHY_erfc_DrvDFESetAcp405Gain
+ 0x10074a49 0x25 _zPHY_erfc_DrvSpiCtrlWordPreDef
+ 0x10074a6e 0x4b _zPHY_erfc_DrvPaAndAntOpenForRX
+ 0x10074ab9 0x7b _zPHY_erfc_DrvPaAndAntOpenForTX
+ 0x10074b34 0x8e _zPHY_erfc_Idle2TDRX
+ 0x10074bc2 0x82 _zPHY_erfc_Idle2TDTX
+ 0x10074c44 0x2f _zPHY_erfc_TxDbbSingleTone
+ 0x10074c73 0xc _zPHY_erfc_TransToRX
+ 0x10074c7f 0xe _zPHY_erfc_TransToTX
+ 0x10074c8d 0x1 _zPHY_erfc_DrvACP405GpioTest
+ 0x10074c8e 0xc _zPHY_erfc_DrvACP405Spi32BitWrReg
+ 0x10074c9a 0x11 _zPHY_erfc_ZTERfSPIWrite
+ 0x10074cab 0x20 _zPHY_erfc_ZTERfSPIRead
+ 0x10074ccb 0x1f _zPHY_erfc_ZTERfMIPIRead
+ 0x10074cea 0x1f _zPHY_erfc_ZTEAbbSPIRead
+ 0x10074d09 0xa _zPHY_erfc_DrvZTE110RegSet
+ 0x10074d13 0x49 _zPHY_erfc_DrvZTE110RxBandAndWidthConf
+ 0x10074d5c 0x10 _zPHY_erfc_DrvZTE120TxDACEn
+ 0x10074d6c 0x10 _zPHY_erfc_DrvZTE120TxDTXModeEn
+ 0x10074d7c 0xf _zPHY_erfc_DrvZTE120TxDACClk
+ 0x10074d8b 0x33 _zPHY_erfc_DrvCalcFracFreq
+ 0x10074dbe 0x72 _zPHY_erfc_ZTE110_RxRegConfig
+ 0x10074e30 0x65 _zPHY_erfc_ZTE110_TxRegConfig
+ 0x10074e95 0x3a _zPHY_erfc_ZTE120_RxRegConfig
+ 0x10074ecf 0x36 _zPHY_erfc_ZTE120_TxRegConfig
+ 0x10074f05 0x8c _zPHY_erfc_GetOpenRxRamNum
+ 0x10074f91 0x1c5 _zPHY_erfc_EventOpenRx
+ 0x10075156 0x89 _zPHY_erfc_EventOpenRxAntenna
+ 0x100751df 0x18c _zPHY_erfc_EventOpenTx
+ 0x1007536b 0x65 _zPHY_erfc_EventOpenTxAntenna
+ 0x100753d0 0x92 _zPHY_erfc_GetOpenRxAntennaIndex
+ 0x10075462 0xe9 _zPHY_erfc_GetOpenRxIndex
+ 0x1007554b 0x30 _zPHY_erfc_GetOpenTxIndex
+ 0x1007557b 0x35 _zPHY_erfc_GetOpenTxAntennaIndex
+ 0x100755b0 0x26 _zPHY_erfc_GetOpenTxRamNum
+ 0x100755d6 0xdc _zPHY_erfc_GetOpenRxLineIndex
+ 0x100756b2 0x70 _zPHY_erfc_GetOpenRxLineData
+ 0x10075722 0x55 _zPHY_erfc_GetNorTxOpenIndex
+ 0x10075777 0x57 _zPHY_erfc_GetOpenTxLineIndex
+ 0x100757ce 0x6d _zPHY_erfc_GetOpenTxLineData
+ 0x1007583b 0xb6 _zPHY_erfc_EventTableOpenRx
+ 0x100758f1 0xae _zPHY_erfc_TxTableOpenTx
+ 0x1007599f 0xd8 _zPHY_erfc_GetCloseAntennaIndex
+ 0x10075a77 0xdf _zPHY_erfc_GetRfToIdleIndex
+ 0x10075b56 0x75 _zPHY_erfc_GetRfToIdleData
+ 0x10075bcb 0x97 _zPHY_erfc_EventAntennaToIdle
+ 0x10075c62 0xb9 _zPHY_erfc_EventRfToIdle
+ 0x10075d1b 0x2d _zPHY_erfc_GetCloseRfRamNum
+ 0x10075d48 0x54 _zPHY_erfc_EventTableToIdle
+ 0x10075d9c 0x111 _zPHY_erfc_GetPAIndex
+ 0x10075ead 0x7d _zPHY_erfc_AmtRfFrontSet
+ 0x10075f2a 0x2f _zPHY_erfc_RfAntenna_set
+ 0x10075f59 0x6b _zPHY_erfc_RfPAFrontSet
+ 0x10075fc4 0x25 _zPHY_erfc_ATSetAptFixVoltage
+ 0x10075fe9 0xe8 _zPHY_erfc_GetRfVGACtrlWord
+ 0x100760d1 0x14 _zPHY_erfc_LittleTabWritePATrigEna
+ 0x100760e5 0x14 _zPHY_erfc_LittleTabWritePATrigLoad
+ 0x100760f9 0x14 _zPHY_erfc_LittleTabWritePATrigDisa
+ 0x1007610d 0x13e _zPHY_erfc_LittleTabWritePaAndVga
+ 0x1007624b 0x49 _zPHY_erfc_SupCheckPAMode
+ 0x10076294 0x1 _zPHY_erfc_RxSinToneTest
+ 0x10076295 0x1 _zPHY_erfc_TxSinToneTest
+ 0x10076296 0x1 _zPHY_erfc_DrvRfNvInit
+ 0x10076297 0x53 _zPHY_erfc_GetRfDCOC_CalVaue
+ .text 0x100762ea 0x204 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100762ea 0x21 _zPHY_erfc_DrvRfcTxSampleRateSet
+ 0x1007630b 0x34 _zPHY_erfc_DrvRfcDfeSampleRateSet
+ 0x1007633f 0x4c _zPHY_erfc_DrvInitMainSyncTable
+ 0x1007638b 0xa5 _zPHY_erfc_DrvInitMeasTable0
+ 0x10076430 0x45 _zPHY_erfc_DrvInitTxSendTable
+ 0x10076475 0x42 _zPHY_erfc_DrvEventTableBoundaryInit
+ 0x100764b7 0xc _zPHY_erfc_IRAM_Set
+ 0x100764c3 0x1a _zPHY_erfc_IRAM_Get
+ 0x100764dd 0x10 _zPHY_erfc_DrvDBBDely
+ 0x100764ed 0x1 _zPHY_erfc_DrvRfTopIntfInit
+ .text 0x100764ee 0xb70 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x100764ee 0x4a _zPHY_edfe_DrvInitInt
+ 0x10076538 0x53 _zPHY_edfe_DrvResetHw
+ 0x1007658b 0x3b _zPHY_edfe_DrvConfigRXBandwidth
+ 0x100765c6 0x3b _zPHY_edfe_DrvConfigCSRMBandwidth
+ 0x10076601 0x1f _zPHY_edfe_DrvGetDCOffsetEsti
+ 0x10076620 0x2c _zPHY_edfe_DrvConfigDCOffset
+ 0x1007664c 0x1f _zPHY_edfe_DrvGetIQEstiSum
+ 0x1007666b 0x1f _zPHY_edfe_DrvGetIQEstiCPSum
+ 0x1007668a 0x30 _zPHY_edfe_DrvConfigIQImbal
+ 0x100766ba 0x6a _zPHY_edfe_DrvConfigAGCPara
+ 0x10076724 0x14 _zPHY_edfe_DrvGetAGCMeanPower
+ 0x10076738 0x12 _zPHY_edfe_DrvGetAGCLFOutVal
+ 0x1007674a 0xa _zPHY_edfe_DrvGetAGCHWGainValue
+ 0x10076754 0xa _zPHY_edfe_DrvCompesateCFO
+ 0x1007675e 0x27 _zPHY_edfe_DrvDcIqParaInit
+ 0x10076785 0x8a _zPHY_edfe_DrvConfigFIRCoeff
+ 0x1007680f 0x50 _zPHY_edfe_DrvConfigDAGCPara
+ 0x1007685f 0x31 _zPHY_edfe_DrvGetDAGCMeanPower
+ 0x10076890 0x12 _zPHY_edfe_DrvGetMbsfnDAGCMeanPower
+ 0x100768a2 0x52 _zPHY_edfe_DrvConfigDAGCSWGainValue
+ 0x100768f4 0x3b _zPHY_edfe_DrvConfigMbsfnRxDAGCSWGainValue
+ 0x1007692f 0x1 _zPHY_edfe_DrvAGCGainConvertTableInit
+ 0x10076930 0x7e _zPHY_edfe_DrvInitDFE
+ 0x100769ae 0x72 _zPHY_edfe_DrvDcIqCfoDagcApplyEn
+ 0x10076a20 0xd0 _zPHY_edfe_DrvRxCPModeConfig
+ 0x10076af0 0x1 _zPHY_edfe_DrvCsrmCPModeConfig
+ 0x10076af1 0x29 _zPHY_edfe_DrvAgcExtModeConfig
+ 0x10076b1a 0x22 _zPHY_edfe_DrvDfeAbbSamplingRateConfig
+ 0x10076b3c 0x1a _zPHY_edfe_DrvMbsfnTwoAgcDagcEn
+ 0x10076b56 0xb _zPHY_edfe_DrvMbsfnTimingOffset
+ 0x10076b61 0x14 _zPHY_edfe_DrvTxCaliConfig
+ 0x10076b75 0x1e _zPHY_edfe_DrvMeasBufferModeComnParaConfig
+ 0x10076b93 0x15 _zPHY_edfe_DrvMeasBufferModeCellParaConfig
+ 0x10076ba8 0x9 _zPHY_edfe_DrvMeasBufferModeRamReadEn
+ 0x10076bb1 0x29 _zPHY_edfe_DrvMeasMode
+ 0x10076bda 0x15 _zPHY_edfe_DrvMeasClock
+ 0x10076bef 0xe _zPHY_edfe_DrvMeasClockClose
+ 0x10076bfd 0x15 _zPHY_edfe_DrvMeasReset
+ 0x10076c12 0x14 _zPHY_edfe_DrvGetMbsfnAGCMeanPower
+ 0x10076c26 0x29 _zPHY_edfe_DrvConfigMbsfnAGCSWGainValue
+ 0x10076c4f 0x14 _zPHY_edfe_DrvLpcSaveRegForCsr
+ 0x10076c63 0x2a _zPHY_edfe_DrvLpcSaveRegForRxCommon
+ 0x10076c8d 0xe8 _zPHY_edfe_DrvLpcResumeRxCommon
+ 0x10076d75 0x3 _zPHY_edfe_DrvLpcResumePower1Public
+ 0x10076d78 0x68 _zPHY_edfe_DrvLpcResumeCsr
+ 0x10076de0 0x20 _zPHY_edfe_DrvLpcResumePower0Public
+ 0x10076e00 0x12 _zPHY_edfe_DrvAgcLenStepConfig
+ 0x10076e12 0xb _zPHY_edfe_DrvDagc2LenStepConfig
+ 0x10076e1d 0x13 _zPHY_edfe_DrvAntModeConfig
+ 0x10076e30 0x26 _zPHY_edfe_DrvAgcIntStateConfig
+ 0x10076e56 0x8 _zPHY_edfe_DrvConfigAgcCalControl
+ 0x10076e5e 0x18 _zPHY_edfe_DrvGetEverySampMeanPower
+ 0x10076e76 0x1 _zPHY_edfe_DrvRfcDfeInterfaceSet
+ 0x10076e77 0x1 _zPHY_edfe_DrvPrsMeasModeComnParaConfig
+ 0x10076e78 0x1 _zPHY_edfe_DrvCsrInputSelect
+ 0x10076e79 0x2 _zPHY_edfe_DrvGetCsrInputSelState
+ 0x10076e7b 0x54 _zPHY_edfe_DrvResetPwr0
+ 0x10076ecf 0xa _zPHY_edfe_DrvDfeIntfSel
+ 0x10076ed9 0x16 _zPHY_edfe_DrvCPAddLenConfig
+ 0x10076eef 0x30 _zPHY_edfe_DrvCsrDDrCatchDataEn
+ 0x10076f1f 0xd _zPHY_edfe_DrvCsrDDrCatchDataStop
+ 0x10076f2c 0x1f _zPHY_edfe_DrvPwr0RestCsrSyncHw
+ 0x10076f4b 0x3c _L1l_DrvDfeCalcNotchParaA
+ 0x10076f87 0x8 _L1l_DrvDfeNotchSetBypass
+ 0x10076f8f 0xa _L1l_DrvDfeNotchSetA_First
+ 0x10076f99 0xa _L1l_DrvDfeNotchSetA_Second
+ 0x10076fa3 0xa _L1l_DrvDfeNotchSetA_Third
+ 0x10076fad 0xc _L1l_DrvDfeNotchSetT_A
+ 0x10076fb9 0xc _L1l_DrvDfeNotchSetT_B
+ 0x10076fc5 0xe _L1l_DrvDfeNotchSetK_A
+ 0x10076fd3 0xe _L1l_DrvDfeNotchSetK_B
+ 0x10076fe1 0xf _zPHY_edfe_DrvEnableDcInt
+ 0x10076ff0 0x5 _zPHY_edfe_ClkPrintf
+ 0x10076ff5 0x69 _zPHY_edfe_LteBuffRegPrint
+ .text 0x1007705e 0x879 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x1007705e 0x2a _zEcsr_CurrentGapTime
+ 0x10077088 0x1d _zEcsr_CurrentGapSuperTime
+ 0x100770a5 0x3c _zEcsr_GetGapStateEx
+ 0x100770e1 0x13 _zEcsr_GetLteGapState
+ 0x100770f4 0x9 _zEcsr_GetGapState
+ 0x100770fd 0x16 _zEcsr_GetIratGapState
+ 0x10077113 0x23 _zEcsr_GapCnt
+ 0x10077136 0x48 _zEcsr_GetLastGapTime
+ 0x1007717e 0x42 _zEcsr_GetGapStartTime
+ 0x100771c0 0x4b _zEcsr_GetNeartGapTime
+ 0x1007720b 0x76 _zEcsr_GetTimeBeforeIratGap
+ 0x10077281 0x42 _zEcsr_GetTimeBeforeGapEx
+ 0x100772c3 0x8 _zEcsr_GetTimeBeforeGap
+ 0x100772cb 0x12 _zEcsr_GetTimeBeforeLteGap
+ 0x100772dd 0x19 _zEcsr_Compare
+ 0x100772f6 0xb _zEcsr_GapTimeCompare
+ 0x10077301 0x7 _zEcsr_TimeCompare
+ 0x10077308 0x40 _zEcsr_BeforeGapHalfFrame
+ 0x10077348 0x40 _zEcsr_AfterGapHalfFrame
+ 0x10077388 0x33 _zEcsr_GetGapOffsetEx
+ 0x100773bb 0x8 _zEcsr_GetGapOffset
+ 0x100773c3 0x60 _zEcsr_GetGapType
+ 0x10077423 0x32 _zEcsr_IsValidGapTime
+ 0x10077455 0x61 _zEcsr_GetGapDistance
+ 0x100774b6 0x89 _zEcsr_GapType
+ 0x1007753f 0x13 _zEcsr_GetLteGapOffset
+ 0x10077552 0x14 _zEcsr_IsAroundGap
+ 0x10077566 0x14 _zEcsr_IsAroundLteGap
+ 0x1007757a 0x54 _zEcsr_CurrentGapType
+ 0x100775ce 0x3d _zEcsr_CurrentGapStartTime
+ 0x1007760b 0x10 _zEcsr_CurrentGapFrame
+ 0x1007761b 0x18 _zEcsr_NextGapFrame
+ 0x10077633 0xd _zEcsr_GapSubFrame
+ 0x10077640 0xe _zEcsr_LteGapGapAvai
+ 0x1007764e 0xc _zEcsr_CurrentGapStartMrtr
+ 0x1007765a 0x19 _zEcsr_CurrentMrtrUpper
+ 0x10077673 0x2a _zEcsr_NextHalfFrame
+ 0x1007769d 0x2d _zEcsr_TimeToMrtr
+ 0x100776ca 0x12 _zEcsr_MrtrToTime
+ 0x100776dc 0xb _zEcsr_TimeToTs
+ 0x100776e7 0x57 _zEcsr_TimeOnGapConfig
+ 0x1007773e 0x1a _zEcsr_TimeInit
+ 0x10077758 0x7 _zPHY_ecsrc_CtrltTime2Ts
+ 0x1007775f 0x1f _zPHY_ecsrc_TimeAdd
+ 0x1007777e 0x25 _zPHY_ecsrc_TimeSub
+ 0x100777a3 0x16 _zPHY_ecsrc_MrtrAddTs
+ 0x100777b9 0x19 _zPHY_ecsrc_MrtrAddSlot
+ 0x100777d2 0x1c _zPHY_ecsrc_MrtrSubTs
+ 0x100777ee 0x1f _zPHY_ecsrc_MrtrSubSlot
+ 0x1007780d 0x2b _zPHY_ecsrc_MrtrAddSignTs
+ 0x10077838 0x24 _zPHY_ecsrc_GetCurTime
+ 0x1007785c 0x18 _zPHY_ecsrc_Mrtr2LocalMrtr
+ 0x10077874 0x18 _zPHY_ecsrc_LocalMrtr2Mrtr
+ 0x1007788c 0x4 _zPHY_ecsrc_RemoveMrtrTs
+ 0x10077890 0x23 _zPHY_ecsrc_MakeMrtr
+ 0x100778b3 0x24 _zPHY_ecsrc_TsToLocalTs
+ .text 0x100778d7 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc.o)
+ 0x100778d7 0x571 _zPHY_erapc_ThreadEntry
+ .text 0x10077e48 0x131f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x10077e48 0xcf _zPHY_ecsrc_InitMeasOnIdle
+ 0x10077f17 0x31 _zPHY_ecsrc_ConfigRfcOffset
+ 0x10077f48 0x96 _zPHY_ecsrc_CtrlCampOnProcess
+ 0x10077fde 0x9a _zPHY_ecsrc_CtrlMeasConfigProcess
+ 0x10078078 0x141 _zPHY_ecsrc_CtrlMeasSetProcess
+ 0x100781b9 0x37 _zPHY_ecsrc_SetMeasAge
+ 0x100781f0 0x7b _L1e_csrc_IdleSetAgeThrold
+ 0x1007826b 0x147 _L1e_csrc_ConnectSetAgeThrold
+ 0x100783b2 0x46 _zPHY_ecsrc_CtrlSetSearchMeasAgeThrold
+ 0x100783f8 0x73 _zPHY_ecsrc_ReadRxMeas
+ 0x1007846b 0x47 _zPHY_ecsrc_ReadServCellRxMeas
+ 0x100784b2 0x23 _zPHY_ecsrc_GetCellMeasReslut
+ 0x100784d5 0x96 _zPHY_ecsrc_CtrlWriteServingCellResult
+ 0x1007856b 0x3d _zPHY_ecsrc_SetMeasResultValue
+ 0x100785a8 0x3c _zPHY_ecsrc_WriteNeibMeasResult
+ 0x100785e4 0x10 _zPHY_ecsrc_CtrlWritePccMeasResult
+ 0x100785f4 0x14d _zPHY_ecsrc_CtrlMeasFilterReq
+ 0x10078741 0x13 _zPHY_ecsrc_ConnAcquireIntraMeas
+ 0x10078754 0x70 _zPHY_ecsrc_AcquireInterMeas
+ 0x100787c4 0x16 _zPHY_ecsrc_AcquireServMeas
+ 0x100787da 0xd _zPHY_ecsrc_ReportMeasReslutIntra
+ 0x100787e7 0x50 _zPHY_ecsrc_ReportMeasReslutInter
+ 0x10078837 0x2b _zPHY_ecsrc_UpdateRsrpKByFlagCounter
+ 0x10078862 0x38 _zPHY_ecsrc_AdaptFilterFactor
+ 0x1007889a 0xb5 _zPHY_ecsrc_FreqFilter
+ 0x1007894f 0x33 _zPHY_ecsrc_FilterNoResult
+ 0x10078982 0x30 _zPHY_ecsrc_DelInvalidCell
+ 0x100789b2 0x9b _zPHY_ecsrc_InterMeasFilter
+ 0x10078a4d 0x72 _zPHY_ecsrc_IntraMeasFilter
+ 0x10078abf 0x69 _zPHY_ecsrc_FilterMeasRank
+ 0x10078b28 0x42 _zPHY_ecsrc_ReportMeasRank
+ 0x10078b6a 0x34 _zPHY_ecsrc_UpdateFreqReport
+ 0x10078b9e 0x7a _zPHY_ecsrc_UpdateIntraReport
+ 0x10078c18 0x9 _zPHY_ecsrc_GetFilterIntraMeasRsrp
+ 0x10078c21 0x70 _zPHY_ecsrc_UpdateInterReport
+ 0x10078c91 0x12 _zPHY_ecsrc_ClearNeibCellRsrp
+ 0x10078ca3 0x1c _zPHY_ecsrc_ClearIntraFilter
+ 0x10078cbf 0x23 _L1e_csrc_SetIdleFilterFactor
+ 0x10078ce2 0x2e _zPHY_ecsrc_SetFilterFactor
+ 0x10078d10 0x62 _zPHY_ecsrc_FilterMeasCfg
+ 0x10078d72 0x4 _zPHY_ecsrc_FilterComnCfg
+ 0x10078d76 0xc _zPHY_ecsrc_InitInterFilter
+ 0x10078d82 0x36 _zPHY_ecsrc_InitInterFilterFreq
+ 0x10078db8 0x60 _zPHY_ecsrc_InitIntraFilter
+ 0x10078e18 0x47 _zPHY_ecsrc_InterMeasIndPrint
+ 0x10078e5f 0x49 _zPHY_ecsrc_CtrlIntraMeasInfoPrint
+ 0x10078ea8 0x37 _zPHY_ecsrc_IntraFilterDebugInfo
+ 0x10078edf 0x4a _zPHY_ecsrc_InterFilterDebugInfo
+ 0x10078f29 0x12 _zPHY_ecsrc_CaSwitch
+ 0x10078f3b 0x78 _zPHY_ecsrc_ProPhy2PsMsgSINRandRSSI
+ 0x10078fb3 0x54 _zPHY_ecsrc_WriteRssiToSearchCnf
+ 0x10079007 0x25 _zPHY_ecsrc_AcquireIntraMeas
+ 0x1007902c 0x41 _zPHY_ecsrc_SrvCellResltDeal
+ 0x1007906d 0x45 _zPHY_ecsrc_ClearAfcInfo
+ 0x100790b2 0x6a _L1e_DevCsrNCellRsNullInd
+ 0x1007911c 0x10 _L1e_DevCsrGetMeasResult
+ 0x1007912c 0x3b _zPHY_ecsrc_CtrlIdleSetInterFilterFact
+ .text 0x10079167 0x21b2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x10079167 0x8 _L1e_Sir_RxMeasMask
+ 0x1007916f 0x8 _L1e_Sir_QuryRxMeasMask
+ 0x10079177 0x27f _L1e_Sir_MainCtrlFlow
+ 0x100793f6 0x33 _L1e_Sir_DbReset
+ 0x10079429 0x31 _L1e_Sir_LpcAndTurboCtrl
+ 0x1007945a 0x30 _L1e_Sir_AddTpuEvt
+ 0x1007948a 0x28 _L1e_Sir_DelAllTpuEvt
+ 0x100794b2 0x26 _L1e_Sir_QueryTpuEvt
+ 0x100794d8 0x33 _L1e_Sir_DelTpuEvt
+ 0x1007950b 0x4a _L1e_Sir_RegDelayEvt
+ 0x10079555 0x21 _L1e_Sir_PreProc
+ 0x10079576 0x8 _L1e_Sir_MainState
+ 0x1007957e 0x8 _L1e_Sir_StepState
+ 0x10079586 0x8 _L1e_Sir_SyncState
+ 0x1007958e 0x19 _L1e_Sir_CommInSiProc
+ 0x100795a7 0x34 _L1e_Sir_SetState
+ 0x100795db 0x98 _L1e_Sir_UpSib1Para
+ 0x10079673 0x75 _L1e_Sir_UpSiPara
+ 0x100796e8 0x15 _L1e_Sir_UpSerPara
+ 0x100796fd 0x2d _L1e_Sir_UpDecPara
+ 0x1007972a 0x8 _L1e_Sir_UpDecState
+ 0x10079732 0xd _L1e_Sir_QurySerSir
+ 0x1007973f 0xc _L1e_Sir_QurySib1State
+ 0x1007974b 0xd _L1e_Sir_QurySiState
+ 0x10079758 0x1a _L1e_Sir_QueryRptEn
+ 0x10079772 0x14 _L1e_Sir_CtrlDecOps
+ 0x10079786 0x23 _L1e_Sir_UpSibWin
+ 0x100797a9 0x56 _L1e_Sir_StopSibProc
+ 0x100797ff 0x4e _L1e_Sir_UpSchedPara
+ 0x1007984d 0x96 _L1e_Sir_StartSib1
+ 0x100798e3 0x71 _L1e_Sir_BchSync
+ 0x10079954 0x5c _L1e_Sir_RestartBch
+ 0x100799b0 0xcc _L1e_Sir_StartSi
+ 0x10079a7c 0xb7 _L1e_Sir_AbortSi
+ 0x10079b33 0x64 _L1e_Sir_SchedSib1
+ 0x10079b97 0xd4 _L1e_Sir_SchedSi
+ 0x10079c6b 0xcb _L1e_Sir_ProcDecSucc
+ 0x10079d36 0xd0 _L1e_Sir_BackSerCell
+ 0x10079e06 0x2c _L1e_Sir_DataReport
+ 0x10079e32 0x92 _L1e_Sir_SndMibReq
+ 0x10079ec4 0x39 _L1e_Sir_SndMibCnf
+ 0x10079efd 0x19 _L1e_Sir_SndBchFail
+ 0x10079f16 0x7d _L1e_Sir_QueryMib
+ 0x10079f93 0x2e _L1e_Sir_ProBchHandle
+ 0x10079fc1 0x43 _L1e_Sir_QueryCell
+ 0x1007a004 0x15 _L1e_Sir_CtrlAgcState
+ 0x1007a019 0x40 _L1e_Sir_UpRfcCfg
+ 0x1007a059 0x7 _L1e_Sir_CalBoundryTs
+ 0x1007a060 0x81 _L1e_Sir_DelyTpuAdjust
+ 0x1007a0e1 0x60 _L1e_Sir_TpuMacroAdjust
+ 0x1007a141 0x2 _L1e_Sir_SndTpuAdjust
+ 0x1007a143 0x8f _L1e_Sir_StartWinEvtCB
+ 0x1007a1d2 0x60 _L1e_Sir_EndWinEvtCB
+ 0x1007a232 0x32 _L1e_Sir_RegWindowEvt
+ 0x1007a264 0x9e _L1e_Sir_CalNearRxRcv
+ 0x1007a302 0x5a _L1e_Sir_CheckRxRcv
+ 0x1007a35c 0x39 _L1e_Sir_CellSync
+ 0x1007a395 0x3d _L1e_Sir_CheckPaging
+ 0x1007a3d2 0x7d _L1e_Sir_CheckGapPos
+ 0x1007a44f 0x5e _L1e_Sir_SerCellBackProc
+ 0x1007a4ad 0x7 _L1e_Sir_SetAbortSiProcState
+ 0x1007a4b4 0x7 _L1e_Sir_GetAbortSiProcState
+ 0x1007a4bb 0x7 _L1e_Sir_SetSiDelayProcState
+ 0x1007a4c2 0x7 _L1e_Sir_GetSiDelayProcState
+ 0x1007a4c9 0x7 _L1e_Sir_SetTimingNeibState
+ 0x1007a4d0 0x7 _L1e_Sir_GetTimingNeibState
+ 0x1007a4d7 0x10 _L1e_Sir_GetMibReadStateInSib
+ 0x1007a4e7 0x13 _L1e_Sir_GetSibState
+ 0x1007a4fa 0x68 _L1e_Sir_GetNextSiWinTime
+ 0x1007a562 0x1a _L1e_Sir_GetNeiBorSiState
+ 0x1007a57c 0x1e _L1e_Sir_GetNeiBorSibState
+ 0x1007a59a 0x2d _L1e_Sir_GetNeiBorSib1ReportState
+ 0x1007a5c7 0x1c _L1e_Sir_GetSerSibState
+ 0x1007a5e3 0x12 _L1e_Sir_GetNeiBorSiBackState
+ 0x1007a5f5 0xd _L1e_Sir_CleanSiPreSyncState
+ 0x1007a602 0x8 _L1e_Sir_GetSiSubFrmPat
+ 0x1007a60a 0xb9 _L1e_Sir_PreSyncProc
+ 0x1007a6c3 0x80 _L1e_Sir_PreSyncSched
+ 0x1007a743 0x7 _L1e_Sir_SetSiSyncState
+ 0x1007a74a 0x7 _L1e_Sir_GetSiSyncState
+ 0x1007a751 0x7 _L1e_Sir_SetSiSyncSchedState
+ 0x1007a758 0x7 _L1e_Sir_GetSiSyncSchedState
+ 0x1007a75f 0x28 _L1e_Sir_SiWakeUpProc
+ 0x1007a787 0x12 _L1e_Sir_GetBandWidth
+ 0x1007a799 0xc5 _L1e_Sir_StartAnr
+ 0x1007a85e 0x8 _L1e_Anr_QueryEn
+ 0x1007a866 0x8 _L1e_Anr_GetState
+ 0x1007a86e 0x8 _L1e_Anr_ProcIndGet
+ 0x1007a876 0x1f _L1e_Anr_SetState
+ 0x1007a895 0x2fd _L1e_Anr_SubFrmProc
+ 0x1007ab92 0x1c _L1e_Anr_BchProc
+ 0x1007abae 0x6 _L1e_Anr_BchBackSerRx
+ 0x1007abb4 0x19 _L1e_Anr_AbortSi
+ 0x1007abcd 0x2f _L1e_Anr_Reset
+ 0x1007abfc 0x11 _L1e_Anr_ProcDecSucc
+ 0x1007ac0d 0x7e _L1e_Anr_NeibLocalMrtr
+ 0x1007ac8b 0xc1 _L1e_Anr_SwitchRF
+ 0x1007ad4c 0x1a _L1e_Anr_GetAutoGapState
+ 0x1007ad66 0x49 _L1e_Anr_TpuMacroAdjust
+ 0x1007adaf 0xe _L1e_Anr_EnableRxRcv
+ 0x1007adbd 0x6e _L1e_Anr_CalNeibTime
+ 0x1007ae2b 0x2 _L1e_Anr_BchAbortProc
+ 0x1007ae2d 0xd _L1e_Anr_SibAbortProc
+ 0x1007ae3a 0x2c _L1e_Sir_Sib1MsgMonitor
+ 0x1007ae66 0x59 _L1e_Sir_SiMsgMonitor
+ 0x1007aebf 0x29 _L1e_Sir_SibReportMonitor
+ 0x1007aee8 0x2c _L1e_Sir_StateMonitor
+ 0x1007af14 0x2f _L1e_Sir_ErrMonitor
+ 0x1007af43 0x5c _L1e_Sir_RfcMonitor
+ 0x1007af9f 0x93 _L1e_Sir_CellMonitor
+ 0x1007b032 0x38 _L1e_Sir_SibParaMonitor
+ 0x1007b06a 0x43 _L1e_Sir_MibCnfMonitor
+ 0x1007b0ad 0x2c _L1e_Sir_RxRcvCtrlMonitor
+ 0x1007b0d9 0x5b _L1e_Sir_SchedParaMonitor
+ 0x1007b134 0x6e _L1e_Sir_StartWinMonitor
+ 0x1007b1a2 0x6e _L1e_Sir_EndWinMonitor
+ 0x1007b210 0x24 _L1e_Sir_AnrStateMonitor
+ 0x1007b234 0x51 _L1e_Anr_StartMonitor
+ 0x1007b285 0x34 _L1e_Sir_AnrRfcMonitor
+ 0x1007b2b9 0x32 _L1e_Anr_GapPrintf
+ 0x1007b2eb 0x2e _L1e_Anr_ErrProcMonitor
+ .text 0x1007b319 0x3fde T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x1007b319 0x27 _zPHY_emc_DvfsPatch
+ 0x1007b340 0x12 _zPHY_emc_PsMsgIdFindIndex
+ 0x1007b352 0x12 _zPHY_emc_PhyMsgIdFindIndex
+ 0x1007b364 0x12 _zPHY_emc_FindSynMsgIndex
+ 0x1007b376 0x12 _zPHY_emc_FindEmpLoc
+ 0x1007b388 0xf _zPHY_emc_FindAllSyncMsg
+ 0x1007b397 0x26 _zPHY_emc_ClearSyncMsg
+ 0x1007b3bd 0x131 _zPHY_emc_ReadSyncMsg
+ 0x1007b4ee 0x55 _zPHY_emc_StubRecvSyncMsg
+ 0x1007b543 0x1a _zPHY_emc_GetPs2PhyCF
+ 0x1007b55d 0x3a _zPHY_emc_LteAmtUpdateServeCellEarfch
+ 0x1007b597 0x8 _l1e_SchedMcIdlePiCnt
+ 0x1007b59f 0x17b _zPHY_emc_ProInitial
+ 0x1007b71a 0x11 _memcpy_Ps2PhySram
+ 0x1007b72b 0x35 _zPHY_emc_ProPs2PhyMsgLog
+ 0x1007b760 0x5a _zPHY_emc_ProPhy2PsMsgLog
+ 0x1007b7ba 0x6b8 _zPHY_emc_ProSyncMsgSend
+ 0x1007be72 0x27e _zPHY_emc_ProDedicatedMsg
+ 0x1007c0f0 0x1a1 _zPHY_emc_ProPs2PhySyncMsg
+ 0x1007c291 0x41 _zPHY_emc_ProAbortAccessMsg
+ 0x1007c2d2 0x1ad _zPHY_emc_ProAccessMsg
+ 0x1007c47f 0x5 _zPHY_emc_ProTaCmdMsg
+ 0x1007c484 0x12 _zPHY_emc_ProTaTimeStopMsg
+ 0x1007c496 0x24e _zPHY_emc_ProPs2PhyMsgRouter
+ 0x1007c6e4 0x2c _zPHY_emc_WakeUpPS
+ 0x1007c710 0x1c _zPHY_emc_SendIcpToPS
+ 0x1007c72c 0xd5 _zPHY_emc_ProPhy2PsMsgRouter
+ 0x1007c801 0x275 _zPHY_emc_ProReleaseFlow
+ 0x1007ca76 0x1a8 _zPHY_emc_ProTimingCtrlFlow
+ 0x1007cc1e 0x1fd _zPHY_emc_ProTASchedFlow
+ 0x1007ce1b 0x46 _zPHY_emc_ProMacResetFlow
+ 0x1007ce61 0x57 _zPHY_emc_ProSubfrmTypeConfig
+ 0x1007ceb8 0x20d _zPHY_emc_ProResetFlow
+ 0x1007d0c5 0x207 _zPHY_emc_ProSetModeFlow
+ 0x1007d2cc 0x2b _zPHY_emc_ProShowLtePhyStateInfo
+ 0x1007d2f7 0x58 _zPHY_emc_ProShowLtePhySIDInfo
+ 0x1007d34f 0x11b _zPHY_emc_ProAfcConfig
+ 0x1007d46a 0x14 _zPHY_emc_UpdateIniFreq
+ 0x1007d47e 0x12 _zPHY_emc_ReadIniFreq
+ 0x1007d490 0x53 _zPHY_emc_StartGapDelayPro
+ 0x1007d4e3 0x63 _zPHY_emc_GetRfTpuRegTime
+ 0x1007d546 0x25 _zPHY_emc_RegEvent
+ 0x1007d56b 0x13 _zPHY_emc_DelEvent
+ 0x1007d57e 0x40 _zPHY_emc_RfDeal
+ 0x1007d5be 0xb _zPHY_emc_ResetProOn
+ 0x1007d5c9 0xb _zPHY_emc_RelProOn
+ 0x1007d5d4 0x15 _zPHY_emc_InitScellInfo
+ 0x1007d5e9 0x1 _zPHY_emc_ModifyScellExistFlag
+ 0x1007d5ea 0x1 _zPHY_emc_ModifyScellActiveFlag
+ 0x1007d5eb 0x1d _zPHY_emc_InitScellDefaultPara
+ 0x1007d608 0x21 _zPHY_emc_ScellRatModeSet
+ 0x1007d629 0x10 _zPHY_emc_FindFreeSCarrier
+ 0x1007d639 0x10 _zPHY_emc_AddSCarrier
+ 0x1007d649 0x29 _zPHY_emc_ReleaseSCarrier
+ 0x1007d672 0x41 _zPHY_emc_ModifyScellInfo
+ 0x1007d6b3 0x2 _zPHY_emc_ActiveScell
+ 0x1007d6b5 0x2 _zPHY_emc_DeactiveScell
+ 0x1007d6b7 0x2 _zPHY_emc_AutoDeactiveScell
+ 0x1007d6b9 0x2 _zPHY_emc_UpdateDeactInfo
+ 0x1007d6bb 0xa _zPHY_emc_IsAnyScellExist
+ 0x1007d6c5 0xa _zPHY_emc_IsAnyScellActive
+ 0x1007d6cf 0x2 _zPHY_emc_IsScellExist
+ 0x1007d6d1 0x2 _zPHY_emc_IsScellActive
+ 0x1007d6d3 0x2 _zPHY_emc_ReadScellCfgDedi
+ 0x1007d6d5 0x2 _zPHY_emc_ReadScellCfgComn
+ 0x1007d6d7 0x11 _zPHY_emc_ReadScellBasicInfo
+ 0x1007d6e8 0x23 _zPHY_emc_ReadFixDlDelay
+ 0x1007d70b 0x4e _zPHY_emc_SetSysband
+ 0x1007d759 0x52 _zPHY_emc_AlterRateRefreshFB
+ 0x1007d7ab 0x44 _L1e_Anr_AlterRateRefreshFB
+ 0x1007d7ef 0x1e _zPHY_emc_CfgSysband
+ 0x1007d80d 0x1c _zPHY_emc_IsSysbandVarious
+ 0x1007d829 0x19 _zPHY_emc_ReadGapStatue
+ 0x1007d842 0x1f _zPHY_emc_ReadIratGapStatue
+ 0x1007d861 0x15 _zPHY_emc_RfcRbdpCfg
+ 0x1007d876 0x76 _zPHY_emc_ProGapDelayFlow
+ 0x1007d8ec 0x153 _zPHY_emc_ProGapSchedFlow
+ 0x1007da3f 0x2f _zPHY_emc_ScellActiveNoactiveMain
+ 0x1007da6e 0xe _L1e_SchedMcSetSCellDeactivationTimerParam
+ 0x1007da7c 0x7 _L1e_SchedMcGetSCellDeactivationTimerParam
+ 0x1007da83 0x9 _L1e_SchedMcSetSCellDeactivationTimer
+ 0x1007da8c 0xc _L1e_SchedMcIncSCellDeactivationTimer
+ 0x1007da98 0x9 _L1e_SchedMcGetSCellDeactivationTimer
+ 0x1007daa1 0x35 _L1e_SchedMcAutoDeactiveScc
+ 0x1007dad6 0x34 _L1e_SchedMcDeactiveScc
+ 0x1007db0a 0x8f _zPHY_emc_ScellGetRFPara
+ 0x1007db99 0x45 _L1e_SchedMc_CfgUlFreqPoint
+ 0x1007dbde 0x3d _zPHY_emc_ScellRFParaPrint
+ 0x1007dc1b 0x45 _L1e_LogMcSCellInfo
+ 0x1007dc60 0x1d _L1e_SchedMc_ConvertBW
+ 0x1007dc7d 0x86 _L1e_SchedMc_CloseRxRecv
+ 0x1007dd03 0x20 _zPHY_emc_ProClrRfcDBState
+ 0x1007dd23 0x135 _L1e_SchedMc_CfgRfcRxSFData
+ 0x1007de58 0xd _L1e_SchedMc_GetRxRecvState
+ 0x1007de65 0xd _L1e_SchedMc_GetCalcTimeState
+ 0x1007de72 0xd _L1e_SchedMc_GetCfgSrcIdx
+ 0x1007de7f 0x32 _L1e_SchedMc_OpenRxRecv
+ 0x1007deb1 0xc1 _L1e_SchedMc_CalcRxRecvTime
+ 0x1007df72 0x1a _L1e_SchedMc_CalcRxCloseTime
+ 0x1007df8c 0xb9 _L1e_SchedMc_OpenRxRF
+ 0x1007e045 0x147 _L1e_SchedMc_OpenRxRFByCc
+ 0x1007e18c 0x30 _L1e_SchedMc_JudgeRfOpenTime
+ 0x1007e1bc 0x1e _L1e_SchedMc_JudgeRfClose
+ 0x1007e1da 0x16 _L1e_SchedMc_Set4RxRcv
+ 0x1007e1f0 0x8 _L1e_SchedMc_Clr4RxRcv
+ 0x1007e1f8 0x7 _L1e_SchedMc_Get4RxRcv
+ 0x1007e1ff 0x1a _L1e_SchedMc_CfgRfcRxClose
+ 0x1007e219 0x17c _zPHY_emc_SetAndReadPhyPara
+ 0x1007e395 0x8 _zPHY_emc_AsynMsgProcIratGapConfigReq
+ 0x1007e39d 0x9f _zPHY_emc_RdPs2PhyAsyncMsg
+ 0x1007e43c 0x63 _zPHY_emc_CalTpuMrtrAdjType
+ 0x1007e49f 0x48 _zPHY_emc_RefreshPagePara
+ 0x1007e4e7 0x1b _zPHY_SendMsg
+ 0x1007e502 0x1c _zPHY_SendNullMsg
+ 0x1007e51e 0x62 _L1e_SchedMcGetCellInfo
+ 0x1007e580 0xd _L1e_SchedMc_AbortSi
+ 0x1007e58d 0xd _L1e_SchedMc_AbortSearch
+ 0x1007e59a 0xd _L1e_SchedMc_StoreSib
+ 0x1007e5a7 0xd _L1e_SchedMc_StoreSi
+ 0x1007e5b4 0x8 _L1e_SchedMc_SetDelayAnrState
+ 0x1007e5bc 0x8 _L1e_SchedMc_GetDelayAnrState
+ 0x1007e5c4 0xd _L1e_SchedMc_StoreSearch
+ 0x1007e5d1 0xd _L1e_SchedMc_StoreFreqScan
+ 0x1007e5de 0xd _L1e_SchedMc_StoreRapc
+ 0x1007e5eb 0x3b _L1e_SchedMc_SndDelaySearch
+ 0x1007e626 0x3c _L1e_SchedMc_SendDelayFreqScan
+ 0x1007e662 0x1a _L1e_SchedMc_SndDelaySib
+ 0x1007e67c 0x1a _L1e_SchedMc_SndDelaySi
+ 0x1007e696 0x10 _L1e_SchedMc_SndDelayRapc
+ 0x1007e6a6 0x1e _L1e_SchedMc_ReadTpuOffset
+ 0x1007e6c4 0x10 _zPHY_emc_ATSetDrxCtrl
+ 0x1007e6d4 0x83 _zPHY_emc_ATSetAndReadRlm
+ 0x1007e757 0x65 _zPHY_emc_ATSetAndReadCsi
+ 0x1007e7bc 0xc5 _zPHY_emc_ATSetAndReadUlpc
+ 0x1007e881 0x72 _zPHY_emc_ATSetAntenna
+ 0x1007e8f3 0x56 _zPHY_emc_ATSetAndReadUeCategory
+ 0x1007e949 0x21 _zPHY_emc_ATCheckSinr
+ 0x1007e96a 0x20 _zPHY_emc_ATCheckTmMode
+ 0x1007e98a 0x4f _zPHY_emc_ATCheckMcsQmod
+ 0x1007e9d9 0x6e _zPHY_emc_ATCheckHarqNack
+ 0x1007ea47 0x32 _zPHY_emc_ATCheckThrougput
+ 0x1007ea79 0x1f _zPHY_emc_ATCheckRssi
+ 0x1007ea98 0x32 _zPHY_emc_ATCheckSinrRsrp
+ 0x1007eaca 0x2a _zPHY_emc_ATCheckResidualBler
+ 0x1007eaf4 0x8a _zPHY_emc_ATCheckAll
+ 0x1007eb7e 0x1f _zPHY_emc_ATThinkWill
+ 0x1007eb9d 0x2b _zPHY_emc_ATLowPower
+ 0x1007ebc8 0x3d _zPHY_emc_ExtraCheck
+ 0x1007ec05 0x6f2 _zPHY_emc_ThreadEntry
+ .text 0x1007f2f7 0x542f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x1007f2f7 0x16 _zPHY_ecsrc_LteAmtUpdateServeCellEarfch
+ 0x1007f30d 0x35 _zPHY_ecsrc_ReadEarfcnInfo
+ 0x1007f342 0x3a _zPHY_ecsrc_GetDLULEarfchTableInfo
+ 0x1007f37c 0x52 _zPHY_ecsrc_GetEarfchTableInfo
+ 0x1007f3ce 0x11 _zPHY_ecsrc_SchedEarfcn2Freq
+ 0x1007f3df 0x14 _zPHY_ecsrc_SchedFreq2Earfcn
+ 0x1007f3f3 0x2e _zPHY_ecsrc_FindEarfchFromEarfcn
+ 0x1007f421 0x58 _zPHY_ecsrc_GetUlEarfchTableInfo
+ 0x1007f479 0x19 _zPHY_ecsrc_GetTddFddMode
+ 0x1007f492 0x13 _zPHY_ecsrc_CtrlRsrpTrans
+ 0x1007f4a5 0x12 _zPHY_ecsrc_CtrlRsrqTrans
+ 0x1007f4b7 0xc _zPHY_ecsrc_NvReadRsrpFixedOffset
+ 0x1007f4c3 0x36 _zPHY_ecsrc_SendSearchStartReq
+ 0x1007f4f9 0x37 _zPHY_ecsrc_SendCfoStartReq
+ 0x1007f530 0x8f _zPHY_ecsrc_SendMeasStartReq
+ 0x1007f5bf 0x24 _zPHY_ecsrc_SendHandoverCnf
+ 0x1007f5e3 0x51 _zPHY_ecsrc_SendMibReadReq
+ 0x1007f634 0x2c _zPHY_ecsrc_SendTpuMacroAdjReq
+ 0x1007f660 0x2c _zPHY_ecsrc_SendFreqScanReq
+ 0x1007f68c 0xd _zPHY_ecsrc_OnSendFreqScanReq
+ 0x1007f699 0x8 _zPHY_ecsrc_SetAllRxMaskFlag
+ 0x1007f6a1 0x11 _zPHY_ecsrc_SleepCtrlPowerOn
+ 0x1007f6b2 0x13 _L1e_csrc_InitStrInfo
+ 0x1007f6c5 0xec _zPHY_ecsrc_ProInitial
+ 0x1007f7b1 0x11 _zPHY_ecsrc_InitSlaveWorkState
+ 0x1007f7c2 0x13 _zPHY_ecsrc_ProReset
+ 0x1007f7d5 0x15 _zPHY_ecsrc_SetPhyModeByEarfcn
+ 0x1007f7ea 0x10 _zPHY_emc_SetPhyMode
+ 0x1007f7fa 0x14 _zPHY_ecsrc_FindTpuEvent
+ 0x1007f80e 0x40 _zPHY_ecsrc_TpuEventReset
+ 0x1007f84e 0x3a _zPHY_ecsrc_TpuEventMark
+ 0x1007f888 0x1b _zPHY_ecsrc_TpuEventCheck
+ 0x1007f8a3 0x4c _zPHY_ecsrc_DelTpuEvent
+ 0x1007f8ef 0x1c _zPHY_ecsrc_TpuEventClean
+ 0x1007f90b 0x7 _zPHY_ecsrc_FilterEnDelay
+ 0x1007f912 0x22 _zPHY_ecsrc_GetBandIdx
+ 0x1007f934 0x2b _zPHY_ecsrc_MibInfoOutput
+ 0x1007f95f 0x23 _zPHY_ecsrc_FilterOut
+ 0x1007f982 0x62 _zPHY_ecsrc_CtrlReleaseProcess
+ 0x1007f9e4 0x69 _zPHY_ecsrc_CfgRfcFreqBand
+ 0x1007fa4d 0x1c _L1e_csrc_CfgSysband
+ 0x1007fa69 0x2d _zPHY_ecsrc_RecoverToServingFreq
+ 0x1007fa96 0x1c _zPHY_ecsrc_ResetSearchMeas
+ 0x1007fab2 0x71 _zPHY_ecsrc_StopInterSearchMeas
+ 0x1007fb23 0x40 _L1e_csrc_PreWakeUpPS
+ 0x1007fb63 0x18 _zPHY_ecsrc_TsDelayMsgRegister
+ 0x1007fb7b 0x34 _zPHY_ecsrc_DelayMsgRegister
+ 0x1007fbaf 0x4d _zPHY_ecsrc_RegTpuAdjDelay
+ 0x1007fbfc 0x11a _zPHY_ecsrc_CtrlConnectedIntraReportEvent
+ 0x1007fd16 0x4a _zPHY_ecsrc_CtrlConnectedInterReportEvent
+ 0x1007fd60 0x38 _zPHY_ecsrc_CtrlConnectAgingProcess
+ 0x1007fd98 0x17 _zPHY_ecsrc_CfgRfcSynState
+ 0x1007fdaf 0x37 _zPHY_ecsrc_GetInterReportPeriod
+ 0x1007fde6 0x88 _zPHY_ecsrc_CtrlConnectedMeasSchedule
+ 0x1007fe6e 0x31 _zPHY_ecsrc_OpenSubFrameInt
+ 0x1007fe9f 0x15 _zPHY_ecsrc_DelSfInt
+ 0x1007feb4 0x18 _zPHY_ecsrc_InitGapCnt
+ 0x1007fecc 0x19 _zPHY_ecsrc_UpdateGapCnt
+ 0x1007fee5 0x3d _zPHY_ecsrc_DrxRefreshGapCnt
+ 0x1007ff22 0x48 _zPHY_ecsrc_DrxSetIntraWorkPeriod
+ 0x1007ff6a 0x80 _zPHY_ecsrc_DrxSetInterWorkPeriod
+ 0x1007ffea 0x13 _zPHY_ecsrc_DrxSetInterRprtPeriod
+ 0x1007fffd 0x8d _L1e_csrc_RegConEvent
+ 0x1008008a 0x77 _zPHY_ecsrc_CtrlDedicateConfigProcess
+ 0x10080101 0x48 _zPHY_ecsrc_CtrlConncetGapConfigProcess
+ 0x10080149 0x100 _zPHY_ecsrc_CtrlConnectedSetInterFreq
+ 0x10080249 0xa6 _zPHY_ecsrc_CtrlConnectedScheduleInterFreq
+ 0x100802ef 0xc7 _zPHY_ecsrc_CtrlHandoverSearch
+ 0x100803b6 0x25 _zPHY_ecsrc_CtrlHandoverCfoEn
+ 0x100803db 0x1f _zPHY_ecsrc_CtrlHandoverMibInd
+ 0x100803fa 0x112 _zPHY_ecsrc_CtrlHandoverPro
+ 0x1008050c 0x114 _zPHY_ecsrc_CtrlHandoverSearchTimeEvent
+ 0x10080620 0x49 _zPHY_ecsrc_CtrlHandoverPbchTimeEvent
+ 0x10080669 0x38 _zPHY_ecsrc_LteAmtULEarfchTableInfo
+ 0x100806a1 0x38 _zPHY_ecsrc_LteAmtDLEarfchTableInfo
+ 0x100806d9 0x3a _zPHY_ecsrc_LteAmtFDTEarfchTableInfo
+ 0x10080713 0x86 _zPHY_ecsrc_AmtUpdateEarfcnBand
+ 0x10080799 0x2d _zPHY_ecsrc_RegDrxNoUseEvent
+ 0x100807c6 0x24 _zPHY_ecsrc_DelDrxNoUseEvent
+ 0x100807ea 0xc _zPHY_ecsrc_IsDrxUsed
+ 0x100807f6 0x29 _zPHY_ecsrc_IsWorkGap
+ 0x1008081f 0x34 _zPHY_ecsrc_WaitIratGap
+ 0x10080853 0x42 _zPHY_ecsrc_IntraFreqEnable
+ 0x10080895 0x5e _zPHY_ecsrc_InterFreqEnable
+ 0x100808f3 0xb8 _zPHY_ecsrc_CalIntraWorkTime
+ 0x100809ab 0x4d _zPHY_ecsrc_SetSearchPhase
+ 0x100809f8 0x4c _zPHY_ecsrc_GetSearchPhase
+ 0x10080a44 0x1b _zPHY_ecsrc_ClearSearchEnable
+ 0x10080a5f 0x49 _zPHY_ecsrc_FindEnableFreq
+ 0x10080aa8 0x3a _zPHY_ecsrc_UpdateSearchEnable
+ 0x10080ae2 0x2f _zPHY_ecsrc_IsSearchDone
+ 0x10080b11 0x4b _zPHY_ecsrc_RecoverEnableFlag
+ 0x10080b5c 0x90 _zPHY_ecsrc_CalRemainTime
+ 0x10080bec 0x1cf _zPHY_ecsrc_FindUndoneFreq
+ 0x10080dbb 0x1b _L1e_csrc_FindEnableInterFreq
+ 0x10080dd6 0x1d5 _L1e_csrc_FindUndoFreq
+ 0x10080fab 0x6c _L1e_csrc_DrxIntraReport
+ 0x10081017 0x4e _L1e_csrc_DrxInterReport
+ 0x10081065 0xb7 _L1e_csrc_DrxSchdEnd
+ 0x1008111c 0x3b _L1e_csrc_DrxIntraSchd
+ 0x10081157 0x42 _L1e_csrc_DrxInterSchd
+ 0x10081199 0x6e _L1e_csrc_ShortDrxIntraSchd
+ 0x10081207 0x40 _L1e_csrc_ShortDrxInterSchd
+ 0x10081247 0x49 _L1e_csrc_AbortDrxSchd
+ 0x10081290 0x15 _L1e_csrc_CsrIsWork
+ 0x100812a5 0x127 _zPHY_ecsrc_DrxCheckEvent
+ 0x100813cc 0x8 _L1e_csrc_GetStopMeas
+ 0x100813d4 0xe _L1e_csrc_CfgGapCnt
+ 0x100813e2 0xca _L1e_csrc_ShortDrxSchd
+ 0x100814ac 0x30 _L1e_csrc_ShortDrxReSchd
+ 0x100814dc 0x104 _zPHY_ecsrc_CnnDrxStartSchedule
+ 0x100815e0 0x48 _zPHY_ecsrc_CnnDrxSetup
+ 0x10081628 0x1b _zPHY_ecsrc_CnnDrxRelease
+ 0x10081643 0x41 _L1e_csrc_ShortDrxSchdFlag
+ 0x10081684 0x8 _L1e_csrc_GetDfeValidFlag
+ 0x1008168c 0x87 _zPHY_ecsrc_CtrlAbortMeasProcess
+ 0x10081713 0x8 _zPHY_ecsrc_ReadSubframeOffset
+ 0x1008171b 0x15 _zPHY_ecsrc_SubframeOffsetToRfc
+ 0x10081730 0x8 _zPHY_ecsrc_SetFddAdjust
+ 0x10081738 0x30 _zPHY_ecsrc_ClearRfcSFData
+ 0x10081768 0x12 _zPHY_ecsrc_ClearRfTable
+ 0x1008177a 0x12 _L1e_csrc_ClearRfMeasState
+ 0x1008178c 0x2c _zPHY_ecsrc_SetFreq
+ 0x100817b8 0xa _zPHY_ecsrc_SetInterFreq
+ 0x100817c2 0x15 _zPHY_ecsrc_FindEvent
+ 0x100817d7 0x43 _zPHY_ecsrc_RegisterEvent
+ 0x1008181a 0x1d _zPHY_ecsrc_CancelEvent
+ 0x10081837 0x12 _zPHY_ecsrc_CancelAllEvent
+ 0x10081849 0x7b _zPHY_ecsrc_CheckEvent
+ 0x100818c4 0x40 _zPHY_ecsrc_ConnCheckEvent
+ 0x10081904 0x44 _zPHY_ecsrc_ExcuteEvent
+ 0x10081948 0x25 _zPHY_ecsrc_ChangeIntraReportPeriod
+ 0x1008196d 0x33 _zPHY_ecsrc_ChangeIntraReportPeriodDrx
+ 0x100819a0 0x7 _zPHY_ecsrc_OnSetMode
+ 0x100819a7 0x25 _zPHY_ecsrc_OnIratIdlePeriodRepReq
+ 0x100819cc 0x37 _zPHY_ecsrc_OnInactiveTimeReportInt
+ 0x10081a03 0x19 _zPHY_ecsrc_OnFreqListConfigReq
+ 0x10081a1c 0x2e _zPHY_ecsrc_OnIratMeasConfigReq
+ 0x10081a4a 0x32 _zPHY_ecsrc_OnIratMeasReportInt
+ 0x10081a7c 0xf1 _zPHY_ecsrc_OnIratGapConfigReq
+ 0x10081b6d 0x6f _zPHY_ecsrc_OnIratGapConfigDelayInt
+ 0x10081bdc 0x24 _zPHY_ecsrc_OnRfStartDealSfInt
+ 0x10081c00 0x14 _zPHY_ecsrc_OnRfCloseDealSfInt
+ 0x10081c14 0x37 _zPHY_ecsrc_OnReset
+ 0x10081c4b 0x4e _zPHY_ecsrc_OnCellSearchReq
+ 0x10081c99 0x39 _zPHY_ecsrc_InitOnCellSearchReq
+ 0x10081cd2 0xae _zPHY_ecsrc_CtrlAppointSearchPbchTimeEvent
+ 0x10081d80 0x52 _zPHY_ecsrc_CtrlAppointSearchTimeEvent
+ 0x10081dd2 0x2a _zPHY_ecsrc_CtrlAppointSearchPbchEndEvent
+ 0x10081dfc 0xd _zPHY_ecsrc_AppointCellSearchType
+ 0x10081e09 0x17 _zPHY_ecsrc_NeibCellSearchType
+ 0x10081e20 0x99 _zPHY_ecsrc_IdleOnCellSearchReq
+ 0x10081eb9 0x16 _zPHY_ecsrc_SlaveOnCellSearchReq
+ 0x10081ecf 0x1a _zPHY_ecsrc_OnCtrlIniSearchCnf
+ 0x10081ee9 0x19 _zPHY_ecsrc_OnTimeDelayInt
+ 0x10081f02 0x19 _zPHY_ecsrc_OnSssUpdateCounterCnf
+ 0x10081f1b 0xd _zPHY_ecsrc_OnIniMeasTimeEvent
+ 0x10081f28 0x1c _zPHY_ecsrc_OnAbortCellSearchReq
+ 0x10081f44 0x27 _zPHY_ecsrc_OnCommonConfigReq
+ 0x10081f6b 0x4e _zPHY_ecsrc_OnMeasConfigReq
+ 0x10081fb9 0x132 _zPHY_ecsrc_SaveMask
+ 0x100820eb 0x98 _zPHY_ecsrc_OnMeasMaskSetReq
+ 0x10082183 0x30 _zPHY_ecsrc_OnAbortMeasReq
+ 0x100821b3 0x3e _zPHY_ecsrc_OnChangeMeasPeriodReq
+ 0x100821f1 0x11 _zPHY_ecsrc_OnIdleInterRfChangeFinishedEvent
+ 0x10082202 0x39 _zPHY_ecsrc_OnIratMeasGapConfigReq
+ 0x1008223b 0x21 _zPHY_ecsrc_OnFreqScanReq
+ 0x1008225c 0x3b _zPHY_ecsrc_InitOnFreqScanReq
+ 0x10082297 0x53 _zPHY_ecsrc_IdleOnFreqScanReq
+ 0x100822ea 0x27 _zPHY_ecsrc_SlaveOnFreqScanReq
+ 0x10082311 0x21 _zPHY_ecsrc_OnCtrlSearchFreqScanCnf
+ 0x10082332 0x1c _zPHY_ecsrc_OnHandoverReq
+ 0x1008234e 0x10 _zPHY_ecsrc_OnPlmnResumeSrvCellTpu
+ 0x1008235e 0x2c _zPHY_ecsrc_OnPlmnPeriodTpuIntIn
+ 0x1008238a 0x26 _zPHY_ecsrc_FreqScanSubFrameIntDelay
+ 0x100823b0 0x47 _zPHY_ecsrc_RunningCheck
+ 0x100823f7 0x8d _zPHY_ecsrc_OnArfcnListInfo
+ 0x10082484 0x47 _zPHY_amt_Lte_Set_EarfcnInfo
+ 0x100824cb 0xf _L1e_csrc_HandoverSuccPro
+ 0x100824da 0x1b _zPHY_ecsrc_StartProc
+ 0x100824f5 0x15f _zPHY_ecsrc_ComProc
+ 0x10082654 0x15 _zPHY_ecsrc_InitProc
+ 0x10082669 0x6f _zPHY_ecsrc_IdleProc
+ 0x100826d8 0x21 _zPHY_ecsrc_ConnProc
+ 0x100826f9 0x91 _zPHY_ecsrc_SlaveProc
+ 0x1008278a 0x5b _zPHY_ecsrc_Ctrl
+ 0x100827e5 0x48 _zPHY_ecsrc_ThreadEntry
+ 0x1008282d 0xc8 _zEcsrc_PreEvent
+ 0x100828f5 0x38 _zEcsrc_OnEvent
+ 0x1008292d 0x52 _zPHY_ecsrc_ReadSnr
+ 0x1008297f 0xd6 _zPHY_ecsrc_ReadSearctT
+ 0x10082a55 0x1e _zPHY_ecsrc_ReadIntraSearctT
+ 0x10082a73 0x1e _zPHY_ecsrc_ReadSpeedSearctT
+ 0x10082a91 0x1d _zPHY_ecsrc_ReadCfoUpdateT
+ 0x10082aae 0x2a _zPHY_ecsrc_GetDestTime
+ 0x10082ad8 0x1c _zPHY_ecsrc_CalDestTimeOffset
+ 0x10082af4 0x19 _zPHY_ecsrc_GetNonHighPrioFreqNum
+ 0x10082b0d 0x19 _zPHY_ecsrc_GetHighPrioFreqNum
+ 0x10082b26 0x13 _zPHY_ecsrc_GetReportNum
+ 0x10082b39 0x31 _zPHY_ecsrc_NeedIntraSearchStep
+ 0x10082b6a 0x2e _zPHY_ecsrc_NeedIntraSearchStepNormal
+ 0x10082b98 0x45 _zPHY_ecsrc_NeedIntraSearch
+ 0x10082bdd 0x22 _zPHY_ecsrc_IsNonHighPrioWorkDrx
+ 0x10082bff 0xaa _zPHY_ecsrc_NeedWork
+ 0x10082ca9 0x54 _zPHY_ecsrc_CalcInitDrxNum
+ 0x10082cfd 0x7f _zPHY_ecsrc_CalcWorkDrxNum
+ 0x10082d7c 0x22 _zPHY_ecsrc_NeedInterSearch
+ 0x10082d9e 0x9 _zPHY_ecsrc_NeedInterMeas
+ 0x10082da7 0x52 _zPHY_ecsrc_NeedIntraMeas
+ 0x10082df9 0x1c _zPHY_ecsrc_FreqIndexAcc
+ 0x10082e15 0x37 _zPHY_ecsrc_IsLastFreqInDrx
+ 0x10082e4c 0x72 _L1e_csrc_SRCellRank
+ 0x10082ebe 0x9a _L1e_csrc_SaveSRCellInfo
+ 0x10082f58 0x52 _L1e_csrc_SetSRCellInfo
+ 0x10082faa 0x121 _L1e_csrc_GetMobileCxtFlag
+ 0x100830cb 0x49 _zPHY_ecsrc_CtrlIdleIntraMeasEndEventNew
+ 0x10083114 0x37 _zPHY_ecsrc_GetReportDrxNum
+ 0x1008314b 0x2 _zPHY_ecsrc_EverTrue
+ 0x1008314d 0x10 _zPHY_ecsrc_StartDelayTimer
+ 0x1008315d 0x9 _zPHY_ecsrc_WaitEvent
+ 0x10083166 0x1d _zPHY_ecsrc_SchedInit
+ 0x10083183 0x20 _zPHY_ecsrc_SchedStop
+ 0x100831a3 0x8 _zPHY_ecsrc_SchedStart
+ 0x100831ab 0x15 _zPHY_ecsrc_NeedWorkInReportPeriod
+ 0x100831c0 0xbc _zPHY_ecsrc_OnStartPi
+ 0x1008327c 0x63 _zPHY_ecsrc_OnEndPi
+ 0x100832df 0x9b _zPHY_ecsrc_ReportOneFreq
+ 0x1008337a 0x7c _zPHY_ecsrc_ReportPreValue
+ 0x100833f6 0x49 _zPHY_ecsrc_ReportInra
+ 0x1008343f 0x57 _zPHY_ecsrc_DoReportIner
+ 0x10083496 0x11 _zPHY_ecsrc_ReportInter
+ 0x100834a7 0x12 _zPHY_ecsrc_OneFreqModeWork
+ 0x100834b9 0x1a _zPHY_ecsrc_OneFreqIntraWork
+ 0x100834d3 0x27 _zPHY_ecsrc_IntraSearchInLowSnr
+ 0x100834fa 0x36 _zPHY_ecsrc_FixedStrongSearch
+ 0x10083530 0x8 _zPHY_ecsrc_GetFixedStrongSearchFlag
+ 0x10083538 0x30 _zPHY_ecsrc_NeedSearchInLowSnr
+ 0x10083568 0x25 _zPHY_ecsrc_NeedSearchInRA
+ 0x1008358d 0x14 _zPHY_ecsrc_OneFreqInterWork
+ 0x100835a1 0x11 _zPHY_ecsrc_GerFreqNumPerDrx
+ 0x100835b2 0x5c _zPHY_ecsrc_NextInterFreqInDrx
+ 0x1008360e 0x23 _zPHY_ecsrc_IntraWorkInDrx
+ 0x10083631 0x20 _zPHY_ecsrc_InterFinishInDrx
+ 0x10083651 0x35 _zPHY_ecsrc_RecordInterDoneInDrx
+ 0x10083686 0x65 _zPHY_ecsrc_InterSchedInitPerDrx
+ 0x100836eb 0x9b _zPHY_ecsrc_GetIntraSearchTime
+ 0x10083786 0x2e _zPHY_ecsrc_GetInterSearchTime
+ 0x100837b4 0x7f _zPHY_ecsrc_GetIntraMeasTime
+ 0x10083833 0xa1 _zPHY_ecsrc_GetInterMeasTime
+ 0x100838d4 0x4d _zPHY_ecsrc_GetIntraWorkTime
+ 0x10083921 0x15 _zPHY_ecsrc_GetInterWorkTime
+ 0x10083936 0x69 _zEcsr_GetWorkTimeInCurDrx
+ 0x1008399f 0x71 _zPHY_ecsrc_ChangeMeasMode
+ 0x10083a10 0x36 _zPHY_ecsrc_IntraMeasStart
+ 0x10083a46 0x3 _zPHY_ecsrc_InterMeasStart
+ 0x10083a49 0x15 _zPHY_ecsrc_IntraSearchStart
+ 0x10083a5e 0xd _zPHY_ecsrc_SetIntraWorkTime
+ 0x10083a6b 0x1e _zPHY_ecsrc_SetInterWorkTime
+ 0x10083a89 0x12 _zPHY_ecsrc_ServCellStart
+ 0x10083a9b 0x26 _zPHY_ecsrc_SearchInMeasConfig
+ 0x10083ac1 0x21 _zPHY_ecsrc_ReadIndexInSchedContext
+ 0x10083ae2 0x21 _zPHY_ecsrc_IntraFreqStart
+ 0x10083b03 0x12b _zPHY_ecsrc_InterFreqStart
+ 0x10083c2e 0xb4 _zPHY_ecsrc_OneFreqStart
+ 0x10083ce2 0x26 _zPHY_ecsrc_NeedSchedInter
+ 0x10083d08 0x1 _zPHY_ecsrc_BeforeInter
+ 0x10083d09 0x15 _zPHY_ecsrc_BeforeOneFreq
+ 0x10083d1e 0x24 _zPHY_ecsrc_NeedInitial
+ 0x10083d42 0x49 _zPHY_ecsrc_ChangeMeasPeriodIdle
+ 0x10083d8b 0x32 _zPHY_ecsrc_ReportNoInactiveTime
+ 0x10083dbd 0x7 _zPHY_ecsrc_NeedAdjustBndFrmCfo
+ 0x10083dc4 0x5e _zPHY_ecsrc_AdjustBndFrmCfo
+ 0x10083e22 0x15 _zPHY_ecsrc_SetShortDrxState
+ 0x10083e37 0x12 _zPHY_ecsrc_CfgRfcRxOffset
+ 0x10083e49 0x2b _zPHY_ecsrc_AdjustSrvTpu
+ 0x10083e74 0x7 _zPHY_ecsrc_BackupCFOFreqOffset
+ 0x10083e7b 0x8 _l1e_csrc_GetDrxCnt
+ 0x10083e83 0x3b _zPHY_ecsrc_DrxReStartSearchMeas
+ 0x10083ebe 0x2a _zPHY_ecsrc_ReadPrio
+ 0x10083ee8 0x85 _zPHY_ecsrc_WakeupPs
+ 0x10083f6d 0x8 _L1e_csrc_GetCurCtx
+ 0x10083f75 0x8 _L1e_csrc_GetMeasBit
+ 0x10083f7d 0x98 _L1e_csrc_TempRead
+ 0x10084015 0x92 _L1e_ecsrc_UpdateBackBchBnd
+ 0x100840a7 0x9 _L1e_csrc_AtZepcgSetLowPower
+ 0x100840b0 0x9 _L1e_csrc_AtZepcgClrLowPower
+ 0x100840b9 0x40 _L1e_csrc_AtZepcgSetPhyCfg
+ 0x100840f9 0x67 _L1e_csrc_GetFreqOffset
+ 0x10084160 0x90 _L1e_csrc_SetDisableAfcReloadFlag
+ 0x100841f0 0x4a _L1e_csrc_SetScanFailNum
+ 0x1008423a 0x95 _L1e_csrc_C0CaliPeriod
+ 0x100842cf 0x87 _L1e_csrc_C0CaliEvalue
+ 0x10084356 0x10b _L1e_csrc_C0Update
+ 0x10084461 0x80 _L1e_csrc_C0CalRsrp
+ 0x100844e1 0x5f _L1e_csrc_C0CalAfc
+ 0x10084540 0x1c _L1e_csrc_C0CaliRestart
+ 0x1008455c 0x16 _L1e_csrc_C0CaliInit
+ 0x10084572 0x13 _L1e_csrc_C0FactorUtcValid
+ 0x10084585 0x6f _L1e_csrc_UtcTimeExpired
+ 0x100845f4 0x65 _L1e_csrc_BackupCurPpm
+ 0x10084659 0x30 _L1e_csrc_GetCurPpmValid
+ 0x10084689 0x44 _L1e_csrc_TempNoChange
+ 0x100846cd 0x33 _L1e_csrc_FindFreqOffsetIndex
+ 0x10084700 0x26 _L1e_csrc_UpdateFtErrorList
+ .text 0x10084726 0x212 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_fsm.o)
+ 0x10084726 0x212 _zPHY_emc_ProPhyStateCtrl
+ .text 0x10084938 0xb29 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_db.o)
+ 0x10084938 0x7 _zPHY_ecsrc_SatAdd
+ 0x1008493f 0x9 _zPHY_ecsrc_SatSub
+ 0x10084948 0x18 _zPHY_ecsrc_CellDatabaseReset
+ 0x10084960 0x2b _zPHY_ecsrc_GetCellInfo
+ 0x1008498b 0x48 _zPHY_ecsrc_GetAddCell
+ 0x100849d3 0x61 _zPHY_ecsrc_DeleteCell
+ 0x10084a34 0x4d _zPHY_ecsrc_DeleteOldCell
+ 0x10084a81 0x69 _zPHY_ecsrc_DeleteAllCell
+ 0x10084aea 0x4d _zPHY_ecsrc_DeleteNoCfgCell
+ 0x10084b37 0x1a _L1e_Csrc_IsServcell
+ 0x10084b51 0x13 _L1e_Csrc_IsServcellEarfcn
+ 0x10084b64 0x42 _zPHY_ecsrc_FindCell
+ 0x10084ba6 0x29 _zPHY_ecsrc_ClearOtherCell
+ 0x10084bcf 0x12 _zPHY_ecsrc_FindServCell
+ 0x10084be1 0x4e _zPHY_ecsrc_CtrlICPWriteMeasPriority
+ 0x10084c2f 0x9e _zPHY_ecsrc_SearchAddCellToDatabase
+ 0x10084ccd 0x8d _zPHY_ecsrc_CtrlRefreshDataBase
+ 0x10084d5a 0x54 _zPHY_ecsrc_CtrlUpdateBoundary
+ 0x10084dae 0x49 _zPHY_ecsrc_AdjustCellAge
+ 0x10084df7 0x3a _zPHY_ecsrc_CtrlGetStrongestCell
+ 0x10084e31 0xc _zPHY_ecsrc_ScellDatabaseReset
+ 0x10084e3d 0x44 _zPHY_ecsrc_CtrlCellDatabaseAging
+ 0x10084e81 0x2a _zPHY_ecsrc_ClearSearchNewCellFlag
+ 0x10084eab 0x2e _zPHY_ecsrc_ClearAppointCellFlag
+ 0x10084ed9 0x23 _zPHY_ecsrc_ClearValidCellFlag
+ 0x10084efc 0x22 _zEcsrc_FindFreq
+ 0x10084f1e 0x13 _zEcsrc_IsIcp
+ 0x10084f31 0x40 _zEcsrc_GetMeasBand
+ 0x10084f71 0x19 _zEcsrc_GetMeasTimes
+ 0x10084f8a 0x2c _zPHY_ecsrc_ClearFreqInfo
+ 0x10084fb6 0x34 _zPHY_ecsrc_ClearNoCfgFreqInfo
+ 0x10084fea 0x1f _zPHY_ecsrc_FindFreqInfo
+ 0x10085009 0x60 _zPHY_ecsrc_ExChangeFreqInfo
+ 0x10085069 0x9e _zPHY_ecsrc_SaveFreqInfo
+ 0x10085107 0x4d _zPHY_ecsrc_ReadRsrpCaliInfo
+ 0x10085154 0x4a _zPHY_ecsrc_UpdateTimeOffset
+ 0x1008519e 0x41 _zPHY_ecsrc_RecoverTimeOffset
+ 0x100851df 0x48 _zPHY_ecsrc_ChangeTimeOffset
+ 0x10085227 0x23 _zPHY_ecsrc_ReadTimeOffset
+ 0x1008524a 0x1e _zPHY_ecsrc_GetCellNum
+ 0x10085268 0xb _L1e_Csrc_UpdateServCell
+ 0x10085273 0x10 _L1e_Csrc_ServCellChange
+ 0x10085283 0xc _L1e_Csrc_ChangeNeiConfigFlag
+ 0x1008528f 0x7e _zPHY_ecsrc_DealSrvBndFrmCfo
+ 0x1008530d 0x25 _L1e_csrc_SetMeasState
+ 0x10085332 0x87 _zPHY_ecsrc_GetMeasCell
+ 0x100853b9 0x4b _zPHY_ecsrc_GetMeasCellNum
+ 0x10085404 0x12 _zPHY_ecsrc_GetFddBufferMode
+ 0x10085416 0x1e _zPHY_ecsrc_GetIndexInFreqMeasMode
+ 0x10085434 0x11 _zPHY_ecsrc_GetMeasAge
+ 0x10085445 0x1c _zPHY_ecsrc_GetFreqOffset
+ .text 0x10085461 0x2c26 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x10085461 0xb _zPHY_ecsrc_CtrlShiftSlaveFunState
+ 0x1008546c 0x14 _zPHY_ecsrc_CtrlShiftSlaveSynState
+ 0x10085480 0xa _zPHY_ecsrc_MulmSetRfWorkSet
+ 0x1008548a 0x65 _zPHY_ecsrc_MulmCfgRFCModem7510
+ 0x100854ef 0x5f _zPHY_ecsrc_MulmRegRFStartClose
+ 0x1008554e 0x121 _zPHY_ecsrc_MulmIratIdlePeriodRepProcess7510
+ 0x1008566f 0x44 _zEcsr_UpdateSiReadState
+ 0x100856b3 0x35 _zPHY_ecsrc_MulmCtrlSetMode
+ 0x100856e8 0xa3 _zPHY_ecsrc_MulmSlaveReset
+ 0x1008578b 0x14 _zPHY_ecsrc_MulmFreqListConfigProcess
+ 0x1008579f 0x60 _L1e_Mulm_ReadSearchT
+ 0x100857ff 0x58 _L1e_Mulm_NeedSearch
+ 0x10085857 0x34 _L1e_Mulm_NeedMeas
+ 0x1008588b 0x47 _zPHY_ecsrc_MulmIratMeasScheduleProcess
+ 0x100858d2 0x3c _zPHY_ecsrc_MulmIratAddMeasReport
+ 0x1008590e 0x77 _zPHY_ecsrc_MulmMeasReset
+ 0x10085985 0xe5 _zPHY_ecsrc_MulmIratMeasConfigProcess
+ 0x10085a6a 0x72 _zPHY_ecsrc_MulmReportFreqMeasResult
+ 0x10085adc 0x5d _zPHY_ecsrc_MulmIratMeasResultHandle
+ 0x10085b39 0x9 _zPHY_ecsrc_MulmIratResetMeasCnt
+ 0x10085b42 0x8d _zPHY_ecsrc_MulmIratMeasReportIntHandle
+ 0x10085bcf 0xaf _zPHY_ecsrc_MulmIratMeasFilter
+ 0x10085c7e 0x88 _zPHY_ecsrc_MulmIratFreqFilter
+ 0x10085d06 0x72 _zPHY_ecsrc_MulmIratUpdateMeasInd
+ 0x10085d78 0x34 _zPHY_ecsrc_MulmIratUpdateFreqReport
+ 0x10085dac 0x40 _zPHY_ecsrc_MulmIratSetFilterFact
+ 0x10085dec 0x2a _zPHY_ecsrc_MulmIratReadPrio
+ 0x10085e16 0x55 _zPHY_ecsrc_MulmIratSearchMeasureStartSchedule
+ 0x10085e6b 0x17 _zPHY_ecsrc_MulmSlaveCfgRfcMeas1Offset7510
+ 0x10085e82 0x37 _zPHY_ecsrc_MulmSlaveGapStartOffsetCfg7510
+ 0x10085eb9 0x43 _zPHY_ecsrc_MulmSlaveGapEndOffsetCfg7510
+ 0x10085efc 0x36 _zPHY_ecsrc_MulmRegTpuSingleEvent
+ 0x10085f32 0x63 _zPHY_ecsrc_MulmGetGapType
+ 0x10085f95 0x28 _zPHY_ecsrc_MulmRegTpuEvent
+ 0x10085fbd 0xed _zPHY_ecsrc_MulmIratGapSchedFlow
+ 0x100860aa 0x62 _zPHY_ecsrc_ReRegistGapConfigDelag
+ 0x1008610c 0x62 _zPHY_ecsrc_MulmIratGapSchedFlowProtect
+ 0x1008616e 0x56 _zPHY_ecsrc_MulmBlackCellFilter
+ 0x100861c4 0x60 _zPHY_ecsrs_MulmRemainTimeInGap
+ 0x10086224 0x2d _zPHY_ecsrs_MulmProtectTimeBeforeGap
+ 0x10086251 0x1a _zPHY_ecsrc_MulmCalMeasTime
+ 0x1008626b 0x5b _zPHY_ecsrc_MulmCalSearchTime
+ 0x100862c6 0x104 _zPHY_ecsrc_MulmTpuCnf
+ 0x100863ca 0x13 _zPHY_ecsrc_MulmCsr2TpuUpdateCounterCnfHandle
+ 0x100863dd 0x4a _zPHY_ecsrc_MulmSlavePlmnSearchStart
+ 0x10086427 0x2a _zPHY_ecsrc_MulmSlavePlmnSearchFinHandle
+ 0x10086451 0x42 _zPHY_ecsrc_MulmSlavePlmnMeasureTimerIntHandle
+ 0x10086493 0x2e _zPHY_ecsrc_MulmSlavePlmnAbortCellSearchHandle
+ 0x100864c1 0x45 _zPHY_ecsrs_MulmPlmnSib1InGap
+ 0x10086506 0x45 _zPHY_ecsrc_MulmRegNotSynSubFrameInt
+ 0x1008654b 0x2c _zPHY_ecsrc_MulmRegCsrmSfInt
+ 0x10086577 0xaa _zPHY_ecsrc_MulmIratGapStartTpuIntHandle
+ 0x10086621 0x20 _zPHY_ecsrc_MulmUnRegistSearchMeasInt
+ 0x10086641 0x42 _zPHY_ecsrc_MulmIratGapEndTpuIntHandle
+ 0x10086683 0x50 _zPHY_ecsrc_MulmSlaveAbortGapProtectTimerEnable
+ 0x100866d3 0x48 _zPHY_ecsrc_MulmIratMeasDoneHandle
+ 0x1008671b 0x6e _zPHY_ecsrc_MulmIratAbortGapHandle
+ 0x10086789 0x68 _zPHY_ecsrc_MulmIratAbortGapProtectTimerHandle
+ 0x100867f1 0x97 _zPHY_ecsrs_MulmIratGapPositionCheck
+ 0x10086888 0x27 _zPHY_ecsrs_MulmGapCoverTime
+ 0x100868af 0x42 _zPHY_ecsrm_MulmPbchStartCheck
+ 0x100868f1 0x27 _zPHY_ecsrs_MulmEnableRfcEventTable
+ 0x10086918 0x26 _zPHY_ecsrs_Mulm6MSRfcMeas1GapOffsetCfg
+ 0x1008693e 0x64 _zPHY_ecsrs_MulmRfOpenNo
+ 0x100869a2 0x49 _zPHY_ecsrs_MulmConfigSynState
+ 0x100869eb 0x56 _zPHY_ecsrs_MulmEnableRF
+ 0x10086a41 0x45 _zPHY_emc_MulmCsrRfStartDeal
+ 0x10086a86 0x62 _zPHY_emc_MulmCsrRfEndDeal
+ 0x10086ae8 0x20 _zPHY_emc_DealRFCloseEvent
+ 0x10086b08 0x2d _zPHY_ecsrc_CtrlMulmDbAging
+ 0x10086b35 0xf _zPHY_ecsrc_CtrlSetMulmSlaveSearchMeasAgeInfor
+ 0x10086b44 0x97 _zPHY_ecsrc_CtrlMulmRefreshDataBase
+ 0x10086bdb 0x50 _zPHY_ecsrs_MulmTpuAdjCheckTime
+ 0x10086c2b 0x2f _zPHY_ecsrs_MulmIcpPssBoundryAdj
+ 0x10086c5a 0x1a _zPHY_ecsrs_MulmPssTpuCnf
+ 0x10086c74 0x46 _zPHY_ecsrs_MulmIsPssWorkTime
+ 0x10086cba 0xa0 _zPHY_ecsrs_MulmGetPssHwStartTime
+ 0x10086d5a 0x53 _zPHY_ecsrs_MulmPssCfg
+ 0x10086dad 0xb _zPHY_ecsrs_MulmPssConfig
+ 0x10086db8 0x16 _zPHY_ecsrs_MulmPssGapCoverTime
+ 0x10086dce 0x68 _zPHY_ecsrc_MulmGetValidCellFrameBoundry7510
+ 0x10086e36 0x3f _zPHY_ecsrc_MulmTpuAdjPro
+ 0x10086e75 0x27 _zPHY_ecsrc_MulmBoundryAdj
+ 0x10086e9c 0x7f _zPHY_ecsrs_MulmCheckTpuAdj
+ 0x10086f1b 0x28 _zPHY_ecsrs_MulmStartTpuAdj
+ 0x10086f43 0xf3 _zPHY_ecsrc_MulmIratSearchStartSchedule7510
+ 0x10087036 0x56 _zPHY_emc_MulmSlaveMeasureReportProtect
+ 0x1008708c 0x190 _zPHY_emc_MulmSlaveMeasureFlow
+ 0x1008721c 0x7 _zPHY_ecsrs_MulmIratFSPssGapPositionCheck
+ 0x10087223 0x17 _zPHY_ecsrs_MulmIratCheckGapTime
+ 0x1008723a 0x3d _zPHY_ecsrs_MulmIratPssTimeCheck
+ 0x10087277 0x4b _zPHY_ecsrs_MulmIratSssGapPositionCheck
+ 0x100872c2 0x39 _zPHY_ecsrs_MulmAgcStable
+ 0x100872fb 0x15 _L1e_mulm_CfoAccNum
+ 0x10087310 0x87 _zPHY_ecsrs_MulmCfoConfig
+ 0x10087397 0x1e _zPHY_ecsrs_MulmSssCfg
+ 0x100873b5 0x8b _zPHY_ecsrs_MulmIsTddSssWorkTime
+ 0x10087440 0x18 _zPHY_ecsrs_MulmStartICSPSubFrameInt
+ 0x10087458 0x13 _zPHY_ecsrs_MulmStartSynSearchSubFrameInt
+ 0x1008746b 0x40 _zPHY_ecsrs_MulmGapCoverTime7510
+ 0x100874ab 0x136 _zPHY_ecsrs_MulmIsFddSssWorkTime
+ 0x100875e1 0x1d _zPHY_ecsrs_MulmGetMeasBaseTime
+ 0x100875fe 0x154 _zPHY_ecsrs_MulmCfoCheckTime
+ 0x10087752 0xa9 _zPHY_ecsrs_MulmIsValidTime
+ 0x100877fb 0xfd _zPHY_ecsrs_MulmCheckOpenTime
+ 0x100878f8 0xb3 _zPHY_ecsrm_MulmBuffCheckOpenTimePeriod
+ 0x100879ab 0x5a _zPHY_ecsrs_MulmGapCoverCheck
+ 0x10087a05 0x47 _zPHY_ecsrs_MulmGapCoverBufferCheck
+ 0x10087a4c 0x14 _zPHY_ecsrs_MulmIsShortGap
+ 0x10087a60 0x16 _zPHY_ecsrs_MulmGetFreqIndex
+ 0x10087a76 0x2e _zPHY_ecsrc_MulmIratClearPreFilter
+ 0x10087aa4 0x26 _zPHY_ecsrs_AbsModSub
+ 0x10087aca 0xc _zPHY_ecsrs_MulmCsBefore
+ 0x10087ad6 0x26 _zPHY_ecsrs_MulmCsNeedCs
+ 0x10087afc 0xc _zPHY_ecsrs_MulmCsNeedAgc
+ 0x10087b08 0x37 _zPHY_ecsrs_MulmCsBeforeAgc
+ 0x10087b3f 0xb _zPHY_ecsrs_MulmCsIsOnAgc
+ 0x10087b4a 0x1c _zPHY_ecsrs_MulmCsAgcProc
+ 0x10087b66 0x8 _zPHY_ecsrs_MulmCsAgcProcEnd
+ 0x10087b6e 0xb _zPHY_ecsrs_MulmCsNeedPss
+ 0x10087b79 0x2d _zPHY_ecsrs_MulmCsBeforePss
+ 0x10087ba6 0x18 _zPHY_ecsrs_MulmCsIsOnPss
+ 0x10087bbe 0x41 _zPHY_ecsrs_MulmCsPssProc
+ 0x10087bff 0x43 _zPHY_ecsrs_MulmCsPssProcEnd
+ 0x10087c42 0x14 _zPHY_ecsrs_MulmCsNeedTpuAdj1
+ 0x10087c56 0xc _zPHY_ecsrs_MulmCsNeedTpuAdj
+ 0x10087c62 0xc _zPHY_ecsrs_MulmCsTpuAdjProc
+ 0x10087c6e 0x1a _zPHY_ecsrs_MulmCsTpuAdjProc2
+ 0x10087c88 0xe _zPHY_ecsrs_MulmCsTpuCheck
+ 0x10087c96 0xc _zPHY_ecsrs_MulmCsNeedCfo
+ 0x10087ca2 0x15 _zPHY_ecsrs_MulmCsBeforeCfo
+ 0x10087cb7 0x25 _zPHY_ecsrs_MulmCsBeforeCfoOnce
+ 0x10087cdc 0x20 _zPHY_ecsrs_MulmCsIsOnCfo
+ 0x10087cfc 0x1d _zPHY_ecsrs_MulmCsNeedMoreCfo
+ 0x10087d19 0x30 _zPHY_ecsrs_MulmCsCfoProc
+ 0x10087d49 0x4a _zPHY_ecsrs_MulmCsCfoOnceProcEnd
+ 0x10087d93 0x8 _zPHY_ecsrs_MulmCsCfoProcEnd
+ 0x10087d9b 0x31 _zPHY_ecsrs_MulmLteCordicConfig
+ 0x10087dcc 0x12 _zPHY_ecsrs_MulmGetLteCordicValue
+ 0x10087dde 0xc _zPHY_ecsr_MulmCordicAdjust
+ 0x10087dea 0x5a _zPHY_ecsr_MulmToLteCfo
+ 0x10087e44 0x8 _zPHY_ecsr_MulmReadCordicValue
+ 0x10087e4c 0x8 _zPHY_ecsr_MulmWriteCordicValue
+ 0x10087e54 0xc _zPHY_ecsrs_MulmCsNeedSss
+ 0x10087e60 0x28 _zPHY_ecsrs_MulmCsBeforeSss
+ 0x10087e88 0x29 _zPHY_ecsrs_MulmCsIsOnSss
+ 0x10087eb1 0x18 _zPHY_ecsrs_MulmIsSssWorkTime
+ 0x10087ec9 0x47 _zPHY_ecsrs_MulmCsSssProc
+ 0x10087f10 0x50 _zPHY_ecsrs_MulmCsSssProcEnd
+ 0x10087f60 0x75 _zPHY_ecsrs_MulmCsProEnd
+ 0x10087fd5 0x8 _zPHY_ecsrc_MulmSetRfState
+ 0x10087fdd 0x25 _zPHY_ecsrc_MulmSchedCheck
+ 0x10088002 0x15 _zPHY_ecsrs_MulmCheckReadTime
+ 0x10088017 0x66 _zPHY_ecsrs_MulmIsSssSchedSubFrm
+ 0x1008807d 0xa _zPHY_ecsrs_Wait
+ .text 0x10088087 0xf36 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x10088087 0x1a _zPHY_ecsrc_InitCellSearchProc
+ 0x100880a1 0x1c _zPHY_ecsrc_IdleCellSearchProc
+ 0x100880bd 0x4d _zPHY_ecsrc_SetCellSearchCnf
+ 0x1008810a 0x7c _zPHY_ecsrc_InitAppointedCS
+ 0x10088186 0x16 _zPHY_ecsrc_InitNotAppointedCS
+ 0x1008819c 0x46 _zPHY_ecsrc_CtrlSssUpdateProcess
+ 0x100881e2 0x42 _zPHY_ecsrc_ReSearchOrReportCell
+ 0x10088224 0x37 _zPHY_ecsrc_SetInitMeasTime
+ 0x1008825b 0x6b _zPHY_ecsrc_CtrlICPTimeEvent
+ 0x100882c6 0x3f _zPHY_ecsrc_CtrlICPTpuAdjust
+ 0x10088305 0xaf _zPHY_ecsrc_CtrlICPMeasTimeEvent
+ 0x100883b4 0x3c _zPHY_ecsrc_SortCellSearchCnf
+ 0x100883f0 0x4a _zPHY_ecsrc_SetReportCellList
+ 0x1008843a 0x99 _zPHY_ecsrc_CtrlICPReportResult
+ 0x100884d3 0xc2 _zPHY_ecsrc_CtrlIcpBchHandle
+ 0x10088595 0x4f _zPHY_ecsrc_CtrlBchDecodeEvent
+ 0x100885e4 0x48 _zPHY_ecsrc_CtrlIcpReportNoCell
+ 0x1008862c 0x62 _zPHY_ecsrc_CtrlIcpTimeEndEvent
+ 0x1008868e 0x29 _zPHY_ecsrc_CfgSynTable
+ 0x100886b7 0x36 _zPHY_ecsrc_ReConstructRxPara
+ 0x100886ed 0x16 _zPHY_ecsrc_ConfirmRxPara
+ 0x10088703 0x35 _zPHY_ecsrc_PlmnBackupSrvCell
+ 0x10088738 0x86 _zPHY_ecsrc_PlmnResumeDlRfcEnableEvent
+ 0x100887be 0xcc _zPHY_ecsrc_PlmnPhyResultReport
+ 0x1008888a 0x54 _zPHY_ecsrc_FreqScanResultReportHandle
+ 0x100888de 0x43 _zPHY_ecsrc_PlmnResumeSrvCellTPU
+ 0x10088921 0x3b _zPHY_ecsrc_PlmnCurTime2PiTimeDistance
+ 0x1008895c 0x10 _zPHY_ecsrc_PlmnHasEnoughTime
+ 0x1008896c 0x30 _zPHY_ecsrc_PlmnProcessPeriodicalTpuIntIn
+ 0x1008899c 0x24 _zPHY_ecsrc_PlmnResumeSrvCellNew
+ 0x100889c0 0x31 _zPHY_ecsrc_PlmnSearchResultHandleNew
+ 0x100889f1 0x37 _zPHY_ecsrc_PlmnFreqScanReqPro
+ 0x10088a28 0x15 _zPHY_ecsrc_PlmnCellSearchReqPro
+ 0x10088a3d 0x72 _zPHY_ecsrc_PlmnPeriodTpuInPro
+ 0x10088aaf 0x33 _L1e_csrc_CalcProTime
+ 0x10088ae2 0x1d _zPHY_ecsrc_PlmnGetPhaseMinTime
+ 0x10088aff 0xa2 _zPHY_ecsrc_PlmnBackupAfc
+ 0x10088ba1 0x1c _zPHY_ecsrc_PlmnResumeAgcAFc
+ 0x10088bbd 0xf _zPHY_ecsrc_PlmnPhasePro
+ 0x10088bcc 0x4a _zPHY_ecsrc_SearchPhaseCheck
+ 0x10088c16 0xa _zPHY_ecsrc_PlmnReadPhase
+ 0x10088c20 0xf _zPHY_ecsrc_PlmnPhaseShift
+ 0x10088c2f 0x3c _zPHY_ecsrc_PlmnPhaseContinue
+ 0x10088c6b 0x28 _zPHY_ecsrc_SearchDone
+ 0x10088c93 0x38 _zPHY_ecsrc_SendCellSearchReq
+ 0x10088ccb 0x9 _zPHY_ecsrc_RestartCellSearch
+ 0x10088cd4 0xd4 _zPHY_ecsrc_CtrlAbortICPProcess
+ 0x10088da8 0x35 _zPHY_ecsrc_BchCellInfoBak
+ 0x10088ddd 0x155 _l1e_SchedCsrcGetOverlapInfo
+ 0x10088f32 0x53 _zPHY_ecsrc_ProWriteBch2CsrDb
+ 0x10088f85 0x38 _zPHY_ecsrc_ProBackBchInfo
+ .text 0x10088fbd 0x379 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ 0x10088fbd 0x35 _CheckThread
+ 0x10088ff2 0x6b _NextStep
+ 0x1008905d 0x33 _RunProc
+ 0x10089090 0x12 _RunFun0
+ 0x100890a2 0x14 _RunFun0P1
+ 0x100890b6 0xc _RunFun1
+ 0x100890c2 0x15 _RunOpt
+ 0x100890d7 0x4c _RunWhile
+ 0x10089123 0x27 _RunEnd
+ 0x1008914a 0x1c _RunDo
+ 0x10089166 0x43 _RunWhile1
+ 0x100891a9 0x15 _RunLoop0
+ 0x100891be 0x15 _RunLoop1
+ 0x100891d3 0x25 _RunReturnIf
+ 0x100891f8 0x8b _DispatchStep
+ 0x10089283 0x26 _RunSync
+ 0x100892a9 0x4c _EventHandlerOnce
+ 0x100892f5 0x16 _EventHandler
+ 0x1008930b 0x2b _StartProc
+ .text 0x10089336 0x1ff T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ 0x10089336 0xc _L1e_SchedMbmsInit
+ 0x10089342 0x48 _L1e_SchedMbmsProcMsg
+ 0x1008938a 0x20 _L1e_SchedMbmsGenMbsfnSfBmp
+ 0x100893aa 0xe3 _L1e_SchedMbmsGenAllocSfBmp
+ 0x1008948d 0xd _L1e_SchedMbmsGetNextTimeInfo
+ 0x1008949a 0x31 _L1e_SchedMbmsProcMchRecv
+ 0x100894cb 0xb _L1e_SchedMbmsGetMbsfnInd
+ 0x100894d6 0xb _L1e_SchedMbmsSetMbsfnFlag
+ 0x100894e1 0xb _L1e_SchedMbmsSetMbmsFlag
+ 0x100894ec 0xd _L1e_SchedMbmsGetMbsfnFlag
+ 0x100894f9 0xf _L1e_SchedMbmsGetMbmsFlag
+ 0x10089508 0x2 _L1e_SchedMBmsGetMbsfnAllocNum
+ 0x1008950a 0xd _L1e_SchedMbmsGetAreaIndex
+ 0x10089517 0xd _L1e_SchedMbmsGetNonMbsfnLen
+ 0x10089524 0x11 _L1e_SchedMBmsGetConfigNum
+ .text 0x10089535 0x141c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x10089535 0x44 _zPHY_DrxPreSyncStartCtrl
+ 0x10089579 0x1f1 _zPHY_emc_ProDrxSchedFlow
+ 0x1008976a 0x97 _zPHY_emc_DrxInactivityTimerCtrl
+ 0x10089801 0x73 _zPHY_emc_DrxOnDurationTimerCtrl
+ 0x10089874 0x128 _zPHY_emc_DrxRttTimerAndDlHarqRetranTimerCtrl
+ 0x1008999c 0xf9 _zPHY_emc_DrxUlHarqCtrl
+ 0x10089a95 0x31 _zPHY_emc_ProDrxTpuEventSchedFlow
+ 0x10089ac6 0x88 _zPHY_emc_DrxCalcOndurationTimerStartTime
+ 0x10089b4e 0x64 _zPHY_emc_ProDrxCallBackFunction
+ 0x10089bb2 0x62 _zPHY_emc_RegOndurStartEvent
+ 0x10089c14 0x9e _zPHY_emc_RegShortDrxCycleEvent
+ 0x10089cb2 0x64 _zPHY_emc_CurSubFrDRXStateCtrl
+ 0x10089d16 0x1f _zPHY_emc_DRXCompare2Time
+ 0x10089d35 0x65 _zPHY_emc_OnDurationPre2SubFrm
+ 0x10089d9a 0x41 _zPHY_emc_InactivityPre2SubFrm
+ 0x10089ddb 0x9b _zPHY_emc_DlHarqPre2SubFrm
+ 0x10089e76 0x89 _zPHY_emc_UlHarqPhichPre2SubFrm
+ 0x10089eff 0x63 _zPHY_emc_Next2SubFrameDrxStateCtrl
+ 0x10089f62 0x93 _zPHY_emc_ProDrxInitial
+ 0x10089ff5 0xb _zPHY_emc_ChePwrCtrlFlg
+ 0x1008a000 0x90 _Ltel1_GetConnNearestGap
+ 0x1008a090 0x28d _zPHY_emc_DrxPresyncCalc
+ 0x1008a31d 0x4e _zPHY_emc_DrxStateCtrl
+ 0x1008a36b 0xaf _zPHY_emc_DrxCsi_OpenRXCtrl
+ 0x1008a41a 0xa1 _zPHY_emc_DRXProcLpCtrl
+ 0x1008a4bb 0x15a _zPHY_emc_DrxSpsLpCtrl
+ 0x1008a615 0x23 _zPHY_emc_GetDrxCloseRfState
+ 0x1008a638 0x162 _zPHY_emc_DRXCalOpenRFTime
+ 0x1008a79a 0x84 _zPHY_emc_DRXSleepJudge
+ 0x1008a81e 0x75 _zPHY_emc_DrxParallelSleepCtrl
+ 0x1008a893 0x9d _zPHY_emc_DrxParallelFlowLog
+ 0x1008a930 0x21 _zPHY_emc_DrxParallelFlowCtrl
+ .text 0x1008a951 0x3f8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x1008a951 0x7 _zPHY_emc_ProRadioLink_GetFIUpdateInd
+ 0x1008a958 0x7 _zPHY_emc_ProRadioLink_SetFIUpdateInd
+ 0x1008a95f 0x4e _zPHY_emc_ProRadioLink_ParaGetInDrx
+ 0x1008a9ad 0x1e _zPHY_emc_ProRadioLink_THInit
+ 0x1008a9cb 0x28 _zPHY_emc_ProRadioLink_THFilterInFI
+ 0x1008a9f3 0x60 _zPHY_emc_ProRadioLink_GetFinalTH
+ 0x1008aa53 0x52 _zPHY_emc_ProRadioLink_DrxFilter
+ 0x1008aaa5 0xa2 _zPHY_emc_ProRadioLink_DrxFlow
+ 0x1008ab47 0x60 _zPHY_emc_ProRadioLink_NoDrxFilter
+ 0x1008aba7 0x45 _zPHY_emc_ProRadioLink_StateSwitch
+ 0x1008abec 0xb7 _zPHY_emc_ProRadioLink_MainPro
+ 0x1008aca3 0xa6 _zPHY_emc_ProRadioLinkFlow
+ .text 0x1008ad49 0x2e13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x1008ad49 0x40 _zPHY_amt_Lte_PrintMsgLog
+ 0x1008ad89 0x4c _zPHY_AMT_Rfc_WriteRfFrontReg
+ 0x1008add5 0x66 _zPHY_AMT_erfc_SetCurrentBandAntGPIO
+ 0x1008ae3b 0xc1 _zPHY_AMT_erfc_SetCurrentBandPaModeGPIO
+ 0x1008aefc 0x17 _zPHY_AMT_RFC_110_RxOn
+ 0x1008af13 0x16 _zPHY_AMT_RFC_110_RxOff
+ 0x1008af29 0x17 _zPHY_AMT_RFC_110_TxOn
+ 0x1008af40 0x16 _zPHY_AMT_RFC_110_TxOff
+ 0x1008af56 0x16 _zPHY_AMT_RFC_120_RxOn
+ 0x1008af6c 0x16 _zPHY_AMT_RFC_120_RxOff
+ 0x1008af82 0x16 _zPHY_AMT_RFC_120_TxOn
+ 0x1008af98 0x16 _zPHY_AMT_RFC_120_TxOff
+ 0x1008afae 0x17 _zPHY_AMT_RFC_RXENABLE_On
+ 0x1008afc5 0x16 _zPHY_AMT_RFC_RXENABLE_Off
+ 0x1008afdb 0x17 _zPHY_AMT_RFC_TXENABLE_On
+ 0x1008aff2 0x16 _zPHY_AMT_RFC_TXENABLE_Off
+ 0x1008b008 0xf _zPHY_AMT_RFC_110_AfcSet
+ 0x1008b017 0x1 _zPHY_AMT_RFC_110_Xo_AfcSet
+ 0x1008b018 0x22 _zPHY_AMT_RFC_120_DCIQSet
+ 0x1008b03a 0x42 _zPHY_AMT_RFC_110_TempDacGet
+ 0x1008b07c 0x42 _zPHY_AMT_RFC_110_Xo_TempDacGet
+ 0x1008b0be 0x1d _zPHY_AMT_RFC_110_BandWidthModeGet
+ 0x1008b0db 0xa1 _zPHY_AMT_RFC_110_TxFreqSet
+ 0x1008b17c 0x35 _zPHY_AMT_RFC_110_RegTxCfg
+ 0x1008b1b1 0x24 _zPHY_AMT_RFC_120_RegTxCfg
+ 0x1008b1d5 0x36 _zPHY_AMT_RFC_110_RegRxCfg
+ 0x1008b20b 0x30 _zPHY_AMT_RFC_120_RegRxCfg
+ 0x1008b23b 0x28 _zPHY_AMT_RFC_ZTERF_TxApcSet
+ 0x1008b263 0x33 _zPHY_AMT_RFC_ZTERF_Tx2Idle
+ 0x1008b296 0x33 _zPHY_AMT_RFC_ZTERF_Rx2Idle
+ 0x1008b2c9 0x70 _zPHY_AMT_RFC_ZTERF_ToTx
+ 0x1008b339 0x70 _zPHY_AMT_RFC_ZTERF_ToRx
+ 0x1008b3a9 0x13 _zPHY_AMT_RFC_ZTERF_ToIdle
+ 0x1008b3bc 0xd _zPHY_amt_Lte_GetCarrierMode
+ 0x1008b3c9 0x1f _zPHY_amt_Lte_SetCarrierMode
+ 0x1008b3e8 0xdc _zPHY_amt_Lte_ChangeMode
+ 0x1008b4c4 0x15 _zPHY_amt_Lte_TxParaUpdate
+ 0x1008b4d9 0xc7 _zPHY_amt_Lte_ServCellFreqUpdate
+ 0x1008b5a0 0x135 _zPHY_amt_Lte_CellSyncProc
+ 0x1008b6d5 0xd1 _zPHY_amt_Lte_MprDeterm
+ 0x1008b7a6 0xa8 _zPHY_amt_Lte_RfcTxDataBaseSet
+ 0x1008b84e 0x48 _zPHY_amt_Lte_FDTTransTxVgaCtrl
+ 0x1008b896 0x226 _zPHY_amt_Lte_FDT_PAVGAVOL_Update
+ 0x1008babc 0x1f _zPHY_amt_Lte_FDTTxOffsetSet
+ 0x1008badb 0x12e _zPHY_amt_Lte_FDTRfcDataBaseSet
+ 0x1008bc09 0x1c _zPHY_amt_Lte_FDTRfcDataBaseClear
+ 0x1008bc25 0xe _zPHY_amt_Lte_FDTGetAgcGain
+ 0x1008bc33 0x7c _zPHY_amt_Lte_FDTSaveAgcGain
+ 0x1008bcaf 0xf6 _zPHY_amt_Lte_FDTControl
+ 0x1008bda5 0x2 _zPHY_amt_Lte_FDTGetAGC
+ 0x1008bda7 0xb1 _zPHY_amt_Lte_FDTStart
+ 0x1008be58 0x12 _zPHY_amt_Lte_FDTCellSyncProc
+ 0x1008be6a 0x20 _zPHY_amt_Lte_NSTCellSyncProc
+ 0x1008be8a 0x37 _zPHY_amt_Lte_NSTCellSyncSuccessRsp
+ 0x1008bec1 0x43 _zPHY_amt_Lte_NSTStartBler
+ 0x1008bf04 0xed _zPHY_amt_Lte_NSTGetBler
+ 0x1008bff1 0x32 _zPHY_amt_Lte_NSTStart
+ 0x1008c023 0x22 _zPHY_amt_Lte_NSTCirCfoStop
+ 0x1008c045 0x39 _zPHY_amt_Lte_NSTChangeFreq
+ 0x1008c07e 0x15b _zPHY_amt_Lte_NSTControl
+ 0x1008c1d9 0x13 _zPHY_amt_Lte_FSTCellSyncProc
+ 0x1008c1ec 0x89 _zPHY_amt_Lte_FSTStart
+ 0x1008c275 0xc9 _zPHY_amt_Lte_FSTRfcDataBaseSet
+ 0x1008c33e 0xda _zPHY_amt_Lte_FSTPowerUpdate
+ 0x1008c418 0xc0 _zPHY_amt_Lte_FSTSaveBlerAndRsrp
+ 0x1008c4d8 0xf6 _zPHY_amt_Lte_FSTControl
+ 0x1008c5ce 0x29 _zPHY_amt_Lte_Control
+ 0x1008c5f7 0x294 _zPHY_amt_Lte_Tx_Init_Power
+ 0x1008c88b 0x1a4 _zPHY_amt_Lte_Tx_Init_RFC
+ 0x1008ca2f 0x7a _zPHY_amt_Lte_Tx_Init_MC
+ 0x1008caa9 0x7a _zPHY_amt_Lte_Tx_Init_MC_Power
+ 0x1008cb23 0x6e _zPHY_amt_Lte_Close_Rfc
+ 0x1008cb91 0x51 _zPHY_amt_Lte_Tx_Close_MC
+ 0x1008cbe2 0x3c _zPHY_amt_Lte_TxFreq_RFC
+ 0x1008cc1e 0x1d _zPHY_amt_Lte_TxPaMode_RFC
+ 0x1008cc3b 0x4c _zPHY_amt_Lte_TxAPC_RFC
+ 0x1008cc87 0x3a _zPHY_amt_Lte_AFC_RFC
+ 0x1008ccc1 0x38 _zPHY_amt_Lte_XO_AFC_RFC
+ 0x1008ccf9 0x159 _zPHY_amt_Lte_Rx_Init_RFC
+ 0x1008ce52 0x1a _zPHY_amt_Lte_SetSyncTimer
+ 0x1008ce6c 0x4f _zPHY_amt_Lte_Cell_Search
+ 0x1008cebb 0xa3 _zPHY_amt_Lte_CommMsg_Stub
+ 0x1008cf5e 0x3d _zPHY_amt_Lte_CommMsg_Send
+ 0x1008cf9b 0x19f _zPHY_amt_Lte_DediMsg_Stub
+ 0x1008d13a 0x33 _zPHY_amt_Lte_DediMsg_Send
+ 0x1008d16d 0x26b _zPHY_amt_Lte_Sync_Process
+ 0x1008d3d8 0x74 _zPHY_amt_Lte_Rx_Init_MC
+ 0x1008d44c 0x71 _zPHY_amt_Lte_Rx_Close_MC
+ 0x1008d4bd 0x1b _zPHY_amt_Lte_RxFreq_RFC
+ 0x1008d4d8 0x2 _zPHY_amt_Lte_RxLNAMode_RFC
+ 0x1008d4da 0x2 _zPHY_amt_Lte_RxVGA_RFC
+ 0x1008d4dc 0x3c _zPHY_amt_Lte_Get_Rsrp
+ 0x1008d518 0xe _zPHY_amt_Lte_Get_TempDAC
+ 0x1008d526 0xe _zPHY_amt_Lte_Get_Xo_TempDAC
+ 0x1008d534 0xe _zPHY_amt_Lte_Set_AfcData
+ 0x1008d542 0x25 _zPHY_amt_Lte_Tx_DcOffset
+ 0x1008d567 0xbc _zPHY_amt_Lte_CellSearchResult
+ 0x1008d623 0x9b _zPHY_amt_Lte_CalcServCellAntAMT
+ 0x1008d6be 0x49 _zPHY_amt_Lte_UpCellSearchResult
+ 0x1008d707 0xf5 _zPHY_amt_Lte_RxAlways_Init
+ 0x1008d7fc 0xa _zPHY_amt_Lte_RxAlways_Close
+ 0x1008d806 0xe _zPHY_amt_Lte_RxAlwaysOpen_GetAgc
+ 0x1008d814 0x76 _zPHY_amt_Lte_RxAlwaysOpen
+ 0x1008d88a 0x2 _zPHY_amt_Lte_RxCwControl
+ 0x1008d88c 0x2d0 _zPHY_amtTool_ThreadEntry
+ .text 0x1008db5c 0x1b39 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ 0x1008db5c 0x4a _zPHY_erapc_InitialProc
+ 0x1008dba6 0x33 _zPHY_erapc_RaParamReset
+ 0x1008dbd9 0xa4 _zPHY_erapc_BiProc
+ 0x1008dc7d 0x106 _zPHY_erapc_RaResourceSelect
+ 0x1008dd83 0x164 _zPHY_erapc_RaResourceSelectFDD
+ 0x1008dee7 0x12d _zPHY_erapc_RaResourceSelectTDD
+ 0x1008e014 0x48 _zPHY_erapc_PreambleGroupSelect
+ 0x1008e05c 0x4f _zPHY_erapc_PreambleSelect
+ 0x1008e0ab 0x1d0 _zPHY_erapc_PreamCycShiftCalc
+ 0x1008e27b 0x12b _zPHY_erapc_KValueCalc
+ 0x1008e3a6 0xb8 _zPHY_erapc_PreambleTransPower
+ 0x1008e45e 0x6f _zPHY_erapc_PcmaxCalc
+ 0x1008e4cd 0x12a _zPHY_erapc_RarMacPduDecode
+ 0x1008e5f7 0x9c _zPHY_erapc_TpuEventDelete
+ 0x1008e693 0x42 _zPHY_erapc_RntiDelete
+ 0x1008e6d5 0x4b _zPHY_erapc_SetRapcState
+ 0x1008e720 0x43 _zPHY_erapc_PreamFormatDetermFDD
+ 0x1008e763 0x3e _zPHY_erapc_PreamFormatDetermTDD
+ 0x1008e7a1 0xff _zPHY_erapc_ResrConfigDetermFDD
+ 0x1008e8a0 0x1e1 _zPHY_erapc_ResrConfigDetermTDD
+ 0x1008ea81 0x8f _zPHY_erapc_NextAvailSFDetermTDD
+ 0x1008eb10 0x67 _zPHY_erapc_NPrbRaCalcTDD
+ 0x1008eb77 0x21 _zPHY_erapc_RandomNumGenerate
+ 0x1008eb98 0xdd _zPHY_erapc_RaRntiCalc
+ 0x1008ec75 0x8f _zPHY_erapc_SendRaCnfMsg
+ 0x1008ed04 0x152 _zPHY_erapc_ConfigSAD
+ 0x1008ee56 0x235 _zPHY_erapc_PreamTransPro
+ 0x1008f08b 0x7a _zPHY_erapc_RaRetransProc
+ 0x1008f105 0x150 _zPHY_erapc_RarDetectedProc
+ 0x1008f255 0x7b _zPHY_erapc_CRntiMsg4Proc
+ 0x1008f2d0 0x79 _zPHY_erapc_CcchSduMsg4Proc
+ 0x1008f349 0x55 _zPHY_erapc_AbortRaProc
+ 0x1008f39e 0x63 _zPHY_erapc_ContenStopProc
+ 0x1008f401 0x3d _zPHY_erapc_GetRapcTpuEventFlag
+ 0x1008f43e 0x37 _zPHY_erapc_SetRapcTpuEventFlag
+ 0x1008f475 0xae _zPHY_erapc_Format4PrachNumCalc
+ 0x1008f523 0xda _zPHY_erapc_GapConflictIndicate
+ 0x1008f5fd 0x94 _zPHY_erapc_Format4PrachNumCalc_ForUla
+ 0x1008f691 0x4 _zPHY_erapc_PrachAntennaSelect
+ .text 0x1008f695 0x5eb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x1008f695 0x283 _zPHY_emc_ProHandover2Module
+ 0x1008f918 0x35d _zPHY_emc_ProHandoverFlow
+ 0x1008fc75 0xb _zPHY_emc_InHandoverProc
+ .text 0x1008fc80 0xd01 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x1008fc80 0x1f9 _zPHY_emc_ProPagingFlow
+ 0x1008fe79 0xf8 _zPHY_L1e_DcxoDelayProc
+ 0x1008ff71 0x8 _zPHY_L1e_GetPreSyncValidInd
+ 0x1008ff79 0x8 _zPHY_L1e_SetPreSyncValidInd
+ 0x1008ff81 0x7 _zPHY_L1e_GetPreSyncAccNum
+ 0x1008ff88 0x39 _zPHY_emc_RegPageCallEvent
+ 0x1008ffc1 0x1f2 _zPHY_emc_CalPagingParam
+ 0x100901b3 0x103 _zPHY_emc_ProPagingCallBackFunction
+ 0x100902b6 0x31 _zPHY_emc_NxtSubFrmIsPage
+ 0x100902e7 0x16 _zPHY_emc_DrxPoLpCtrl
+ 0x100902fd 0x53 _L1e_Page_ReUpdatePoEvt
+ 0x10090350 0xd5 _L1e_SchedGetPreSyncSchdInfo
+ 0x10090425 0x4b _L1e_SchedPreSyncGetIdleWorkTimer
+ 0x10090470 0x8 _L1e_SchedReturnPreSyncWorkTime
+ 0x10090478 0x29 _L1e_SchedPreSyncGetAgcWorkTimer
+ 0x100904a1 0x1b _L1e_SchedPreSyncSetState
+ 0x100904bc 0x7 _L1e_SchedPreSyncGetState
+ 0x100904c3 0xc _L1e_SchedPreSyncSetWorkCnt
+ 0x100904cf 0x12 _L1e_SchedPreSyncIsWorkSn
+ 0x100904e1 0x12 _L1e_SchedPreSyncIsWorkInd
+ 0x100904f3 0x17 _L1e_SchedPreSyncGetRfOpenInd
+ 0x1009050a 0x29 _L1e_SchedPreSyncGetAgcWorkInd
+ 0x10090533 0x24 _L1e_SchedPreSyncGetFssWorkInd
+ 0x10090557 0x2d _L1e_SchedPreSyncGetCfoWorkInd
+ 0x10090584 0x8 _L1e_SchedPreSyncGetFssWorkCnt
+ 0x1009058c 0x8 _L1e_SchedPreSyncGetRfcWorkCnt
+ 0x10090594 0x8 _L1e_SchedPreSyncSetCfgSfnInd
+ 0x1009059c 0x8 _L1e_SchedPreSyncGetCfgSfnInd
+ 0x100905a4 0x8 _L1e_SchedPreSyncGetSfnBmp
+ 0x100905ac 0xa _L1e_SchedPreSyncGetPoMarkSn
+ 0x100905b6 0x2e _L1e_SchedPreSyncGetConnWorkTimer
+ 0x100905e4 0x75 _L1e_SchedPreSyncUpdateStep
+ 0x10090659 0x8 _L1e_SchedPreSyncSetStep
+ 0x10090661 0x8 _L1e_SchedPreSyncGetStep
+ 0x10090669 0x66 _L1e_DbgPreSyncCtrlInfo
+ 0x100906cf 0x7f _L1e_SchedPreSyncCtrl
+ 0x1009074e 0x13b _zPHY_emc_tRxCirPreSyncStart
+ 0x10090889 0xa1 _zPHY_emc_RfcRxColseOperationCheck
+ 0x1009092a 0x57 _zPHY_emc_ProLpcSleepSchd
+ .text 0x10090981 0x670 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_meas.o)
+ 0x10090981 0x71 _zPHY_ecscMeas_LogMeasConfigReq
+ 0x100909f2 0x35 _zPHY_ecscMeas_LogMeasBitMask
+ 0x10090a27 0x71 _zPHY_ecscMeas_LogMeasAgeThrold
+ 0x10090a98 0x5e _zPHY_ecscMeas_LogServCellResult
+ 0x10090af6 0x3f _zPHY_ecscMeas_LogPccMeasResult
+ 0x10090b35 0x78 _zPHY_ecscMeas_LogInterCellInfo
+ 0x10090bad 0x47 _zPHY_ecsrc_LogInterMeasInd
+ 0x10090bf4 0x23 _zPHY_ecscMeas_LogConnInterReport
+ 0x10090c17 0x4f _zPHY_ecscMeas_LogSccIntraMeasFilter
+ 0x10090c66 0x1a _zPHY_ecscMeas_LogSccIntraMeasFilter2
+ 0x10090c80 0x2e _zPHY_ecscMeas_LogIntraFilter2
+ 0x10090cae 0x19 _zPHY_ecscMeas_LogInterMeasFilter
+ 0x10090cc7 0x1f _zPHY_ecscMeas_LogIntraRSSI
+ 0x10090ce6 0x16 _zPHY_ecscMeas_LogUpdateInterReportFail1
+ 0x10090cfc 0x47 _zPHY_ecscMeas_LogFilterInterReport3
+ 0x10090d43 0x33 _zPHY_ecscMeas_LogPCCIntraMeasCell
+ 0x10090d76 0x43 _zPHY_ecscMeas_LogPCCIntraMeasCell4
+ 0x10090db9 0x21 _zPHY_ecscMeas_LogSCCIntraMeasCell
+ 0x10090dda 0x85 _zPHY_ecscMeas_LogSCCIntraMeasCell2
+ 0x10090e5f 0x76 _zPHY_ecscMeas_LogSCCIntraMeasCell4
+ 0x10090ed5 0x41 _zPHY_ecscMeas_LogFilterIntraDebug
+ 0x10090f16 0x53 _zPHY_ecscMeas_LogFilterIntraDebug2
+ 0x10090f69 0x4f _zPHY_ecscMeas_LogFilterInterDebug
+ 0x10090fb8 0x39 _zPHY_ecscMeas_LogCsrSnr
+ .text 0x10090ff1 0x6f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_dls.o)
+ 0x10090ff1 0x6f _L1e_LogDlDlsDciDetInfo
+ .text 0x10091060 0x9e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc.o)
+ 0x10091060 0x31 _zPHY_ecsc_LogMibReqCellInfo
+ 0x10091091 0x17 _zPHY_ecsc_LogEarfchTable
+ 0x100910a8 0x2f _zPHY_ecsc_LogTpuEventMark
+ 0x100910d7 0x59 _zPHY_ecsc_LogTimeOffsetPerfreq
+ 0x10091130 0x25 _L1e_csrc_LogDrxRefreshGapCnt
+ 0x10091155 0xa0 _L1e_csrc_LogCnnDrxSchedule
+ 0x100911f5 0x15 _zPHY_ecsc_LogRecv_REL_REQ
+ 0x1009120a 0x29 _zPHY_ecsc_LogRecv_StopInterSearchMeas
+ 0x10091233 0x15 _zPHY_ecsc_LogReportMEASErr
+ 0x10091248 0x48 _zPHY_ecsc_LogGAPTime
+ 0x10091290 0x2e _zPHY_ecsc_LogInterFreq
+ 0x100912be 0x2e _zPHY_ecsc_LogHandover
+ 0x100912ec 0x24 _zPHY_ecsc_LogRecv_MULM_IRAT_IDLE_PERIOD_REP_REQ
+ 0x10091310 0x20 _zPHY_ecsc_LogRecv_FREQ_LIST_CONFIG_REQ
+ 0x10091330 0x1d _zPHY_ecsc_LogRecv_IRAT_MEAS_CONFIG_REQ
+ 0x1009134d 0x1d _zPHY_ecsc_LogRecv_IRAT_MEASURE_REPORT_INT
+ 0x1009136a 0x15 _zPHY_ecsc_LogAbortGap
+ 0x1009137f 0x3f _zPHY_ecsc_LogREG_IRAT_GAP_CONFIG_DELAY_INT
+ 0x100913be 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_REQ
+ 0x100913ec 0x15 _zPHY_ecsc_LogTPUAdjusting
+ 0x10091401 0x2e _zPHY_ecsc_LogRecv_IRAT_GAP_CONFIG_DELAY_INT
+ 0x1009142f 0x15 _zPHY_ecsc_LogRecv_RF_START_DEAL_PRE2SFINT
+ 0x10091444 0x15 _zPHY_ecsc_LogRecv_RF_CLOSE_DEAL_PRE2SFINT
+ 0x10091459 0x15 _zPHY_ecsc_LogRecv_RESET_REQ
+ 0x1009146e 0x2a _zPHY_ecsc_LogRecv_CELL_SEARCH_REQ
+ 0x10091498 0x15 _zPHY_ecsc_LogRecv_ABORT_CELL_SEARCH_REQ
+ 0x100914ad 0x21 _zPHY_ecsc_LogRecv_COMMON_CONFIG_REQ
+ 0x100914ce 0x15 _zPHY_ecsc_LogRecv_ABORT_MEAS_REQ
+ 0x100914e3 0x73 _zPHY_ecsc_LogRecv_PI_START_REQ
+ 0x10091556 0x15 _zPHY_ecsc_LogRecv_ONE_FREQ_END_REQ
+ 0x1009156b 0x2e _zPHY_ecsc_LogRecv_IRAT_MEAS_GAP_CONFIG_REQ
+ 0x10091599 0x1d _zPHY_ecsc_LogRecv_FREQ_SCAN_REQ
+ 0x100915b6 0x2b _zPHY_ecsc_LogPhyModeConfig
+ 0x100915e1 0x27 _zPHY_ecsc_LogReportGap
+ 0x10091608 0x3c _L1e_CsrcDb_LogDelCell
+ 0x10091644 0x18 _L1e_csrc_LogReTimeOffset
+ 0x1009165c 0x66 _zPHY_ecscDb_LogCellToDB
+ 0x100916c2 0x3d _zPHY_ecscDb_LogRefreshDB
+ 0x100916ff 0x16 _zPHY_ecscDb_LogUpdateBoundary
+ 0x10091715 0x1e _zPHY_ecsc_LogChangeMeasPeriodIdle
+ 0x10091733 0x39 _zPHY_ecsc_Log_Earfcn_BandInfo
+ 0x1009176c 0x22 _zPHY_ecscMeas_LogSrvCellReslt
+ 0x1009178e 0x1f _zPHY_ecsc_LogStandardOutput
+ 0x100917ad 0x15 _zPHY_ecsc_LogMeasPeriodChgDelay
+ 0x100917c2 0x1d _zPHY_ecsc_LogSibOrRapcConflict
+ 0x100917df 0x1d _zPHY_ecsc_LogSubFreqOffset
+ 0x100917fc 0x16 _zPHY_ecsc_LogEarfcnError
+ 0x10091812 0x76 _L1e_csrc_LogShortDrxInfo
+ 0x10091888 0x15 _L1e_csrc_LogTempComp
+ 0x1009189d 0x15 _L1e_csrc_LogTempRead
+ 0x100918b2 0x1f _L1e_csrc_LogGetFreqOffset
+ 0x100918d1 0x1d _L1e_csrc_LogSetDisableAfcReloadFlag
+ 0x100918ee 0x25 _L1e_csrc_LogC0CaliUpDate
+ 0x10091913 0x21 _L1e_csrc_LogC0CaliPeriod
+ 0x10091934 0x22 _L1e_csrc_LogC0CaliEvalue
+ 0x10091956 0x2f _L1e_csrc_LogC0Update
+ 0x10091985 0x1e _L1e_csrc_LogC0Debug
+ 0x100919a3 0x27 _L1e_csrc_LogC0CalRsrp
+ 0x100919ca 0x1f _L1e_csrc_LogC0CalAfc
+ 0x100919e9 0x21 _L1e_csrc_LogC0UtcTimeExp
+ 0x10091a0a 0x15 _L1e_csrc_LogC0CaliRestart
+ 0x10091a1f 0x21 _L1e_csrc_LogNewUtcError
+ .text 0x10091a40 0x276 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm_normal.o)
+ 0x10091a40 0x4c _zPHY_ecsm_LogMeasHwInfo
+ 0x10091a8c 0x79 _zPHY_ecsmNormal_LogUpdateRes
+ 0x10091b05 0x16 _zPHY_ecsrm_BuffLogSlaveMaxBdySub
+ 0x10091b1b 0x22 _zPHY_ecsrm_LogSetMeasAge
+ 0x10091b3d 0x19 _zPHY_ecsrm_LogBuffFbRelatn
+ 0x10091b56 0x17 _zPHY_ecsrm_LogMeasStartSubFrame
+ 0x10091b6d 0x2b _zPHY_ecsrm_LogBuffCellPara
+ 0x10091b98 0x3f _zPHY_ecsrm_LogBuffCommPara
+ 0x10091bd7 0x2d _zPHY_ecsrm_LogMeasResultRead
+ 0x10091c04 0x18 _zPHY_ecsrm_LogBuffMulmsubf
+ 0x10091c1c 0x29 _zPHY_ecsrm_LogBuffSortCell
+ 0x10091c45 0x27 _zPHY_ecsrm_LogBuffBdyCell
+ 0x10091c6c 0x27 _zPHY_ecsrm_LogBuffwait
+ 0x10091c93 0x23 _zPHY_ecsrm_LogBuffMeasConfig
+ .text 0x10091cb6 0x378 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrc_cs.o)
+ 0x10091cb6 0x15 _zPHY_ecsccs_LogRSStart
+ 0x10091ccb 0x27 _zPHY_ecsccs_LogSearchReq
+ 0x10091cf2 0x41 _zPHY_ecsccs_LogCellInfo
+ 0x10091d33 0x1a _zPHY_ecsc_LogRecv_PBCH
+ 0x10091d4d 0x24 _zPHY_ecsccs_LogMeasStart
+ 0x10091d71 0x26 _zPHY_ecsccs_LogSendTPUAdjust
+ 0x10091d97 0x30 _zPHY_ecsccs_LogCellRank
+ 0x10091dc7 0x1d _zPHY_ecsccs_LogNoAppointedCell
+ 0x10091de4 0x42 _zPHY_ecsccs_LogICPReportResultRIGHT
+ 0x10091e26 0x18 _zPHY_ecsccs_LogIcpBchCell
+ 0x10091e3e 0x15 _zPHY_ecsccs_LogNoCell
+ 0x10091e53 0x44 _zPHY_ecsccs_LogStartResumeSrv
+ 0x10091e97 0x4b _zPHY_ecsccs_LogNewPlmnRS_ReportStatus
+ 0x10091ee2 0x29 _zPHY_ecsccs_LogNewPlmnRS_SearchFinished
+ 0x10091f0b 0x1f _zPHY_ecsccs_LogNewPlmnRS_MeasFinished
+ 0x10091f2a 0x3c _zPHY_ecsccs_LogResumeServBCHBoundry
+ 0x10091f66 0x26 _zPHY_ecsccs_LogCurTime2PiTime
+ 0x10091f8c 0x30 _zPHY_ecsccs_LogReg_PLMN_PERIODICAL_TPU_INT
+ 0x10091fbc 0x21 _zPHY_ecsccs_LogRecv_PLMN_SEARCH_TIME_EVENT
+ 0x10091fdd 0x51 _zPHY_ecsccs_LogWriteBch2CsrDb
+ .text 0x1009202e 0x198 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_dl_rx.o)
+ 0x1009202e 0x29 _L1e_LogDlRxMbsfnCirInfo
+ 0x10092057 0x52 _L1e_LogRxMbmsCirAreaInfo
+ 0x100920a9 0x9f _L1e_LogRxCirDataInfo
+ 0x10092148 0x42 _L1e_LogRxMbmsCirSearchInfo
+ 0x1009218a 0x22 _L1e_LogRxBetaInfo
+ 0x100921ac 0x1a _L1e_LogRxCfoCfgInfo
+ .text 0x100921c6 0xb03 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_mulm.o)
+ 0x100921c6 0x17 _zPHY_emulm_LogCsrSlaveStateChange
+ 0x100921dd 0x17 _zPHY_emulm_LogCsrSlaveSYNStateChange
+ 0x100921f4 0x20 _zPHY_emulm_LogCsrcGapStartOffset
+ 0x10092214 0x2c _zPHY_emulm_LogCsrcFreeTimeRep
+ 0x10092240 0x17 _zPHY_emulm_LogCsrcSetModeReq
+ 0x10092257 0x17 _zPHY_emulm_LogCsrcMeasSche
+ 0x1009226e 0x26 _zPHY_emulm_LogCsrcMeasReportProct
+ 0x10092294 0x2f _zPHY_emulm_LogCsrcMeasReportInt
+ 0x100922c3 0x16 _zPHY_emulm_LogMeasNoCell
+ 0x100922d9 0x18 _zPHY_emulm_LogMeasCell
+ 0x100922f1 0x19 _zPHY_emulm_LogMeasNoCellReport
+ 0x1009230a 0x73 _zPHY_emulm_LogMeasRight
+ 0x1009237d 0x16 _zPHY_emulm_LogASynSearch
+ 0x10092393 0x2a _zPHY_emulm_LogGapStartOffset
+ 0x100923bd 0x17 _zPHY_emulm_LogSubFrameOnOff
+ 0x100923d4 0x2a _zPHY_emulm_LogGapEndOffset
+ 0x100923fe 0x56 _zPHY_emulm_LogRegCsrIratGapStart
+ 0x10092454 0x94 _zPHY_emulm_LogRegCsrGapEnd
+ 0x100924e8 0x56 _zPHY_emulm_LogRegCsrRfClose
+ 0x1009253e 0x17 _zPHY_emulm_LogBlackList
+ 0x10092555 0x1c _zPHY_emulm_LogRemainTime
+ 0x10092571 0x20 _zPHY_emulm_LogSynInterSearchMeas
+ 0x10092591 0x22 _zPHY_emulm_LogRegIratPlmnMeas
+ 0x100925b3 0x22 _zPHY_emulm_LogRegSlaveAbortGap
+ 0x100925d5 0x1d _zPHY_emulm_LogIratAbortGap
+ 0x100925f2 0x1d _zPHY_emulm_LogIratMeasDone
+ 0x1009260f 0x1e _zPHY_emulm_LogGapPosition
+ 0x1009262d 0x4d _zPHY_emulm_LogGapTime
+ 0x1009267a 0x4d _zPHY_emulm_LogGapTime1
+ 0x100926c7 0x4d _zPHY_emulm_LogGapTime2
+ 0x10092714 0x17 _zPHY_emulm_LogPbchInGap
+ 0x1009272b 0x28 _zPHY_emulm_LogEnRfcEventTable
+ 0x10092753 0x54 _zPHY_emulm_Log6MSRfcEventTableInGap
+ 0x100927a7 0x39 _zPHY_emulm_LogrRfStartDeal
+ 0x100927e0 0x39 _zPHY_emulm_LogrRfEndDeal
+ 0x10092819 0x36 _zPHY_emulm_LogRefreshDataBase1
+ 0x1009284f 0x18 _zPHY_emulm_LogtpuAdjust
+ 0x10092867 0x18 _zPHY_emulm_LogtpuCantAdjust
+ 0x1009287f 0x29 _zPHY_emulm_LogPssAdjust
+ 0x100928a8 0x15 _zPHY_emulm_LogRecvSlaveAbortGap
+ 0x100928bd 0x15 _zPHY_emulm_LogRecvCsrAbortGap
+ 0x100928d2 0x15 _zPHY_emulm_LogRecvCsrTpuIratGap
+ 0x100928e7 0x15 _zPHY_emulm_LogRecvCsrTpuIratGapStart
+ 0x100928fc 0x65 _zPHY_emulm_LogSlaveMeasureFlow
+ 0x10092961 0x15 _zPHY_emulm_LogRecvCsrTpuIratPlmnMeas
+ 0x10092976 0x15 _zPHY_emulm_LogRecvCsrTpuUpdateCounter
+ 0x1009298b 0x15 _zPHY_emulm_LogCsrcRecvGapEndOffsetCfg
+ 0x100929a0 0x38 _zPHY_emulm_LogCsrcGatValidCellFbInfo
+ 0x100929d8 0x21 _zPHY_emulm_LogCsrcTimeDelayIntEvent
+ 0x100929f9 0x2c _zPHY_emulm_LogCsrcAfterAdjTpu
+ 0x10092a25 0x31 _L1e_Mulm_LogNeedSearchAndMeas
+ 0x10092a56 0x19 _zPHY_emulm_LogCsrcStartEarfcnInfo
+ 0x10092a6f 0x2f _zPHY_emulm_LogCsrcEndEarfcnInfo
+ 0x10092a9e 0x67 _zPHY_emulm_LogCsrcGapAndSssInfo
+ 0x10092b05 0x6a _zPHY_emulm_LogCsrcHbTimeInfo
+ 0x10092b6f 0x2c _zPHY_emulm_LogCsrcSssBufferAndGap
+ 0x10092b9b 0x21 _zPHY_emulm_LogCsrcAgcStart
+ 0x10092bbc 0x39 _zPHY_emulm_LogCsrcSlaveSssProcessInfo
+ 0x10092bf5 0x43 _zPHY_emulm_LogBuffCheckOpenTimePeriod
+ 0x10092c38 0x21 _zPHY_emulm_LogGapCoverBuffCheck
+ 0x10092c59 0x1a _zPHY_emulm_LogMeasFilter
+ 0x10092c73 0x16 _zPHY_emulm_LogUpdateReportFail
+ 0x10092c89 0x26 _zPHY_emulm_LogSetFilterFact
+ 0x10092caf 0x1a _zPHY_emulm_LogGetFilterFact
+ .text 0x10092cc9 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_cmn_mbms.o)
+ 0x10092cc9 0x91 _L1e_logCmnMbmsMbsfnSubfListInfo
+ 0x10092d5a 0x8f _L1e_LogCmnMbmsMbsfnAllocInfo
+ .text 0x10092de9 0x10f2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrs.o)
+ 0x10092de9 0x35 _zPHY_ecsrc_LogSlaveSearchMode
+ 0x10092e1e 0x34 _zPHY_ecsrc_LogRecvUpdateCounterCnf
+ 0x10092e52 0x64 _zPHY_ecsrc_LogPssTpuAdjust3
+ 0x10092eb6 0x26 _zPHY_ecsrc_LogModifyRfCfgInfo
+ 0x10092edc 0x85 _zPHY_ecsrc_LogIsRfOpen
+ 0x10092f61 0x4f _zPHY_ecsrs_LogCommonInfor
+ 0x10092fb0 0x36 _zPHY_ecsrs_LogInterFreqChange
+ 0x10092fe6 0x2e _zPHY_ecsrs_LogGetHwConfigMode
+ 0x10093014 0x34 _zPHY_ecsrs_LogGetReadAndConfigIndex
+ 0x10093048 0x18 _zPHY_ecsrs_LogTFConfirmSearchMode
+ 0x10093060 0x19 _zPHY_ecsrs_LogGetSubTime
+ 0x10093079 0x16 _zPHY_ecsrs_LogSubFrameOnOff
+ 0x1009308f 0xba _zPHY_ecsrs_LogCsPssPro
+ 0x10093149 0x48 _zPHY_ecsrs_LogGetPssStartTime
+ 0x10093191 0x14 _zPHY_ecsrs_LogCsCfoProcEnd
+ 0x100931a5 0x9a _zPHY_ecsrs_LogCsSssPro
+ 0x1009323f 0x3e _zPHY_ecsrpss_LogAdjustPssStartTime
+ 0x1009327d 0x1c _zPHY_ecsrpss_LogUrfcnFreqIdx
+ 0x10093299 0x57 _zPHY_ecsrpss_LogSearchResult
+ 0x100932f0 0x5f _zPHY_ecsrpss_LogPssDb
+ 0x1009334f 0x1b _zPHY_ecsrpss_LogSendRfcOffset
+ 0x1009336a 0x2a _zPHY_ecsrpss_LogCalRedoCfoBoundary
+ 0x10093394 0x2a _zPHY_ecsrpss_LogFilterFinger
+ 0x100933be 0x4d _zPHY_ecsrSss_LogStartFinger
+ 0x1009340b 0x3c _zPHY_ecsrSss_LogStartTime
+ 0x10093447 0x4f _zPHY_ecsrSss_LogStartFingerAll
+ 0x10093496 0x4a _zPHY_ecsrSss_LogSLAVE_HWStart
+ 0x100934e0 0x22 _zPHY_ecsrSss_LogGetRfcEnableInfo
+ 0x10093502 0x27 _zPHY_ecsrSss_LogReadFlagInfor
+ 0x10093529 0xc5 _zPHY_ecsrSss_LogThreshold
+ 0x100935ee 0x5d _zPHY_ecsrSss_LogResultInfo
+ 0x1009364b 0x65 _zPHY_ecsrSss_LogSssFingerReorder
+ 0x100936b0 0x18 _zPHY_ecsrSss_LogAdjustSssFddProc
+ 0x100936c8 0x2e _zPHY_ecsrSss_LogSssState
+ 0x100936f6 0x62 _zPHY_ecsrSss_LogStartFingerAfterSort
+ 0x10093758 0x14 _zPHY_ecsrSss_LogGetSssStartInfo
+ 0x1009376c 0x27 _zPHY_ecsrCfo_LogFreqOffset
+ 0x10093793 0x6a _zPHY_ecsrCfo_LogSLAVE_HWStart
+ 0x100937fd 0x28 _zPHY_ecsrCfo_LogCfoResultMerge
+ 0x10093825 0x41 _zPHY_ecsrIc_LogCellFlag
+ 0x10093866 0x7e _zPHY_ecsrIc_LogCoverInfo
+ 0x100938e4 0x60 _zPHY_ecsrIc_LogCellInfo
+ 0x10093944 0xa9 _zPHY_ecsrs_LogCfgIcFifo
+ 0x100939ed 0x191 _zPHY_ecsrs_LogCfgIc
+ 0x10093b7e 0x136 _zPHY_ecsrs_LogCfgPssHw
+ 0x10093cb4 0x5f _zPHY_ecsrs_LogCfgCfoHw
+ 0x10093d13 0x138 _zPHY_ecsrs_LogCfgSssHw
+ 0x10093e4b 0x20 _zPHY_ecsrSss_LogCheckCfoValid
+ 0x10093e6b 0x2d _L1e_csrs_LogSetFtErrorList
+ 0x10093e98 0x25 _L1e_csrs_LogSetFreqOffsetAge
+ 0x10093ebd 0x1e _L1e_csrs_LogGetFreqOffset
+ .text 0x10093edb 0x239 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_csrm.o)
+ 0x10093edb 0x30 _zPHY_ecsm_LogBlackCell
+ 0x10093f0b 0xba _zPHY_ecsm_LogRfcOpenTime
+ 0x10093fc5 0x4d _zPHY_ecsm_LogRfcOpenTimeFddIdle
+ 0x10094012 0x54 _zPHY_ecsm_LogTDDRfcEventTab
+ 0x10094066 0x14 _zPHY_ecsm_LogRecv_RESET_REQ
+ 0x1009407a 0x32 _zPHY_ecsm_LogMeasStart
+ 0x100940ac 0x14 _zPHY_ecsm_Logrec_MEASRESET
+ 0x100940c0 0x16 _zPHY_ecsm_LogRecv_UnknownMsg
+ 0x100940d6 0x1e _zPHY_ecsm_Buff_LogRfcOpenTime
+ 0x100940f4 0x20 _zPHY_ecsm_LogRfcEventTablength
+ .text 0x10094114 0x3c8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_func.o)
+ 0x10094114 0xc _zPHY_GetUINT32BitsField
+ 0x10094120 0x27 _zPHY_GetUINT64BitsField
+ 0x10094147 0x1f _zPHY_GetUINT16DivCeilValue
+ 0x10094166 0x22 _zPHY_GetUINT32DivCeilValue
+ 0x10094188 0x28 _zPHY_GetSINT16DivFloorValue
+ 0x100941b0 0x2e _zPHY_GetSINT32DivFloorValue
+ 0x100941de 0x16 _zPHY_BinarySearch
+ 0x100941f4 0x132 _zPHY_Pow2
+ 0x10094326 0x5b _zPHY_Fixpoint2Float
+ 0x10094381 0x88 _zPHY_Float2Fixpoint
+ 0x10094409 0x6c _zPHY_DivRet2Fixpoint7510
+ 0x10094475 0x57 _zPHY_DivRet2Fixpoint
+ 0x100944cc 0x10 _zPHY_LteaDelay
+ .text 0x100944dc 0x60 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x100944dc 0x57 _zPHY_setRxMaskFlag
+ 0x10094533 0x9 _zPHY_getRxMaskFlag
+ .text 0x1009453c 0x95 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x1009453c 0x37 _L1l_CmnAssert
+ 0x10094573 0x5a _zPHY_RecvUnknownMsg
+ 0x100945cd 0x4 _zPHY_create_handler
+ .text 0x100945d1 0x28c6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ 0x100945d1 0x2f _zPHY_eula_PucchSrsRelease
+ 0x10094600 0x6d _zPHY_eula_SetSrsScale
+ 0x1009466d 0x58 _zPHY_eula_LtxParas_QDivNRsZcSrs
+ 0x100946c5 0x31f _zPHY_eula_UpdataSrsBGParas_Cell
+ 0x100949e4 0xd0 _zPHY_eula_UpdataSrsBGParas_APSfOffset
+ 0x10094ab4 0x19d _zPHY_eula_UpdataSrsBGParas_APTiming
+ 0x10094c51 0x159 _zPHY_eula_UpdataSrsBGParas_APParaCalc_PTS
+ 0x10094daa 0x29b _zPHY_eula_UpdataSrsBGParas_APParaCalc
+ 0x10095045 0x3d _zPHY_eula_UpdataSrsBGParas_APParaAssign
+ 0x10095082 0x62 _zPHY_eula_UpdataSrsBGParas_AP
+ 0x100950e4 0x2f6 _zPHY_eula_UpdataSrsBGParas_PTiming
+ 0x100953da 0x15a _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc_PTS
+ 0x10095534 0x219 _zPHY_eula_UpdataSrsBGParas_PNonHopParaCalc
+ 0x1009574d 0x118 _zPHY_eula_UpdataSrsBGParas_PHopParaCalc_PTS
+ 0x10095865 0x27d _zPHY_eula_UpdataSrsBGParas_PHopParaCalc
+ 0x10095ae2 0x6d _zPHY_eula_UpdataSrsBGParas_P
+ 0x10095b4f 0xb2 _zPHY_eula_UpdataSrsBGParas
+ 0x10095c01 0xe4 _zPHY_eula_CommSrsProc
+ 0x10095ce5 0x22e _zPHY_eula_ScheApSrs
+ 0x10095f13 0x27 _zPHY_eula_WipeSrsInRarBasedPusch
+ 0x10095f3a 0x80 _zPHY_eula_DetermineSrsCellSpecStateInPusch
+ 0x10095fba 0xbe _zPHY_eula_ProcConflictOfSrsAndPucchPusch_OneCell
+ 0x10096078 0x50 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell
+ 0x100960c8 0x4d _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschScell
+ 0x10096115 0x86 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_PuschScell
+ 0x1009619b 0x120 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch
+ 0x100962bb 0x136 _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_Pucch_PuschScell
+ 0x100963f1 0x12e _zPHY_eula_ProcConflictOfSrsAndPucchPusch_CA_PuschPcell_Pucch_PuschScell
+ 0x1009651f 0x2 _zPHY_eula_ProcConflictOfSrsAndPucchPusch
+ 0x10096521 0x5e _zPHY_eula_ScheSrsInPusch_AntMapping
+ 0x1009657f 0x7d _zPHY_eula_ScheSrsInPusch
+ 0x100965fc 0xb1 _zPHY_eula_ProcConflictOfSrsAndPucch_OneCell
+ 0x100966ad 0x2 _zPHY_eula_ProcConflictOfSrsAndPucch
+ 0x100966af 0x1d _zPHY_eula_ProcConflictOfSrsAndDrx
+ 0x100966cc 0x4b _zPHY_eula_ScheSrsInNonPusch
+ 0x10096717 0x4e _zPHY_eula_ProcSrsInDurationMode0
+ 0x10096765 0x4c _zPHY_eula_GetPtsState
+ 0x100967b1 0xbe _zPHY_eula_CalcApSrsParas
+ 0x1009686f 0xbe _zPHY_eula_CalcPNonHopSrsParas
+ 0x1009692d 0x389 _zPHY_eula_CalcPHopSrsParas
+ 0x10096cb6 0x46 _zPHY_eula_CalcSrsParas
+ 0x10096cfc 0x70 _zPHY_eula_InitSrsDB
+ 0x10096d6c 0x4e _zPHY_eula_SrsSrcRelease
+ 0x10096dba 0x18 _zPHY_eula_ClearApSrsSche
+ 0x10096dd2 0xbc _zPHY_eula_CalcnSrs
+ 0x10096e8e 0x9 _zPHY_eula_SrsAntennaSelect
+ .text 0x10096e97 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x10096e97 0x53 _zPHY_edla_GetPhichGrpNum
+ 0x10096eea 0xb _zPHY_edla_GetPhichRegNum
+ 0x10096ef5 0x10b _zPHY_edla_GetNextSubFrmPhichInfo
+ 0x10097000 0x100 _zPHY_edla_UpdateIphichInfo
+ 0x10097100 0x10 _zPHY_edla_GetPhichInfo
+ 0x10097110 0xc9 _zPHY_edla_GetPerPhichSeq
+ 0x100971d9 0x95 _zPHY_edla_GetPerTBPhichSeq
+ 0x1009726e 0x11 _zPHY_edla_GetPhichSeq
+ 0x1009727f 0x23 _zPHY_edla_GetHichSubFreq
+ 0x100972a2 0xbb _zPHY_edla_PhichProc
+ 0x1009735d 0x45 _zPHY_edla_UpdatePhichInfo
+ 0x100973a2 0xb _zPHY_edla_HiValidJudgment
+ .text 0x100973ad 0x1540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x100973ad 0x5d _zPHY_edfe_SupCommonCalAGC
+ 0x1009740a 0x72 _zPHY_edfe_SupFastAGC
+ 0x1009747c 0xd9 _zPHY_edfe_SupNotSyncAGC
+ 0x10097555 0x295 _zPHY_edfe_SupNotSyncAGCAnt0And1
+ 0x100977ea 0x18 _zPHY_edfe_GetAgcReloadVal
+ 0x10097802 0x11 _zPHY_edfe_ConfigAgcReloadVal
+ 0x10097813 0x16 _zPHY_edfe_ACP405AgcGainConfig
+ 0x10097829 0xac _zPHY_edfe_SupAGCLostLockMethod
+ 0x100978d5 0x3f _zPHY_edfe_InitAgcPara
+ 0x10097914 0x1a _zPHY_edfe_ResetAgcCoverJudgePara
+ 0x1009792e 0x24 _zPHY_edfe_InitAgcDagcGain
+ 0x10097952 0x155 _zPHY_edfe_JudgeAgcCoverOpt
+ 0x10097aa7 0x67 _zPHY_edfe_CalcAGCForBandChange
+ 0x10097b0e 0xb8 _zPHY_edfe_GetNextAGCInitGain
+ 0x10097bc6 0x9b _zPHY_edfe_CalcAGCNewMethodAnt
+ 0x10097c61 0x9d _zPHY_edfe_CalcAGCGainNewMethod
+ 0x10097cfe 0x139 _zPHY_edfe_SupHandleAGCOpt
+ 0x10097e37 0x51 _zPHY_edfe_FindOldestPosInAgcGainDB
+ 0x10097e88 0x9 _zPHY_edfe_SupResetAGCLoopOpt
+ 0x10097e91 0xb7 _zPHY_edfe_NotSyncToSyncSetAgc
+ 0x10097f48 0x3d _zPHY_edfe_SyncToNotSyncSetAgc
+ 0x10097f85 0x10b _zPHY_edfe_UpdateSCCAGC
+ 0x10098090 0x12 _zPHY_edfe_CompAgcDBTimeInfo
+ 0x100980a2 0xc7 _zPHY_edfe_IratHandoverAfcManage
+ 0x10098169 0x71 _zPHY_edfe_SupSaveSlaveAfcCtrl
+ 0x100981da 0xfd _zPHY_edfe_IratHandoverCordicManage
+ 0x100982d7 0x8e _zPHY_edfe_IratCordicManage
+ 0x10098365 0x6e _zPHY_edfe_SupSaveSlaveCordicCtrl
+ 0x100983d3 0x77 _zPHY_edfe_FSNewAgcIntHandle
+ 0x1009844a 0x72 _zPHY_edfe_InitSubFramePwrDB
+ 0x100984bc 0x263 _zPHY_edfe_SupSemiStaticAgcNew
+ 0x1009871f 0x26 _zPHY_edfe_MbsfnAgcDbInit
+ 0x10098745 0xc _zPHY_edfe_MbsfnAgcParaConfig
+ 0x10098751 0x9f _zPHY_edfe_SupCalMbsfnRegionAgc
+ 0x100987f0 0xb6 _zPHY_edfe_SupHandleMbsfnAGC
+ 0x100988a6 0x2f _zPHY_edfe_NewMbsfnAGCGainInit
+ 0x100988d5 0x1 _zPHY_edfe_MbsfnAgcCoverJudge
+ 0x100988d6 0x17 _zPHY_edfe_MbsfnAgcGainConfig
+ .text 0x100988ed 0x251 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ 0x100988ed 0x1ae _zPHY_eulpc_SrsPowCalc
+ 0x10098a9b 0xa3 _zPHY_eulpc_SrsPowCtrl
+ .text 0x10098b3e 0x1173 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ 0x10098b3e 0x1 _zPHY_euls_L_Entry
+ 0x10098b3f 0x34c _zPHY_euls_Entry
+ 0x10098e8b 0x2cc _zPHY_euls_TPU_INT1_RARGrantProcess
+ 0x10099157 0x2f8 _zPHY_euls_TPU_INT1_DCIProcess
+ 0x1009944f 0x435 _zPHY_euls_TPU_INT1_Step1_process
+ 0x10099884 0x191 _zPHY_euls_TPU_INT1_Step2_process
+ 0x10099a15 0x8b _zPHY_euls_GetDediCfgParas
+ 0x10099aa0 0x7f _zPHY_euls_GetSCellCfgParas
+ 0x10099b1f 0x80 _zPHY_euls_GetCommCfgParas
+ 0x10099b9f 0x10e _zPHY_euls_GetHandoverCfgParas
+ 0x10099cad 0x4 _zPHY_euls_PuschAntennaSelect
+ .text 0x10099cb1 0x2362 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x10099cb1 0x2c _L1e_FS_SwReset
+ 0x10099cdd 0x16 _L1e_FS_Init
+ 0x10099cf3 0x32 _L1e_FS_FreqScanEnRfcNotSyncTable
+ 0x10099d25 0xb3 _L1e_FS_HandleFreqscanAddSearchResult
+ 0x10099dd8 0x9c _L1e_FS_CalcSssAgcGainCompen
+ 0x10099e74 0xec _L1e_FS_FreqScanAddSearchResultSort
+ 0x10099f60 0x30 _L1e_FS_SetFSResult
+ 0x10099f90 0x110 _L1e_FS_FindFSEarfcnToReport
+ 0x1009a0a0 0x34 _L1e_FS_FindEarfcnForSearch
+ 0x1009a0d4 0x36 _L1e_FS_SendFsCnf
+ 0x1009a10a 0x8f _L1e_FS_BufForSearch
+ 0x1009a199 0x86 _L1e_Fs_CreateList_Band38_Bak
+ 0x1009a21f 0x6c _L1e_Fs_CreateListBak
+ 0x1009a28b 0x6a _L1e_Fs_IsFreqPointValid
+ 0x1009a2f5 0x36 _L1e_Fs_MaxPeakSetZero
+ 0x1009a32b 0x2a _L1e_Fs_GetMaxValue
+ 0x1009a355 0x28 _L1e_Fs_GetMinValue
+ 0x1009a37d 0x1c _L1e_FS_LogNumPrint
+ 0x1009a399 0x33 _L1e_Fs_SetProfileInfo
+ 0x1009a3cc 0x34 _L1e_Fs_DelList
+ 0x1009a400 0x6 _L1e_FS_ClearPssResultList
+ 0x1009a406 0x6 _L1e_FS_ClearMeanPowerResultList
+ 0x1009a40c 0xe _L1e_FS_SetRedoInfo
+ 0x1009a41a 0xf4 _L1e_FS_GetAllGainProfileInfo
+ 0x1009a50e 0x63 _L1e_FS_GetAllProfileInfo
+ 0x1009a571 0xcf _L1e_Fs_GetAllValidFreqPoint
+ 0x1009a640 0x33 _L1e_FS_SetBandInfo
+ 0x1009a673 0xf _L1e_FS_SetSpecialBandInfo
+ 0x1009a682 0x5c _L1e_FS_SetOverLapFreqBand
+ 0x1009a6de 0x1bc _L1e_FS_GenFreqBand
+ 0x1009a89a 0x1e _L1e_FS_CfgRfcNotSyncTable
+ 0x1009a8b8 0x51 _L1e_FS_ReqMsgHandle
+ 0x1009a909 0x13 _L1e_FS_SetFreqPoint
+ 0x1009a91c 0x74 _L1e_FS_InsertPssResult
+ 0x1009a990 0xe3 _L1e_FS_SetIniCsrInfo
+ 0x1009aa73 0xdf _L1e_FS_SetFsRslt
+ 0x1009ab52 0x8b _L1e_FS_ResultSort
+ 0x1009abdd 0x1b _L1e_FS_PlmnPeriodTpuInPro
+ 0x1009abf8 0xd2 _L1e_FS_SetDisctRslt
+ 0x1009acca 0x21 _L1e_FS_SeekToHalfFram
+ 0x1009aceb 0xce _L1e_FS_DoPss
+ 0x1009adb9 0x109 _L1e_FS_PssNext100KFreqPointNoPreCFO
+ 0x1009aec2 0x61 _L1e_FS_PssNext100KFreqPointPreCFO
+ 0x1009af23 0x35 _L1e_FS_PssNext100KFreqPoint
+ 0x1009af58 0x35 _L1e_FS_PssNextAgcGain
+ 0x1009af8d 0x1b _L1e_FS_PssNextProfile
+ 0x1009afa8 0x6c _L1e_FS_InitFreqOffset
+ 0x1009b014 0x49 _L1e_FS_PssNextFreqOffset
+ 0x1009b05d 0x3d _L1e_FS_PreFreqOffset
+ 0x1009b09a 0x136 _L1e_FS_Pss100KResult
+ 0x1009b1d0 0x3d _L1e_FS_DiscreteFreqOffsetLoop
+ 0x1009b20d 0x7f _L1e_FS_PssDisctResult
+ 0x1009b28c 0x1b _L1e_FS_PssProfileLoopStart
+ 0x1009b2a7 0x54 _L1e_FS_NextBand
+ 0x1009b2fb 0x1b _L1e_FS_Pss500KFreqPointLoopStart
+ 0x1009b316 0x31 _L1e_FS_PssNext500KFreqPoint
+ 0x1009b347 0x11 _L1e_FS_GetFsMode
+ 0x1009b358 0x56 _L1e_FS_SetFsTempResult
+ 0x1009b3ae 0xa4 _L1e_FS_FreqScanCellSearch
+ 0x1009b452 0x4a _L1e_FS_PssOneFreqPointStart
+ 0x1009b49c 0x2b _L1e_FS_PssAgcGainLoopStart
+ 0x1009b4c7 0x6a _L1e_FS_Pss100KFreqPointLoopStart
+ 0x1009b531 0xc _L1e_FS_PssNeedOffset
+ 0x1009b53d 0xd _L1e_FS_PssNeedDo100K
+ 0x1009b54a 0xe _L1e_FS_BandLoopStart
+ 0x1009b558 0x2b _L1e_FS_PssSkipPiTime
+ 0x1009b583 0x1e _L1e_FS_PssSeekToSlaveGap
+ 0x1009b5a1 0x23 _L1e_FS_SeekToWorkTime
+ 0x1009b5c4 0x24 _L1e_FS_MpFreqPointLoopStart
+ 0x1009b5e8 0x7b _L1e_FS_SegmentInfoSort
+ 0x1009b663 0x93 _L1e_FS_SetSegmentInfo
+ 0x1009b6f6 0xd3 _L1e_FS_SetSegmentInfoEnd
+ 0x1009b7c9 0xb4 _L1e_FS_FreqSegmentAlorigthm
+ 0x1009b87d 0x61 _L1e_FS_SetBackupFreqOffset
+ 0x1009b8de 0x62 _L1e_FS_FreqSegment
+ 0x1009b940 0x2f _L1e_FS_MpNextFreqPoint
+ 0x1009b96f 0x24 _L1e_FS_MpOneFreqPointStart
+ 0x1009b993 0x40 _L1e_FS_MeanPowerCal
+ 0x1009b9d3 0xc _L1e_FS_MpMethod
+ 0x1009b9df 0x11 _L1e_FS_PssMethod
+ 0x1009b9f0 0x14 _L1e_FS_PLMN
+ 0x1009ba04 0xb _L1e_FS_SetState
+ 0x1009ba0f 0x8 _L1e_FS_GetState
+ 0x1009ba17 0x34 _L1e_FS_MpStart
+ 0x1009ba4b 0x15 _L1e_FS_SetCnfInfo
+ 0x1009ba60 0x68 _L1e_FS_OverlapSegment
+ 0x1009bac8 0x89 _L1e_FS_Report2PsResult
+ 0x1009bb51 0x1b _l1e_FS_MPEnvelopeSort
+ 0x1009bb6c 0x22 _L1e_FS_MpEnvelope
+ 0x1009bb8e 0xa _L1e_FS_PssNeedReDo500K
+ 0x1009bb98 0xc _L1e_FS_Redo500KStart
+ 0x1009bba4 0xf _L1e_FS_PssReDo500KNextProfile
+ 0x1009bbb3 0x1c _L1e_FS_PssReDo500KFpLoopStart
+ 0x1009bbcf 0x43 _L1e_Fs_ReDoGetAllValidFreqPoint
+ 0x1009bc12 0x24 _L1e_FS_PssReDoNext500KFreqPoint
+ 0x1009bc36 0xa _L1e_FS_PssNeedAgc
+ 0x1009bc40 0x9 _L1e_FS_AgcLoopStart
+ 0x1009bc49 0x45 _L1e_FS_AgcNextFreqPoint
+ 0x1009bc8e 0x21 _L1e_FS_BeforeAgc
+ 0x1009bcaf 0x16 _L1e_FS_AddAgcWaitTime
+ 0x1009bcc5 0xc5 _L1e_FS_AgcProc
+ 0x1009bd8a 0x17 _L1e_FS_PssNeedReDo100K
+ 0x1009bda1 0x17 _L1e_FS_IsSerialMode
+ 0x1009bdb8 0x35 _L1e_FS_IsDiscreteMode
+ 0x1009bded 0x2b _L1e_FS_DiscretePssStart
+ 0x1009be18 0x12 _L1e_FS_DiscretePssSnrBackup
+ 0x1009be2a 0xc _L1e_FS_DiscretePssSnrClear
+ 0x1009be36 0x31 _L1e_FS_CheckSearchMode
+ 0x1009be67 0x192 _L1e_FS_CfgRfAndGetMp
+ 0x1009bff9 0x1a _L1e_FS_MpSeekWorkTime
+ .text 0x1009c013 0x345b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x1009c013 0x119 _zPHY_euls_UlGrantReception
+ 0x1009c12c 0x13d _zPHY_euls_HARQEntity
+ 0x1009c269 0x332 _zPHY_euls_HARQProcess
+ 0x1009c59b 0x57 _zPHY_euls_ProInitial
+ 0x1009c5f2 0x31 _zPHY_euls_InitUlHarqIDInHarqDB
+ 0x1009c623 0x141 _zPHY_euls_UlHarqProcessCtrl
+ 0x1009c764 0x364 _zPHY_euls_DecodeDci4
+ 0x1009cac8 0x3bf _zPHY_euls_DecodeDci0
+ 0x1009ce87 0x104 _zPHY_euls_DecodeDci
+ 0x1009cf8b 0x4f _zPHY_euls_DecodePucchTPC
+ 0x1009cfda 0x8f _zPHY_euls_GetMsg3SendSubFrmNo
+ 0x1009d069 0x99 _zPHY_euls_DecodeRARGrant
+ 0x1009d102 0xaf _zPHY_euls_ReportUlGrantParas
+ 0x1009d1b1 0xa8 _zPHY_euls_ReportUlGrantToPS
+ 0x1009d259 0xab _zPHY_euls_CalcLUtrPara
+ 0x1009d304 0x9c _zPHY_euls_CalcLTxPara
+ 0x1009d3a0 0x129 _zPHY_euls_PuschPrmFHType1
+ 0x1009d4c9 0x1df _zPHY_euls_PuschPrmFHType2
+ 0x1009d6a8 0x10 _zPHY_euls_CalcX2Cinit
+ 0x1009d6b8 0x62 _zPHY_euls_CalcNPuschSymb
+ 0x1009d71a 0x148 _zPHY_euls_DecodeModuleCodeSchem
+ 0x1009d862 0x25 _zPHY_euls_Nchoosek
+ 0x1009d887 0x1b5 _zPHY_euls_DecodeRIV_Ratype1
+ 0x1009da3c 0x75 _zPHY_euls_DecodeRIV
+ 0x1009dab1 0x44 _zPHY_euls_GetRbAssignBitWidInDci4
+ 0x1009daf5 0x43 _zPHY_euls_GetRbAssignBitWidInDci0
+ 0x1009db38 0xc9 _zPHY_euls_GetPuschPosByPdcchOrPhichPos
+ 0x1009dc01 0x59 _zPHY_euls_AddMsg4DetectStartEvent
+ 0x1009dc5a 0x5a _zPHY_euls_AddMsg4DetectStopEvent
+ 0x1009dcb4 0x1f _zPHY_euls_AddMsg4DetectWinEvents
+ 0x1009dcd3 0x2d _zPHY_euls_ModifyMsg4DetectWinEvents
+ 0x1009dd00 0xde _zPHY_euls_AddMsg3LtxDealEvent
+ 0x1009ddde 0x49 _zPHY_euls_AddCqiRarSchdEvents
+ 0x1009de27 0x32 _zPHY_euls_InitSPSMode
+ 0x1009de59 0x2b _zPHY_euls_SetupSPSMode
+ 0x1009de84 0x7a _zPHY_euls_SetupSPSMode_DealComnPara
+ 0x1009defe 0x37 _zPHY_euls_SetupSPSMode_CalNextRecurPara
+ 0x1009df35 0x41 _zPHY_euls_JudgeAndDealUlSpsInterval_TDD
+ 0x1009df76 0x2e _zPHY_euls_JudgeAndDealUlSpsInterval_FDD
+ 0x1009dfa4 0x53 _zPHY_euls_ProSPSMode
+ 0x1009dff7 0x53 _zPHY_euls_ProSPSMode_GetUlSfUponCfgGrantSf
+ 0x1009e04a 0x44 _zPHY_euls_ProSPSMode_CalNextRecurPara
+ 0x1009e08e 0x32 _zPHY_euls_ReleaseSPSMode
+ 0x1009e0c0 0x37 _zPHY_euls_ProcessSPSImplicitRelease
+ 0x1009e0f7 0x11 _zPHY_euls_GetDCI0InfoFromConfiguredGrant
+ 0x1009e108 0x11 _zPHY_euls_LastSubframe_SFN
+ 0x1009e119 0xd _zPHY_euls_LastSubframe_Subframe
+ 0x1009e126 0xc _zPHY_euls_JudgeIfBitsIsAll1s_ForSPSRelease
+ 0x1009e132 0x4b _zPHY_euls_TATimerStop
+ 0x1009e17d 0xe _zPHY_euls_MACReset
+ 0x1009e18b 0xa1 _zPHY_euls_Release
+ 0x1009e22c 0x1e _zPHY_euls_ProcDci0PhichSelec
+ 0x1009e24a 0xcd _zPHY_euls_ProcDci0PhichSelec_Assign
+ 0x1009e317 0x46 _zPHY_euls_ProcDci0PhichSelec_Selec
+ 0x1009e35d 0x34 _zPHY_euls_DecodeUlIndexDci0
+ 0x1009e391 0x33 _zPHY_euls_DecodeUlIndexDci4
+ 0x1009e3c4 0x152 _zPHY_euls_AssignDCI0PHICH
+ 0x1009e516 0x5e _zPHY_euls_AssignDCI0_Schedule
+ 0x1009e574 0x26 _zPHY_euls_AssignPHICH_Schedule
+ 0x1009e59a 0x5a _zPHY_euls_SelecDCI0PHICH
+ 0x1009e5f4 0x21 _zPHY_euls_ReleaseDCI0PHICHSelecDB
+ 0x1009e615 0x67 _zPHY_euls_UpdataTTIBundlingHarqID
+ 0x1009e67c 0xa1 _zPHY_euls_DealBundlingGrant
+ 0x1009e71d 0x5a _zPHY_euls_ProcRealPHICH
+ 0x1009e777 0x59 _zPHY_euls_ProcVirtualPHICH
+ 0x1009e7d0 0x7b _zPHY_euls_InitTTIBundlingHarqID
+ 0x1009e84b 0x16 _zPHY_euls_InitTTIBundlingMode
+ 0x1009e861 0xc _zPHY_euls_ReleaseTTIBundlingMode
+ 0x1009e86d 0x6c _zPHY_euls_GetBundlingIDAndHarqID_InULA
+ 0x1009e8d9 0x75 _zPHY_euls_UpdataHarqID
+ 0x1009e94e 0x8 _zPHY_euls_AddAbsSubframe
+ 0x1009e956 0x66 _zPHY_euls_SetDrxFlag
+ 0x1009e9bc 0xcd _zPHY_euls_Dci0SelecAndCsiReport_Proc
+ 0x1009ea89 0x3d3 _zPHY_euls_CalcDciCsiReqFlag
+ 0x1009ee5c 0xf7 _zPHY_euls_CalLutrAndLtx
+ 0x1009ef53 0x16 _zPHY_euls_ScheduleTxChannelType
+ 0x1009ef69 0x7d _zPHY_euls_SchedulePuschAndPucch
+ 0x1009efe6 0x16f _zPHY_euls_DeterminePuschTransType
+ 0x1009f155 0x37 _zPHY_euls_GetPuschHarqAckInfo
+ 0x1009f18c 0x12d _zPHY_euls_DeterminePucchFmt
+ 0x1009f2b9 0x26 _zPHY_euls_GetSysTimeInfo
+ 0x1009f2df 0x75 _zPHY_euls_TM2_ChanExchange
+ 0x1009f354 0x66 _zPHY_euls_PuschPowerControl_Process
+ 0x1009f3ba 0x50 _zPHY_euls_NoPuschPowerControl_Process
+ 0x1009f40a 0x2a _zPHY_euls_GaoTong_Statistics_Process
+ 0x1009f434 0x1 _zPHY_euls_AmtTest_DciStubProcess
+ 0x1009f435 0x39 _zPHY_euls_GetPhichSubFrmNo
+ .text 0x1009f46e 0xa6d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x1009f46e 0x5 _zPHY_ecsrs_GetIdleDrxInterPssWorkTime
+ 0x1009f473 0x165 _zPHY_ecsrs_GetPssStartTime
+ 0x1009f5d8 0x63 _zPHY_ecsrs_AdjustPssStartTime
+ 0x1009f63b 0x14e _zPHY_ecsrs_SetPssFirstStartInfo
+ 0x1009f789 0xca _zPHY_ecsrs_SetPssNotFirstStartInfo
+ 0x1009f853 0x9a _zPHY_ecsrs_GetPssStartInfo
+ 0x1009f8ed 0x4f _zPHY_ecsrs_GetPssReadFlag
+ 0x1009f93c 0x23 _zPHY_ecsrs_ClearPeakList
+ 0x1009f95f 0x1a _zPHY_ecsrs_GetPssData
+ 0x1009f979 0x1c _zPHY_ecsrs_BackupPssFinger
+ 0x1009f995 0xb _zPHY_ecsrs_ClearPssFinger
+ 0x1009f9a0 0xd _zPHY_ecsrs_ClearInnerPeakList
+ 0x1009f9ad 0x5e _zPHY_ecsrs_AdjustPeakTime
+ 0x1009fa0b 0x19 _zPHY_ecsrs_FindFreq
+ 0x1009fa24 0x3d _zPHY_ecsrs_BackupPeakList
+ 0x1009fa61 0xa8 _zPHY_ecsrs_RecoverPeakList
+ 0x1009fb09 0x215 _zPHY_ecsrs_PssResultReadNew
+ 0x1009fd1e 0x63 _zPHY_ecsrs_CalBoundary
+ 0x1009fd81 0x2b _zPHY_ecsrs_CalRedoCfoBoundary
+ 0x1009fdac 0x46 _zPHY_ecsrs_PssAdjustPro
+ 0x1009fdf2 0x28 _zPHY_ecsrs_PssTpuAdjust
+ 0x1009fe1a 0x13 _zPHY_ecsrs_SearchMaxFinger
+ 0x1009fe2d 0xa0 _zPHY_ecsrs_FilterFinger
+ 0x1009fecd 0xe _zPHY_ecsrs_FingerIsValid
+ .text 0x1009fedb 0xc54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ 0x1009fedb 0x69 _zPHY_eula_PuschAckProcess
+ 0x1009ff44 0x177 _zPHY_eula_PuschCsiProcess
+ 0x100a00bb 0xc2 _zPHY_eula_SetPuschScale
+ 0x100a017d 0x1ed _zPHY_eula_PuschAckEncodedLenCalc
+ 0x100a036a 0x2b9 _zPHY_eula_TDD_PuschAckParasCalc
+ 0x100a0623 0x57 _zPHY_eula_TDD_PuschAckParasCalc_UlDl0
+ 0x100a067a 0x86 _zPHY_eula_LtxParas_acNcsPuschDmrs
+ 0x100a0700 0xc7 _zPHY_eula_LtxParas_acUVPuschDmrs
+ 0x100a07c7 0x290 _zPHY_eula_PuschCqiRiEncodedLenCalc
+ 0x100a0a57 0x24 _zPHY_eula_FDD_PuschAckParasCalc
+ 0x100a0a7b 0x8e _zPHY_eula_LtxParas_adwNcsDiv6PuschDmrs
+ 0x100a0b09 0x26 _zPHY_eula_HarqPuschMsg3Stub
+ .text 0x100a0b2f 0x547 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ 0x100a0b2f 0x80 _zPHY_eulpc_PuschPowParasCalc
+ 0x100a0baf 0x119 _zPHY_eulpc_UlsRelativePuscchPowCtrlProc
+ 0x100a0cc8 0x190 _zPHY_eulpc_PuschPowCalcProc
+ 0x100a0e58 0xa9 _zPHY_eulpc_NoPuschPowCalc
+ 0x100a0f01 0xb3 _zPHY_eulpc_DeltaTFCalc
+ 0x100a0fb4 0x89 _zPHY_eulpc_Log10yLinear
+ 0x100a103d 0x39 _zPHY_eulpc_PuschGetCsiInfo
+ .text 0x100a1076 0x540 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x100a1076 0x6d _zPHY_edfe_Q8log2
+ 0x100a10e3 0x21 _zPHY_edfe_Logarithm
+ 0x100a1104 0x34 _zPHY_edfe_SupCalLog
+ 0x100a1138 0x8 _zPHY_edfe_SetCsrmDAGCGain
+ 0x100a1140 0x76 _zPHY_edfe_CalcRxDAGCGain
+ 0x100a11b6 0xa2 _zPHY_edfe_HandleRxDAGCGain
+ 0x100a1258 0x57 _zPHY_edfe_FixedRXDagcGain
+ 0x100a12af 0x105 _zPHY_edfe_CalcCsrsDAGCGain
+ 0x100a13b4 0x26 _zPHY_edfe_JudgeRxDagcCover
+ 0x100a13da 0x6d _zPHY_edfe_JudgeCsrsDagcCover
+ 0x100a1447 0xa8 _zPHY_edfe_HandleCsrsDagcInt
+ 0x100a14ef 0x39 _zPHY_edfe_ConfigDagcCalcPara
+ 0x100a1528 0x8e _zPHY_edfe_SetInterCsrsDAGCGain
+ .text 0x100a15b6 0x777 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ 0x100a15b6 0x26 _zAsn1_GetU16Bits
+ 0x100a15dc 0x39 _zAsn1_SetU16Bits
+ 0x100a1615 0x18 _zEasn1p_perGetConVal
+ 0x100a162d 0xc _zEasn1p_perGetDivbVal
+ 0x100a1639 0xa _zEasn1p_perGetIntVal
+ 0x100a1643 0x13 _zEasn1p_perGetBitNum
+ 0x100a1656 0x1a _zEasn1p_perGetRange
+ 0x100a1670 0x67 _zEasn1p_DcGetBitsVal32_Dec
+ 0x100a16d7 0x2 _zEasn1p_DcGetBitsVal32
+ 0x100a16d9 0x13 _zEasn1p_MovePtr_Dec
+ 0x100a16ec 0x1d _zEasn1p_EcSetBitStr_Dec
+ 0x100a1709 0xa2 _zEasn1p_DcGetBitsStr_Dec
+ 0x100a17ab 0x2 _zEasn1p_DcGetBitsStr
+ 0x100a17ad 0x1a _zEasn1p_ChkCodeLen_Dec
+ 0x100a17c7 0x91 _zEasn1p_per_dcOctStr
+ 0x100a1858 0xe5 _zEasn1p_per_dcLen
+ 0x100a193d 0x2f _zEasn1p_per_DcExt
+ 0x100a196c 0x2f _zEasn1p_per_dcIndefiniteLenWholeNum
+ 0x100a199b 0x2e _zEasn1p_per_dcConWholeNum
+ 0x100a19c9 0x8f _zEasn1p_per_dcSequenceOf
+ 0x100a1a58 0x2 _zEasn1p_MovePtr
+ 0x100a1a5a 0x24 _zEasn1p_per_dcPreamble
+ 0x100a1a7e 0x29 _zEasn1p_per_dcPreamble_Sequence
+ 0x100a1aa7 0x47 _zEasn1p_per_dcSmallWholeNum
+ 0x100a1aee 0x46 _zEasn1p_per_dcSkipAllExtData
+ 0x100a1b34 0xb7 _zEasn1p_per_dcInt
+ 0x100a1beb 0x66 _zEasn1p_per_dcChoiceOf
+ 0x100a1c51 0x4a _zEasn1p_per_dcSkipOneExtData
+ 0x100a1c9b 0x92 _zEasn1p_per_dcBitStr
+ .text 0x100a1d2d 0x391 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ 0x100a1d2d 0x55 _zPHY_ecsrs_GetCfoStartTime
+ 0x100a1d82 0x54 _zPHY_ecsrs_SetCfoStartInfoSymMap
+ 0x100a1dd6 0xa1 _zPHY_ecsrs_GetCfoStartInfo
+ 0x100a1e77 0x1e _zPHY_ecsrs_CalPowerNcpEcp
+ 0x100a1e95 0x46 _zPHY_ecsrs_CfoCalcPower
+ 0x100a1edb 0x5e _zPHY_ecsrs_CfoCalcPowerNcpEcp
+ 0x100a1f39 0x5e _zPHY_ecsrs_Codic_atan_FixPoint
+ 0x100a1f97 0x76 _zPHY_ecsrs_CsCfoResultMerge
+ 0x100a200d 0xb1 _zPHY_ecsrs_CfoResultRead
+ .text 0x100a20be 0x189 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ 0x100a20be 0x186 _zPHY_edla_CalcPcfichRegFilePara
+ 0x100a2244 0x3 _zPHY_edla_PcfichProc
+ .text 0x100a2247 0x1107 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ 0x100a2247 0xb7 _zPHY_ecsrs_SssStartFingerSort
+ 0x100a22fe 0xff _zPHY_ecsrs_SssFingerReorder
+ 0x100a23fd 0x49 _zPHY_ecsrs_AdjustSssFddProc
+ 0x100a2446 0x7c _zPHY_ecsrs_GetSssStartFinger
+ 0x100a24c2 0x37 _zPHY_ecsrs_GetNearValidTime
+ 0x100a24f9 0x33 _zPHY_ecsrs_CalSssBufferTime
+ 0x100a252c 0x170 _zPHY_ecsrs_GetSssStartTime
+ 0x100a269c 0x92 _zPHY_ecsrs_GetRfcEnableInfo
+ 0x100a272e 0x3e _zPHY_ecsrs_GetSssStartFg
+ 0x100a276c 0x50 _zPHY_ecsrs_InitSssStartInfo
+ 0x100a27bc 0x8f _zPHY_ecsrs_SetSssFddStartInfoAllProc
+ 0x100a284b 0xb7 _zPHY_ecsrs_SetSssTddStartInfoAllProc
+ 0x100a2902 0x251 _zPHY_ecsrs_SetSssFirstStartInfo
+ 0x100a2b53 0xd9 _zPHY_ecsrs_SetSssComStartInfo
+ 0x100a2c2c 0x4d _zPHY_ecsrs_GetSssStartInfo
+ 0x100a2c79 0x9b _zPHY_ecsrs_GetSssReadFlag
+ 0x100a2d14 0xe2 _zPHY_ecsrs_GetThresholdAndFilterCell
+ 0x100a2df6 0x2ae _zPHY_ecsrs_SssResultReadNew
+ 0x100a30a4 0x1a7 _zPHY_ecsrs_SssResultReadAppointCell
+ 0x100a324b 0x28 _zPHY_ecsrs_RecodCfoInfo
+ 0x100a3273 0x3e _zPHY_ecsrs_CheckCfoValid
+ 0x100a32b1 0x77 _zPHY_ecsrs_SearchForSssHwReset
+ 0x100a3328 0x26 _zPHY_ecsrs_SetSssHwCfgTime
+ .text 0x100a334e 0x1722 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x100a334e 0x5 _zPHY_ecsrs_Init
+ 0x100a3353 0x17 _zPHY_ecsrs_Reset
+ 0x100a336a 0x1 _zPHY_ecsrs_DebugModeInitPara
+ 0x100a336b 0x24 _zPHY_ecsrs_InitCommonInfor
+ 0x100a338f 0x1b _zPHY_ecsrs_DeleteAllSubFrameInt
+ 0x100a33aa 0x8 _zPHY_ecsrs_ResetSynInforTable
+ 0x100a33b2 0x30 _zPHY_ecsrs_GetIntraEarfcnInfo
+ 0x100a33e2 0x1e _zPHY_ecsrs_GetInterEarfcnInfo
+ 0x100a3400 0x1c4 _zPHY_ecsrs_GetCommonInfor
+ 0x100a35c4 0x34 _zPHY_ecsrs_CsRfcConfig
+ 0x100a35f8 0x1a _zPHY_ecsrs_BeforeInitSearch
+ 0x100a3612 0x15 _zPHY_ecsrs_TimeRelation
+ 0x100a3627 0x88 _zPHY_ecsrs_InterFreqChange
+ 0x100a36af 0x62 _zPHY_ecsrs_GetHwConfigMode
+ 0x100a3711 0x112 _zPHY_ecsrs_GetReadAndConfigIndex
+ 0x100a3823 0x1e _zPHY_ecsrs_SetSyncRelation
+ 0x100a3841 0x25 _zPHY_ecsrs_TFConfirmSearchMode
+ 0x100a3866 0x31 _zPHY_ecsrs_SetFilterRange
+ 0x100a3897 0xd _zPHY_ecsrs_OpenSubFrameInt
+ 0x100a38a4 0xd _zPHY_ecsrs_DelSubFrameInt
+ 0x100a38b1 0x8 _zPHY_ecsrs_UpdateInnOffset
+ 0x100a38b9 0x2b _zPHY_ecsrs_ReadSearchResult
+ 0x100a38e4 0x3d _zPHY_ecsrs_GetSubTime
+ 0x100a3921 0x31 _L1e_csrs_InitGloPara
+ 0x100a3952 0x8 _zPHY_ecsrs_OnReset
+ 0x100a395a 0x3 _zPHY_ecsrs_OnSearchMeasReset
+ 0x100a395d 0x48 _zPHY_ecsrs_OnSearchFreqScan
+ 0x100a39a5 0x81 _zPHY_ecsrs_OnSearchMeasStart
+ 0x100a3a26 0x1f _zPHY_ecsrs_OnPssUpdateCounterCnf
+ 0x100a3a45 0x70 _zPHY_ecsrs_OnTimeDelayInt
+ 0x100a3ab5 0xd _zPHY_ecsrs_OnNotSynSubFrameInt
+ 0x100a3ac2 0x57 _zPHY_ecsrs_InitFreqOffset
+ 0x100a3b19 0x9b _L1e_csrs_GetFreqOffset
+ 0x100a3bb4 0x6e _L1e_csrs_SetFtErrorList
+ 0x100a3c22 0x65 _L1e_csrs_SetFreqOffsetAge
+ 0x100a3c87 0x11 _L1e_csrs_GetMaxAgeIndex
+ 0x100a3c98 0x30 _L1e_csrs_NormalTemp
+ 0x100a3cc8 0x89 _zPHY_ecsrs_ModifyRfCfgInfo
+ 0x100a3d51 0x7 _zPHY_ecsrs_setMode
+ 0x100a3d58 0xa _zPHY_ecsrs_IsIntraMode
+ 0x100a3d62 0x86 _zEcsrs_PreEvent
+ 0x100a3de8 0x9e _L1e_csrs_SfProc
+ 0x100a3e86 0x2c _L1e_FS_SfProc
+ 0x100a3eb2 0x2e _zEcsrs_OnEvent
+ 0x100a3ee0 0xb _zPHY_ecsrs_IsInitCs
+ 0x100a3eeb 0x3c _zPHY_ecsrs_CsNeedReCfo
+ 0x100a3f27 0x16 _zPHY_ecsrs_CsNeedReSss
+ 0x100a3f3d 0x67 _zPHY_ecsrs_IsRfOpen
+ 0x100a3fa4 0x14c _zPHY_csr_RfcConfig
+ 0x100a40f0 0x1e _zPHY_ecsrs_IsOptSearch
+ 0x100a410e 0x1a _zPHY_ecsrs_CfoAccNum
+ 0x100a4128 0x1a _zPHY_ecsrs_GetConfigRfFlag
+ 0x100a4142 0x3d _zPHY_ecsrs_GetScheduleFlag
+ 0x100a417f 0x9 _zPHY_ecsrs_CsBeforeAgc
+ 0x100a4188 0x17 _zPHY_ecsrs_CsNeedAgc
+ 0x100a419f 0x6b _zPHY_ecsrs_CsNeedPss
+ 0x100a420a 0x2 _zPHY_ecsrs_CsNeedCfo
+ 0x100a420c 0x82 _zPHY_ecsrs_CsNeedSss
+ 0x100a428e 0x16 _zPHY_ecsrs_CsNeedTempComp
+ 0x100a42a4 0x26 _zPHY_ecsrs_CsIsOnAgc
+ 0x100a42ca 0x37 _zPHY_ecsrs_CsAgcProc
+ 0x100a4301 0x1 _zPHY_ecsrs_CsAgcProcEnd
+ 0x100a4302 0xd _zPHY_ecsrs_CsNeedPssAgain
+ 0x100a430f 0x17 _zPHY_ecsrs_CsBeforePss
+ 0x100a4326 0x1a _zPHY_ecsrs_CsIsOnPss
+ 0x100a4340 0x91 _zPHY_ecsrs_CsGetPssRfCfgInfo
+ 0x100a43d1 0x50 _zPHY_ecsrs_SniffInterFreqChange
+ 0x100a4421 0x13b _zPHY_ecsrs_CsPssProc
+ 0x100a455c 0xda _zPHY_ecsrs_CsPssProcEnd
+ 0x100a4636 0x2a _zPHY_ecsrs_CsNeedMoreCfo
+ 0x100a4660 0x23 _zPHY_ecsrs_CsBeforeCfo
+ 0x100a4683 0x12 _zPHY_ecsrs_CsCfoTpuAdjPro
+ 0x100a4695 0x14 _zPHY_ecsrs_CsIsOnCfo
+ 0x100a46a9 0x6f _zPHY_ecsrs_CsCfoProc
+ 0x100a4718 0x60 _zPHY_ecsrs_CsCfoProcEnd
+ 0x100a4778 0x13 _zPHY_ecsrs_CsBeforeSss
+ 0x100a478b 0x1a _zPHY_ecsrs_CsIsOnSss
+ 0x100a47a5 0x8d _zPHY_ecsrs_CsGetSssRfCfgInfo
+ 0x100a4832 0x12d _zPHY_ecsrs_CsSssProc
+ 0x100a495f 0x1d _zPHY_ecsrs_InitSearchCnf
+ 0x100a497c 0x56 _zPHY_ecsrs_CsSssProcEnd
+ 0x100a49d2 0x18 _zPHY_ecsrs_CsNeedCs
+ 0x100a49ea 0x1a _zPHY_ecsrs_CsBeforeCs
+ 0x100a4a04 0xb _zPHY_ecsrs_WaitSubFrameInt
+ 0x100a4a0f 0x1c _zPHY_ecsrs_SSSearctT
+ 0x100a4a2b 0x3d _zPHY_ecsrs_CheckSssCount
+ 0x100a4a68 0x8 _zPHY_ecsrs_SetSssHwRestartCnt
+ .text 0x100a4a70 0x3c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ .text 0x100a4aac 0x458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x100a4aac 0x13 _zPHY_ecsrs_HwIntHandle
+ 0x100a4abf 0x49 _zPHY_ecsrs_HwReset
+ 0x100a4b08 0x33 _zPHY_ecsrs_AllHwReset
+ 0x100a4b3b 0x15 _zPHY_ecsr_HwSssTdCommonReset
+ 0x100a4b50 0xa3 _zPHY_ecsrs_ConfigIcFiFoHw
+ 0x100a4bf3 0x8a _zPHY_ecsrs_ConfigIcHw
+ 0x100a4c7d 0x4f _zPHY_ecsrs_ConfigPssHw
+ 0x100a4ccc 0x36 _zPHY_ecsrs_ConfigCfoHw
+ 0x100a4d02 0x47 _zPHY_ecsrs_ConfigSssHw
+ 0x100a4d49 0xc _zPHY_ecsrs_CfgTopClkGating
+ 0x100a4d55 0x14 _zPHY_ecsrs_CfgTopReg
+ 0x100a4d69 0x27 _zPHY_ecsrs_SssCfgPschLocalSeq
+ 0x100a4d90 0x31 _zPHY_ecsrs_AgcBalanceCfgRegs
+ 0x100a4dc1 0xc _zPHY_ecsrs_AgcBalanceDisable
+ 0x100a4dcd 0x23 _zPHY_ecsrc_SwClkGateCtrl
+ 0x100a4df0 0x49 _zPHY_ecsr_ConvertFinger
+ 0x100a4e39 0x1f _zPHY_ecsr_GetHwPssFinger
+ 0x100a4e58 0x8 _zPHY_ecsr_GetHwPssFreqInd
+ 0x100a4e60 0xd _zPHY_ecsr_GetHwPssDoneMark
+ 0x100a4e6d 0xd _zPHY_ecsr_GetHwPssNumHalfFrame
+ 0x100a4e7a 0x3 _zPHY_ecsr_GetHwPssPeakValid
+ 0x100a4e7d 0x8 _zPHY_ecsr_GetHwPssMaxPower
+ 0x100a4e85 0xa _zPHY_ecsr_GetHwCfoOutput
+ 0x100a4e8f 0x10 _zPHY_ecsr_GetHwSssPeakList
+ 0x100a4e9f 0xa _zPHY_ecsr_GetHwSssComResult
+ 0x100a4ea9 0xb _zPHY_ecsr_GetHwSssProcCount
+ 0x100a4eb4 0xb _zPHY_ecsr_GetHwSssProcStatus
+ 0x100a4ebf 0xd _zPHY_ecsr_GetHwSssProcEnable
+ 0x100a4ecc 0x8 _zPHY_ecsr_GetHwSssProcRdWrState
+ 0x100a4ed4 0x8 _zPHY_ecsr_GetHwIcWorkState
+ 0x100a4edc 0x8 _zPHY_ecsr_GetHwTopClkGating
+ 0x100a4ee4 0x8 _zPHY_ecsr_GetHwPssClkGatingBypass
+ 0x100a4eec 0x8 _zPHY_ecsr_GetHwIcClkGatingBypass
+ 0x100a4ef4 0x8 _zPHY_ecsr_GetHwSssClkGatingEn
+ 0x100a4efc 0x8 _zPHY_ecsr_GetHwSssWorkStatus
+ .text 0x100a4f04 0x571 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ 0x100a4f04 0x2f _L1e_FS_LogAddSearchResult
+ 0x100a4f33 0x25 _L1e_FS_LogAddSearchResultFail
+ 0x100a4f58 0x14 _L1e_FS_LogGainCompenError
+ 0x100a4f6c 0x17 _L1e_FS_LogMinAgcGainError
+ 0x100a4f83 0x17 _L1e_FS_LogDeleteEarfcn
+ 0x100a4f9a 0x2d _L1e_FS_LogSssResult
+ 0x100a4fc7 0x17 _L1e_FS_LogFsResultNum
+ 0x100a4fde 0x1e _L1e_FS_LogDeleteFreqPoint
+ 0x100a4ffc 0x5c _L1e_FS_LogBandInfo
+ 0x100a5058 0x40 _L1e_FS_LogProfileInfo
+ 0x100a5098 0x38 _L1e_FS_LogInsertPSSResult
+ 0x100a50d0 0x54 _L1e_FS_LogAddSearchwEarfcn
+ 0x100a5124 0x21 _L1e_FS_LogPlmnReturnSrvCell
+ 0x100a5145 0x95 _L1e_FS_LogPSSFinger
+ 0x100a51da 0x14 _L1e_FS_LogPSSNoValidEarfcn
+ 0x100a51ee 0x22 _L1e_FS_LogResultNULL
+ 0x100a5210 0x1d _L1e_FS_LogChangeAgc
+ 0x100a522d 0x1a _L1e_FS_LogAllAgcFail
+ 0x100a5247 0x14 _L1e_FS_LogReqMsgError
+ 0x100a525b 0x41 _L1e_FS_LogSegmeantInfo
+ 0x100a529c 0x31 _L1e_FS_LogSssAgcGain
+ 0x100a52cd 0x26 _L1e_FS_LogMpInfo
+ 0x100a52f3 0x5b _L1e_FS_LogProGainInfo
+ 0x100a534e 0x1d _L1e_FS_LogAGCInfo
+ 0x100a536b 0x4a _L1e_FS_LogProRedo100KInfo
+ 0x100a53b5 0x1d _L1e_FS_StartAGC
+ 0x100a53d2 0x2a _L1e_FS_AGCInfo
+ 0x100a53fc 0x27 _L1e_FS_TestInfo
+ 0x100a5423 0x1e _L1e_FS_LogBackup100KResult
+ 0x100a5441 0x17 _L1e_FS_LogFreqOffsetIndex
+ 0x100a5458 0x1d _zPHY_ecsc_LogPss100KResult
+ .text 0x100a5475 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ 0x100a5475 0x1c _zPHY_ecsrs_ListInsert
+ 0x100a5491 0x5 _zPHY_ecsrs_ListAdd
+ 0x100a5496 0x1a _zPHY_ecsrs_ListDelete
+ 0x100a54b0 0x3 _zPHY_ecsrs_ListFirst
+ 0x100a54b3 0x3 _zPHY_ecsrs_ListLast
+ 0x100a54b6 0x2 _zPHY_ecsrs_ListNext
+ 0x100a54b8 0x3 _zPHY_ecsrs_ListPrev
+ 0x100a54bb 0x8 _zPHY_ecsrs_IsListEmpty
+ .text 0x100a54c3 0x9c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ 0x100a54c3 0x9c _s_create_pool
+ .text 0x100a555f 0x20 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ 0x100a555f 0x20 _create_sem
+ .text 0x100a557f 0x9 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ 0x100a557f 0x9 _current_process
+ .text 0x100a5588 0x50 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ 0x100a5588 0x50 _delay
+ .text 0x100a55d8 0x63 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ 0x100a55d8 0x63 _free_buf
+ .text 0x100a563b 0x49 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ 0x100a563b 0x49 _get_pri
+ .text 0x100a5684 0x8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ 0x100a5684 0x8 _get_ticks
+ .text 0x100a568c 0x4c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ 0x100a568c 0x4c _kill_sem
+ .text 0x100a56d8 0x7c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ 0x100a56da 0x7a _receive
+ .text 0x100a5754 0xc7 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ 0x100a5756 0xc5 _s_alloc_nil
+ .text 0x100a581b 0x16 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ 0x100a581b 0x16 _sender
+ .text 0x100a5831 0x116 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ 0x100a5831 0x77 _set_pri
+ 0x100a58a8 0x9f _set_ot_pri
+ .text 0x100a5947 0x31 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ 0x100a5947 0x31 _signal_sem
+ .text 0x100a5978 0x65 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ 0x100a5978 0x65 _start
+ .text 0x100a59dd 0x1c5 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ 0x100a59dd 0xa _zcos_sysd_init
+ 0x100a59e7 0x5b _odo_kill_proc
+ 0x100a5a42 0x39 _odo_hunt_kill_proc
+ 0x100a5a7b 0x7b _odo_new_process
+ 0x100a5af6 0x34 _odo_hunt_request_local
+ 0x100a5b2a 0x55 _ose_sysd_handle_signal
+ 0x100a5b7f 0x23 _zcos_sysd
+ .text 0x100a5ba2 0x83 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ 0x100a5ba2 0x83 _tick
+ .text 0x100a5c25 0x4c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ 0x100a5c25 0x4c _wait_sem
+ .text 0x100a5c71 0xfa T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ 0x100a5c71 0x36 _odo_hunt_find_name
+ 0x100a5ca7 0xc4 _hunt
+ .text 0x100a5d6b 0x43 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ 0x100a5d6b 0x43 _restore
+ .text 0x100a5dae 0x98 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ 0x100a5dae 0x98 _send_w_s
+ .text 0x100a5e46 0x5b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ 0x100a5e46 0x5b _zDrvEfuse_IsSpe
+ .text 0x100a5ea1 0x4f C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(32.o)
+ 0x100a5ea1 0xf ___modhi3
+ 0x100a5eb0 0x19 ___umodhi3
+ 0x100a5ec9 0x11 ___divhi3
+ 0x100a5eda 0x16 ___udivhi3
+ .text 0x100a5ef0 0x19e C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Add.o)
+ 0x100a5ef0 0x19e ___addsf3
+ .text 0x100a608e 0x2a C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(compare_IEEE.o)
+ 0x100a608e 0x0 ___gehf2
+ 0x100a608e 0x0 ___nehf2
+ 0x100a608e 0x0 ___eqhf2
+ 0x100a608e 0x0 ___lthf2
+ 0x100a608e 0x0 ___gthf2
+ 0x100a608e 0x2a ___lehf2
+ .text 0x100a60b8 0x2d C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convert.o)
+ 0x100a60b8 0x21 ___floatunshihf2
+ 0x100a60d9 0xc ___floathihf2
+ .text 0x100a60e5 0x18 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(convertqi.o)
+ 0x100a60e5 0xb ___floatqihf2
+ 0x100a60f0 0xd ___floatunsqihf2
+ .text 0x100a60fd 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(div.o)
+ 0x100a6105 0x21 ___divqi3
+ .text 0x100a6126 0x112 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Div.o)
+ 0x100a6126 0x112 ___divsf3
+ .text 0x100a6238 0x29 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(divzi3_v2.o)
+ 0x100a6238 0x29 ___divzi3_v2
+ *fill* 0x100a6261 0x80000001 00
+ .text 0x100a6262 0x17 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(ftou.o)
+ 0x100a6262 0x17 ___ieee754_ftou
+ .text 0x100a6279 0xf C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcmp.o)
+ 0x100a6279 0xf _memcmp
+ .text 0x100a6288 0x12 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy16.o)
+ 0x100a6289 0x11 ___memcpy16
+ .text 0x100a629a 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memcpy.o)
+ 0x100a629f 0x10 _memcpy
+ .text 0x100a62af 0x15 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(memset.o)
+ 0x100a62b0 0x14 _memset
+ .text 0x100a62c4 0x21 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(mod.o)
+ 0x100a62c4 0x21 ___modqi3
+ .text 0x100a62e5 0x27 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(modzi3_v2.o)
+ 0x100a62e5 0x27 ___modzi3_v2
+ .text 0x100a630c 0xe1 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(Mul.o)
+ 0x100a630c 0x0 ___ieee754_mul
+ 0x100a630c 0xe1 ___mulsf3
+ .text 0x100a63ed 0x6b C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(pnan.o)
+ 0x100a63ed 0x6b ___ieee754_propagate_nan
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+ 0x100db49b 0xc _L1W_TAB_HSUPA_RG_THRESH
+ 0x100db4a7 0x8 _L1W_TAB_HSUPA_HI_THRESH
+ 0x100db4af 0x1 _g_eL1wServHiNckDtx
+ 0x100db4b0 0x1 _g_hiNackCnt
+ .data 0x100db4b1 0x269 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x100db719 0x1 _g_L1LteaInitFlag
+ .data 0x100db71a 0x61a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ .data 0x100dbd34 0x34 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x100dbd34 0x1f _swTpuSym2Ts
+ 0x100dbd53 0x15 _s_awNextXSubFrm
+ .data 0x100dbd68 0x13 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x100dbd68 0x8 _g_tCsi
+ 0x100dbd70 0x1 _g_wCsiSCellActive
+ 0x100dbd71 0xa _g_awCsiNoUpFlg
+ .data 0x100dbd7b 0x87 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x100dbd7b 0x10 _g_aswDdrPro
+ 0x100dbd8b 0x4 _g_aswDdrStartPro
+ 0x100dbd8f 0x40 _g_awDdrBmpConv
+ 0x100dbdcf 0x32 _g_awStartBlockIdx
+ 0x100dbe01 0x1 _wPchUseSibFlag
+ .data 0x100dbe02 0x235 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x100dbe02 0x39 _T_ZPHY_RFSD_CONFIG
+ 0x100dbe3b 0x1c _T_ZPHY_RFCSA_CSRC_CONFIG
+ 0x100dbe57 0x15 _T_ZPHY_RFCSA_RX_CONFIG
+ 0x100dbe6c 0x18 _T_ZPHY_RFCSA_TX_CONFIG
+ 0x100dbe84 0x16 _T_ZPHY_TA_MAX
+ 0x100dbe9a 0x31 _T_ZPHY_ACP405_TRANS_TABLE
+ 0x100dbecb 0x6 _T_ZPHY_ACP405_FASTAGC_APPLY
+ 0x100dbed1 0x6 _T_ZPHY_RFC_FASTAGC_ESTI
+ 0x100dbed7 0x28 _g_at_zPHY_erfc_VgaTempDiffList
+ 0x100dbeff 0xc _g_adwFixDlDelay
+ 0x100dbf0b 0xc _g_dwFixUlDelay
+ 0x100dbf17 0xc _g_dwULDBBRFDelay
+ 0x100dbf23 0x1 _g_wTddOrFddbuff
+ 0x100dbf24 0x14 _g_asdzPHY_erfc_Rxoffset0SFConfig
+ 0x100dbf38 0x14 _g_asdzPHY_erfc_Rxoffset1SFConfig
+ 0x100dbf4c 0x1 _g_zPHY_erfc_wMeas0TabJumpToNum
+ 0x100dbf4d 0x1 _g_zPHY_erfc_cTxTabJumpToSubNum
+ 0x100dbf4e 0x14 _g_asdzPHY_erfc_TAoffsetSFConfig
+ 0x100dbf62 0x2 _g_ptzPHY_etpu_LocalMrtrOffset
+ 0x100dbf64 0x98 _g_zPHY_erfc_Temp_Dac_Data
+ 0x100dbffc 0x2 _g_swATCtrlFixTa
+ 0x100dbffe 0x2 _g_ePhyRatMode
+ 0x100dc000 0x12 _g_zPHY_RfcDataPointer
+ 0x100dc012 0x1 _g_zPHY_erfc_bRfcProfileInd
+ 0x100dc013 0x1 _g_zPHY_edfe_bRfcProfileInd
+ 0x100dc014 0x1 _g_zPHY_erfc_NextSfnSccIdleFlag
+ 0x100dc015 0x6 _g_atL1lRfcNextSfOffset
+ 0x100dc01b 0x6 _g_tXoAtDebugC0
+ 0x100dc021 0x16 _g_zPHY_erfc_tDcxoPara
+ .data 0x100dc037 0x4e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x100dc037 0x9 _g_wCddRiFirCalc
+ 0x100dc040 0x297 _g_awLog2TableDot16
+ 0x100dc2d7 0x80 _g_awLog2Table
+ 0x100dc357 0x10 _g_atCDDL2CB
+ 0x100dc367 0x18 _g_atCBTX2NL1
+ 0x100dc37f 0x20 _g_atCBTX2NL2
+ 0x100dc39f 0x100 _g_atCBTX4NL2
+ 0x100dc49f 0x48 _g_atCBCDDTx4
+ 0x100dc4e7 0x2a _g_awCqiEfficiency
+ 0x100dc511 0x1 _g_RiVal2Dl
+ 0x100dc512 0x4 _g_adCddRiCurSnr
+ 0x100dc516 0x4 _g_adCddRiFilterSnr
+ .data 0x100dc51a 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x100dc51a 0x2 _ptrBch
+ 0x100dc51c 0x2 _g_dwCsrsMulmPbchWorkFlag
+ .data 0x100dc51e 0x52 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x100dc53c 0x12 _g_ptL1eDevDlsDlaIx
+ 0x100dc54e 0x20 _g_dwHarqAddr
+ 0x100dc56e 0x2 _gDLHarqPduMutex
+ .data 0x100dc570 0x97 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x100dc5d4 0x6 _s_aWBHiCfgSBSize
+ 0x100dc5da 0x6 _s_aWBHiCfgLastSBSize
+ 0x100dc5e0 0x24 _s_aWBHiCfgSBNum
+ 0x100dc604 0x2 _g_PatCsiEnFinal
+ 0x100dc606 0x1 _g_awFeedBack_ConfigTimes
+ .data 0x100dc607 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x100dc607 0x2 _g_sdwTxOffset
+ *fill* 0x100dc609 0x80000001 00
+ .data 0x100dc60a 0xf4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x100dc629 0x2 _g_ptRxp_Ops
+ 0x100dc62b 0x1a _g_lsdwL1eRxSnrRefValue
+ 0x100dc645 0x28 _g_tLtel1RxAdaptAntCb
+ 0x100dc66d 0x16 _g_tLtel1DlaRfcDfeInfo
+ 0x100dc683 0x20 _g_lsdwNbnbRsrp
+ 0x100dc6a3 0x8 _g_lsdwNbnbN0
+ 0x100dc6ab 0x10 _g_lsdwNbnbRsrpPwr
+ 0x100dc6bb 0x40 _g_asdwL1eRxDrsRsrp
+ 0x100dc6fb 0x1 _g_wSingleAnt
+ 0x100dc6fc 0x2 _g_dwDrxState_For712Cir
+ *fill* 0x100dc6fe 0x80000002 00
+ .data 0x100dc700 0x1eee T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x100dc700 0x2 _g_dwSf_BeforeTAAdjust
+ 0x100dc702 0x20 _G_AW_SRS_M_NB_0640
+ 0x100dc722 0x20 _G_AW_SRS_M_NB_4060
+ 0x100dc742 0x20 _G_AW_SRS_M_NB_6080
+ 0x100dc762 0x20 _G_AW_SRS_M_NB_80110
+ 0x100dc782 0x50 _G_AC_SRS_SUBFRM_CONFIG_TDD
+ 0x100dc7d2 0xa0 _G_CELL_SRS_POS_SUBFRM_CONFIG_TDD
+ 0x100dc872 0x1e _G_AC_SRS_UE_SPEC_CONFIG_TDD
+ 0x100dc890 0x64 _G_UE_SRS_POS_CONFIG_TDD
+ 0x100dc8f4 0xc _G_AC_K_SRS1
+ 0x100dc900 0xc _G_AC_K_SRS2
+ 0x100dc90c 0x14 _G_AC_MULTI_ACKNACK_B0B1
+ 0x100dc920 0x9 _G_NEXT_ACK_ORDER
+ 0x100dc929 0x46 _G_AC_DL_SET_K_INFO
+ 0x100dc96f 0x46 _G_AC_DL_SET_K_FDD_TDD_INFO
+ 0x100dc9b5 0x9 _G_AC_M2_ACK_MULTIPLEXING
+ 0x100dc9be 0x1b _G_AC_M3_ACK_MULTIPLEXING
+ 0x100dc9d9 0x51 _G_AC_M4_ACK_MULTIPLEXING
+ 0x100dca2a 0x9 _G_AC_M2_ACK_MULTIPLEXING_R10
+ 0x100dca33 0x1b _G_AC_M3_ACK_MULTIPLEXING_R10
+ 0x100dca4e 0x51 _G_AC_M4_ACK_MULTIPLEXING_R10
+ 0x100dca9f 0x8 _G_AC_CA_A2_ACK_MULTIPLEXING
+ 0x100dcaa7 0x10 _G_AC_CA_A3_ACK_MULTIPLEXING
+ 0x100dcab7 0x20 _G_AC_CA_A4_ACK_MULTIPLEXING
+ 0x100dcad7 0x20 _G_FDD_CA_A4_ACK_FORMAT1B
+ 0x100dcaf7 0x12 _G_FDD_CA_A3_ACK_FORMAT1B
+ 0x100dcb09 0x8 _G_FDD_CA_A2_ACK_FORMAT1B
+ 0x100dcb11 0x20 _G_AC_CA_M3_ACK_MULTIPLEXING
+ 0x100dcb31 0x4c _G_AC_CA_M4_ACK_MULTIPLEXING
+ 0x100dcb7d 0x20 _G_AC_CA_M3_ACK_RESOURCE_VALUE
+ 0x100dcb9d 0x4c _G_AC_CA_M4_ACK_RESOURCE_VALUE
+ 0x100dcbe9 0x9 _G_AC_ULDL5_ACK_ORDER
+ 0x100dcbf2 0x46 _G_AC_SPECIAL_SUBFRAME_FLAG
+ 0x100dcc38 0x90 _G_AC_SRS_SUBFRM_CONFIG_FDD
+ 0x100dccc8 0xa0 _G_CELL_SRS_POS_SUBFRM_CONFIG_FDD
+ 0x100dcd68 0x10 _G_AW_HARQ_ACK_OFFSET
+ 0x100dcd78 0x10 _G_AW_RI_OFFSET
+ 0x100dcd88 0x10 _G_AW_CQI_OFFSET
+ 0x100dcd98 0xc5 _G_AW_PRIME_NUMBER
+ 0x100dce5d 0x8 _G_AW_CYCLIC_SHIFT_NDMRS1
+ 0x100dce65 0x18 _G_AW_CYCLIC_SHIFT_INDCI_NDMRS2_OCC
+ 0x100dce7d 0x5 _G_AW_FORMAT3_NOC_NPNS_NSF1_5
+ 0x100dce82 0x4 _G_AW_FORMAT3_NOC_NPNS_NSF1_4
+ 0x100dce86 0x7 _G_W_PRACH0_3_SCALE1
+ 0x100dce8d 0x1 _G_W_PRACH0_3_SCALE3
+ 0x100dce8e 0x7 _G_W_PRACH4_SCALE1
+ 0x100dce95 0x1 _G_W_PRACH4_SCALE3
+ 0x100dce96 0x7 _G_W_PUCCH_SCALE1_1_92M_SAMPLE
+ 0x100dce9d 0x7 _G_W_PUCCH_SCALE1_3_84M_SAMPLE
+ 0x100dcea4 0x7 _G_W_PUCCH_SCALE1_7_68M_SAMPLE
+ 0x100dceab 0x7 _G_W_PUCCH_SCALE1_15_36M_SAMPLE
+ 0x100dceb2 0x7 _G_W_PUCCH_SCALE1_30_72M_SAMPLE
+ 0x100dceb9 0x1 _G_W_PUCCH_SCALE3
+ 0x100dceba 0x1 _G_W_SRS_SCALE3
+ 0x100dcebb 0x7 _G_W_SRS_SCALE1_1_92M_SAMPLE
+ 0x100dcec2 0x1c _G_W_SRS_SCALE1_3_84M_SAMPLE
+ 0x100dcede 0x31 _G_W_SRS_SCALE1_7_68M_SAMPLE
+ 0x100dcf0f 0x62 _G_W_SRS_SCALE1_15_36M_SAMPLE
+ 0x100dcf71 0xaf _G_W_SRS_SCALE1_30_72M_SAMPLE
+ 0x100dd020 0x7 _G_W_PUSCH_SCALE1_1_92M_SAMPLE
+ 0x100dd027 0x7 _G_W_PUSCH_SCALE3_1_92M_SAMPLE
+ 0x100dd02e 0x7 _G_W_PUSCH_SCALE1_3_84M_SAMPLE
+ 0x100dd035 0x10 _G_W_PUSCH_SCALE3_3_84M_SAMPLE
+ 0x100dd045 0x7 _G_W_PUSCH_SCALE1_7_68M_SAMPLE
+ 0x100dd04c 0x1a _G_W_PUSCH_SCALE3_7_68M_SAMPLE
+ 0x100dd066 0x7 _G_W_PUSCH_SCALE1_15_36M_SAMPLE
+ 0x100dd06d 0x33 _G_W_PUSCH_SCALE3_15_36M_SAMPLE
+ 0x100dd0a0 0xe _G_W_PUSCH_SCALE1_30_72M_SAMPLE
+ 0x100dd0ae 0x65 _G_W_PUSCH_SCALE3_30_72M_SAMPLE
+ 0x100dd113 0x42 _G_W_FIRST_FILTER_1_4M_SAMPLE
+ 0x100dd155 0x42 _G_W_FIRST_FILTER_1_4M_SAMPLE_FIX3072
+ 0x100dd197 0x42 _G_W_FIRST_FILTER_3M_SAMPLE
+ 0x100dd1d9 0x42 _G_W_FIRST_FILTER_3M_SAMPLE_FIX3072
+ 0x100dd21b 0x42 _G_W_FIRST_FILTER_5M_SAMPLE
+ 0x100dd25d 0x42 _G_W_FIRST_FILTER_5M_SAMPLE_FIX3072
+ 0x100dd29f 0x42 _G_W_FIRST_FILTER_10M_SAMPLE
+ 0x100dd2e1 0x42 _G_W_FIRST_FILTER_10M_SAMPLE_FIX3072
+ 0x100dd323 0x42 _G_W_FIRST_FILTER_15M_SAMPLE
+ 0x100dd365 0x42 _G_W_FIRST_FILTER_20M_SAMPLE
+ 0x100dd3a7 0x42 _G_W_FIRST_FILTER_BYPASS_STUB_SAMPLE
+ 0x100dd3e9 0x42 _G_W_PRACH_FILTER_20M_15M_SAMPLE
+ 0x100dd42b 0x42 _G_W_PRACH_FILTER_3M_SAMPLE
+ 0x100dd46d 0x42 _G_W_PRACH_FILTER_5M_SAMPLE
+ 0x100dd4af 0x42 _G_W_PRACH_FILTER_10M_SAMPLE
+ 0x100dd4f1 0x18 _G_ADW_NCS_DIV_6
+ 0x100dd509 0x10 _G_ADW_NCS_DIV_4
+ 0x100dd519 0x6 _G_AW_C_NRBSC_DELTAPUCCHSHIFT
+ 0x100dd51f 0x208 _G_AW_MOD_30
+ 0x100dd727 0x12c _G_AW_MOD_12
+ 0x100dd853 0x24 _G_A_ZPHY_EULA_CHANNELTIMINGSEQTAB
+ 0x100dd877 0x25 _G_A_ZPHY_EULA_TQADJSUBFRAME
+ 0x100dd89c 0xc8 _g_adw_zPHY_eula_PuschMsg3Data
+ 0x100dd964 0xc76 _g_adw_zPHY_eula_TestCase12_2Data
+ 0x100de5da 0x14 _g_aeUlChannelType
+ .data 0x100de5ee 0x104 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x100de5ee 0x1 _g_zPHY_eWakeUpMode
+ 0x100de5ef 0x2 _g_zPHY_SleepFlag
+ 0x100de5f1 0x55 _G_ZPHY_ELPC_DVFS
+ 0x100de646 0x14 _g_zPHY_LPMCALIPARA
+ 0x100de65a 0x4 _G_ZPHY_ELPC_ZSPCLK
+ 0x100de65e 0x8f _G_ZPHY_ELPC_AXICLK
+ 0x100de6ed 0x1 _g_wWakeUpFlag
+ 0x100de6ee 0x1 _g_zPHY_bSccRficSleepFlag
+ 0x100de6ef 0x1 _g_zPHY_bUlGrantIntState
+ 0x100de6f0 0x1 _g_wLteCfunReset
+ 0x100de6f1 0x1 _g_wLtePrint1
+ .data 0x100de6f2 0x27 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x100de6f2 0x2 _g_dwInitalBandwidth
+ 0x100de6f4 0x24 _T_ZPHY_RELOAD_CONFIG
+ 0x100de718 0x1 _g_zPHY_tRfSleepState
+ .data 0x100de719 0x110 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x100de719 0x1 _g_zPHY_ecsrm_tConnectedMeasMode
+ 0x100de71a 0x10f _g_ThreadMeas
+ .data 0x100de829 0x17a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x100de829 0xa _g_awCsrmRsNumLog2
+ 0x100de833 0xa _g_awCsrmRsNumLog2_Single_Symbol
+ 0x100de83d 0x6 _g_awCsrmNumFftLogVal
+ 0x100de843 0x8 _MeasOnceSteps
+ 0x100de84b 0x67 _MeasOnce
+ 0x100de8b2 0x8 _MeasPrimarySteps
+ 0x100de8ba 0x67 _MeasPrimary
+ 0x100de921 0x18 _MeasProcSteps
+ 0x100de939 0x67 _MeasProc
+ 0x100de9a0 0x1 _g_zPHY_ecsrm_bHalfFrame
+ 0x100de9a1 0x2 _g_awMeasSingleSymModeFlag
+ .data 0x100de9a3 0x37 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x100de9a3 0x35 _g_awTriangleCoefft
+ 0x100de9d8 0x1 _gwCellchangeFlag
+ 0x100de9d9 0x1 _g_wMaxTxIndex
+ *fill* 0x100de9da 0x80000026 00
+ .data 0x100dea00 0x200 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft.o)
+ 0x100dea00 0x200 _g_aswOutdata
+ .data 0x100dec00 0x64 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x100dec00 0x50 _g_awL1eRxRsrpIdleFilterCoeff
+ 0x100dec50 0x14 _g_awL1eRxRsrpFilterCoeff
+ .data 0x100dec64 0x9b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x100dec64 0x2 _g_zPHY_edfe_dwAgcHwModeVari
+ 0x100dec66 0x1 _g_wFirstFlagDC0
+ 0x100dec67 0x1 _g_wFirstFlagDC1
+ 0x100dec68 0x84 _WDFE_GAINDBTOLINEVALUE
+ 0x100decec 0x1 _g_Csrs_Csrm_Start_Flag
+ 0x100deced 0x1 _g_bDfeIntCheckEventFlag
+ 0x100decee 0x1 _g_bCsrsDagcEstiEnableFlag
+ 0x100decef 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd
+ 0x100decf0 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd0
+ 0x100decf1 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCalEnd1
+ 0x100decf2 0x1 _g_zPHY_edfe_bFreqScanNotSyncAgcCoverFlag
+ 0x100decf3 0x2 _g_dwRspRx0Tx0
+ 0x100decf5 0x2 _g_dwRspRx1Tx0
+ 0x100decf7 0x2 _g_dwRspRx0Tx1
+ 0x100decf9 0x2 _g_dwRspRx1Tx1
+ 0x100decfb 0x1 _g_Idle_Inter_Freq_Flag
+ 0x100decfc 0x1 _g_wRxDagcIntCounter
+ 0x100decfd 0x1 _g_zPHY_edfe_RxDagcDoneFlag
+ 0x100decfe 0x1 _g_wFreqScanWorkOnFlag
+ .data 0x100decff 0xb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x100decff 0x1 _g_wPreSubFrame
+ 0x100ded00 0x1 _g_wCurSubFrame
+ 0x100ded01 0x1 _g_wPreFrame
+ 0x100ded02 0x1 _g_wCurFrame
+ 0x100ded03 0x1 _g_wSrsUpdataFlg
+ 0x100ded04 0x1 _g_wSrsUpdataFlg_Scell
+ 0x100ded05 0x2 _g_b_zPHY_eula_SrsSendFlag
+ 0x100ded07 0x1 _g_wMSG4AckINTLOCKCnt
+ 0x100ded08 0x1 _g_b711712Test1Test2Flg
+ 0x100ded09 0x1 _g_b711Test3Flg
+ .data 0x100ded0a 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x100ded0a 0x1 _wTddFddCaEnFlg
+ .data 0x100ded0b 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pucch.o)
+ 0x100ded4f 0x1 _g_zPHY_RFQuickAdjTxoffsetFlag
+ .data 0x100ded50 0x58 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x100ded50 0x28 _g_zPHY_Int0HandleCfg
+ 0x100ded78 0x18 _g_zPHY_Int1HandleCfg
+ 0x100ded90 0x18 _g_zPHY_Int2HandleCfg
+ .data 0x100deda8 0x12 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc.o)
+ .data 0x100dedba 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x100dedba 0x1 _G_ZPHY_WORD32_BYTENUM
+ 0x100dedbb 0x1 _G_ZPHY_T_EngPrintMsg_BYTENUM
+ 0x100dedbc 0x1 _G_ZPHY_SIZEOF_WORD32
+ 0x100dedbd 0x1 _G_ZPHY_SIZEOF_WORD16
+ 0x100dedbe 0x1 _G_ZPHY_SIZEOF_T_EngPrintMsg
+ 0x100dedbf 0x1 _G_ZPHY_SIZEOF_T_EngLogHeader
+ 0x100dedc0 0x1 _g_bL1lLogOutUsing
+ .data 0x100dedc1 0x14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pdcch.o)
+ .data 0x100dedd5 0x5d3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x100dedd5 0x60 _G_AC_UL_MODULE_CODE_SCHEME
+ 0x100dee35 0x4 _G_AC_ULS_RV_VALUE
+ 0x100dee39 0x234 _G_AW_ULS_TURBO_INTERLEAVER
+ 0x100df06d 0x46 _G_AC_UL_TDD_HARQ_ID_DATABASE
+ 0x100df0b3 0xa _G_AC_UL_FDD_HARQ_ID_DATABASE
+ 0x100df0bd 0x46 _G_AC_UL_NORM_HARQ_PUSCH_KVALUE
+ 0x100df103 0x46 _G_AC_UL_NORM_HARQ_PHICH_KVALUE
+ 0x100df149 0x46 _G_AC_UL_SPS_SUBFRAMOFFSET
+ 0x100df18f 0x46 _G_AC_UL_PRE_UL_SUBFRAME
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+ 0x100df225 0xa _G_AC_UL_NEXT_UL_SUBFRAME_FDD
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+ 0x100df3a6 0x1 _g_bIsRarNewTrans
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+ 0x100df407 0x1 _g_ReadTpFlagCnt
+ 0x100df408 0x1 _g_sdAtCtl_TxPowerValue
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+ .data 0x100df41d 0x2e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x100df445 0x1 _g_wL1eRxCrsIIRInd
+ 0x100df446 0x1 _g_wBchUseSoftNoFlag
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+ 0x100df449 0x2 _g_sdwRxTemp2
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+ .data 0x100df45b 0x24c0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
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+ 0x100df4a1 0x1e _g_ac_zPHY_edls_NcpSpeSubfrmCfg
+ 0x100df4bf 0x1b _g_ac_zPHY_edls_EcpSpeSubfrmCfg
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+ 0x100df4de 0x4 _g_ac_zPHY_edls_DeltaShiftBw4
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+ 0x100df5df 0x1a _g_ac_zPHY_edls_PrbIndexTabBw2
+ 0x100df5f9 0x10 _g_ac_zPHY_edls_PrbIndexTabBw1
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+ 0x100df6d1 0xc8 _g_ac_zPHY_edls_VrbTabBw5Gap2
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+ 0x100df82f 0x96 _g_ac_zPHY_edls_VrbTabBw4Gap2
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+ 0x100df929 0x64 _g_ac_zPHY_edls_VrbTabBw3Gap2
+ 0x100df98d 0x32 _g_ac_zPHY_edls_VrbTabBw2Gap1
+ 0x100df9bf 0x1e _g_ac_zPHY_edls_VrbTabBw1Gap1
+ 0x100df9dd 0xc _g_ac_zPHY_edls_VrbTabBw0Gap1
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+ 0x100e133d 0xbc _g_aw_zPHY_edls_TurboParaK
+ 0x100e13f9 0x20 _g_aw_zPHY_edls_PcInfoAnt2Dci2
+ 0x100e1419 0x100 _g_aw_zPHY_edls_PcInfoAnt4Dci2
+ 0x100e1519 0x8 _g_ac_zPHY_edls_PcInfoAnt4Dci2A
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+ 0x100e1528 0x7 _g_ac_zPHY_edls_DlHarqProNumMin
+ 0x100e152f 0x46 _g_ac_zPHY_edls_TddDlHarqCapM
+ 0x100e1575 0x46 _g_ac_zPHY_edls_TddDlHarqCapM_TddFddCA
+ 0x100e15bb 0x46 _g_ac_zPHY_edls_TddDlHarqTiming
+ 0x100e1601 0x46 _g_ac_zPHY_edls_TddDlHarqTiming_TddFddCA
+ 0x100e1647 0x46 _g_ac_zPHY_edls_TddDlHarqOrder
+ 0x100e168d 0x46 _g_ac_zPHY_edls_TddDlHarqOrder_TddFddCA
+ 0x100e16d3 0x46 _g_ac_zPHY_edls_TddDlHarqSetK
+ 0x100e1719 0xa _g_ac_zPHY_edls_FddDlHarqTiming
+ 0x100e1723 0x8 _awRohAPowerTable1ForSinglePort
+ 0x100e172b 0xa _awRohAPowerTable1
+ 0x100e1735 0x8 _awRohAVoltageTable1SinglePort
+ 0x100e173d 0xa _awRohAVoltageTable1
+ 0x100e1747 0x20 _awRohBPowerTable1ForSinglePort
+ 0x100e1767 0x20 _awRohBVoltageTable1SinglePort
+ 0x100e1787 0x28 _awRohBPowerTable2
+ 0x100e17af 0x28 _awRohBVoltageTable2
+ 0x100e17d7 0xa _awRohAPowerTable2
+ 0x100e17e1 0xa _awRohAVoltageTable2
+ 0x100e17eb 0x28 _awRohBPowerTable4
+ 0x100e1813 0x28 _awRohBVoltageTable4
+ 0x100e183b 0x8 _g_wLteL1MultiPortPA3dBRouAPow
+ 0x100e1843 0x20 _g_wLteL1MultiPortPA3dBRouBPow
+ 0x100e1863 0x8 _g_wLteL1MultiPortPA3dBRouAVol
+ 0x100e186b 0x20 _g_wLteL1MultiPortPA3dBRouBVol
+ 0x100e188b 0x8 _g_wLteL1MultiPortPA6dBRouAPow
+ 0x100e1893 0x20 _g_wLteL1MultiPortPA6dBRouBPow
+ 0x100e18b3 0x8 _g_wLteL1MultiPortPA6dBRouAVol
+ 0x100e18bb 0x20 _g_wLteL1MultiPortPA6dBRouBVol
+ 0x100e18db 0x20 _g_wLteL1MultiPortPA6dBRouBVolTable
+ 0x100e18fb 0x20 _g_wLteL1MultiPortPA6dBRouBPowTable
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+ .data 0x100e191f 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ .data 0x100e1929 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .data 0x100e192b 0x27c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x100e192b 0x13 _g_tzPHY_eulpc_At2UlPc
+ 0x100e193e 0x2 _g_zPHY_emc_dwIcpArm1CtrlInfoRegAddr
+ 0x100e1940 0x266 _g_ateMcMsgTable
+ 0x100e1ba6 0x1 _g_bPchReportFlag
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+ 0x100e1bc3 0x4 _g_zPHY_tLpcPwrDomainState
+ .data 0x100e1bc7 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tx.o)
+ .data 0x100e1bd5 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_meas.o)
+ *fill* 0x100e1bd7 0x80000001 00
+ .data 0x100e1bd8 0xa82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x100e1bd8 0x800 _g_adw_Drv_Rx_CosineCoeff
+ 0x100e23d8 0x31 _g_aw_Drv_Rx_FiTriangleCoeff
+ 0x100e2409 0x62 _g_adw_Drv_Rx_FixedFirCoeff
+ 0x100e246b 0x62 _g_adw_Drv_Rx_Eicic_FixedFirCoeff
+ 0x100e24cd 0x62 _g_adw_Drv_Rx_FixFirCoeff_16QAM
+ 0x100e252f 0x62 _g_adw_Drv_Rx_FixFirCoeff_64QAM
+ 0x100e2591 0x62 _g_aw_Drv_FiCoeffPrbBundling
+ 0x100e25f3 0x66 _g_adwL1eDrvRxMbsfnFirCoeff
+ 0x100e2659 0x1 _g_wL1eDrvRxFirCoeffFormatInd
+ .data 0x100e265a 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_utr.o)
+ .data 0x100e265c 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_pbch.o)
+ .data 0x100e2660 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_cdtr.o)
+ *fill* 0x100e2666 0x80000002 00
+ .data 0x100e2668 0x229 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x100e2668 0x80 _g_zPHY_erfc_atDBBMainSyncEvent
+ 0x100e26e8 0x80 _g_zPHY_erfc_atDBBMeas0Event
+ 0x100e2768 0x20 _g_zPHY_erfc_atDBBTxSendEvent
+ 0x100e2788 0x24 _g_zPHY_erfc_SubframeStartAddr
+ 0x100e27ac 0x24 _g_zPHY_erfc_SubframeDDRBackUpStartAddr
+ 0x100e27d0 0x8 _g_atzPHY_erfc_TuRegTxEvent
+ 0x100e27d8 0xb9 _g_atzPHY_erfc_TuRamTxEvent
+ *fill* 0x100e2891 0x80000003 00
+ .data 0x100e2894 0xb54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x100e2894 0x400 _g_atzPHY_erfc_atRFABBMainSyncEvent
+ 0x100e2c94 0x200 _g_atzPHY_erfc_atRFABBMeas0Event
+ 0x100e2e94 0x554 _g_atzPHY_erfc_atRFABBTxSendEvent
+ .data 0x100e33e8 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x100e33e8 0x1 _g_zPHY_erfc_cTddOrFddTemp
+ 0x100e33e9 0x1 _g_zPHY_erfc_cTddOrFddSel
+ 0x100e33ea 0x1 _g_zPHY_erfc_cTddOrFddlast
+ .data 0x100e33eb 0x3a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x100e33ef 0x14 _AWNCPSUBFRMPATREGVALUE
+ 0x100e3403 0x22 _AWDFEECPSUBFRMPATREGVALUE
+ .data 0x100e3425 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x100e3425 0x2 _xlb_g_zPHY_SID
+ .data 0x100e3427 0x2e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x100e3427 0x2e _g_azPHY_ecsrc_abFilterFactor
+ .data 0x100e3455 0xf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x100e3455 0x2 _ptrSib1Req
+ 0x100e3457 0x2 _ptrSiReq
+ 0x100e3459 0x2 _gSirMrtr
+ 0x100e345b 0x2 _g_zPHY_emc_TpuUpdateSemId4SI
+ 0x100e345d 0x1 _g_wSibPrintCtrlCnt
+ 0x100e345e 0x1 _g_wSiPreSyncFlag
+ 0x100e345f 0x1 _g_wSiPreSchedFlag
+ 0x100e3460 0x1 _g_L1e_wAbortSiMsgProc
+ 0x100e3461 0x1 _g_L1e_wSiDelayProc
+ 0x100e3462 0x1 _g_wAnrBchFailInd
+ 0x100e3463 0x1 _g_wAnrBchSuccInd
+ .data 0x100e3464 0x16f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x100e3464 0x1 _g_bDrxLowCtrlFg
+ 0x100e3465 0xa _g_wRegTpuMsgId
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+ 0x100e34bf 0x103 _G_ZPS_LTE_ASYNMSG_NUM
+ 0x100e35c2 0x1 _g_zPHY_emc_tCpMode
+ 0x100e35c3 0x1 _g_zPHY_emc_bPagingPoAndGapConflictFlag
+ 0x100e35c4 0x1 _g_zPHY_emc_bPagingPoCallBackFlag
+ 0x100e35c5 0x1 _gwUe4RxRcvFalg
+ 0x100e35c6 0x1 _g_zPHY_emc_bRfcETCSuspendFlag
+ 0x100e35c7 0x2 _g_zPHY_emc_TpuUpdateSemId4Com
+ 0x100e35c9 0x2 _g_zPHY_emc_TpuUpdateSemId4HO
+ 0x100e35cb 0x2 _g_zPHY_emc_TpuUpdateSemId4PreSync
+ 0x100e35cd 0x1 _g_bMaxTimeAdvance
+ 0x100e35ce 0x1 _g_wFreqAbortcellsearchConflictTimer
+ 0x100e35cf 0x1 _wCommInSiProc
+ 0x100e35d0 0x2 _dwLastRxoffset
+ 0x100e35d2 0x1 _g_wDelayAnrCnt
+ .data 0x100e35d3 0x1081 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x100e35d3 0x8 _g_zPHY_SearchPeriod
+ 0x100e35db 0x39c _g_zPHY_ecsrc_tEarfcnTable
+ 0x100e3977 0x42 _s_awzPHY_CsrcEarfcnMInBandTable
+ 0x100e39b9 0xa5 _g_adwCsrcTpuEventTable
+ 0x100e3a5e 0x4 _g_awPiSearchPeriod
+ 0x100e3a62 0x4 _g_awPiSearchPeriodAT
+ 0x100e3a66 0x4 _g_awPiSearchPeriodPerDrx
+ 0x100e3a6a 0x4 _g_awPiSearchPeriodSpeed
+ 0x100e3a6e 0x4 _g_awPiSearchPeriodFixStrong
+ 0x100e3a72 0x4 _g_awMovCtxSchPeriod
+ 0x100e3a76 0x4 _g_awCfoUpdatePeriod
+ 0x100e3a7a 0x60 _g_atCsrEventManage
+ 0x100e3ada 0x5a _g_L1e_C0_UtcInfo
+ 0x100e3b34 0x8 _DelaySteps
+ 0x100e3b3c 0x67 _Delay
+ 0x100e3ba3 0x20 _SchedServCellSteps
+ 0x100e3bc3 0x67 _SchedServCell
+ 0x100e3c2a 0x8 _AdjustBndFrmCfoSteps
+ 0x100e3c32 0x67 _AdjustBndFrmCfo
+ 0x100e3c99 0x14 _SchedOneFreqSteps
+ 0x100e3cad 0x67 _SchedOneFreq
+ 0x100e3d14 0xc _SchedIntraSteps
+ 0x100e3d20 0x67 _SchedIntra
+ 0x100e3d87 0x18 _SchedInterSteps
+ 0x100e3d9f 0x67 _SchedInter
+ 0x100e3e06 0x4 _SchedInitSteps
+ 0x100e3e0a 0x67 _SchedInit
+ 0x100e3e71 0x28 _SchedIdleSteps
+ 0x100e3e99 0x67 _SchedIdle
+ 0x100e3f00 0x1 _g_bCsrPlmnStatusFlagNew
+ 0x100e3f01 0x1 _g_csrc_wSearchInFreqscanState
+ 0x100e3f02 0x1 _g_zPHY_ecsrc_bNeedAdjustBndFrmCfo
+ 0x100e3f03 0x1 _g_zPHY_Csrc_bConnSetInterFg
+ 0x100e3f04 0x2 _g_AtZepcgSetLowPower
+ 0x100e3f06 0x63f _g_SchedContext
+ 0x100e4545 0x10f _g_ThreadCsrc
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+ 0x100e4654 0x180 _G_AC_RA_RESR_CFG_FDD
+ 0x100e47d4 0x80 _G_AC_RA_RESR_CFG_TDD1
+ 0x100e4854 0x43d _G_AC_RA_RESR_CFG_TDD2
+ 0x100e4c91 0x20 _G_AW_NCS_VAL_FORMAT0TO3
+ 0x100e4cb1 0x10 _G_AW_NCS_VAL_FORMAT4
+ 0x100e4cc1 0x346 _G_AW_P_VAL_FORMAT0TO3
+ 0x100e5007 0x8a _G_AW_P_VAL_FORMAT4
+ 0x100e5091 0x5 _G_ASC_DELTA_PREAMBLE_VAL
+ 0x100e5096 0x8 _G_ASC_MSG_POWOFFSET_GROUPB
+ 0x100e509e 0x6 _G_AW_RA_BASEBAND_PARAS_1_4
+ 0x100e50a4 0x6 _G_AW_RA_BASEBAND_PARAS_3
+ 0x100e50aa 0x6 _G_AW_RA_BASEBAND_PARAS_5
+ 0x100e50b0 0x6 _G_AW_RA_BASEBAND_PARAS_10
+ 0x100e50b6 0x6 _G_AW_RA_BASEBAND_PARAS_15_20
+ 0x100e50bc 0x6 _G_AW_RA_BASEBAND_PARAS
+ 0x100e50c2 0x5 _G_AC_PREAMBLE_LENGTH
+ 0x100e50c7 0x10 _G_AW_BI_VALUE
+ 0x100e50d7 0x24 _G_AC_FID_VALUE_FORMAT0TO3
+ 0x100e50fb 0x39 _g_zPHY_erapc_tCtrlBlock
+ .data 0x100e5134 0x46e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x100e5134 0x1 _g_zPHY_emulm_PlmnSearchMeasFlag
+ 0x100e5135 0x2 _g_azPHY_emulm_UsedGapCount
+ 0x100e5137 0x18 _MulmCsAgcSteps
+ 0x100e514f 0x67 _MulmCsAgc
+ 0x100e51b6 0x18 _MulmCsPssSteps
+ 0x100e51ce 0x67 _MulmCsPss
+ 0x100e5235 0xc _MulmCsTpuAdjType1Steps
+ 0x100e5241 0x67 _MulmCsTpuAdjType1
+ 0x100e52a8 0xc _MulmCsTpuAdjType2Steps
+ 0x100e52b4 0x67 _MulmCsTpuAdjType2
+ 0x100e531b 0x14 _MulmCsCfoOnceSteps
+ 0x100e532f 0x67 _MulmCsCfoOnce
+ 0x100e5396 0x14 _MulmCsCfoSteps
+ 0x100e53aa 0x67 _MulmCsCfo
+ 0x100e5411 0x18 _MulmCsSssSteps
+ 0x100e5429 0x67 _MulmCsSss
+ 0x100e5490 0x34 _MulmCellSearchOnceSteps
+ 0x100e54c4 0x67 _MulmCellSearchOnce
+ 0x100e552b 0xc _MulmCellSearchProcSteps
+ 0x100e5537 0x67 _MulmCellSearchProc
+ 0x100e559e 0x1 _g_eCsrsTpuAdjStep
+ 0x100e559f 0x1 _g_L1e_mulm_SatisfyFlag
+ 0x100e55a0 0x1 _g_L1e_mulm_SlaveLpcFlagCnt
+ 0x100e55a1 0x1 _g_bMulmConnectedAbortGapFlag
+ .data 0x100e55a2 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ .data 0x100e55b0 0x1e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_proc.o)
+ .data 0x100e55ce 0xc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ 0x100e55ce 0x6 _g_awL1eFddMbsfnSubfNumTab
+ 0x100e55d4 0x6 _g_awL1eTddMbsfnSubfNumTab
+ .data 0x100e55da 0x5 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x100e55da 0x1 _g_wDrxUnActiveFlag
+ 0x100e55db 0x1 _g_wDrxActiveFlag
+ 0x100e55dc 0x1 _g_zPHY_emc_bDediHoReveFlag
+ 0x100e55dd 0x1 _g_zPHY_emc_bDrxActvieFlag
+ 0x100e55de 0x1 _g_wLastPreSyncAbsSubf
+ .data 0x100e55df 0x194 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x100e55df 0x2 _g_zPHY_AMT_Tool_Agc_Open
+ 0x100e55e1 0x4 _g_tLteAmtAfc
+ 0x100e55e5 0x186 _g_zPHY_tCurrentBandCtrlInfo
+ 0x100e576b 0x2 _ptLteAmtFdtParameter
+ 0x100e576d 0x2 _g_tLteAmtFdtParameter
+ 0x100e576f 0x2 _ptLteAmtFstParameter
+ 0x100e5771 0x2 _g_tLteAmtFstParameter
+ .data 0x100e5773 0x40 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_func.o)
+ 0x100e57ac 0x1 _g_sbFixTaAutoAdjFlg
+ 0x100e57ad 0x2 _g_dwRaPIDNotMatchCnt
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+ 0x100e67ff 0x6 _g_aw_zPHY_FDD_DCI01APadding_COM
+ 0x100e6805 0x6 _g_aw_zPHY_DCI_1C_COM
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+ 0x100e72b4 0x2 _g_ptTi_Ctl
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+ 0x100e7450 0xbe _GainValueConfig_TDD
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+ 0x100e75cc 0x7 _g_pcZcosVersion
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+ 0x100e75d3 0x4 _gtHuntList
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+ 0x100e75d7 0x2 _efuseMutex
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+ 0x100e77b0 0x2 LONG 0xa (SIZEOF (.d2tcm_s) / 0x2)
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+
+.display
+ *(.display_data_buffer)
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+
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+ .bss 0x100f0b70 0x392 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_bch.o)
+ .bss 0x100f0f02 0x43a T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cs.o)
+ .bss 0x100f133c 0x3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_gap.o)
+ .bss 0x100f133f 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsdpa.o)
+ .bss 0x100f1340 0x259c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_fs.o)
+ .bss 0x100f38dc 0x1d2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ .bss 0x100f3aae 0x564 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rm.o)
+ .bss 0x100f4012 0x1e1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ .bss 0x100f41f3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ .bss 0x100f41f4 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ .bss 0x100f41f7 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ .bss 0x100f41fd 0x981 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ .bss 0x100f4b7e 0x24 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ .bss 0x100f4ba2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ .bss 0x100f4ba3 0x82 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ .bss 0x100f4c25 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ *fill* 0x100f4c27 0x80000001 00
+ .bss 0x100f4c28 0x45 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ .bss 0x100f4c6d 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ .bss 0x100f4c70 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ .bss 0x100f4c72 0x4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ .bss 0x100f4c76 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ .bss 0x100f4c77 0x234 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ .bss 0x100f4eab 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ .bss 0x100f4eb3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ .bss 0x100f4eb4 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ .bss 0x100f4eb6 0x72 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mbs.o)
+ .bss 0x100f4f28 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ .bss 0x100f4f2a 0x50 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ .bss 0x100f4f7a 0x3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ .bss 0x100f4f7d 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ .bss 0x100f4f7e 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ .bss 0x100f4f80 0x34 C:/ZSP/ZView4.1.0/zspg2/libg3i2/libc.a(userIO.o)
+ *(COMMON)
+ COMMON 0x100f4fb4 0x6 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ 0x0 (size before relaxing)
+ 0x100f4fb4 0x6 _err_msg
+ COMMON 0x100f4fba 0x18f T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ 0x0 (size before relaxing)
+ 0x100f4fba 0x18f _odo_sys
+ COMMON 0x100f5149 0x44 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ 0x0 (size before relaxing)
+ 0x100f5149 0x1 _zsp_cmm_len
+ 0x100f514a 0x5 _g_L1ErrInfo
+ 0x100f514f 0x3e _zsp_ramdump_regs
+ COMMON 0x100f518d 0x364 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x0 (size before relaxing)
+ 0x100f518d 0x1 _g_erfc_cnt
+ 0x100f518e 0x302 _g_atHookInfo
+ 0x100f5490 0x60 _g_erfc_tpu
+ 0x100f54f0 0x1 _gIramHookCnt
+ COMMON 0x100f54f1 0x1c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ 0x0 (size before relaxing)
+ 0x100f54f1 0x1 _g_wRficRev
+ 0x100f54f2 0x1b _g_awTempDAC
+ COMMON 0x100f550d 0x1a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x0 (size before relaxing)
+ 0x100f550d 0x1a _g_tL1wCallStackInfo
+ COMMON 0x100f5527 0x1 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ 0x0 (size before relaxing)
+ 0x100f5527 0x1 _g_uComPhyFunc
+ COMMON 0x100f5528 0xd00 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ 0x0 (size before relaxing)
+ 0x100f5528 0x100 _gReadBlockCnt
+ 0x100f5628 0x100 _RpMsgRead_Exit
+ 0x100f5728 0x100 _gWriteBlockCnt
+ 0x100f5828 0x100 _gRpMsgWriteMutex
+ 0x100f5928 0x100 _s_RpMsgCallbackList
+ 0x100f5a28 0x300 _phy2ps_chinfo
+ 0x100f5d28 0x100 _rpMsgSem
+ 0x100f5e28 0x300 _ps2phy_chinfo
+ 0x100f6128 0x100 _gRpMsgReadMutex
+ COMMON 0x100f6228 0x9 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x0 (size before relaxing)
+ 0x100f6228 0x2 _g_L1_tModeState
+ 0x100f622a 0x6 _g_L1_tLpmCaliTime
+ 0x100f6230 0x1 _g_L1_tLpCalibrationFlag
+ COMMON 0x100f6231 0xd T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sys_task.o)
+ 0x0 (size before relaxing)
+ 0x100f6231 0x9 _g_L1wPriTaskPid
+ 0x100f623a 0x4 _g_L1wIsrTaskPid
+ COMMON 0x100f623e 0xc9e6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_nv_data.o)
+ 0x0 (size before relaxing)
+ 0x100f623e 0xbec _g_tWcdmaUserNv
+ 0x100f6e2a 0x22c _g_tL1wNvBb
+ 0x100f7056 0xbbca _g_tWcdmaCalibNv
+ 0x10102c20 0x4 _g_tL1wAtNv
+ COMMON 0x10102c24 0x427 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_meas.o)
+ 0x0 (size before relaxing)
+ 0x10102c24 0x3eb _g_tL1wDevMeasInfo
+ 0x1010300f 0x3c _g_atMeasSpsrInfo
+ COMMON 0x1010304b 0x5b3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hspa.o)
+ 0x0 (size before relaxing)
+ 0x1010304b 0x4e4 _s_tL1wDevHsupaInfo
+ 0x1010352f 0xcf _g_PsrUpdateReq
+ COMMON 0x101035fe 0x3d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc.o)
+ 0x0 (size before relaxing)
+ 0x101035fe 0x1 _g_SSC_CFLT_chip
+ 0x101035ff 0x14 _g_tRfcNotchInfo
+ 0x10103613 0x24 _g_tWRfcRpiPwrCtl
+ 0x10103637 0x1 _g_wRfcResetState
+ 0x10103638 0x1 _g_SSC_CFLT_ssfn
+ 0x10103639 0x2 _g_zPHYRfcSSCDebugCnt
+ COMMON 0x1010363b 0x13e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_dpch.o)
+ 0x0 (size before relaxing)
+ 0x1010363b 0x48 _tPcDataDb
+ 0x10103683 0x62 _tPcCnt
+ 0x101036e5 0x94 _g_tPcDpchSirCalInfo
+ COMMON 0x10103779 0x113 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa.o)
+ 0x0 (size before relaxing)
+ 0x10103779 0x2 _g_Rt
+ 0x1010377b 0x11 _g_tL1wHsdpaSnrAdjInfo
+ 0x1010378c 0x36 _g_tHsdpaAdrIcRstInfo
+ 0x101037c2 0x6 _g_tL1wHsdpaDbgInfo
+ 0x101037c8 0x78 _g_tL1wHsdpaPacketInfo
+ 0x10103840 0x19 _g_tHsdpaIcFingerDiffInfo
+ 0x10103859 0x1 _g_wAdrIcEn
+ 0x1010385a 0x26 _g_tL1wHsdpaCodingInfo
+ 0x10103880 0x1 _g_wL1wHsdpaRxDivMode
+ 0x10103881 0xb _g_tHsdpaResetInfo
+ COMMON 0x1010388c 0x191 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_plus.o)
+ 0x0 (size before relaxing)
+ 0x1010388c 0x168 _g_atLessDecodeCfg
+ 0x101039f4 0x28 _g_atLessDemoluleCfg
+ 0x10103a1c 0x1 _g_wL1wLessCfgIdx
+ COMMON 0x10103a1d 0x1b6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tx_rf_res.o)
+ 0x0 (size before relaxing)
+ 0x10103a1d 0x1b6 _g_tUlRfTbl
+ COMMON 0x10103bd3 0x26c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_dpch.o)
+ 0x0 (size before relaxing)
+ 0x10103bd3 0x26c _g_tWuldataBuf
+ COMMON 0x10103e3f 0x624 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_calc.o)
+ 0x0 (size before relaxing)
+ 0x10103e3f 0x604 _g_uLSfInfo
+ 0x10104443 0x20 _g_atL1wHsupaFirstTranPara
+ COMMON 0x10104463 0xd06 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rfc_db.o)
+ 0x0 (size before relaxing)
+ 0x10104463 0x12 _g_tRfcPowerAdcReadInfo
+ 0x10104475 0x5a _g_atRfcAgcDbLog
+ 0x101044cf 0x1 _g_eAntSel
+ 0x101044d0 0x1 _g_bNvCheck
+ 0x101044d1 0x1 _g_wRfcTxRxState
+ 0x101044d2 0x318 _g_tRfcCtrlDbRx
+ 0x101047ea 0x26 _g_tRfcGapMixLog
+ 0x10104810 0x5df _g_tRfcAgcDb
+ 0x10104def 0x1e _g_atRfcStateLog
+ 0x10104e0d 0x1 _g_eDivState
+ 0x10104e0e 0xb _g_tRfcAfcDb
+ 0x10104e19 0x1 _g_eAntState
+ 0x10104e1a 0x318 _g_tRfcCtrlDbTx
+ 0x10105132 0x23 _g_tRfcCmnInfoLOG
+ 0x10105155 0xe _g_tRfcTxPowLog
+ 0x10105163 0x5 _g_tRfcTmpReadInfo
+ 0x10105168 0x1 _g_eRfcRamState
+ COMMON 0x10105169 0x1f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_calc.o)
+ 0x0 (size before relaxing)
+ 0x10105169 0x4 _g_wAdrIcCellState
+ 0x1010516d 0x1 _g_wL1wHsdpaSfnCfnSubFrmOffset
+ 0x1010516e 0x5 _g_awL1wHsdpaMvalue
+ 0x10105173 0x4 _g_wSubFrmOffset
+ 0x10105177 0x1 _g_wL1wHsdpaHsdpcchUldpcchOffset
+ 0x10105178 0xf _g_awL1wHsdpaCfnSlot2SfnSubFrm
+ 0x10105187 0x1 _g_wL1wHsdpaSfnCfnOffset
+ COMMON 0x10105188 0x2824 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_csr.o)
+ 0x0 (size before relaxing)
+ 0x10105188 0x24 _s_tCsStatisticInfo
+ 0x101051ac 0x2800 _dwPeakInfoInSlot
+ COMMON 0x101079ac 0xc5d T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc.o)
+ 0x0 (size before relaxing)
+ 0x101079ac 0x26 _g_tPcUphDb
+ 0x101079d2 0x3e _tDevEngStardardParam
+ 0x10107a10 0x559 _g_tPcOverEstDb
+ 0x10107f69 0x3e3 _tPcBetaDb
+ 0x1010834c 0xa _swPcTimeOff
+ 0x10108356 0x1 _wTimeOff
+ 0x10108357 0xa _swPcTimeOff2
+ 0x10108361 0x95 _tPcCalcDb
+ 0x101083f6 0x2 _g_tIqMappingCon
+ 0x101083f8 0x146 _tPcInfoDb
+ 0x1010853e 0xcb _tMprTest
+ COMMON 0x10108609 0x286 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_eng.o)
+ 0x0 (size before relaxing)
+ 0x10108609 0x4 _g_awL1wStandardMsgRpt
+ 0x1010860d 0x80 _g_awL1wPrintMsgProcRpt
+ 0x1010868d 0x2 _gL1w_MissLogInfo
+ 0x1010868f 0x200 _g_awL1wEngTempBuffer
+ COMMON 0x1010888f 0xb T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx_dtr.o)
+ 0x0 (size before relaxing)
+ 0x1010888f 0x5 _g_RxDataPn9Check
+ 0x10108894 0x2 _g_dwCfgSsfn
+ 0x10108896 0x1 _g_RxTtiNum
+ 0x10108897 0x1 _g_RxTfciNum
+ 0x10108898 0x2 _g_dwTtiSsfn
+ COMMON 0x1010889a 0x11c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa.o)
+ 0x0 (size before relaxing)
+ 0x1010889a 0xe _g_tWUpaStdlogStatisitcInfo
+ 0x101088a8 0x2 _g_EdchNewTbTotal
+ 0x101088aa 0x20 _g_atWHsupaEhichInfTab
+ 0x101088ca 0x1 _g_EagchCnt500Ms
+ 0x101088cb 0x38 _g_tWUpaStdlogPacketInfo
+ 0x10108903 0x2 _g_EdchTbTotal
+ 0x10108905 0x10 _g_atWHsupaEdchReadyFlag
+ 0x10108915 0x36 _g_tWUpaUlDebugInfo
+ 0x1010894b 0x6b _g_tWUpaDlDebugInfo
+ COMMON 0x101089b6 0x11b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_psr.o)
+ 0x0 (size before relaxing)
+ 0x101089b6 0xc _g_atL1wCellType
+ 0x101089c2 0x2f _g_tL1wMeasCellReq
+ 0x101089f1 0x24 _g_atL1wRlsTrace
+ 0x10108a15 0x8 _g_tL1wFmoDlsPsrParaConfig
+ 0x10108a1d 0x2 _g_tL1wPsrAntNumPara
+ 0x10108a1f 0x2 _g_dIntIndex
+ 0x10108a21 0xe _g_tL1wCmPsrPatternInfo
+ 0x10108a2f 0x1 _g_wL1wDpchOffset
+ 0x10108a30 0x2f _g_tL1wDchDlsLastReq
+ 0x10108a5f 0x2f _g_tL1wDchDlsPsrReq
+ 0x10108a8e 0x6 _g_asL1wAdujstFlag
+ 0x10108a94 0x4 _g_tL1wHsupaRlToPsr
+ 0x10108a98 0x7 _g_tL1wFachDlsPsrReq
+ 0x10108a9f 0x1 _g_sL1wUlAdujstFlag
+ 0x10108aa0 0x2 _g_dOldUlTiming
+ 0x10108aa2 0x2f _g_tL1wDpaRlReqInfo
+ COMMON 0x10108ad1 0xec T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x0 (size before relaxing)
+ 0x10108ad1 0xe8 _g_tResInfo
+ 0x10108bb9 0x4 _g_tSendIcpTpuTime
+ COMMON 0x10108bbd 0x163 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_dls_afc.o)
+ 0x0 (size before relaxing)
+ 0x10108bbd 0x106 _g_tL1wAfcFreqOffsetValue
+ 0x10108cc3 0x30 _g_atL1wRxHistoryIQBuffer
+ 0x10108cf3 0x3 _g_tAfcErrorPrint
+ 0x10108cf6 0x20 _g_tL1wAfcWorkPara
+ 0x10108d16 0x6 _g_tL1wSlaveAfcWorkPara
+ 0x10108d1c 0x4 _g_tL1wBchDataHistoryIQValue
+ COMMON 0x10108d20 0xe47 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_tpu.o)
+ 0x0 (size before relaxing)
+ 0x10108d20 0x1a _g_adL1wTpuTaskID
+ 0x10108d3a 0x235 _g_atL1wTpuRegRtVarEventInfo
+ 0x10108f6f 0x4db _g_atL1wTpuRegNtVarEventInfo
+ 0x1010944a 0x4 _g_tL1wTpuLastMicroAdjustInfo
+ 0x1010944e 0x1 _g_wL1wTpuDoffVal
+ 0x1010944f 0x8 _g_tL1wTpuFrmInfo
+ 0x10109457 0x710 _g_atL1wTpuRegNtFixedEventInfo
+ *fill* 0x10109b67 0x80000001 00
+ COMMON 0x10109b68 0x427f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_db.o)
+ 0x0 (size before relaxing)
+ 0x10109b68 0x7c _g_tL1wDevDbHsdpaCfgReqB
+ 0x10109be4 0x7a _g_atDevBchAfcdb
+ 0x10109c5e 0x3d6 _g_tL1wDevDbUlDpchCfgReqA
+ 0x1010a034 0x7c _g_tL1wDevDbHsdpaCfgReqA
+ 0x1010a0b0 0x41c _g_tL1wDevDbRtxIscpInfo
+ 0x1010a4cc 0x4 _g_tL1wDevDbRaMacProcReq
+ 0x1010a4d0 0x7e _g_tL1wDevDbDlFdpchCfgReqA
+ 0x1010a54e 0xf8 _g_tDevDbHsupaCfgReqB
+ 0x1010a646 0x382 _g_tL1wDevDbPageFachCfgReq
+ 0x1010a9c8 0x2 _g_tL1wDevDbTrchTtiInfo
+ 0x1010a9ca 0xf8 _g_tDevDbHsupaCfgReqA
+ 0x1010aac2 0x39a _g_tL1wDevDbRaEraRrcReq
+ 0x1010ae5c 0x5 _g_tL1wDevDbHsdpaInd
+ 0x1010ae61 0x880 _g_tDevDbHsdpaFingMaskBuffer
+ 0x1010b6e1 0x27 _g_tDevDbHspaToMacInfo
+ 0x1010b708 0x200 _g_tDevDbHsdpaAdrCirData
+ 0x1010b908 0x1a70 _g_tL1wDevDbRtxAfcInfo
+ 0x1010d378 0xb _g_tDevDbHsdpaAntSwitch
+ 0x1010d383 0x62 _g_tL1wDevDbHsdpaPlusPchCfgReq
+ 0x1010d3e5 0x4be _g_tL1wDevDbDlDpchCfgReqA
+ 0x1010d8a3 0x544 _g_tWDevDbHspaPlusFachCfgReq
+ COMMON 0x1010dde7 0x85 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010dde7 0x3b _g_tRxEng
+ 0x1010de22 0x4a _g_tDlCpchEng
+ COMMON 0x1010de6c 0x86 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc_dfe.o)
+ 0x0 (size before relaxing)
+ 0x1010de6c 0x4 _g_tRfcIQInfo
+ 0x1010de70 0x2 _g_sdAnt0CarrierPhase
+ 0x1010de72 0x78 _g_atRfcDcLog
+ 0x1010deea 0x2 _g_sdAnt1CarrierPhase
+ 0x1010deec 0x4 _g_tRfcDcInfo
+ 0x1010def0 0x2 _g_tRfcDagcGain
+ COMMON 0x1010def2 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_top.o)
+ 0x0 (size before relaxing)
+ 0x1010def2 0x38 _g_TopRegLpcSave
+ COMMON 0x1010df2a 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_tpu.o)
+ 0x0 (size before relaxing)
+ 0x1010df2a 0xa _g_wTpuRtRegLpcSave
+ 0x1010df34 0x36 _g_wTpuNtRegLpcSave
+ COMMON 0x1010df6a 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_meas.o)
+ 0x0 (size before relaxing)
+ 0x1010df6a 0xd0 _g_atL1wDrvMeasResultInfo
+ COMMON 0x1010e03a 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_dpram.o)
+ 0x0 (size before relaxing)
+ 0x1010e03a 0x2 _g_dL1wDprICPSSFN
+ 0x1010e03c 0x1 _g_wLastSubframe
+ 0x1010e03d 0x1 _g_wL1wDprModState
+ 0x1010e03e 0x26 _g_tL1wDrvDpramStruct
+ 0x1010e064 0x2 _g_dL1wDprResetCnfSSFN
+ 0x1010e066 0x2 _g_wL1wDprSubFrmCnt
+ 0x1010e068 0xa _g_awReportCFN
+ COMMON 0x1010e072 0x808 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010e072 0x808 _s_tDrvRxCfg
+ COMMON 0x1010e87a 0x7b8 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010e87a 0x7b8 _g_tRegRxRakeReg
+ COMMON 0x1010f032 0x7 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_rfc.o)
+ 0x0 (size before relaxing)
+ 0x1010f032 0x1 _wLastBand
+ 0x1010f033 0x2 _g_l1wATSetAPCTmpCmpVal
+ 0x1010f035 0x2 _g_l1wATOriAPCTmpCmpVal
+ 0x1010f037 0x2 _g_l1wATSetAPCFlag
+ COMMON 0x1010f039 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_drv_hsdpa.o)
+ 0x0 (size before relaxing)
+ 0x1010f039 0x1 _g_TxCfgOver
+ 0x1010f03a 0x1 _g_TpuCfgOver
+ COMMON 0x1010f03b 0x415 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_main.o)
+ 0x0 (size before relaxing)
+ 0x1010f03b 0x3a _g_tRfcDrvOpen
+ 0x1010f075 0x1 _g_wRfOpCnt
+ 0x1010f076 0x3a _g_atLastRfcOpen
+ 0x1010f0b0 0x3a0 _g_atRfcOpen
+ COMMON 0x1010f450 0xa3 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_meas_db.o)
+ 0x0 (size before relaxing)
+ 0x1010f450 0xa3 _g_tL1wInnerCellDb
+ COMMON 0x1010f4f3 0x8f T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_fsm.o)
+ 0x0 (size before relaxing)
+ 0x1010f4f3 0x19 _g_tL1wCtrlDb
+ 0x1010f50c 0x1c _g_tL1MainMixInfo
+ 0x1010f528 0x1 _g_eL1wAmtL1sStateInfo
+ 0x1010f529 0x1a _g_tL1wStateCnt
+ 0x1010f543 0x3f _g_tL1wProcSetDb
+ COMMON 0x1010f582 0xf4 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_db.o)
+ 0x0 (size before relaxing)
+ 0x1010f582 0x1 _g_wBackupCellMainIdx
+ 0x1010f583 0x79 _g_tServCellDb
+ 0x1010f5fc 0x60 _g_atBackupCellInfo
+ 0x1010f65c 0x1a _g_tL1wAddionCtrl
+ COMMON 0x1010f676 0xa1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hsupa.o)
+ 0x0 (size before relaxing)
+ 0x1010f676 0xa1 _g_tWL1sHsupaProcInfo
+ COMMON 0x1010f717 0x350 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_cm.o)
+ 0x0 (size before relaxing)
+ 0x1010f717 0x5a _g_tL1wCmCfnN0123Bitmap
+ 0x1010f771 0x78 _g_atL1wCmWaitCfgPatternDB
+ 0x1010f7e9 0x5a _g_tL1wCmCfnN0123BitmapTemp
+ 0x1010f843 0xdc _g_tL1wCmInnerInfo
+ 0x1010f91f 0xca _g_tL1wCmInfoForN4N9
+ 0x1010f9e9 0x7e _g_tL1wPsCmConfigBuffer
+ COMMON 0x1010fa67 0x339 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_res_alloc.o)
+ 0x0 (size before relaxing)
+ 0x1010fa67 0xa0 _g_atL1RfSegInfo
+ 0x1010fb07 0x4 _g_tTimerCnt
+ 0x1010fb0b 0x2 _g_tL1wResCtrl
+ 0x1010fb0d 0x28f _g_tL1wRfTbl
+ 0x1010fd9c 0x3 _g_tL1wResAgcCtrl
+ 0x1010fd9f 0x1 _g_wRfSegNum
+ COMMON 0x1010fda0 0x33 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_sched_proc_hspa.o)
+ 0x0 (size before relaxing)
+ 0x1010fda0 0x33 _g_tDchAscPara
+ COMMON 0x1010fdd3 0x2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_rtx_tx_prach.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd3 0x1 _g_RxRachAiNum
+ 0x1010fdd4 0x1 _g_RxAichIntCnt
+ COMMON 0x1010fdd5 0x1 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsdpa_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd5 0x1 _g_wMissHdtrInt
+ COMMON 0x1010fdd6 0x19 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_pc_ra.o)
+ 0x0 (size before relaxing)
+ 0x1010fdd6 0x5 _g_tPcPrachConfigInfo
+ 0x1010fddb 0x1 _g_swPrachSlotPower
+ 0x1010fddc 0x13 _g_tRtxPcPrachMessageInfo
+ COMMON 0x1010fdef 0x18 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_hsupa_rx.o)
+ 0x0 (size before relaxing)
+ 0x1010fdef 0x18 _g_atL1wHsupaDlCmPattern
+ COMMON 0x1010fe07 0x1d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_sys_init.o)
+ 0x0 (size before relaxing)
+ 0x1010fe07 0x4 _g_L1LteAIsrTaskPid
+ 0x1010fe0b 0x2 _g_pSemId_INTH1
+ 0x1010fe0d 0x11 _g_L1LteAPriTaskPid
+ 0x1010fe1e 0x2 _g_pSemId_ICP
+ 0x1010fe20 0x2 _g_pSemId_TXIntPulse
+ 0x1010fe22 0x2 _g_pSemId_INTH2
+ COMMON 0x1010fe24 0x2bf08 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_nv.o)
+ 0x0 (size before relaxing)
+ 0x1010fe24 0x8 _g_tUEIdInfo
+ 0x1010fe2c 0x28000 _g_zPHY_AMT_tNVInfo
+ 0x10137e2c 0x2540 _g_zPHY_tNVInfo
+ 0x1013a36c 0x198c _g_zPHY_tNV_user
+ 0x1013bcf8 0x2e _g_zPsPhyATNvLte
+ 0x1013bd26 0x6 _g_zPsPhyATNvcom
+ COMMON 0x1013bd2c 0xe5b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_log.o)
+ 0x0 (size before relaxing)
+ 0x1013bd2c 0x158 _g_EUL_SrsStatisticsInfo
+ 0x1013be84 0x136 _g_EDL_PDSCH_INFO
+ 0x1013bfba 0x2 _g_dwUlResidualBlerCount
+ 0x1013bfbc 0xb8 _g_EUL_CqiHarqSimulStatisticsInfo
+ 0x1013c074 0x2 _g_EDL_PA_INFO
+ 0x1013c076 0xc _g_UL_SrHarqSimulStatisticsInfo
+ 0x1013c082 0x2a _g_UE_BASE_INFO
+ 0x1013c0ac 0x4 _g_dwTxThroughPutBps
+ 0x1013c0b0 0x72 _g_EDL_PCFICH_INFO
+ 0x1013c122 0x82 _g_EUL_Dci0Info
+ 0x1013c1a4 0x10e _g_EDL_PHICH_INFO
+ 0x1013c2b2 0x4 _g_dwUlNewTransCount
+ 0x1013c2b6 0x8 _g_EUL_DCI3Or3AInfo
+ 0x1013c2be 0x230 _g_EDL_DCI_INFO
+ 0x1013c4ee 0x4 _g_dwRxThroughPutBps
+ 0x1013c4f2 0x40 _g_EDL_CALC_For_SINR
+ 0x1013c532 0x12 _g_EDLUL_FLOW_INFO
+ 0x1013c544 0x20 _g_EUL_PucchFmtStatisticsInfo
+ 0x1013c564 0x44 _g_UL_MutiplexingANStatisticsInfo
+ 0x1013c5a8 0x9a _g_EDL_HARQ_INFO
+ 0x1013c642 0x52 _g_EUL_HarqTransStatisticsInfo
+ 0x1013c694 0x3c _g_EDL_WORK_INFO
+ 0x1013c6d0 0x22 _g_EUL_AT_INFO
+ 0x1013c6f2 0x3c _g_EUL_BunldingANStatisticsInfo
+ 0x1013c72e 0x52 _g_EUL_PowerCtrlInfo
+ 0x1013c780 0x2d0 _g_EDL_PDCCH_INFO
+ 0x1013ca50 0x2 _gdwUlTmtFlowCount
+ 0x1013ca52 0x54 _g_EDL_AT_INFO
+ 0x1013caa6 0x2 _g_TmtLogCnt
+ 0x1013caa8 0x2 _gdwTmtFlowCount
+ 0x1013caaa 0xd9 _g_EUL_PrachStatisticsInfo
+ 0x1013cb83 0x4 _g_dwUlHarqFailCount
+ COMMON 0x1013cb87 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi.o)
+ 0x0 (size before relaxing)
+ 0x1013cb87 0x4 _gt_CsiPrintCtrl
+ 0x1013cb8b 0x1 _g_wLastAbsSfn
+ 0x1013cb8c 0x1 _g_wCsiWorkFlg
+ COMMON 0x1013cb8d 0x16 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_dint.o)
+ 0x0 (size before relaxing)
+ 0x1013cb8d 0x4 _g_adwTbCbCrc
+ 0x1013cb91 0x10 _g_adwDebugDLS
+ 0x1013cba1 0x2 _g_awTbCrc
+ COMMON 0x1013cba3 0x51 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x0 (size before relaxing)
+ 0x1013cba3 0x1 _g_zPHY_bDdtrWorkFlag
+ 0x1013cba4 0x1 _wTest
+ 0x1013cba5 0x2 _g_zPHY_dwDdtrCfgTimer
+ 0x1013cba7 0x2 _g_awHarqPrintFlg
+ 0x1013cba9 0x32 _g_tdbCqi2DlsPmiInfo
+ 0x1013cbdb 0x2 _dwCrcRlt
+ 0x1013cbdd 0x14 _awCfgHarqErr
+ 0x1013cbf1 0x2 _g_awHarqPreTime
+ 0x1013cbf3 0x1 _g_wLayerNum
+ COMMON 0x1013cbf4 0x89 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x0 (size before relaxing)
+ 0x1013cbf4 0x2 _g_dwOffsetDelta
+ 0x1013cbf6 0x2 _g_zPHY_erfc_tempDac
+ 0x1013cbf8 0x1 _g_zPHY_erfc_TempStartRecordFlag
+ 0x1013cbf9 0x1 _g_dwOffsetFlag
+ 0x1013cbfa 0x1 _g_zPHY_erfc_wMID2RXFlag
+ 0x1013cbfb 0x1 _g_slot1_nRBNum
+ 0x1013cbfc 0x14 _g_asdzPHY_erfc_CirServOrNeibor
+ 0x1013cc10 0x1 _g_zPHY_erfc_Meas0SubfNum
+ 0x1013cc11 0x2 _g_dwSubframeNumForTest
+ 0x1013cc13 0x2 _g_zPHY_erfc_CleanTxoffset
+ 0x1013cc15 0x2 _g_zPHY_erfc_Meas0Offset
+ 0x1013cc17 0x1 _g_zPHY_erfc_wSyncState
+ 0x1013cc18 0x1 _g_slot0_RBStart
+ 0x1013cc19 0x2 _g_zPHY_erfc_Meas1Offset
+ 0x1013cc1b 0x2 _g_zPHY_erfc_InitialTempDac
+ 0x1013cc1d 0x2 _g_zPHY_erfc_TxMulmOffset
+ 0x1013cc1f 0x2 _g_zPHY_erfc_RxoffsetAcumulator
+ 0x1013cc21 0x2 _g_AgcHwModeOnFalg
+ 0x1013cc23 0x1 _g_zPHY_erfc_eAcp405NextState
+ 0x1013cc24 0x1 _g_slot1_RBStart
+ 0x1013cc25 0x1 _g_zPHY_erfc_eAcp405CurrState
+ 0x1013cc26 0x1 _g_wReadState
+ 0x1013cc27 0x4 _g_tLteRfcTmpReadInfo
+ 0x1013cc2b 0x14 _g_adzPHY_erfc_MainAntInd
+ 0x1013cc3f 0x1 _g_zPHY_erfc_TaTimer
+ 0x1013cc40 0x2 _g_adzPHY_erfc_CurMainAntInd
+ 0x1013cc42 0x2 _g_dwTxoffset
+ 0x1013cc44 0x2 _g_dwDbgSubfCount
+ 0x1013cc46 0x1 _g_slot0_nRBNum
+ 0x1013cc47 0x33 _gtLteRfcRpiPwrCtl
+ 0x1013cc7a 0x2 _g_zPHY_erfc_RfStateMap
+ 0x1013cc7c 0x1 _g_zPHY_erfc_Meas0SubfDef
+ COMMON 0x1013cc7d 0x10f T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x0 (size before relaxing)
+ 0x1013cc7d 0x1 _g_wRi1LstCqi
+ 0x1013cc7e 0x1 _g_wStartCNTFlg
+ 0x1013cc7f 0x61 _gt_CsiFilter
+ 0x1013cce0 0x1 _g_wLstTm
+ 0x1013cce1 0xaa _g_atCsiPmiRiCalcResult
+ 0x1013cd8b 0x1 _g_wCNT
+ COMMON 0x1013cd8c 0xbb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pbch.o)
+ 0x0 (size before relaxing)
+ 0x1013cd8c 0x28 _g_L1e_dwPbchEvtList
+ 0x1013cdb4 0x1e _g_L1e_tPbchCB
+ 0x1013cdd2 0x22 _g_L1e_tMibRxReg
+ 0x1013cdf4 0x9 _g_L1e_tDlaparaSave
+ 0x1013cdfd 0x14 _g_L1e_tMibPbchReg
+ 0x1013ce11 0x15 _g_L1e_tMibInfo
+ 0x1013ce26 0xc _g_L1e_tBchOps
+ 0x1013ce32 0xa _g_DbgMibPerStat
+ 0x1013ce3c 0xb _g_L1e_tMibRfcBackUp
+ COMMON 0x1013ce47 0x2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x0 (size before relaxing)
+ 0x1013ce47 0x1 _g_wMsg4AckRaConflictCnt
+ 0x1013ce48 0x1 _g_wHarqGroupNum
+ COMMON 0x1013ce49 0x9c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_ctrl.o)
+ 0x0 (size before relaxing)
+ 0x1013ce49 0x9 _g_atCqiCommonInfo
+ 0x1013ce52 0x1 _g_awCqiPmiRiIndex
+ 0x1013ce53 0xd _g_atBandWidthInfo
+ 0x1013ce60 0xa _g_adAperLastCqiPmiDataBuffer
+ 0x1013ce6a 0x1 _g_awAPERLastRI
+ 0x1013ce6b 0x32 _g_atCsiEnFinal
+ 0x1013ce9d 0x8 _g_atPeriodRepPara
+ 0x1013cea5 0x1 _g_awLastReportIndex
+ 0x1013cea6 0x2 _g_awLastWBPMI
+ 0x1013cea8 0x4 _g_tCsiTime
+ 0x1013ceac 0x1 _g_awLastWBCQICW0
+ 0x1013cead 0x1 _g_awRiBitLen
+ 0x1013ceae 0x1 _g_awAPERLastWBCQICW0
+ 0x1013ceaf 0x2 _g_awLastRI
+ 0x1013ceb1 0x32 _g_atCqiDedicateInfo
+ 0x1013cee3 0x1 _g_awLastWBCQICW1
+ 0x1013cee4 0x1 _g_awMaxLayerNum
+ COMMON 0x1013cee5 0x233b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ul_db.o)
+ 0x0 (size before relaxing)
+ 0x1013cee5 0x50 _g_awFHopSeq4SubBands
+ 0x1013cf35 0x2 _g_dwTpcPrintCnt
+ 0x1013cf37 0x50 _g_awFHopSeq3SubBands
+ 0x1013cf87 0x2 _g_dwSrsPrintCnt
+ 0x1013cf89 0x2 _g_dwPucchPrintCnt
+ 0x1013cf8b 0x2 _g_dwPrachPrintCnt
+ 0x1013cf8d 0x50 _g_awFHopSeq2SubBands
+ 0x1013cfdd 0x4 _g_awSpecPrachNum
+ 0x1013cfe1 0x50 _g_awFmSeq
+ 0x1013d031 0xe98 _g_zPHY_etx_HarqProDbPort0
+ 0x1013dec9 0x50 _g_awFmSeq_Scell
+ 0x1013df19 0x8 _g_t_zPHY_etx_Uls_H2L_HarqProcessIDInfo
+ 0x1013df21 0x8 _g_t_zPHY_etx_HarqProcessIDInfo
+ 0x1013df29 0x25f _g_awUlTestMacPduBuf
+ 0x1013e188 0x50 _g_awFHopSeq2SubBands_Scell
+ 0x1013e1d8 0xe98 _g_zPHY_etx_HarqProDbPort1
+ 0x1013f070 0x104 _g_t_zPHY_Dls2UlsDciValue
+ 0x1013f174 0x50 _g_awFHopSeq4SubBands_Scell
+ 0x1013f1c4 0x2 _g_dwCloseLoopPowerPrintCnt
+ 0x1013f1c6 0x2 _g_dwPuschPrintCnt
+ 0x1013f1c8 0x50 _g_awFHopSeq3SubBands_Scell
+ 0x1013f218 0x8 _g_t_zPHY_etx_RarUlGrant
+ COMMON 0x1013f220 0x4e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp.o)
+ 0x0 (size before relaxing)
+ 0x1013f220 0x1 _g_swPrintProNoInt
+ 0x1013f221 0x10 _g_asdwL1eRxCrsRsrp
+ 0x1013f231 0x4 _g_adwL1eRxCrsRssi
+ 0x1013f235 0x4 _g_lsdwNsIot_8242_SINR
+ 0x1013f239 0x18 _g_adwL1eRxDrsRsp
+ 0x1013f251 0x1 _g_zPHY_emc_wCellComponFlag
+ 0x1013f252 0xc _g_adwL1eRxCrsRsp
+ 0x1013f25e 0x1 _g_wLtel1IdleAccessReqInd
+ 0x1013f25f 0x1 _g_awL1eRxBfDagcFlag
+ 0x1013f260 0x1 _g_awL1eRxBfTransFlag
+ 0x1013f261 0x1 _g_wL1eRxNbNbSinrCalInd
+ 0x1013f262 0xb _g_zPHY_emc_tSinrInfo
+ 0x1013f26d 0x1 _g_awL1eRxDrsAccNum
+ COMMON 0x1013f26e 0x118e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_data.o)
+ 0x0 (size before relaxing)
+ 0x1013f26e 0xa _g_awPSeqCellIDDiv30
+ 0x1013f278 0x12b _g_tUlaLtxParas
+ 0x1013f3a3 0x46 _g_awPSeqCellIDDiv30SS
+ 0x1013f3e9 0x1 _g_EUL_wPuschPowerIdx
+ 0x1013f3ea 0x1 _g_EUL_wPucchPowerIdx
+ 0x1013f3eb 0xe7 _g_tUlaCommRelatedParasScell
+ 0x1013f4d2 0x46 _g_awPSeqCellIDDiv30SS_Scell
+ 0x1013f518 0x1 _g_EUL_wSrsPowerIdx
+ 0x1013f519 0x6 _g_tUlaDediRelatedParas
+ 0x1013f51f 0x4 _g_tUlaCID
+ 0x1013f523 0xa6d _g_t_zPHY_eula_CtrlBlock
+ 0x1013ff90 0x50 _g_awPSeqCellID
+ 0x1013ffe0 0x1c _g_tUlaCommConfig
+ 0x1013fffc 0xac _g_tUlaDediConfig
+ 0x101400a8 0xa _g_awPSeqPuschSeqShift
+ 0x101400b2 0xc8 _g_tUlaScellInfo
+ 0x1014017a 0xe7 _g_tUlaCommRelatedParas
+ 0x10140261 0xa _g_awPSeqCellIDDiv30_Scell
+ 0x1014026b 0x1f _g_tUlaPucchInfo
+ 0x1014028a 0x120 _g_tSrsInfo
+ 0x101403aa 0x50 _g_awPSeqCellID_Scell
+ 0x101403fa 0x1 _g_w_FirstFlgSet
+ 0x101403fb 0x1 _g_EUL_wPrachPowerIdx
+ COMMON 0x101403fc 0x54 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x0 (size before relaxing)
+ 0x101403fc 0x1 _g_L1l_LpmCaliIdx
+ 0x101403fd 0x8 _g_L1l_MrtrBeforeWakup
+ 0x10140405 0xa _g_wTpuIntTypeforlpm
+ 0x1014040f 0x2 _g_L1l_LpmCaliCnt
+ 0x10140411 0x6 _g_zPHY_tSuperFrameCtrlInfo
+ 0x10140417 0x22 _g_zPHY_tWakeupTimerInfo
+ 0x10140439 0x1 _g_zPHY_dwTpuSleepTimeLenByFrame
+ 0x1014043a 0x1 _g_L1lLpAwakeTimerCtrl
+ 0x1014043b 0x2 _g_zPHY_tWakeupReq
+ 0x1014043d 0x1 _g_L1lLpTaskStateCtrl
+ 0x1014043e 0x2 _g_L1l_LpmModemWakeupTime
+ 0x10140440 0x2 _g_L1l_LpmCaliAbortTime
+ 0x10140442 0x2 _g_tL1lLpCtrl
+ 0x10140444 0x2 _g_L1l_LpmSocWakeupTime
+ 0x10140446 0x2 _g_zPHY_LtePhySleepCnt
+ 0x10140448 0x8 _g_L1l_MrtrAfterSleep
+ COMMON 0x10140450 0x14e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x0 (size before relaxing)
+ 0x10140450 0x10 _g_adw_zPHY_erfc_profile_DB
+ 0x10140460 0x2 _g_dwLPTxoffset
+ 0x10140462 0x1 _g_zPHY_erfc_AfcWord
+ 0x10140463 0xc0 _g_zPHY_erfc_aNVBandIndex
+ 0x10140523 0x39 _g_zPHY_erfc_atLPCSFConfig
+ 0x1014055c 0x2 _g_zPHY_erfc_ACP405Version
+ 0x1014055e 0x40 _g_at_zPHY_erfc_atReloadData
+ COMMON 0x1014059e 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas.o)
+ 0x0 (size before relaxing)
+ 0x1014059e 0x1 _g_zPHY_ecsrm_wNextIntFlag
+ 0x1014059f 0x1 _g_ZPHY_ecsrm_tMeasState
+ 0x101405a0 0xf _g_zPHY_ecsrm_tCommInfo
+ COMMON 0x101405af 0x120 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_meas_normal.o)
+ 0x0 (size before relaxing)
+ 0x101405af 0x120 _g_MeasContext
+ COMMON 0x101406cf 0x7 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmb_task.o)
+ 0x0 (size before relaxing)
+ 0x101406cf 0x7 _g_tUlBlerInfo
+ *fill* 0x101406d6 0x80000002 00
+ COMMON 0x101406d8 0x3ec T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x0 (size before relaxing)
+ 0x101406d8 0x2 _g_awMbmsClusterNum
+ 0x101406da 0x1 _g_ePreRapcState
+ 0x101406db 0x30 _g_aswMBMS_MaxDelay
+ 0x1014070b 0x31 _g_aswMBMS_FftWinStart
+ 0x1014073c 0xc4 _g_aswFreq_Inter_Coeff
+ 0x10140800 0xc4 _g_aswFreq_NormalCoeff
+ 0x101408c4 0x200 _g_aiInitSequence
+ COMMON 0x10140ac4 0x1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cfo.o)
+ 0x0 (size before relaxing)
+ 0x10140ac4 0x14 _g_tLteA1DlaRxCb
+ 0x10140ad8 0x4 _g_awL1eRxRsrpFilter
+ 0x10140adc 0x4 _g_awL1eRxRsrpFilterFlag
+ COMMON 0x10140ae0 0x3cf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x0 (size before relaxing)
+ 0x10140ae0 0x1 _g_zPHY_edfe_wAgcEnEventFlag
+ 0x10140ae1 0x8 _g_tTempDCOffsetComp
+ 0x10140ae9 0xd _g_zPHY_edfe_tPlmnSaveServCellAgc
+ 0x10140af6 0x1 _g_zPHY_edfe_wRxLinDagc1
+ 0x10140af7 0x1 _g_zPHY_edfe_swAgcMeanPwr1
+ 0x10140af8 0x2 _g_zPHY_edfe_dwScanFreqAgcCalFlag
+ 0x10140afa 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp0
+ 0x10140afc 0x1 _g_zPHY_edfe_wNotSyncAGCDone
+ 0x10140afd 0x1 _g_zPHY_edfe_wRfcSingleAnt
+ 0x10140afe 0x8 _g_tIQComp
+ 0x10140b06 0x1 _g_wAgcCntForFirstDC
+ 0x10140b07 0x6 _g_awAgcGain0
+ 0x10140b0d 0x1 _g_zPHY_edfe_wAgcLog2Gain0
+ 0x10140b0e 0x1 _g_zPHY_edfe_wCsrsLinDagc0
+ 0x10140b0f 0x1 _g_zPHY_edfe_wCsrmLinDagc1
+ 0x10140b10 0x78 _g_zPHY_edfe_MeasAgcPara
+ 0x10140b88 0x1 _g_wCount
+ 0x10140b89 0x120 _g_a_zPHY_edfe_tReloadAgcData
+ 0x10140ca9 0x1 _g_zPHY_edfe_cRxAntennaMode
+ 0x10140caa 0x18 _g_zPHY_edfe_tPlmnAgcPara
+ 0x10140cc2 0x8 _g_tDCOffsetCompRecord
+ 0x10140cca 0x2 _g_dwCsrmRssiRx0
+ 0x10140ccc 0x1 _g_zPHY_edfe_wAgcExtendModeEn
+ 0x10140ccd 0x6 _g_awAgcGain1
+ 0x10140cd3 0x2 _g_zPHY_edfe_aswAgcMeanPwr_Samp7
+ 0x10140cd5 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt1
+ 0x10140cd6 0x1 _g_zPHY_edfe_wRxLinDagc0
+ 0x10140cd7 0x28 _g_a_zPHY_edfe_wCsrmTotalAgcGainLog2
+ 0x10140cff 0x78 _g_tDfeNotchInfo
+ 0x10140d77 0x1 _g_zPHY_edfe_wAgcIntReportFlag
+ 0x10140d78 0x6 _g_awTempMeanPower1
+ 0x10140d7e 0x1 _g_zPHY_edfe_wAgcMeaPwSavReg
+ 0x10140d7f 0x1 _g_zPHY_edfe_wAgcLog2Gain1
+ 0x10140d80 0x1 _g_zPHY_edfe_wSaveRxBand
+ 0x10140d81 0x1 _g_wAgcWorkState
+ 0x10140d82 0x1 _g_zPHY_edfe_wCsrmLinDagc0
+ 0x10140d83 0x1 _g_zPHY_edfe_wRfcSyncState
+ 0x10140d84 0xd7 _g_EDFE_SYSTEM_INFO
+ 0x10140e5b 0x1 _g_zPHY_edfe_swAgcMeanPwr0
+ 0x10140e5c 0x1 _g_zPHY_edfe_wAgcdBGain0
+ 0x10140e5d 0x2 _g_DcCounter
+ 0x10140e5f 0x8 _g_tDCOffsetEsti
+ 0x10140e67 0x2 _g_dwCsrmRssiRx1
+ 0x10140e69 0x8 _g_tDCOffsetComp
+ 0x10140e71 0x1 _g_wIqCount
+ 0x10140e72 0x2 _g_zPHY_edfe_dwSearchAgcCalFlag
+ 0x10140e74 0x1 _g_zPHY_edfe_wCsrsLinDagc1
+ 0x10140e75 0x28 _g_a_zPHY_edfe_wRxTotalAgcGainLog2
+ 0x10140e9d 0x1 _g_zPHY_erfc_SlaveOutGapAGC
+ 0x10140e9e 0x1 _g_wCsrs_RX_Sib1_Read_Flag
+ 0x10140e9f 0x8 _g_zPHY_edfe_tRxAgcBalance
+ 0x10140ea7 0x6 _g_awTempMeanPower0
+ 0x10140ead 0x1 _g_zPHY_edfe_wAgcdBGain1
+ 0x10140eae 0x1 _g_zPHY_edfe_wNotSyncAGCDoneAnt0
+ COMMON 0x10140eaf 0x1e3 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula.o)
+ 0x0 (size before relaxing)
+ 0x10140eaf 0x1 _g_eTxCalibrationStep
+ 0x10140eb0 0x1 _g_wTxSendScaleDC
+ 0x10140eb1 0x4 _g_awDfeFftOutputDC
+ 0x10140eb5 0x4 _g_awDfeFftOutputIQ
+ 0x10140eb9 0x2 _g_dwCalibration_angle
+ 0x10140ebb 0x1d3 _g_atzPHY_UlAMTHarqProcessDB
+ 0x1014108e 0x1 _g_wTxSendScaleIQ
+ 0x1014108f 0x1 _Configdelay
+ 0x10141090 0x2 _g_dwCalibration_amp
+ COMMON 0x10141092 0x269d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla.o)
+ 0x0 (size before relaxing)
+ 0x10141092 0x1 _g_wAutoDeactiveTimer
+ 0x10141093 0x6 _g_t_zPHY_DlaDciInfo
+ 0x10141099 0xa _g_tL1eDevRxLpConvergeCb
+ 0x101410a3 0x268c _g_t_zPHY_DlaCb
+ COMMON 0x1014372f 0xd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x0 (size before relaxing)
+ 0x1014372f 0x2 _g_Scc_Rsrp_Cfo_IntCnt
+ 0x10143731 0x1 _g_wULA_Process_SubFrame
+ 0x10143732 0x2 _gTimer1Int_RcvNum
+ 0x10143734 0x6 _g_zPHY_Int_dwDFEIntType
+ 0x1014373a 0x2 _g_zPHY_Int_dwDFEIntType_agc
+ COMMON 0x1014373c 0xc0a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x0 (size before relaxing)
+ 0x1014373c 0x2 _g_dwL1lPreHookEntry
+ 0x1014373e 0x2 _gL1l_MissLogInfo
+ 0x10143740 0xc00 _g_awL1lEngTempBuffer
+ 0x10144340 0x2 _L1L_STANDARD_LOG_ID_BASE
+ 0x10144342 0x2 _g_dwL1lCurrentHookEntry
+ 0x10144344 0x2 _g_wL1lRemainLen
+ COMMON 0x10144346 0x138d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_data.o)
+ 0x0 (size before relaxing)
+ 0x10144346 0xd _g_tTTIBundlingDB
+ 0x10144353 0xe _g_zPHY_euls_tTpcCommands
+ 0x10144361 0x1 _g_EUL_wRachIdx
+ 0x10144362 0x14 _g_tRarCtrlDB
+ 0x10144376 0x2 _g_EUL_wDci0InfoIdx
+ 0x10144378 0x2d _g_tUlSPSDB
+ 0x101443a5 0x2a _g_zPHY_euls_ComConfig
+ 0x101443cf 0x123e _g_tShadowHarqDB
+ 0x1014560d 0x8 _g_tUlsDB
+ 0x10145615 0x72 _g_atDCI0PhichSelecDB
+ 0x10145687 0x4c _g_zPHY_euls_DedConfig
+ COMMON 0x101456d3 0x33 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x0 (size before relaxing)
+ 0x101456d3 0x4 _g_zPHY_erfc_tCordicAdjustPara
+ 0x101456d7 0x2 _g_ACP405_AFC_DIFF
+ 0x101456d9 0x5 _g_zPHY_erfc_tAfcPara
+ 0x101456de 0x28 _g_sdAtCtl_ApcOffsetTime
+ COMMON 0x10145706 0x2c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_cfg_rx.o)
+ 0x0 (size before relaxing)
+ 0x10145706 0x2 _gadwZeroCsiRsCollideInd
+ 0x10145708 0x2 _gau_zPHY_Rx_CsiRsIdicator
+ 0x1014570a 0x1 _g_PchBlerInfo_0
+ 0x1014570b 0x8 _gau_zPHY_Rx_ZeroPowerCisPos
+ 0x10145713 0x1 _g_PchBlerInfo_3
+ 0x10145714 0x2 _g_dwRxPreN0Value
+ 0x10145716 0x1 _g_wPrbNoPrintFlg
+ 0x10145717 0x2 _gauZeroPowerCsiBitMap
+ 0x10145719 0x2 _gadwCsiRsCollideInd
+ 0x1014571b 0x1 _g_PchBlerInfo_1
+ 0x1014571c 0x1 _g_PchTiCfgInd_1
+ 0x1014571d 0x2 _gadwZeroPowerCsiRsPosCalculated
+ 0x1014571f 0x1 _g_tRxPreState
+ 0x10145720 0x1 _g_wPchFlag
+ 0x10145721 0x1 _g_tRxCurrState
+ 0x10145722 0x1 _g_PchBlerInfo_4
+ 0x10145723 0x2 _g_dwTempN0
+ 0x10145725 0x1 _gwNS_IOT_8242_Ind
+ 0x10145726 0x1 _g_awL1eRxNCellRsNullEnInd
+ 0x10145727 0x2 _gadwCsiRsPosCalculated
+ 0x10145729 0x1 _g_awRxCirTiCfgInd
+ 0x1014572a 0x2 _gt_zPHY_Rx_ZeroCsiRsExistInd
+ 0x1014572c 0x2 _g_awCsiRsCheCfgVal
+ 0x1014572e 0x1 _g_PchBlerInfo_2
+ 0x1014572f 0x1 _g_PchTiCfgInd_2
+ 0x10145730 0x2 _gt_zPHY_Rx_CsiRsExistInd
+ COMMON 0x10145732 0xa04 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_data.o)
+ 0x0 (size before relaxing)
+ 0x10145732 0x510 _g_adwCommDlschPara1A
+ 0x10145c42 0x300 _g_adwCommDlschPara1C
+ 0x10145f42 0x1f4 _g_adwPhyNirDivC
+ COMMON 0x10146136 0x258 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x0 (size before relaxing)
+ 0x10146136 0x24c _g_TopReg
+ 0x10146382 0xc _g_LteaTopIntRegBitMap
+ COMMON 0x1014638e 0x3d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_sram_ddr.o)
+ 0x0 (size before relaxing)
+ 0x1014638e 0xa _g_zPHY_emc_tDlDataRecvCtrlInfo
+ 0x10146398 0x1 _g_wRLMATQInFlg
+ 0x10146399 0x2 _g_sdRLMATQIn
+ 0x1014639b 0x1 _g_zPHY_emc_wSIDataBufSel
+ 0x1014639c 0x2 _g_sdRLMATQOut
+ 0x1014639e 0x1 _g_wRLMATQOutFlg
+ 0x1014639f 0x1e _g_zPHY_emc_tScheduleSiReq
+ 0x101463bd 0x8 _g_zPHY_emc_tPchDataRecvCtrlInfo
+ 0x101463c5 0x6 _g_zPHY_emc_tReadSib1Req
+ COMMON 0x101463cb 0x8 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_lpm.o)
+ 0x0 (size before relaxing)
+ 0x101463cb 0x8 _g_zPHY_tLpcPwrCtrlScenExpect
+ COMMON 0x101463d3 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rx.o)
+ 0x0 (size before relaxing)
+ 0x101463d3 0x1 _g_VrbFlag
+ COMMON 0x101463d4 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1.o)
+ 0x0 (size before relaxing)
+ 0x101463d4 0x2 _g_zPHY_erfc_dwConFr40AuxAdcClkBase
+ 0x101463d6 0x2 _g_dwAptFixVoltageNvSet
+ 0x101463d8 0x2 _g_zPHY_erfc_dwConFr11_19Xtal
+ 0x101463da 0x2 _g_zPHY_erfc_dwConFr24LowRefMode
+ 0x101463dc 0x2 _g_ACP405_RxPGC1_Word
+ 0x101463de 0x2 _g_ACP405_RxPGC0_Word
+ 0x101463e0 0x2 _g_zPHY_erfc_dwConFr33RefClk
+ COMMON 0x101463e2 0x28 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x0 (size before relaxing)
+ 0x101463e2 0x28 _g_a_zPHY_edfe_dwLpcSaveReg
+ COMMON 0x1014640a 0xa T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_time.o)
+ 0x0 (size before relaxing)
+ 0x1014640a 0xa _g_CsrGapInfo
+ COMMON 0x10146414 0x63b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_meas.o)
+ 0x0 (size before relaxing)
+ 0x10146414 0x1 _g_dwCsrIntraRsrpFilterPrintCnt
+ 0x10146415 0x2 _g_swCsr_Rssi_SearCnf
+ 0x10146417 0x55d _g_zPHY_ecsrc_tFilterInterMeas
+ 0x10146974 0x2 _g_swCsr_Rssi_Report
+ 0x10146976 0xc4 _g_zPHY_ecsrc_tFilterIntraMeas
+ 0x10146a3a 0x1 _g_awAgcNoBalance
+ 0x10146a3b 0x12 _g_zPHY_ecsrc_tFilterFactor
+ 0x10146a4d 0x1 _g_dwCsrInterRsrpFilterPrintCnt
+ 0x10146a4e 0x1 _g_dwCsrInterRsrpFilterRepPrintCnt
+ COMMON 0x10146a4f 0x11b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_sib.o)
+ 0x0 (size before relaxing)
+ 0x10146a4f 0x78 _g_L1e_dwSirEvtList
+ 0x10146ac7 0x5 _g_l1e_tSirRxRcv
+ 0x10146acc 0x95 _g_L1e_tSirDb
+ 0x10146b61 0x1 _g_zPHY_wSibStartPbchTimes
+ 0x10146b62 0x1 _g_L1e_wSibRptDelay
+ 0x10146b63 0x6 _g_L1e_tSibCrc
+ 0x10146b69 0x1 _g_L1e_wSiTimingNeibState
+ COMMON 0x10146b6a 0x352b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x0 (size before relaxing)
+ 0x10146b6a 0x2ee0 _g_awSyncMsgBuff
+ 0x10149a4a 0x5 _g_zPHY_tRfRxOffsetCfgInfo
+ 0x10149a4f 0x1 _g_zPHY_emc_wSetRfcIdleModeOkCnt
+ 0x10149a50 0x96 _g_zPHY_emc_tCommonConfigReq
+ 0x10149ae6 0x2 _g_zPHY_emc_tMcCtrlParam
+ 0x10149ae8 0x1 _g_zPHY_emc_wSoftResetOkFlag
+ 0x10149ae9 0x2 _g_dwNextX
+ 0x10149aeb 0x1 _g_zPHY_emc_bGapConfigState
+ 0x10149aec 0x1 _g_wSCellDeactivationTimerParam
+ 0x10149aed 0x1 _g_zPHY_emc_wReleaseDlDelayCnt
+ 0x10149aee 0x50 _g_atzPhy_emc_SyncMsgInfo
+ 0x10149b3e 0x1 _g_wPlmnRapcConflictTimer
+ 0x10149b3f 0x1 _g_zPHY_emc_wIsCampOn
+ 0x10149b40 0x4 _g_zPHY_emc_tTimingCtrlParam
+ 0x10149b44 0x4 _g_zPHY_emc_ScellCtrlReq
+ 0x10149b48 0x2 _g_dwGapStatue
+ 0x10149b4a 0x1 _g_zPHY_emc_wUseServeInfoFlag
+ 0x10149b4b 0x1 _g_zPHY_emc_wReleaseRfcIdleModeOkCnt
+ 0x10149b4c 0x4 _g_zPHY_emc_tTACtrlParam
+ 0x10149b50 0x2 _g_dwSubFrm
+ 0x10149b52 0x2 _g_dwErrorNum
+ 0x10149b54 0x13 _g_zPHY_emc_tDrxSPSCtrlInfo
+ 0x10149b67 0x1 _g_ePrePhyState
+ 0x10149b68 0x4 _g_awSCellDeactivationTimer
+ 0x10149b6c 0x412 _g_zPHY_emc_tDedicatedConfigReq
+ 0x10149f7e 0x8 _g_zPHY_emc_tAccessReq
+ 0x10149f86 0x1 _g_zPHY_emc_wCommonMsgDisPathFlag
+ 0x10149f87 0x1 _g_wThinkWill_Flg
+ 0x10149f88 0x50 _g_CellSearchData
+ 0x10149fd8 0xd _g_zPHY_emc_tRec_Tpu
+ 0x10149fe5 0x1 _g_zPHY_emc_wSetModeOkFlag
+ 0x10149fe6 0x86 _g_FreqScanData
+ 0x1014a06c 0x2 _g_zPHY_emc_tReleaseCtrlParam
+ 0x1014a06e 0x3 _g_zPHY_emc_tRaMsgHoldFlag
+ 0x1014a071 0x24 _g_L1e_tDlRfcCfgInfo
+ COMMON 0x1014a095 0x1513 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc.o)
+ 0x0 (size before relaxing)
+ 0x1014a095 0x1 _g_zPHY_ecsrc_wGapConfigCsrRecive
+ 0x1014a096 0x1 _g_zPHY_ecsrc_wPiPeriod
+ 0x1014a097 0x8 _g_zPHY_ecsrc_tSearchMeasAgeThrold
+ 0x1014a09f 0x2 _g_zPHY_ecsrs_dwTpuAdjTime
+ 0x1014a0a1 0x86 _g_zPHY_ecsrc_tFreqScanReq
+ 0x1014a127 0x28 _g_zPHY_ecsrc_tCommInfo
+ 0x1014a14f 0x4 _g_L1e_Csrc_PreCfo
+ 0x1014a153 0x10 _g_zPHY_ecsrc_tEarfcnTable_B28
+ 0x1014a163 0x39e _g_zPHY_ecsrc_tCsrPsInterMeasInd
+ 0x1014a501 0x55 _g_L1e_Csrc_C0Update
+ 0x1014a556 0x6 _g_zPHY_ecsrc_tMeasMaskSetBack
+ 0x1014a55c 0x50 _g_zPHY_ecsrc_tCellSearchReq
+ 0x1014a5ac 0x1f _g_zPHY_ecsrc_tCnnDrxMeasSchedule
+ 0x1014a5cb 0x6 _g_zPHY_ecsrc_tMeasMaskSetReq
+ 0x1014a5d1 0x82 _g_zPHY_ecsrc_tFreqScanCnf
+ 0x1014a653 0x4 _g_atAgeTimer
+ 0x1014a657 0x1 _g_L1e_Csrc_DisFreqScan
+ 0x1014a658 0x1 _g_zPHY_ecsrc_wScheduleInfoCnt
+ 0x1014a659 0x1 _g_L1e_C0ConIntraRptCnt
+ 0x1014a65a 0x1 _g_L1e_C0ConDrxCnt
+ 0x1014a65b 0x6 _g_L1e_Csrc_CurPpm
+ 0x1014a661 0x1 _g_wcsrc_HoOnflag
+ 0x1014a662 0x2ae _g_zPHY_ecsrc_tCsrPsIntraMeasInd
+ 0x1014a910 0x1 _g_zPHY_ecsrc_wWorkInterFreqIndex
+ 0x1014a911 0x6a7 _g_zPHY_ecsrc_tCsrCellDatabase
+ 0x1014afb8 0x9 _g_zPHY_ecsrc_tFliterSchduInd
+ 0x1014afc1 0x1 _g_zPHY_wHoStartPbchTimes
+ 0x1014afc2 0x2 _g_zPHY_ecsrc_dwCsrcFlag
+ 0x1014afc4 0x2 _g_L1e_csrc_tMeasPeriodChgReq
+ 0x1014afc6 0x1 _g_zPHY_ecsrc_AferGapFlag
+ 0x1014afc7 0x12 _g_zPHY_ecsrc_wDoneInterPerDrx
+ 0x1014afd9 0x5c8 _g_zPHY_ecsrc_tMeasConfigReq
+ 0x1014b5a1 0x2 _g_zPHY_ecsrc_swBackupCFOFreqOffset
+ 0x1014b5a3 0x1 _g_L1e_ConnIntraRptCnt
+ 0x1014b5a4 0x1 _g_zPHY_ecsrs_wCsrsWorkFlag
+ 0x1014b5a5 0x2 _g_L1eTempAdc
+ 0x1014b5a7 0x1 _g_L1e_Csrc_bCellSearchPbch
+ COMMON 0x1014b5a8 0x1c2 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_rapc_data.o)
+ 0x0 (size before relaxing)
+ 0x1014b5a8 0x1c1 _g_aw_RarMacPdu
+ 0x1014b769 0x1 _g_zPHY_swRsrpFilter
+ COMMON 0x1014b76a 0x919 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_mm.o)
+ 0x0 (size before relaxing)
+ 0x1014b76a 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReq
+ 0x1014b772 0x134 _g_zPHY_ecsrc_tMulmFreqListConfig
+ 0x1014b8a6 0x8 _g_zPHY_ecsrc_tIratGapConfig
+ 0x1014b8ae 0x3 _g_tSlaveSearchMeasAgeThrold
+ 0x1014b8b1 0x8 _g_zPHY_ecsrc_tMulmMeasGapConfigReqBackUp
+ 0x1014b8b9 0x1 _g_zPHY_emulm_PlmnSearchMeasCnt
+ 0x1014b8ba 0x6 _g_zPHY_emulm_tFilterFactor
+ 0x1014b8c0 0x1 _g_L1e_mulm_NoSatisfyCfoCnt
+ 0x1014b8c1 0x2 _g_zPHY_SetModeReq
+ 0x1014b8c3 0x6 _g_zPHY_ecsrc_tMulmInactiveTimeInd
+ 0x1014b8c9 0x1a _g_zPHY_emulm_SlaveHwEnable
+ 0x1014b8e3 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfigBackUp
+ 0x1014b8e9 0x8 _g_zPHY_ecsrc_tIratGapConfig1
+ 0x1014b8f1 0x1 _g_L1e_mulm_40msGapCnt
+ 0x1014b8f2 0x2 _g_zPHY_emulm_tMulmIdlePeriodReqFlag
+ 0x1014b8f4 0x3 _g_zPHY_emulm_tMulmAfcPara
+ 0x1014b8f7 0x165 _g_zPHY_ecsrc_atSlaveMeasInfo
+ 0x1014ba5c 0x621 _g_zPHY_emulm_tFilterMeas
+ 0x1014c07d 0x6 _g_zPHY_ecsrc_tMulmIratMeasConfig
+ COMMON 0x1014c083 0x11 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_csrc_cs.o)
+ 0x0 (size before relaxing)
+ 0x1014c083 0x11 _g_RxOpenPara
+ COMMON 0x1014c094 0x88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_drx.o)
+ 0x0 (size before relaxing)
+ 0x1014c094 0x6c _g_zPHY_emc_tDrxCtrlInfo
+ 0x1014c100 0xa _g_wIntTypeforDrx
+ 0x1014c10a 0x10 _g_awDrxUlRetranCnt
+ 0x1014c11a 0x2 _g_Next2SubFrameDrxActiveSidFlag
+ COMMON 0x1014c11c 0x10 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_rlm.o)
+ 0x0 (size before relaxing)
+ 0x1014c11c 0x1 _g_wFIUpdate2RLM
+ 0x1014c11d 0xf _g_zPHY_emc_tRadioLinkCtrlInfo
+ COMMON 0x1014c12c 0x19c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_amt.o)
+ 0x0 (size before relaxing)
+ 0x1014c12c 0x10 _g_tLteAmtCellSyncPara
+ 0x1014c13c 0x157 _g_tLteAmtInfo
+ 0x1014c293 0x2 _g_zPHY_AMT_SearchCellCnt
+ 0x1014c295 0x2 _g_zPHY_AMT_Strongest_CellId
+ 0x1014c297 0x1f _gtAmtCellSyncProc
+ 0x1014c2b6 0x2 _g_zPHY_AMT_Strongest_Rsrp
+ 0x1014c2b8 0x2 _g_zPHY_AMT_Earfcn
+ 0x1014c2ba 0xa _g_zPHY_AMT_SrvCellRsrp
+ 0x1014c2c4 0x2 _g_dwFdt10MsCnt
+ 0x1014c2c6 0x2 _g_zPHY_AMT_Frequency
+ COMMON 0x1014c2c8 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_ho.o)
+ 0x0 (size before relaxing)
+ 0x1014c2c8 0x2 _g_tHandoverCnf
+ 0x1014c2ca 0x488 _g_tHandoverReq
+ COMMON 0x1014c752 0x5a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_proc_page.o)
+ 0x0 (size before relaxing)
+ 0x1014c752 0xa _g_wIntTypeforPaging
+ 0x1014c75c 0x12 _g_tL1eSchedPreSyncCb
+ 0x1014c76e 0x3a _g_tL1eDcxoProcCb
+ 0x1014c7a8 0x2 _g_zPHY_sdwRxAnt0OffsetValue
+ 0x1014c7aa 0x2 _g_zPHY_sdwRxAnt1OffsetValue
+ COMMON 0x1014c7ac 0x248 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x0 (size before relaxing)
+ 0x1014c7ac 0x23a _g_atzPHY_RFSD
+ 0x1014c9e6 0xa _g_atCsiATCMDInfo
+ 0x1014c9f0 0x4 _g_zPHY_LteRfWorkSet
+ COMMON 0x1014c9f4 0x18 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x0 (size before relaxing)
+ 0x1014c9f4 0x18 _g_tL1lCallStackInfo
+ COMMON 0x1014ca0c 0x90 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x0 (size before relaxing)
+ 0x1014ca0c 0x48 _g_at_zPHY_NxtHiQuadPosTab
+ 0x1014ca54 0x48 _g_at_zPHY_CurHiQuadPosTab
+ COMMON 0x1014ca9c 0x2e0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x0 (size before relaxing)
+ 0x1014ca9c 0x1 _g_zPHY_edfe_wNotSyncAGCBegin
+ 0x1014ca9d 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr1
+ 0x1014ca9e 0x1 _g_Connect_State_Inter_Freq_Flag
+ 0x1014ca9f 0x1 _g_wConnectAgcIntCounter
+ 0x1014caa0 0x1 _g_zPHY_edfe_LostLock_MAX
+ 0x1014caa1 0x1 _g_zPHY_edfe_wFirstInInterFreq
+ 0x1014caa2 0x2 _g_wContinGreaterCount
+ 0x1014caa4 0x1 _g_zPHY_edfe_LostLock_MIN
+ 0x1014caa5 0x1 _g_zPHY_edfe_ScellActiveState
+ 0x1014caa6 0x61 _g_zPHY_edfe_FSNewPara
+ 0x1014cb07 0x1e _g_zPHY_edfe_tAgcDagcPara
+ 0x1014cb25 0x1 _g_dwAgcTargetSync
+ 0x1014cb26 0x1 _g_zPHY_edfe_ScellActiveCounter
+ 0x1014cb27 0x2 _g_wContinLessCount
+ 0x1014cb29 0x1 _g_zPHY_edfe_wPrePhyState
+ 0x1014cb2a 0x1 _g_wAgcFactLf
+ 0x1014cb2b 0x1 _g_zPHY_edfe_swMaxAGCMeanPwr0
+ 0x1014cb2c 0x1 _g_zPHY_edfe_wNotSyncAgcIntCnt
+ 0x1014cb2d 0xa _g_zPHY_edfe_AgcDagcIntCount
+ 0x1014cb37 0x1 _g_dwAgcAvePowLenSync
+ 0x1014cb38 0x1f0 _g_zPHY_edfe_wAgcDagcGain
+ 0x1014cd28 0x4 _g_zPHY_edfe_tMbsfnAgcInfo
+ 0x1014cd2c 0x50 _g_zPHY_edfe_tMbsfnAgcGain
+ COMMON 0x1014cd7c 0xdac T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x0 (size before relaxing)
+ 0x1014cd7c 0xd91 _g_tzPHY_ecsrs_FSPara
+ 0x1014db0d 0x4 _g_FS_swMeanPower
+ 0x1014db11 0x1 _g_tzPHY_ecsrs_FS_RepNum
+ 0x1014db12 0x4 _g_PssContext
+ 0x1014db16 0x12 _g_tFS_BackUpPssResult
+ COMMON 0x1014db28 0xd6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x0 (size before relaxing)
+ 0x1014db28 0x2 _TotalPuschNackTB0
+ 0x1014db2a 0x2 _TotalPuschNackTB1
+ 0x1014db2c 0x2 _TotalPuschNumTB1
+ 0x1014db2e 0x6 _g_tUlReportBlerInfo
+ 0x1014db34 0x2 _TotalPuschNumTB0
+ 0x1014db36 0xc8 _g_adwDebug
+ COMMON 0x1014dbfe 0x418 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x0 (size before relaxing)
+ 0x1014dbfe 0x3c8 _g_atEcsrPeakList
+ 0x1014dfc6 0x50 _g_tPssHwResult
+ COMMON 0x1014e016 0xe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x0 (size before relaxing)
+ 0x1014e016 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrsDagc
+ 0x1014e01a 0x1 _g_swCsrsDagcMeanPower0
+ 0x1014e01b 0x1 _g_zPHY_edfe_wRxLog2Dagc1
+ 0x1014e01c 0x1 _g_zPHY_edfe_wCsrsLog2Dagc1
+ 0x1014e01d 0x1 _g_swCsrsDagcMeanPower1
+ 0x1014e01e 0x1 _g_zPHY_edfe_wCsrsLog2Dagc0
+ 0x1014e01f 0x4 _g_zPHY_edfe_tPlmnSaveServCellCsrmDagc
+ 0x1014e023 0x1 _g_zPHY_edfe_wRxLog2Dagc0
+ COMMON 0x1014e024 0x8d T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ 0x0 (size before relaxing)
+ 0x1014e024 0x5f _g_tzPHY_eulpc_PowerCtrlBlock
+ 0x1014e083 0x1 _g_EUL_wPuschPowerHeadroomIdx
+ 0x1014e084 0x1 _g_tzPHY_eulpc_Ulpc2DlParas
+ 0x1014e085 0x13 _g_tzPHY_eulpc_PcmaxInputInfo
+ 0x1014e098 0x6 _g_tzPHY_eulpc_TempPowerBackoffInfo
+ 0x1014e09e 0x13 _g_tzPHY_eulpc_PowerCtrlParas
+ COMMON 0x1014e0b1 0x9a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x0 (size before relaxing)
+ 0x1014e0b1 0x10f _g_ThreadIntraCs
+ 0x1014e1c0 0xf2 _g_atEcsrSearchPeakdatabase
+ 0x1014e2b2 0x1 _g_CsContext
+ 0x1014e2b3 0x10f _g_ThreadFreqScan
+ 0x1014e3c2 0x60 _g_l1e_tDcxoFtErrorList
+ 0x1014e422 0x2e6 _g_tEcsrSearchCommonInfor
+ 0x1014e708 0xa _g_tTddAndFddCommInfo
+ 0x1014e712 0x2 _g_zPHY_ecsrs_dwPssFrameBnd_dbg
+ 0x1014e714 0x1 _g_eCsrsSynStatus
+ 0x1014e715 0x4 _g_tEmulmSubFrameIntTable
+ 0x1014e719 0xe _g_atEcsrReCfoInfo
+ 0x1014e727 0x1 _g_wSssHwRestartCnt
+ 0x1014e728 0x10f _g_ThreadCfoCs
+ 0x1014e837 0x10f _g_ThreadInterCs
+ 0x1014e946 0x10f _g_ThreadMulmCs
+ COMMON 0x1014ea55 0x11e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x0 (size before relaxing)
+ 0x1014ea55 0x11e _g_CsrDrvCfgInfor
+ 0x1014eb73 ___bss_end = .
+
+.itcm 0x00000000 0x6e38 load address 0x100e8000
+ 0x00000000 _itcm_start = .
+ *(.vectors)
+ .vectors 0x00000000 0xb8 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ 0x00000000 0x20 _zsp_int_vector
+ 0x00000020 0x8 _odo_stub_Int12
+ 0x00000028 0x8 _odo_stub_Int11
+ 0x00000030 0x8 _odo_stub_Int10
+ 0x00000038 0x8 _odo_stub_Int9
+ 0x00000040 0x8 _odo_stub_Int8
+ 0x00000048 0x8 _odo_stub_Int7
+ 0x00000050 0x8 _odo_stub_Int6
+ 0x00000058 0x8 _odo_stub_Int5
+ 0x00000060 0x8 _odo_stub_Int4
+ 0x00000068 0x8 _odo_stub_Int3
+ 0x00000070 0x8 _odo_stub_Int2
+ 0x00000078 0x8 _odo_stub_Int1
+ 0x00000080 0x38 _odo_stub_Int0
+ *(.dmc)
+ .dmc 0x000000b8 0x17e T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+ 0x000000b8 0x17e _dei_handler
+ *(.zcos_vector_code)
+ *fill* 0x00000236 0x2 00
+ .zcos_vector_code
+ 0x00000238 0x1a0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ 0x00000238 0x20 _odo_wakeup_osint
+ 0x00000258 0x38 _jump_int
+ 0x00000290 0xf1 _odo_zsp_do_int
+ 0x00000381 0x27 _odo_swap_context
+ 0x000003a8 0x6 _odo_zsp_restore_flags
+ 0x000003ae 0xb _odo_restart
+ 0x000003b9 0x1f _odo_setup_context
+ .zcos_vector_code
+ 0x000003d8 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x000003d8 0x4d _L1_SwapHookUseTimer
+ *(.TcmLtePhyCode)
+ .TcmLtePhyCode
+ 0x00000425 0x290 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x0000055d 0x108 _L1Comm_DevEngCopyMem2Dpram
+ 0x00000665 0x50 _L1Comm_EmtpyLogUnit
+ .TcmLtePhyCode
+ 0x000006b5 0x193 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x000006b5 0xfb _L1L_TpuSubFrmUpdate
+ 0x000007b0 0x55 _L1L_TpuIntISRProc
+ 0x00000805 0x1b _L1L_TpuSysTimeUpdate
+ 0x00000820 0x28 _L1L_TpuHwIntGen
+ .TcmLtePhyCode
+ 0x00000848 0x2b1c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_cint.o)
+ 0x00000848 0x31a _L1e_DevDlsCdtrIntProc
+ 0x00000b62 0x37 _L1e_DevDlsGetDlCcInfo
+ 0x00000b99 0x26 _L1e_DevDlsGetDciDetInfo
+ 0x00000bbf 0x26 _L1e_DevDlsGetDciInfo
+ 0x00000be5 0x10 _L1e_DevDlsGetDciNum
+ 0x00000bf5 0x18 _L1e_DevDlsSwapDciInfo
+ 0x00000c0d 0x89 _L1e_DevDlsDciSelection
+ 0x00000c96 0x13 _L1e_DevDlsGetDestDci
+ 0x00000ca9 0x16 _L1e_DevDlsGetDestDciInfo
+ 0x00000cbf 0x369 _L1e_DevDlsGetUlCcInfo
+ 0x00001028 0x16 _L1e_DevDlsJudgeSccAssignment
+ 0x0000103e 0x10 _L1e_DevDlsRxUeRsAlgoCfg
+ 0x0000104e 0x15f _L1e_DevDlsRxCtrlRegCfg
+ 0x000011ad 0xe _L1e_DevDlsCalcTurboDelay
+ 0x000011bb 0x62 _L1e_DevDlsCalcTurboITs
+ 0x0000121d 0x67 _L1e_DevDlsTurboCtrlRegCfg
+ 0x00001284 0x22 _L1e_DevDlsGetDdtrWorkStatusInd
+ 0x000012a6 0x1d _L1e_DevDlsResetTurbo
+ 0x000012c3 0xf _L1e_DevDlsSubfNumRegCfg
+ 0x000012d2 0x8 _L1e_DevDlsPdschEnRegCfg
+ 0x000012da 0x1 _L1e_DevDlsDdtrClkSelCfg
+ 0x000012db 0x33 _L1e_DevDlsDdtrModeRegCfg
+ 0x0000130e 0x52 _L1e_DevDlsUpdateDdtr
+ 0x00001360 0x17 _L1e_DevDlsGetKmimoParam
+ 0x00001377 0x98 _L1e_DevDlsGetCcParam
+ 0x0000140f 0x40 _L1e_DevDlsGetCcCommParam
+ 0x0000144f 0x36c _zPHY_edls_ProRxBFCfg
+ 0x000017bb 0x48 _zPHY_edls_ProHarqInfoUpdate
+ 0x00001803 0x2c _zPHY_edls_HarqDdrRel
+ 0x0000182f 0x6b _zPHY_edls_HarqDdrTimeOut
+ 0x0000189a 0x13b _zPHY_edls_HarqDdr_DtchDone
+ 0x000019d5 0x2e _zPHY_edls_HarqDdr_DbgMonitorRst
+ 0x00001a03 0x14 _zPHY_edls_HarqDdr_BlockNumIdx
+ 0x00001a17 0x106 _zPHY_edls_HarqDdrReq
+ 0x00001b1d 0x2b7 _zPHY_edls_ProHarqDdrAddrCfg
+ 0x00001dd4 0x1ab _zPHY_edls_ProHarqInfoCfg
+ 0x00001f7f 0x68 _zPHY_edls_ProDciF1BTpmiValueCfg
+ 0x00001fe7 0x1f _zPHY_edls_ProDciF1DTpmiValueCfg
+ 0x00002006 0x1ce _zPHY_edls_ProDciF2TpmiValueCfg
+ 0x000021d4 0xa0 _zPHY_edls_ProDciF2LayerCfg
+ 0x00002274 0x451 _zPHY_edls_ProCommDlSchDecCfg
+ 0x000026c5 0x36 _zPHY_edls_ProPdcchOrder
+ 0x000026fb 0x3d5 _zPHY_edls_ProDediDlSchDecCfg
+ 0x00002ad0 0x79 _zPHY_edls_ProDLHarqValidInfo
+ 0x00002b49 0x30 _zPHY_edls_ProCwCrcValidGen
+ 0x00002b79 0xda _zPHY_edls_ProTddCwValidFeedback
+ 0x00002c53 0x1e _zPHY_edls_ProFddCwValidFeedback
+ 0x00002c71 0x170 _zPHY_edla_PdschPowCompensate
+ 0x00002de1 0x97 _zPHY_edla_PdschDefaultPCCfg
+ 0x00002e78 0x13 _zPHY_edls_DrvArmDspRamRead
+ 0x00002e8b 0x51 _zPHY_edls_GetUeFeedbackPmiIndex
+ 0x00002edc 0x10 _zPHY_edls_ProValidateSpsRecurs
+ 0x00002eec 0x3b _zPHY_edls_ProCalSpsRecurs
+ 0x00002f27 0x27 _zPHY_edls_ProCalSpsHarqId
+ 0x00002f4e 0xf0 _zPHY_edls_ProLTESpsDecCfg
+ 0x0000303e 0x31 _zPHY_edls_ProSpsValidation
+ 0x0000306f 0x94 _zPHY_edls_ProSpsActive
+ 0x00003103 0x84 _zPHY_edls_ProSpsRelease
+ 0x00003187 0x1dd _L1e_DevDlsDlMacPduBufCfg
+ .TcmLtePhyCode
+ 0x00003364 0x6bd T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc.o)
+ 0x00003364 0xb6 _zPHY_erfc_ProEventRamNumSet
+ 0x0000341a 0x7a _zPHY_erfc_ProRxReceiveCtrl
+ 0x00003494 0x8f _zPHY_erfc_ProCellSearchCtrl
+ 0x00003523 0x148 _zPHY_erfc_ProPowerCtrl
+ 0x0000366b 0x17 _zPHY_erfc_ProTDDCalcNextACP405State
+ 0x00003682 0x33 _zPHY_erfc_ProFDDCalcNextACP405State
+ 0x000036b5 0x20b _zPHY_erfc_ProRfsdCheck
+ 0x000038c0 0xd4 _zPHY_erfc_ProRFSDMerge
+ 0x00003994 0x8d _zPHY_erfc_ProMeas0Ctrl
+ .TcmLtePhyCode
+ 0x00003a21 0x55a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_dbb.o)
+ 0x00003a21 0xf0 _zPHY_erfc_SupMainSyncTableControl
+ 0x00003b11 0x9d _zPHY_erfc_SupTxSendSyncTableControl
+ 0x00003bae 0xb3 _zPHY_erfc_SupMeas0SyncTableControl
+ 0x00003c61 0x31a _zPHY_erfc_SupDFEAGCEsti
+ .TcmLtePhyCode
+ 0x00003f7b 0xdb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe.o)
+ 0x00003f7b 0xdb _zPHY_edfe_SupHandleDFESyncInt
+ .TcmLtePhyCode
+ 0x00004056 0xfb T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_cmn_int.o)
+ 0x00004056 0x60 _zPHY_eintc_InthHandler
+ 0x000040b6 0x22 _zPHY_eintc_Inth0Handler
+ 0x000040d8 0x22 _zPHY_eintc_Inth1Handler
+ 0x000040fa 0x22 _zPHY_eintc_Inth2Handler
+ 0x0000411c 0xa _zPHY_eintc_IntTimer1Handler
+ 0x00004126 0x2b _zPHY_eintc_ICPHandler
+ .TcmLtePhyCode
+ 0x00004151 0x1e6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x00004151 0x67 _L1l_DevEng_DbgExceptLog
+ 0x000041b8 0x24 _L1l_DevEng_DbgInfo
+ 0x000041dc 0xc0 _L1l_DevEngDisplay
+ 0x0000429c 0x58 _L1l_DevEngLogHeaderUpdate
+ 0x000042f4 0x43 _L1l_DevEngCopyMem2Dpram
+ .TcmLtePhyCode
+ 0x00004337 0x92 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rfc_abb_zx220a1.o)
+ 0x00004337 0x92 _zPHY_erfc_SupAGCControl
+ .TcmLtePhyCode
+ 0x000043c9 0x1894 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_param.o)
+ 0x000043c9 0x31 _L1e_DevDlsGetDciField
+ 0x000043fa 0x1bf _L1e_DevDlsDecodeDciF1A
+ 0x000045b9 0x1d _L1e_DevDlsGetTpmiFieldSize
+ 0x000045d6 0x6b _L1e_DevDlsGetRaType1Info
+ 0x00004641 0x26b _L1e_DevDlsDecodeDualCwDci
+ 0x000048ac 0x17f _L1e_DevDlsDecodeSLSMDci
+ 0x00004a2b 0x176 _zPHY_edls_AdaDecodeDciF1
+ 0x00004ba1 0x8e _zPHY_edls_ProDciF2ALayerCfg
+ 0x00004c2f 0x59 _zPHY_edls_AdaCalRbStartRbLength
+ 0x00004c88 0x8a _zPHY_edls_AdaRbDmpType1
+ 0x00004d12 0x1c2 _zPHY_edls_AdaRbDmpType2Dvrb
+ 0x00004ed4 0x8e _zPHY_edls_AdaRbDmpType2Lvrb
+ 0x00004f62 0x72 _zPHY_edls_AdaRbDmpType01Ctrl
+ 0x00004fd4 0x36 _zPHY_edls_AdaRbDmpType0Bw100Rb
+ 0x0000500a 0x62 _zPHY_edls_AdaRbDmpType0Bw75Rb
+ 0x0000506c 0xb5 _zPHY_edls_AdaRbDmpType0Bw50Rb
+ 0x00005121 0xf9 _zPHY_edls_AdaCalTotalREs
+ 0x0000521a 0x5d _zPHY_edls_CsiRsSfnCal
+ 0x00005277 0xde _zPHY_edls_AdaCalOverlapRbNum
+ 0x00005355 0x2b8 _zPHY_edls_AdaCalTddFddNcpTbREs
+ 0x0000560d 0x10e _zPHY_edls_AdaCalTddFddEcpTbREs
+ 0x0000571b 0xc3 _zPHY_edls_AdaCalTddNcpSpeTbREs
+ 0x000057de 0x92 _zPHY_edls_AdaCalTddEcpSpeTbREs
+ 0x00005870 0x79 _zPHY_edls_AdaGetTbTbs
+ 0x000058e9 0x61 _zPHY_edls_AdaCalTbDecodeParas
+ 0x0000594a 0x3c _zPHY_edls_AdaCalTbCbNum
+ 0x00005986 0x1c _zPHY_edls_AdaCalTbParaKParaC
+ 0x000059a2 0xf0 _zPHY_edls_AdaCalTbParaCEParaE
+ 0x00005a92 0x92 _zPHY_edls_AdaCalTbParaNcbParaK0
+ 0x00005b24 0x45 _zPHY_edls_AdaCalTbK0Start
+ 0x00005b69 0x85 _zPHY_edls_AdaCalTbK1Start
+ 0x00005bee 0x6f _zPHY_edls_AdaCalTbNcbStart
+ .TcmLtePhyCode
+ 0x00005c5d 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_top.o)
+ 0x00005c5d 0x1 _zPHY_DrvTop_IntReg_Clear
+ .TcmLtePhyCode
+ 0x00005c5e 0x15 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_tpu.o)
+ 0x00005c5e 0x15 _L1L_TpuDrvTpuUnregister
+ .TcmLtePhyCode
+ 0x00005c73 0x3f4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00005c73 0x69 _zPHY_erfc_DrvSubframeEventEn
+ 0x00005cdc 0xbb _zPHY_erfc_DrvEventEn
+ 0x00005d97 0x174 _zPHY_erfc_DrvWriteEventEnArrayToABBRamHwReg
+ 0x00005f0b 0x92 _zPHY_erfc_DrvWriteEventEnArrayToDBBNextRamHwReg
+ 0x00005f9d 0x24 _zPHY_erfc_DrvWriteMainEventEnArrayToDBBRamHwReg
+ 0x00005fc1 0x1c _zPHY_erfc_DrvWriteTuReg
+ 0x00005fdd 0x6 _zPHY_erfc_DrvDisableTuReg
+ 0x00005fe3 0x2c _zPHY_erfc_DrvWriteTuRegMrtr
+ 0x0000600f 0x17 _zPHY_erfc_DrvTuRamDisable
+ 0x00006026 0x16 _zPHY_erfc_DrvTuRamEnable
+ 0x0000603c 0x2b _zPHY_erfc_DrvWriteTuRamData
+ .TcmLtePhyCode
+ 0x00006067 0xdc T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc.o)
+ 0x00006067 0x7b _zPHY_erfc_DrvWriteOtherCmdDataToEventTable
+ 0x000060e2 0x61 _zPHY_erfc_DrvWriteCmdDataToEventTable
+ .TcmLtePhyCode
+ 0x00006143 0xa9 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_sched_mc.o)
+ 0x00006143 0xa9 _zPHY_Phy_TdlThreadPriprintf
+ *(.fasttext)
+ .fasttext 0x000061ec 0x242 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_pmi.o)
+ 0x000061ec 0xe7 _Asm_Tx2Rx2_NL2_PMICalc
+ 0x000062d3 0x85 _Asm_NL1_PMICalc
+ 0x00006358 0xd6 _Asm_Tx4Rx2_NL2_PMICalc
+ .fasttext 0x0000642e 0x4b4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_ri.o)
+ 0x0000642e 0x42 _Asm_SumLOGNoSqrt_RICalc
+ 0x00006470 0x85 _Asm_Tx2Rx2_CL_NL1_RICalc
+ 0x000064f5 0x105 _Asm_Tx2Rx2_CDD_RICalc
+ 0x000065fa 0x122 _Asm_Tx4Rx2_CL_NL2_RICalc
+ 0x0000671c 0x41 _Asm_Tx4Rx2_CL_NL1_RICalc
+ 0x0000675d 0x65 _Asm_Rx2_DIV_RICalc
+ 0x000067c2 0x120 _Asm_Tx4Rx2_CDD_RICalc
+ .fasttext 0x000068e2 0x48a T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc_cqi.o)
+ 0x000068e2 0x36 _Asm_CqiSinglePort_TX1_RX1_NL1
+ 0x00006918 0x6d _Asm_CqiTransDiver_Common_NL1
+ 0x00006985 0x8d _Asm_CqiSpatiMulti_RX2_NL1
+ 0x00006a12 0xf3 _Asm_CqiSpatiMulti_RX2_NL2
+ 0x00006b05 0xb0 _Asm_CqiCDD_TX2_RX2_NL2
+ 0x00006bb5 0xff _Asm_CqiCDD_TX4_RX2_NL2
+ 0x00006cb4 0x41 _ASM_Log2
+ 0x00006cf5 0x77 _Asm_RLMSNR_Calc
+ *(.LpcCodeTcm)
+ .LpcCodeTcm 0x00006d6c 0x4d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x00006d6c 0x2e _L1_SocLpModeControlCfg
+ 0x00006d9a 0x1f _L1_SocCpuIdle
+ .LpcCodeTcm 0x00006db9 0x2f T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00006db9 0x2f _L1_CpuEnterIdleMode
+ *(.save_zsp_reg)
+ .save_zsp_reg 0x00006de8 0x50 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ 0x00006de8 0x50 _save_zsp880_reg
+ *Cqi_control.o(.text)
+ *Cqi.o(.text)
+ *CQI_Period.o(.text)
+ allnil*(.text)
+ send*(.text)
+ swap*(.text)
+ timer*(.text)
+ alloc*(.text)
+ arch*(.text)
+ free*(.text)
+ receive*(.text)
+ set_pri*(.text)
+ error*(.text)
+ 0x00006e38 _itcm_end = .
+
+.dtcm 0x00010000 0x63fa load address 0x100f0000
+ 0x00010000 _dtcm_start = .
+ *(.LteDataTcm)
+ .LteDataTcm 0x00010000 0xb T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ 0x00010000 0x2 _g_lte_log_buf
+ 0x00010002 0x2 _g_w_log_buf
+ 0x00010004 0x2 _g_td_log_buf
+ 0x00010006 0x2 _g_sig_log_buf
+ 0x00010008 0x1 _g_bL1CommLogOutUsing
+ 0x00010009 0x2 _g_bL1CommIcpFailCnt
+ .LteDataTcm 0x0001000b 0x1bf T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_tpu.o)
+ 0x0001000b 0x4 _g_tLocalSSFrm
+ 0x0001000f 0x4 _g_tNativeSSFrm
+ 0x00010013 0x2 _g_zPHY_SuperFrameNumber
+ 0x00010015 0x2 _g_pFreeItemsNum
+ 0x00010017 0x1a0 _g_pBusyItemsNum
+ 0x000101b7 0x13 _stTpuInfo
+ *fill* 0x000101ca 0x80000006 00
+ .LteDataTcm 0x000101d0 0x1480 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csi_calc.o)
+ 0x000101d0 0x190 _g_awNo
+ 0x00010360 0x320 _g_adHRx0
+ 0x00010680 0x320 _g_adHRx1
+ 0x000109a0 0x400 _s_awSNR_P1
+ 0x00010da0 0x400 _s_awSNR_P2
+ 0x000111a0 0xc8 _g_awSNR_RLM
+ 0x00011268 0x320 _g_aCqiRamChe
+ 0x00011588 0xc8 _g_aCqiRamNo
+ .LteDataTcm 0x00011650 0x53b T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls.o)
+ 0x00011650 0x53b _g_zPHY_edls_tDlsCb
+ .LteDataTcm 0x00011b8b 0x6 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_lpm.o)
+ 0x00011b8b 0x2 _g_zPHY_InthTpuCnt
+ 0x00011b8d 0x4 _g_zPHY_InthTpuCntDebug
+ *fill* 0x00011b91 0x80000003 00
+ .LteDataTcm 0x00011b94 0x3344 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_cir.o)
+ 0x00011b94 0x2b44 _g_tRxpCirCb
+ 0x000146d8 0x800 _g_awL1eRxCirRam
+ .LteDataTcm 0x00014ed8 0x20 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_eng.o)
+ 0x00014ed8 0x20 _g_tL1lEngDgbInfo
+ .LteDataTcm 0x00014ef8 0xea T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_dbb.o)
+ 0x00014ef8 0x39 _g_zPHY_erfc_atCurrentSFConfig
+ 0x00014f31 0x39 _g_zPHY_erfc_atNextSFConfig
+ 0x00014f6a 0x20 _g_adwzPHY_erfc_RFABBMainSyncEventEnArray
+ 0x00014f8a 0x18 _g_adwzPHY_erfc_RFABBMeas0SyncEventEnArray
+ 0x00014fa2 0x20 _g_adwzPHY_erfc_RFABBTxSyncEventEnArray
+ 0x00014fc2 0x8 _g_adwzPHY_erfc_DBBMainSyncEventEnArray
+ 0x00014fca 0xc _g_adwzPHY_erfc_DBBMeas0SyncEventEnArray
+ 0x00014fd6 0x2 _g_zPHY_erfc_DBBTxSyncEventEn
+ 0x00014fd8 0xa _g_zPHY_erfc_wRamNum
+ .LteDataTcm 0x00014fe2 0x1 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_dfe.o)
+ 0x00014fe2 0x1 _g_zPHY_edfe_cAGCCalMode
+ .LteDataTcm 0x00014fe3 0x1209 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x00014fe3 0x4ad _g_zPHY_SID
+ 0x00015490 0xa82 _g_atzPHY_SAD
+ 0x00015f12 0x118 _g_atzPHY_erfc_CsrcSFData
+ 0x0001602a 0xd2 _g_atzPHY_erfc_RxSFData
+ 0x000160fc 0xf0 _g_atzPHY_erfc_TxSFData
+ *(.LpcDataTcm)
+ .LpcDataTcm 0x000161ec 0x48 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
+ 0x000161ec 0x2 _g_tAtCommM0PsmCtr
+ 0x000161ee 0x2 _g_tAtCommZspPsmCtr
+ 0x000161f0 0x3 _g_tAtCommPsApPsmCtr
+ 0x000161f3 0x10 _g_L1SoCResExpStat
+ 0x00016203 0x2 _g_dSleepLenMs
+ 0x00016205 0x1 _g_wImaskReg
+ 0x00016206 0x2b _g_tLpDebugInfo
+ 0x00016231 0x2 _g_dwPHY_USE_PSM
+ 0x00016233 0x1 _g_bPhyCanSendIcp
+ .LpcDataTcm 0x00016234 0x5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv.o)
+ 0x00016234 0x5 _g_wSharePwrUseBit
+ .LpcDataTcm 0x00016239 0x5 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_irat.o)
+ 0x00016239 0x1 _g_tL1IratLpCtrl
+ 0x0001623a 0x2 _g_L1Lpc_tSlaveShortGapFlg
+ 0x0001623c 0x1 _g_eWdRfCfgFlg
+ 0x0001623d 0x1 _g_eTdRfCfgFlg
+ .LpcDataTcm 0x0001623e 0x3 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_drv_7521.o)
+ 0x0001623e 0x1 _g_L1Lpc_wHarqTurboUsedFlg
+ 0x0001623f 0x1 _g_L1Lpc_w3gSyncUsedFlg
+ 0x00016240 0x1 _g_L1Lpc_w3gDpaUsedFlg
+ .LpcDataTcm 0x00016241 0x6b T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_dev_sleep.o)
+ 0x00016241 0x1 _g_bIsWUsePsm
+ 0x00016242 0x2 _g_tL1wLpCtrl
+ 0x00016244 0x49 _g_tL1wLpcInfo
+ 0x0001628d 0x2 _g_wLpmFactorBefSleep
+ 0x0001628f 0x2 _g_wLpmFactorAftWakeup
+ 0x00016291 0x1 _g_wLpmFactorErrCnt
+ 0x00016292 0x1 _g_bL1wLpcCfunReset
+ 0x00016293 0x2 _g_dwPrintSsfn1
+ 0x00016295 0x2 _g_dwPrintSsfn2
+ 0x00016297 0x2 _g_dwPrintSsfn3
+ 0x00016299 0x2 _g_dwPrintSsfn4
+ 0x0001629b 0x2 _g_dwSleepSchedSsfn
+ 0x0001629d 0x7 _g_tWLpmFactorLast
+ 0x000162a4 0x7 _g_tWLpmFactorCurent
+ 0x000162ab 0x1 _g_wLpmChangeOneDir
+ *(.dncsram)
+ .dncsram 0x000162ac 0x14c T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ 0x000162ac 0x4 _odo_pool_list
+ 0x000162b0 0x100 _odo_pcb_list
+ 0x000163b0 0x1 _odo_max_valid_pid
+ 0x000163b1 0x26 _odo_config
+ 0x000163d7 0x21 _config_int_mask_list
+ .dncsram 0x000163f8 0x2 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ 0x000163f8 0x2 _g_wHookCnt
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(.data)
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(.bss)
+ ../../../../rtos/zcos/os_krn/zcos_zsp880_krn.a(COMMON)
+ init*(COMMON)
+
+.reg_icp1
+ *(.icp_reg)
+
+.reg_icp2
+ *(.icp_reg_m0)
+
+.reg_dma 0x00980000 0x41a
+ *(.dma_reg)
+ .dma_reg 0x00980000 0x41a T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma_reg.o)
+ 0x00980000 0x400 _g_atDmaRegCh
+ 0x00980400 0x2 _g_dDmaIntTcStatus
+ 0x00980402 0x2 _g_dDmaSerrorStatus
+ 0x00980404 0x2 _g_dDmaDerrorStatus
+ 0x00980406 0x2 _g_dDmaCfgError
+ 0x00980408 0x2 _g_dDmaRawIntTcStatus
+ 0x0098040a 0x2 _g_dDmaRawIntSerrorStatus
+ 0x0098040c 0x2 _g_dDmaRawIntDerrorStatus
+ 0x0098040e 0x2 _g_dDmaRawIntCfgErrorStatus
+ 0x00980410 0x2 _g_dDmaWorkingStatus
+ 0x00980412 0x2 _g_dDmaGroupOrder
+ 0x00980414 0x2 _g_dDmaArbitMode
+ 0x00980416 0x2 _g_dDmaIrqType
+ 0x00980418 0x2 _g_dDmaVersion
+
+.reg_icu 0x00400800 0x238
+ *(.icu_reg)
+ .icu_reg 0x00400800 0x238 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+ 0x00400800 0x2 _g_dRegIcuVersion
+ 0x00400802 0x2 _g_dRegIcuReserved1
+ 0x00400804 0x2 _g_dRegIcuReserved2
+ 0x00400806 0x2 _g_dRegIcuReserved3
+ 0x00400808 0x2 _g_dRegIcuIntIrqNum
+ 0x0040080a 0x2 _g_dRegIcuIntFiqNum
+ 0x0040080c 0x2 _g_dRegIcuIrqCur
+ 0x0040080e 0x2 _g_dRegIcuFiqCur
+ 0x00400810 0x2 _g_dRegIcuReserved4
+ 0x00400812 0x2 _g_dRegIcuIntStatus
+ 0x00400814 0x8 _g_dRegIcuReserved5
+ 0x0040081c 0x2 _g_dRegIcuTest
+ 0x0040081e 0x8 _g_dRegIcuIntSigBitSet
+ 0x00400826 0x8 _g_dRegIcuIntClr
+ 0x0040082e 0x8 _g_dRegIcuIntEn
+ 0x00400836 0x8 _g_dRegIcuIntDisEn
+ 0x0040083e 0x2 _g_dRegIcuReserved6
+ 0x00400840 0x100 _g_dRegIcuIntMode
+ 0x00400940 0x2 _g_dRegIcuReserved7
+ 0x00400942 0x2 _g_dRegIcuFiqNum
+ 0x00400944 0x2 _g_dRegIcuClkGateEn
+ 0x00400946 0x2 _g_dRegIcuReserved8
+ 0x00400948 0x8 _g_dRegIcuIntMask
+ 0x00400950 0x30 _g_dRegIcuReserved9
+ 0x00400980 0x8 _g_dRegIcuIntReq
+ 0x00400988 0xa8 _g_dRegIcuReserved10
+ 0x00400a30 0x8 _g_dRegIcuIntSetReq
+
+.reg4 0x7e080000 0x40
+ *(.top_reg)
+ .top_reg 0x7e080000 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_top.o)
+ 0x7e080000 0x2 _g_wL1wTop00SoftReset
+ 0x7e080002 0x2 _g_wL1wTop01GdtrHdtrChoose
+ 0x7e080004 0x2 _g_wL1wTop02Version1
+ 0x7e080006 0x2 _g_wL1wTop03BmiClkGate
+ 0x7e080008 0x2 _g_wL1wTop04ModeCtrl
+ 0x7e08000a 0x2 _g_wL1wTop05FixIqValue
+ 0x7e08000c 0x6 _g_wL1wTopReserved
+ 0x7e080012 0x2 _g_wL1wTop09GateClkCtrl
+ 0x7e080014 0x2 _g_wL1wTopAWdTimingRtVal0
+ 0x7e080016 0x2 _g_wL1wTopBWdTimingRtVal1
+ 0x7e080018 0x2 _g_wL1wTopCWdTimingNtVal0
+ 0x7e08001a 0x2 _g_wL1wTopDWdTimingNtVal1
+ 0x7e08001c 0x2 _g_wL1wTopEDmaIntBypass
+ 0x7e08001e 0x2 _g_wL1wTopReserved1
+ 0x7e080020 0x2 _g_wL1wTop10TpuRakeIntMask
+ 0x7e080022 0x2 _g_wL1wTop11RakeDfeRfcIntMask
+ 0x7e080024 0x2 _g_wL1wTop12TpuCsrAdrHsscchIntMask
+ 0x7e080026 0x2 _g_wL1wTop13CsrDtrPsrIntMask
+ 0x7e080028 0x2 _g_wL1wTop14TpuRakeIntStateMask
+ 0x7e08002a 0x2 _g_wL1wTop15RakeDfeRfcIntStateMask
+ 0x7e08002c 0x2 _g_wL1wTop16TpuCsrAdrHsscchIntStateMask
+ 0x7e08002e 0x2 _g_wL1wTop17CsrDtrPsrIntStateMask
+ 0x7e080030 0x2 _g_wL1wTop18TpuRakeIntStat
+ 0x7e080032 0x2 _g_wL1wTop19RakeDfeRfcIntStat
+ 0x7e080034 0x2 _g_wL1wTop1ATpuCsrAdrHsscchIntState
+ 0x7e080036 0x2 _g_wL1wTop1BCsrDtrPsrIntState
+ 0x7e080038 0x2 _g_wL1wTop1CReserved
+ 0x7e08003a 0x2 _g_wL1wTop1DReserved
+ 0x7e08003c 0x2 _g_wL1wTop1EReserved
+ 0x7e08003e 0x2 _g_wL1wTop1FReserved
+
+.reg5 0x7e080800 0xe0
+ *(.tpu_reg)
+ .tpu_reg 0x7e080800 0xe0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tpu.o)
+ 0x7e080800 0x2 _g_tRegTpuReset
+ 0x7e080802 0x2 _g_tRegTpuMrtrAdjConfig
+ 0x7e080804 0x2 _g_tRegTpuMrtrOffset
+ 0x7e080806 0x2 _g_tRegTpuMrtrCnt
+ 0x7e080808 0x2 _g_tRegTpuMrtrLatch
+ 0x7e08080a 0x2 _g_tRegTpuLocalMrtrCnt
+ 0x7e08080c 0x2 _g_tRegTpuLocalMrtrLatch
+ 0x7e08080e 0x2 _g_tRegTpuMacroCtrl
+ 0x7e080810 0x2 _g_tRegTpuMrtrGoal
+ 0x7e080812 0x2 _g_tRegTpuMrtrAdjustCtrl
+ 0x7e080814 0x2 _g_tRegTpuReserve0
+ 0x7e080816 0x2 _g_tRegTpuNt2RtOffset
+ 0x7e080818 0x2 _g_tRegTpuMrtrSSFN
+ 0x7e08081a 0x2 _g_tRegTpuLocalMrtrSSFN
+ 0x7e08081c 0x2 _g_tRegTpuMrtrSuperfrGoal
+ 0x7e08081e 0x2 _g_tRegTpuTip
+ 0x7e080820 0x4 _g_tRegTpuReserve1
+ 0x7e080824 0x2 _g_tRegTpuRestore
+ 0x7e080826 0x2 _g_tRegTpuSsfnOffRestore
+ 0x7e080828 0x2 _g_tRegTpuSsfnOff
+ 0x7e08082a 0x2 _g_tRegTpuMrtrLatchSSFN
+ 0x7e08082c 0x2 _g_tRegTpuLocalMrtrLatchSSFN
+ 0x7e08082e 0x52 _g_tRegTpuReserve2
+ 0x7e080880 0x36 _g_atRegTpuNtInt
+ 0x7e0808b6 0xa _g_atRegTpuRtInt
+ 0x7e0808c0 0x20 _g_tRegTpuReserve4
+
+.reg6 0x7e082000 0x2420
+ *(.rfc_reg)
+ .rfc_reg 0x7e082000 0x2420 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ 0x7e082000 0x2 _g_dRegRfcReset
+ 0x7e082002 0x2 _g_dRegRfcGpioVal
+ 0x7e082004 0x2 _g_dRegRfcFilterEn
+ 0x7e082006 0x2 _g_dRfcSpiReadData
+ 0x7e082008 0x2 _g_dRfcFAgcEventEn
+ 0x7e08200a 0x2 _g_dRegRfcFAgcRldVal
+ 0x7e08200c 0x4 _g_tRegRfcAnt0FAgcCtrlData
+ 0x7e082010 0x4 _g_tRegRfcAnt1FAgcCtrlData
+ 0x7e082014 0x2 _g_dRegRfcFAgcSpiBitSel
+ 0x7e082016 0x2 _g_dRegRfcFAgcTimeOffst
+ 0x7e082018 0x2 _g_dRegRfcFAgcEn
+ 0x7e08201a 0x2 _g_dRegRfcDebugSel
+ 0x7e08201c 0x2 _g_dRegRfcG1GpioSyncSel
+ 0x7e08201e 0x2 _g_dRegRfcMrtrTpuSel
+ 0x7e082020 0x2 _g_dRegRfcIntSel
+ 0x7e082022 0x2 _g_dRegRfcIntTimeCfg
+ 0x7e082024 0x4 _g_adRegRfcCtrlRamRegEn
+ 0x7e082028 0x8 _g_adRegRfcCtrlRamRx0En0
+ 0x7e082030 0x8 _g_adRegRfcCtrlRamRx0En1
+ 0x7e082038 0x8 _g_adRegRfcCtrlRamRx1En0
+ 0x7e082040 0x8 _g_adRegRfcCtrlRamRx1En1
+ 0x7e082048 0x8 _g_adRegRfcCtrlRamTxEn0
+ 0x7e082050 0x2 _g_dRegRfcUnsualIntClr
+ 0x7e082052 0xe _g_adRegRfcSpiFormatMap
+ 0x7e082060 0x2 _g_dRegRfcRffeDataMap
+ 0x7e082062 0x2 _g_dRegRfcWRfcEn
+ 0x7e082064 0x2 _g_dRegRfcMrtrConCrrnt
+ 0x7e082066 0x8 _g_adRegRfcCtrlRamTxEn1
+ 0x7e08206e 0x2 _g_dRegRfcFAgcCtrlWordAnt01Lsb
+ 0x7e082070 0x2 _g_dRegRfcFAgcCtrlWordAnt11Lsb
+ 0x7e082072 0x2 _g_dRegRfcFAgcCtrlWordAntSecMsb
+ 0x7e082074 0x2 _g_dRegRfcFAgcTimeInterval
+ 0x7e082076 0x18a _g_adReserved5
+ 0x7e082200 0x5a _g_atRegRfcCtrlReg
+ 0x7e08225a 0x6 _g_tRegRfcCtrlReg15
+ 0x7e082260 0x1a0 _g_adReserved6
+ 0x7e082400 0x20 _g_atRegRfcRxTu
+ 0x7e082420 0x1e0 _g_adReserved1
+ 0x7e082600 0x20 _g_atRegRfcTxTu
+ 0x7e082620 0x1e0 _g_adReserved2
+ 0x7e082800 0x40 _g_adRegRfcFastAgcRam
+ 0x7e082840 0x7c0 _g_adReserved3
+ 0x7e083000 0x100 _g_atRegRfcCtrlRamReg
+ 0x7e083100 0x300 _g_adReserved4
+ 0x7e083400 0x400 _g_atRegRfcCtrlRamRx0
+ 0x7e083800 0x400 _g_atRegRfcCtrlRamRx1
+ 0x7e083c00 0x400 _g_atRegRfcCtrlRamTx
+ 0x7e084000 0x2 _g_dRegDfeRxVersion
+ 0x7e084002 0x2 _g_dRegDfeRxReset
+ 0x7e084004 0x2 _g_dRegDfeRxAntEn
+ 0x7e084006 0x2 _g_dRegDfeRxAnt0ClkCtrl
+ 0x7e084008 0x2 _g_dRegDfeRxAnt1ClkCtrl
+ 0x7e08400a 0x2 _g_dRegDfeRxFilterEnDelay
+ 0x7e08400c 0x2 _g_dRegDfeRxDagcDelay
+ 0x7e08400e 0x2 _g_dRegDfeRxCompEn
+ 0x7e084010 0x2 _g_dRegDfeRxEstLen
+ 0x7e084012 0x2 _g_dRegDfeRxAnt0DcEst
+ 0x7e084014 0x2 _g_dRegDfeRxAnt1DcEst
+ 0x7e084016 0x2 _g_dRegDfeRxAnt0DcComp
+ 0x7e084018 0x2 _g_dRegDfeRxAnt1DcComp
+ 0x7e08401a 0x2 _g_dRegDfeRxAnt0IqEstSum
+ 0x7e08401c 0x2 _g_dRegDfeRxAnt1IqEstSum
+ 0x7e08401e 0x2 _g_dRegDfeRxRxAnt0IqCorr
+ 0x7e084020 0x2 _g_dRegDfeRxRxAnt1IqCorr
+ 0x7e084022 0x2 _g_dRegDfeRxIqAmpComp
+ 0x7e084024 0x2 _g_dRegDfeRxIqPhaComp
+ 0x7e084026 0x2 _g_dRegDfeRxHwAgcGainInit
+ 0x7e084028 0x2 _g_dRegDfeRxAgcLfCoff
+ 0x7e08402a 0x2 _g_dRegDfeRxAgcTarget
+ 0x7e08402c 0x2 _g_dRegDfeRxAgcMaxGain
+ 0x7e08402e 0x2 _g_dReserved11
+ 0x7e084030 0x2 _g_dRegDfeRxAgcLfIntEn
+ 0x7e084032 0x2 _g_dRegDfeRxAgcMeanPwr
+ 0x7e084034 0x2 _g_dRegDfeRxAgcLoopOut
+ 0x7e084036 0x2 _g_dReserved12
+ 0x7e084038 0x2 _g_dReserved13
+ 0x7e08403a 0x2 _g_dRegDfeRxAnt0HwAgcGain
+ 0x7e08403c 0x2 _g_dRegDfeRxAnt1HwAgcGain
+ 0x7e08403e 0x2 _g_dRegDfeRxFreqCorrPhaVal
+ 0x7e084040 0x2 _g_dReserved10
+ 0x7e084042 0x2 _g_dRegDfeRxAnt0DagcMeanPwr
+ 0x7e084044 0x2 _g_dRegDfeRxAnt1DagcMeanPwr
+ 0x7e084046 0x2 _g_dRegDfeRxDagcCtrl
+ 0x7e084048 0x2 _g_dRegDfeRxDagcBitSel
+ 0x7e08404a 0x2 _g_dRegDfeRxFifoReset
+ 0x7e08404c 0x2 _g_dRegDfeRxIntfSel
+ 0x7e08404e 0x2 _g_dRegDfeRxDLIntf1Cfg
+ 0x7e084050 0x2 _g_dRegDfeRxDLIntf2Cfg
+ 0x7e084052 0x2 _g_dRegDfeRxDLIntf3Cfg
+ 0x7e084054 0x2 _g_dRegDfeRxDLIntfDebugSel
+ 0x7e084056 0x2 _g_dRegDfeRxDLIntfDebugData
+ 0x7e084058 0x2 _g_dRegDfeRxDLIntfFifoDebug
+ 0x7e08405a 0x2 _g_dRegDfeRxBypass
+ 0x7e08405c 0x2 _g_dRegDfeRxTestCtrl
+ 0x7e08405e 0x2 _g_adReserved9
+ 0x7e084060 0x2 _g_dRegDfeNotchFreq
+ 0x7e084062 0x2 _g_dRegDfeNotchFs
+ 0x7e084064 0x2 _g_dRegDfeNotchStart
+ 0x7e084066 0x2 _g_dRegDfeNotchTimeA
+ 0x7e084068 0x2 _g_dRegDfeNotchTimeBAnt0
+ 0x7e08406a 0x2 _g_dRegDfeNotchParKA
+ 0x7e08406c 0x2 _g_dRegDfeNotchParKBAnt0
+ 0x7e08406e 0x2 _g_dRegDfeNotchParARe
+ 0x7e084070 0x2 _g_dRegDfeNotchParAIm
+ 0x7e084072 0x2 _g_dRegDfeNotchParAOutRe
+ 0x7e084074 0x2 _g_dRegDfeNotchParAOutIm
+ 0x7e084076 0x2 _g_dRegDfeNotchCordicSt
+ 0x7e084078 0x2 _g_dRegDfeNotchTimeBAnt1
+ 0x7e08407a 0x2 _g_dRegDfeNotchParKBAnt1
+ 0x7e08407c 0x2 _g_dRegDfeRxDLIntf4Cfg
+ 0x7e08407e 0x2 _g_dRegDfeRxDLIntf5Cfg
+ 0x7e084080 0x2 _g_dRegDfeRxAgcRamClkSel
+ 0x7e084082 0x2 _g_dRegDfeNotch1TimeA
+ 0x7e084084 0x2 _g_dRegDfeNotch1ParKA
+ 0x7e084086 0x2 _g_dRegDfeNotch2TimeA
+ 0x7e084088 0x2 _g_dRegDfeNotch2ParKA
+ 0x7e08408a 0x2 _g_dRegDfeNotch1TimeBAnt0
+ 0x7e08408c 0x2 _g_dRegDfeNotch1ParKBAnt0
+ 0x7e08408e 0x2 _g_dRegDfeNotch2TimeBAnt0
+ 0x7e084090 0x2 _g_dRegDfeNotch2ParKBAnt0
+ 0x7e084092 0x2 _g_dRegDfeNotch1TimeBAnt1
+ 0x7e084094 0x2 _g_dRegDfeNotch1ParKBAnt1
+ 0x7e084096 0x2 _g_dRegDfeNotch2TimeBAnt1
+ 0x7e084098 0x2 _g_dRegDfeNotch2ParKBAnt1
+ 0x7e08409a 0x2 _g_dRegDfeNotch1ParARe
+ 0x7e08409c 0x2 _g_dRegDfeNotch1ParAIm
+ 0x7e08409e 0x2 _g_dRegDfeNotch2ParARe
+ 0x7e0840a0 0x2 _g_dRegDfeNotch2ParAIm
+ 0x7e0840a2 0x2 _g_dRegDfeNotchbyPass
+ 0x7e0840a4 0x2 _g_dRegDfeFcInitPhase
+ 0x7e0840a6 0x2 _g_dRegDfeFcRotValSum
+ 0x7e0840a8 0x158 _g_adReserved19
+ 0x7e084200 0xc8 _g_adAgcCwTable
+ 0x7e0842c8 0x138 _g_adReserved14
+ 0x7e084400 0x2 _g_dRegDfeTxReset
+ 0x7e084402 0x2 _g_dRegDfeTxAmpCorr
+ 0x7e084404 0x2 _g_dRegDfeTxPhaCorr
+ 0x7e084406 0x2 _g_dRegDfeTxDcComp
+ 0x7e084408 0x2 _g_dRegDfeTxFirBitSel
+ 0x7e08440a 0x2 _g_dRegDfeTxBypassCtrl
+ 0x7e08440c 0x2 _g_dRegDfeTxEnExtnd
+ 0x7e08440e 0x2 _g_dRegDfeTxEnCtrl
+ 0x7e084410 0x2 _g_dRegDfeTxChainEn
+ 0x7e084412 0x2 _g_dRegDfeTxIntfSel
+ 0x7e084414 0x2 _g_dRegDfeTxIntf1Cfg
+ 0x7e084416 0x2 _g_dRegDfeTxIntf2Cfg
+ 0x7e084418 0x2 _g_dRegDfeTxIntf3Cfg
+ 0x7e08441a 0x2 _g_dRegDfeTxClkGate
+ 0x7e08441c 0x2 _g_dRegDfeTxOutEnSel
+ 0x7e08441e 0x2 _g_dRegDfeTxFirDlyNum
+
+.reg7 0x7e084800 0xa00
+ *(.csr_reg)
+ .csr_reg 0x7e084800 0xa00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7e084800 0x2 _g_adCsrReserved2400
+ 0x7e084802 0x2 _g_tRegCsrFpgaVersion
+ 0x7e084804 0x2 _g_tRegCsrTestMode
+ 0x7e084806 0x2 _g_tRegCsrStepIqSel
+ 0x7e084808 0x2 _g_tRegCsrRotate0
+ 0x7e08480a 0x2 _g_tRegCsrRotateParaEn0
+ 0x7e08480c 0x2 _g_tRegCsrRotate1
+ 0x7e08480e 0x2 _g_tRegCsrRotateParaEn1
+ 0x7e084810 0x2 _g_tRegCsrOfflineSPSRRotate
+ 0x7e084812 0x2 _g_tRegCsrReadMrtrReq
+ 0x7e084814 0x2 _g_tRegCsrSetWdtReq
+ 0x7e084816 0x2 _g_tRegCsrIntMrtrValue
+ 0x7e084818 0x2 _g_tRegCsrFreqInd
+ 0x7e08481a 0x2 _g_tRegCsrFxEndBoundary
+ 0x7e08481c 0x2 _g_tRegCsrFxStartBoundary
+ 0x7e08481e 0x2 _g_tRegCsrDataValidEn
+ 0x7e084820 0x2 _g_tRegCsrPatternSoft
+ 0x7e084822 0x2 _g_tRegCsrPatternMode
+ 0x7e084824 0x2 _g_tRegCsrPatternIntEn
+ 0x7e084826 0x2 _g_tRegCsrTopClkGating
+ 0x7e084828 0x2 _g_tRegCsrTestpinSel
+ 0x7e08482a 0x2 _g_tRegCsrSaveDataEn
+ 0x7e08482c 0x2 _g_tRegCsrSaveDataSymNum
+ 0x7e08482e 0x2 _g_tRegCsrFsBuffMrtr
+ 0x7e084830 0x2 _g_tRegCsrFsBuffEndClear
+ 0x7e084832 0x6e _g_adCsrReserved1
+ 0x7e0848a0 0x2 _g_tRegCsrRdMrtrValue
+ 0x7e0848a2 0x2 _g_tRegCsrFsBuffState
+ 0x7e0848a4 0x2 _g_tRegCsrFsBuffEndMrtr
+ 0x7e0848a6 0x15a _g_adCsrReserved2
+ 0x7e084a00 0x2 _g_tRegCsrStep1Reset
+ 0x7e084a02 0x2 _g_tRegCsrNSlot1
+ 0x7e084a04 0x2 _g_tRegCsrStartEn1
+ 0x7e084a06 0x2 _g_tRegCsrMrtrS1
+ 0x7e084a08 0x2 _g_tRegCsrPeakWidth
+ 0x7e084a0a 0x2 _g_tRegCsrPeakMask
+ 0x7e084a0c 0x2 _g_tRegCsrGapModeIndex
+ 0x7e084a0e 0x2 _g_tRegCsrSatCtrlbits
+ 0x7e084a10 0x2 _g_tRegCsrS1ClkGating
+ 0x7e084a12 0x2 _g_tRegCsrStep1Start
+ 0x7e084a14 0x8c _g_adCsrReserved3
+ 0x7e084aa0 0x2 _g_tRegCsrOutMrtrS1
+ 0x7e084aa2 0x2 _g_tRegCsrSlotNo1
+ 0x7e084aa4 0x2 _g_tRegCsrStep1Status
+ 0x7e084aa6 0x2 _g_tRegCsrPowerAvg1
+ 0x7e084aa8 0x158 _g_adCsrReserved4
+ 0x7e084c00 0x2 _g_tRegCsrIcVersion
+ 0x7e084c02 0x2 _g_tRegCsrIcEnable
+ 0x7e084c04 0x2 _g_tRegCsrIcStartPos
+ 0x7e084c06 0x2 _g_tRegCsrIcCpichSlotHead
+ 0x7e084c08 0x2 _g_tRegCsrIcPrar
+ 0x7e084c0a 0x2 _g_tRegCsrIcScramblePra
+ 0x7e084c0c 0x2 _g_tRegCsrIcClkGatingBypas
+ 0x7e084c0e 0x2 _g_tRegCsrIcUpdate
+ 0x7e084c10 0x10 _g_adCsrReserved5
+ 0x7e084c20 0x2 _g_tRegCsrIcScchValue
+ 0x7e084c22 0x2 _g_tRegCsrIcCpichValue
+ 0x7e084c24 0x1dc _g_adCsrReserved6
+ 0x7e084e00 0x2 _g_tRegCsrStep2BReset
+ 0x7e084e02 0x2 _g_tRegCsrNSlot2B
+ 0x7e084e04 0x2 _g_tRegCsrMrtrS2B
+ 0x7e084e06 0x2 _g_tRegCsrTimeAdjMode2B
+ 0x7e084e08 0x2 _g_tRegCsrResyncWinWidth2B
+ 0x7e084e0a 0x8 _g_adCodeGroupListSet
+ 0x7e084e12 0x2 _g_tRegCsrBurstContextS2B
+ 0x7e084e14 0x2 _g_tRegCsrTimingAdjustS2B
+ 0x7e084e16 0x2 _g_tRegCsrMrtrS2BStart
+ 0x7e084e18 0x2 _g_tRegCsrStartEn2B
+ 0x7e084e1a 0x2 _g_tRegCsrS2bClkGateBypass
+ 0x7e084e1c 0x2 _g_tRegCsrStep2BStart
+ 0x7e084e1e 0x82 _g_adCsrReserved7
+ 0x7e084ea0 0x2 _g_tRegCsrMrtrS2BSlot
+ 0x7e084ea2 0x2 _g_tRegCsrSlotNo2B
+ 0x7e084ea4 0x2 _g_tRegCsrSlotNum2B
+ 0x7e084ea6 0x2 _g_tRegCsrGroupNum2B
+ 0x7e084ea8 0x2 _g_tRegCsrCorNormMax2B
+ 0x7e084eaa 0xe _g_atRegCsrAccCorTmPos2B
+ 0x7e084eb8 0x2 _g_tRegCsrMaxTmPosSel2B
+ 0x7e084eba 0x2 _g_tRegCsrSelfResyncS2B
+ 0x7e084ebc 0x2 _g_tRegCsrStep2BStatus
+ 0x7e084ebe 0x2 _g_tRegCsrBurstPatternS2B
+ 0x7e084ec0 0x10 _g_atRegCsrSlotNum2B
+ 0x7e084ed0 0x10 _g_atRegCsrGroupNum2B
+ 0x7e084ee0 0x10 _g_atRegCsrCorNormMax2B
+ 0x7e084ef0 0x10 _g_atRegCsrMaxTmPosSel2B
+ 0x7e084f00 0x2 _g_tRegCsrGrpSumMaxVal2B
+ 0x7e084f02 0xfe _g_adCsrReserved8
+ 0x7e085000 0x2 _g_tRegCsrStep3Reset
+ 0x7e085002 0x2 _g_tRegCsrNSlot3
+ 0x7e085004 0x2 _g_tRegCsrMrtrS3
+ 0x7e085006 0x2 _g_tRegCsrMrtrS3Slot
+ 0x7e085008 0x2 _g_tRegCsrScramblingCodeS3
+ 0x7e08500a 0x2 _g_tRegCsrResyncWinWidthS3
+ 0x7e08500c 0x2 _g_tRegCsrBurstContextS3
+ 0x7e08500e 0x2 _g_tRegCsrMrtrS3Start
+ 0x7e085010 0x2 _g_tRegCsrStartEn3
+ 0x7e085012 0x2 _g_tRegCsrStep3Start
+ 0x7e085014 0x2 _g_tRegCsrStep3ClkBypass
+ 0x7e085016 0x8a _g_adCsrReserved9
+ 0x7e0850a0 0x2 _g_tRegCsrSlotNo3
+ 0x7e0850a2 0x2 _g_tRegCsrCorNormAvg
+ 0x7e0850a4 0x10 _g_atRegCsrCorNormMax3
+ 0x7e0850b4 0x10 _g_atRegCsrTimeAdj3
+ 0x7e0850c4 0x2 _g_tRegCsrStep3Status
+ 0x7e0850c6 0x2 _g_tRegCsrBurstPatternS3
+ 0x7e0850c8 0x138 _g_adCsrReserved10
+
+.reg8 0x7e085200 0xb6
+ *(.meas_reg)
+ .meas_reg 0x7e085200 0xb6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ 0x7e085200 0x2 _g_tL1wRegMeasSoftReset
+ 0x7e085202 0x2 _g_tRegMeasBufOffline
+ 0x7e085204 0x2 _g_tRegMeasBufOffMrtr
+ 0x7e085206 0x2 _g_tRegMeasBufUpdate
+ 0x7e085208 0x2 _g_tRegMeasWorkMode
+ 0x7e08520a 0x2 _g_tRegMeasOnLineMrtr
+ 0x7e08520c 0x2 _g_tRegMeasOnLineAgc0Para
+ 0x7e08520e 0x2 _g_tRegMeasOnLineAgc1Para
+ 0x7e085210 0x2 _g_tRegMeasOnLineAgc0Mrtr
+ 0x7e085212 0x2 _g_tRegMeasOnLineAgc1Mrtr
+ 0x7e085214 0x2 _g_tRegMeasContxtSel
+ 0x7e085216 0x2 _g_tRegMeasSpsrParaCfg
+ 0x7e085218 0x2 _g_tL1wRegMeasSttdMode
+ 0x7e08521a 0x2 _g_tL1wRegMeasCell012
+ 0x7e08521c 0x2 _g_tL1wRegMeasCell345
+ 0x7e08521e 0x2 _g_tL1wRegMeasCell67
+ 0x7e085220 0x10 _g_atL1wMeasCellMrtr
+ 0x7e085230 0x2 _g_tRegMeasClkInfo
+ 0x7e085232 0x2 _g_tRegMeasParaUpdate
+ 0x7e085234 0x6e _g_adReserved
+ 0x7e0852a2 0x2 _g_tRegMeasSpsrStatus
+ 0x7e0852a4 0x2 _g_tRegMeasBurstPattern
+ 0x7e0852a6 0x10 _g_atL1wRegMeasCellAgc
+
+.reg9 0x7e086000 0x200
+ *(.csr_fullscan_reg)
+ .csr_fullscan_reg
+ 0x7e086000 0x200 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7e086000 0x2 _g_tRegCsrFsSoftReset
+ 0x7e086002 0x2 _g_tRegCsrFsAccLen
+ 0x7e086004 0x14 _g_atRegCsrFsDataOffset
+ 0x7e086018 0x28 _g_atRegCsrFsScrambleGroup
+ 0x7e086040 0x2 _g_tRegCsrFsScrambleGroup
+ 0x7e086042 0x2 _g_tRegCsrFsClkGating
+ 0x7e086044 0x2 _g_tRegCsrFsStart
+ 0x7e086046 0x5a _g_adCsrReserved11
+ 0x7e0860a0 0x2 _g_tRegCsrFsFirstDataMrtr
+ 0x7e0860a2 0x14 _g_atRegCsrFsPeakPowerPos
+ 0x7e0860b6 0x14 _g_atRegCsrFsPeakScrambleOffset
+ 0x7e0860ca 0x2 _g_tRegCsrFsInt
+ 0x7e0860cc 0x2 _g_dCsrFsNoise
+ 0x7e0860ce 0x132 _g_adCsrReserved12
+
+.reg10 0x7e086200 0x26e
+ *(.bch_reg)
+ .bch_reg 0x7e086200 0x26e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ 0x7e086200 0x2 _g_uRegBchSoftReset
+ 0x7e086202 0x2 _g_uRegBchTxdMode
+ 0x7e086204 0x2 _g_uRegBchBchPichSel
+ 0x7e086206 0x2 _g_uRegBchTtiSync
+ 0x7e086208 0x2 _g_uRegBchWindowTh
+ 0x7e08620a 0x2 _g_uRegBchPichOvsfK
+ 0x7e08620c 0x6c _g_atRegBchFingerConfig
+ 0x7e086278 0x2 _g_uRegBchClkGate
+ 0x7e08627a 0x186 _g_adRegBchReserved1
+ 0x7e086400 0x48 _g_atRegBchFingerStatus
+ 0x7e086448 0x12 _g_adRegBchViterbiOut
+ 0x7e08645a 0x10 _g_asdRegBchPichData
+ 0x7e08646a 0x2 _g_uRegBchTotalStatus
+ 0x7e08646c 0x2 _g_uRegBchCrcResult
+
+.reg11 0x7e086800 0xb6
+ *(.psr_reg)
+ .psr_reg 0x7e086800 0xb6 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ 0x7e086800 0x2 _g_tRegPsrReset
+ 0x7e086802 0x2 _g_tRegPsrSuspendEn
+ 0x7e086804 0x2 _g_tRegPsrPilotPatternConfig
+ 0x7e086806 0x2 _g_tRegPsrClkGatePassConfig
+ 0x7e086808 0x2 _g_tRegPsrAntSelectCfg
+ 0x7e08680a 0x2 _g_tRegPsrWinPosCfg
+ 0x7e08680c 0x2 _g_tRegPsrRlInfoCfg
+ 0x7e08680e 0x2 _g_tRegPsrMasterRlEn
+ 0x7e086810 0x2 _g_tRegPsrRlSttdCfg
+ 0x7e086812 0x2 _g_tRegPsrPeriodCfg
+ 0x7e086814 0x2 _g_tRegPsrIntInfo
+ 0x7e086816 0xc _g_atRegPsrSrcAndChanCfg
+ 0x7e086822 0xc _g_atRegPsrRlMrtrCfg
+ 0x7e08682e 0x2 _g_tRegPsrStartPosCfg
+ 0x7e086830 0x2 _g_tRegPsrPosEnCfg
+ 0x7e086832 0x2 _g_tRegPsrCmModeConfig
+ 0x7e086834 0x2 _g_tRegPsrCmEnCfg
+ 0x7e086836 0x6a _g_wRegPsrCfg
+ 0x7e0868a0 0x2 _g_tRegPsrIntStatus
+ 0x7e0868a2 0x2 _g_tRegPsrProFileNum
+ 0x7e0868a4 0x2 _g_tRegPsrFrameNum
+ 0x7e0868a6 0x2 _g_tRegPsrWorkStatus
+ 0x7e0868a8 0x2 _g_tRegPsrCfgError
+ 0x7e0868aa 0xc _g_atRegPsrRlPosReports
+
+.reg12 0x7e087000 0x4c
+ *(.tx_reg)
+ .tx_reg 0x7e087000 0x4c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7e087000 0x4c _g_tRegTxReg
+
+.reg13 0x7e087600 0xf2
+ *(.utr_reg)
+ .utr_reg 0x7e087600 0xf2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ 0x7e087600 0xf2 _g_tL1wRegRtxUtrReg
+
+.reg14 0x7e087c00 0x40
+ *(.eutr_reg)
+ .eutr_reg 0x7e087c00 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ 0x7e087c00 0x40 _g_tL1wEutrParaConf
+
+//.reg15
+ *(.rake_reg)
+
+.reg16 0x7e088000 0x480
+ *(.rx_cfg_chip)
+ .rx_cfg_chip 0x7e088000 0x480 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e088000 0x480 _g_tRegRxRakeChipLvl
+
+.reg17 0x7e088800 0x240
+ *(.rx_cfg_symb)
+ .rx_cfg_symb 0x7e088800 0x240 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e088800 0x240 _g_tRegRxRakeSymbLvl
+
+.reg18 0x7e089000 0x38
+ *(.rx_cfg_comb)
+ .rx_cfg_comb 0x7e089000 0x38 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e089000 0x38 _g_tRegRxRakeCombLvl
+
+.reg19 0x7e089800 0xc0
+ *(.rx_cfg_post)
+ .rx_cfg_post 0x7e089800 0xc0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7e089800 0xc0 _g_tRegRxRakePostLvl
+
+.reg20 0x7e08a000 0xc00
+ *(.gdtr_reg)
+ .gdtr_reg 0x7e08a000 0xc00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7e08a000 0x200 _g_tRegRtxDtrReg
+ 0x7e08a200 0x600 _g_adReserve
+ 0x7e08a800 0x400 _g_tRegRtxDtrNewReg
+
+.reg21 0x7e08c000 0x1e
+ *(.eagch_reg)
+ .eagch_reg 0x7e08c000 0x1e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7e08c000 0x1e _g_tRegRtxAgchReg
+
+.adr_reg 0x7e08c400 0x164
+ *(.adr_reg)
+ .adr_reg 0x7e08c400 0x164 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08c400 0x2 _g_dL1wRegAdrVer
+ 0x7e08c402 0x2 _g_tL1wRegAdrCtrl
+ 0x7e08c404 0x4 _g_adL1wRegAdrReserved1
+ 0x7e08c408 0x2 _g_tL1wRegAdrAnt1Slot0Fc
+ 0x7e08c40a 0x2 _g_tL1wRegAdrAnt1Slot1Fc
+ 0x7e08c40c 0x2 _g_tL1wRegAdrAnt1Slot2Fc
+ 0x7e08c40e 0x2 _g_tL1wRegAdrAnt2Slot0Fc
+ 0x7e08c410 0x2 _g_tL1wRegAdrAnt2Slot1Fc
+ 0x7e08c412 0x2 _g_tL1wRegAdrAnt2Slot2Fc
+ 0x7e08c414 0x2 _g_adL1wRegAdrReserved2
+ 0x7e08c416 0x2 _g_tL1wRegAdrRxTxMode
+ 0x7e08c418 0x2 _g_tL1wRegAdrCir
+ 0x7e08c41a 0x2 _g_tL1wRegAdrCirAlpha
+ 0x7e08c41c 0x2 _g_dL1wRegAdrFingerMaskR1T1L
+ 0x7e08c41e 0x2 _g_dL1wRegAdrFingerMaskR1T1H
+ 0x7e08c420 0x2 _g_dL1wRegAdrFingerMaskR1T2L
+ 0x7e08c422 0x2 _g_dL1wRegAdrFingerMaskR1T2H
+ 0x7e08c424 0x2 _g_dL1wRegAdrFingerMaskR2T1L
+ 0x7e08c426 0x2 _g_dL1wRegAdrFingerMaskR2T1H
+ 0x7e08c428 0x2 _g_dL1wRegAdrFingerMaskR2T2L
+ 0x7e08c42a 0x2 _g_dL1wRegAdrFingerMaskR2T2H
+ 0x7e08c42c 0x2 _g_tL1wRegAdrNoiseThresh
+ 0x7e08c42e 0x4 _g_adL1wRegAdrReserved3
+ 0x7e08c432 0x2 _g_tL1wRegAdrDataPscCoeQ
+ 0x7e08c434 0x2 _g_tL1wRegAdrAntLambda
+ 0x7e08c436 0x2 _g_tL1wRegAdrDataPscCoeP
+ 0x7e08c438 0x2 _g_tL1wRegAdrCirFft
+ 0x7e08c43a 0x2 _g_tL1wRegAdrDataFft
+ 0x7e08c43c 0x2 _g_tL1wRegAdrRyyCoeff
+ 0x7e08c43e 0x2 _g_tL1wRegAdrSchCancelCoeff
+ 0x7e08c440 0x2 _g_tL1wRegAdrSchCancel
+ 0x7e08c442 0x2 _g_tL1wRegAdrCpichCodeX
+ 0x7e08c444 0x2 _g_tL1wRegAdrCpichCodeY
+ 0x7e08c446 0x2 _g_tL1wRegAdrHsscchHsdschCodeX
+ 0x7e08c448 0x2 _g_tL1wRegAdrHsscchHsdschCodeY
+ 0x7e08c44a 0x2 _g_tL1wRegAdrCpichHsscchChEn
+ 0x7e08c44c 0x2 _g_tL1wRegAdrHsdsch
+ 0x7e08c44e 0x2 _g_tL1wRegAdrHsscch
+ 0x7e08c450 0x2 _g_tL1wRegAdrChCompsEn
+ 0x7e08c452 0x2 _g_tL1wRegAdrSymCpichAlpha
+ 0x7e08c454 0x2 _g_tL1wRegAdrCltd1
+ 0x7e08c456 0x2 _g_tL1wRegAdrTimeCfg
+ 0x7e08c458 0x2 _g_tL1wRegAdrHsdschParaA
+ 0x7e08c45a 0x2 _g_tL1wRegAdrMemClkBypass
+ 0x7e08c45c 0x2 _g_tL1wRegAdrModuleClkBypass
+ 0x7e08c45e 0x2 _g_tL1wRegAdrAmMean
+ 0x7e08c460 0x2 _g_tL1wRegAdrAnt1EqNoise
+ 0x7e08c462 0x2 _g_tL1wRegAdrAnt2EqNoise
+ 0x7e08c464 0x9c _g_adL1wRegAdrReserved4
+ 0x7e08c500 0x3c _g_atL1wRegAdrCpichData
+ 0x7e08c53c 0x2 _g_dL1wRegAdrReserved5
+ 0x7e08c53e 0x2 _g_tL1wRegAdrCirSlotNum
+ 0x7e08c540 0x2 _g_dL1wRegAdrMaxPowerR1T1
+ 0x7e08c542 0x2 _g_dL1wRegAdrMaxPowerR2T1
+ 0x7e08c544 0x2 _g_dL1wRegAdrMaxPowerR1T2
+ 0x7e08c546 0x2 _g_dL1wRegAdrMaxPowerR2T2
+ 0x7e08c548 0x2 _g_dL1wRegAdrNoisePowerR1
+ 0x7e08c54a 0x2 _g_dL1wRegAdrNoisePowerR2
+ 0x7e08c54c 0x2 _g_dL1wRegAdrMaxPowerR1T1Bak
+ 0x7e08c54e 0x2 _g_dL1wRegAdrMaxPowerR2T1Bak
+ 0x7e08c550 0x2 _g_dL1wRegAdrMaxPowerR1T2Bak
+ 0x7e08c552 0x2 _g_dL1wRegAdrMaxPowerR2T2Bak
+ 0x7e08c554 0x2 _g_dL1wRegAdrNoisePowerR1Bak
+ 0x7e08c556 0x2 _g_dL1wRegAdrNoisePowerR2Bak
+ 0x7e08c558 0x6 _g_adL1wRegAdrCpichT1SlotAbs
+ 0x7e08c55e 0x6 _g_adL1wRegAdrCpichT2SlotAbs
+
+.ic_reg 0x7e08c600 0xd2
+ *(.ic_reg)
+ .ic_reg 0x7e08c600 0xd2 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08c600 0x2 _g_tL1wRegIcVer
+ 0x7e08c602 0x2 _g_tL1wRegIcEnable
+ 0x7e08c604 0x2 _g_tL1wRegIcMode
+ 0x7e08c606 0x2 _g_uL1wRegIcSubFrameHead
+ 0x7e08c608 0x40 _g_tL1wRegIcCellFinger
+ 0x7e08c648 0x10 _g_atL1wRegIcScrcodeXY
+ 0x7e08c658 0x8 _g_atL1wRegIcSchCodeNum
+ 0x7e08c660 0x2 _g_tL1wRegIcBchLambda
+ 0x7e08c662 0x2 _g_tL1wRegIcSchLambda
+ 0x7e08c664 0x2 _g_tL1wRegIcAlpha
+ 0x7e08c666 0x2 _g_tL1wRegIcCpichLambda
+ 0x7e08c668 0x2 _g_tL1wRegIcAnt0Che4xPos
+ 0x7e08c66a 0x2 _g_tL1wRegIcAnt1Che4xPos
+ 0x7e08c66c 0x6 _g_uL1wRegIcAnt0CellSubFrmHead
+ 0x7e08c672 0xc _g_adL1wRegIcReserved1
+ 0x7e08c67e 0x2 _g_tL1wRegIcConfigOver
+ 0x7e08c680 0x18 _g_adL1wRegIcReserved2
+ 0x7e08c698 0x6 _g_uL1wRegAdjIcConfigTime
+ 0x7e08c69e 0x2 _g_tRegIcSubFrmHeadTime
+ 0x7e08c6a0 0x2 _g_uL1wRegIcConfigTime
+ 0x7e08c6a2 0x6 _g_tL1wRegIcCell0CpichSymModulus
+ 0x7e08c6a8 0x6 _g_tL1wRegIcCell1CpichSymModulus
+ 0x7e08c6ae 0x6 _g_tL1wRegIcCell2CpichSymModulus
+ 0x7e08c6b4 0x6 _g_tL1wRegIcCell3CpichSymModulus
+ 0x7e08c6ba 0x6 _g_tL1wRegIcCell0BchSymModulus
+ 0x7e08c6c0 0x6 _g_tL1wRegIcCell1BchSymModulus
+ 0x7e08c6c6 0x6 _g_tL1wRegIcCell2BchSymModulus
+ 0x7e08c6cc 0x6 _g_tL1wRegIcCell3BchSymModulus
+
+.hdtr_reg 0x7e08e000 0xce
+ *(.hdtr_reg)
+ .hdtr_reg 0x7e08e000 0xce T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08e000 0x2 _g_tL1wRegHdtrDemodule
+ 0x7e08e002 0x2 _g_tL1wRegHdtrHsdsch
+ 0x7e08e004 0xa _g_adL1wRegHdtrReserved1
+ 0x7e08e00e 0x2 _g_tL1wRegHdtr2ndRmNtp1
+ 0x7e08e010 0x2 _g_tL1wRegHdtr2ndRmNtp2
+ 0x7e08e012 0x2 _g_tL1wRegHdtr2ndRmNdi
+ 0x7e08e014 0x2 _g_dL1wRegHdtrReserved1
+ 0x7e08e016 0x2 _g_tL1wRegHdtrHarqId
+ 0x7e08e018 0x6 _g_adL1wRegHdtrReserved2
+ 0x7e08e01e 0x2 _g_tL1wRegHdtrTurboCfg
+ 0x7e08e020 0x14 _g_adL1wRegHdtrReserved3
+ 0x7e08e034 0x2 _g_tL1wRegHdtr2ndRmType
+ 0x7e08e036 0x2 _g_tL1wRegHdtr2ndRmEiniSys
+ 0x7e08e038 0x2 _g_tL1wRegHdtr2ndRmEplusSys
+ 0x7e08e03a 0x2 _g_tL1wRegHdtr2ndRmEminusSys
+ 0x7e08e03c 0x2 _g_tL1wRegHdtr2ndRmEiniP1
+ 0x7e08e03e 0x2 _g_tL1wRegHdtr2ndRmEplusP1
+ 0x7e08e040 0x2 _g_tL1wRegHdtr2ndRmEminusP1
+ 0x7e08e042 0x2 _g_tL1wRegHdtr2ndRmEiniP2
+ 0x7e08e044 0x2 _g_tL1wRegHdtr2ndRmEplusP2
+ 0x7e08e046 0x2 _g_tL1wRegHdtr2ndRmEminusP2
+ 0x7e08e048 0x2 _g_tL1wRegHdtr1stRmFlg
+ 0x7e08e04a 0x2 _g_tL1wRegHdtr2ndRmNp1
+ 0x7e08e04c 0x2 _g_tL1wRegHdtr2ndRmNp2
+ 0x7e08e04e 0x2 _g_tL1wRegHdtr1stRmEiniP1
+ 0x7e08e050 0x2 _g_tL1wRegHdtr1stRmEplusP1
+ 0x7e08e052 0x2 _g_tL1wRegHdtr1stRmEminusP1
+ 0x7e08e054 0x2 _g_tL1wRegHdtr1stRmEiniP2
+ 0x7e08e056 0x2 _g_tL1wRegHdtr1stRmEplusP2
+ 0x7e08e058 0x2 _g_tL1wRegHdtr1stRmEminusP2
+ 0x7e08e05a 0x2 _g_dL1wRegHdtrReserved2
+ 0x7e08e05c 0x2 _g_tL1wRegHdtrCodeBlk
+ 0x7e08e05e 0x2 _g_tL1wRegHdtrCrcRslt
+ 0x7e08e060 0x2 _g_tL1wRegHdtrTbSize
+ 0x7e08e062 0x14 _g_adL1wRegHdtrReserved4
+ 0x7e08e076 0x2 _g_tL1wRegHdtrEn
+ 0x7e08e078 0x2 _g_dL1wRegHdtrReserved3
+ 0x7e08e07a 0x2 _g_tL1wRegHdtrHarqAddr
+ 0x7e08e07c 0x2 _g_tL1wRegHdtr2ndRmNtsys
+ 0x7e08e07e 0x2 _g_tL1wRegHdtr2ndRmNsys
+ 0x7e08e080 0x2 _g_tL1wRegHdtrNdataCodeBlkNum
+ 0x7e08e082 0x2 _g_tL1wRegHdtrTbWithCrc
+ 0x7e08e084 0x2 _g_tL1wRegHdtrCtrl
+ 0x7e08e086 0x2 _g_tL1wRegHdtrLlrBitWidth
+ 0x7e08e088 0x4 _g_adL1wRegHdtrReserved5
+ 0x7e08e08c 0x2 _g_tL1wRegHdtrTargetBitWidth
+ 0x7e08e08e 0x2 _g_dL1wRegHdtrReserved8
+ 0x7e08e090 0x2 _g_tL1wRegHdtrHarqBitWidth
+ 0x7e08e092 0x2 _g_tL1wRegHdtrTurboModuleClkMsk
+ 0x7e08e094 0x6 _g_dL1wRegHdtrReserved9
+ 0x7e08e09a 0x2 _g_tL1wRegHdtrDeintlvClkCtrl
+ 0x7e08e09c 0x2 _g_tL1wRegHdtrSoftBitsClkCtrl
+ 0x7e08e09e 0x2 _g_dL1wRegHdtrReserved10
+ 0x7e08e0a0 0x2 _g_tL1wRegHdtrDrmClkCtrl
+ 0x7e08e0a2 0x2 _g_tL1wRegHdtrCrcClkCtrl
+ 0x7e08e0a4 0x2 _g_tL1wRegHdtrTrchRamClkCtrl
+ 0x7e08e0a6 0x2 _g_tL1wRegHdtrTurboSoftReset
+ 0x7e08e0a8 0x2 _g_tL1wRegHdtrStartCfg
+ 0x7e08e0aa 0x2 _g_tL1wRegHdtrDemoduleCfg
+ 0x7e08e0ac 0x14 _g_adL1wRegHdtrReserved6
+ 0x7e08e0c0 0x2 _g_tL1wRegHdtrSubFrm
+ 0x7e08e0c2 0x2 _g_tL1wRegHdtrModuleVer
+ 0x7e08e0c4 0x2 _g_tL1wRegHdtrChipName
+ 0x7e08e0c6 0x2 _g_adL1wRegHdtrReserved7
+ 0x7e08e0c8 0x2 _g_tL1wRegHdtrCrcRedundancy
+ 0x7e08e0ca 0x2 _g_tL1wRegHdtrHrnti
+ 0x7e08e0cc 0x2 _g_tL1wRegHdtrChStart
+
+.reg_hsscch 0x7e08e400 0x4c
+ *(.hsscch_reg)
+ .hsscch_reg 0x7e08e400 0x4c T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08e400 0x2 _g_tL1wRegHsscchCtrl
+ 0x7e08e402 0x2 _g_tL1wRegHsscchMode
+ 0x7e08e404 0x2 _g_tL1wRegHsscchHrnti
+ 0x7e08e406 0x2 _g_tL1wRegHsscchViterbiThresh
+ 0x7e08e408 0x2 _g_tL1wRegHsscchPart1Rcv
+ 0x7e08e40a 0x2 _g_tL1wRegHsscchPart1Flg
+ 0x7e08e40c 0x2 _g_tL1wRegHsscchPart2Rcv
+ 0x7e08e40e 0x2 _g_tL1wRegHsscchHmRslt
+ 0x7e08e410 0x8 _g_atL1wRegHsscchSmRslt
+ 0x7e08e418 0x2 _g_tL1wRegHsscchSmPart1ChMsk
+ 0x7e08e41a 0x8 _g_atL1wRegHsscchS0Dist
+ 0x7e08e422 0x8 _g_atL1wRegHsscchMaxDist
+ 0x7e08e42a 0x8 _g_atL1wRegHsscchMinDist
+ 0x7e08e432 0x8 _g_atL1wRegHsscchPart1Sum
+ 0x7e08e43a 0x2 _g_tL1wRegHsscchPart2Rslt
+ 0x7e08e43c 0x2 _g_tL1wRegHsscchModuleVer
+ 0x7e08e43e 0x2 _g_tL1wRegHsscchChipName
+ 0x7e08e440 0x2 _g_tL1wRegHsscchBcchHrntiEn
+ 0x7e08e442 0x2 _g_tL1wRegHsscchBcchHrntiSmRslt
+ 0x7e08e444 0x2 _g_tL1wRegHsscchBcchHrntiS0Dist
+ 0x7e08e446 0x2 _g_tL1wRegHsscchBcchHrntiMaxDist
+ 0x7e08e448 0x2 _g_tL1wRegHsscchBcchHrntiMinDist
+ 0x7e08e44a 0x2 _g_tL1wRegHsscchBcchHrntiPart1Sum
+
+.reg22 0x7e08e800 0x30
+ *(.pich_reg)
+ .pich_reg 0x7e08e800 0x30 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ 0x7e08e800 0x2 _g_wRegPiAiVersion
+ 0x7e08e802 0x2 _g_tRegPiAiEnble
+ 0x7e08e804 0x2 _g_tRegPichMode
+ 0x7e08e806 0x2 _g_tRegAlpha
+ 0x7e08e808 0x2 _g_tRegRotatePara
+ 0x7e08e80a 0x10 _g_tRegFingerPara
+ 0x7e08e81a 0x2 _g_tRegPiAIOffsetPara
+ 0x7e08e81c 0x2 _g_tRegPiAIOvsfPara
+ 0x7e08e81e 0x2 _g_tRegAfcFingerNum
+ 0x7e08e820 0x2 _g_tRegAichSeqIndex
+ 0x7e08e822 0x2 _g_tRegSetUpdateTime
+ 0x7e08e824 0x2 _g_tRegConfigOver
+ 0x7e08e826 0x4 _g_tRegCpichPower
+ 0x7e08e82a 0x2 _g_tRegAichAmplitude
+ 0x7e08e82c 0x2 _g_tRegConfigState
+ 0x7e08e82e 0x2 _g_tRegConfigTime
+
+.reg23
+ *(.slotbuf_reg)
+
+.less_reg 0x7e08f400 0x280
+ *(.less_reg)
+ .less_reg 0x7e08f400 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7e08f400 0x200 _g_atL1wRegLessTbCfg
+ 0x7e08f600 0x2 _g_tL1wRegLessReset
+ 0x7e08f602 0x2 _g_tL1wRegLessDataOrder
+ 0x7e08f604 0x2 _g_tL1wRegLessHrnti
+ 0x7e08f606 0x2 _g_tL1wRegLessSubFrm
+ 0x7e08f608 0x2 _g_tL1wRegLessTurboCtrl
+ 0x7e08f60a 0x2 _g_tL1wRegLessClkCtrl
+ 0x7e08f60c 0x2 _g_tL1wRegLessLlrRepBitWidth
+ 0x7e08f60e 0x2 _g_tL1wRegLessTranPara
+ 0x7e08f610 0x2 _g_tL1wRegLessUpdate
+ 0x7e08f612 0x6e _g_adL1wRegLessReserved1
+
+.reg24 0x7c080000 0x280
+ *(.csr_reg_ram)
+ .csr_reg_ram 0x7c080000 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_csr.o)
+ 0x7c080000 0x78 _g_atRegCsrStep1Peek
+ 0x7c080078 0x8 _g_adCsrReserved13
+ 0x7c080080 0x78 _g_atRegCsrStep1PeekVal
+ 0x7c0800f8 0x108 _g_adCsrReserved14
+ 0x7c080200 0x80 _g_dwCodeListSet
+
+.reg25 0x7c080400 0xd0
+ *(.meas_ram)
+ .meas_ram 0x7c080400 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_meas.o)
+ 0x7c080400 0xd0 _g_atL1wRegMeasResultInfo
+
+.reg26 0x7c080600 0x300
+ *(.bch_ram)
+ .bch_ram 0x7c080600 0x300 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_bch.o)
+ 0x7c080600 0x300 _g_atRegBchBmiSymbol
+
+.reg27 0x7c088000 0x398
+ *(.psr_data_ram)
+ .psr_data_ram 0x7c088000 0x398 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_psr.o)
+ 0x7c088000 0x180 _g_atRegPsrAnt0RLFingerInfo
+ 0x7c088180 0xc _g_atRegPsrAnt0NoiseMantisse
+ 0x7c08818c 0xc _g_atRegPsrAnt0NoiseFingerCommExp
+ 0x7c088198 0x68 _g_wRegPsrRamCfg
+ 0x7c088200 0x180 _g_atRegPsrAnt1RLsFingerInfo
+ 0x7c088380 0xc _g_atRegPsrAnt1NoiseMantisse
+ 0x7c08838c 0xc _g_atRegPsrAnt1NoiseFingerCommExp
+
+.reg28 0x7c08e000 0xf00
+ *(.tx_ram0)
+ .tx_ram0 0x7c08e000 0xf00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7c08e000 0xf00 _g_atTxRam0
+
+.reg29 0x7c090000 0xf00
+ *(.tx_ram1)
+ .tx_ram1 0x7c090000 0xf00 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_tx.o)
+ 0x7c090000 0xf00 _g_atTxRam1
+
+.reg30 0x7c092000 0x490
+ *(.utr_ram)
+ .utr_ram 0x7c092000 0x490 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_utr.o)
+ 0x7c092000 0x490 _g_awL1wRamUtrData
+
+.reg31 0x7c096000 0x500
+ *(.eutr_ram)
+ .eutr_ram 0x7c096000 0x500 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsupa.o)
+ 0x7c096000 0x500 _g_awL1wRamEutrData
+
+.reg32 0x7c09a000 0x140
+ *(.rx_raw_cpich)
+ .rx_raw_cpich 0x7c09a000 0x140 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a000 0x140 _g_atRegRxRawCpich
+
+.reg33 0x7c09a140 0x40
+ *(.rx_slotwt)
+ .rx_slotwt 0x7c09a140 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a140 0x40 _g_atRegRxSlotwt
+
+.reg34 0x7c09a180 0x40
+ *(.rx_afc)
+ .rx_afc 0x7c09a180 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a180 0x40 _g_atRegRxAfcRam
+
+.reg35 0x7c09a1c0 0x40
+ *(.rx_raw_noise)
+ .rx_raw_noise 0x7c09a1c0 0x40 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a1c0 0x40 _g_atRegRxRawNoise
+
+.reg36 0x7c09a240 0x30
+ *(.rx_comb_tpcpl)
+ .rx_comb_tpcpl
+ 0x7c09a240 0x30 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a240 0x30 _g_tRegRxCombTpcPilot
+
+.reg37 0x7c09a800 0x100
+ *(.rx_pilot)
+ .rx_pilot 0x7c09a800 0x100 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09a800 0x100 _g_atRegRxRawPilot
+
+.reg38 0x7c09ac00 0x14
+ *(.rx_piaipage0)
+ .rx_piaipage0 0x7c09ac00 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ac00 0x14 _g_tRegRxCombPiAiPage0
+
+.reg39 0x7c09ac20 0x14
+ *(.rx_piaipage1)
+ .rx_piaipage1 0x7c09ac20 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ac20 0x14 _g_tRegRxCombPiAiPage1
+
+.reg40 0x7c09c000 0x280
+ *(.rx_dpch0)
+ .rx_dpch0 0x7c09c000 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09c000 0x280 _g_tRegRxCombDpch0
+
+.reg41 0x7c09c800 0x280
+ *(.rx_dpch1)
+ .rx_dpch1 0x7c09c800 0x280 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09c800 0x280 _g_tRegRxCombDpch1
+
+.reg42 0x7c09d800 0xa0
+ *(.rx_scch0)
+ .rx_scch0 0x7c09d800 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09d800 0xa0 _g_tRegRxCombScchPage0
+
+.reg43 0x7c09d900 0xa0
+ *(.rx_scch1)
+ .rx_scch1 0x7c09d900 0xa0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09d900 0xa0 _g_tRegRxCombScchPage1
+
+.reg44 0x7c09dc00 0x28
+ *(.rx_rghi00)
+ .rx_rghi00 0x7c09dc00 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc00 0x28 _g_tRegRxCombRgHiRl0Page0
+
+.reg45 0x7c09dc40 0x28
+ *(.rx_rghi01)
+ .rx_rghi01 0x7c09dc40 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc40 0x28 _g_tRegRxCombRgHiRl0Page1
+
+.reg46 0x7c09dc80 0x28
+ *(.rx_rghi10)
+ .rx_rghi10 0x7c09dc80 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dc80 0x28 _g_tRegRxCombRgHiRl1Page0
+
+.reg47 0x7c09dcc0 0x28
+ *(.rx_rghi11)
+ .rx_rghi11 0x7c09dcc0 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dcc0 0x28 _g_tRegRxCombRgHiRl1Page1
+
+.reg48 0x7c09dd00 0x28
+ *(.rx_rghi20)
+ .rx_rghi20 0x7c09dd00 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd00 0x28 _g_tRegRxCombRgHiRl2Page0
+
+.reg49 0x7c09dd40 0x28
+ *(.rx_rghi21)
+ .rx_rghi21 0x7c09dd40 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd40 0x28 _g_tRegRxCombRgHiRl2Page1
+
+.reg50 0x7c09dd80 0x28
+ *(.rx_rghi30)
+ .rx_rghi30 0x7c09dd80 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09dd80 0x28 _g_tRegRxCombRgHiRl3Page0
+
+.reg51 0x7c09ddc0 0x28
+ *(.rx_rghi31)
+ .rx_rghi31 0x7c09ddc0 0x28 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09ddc0 0x28 _g_tRegRxCombRgHiRl3Page1
+
+.reg52 0x7c09df00 0x14
+ *(.rx_agch0)
+ .rx_agch0 0x7c09df00 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09df00 0x14 _g_tRegRxCombAgchPage0
+
+.reg53 0x7c09df20 0x14
+ *(.rx_agch1)
+ .rx_agch1 0x7c09df20 0x14 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rx.o)
+ 0x7c09df20 0x14 _g_tRegRxCombAgchPage1
+
+.reg54 0x7c0a0000 0x400
+ *(.gdtr_ram)
+ .gdtr_ram 0x7c0a0000 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_dtr.o)
+ 0x7c0a0000 0x400 _g_uRegDtrTtiResultReg
+
+.reg55
+ *(.slotbuf_ram)
+
+.reg56 0x0009a300 0x36
+ *(.sleep_reg)
+ .sleep_reg 0x0009a300 0x36 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_sleep.o)
+ 0x0009a300 0x2 _g_URegLpmTime1CtrlCmd
+ 0x0009a302 0x2 _g_uRegLpmTime1Cfg
+ 0x0009a304 0x2 _g_uRegLpmTime2Cfg
+ 0x0009a306 0x2 _g_uRegLpmTime3Cfg
+ 0x0009a308 0x2 _g_uRegLpmTime4Cfg
+ 0x0009a30a 0x2 _g_uRegLpmTime5PosedgeCfg
+ 0x0009a30c 0x2 _g_uRegLpmTime5EngedgeCfg
+ 0x0009a30e 0x2 _g_uRegLpmMrtrTrace
+ 0x0009a310 0x2 _g_uRegLpmLocalMrtrTrace
+ 0x0009a312 0x2 _g_uRegLpm32KCailSelCfg
+ 0x0009a314 0x2 _g_dRegLpmCount32K
+ 0x0009a316 0x2 _g_dRegLpm15MCountOffset
+ 0x0009a318 0x2 _g_dRegLpmReserve2
+ 0x0009a31a 0x2 _g_dRegLpm32KFactorInteg
+ 0x0009a31c 0x2 _g_dRegLpm32KFactorDecimal
+ 0x0009a31e 0x2 _g_dRegLpm32KSoftFactorInteg
+ 0x0009a320 0x2 _g_dRegLpm32KSoftFactorDecimal
+ 0x0009a322 0x2 _g_dRegLpmSoftReset
+ 0x0009a324 0x2 _g_dRegLpmMrtrOffset
+ 0x0009a326 0x2 _g_uRegLowPowerCtrl
+ 0x0009a328 0x2 _g_dRegLpmSuperframeOff
+ 0x0009a32a 0x2 _g_dRegLpmReserve3
+ 0x0009a32c 0x2 _g_URegLpmTime2CtrlCmd
+ 0x0009a32e 0x2 _g_URegLpmTime3CtrlCmd
+ 0x0009a330 0x2 _g_URegLpmTime4CtrlCmd
+ 0x0009a332 0x2 _g_URegLpmTime5CtrlCmd
+ 0x0009a334 0x2 _g_tRegLpmClkEnDisable
+
+.reg57 0x7c250000 0x34
+ *(.rffe_reg)
+ .rffe_reg 0x7c250000 0x34 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_rfc.o)
+ 0x7c250000 0x2 _g_dRegRffeReset
+ 0x7c250002 0x2 _g_dRegRffeRdSpeedSet
+ 0x7c250004 0xe _g_adReserved16
+ 0x7c250012 0x2 _g_dRegRffeWcdmaRdData
+ 0x7c250014 0x4 _g_adReserved17
+ 0x7c250018 0x2 _g_dRegRffeCh0Packet
+ 0x7c25001a 0x16 _g_adReserved18
+ 0x7c250030 0x2 _g_dRegRffeConCrrnt
+ 0x7c250032 0x2 _g_dRegRffeFreqDiv
+
+.reg58
+ *(.spi_reg)
+
+.adr_ram 0x7c0b0000 0x400
+ *(.adr_ram)
+ .adr_ram 0x7c0b0000 0x400 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7c0b0000 0x80 _g_atL1wRamAdrCirR1T1
+ 0x7c0b0080 0x80 _g_atL1wRamAdrCirR2T1
+ 0x7c0b0100 0x80 _g_atL1wRamAdrCirR1T2
+ 0x7c0b0180 0x80 _g_atL1wRamAdrCirR2T2
+ 0x7c0b0200 0x80 _g_atL1wRamAdrCirR1T1Bak
+ 0x7c0b0280 0x80 _g_atL1wRamAdrCirR2T1Bak
+ 0x7c0b0300 0x80 _g_atL1wRamAdrCirR1T2Bak
+ 0x7c0b0380 0x80 _g_atL1wRamAdrCirR2T2Bak
+
+.hdtr_ram 0x7c0c0000 0xa4e
+ *(.hdtr_ram)
+ .hdtr_ram 0x7c0c0000 0xa4e T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_hsdpa.o)
+ 0x7c0c0000 0xa4e _g_adL1wRamHdtr
+
+.piai_ram 0x7c0c8000 0xd0
+ *(.piai_ram)
+ .piai_ram 0x7c0c8000 0xd0 T:/cp/phy/l1_w/lib/zx297520v3/debug/wphy.a(l1w_reg_piai.o)
+ 0x7c0c8000 0x20 _g_tRegEAISymbolRam
+ 0x7c0c8020 0x20 _g_tRegRservedRam
+ 0x7c0c8040 0x40 _g_tRegPIAISymbolRam
+ 0x7c0c8080 0x50 _g_tRegCpichSymbolRam
+
+.slotbuf_ram
+ *(.slotbuf_ram)
+
+.slotbuf_lte_reg
+ *(.slotbuf_lte_reg)
+
+.td_tpu_reg
+ *(.td_tpu_reg)
+
+.td_top_reg
+ *(.td_top_reg)
+
+.td_csr_reg
+ *(.td_csr_reg)
+
+.td_csr_dpram
+ *(.td_csr_dpram)
+
+.td_rfc_reg
+ *(.td_rfc_reg)
+
+.td_dst_reg
+ *(.td_dst_reg)
+
+.td_dst_dpram
+ *(.td_dst_dpram)
+
+.td_dst_interf_dpram
+ *(.td_dst_interf_dpram)
+
+.td_jd_reg
+ *(.td_jd_reg)
+
+.td_jd_dpram2
+ *(.td_jd_dpram2)
+
+.td_utr_dpram
+ *(.td_utr_dpram)
+
+.td_utr_reg
+ *(.td_utr_reg)
+
+.td_ulc_reg
+ *(.td_ulc_reg)
+
+.td_afc_reg
+ *(.td_afc_reg)
+
+.td_gdtr_reg
+ *(.td_gdtr_reg)
+
+.td_gdtr_dpram
+ *(.td_gdtr_dpram)
+
+.td_ul_hsupa_reg
+ *(.td_ul_hsupa_reg)
+
+.td_ul_hsupa_dpram
+ *(.td_ul_hsupa_dpram)
+
+.td_dm_rdb_reg
+ *(.td_dm_rdb_reg)
+
+.td_hdtr_reg
+ *(.td_hdtr_reg)
+
+.td_hdtr_dpram
+ *(.td_hdtr_dpram)
+
+.td_sleep_reg
+ *(.td_sleep_reg)
+
+.td_pslpm_reg
+ *(.td_pslpm_reg)
+
+.td_uart_reg
+ *(.td_uart_reg)
+
+.td_tfci_reg
+ *(.td_tfci_reg)
+
+.td_viterbi_reg
+ *(.td_viterbi_reg)
+
+.dst_slot_buf
+ *(.dst_slot_buf)
+ 0x00017000 __heap_start = 0x17000
+ 0x00017010 __heap_limit = 0x17010
+ 0x00017fff __stack_start = 0x17fff
+ 0x00017010 __stack_end = __heap_limit
+ 0x00000001 ___ZSP_G3___ = 0x1
+OUTPUT(T:/cp/phy/project/7520_phy_plat_zsp/bin/debug/proj_lte_w_td.out elf32-sdsp)
+
+.comment 0x00000000 0x4875
+ .comment 0x00000000 0x15 /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ .comment 0x00000015 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu.o
+ .comment 0x00000051 0x31 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/dmc_zsp_0x140.o
+ .comment 0x00000082 0x3c T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_int.o
+ .comment 0x000000be 0x3e T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/drv_icu_reg.o
+ .comment 0x000000fc 0x15 T:/cp/phy/project/7520_phy_plat_zsp/temp/zx297520v3/debug/plat/int/zcos_zsp880_asm.o
+ .comment 0x00000112 0x15 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch_asm.o)
+ .comment 0x00000127 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cre_proc.o)
+ .comment 0x0000015b 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(error.o)
+ .comment 0x0000018e 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(init.o)
+ .comment 0x000001c0 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(main.o)
+ .comment 0x000001f2 0x33 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(process.o)
+ .comment 0x00000225 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send.o)
+ .comment 0x00000257 0x34 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(startzcos.o)
+ .comment 0x0000028c 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(swap.o)
+ .comment 0x000002be 0x32 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(alloc.o)
+ .comment 0x000002f0 0x36 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(arch.o)
+ .comment 0x00000327 0x35 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_use_dcfgr_describe.o)
+ .comment 0x0000035c 0x31 T:/cp/phy/rtos/zcos/os_krn/libzspcache.a(dc_descriptor.o)
+ .comment 0x0000038e 0x41 T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_zsp880_cfg.o)
+ .comment 0x000003cf 0x3e T:/cp/phy/rtos/zcos/hal/zsp880/lib/zx297520v3/zsp880.a(zcos_sys.o)
+ .comment 0x0000040d 0x41 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(bsp_timer_zsp880.o)
+ .comment 0x0000044f 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_timer.o)
+ .comment 0x0000048d 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_error_handler.o)
+ .comment 0x000004cd 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_tcm.o)
+ .comment 0x00000509 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(SysEntry.o)
+ .comment 0x00000546 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(rtos_sys.o)
+ .comment 0x00000582 0x3b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_cmn.o)
+ .comment 0x000005be 0x3b T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_dbg.o)
+ .comment 0x000005f9 0x40 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_multimode_cfg.o)
+ .comment 0x0000063a 0x15 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_save_zsp880_reg.o)
+ .comment 0x0000064f 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_l2cache.o)
+ .comment 0x0000068d 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_cache.o)
+ .comment 0x000006ca 0x3c T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_dma.o)
+ .comment 0x00000706 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_rpmsg.o)
+ .comment 0x00000743 0x3e T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(soc_top.o)
+ .comment 0x00000781 0x3d T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(l1_lpc_soc.o)
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+.stab 0x00000000 0x1685d0
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+ .stab 0x00146c1c 0x240 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_db.o)
+ 0x1a28 (size before relaxing)
+ .stab 0x00146e5c 0x27c T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_cmn_dbg.o)
+ 0x1a16 (size before relaxing)
+ .stab 0x001470d8 0x3a3e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_srs.o)
+ 0x5c6a (size before relaxing)
+ .stab 0x0014ab16 0x1a4 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rx_data.o)
+ 0x177c (size before relaxing)
+ .stab 0x0014acba 0x942 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_phich.o)
+ 0x2d5a (size before relaxing)
+ .stab 0x0014b5fc 0x28b0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_agc.o)
+ 0x567c (size before relaxing)
+ .stab 0x0014deac 0x516 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_srs.o)
+ 0x259e (size before relaxing)
+ .stab 0x0014e3c2 0x1b12 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls.o)
+ 0x4734 (size before relaxing)
+ .stab 0x0014fed4 0x13e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_fft_twf.o)
+ 0x4b6 (size before relaxing)
+ .stab 0x00150012 0x3d68 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_fs.o)
+ 0x719a (size before relaxing)
+ .stab 0x00153d7a 0x4eea T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_uls_harq.o)
+ 0x7fa4 (size before relaxing)
+ .stab 0x00158c64 0x1116 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_pss.o)
+ 0x3fde (size before relaxing)
+ .stab 0x00159d7a 0x1fe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_data.o)
+ 0x260a (size before relaxing)
+ .stab 0x00159f78 0x1458 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_ula_pusch.o)
+ 0x3d9e (size before relaxing)
+ .stab 0x0015b3d0 0xa92 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_pusch.o)
+ 0x321c (size before relaxing)
+ .stab 0x0015be62 0x139e T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dfe_dagc.o)
+ 0x3b6a (size before relaxing)
+ .stab 0x0015d200 0x1278 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dls_decbasic.o)
+ 0x146a (size before relaxing)
+ .stab 0x0015e478 0x270 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_pc_data.o)
+ 0x22c8 (size before relaxing)
+ .stab 0x0015e6e8 0x840 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_cfo.o)
+ 0x3678 (size before relaxing)
+ .stab 0x0015ef28 0x3ae T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_dla_pcfich.o)
+ 0x27ba (size before relaxing)
+ .stab 0x0015f2d6 0x1746 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_sss.o)
+ 0x460e (size before relaxing)
+ .stab 0x00160a1c 0x2d66 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr.o)
+ 0x6228 (size before relaxing)
+ .stab 0x00163782 0xe88 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_rxp_ti.o)
+ 0x38e2 (size before relaxing)
+ .stab 0x0016460a 0xd08 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_csr.o)
+ 0x3834 (size before relaxing)
+ .stab 0x00165312 0x1fe T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_drv_rfc_abb_zx220a1_ref.o)
+ 0x266a (size before relaxing)
+ .stab 0x00165510 0xa14 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_log_csr_fs.o)
+ 0x3600 (size before relaxing)
+ .stab 0x00165f24 0x2a0 T:/cp/phy/l1_ltea/lib/zx297520v3/debug/l1_ltea.a(l1l_dev_csr_list.o)
+ 0x492 (size before relaxing)
+ .stab 0x001661c4 0x1b0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(crepool.o)
+ 0x324 (size before relaxing)
+ .stab 0x00166374 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(cresem.o)
+ 0x258 (size before relaxing)
+ .stab 0x00166482 0xe4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(current.o)
+ 0x22e (size before relaxing)
+ .stab 0x00166566 0x186 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(delay.o)
+ 0x2d0 (size before relaxing)
+ .stab 0x001666ec 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(free.o)
+ 0x2ca (size before relaxing)
+ .stab 0x0016686c 0x126 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(get_pri.o)
+ 0x270 (size before relaxing)
+ .stab 0x00166992 0xe4 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(getticks.o)
+ 0x22e (size before relaxing)
+ .stab 0x00166a76 0xc0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(id.o)
+ 0xc6 (size before relaxing)
+ .stab 0x00166b36 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(killsem.o)
+ 0x288 (size before relaxing)
+ .stab 0x00166c74 0x1e0 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(receive.o)
+ 0x32a (size before relaxing)
+ .stab 0x00166e54 0x216 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(s_allnil.o)
+ 0x360 (size before relaxing)
+ .stab 0x0016706a 0x10e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sender.o)
+ 0x258 (size before relaxing)
+ .stab 0x00167178 0x294 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(set_pri.o)
+ 0x3de (size before relaxing)
+ .stab 0x0016740c 0x14a T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(signsem.o)
+ 0x294 (size before relaxing)
+ .stab 0x00167556 0x15c T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(start.o)
+ 0x2a6 (size before relaxing)
+ .stab 0x001676b2 0x480 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(sysd.o)
+ 0x5f4 (size before relaxing)
+ .stab 0x00167b32 0x1c8 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(timer.o)
+ 0x312 (size before relaxing)
+ .stab 0x00167cfa 0x180 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(waitsem.o)
+ 0x2ca (size before relaxing)
+ .stab 0x00167e7a 0x288 T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(hunt.o)
+ 0x3fc (size before relaxing)
+ .stab 0x00168102 0x13e T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(restore.o)
+ 0x288 (size before relaxing)
+ .stab 0x00168240 0x1bc T:/cp/phy/rtos/zcos/os_krn/zcos_zsp880_krn.a(send_w_s.o)
+ 0x306 (size before relaxing)
+ .stab 0x001683fc 0x1d4 T:/cp/phy/l1_comm/7520_asic/lib/zx297520v3/plat.a(drv_efuse.o)
+ 0x660 (size before relaxing)
+
+.stabstr 0x00000000 0x364cca
+ .stabstr 0x00000000 0x364cca /cygdrive/t/cp/phy/project/7520_phy_plat_zsp/dosmake/zcos/crt0.o
+ 0x0 (size before relaxing)
+
+.dmc_data 0x00000000 0x0
+
+.dmc_lp_data 0x00000000 0x0
+ 0x00017010 __stack_end.linker_defined = 0x17010
+ 0x00000ff0 __stack_size.linker_defined = 0xff0
diff --git a/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
new file mode 100755
index 0000000..86ac87e
--- /dev/null
+++ b/Uboot/cp/phy/bin/zx297520v3/merge_lte_220a1_bin/ps/evb_cpuphy_out.7z
Binary files differ
diff --git a/Uboot/cp/ps/driver/src/chipsets/src/audio_base/volte/hal_volte.c b/Uboot/cp/ps/driver/src/chipsets/src/audio_base/volte/hal_volte.c
new file mode 100755
index 0000000..ebdb296
--- /dev/null
+++ b/Uboot/cp/ps/driver/src/chipsets/src/audio_base/volte/hal_volte.c
Binary files differ
diff --git a/Uboot/cp/ps/project/zx297520v3/config/ps/ps_cfg.mk b/Uboot/cp/ps/project/zx297520v3/config/ps/ps_cfg.mk
new file mode 100755
index 0000000..134b508
--- /dev/null
+++ b/Uboot/cp/ps/project/zx297520v3/config/ps/ps_cfg.mk
@@ -0,0 +1,383 @@
+# /*****************************************************************************
+#* °æȨËùÓÐ (C)2015, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+#*
+#* ÎļþÃû³Æ: ps.mk
+#* Îļþ±êʶ: ps.mk
+#* ÄÚÈÝÕªÒª: ÐÒéÕ»ÅäÖÃÎļþ
+#* ʹÓ÷½·¨: include project.mk
+#*
+#* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+#* -----------------------------------------------------------------------------
+#* 2015/05/20 V1.0 ÕûºÏ ÁõÑÇÄÏ ÕûºÏ
+#*
+# ******************************************************************************/
+
+################################################################################
+# ÏîÄ¿°æ±¾ÅäÖÃ,Óû§ÉèÖÃ
+# ±àÒëGSMµ¥Ä£:PS_PRJ_TYPE=gsm
+# ±àÒëTDDµ¥Ä£:PS_PRJ_TYPE=tdd
+# ±àÒëË«Ä£:PS_PRJ_TYPE=tdd_gsm
+# ±àÒëÖ§³Ö2963Ë«Ä£:PS_PRJ_TYPE=tdd_gsm_2963
+# ±àÒëLTEµ¥Ä££ºPS_PRJ_TYPE=lte
+# ±àÒëLTEºÍTDË«Ä££ºPS_PRJ_TYPE=lte_tdd
+# ±àÒëLTE¶àÄ££ºPS_PRJ_TYPE=lte_tdd_gsm
+#±àÒë:wcdma_r6
+#±àÒë:wcdma_r8
+#±àÒë:wcdma_r9
+#±àÒë:wcdma_gsm_r6
+#±àÒë:wcdma_gsm_r8
+#±àÒë:wcdma_gsm_r9
+#±àÒë:lte_wcdma_r9
+#±àÒë:lte_wcdma_gsm_R8
+#±àÒë:lte_wcdma_gsm_R9
+#±àÒë:lte_wcdma_tdd_gsm
+#±àÒë:lte_gsm
+################################################################################
+export PS_PRJ_TYPE = lte_wcdma_tdd_gsm
+
+ifeq ($(USE_DUAL_CARD_DUAL_STANDBY), yes)
+DEFINE += -DDUAL_CARD_DUAL_STANDBY
+endif
+
+ifeq ($(USE_DSDS_VSIM), yes)
+DEFINE += -DDSDS_VSIM
+endif
+
+#*******************************************************************************
+# RAT¹¦ÄÜ¿ª¹Ø
+#*******************************************************************************
+ifeq ($(USE_RAT_TDS), yes)
+DEFINE += -DPS_RAT_TDD
+endif
+
+ifeq ($(USE_RAT_WCDMA), yes)
+DEFINE += -DPS_RAT_FDD
+endif
+
+ifeq ($(USE_RAT_LTE), yes)
+DEFINE += -DPS_RAT_LTE
+endif
+
+
+ifeq ($(USE_RAT_TDS), no)
+export PS_PRJ_TYPE = lte_wcdma_gsm_R9
+
+ifeq ($(USE_L1G), no)
+export PS_PRJ_TYPE = lte_wcdma_r9
+
+ifeq ($(USE_RAT_WCDMA), no)
+export PS_PRJ_TYPE = lte
+endif
+endif
+endif
+
+
+
+#===============================================================================
+# ÊÇ·ñÓÐÕæʵSIM(USIM)¿¨£¬Óû§ÉèÖÃ
+# Óп¨´æÔÚ:PS_PRJ_NOCARD=no
+# ûÓп¨:PS_PRJ_NOCARD=yes
+#===============================================================================
+export PS_PRJ_NOCARD = no
+
+#===============================================================================
+# ÊÇ·ñʹÓÃÄ£ÄâÎïÀí²ã
+# yes:ʹÓÃÄ£ÄâÎïÀí²ã
+# no:²»Ê¹ÓÃÄ£ÄâÎïÀí²ã
+#===============================================================================
+export PS_USE_SIM_PHY = no
+####################################################################################################
+# ºê¶¨Òå
+####################################################################################################
+
+#===============================================================================
+# ûÓÐÕæʵÎïÀí²ãʱÐèÒª´ò¿ªÄ£ÄâÎïÀí²ãµÄºê
+#===============================================================================
+ifeq ($(PS_USE_SIM_PHY), yes)
+DEFINE += -DZ_SEND_TO_SIMPHY #Ä£ÄâÎïÀí²ãºê
+#DEFINE += -DZ_SIM_CIPHER #¼ÓÃÜÄ£Äâºê
+DEFINE += -DZ_SIM_AMR #AMRÄ£Äâºê
+DEFINE += -DSDTENV #by zyn
+endif
+
+#===============================================================================
+# ûÓÐÕæʵSIM¿¨Ê±ÐèÒª´ò¿ªµÄºê
+#===============================================================================
+ifeq ($(PS_PRJ_NOCARD), yes)
+DEFINE += -DZ_SIM_UICC #UICCÄ£Äâºê
+endif
+
+#===============================================================================
+# ÐÒéÕ»Ïà¹Øºê¶¨Òå
+#===============================================================================
+DEFINE += -DZ_IGNORE_SECURITY
+DEFINE += -DZ_TEST_AGENT
+#DEFINE += -DZ_FOR_TEST
+#DEFINE += -DR9_SUPPORT
+#DEFINE += -DR8_SUPPORT
+#DEFINE += -DR6_SUPPORT
+DEFINE += -DINTERRAT_SUPPORT
+DEFINE += -DPS_TG_USE_PS_HO
+#DEFINE += -DZ_CDEC_FOR_TOOL
+#DEFINE += -DZ_SIM_CIPHER
+DEFINE += -DLTE_R9_SUPPORT
+DEFINE += -D_USE_GLOBAL_TRACE
+#DEFINE += -DZ_SIM_AMR #AMRÄ£Äâºê
+DEFINE += -D_CHIP_ZX297520_LATER
+DEFINE += -DLTE_R10_DEFAULT_SUPPORT
+DEFINE += -DNAS_FULL_USAT_SUPPORT #usatÈ«¹¦ÄÜ
+DEFINE += -DUSAT_USER_REF #usatÓû§½çÃæ½»»¥¹¦ÄÜ
+
+#===============================================================================
+# ECID¹¦Äܺ꣺
+# _USE_LPP_ECID£º´ò¿ªÕâ¸öºê±íʾ֧³ÖECID¹¦ÄÜ£»
+#===============================================================================
+DEFINE += -D_USE_LPP_ECID
+
+#===============================================================================
+# ÐÅÁî¸ú×Ù¿ØÖƺ꣺
+# _USE_SIG_TRACE£º´ò¿ªÕâ¸öºê±íʾÐèÒª½øÐÐÐÅÁî¸ú×Ù£»
+#===============================================================================
+DEFINE += -D_USE_SIG_TRACE
+
+#===============================================================================
+# Òì³£ÐÅÏ¢¿ØÖƺ꣺
+# _USE_EXCP_TRACE£º´ò¿ªÕâ¸öºê±íʾÐèÒª½øÐÐÒì³£ÐÅÏ¢Éϱ¨£»
+#===============================================================================
+ifeq ($(USE_DSDS_VSIM), yes)
+DEFINE += -D_USE_EXCP_TRACE
+endif
+
+#===============================================================================
+# QXDMÉϱ¨¿ØÖƺ꣺
+# _USE_COMSIG_TRACE£º´ò¿ªÕâ¸öºê±íʾÐèÒªÐÒéÕ»Éϱ¨±ê×¼log£¨¼´QXDMµÄ¶ÔÍâ½Ó¿Ú˵Ã÷ÖÐËùÓÐÉϱ¨ÏûÏ¢£©£»
+#===============================================================================
+DEFINE += -D_USE_COMSIG_TRACE
+
+#===============================================================================
+# ATI2_3GPP_R5£º¶¨Òå±íʾATIÖ§³Ö3GPP R5°æ±¾
+# ATI2_3GPP_R7£º¶¨Òå±íʾATIÖ§³Ö3GPP R7°æ±¾
+# R9_SUPPORT£º¶¨Òå±íʾATIÖ§³Ö3GPP R9°æ±¾
+#ÕâÈý¸öºê¶¨ÒåÊÇ»¥³âµÄ£¬°æ±¾ÖÐÖ»¿ªÒ»¸ö
+#===============================================================================
+#DEFINE += -DATI2_3GPP_R7
+
+#===============================================================================
+# ATI_FOR_2963£º¿ØÖÆATIÖÐTGÓëLTEµÄ²îÒ죬Ŀǰ½öÔÚ TG°æ±¾(296300/296320)ÖпªÆô
+#===============================================================================
+#DEFINE += -DATI_FOR_2963
+
+
+#===============================================================================
+# ZSTM_SUPPT_EFBAK£º¶¨Òå±íʾ´ò¿ªSTM±¸·Ý¹¦ÄÜ
+#===============================================================================
+#DEFINE += -DZSTM_SUPPT_EFBAK
+
+#===============================================================================
+# ZSTM_SUPPT_EFBAK_ONREAD£º¶¨ÒåÕâ¸öºê±íʾÔÚÖ§³Ö±¸·ÝµÄÇé¿öÏ£¬ÔÚµÚÒ»´Î¶ÁÈ¡Êý¾Ýʱ
+# ±¸·Ýµç»°±¾Êý¾Ý£¨¶ø²»ÊÇ¿ª»ú±¸·Ý£©£¬Ç°ÖÃÌõ¼þ¶¨ÒåZSTM_SUPPT_EFBAK
+#===============================================================================
+#DEFINE += -DZSTM_SUPPT_EFBAK_ONREAD
+
+ifeq ($(PRJ_NAME), zx297502)
+DEFINE += -DZ_LTE_SIMEDCP_AND_REALEDCP_SIMULTANEOUS
+endif
+
+ifeq ($(PRJ_NAME), zx297510)
+DEFINE += -D_USE_ETWS_REPORT
+endif
+
+################################################################################
+# gsmµ¥Ä£ÐèÒª´ò¿ªµÄºê
+
+################################################################################
+ifeq ($(PS_PRJ_TYPE), gsm)
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -D_USE_GSM
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN -DR8_SUPPORT -DR6_SUPPORT
+endif
+################################################################################
+# TDDµ¥Ä£ÐèÒª´ò¿ªµÄºê
+
+################################################################################
+ifeq ($(PS_PRJ_TYPE), tdd)
+DEFINE += -DINDUSTRY_STANDARD -DR7_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY -DR8_SUPPORT -DR6_SUPPORT
+endif
+
+################################################################################
+# LTEÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte)
+DEFINE += -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN -DZPS_ENODEB_TEST -DNEW_PS_BUF
+DEFINE += -DZ_ENODEB_TEST -DZ_LTE_ENABLE_SECURITY -DDEBUG_LTE_IT_ON_BOARD -DLITTLE_ENDIAN
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -D_USE_LTE_GCF -DZ_IGNORE_SECURITY -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -D_USE_DRV_OPTIMIZATION -D_USE_FREQ_AMTNV -D_USE_LPM_INTERRUPT
+endif
+
+################################################################################
+# TDD_GSMÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), tdd_gsm)
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DINDUSTRY_STANDARD -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -DR7_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN -DR8_SUPPORT -DR6_SUPPORT
+endif
+
+################################################################################
+# TDD_GSMÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), tdd_gsm_2963)
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DINDUSTRY_STANDARD -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -DR7_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY -DMULTI_IRAT_2963
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN
+endif
+
+################################################################################
+# TDD_GSMÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_tdd)
+#DEFINE += -DINDUSTRY_STANDARD -DR7_SUPPORT -DZ_UE_UNUSED_CDEC -DZ_LTE_ENABLE_SECURITY -DZ_SIM_PSI -DDEBUG_LTE_IT -DDEBUG_LTE_IT_ON_BOARD -DZ_SIM_AMR -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -DINDUSTRY_STANDARD -DR7_SUPPORT -DZ_UE_UNUSED_CDEC -DZ_SIM_PSI -DDEBUG_LTE_IT_ON_BOARD -DZ_SIM_AMR -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -D_USE_LTE_GCF -DR8_SUPPORT -DR6_SUPPORT
+endif
+
+################################################################################
+# LTE_TDD_GSMÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_tdd_gsm)
+#DEFINE += -DDEBUG_LTE_IT -DZ_LTE_ENABLE_SECURITY -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DINDUSTRY_STANDARD -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -DR7_SUPPORT -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY -DDEBUG_LTE_IT_ON_BOARD -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -DZ_LTE_ENABLE_SECURITY -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DINDUSTRY_STANDARD -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -DR7_SUPPORT -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY -DDEBUG_LTE_IT_ON_BOARD -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -D_USE_GSM -D_USE_SDL -DLITTLE_ENDIAN -DZPS_ENODEB_TEST
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -DR8_SUPPORT -DR6_SUPPORT
+DEFINE += -D_USE_LTE_GCF
+endif
+
+################################################################################
+# wcdma_r6ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), wcdma_r6)
+DEFINE += -DR6_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN
+endif
+
+################################################################################
+# wcdma_r8ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), wcdma_r8)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN
+endif
+
+################################################################################
+# wcdma_r9ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), wcdma_r9)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DW_R9_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN
+endif
+
+################################################################################
+# wcdma_gsm_r6ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), wcdma_gsm_r6)
+DEFINE += -DR6_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -D_USE_GSM
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN
+endif
+
+################################################################################
+# wcdma_gsm_r8ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), wcdma_gsm_r8)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -D_USE_GSM
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN
+endif
+
+################################################################################
+# wcdma_gsm_r9ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), wcdma_gsm_r9)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DW_R9_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -D_USE_GSM
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN
+endif
+
+################################################################################
+# lte_wcdma_r9ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_wcdma_r9)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DW_R9_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH
+DEFINE += -DZ_UE_UNUSED_CDEC -DDL_DATA_DWORD_ALIGN -DZPS_ENODEB_TEST -DPDCP_PDU_IN_PSBUFFER -DNEW_PS_BUF
+DEFINE += -DZ_ENODEB_TEST -DZ_LTE_ENABLE_SECURITY -DDEBUG_LTE_IT_ON_BOARD -DLITTLE_ENDIAN
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -D_USE_LTE_GCF -DZ_IGNORE_SECURITY -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -D_USE_DRV_OPTIMIZATION -D_USE_FREQ_AMTNV -D_USE_LPM_INTERRUPT
+endif
+
+################################################################################
+# lte_wcdma_gsm_R8ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_wcdma_gsm_R8)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC
+DEFINE += -DZ_ENODEB_TEST -DZ_LTE_ENABLE_SECURITY -DDEBUG_LTE_IT_ON_BOARD
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -D_USE_GSM
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -D_USE_LTE_GCF -DDL_DATA_DWORD_ALIGN
+endif
+
+################################################################################
+# lte_wcdma_gsm_R9ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_wcdma_gsm_R9)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DW_R9_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DZ_USCH -DZ_USCH -DZ_UE_UNUSED_CDEC
+DEFINE += -DZ_ENODEB_TEST -DZ_LTE_ENABLE_SECURITY -DDEBUG_LTE_IT_ON_BOARD
+DEFINE += -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -D_USE_GSM
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -DLITTLE_ENDIAN
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -D_USE_LTE_GCF -DDL_DATA_DWORD_ALIGN
+endif
+
+################################################################################
+# lte_wcdma_gsm_R9ÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_wcdma_tdd_gsm)
+DEFINE += -DR6_SUPPORT -DW_R8_SUPPORT -DW_R9_SUPPORT -DR7_SUPPORT -DR8_SUPPORT -DINDUSTRY_STANDARD
+DEFINE += -DZ_LTE_ENABLE_SECURITY -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -DR7_SUPPORT -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY -DDEBUG_LTE_IT_ON_BOARD -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -D_USE_GSM -D_USE_SDL -DLITTLE_ENDIAN -DZPS_ENODEB_TEST
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -DPDCP_PDU_IN_PSBUFFER -DNEW_PS_BUF
+DEFINE += -D_USE_LTE_GCF -DDL_DATA_DWORD_ALIGN -D_USE_DRV_OPTIMIZATION -D_USE_FREQ_AMTNV
+DEFINE += -D_USE_LPM_INTERRUPT -D_USE_EXCP_TRACE
+endif
+
+
+################################################################################
+# LTE_GSMÐèÒª´ò¿ªµÄºê
+################################################################################
+ifeq ($(PS_PRJ_TYPE), lte_gsm)
+DEFINE += -DZ_LTE_ENABLE_SECURITY -DPARANOID -DRLC_PEDANTIC -DXUSE_GENERIC_FUNC -DINDUSTRY_STANDARD -DCOMNEON_TARGET_ENV -DPS_RAT_GSM -DR7_SUPPORT -DZ_UE_UNUSED_CDEC -DZ_IGNORE_SECURITY -DDEBUG_LTE_IT_ON_BOARD -DLTE_REAL_EDCP_ON_BOARD
+DEFINE += -DEGPRS_SUPPORT -DR5_SUPPORT -DR4_SUPPORT -DEGPRS_IR_SUPPORT -D_USE_GSM -D_USE_SDL -DLITTLE_ENDIAN -DZPS_ENODEB_TEST
+DEFINE += -DZ_AVOID_KEYSIB_BAR_CELL -DR8_SUPPORT -DR6_SUPPORT
+DEFINE += -D_USE_LTE_GCF
+endif
+
+
+#===============================================================================
+# Ë«´ý°æ±¾ºê£º
+# Z_DUALSTAND£º´ò¿ªÕâ¸öºê±íʾÊÇË«´ý°æ±¾£»
+#===============================================================================
+ifeq ($(USE_DUAL_STANDBY),yes)
+DEFINE += -DZ_DUALSTAND
+endif
+
+#===============================================================================
+# ÓïÒô¹¦Äܺ꣺
+# USE_VOICE_SUPPORT£º´ò¿ªÕâ¸öºê±íʾ°æ±¾Ö§³ÖVOICE¹¦ÄÜ£»
+#===============================================================================
+ifeq ($(USE_VOICE_SUPPORT),yes)
+DEFINE += -DUSE_VOICE_SUPPORT
+endif
+
+#===============================================================================
+# ¼¯Èº¹¦Äܺ꣺
+# USE_BTRUNK_SUPPORT£º´ò¿ªÕâ¸öºê±íʾ°æ±¾Ö§³Ö¼¯Èº¹¦ÄÜ£»
+#===============================================================================
+ifeq ($(USE_BTRUNK_SUPPORT),yes)
+DEFINE += -D_R2_SUPPORT
+endif
+
+ifeq ($(USE_ECALL_SUPPORT),yes)
+DEFINE += -DECALL_SUPPORT
+endif
diff --git a/Uboot/pub/include/ps_phy/psevent.h b/Uboot/pub/include/ps_phy/psevent.h
new file mode 100755
index 0000000..d1fbdf8
--- /dev/null
+++ b/Uboot/pub/include/ps_phy/psevent.h
@@ -0,0 +1,5172 @@
+/*****************************************************************************
+ *°æ±¾ËùÓÐ (C)2007ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
+ * Ä£¿éÃû £ºPUB
+ * ÎļþÃû £ºpsEvent.h
+ * Îļþ±êʶ£º
+ * Ïà¹ØÎļþ£º
+ * ʵÏÖ¹¦ÄÜ£ºÐÒéÕ»Èí¼þʼþºÅ¶¨Òå
+ * ×÷Õß £º
+ * °æ±¾ £º
+ * Íê³ÉÈÕÆÚ£º
+ * ÆäËü˵Ã÷£º
+ *
+ * Ð޸ļǼºÅ ÈÕÆÚ ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+ 1 2008.02.23 ½ºè 1)ÐÒéÕ»ÐèÒªºÍCOMNEON´úÂ뻥ͨ£¬ÆäʼþºÅ¶¨ÒåΪ16λ¡£¹ÊÏÞÖÆÐÒéջʼþºÅÓÐЧ·¶Î§ÎªµÍ16λ¡£
+ 2 2008.05.14 ½ºè 1)Ôö¼ÓÁËSCIÓëURRC/CCÖ®¼äµÄʼþºÅ¶¨Òå
+ 3 2008.05.15 ½ºè 1)Ôö¼ÓÁËCCÓëURRC¼äµÄʼþºÅ¶¨Òå:GMMAS_CALLTYPENOTIFYREQ_EV
+ 4 2008.05.19 ½ºè 1Ôö¼ÓTAFÓëL1G¼äµÄʼþºÅ¶¨Òå
+ 5 2008.05.29 ½ºè 1)Ôö¼ÓGSM²âÊÔÄ£¿é¼äʼþºÅ
+ 6 2008.06.05 ½ºè 1)Ôö¼ÓGVAR_SCI_GETREQ_EV¡¢GVAR_SCI_GETCNF_EV¡¢CSCI_CONFIGREL_EV
+ 7 2008.06.12 ½ºè 1)Ôö¼ÓATIÓëCSD¼äµÄʼþºÅ¶¨Òå
+ 8 2008.06.12 ½ºè 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁË£º
+ LLGMM_USERDATAPRESENT_EV;
+ GMMAS_ASSIGNREQ_EV¡¢GMMAS_INFOREQ_EV¡¢GMMAS_SUSPENDIND_EV
+ CPDI_SENDDATAIND_EV£»
+ SM_PDCP_RATACTIND_EV¡¢SM_PDCP_RATACTRSP_EV¡¢SM_PDCP_RATDEACTIND_EV¡¢
+ SM_PDCP_RATSEQIND_EV¡¢SM_PDCP_RATSEQRSP_EV¡¢SM_PDCP_READYIND_EV£»
+ SNSM_RATDEACTRSP_EV£»
+ UMMAS_PLMNLISTREJ_EV¡¢UMMAS_PCHPRE_REQ¡¢UMMAS_ABORTHPPLMNREQ_EV¡¢
+ UMMAS_UPDATEPARAMREQ_EV¡¢UMMAS_INACTIVEREQ_EV¡¢UMMAS_INACTIVECNF_EV¡¢
+ UMMAS_RATCHNIND_EV¡¢UMMAS_HOSTARTIND_EV¡¢UMMAS_CCOSTARTIND_EV
+ 9 2008.06.14 ½ºè 1)Ôö¼ÓTOOL_NGMAC_PMO_REQ_EV¡¢TOOL_NGMAC_PSI_REQ_EV¶¨Òå
+ 2)¸üÃû£ºUMMAS_PCHPRE_REQ £½¡·UMMAS_PCHPREREQ_EV
+ 10 2008.06.16 ËïÒÔÀ× 1)Ôö¼ÓSNDCP-SMÖ®¼äʼþºÅ
+ 2)Ôö¼ÓGSMA²âÊÔʼþºÅ:GVAR_GSMA_GETREQ_EV¡¢GVAR_GSMA_GETCNF_EV
+ 11 2008.06.17 ÕÅÅô³Ì 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁËURRC-GRR¡¢URRCÄÚ²¿¡¢URRC-PHYÖ®¼äʼþºÅ
+ 12 2008.06.18 ÕÅÅô³Ì 1)Ôö¼ÓUMMAS_TRYHPPLMNCNF_EV
+ 13 2008.06.18 ½ºè 1)ÐÞ¸ÄÁËURRC-GRRÖ®¼äʼþºÅÃû³Æ
+ 14 2008.06.19 ÍõÀò 1)Ôö¼ÓSNSM_READYIND_EV,ɾ³ýSNSM_RATDEACTRSP_EV
+ 15 2008.06.20 ËïȪ 1)Ôö¼ÓTOOL_L1SIMU_DCCHFAIL_CFG_EV
+ 16 2008.06.20 ÕÅÅô³Ì 1)Ôö¼ÓURRCGRR_CAMPONCELLCNF_EV¡¢URRCGRR_CAMPONCELLIND_EV
+ 17 2008.06.30 Ç®¿¡ 1)Ôö¼ÓNGMACʼþºÅ:
+ TOOL_NGMAC_ULTBF_EST_CFG_EV ¡¢TOOL_NGMAC_DLTBF_EST_CFG_EV
+ TOOL_NGMAC_ULTBF_REL_CFG_EV ¡¢TOOL_NGMAC_DLTBF_REL_CFG_EV
+ TOOL_NGMAC_PKTTSRECFG_REQ_EV ¡¢TOOL_NGMAC_PKTTBFREL_REQ_EV
+ TOOL_NGMAC_PKTPDCHREL_REQ_EV ¡¢TOOL_NGMAC_PKTCCC_REQ_EV
+ TOOL_NGMAC_PKTCCO_REQ_EV ¡¢TOOL_NGMAC_PKTNCD_REQ_EV
+ TOOL_NGMAC_PKTPOLL_REQ_EV ¡¢TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV
+ TOOL_NGMAC_PKTPRACHPARA_REQ_EV ¡¢TOOL_NGMAC_PKTSCD_REQ_EV
+ TOOL_NGMAC_PKTQUENOTI_REQ_EV ¡¢TOOL_NGMAC_PKTACCREJ_REQ_EV
+ NGMAC_TOOL_PKTMEARPT_EV¡¢NGMAC_TOOL_PKTMOBTBFSTA_EV
+ NGMAC_TOOL_PKTPSISTA_EV ¡¢NGMAC_TOOL_PKTPAUSE_EV
+ NGMAC_TOOL_PKTEMEARPT_EV ¡¢NGMAC_TOOL_PKTADDMSRAC_EV
+ NGMAC_TOOL_PKTCCN_EV ¡¢NGMAC_TOOL_PKTSISTA_EV
+ 2)Ôö¼ÓNGRLCʼþºÅ:
+ TOOL_NGRLC_ULTBF_EST_CFG_EV ¡¢TOOL_NRLC_PUAN_REQ_EV
+ TOOL_NGRLC_DLTBF_CFG_EV ¡¢NGRLC_TOOL_DLTBF_HALF_IND_EV
+ NGRLC_TOOL_DLTBF_FINAL_IND_EV ¡¢NGRLC_TOOL_ULTBF_HALF_IND_EV
+ NGRLC_TOOL_ULTBF_FINAL_IND_EV ¡¢TOOL_NGRLC_ULTBF_REL_EV
+ NGRLC_TOOL_ULTBF_FAI_IND_EV
+ 3)À©Õ¹ÁËNGMACʼþ·¶Î§£º50-¡·100
+ 18 2008.07.02 ½¯Õ×´º 1)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄǰ׺°´AP-MMIAʼþºÅǰ׺
+ 2)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄ·¶Î§ÓÉÔÀ´µÄMMIA-NASÒƵ½AP-MMIA
+ 19 2008.07.03 ½ºè 1)Ôö¼ÓÉèÖÃNUMAC¡¢NURLCÓ¦´ð¿ØÖÆÏûÏ¢:
+ TEST_URLCACKCTRL_UTRAN_EV¡¢TEST_UMACACKCTRL_UTRAN_EV
+ 20 2008.07.19 ½ºè 1)Ôö¼ÓTOOL_L1SIMU_SYSINFOFAIL_CFG_EV¡¢
+ GMAC_GET_BLOCKS_EV¡¢GMAC_ACK_BLOCKS_EV¡¢TOOL_NGMAC_PKTPGREQ_REQ_EV
+ 2)ÐÞ¸ÄNGRLCʼþºÅ¶¨Òå
+ 21 2008.07.22 ½ºè 1)Ôö¼ÓGSMÄ£ÄâʼþºÅ·¶Î§ºê¶¨Ò壺EVENT_PS_GSM_SIMU_BEGIN/EVENT_PS_GSM_SIMU_END
+ 22 2008.07.25 ÅËÀÚ 1)Ôö¼ÓÓëTCÏà¹ØʼþºÅ¶¨Òå
+ 23 2008.08.13 ½ºè 1)Ôö¼ÓÁËUMCR-GPHYÖ®¼äµÄʼþºÅ·¶Î§¶¨Òå
+ 2)½«UMCRÓëGSM²âÁ¿Ïà¹ØʼþºÅ¶¨ÒåÒÆÈëUMCR-GPHY·¶Î§ÄÚ
+ 3)Ôö¼ÓÁËURRAÄ£¿éµÄ¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 24 2008.08.14 ÕÅÅô³Ì 1)Ôö¼ÓÁËURRC-GRR¼äURRCGRR_HOINFOCNF_EV¡¢URRCGRR_HOINFOIND_EV
+ 2)Ôö¼ÓÁ˺¯ÊýÐÅÁî¸ú×ÙʼþºÅ·¶Î§ºÍURRCÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+ 25 2008.08.15 ÌÀÔ±¦ 1)Ôö¼ÓURRCINTRA_RADIOLINKFAIL_IND_EVÏûÏ¢
+ 26 2008.08.18 ÍõÀò 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_RXLEVREQ_CFG_EV
+ L1SIMU_TOOL_SYNCREQ_CFG_EV
+ L1SIMU_TOOL_SYSREQ_CFG_EV
+ L1SIMU_TOOL_IDLEMODEREQ_CFG_EV
+ L1SIMU_TOOL_NCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_SCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_MEAS_REPORT_CFG_EV
+ L1SIMU_TOOL_DLTBFRELIND_EV
+ L1SIMU_TOOL_ULTBFRELIND_EV
+ 2)Ôö¼ÓNGMACʼþºÅ£ºTOOL_NGMAC_CTRLBLOCK_REQ_EV
+ ʯ×ÚÀ¤ 1)Ôö¼ÓURRAÓëTD PHYÖ®¼äʼþºÅ¶¨Òå
+ 2)Ôö¼ÓL1G-GSMAÖ®¼äʼþºÅ¶¨Òå
+ ×ÞÑÞ 1)Ôö¼ÓGMMAS_CCSYNCIND_GSM_EVʼþºÅ
+ ÕŽ¡ 1)Ôö¼ÓNLAPDMºÍTRSÖ®¼äÓÃÓÚ²»Í¬SAPI¼äÏûÏ¢·¢ËͺÍÒì³£²âÊÔµÄʼþºÅ¶¨Òå
+ NLAPDM_L2_DATA_IND_EV
+ NLAPDM_TOOL_SABM_IND_EV
+ TOOL_NLAPDM_UA_RSP_EV
+ NLAPDM_TOOL_SABM_COR_IND_EV
+ TOOL_NLAPDM_UA_COR_RSP_EV
+ TOOL_NLAPDM_EXCEPT_DATA_EV
+ NLAPDM_TOOL_I_IND_EV
+ ׿Խ 1)Ôö¼ÓURRC_FUNC_SUSPENDMEASREQ_EV
+ 27 2008.08.20 ʯ×ÚÀ¤ 1)Ôö¼ÓL1GÐÅÁî¸ú×ÙʼþºÅ¶¨Ò壺L1G_ST_....
+ 2)Ôö¼ÓURRA-GPHYʼþºÅ·¶Î§¶¨Òå
+ 28 2008.08.30 ½ª²¨ 1)ÓÉÓÚ´¦Àí¸ÕפÁôijСÇø1SÄÚ²»ÄܶԲâÁ¿¸üºÃµÄСÇø½øÐÐÖØÑ¡£¬Ôö¼ÓUCSR_TCAMP1S_EXPIRY_EV
+ Ç®¿¡ 2)Ôö¼ÓGSMÐÅÁî¸ú×ÙʼþºÅ¶¨Òå¡£
+ 29 2008.09.03 ½ºè 1)L1G_GSMA_EVENT_BASE/L1G_GSMA_EVENT_END ÐÞ¸ÄΪ£ºL1G_DM_EVENT_BASE/L1G_DM_EVENT_END
+ 2)L1GË«Ä£ÏûϢǰ׺¸ü¸ÄΪ£ºL1G_DM_
+ 3)Ôö¼ÓÁËL1G_DM_TDD_CELL_MEAS_REQ
+ 4)Ôö¼ÓÁËL1SIMU_TOOL_TAFIND_EV¡¢L1SIMU_TOOL_TAFREQ_EV
+ 30 2008.09.16 ÍõÀò 1)Ôö¼Ó3Gʱ,UMMÏòRBCÅäÖÃÑ°ºôµÄÇëÇóʼþºÅ£º
+ UMMAS_PAGEREQ_EV
+ 31 2008.09.19 ½ºè 1)SDLÈÎÎñºÍÆÕͨÈÎÎñ¼äÏûÏ¢¶¨ÒåͳһÔÚSIG_CODE.HÖУ¬ÏÂÁкêÃû±»ÒÆ×ߣº
+ L1G_DM_DEACT_UMTS_REQ¡¢L1G_DM_DEACT_GSM_CNF
+ L1G_DM_TDD_CELL_MEAS_REQ¡¢L1G_UTRAN_MEAS_PERIOD_IND
+ 2)ɾ³ýÁË£º
+ L1G_DM_EVENT_BASE¡¢L1G_DM_EVENT_END
+ P_GSM_INACT_TIME_REQ_EV¡¢P_ABORT_GSM_GAP_REQ_EV¡¢P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ 32 2008.09.22 ÍõС½ø 1)Ôö¼ÓAP_MMIA_SMSABORTMOREQ_EV¡¢MMIASMS_ABORTMOREQ_EV
+ 33 2008.10.10 ÍõÀò 1)Ôö¼ÓUMMAS_PWRONREQ_EV
+ 34 2008.10.15 Íõ¾´Ò¢ 1)Ôö¼ÓNGMACʼþºÅ:
+ NGMAC_TOOL_CCF_IND_EV
+ 35 2008.10.24 ʯ×ÚÀ¤ 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV¡¢
+ L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV
+ 36 2008.11.05 ½ºè 1)ÐÞ¸ÄËùÓÐZ_ǰ׺Ϊ
+ 37 2008.11.13 ÍõÀò 1)Ôö¼ÓGMM_TPOWEROFF_EXPIRY_EV:2G¹Ø»ú¼à¿ØÈ¥»îÁ÷³Ì¶¨Ê±Æ÷
+ 38 2008.11.17 ÑîÎÄÇ¿ 1)È¡ÏûÏûÏ¢NGRLC_START_TIMER_EV(²»ÔÙʹÓÃ)
+ 2)Ôö¼Ó ÏûÏ¢NGRLC_TOOL_DLTBF_FAI_IND_EV¡¢TOOL_NGRLC_BEGINTESTMODE_EV¡¢NGRLC_TOOL_PDANNOTIFY_EV
+ 39 2008.11.27 ¸ßÏè 1)Ôö¼ÓCUMAC_GETTVBOCMPIND_EV£¬ÒÔ֪ͨUMCRÄ£¿é²ÉÑùÍê³É£¬¿ÉÒÔ½øÐÐÏà¹ØÆÀ¹ÀºÍ±¨¸æ¡£
+ ΤÓñÕä 1)Ôö¼ÓP_GSM_MEAS_DONE_REQ_EV
+ 40 2008.11.28 ׿Խ 1)ɾ³ýÁËMAC²âÁ¿²¿·ÖÐÅÁî¸ú×ÙÏûÏ¢URRC_FUNC_SUSPENDMEASREQ_EV,URRC_FUNC_TVMEASREQ_EV,URRC_FUNC_QUAMEASREQ_EV,URRC_FUNC_UEINTERMEASREQ_EV,
+ URRC_FUNC_RESUMEMEASREQ_EV,URRC_FUNC_MACRPT_EV,URRC_FUNC_TVDISTRIBUTE_EV,URRC_FUNC_QUADISTRIBUTE_EV,URRC_FUNC_UEINTERDISTRIBUTE_EV
+ 41 2008.12.10 ½¯Õ×´º 1)Ôö¼ÓUMMAS_ABORTCNF_EV
+ 42 2008.12.29 ½ºè 1)Ϊ֧³Ö½Å±¾¿ØÖÆCSDÒµÎñ£¬Ôö¼ÓTEST_TAFDATAIND_UTRAN_EV
+ ¸ßÏè148725 1)ÐÞ¸ÄSM¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 2)Ôö¼ÓMMIASM_PDPAUTOACTIND_EV
+ 43 2008.12.31 ×ÞÑÞ 1)Ôö¼ÓÁËCC¶¨Ê±Æ÷ʼþºÅ £ºCC_TMMCONN_EXPIRY_EV ¼à¿ØMMÁ¬½ÓµÄ½¨Á¢
+ 44 2009.02.10 ÑîÔÊ 1)Ôö¼ÓÁËMMÄ£¿é¶¨Ê±Æ÷ÏûÏ¢£ºMM_T3231_EXPIRY_EV¡¢MM_T3232_EXPIRY_EV
+ 45 2009.02.12 ½ºè 1)TAFÓëL1GÏûÏ¢¶¨ÒåÒÆÈëSIG_CODE.H£¬É¾³ýTAF_L1GÏûÏ¢·¶Î§
+ 2)Ôö¼ÓTAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢£ºTAF_FUNC_L1GDATAREQ_EV
+ 46 2009.02.16 ÍõС½ø 1)UMMÐÂÔöATÃüÁIMSI¼¤»îÈ¥»îÇëÇ󡢶ÔÁ½¸öÓòͬʱ½øÐÐÈ¥»îµÄÇëÇó¡¢ÉèÖÃGPRS×Ô¶¯¸½×ÅÇëÇó£¬
+ Ôö¼ÓÏûÏ¢¶¨Ò壺AP_MMIA_ZATTSETREQ_EV¡¢AP_MMIA_ZATTQUERYREQ_EV¡¢
+ AP_MMIA_ZGAATSETREQ_EV¡¢AP_MMIA_ZGAATQUERYREQ_EV¡¢
+ AP_MMIA_ZATTQUERYCNF_EV¡¢AP_MMIA_ZGAATQUERYCNF_EV
+ 47 2009.02.19 Ëﳤ½ 1)MM/GMM/CC£RRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºGMMAS_CSRABRELIND_EV;
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_ABORTCFGREQ_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_ACTTIMENOTIFY_REQ_EV£»
+ 48 2009.02.21 ×ÞÑÞ 1)Ö§³ÖMODIFY¹ý³Ì£¬Ôö¼ÓCCÓëTAFʼþºÅ¶¨Ò壺
+ CCTAF_PEND_REQ_EV¡¢CCTAF_RESUME_REQ_EV¡¢CCTAF_MODIFYBC_REQ_EV¡¢CCTAF_MODIFYBC_CNF_EV
+ 2)Ôö¼ÓCC¶¨Ê±Æ÷ʼþºÅ¶¨Ò壺
+ CC_TRELTAF_EXPIRY_EV
+ CC_TCONNTAF_EXPIRY_EV
+ CC_TSYNCIND_EXPIRY_EV
+ CC_TMODIFYBC_EXPIRY_EV
+ 49 2009.02.24 ½»¶ 1)Ϊ֧³ÖUSAT¹¦ÄÜ£¬Ôö¼ÓMMIAÓëATI/UICCÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_USAT_ENVELOPREQ_EV
+ AP_MMIA_USAT_ENVELOPCNF_EV
+ AP_MMIA_USAT_TERMNLRSPREQ_EV
+ AP_MMIA_USAT_TERMNLPROFREQ_EV
+ AP_MMIA_USAT_PROCMDIND_EV
+ AP_UICC_USAT_ENVELOPREQ_EV
+ AP_UICC_USAT_ENVELOPCNF_EV
+ AP_UICC_USAT_TERMNLRSPREQ_EV
+ AP_UICC_USAT_TERMNLPROFREQ_EV
+ AP_UICC_USAT_COMMONCNF_EV
+ AP_UICC_USAT_PROVCMDIND_EV
+ 50 2009.03.05 ÍõС½ø 1)UICCNOCARDIND²»ÔÙÉϱ¨¸øATI£¬ËùÒÔɾ³ýAP_MMIA_UICCNOCARDIND_EV
+ 51 2009.03.10 ½ºè Ôö¼ÓÖ§³ÖCBS¹¦ÄÜ
+ 1)Ôö¼ÓMMIA-ATI¡¢MMIA-CBSÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_CBS_CSCBSETREQ_EV
+ AP_MMIA_CBS_CSCBREADREQ_EV
+ AP_MMIA_CBS_SAVINGSETREQ_EV
+ AP_MMIA_CBS_RESTORESETREQ_EV
+ AP_MMIA_CBS_CSCBREADCNF_EV
+ AP_MMIA_CBS_TCBMIND_EV
+ AP_MMIA_CBS_PCBMIND_EV
+ AP_MMIA_CBS_TCBMLISTCNF_EV
+ AP_MMIA_CBS_PCBMLISTCNF_EV
+ AP_MMIA_CBS_TCBMREADCNF_EV
+ AP_MMIA_CBS_PCBMREADCNF_EV
+ MMIACBS_ACTIVATEREQ_EV
+ MMIACBS_ACTIVATECNF_EV
+ MMIACBS_DATAIND_EV
+ 2)CBSÏà¹ØATÃüÁî¶ÔÓ¦ÏûÏ¢´ÓAP-MMIA SMS²¿·Ö¶¨ÒåÖÐɾ³ý£º
+ AP_MMIA_SMSCSCBREQ_EV
+ AP_MMIA_SMSCSASREQ_EV
+ AP_MMIA_SMSCRESREQ_EV
+ AP_MMIA_SMSTCBMIND_EV
+ AP_MMIA_SMSTCBMREADCNF_EV
+ AP_MMIA_SMSCSCBCNF_EV
+ AP_MMIA_SMSCSASCNF_EV
+ AP_MMIA_SMSCRESCNF_EV
+ AP_MMIA_SMSTCBMLISTCNF_EV
+ 3)CBSÓëURBCµÄÖ®¼äµÄʼþºÅ¶¨Òå:
+ CBSAS_NODRXREQ_EV
+ CBSAS_DRXRSVREQ_EV
+ CBSAS_STOPREQ_EV
+ CBSAS_PCHCELLINFOIND_EV
+ 4)CBSÓëUMMÖ®¼äµÄʼþºÅ¶¨ÒåµÄ¶¨Òå:
+ UMMCBS_STARTREQ_EV
+ UMMCBS_STOPREQ_EV
+ UMMCBS_CELLINFOIND_EV
+ 5)CBS¶¨Ê±Æ÷ÏûϢʼþºÅµÄ¶¨Òå:
+ CBS_TSCHEDCHECK_EXPIRY_EV
+ 6)Ôö¼ÓURBCÓëURLCÖ®¼ä½Ó¿Ú¶¨Ò壺
+ CURLC_CBSRBCONFIGREQ_EV
+ 7)Ôö¼ÓURBCÓëPHYÖ®¼ä½Ó¿Ú¶¨Ò壺
+ P_CBS_NODRX_REQ_EV
+ P_CBS_DRX_REQ_EV
+ P_ADD_MODIFY_CBS_REQ_EV
+ P_STOP_CBS_REQ_EV
+ 52 2009.03.20 ÍõС½ø 1)Ôö¼ÓÖ§³ÖATÃüÁ+ZUSTAT,+ZURDY,+ZUSLOT,+ZPINSTAT
+ AP_MMIA_UICCCOMMANDREQ_EV
+ AP_MMIA_UICCCOMMANDQUERYCNF_EV
+ 53 2009.03.23 ÍõС½ø 1)Ôö¼ÓÏûÏ¢£º
+ AP_MMIA_USAT_LOCINFOCNF_EV
+ AP_MMIA_USAT_LOCINFOREQ_EV
+ 54 2009.03.31 ½»¶ 1)Ôö¼ÓÖ§³Ö¹¤³Ìģʽ£º
+ AP_MMIA_EM_CELLINFOREQ_EV
+ AP_MMIA_EM_CELLINFOQUERYREQ_EV
+ AP_MMIA_EM_LOCKCELLREQ_EV
+ AP_MMIA_EM_HOINFOREQ_EV
+ AP_MMIA_EM_HOINFOQUERYREQ_EV
+ AP_MMIA_EM_CELLINFOIND_EV
+ AP_MMIA_EM_CELLINFOQUERYCNF_EV
+ AP_MMIA_EM_HOINFOIND_EV
+ AP_MMIA_EM_HOINFOQUERYCNF_EV
+ MMIAUMM_EM_LOCKCELLREQ_EV
+ MMIAUMM_EM_LOCKCELLCNF_EV
+ MMIAAS_EM_CELLINFOREQ_EV
+ MMIAAS_EM_HOINFO_REQ
+ MMIAAS_EM_UCELLINFOIND_EV
+ MMIAAS_EM_UHOINFOIND_EV
+ UMMAS_LOCKCELLREQ_EV
+ UMMAS_UNLOCKCELLREQ_EV
+ UMMAS_LOCKCELLCNF_EV
+ MMIA_EM_HOINFO_EXPIRY_EV
+ UMCR_EM_CELLINFO_EXPIRY_EV
+ 55 2009.04.02 ΤÓñÕä 1)ÐÞ¸ÄÐźÅÇ¿¶ÈÉϱ¨·½Ê½£¬Ôö¼Ó£º
+ AP_MMIA_RXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVQUERYREQ_EV
+ AP_MMIA_RXLEVCNF_EV
+ AP_MMIA_ZRPTRXLEVIND_EV
+ AP_MMIA_ZRPTRXLEVQUERYCNF_EV
+ MMIAAS_RPTRXLEV_REQ_EV
+ MMIAAS_QUERYRXLEV_REQ_EV
+ MMIAAS_RPTRXLEV_IND_EV
+ MMIAAS_QUERYRXLEV_IND_EV
+ ɾ³ý:
+ MMIAMCR_RPTPRDREQ_EV
+ MMIAMCR_RSSIIND_EV
+ AP_MMIA_CSQEXEREQ_EV
+ AP_MMIA_ZSQSETREQ_EV
+ AP_MMIA_ZSQQUERYREQ_EV
+ AP_MMIA_ZSQIND_EV
+ AP_MMIA_CSQEXECNF_EV
+ AP_MMIA_ZSQQUERYCNF_EV
+ 56 2009.04.13 ½ºè 1)ΪÔö¼ÓL1GÓëPHYÖ®¼ä˫ģʼþºÅ¶¨Ò壺
+ P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ P_GSM_INACT_TIME_REQ_EV
+ P_ABORT_GSM_GAP_REQ_EV
+ 2)ºô½ÐÐÅÏ¢Éϱ¨£º
+ AP_MMIA_CCPROCINFOIND_EV
+ MMIACC_PROCINFOIND_EV
+ 3)Ϊ±ÜÃⲻͬ½á¹¹¶ÔӦͬÃûÏûÏ¢£¬Ôö¼Ó£º
+ TEST_UURLCDATAIND_UTRAN_EV
+ TEST_UURLCCONFIGREQ_UTRAN_EV
+ 57 2009.05.08 ½ª²¨ 1)Ôö¼ÓUMCRͬUCSRÖ®¼ä֪ͨÁÚÇø¸ü¸ÄµÄURRCÄÚ²¿Ê¼þºÅ:
+ URRCINTRA_NEIBCELLCHGIND_EV
+ 58 2009.05.11 ½ª²¨ 1)ɾ³ýUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CAMPONCELLREQ_EV
+ URRCGRR_CAMPONCELLCNF_EV
+ URRCGRR_CAMPONCELLIND_EV
+ URRCGRR_CAMPONCELLRSP_EV
+ 2)Ôö¼ÓUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CELLRESELREQ_EV
+ URRCGRR_ANYCELLRESELREQ_EV
+ URRCGRR_CELLRESELIND_EV
+ URRCGRR_CELLRESELREJ_EV
+
+ 59 2009.05.19 ½¯Õ×´º 1)Ôö¼ÓUMMͬGSMAÖ®¼äµÄʼþºÅ
+ UMMAS_GSMSRVNOTIFYREQ_EV
+ 60 2009.05.20 Ëﳤ½ 1)URLC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCURLC_CONFIGCNF_EV£»
+ ɾ³ýÏûÏ¢ºÅCURLC_STOPREQ_EV£»
+ 2)URRC/CC£SCIÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCSCI_CONFIGCNF_EV£»
+ 3)PDCP£URRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCPDCP_CONFIGCNF_EV£»
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_FACHCFGREQ_EV£»
+ URRCINTRA_FACHCFGIND_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_CONTINUEREQ_EV£»
+
+ 61 2009.5.22 ËïÒÔÀ× 1)Ôö¼ÓGSMA¶¨Ê±Æ÷µÄʼþºÅ¶¨Òå
+ GSMA_PROCTIMER_EXPIRY_EV
+ GSMA_INACTTIMER_EXPIRY_EV
+
+ 62 2009.06.04 ʷѧºì 1)PDCP£URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£º
+ CPDCP_RELOCREJ_EV
+ CPDCP_RELOCCOMPIND_EV
+ CPDCP_RELOCFAILIND_EV
+ CPDCP_DLPDUSIZECHANGEREQ_EV
+ CPDCP_DLPDUSIZECHANGECNF_EV
+ CPDCP_ROHCTARGETMODEREQ_EV
+ 2)PDCP£URRC ÏûÏ¢ºÅ¶¨Òåɾ³ý£º
+ CPDCP_RELOCCOMPREQ_EV
+
+ 63 2009.06.22 ΤÓñÕä 1)ÐÂÔöMACUL->MACDLÏûÏ¢£º
+ CUMAC_NOTIFYDLPERIODREPORTREQ_EV
+ 2)ɾ³ýÒÔÏÂÏûÏ¢£º
+ CUMAC_MEASRELREQ_EV
+ CUMAC_MEASREPORTIND_EV
+ CUMAC_PERIODMEASDELNOTIFYREQ_EV
+ CUMAC_GETTVBOCMPIND_EV
+ 3)ÐÂÔöRRCÓëUMAC½Ó¿ÚÏûÏ¢£º
+ CUMAC_TRAFFICMEASREQ_EV
+ CUMAC_QUANLITYMEASREQ_EV
+ CUMAC_INTERNALMEASREQ_EV
+ CUMAC_TVMEASRELREQ_EV
+ CUMAC_QMEASRELREQ_EV
+ CUMAC_UEMEASRELREQ_EV
+ CUMAC_TVMEASRESUMEREQ_EV
+ CUMAC_TVMEASSUSPENDREQ_EV
+ CUMAC_DLMEASSUSPENDREQ_EV
+ CUMAC_DLMEASRESUMEREQ_EV
+ CUMAC_ADDTVMEASREPORTREQ_EV
+ CUMAC_ADDQMEASREPORTREQ_EV
+ CUMAC_ADDUEMEASREPORTREQ_EV
+
+65 2009.06.23 ÑîÔÊ 1)Ôö¼ÓGMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ GMM_TWSPN_EXPIRY_EV
+ GMM_TWCRS_EXPIRY_EV
+ GMM_TWTRG_EXPIRY_EV
+
+66 2009.06.24 ½ºè 1)ÐÞ¸ÄTEST_GVAR_XXXΪGVAR_XXX
+ 2)ÖØÐÂÕûÀíÁ˲âÊÔÏûϢʼþ¶¨Ò巶Χ
+ 3)Ôö¼ÓÁËNCBSÏà¹ØÏûÏ¢¶¨Ò壺£¨½ªéª£©
+ TEST_UCBSSCHEDCFG_UTRAN_EV
+ TEST_UCBSDATAREQ_UTRAN_EV
+ TEST_UCBSOUTPUTEND_UTRAN_EV
+ TEST_UCBSUMAC_TFSCFG_UTRAN_EV
+ TEST_UCBSUMAC_SFNINFO_UTRAN_EV
+ TEST_UURLCDATACNF_UTRAN_EV
+ TOOL_L1SIMU_CBSBLK_START_EV
+ TOOL_L1SIMU_CBSFSTBLK_REQ_EV
+ TOOL_L1SIMU_CBSOTHERBLK_REQ_EV
+
+67 2009.06.29 QIANJUN155488 1)Ôö¼ÓÓû§ÃæÐÅÁî¸ú×ÙαÏûÏ¢¶¨Òå
+ ATIPDI_DATAREQ_TRACE_EV
+ UPDI_DATAREQ_TRACE_EV
+ SN_DATA_REQ_TRACE
+ SN_UNITDATA_REQ_TRACE
+ LL_DATA_REQ_TRACE
+ LL_UNITDATA_REQ_TRACE
+ LLC_GET_NEXT_PDU_TRACE_EV
+ GMAC_GET_BLOCKS_TRACE_EV
+ GMAC_ACK_BLOCKS_TRACE_EV
+ PDCP_UPDATA_TRACE_EV
+ URLC_GETBO_TRACE_EV
+ URLC_SENDPDU_TRACE_EV
+ UMAC_TFCSEL_TRACE_EV
+ PH_MAC_DATA_IND_TRACE
+ PH_RLC_DATA_IND_TRACE
+ MAC_RLC_DATA_IND_TRACE
+ RLC_DATA_IND_TRACE
+ RLC_UNITDATA_IND_TRACE
+ LL_DATA_IND_TRACE
+ LL_UNITDATA_IND_TRACE
+ SN_DATA_IND_TRACE
+ SN_UNITDATA_IND_TRACE
+ UPDI_DATAIND_TRACE_EV
+ ATIPDI_DATAIND_TRACE_EV
+ UUMAC_DATAIND_TRACE_EV
+ PDCP_DOWNDATA_TRACE_EV
+ TAF_COUNTER_TRACE_EV
+ TAF_RLP_XID_ULFRAME_TRACE_EV
+ TAF_RLP_XID_DLFRAME_TRACE_EV
+ TAF_RLP_SABM_ULFRAME_TRACE_EV
+ TAF_RLP_SABM_DLFRAME_TRACE_EV
+ TAF_RLP_UA_ULFRAME_TRACE_EV
+ TAF_RLP_UA_DLFRAME_TRACE_EV
+ TAF_RLP_DISC_ULFRAME_TRACE_EV
+ TAF_RLP_DISC_DLFRAME_TRACE_EV
+ TAF_RLP_DM_ULFRAME_TRACE_EV
+ TAF_RLP_DM_DLFRAME_TRACE_EV
+ TAFL1G_DATA_IND_TRACE_EV
+ TAFL1G_DATA_REQ_TRACE_EV
+ TAF_FUNC_UURLCDATAIND_EV
+ TAF_FUNC_UURLCDATAREQ_EV
+68 2009.7.2 ½»¶ 1)Ϊ֧³ÖÖÐÒÆËæEÐÐATÃüÁÔö¼ÓÏÂÁÐÏûÏ¢£º
+ AP_UICC_PINENABLEQUERYREQ_EV
+ AP_UICC_PINENABLEQUERYCNF_EV
+ AP_UICC_PINSTATQUREYREQ_EV
+ AP_UICC_PINSTATQUREYCNF_EV
+ AP_UICC_CARDMODEREQ_EV
+ AP_UICC_CARDMODECNF_EV
+ AP_MMIA_SETPINAPPLREQ_EV
+ AP_MMIA_SETPINAPPLCNF_EV
+ AP_MMIA_PINAPPLREADREQ_EV
+ AP_MMIA_PINAPPLREADCNF_EV
+ AP_MMIA_CPINREQ_EV
+ AP_MMIA_CPINREADREQ_EV
+ AP_MMIA_CPINREADCNF_EV
+ AP_MMIA_CARDMODEREQ_EV
+ AP_MMIA_CARDMODECNF_EV
+ AP_MMIA_MODEREQ_EV
+ AP_MMIA_MODECNF_EV
+69 2009.7.15 ½ºè 1)Òƶ¯L1G_ST_EVENT·¶Î§µ½SIGTRACE_EVENT·¶Î§ÄÚ
+ 2)Ôö¼ÓGVAR_CBS_GETREQ_EV¡¢GVAR_CBS_GETCNF_EV
+70 2009.7.17 Áõµ¤ 1)Ôö¼ÓURRC-URLCµÄʼþºÅ:
+ CURLC_SETDATANOTIFYMODE_EV
+ CURLC_PCHULDATATRREQ_EV
+71 2009.7.21 ½»¶ 1)ɾ³ý£º
+ AP_MMIA_ZBDMDSETREQ_EV
+ AP_MMIA_ZBDMDQUERYREQ_EV
+ AP_MMIA_ZBDMDQUERYCNF_EV
+ 2)ÐÂÔö£º
+ AP_MMIA_ZACTSETREQ_EV
+ AP_MMIA_ZACTQUERYREQ_EV
+ AP_MMIA_ZACTQUERYCNF_EV
+ AP_MMIA_MODEQRYREQ_EV
+ AP_MMIA_MODEQRYCNF_EV
+ AP_MMIA_MODESETREQ_EV
+72 2009.7.23 ÍõÀò 1)Ôö¼Ó£¬UMCRÔÚ½øÈë·ÉÐÐģʽʱ£¬Í¨ÖªURRCA½øÈë¿ÕÏеÄÏûÏ¢£º
+ P_GSM_MEAS_TONULL_REQ_EV
+73 2009.7.28 ΤÓñÕä 1)Ö§³ÖÈý°æÐб꣬Ôö¼ÓURRCÄÚ²¿Ê¼þºÅURBC-UMCR: URRCINTRA_DRXCHGIND_EV
+ Ôö¼ÓUMCR-URRCAµÄʼþºÅ: P_GSM_MEAS_DRX_CHANGE_REQ_EV
+74 2009.7.28 ʷѧºì 1)Ôö¼ÓNPDCP_EVENT_BASE¡¢NPDCP_EVENT_END
+ 2)Ôö¼ÓNPDCPʼþºÅ£º
+ CPDCP_CONFIGREQ_UTRAN_EV
+ CPDCP_RELEASEREQ_UTRAN_EV
+ NPDCP_DATAREQ_UTRAN_EV
+ NPDCP_DATAIND_UTRAN_EV
+ TEST_NPDCP_DATAERRIND_UTRAN_EV
+ TEST_NPDCP_DATACNF_UTRAN_EV
+75 2009.8.11 ÍõÀò CC/SM/SS²¿·ÖÓëATIÓÅ»¯½Ó¿ÚÐÞ¸Ä
+ 1)Ôö¼ÓºÍÐÞ¸ÄCCÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ Ôö¼Ó£ºAP_MMIA_CCQUERYREQ_EV/AP_MMIA_RINGIND_EV/AP_MMIA_CRINGIND_EV/AP_MMIA_CCWAIND_EV
+ AP_MMIA_MOCALLSSNOTIFY_EV/AP_MMIA_MTCALLSSNOTIFY_EV/AP_MMIA_CCQUERYCNF_EV/AP_MMIA_CLIPIND_EV
+ AP_MMIA_CRIND_EV/AP_MMIA_CCSETREQ_EV/AP_MMIA_COLPIND_EV/MMIACC_CSTAQUERYREQ_EV
+ MMIACC_CSTASETREQ_EV/MMIACC_CSTAQUERYCNF_EV/AP_MMIA_MODTOMULTMEDIARSP_EV
+ AP_MMIA_MODTOMULTMEDIAIND_EV/MMIACC_MODTOMULTMEDIARSP_EV/MMIACC_MODTOMULTMEDIAIND_EV
+ ɾ³ý£ºAP_MMIA_CRLPSETREQ_EV/AP_MMIA_CRLPQUERYREQ_EV/AP_MMIA_CHSNSETREQ_EV/AP_MMIA_CHSNQUERYREQ_EV
+ AP_MMIA_ETBMSETREQ_EV/AP_MMIA_ETBMQUERYREQ_EV
+ AP_MMIA_CCSETREQ_EV/AP_MMIA_CCSETUPIND_EV/AP_MMIA_CCCOMMANDCNF_EV/AP_MMIA_SSNOTIFYIND_EV
+ AP_MMIA_CHSNQUERYCNF_EV/AP_MMIA_DSQUERYCNF_EV/AP_MMIA_ETBMQUERYCNF_EV/AP_MMIA_CRLPQUERYCNF_EV
+ AP_MMIA_CCCAUSEQUERYREQ_EV/AP_MMIA_CCCAUSEQUERYCNF_EV
+
+ 2)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£º AP_MMIA_SMQUERYREQ_EV¡¢AP_MMIA_SMHANDLEREQ_EV¡¢AP_MMIA_SMANSREQ_EV
+ AP_MMIA_SMPDPADDRREQ_EV¡¢AP_MMIA_SMNEGQOSREQ_EV¡¢AP_MMIA_SMMODEMMOREQ_EV¡¢
+ AP_MMIA_SMMODEMANSREQ_EV¡¢AP_MMIA_SMCAUSEREQ_EV¡¢AP_MMIA_SMCANCELREQ_EV¡¢
+ AP_MMIA_SMQUERYPDPINFOREQ_EV¡¢AP_MMIA_SMQUERYCNF_EV¡¢AP_MMIA_SMHANDLECNF_EV¡¢
+ AP_MMIA_SMANSCNF_EV¡¢AP_MMIA_SMPDPADDRCNF_EV¡¢AP_MMIA_SMNEGQOSCNF_EV¡¢
+ AP_MMIA_SMMODEMMOCNF_EV¡¢AP_MMIA_SMMODEMANSCNF_EV¡¢AP_MMIA_SMCAUSECNF_EV¡¢
+ AP_MMIA_SMMTDEACTIVATEIND_EV¡¢AP_MMIA_SML2PIND_EV¡¢AP_MMIA_SMQUERYPDPINFOCNF_EV
+ Ôö¼Ó£ºAP_MMIA_SMREADREQ_EV¡¢AP_MMIA_SMQUERYPDPSTATUSREQ_EV¡¢AP_MMIA_SMQUERYACTCIDREQ_EV¡¢
+ AP_MMIA_SMQUERYDEFCIDREQ_EV¡¢AP_MMIA_SMQUERYPDPADDRREQ_EV¡¢AP_MMIA_SMQUERYNEGQOSREQ_EV¡¢
+ AP_MMIA_SMQUERYNEGEQOSREQ_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV¡¢AP_MMIA_SMACTDEACTREQ_EV¡¢
+ AP_MMIA_SMMODREQ_EV¡¢AP_MMIA_SMMTACTANSREQ_EV¡¢AP_MMIA_SMIPPDPACTREQ_EV¡¢
+ AP_MMIA_SMOPENCHRSP_EV¡¢AP_MMIA_SMQUERYIDLECHRSP_EV¡¢AP_MMIA_SMGETPCORSP_EV¡¢
+ AP_MMIA_SMQUERYPDPSTATUSCNF_EV¡¢AP_MMIA_SMQUERYACTCIDCNF_EV¡¢AP_MMIA_SMQUERYDEFCIDCNF_EV¡¢
+ AP_MMIA_SMQUERYPDPADDRCNF_EV¡¢AP_MMIA_SMQUERYNEGQOSCNF_EV¡¢AP_MMIA_SMQUERYNEGEQOSCNF_EV¡¢
+ AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMACTDEACTCNF_EV¡¢AP_MMIA_SMMODCNF_EV¡¢
+ AP_MMIA_SMCGEVIND_EV¡¢AP_MMIA_SMIPPDPACTCNF_EV¡¢AP_MMIA_SMOPENCHIND_EV¡¢
+ AP_MMIA_SMCLOSECHIND_EV¡¢AP_MMIA_SMQUERYIDLECHIND_EV¡¢AP_MMIA_SMGETPCOIND_EV¡¢
+ AP_MMIA_SMCONNECTIND_EV¡¢AP_MMIA_SMNOCARRIERCNF_EV
+
+ 3)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£ºAP_MMIA_CAAPTESTREQ_EV/AP_MMIA_CFCSQUERYREQ_EV/AP_MMIA_CPPSEXEREQ_EV/AP_MMIA_CFCSTESTREQ_EV
+ AP_MMIA_CAAPQUERYREQ_EV/AP_MMIA_CPPSEXECNF_EV/AP_MMIA_CFCSQUERYCNF_EV/AP_MMIA_CFCSTESTCNF_EV
+ Ôö¼Ó£ºAP_MMIA_COLRQUERYREQ_EV/AP_MMIA_COLRQUERYCNF_EV
+ ÆÁ±ÎÔÝδʵÏÖ¹¦ÄܵÄʼþºÅ£ºAP_MMIA_CAEMLPPSETREQ_EV /AP_MMIA_CAEMLPPQUERYREQ_EV /AP_MMIA_CFCSSETREQ_EV
+ AP_MMIA_CAAPSETREQ_EV/AP_MMIA_CAEMLPPQUERYCNF_EV /AP_MMIA_CAAPQUERYCNF_EV
+ AP_MMIA_CAAPTESTCNF_EV
+
+ 4)Ôö¼ÓIMEI/IMSI²éѯºÍ֤ʵµÄÏûϢʼþºÅ AP_MMIAÖ®¼ä
+ AP_MMIA_QUERYIMSIREQ_EV/AP_MMIA_QUERYIMEIREQ_EV/AP_MMIA_QUERYIMSICNF_EV/AP_MMIA_QUERYIMEICNF_EV
+
+ 5)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯µÄʼþºÅ MMIASSÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ Ôö¼Ó:MMIASS_COLRREADREQ_EV/MMIASS_ABORTREQ_EV/MMIASS_COMMONCNF_EV/SS_WAIT_TIMER_EXPIRY_EV
+ MMIASS_CUSDMTIND_EV
+
+ ɾ³ý:MMIASS_CAEMLPPSETREQ_EV/MMIASS_CAEMLPPREADREQ_EV/MMIASS_CPWDSETCNF_EV/MMIASS_CCFCSETCNF_EV
+ MMIASS_CCWASETCNF_EV/MMIASS_CAEMLPPSETCNF_EV/MMIASS_CAEMLPPREADCNF_EV/MMIASS_FORWARDCHECK_IND_EV
+ SS_T5000_EXPIRY_EV/MMIASS_CUSDUNSCNF_EV
+
+ 6)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯µÄʼþºÅ MMIASMÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ ɾ³ý:
+ MMIASM_PDPSTATUSREQ_EV¡¢MMIASM_NEGQOSREQ_EV¡¢MMIASM_PDPADDRREQ_EV¡¢
+ MMIASM_CAUSEREQ_EV¡¢MMIASM_PDPACTREJ_EV¡¢MMIASM_QUERYPDPINFOREQ_EV¡¢
+ MMIASM_PDPDEACTIVATEIND_EV¡¢MMIASM_PDPSTATUSCNF_EV¡¢MMIASM_NEGQOSCNF_EV¡¢
+ MMIASM_PDPADDRCNF_EV¡¢MMIASM_CAUSECNF_EV¡¢MMIASM_QUERYPDPINFOCNF_EV
+ SM_ATHRELEASE_EXPIRY_EV¡¢AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV
+ Ôö¼Ó:
+ MMIASM_QUERYNEGQOSREQ_EV¡¢MMIASM_QUERYNEGEQOSREQ_EV¡¢MMIASM_QUERYACTCIDREQ_EV¡¢
+ MMIASM_QUERYPDPSTATUSREQ_EV¡¢MMIASM_QUERYPDPADDRREQ_EV¡¢MMIASM_QUERYPDPCAUSEREQ_EV¡¢
+ MMIASM_MTACTANSREQ_EV¡¢MMIASM_IPPDPACTREQ_EV¡¢MMIASM_OPENCHRSP_EV¡¢
+ MMIASM_QUERYIDLECHRSP_EV¡¢MMIASM_GETPCORSP_EV¡¢MMIASM_QUERYNEGQOSCNF_EV¡¢
+ MMIASM_QUERYNEGEQOSCNF_EV¡¢MMIASM_QUERYACTCIDCNF_EV¡¢MMIASM_QUERYPDPSTATUSCNF_EV¡¢
+ MMIASM_QUERYPDPADDRCNF_EV¡¢MMIASM_QUERYPDPCAUSECNF_EV¡¢MMIASM_CGEVIND_EV¡¢
+ MMIASM_IPPDPACTCNF_EV¡¢MMIASM_OPENCHIND_EV¡¢MMIASM_CLOSECHIND_EV¡¢
+ MMIASM_QUERYIDLECHIND_EV¡¢MMIASM_GETPCOIND_EV¡¢MMIASM_COMMONCNF_EV¡¢
+ MMIASM_CONNECTIND_EV¡¢MMIASM_NOCARRIERCNF_EV
+ SM_AUTOANSMTACT_EXPIRY_EV
+ 7)Ôö¼ÓAP_MMIA_CAUSEQUERYREQ_EV, AP_MMIA_CAUSEQUERYCNF_EV
+ ɾ³ýAP_MMIA_SMSABORTMOREQ_EV/AP_MMIA_ABORTSEARCHPLMNREQ_EV
+
+76 2009.9.10 ºÎ½¨Î° 1)Ôö¼ÓLTEÖÆʽÏÂÏà¹ØµÄʼþºÅ
+ ½»¶ 2)½«AP_MMIA_EVENT_UICC_ENDºêÖµÔö¼Ó1
+
+77 2009.9.16 ÓÈ±ó ½«SIG_CODE.HÖÐÔÀ´²¿·ÖSDLÏûÏ¢£¨ÕâЩÏûÏ¢µÄÔ´ºÍÄ¿Ç°Ä£¿é¶¼¸ÄΪÁËÆÕͨÈÎÎñ£©µÄ¶¨Ò壬¸ÄΪÆÕͨÈÎÎñÏûÏ¢µÄ¶¨Òå
+
+78 2009.9.27 ÍõС½ø ΪʵÏÖ´æ´¢¹ÜÀí¹¦ÄÜÔö¼ÓÈçÏÂÏûÏ¢:
+ AP_MMIA_SMSCPMSTESTREQ_EV,AP_MMIA_SMSZMENAREQ_EV,AP_MMIA_SMSCPMSTESTCNF_EV,
+ AP_MMIA_CPBSTESTREQ_EV,AP_MMIA_CPBRSETENDCNF_EV,AP_MMIA_CPBSTESTCNF_EV,
+ AP_MMIA_PBPREFMSGSTOREQ_EV,AP_MMIA_PBPREFMSGSTOTESTREQ_EV,AP_MMIA_PBTPMRUPDATEREQ_EV,
+ AP_MMIA_PBMEMCAPAREQ_EV,AP_MMIA_PBMTPARAIND_EV,AP_MMIA_PBEMERNUMLISTIND_EV,
+ AP_MMIA_PBSTOSETREQ_EV,AP_MMIA_PBSTOTESTREQ_EV,AP_MMIA_PBFINDINDEXENDCNF_EV,
+ AP_MMIA_PBPREFMSGSTOCNF_EV,AP_MMIA_PBPREFMSGSTOTESTCNF_EV,AP_MMIA_PBCOMMONCNF_EV ,
+ AP_MMIA_PBINITCMPLTIND_EV,AP_MMIA_ZPBICIND_EV,
+
+79 2009.9.28 ΤÓñÕä ±ÜÃâ3GÖ÷ģʽÏ£¬¸ø³öGAPºó£¬ÓÖ·¢ÆðËæ»ú½ÓÈë¹ý³Ì¶øµ¼ÖµÄÉäƵͬÇÀ¶øÔö¼ÓµÄÏûÏ¢:
+ CUMAC_URRCAMEASSUSPENDREQ_EV
+ CUMAC_URRCAMEASRESUMEREQ_EV
+ P_GSM_RACH_ACTIVE_CNF_EV
+80 2009.9.28 ½ª²¨ Ôö¼ÓUSIRÖÜÆÚÐÔ½ÓÊÕϵͳÐÅÏ¢µÄ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ:
+ USIR_TIMER_R_EXPIRY_EV
+
+81 2009.9.28 ³Â¹â»ª 1)AP-MMIA SMSÏûÏ¢ºÅ¶¨Ò壬Ôö¼Ó
+ AP_MMIA_CPMSTESTREQ_EV
+ AP_MMIA_CPMSTESTCNF_EV
+ AP_MMIA_SMSZPBICIND_EV
+82 2009.9.28 ½¯Õ×´º 1)Ôö¼ÓUMM/GSMA½Ó¿ÚÏûÏ¢UMMAS_TBFRELEASEIND_EV
+ 2)Ôö¼ÓUMM¶¨Ê±Æ÷ÏûÏ¢UMM_TLIST_EXPIRY_EV
+
+83 2009.9.28 ½»¶ 1¡¢Ôö¼Ó»ñÈ¡PSDEVÊý¾ÝʼþºÅ
+ GVAR_UICC_DEV_GETREQ_EV
+ GVAR_UICC_DEV_GETCNF_EV
+ 2¡¢Ôö¼Ó¹Ø¿¨È·ÈÏÏûÏ¢£ºAP_UICC_PWROFFCNF_EV
+ 3¡¢È¡Ïû¹Ø¿¨¶¨Ê±Æ÷ÏûÏ¢£ºUICC_TIMER_EXPIRY_EV
+84 2009.9.29 ½»¶ 1¡¢Ôö¼ÓPBʼþºÅ
+ AP_MMIA_PBSTOTESTCNF_EV
+85 2009.9.30 ʯ×ÚÀ¤ 1¡¢AP-MMIA¼äʼþºÅÒÑʹÓÃÁË510¸ö£¬ÐèÔö¼ÓAP_MMIA_EVENT_BASEµÄ¿Õ¼ä£¬´Ó500£>600
+
+86 2009.10.19 ÑîÔÊ 1¡¢ Ôö¼ÓMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺 MM_TWRRR_EXPIRY_EV
+87 2009.10.27 Ç®¿¡ 1)Ϊ֧³ÖEGPRS,Ôö¼Ó2GÍø²àÄ£ÄâʼþºÅNGMAC_NGRLC_EPDAN_IND_EV,
+ NGRLC_NGRLC_PUAN_REQ_EV,NGRLC_FILL_DATA_QUEUE_REQ_EV,L1SIMU_NGRLC_DATA_IND_EV
+88 2009.10.27 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+89 2009.11.09 ÑîÔÊ 1¡¢Ôö¼ÓÁËMMIAºÍUMMÖ®¼äÔö¼ÓSYSCONFIGÏà¹ØÏûÏ¢ºê¶¨Ò壺
+ MMIAUMM_SYSCONFIGREQ_EV¡¢MMIAUMM_COMMONCNF_EV£»
+ 2¡¢Ôö¼ÓÁËUMMºÍASÖ®¼äϵͳÅäÖÃÏûÏ¢ºê¶¨Ò壺
+ UMMAS_UPDATESYSCONFIGREQ_EV ¡£
+90 2009.11.12 ½ª²¨/Ëﳤ½ ×Óϵͳ·½°¸ÐÞ¸Ä
+ 1.USIR_TBCCHMOD_EXPIRY_EV,UCSR_TBARGSMCELL_EXPIRY_EV
+ 2.URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨ÒåÖÐÔö¼ÓÏûÏ¢ºÅ:
+ URRC_FUNC_RELSCCPCHSTOPMACREQ_EV
+ URRC_FUNC_RESUMEFACHCFGREQ_EV
+91 2009.11.17 ³Â¹â»ª
+ MMIA£SMSÏûÏ¢ºÅ¶¨ÒåÖÐÐÂÔö£ºMMIASMS_COMMONCNF_EV
+
+92 2009.11.17 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+93 2009.11.18 ÑîÎÄÇ¿ Ôö¼ÓEDGEÖ§³ÖµÄÏà¹ØʼþºÅ:
+ TOOL_NGRLC_MODE_CFG_REQ_EV£¬NGRLC_TOOL_UL_DATABLOCK_IND_EV £¬
+ TOOL_NGRLC_DUMMYBLOCK_REQ_EV £¬DOWNLINK_DUMMY_BLOCK_REQ_EV£¬
+ TOOL_NGRLC_DOWNLINKBLOCK_REQ_EV
+94 2009.12.14 ÑîÔÊ Ôö¼Ó¼à¿ØÑ°ºôµÄ¶¨Ê±Æ÷ÏûÏ¢ºÅ:(CQNJ00137720)
+ GMM_TPAGE_EXPIRY_EV, MM_TWPGR_EXPIRY_EV;
+
+95 2009.12.16 ÍõС½ø 1)Ôö¼ÓËæEÐÐÏà¹ØʼþºÅ:
+ MMIACC_CLOSEVOICECHNLIND_EV,MMIACC_OPENVOICECHNLIND_EV,AP_MMIA_PBSFINDINDEXCNF_EV
+ AP_MMIA_PBSFINDINDEXENDCNF_EV,AP_MMIA_PBSEDITCNF_EV,AP_MMIA_PBSCPBRTESTCNF_EV,
+ AP_MMIA_PBSCPBWTESTCNF_EV,AP_MMIA_PBCNUM_CNF,AP_MMIA_PBCLCKSTATUSCNF_EV
+ AP_MMIA_PBSFINDINDEXREQ_EV,AP_MMIA_PBSEDITREQ_EV,AP_MMIA_PBCNUM_REQ
+ AP_MMIA_PBCLCKSETREQ_EV,AP_MMIA_PBSCPBRTESTREQ_EV,AP_MMIA_PBSCPBWTESTREQ_EV
+ AP_MMIA_PBUICCOKIND_EV,AP_MMIA_SCPBRSETCNF_EV ,AP_MMIA_SCPBRSETENDCNF_EV
+ AP_MMIA_SCPBRTESTCNF_EV,AP_MMIA_SCPBWTESTCNF_EV ,AP_MMIA_CNUMCNF_EV
+ AP_MMIA_SCPBRSETREQ_EV ,AP_MMIA_SCPBRTESTREQ_EV,AP_MMIA_SCPBWTESTREQ_EV
+ AP_MMIA_SCPBWSETREQ_EV ,AP_MMIA_CNUMREQ_EV ,AP_UICC_CRSM_CNF_EV
+ AP_UICC_COMMONCNF_EV,
+ 2)ÐÞ¸ÄPB,UICCʼþºÅ·¶Î§Öµ:
+ AP_MMIA_PB_RSP_EVENT,AP_MMIA_EVENT_PB_END
+ AP_MMIA_EVENT_UICC_END,AP_UICC_EVENT_END
+
+96 2009.12.07 ³ÂÎÄ Ôö¼Ó¶ÁдIMEIµÄʼþºÅTEST_SET_NV_DATA_IMEI_EV
+ Ôö¼ÓCRSMÃüÁîʼþºÅAP_UICC_CRSM_REQ_EV
+ Ôö¼ÓUICCÄ£¿éµÄͨÓÃʼþºÅ AP_UICC_COMMONCNF_EV
+
+97 2010.01.05 ΤÓñÕä Ôö¼ÓURRCINTRA_GETSERVCELLINFO_EV,ÒÔ±ãÔÚMSGTRACEÖÐÏÔʾʵʱСÇøÐÅÏ¢
+
+98 2010.01.08 Ëïºóɽ Ôö¼ÓPDIµãµÆºÍÏúÁ¿Í³¼Æ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ PDI_SWITCHLEDTIMER_EXPIRY_EV£¬
+ PDI_WAITDNSACKTIMER_EXPIRY_EV£¬
+ PDI_WAITZSSACKTIMER_EXPIRY_EV£¬
+
+99 2010.01.09 ÍõС½ø 1)Ôö¼ÓÏúÁ¿Í³¼ÆÏà¹ØʼþºÅ:
+ AP_MMIA_SELL_STAT_SWITCHSETREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYREQ_EV,AP_MMIA_SELL_STAT_UDPINFOQUERYREQ_EV
+ AP_MMIA_SELL_STAT_TESTSENDREQ_EV,AP_MMIA_SELL_STAT_DOMAINSETREQ_EV,AP_MMIA_SELL_STAT_DOMAINQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_CRCSETREQ_EV,AP_MMIA_SELL_STAT_CRCQUERYREQ_EV,AP_MMIA_SELL_STAT_DEBUGSETREQ_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYREQ_EV,AP_MMIA_SELL_STAT_PORTSETREQ_EV,AP_MMIA_SELL_STAT_PORTQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_TRITYPEQUERYREQ_EV,AP_MMIA_SELL_STAT_DNSCNTQUERYREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_UDPINFOQUERYCNF_EV,AP_MMIA_SELL_STAT_DOMAINQUERYCNF_EV,AP_MMIA_SELL_STAT_CRCQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYCNF_EV,AP_MMIA_SELL_STAT_PORTQUERYCNF_EV,AP_MMIA_SELL_STAT_TRITYPEQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DNSCNTQUERYCNF_EV,MMIASM_CIDDEACTIND_EV,MMIAPDI_SELLSTAT_STARTSENDPACKETIND_EV,
+ MMIAPDI_SELLSTAT_ABORTIND_EV,MMIA_SELLSTAT_ONEPDP_EXPIRY_EV,MMIA_SELLSTAT_SUMPDP_EXPIRY_EV,
+ MMIA_SELLSTAT_REG_EXPIRY_EV
+ ÐÞ¸ÄAP_MMIA_UICC_RSP_EVENT£¬AP_MMIA_EM_RSP_EVENT
+ 2) Ôö¼ÓZIMGE,ZGIIDFʼþºÅ
+ AP_MMIA_ZIMGREQ_EV,AP_MMIA_ZGIIDFREQ_EV,AP_MMIA_ZIMGCNF_EV,AP_MMIA_ZGIIDFCNF_EV
+ 3)´æ´¢ÁоÙÏûÏ¢µÄ֪ͨÏûÏ¢
+ AP_MMIA_PBCPBRIND_EV,AP_MMIA_PBCPBFIND_EV,AP_MMIA_PBSCPBRIND_EV,AP_MMIA_PBCMGLIND_EV
+
+100 2010.01.21 ʯ×ÚÀ¤ ½«UMCR-UPHY¸ÄΪUMACÉÏÏÂÐÐÁ½¶Î£¬Í¬Ê±½«ÏÂÁÐÏûÏ¢IDµÄ»ùµØÖ·¶¨Òå´ÓUMCR-UPHY¸ÄΪUMAC_DL-UPHY£º
+ P_QUALITY_MEAS_REQ_EV
+ P_UE_INTERNAL_MEAS_REQ_EV
+ P_QUALITY_MEAS_IND_EV
+ P_UE_INTERNAL_MEAS_IND_EV
+
+101 2010.02.05 ³ÂÎÄ Ôö¼ÓUICCʼþºÅ
+ UICC_CARDDETECT_EXPIRY_EV
+ AP_UICC_UICCUNSYNCIND_EV
+
+102 2010.02.20 ÕÅÅô³Ì Ôö¼ÓL1TʼþºÅ
+ P_ABORT_FREQ_SCAN_CNF_EV,P_ABORT_CELL_SEARCH_CNF_EV,P_BCH_RELEASE_CNF_EV,
+ P_CAMPON_A_CELL_CNF_EV,P_CHECK_RF_IND_EV£¨´¦ÀíÉäƵ³åÍ»£©,P_DPCH_CFG_FINAL_EV£¨¸ÃÏûÏ¢²»·¢µ½DPRAM£©,
+ P_DPCH_REL_CNF_EV,P_REL_SCCPCH_CNF_EV,P_STOP_PAGING_CNF_EV,P_STOP_CBS_CNF_EV
+ P_REL_HSDPA_CNF_EV,P_REL_HSUPA_CNF_EV,P_ACTIVE_IND_EV£¨´¦Àí¼¤»îʱ¼äµ½£©
+ P_RACH_PRCEDURE_CNF_EV,P_ERUCCH_PRCEDURE_CNF_EV
+
+103 2010.02.20 YANGYUN ÐÞ¸ÄÖÆʽ¼äÖØÑ¡£¬Ìí¼ÓʼþºÅ£º
+ UMMAS_CELLRESSTARTIND_EV
+
+104 2010.03.09 ʯ×ÚÀ¤ ÐÞ¸ÄL1TµÄÈýÌõÏûÏ¢ID£º
+ P_DPCH_CFG_FINAL_EV¸ÄΪP_L1_RESOURCE_CFG_FINAL_EV
+ P_RACH_PRCEDURE_CNF_EV¸ÄΪP_RACH_PROCEDURE_CNF_EV
+ P_ERUCCH_PRCEDURE_CNF_EV¸ÄΪP_ERUCCH_PROCEDURE_CNF_EV
+
+101 2010 .03.11 ׿Խ/ºÎ«Â‘ Ôö¼ÓÏûÏ¢£º
+ URRCINTRA_GETNCELLINFO_EV
+ MSGTRACEPS_CELLDISPLAYREQ_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+
+102 2010 .03.12 ËïȪ Ôö¼ÓÏûÏ¢£º
+ MMIASS_USSDCANCELREQ_EV
+
+103 2010 .03.17 ³Â¹â»ª Ôö¼ÓSMS¶¨Ê±Æ÷ʼþºÅ£º
+ SMS_TWSI_EXPIRY_EV
+
+104 2010.3.30 ×ÞÑÞ Ôö¼Ó2GÏÂTCHÊÍ·ÅʱGSMAÉϱ¨¸øCCµÄÏûÏ¢
+ GMMAS_CCTCHRELIND_GSM_EV
+
+105 2010 .04.04 ½ª²¨ ÐÞ¸ÄÁбí¹ý³Ìʱ³¤Ïà¹ØÐÞ¸Ä
+ ½«PS_UMMAS_ABORTPLMNREQ_EV ÐÞ¸ÄΪ UMMAS_STOPPLMNLISTREQ_EV
+ ½«UMMAS_ABORTCNF_EV ÐÞ¸ÄΪ UMMAS_ABORTHPPLMNCNF_EV
+ Ôö¼Ó³¬Ê±ÏûÏ¢: UMM_TPLMNLIST_EXPIRY_EV
+
+106 2010 .04.06 ½ª²¨ Ôö¼ÓURRCÄÚ²¿Ê¼þºÅ£º
+ URRCINTRA_SENDBUFESTREQ_EV
+ URRCINTRA_ABORTCCOREQ_EV
+
+107 2010 .04.13 ½ª²¨ Ð޸ı»BAR´¦ÀíÏà¹Ø£¬Ôö¼ÓÁ½¸öʼþºÅ
+ URRCINTRA_BARRESUMEIND_EV
+ UCSR_TBARFREQ_EXPIRY_EV
+
+108 2010 .04.23 ½»¶ ÐÞ¸ÄSUBMODE,Ôö¼ÓʼþºÅ
+ MMIAAS_SUBMODEIND_EV
+
+ 109 2010 .04.24 ËÕá° Ôö¼ÓUMAC-ULÏòUMAC-DL֪ͨÏÂÐÐÅäÖõı仯
+ CUMAC_ACTDLCFG_EV
+
+110 2010.04.29 ½¯Õ×´º Ôö¼ÓUMM¶ÔMMIAËÑÍøÇëÇóµÄ»Ø¸´£¬Ê¼þºÅ
+ MMIAUMM_SEARCHPLMNCNF_EV
+
+111 2010.04.30 ½¯Õ×´º ɾ³ý UMM_TPROC_EXPIRY_EV
+ Ôö¼Ó UMM_TUICCINIT_EXPIRY_EV
+ UMM_TCAMP_EXPIRY_EV
+ UMM_TDETACH_EXPIRY_EV
+
+ 112 2010 .05.04 ʯ×ÚÀ¤ Ôö¼ÓR7Ö§³Ö
+
+ 113 2010.05.14 Éòº® Ôö¼ÓGSMA֪ͨUCSR2GפÁô³É¹¦µÄָʾ
+ URRCGRR_GSMCAMPSUCCIND_EV
+
+ 114 2010.05.20 ʯ×ÚÀ¤ UICCÏûÏ¢ÒѾ³¬³öÔÓеÄÇø¼ä£¬Õ¼ÓÃÁËÆäËûÄ£¿éµÄÏûÏ¢Çø¼ä£¬µ÷ÕûUICCµÄÏûÏ¢Çø¼ä
+
+115 2010.05.22 ÑîÔÊ Ôö¼ÓCS¡¢PS¸½×Å״̬²éѯÏûÏ¢
+ MMIAUMM_CGATTQUERYREQ_EV
+ MMIAUMM_ZATTQUERYREQ_EV
+ MMIAUMM_CGATTQUERYCNF_EV
+ MMIAUMM_ZATTQUERYCNF_EV
+
+116 2010.05.25 ÑîÔÊ Ôö¼ÓUMM֪ͨGMMÖÆʽ¸ü¸Ä³É¹¦ÏûÏ¢
+ UMM_RATCHNIND_EV
+
+ 117 2010 .05.24 ÍõС½ø Ôö¼ÓAP_MMIA_ESMTFADTESTREQ_EV
+ AP_MMIA_ESMTFADTESTCNF_EV
+
+ 118 2010 .05.29 ³ÂÎÄ Ôö¼Ó£º
+ AP_UICC_ACTIVEORDEACTIVEFILEREQ_EV¡¢AP_UICC_ACTIVEORDEACTIVEFILECNF_EV
+
+119 2010.06.07 ʯ×ÚÀ¤ ÐÞ¸ÄÉϱ¨MSGTRACE·þÎñСÇøºÍÁÚÇøµÄ·½Ê½
+ Ôö¼Ó£ºMSGTRACEPS_SCELLINFOIND_EV£¨·þÎñСÇøÐÅÏ¢£©¡¢MSGTRACEPS_NCELLINFOIND_EV£¨ÁÚÇøÐÅÏ¢£©
+ ɾ³ýÔÓеÄÏûÏ¢£º
+ URRCINTRA_GETSERVCELLINFO_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+ URRCINTRA_GETNCELLINFO_EV
+
+120 2010.06.08 ÍõС½ø ΪUSATÃüÁîÔÚ90 00ʱÔö¼ÓÖ÷¶¯Éϱ¨ÏûÏ¢
+ AP_UICC_NOPROCNOTIFYIND_EV, AP_MMIA_USAT_NOPROCNOTIFYIND_EV
+
+121 2010.06.08 ʯ×ÚÀ¤ ½«RRAT_RXSTAT_IND¡¢RRMI_RXSTAT_IND¡¢RR_EM_HO_INFO_IND¡¢RR_EM_CELL_INFO_IND
+ ÒƵ½PSEVENT.HÖÐÈ¥
+121 2010.07.02 ÍõÀò£¨Ó¦¸ßÏè148604ÒªÇóÐ޸ģ© Ôö¼Ó
+ P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV¡¢
+
+122 2010.07.08 ʯ×ÚÀ¤ ½«P_RESEL_GSMCELL_START_REQ_EV¡¢P_RESEL_GSMCELL_START_CNF_EVÌ滻Ϊ
+ P_TD_RF_REL_REQ_EV¡¢P_TD_RF_REL_CNF_EV
+ ½«P_RESEL_GSMCELL_SUCC_REQ_EV¡¢P_RESEL_GSMCELL_SUCC_CNF_EVºÍ
+ P_TD_CLOSE_REQ_EV¡¢P_TD_CLOSE_IND_EVÌ滻Ϊ
+ P_TD_RESET_REQ_EV¡¢P_TD_RESET_CNF_EV
+ ÐÂÔöP_TD_RF_RESUME_REQ¡¢P_ABORT_GSM_GAP_CNF_EV
+
+123 2010.07.08 ¸ßÏè È¥³ýÏûÏ¢¶¨ÒåP_INTER_FREQ_BLIND_MEAS_IND_EV
+
+124 2010 .07.10 ¹Ë±¦³É Ôö¼Ó£º
+ SM_PDCP_HCMODIND_EV
+
+125 2010.07.10 ΤÓñÕä Ôö¼ÓRRCÄÚ²¿Ê¼þºÅ£ºURRCINTRA_CHANGECAMPONTYPE_EV CSR֪ͨ
+ MCR ÈÎÒâפÁôתºÏÊÊפÁô»òÕßÊǺÏÊÊתÈÎÒâ
+
+126 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ MMIAESM_ABORTREQ_EV
+
+127 2010.07.10 ÕÔÕñ»Ôɾ³ýÏûÏ¢MMIAESM_MTEPSBEARERACT_CNF_EV
+
+128 2010.07.10 ÍõС½øÔö¼Ó £º
+ AP_UICC_EFSTATUSQUERYREQ_EV, AP_UICC_EFSTATUSMODIFYREQ_EV
+ AP_UICC_EFSTATUSQUERYCNF_EV,AP_UICC_EFSTATUSMODIFYCNF_EV
+
+129 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ AP_MMIA_PBCHGINDEXIND_EV
+ AP_MMIA_CHGINDEXIND_EV
+
+130 2010.07.10 ÕÔÕñ»ÔΪ×Û²âÔö¼ÓÏûÏ¢AP_MMIA_AUTOSTARTREQ_EV
+
+131 2010.08.18 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢AP_MMIA_CGEQOSSETREQ_EV¡¢AP_MMIA_CGEQOSQUERYREQ_EV
+ AP_MMIA_CGEQOSQUERYCNF_EV¡¢AP_MMIA_CGEQOSRDPREQ_EV
+ AP_MMIA_CGEQOSRDPCNF_EV¡¢MMIAESM_QUERYPDPADDRCNF_EV
+ ɾ³ýÏûÏ¢MMIAESM_ABORTREQ_EV¡¢AP_MMIA_ESMQOSQUERYREQ_EVºÍAP_MMIA_ESMQOSQUERYCNF_EV
+ µ÷ÕûMMIAºÍATIÏûÏ¢Çø¼ä
+
+132 2010.08.26 ÑîÔÊ Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATELTEACT_EV¡¢MMIAUMM_SETLTEACT_REQ_EV
+
+133 2010.09.13 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_MMIA_ZEACTSETREQ_EV¡¢AP_MMIA_ZEACTREADREQ_EVºÍ
+ AP_MMIA_ZEACTREADCNF_EV
+
+134 2010.09.14 ³Â¹â»ª Ôö¼ÓÏûÏ¢GMMAS_SAPI3RELIND_EV
+
+135 2010.09.25 ÍõС½ø ½â¾ö֪ͨSTMËø¿¨ºÍ½âËø£¬Ôö¼ÓÏûÏ¢AP_UICC_CARDLOCKSTATUSIND_EV
+
+136 2010.09.27 ÀîÎľ² Ôö¼Ó¡¢µ÷ÕûLTEÏà¹ØÏûÏ¢
+
+137 2010.10.18 Ëﳤ½ È¥µôÏûÏ¢ºÅ£ºP_CBS_NODRX_REQ_EV¡¢ P_CBS_DRX_REQ_EVµÄ¶¨Ò壻
+ ºóÃæµÄÏûÏ¢µÄʼþºÅͬʱǰÒÆ£¬ÓУºP_ADD_MODIFY_CBS_REQ_EV¡¢P_STOP_CBS_REQ_EV¡¢P_L1_RESOURCE_CFG_FINAL_EV¡¢
+ P_ADD_HSUPA_REQ_EV¡¢P_REL_HSUPA_REQ_EV¡¢P_PLCCH_ADD_MODIFY_REQ_EV
+
+137 2010.10.28 ΤÓñÕä Ôö¼ÓÏûÏ¢UMCR_TBSIC_EXPIRY_EVÖ§³ÖTD϶ÔGSMСÇøͬ²½ÐÅÏ¢µÄÓÐЧÆÚά»¤
+138 2010.10.29 ÁõÒí Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATESCANUEBANDFG_EV¡¢UMMAS_SCANUEBANDIND_EV
+ ɾ³ýÏûÏ¢£ºUCSR_TFREQSCAN_EXPIRY_EV
+
+139 2010.11.05 YANGYUN Ôö¼ÓUMM_CELLNOCHANGEIND_EV
+
+140 2010.11.15 YANGYUN Ôö¼Ó CM_RRCRELIND_EVÏûÏ¢
+
+141 2010.11.29 ÀîÎľ² ÐÞ¸ÄESM_EPDCP_EVENT_BASEµÄºê¶¨Òå
+
+142 2010.11.30 ÍõС½ø ½â¾ö¿¨³õʼ»¯¹ý³ÌÖйػú»ØÏÔ´íÎóÎÊÌ⣬Ôö¼ÓÏûÏ¢ AP_UICC_PWROFFIND_EV
+ PSDEVÐ޸ķ½°¸£¬Ôö¼ÓÏûÏ¢ AP_UICC_WRITEITEMIND_EV,AP_UICC_UPDATEITEMREQ_EV,AP_UICC_UPDATEITEMCNF_EV
+
+143 2010.12.1 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢GVAR_ATMEM_DEV_GETREQ_EV¡¢GVAR_ATMEM_DEV_GETCNF_EV¡¢GVAR_NV_DEV_GETREQ_EV¡¢
+ GVAR_NV_DEV_GETCNF_EV
+
+144 2010.12.15 ʷѧºì ɾ³ýROHCµÄ¶¨Ê±Æ÷ÏûÏ¢ROHC_FO2IRTIMER_EXPIRY_EV¡¢ROHC_SO2IRTIMER_EXPIRY_EV£¬
+ Ôö¼ÓÒ»¸öÓÉSO¡¢FOµ½IRµÄ¶¨Ê±Æ÷ÏûÏ¢£ºROHC_IRTIMER_EXPIRY_EV
+
+145 2010.12.30 Ëﳤ½ µ¥¶ÀµÄСÇø¸üйý³Ì£¬ÊÕµ½Á½ÌõTI²»Í¬µÄCUCÏûÏ¢µÄ´¦Àí£¬Ðèɾ³ý£º
+ URRCINTRA_ABORTCFGREQ_EV
+
+146 2010.12.31 ׿±Ø²¨ CQNJ00240340 PSEVENT.HÖÐÓÐЩʼþºÅ¶¨ÒåËæ×Å°æ±¾µÄÑݽøÒѾ²»ÔÙʹÓÃ
+
+147 2010.12.31 ÍõС½ø ΪÔö¼Ó¿¨SEARCH¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢ AP_UICC_PREPERSONRECSEARCHREQ_EV,AP_UICC_PREPERSNRECSRCHCNF_EV
+
+148 2011.1.28 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢MMIASM_DISCONNECTREQ_EV¡¢AP_MMIA_DISCONNECTREQ_EV
+
+149 2011.1.30 ׿±Ø²¨ EC 614000686090 ½«MMIA£SMÏûÏ¢ºÅ¶¨Òå°´ÊÇ·ñ
+ ¶ÔÓ¦ATÃüÁî·ÖÀ࣬µ÷ÕûMMIASM_ABORTREQ_EVµÈ3ÌõÏûÏ¢µÄÈ¡Öµ
+150 2011.2.11 ÍõС½ø Ôö¼ÓÏûÏ¢AP_UICC_VERIFYPIN2REQ_EV£¬AP_UICC_VERIFYPIN2CNF_EV
+
+151 2011.01.25 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢
+ AP_MMIA_CAOCSETREQ_EV ¡¢AP_MMIA_CAOCQRYREQ_EV¡¢AP_MMIA_CACMQRYREQ_EV¡¢AP_MMIA_CAMMQRYREQ_EV
+ AP_MMIA_CPUCQRYREQ_EV¡¢AP_MMIA_CCWEQRYREQ_EV¡¢AP_MMIA_CACMSETREQ_EV¡¢AP_MMIA_CAMMSETREQ_EV
+ AP_MMIA_CPUCSETREQ_EV¡¢AP_MMIA_CCWESETREQ_EV¡¢AP_MMIA_CAOCSETCNF_EV¡¢AP_MMIA_CAOCQRYCNF_EV
+ AP_MMIA_CACMQRYCNF_EV¡¢AP_MMIA_CAMMQRYCNF_EV¡¢AP_MMIA_CPUCQRYCNF_EV¡¢AP_MMIA_CCWEQRYCNF_EV
+ AP_MMIA_CCCMIND_EV¡¢AP_MMIA_CCWVIND_EV¡¢MMIACC_CCMQUERYREQ_EV¡¢MMIACC_CCMQUERYCNF_EV
+ MMIACC_CCWVIND_EV¡¢MMIACC_NOTIFYAOCTIMERIND_EV
+
+152 2011.03.01 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_UICC_ZPUKREQ_EV¡¢AP_MMIA_ZPUKREQ_EV
+
+153 2011.3.2 ÍõС½ø Ôö¼Ó¼Æ·Ñ¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢AP_UICC_INCREASEACMFAILIND_EV£¬
+ AP_UICC_INCREASEREQ_EV£¬AP_UICC_RESETACMREQ_EV
+ ¼Æ·Ñ¹¦ÄÜYUZHIMING²¹³ä CC_TACMUPD_EXPIRY_EV ,CC_TCDUR_EXPIRY_EV
+
+154 2011.3.10 ZHANGCHONG ͬ²½LTEÐÞ¸Ä
+
+155 2011.3.16 ʯ×ÚÀ¤ ÃüÃûÐÞ¸Ä
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼ÓGSM PS HOÏûÏ¢id
+ 2£©Ôö¼Ó¶àÄ£Ïà¹ØÏûÏ¢idºÍASCÏà¹ØÏûÏ¢
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼Ó¿ìËÙ˯ÃßÏûÏ¢CPDCP_SCRI_IND_EV/CPDCP_ULDATA_TRANSFER_REQ_EV
+
+157 2011.04.02 ÕÔÕñ»Ô
+ 1) ΪR9Éý¼¶Ôö¼ÓÏûÏ¢
+
+158 2011.04.23 ÕÔÕñ»Ô
+ Õë¶ÔUICCÓÅ»¯£¬É¾³ýÎÞÓõÄÏûÏ¢AP_MMIA_UICC_INFO_REQ_EV ¡¢
+ AP_MMIA_UICC_INFO_CNF_EV¡¢AP_MMIA_PIN_STATE_IND_EV
+
+159 2011.05.03 ÕÔÕñ»ÔΪ3GÃûƬ¼ÐÔö¼ÓÏûÏ¢AP_MMIA_ZCPBQ_SET_REQ_EV¡¢AP_MMIA_ZCPBQ_QUERY_REQ_EV
+ AP_MMIA_ZEER_READ_REQ_EV¡¢AP_MMIA_ZCPBQ_SET_CNF_EV¡¢AP_MMIA_ZCPBQ_QUERY_CNF_EV
+ AP_MMIA_ZEER_READ_CNF_EV¡¢AP_MMIA_PB_READ_CAPA_REQ_EV¡¢AP_MMIA_PB_READ_SET_NUM_REQ_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_REQ_EV¡¢AP_MMIA_PB_READ_CAPA_CNF_EV¡¢AP_MMIA_PB_READ_SET_NUM_CNF_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_CNF_EV
+160 2011.05.31 ʷѧºì
+ Ôö¼ÓROHCv2¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¶Î,Ôö¼ÓROHCv2_T_IR_EXPIRY_EVÏûÏ¢ºÅ
+
+161 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼Ó´¦Àí+ZIMIµÄÏûÏ¢AP_MMIA_SET_IMSI_REQ_EV
+
+162 2011.06.16 ËÎÑÇÅô
+ Ôö¼ÓGMM¼à¿ØMSÖ÷¶¯ÇëÇóÊÍ·ÅÁ´½Ó¶¨Ê±Æ÷Z_GMM_Twrel³¬Ê±µÄÏûÏ¢GMM_T_WREL_EXPIRY_EV
+ EC614000821119£ºGMMÄ£¿éÊÍ·ÅRRCÁ¬½ÓÔö¼ÓÎÕÊÖ¹ý³Ì£¬Ôö¼Ó¶¨Ê±Æ÷Twrel¼à¿Ø´Ë¹ý³Ì£¬Í¬Ê±ÐèÒªÔö¼Ó¶¨Ê±Æ÷³¬Ê±ÏûÏ¢
+163 2011.06.20 ¹ù·å
+ EC614000815619£ºCM²ãÔÚUMM»»Íø¹ý³ÌÖÐÓÐÒµÎñÁ÷³Ì£¬²»¶ÏµÄ·¢ÆðCM_EST£»Í¨¹ý¶¨Ê±Æ÷À´¿ØÖÆÖØ·¢´ÎÊý
+
+ 164 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼ÓÏûÏ¢AP_MMIA_CS_SRV_IND_EV
+
+165 2011.06.30 Ëﳤ½Ôö¼ÓPA+Éý¼¶ÐÞ¸Ä
+ 1£©URBC_UPHY_RSP_EVENTÓëURBC_UPHY_EVENT_BASEÖ®¼äµÄÆ«ÒÆÓÉ20±äΪ30£»
+ 2£©Ôö¼ÓÏûÏ¢ºÅCSCI_UNRECOVER_ERR_EV£¬URRC_EFACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_REQ_EV£¬CUMAC_HSPA_EPCH_CFG_REQ_EV£¬
+ CUMAC_UPDATE_ERNTI_REQ_EV£¬CUMAC_FACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_CNF_EV£¬P_HSPA_PLUS_FACH_REQ_EV£¬P_HSPA_PLUS_PCH_REQ_EV
+ P_HSPA_PLUS_FACH_REL_REQ_EV£¬P_HSPA_PLUS_PCH_REL_REQ_EV£¬P_EFACH_UPDATE_RNTI_REQ_EV£¬P_CELL_RESEL_REQ_EV£¬P_CELL_RESEL_CNF_EV£¬P_SYNC_CMD_RESP_EV,
+ P_HSPA_PLUS_FACH_REL_CNF_EV,P_HSPA_PLUS_FACH_REL_CNF_EV
+ 3£©P_DL_DPCH_SETUP_MODIFY_CNF_EV¸ÄÃûΪP_DL_RL_SETUP_MODIFY_CNF_EV
+
+ 166 2011.7.1 ¹Ë±¦³ÉÔö¼ÓÄ£ÄâPSIÏûÏ¢SIMULPSI_CONFIG_EV
+
+ 167 2011.7.7 ÕÔÕñ»ÔÔö¼Ó¶ÔCSÑ°ºôµÄÓ¦´ðÏûÏ¢AP_MMIA_CS_SRV_RSP_EV
+ 168 2011.7.15 ÕÅÅô³ÌÔö¼ÓÖ§³ÖLTE±³¾°ËÑË÷¹¦ÄÜÐÂÔöµÄʼþºÅ
+ AP_MMIA_BGPLMNSEL_SETREQ_EV¡¢AP_MMIA_BGPLMNSEL_QUERYCNF_EV¡¢AP_MMIA_BGPLMNSEL_QUERYREQ_EV
+ MMIA_UMM_BGPLMNSEL_REQ_EV
+ UMM_ASC_TRY_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_CNF_EV¡¢UMM_ASC_TRY_BGPLMN_REJ_EV¡¢UMM_ASC_TRY_BGPLMN_CNF_EV
+ ASC_LTE_TRY_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_CNF_EV¡¢ASC_LTE_TRY_BGPLMN_REJ_EV¡¢ASC_LTE_TRY_BGPLMN_CNF_EV
+169 2011.7.18 Ëﳤ½ Õë¶Ô614000878724 ɾ³ýÈçÏÂÏûÏ¢ºÅ
+ AS_LTE_TD_CSHO_REQ_EV¡¢AS_LTE_TD_CSHO_CNF_EV¡¢AS_LTE_TD_CSHO_REJ_EV
+170 2011.7.28 ½ª²¨ Õë¶Ô614000920283 Ôö¼ÓÈçÏÂÏûÏ¢ºÅ
+ ASC_LTE_LOCK_CELL_REQ_EV¡¢ASC_LTE_UNLOCK_CELL_REQ_EV¡¢ASC_LTE_LOCK_CELL_CNF_EV
+171 2011.8.2 ÅËÀÚ Ôö¼ÓÏûÏ¢ºÅUURLC_PDCP_DATA_IND_EV
+172 2011.8.2 Ëﳤ½ ÏûÏ¢ºÅ¶¨ÒåÖظ´ÁË£¬ÐèҪɾ³ýÏûÏ¢ºÅCUMAC_RESEL_REQ_EV£¬CUMAC_RESEL_IND_EV
+173 2011.8.15 ³Â¹â»ªÔö¼ÓCBSÏûÏ¢ºÅCBS_ASC_CMAS_NOTIFY_IND_EV
+174 2011.8.17 ¿µÊé½ÜÔö¼ÓCSGÏûÏ¢ºÅEURRC_CSG_PROXIMITY_IND_EV
+175 2011.8.23 ¿µÊé½Üɾ³ýLTE_P_SWITCH_RF_REQ_EV,LTE_P_START_PAGING_REQ_EV,LTE_P_SWITCH_RF_CNF_EV
+ Ôö¼ÓLTE_P_SLEEP_TIME_IND_EV£¬LTE_P_WAKEUP_REQ_EV
+176 2011.8.23 ÕÔÕñ»ÔΪCMMB/×¼FR/Refresh/·þÎñÁбí/CCOͳ¼ÆÔö¼ÓÏûÏ¢AP_MMIA_MB_AUTH_REQ_EV¡¢
+ AP_MMIA_MB_CELL_ID_REQ_EV¡¢AP_MMIA_PSEUDO_FR_SET_REQ_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_REQ_EV¡¢
+ AP_MMIA_REFRESH_REQ_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_REQ_EV¡¢AP_MMIA_MB_AUTH_CNF_EV ¡¢
+ AP_MMIA_MB_CELL_ID_CNF_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_CNF_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_CNF_EV¡¢
+ MSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV
+177 2011.8.24 ΤÓñÕäÔö¼Ólte gap±¨¸æ¸øtrs
+178 2011.8.25 ÑîÔÊÔö¼ÓESM_EMM_EMERGENCY_PDN_ONLY_IND_EV,EMM_ESM_DETACH_NORMAL_IND_EV
+179 2011.8.25 ÑÔö¼ÓESM_UMM_LOCAL_DEACT_IND_EV
+180 2011.8.25 ׿±Ø²¨Ôö¼ÓCM_SM_DEACT_NON_EMERGENCY_EV
+181 2011.8.29 ½ª²¨Ôö¼ÓMSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV¡¢MSGTRACEPS_CELLRESORCCO_IND_EV¡¢MMIA_AS_EM_CELLRESORCCOCOUNT_REQ_EV¡¢
+ ASC_LTE_CMAS_NOTIFY_IND_EV¡¢EUSIR_T_ETWS_EXPIRY_EV¡¢EUSIR_T_CMAS_EXPIRY_EV
+ ÐÞ¸ÄEURRC_ETWS_INFO_EV Ϊ EURRC_WARNING_NOTIFY_INFO_EV
+182 2011.8.29 ÓȺ£Ó¢ refresh Ôö¼Ó AP_UICC_REFRESH_REQ_EV AP_UICC_DEACTEND_IND_EV AP_UICC_FILECHANGEEND_IND_EV AP_UICC_FILECHANGE_IND_EV
+183 2011.9.15 ½ª²¨Ôö¼ÓEURRC_SI_END_FOR_HO_EV
+184 2011.9.15 ÍõÖ¾Ôö¼ÓENBRRC_PROXIMITY_RPT_EV
+185 2011.9.16 Ðì¿¡Ôö¼ÓGRRº¯Êý½Ó¿Ú
+186 2011.9.16 Ëﳤ½ÉêÇëÔö¼ÓENBRRC_UE_INFO_REQ_EV¡¢ENBRRC_UE_INFO_RSP_EV
+187 2011.9.26 ð¿¡µ÷ÕûGRR¶¨Ê±Æ÷ÏûÏ¢ºÅ·¶Î§
+
+188 2011.10.12 lh ɾ³ýÁÚÇøÉϱ¨ºÍ·þÎñСÇøÉϱ¨ÏûÏ¢½Ó¿Ú£¬Ôö¼ÓLTEСÇøÐÅÏ¢Éϱ¨Ê¼þºÅ
+189 2011.10.18 ÕÔÕñ»ÔΪLTE±³¾°ËÑË÷Ôö¼ÓÏûÏ¢AP_MMIA_LTEBGPLMN_TESTREQ_EVºÍAP_MMIA_LTEBGPLMN_TESTCNF_EV
+
+190 2011.10.19 ºÎ«Â‘Ôö¼Ó¶¨Ê±Æ÷ʼþºÅT_DISABLE_UMTS_MEAS_EV,T_DISABLE_LTE_MEAS_EV
+191 2011.11.3 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SMSOVERIPNET_SETREQ_EV¡¢AP_MMIA_SMSOVERIPNET_QUERYREQ_EV
+ AP_MMIA_SMSOVERIPNET_QUERYCNF_EV¡¢MMIA_UMM_SMSOVERIPNET_SETREQ_EV
+ EC614001128873
+
+192 2011.11.4 ÕÔÕñ»ÔÔö¼ÓËæeÐа汾IccIdµÄÉϱ¨ºÍ»ú¿¨»¥ËøÐèÇó:
+ Ôö¼ÓÏûÏ¢ZPS_ApUicc_ToReadCardReq_Ev¡¢ZPS_ApMmia_Iccid_Ind_EV¡¢ZPS_ApMmia_USAT_ToReadCardReq_Ev
+
+193 2011.11.4 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SM_DEACT_IND_EV, EC614001103133
+194 2011.11.22 ÓȺ£Ó¢Ôö¼ÓTEST_SET_NV_DATA_SPCLFUNC_EV £¬EC 614001151291
+
+195 2011.12.2 ÁºÐ¡º®Ôö¼ÓÏûÏ¢AP_MMIA_CALL_LINE_SET_REQ_EV¡¢AP_MMIA_CALL_LINE_QRY_REQ_EVºÍAP_MMIA_CALL_LINE_QUERY_CNF_EV 614001181454
+ R9 U115¸£ÖÝ°æ±¾Ò»»úË«ºÅÐèÇó ºÏÈë
+
+196 2011.12.26 EC617001225651,MMIAÔö¼ÓUE InfoµÄÉϱ¨,ÕÔÕñ»ÔÔö¼ÓÏûÏ¢ROADTEST_UEINFO_REQ_EV¡¢ROADTEST_UEINFO_CNF_EV
+197 2011.12.27 ËÎÑÇÅôÐÂÔöPDCP(RABM)֪ͨGMM¹ØÓÚRABÐÅÏ¢
+
+198 2012.1.5 EC617001233064Ôö¼ÓÄ£ÄâPDI·¢Ë͸øGSMAµÄÏûÏ¢PDI_GSM_DATA_REQ_EV
+199 2012.1.11 ¹Ë±¦³ÉÐÂÔöÈýÌõÏûÏ¢ÓÃÓÚÓû§ÃæÌØÊâÐÅÁî¸ú×Ù
+200 2012.03.12 ΤÓñÕä Ôö¼ÓÏûÏ¢P_DETECT_CELL_INFO_IND_EV
+201 2012.03.27 ³ÂΰÐÂÔöLTE_P_DLSCH_DATA_TRACE_EVºÍLTE_P_ULSCH_DATA_TRACE_EVÓÃÓÚEPHYºÍEUMAC¼äµÄÉÏÏÂÐÐÊý¾ÝÐÅÁî¸ú×Ù
+
+202 2012.04.16 ºÎ«Â‘ÐÂÔöGRR_RRC_POWEROFF_IND_EVÏûÏ¢ÓÃÀ´Í¨ÖªGRRC(Èí)¹Ø»ú
+203 2012.05.08 Ëﳤ½ÐÂÔöASC_TD_LOSTCOV_CAMP_SUCC_IND_EVÏûÏ¢ÓÃÓÚÆäËüÖÆʽ¶ªÊ§¸²¸ÇÖØÑ¡µ½TD³É¹¦ºó£¬ASC֪ͨUCER±íʾ¿çÖÆʽÖØÑ¡³É¹¦¡£
+204 2012.05.10 ³ÂΰÐÂÔöLTE_P_MAC_SR_REQ_EVÓÃÓÚTMTÐÅÁî¸ú×ÙSRµÄ·¢ËÍ
+205 2012.05.10 Ëﳤ½ÐÂÔöP_UL_PHY_CH_CTRL_REQ_EvÏûÏ¢ÓÃÓÚ½øÐÐUl-DTXÅäÖÃ?
+206 2012.07.15 ÁºÐ¡º®ÐÂÔöMMIA_EUCSR_LTEINFO_REQ_EVµÈÏûÏ¢ÓÃÓÚatÃüÁîÉϱ¨×ÓÖ¡ÅäÖÃÐÅÏ¢
+207 2012.08.02 ÍõС½ø EC617001662142£¬ Ôö¼Ó
+ AP_UICC_CCHO_REQ_EV,AP_UICC_CCHC_REQ_EV,AP_UICC_CGLA_REQ_EV,AP_UICC_CRSM_REQ_EV,
+ AP_UICC_CCHO_CNF_EV,AP_UICC_CGLA_CNF_EV,AP_UICC_CRSM_CNF_EV,AP_UICC_USAT_FETCH_IND_EV,
+208 2012.11.06 W GROUPÐ޸ģºÐÞ¸Äpsenent end,ÔÚÔÀ´µÄ»ù´¡ÉÏÔö¼ÓÁË8000.W·ÇÎïÀí²ãÏûϢλÓÚLTEÏûÏ¢Ö®ºó£¬ÔÚ16384--end
+ WµÄÎïÀí²ãÏûÏ¢·ÅÔÚps+6500---ps+7000µÄµØ·½£¬¶ÔÓÚTW¹²ÓÃÏûÏ¢²ÉÓÃÐÞ¸ÄÃüÃûµÄ·½Ê½TD¸ÄΪUTRA
+209 2012.11.21 ÍõС½ø EC617001860117£¬ ÖÇÄÜ»úÈȲå°ÎÐèÇó£¬Ôö¼ÓÏûÏ¢
+ AP_UICC_MOVECARD_IND_EV AP_UICC_INSERTCARD_IND_EV
+210 2013.10.18 ΤÓñÕäÔö¼ÓATIÓëASµÄÏûÏ¢MMIA_AS_B39_INFO_IND_EV(EUMCR,UMCR->ATI)ºÍMMIA_AS_B39_INFO_REQ_EV(ATI->GRR)
+ *****************************************************************************/
+#ifndef Z_EVENTDEF_H
+#define Z_EVENTDEF_H
+
+#include "atipsevent.h"
+
+/*=====================================================================================================================
+ ÏûÏ¢Çø¼ä£º
+
+ ||______________________|__________UPHY__________|_____________________|_____________________||
+ PS_BASE UPHY_BASE(+6K) UPHY_BASE(+6.5K) PS_LTE_BASE(+10K) PS_END(PS_LTE_END)
+ =====================================================================================================================*/
+
+/*GSM SDLÏûϢʼþºÅ·¶Î§£¬¾ßÌåµÄGSMʼþºÅ¶¨ÒåÔÚSIG_CODE.HÖУ¬½öÔÚpstestÖÐʹÓÃ*/
+#define EVENT_PS_GSM_SDL_BASE (DWORD)0x00010000
+#define EVENT_PS_GSM_SDL_END (DWORD)0xff7d0003
+
+/*LTEʼþºÅ·¶Î§*/
+#define EVENT_PS_LTE_BASE (DWORD)(EVENT_PS_BASE + 10000)
+#define EVENT_PS_LTE_END (DWORD)(EVENT_PS_BASE + 16383)
+
+/*WCDMAʼþºÅ·¶Î§*/
+#define EVENT_PS_W_BASE (DWORD)(EVENT_PS_BASE + 16384)
+#define EVENT_PS_W_END (DWORD)EVENT_PS_END
+/**************************************************PHY msg base-end start********************************************************/
+/*Õⲿ·ÖID²»ÄÜËæÒâÐ޸ģ¬»áÓ°Ïì½Ó¿ÚÖеÄmsgidµÄÖµ£¬´Ó¶øʹÎïÀí²ãµ¼ÖÂÎóÅÐÏûÏ¢*/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define PS_UPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6000)
+/*ÐÒéÕ»ÓëWCDMAÎïÀí²ãÏûÏ¢·¶Î§.TDÓëWÎïÀí²ãÏûÏ¢·¶Î§¹Ì¶¨ÔÚ6000µ½7000.ÆäÖÐÇ°500ÓÃÓÚTD£¬ºó500ÓÃÓÚW*/
+#define PS_WPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6500)
+
+/*ÐÒéÕ»ÓëLTEÎïÀí²ãÏûÏ¢·¶Î§£¬±£Ö¤ÎïÀí²ãºÍÐÒéÕ»IDÆðʼֵµÍ8λȫÁ㣬±£Ö¤Ç¿ÖÆת»»ÎªBYTEΪÕý³£Öµ*/
+#define LTE_PS_EUPHY_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 2544)
+#define LTE_PS_EUPHY_RSP_EVENT (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 60)
+#define LTE_PS_EUPHY_EVENT_END (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 120)
+/**************************************************PHY msg base-end end********************************************************/
+
+/*UMM¡¢MM¡¢GMMÄÚ²¿ÏûÏ¢·¶Î§(50)*/
+#define UMM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2570)
+#define UMM_EVENT_END (DWORD)(UMM_EVENT_BASE + 49)
+
+/*SS/SMS/SM/CC/PDCPÓëMM/GMMµÄÏûÏ¢·¶Î§(50)*/
+#define CM_MM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2620)
+#define CM_MM_EVENT_END (DWORD)(CM_MM_EVENT_BASE + 49)
+
+/*UMMºÍASCµÄÏûÏ¢·¶Î§ (100)*/
+#define UMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2670)
+#define UMM_ASC_RSP_EVENT (DWORD)(UMM_ASC_EVENT_BASE + 50)
+#define UMM_ASC_EVENT_END (DWORD)(UMM_ASC_EVENT_BASE + 99)
+
+/*GMMºÍASCµÄÏûÏ¢·¶Î§(100) */
+#define GMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2770)
+#define GMM_ASC_RSP_EVENT (DWORD)(GMM_ASC_EVENT_BASE + 50)
+#define GMM_ASC_EVENT_END (DWORD)(GMM_ASC_EVENT_BASE + 99)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_UAS_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2870)
+#define ASC_UAS_RSP_EVENT (DWORD)(ASC_UAS_EVENT_BASE + 50)
+#define ASC_UAS_EVENT_END (DWORD)(ASC_UAS_EVENT_BASE + 99)
+
+/*ASCºÍGSM ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_GAS_EVENT_BASE (DWORD)(ASC_UAS_EVENT_END + 1)
+#define ASC_GAS_RSP_EVENT (DWORD)(ASC_GAS_EVENT_BASE + 50)
+#define ASC_GAS_EVENT_END (DWORD)(ASC_GAS_EVENT_BASE + 99)
+
+/*ASCºÍLTE ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_EUAS_EVENT_BASE (DWORD)(ASC_GAS_EVENT_END + 1)
+#define ASC_EUAS_RSP_EVENT (DWORD)(ASC_EUAS_EVENT_BASE + 50)
+#define ASC_EUAS_EVENT_END (DWORD)(ASC_EUAS_EVENT_BASE + 99)
+
+/*ASCºÍ¸÷AS¹«¹²µÄÏûÏ¢·¶Î§(100) */
+#define ASC_AS_EVENT_BASE (DWORD)(ASC_EUAS_EVENT_END + 1)
+#define ASC_AS_EVENT_END (DWORD)(ASC_AS_EVENT_BASE + 149)
+
+/*CBSºÍRRCµÄÏûÏ¢·¶Î§(30)*/
+#define CBS_RRC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 3320)
+#define CBS_RRC_RSP_EVENT (DWORD)(CBS_RRC_EVENT_BASE + 20)
+#define CBS_RRC_EVENT_END (DWORD)(CBS_RRC_EVENT_BASE + 29)
+
+/*GMMºÍSNDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_SNDCP_EVENT_BASE (DWORD)(CBS_RRC_EVENT_END + 1)
+#define GMM_SNDCP_EVENT_END (DWORD)(GMM_SNDCP_EVENT_BASE + 24)
+
+/*GMMºÍPDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_PDCP_EVENT_BASE (DWORD)(GMM_SNDCP_EVENT_END + 1)
+#define GMM_PDCP_EVENT_END (DWORD)(GMM_PDCP_EVENT_BASE + 24)
+
+/*SMºÍPDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_PDCP_EVENT_BASE (DWORD)(GMM_PDCP_EVENT_END + 1)
+#define SM_PDCP_RSP_EVENT (DWORD)(SM_PDCP_EVENT_BASE + 25)
+#define SM_PDCP_EVNET_END (DWORD)(SM_PDCP_EVENT_BASE + 49)
+
+/*SMºÍSNDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_SNDCP_EVENT_BASE (DWORD)(SM_PDCP_EVNET_END + 1)
+#define SM_SNDCP_RSP_EVENT (DWORD)(SM_SNDCP_EVENT_BASE + 20)
+#define SM_SNDCP_EVENT_END (DWORD)(SM_SNDCP_EVENT_BASE + 49)
+
+/*PDIºÍGSMAµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_GSMA_EVENT_BASE (DWORD)(SM_SNDCP_EVENT_END + 1)
+#define PDI_GSMA_RSP_EVENT (DWORD)(PDI_GSMA_EVENT_BASE + 10)
+#define PDI_GSMA_EVENT_END (DWORD)(PDI_GSMA_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_PDCP_EVENT_BASE (DWORD)(PDI_GSMA_EVENT_END + 1)
+#define PDI_PDCP_RSP_EVENT (DWORD)(PDI_PDCP_EVENT_BASE + 10)
+#define PDI_PDCP_EVENT_END (DWORD)(PDI_PDCP_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_URLC_EVENT_BASE (DWORD)(PDI_PDCP_EVENT_END + 1)
+#define PDCP_URLC_EVENT_END (DWORD)(PDCP_URLC_EVENT_BASE + 9)
+
+/*TAFºÍCCÏûÏ¢·¶Î§(50)*/
+#define CC_TAF_EVENT_BASE (DWORD)(PDCP_URLC_EVENT_END + 1)
+#define CC_TAF_EVENT_END (DWORD)(CC_TAF_EVENT_BASE + 49)
+
+/*UMMºÍCBSÏûÏ¢·¶Î§(50)*/
+#define UMM_CBS_EVENT_BASE (DWORD)(CC_TAF_EVENT_END + 1)
+#define UMM_CBS_RSP_EVENT (DWORD)(UMM_CBS_EVENT_BASE + 20)
+#define UMM_CBS_EVENT_END (DWORD)(UMM_CBS_EVENT_BASE + 49)
+
+/*SCIºÍURRC/CCÏûÏ¢·¶Î§(30)*/
+#define AP_SCI_EVENT_BASE (DWORD)(UMM_CBS_EVENT_END + 1)
+#define AP_SCI_EVENT_END (DWORD)(AP_SCI_EVENT_BASE + 29)
+
+/*URLCºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define URLC_URRC_EVENT_BASE (DWORD)(AP_SCI_EVENT_END + 1)
+#define URLC_URRC_RSP_EVENT (DWORD)(URLC_URRC_EVENT_BASE + 30)
+#define URLC_URRC_EVENT_END (DWORD)(URLC_URRC_EVENT_BASE + 59)
+
+/*UMACºÍURRCµÄÏûÏ¢·¶Î§(70)*/
+#define UMAC_URRC_EVENT_BASE (DWORD)(URLC_URRC_EVENT_END + 1)
+#define UMAC_URRC_RSP_EVENT (DWORD)(UMAC_URRC_EVENT_BASE + 40)
+#define UMAC_URRC_EVENT_END (DWORD)(UMAC_URRC_EVENT_BASE + 69)
+
+/*UMAC-UL/DLºÍUMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define UMAC_UMAC_EVENT_BASE (DWORD)(UMAC_URRC_EVENT_END + 1)
+#define UMAC_UMAC_EVENT_END (DWORD)(UMAC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1T_URRC_EVENT_BASE (DWORD)(UMAC_UMAC_EVENT_END + 1)
+#define L1T_URRC_RSP_EVENT (DWORD)(L1T_URRC_EVENT_BASE + 30)
+#define L1T_URRC_EVENT_END (DWORD)(L1T_URRC_EVENT_BASE + 59)
+
+/*PDCPºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_URRC_EVENT_BASE (DWORD)(L1T_URRC_EVENT_END + 1)
+#define PDCP_URRC_RSP_EVENT (DWORD)(PDCP_URRC_EVENT_BASE + 30)
+#define PDCP_URRC_EVENT_END (DWORD)(PDCP_URRC_EVENT_BASE + 59)
+
+/*URLCºÍUMACµÄÏûÏ¢·¶Î§(20)*/
+#define URLC_UMAC_EVENT_BASE (DWORD)(PDCP_URRC_EVENT_END + 1)
+#define URLC_UMAC_EVENT_END (DWORD)(URLC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍUMACµÄÏûÏ¢·¶Î§(10)*/
+#define UMAC_L1T_EVENT_BASE (DWORD)(URLC_UMAC_EVENT_END + 1)
+#define UMAC_L1T_EVENT_END (DWORD)(UMAC_L1T_EVENT_BASE + 9)
+
+/*URRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define URRC_EVENT_BASE (DWORD)(UMAC_L1T_EVENT_END + 1)
+#define URRC_EVENT_END (DWORD)(URRC_EVENT_BASE + 99)
+
+/*L1TÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1T_EVENT_BASE (DWORD)(URRC_EVENT_END + 1)
+#define L1T_EVENT_END (DWORD)(L1T_EVENT_BASE + 19)
+
+/*ÎïÀí²ãÊÊÅä²ãÖ®¼äL1T/L1EÏûÏ¢·¶Î§(30)£¨²»°üº¬L1G£¬ÓëL1G½»»¥µÄÏûϢȫ²¿ÊÇSDLÏûÏ¢£¬¶¨ÒåÔÚsig_code.hÖУ©*/
+#define L1A_EVENT_BASE (DWORD)(L1T_EVENT_END + 1)
+#define L1A_EVENT_END (DWORD)(L1A_EVENT_BASE + 29)
+
+/*ÐÒéÕ»ÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§(530)*/
+#define UMM_TIMER_EVENT_BASE (DWORD)(MMIA_TIMER_EVENT_END + 1)
+#define UMM_TIMER_EVENT_END (DWORD)(UMM_TIMER_EVENT_BASE + 49)
+
+#define MM_TIMER_EVENT_BASE (DWORD)(UMM_TIMER_EVENT_END + 1)
+#define MM_TIMER_EVENT_END (DWORD)(MM_TIMER_EVENT_BASE + 29)
+
+#define GMM_TIMER_EVENT_BASE (DWORD)(MM_TIMER_EVENT_END + 1)
+#define GMM_TIMER_EVENT_END (DWORD)(GMM_TIMER_EVENT_BASE + 29)
+
+#define CC_TIMER_EVENT_BASE (DWORD)(GMM_TIMER_EVENT_END + 1)
+#define CC_TIMER_EVENT_END (DWORD)(CC_TIMER_EVENT_BASE + 49)
+
+#define SMS_TIMER_EVENT_BASE (DWORD)(CC_TIMER_EVENT_END + 1)
+#define SMS_TIMER_EVENT_END (DWORD)(SMS_TIMER_EVENT_BASE + 19)
+
+#define SM_TIMER_EVENT_BASE (DWORD)(SMS_TIMER_EVENT_END + 1)
+#define SM_TIMER_EVENT_END (DWORD)(SM_TIMER_EVENT_BASE + 19)
+
+#define SS_TIMER_EVENT_BASE (DWORD)(SM_TIMER_EVENT_END + 1)
+#define SS_TIMER_EVENT_END (DWORD)(SS_TIMER_EVENT_BASE + 9)
+
+#define CBS_TIMER_EVENT_BASE (DWORD)(SS_TIMER_EVENT_END + 1)
+#define CBS_TIMER_EVENT_END (DWORD)(CBS_TIMER_EVENT_BASE + 9)
+
+#define UICC_TIMER_EVENT_BASE (DWORD)(CBS_TIMER_EVENT_END + 1)
+#define UICC_TIMER_EVENT_END (DWORD)(UICC_TIMER_EVENT_BASE + 19)
+
+#define URRC_TIMER_EVENT_BASE (DWORD)(UICC_TIMER_EVENT_END + 1)
+#define URRC_TIMER_EVENT_END (DWORD)(URRC_TIMER_EVENT_BASE + 79)
+
+#define URLC_TIMER_EVENT_BASE (DWORD)(URRC_TIMER_EVENT_END + 1)
+#define URLC_TIMER_EVENT_END (DWORD)(URLC_TIMER_EVENT_BASE + 19)
+
+#define UMAC_TIMER_EVENT_BASE (DWORD)(URLC_TIMER_EVENT_END + 1)
+#define UMAC_TIMER_EVENT_END (DWORD)(UMAC_TIMER_EVENT_BASE + 19)
+
+#define L1T_TIMER_EVENT_BASE (DWORD)(UMAC_TIMER_EVENT_END + 1)
+#define L1T_TIMER_EVENT_END (DWORD)(L1T_TIMER_EVENT_BASE + 19)
+
+#define PDCP_TIMER_EVENT_BASE (DWORD)(L1T_TIMER_EVENT_END + 1)
+#define PDCP_TIMER_EVENT_END (DWORD)(PDCP_TIMER_EVENT_BASE + 9)
+
+#define ROHCv1_TIMER_EVENT_BASE (DWORD)(PDCP_TIMER_EVENT_END + 1)
+#define ROHCv1_TIMER_EVENT_END (DWORD)(ROHCv1_TIMER_EVENT_BASE + 19)
+
+#define TAF_TIMER_EVENT_BASE (DWORD)(ROHCv1_TIMER_EVENT_END + 1)
+#define TAF_TIMER_EVENT_END (DWORD)(TAF_TIMER_EVENT_BASE + 19)
+
+#define GSMA_TIMER_EVENT_BASE (DWORD)(TAF_TIMER_EVENT_END + 1)
+#define GSMA_TIMER_EVENT_END (DWORD)(GSMA_TIMER_EVENT_BASE + 19)
+
+#define PDI_TIMER_EVENT_BASE (DWORD)(GSMA_TIMER_EVENT_END + 1)
+#define PDI_TIMER_EVENT_END (DWORD)(PDI_TIMER_EVENT_BASE + 19)
+
+#define ROHCv2_TIMER_EVENT_BASE (DWORD)(PDI_TIMER_EVENT_END + 1)
+#define ROHCv2_TIMER_EVENT_END (DWORD)(ROHCv2_TIMER_EVENT_BASE + 19)
+
+#define SCI_TIMER_EVENT_BASE (DWORD)(ROHCv2_TIMER_EVENT_END + 1)
+#define SCI_TIMER_EVENT_END (DWORD)(SCI_TIMER_EVENT_BASE + 9)
+
+#define STM_TIMER_EVENT_BASE (DWORD)(SCI_TIMER_EVENT_END + 1)
+#define STM_TIMER_EVENT_END (DWORD)(STM_TIMER_EVENT_BASE + 9)
+
+#define USAT_TIMER_EVENT_BASE (DWORD)(STM_TIMER_EVENT_END + 1)
+#define USAT_TIMER_EVENT_END (DWORD)(USAT_TIMER_EVENT_BASE + 9)
+
+#define TIMER_EVENT_END (DWORD)USAT_TIMER_EVENT_END
+
+/**************************************************PS msg range end********************************************************/
+
+/**************************************************UPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§(300)*/
+#define USIR_UPHY_EVENT_BASE (DWORD)PS_UPHY_EVENT_BASE
+#define USIR_UPHY_RSP_EVENT (DWORD)(USIR_UPHY_EVENT_BASE + 20)
+#define USIR_UPHY_EVENT_END (DWORD)(USIR_UPHY_EVENT_BASE + 49)
+
+#define UCSR_UPHY_EVENT_BASE (DWORD)(USIR_UPHY_EVENT_END + 1)
+#define UCSR_UPHY_RSP_EVENT (DWORD)(UCSR_UPHY_EVENT_BASE + 20)
+#define UCSR_UPHY_EVENT_END (DWORD)(UCSR_UPHY_EVENT_BASE + 49)
+
+#define UMCR_UPHY_EVENT_BASE (DWORD)(UCSR_UPHY_EVENT_END + 1)
+#define UMCR_UPHY_RSP_EVENT (DWORD)(UMCR_UPHY_EVENT_BASE + 20)
+#define UMCR_UPHY_EVENT_END (DWORD)(UMCR_UPHY_EVENT_BASE + 49)
+
+#define URBC_UPHY_EVENT_BASE (DWORD)(UMCR_UPHY_EVENT_END + 1)
+#define URBC_UPHY_RSP_EVENT (DWORD)(URBC_UPHY_EVENT_BASE + 30)
+#define URBC_UPHY_EVENT_END (DWORD)(URBC_UPHY_EVENT_BASE + 49)
+
+#define UMAC_UL_UPHY_EVENT_BASE (DWORD)(URBC_UPHY_EVENT_END + 1)
+#define UMAC_UL_UPHY_EVENT_END (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 19)
+
+#define UMAC_DL_UPHY_EVENT_BASE (DWORD)(UMAC_UL_UPHY_EVENT_END + 1)
+#define UMAC_DL_UPHY_EVENT_END (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 29)
+
+/*L1TÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1T_UPHY_EVENT_BASE (DWORD)(UMAC_DL_UPHY_EVENT_END + 1)
+#define L1T_UPHY_RSP_EVENT (DWORD)(L1T_UPHY_EVENT_BASE + 20)
+#define L1T_UPHY_EVENT_END (DWORD)(L1T_UPHY_EVENT_BASE + 49)
+
+#define PS_UPHY_EVENT_END (DWORD)L1T_UPHY_EVENT_END
+/**************************************************WPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define WSIR_WPHY_EVENT_BASE (DWORD)PS_WPHY_EVENT_BASE
+#define WSIR_WPHY_RSP_EVENT (DWORD)(WSIR_WPHY_EVENT_BASE + 20)
+#define WSIR_WPHY_EVENT_END (DWORD)(WSIR_WPHY_EVENT_BASE + 49)
+
+#define WCSR_WPHY_EVENT_BASE (DWORD)(WSIR_WPHY_EVENT_END + 1)
+#define WCSR_WPHY_RSP_EVENT (DWORD)(WCSR_WPHY_EVENT_BASE + 20)
+#define WCSR_WPHY_EVENT_END (DWORD)(WCSR_WPHY_EVENT_BASE + 49)
+
+#define WMCR_WPHY_EVENT_BASE (DWORD)(WCSR_WPHY_EVENT_END + 1)
+#define WMCR_WPHY_RSP_EVENT (DWORD)(WMCR_WPHY_EVENT_BASE + 20)
+#define WMCR_WPHY_EVENT_END (DWORD)(WMCR_WPHY_EVENT_BASE + 49)
+
+#define WRBC_WPHY_EVENT_BASE (DWORD)(WMCR_WPHY_EVENT_END + 1)
+#define WRBC_WPHY_RSP_EVENT (DWORD)(WRBC_WPHY_EVENT_BASE + 30)
+#define WRBC_WPHY_EVENT_END (DWORD)(WRBC_WPHY_EVENT_BASE + 49)
+
+#define WMAC_UL_WPHY_EVENT_BASE (DWORD)(WRBC_WPHY_EVENT_END + 1)
+#define WMAC_UL_WPHY_EVENT_END (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 19)
+
+#define WMAC_DL_WPHY_EVENT_BASE (DWORD)(WMAC_UL_WPHY_EVENT_END + 1)
+#define WMAC_DL_WPHY_EVENT_END (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 29)
+
+/*L1WÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1W_WPHY_EVENT_BASE (DWORD)(WMAC_DL_WPHY_EVENT_END + 1)
+#define L1W_WPHY_RSP_EVENT (DWORD)(L1W_WPHY_EVENT_BASE + 20)
+#define L1W_WPHY_EVENT_END (DWORD)(L1W_WPHY_EVENT_BASE + 49)
+
+#define PS_WPHY_EVENT_END (DWORD)L1W_WPHY_EVENT_END
+/**************************************************WPHY msg range end********************************************************/
+
+/**************************************************PS LTE msg range start********************************************************/
+/*EMMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EMM_TIMER_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1)
+#define EMM_TIMER_EVENT_END (DWORD)(EMM_TIMER_EVENT_BASE + 19)
+
+/*ESMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define ESM_TIMER_EVENT_BASE (DWORD)(EMM_TIMER_EVENT_END + 1)
+#define ESM_TIMER_EVENT_END (DWORD)(ESM_TIMER_EVENT_BASE + 19)
+
+/*EUPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EPDCP_TIMER_EVENT_BASE (DWORD)(ESM_TIMER_EVENT_END + 1)
+#define EPDCP_TIMER_EVENT_END (DWORD)(EPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EURLC_TIMER_EVENT_BASE (DWORD)(EPDCP_TIMER_EVENT_END + 1)
+#define EURLC_TIMER_EVENT_END (DWORD)(EURLC_TIMER_EVENT_BASE + 9)
+
+/*EUMACÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EUMAC_TIMER_EVENT_BASE (DWORD)(EURLC_TIMER_EVENT_END + 1)
+#define EUMAC_TIMER_EVENT_END (DWORD)(EUMAC_TIMER_EVENT_BASE + 9)
+
+/*EURRCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define EURRC_TIMER_EVENT_BASE (DWORD)(EUMAC_TIMER_EVENT_END + 1)
+
+/*EUCER×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCER_TIMER_EVENT_BASE (DWORD)(EURRC_TIMER_EVENT_BASE + 1)
+#define EUCER_TIMER_EVENT_END (DWORD)(EUCER_TIMER_EVENT_BASE + 19)
+
+/*EUMCR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUMCR_TIMER_EVENT_BASE (DWORD)(EUCER_TIMER_EVENT_END + 1)
+#define EUMCR_TIMER_EVENT_END (DWORD)(EUMCR_TIMER_EVENT_BASE + 19)
+
+/*EUCSR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCSR_TIMER_EVENT_BASE (DWORD)(EUMCR_TIMER_EVENT_END + 1)
+#define EUCSR_TIMER_EVENT_END (DWORD)(EUCSR_TIMER_EVENT_BASE + 19)
+
+/*EUSIR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUSIR_TIMER_EVENT_BASE (DWORD)(EUCSR_TIMER_EVENT_END + 1)
+#define EUSIR_TIMER_EVENT_END (DWORD)(EUSIR_TIMER_EVENT_BASE + 19)
+
+#define EURRC_TIMER_EVENT_END (DWORD)EUSIR_TIMER_EVENT_END
+
+/*EMMºÍUMMÄ£¿é¼äµÄÏûÏ¢IDºÅ*/
+#define EMM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 200)
+#define EMM_UMM_RSP_EVENT (DWORD)(EMM_UMM_EVENT_BASE + 19)
+#define EMM_UMM_EVENT_END (DWORD)(EMM_UMM_EVENT_BASE + 29)
+
+/*UMMºÍEPDCPÄ£¿éÖ®¼äµÄÏûÏ¢ID */
+#define UMM_EPDCP_EVENT_BASE (DWORD)(EMM_UMM_EVENT_END + 1)
+#define UMM_EPDCP_RSP_EVENT (DWORD)(UMM_EPDCP_EVENT_BASE + 9)
+#define UMM_EPDCP_EVENT_END (DWORD)(UMM_EPDCP_EVENT_BASE + 19)
+
+/* CM²ãºÍESMÄ£¿é¼äÏûÏ¢IDºÅ(ÐÂÔö)*/
+#define CM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 260)
+#define CM_ESM_RSP_EVENT (DWORD)(CM_ESM_EVENT_BASE + 9)
+#define CM_ESM_EVENT_END (DWORD)(CM_ESM_EVENT_BASE + 19)
+
+/* CM²ãºÍEMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define CM_EMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 280)
+#define CM_EMM_RSP_EVENT (DWORD)(CM_EMM_EVENT_BASE + 9)
+#define CM_EMM_EVENT_END (DWORD)(CM_EMM_EVENT_BASE + 19)
+
+/* EMMºÍESMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_EMM_EVENT_BASE (DWORD)(CM_EMM_EVENT_END + 1)
+#define ESM_EMM_RSP_EVENT (DWORD)(ESM_EMM_EVENT_BASE + 19)
+#define ESM_EMM_EVENT_END (DWORD)(ESM_EMM_EVENT_BASE + 29)
+
+/*EMMºÍERRC(CER)Ä£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_ASC_EVENT_BASE (DWORD)(ESM_EMM_EVENT_END + 1)
+#define EMM_ASC_RSP_EVENT (DWORD)(EMM_ASC_EVENT_BASE + 19)
+#define EMM_ASC_EVENT_END (DWORD)(EMM_ASC_EVENT_BASE + 49)
+
+/*EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_EPDCP_EVENT_BASE (DWORD)(EMM_ASC_EVENT_END + 1)
+#define EMM_EPDCP_RSP_EVENT (DWORD)(EMM_EPDCP_EVENT_BASE + 9)
+#define EMM_EPDCP_EVENT_END (DWORD)(EMM_EPDCP_EVENT_BASE + 19)
+
+/*ESMºÍUMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 400)
+#define ESM_UMM_RSP_EVENT (DWORD)(ESM_UMM_EVENT_BASE + 19)
+#define ESM_UMM_EVENT_END (DWORD)(ESM_UMM_EVENT_BASE + 29)
+
+
+/* ESMºÍPDCP Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define ESM_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 430)
+#define ESM_EPDCP_RSP_EVENT (DWORD)(ESM_EPDCP_EVENT_BASE + 9)
+#define ESM_EPDCP_EVENT_END (DWORD)(ESM_EPDCP_EVENT_BASE + 19)
+
+/*EURRCºÍEPDCPÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 450)
+#define EURRC_EPDCP_RSP_EVENT (DWORD)(EURRC_EPDCP_EVENT_BASE + 25)
+#define EURRC_EPDCP_EVENT_END (DWORD)(EURRC_EPDCP_EVENT_BASE + 49)
+
+/*EURRCºÍEURLCÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EURLC_EVENT_BASE (DWORD)(EURRC_EPDCP_EVENT_END + 1)
+#define EURRC_EURLC_RSP_EVENT (DWORD)(EURRC_EURLC_EVENT_BASE + 19)
+#define EURRC_EURLC_EVENT_END (DWORD)(EURRC_EURLC_EVENT_BASE + 29)
+
+/*EURRCºÍEUMACÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EUMAC_EVENT_BASE (DWORD)(EURRC_EURLC_EVENT_END + 1)
+#define EURRC_EUMAC_RSP_EVENT (DWORD)(EURRC_EUMAC_EVENT_BASE + 25)
+#define EURRC_EUMAC_EVENT_END (DWORD)(EURRC_EUMAC_EVENT_BASE + 49)
+
+/*EURRCºÍMEL2Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_MEL2_EVENT_BASE (DWORD)(EURRC_EUMAC_EVENT_END + 1)
+#define EURRC_MEL2_RSP_EVENT (DWORD)(EURRC_MEL2_EVENT_BASE + 4)
+#define EURRC_MEL2_EVENT_END (DWORD)(EURRC_MEL2_EVENT_BASE + 6)
+
+/*SMºÍESMÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define SM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 750) /*Added:KangShuJie*/
+#define SM_ESM_RSP_EVENT (DWORD)(SM_ESM_EVENT_BASE + 25) /*Added:KangShuJie*/
+#define SM_ESM_EVENT_END (DWORD)(SM_ESM_EVENT_BASE + 49) /*Added:KangShuJie*/
+
+/*EURRCÄÚ²¿ÏûϢʼþID*/
+#define EURRC_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1000)
+#define EURRC_EVENT_END (DWORD)(EURRC_EVENT_BASE + 54)
+
+#define EUPDCP_EURLC_EVENT_BASE (DWORD)(EURRC_EVENT_END + 1)
+#define EUPDCP_EURLC_EVENT_END (DWORD)(EUPDCP_EURLC_EVENT_BASE + 4)
+
+/*EURRCºÍL1EÄ£¿éÖ®¼äÏûϢʼþ*/
+#define EURRC_L1E_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1200)
+#define EURRC_L1E_RSP_EVENT (DWORD)(EURRC_L1E_EVENT_BASE + 20)
+#define EURRC_L1E_EVENT_END (DWORD)(EURRC_L1E_EVENT_BASE + 39)
+
+
+#define EUDBG_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1400)
+#define EUDBG_EVENT_END (DWORD)(EUDBG_EVENT_BASE + 19)
+
+#define LPP_ECID_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1450)
+#define LPP_ECID_EVENT_END (DWORD)(EVENT_PS_LTE_BASE + 1499)
+
+/* LTE¼¯³É²âÊÔ¼ÓÈëµÄ²âÊÔÄ£¿éʹÓõÄÏûÏ¢ */
+#define TRS_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1500)
+#define TRS_ESM_RSP_EVENT (DWORD)(TRS_ESM_EVENT_BASE + 9)
+#define TRS_ESM_EVENT_END (DWORD)(TRS_ESM_EVENT_BASE + 29)
+
+#define TRS_EMM_EVENT_BASE (DWORD)(TRS_ESM_EVENT_END + 1)
+#define TRS_EMM_RSP_EVENT (DWORD)(TRS_EMM_EVENT_BASE + 5)
+#define TRS_EMM_EVENT_END (DWORD)(TRS_EMM_EVENT_BASE + 29)
+
+#define ENB_EMM_ESM_EVENT_BASE (DWORD)(TRS_EMM_EVENT_END + 1)
+#define ENB_EMM_ESM_RSP_EVENT (DWORD)(ENB_EMM_ESM_EVENT_BASE + 9)
+#define ENB_EMM_ESM_EVENT_END (DWORD)(ENB_EMM_ESM_EVENT_BASE + 19)
+
+#define ENB_RRC_EMM_EVENT_BASE (DWORD)(ENB_EMM_ESM_EVENT_END + 1)
+#define ENB_RRC_EMM_RSP_EVENT (DWORD)(ENB_RRC_EMM_EVENT_BASE + 9)
+#define ENB_RRC_EMM_EVENT_END (DWORD)(ENB_RRC_EMM_EVENT_BASE + 19)
+
+#define ENB_RRC_EVENT_BASE (DWORD)(ENB_RRC_EMM_EVENT_END + 1)
+#define ENB_RRC_RSP_EVENT (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENB_RRC_EVENT_END (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+/* LTE ¼¯³É²âÊÔÊý¾ÝÃæÔö¼ÓµÄÏûÏ¢ÆðʼºêADD BY LIUZHIPENG AT 09-12-28 */
+
+#define ENRRC_ENPDCP_EVENT_BASE (DWORD)(ENB_RRC_EVENT_END + 1)
+#define ENRRC_ENPDCP_RSP_EVENT (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 20)
+#define ENRRC_ENPDCP_EVENT_END (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 44)
+/* EDCP Ó²¼þ¼ÓËÙ½Ó¿ÚÏûÏ¢ */
+#define PS_ENDCP_EVENT_BASE (DWORD)(ENRRC_ENPDCP_EVENT_END + 1)
+#define PS_ENDCP_RSP_EVENT (DWORD)(PS_ENDCP_EVENT_BASE + 9)
+#define PS_ENDCP_EVENT_END (DWORD)(PS_ENDCP_EVENT_BASE + 19)
+
+/* ENPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENPDCP_TIMER_EVENT_BASE (DWORD)(PS_ENDCP_EVENT_END + 1)
+#define ENPDCP_TIMER_EVENT_END (DWORD)(ENPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENRLC_TIMER_EVENT_BASE (DWORD)(ENPDCP_TIMER_EVENT_END + 1)
+#define ENRLC_TIMER_EVENT_END (DWORD)(ENRLC_TIMER_EVENT_BASE + 9)
+
+/* ENRRCÓëENRLCµÄÏûÏ¢¿Õ¼ä */
+#define ENRRC_ENRLC_EVENT_BASE (DWORD)(ENRLC_TIMER_EVENT_END + 1)
+#define ENRRC_ENRLC_RSP_EVENT (DWORD)(ENRRC_ENRLC_EVENT_BASE + 9)
+#define ENRRC_ENRLC_EVENT_END (DWORD)(ENRRC_ENRLC_EVENT_BASE + 19)
+/* ENMACÓëEPHYµÄÏûÏ¢¿Õ¼ä*/
+#define ENMAC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENRLC_EVENT_END + 1)
+#define ENMAC_EPHY_RSP_EVENT (DWORD)(ENMAC_EPHY_EVENT_BASE + 9)
+#define ENMAC_EPHY_EVENT_END (DWORD)(ENMAC_EPHY_EVENT_BASE + 19)
+
+#define ENRRC_ENMAC_EVENT_BASE (DWORD)(ENMAC_EPHY_EVENT_END + 1)
+#define ENRRC_ENMAC_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 9)
+#define ENRRC_ENMAC_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 19)
+
+#define ENRRC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENMAC_EVENT_END + 1)
+#define ENRRC_EPHY_RSP_EVENT (DWORD)(ENRRC_EPHY_EVENT_BASE + 9)
+#define ENRRC_EPHY_EVENT_END (DWORD)(ENRRC_EPHY_EVENT_BASE + 19)
+
+#define TRS_EPHY_EVENT_BASE (DWORD)(ENRRC_EPHY_EVENT_END + 1)
+#define TRS_EPHY_RSP_EVENT (DWORD)(TRS_EPHY_EVENT_BASE + 10)
+#define TRS_EPHY_EVENT_END (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+
+#define TRS_ENMAC_EVENT_BASE (DWORD)(TRS_EPHY_EVENT_END + 1)
+#define TRS_ENMAC_RSP_EVENT (DWORD)(TRS_ENMAC_EVENT_BASE + 10)
+#define TRS_ENMAC_EVENT_END (DWORD)(TRS_ENMAC_EVENT_BASE + 19)
+
+#define ENPDI_ENPDCP_EVENT_BASE (DWORD)(TRS_ENMAC_EVENT_END + 1)
+#define ENPDI_ENPDCP_RSP_EVENT (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 10)
+#define ENPDI_ENPDCP_EVENT_END (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 19)
+
+#define TRS_SIMULPDI_EVENT_BASE (DWORD)(ENPDI_ENPDCP_EVENT_END + 1)
+#define TRS_SIMULPDI_RSP_EVENT (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define TRS_SIMULPDI_EVENT_END (DWORD)(TRS_SIMULPDI_EVENT_BASE + 19)
+
+#define TRS_SIMULENPDI_EVENT_BASE (DWORD)(TRS_SIMULPDI_EVENT_END + 1)
+#define TRS_SIMULENPDI_RSP_EVENT (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define TRS_SIMULENPDI_EVENT_END (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 19)
+
+/* =========================================================================
+ TRS --ΪÁËGCF²âÊÔ¶ø¶¨Òå2010/3/3 SHIFANGMING
+=========================================================================*/
+#define LTE_GCF_TRS_EVENT_BASE (DWORD)(TRS_SIMULENPDI_EVENT_END + 1)
+#define LTE_GCF_TRS_RSP_EVENT (DWORD)(LTE_GCF_TRS_EVENT_BASE + 10)
+#define LTE_GCF_TRS_EVENT_END (DWORD)(LTE_GCF_TRS_EVENT_BASE + 19)
+
+#define LTE_GCF_TIMER_EVENT_BASE (DWORD)(LTE_GCF_TRS_EVENT_END + 1)
+#define LTE_GCF_TIMER_EVENT_END (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 19)
+
+
+/*TRSºÍENRLCÄ£¿éÖ®¼äµÄÏûϢʼþ2010/3/1 LIUHUAN*/
+#define TRS_ENRLC_EVENT_BASE (DWORD)(LTE_GCF_TIMER_EVENT_END + 1)
+#define TRS_ENRLC_RSP_EVENT (DWORD)(TRS_ENRLC_EVENT_BASE + 10)
+#define TRS_ENRLC_EVENT_END (DWORD)(TRS_ENRLC_EVENT_BASE + 19)
+
+#define ENPDCP_ENRLC_EVENT_BASE (DWORD)(TRS_ENRLC_EVENT_END + 1)
+#define ENPDCP_ENRLC_EVENT_END (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 9)
+
+//--ENMEL2ÏûϢʼþ
+#define ENMEL2_EVENT_BASE (DWORD)(ENPDCP_ENRLC_EVENT_END + 1)
+#define ENMEL2_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5)
+#define ENMEL2_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6)
+/**************************************************PS LTE msg range end********************************************************/
+
+
+/**************************************************PS W msg range start********************************************************/
+
+/*WRLCºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_WRLC_EVENT_BASE (DWORD)(EVENT_PS_W_BASE + 1)
+#define PDCP_WRLC_EVENT_END (DWORD)(PDCP_WRLC_EVENT_BASE + 9)
+
+
+/*WRLCºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define WRLC_WRRC_EVENT_BASE (DWORD)(PDCP_WRLC_EVENT_END + 1)
+#define WRLC_WRRC_RSP_EVENT (DWORD)(WRLC_WRRC_EVENT_BASE + 30)
+#define WRLC_WRRC_EVENT_END (DWORD)(WRLC_WRRC_EVENT_BASE + 59)
+
+/*WMACºÍWRRCµÄÏûÏ¢·¶Î§(70)*/
+#define WMAC_WRRC_EVENT_BASE (DWORD)(WRLC_WRRC_EVENT_END + 1)
+#define WMAC_WRRC_RSP_EVENT (DWORD)(WMAC_WRRC_EVENT_BASE + 40)
+#define WMAC_WRRC_EVENT_END (DWORD)(WMAC_WRRC_EVENT_BASE + 69)
+
+/*WMAC-UL/DLºÍWMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define WMAC_WMAC_EVENT_BASE (DWORD)(WMAC_WRRC_EVENT_END + 1)
+#define WMAC_WMAC_EVENT_END (DWORD)(WMAC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1W_WRRC_EVENT_BASE (DWORD)(WMAC_WMAC_EVENT_END + 1)
+#define L1W_WRRC_RSP_EVENT (DWORD)(L1W_WRRC_EVENT_BASE + 30)
+#define L1W_WRRC_EVENT_END (DWORD)(L1W_WRRC_EVENT_BASE + 59)
+
+/*PDCPºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_WRRC_EVENT_BASE (DWORD)(L1W_WRRC_EVENT_END + 1)
+#define PDCP_WRRC_RSP_EVENT (DWORD)(PDCP_WRRC_EVENT_BASE + 30)
+#define PDCP_WRRC_EVENT_END (DWORD)(PDCP_WRRC_EVENT_BASE + 59)
+
+/*WRLCºÍWMACµÄÏûÏ¢·¶Î§(20)*/
+#define WRLC_WMAC_EVENT_BASE (DWORD)(PDCP_WRRC_EVENT_END + 1)
+#define WRLC_WMAC_EVENT_END (DWORD)(WRLC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWMACµÄÏûÏ¢·¶Î§(10)*/
+#define WMAC_L1W_EVENT_BASE (DWORD)(WRLC_WMAC_EVENT_END + 1)
+#define WMAC_L1W_EVENT_END (DWORD)(WMAC_L1W_EVENT_BASE + 9)
+
+/*WRRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define WRRC_EVENT_BASE (DWORD)(WMAC_L1W_EVENT_END + 1)
+#define WRRC_EVENT_END (DWORD)(WRRC_EVENT_BASE + 99)
+
+/*L1WÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1W_EVENT_BASE (DWORD)(WRRC_EVENT_END + 1)
+#define L1W_EVENT_END (DWORD)(L1W_EVENT_BASE + 19)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_WAS_EVENT_BASE (DWORD)(L1W_EVENT_END + 1)
+#define ASC_WAS_RSP_EVENT (DWORD)(ASC_WAS_EVENT_BASE + 50)
+#define ASC_WAS_EVENT_END (DWORD)(ASC_WAS_EVENT_BASE + 99)
+
+/*WÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§140()*/
+
+#define WRRC_TIMER_EVENT_BASE (DWORD)(ASC_WAS_EVENT_END + 1)
+#define WRRC_TIMER_EVENT_END (DWORD)(WRRC_TIMER_EVENT_BASE + 79)
+
+#define WRLC_TIMER_EVENT_BASE (DWORD)(WRRC_TIMER_EVENT_END + 1)
+#define WRLC_TIMER_EVENT_END (DWORD)(WRLC_TIMER_EVENT_BASE + 19)
+
+#define WMAC_TIMER_EVENT_BASE (DWORD)(WRLC_TIMER_EVENT_END + 1)
+#define WMAC_TIMER_EVENT_END (DWORD)(WMAC_TIMER_EVENT_BASE + 19)
+
+#define L1W_TIMER_EVENT_BASE (DWORD)(WMAC_TIMER_EVENT_END + 1)
+#define L1W_TIMER_EVENT_END (DWORD)(L1W_TIMER_EVENT_BASE + 19)
+
+/*W²âÊÔÏûÏ¢·¶Î§(40)*/
+
+#define WSIR_TEST_EVENT_BASE (DWORD)(L1W_TIMER_EVENT_END + 1)
+#define WSIR_TEST_EVENT_END (DWORD)(WSIR_TEST_EVENT_BASE + 9)
+
+#define NWRLC_EVENT_BASE (DWORD)(WSIR_TEST_EVENT_END + 1)
+#define NWRLC_EVENT_END (DWORD)(NWRLC_EVENT_BASE + 19)
+
+#define NWMAC_EVENT_BASE (DWORD)(NWRLC_EVENT_END + 1)
+#define NWMAC_EVENT_END (DWORD)(NWMAC_EVENT_BASE + 9)
+
+/*º¯ÊýÐÅÁî¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define WRRC_FUNC_EVENT_BASE (DWORD)(NWMAC_EVENT_END + 1)
+#define WRRC_FUNC_EVENT_END (DWORD)(WRRC_FUNC_EVENT_BASE + 49)
+
+/*º¯Êý·µ»ØÖµ¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define RRC_FUNC_TRACE_BASE (DWORD)(WRRC_FUNC_EVENT_END + 1)
+#define RRC_FUNC_TRACE_END (DWORD)(RRC_FUNC_TRACE_BASE + 49)
+
+/**************************************************PS W msg range end********************************************************/
+/* ========================================================================
+ CM-MM/GMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 0)
+#define CM_EST_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 1)
+#define CM_REL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 2)
+#define CM_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 3)
+#define CM_CANCEL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 4)
+#define CM_REEST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 5)
+#define CM_CMSRV_IND_EV (DWORD)(CM_MM_EVENT_BASE + 6)
+#define CM_IN_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 7)
+#define CM_OUT_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 8)
+#define CM_DATA_IND_EV (DWORD)(CM_MM_EVENT_BASE + 9)
+#define CM_RATCHG_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 10)
+#define CM_RATCHG_END_IND_EV (DWORD)(CM_MM_EVENT_BASE + 11)
+#define CM_RRC_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 12)
+#define CM_SRVCC_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 13)
+#define CM_SRVCC_SUCC_IND_EV (DWORD)(CM_MM_EVENT_BASE + 14)
+#define CM_SRVCC_FAIL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 15)
+#define CM_SM_ONLY_ONE_EPDNCON_EV (DWORD)(CM_MM_EVENT_BASE + 16)
+#define CM_ESM_DETACH_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 17)
+#define CM_SM_DEACT_NON_EMERGENCY_EV (DWORD)(CM_MM_EVENT_BASE + 18)
+#define CC_UMM_RETURN_IMS_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 19)
+#define UMM_CC_RETURN_IMS_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 20)
+/*IVSÏ߳̽ÓÊÕÏûÏ¢*/
+#define IVS_DL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 21)
+#define CC_IVS_RESET_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 22)
+#define CC_IVS_MSD_IND_EV (DWORD)(CM_MM_EVENT_BASE + 23)
+/*IVS·¢¸øCC*/
+#define IVS_CC_MSD_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 24)
+#define IVS_CC_MSD_STATE_IND_EV (DWORD)(CM_MM_EVENT_BASE + 25)
+
+#define PSAP_UL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 26)
+
+/* ========================================================================
+ UMM£MM/GMM/EMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 0)
+#define UMM_DETACH_REQ_EV (DWORD)(UMM_EVENT_BASE + 1)
+#define UMM_PENDING_REQ_EV (DWORD)(UMM_EVENT_BASE + 2)
+#define UMM_RESUME_REQ_EV (DWORD)(UMM_EVENT_BASE + 3)
+#define UMM_ABORT_REQ_EV (DWORD)(UMM_EVENT_BASE + 4)
+#define UMM_EMERGENCY_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 5)
+#define UMM_CSEST_REQ_EV (DWORD)(UMM_EVENT_BASE + 6)
+#define UMM_PAGE_IND_EV (DWORD)(UMM_EVENT_BASE + 7)
+#define UMM_CCO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 8)
+#define UMM_HO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 9)
+#define UMM_CELL_RESEL_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 10)
+#define UMM_LU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 11)
+#define UMM_FAIL_IND_EV (DWORD)(UMM_EVENT_BASE + 12)
+#define UMM_RU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 13)
+#define UMM_DETACH_IND_EV (DWORD)(UMM_EVENT_BASE + 14)
+#define UMM_DETACH_CNF_EV (DWORD)(UMM_EVENT_BASE + 15)
+#define UMM_MM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 16)
+#define UMM_GMM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 17)
+#define UMM_EMERGENCY_T3412_EXPIRY_IND_EV (DWORD)(UMM_EVENT_BASE + 18)
+#define UMM_CELL_NO_CHG_IND_EV (DWORD)(UMM_EVENT_BASE + 19)
+#define UMM_CS_EST_REJ_EV (DWORD)(UMM_EVENT_BASE + 20)
+#define UMM_CS_SRV_NOTIFY_IND_EV (DWORD)(UMM_EVENT_BASE + 21)
+#define UMM_CCO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 22)
+#define UMM_HO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 23)
+#define UMM_CELL_RESEL_END_IND_EV (DWORD)(UMM_EVENT_BASE + 24)
+#define UMM_ATTACH_STATE_SYNC_REQ_EV (DWORD)(UMM_EVENT_BASE + 25)
+#define UMM_CHECK_REL_RRC_REQ_EV (DWORD)(UMM_EVENT_BASE + 26)
+#define UMM_PS_CONTEXT_IND_EV (DWORD)(UMM_EVENT_BASE + 27)
+#define UMM_START_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 28)
+#define UMM_STOP_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 29)
+#define UMM_POWEROFF_IND_RV (DWORD)(UMM_EVENT_BASE + 30)
+#define UMM_SWITCH_CARD_END_EV (DWORD)(UMM_EVENT_BASE + 31)
+/* ========================================================================
+ UMM£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_ASC_CAMPON_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 0)
+#define UMM_ASC_CAMPON_ANYCELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 1)
+#define UMM_ASC_UPDATE_PLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 2)
+#define UMM_ASC_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 3)
+#define UMM_ASC_SWITCH_RADIO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 4)
+#define UMM_ASC_TRY_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 5)
+#define UMM_ASC_STOP_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 6)
+#define UMM_ASC_PCH_PRE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 7)
+#define UMM_ASC_ABORT_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 8)
+#define UMM_ASC_UPDATE_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 9)
+#define UMM_ASC_INACTIVE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 10)
+#define UMM_ASC_PAGE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 11)
+#define UMM_ASC_LOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 12)
+#define UMM_ASC_UNLOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 13)
+#define UMM_ASC_GSM_SRV_NOTIFY_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 14)
+#define UMM_ASC_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 15)
+#define UMM_ASC_UPDATE_SYSCONFIG_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 16)
+#define UMM_ASC_UPDATE_LTE_ACT_EV (DWORD)(UMM_ASC_EVENT_BASE + 17)
+#define UMM_ASC_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(UMM_ASC_EVENT_BASE + 18)
+#define UMM_ASC_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 19)
+#define UMM_ASC_STOP_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 20)
+#define UMM_ASC_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 21)
+#define UMM_ASC_SYS_CAMP_LTESUBACT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 22)
+#define UMM_ASC_DELFORBIDDENLAILIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 23)
+#define UMM_ASC_HPPLMN_END_IND_EV (DWORD)(UMM_ASC_EVENT_BASE + 24)
+#define UMM_ASC_XCELLINFO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 25)
+#define UMM_ASC_XCELLINFO_ABORT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 26)
+#define UMM_ASC_UPDATE_ECALLMODE_EV (DWORD)(UMM_ASC_EVENT_BASE + 27)
+
+#define UMM_ASC_CELL_INFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 0)
+#define UMM_ASC_NOCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 1)
+#define UMM_ASC_PLMN_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 2)
+#define UMM_ASC_SWITCH_RADIO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 3)
+#define UMM_ASC_CNINFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 4)
+#define UMM_ASC_TRY_HPPLMN_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 5)
+#define UMM_ASC_PLMN_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 6)
+#define UMM_ASC_INACTIVE_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 7)
+#define UMM_ASC_HO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 9)
+#define UMM_ASC_CCO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 10)
+#define UMM_ASC_CELL_RESEL_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 11)
+#define UMM_ASC_HO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 12)
+#define UMM_ASC_CCO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 13)
+#define UMM_ASC_CELL_RESEL_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 14)
+#define UMM_ASC_TRY_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 15)
+#define UMM_ASC_ABORT_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 16)
+#define UMM_ASC_LOCK_CELL_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 17)
+#define UMM_ASC_CSG_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 18)
+#define UMM_ASC_CSG_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 19)
+#define UMM_ASC_TBF_RELEASE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 20)
+#define UMM_ASC_SCAN_UE_BAND_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 21)
+#define UMM_ASC_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(UMM_ASC_RSP_EVENT + 22)
+#define UMM_ASC_CELL_UPDATE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 23) /*GRR֪ͨUMM×öСÇø¸üÐÂ*/
+#define UMM_ASC_RECONST_PSRES_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 24)
+#define UMM_ASC_SUBMODE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 25)
+#define UMM_ASC_CELL_LOST_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 26)
+#define UMM_ASC_CELL_RECOVERAGE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 27)
+#define UMM_ASC_XCELLINFO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 28)
+#define UMM_ASC_XCELLINFO_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 29)
+#define UMM_ASC_NEIGCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 30)
+#define UMM_ASC_SCAN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 31)
+/* ========================================================================
+ MM/GMM/CC£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_ASC_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 0)
+#define GMM_ASC_REL_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 1)
+#define GMM_ASC_DATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 2)
+#define GMM_ASC_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 3)
+#define GMM_ASC_GRR_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 4)
+#define GMM_ASC_GRR_INFO_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 5)
+#define GMM_ASC_LL_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 6)
+#define GMM_ASC_LL_TRIGGER_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 7)
+#define GMM_ASC_LL_SUSPEND_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 8)
+#define GMM_ASC_LL_RESUME_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 9)
+#define GMM_ASC_LL_UNITDATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 10)
+#define GMM_ASC_CLEAN_PEND_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 11)
+
+#define GMM_ASC_EST_CNF_EV (DWORD)(GMM_ASC_RSP_EVENT + 0)
+#define GMM_ASC_EST_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 1)
+#define GMM_ASC_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 2)
+#define GMM_ASC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 3)
+#define GMM_ASC_CCSYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 4)
+#define GMM_ASC_PAGE_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 5)
+#define GMM_ASC_DATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 6)
+#define GMM_ASC_SUSPEND_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 7)
+#define GMM_ASC_GSM_CC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 8)
+#define GMM_ASC_CS_RAB_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 9)
+#define GMM_ASC_GSM_CC_TCH_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 10)
+#define GMM_ASC_SAPI3_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 11)
+#define GMM_ASC_SRVCC_START_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 12)
+#define GMM_ASC_SRVCC_END_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 13)
+#define GMM_ASC_LL_UNITDATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 14)
+#define GMM_ASC_LL_TRIGGER_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 15)
+#define GMM_ASC_LL_STATUS_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 16)
+#define GMM_ASC_LL_USER_DATA_PRESENT_EV (DWORD)(GMM_ASC_RSP_EVENT + 17)
+#define GMM_ASC_GSM_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 18)
+#define GMM_ASC_UTRA_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 19)/*WCDMA*//*¶ÔÓ¦AS²ãµÄASC_TD_CURR_BEAR_IND_EVºÍASC_W_CURR_BEAR_IND_EV*/
+#define GMM_ASC_PSHO_INFO_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 20) /*LLC֪ͨGMMÇл»Ïà¹Ø¼ÓÃÜËã·¨ ASC£>GMM*/
+#define GMM_ASC_SEND_CMP_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 21)
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* ========================================================================
+ ASC£TD ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->UCSR*/
+#define ASC_TD_SWITCH_RADIO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 0)
+#define ASC_TD_CAMPON_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 1)
+#define ASC_TD_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 2)
+#define ASC_TD_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 3)
+#define ASC_TD_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 4)
+#define ASC_TD_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 5)
+#define ASC_TD_TRY_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 6)
+#define ASC_TD_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 7)
+#define ASC_TD_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_UAS_EVENT_BASE + 8)
+#define ASC_TD_IRAT_CAMPON_REJ_EV (DWORD)(ASC_UAS_EVENT_BASE + 9)
+#define ASC_TD_IRAT_CAMPON_CNF_EV (DWORD)(ASC_UAS_EVENT_BASE + 10)
+#define ASC_TD_ABORT_RSP_EV (DWORD)(ASC_UAS_EVENT_BASE + 11)
+
+/*NAS->ASC->AS*/
+#define ASC_TD_LOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 12)
+#define ASC_TD_UNLOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 13)
+#define ASC_TD_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 14)
+#define ASC_TD_DATA_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 15)
+#define ASC_TD_REL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 16)
+#define ASC_TD_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 17)
+#define ASC_TD_PAGE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 18)
+#define ASC_TD_INACTIVE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 19)
+#define ASC_TD_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 20)
+#define ASC_TD_NO_DRX_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 21)
+#define ASC_TD_DRX_RSV_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 22)
+#define ASC_TD_STOP_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 23)
+#define ASC_TD_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 24)
+#define ASC_TD_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 25)
+#define ASC_TD_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 26)
+#define ASC_TD_XCELLINFO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 27)
+#define ASC_TD_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 28)
+
+/*UCSR->ASC */
+#define ASC_TD_SWITCH_RADIO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 0)
+#define ASC_TD_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 1)
+#define ASC_TD_IRAT_CAMPON_REQ_EV (DWORD)(ASC_UAS_RSP_EVENT + 2)
+#define ASC_TD_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 3)
+#define ASC_TD_TRY_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 4)
+
+#define ASC_TD_NOCELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 5)
+#define ASC_TD_PLMN_LIST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 6)
+#define ASC_TD_PLMN_LIST_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 7)
+#define ASC_TD_TRY_HPPLMN_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 8)
+#define ASC_TD_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 9)
+#define ASC_TD_ABORT_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 10)
+#define ASC_TD_SUBMODE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 11)
+#define ASC_TD_LOCK_CELL_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 12)
+#define ASC_TD_SCAN_UE_BAND_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 13)
+
+/*UCSR->ASC or UCER->ASC*/
+#define ASC_TD_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_UAS_RSP_EVENT + 14)
+#define ASC_TD_INACTIVE_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 15)
+#define ASC_TD_EST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 16)
+#define ASC_TD_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 17)
+#define ASC_TD_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 18)
+#define ASC_TD_PAGING_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 19)
+#define ASC_TD_SYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 20)
+#define ASC_TD_PCH_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 21)
+#define ASC_TD_UURLC_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 22)
+#define ASC_TD_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 23)
+#define ASC_TD_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 24)
+#define ASC_TD_SRVCC_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 25)
+#define ASC_TD_SRVCC_END_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 26)
+#define ASC_TD_CCSYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 27)
+#define ASC_TD_CS_RAB_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 28)
+#define ASC_TD_CNINFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 29)
+
+/* URBC->ASC */
+#define ASC_TD_CURR_BEAR_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 30)
+#define ASC_TD_RECONST_PSRES_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 31)
+#define ASC_TD_CELL_LOST_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 32)
+#define ASC_TD_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 33)
+
+/*UCSR->ASC add*/
+#define ASC_TD_XCELLINFO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 34)
+#define ASC_TD_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 35)
+#define ASC_TD_XCELLINFO_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 36)
+
+/* ========================================================================
+ ASC£WCDMA ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->WCSR*/
+#define ASC_W_SWITCH_RADIO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 0)
+#define ASC_W_CAMPON_CELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 1)
+#define ASC_W_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 2)
+#define ASC_W_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 3)
+#define ASC_W_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 4)
+#define ASC_W_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 5)
+#define ASC_W_TRY_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 6)
+#define ASC_W_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 7)
+#define ASC_W_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_WAS_EVENT_BASE + 8)
+#define ASC_W_IRAT_CAMPON_REJ_EV (DWORD)(ASC_WAS_EVENT_BASE + 9)
+#define ASC_W_IRAT_CAMPON_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 10)
+#define ASC_W_ABORT_RSP_EV (DWORD)(ASC_WAS_EVENT_BASE + 11)
+#define ASC_W_IRAT_INACTIVE_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 12)
+
+/*NAS->ASC->AS*/
+#define ASC_W_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 13)
+#define ASC_W_DATA_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 14)
+#define ASC_W_REL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 15)
+#define ASC_W_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 16)
+#define ASC_W_PAGE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 17)
+#define ASC_W_INACTIVE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 18)
+#define ASC_W_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 19)
+#define ASC_W_NO_DRX_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 20)
+#define ASC_W_DRX_RSV_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 21)
+#define ASC_W_STOP_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 22)
+#define ASC_W_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 23)
+#define ASC_W_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 24)
+#define ASC_W_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 25)
+#define ASC_W_XCELLINFO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 26)
+#define ASC_W_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 27)
+
+/*WCSR->ASC */
+#define ASC_W_SWITCH_RADIO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 0)
+#define ASC_W_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 1)
+#define ASC_W_IRAT_CAMPON_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 2)
+#define ASC_W_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 3)
+#define ASC_W_TRY_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 4)
+#define ASC_W_IRAT_INACTIVE_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 5)
+
+#define ASC_W_NOCELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 6)
+#define ASC_W_PLMN_LIST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 7)
+#define ASC_W_PLMN_LIST_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 8)
+#define ASC_W_TRY_HPPLMN_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 9)
+#define ASC_W_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 10)
+#define ASC_W_ABORT_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 11)
+#define ASC_W_SUBMODE_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 12)
+#define ASC_W_SCAN_UE_BAND_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 13)
+
+/*WCSR->ASC or WCER->ASC*/
+#define ASC_W_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_WAS_RSP_EVENT + 14)
+#define ASC_W_INACTIVE_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 15)
+#define ASC_W_EST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 16)
+#define ASC_W_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 17)
+#define ASC_W_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 18)
+#define ASC_W_PAGING_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 19)
+#define ASC_W_SYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 20)
+#define ASC_W_PCH_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 21)
+#define ASC_W_UURLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 22)
+#define ASC_W_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 23)
+#define ASC_W_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 24)
+#define ASC_W_SRVCC_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 25)
+#define ASC_W_SRVCC_END_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 26)
+#define ASC_W_CCSYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 27)
+#define ASC_W_CS_RAB_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 28)
+#define ASC_W_CNINFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 29)
+/* WRBC->ASC */
+#define ASC_W_CURR_BEAR_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 30)
+#define ASC_W_RECONST_PSRES_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 31)
+/*WCDMA*/
+#define ASC_W_UWRLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 32)
+/*WCSR/UCSR -> ASC*/
+#define ASC_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 33)
+#define ASC_UTRA_RESEL_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 34)
+#define ASC_UTRA_COMPLETE_EV (DWORD)(ASC_WAS_RSP_EVENT + 35)
+#define ASC_W_XCELLINFO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 36)
+#define ASC_W_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 37)
+#define ASC_W_XCELLINFO_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 38)
+
+/* ========================================================================
+ ASC£GSM ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->GSMAÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 0)
+#define ASC_GSM_CAMPON_CELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 1)
+#define ASC_GSM_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 2)
+#define ASC_GSM_INACTIVE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 3)
+#define ASC_GSM_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 4)
+#define ASC_GSM_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 5)
+#define ASC_GSM_TRY_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 6)
+#define ASC_GSM_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 7)
+#define ASC_GSM_UPDATE_PARAM_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 8)
+#define ASC_GSM_UPDATE_EPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 9)
+#define ASC_GSM_GSM_SRV_NOTIFY_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 10)
+#define ASC_GSM_PCHPRE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 11)
+#define ASC_GSM_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 12)
+#define ASC_GSM_EST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 13)
+#define ASC_GSM_DATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 14)
+#define ASC_GSM_REL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 15)
+#define ASC_GSM_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 16)
+#define ASC_GSM_INFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 17)
+#define ASC_GSM_ABORT_RSP_EV (DWORD)(ASC_GAS_EVENT_BASE + 18)
+
+/*ASC->GSMAµÄ,GSMAÊÊÅäLLCµÄÏûϢʼþºÅ*/
+#define ASC_LLC_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 19)
+#define ASC_LLC_TRIGGER_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 20)
+#define ASC_LLC_SUSPEND_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 21)
+#define ASC_LLC_RESUME_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 22)
+#define ASC_LLC_UNITDATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 23)
+#define ASC_SNP_GMM_SEQ_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 24)
+
+//ÁÚÇøÐÅÏ¢»ñÈ¡ÏûÏ¢
+#define ASC_GSM_XCELLINFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 25)
+#define ASC_GSM_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 26)
+
+/*GSMA->ASCÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 0)
+#define ASC_GSM_CELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 1)
+#define ASC_GSM_NOCELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 2)
+#define ASC_GSM_INACTIVE_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 3)
+#define ASC_GSM_PLMN_LIST_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 4)
+#define ASC_GSM_PLMN_LIST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 5)
+#define ASC_GSM_ABORT_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 6)
+#define ASC_GSM_TRY_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 7)
+#define ASC_GSM_TRY_HPPLMN_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 8)
+#define ASC_GSM_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 9)
+#define ASC_GSM_CELL_UPDATE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 10)
+#define ASC_GSM_SUBMODE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 11)
+#define ASC_GSM_EST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 12)
+#define ASC_GSM_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 13)
+#define ASC_GSM_SYNC_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 14)
+#define ASC_GSM_CCSYNC_IND_GSM_EV (DWORD)(ASC_GAS_RSP_EVENT + 15)
+#define ASC_GSM_SUSPEND_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 16)
+#define ASC_GSM_PAGE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 17)
+#define ASC_GSM_EST_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 18)
+#define ASC_GSM_DATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 19)
+#define ASC_GSM_SAPI3_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 20)
+#define ASC_GSM_CCTCH_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 21)
+#define ASC_GSM_TBF_RELEASE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 22)
+#define ASC_GSM_UTRA_CSHO_ENDIND_EV (DWORD)(ASC_GAS_RSP_EVENT + 23)
+
+#define ASC_LLC_UNITDATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 24)
+#define ASC_LLC_TRIGGER_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 25)
+#define ASC_LLC_STATUS_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 26)
+#define ASC_LLC_USER_DATA_PRESENT_EV (DWORD)(ASC_GAS_RSP_EVENT + 27)
+#define ASC_LLC_PSHO_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 28)
+
+/*GSMA->ASC->CBS (ASC͸´«)*/
+#define ASC_GSM_ETWS_NOTIFY_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 29)
+/*AS_GSM_LTE_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_REDIRECT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 30)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_RESEL_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 31)
+
+/*GSMA->ASC->SM (ASC͸´«)*/
+#define ASC_GSM_CURR_BEAR_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 32)
+#define ASC_SNP_GMM_SEQ_RSP_EV (DWORD)(ASC_GAS_RSP_EVENT + 33)
+
+/*GSMA->ASC->SMS (ASC͸´«)*/
+#define ASC_GSM_SEND_CMP_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 34)
+
+#define ASC_GSM_XCELLINFO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 35)
+#define ASC_GSM_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 36)
+#define ASC_GSM_XCELLINFO_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 37)
+
+/* ========================================================================
+ ASC£LTE ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC-->EURRC*/
+#define ASC_LTE_SWITCH_RADIO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 0)
+#define ASC_LTE_CAMPON_CELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 1)
+#define ASC_LTE_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 2)
+#define ASC_LTE_UPDATE_PLMN_FTAI_IND_EV (DWORD)(ASC_EUAS_EVENT_BASE + 3)
+#define ASC_LTE_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 4)
+#define ASC_LTE_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 5)
+#define ASC_LTE_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 6)
+#define ASC_LTE_STOP_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 7)
+#define ASC_LTE_TRY_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 8)
+#define ASC_LTE_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 9)
+#define ASC_LTE_EST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 10)
+#define ASC_LTE_EST_ABT_EV (DWORD)(ASC_EUAS_EVENT_BASE + 11)
+#define ASC_LTE_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 12)
+#define ASC_LTE_KENB_RSP_EV (DWORD)(ASC_EUAS_EVENT_BASE + 13)
+#define ASC_LTE_REL_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 14)
+#define ASC_LTE_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 15)
+#define ASC_LTE_INACTIVE_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 16)
+#define ASC_LTE_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_EUAS_EVENT_BASE + 17)
+#define ASC_LTE_DETACH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 18)
+#define ASC_LTE_GROUP_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 19)
+#define ASC_LTE_SCANSWITCH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 20)
+#define ASC_LTE_XCELLINFO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 21)
+#define ASC_LTE_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 22)
+#define ASC_LTE_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 23)
+
+/* EURRC->ASC */
+#define ASC_LTE_SWITCH_RADIO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 0)
+#define ASC_LTE_CELL_INFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 1)
+#define ASC_LTE_NOCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 2)
+#define ASC_LTE_PAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 3)
+#define ASC_LTE_PLMN_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 4)
+#define ASC_LTE_PLMN_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 5)
+#define ASC_LTE_CSG_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 6)
+#define ASC_LTE_CSG_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 7)
+#define ASC_LTE_TRY_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 8)
+#define ASC_LTE_TRY_HPPLMN_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 9)
+#define ASC_LTE_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 10)
+#define ASC_LTE_ABORT_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 11)
+#define ASC_LTE_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 13)
+#define ASC_LTE_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 14)
+#define ASC_LTE_DATA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 15)
+#define ASC_LTE_EST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 16)
+#define ASC_LTE_EST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 17)
+#define ASC_LTE_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 18)
+#define ASC_LTE_ABA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 19)
+#define ASC_LTE_DRB_SETUP_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 20)
+#define ASC_LTE_TRANS_FAIL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 21)
+#define ASC_LTE_KENB_REQ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 22)
+#define ASC_LTE_UE_INFO_CHANGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 23)
+#define ASC_LTE_DATA_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 24)
+#define ASC_LTE_SEC_PARA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 25)
+#define ASC_LTE_INACTIVE_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 26)
+#define ASC_LTE_ABORT_RSP_EV (DWORD)(ASC_EUAS_RSP_EVENT + 27)
+/*AS_LTE_TD_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_REDIRECT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 28)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_RESEL_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 29)
+#define ASC_LTE_SRVCC_START_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 30)
+#define ASC_LTE_SRVCC_END_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 31)
+#define ASC_LTE_CMAS_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 32)
+#define ASC_LTE_SCAN_UE_BAND_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 33)
+#define ASC_LTE_CELL_LOST_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 34)
+#define ASC_LTE_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 35)
+#define ASC_LTE_GROUP_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 36)
+#define ASC_LTE_TGCCH_MSG_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 37)
+#define ASC_LTE_SCANGROUPINFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 38)
+#define ASC_LTE_SET_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 39)
+#define ASC_LTE_REL_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 40)
+#define ASC_LTE_XCELLINFO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 41)
+#define ASC_LTE_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 42)
+#define ASC_LTE_XCELLINFO_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 43)
+#define ASC_LTE_NEIGCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 44)
+#define ASC_LTE_SCAN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 45)
+/* ========================================================================
+ ASC£¸÷AS¹«¹²ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*LTE->UTRAÖØÑ¡*/
+#define AS_LTE_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 0)
+#define AS_LTE_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 1)
+#define AS_LTE_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 2)
+
+/*LTE->UTRAÖض¨Ïò*/
+#define AS_LTE_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 3)
+#define AS_LTE_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 4)
+#define AS_LTE_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 5)
+
+/*LTE->UTRA PSÇл»*/
+#define AS_LTE_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 6)
+#define AS_LTE_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 7)
+#define AS_LTE_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 8)
+
+/*LTE->GSMÖØÑ¡*/
+#define AS_LTE_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 9)
+#define AS_LTE_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 10)
+#define AS_LTE_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 11)
+
+/*LTE->GSMÖض¨Ïò*/
+#define AS_LTE_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 12)
+#define AS_LTE_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 13)
+#define AS_LTE_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 14)
+
+/*LTE->TD CSÇл»*/
+#define AS_LTE_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 15)
+#define AS_LTE_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 16)
+#define AS_LTE_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 17)
+
+/*LTE->GSM CCO*/
+#define AS_LTE_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 18)
+#define AS_LTE_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 19)
+#define AS_LTE_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 20)
+
+/*LTE->GSM PSÇл»*/
+#define AS_LTE_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 21)
+#define AS_LTE_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 22)
+#define AS_LTE_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 23)
+
+/*UTRA->LTEÖØÑ¡*/
+#define AS_UTRA_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 24)
+#define AS_UTRA_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 25)
+#define AS_UTRA_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 26)
+
+/*UTRA->LTEÖض¨Ïò*/
+#define AS_UTRA_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 27)
+#define AS_UTRA_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 28)
+#define AS_UTRA_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 29)
+
+/*UTRA->LTE PSÇл»*/
+#define AS_UTRA_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 30)
+#define AS_UTRA_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 31)
+#define AS_UTRA_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 32)
+
+/*UTRA->GSMÖØÑ¡*/
+#define AS_UTRA_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 33)
+#define AS_UTRA_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 34)
+#define AS_UTRA_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 35)
+
+/*UTRA>GSMÖض¨Ïò*/
+#define AS_UTRA_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 36)
+#define AS_UTRA_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 37)
+#define AS_UTRA_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 38)
+
+/*UTRA->GSM CSÇл»*/
+#define AS_UTRA_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 39)
+#define AS_UTRA_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 40)
+#define AS_UTRA_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 41)
+
+/*UTRA->GSM CCO*/
+#define AS_UTRA_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 42)
+#define AS_UTRA_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 43)
+#define AS_UTRA_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 44)
+
+/*UTRA->GSM PSÇл»*/
+#define AS_UTRA_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 45)
+#define AS_UTRA_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 46)
+#define AS_UTRA_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 47)
+
+/*UTRA->GSM Êý¾Ý°áÒÆ*/
+#define AS_UTRA_GSM_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 48)
+
+/*GSM->LTEÖØÑ¡*/
+#define AS_GSM_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 49)
+#define AS_GSM_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 50)
+#define AS_GSM_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 51)
+
+/*GSM->LTEÖض¨Ïò*/
+#define AS_GSM_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 52)
+#define AS_GSM_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 53)
+#define AS_GSM_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 54)
+
+/*GSM->LTE PSÇл»*/
+#define AS_GSM_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 55)
+#define AS_GSM_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 56)
+#define AS_GSM_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 57)
+
+/*GSM->LTE CCO*/
+#define AS_GSM_LTE_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 58)
+#define AS_GSM_LTE_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 59)
+#define AS_GSM_LTE_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 60)
+
+/*GSM->UTRAÖØÑ¡*/
+#define AS_GSM_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 61)
+#define AS_GSM_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 62)
+#define AS_GSM_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 63)
+
+/*GSM->UTRAÖض¨Ïò*/
+#define AS_GSM_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 64)
+#define AS_GSM_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 65)
+#define AS_GSM_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 66)
+
+/*GSM->UTRA CSÇл»*/
+#define AS_GSM_UTRA_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 67)
+#define AS_GSM_UTRA_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 68)
+#define AS_GSM_UTRA_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 69)
+
+/*GSM->UTRA PSÇл»*/
+#define AS_GSM_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 70)
+#define AS_GSM_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 71)
+#define AS_GSM_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 72)
+
+/*GSM->UTRA CCO*/
+#define AS_GSM_UTRA_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 73)
+#define AS_GSM_UTRA_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 74)
+#define AS_GSM_UTRA_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 75)
+
+/*GSM->UTRA Êý¾Ý°áÒÆ*/
+#define AS_GSM_UTRA_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 76)
+/*WCDMA PREDEF*/
+#define AS_GSM_UTRA_READ_PREDEF_CONF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 77)
+#define AS_GSM_UTRA_READ_PREDEF_CONF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 78)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 79)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 80)
+
+
+/*NAS->ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_UPDATE_SYSCONFIG_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 81)
+#define AS_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 82)
+
+/*ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_L1_RSRC_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 83)
+#define AS_L1_RSRC_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 84)
+#define AS_L1_RSRC_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 85)
+#define AS_L1_RSRC_FREE_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 86)
+
+/*.(UCSR EUCSR GSMA)AS->ASC*/
+#define AS_IRAT_CCO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 87)
+#define AS_IRAT_HO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 88)
+#define AS_IRAT_CELL_RESEL_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 89)
+
+#define AS_LTE_GSM_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 90)
+#define AS_LTE_GSM_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 91)
+#define AS_LTE_GSM_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 92)
+#define AS_LTE_GSM_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 93)
+
+#define AS_LTE_UTRA_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 94)
+#define AS_LTE_UTRA_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 95)
+#define AS_LTE_UTRA_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 96)
+#define AS_LTE_UTRA_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 97)
+
+#define AS_LTE_TD_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 98)
+#define AS_LTE_W_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 99)
+
+/* ========================================================================
+ CBS£ASCÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_ASC_NO_DRX_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 0)
+#define CBS_ASC_DRX_RSV_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 1)
+#define CBS_ASC_STOP_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 2)
+
+#define CBS_ASC_PCH_CELL_INFO_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 0)
+#define CBS_ASC_UURLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 1)
+#define CBS_ASC_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 2)
+#define CBS_ASC_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 3)
+#define CBS_ASC_CMAS_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 4)
+/*WCDMA*/
+#define CBS_ASC_UWRLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ GMM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_GMM_SEQ_IND_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 0)
+#define SNP_GMM_SEQ_RSP_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ GMM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDCP_GMM_NW_REL_ANYRB_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 0)
+#define GMM_PDCP_RB_CHG_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ SM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_SM_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 0)
+#define SNP_SM_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 1)
+#define SNP_SM_MOD_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 2)
+#define SNP_SM_RAT_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 3)
+#define SNP_SM_RAT_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 4)
+#define SNP_SM_RAT_SEQ_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 5)
+#define SNP_SM_RAT_CHG_COMP_EV (DWORD)(SM_SNDCP_EVENT_BASE + 6)
+
+#define SNP_SM_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 0)
+#define SNP_SM_MOD_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 1)
+#define SNP_SM_STATUS_REQ_EV (DWORD)(SM_SNDCP_RSP_EVENT + 2)
+#define SNP_SM_RAT_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 3)
+#define SNP_SM_RAT_SEQ_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 4)
+#define SNP_SM_RAT_DEACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 5)
+
+/* ========================================================================
+ TAF£CCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_TAF_CONNECT_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 0)
+#define CC_TAF_CONNECT_CNF_EV (DWORD)(CC_TAF_EVENT_BASE + 1)
+#define CC_TAF_CONNECT_CNF_NEG_EV (DWORD)(CC_TAF_EVENT_BASE + 2)
+#define CC_TAF_RELEASE_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 3)
+#define CC_TAF_RELEASE_IND_EV (DWORD)(CC_TAF_EVENT_BASE + 4)
+#define CC_TAF_PEND_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 5)
+#define CC_TAF_RESUME_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS-UMMÖ®¼äµÄÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define UMM_CBS_START_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 0)
+#define UMM_CBS_STOP_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 1)
+
+#define UMM_CBS_CELL_INFO_IND_EV (DWORD)(UMM_CBS_RSP_EVENT + 0)
+
+/* ========================================================================
+ URRC/CC£SCIÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CSCI_CONFIG_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 0)
+#define CSCI_CDEC_CTRL_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 1)
+#define CSCI_CONFIG_REL_EV (DWORD)(AP_SCI_EVENT_BASE + 2)
+#define CSCI_CONFIG_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 3)
+#define CSCI_UNRECOVER_ERR_EV (DWORD)(AP_SCI_EVENT_BASE + 4)
+#define CSCI_CDEC_CTRL_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 5)
+
+/* ========================================================================
+ URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_READ_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 0)
+#define URRC_READ_SYSINFO_IND_EV (DWORD)(URRC_EVENT_BASE + 1)
+#define URRC_READ_SYSINFO_REJ_EV (DWORD)(URRC_EVENT_BASE + 2)
+#define URRC_STOP_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 3)
+#define URRC_READ_DYN_SIB_REQ_EV (DWORD)(URRC_EVENT_BASE + 4)
+#define URRC_READ_DYN_SIB_CNF_EV (DWORD)(URRC_EVENT_BASE + 5)
+#define URRC_SIB_MODIFIED_IND_EV (DWORD)(URRC_EVENT_BASE + 6)
+#define URRC_CELLUPDATE_REQ_EV (DWORD)(URRC_EVENT_BASE + 7)
+#define URRC_CELL_RESEL_REQ_EV (DWORD)(URRC_EVENT_BASE + 8)
+#define URRC_CELL_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 9)
+#define URRC_REL_CONN_REQ_EV (DWORD)(URRC_EVENT_BASE + 10)
+#define URRC_RESUME_CELL_REQ_EV (DWORD)(URRC_EVENT_BASE + 11)
+#define URRC_RPLMN_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 12)
+#define URRC_RESOURE_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 13)
+#define URRC_RESOURCE_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 14)
+#define URRC_UPDATE_EPLMN_REQ_EV (DWORD)(URRC_EVENT_BASE + 15)
+#define URRC_HIGH_MOBILITY_IND (DWORD)(URRC_EVENT_BASE + 16)
+#define URRC_HO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 17)
+#define URRC_HO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 18)
+#define URRC_HO_TO_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 19)
+#define URRC_HO_TO_UTRAN_CNF_EV (DWORD)(URRC_EVENT_BASE + 20)
+#define URRC_HO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 21)
+#define URRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 22)
+#define URRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 23)
+#define URRC_CCO_TO_UTRAN_IND_EV (DWORD)(URRC_EVENT_BASE + 24)
+#define URRC_CCO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 25)
+#define URRC_RADIO_LINK_FAIL_IND_EV (DWORD)(URRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define URRC_NEIBCELL_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 27)
+#define URRC_FACH_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 28)
+#define URRC_FACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 29)
+#define URRC_DRX_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 30)
+#define URRC_SEND_BUF_EST_REQ_EV (DWORD)(URRC_EVENT_BASE + 31)
+#define URRC_ABORT_RATCHG_REQ_EV (DWORD)(URRC_EVENT_BASE + 32)
+#define URRC_BAR_RESUME_IND_EV (DWORD)(URRC_EVENT_BASE + 33)
+#define URRC_CHG_CAMPON_TYPE_EV (DWORD)(URRC_EVENT_BASE + 34)
+#define URRC_GET_RF_REQ_EV (DWORD)(URRC_EVENT_BASE + 35) /*USIR->UCSR*/
+#define URRC_GET_RF_CNF_EV (DWORD)(URRC_EVENT_BASE + 36) /*UCSR->USIR*/
+#define URRC_SYSINFO_CONTAINER_IND_EV (DWORD)(URRC_EVENT_BASE + 37) /*UCSR->USIR*/
+#define URRC_ETWS_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 38)
+#define URRC_ETWS_CFG_END_EV (DWORD)(URRC_EVENT_BASE + 39)
+#define URRC_ETWS_CONTINUE_REQ_EV (DWORD)(URRC_EVENT_BASE + 40)
+#define URRC_DRX_CHANGE_IND_EV (DWORD)(URRC_EVENT_BASE + 41) /*URBC->UMCR*/
+#define URRC_EFACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 42)/*UCMR->URBC*/
+#define URRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(URRC_EVENT_BASE + 43)
+#define URRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(URRC_EVENT_BASE + 44)
+#define URRC_OUT_OF_SYNC_EV (DWORD)(URRC_EVENT_BASE + 45)
+#define URRC_RESUME_IN_SYNC_EV (DWORD)(URRC_EVENT_BASE + 46)
+#define URRC_LBS_MEAS_IND (DWORD)(URRC_EVENT_BASE + 47)
+/* ========================================================================
+ URLC - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CURLC_CONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 0)
+#define CURLC_RELEASE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 1)
+#define CURLC_LOOP_TEST_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 2)
+#define CURLC_SUSPEND_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 3)
+#define CURLC_RESUME_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 4)
+#define CURLC_CONTINUE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 5)
+#define UURLC_DATA_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 6)
+#define CURLC_CBS_RBCONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 7)
+#define CURLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(URLC_URRC_EVENT_BASE + 8)
+
+#define CURLC_SUSPEND_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 0)
+#define CURLC_LOOP_TEST_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 1)
+#define UURLC_DATA_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 2)
+#define CURLC_STATUS_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 3)
+#define UURLC_DATA_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 4)
+#define CURLC_CONFIG_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 5)
+#define CURLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(URLC_URRC_RSP_EVENT + 6)
+
+/* ========================================================================
+ UMAC - URRC/UMAC - UMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 0)
+#define CUMAC_RACH_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 1)
+#define CUMAC_RNTI_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 2)
+#define CUMAC_HS_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 3)
+#define CUMAC_HS_RESET_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 4)
+#define CUMAC_TFC_CTRL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 5)
+#define CUMAC_CONFIG_ABORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 6)
+#define CUMAC_ASC_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 7)
+#define CUMAC_DEL_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 8)
+#define CUMAC_TV_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 9)
+#define CUMAC_Q_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 10)
+#define CUMAC_UE_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 11)
+#define CUMAC_TV_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 12)
+#define CUMAC_Q_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 13)
+#define CUMAC_UE_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 14)
+#define CUMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 15)
+#define CUMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 16)
+#define CUMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 17)
+#define CUMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 18)
+#define CUMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 19)
+#define CUMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 20)
+#define CUMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 21)
+#define CUMAC_CRC_RESULT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 22)
+#define CUMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 23)
+#define CUMAC_CONTINUE_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 24)
+#define CUMAC_IDLE_PERIOD_EV (DWORD)(UMAC_URRC_EVENT_BASE + 25)
+#define CUMAC_CELL_RESEL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 26)
+#define CUMAC_HSPA_EPCH_CFG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 27)
+#define CUMAC_UPDATE_ERNTI_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 28)
+
+#define CUMAC_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 0)
+#define UUMAC_PCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 1)
+#define UUMAC_BCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 2)
+#define CUMAC_CONFIG_CHG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 3)
+#define CUMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 4)
+#define CUMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 5)
+#define CUMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 6)
+#define CUMAC_TV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 7)
+#define CUMAC_Q_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 8)
+#define CUMAC_UE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 9)
+#define CUMAC_ERUCCH_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 10)
+#define CUMAC_FACH_CFG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 11)
+#define CUMAC_CELL_RESEL_CNF_EV (DWORD)(UMAC_URRC_RSP_EVENT + 12)
+/* ========================================================================
+ UMAC - UL/DL - UMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(UMAC_UMAC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1T - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_GSM_MEAS_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 0)
+#define L1T_GSM_BSIC_VERIFY_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 1)
+#define L1T_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 3)
+#define L1T_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 4)
+#define L1T_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 5)
+#define L1T_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 6)
+#define L1T_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 7)
+#define L1T_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 8)
+#define L1T_TD_GET_RF_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 9)
+#define L1T_PLMN_END_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 10)
+#define L1T_IRAT_RSRC_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 11)
+
+#define L1T_GSM_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 0)
+#define L1T_TD_GET_RF_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 1)
+#define L1T_IRAT_RSRC_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 2)
+#define L1T_LTE_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDCP - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 1)
+#define CPDCP_RELOC_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 2)
+#define CPDCP_RELOC_COMP_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 3)
+#define CPDCP_RELOC_FAIL_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 4)
+#define CPDCP_DL_PDU_SIZE_CHG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 5)
+#define CPDCP_ROHC_TARGET_MODE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 6)
+#define CPDCP_SCRI_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 7)
+#define CPDCP_FD_MONITOR_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 8)
+#define CPDCP_FD_NO_DATA_CNF_EV (DWORD)(PDCP_URRC_EVENT_BASE + 9)
+
+
+#define CPDCP_RELOC_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 0)
+#define CPDCP_CONFIG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 1)
+#define CPDCP_RELOC_REJ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 2)
+#define CPDCP_DL_PDU_SIZE_CHG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 3)
+#define CPDCP_DATA_TRANSFER_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 4)
+#define CPDCP_FD_NO_DATA_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 5)
+
+
+/* ========================================================================
+ URLC - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UUMAC_DATA_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 0)
+#define CUMAC_HS_RESET_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 2)
+#define UURLC_DL_CTRL_PDU_REQ_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 3)
+#define UURLC_MAKE_AMDPDU_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ISR_FRAME_IND_EV (DWORD)(UMAC_L1T_EVENT_BASE + 0)
+
+/* ========================================================================
+ SM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_PDCP_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 0)
+#define SM_PDCP_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 1)
+#define SM_PDCP_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 2)
+#define SM_PDCP_ACT_ALREADY_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 3)
+#define SM_PDCP_RAT_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 4)
+#define SM_PDCP_RAT_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 5)
+#define SM_PDCP_RAT_SEQ_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 6)
+#define SM_PDCP_HC_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 7)
+#define SM_PDCP_RAT_CHG_COMP_EV (DWORD)(SM_PDCP_EVENT_BASE + 8)
+#define SM_PDCP_MODIFY_CNF_EV (DWORD)(SM_PDCP_EVENT_BASE + 9)
+
+#define SM_PDCP_STATUS_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 0)
+#define SM_PDCP_RAT_ACT_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 1)
+#define SM_PDCP_RAT_SEQ_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 2)
+#define SM_PDCP_MODIFY_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDI - GSMA ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDI_GSM_DATA_REQ_EV (DWORD)(PDI_GSMA_EVENT_BASE + 0)
+
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UPDI_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 0)
+#define UPDI_DATA_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 1)
+#define CPDI_NOT_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 2)
+#define CPDI_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 3)
+#define PDI_EPDCP_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 4)
+
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UURLC_PDCP_DATA_REQ_EV (DWORD)(PDCP_URLC_EVENT_BASE + 0)
+#define UURLC_PDCP_DATA_IND_EV (DWORD)(PDCP_URLC_EVENT_BASE + 1)
+/* ========================================================================
+ PDCP - RLC ÏûÏ¢ºÅ¶¨Òå(²Î¿¼RLC - RRC)
+======================================================================== */
+
+
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_BCH_READ_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 1)
+#define P_BCH_OPEN_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 2)
+#define P_BCH_RELEASE_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 3)
+
+#define P_SFN_DECODE_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 1)
+#define P_BCH_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 2)
+#define P_BCH_OPEN_REJ_EV (DWORD)(USIR_UPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ UCSR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_FREQUENCY_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 1)
+#define P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 2)
+#define P_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 3)
+#define P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 4)
+#define P_CAMPON_A_CELL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 5)
+#define P_TD_REL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 6)
+#define P_TD_RESET_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 7)
+#define P_TD_SLEEP_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 8)
+#define P_TD_SET_IRAT_MODE_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 9)
+
+#define P_FREQUENCY_SCAN_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 1)
+#define P_CELL_SEARCH_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 2)
+#define P_TD_RESET_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 3)
+#define P_TD_REL_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMCR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 1)
+#define P_INTER_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 2)
+#define P_MEAS_REL_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 5)
+#define P_FMO_INFO_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 6)
+
+#define P_INTRA_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 1)
+#define P_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 2)
+#define P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 3)
+#define P_DETECT_CELL_INFO_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 4)
+#define P_SERVCELL_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 7)
+/* ========================================================================
+ URBC - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 1)
+#define P_DL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 2)
+#define P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 3)
+#define P_UL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 4)
+#define P_DL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 5)
+#define P_UL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 6)
+#define P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 7)
+#define P_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 8)
+#define P_STOP_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 9)
+#define P_ADD_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 10)
+#define P_REL_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 11)
+#define P_REL_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 12)
+#define P_ADD_MODIFY_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 13)
+#define P_STOP_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 14)
+#define P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(URBC_UPHY_EVENT_BASE + 15)
+#define P_ADD_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 16)
+#define P_REL_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 17)
+#define P_PLCCH_ADD_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 18)
+#define P_HSPA_PLUS_FACH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 19)
+#define P_HSPA_PLUS_PCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 20)
+#define P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 21)
+#define P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 22)
+#define P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 23)
+#define P_UL_PHY_CH_CTRL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 24)
+
+#define P_DL_RL_SETUP_MODIFY_CNF_EV (DWORD)(URBC_UPHY_RSP_EVENT + 1)
+#define P_IN_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 2)
+#define P_OUT_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 3)
+#define P_UL_ESTABLISH_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMAC_UL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_RACH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 0)
+#define P_DL_DATA_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 1)
+#define P_TFC_POWER_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 2)
+#define P_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 3)
+#define P_UL_DATA_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 4)
+#define P_ABORT_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 5)
+#define P_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 6)
+#define P_ERUCCH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 7)
+#define P_ABORT_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 8)
+#define P_SET_AGCH_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 9)
+#define P_CELL_RESEL_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 10)
+#define P_CELL_RESEL_CNF_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 11)
+#define P_SYNC_CMD_RESP_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 12)
+/* ========================================================================
+ UMAC_DL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_QUALITY_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 0)
+#define P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 1)
+#define P_QUALITY_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 2)
+#define P_UE_INTERNAL_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1T - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G_L1T_GSM_INACT_TIME_IND_EV*/
+#define P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G_L1T_ABORT_GSM_GAP_REQ_EV*/
+#define P_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 3)
+#define P_CARD2_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 4) /*T_zTD_P_card2_gap_req*/
+#define P_CARD2_GAP_REL_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 5) /*T_zTD_P_card2_gap_rel_req*/
+#define P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 6) /*T_zTD_P_card2_stop_gap_req*/
+#define P_CARD1_SUSPEND_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 7) /*T_zTD_P_card1_suspend_req*/
+#define P_CARD1_RESUME_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 8) /*T_zTD_P_card1_resume_req*/
+#define P_TD_ZTPCG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 9)
+
+#define P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 1)
+#define P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 2)
+#define P_BCH_RELEASE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 3)
+#define P_CAMPON_A_CELL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 4)
+#define P_DPCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 5)
+#define P_REL_SCCPCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 6)
+#define P_STOP_PAGING_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 7)
+#define P_STOP_CBS_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 8)
+#define P_REL_HSDPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 9)
+#define P_REL_HSUPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 10)
+#define P_RACH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 11)
+#define P_ERUCCH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 12)
+#define P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 13)
+#define P_UMTS_TIMER_SNAPSHOT_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 14)
+#define P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 15)
+#define P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 16)
+#define P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 17)
+#define P_CARD2_GAP_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 18) /*T_zTD_P_card2_gap_ind*/
+#define P_CARD2_GAP_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 19) /*T_zTD_P_card2_gap_rel_cnf*/
+#define P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 20) /*T_zTD_P_card2_stop_gap_cnf*/
+#define P_CARD1_SUSPEND_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 21) /*T_zTD_P_card1_suspend_cnf*/
+#define P_TD_ZTPCG_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 22)
+
+/* ========================================================================
+ L1T ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_CHECK_RF_IND_EV (DWORD)(L1T_EVENT_BASE + 1)
+#define P_ACTIVE_IND_EV (DWORD)(L1T_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_DONE_REQ_EV (DWORD)(L1T_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1E/L1Gµ÷L1T º¯ÊýÉèÖÃÖ÷¸¨Ä£Ê½µÄº¯ÊýÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_FUNC_SET_MODE_REQ_EV (DWORD)(L1T_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T/L1E/L1WÖ®¼äÏûÏ¢ºÅ¶¨Òå(ÎïÀí²ãÊÊÅä²ãL1A)
+======================================================================== */
+#define L1_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 0)
+#define L1_GET_RF_CNF_EV (DWORD)(L1A_EVENT_BASE + 1)
+#define UTRAN_IRAT_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 2)
+#define UTRAN_BLIND_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 3)
+/*WCDMA*/
+#define L1A_FUNC_SET_MODE_REQ_EV (DWORD)(L1A_EVENT_BASE + 4)
+#define L1A_TD_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 5)/*TDÏòÖ÷ÖÆʽҪÉäƵÇëÇóÏûÏ¢*/
+#define L1A_GET_RF_FROM_TD_CNF_EV (DWORD)(L1A_EVENT_BASE + 6)/*TDÈóöÉäƵºó¸øÆäËûÖÆʽµÄ»Ø¸´ÏûÏ¢*/
+#define L1A_W_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 7)
+#define L1A_GET_RF_FROM_W_CNF_EV (DWORD)(L1A_EVENT_BASE + 8)
+#define L1A_LTE_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 9)
+#define L1A_GET_RF_FROM_LTE_CNF_EV (DWORD)(L1A_EVENT_BASE + 10)
+/*w¸¨Ä£Ï²âÁ¿Éϱ¨¹²ÓÃW_P_INTER_FREQ_MEAS_IND_EV*/
+/*** ÔSIG_CODE.HÖÐÒÆÖ²¹ýÀ´µÄÏûÏ¢ ***/
+ /* START OF DLL */
+#define L2_CONNECT_IND (DWORD)(LAPDM_EVENT_BASE + 0)
+#define L2_DATA_IND (DWORD)(LAPDM_EVENT_BASE + 1)
+#define DL_UNIT_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 2)
+#define DL_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 3)
+#define DL_ESTABLISH_REQ (DWORD)(LAPDM_EVENT_BASE + 4)
+#define DL_IRAT_HO_REQ (DWORD)(LAPDM_EVENT_BASE + 5)
+#define DL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 6)
+#define DL_RECONNECT_REQ (DWORD)(LAPDM_EVENT_BASE + 7)
+#define DL_RESUME_REQ (DWORD)(LAPDM_EVENT_BASE + 8)
+#define DL_SUSPEND_REQ (DWORD)(LAPDM_EVENT_BASE + 9)
+#define MDL_CONFIG (DWORD)(LAPDM_EVENT_BASE + 10)
+#define MDL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 11)
+#define PH_START_T200 (DWORD)(LAPDM_EVENT_BASE + 12)
+#define T200 (DWORD)(LAPDM_EVENT_BASE + 13)
+ /* END OF DLL */
+
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äBEGIN**************************/
+#define T_SI2N_AVAIL (DWORD)(GRR_EVENT_BASE + 83)
+#define T3206 (DWORD)(GRR_EVENT_BASE + 84)
+#define T3208 (DWORD)(GRR_EVENT_BASE + 85)
+#define T3210 (DWORD)(GRR_EVENT_BASE + 86)
+#define T_NCELL_VALID_TIMER (DWORD)(GRR_EVENT_BASE + 87)
+#define T_P_SI_STATUS_TIMER (DWORD)(GRR_EVENT_BASE + 88)
+#define T_CELL_SUPERVISION (DWORD)(GRR_EVENT_BASE + 89)
+#define T_PENALTY_0 (DWORD)(GRR_EVENT_BASE + 90)
+#define T_PENALTY_1 (DWORD)(GRR_EVENT_BASE + 91)
+#define T_PENALTY_2 (DWORD)(GRR_EVENT_BASE + 92)
+#define T_PENALTY_3 (DWORD)(GRR_EVENT_BASE + 93)
+#define T_PENALTY_4 (DWORD)(GRR_EVENT_BASE + 94)
+#define T_PENALTY_5 (DWORD)(GRR_EVENT_BASE + 95)
+#define T_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 96)
+#define T_RESELECTION_DELAY (DWORD)(GRR_EVENT_BASE + 97)
+#define T_SCELL_RESEL_DELAY (DWORD)(GRR_EVENT_BASE + 98)
+#define T_SYS_INFO_READ (DWORD)(GRR_EVENT_BASE + 99)
+#define T_PSI_CYCLE (DWORD)(GRR_EVENT_BASE + 100)
+#define T_NCELL_SI_READ (DWORD)(GRR_EVENT_BASE + 101)
+#define T_CALL_REEST_TIMEOUT (DWORD)(GRR_EVENT_BASE + 102)
+#define T3122 (DWORD)(GRR_EVENT_BASE + 103)
+#define T3142 (DWORD)(GRR_EVENT_BASE + 104)
+#define T3172 (DWORD)(GRR_EVENT_BASE + 105)
+#define T3200 (DWORD)(GRR_EVENT_BASE + 106)
+#define T_SYS_INFO_VALID (DWORD)(GRR_EVENT_BASE + 107)
+#define T_RXLEV_VALID (DWORD)(GRR_EVENT_BASE + 108)
+#define T_BETTER_C2 (DWORD)(GRR_EVENT_BASE + 109)
+#define T_SYNC_READ (DWORD)(GRR_EVENT_BASE + 110)
+#define T_NON_DRX (DWORD)(GRR_EVENT_BASE + 111)
+#define T_MONITOR_OLD_SCELL (DWORD)(GRR_EVENT_BASE + 112)
+#define T_TWO_IA_SUPERVISION (DWORD)(GRR_EVENT_BASE + 113)
+#define T_SENT_MEAS_REPORT (DWORD)(GRR_EVENT_BASE + 114)
+#define T_PSI_UNSOLICITED (DWORD)(GRR_EVENT_BASE + 115)
+#define T_ABN_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 116)
+#define T_ABN_CELL_RESEL_SCELL (DWORD)(GRR_EVENT_BASE + 117)
+#define T_TESTPARAM (DWORD)(GRR_EVENT_BASE + 118)
+#define T_CELL_BARRED_TIMER (DWORD)(GRR_EVENT_BASE + 119)
+#define T_CELL_SEL_IND (DWORD)(GRR_EVENT_BASE + 120)
+#define T3218 (DWORD)(GRR_EVENT_BASE + 121)
+#define T309 (DWORD)(GRR_EVENT_BASE + 122)
+#define T_BETTER_UTRAN (DWORD)(GRR_EVENT_BASE + 123)
+#define T_IR_WAIT_TIMER (DWORD)(GRR_EVENT_BASE + 124)
+#define T_IR_CELL_INVALID_TIMER (DWORD)(GRR_EVENT_BASE + 125)
+#define T3232_EV (DWORD)(GRR_EVENT_BASE + 126)
+#define T_RESELECTION_EV (DWORD)(GRR_EVENT_BASE + 127)
+#define T3230_EV (DWORD)(GRR_EVENT_BASE + 128)
+#define T_DISABLE_UMTS_MEAS_EV (DWORD)(GRR_EVENT_BASE + 129)
+#define T_DISABLE_LTE_MEAS_EV (DWORD)(GRR_EVENT_BASE + 130)
+
+#define T_IR_READ_PREDEF_CONF_TIMER (DWORD)(GRR_EVENT_BASE + 139)//¸ø¶¨Ê±Æ÷ÏûÏ¢ºÅÔ¤Áô10¸ö
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äEND*****************************/
+ /* END OF GRR */
+
+ /* START OF MAC */
+#define MAC_PDCH_REL_REQ (DWORD)(GMAC_EVENT_BASE + 0)
+#define MAC_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 1)
+#define RLC_MAC_TLLI_ASSIGN_REQ (DWORD)(GMAC_EVENT_BASE + 2)
+#define RLC_MAC_UPLINK_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 3)
+#define RLC_MAC_REL_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 4)
+#define RLC_MAC_DEACT_CNF (DWORD)(GMAC_EVENT_BASE + 5)
+#define RLC_MAC_CTRL_BLOCK_REQ (DWORD)(GMAC_EVENT_BASE + 6)
+#define GRR_MAC_CLASSMARK_IND (DWORD)(GMAC_EVENT_BASE + 7)
+#define GRR_MAC_UPDATE_PARAM_REQ (DWORD)(GMAC_EVENT_BASE + 8)
+#define GRR_MAC_FREQ_UPDATE_REQ (DWORD)(GMAC_EVENT_BASE + 9)
+#define GRR_MAC_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 10)
+#define GRR_MAC_POLLING_REQ (DWORD)(GMAC_EVENT_BASE + 11)
+#define GRR_MAC_CIRCUIT_REQ (DWORD)(GMAC_EVENT_BASE + 12)
+#define GRR_MAC_CIRCUIT_ABORT_REQ (DWORD)(GMAC_EVENT_BASE + 13)
+#define GRR_MAC_DEACT_REQ (DWORD)(GMAC_EVENT_BASE + 14)
+#define GRR_MAC_IDLE_CHN_CNF (DWORD)(GMAC_EVENT_BASE + 15)
+#define GRR_MAC_CELL_CHANGE_IND (DWORD)(GMAC_EVENT_BASE + 16)
+#define GRR_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 17)
+#define GRR_MAC_STOP_TIMER (DWORD)(GMAC_EVENT_BASE + 18)
+#define GRR_MAC_TESTPARAM_REQ (DWORD)(GMAC_EVENT_BASE + 19)
+#define GRR_MAC_SUSPEND_REQ (DWORD)(GMAC_EVENT_BASE + 20)
+#define T3126 (DWORD)(GMAC_EVENT_BASE + 21)
+#define T3146 (DWORD)(GMAC_EVENT_BASE + 22)
+#define T3162 (DWORD)(GMAC_EVENT_BASE + 23)
+#define T3164 (DWORD)(GMAC_EVENT_BASE + 24)
+#define T3166 (DWORD)(GMAC_EVENT_BASE + 25)
+#define T3168_MAC (DWORD)(GMAC_EVENT_BASE + 26)
+#define T3170 (DWORD)(GMAC_EVENT_BASE + 27)
+#define T3174 (DWORD)(GMAC_EVENT_BASE + 28)
+#define T3176 (DWORD)(GMAC_EVENT_BASE + 29)
+#define T3180 (DWORD)(GMAC_EVENT_BASE + 30)
+#define T3184 (DWORD)(GMAC_EVENT_BASE + 31)
+#define T3186 (DWORD)(GMAC_EVENT_BASE + 32)
+#define T3190 (DWORD)(GMAC_EVENT_BASE + 33)
+#define T3192 (DWORD)(GMAC_EVENT_BASE + 34)
+#define T_SINGLE_DL_BLOCK (DWORD)(GMAC_EVENT_BASE + 35)
+#define XPOLLING_RESPONSE (DWORD)(GMAC_EVENT_BASE + 36)
+#define XBLOCK_DL_RELEASE (DWORD)(GMAC_EVENT_BASE + 37)
+#define XBLOCK_UL_RELEASE (DWORD)(GMAC_EVENT_BASE + 38)
+#define GRR_MAC_T3218_EXP_EV (DWORD)(GMAC_EVENT_BASE + 39)
+#define GRR_MAC_PSHO_REQ_EV (DWORD)(GMAC_EVENT_BASE + 40)
+#define GRR_MAC_PSHO_RETURN_REQ_EV (DWORD)(GMAC_EVENT_BASE + 41)
+#define GRR_MAC_PSHO_DEACT_REQ_EV (DWORD)(GMAC_EVENT_BASE + 42)
+#define GMAC_T3216_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 43)
+#define GMAC_T_MULTI_DL_BLOCK_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 44)
+#define GMAC_T3200_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 45)
+
+ /* END OF MAC */
+
+ /* START OF RLC */
+#define RLC_WAKE_UP (DWORD)(GRLC_EVENT_BASE + 0)
+#define RLC_FILL_DATA_QUEUE (DWORD)(GRLC_EVENT_BASE + 1)
+#define RLC_START_TIMER_T3182 (DWORD)(GRLC_EVENT_BASE + 2)
+#define RLC_START_TIMER_T3168 (DWORD)(GRLC_EVENT_BASE + 3)
+#define RLC_FILL_GPRS_TEST_MODE (DWORD)(GRLC_EVENT_BASE + 4)
+#define RLC_UNEXPECTED_INPUT_RECEIVED (DWORD)(GRLC_EVENT_BASE + 5)
+#define RLC_UPL_DEBUG (DWORD)(GRLC_EVENT_BASE + 6)
+#define OM_RLC_TEST_MODE_REQ (DWORD)(GRLC_EVENT_BASE + 7)
+#define GRR_RLC_SUSPEND_REQ (DWORD)(GRLC_EVENT_BASE + 8)
+#define GRR_RLC_RESUME_REQ (DWORD)(GRLC_EVENT_BASE + 9)
+#define GRR_RLC_UPDATE_PARAM_REQ (DWORD)(GRLC_EVENT_BASE + 10)
+#define GRR_RLC_ACCESS_CNF (DWORD)(GRLC_EVENT_BASE + 11)
+#define GRR_RLC_ACCESS_REJ (DWORD)(GRLC_EVENT_BASE + 12)
+#define GRR_RLC_REL_PDCH_REQ (DWORD)(GRLC_EVENT_BASE + 13)
+#define GRR_RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 14)
+#define GRR_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 15)
+#define GRR_RLC_TBF_FAILURE (DWORD)(GRLC_EVENT_BASE + 16)
+#define GRR_RLC_TESTPARAM_REQ (DWORD)(GRLC_EVENT_BASE + 17)
+#define RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 18)
+#define RLC_UNITDATA_REQ (DWORD)(GRLC_EVENT_BASE + 19)
+#define RLC_CLEAR_QUEUE_REQ (DWORD)(GRLC_EVENT_BASE + 20)
+#define LL_RLC_RESUME_MM_REQ (DWORD)(GRLC_EVENT_BASE + 21)
+#define LL_RLC_RESUME_ALL_REQ (DWORD)(GRLC_EVENT_BASE + 22)
+#define RLC_ASSIGN_REQ (DWORD)(GRLC_EVENT_BASE + 23)
+#define RLC_RESET_REQ (DWORD)(GRLC_EVENT_BASE + 24)
+#define MAC_RLC_UPLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 25)
+#define MAC_RLC_UPLINK_PDCH_FAIL (DWORD)(GRLC_EVENT_BASE + 26)
+#define MAC_RLC_REL_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 27)
+#define MAC_RLC_UPLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 28)
+#define MAC_RLC_UPLINK_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 29)
+#define MAC_RLC_DOWNLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 30)
+#define MAC_RLC_DATA_IND (DWORD)(GRLC_EVENT_BASE + 31)
+#define MAC_RLC_UPLINK_DATA_IND (DWORD)(GRLC_EVENT_BASE + 32)
+#define MAC_RLC_ERROR_IND (DWORD)(GRLC_EVENT_BASE + 33)
+#define MAC_RLC_DEACT_REQ (DWORD)(GRLC_EVENT_BASE + 34)
+#define MAC_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 35)
+#define MAC_RLC_TLLI_IND (DWORD)(GRLC_EVENT_BASE + 36)
+#define MAC_RLC_DOWNLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 37)
+#define UPL_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 38)
+#define PTBF_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 39)
+#define T3168 (DWORD)(GRLC_EVENT_BASE + 40)
+#define T3182 (DWORD)(GRLC_EVENT_BASE + 41)
+#define RLC_ENG_MODE_TIMER (DWORD)(GRLC_EVENT_BASE + 42)
+#define GRR_RLC_PSHO_REQ_EV (DWORD)(GRLC_EVENT_BASE + 43)
+#define GRR_RLC_PSHO_SUCC_EV (DWORD)(GRLC_EVENT_BASE + 44)
+#define GRR_RLC_PSHO_FAIL_EV (DWORD)(GRLC_EVENT_BASE + 45)
+
+ /* END OF RLC */
+
+ /* START OF SNP */
+#define SN_DL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 0)
+#define SN_UL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 1)
+#define SN_NPDU_DEL_REQ (DWORD)(SNDCP_EVENT_BASE + 2)
+#define SN_NPDU_AVAIL_REQ (DWORD)(SNDCP_EVENT_BASE + 3)
+#define SN_DATA_REQ (DWORD)(SNDCP_EVENT_BASE + 4)
+#define SN_UNITDATA_REQ (DWORD)(SNDCP_EVENT_BASE + 5)
+#define SN_IR_UL_SUSPEND_RSP (DWORD)(SNDCP_EVENT_BASE + 6)
+#define SN_XID_REQ (DWORD)(SNDCP_EVENT_BASE + 7)
+#define SNSM_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 8)
+#define SNSM_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 9)
+#define SNSM_ASSIGN_IND (DWORD)(SNDCP_EVENT_BASE + 10)
+#define SNSM_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 11)
+#define SNSM_MODIFY_IND (DWORD)(SNDCP_EVENT_BASE + 12)
+#define SNSM_IR_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 13)
+#define SNSM_IR_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 14)
+#define SNSM_IR_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 15)
+#define SNPDU_AVAIL_IND (DWORD)(SNDCP_EVENT_BASE + 16)
+#define SNPDU_DEL_CNF (DWORD)(SNDCP_EVENT_BASE + 17)
+#define SNPDU_DEL_IND (DWORD)(SNDCP_EVENT_BASE + 18)
+#define LL_ESTABLISH_CNF (DWORD)(SNDCP_EVENT_BASE + 19)
+#define LL_ESTABLISH_IND (DWORD)(SNDCP_EVENT_BASE + 20)
+#define LL_RELEASE_CNF (DWORD)(SNDCP_EVENT_BASE + 21)
+#define LL_RELEASE_IND (DWORD)(SNDCP_EVENT_BASE + 22)
+#define LL_STATUS_IND (DWORD)(SNDCP_EVENT_BASE + 23)
+#define LL_RESET_IND (DWORD)(SNDCP_EVENT_BASE + 24)
+#define LL_RESET_PSHO_IND (DWORD)(SNDCP_EVENT_BASE + 25)
+#define LL_DATA_CNF (DWORD)(SNDCP_EVENT_BASE + 26)
+#define LL_XID_CNF (DWORD)(SNDCP_EVENT_BASE + 27)
+#define LL_XID_IND (DWORD)(SNDCP_EVENT_BASE + 28)
+#define LL_DATA_IND (DWORD)(SNDCP_EVENT_BASE + 29)
+#define LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 30)
+#define TIME_REEST (DWORD)(SNDCP_EVENT_BASE + 31)
+#define TIME_LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 32)
+#define TIME_UACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 33)
+#define TIME_ACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 34)
+ /* END OF SNP */
+
+ /* START OF GSMA */
+#define LLSMS_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 0)
+#define SN_NPDU_DEL_IND (DWORD)(GSMA_EVENT_BASE + 1)
+#define SN_NPDU_AVAIL_IND (DWORD)(GSMA_EVENT_BASE + 2)
+#define SN_DATA_IND (DWORD)(GSMA_EVENT_BASE + 3)
+#define SN_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 4)
+#define SN_IR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 5)
+#define SN_IR_TO_UMTS_IND (DWORD)(GSMA_EVENT_BASE + 6)
+#define RR_TESTPARAM_IND (DWORD)(GSMA_EVENT_BASE + 7)
+#define RR_ABORT_IND (DWORD)(GSMA_EVENT_BASE + 8)
+#define RR_ACT_CNF (DWORD)(GSMA_EVENT_BASE + 9)
+#define RR_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 10)
+#define RR_ACT_FAIL (DWORD)(GSMA_EVENT_BASE + 11)
+#define RR_CELL_PARAMETER_IND (DWORD)(GSMA_EVENT_BASE + 12)
+#define RR_ACT_IND (DWORD)(GSMA_EVENT_BASE + 13)
+#define RR_DEACT_CNF (DWORD)(GSMA_EVENT_BASE + 14)
+#define RR_PLMN_CNF (DWORD)(GSMA_EVENT_BASE + 15)
+#define RR_PLMN_REJ (DWORD)(GSMA_EVENT_BASE + 16)
+#define RR_PLMN_IND (DWORD)(GSMA_EVENT_BASE + 17)
+#define RR_PLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 18)
+#define RR_REL_IND (DWORD)(GSMA_EVENT_BASE + 19)
+#define RR_TBF_EST_IND (DWORD)(GSMA_EVENT_BASE + 20)
+#define RR_TBF_REL_IND (DWORD)(GSMA_EVENT_BASE + 21)
+#define RR_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 22)
+#define RR_HPLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 23)
+#define RR_HPLMN_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 24)
+#define RR_EST_CNF (DWORD)(GSMA_EVENT_BASE + 25)
+#define RR_EST_IND (DWORD)(GSMA_EVENT_BASE + 26)
+#define RR_CELL_IND (DWORD)(GSMA_EVENT_BASE + 27)
+#define RR_DATA_IND (DWORD)(GSMA_EVENT_BASE + 28)
+#define RR_SYNC_IND (DWORD)(GSMA_EVENT_BASE + 29)
+#define GMMRR_PAGE_IND (DWORD)(GSMA_EVENT_BASE + 30)
+#define GMMRR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 31)
+#define GMMRR_CELL_UPDATE_IND (DWORD)(GSMA_EVENT_BASE + 32)
+#define RR_DATA_REJ (DWORD)(GSMA_EVENT_BASE + 33)
+#define RR_EST_REJ (DWORD)(GSMA_EVENT_BASE + 34)
+#define RR_HO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 35)
+#define RR_HO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 36)
+#define RR_HO_START_IND (DWORD)(GSMA_EVENT_BASE + 37)
+#define RR_IRAT_RESEL_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 38)
+#define RR_IRAT_RESEL_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 39)
+#define RR_IRAT_RESEL_START_IND (DWORD)(GSMA_EVENT_BASE + 40)
+#define RR_CCO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 41)
+#define RR_CCO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 42)
+#define RR_CCO_START_IND (DWORD)(GSMA_EVENT_BASE + 43)
+#define RR_RAT_CHN_IND (DWORD)(GSMA_EVENT_BASE + 44)
+#define RR_TEST_COUNT_CNF (DWORD)(GSMA_EVENT_BASE + 45)
+#define LLGMM_STATUS_IND (DWORD)(GSMA_EVENT_BASE + 46)
+#define LLGMM_TRIGGER_IND (DWORD)(GSMA_EVENT_BASE + 47)
+#define LLGMM_USER_DATA_PRESENT (DWORD)(GSMA_EVENT_BASE + 48)
+#define LLGMM_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 49)
+#define RR_START_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 50)
+#define RR_END_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 51)
+#define RR_ADD_CELL_RESEL_INFO_IND (DWORD)(GSMA_EVENT_BASE + 52)
+#define RLC_BLOCK_INFO_IND (DWORD)(GSMA_EVENT_BASE + 53)
+#define RRMN_MEAS_RESULTS_CNF (DWORD)(GSMA_EVENT_BASE + 54)
+#define MNRR_CIPHERING_IND (DWORD)(GSMA_EVENT_BASE + 55)
+#define SN_XID_CNF (DWORD)(GSMA_EVENT_BASE + 56)
+#define RR_RRL_DATA_IND (DWORD)(GSMA_EVENT_BASE + 57)
+#define RR_RRL_ABORT_EVENT_IND (DWORD)(GSMA_EVENT_BASE + 58)
+#define RR_RRL_CLASSMARK_IND (DWORD)(GSMA_EVENT_BASE + 59)
+#define SNSM_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 60)
+#define SNSM_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 61)
+#define SNSM_MODIFY_RSP (DWORD)(GSMA_EVENT_BASE + 62)
+#define SNSM_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 63)
+#define SNSM_STATUS_REQ (DWORD)(GSMA_EVENT_BASE + 64)
+#define SNSM_IR_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 65)
+#define SNSM_IR_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 66)
+#define SNSM_IR_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 67)
+#define URRC_RESEL_REQ (DWORD)(GSMA_EVENT_BASE + 68)
+#define URRC_SET_INACTIVE_REQ (DWORD)(GSMA_EVENT_BASE + 69)
+#define RR_SET_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 70)
+#define URRC_READ_PREDEF_CONF_REQ (DWORD)(GSMA_EVENT_BASE + 71)/*WCDMAÏÂʹÓÃ*/
+#define URRC_ABORT_READ_PREDEF_REQ (DWORD)(GSMA_EVENT_BASE + 72)/*WCDMAÏÂʹÓÃ*/
+#define URRC_L1_RSRC_REQ (DWORD)(GSMA_EVENT_BASE + 73)
+#define URRC_L1_RSRC_FREE_IND (DWORD)(GSMA_EVENT_BASE + 74)
+#define RR_L1_RSRC_CNF (DWORD)(GSMA_EVENT_BASE + 75)
+#define RR_L1_RSRC_REJ (DWORD)(GSMA_EVENT_BASE + 76)
+#define RR_CELL_SEARCH_CNF (DWORD)(GSMA_EVENT_BASE + 77)
+#define RR_CELL_SEARCH_REJ (DWORD)(GSMA_EVENT_BASE + 78)
+#define URRC_CELL_SEARCH_REQ (DWORD)(GSMA_EVENT_BASE + 79)
+#define URRC_HO_INFO_REQ (DWORD)(GSMA_EVENT_BASE + 80)
+#define URRC_HO_REQ (DWORD)(GSMA_EVENT_BASE + 81)
+#define URRC_VSD_INFO (DWORD)(GSMA_EVENT_BASE + 82)
+#define RR_HO_CNF (DWORD)(GSMA_EVENT_BASE + 83)
+#define RR_HO_REJ (DWORD)(GSMA_EVENT_BASE + 84)
+#define URRC_CELL_CHANGE_REQ (DWORD)(GSMA_EVENT_BASE + 85)
+#define RR_CELL_CHANGE_CNF (DWORD)(GSMA_EVENT_BASE + 86)
+#define RR_CELL_CHANGE_REJ (DWORD)(GSMA_EVENT_BASE + 87)
+#define RR_RESEL_CNF (DWORD)(GSMA_EVENT_BASE + 88)
+#define RR_RESEL_REJ (DWORD)(GSMA_EVENT_BASE + 89)
+
+#define ERRC_RESEL_REQ_EV (DWORD)(GSMA_EVENT_BASE + 90)
+#define ERRC_CELL_SEARCH_REQ_EV (DWORD)(GSMA_EVENT_BASE + 91)
+#define RR_IRAT_PSHO_START_IND_EV (DWORD)(GSMA_EVENT_BASE + 92)
+#define RR_IRAT_PSHO_COMPLETE_IND_EV (DWORD)(GSMA_EVENT_BASE + 93)
+#define RR_IRAT_PSHO_FAIL_IND_EV (DWORD)(GSMA_EVENT_BASE + 94)
+#define URRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 95)
+#define ERRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 96)
+#define RR_PSHO_CNF_EV (DWORD)(GSMA_EVENT_BASE + 97)
+#define RR_PSHO_REJ_EV (DWORD)(GSMA_EVENT_BASE + 98)
+#define ERRC_CELL_CHANGE_REQ_EV (DWORD)(GSMA_EVENT_BASE + 99)
+#define RR_ETWS_DATA_IND_EV (DWORD)(GSMA_EVENT_BASE + 100)
+#define LLGMM_PSHO_IND_EV (DWORD)(GSMA_EVENT_BASE + 101)
+#define RLC_SM_CURR_BEAR_IND_EV (DWORD)(GSMA_EVENT_BASE + 102)
+#define RR_SENDCMP_IND_EV (DWORD)(GSMA_EVENT_BASE + 103)
+#define RR_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 104)
+#define RR_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 105)
+#define RR_ABORT_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 106)
+#define RR_ABORT_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 107)
+#define RR_XCELLINFO_CNF (DWORD)(GSMA_EVENT_BASE + 108)
+#define RR_XCELLINFO_REJ (DWORD)(GSMA_EVENT_BASE + 109)
+#define RR_XCELLINFO_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 110)
+
+
+ /* START OF LLC */
+#define LLC_START_TIMER_T200 (DWORD)(GLLC_EVENT_BASE + 0)
+#define LLC_START_TIMER_T201 (DWORD)(GLLC_EVENT_BASE + 1)
+#define LLSMS_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 2)
+#define LLGMM_ASSIGN_REQ (DWORD)(GLLC_EVENT_BASE + 3)
+#define LLGMM_RESUME_REQ (DWORD)(GLLC_EVENT_BASE + 4)
+#define LLGMM_SUSPEND_REQ (DWORD)(GLLC_EVENT_BASE + 5)
+#define LLGMM_TRIGGER_REQ (DWORD)(GLLC_EVENT_BASE + 6)
+#define LLGMM_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 7)
+#define LLGMM_CELL_NOTIFICATION_REQ (DWORD)(GLLC_EVENT_BASE + 8)
+#define SNPDU_AVAIL_REQ (DWORD)(GLLC_EVENT_BASE + 9)
+#define SNPDU_DEL_REQ (DWORD)(GLLC_EVENT_BASE + 10)
+#define SNPDU_DEL_RSP (DWORD)(GLLC_EVENT_BASE + 11)
+#define LL_CONFIG_REQ (DWORD)(GLLC_EVENT_BASE + 12)
+#define LL_ESTABLISH_REQ (DWORD)(GLLC_EVENT_BASE + 13)
+#define LL_ESTABLISH_RSP (DWORD)(GLLC_EVENT_BASE + 14)
+#define LL_RELEASE_REQ (DWORD)(GLLC_EVENT_BASE + 15)
+#define LL_DATA_REQ (DWORD)(GLLC_EVENT_BASE + 16)
+#define LL_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 17)
+#define LL_XID_REQ (DWORD)(GLLC_EVENT_BASE + 18)
+#define LL_XID_RSP (DWORD)(GLLC_EVENT_BASE + 19)
+#define GRR_LLC_PSHO_SUCCESS_IND (DWORD)(GLLC_EVENT_BASE + 20)
+#define RRC_LLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 21)
+#define RLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND (DWORD)(GLLC_EVENT_BASE + 23)
+#define RLC_DATA_CNF (DWORD)(GLLC_EVENT_BASE + 24)
+#define RLC_UNITDATA_CNF (DWORD)(GLLC_EVENT_BASE + 25)
+#define RLC_CLEAR_QUEUE_CNF (DWORD)(GLLC_EVENT_BASE + 26)
+#define RLC_CLEAR_QUEUE_IND (DWORD)(GLLC_EVENT_BASE + 27)
+#define RLC_DATA_BUFF_IND (DWORD)(GLLC_EVENT_BASE + 28)
+#define LLC_T200 (DWORD)(GLLC_EVENT_BASE + 29)
+#define T201 (DWORD)(GLLC_EVENT_BASE + 30)
+#define LLC_T100_EV (DWORD)(GLLC_EVENT_BASE + 31)
+ /* END OF LLC */
+
+/* ========================================================================
+ MM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MM_T3210_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 0)
+#define MM_T3211_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 1)
+#define MM_T3212_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 2)
+#define MM_T3213_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 3)
+#define MM_T3214_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 4)
+#define MM_T3216_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 5)
+#define MM_T3218_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 6)
+#define MM_T3220_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 7)
+#define MM_T3221_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 8)
+#define MM_T3230_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 9)
+#define MM_T3240_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 10)
+#define MM_T3241_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 11)
+#define MM_T3225_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 12)
+#define MM_T3222_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 13)
+#define MM_T3231_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 14)
+#define MM_T3232_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 15)
+#define MM_TWRRR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 16)
+#define MM_TWPGR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 17)
+#define MM_TCCSRV_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 18)
+
+/* ========================================================================
+ GMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_T_READY_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 0)
+#define GMM_T3310_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 1)
+#define GMM_T3330_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 2)
+#define GMM_T3317_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 3)
+#define GMM_T3321_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 4)
+#define GMM_T3316_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 5)
+#define GMM_T3318_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 6)
+#define GMM_T3320_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 7)
+#define GMM_T_WRRC_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 8)
+#define GMM_T_WRRR_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 9)
+#define GMM_T_POWER_OFF_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 10)
+#define GMM_T_WSPN_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 11)
+#define GMM_T_WCRS_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 12)
+#define GMM_T_WTRG_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 13)
+#define GMM_T_PAGE_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 14)
+#define GMM_T3319_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 15)
+#define GMM_T_WREL_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 16)/*EC614000821119*/
+/* ========================================================================
+ UMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_T3212_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 0)
+#define UMM_T3311_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 1)
+#define UMM_T3302_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 2)
+#define UMM_T3312_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 3)
+#define UMM_T_NOCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 4)
+#define UMM_T_LIMIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 5)
+#define UMM_T_DELLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 6)
+#define UMM_T_SHHPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 7)
+#define UMM_T_UICCINIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 8) /* ¼àÊÓ¿¨³õʼ»¯¶¨Ê±Æ÷ */
+#define UMM_T_CAMPON_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 9) /* ¼àÊÓפÁô¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_DETACH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 10) /* ¼àÊӹػúÈ¥»î¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_LIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 11) /* ÖØÊÔPLMNÁÐ±í¶¨Ê±Æ÷ */
+#define UMM_T_PLMNLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 12) /* Áбí¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T3411_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 13)
+#define UMM_T3402_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 14)
+#define UMM_T3412_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 15)
+#define UMM_T3442_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 16)
+#define UMM_T_PROC_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 17)
+#define UMM_T_FOCSGLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 18)
+#define UMM_T3323_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 19)
+#define UMM_T3423_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 20)
+#define UMM_TBGSEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 21) /*LTE±³¾°ËÑË÷ÖÜÆÚ¶¨Ê±Æ÷*/
+#define UMM_T_IMSREG_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 22)
+#define UMM_T_NORMALFAILPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 23)
+#define UMM_T_ENABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 24)
+#define UMM_T_DISABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 25)
+#define UMM_T_LOOPTIME_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 26)
+#define UMM_T_DISFRESEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 27)
+#define UMM_T_RESETCAUSEPAR_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 28)
+#define UMM_T_SWITCHCARD_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 29)
+#define UMM_T_ARREARS_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 30)
+#define UMM_TSEARCHECALLCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 31)
+#define UMM_TECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 32)
+#define UMM_TTESTECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 33)
+#define UMM_T_IMSREL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 34)
+/* ========================================================================
+ CC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_T303_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 0)
+#define CC_T305_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 1)
+#define CC_T308_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 2)
+#define CC_T310_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 3)
+#define CC_T313_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 4)
+#define CC_T335_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 5) /*CCBS*/
+#define CC_T332_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 6)
+#define CC_T323_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 7)
+#define CC_T336_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 8)
+#define CC_T337_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 9)
+
+/* ADD A TIMER FOR CALL CONFIRM MESSAGE */
+#define CC_T_CALLCNF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 10)
+
+/* ADD TIMER FOR AOC */
+#define CC_T_ACMUPD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 11)
+#define CC_T_CDUR_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 12)
+
+#define CC_T_HOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 13)
+#define CC_T_RETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 14)
+
+#define CC_T_MPTYBUILD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 15)
+#define CC_T_MPTYHOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 16)
+#define CC_T_MPTYRETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 17)
+#define CC_T_MPTYSPLIT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 18)
+
+#define CC_T322_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 19)
+#define CC_T_SUPPER_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 20)
+#define CC_T_MMCONN_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 21)
+
+#define CC_T_RELTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 22)
+#define CC_T_CONNTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 23)
+#define CC_T_SYNCIND_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 24)
+#define CC_T_MODIFYBC_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 25)
+#define CC_T_DTMFDURA_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 26)
+#define CC_T_MMCONNRETRY_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 27)
+#define CC_T_ALLOWEDCALL_TIME_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 28)
+#define CC_T_ECT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 29)
+#define CC_T_T2_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 30)
+#define CC_T_T5_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 31)
+#define CC_T_T6_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 32)
+#define CC_T_T7_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 33)
+#define CC_T_TIDLE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 34)
+#define CC_T_T9_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 35)
+
+/* ========================================================================
+ SMS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SMS_TR1M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 0) /* FOR MO SM.*/
+#define SMS_TRAM_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 1) /* FOR MO SM.*/
+#define SMS_TC1M_MO_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 2) /* FOR MO SM.*/
+#define SMS_TMMS_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 3) /* FOR MO SM.*/
+#define SMS_TR2M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 4) /* FOR MT SM.*/
+#define SMS_TC1M_MT_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 5) /* FOR MT SM.*/
+/* ========================================================================
+ SS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SS_T_WAIT_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 0)
+#define SS_T_MOLRTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 1)
+#define SS_T_MOLRINTERTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 2)
+#ifdef _USE_SIG_TRACE
+#define SS_DL_L3FACILITY_EV (DWORD)(SS_TIMER_EVENT_BASE + 3)
+#define SS_DL_L3MTREG_EV (DWORD)(SS_TIMER_EVENT_BASE + 4)
+#define SS_DL_L3RELCOMP_EV (DWORD)(SS_TIMER_EVENT_BASE + 5)
+#endif
+
+
+/* ========================================================================
+ SM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_T3380_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 0)
+#define SM_T3381_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 1)
+#define SM_T3390_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 2)
+#define SM_T_CMEST_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 3)
+#define SM_T_PDPHANDLE_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 4)
+#define SM_T_APPANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 5)
+#define SM_T_AUTOANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS¶¨Ê±Æ÷ ÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_T_SCHEDCHECK_EXPIRY_EV (DWORD)(CBS_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ UICC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UICC_CARD_DETECT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 0)
+#define UICC_CARD_USAT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ URRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define USIR_T_BCH_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 0)
+#define USIR_T_SIB7_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 1)
+#define USIR_T_VTSIB_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 2)
+#define USIR_T_R_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 3)
+#define USIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 4)
+#define UCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 5)
+#define UCSR_T_HYSTX_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 6)
+#define UCSR_T_PROTECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 7)
+#define UCSR_T_NCELL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 8)
+#define UCSR_T_OOS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 9)
+#define UCSR_T_CAMP1S_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define UCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 11)
+#define UCSR_T_REDIRECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 12)
+#define UMCR_T_RESELECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 13)
+#define UMCR_T_PERIOD_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 14)
+#define UMCR_T_TRIGGER_EV (DWORD)(URRC_TIMER_EVENT_BASE + 15)
+#define UMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 16)
+#define UCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 17)
+#define UCER_T_ETWS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 18)
+#define UCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 19)
+#define URRC_T300_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 20)
+#define URRC_T302_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 21)
+#define URRC_T304_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 22)
+#define URRC_T305_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 23)
+#define URRC_T307_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 24)
+#define URRC_T308_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 25)
+#define URRC_T309_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 26)
+#define URRC_T312_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 27)
+#define URRC_T313_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 28)
+#define URRC_T314_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 29)
+#define URRC_T315_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 30)
+#define URRC_T316_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 31)
+#define URRC_T319_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 32)
+#define URRC_T320_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 33)
+#define UMCR_T322_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 34)
+#define URRC_T323_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 35)
+#define URRC_T325_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 36)
+#define URRC_T_WAIT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 37)
+#define UCSR_T_LBS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 38)
+
+/* ========================================================================
+ UPDCP¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDCP_T_RABREEST_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 0)
+#define PDCP_T_SNSYNC_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 1)
+#define PDCP_T_DATAMONITOR_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ URLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define URLC_T_DISCARD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 0)
+#define URLC_T_POLL_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 1)
+#define URLC_T_POLLPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 2)
+#define URLC_T_POLLPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 3)
+#define URLC_T_STATUSPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 4)
+#define URLC_T_STATUSPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 5)
+#define URLC_T_RESET_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 6)
+#define URLC_T_MRW_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ UMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define UMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 0)
+#define UMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 1)
+#define UMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 2)
+#define UMAC_T_RACHPROC_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 3)
+#define UMAC_T_HSTIMER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 4)
+#define UMAC_T_RESET_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 5)
+
+
+/* ========================================================================
+ L1T¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define L1T_T_BSIC_EXPIRY_EV (DWORD)(L1T_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ TAF¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define TAF_T_PROC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 0)
+#define TAF_T_DISC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 1)
+#define TAF_T_RA_TSYNC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 2)
+#define TAF_T_RA_TSYNCEND_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 3)
+#define TAF_T_RA_TSBFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 4)
+#define TAF_T_RA_TXFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 5)
+#define TAF_T_RLP_TRCVR_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 6)
+#define TAF_T_RLP_TRCVS_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 7)
+#define TAF_T_RLP_TTEST_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 8)
+#define TAF_T_RLP_TXID_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 9)
+#define TAF_T_RLP_T_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ GSMA¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ ROHCv1¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 0)
+#define ROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 1)
+#define ENROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 2)
+#define ENROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 3)
+#define ROHCv1_T_NACK_FDBK_CNT_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ ROHCv2¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 0)
+#define ENROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ PDI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDI_T_SWITCHLED_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 0)
+#define PDI_T_WAITDNSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 1)
+#define PDI_T_WAITZSSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 2)
+#define PDI_T_WAIT_BUF_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 3)
+#define PDI_LOOPB_TIMER_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 4)
+
+/* ========================================================================
+ SCI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define SCI_T_VOICE_FRAME_EXPIRY_EV (DWORD)(SCI_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ STM¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define STM_MEMAVAILD_EXPIRY_EV (DWORD)(STM_TIMER_EVENT_BASE + 0)
+
+/*========================================================================
+USAT¶¨Ê±Æ÷¶¨Òå
+========================================================================*/
+#define USAT_TIMERMNG_TIMER1_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 0)
+#define USAT_TIMERMNG_TIMER2_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 1)
+#define USAT_TIMERMNG_TIMER3_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 2)
+#define USAT_TIMERMNG_TIMER4_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 3)
+#define USAT_TIMERMNG_TIMER5_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 4)
+#define USAT_TIMERMNG_TIMER6_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 5)
+#define USAT_TIMERMNG_TIMER7_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 6)
+#define USAT_TIMERMNG_TIMER8_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ È«¾ÖÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define FOR_TEST_TEMP_EV (DWORD)(PRI_TEST_EVENT_BASE + 0)
+#define TEST_SET_UICC_RLT_EV (DWORD)(PRI_TEST_EVENT_BASE + 1)
+#define TEST_SET_UICC_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 2)
+#define TEST_SET_NV_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 3)
+#define TEST_SET_NV_DATA_IMEI_EV (DWORD)(PRI_TEST_EVENT_BASE + 4)
+#define TEST_SET_NV_DATA_SPCLFUNC_EV (DWORD)(PRI_TEST_EVENT_BASE + 5)
+#define TEST_SET_COMP_IND_EV (DWORD)(PRI_TEST_EVENT_BASE + 6)
+/* ========================================================================
+ Ä£ÄâTAFÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_TAFDATAIND_UTRAN_EV (DWORD)(TAF_TEST_EVENT_BASE + 0)
+
+/* ========================================================================
+ USIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_BIGSIB_IND_EV (DWORD)(USIR_TEST_EVENT_BASE + 0)
+#define TEST_USIR_DECSIB_EV (DWORD)(USIR_TEST_EVENT_BASE + 1)
+
+/* ========================================================================
+ NURLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UURLC_DATA_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 0)
+#define TEST_UURLC_DATA_IND_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 1)
+#define TEST_CURLC_CONFIG_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 2)
+#define TEST_URLC_ACK_CTRL_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NPDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 1)
+#define NPDCP_DATA_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 2)
+#define NPDCP_DATA_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 3)
+#define TEST_NPDCP_DATA_ERR_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 4)
+#define TEST_NPDCP_DATA_CNF_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 5)
+
+/* ========================================================================
+ NUMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UMAC_ACK_CTRL_UTRAN_EV (DWORD)(NUMAC_EVENT_BASE + 0)
+#define TEST_UMAC_HSUPA_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 1)
+#define TEST_UMAC_HSUPA_CFG_EV (DWORD)(NUMAC_EVENT_BASE + 2)
+#define TEST_UMAC_HSUPA_SIINFO_EV (DWORD)(NUMAC_EVENT_BASE + 3)
+#define TEST_UMAC_HSUPA_HEADER_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 4)
+#define TEST_UMAC_NOTIFY_DATA_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 5)
+#define TEST_UMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 6)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UCBS_SCHED_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 0)
+#define TEST_UCBS_DATA_REQ_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 1)
+#define TEST_UCBS_OUTPUT_END_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 2)
+#define TEST_UCBS_UMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 3)
+#define TEST_UCBS_UMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 4)
+#define TEST_UURLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 5)
+/*WCDMA NCBS_EVENT_BASE=20 */
+#define TEST_UWRLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 6)
+#define TEST_UCBS_WMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 7)
+#define TEST_UCBS_WMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 8)
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TC_ACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 0)
+#define TC_ACTIVE_TEST_CNF_EV (DWORD)(TC_EVENT_BASE + 1)
+#define TC_DEACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 2)
+#define TC_CLOSE_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 3)
+#define TC_CLOSE_LOOP_CNF_EV (DWORD)(TC_EVENT_BASE + 4)
+#define TC_CLOSE_LOOP_REQ_URLC_EV (DWORD)(TC_EVENT_BASE + 5)
+#define TC_OPEN_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 6)
+/*wcdma TC_EVENT_BASE=30*/
+#define TC_CLOSE_LOOP_REQ_WRLC_EV (DWORD)(TC_EVENT_BASE + 7)
+//lte TC_EVERNT
+#define EMM_TC_TEST_CONTROL_REQ_EV (DWORD)(TC_EVENT_BASE + 8)
+#define TC_EMM_TEST_CONTROL_CNF_EV (DWORD)(TC_EVENT_BASE + 9)
+#define TC_PDI_OPEN_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 10)
+#define TC_PDI_CLOSE_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 11)
+/* ========================================================================
+ L1SIMUÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1SIMU_START_EV (DWORD)(L1SIMU_EVENT_BASE + 0) /*Æô¶¯L1_SIMUÄ£¿é*/
+#define L1SIMU_NGMAC_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 1) /*L1_SIMU·¢ËÍÊý¾Ýµ½MAC_N*/
+#define L1SIMU_DLLN_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 2) /*L1_SIMU·¢ËÍÊý¾Ýµ½LAPDM*/
+#define TOOL_L1SIMU_CELL_MEAS_INFO_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 3) /*¹¤¾ß·¢ËÍFCBSBÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_SYSINFO_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 4) /*¹¤¾ß·¢ËÍϵͳÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_PAGING_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 5) /*¹¤¾ß·¢ËÍÑ°ºôÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_DCCH_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 6)
+#define TOOL_L1SIMU_DCCH_REL_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 7)
+#define L1SIMU_DLLN_CONNECT_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 8)
+#define L1SIMU_FRAME_INT_EV (DWORD)(L1SIMU_EVENT_BASE + 9)
+#define TOOL_L1SIMU_SYNC_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 10)
+#define TOOL_L1SIMU_SYSINFO_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 11)
+#define L1SIMU_DLLN_DATA_SENT_CMP_EV (DWORD)(L1SIMU_EVENT_BASE + 12) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define TOOL_L1SIMU_DCCH_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 13) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define TOOL_L1SIMU_SYSINFO_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 14)
+#define L1SIMU_TOOL_RXLEV_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 15)
+#define L1SIMU_TOOL_SYNCREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 16)
+#define L1SIMU_TOOL_SYSREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 17)
+#define L1SIMU_TOOL_IDLE_MODE_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 18)
+#define L1SIMU_TOOL_NCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 19) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define L1SIMU_TOOL_SCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 20) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define L1SIMU_TOOL_MEAS_REPORT_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 21)
+#define L1SIMU_TOOL_DL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 22)
+#define L1SIMU_TOOL_UL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 23)
+#define L1SIMU_TOOL_TAF_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 24)
+#define L1SIMU_TOOL_TAF_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 25)
+#define L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 26)
+#define L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 27)
+#define TOOL_L1SIMU_CBS_BLK_START_EV (DWORD)(L1SIMU_EVENT_BASE + 28)
+#define TOOL_L1SIMU_CBS_FST_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 29)
+#define TOOL_L1SIMU_CBS_OTHER_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 30)
+#define L1SIMU_TOOL_PSHOREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 31)
+#define L1SIMU_TOOL_DEACTIATE_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 32)
+#define TOOL_L1SIMU_ABNORMAL_TA_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 33)
+#define L1SIMU_TOOL_L1G_L1E_GSM_INACT_TIME_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 34)
+#define L1SIMU_TOOL_L1G_L1E_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 35)
+#define L1SIMU_TOOL_L1G_L1E_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 36)
+#define L1SIMU_TOOL_CHANNEL_ASSIGN_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 37)
+#define L1SIMU_TOOL_CHANNEL_TYPE_INFO_EV (DWORD)(L1SIMU_EVENT_BASE + 38)
+
+/* ========================================================================
+ NLAPDMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLAPDM_UNIT_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 0) /*¹¤¾ßÏòLADPN·¢ËÍ·ÇÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_UNIT_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 1) /*LADPNÏò¹¤¾ßÉÏ´«·ÇÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 2) /*¹¤¾ßÏòLADPN·¢ËÍÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 3) /*LADPNÏò¹¤¾ßÉÏ´«È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_ESTABLISH_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 4) /*¹¤¾ßÏòLADPN·¢Ëͽ¨Á´ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 5) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 6) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´È·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_SUSPEND_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 7) /*LADPNÏò¹¤¾ß·¢Ë͹ÒÆðÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_RECONNECT_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 8) /*¹¤¾ßÏòLADPN·¢ËÍÖØÁ¬ÇëÇóÏûÏ¢*/
+#define TOOL_NLAPDM_RELEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 9) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 10) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 11) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_MDL_CONFIG_EV (DWORD)(NLAPDM_EVENT_BASE + 12) /*¹¤¾ßÏòLADPN·¢ËͳõʼÅäÖÃÏûÏ¢*/
+#define NLAPDM_TOOL_MDL_ERROR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 13) /*LADPNÏò¹¤¾ß·¢ËÍ´íÎ󱨸æ*/
+#define TOOL_NLAPDM_MDL_REALEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 14) /*¹¤¾ß·¢ÆðÒì³£±¾µØÊÍ·ÅÏûÏ¢*/
+#define NLAPDM_L2_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 15) /*SAPI0·¢ËÍÏûÏ¢µ½SAPI3*/
+#define NLAPDM_TOOL_SABM_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 16) /*NLAPDMÏò¹¤¾ß·¢ËÍÆÕͨ½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 17) /*¹¤¾ßÏòNLAPDM·¢ËÍÆÕͨ½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define NLAPDM_TOOL_SABM_COR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 18) /*NLAPDMÏò¹¤¾ß·¢ËͳåÍ»½â¾ö½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_COR_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 19) /*¹¤¾ßÏòNLAPDM·¢ËͳåÍ»½â¾ö½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define TOOL_NLAPDM_EXCEPT_DATA_EV (DWORD)(NLAPDM_EVENT_BASE + 20) /*¹¤¾ßÏòNLAPDM·¢ËÍÒì³£Êý¾ÝÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_I_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 21) /*NLAPDMÏò¹¤¾ß·¢ËÍÈ·ÈÏÊý¾ÝÉϱ¨Ö¸Ê¾ÏûÏ¢*/
+
+
+/* ========================================================================
+ NGMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NGMAC_START_EV (DWORD)(NGMAC_EVENT_BASE + 0) /*NGMACÄ£¿éÆô¶¯*/
+#define NGMAC_NGRLC_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 1) /*NGMAC¸øNGRLC·¢ËÍPDANÏûÏ¢*/
+#define NGMAC_NGRLC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 2) /*NGMAC¸øNGRLC·¢ËÍUPLINKÊý¾Ý¿é*/
+#define NGRLC_NGMAC_PUAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 3) /*NGRLC¸øNGMAC·¢ËÍPUANµÄ²ÎÊý*/
+#define NGMAC_NGRLC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 4) /*NGMAC֪ͨNGRLCÊÍ·ÅUPLINK TBF*/
+#define NGRLC_NGMAC_FBI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 5) /*RLC·ÇÈ·ÈÏģʽ£¬NGRLC֪ͨNGMAC×îÖÕ¿éÒÑ·¢³ö£¬NGMACµÈ´ýPCA*/
+#define NGMAC_NGRLC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 6) /*RLC·ÇÈ·ÈÏģʽ£¬NGMAC֪ͨNGRLCÊÍ·ÅTBF*/
+#define NGRLC_NGMAC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 7) /*RLCÈ·ÈÏģʽ£¬NGRLC֪ͨNGMACÊÍ·ÅDOWNLINK TBF*/
+#define NGRLC_NGMAC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 8) /*NGRLC֪ͨNGMACÒì³£ÊÍ·ÅUPLINK TBF*/
+#define NGMAC_NGRLC_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 9) /*NGMAC֪ͨNGRLC DOWNLINK_TBFÒѾÍêÈ«µÃµ½È·ÈÏ*/
+#define TOOL_NGMAC_PUA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 10) /*TOOL¸øNGMAC·¢ËÍPUA*/
+#define NGMAC_TOOL_PRR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 11) /*NGMAC¸øTOOL·¢ËÍPRR£¬Çé¿ö°üÀ¨£ºIDLE̬½¨Á¢µÄUPLINK TBF¡¢ULONULµÄTBF¡¢ULONDLµÄTBF*/
+#define NGMAC_TOOL_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 12) /*NGMAC¸øTOOL·¢ËÍPDANÏûÏ¢£¬½öÔÚÐèÒª½¨Á¢ULONDL TBFʱ²Å·¢*/
+#define TOOL_NGMAC_PUAN_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 13) /*TOOL¸øNGMAC·¢ËÍPUAN£¬½öÔÚ±àÂ뷽ʽ¡¢´°¿Ú´óС¡¢RESEGMENTµÈ¸Ä±äʱ²Å·¢*/
+#define TOOL_NGMAC_PDA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 14) /*TOOL¸øNGMAC·¢ËÍPDA*/
+#define NGMAC_TOOL_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 15) /*NGMAC¸øTOOL·¢ËÍPCA£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR8_IND_EV (DWORD)(NGMAC_EVENT_BASE + 16) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR11_IND_EV (DWORD)(NGMAC_EVENT_BASE + 17) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_CR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 18) /*NGMAC¸øTOOL·¢ËÍCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 19) /*NGMAC֪ͨTOOLÊÍ·ÅDOWNLINK TBF*/
+#define NGMAC_TOOL_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 20) /*NGMAC֪ͨTOOLÊÍ·ÅUPLINK TBF*/
+#define NGMAC_TOOL_TLLI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 21) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬NGMAC¸øTOOLÇëÇóCONT_RES_TLLI*/
+#define TOOL_NGMAC_TLLI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 22) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬TOOL¸øNGMAC·¢ËÍCONT_RES_TLLI*/
+#define TOOL_NGMAC_IMM_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 23) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨*/
+#define TOOL_NGMAC_IMM_EX_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 24) /*TOOL¸øNGMAC·¢ËÍÀ©Õ¹Á¢¼´É趨*/
+#define TOOL_NGMAC_IMM_REJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 25) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨¾Ü¾ø*/
+#define L1_NGMAC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 26) /*L1_SIMU°Ñ´ÓL1G½ÓÊÕµ½µÄÉÏÐÐÊý¾Ý·¢Ë͵½MAC_N*/
+#define NGMAC_NGMAC_TMS_FBI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 27) /*FBI¶¨Ê±Æ÷³¬Ê±*/
+#define NGMAC_NGMAC_TMS_FAI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 28) /*FAI¶¨Ê±Æ÷³¬Ê±*/
+#define TOOL_NGMAC_PMO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 29) /*TOOL¸øNGMAC·¢ËÍPMO*/
+#define TOOL_NGMAC_PSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 30) /*TOOL¸øNGMAC·¢ËÍPSI*/
+#define NGMAC_TOOL_MSACC_IND_EV (DWORD)(NGMAC_EVENT_BASE + 31) /*NGMACÏòTOOLÇëÇóUPLINK TBF½¨Á¢»òÇëÇó½¨Á¢RRÁ¬½Ó*/
+#define TOOL_NGMAC_ULTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 32) /*TOOLÅäÖÃNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 33) /*TOOLÅäÖÃNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_ULTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 34) /*TOOLÊÍ·ÅNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 35) /*TOOLÊÍ·ÅNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PKTTSRECFG_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 36) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TIMESLOT_RECONFIGUREµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTTBFREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 37) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TBF_RELEASEµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTPDCHREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 38) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_PDCH_RELEASEÏûÏ¢*/
+#define TOOL_NGMAC_PKTCCC_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 39) /*TOOLÒªÇóNGMAC·¢ËÍPACKET CELL CHANGE CONTINUE*/
+#define TOOL_NGMAC_PKTCCO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 40) /*TOOLÇëÇóNGMAC·¢ËÍPACKET CELL CHANGE ORDER*/
+#define TOOL_NGMAC_PKTNCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 41) /*TOOLÇëÇóNGMAC·¢ËÍPACKET NEIGHBOUR CELL DATA*/
+#define TOOL_NGMAC_PKTPOLL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 42) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POLLING REQUEST*/
+#define TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 43) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POWER CTRL/TA*/
+#define TOOL_NGMAC_PKTPRACHPARA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 44) /*TOOLÇëÇóNGMAC·¢ËÍPACKET PRACH PARAMETERS*/
+#define TOOL_NGMAC_PKTSCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 45) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVE CELL DATA*/
+#define TOOL_NGMAC_PKTQUENOTI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 46) /*TOOLÇëÇóNGMAC·¢ËÍPACKET QUEUING NOTIFICATION*/
+#define TOOL_NGMAC_PKTACCREJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 47) /*TOOLÇëÇóNGMAC·¢ËÍ·Ö×é½ÓÈë¾Ü¾ø*/
+#define NGMAC_TOOL_PKTMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 48) /*NGMAC½ÓÊÕµ½MS PACKET MEAS REPORT ºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTMOBTBFSTA_EV (DWORD)(NGMAC_EVENT_BASE + 49) /*NGMAC½ÓÊÕµ½MS PACKET MOBILE TBF STATUSºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTPSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 50) /*NGMAC½ÓÊÕµ½MS PACKET PSI STATUSºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTPAUSE_EV (DWORD)(NGMAC_EVENT_BASE + 51) /*NGMAC½ÓÊÕµ½MS PACKET PAUSEºó·¢ËÍÏûÏ¢µ½TOOL*/
+#define NGMAC_TOOL_PKTEMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 52) /*NGMAC½ÓÊÕµ½MS PACKET ENHANCED MEAS REPORTºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTADDMSRAC_EV (DWORD)(NGMAC_EVENT_BASE + 53) /*NGMAC½ÓÊÕµ½MS PACKET ADDITION MS RACºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTCCN_EV (DWORD)(NGMAC_EVENT_BASE + 54) /*NGMAC½ÓÊÕµ½MS PACKET CELL CHANGE NOTIFICATIONºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 55) /*NGMAC½ÓÊÕµ½MS PACKET SI STATUSºó·¢Ë͵½¹¤¾ß*/
+#define GMAC_GET_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 56) /*GMAC·¢ËÍÉÏÐÐÊý¾Ýʱµ÷Óú¯ÊýMAC_GET_BLOCKS,ΪÔö¼ÓTRACEÌí¼ÓµÄʼþºÅ*/
+#define GMAC_ACK_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 57) /*L1Gµ÷ÓÃMAC_ACK_BLOCKSʱΪÔö¼ÓÐÅÁî¸ú×Ù¶øÔö¼ÓµÄʼþºÅ*/
+#define TOOL_NGMAC_PKTPGREQ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 58)
+#define TOOL_NGMAC_CTRLBLOCK_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 59)
+#define NGMAC_TOOL_CCF_IND_EV (DWORD)(NGMAC_EVENT_BASE + 60) /*NGMACÏòTOOL·¢Ë͵ÄPACKET CELL CHANGE FAILUREÏûÏ¢*/
+#define NGMAC_NGRLC_EPDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 61) /*NGMAC¸øNGRLC·¢ËÍEPDANÏûÏ¢*/
+#define TOOL_NGMAC_PSHOCMD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 62) /*TOOLÇëÇóNGMAC·¢ËÍPs Handover Command*/
+#define TOOL_NGMAC_PPI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 63) /*TOOLÇëÇóNGMAC·¢ËÍPacket Physical Information*/
+#define TOOL_NGMAC_PSHO_ULTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 64) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_DLTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 65) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_RETURN_EV (DWORD)(NGMAC_EVENT_BASE + 66) /*TOOL ֪ͨNGMAC ×ÊÔ´»ØÍË*/
+#define TOOL_NGMAC_PSHO_REL_EV (DWORD)(NGMAC_EVENT_BASE + 67) /*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGMAC_TOOL_PSHO_ACC_EV (DWORD)(NGMAC_EVENT_BASE + 68) /*NGMACÏòTOOLÇëÇóPacket Physical Information*/
+#define TOOL_NGMAC_PKTSCELLSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 69) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVING CELL SI*/
+#define TOOL_NGMAC_PKTAPPINF_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 70) /*TOOLÇëÇóNGMAC·¢ËÍPACKET APPLICATION INFORMATION*/
+
+
+/* ========================================================================
+ NLLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLLC_START_EV (DWORD)(NLLC_EVENT_BASE + 0) /*NLLCÄ£¿éÆô¶¯*/
+#define NLLC_NRLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 1) /*֪ͨNRLCÒÔ·ÇÈ·ÈÏģʽ´«ÊäLLC-PDU*/
+#define NRLC_NLLC_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 2) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸öÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define NRLC_NLLC_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 3) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸ö·ÇÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define TOOL_NLLC_ASSIGN_REQ_EV (DWORD)(NLLC_EVENT_BASE + 4) /*¹¤¾ß֪ͨ NLLCÓÐеļÓÃÜËã·¨ºÍ²ÎÊý£¬ÒÔ¼°·ÖÅäTLLI*/
+#define TOOL_NLLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 5) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÓÃÎÞÓ¦´ð´«Êä*/
+#define NLLC_TOOL_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 6) /*NLLC²ãÏòÉϲ㴫ËÍÒÔ·ÇÈ·ÈÏģʽ½ÓÊÕµ½µÄL3_PDU*/
+#define TOOL_NLLC_DATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 7) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÈ·ÈÏ´«Êä*/
+#define NLLC_TOOL_FRMR_RSP_EV (DWORD)(NLLC_EVENT_BASE + 8) /*ÊÕµ½¾Ü¾øÖ¡*/
+#define NLLC_TOOL_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 9) /*NLLCÏòÉϲ㴫ËͽÓÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_DATA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 10) /*¹¤¾ß²àÏìÓ¦ÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_ESTABLISH_REQ_EV (DWORD)(NLLC_EVENT_BASE + 11) /*ÓÃÓÚΪNLLC²ãÖÐÒ»¸öSAPI½¨Á¢»òÖؽ¨ABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_ESTABLISH_RSP_EV (DWORD)(NLLC_EVENT_BASE + 12) /*ÉϲãÔÚ½ÓÊÕµ½LL_ESTABLISHָʾÔÓïÖ®ºóʹÓÃ.Ö÷ÒªÊÇÐÉÌXID²ÎÊý*/
+#define NLLC_TOOL_UA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 13) /*ÊÕµ½UA·µ»Ø*/
+#define NLLC_TOOL_ESTABLISH_IND_EV (DWORD)(NLLC_EVENT_BASE + 14) /*ÓÃÓÚ֪ͨÉϲã²ã¶ÔNLLC²ãÖеÄÒ»¸öSAPIÒѾ½¨Á¢»òÒѾÖؽ¨ÆðÁËABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_RELEASE_REQ_EV (DWORD)(NLLC_EVENT_BASE + 15) /*ÓÃÓÚÊÍ·ÅΪNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽ*/
+#define NLLC_TOOL_DM_RSP_EV (DWORD)(NLLC_EVENT_BASE + 16) /*ÊÕµ½DM·µ»Ø*/
+#define NLLC_TOOL_RELEASE_IND_EV (DWORD)(NLLC_EVENT_BASE + 17) /*ÓÃÓÚָʾNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽÒѱ»ÊÍ·Å*/
+#define TOOL_NLLC_RELEASE_RSP_EV (DWORD)(NLLC_EVENT_BASE + 18) /*ÓÃÓÚ¹¤¾ß֪ͨNLLC·µ»Ø³É¹¦ÊÍ·ÅÏìÓ¦*/
+#define TOOL_NLLC_XID_REQ_EV (DWORD)(NLLC_EVENT_BASE + 19) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÇëÇó*/
+#define TOOL_NLLC_XID_RSP_EV (DWORD)(NLLC_EVENT_BASE + 20) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÏìÓ¦*/
+#define NLLC_TOOL_XID_CNF_EV (DWORD)(NLLC_EVENT_BASE + 21) /*ÓÃÓÚÈ·ÈÏÉϲãXID²ÎÊýÐÉÌÍê³É*/
+#define NLLC_TOOL_XID_IND_EV (DWORD)(NLLC_EVENT_BASE + 22) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐXID²ÎÊýÐèÒªÐÉÌ*/
+#define NLLC_TOOL_NULL_IND_EV (DWORD)(NLLC_EVENT_BASE + 23) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐNULLÖ¡*/
+
+
+/* ========================================================================
+ NRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NRLC_DATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 0)
+#define NRLC_UNITDATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 1)
+#define NRLC_ASSIGN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 2)
+#define TOOL_NGRLC_ULTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 3)
+#define TOOL_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 4)
+#define TOOL_NGRLC_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 5)
+#define NGRLC_TOOL_DLTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 6)
+#define NGRLC_TOOL_DLTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 7)
+#define NGRLC_TOOL_ULTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 8)
+#define NGRLC_TOOL_ULTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 9)
+#define TOOL_NGRLC_ULTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 10)
+#define NGRLC_TOOL_ULTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 11)
+#define TOOL_NGRLC_DLTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 12)
+#define TOOL_NGRLC_DLTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 13)
+#define TOOL_NGRLC_EXTBF_ON_EV (DWORD)(NRLC_EVENT_BASE + 14)
+#define TOOL_NGRLC_EXTBF_OFF_EV (DWORD)(NRLC_EVENT_BASE + 15)
+#define NGRLC_TOOL_DLTBF_TRIGGER_IND_EV (DWORD)(NRLC_EVENT_BASE + 16)
+#define NGRLC_START_TIMER_EV (DWORD)(NRLC_EVENT_BASE + 17) /*ÄÚ²¿ÏûÏ¢£¬ÆäËûÄ£¿é²»»áʹÓÃ*/
+#define NGRLC_TOOL_DLTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 18)
+#define TOOL_NGRLC_BEGINTEST_MODE_EV (DWORD)(NRLC_EVENT_BASE + 19)
+#define NGRLC_TOOL_PDANNOTIFY_EV (DWORD)(NRLC_EVENT_BASE + 20)
+#define NGRLC_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 21)
+#define NGRLC_FILL_DATA_QUEUE_REQ_EV (DWORD)(NRLC_EVENT_BASE + 22)
+#define L1SIMU_NGRLC_DATA_IND_EV (DWORD)(NRLC_EVENT_BASE + 23)
+#define TOOL_NGRLC_MODE_CFG_REQ_EV (DWORD)(NRLC_EVENT_BASE + 24)
+#define NGRLC_TOOL_UL_DATA_BLOCK_IND_EV (DWORD)(NRLC_EVENT_BASE + 25)
+#define TOOL_NGRLC_DUMMYBLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 26)
+#define DOWNLINK_DUMMY_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 27)
+#define TOOL_NGRLC_DOWNLINK_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 28)
+#define TOOL_NGRLC_PSHO_ULTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 29)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 30)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_RETURN_EV (DWORD)(NRLC_EVENT_BASE + 31)/*TOOL ֪ͨNGRLC ×ÊÔ´»ØÍË*/
+#define TOOL_NGRLC_PSHO_REL_EV (DWORD)(NRLC_EVENT_BASE + 32)/*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGRLC_TOOL_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 33)/*NGRLC ֪ͨTOOL PSHO ³É¹¦*/
+#define NGRLC_NGMAC_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 34)/*NGRLC ֪ͨNGMAC PSHO ³É¹¦*/
+/* ========================================================================
+ URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 0)
+#define URRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 1)
+#define URRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 2)
+#define URRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 3)
+#define URRC_FUNC_ENTER_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 4)
+#define URRC_FUNC_READ_SIB_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 5)
+#define URRC_FUNC_READ_SIB_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 6)
+#define URRC_FUNC_SER_CELL_IND_EV (DWORD)(URRC_FUNC_EVENT_BASE + 7)
+#define URRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 8)
+#define URRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 9)
+#define URRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 10)
+#define URRC_FUNC_START_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 11)
+#define URRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 12)
+#define URRC_FUNC_PAGING_TYPE1_EV (DWORD)(URRC_FUNC_EVENT_BASE + 13)
+#define URRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 14)
+#define URRC_FUNC_GET_UE_CAP_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 15)
+#define URRC_FUNC_CFG_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 16)
+#define URRC_FUNC_CFG_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 17)
+#define URRC_FUNC_REL_FACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 18)
+#define URRC_FUNC_REL_FACH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 19)
+#define URRC_FUNC_REL_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 20)
+#define URRC_FUNC_REL_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 21)
+#define URRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 22)
+#define URRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 23)
+#define URRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 24)
+#define URRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 25)
+#define URRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 26)
+#define URRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(URRC_FUNC_EVENT_BASE + 27)
+#define URRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(URRC_FUNC_EVENT_BASE + 28)
+#define URRC_FUNC_STOP_SYSINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 29)
+#define URRC_FUNC_READ_CGIINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 30)
+#define URRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 31)
+#define URRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 32)
+
+/* ========================================================================
+ TAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TAF_FUNC_L1G_DATA_REQ_EV (DWORD)(TAF_FUNC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1GÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1G_ST_MEAS_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 0)
+#define L1G_ST_MEAS_IND_EV (DWORD)(L1G_ST_EVENT_BASE + 1)
+#define L1G_ST_FCB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 2)
+#define L1G_ST_FCB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 3)
+#define L1G_ST_SYNC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 4)
+#define L1G_ST_BSIC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 5)
+#define L1G_ST_SB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 6)
+#define L1G_ST_RX_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 7)
+#define L1G_ST_RX_EQU_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 8)
+#define L1G_ST_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 9)
+#define L1G_ST_RACH_EV (DWORD)(L1G_ST_EVENT_BASE + 10)
+#define L1G_ST_SDCCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 11)
+#define L1G_ST_SACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 12)
+#define L1G_ST_SACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 13)
+#define L1G_ST_FACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 14)
+#define L1G_ST_FACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 15)
+#define L1G_ST_DS_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 16)
+#define L1G_ST_DS_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 17)
+#define L1G_ST_TCH_CTRL_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 18)
+
+/* ========================================================================
+ GRRº¯Êý¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GRR_FUNC_SUSPEND_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 0)
+#define GRR_FUNC_RESUME_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 1)
+#define GRR_FUNC_SUSPEND_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 2)
+#define GRR_FUNC_RESUME_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 3)
+#define GRR_FUNC_IDLE_MODE_SETTING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 4)
+#define GRR_FUNC_LIST_HANDLING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 5)
+#define GRR_FUNC_SCELL_UPDATE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 6)
+#define GRR_FUNC_INIT_SCELL_PARAM_EV (DWORD)(GRR_FUNC_EVENT_BASE + 7)
+#define GRR_FUNC_INIT_GRR_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 8)
+#define GRR_FUNC_INIT_GRR_SCELL_TMP_EV (DWORD)(GRR_FUNC_EVENT_BASE + 9)
+#define GRR_FUNC_INIT_MI_EV (DWORD)(GRR_FUNC_EVENT_BASE + 10)
+#define GRR_FUNC_SI2QUATER_COMPLETE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 11)
+#define GRR_FUNC_CELL_SEL_BCCH_ALL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 12)
+#define GRR_FUNC_CELL_SEL_BCCH_MIN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 13)
+#define GRR_FUNC_RESET_SYSINFO_EV (DWORD)(GRR_FUNC_EVENT_BASE + 14)
+#define GRR_FUNC_STORE_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 15)
+#define GRR_FUNC_STORE_MODIFY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 16)
+#define GRR_FUNC_COPY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 17)
+#define GRR_FUNC_INDIVID_PRIORITY_CHANGE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 18)
+#define GRR_FUNC_GET_QSEARCH_EV (DWORD)(GRR_FUNC_EVENT_BASE + 19)
+#define GRR_FUNC_COPY_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 20)
+
+
+/* ========================================================================
+ αÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GAS_ST_CTRL_BLOCK_TLV_EV (DWORD)(SIGTRACE_EVENT_BASE + 0) /*GRRÏûÏ¢¶ÔµÈ²ãÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_UL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 1) /*GMAC¶ÔµÈ²ãÉÏÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 2) /*GMAC¶ÔµÈ²ãÏÂÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_SEG_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 3) /*GMAC¶ÔµÈ²ãÏÂÐзֶÎÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DLL_READ_DCCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 4)
+#define GAS_ST_DLL_READ_SACCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 5)
+#define ATI_PDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 6)
+#define UPDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 7)
+#define SN_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 8)
+#define SN_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 9)
+#define LL_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 10)
+#define LL_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 11)
+#define LLC_GET_NEXT_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 12)
+#define GMAC_GET_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 13)
+#define GMAC_ACK_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 14)
+#define PDCP_RLC_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 15)
+#define URLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 16)
+#define URLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 17)
+#define UMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 18)
+#define PH_MAC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 19)
+#define PH_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 20)
+#define MAC_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 21)
+#define RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 23)
+#define LL_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 24)
+#define LL_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 25)
+#define SN_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 26)
+#define SN_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 27)
+#define UPDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 28)
+#define ATI_PDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 29)
+#define UUMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 30)
+#define PDCP_RLC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 31)
+#define TAF_COUNTER_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 32)
+#define TAF_RLP_XID_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 33)
+#define TAF_RLP_XID_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 34)
+#define TAF_RLP_SABM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 35)
+#define TAF_RLP_SABM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 36)
+#define TAF_RLP_UA_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 37)
+#define TAF_RLP_UA_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 38)
+#define TAF_RLP_DISC_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 39)
+#define TAF_RLP_DISC_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 40)
+#define TAF_RLP_DM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 41)
+#define TAF_RLP_DM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 42)
+#define TAFL1G_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 43)
+#define TAFL1G_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 44)
+#define TAF_FUNC_UURLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 45)
+#define TAF_FUNC_UURLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 46)
+#define PDI_PDCP_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 47)
+#define PDCP_DATA_BACK_PDI_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 48)
+/*WCDMA(SIGIRACE=100)*/
+#define WRLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 49)
+#define WRLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 50)
+#define WMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 51)
+#define UWMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 52)
+#define TAF_FUNC_UWRLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 53)
+#define TAF_FUNC_UWRLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 54)
+#define WMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 55)
+#define WMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 56)
+#define EUMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 57)
+#define EUMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 58)
+#define EUMAC_HOLD_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 59)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ EMM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_T3410_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 0)
+#define EMM_T3416_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 1)
+#define EMM_T3417_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 2)
+#define EMM_T3418_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 3)
+#define EMM_T3420_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 4)
+#define EMM_T3421_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 5)
+#define EMM_T3430_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 6)
+#define EMM_T3440_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 7)
+#define EMM_T_POWEROFF_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 8)
+#define EMM_T3417EXT_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 9)
+#define EMM_T_WAITRELIND_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ ESM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_TIMER3480_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 0)
+#define ESM_TIMER3481_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 1)
+#define ESM_TIMER3482_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 2)
+#define ESM_TIMER3492_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 3)
+#define ESM_T_MTACTANSWER_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 4)
+#define ESM_T_WAITINGATH_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 5)
+#define ESM_T_PTIBUF_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 6)
+#define ESM_T_CMEST_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ EPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_T_DISCARD_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 0)
+#define EPDCP_T_DELAYMODEB_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 1)
+#define EPDCP_T_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ EURLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURLC_T_POLL_RETRANSMIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 0)
+#define EURLC_T_STATUS_PROHIBIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 1)
+#define EURLC_T_REORDERING_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 2)
+#define EUL2LOG_T_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 3)
+
+/* ========================================================================
+ EUMAC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMAC_T_EXPIRY_EV (DWORD)(EUMAC_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ EUCER×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_T300_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 0)
+#define EURRC_T301_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 1)
+#define EURRC_T302_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 2)
+#define EURRC_T303_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 3)
+#define EURRC_T304_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 4)
+#define EURRC_T305_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 5)
+#define EURRC_T310_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 6)
+#define EURRC_T311_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 7)
+#define EURRC_T60MS_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 8)
+#define EURRC_T3174_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 9)
+#define EURRC_VARRLF_VALID_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 10)
+#define EURRC_T306_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 11)
+#define EURRC_MCCH_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 12)
+#define EURRC_1SECOND_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 13)
+#define EURRC_TGPAGING_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 14)
+#define EURRC_PERIDOSTATUSREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 15)
+#define EURRC_SELFHOREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 16)
+#define EURRC_SINGLEUSEREXIT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 17)
+
+/* ========================================================================
+ EUMCR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMCR_T320_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 0)
+#define EUMCR_T321_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 1)
+#define EUMCR_T_REMAIN_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 2)
+#define EUMCR_T_LEAVE_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 3)
+#define EUMCR_T_HYSTNORMAL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 4)
+#define EUMCR_T_PROXIMITY_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 5)
+#define EUMCR_T_CELLINFO_REPORT_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 6)
+#define EUMCR_T_RESEL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 7)
+#define EUMCR_T_MDT_LOG_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 8)
+#define EUMCR_T330_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 9)
+#define EUMCR_T_48HOURS_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 10)
+#define EUMCR_T_LISTEN_HANDOVER_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 11)
+#define EUMCR_T_MONITOR_PERIOD_CHG_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 12)
+#define EUMCR_T_MONITOR_HO_EXPIR_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 13)
+/* ========================================================================
+ EUCSR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUCSR_T_SI_MODI_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 0)
+#define EUCSR_T_ABORT_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 1)
+#define EUCSR_T_FREQ_SCAN_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 2)
+#define EUCSR_T_CELL_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 3)
+#define EUCSR_T_PLMN_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 4)
+#define EUCSR_T_CSG_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 5)
+#define EUCSR_T_3HOUR_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 6)
+#define EUCSR_T_OOS_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 7)
+#define EUCSR_T_SWITCH_RADIO_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 8)
+#define EUCSR_T_REDIRECT_TO_LTE_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 9)
+#define EUCSR_T_SYNC_BARREDLIST_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 10)
+#define EUCSR_T_WAIT_RESEL_TO_UTRA_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 11)
+#define EUCSR_T_REDIRECT_TO_LTE_OP_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 12)
+#define EUCSR_T_LISTEN_RESEL_SUCC_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 13)
+#define EUCSR_T_LBS_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 14)
+#define EUCSR_T_ECID_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 15)
+
+
+/* ========================================================================
+ EUSIR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUSIR_T_SIB1GUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 0)
+#define EUSIR_T_SIMSGGUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 1)
+#define EUSIR_T_ETWS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 2)
+#define EUSIR_T_CMAS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 3)
+#define EUSIR_T_SIBVALID_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ EMMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_TU_SUCC_IND_EV (DWORD)(EMM_UMM_EVENT_BASE + 0)
+
+#define UMM_CONFIG_REQ_EV (DWORD)(EMM_UMM_RSP_EVENT + 0)
+
+/* ========================================================================
+ UMMºÍEPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_UMM_EST_REJ_EV (DWORD)(UMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_UMM_EST_REQ_EV (DWORD)(UMM_EPDCP_RSP_EVENT + 0)
+
+/* ========================================================================
+ CM²ãºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EMM_DATA_REQ_EV (DWORD)(CM_EMM_EVENT_BASE + 0)
+/* ========================================================================
+ ESMºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESM->EMM*/
+#define ESM_EMM_DEFAULT_ACT_REJ_EV (DWORD)(ESM_EMM_EVENT_BASE + 0)
+#define ESM_EMM_EMERGENCY_PDN_EST_SUCC_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 1)
+#define ESM_EMM_EMERGENCY_PDN_ONLY_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 2)
+
+/* EMM->ESM*/
+#define ESM_EMM_DATA_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 0)
+#define ESM_EMM_ATTACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 1)
+#define ESM_EMM_ATTACH_REJ_EV (DWORD)(ESM_EMM_RSP_EVENT + 2)
+#define ESM_EMM_CONTEXT_STATUS_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 3)
+#define ESM_EMM_DETACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 4)
+#define ESM_EMM_DETACH_EMERGENCY_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 5)
+#define EMM_ESM_DETACH_NORMAL_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 6)
+
+/* ========================================================================
+ EMMºÍASC(ERRC(CER))Ä£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_ASC_EST_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 1)
+#define EMM_ASC_EST_ABT_EV (DWORD)(EMM_ASC_EVENT_BASE + 2)
+#define EMM_ASC_REL_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 3)
+#define EMM_ASC_KENB_RSP_EV (DWORD)(EMM_ASC_EVENT_BASE + 4)
+#define EMM_ASC_REL_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 5)
+#define EMM_ASC_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 6)
+#define EMM_ASC_DETACH_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 7)
+
+/* EURRC->ASC */
+#define EMM_ASC_DATA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 0)
+#define EMM_ASC_EST_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 1)
+#define EMM_ASC_EST_REJ_EV (DWORD)(EMM_ASC_RSP_EVENT + 2)
+#define EMM_ASC_REL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 3)
+#define EMM_ASC_ABA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 4)
+#define EMM_ASC_DRB_SETUP_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 5)
+#define EMM_ASC_TRANS_FAIL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 6)
+#define EMM_ASC_KENB_REQ_EV (DWORD)(EMM_ASC_RSP_EVENT + 7)
+#define EMM_ASC_UE_INFO_CHANGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 8)
+#define EMM_ASC_DATA_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 9)
+#define EMM_ASC_PAGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 10)
+#define EMM_ASC_SEC_PARA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 11)
+/* ========================================================================
+ EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EPDCP_EMM_EST_REJ_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_EMM_BAR_ALLEVIATE_NOTIFY_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 1)
+/* ========================================================================
+ ESMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESMºÍUMMÄ£¿éÖ®¼äµÄÏûϢʼþºÅ--
+* 1.CM_EST_REQ_EV£¬
+* 2.CM_EST_CNF_EV£¬
+* 3.CM_RELIND_EVÑØÓÃÒÔÇ°90AµÄ½Ó¿Ú*/
+/*ESM->UMM*/
+#define ESM_UMM_DETACH_REQ_EV (DWORD)(ESM_UMM_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_UMM_LOCAL_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 1)
+
+/* ========================================================================
+ SMºÍESMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*SM->ESM*/
+#define SM_ESM_DATA_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 0) /*Added:KangShuJie*/
+#define SM_ESM_RAT_ACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define SM_ESM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define SM_ESM_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 3) /*Added:KangShuJie*/
+/*ESM->SM*/
+#define ESM_SM_DATA_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 0) /*Added:KangShuJie*/
+#define ESM_SM_RAT_ACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 1) /*Added:KangShuJie*/
+#define ESM_SM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 2) /*Added:KangShuJie*/
+#define ESM_SM_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 3) /*Added:KangShuJie*/
+
+
+/* ========================================================================
+ ESMºÍEPDCP*Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_EPDCP_DEACTIVATE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_MOVE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_DEL_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define ESM_EPDCP_DIAL_IND_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 3)
+#define DEL_USER_PLANE_BUFFER_DATA_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 4)
+
+#define ESM_EPDCP_LOCAL_DEACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 0)
+#define ESM_EPDCP_RAT_SEQ_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 1)
+#define ESM_EPDCP_RAT_ACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 2)
+#define ESM_EPDCP_RAT_CHANGE_COMP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 3) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_SEQ_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 4) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_ACT_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 5) /*Added:KangShuJie*/
+#define EPDCP_ESM_STATUS_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 6) /*Added:KangShuJie*/
+#define ESM_EPDCP_CURR_BEAR_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 7)
+
+/* ========================================================================
+ EURRCºÍEPDCPÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 0)
+#define EURRC_EPDCP_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 1)
+#define EURRC_EPDCP_DATA_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 2)
+#define EURRC_EPDCP_REESTABLISH_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 3)
+#define EURRC_EPDCP_RELEASE_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 4)
+#define EURRC_EPDCP_RESUME_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 5)
+#define EURRC_EPDCP_SUSPEND_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 6)
+#define EURRC_EPDCP_DECIPHER_AND_INT_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 7)
+#define EURRC_EPDCP_HO_SUCC_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 8)
+#define EURRC_EPDCP_HO_FAIL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 9)
+#define EURRC_EPDCP_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 10)/*Added:KangShuJie*/
+#define EURRC_EPDCP_SMC_END_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 11)
+#define EURRC_EPDCP_TRUNKING_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 12)
+#define EURRC_EPDCP_CELL_RESEL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 13)
+
+
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 0)
+#define EURRC_EPDCP_DATA_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 1)
+#define EURRC_EPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 2)
+#define EURRC_EPDCP_CONFIG_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 3)
+#define EURRC_EPDCP_DATA_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 4)
+#define EURRC_EPDCP_REESTABLISH_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 5)
+#define EURRC_EPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 6)
+/* ========================================================================
+ EURRCºÍEURLCÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EURLC_CONFIG_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EURLC_RELEASE_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+
+#define EURRC_EURLC_CONFIG_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EL2_EURRC_RADIOLINK_FAIL_IND_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EURRC_EL2_TRUNKCH_ERROR_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 3)
+/* ========================================================================
+ EURRCºÍEUMACÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EURRC_EUMAC_CCCH_DATA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_COMM_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_DEDI_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_REL_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 3) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESET_MAC_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 4) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESUME_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 5) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_SUSPEND_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 6) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 7) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_HO_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 8)
+#define EURRC_EUMAC_REL_DEDI_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 11)
+#define EURRC_EUMAC_GRNTI_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 12)
+#define EURRC_EUMAC_SR_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 13)
+#define EURRC_EUMAC_LISTENINGCFG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 14)
+
+#define EUMAC_EURRC_CCCH_DATA_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_PROBLEM_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_SUCC_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_HO_CNF_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 3)
+#define EUMAC_EURRC_PUCCH_SRS_REL_REQ (DWORD)(EURRC_EUMAC_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define EURLC_EPDCP_UM_DATA_CNF_EV (DWORD)(EUPDCP_EURLC_EVENT_BASE + 0)
+
+/* ========================================================================
+ EURRCºÍMEL2Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EUMAC_MCH_CONFIG_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 0)
+#define EURRC_EUMAC_MCH_REL_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 1)
+#define MEL2_DMA_COMPLETE_IND (DWORD)(EURRC_MEL2_EVENT_BASE + 2)
+#define EUMAC_EURRC_MCCH_DATA_IND_EV (DWORD)(EURRC_MEL2_RSP_EVENT + 0)
+
+/* ========================================================================
+ EURRCÄÚ²¿ÏûϢʼþºÅ¶¨Òå
+======================================================================== */
+/*EUCER-EUMCR*/
+#define EURRC_MCR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 0)
+#define EURRC_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 1)
+#define EURRC_IDLE_INFO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 2)
+
+#define EURRC_SCELL_UNSUITABLE_IND_EV (DWORD)(EURRC_EVENT_BASE + 3)
+#define EURRC_CER_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 4)
+
+/*EUCER-EUCSR*/
+#define EURRC_CSR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 5)
+#define EURRC_CELL_INFO2NAS_EV (DWORD)(EURRC_EVENT_BASE + 6)
+#define EURRC_BARRED_CELL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 7)
+#define EURRC_REL_EPHY_CNF_EV (DWORD)(EURRC_EVENT_BASE + 8)
+
+#define EURRC_CER_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 9)
+#define EURRC_CELL_SEL_SUCC_IND_EV (DWORD)(EURRC_EVENT_BASE + 10)
+#define EUCER_TRS_TEST_IND_EV (DWORD)(EURRC_EVENT_BASE + 11)
+#define EURRC_REL_EPHY_REQ_EV (DWORD)(EURRC_EVENT_BASE + 12)
+/*EUCER-EUSIR*/
+
+#define EURRC_CER_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 13)
+
+/*EUCSR-EUMCR*/
+#define EURRC_CELL_RESEL_REJ_EV (DWORD)(EURRC_EVENT_BASE + 14)
+#define EURRC_PLMN_SEL_IND_EV (DWORD)(EURRC_EVENT_BASE + 15)
+#define EURRC_MCR_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 16)
+
+#define EURRC_CELL_RESEL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 17)
+#define EURRC_CSR_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 18)
+/*EUCSR-EUSIR*/
+
+#define EURRC_READ_SI_REQ_EV (DWORD)(EURRC_EVENT_BASE + 19)
+#define EURRC_ABORT_SI_READ_REQ_EV (DWORD)(EURRC_EVENT_BASE + 20)
+
+#define EURRC_CSR_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 21)
+#define EURRC_CSG_IND_EV (DWORD)(EURRC_EVENT_BASE + 22)
+#define EURRC_WARNING_NOTIFY_INFO_EV (DWORD)(EURRC_EVENT_BASE + 23)
+
+/*EUCSR-EUCER*/
+#define EURRC_CER_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 24)
+
+
+/*UMCR-EUSIR*/
+ /*UMCR-EUSIR ͬEURRC_READSI_REQ_EV
+ EURRC_ABORTSIREAD_REQ_EV */
+
+#define EURRC_MCR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 25)
+#define EURRC_CGI_CNF_EV (DWORD)(EURRC_EVENT_BASE + 26)
+#define EURRC_GET_RF_REQ_EV (DWORD)(EURRC_EVENT_BASE + 27)
+#define EURRC_GET_RF_CNF_EV (DWORD)(EURRC_EVENT_BASE + 28)
+#define EURRC_CSG_PROXIMITY_IND_EV (DWORD)(EURRC_EVENT_BASE + 29)
+#define EURRC_SI_END_FOR_HO_EV (DWORD)(EURRC_EVENT_BASE + 30)
+#define EURRC_MDT_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 31)
+#define EURRC_MCR_CGI_PEND_REQ_EV (DWORD)(EURRC_EVENT_BASE + 32)
+#define EURRC_MCR_CGI_PEND_CNF_EV (DWORD)(EURRC_EVENT_BASE + 33)
+#define EURRC_INTEREST_FREQ_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 34)
+#define EURRC_CER_SELFHO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 35)
+#define EURRC_NETWORK_TIME_INFO_IND_EV (DWORD)(EURRC_EVENT_BASE + 36)
+#define EURRC_RRC_STATE_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 37)
+#define EURRC_EUCER_RESUME_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 38)
+#define EURRC_EUCER_ABORT_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 39)
+#define EURRC_CSR_XCELL_IND_EV (DWORD)(EURRC_EVENT_BASE + 40)
+#define EURRC_EUMCR_START_MEAS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 41)
+#define EURRC_CSR_RESEL_START_EV (DWORD)(EURRC_EVENT_BASE + 42)
+#define EURRC_CSR_RESEL_END_EV (DWORD)(EURRC_EVENT_BASE + 43)
+#define EURRC_CSR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 44)
+//LBS
+#define EURRC_CELL_MEAS_IND_EV (DWORD)(EURRC_EVENT_BASE + 45)
+#define EURRC_EUMCR_START_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 46)
+#define EURRC_EUMCR_STOP_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 47)
+#define EURRC_EUCER_UE_INFO_RLF_9E0_EV (DWORD)(EURRC_EVENT_BASE + 48)
+#define EURRC_EUCER_UE_CAPA_LTE_9D0_EV (DWORD)(EURRC_EVENT_BASE + 49)
+#define EURRC_MEAS_GAP_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 50)
+#define EURRC_CER_REL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 51)
+
+
+/*EURRC<->L1E*/
+#define EURRC_L1E_MEAS_SUSPEND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 0)
+#define EURRC_L1E_MEAS_RESUME_EV (DWORD)(EURRC_L1E_EVENT_BASE + 1)
+#define EURRC_L1E_GSM_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 2)
+#define EURRC_L1E_UTRA_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 3)
+#define EURRC_L1E_GSM_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 4)
+#define EURRC_L1E_TD_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 5)
+#define EURRC_L1E_RESOURCE_REL_EV (DWORD)(EURRC_L1E_EVENT_BASE + 6)
+#define EURRC_L1E_RESOURCE_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 7)
+#define EURRC_L1E_SI_END_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 8)
+#define EURRC_L1E_GET_RF_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 9)
+#define EURRC_L1E_STATE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 10)
+#define EURRC_L1E_TRACE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 11)
+#define EURRC_L1E_W_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 12)
+#define EURRC_L1E_IRAT_CGI_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 13)
+#define EURRC_L1E_IRAT_CGI_END_EV (DWORD)(EURRC_L1E_EVENT_BASE + 14)
+
+#define L1E_EURRC_RESOURCE_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 0)
+#define L1E_EURRC_GSM_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 1)
+#define L1E_EURRC_TD_LIST_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 2)
+#define L1E_EURRC_TD_BLIND_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 3)
+#define EURRC_L1E_GET_RF_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 4)
+#define L1E_EURRC_W_MEAS_RLT_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 5)
+/* ========================================================================
+ LTEÐÒéÕ»ºÍÎïÀí²ãÏûϢʼþÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* PS -> EPHY MSG ID */
+#define LTE_P_FREQ_SCAN_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 0)
+#define LTE_P_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 1)
+#define LTE_P_READ_SIB1_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 2)
+#define LTE_P_SCHED_SI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 3)
+#define LTE_P_ABORT_SI_READ_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 4)
+#define LTE_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 5)
+#define LTE_P_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 6)
+#define LTE_P_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 7)
+#define LTE_P_MEAS_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 8)
+#define LTE_P_ABORT_MEAS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 9)
+#define LTE_P_EARFCN_BAND_INFO_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 10)
+#define LTE_P_COMMON_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 11)
+#define LTE_P_DEDICATED_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 12)
+#define LTE_P_HANDOVER_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 13)
+#define LTE_P_MAC_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 14)
+#define LTE_P_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 15)
+#define LTE_P_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 16)
+#define LTE_P_ABORT_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 17)
+#define LTE_P_TA_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 18)
+#define LTE_P_DRX_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 19)
+#define LTE_P_TA_TIMER_STOP_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 20)
+#define LTE_P_FREQ_LIST_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 21)
+#define LTE_P_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 22)
+#define LTE_P_ABORT_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 23)
+#define LTE_P_IRAT_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 24)
+#define LTE_P_IDLE_PERIOD_REP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 25)
+#define LTE_P_SET_MODE_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 26)
+#define LTE_P_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 27)
+#define LTE_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 28)
+#define LTE_P_WAKEUP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 29)
+#define ZPS_LTE_ZEPCG_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 30)
+#define LTE_P_GRNTI_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 31)
+#define LTE_P_BTRUNK_TTCH_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 32)
+#define LTE_P_DEDICATECD_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 33)
+#define LTE_P_BTRUNK_CONFIG_REL_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 34)
+#define LTE_P_ACT_DEACT_SCELL_CTRL_ELEMNT_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 35)
+#define LTE_P_MCCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 36)
+#define LTE_P_MTCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 37)
+#define LTE_P_MTCH_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 38)
+#define LTE_P_PMCH_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 39)
+#define LTE_P_MSI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 40)
+#define LTE_P_CARD2_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 41) /*T_zLTE_P_card2_gap_req*/
+#define LTE_P_CARD2_GAP_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 42) /*T_zLTE_P_card2_gap_rel_req*/
+#define LTE_P_CARD2_STOP_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 43) /*T_zLTE_P_card2_stop_gap_req*/
+#define LTE_P_CARD1_SUSPEND_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 44) /*T_zLTE_P_card1_suspend_req*/
+#define LTE_P_CARD1_RESUME_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 45) /*T_zLTE_P_card1_resume_req*/
+#define LTE_P_MEAS_PERIOD_CHG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 46)
+#define LTE_P_AMT_MSG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 47)
+#define LTE_P_RPI_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 48)
+#define LTE_P_RPI_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 49)
+#define LTE_P_OTDOA_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 50)
+#define LTE_P_OTDOA_MEAS_ABORT_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 51)
+#define ZPS_LTE_CARD_SWITCH_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 52)
+
+
+
+/* EPHY -> PS MSG ID */
+#define LTE_P_SI_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 0)
+#define LTE_P_PBCH_READ_FAIL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 1)
+#define LTE_P_FREQ_SCAN_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 2)
+#define LTE_P_CELL_SEARCH_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 3)
+#define LTE_P_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 4)
+#define LTE_P_INTRA_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 5)
+#define LTE_P_INTER_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 6)
+#define LTE_P_DRX_STATE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 7)
+#define LTE_P_HANDOVER_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 8)
+#define LTE_P_OUT_OF_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 9)
+#define LTE_P_RECOVERY_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 10)
+#define LTE_P_PUCCH_SRS_REL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 11)
+#define LTE_P_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 12)
+#define LTE_P_ACCESS_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 13)
+#define LTE_P_EUMAC_INIT_RA_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 14)
+#define LTE_P_RA_RESPONSE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 15)
+#define LTE_P_DLSCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 16)
+#define LTE_P_IRAT_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 17)
+#define LTE_P_ABORT_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 18)
+#define LTE_P_RESET_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 19)
+#define LTE_P_INACTIVE_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 20)
+#define LTE_P_SLEEP_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 21)
+#define ZPS_LTE_ZEPCG_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 22)
+#define LTE_P_EMBMS_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 23)
+#define LTE_P_ULGRANT_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 24)
+#define LTE_P_OTDOA_MEAS_RLT_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 25)
+#define LTE_P_C0_SAVE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 26)
+#define LTE_P_BTRUNK_CQI_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 27)
+#define LTE_P_LISTENINGHO_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 28)
+#define LTE_P_BTRUNK_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 29)
+#define EPDCP_EDCP_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 30)
+#define EURLC_EMAC_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 31)
+#define LTE_P_CARD2_GAP_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 32) /*T_zLTE_P_card2_gap_ind*/
+#define LTE_P_CARD2_GAP_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 33)
+#define LTE_P_CARD2_STOP_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 34)
+#define LTE_P_CARD1_SUSPEND_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 35)
+#define LTE_P_PHYWAKEUPPS_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 36)
+#define LTE_P_ICP_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 37)
+#define LTE_P_AMT_MSG_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 38)
+#define ZPS_LTE_CARD_SWITCH_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 39)
+
+
+#if 0
+#define LTE_P_RF_ERR_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 40)
+#endif
+
+
+/* ========================================================================
+ LTEÐÒéÕ»ºÍTRSÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TRS_ESM_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 0)
+#define TRS_ESM_L3TC_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 1)
+#define TRS_ESM_ACT_DED_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 0)
+#define TRS_ESM_ACT_DED_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 1)
+#define TRS_ESM_ACT_DEF_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 2)
+#define TRS_ESM_ACT_DEF_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 3)
+#define TRS_ESM_BR_ALLOC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 4)
+#define TRS_ESM_BR_MOD_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 5)
+#define TRS_ESM_DEACT_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 6)
+#define TRS_ESM_ESMINFO_RSP_EV (DWORD)(TRS_ESM_RSP_EVENT + 7)
+#define TRS_ESM_ESMSTATUS_EV (DWORD)(TRS_ESM_RSP_EVENT + 8)
+#define TRS_ESM_MOD_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 9)
+#define TRS_ESM_MOD_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 10)
+#define TRS_ESM_PDN_CON_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 11)
+#define TRS_ESM_PDN_DISC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 12)
+#define TRS_ESM_L3TC_CLOSE_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 13)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 14)
+#define TRS_ESM_L3TC_ACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 15)
+#define TRS_ESM_L3TC_DEACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 16)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMBMSPACKETCNT_RESP_EV (DWORD)(TRS_ESM_RSP_EVENT + 17)
+/* TRS -> MME_EMM */
+#define TRS_EMM_DATA_REQ_EV (DWORD)(TRS_EMM_EVENT_BASE + 0)
+#define TRS_EMM_MAPPED_SEC_PARAM_Ev (DWORD)(TRS_EMM_EVENT_BASE + 1)
+#define TRS_EMM_PS_HO_FROM_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 2)
+#define TRS_EMM_PS_HO_TO_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 3)
+/* MME_EMM ->TRS */
+#define ENB_TRS_ESM_CMD_EV (DWORD)(TRS_EMM_RSP_EVENT + 0)
+#define TRS_EMM_L3MSG_ATTACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 1)
+#define TRS_EMM_L3MSG_ATTACH_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 2)
+#define TRS_EMM_L3MSG_AUTH_FAIL_EV (DWORD)(TRS_EMM_RSP_EVENT + 3)
+#define TRS_EMM_L3MSG_AUTH_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 4)
+#define TRS_EMM_L3MSG_AUTH_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 5)
+#define TRS_EMM_L3MSG_DETACH_APT_EV (DWORD)(TRS_EMM_RSP_EVENT + 6)
+#define TRS_EMM_L3MSG_DETACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 7)
+#define TRS_EMM_L3MSG_ULNAS_TRANS_EV (DWORD)(TRS_EMM_RSP_EVENT + 8)
+#define TRS_EMM_L3MSG_SERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 9)
+#define TRS_EMM_L3MSG_EXSERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 10)
+#define TRS_EMM_L3MSG_GUTI_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 11)
+#define TRS_EMM_L3MSG_IDNT_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 12)
+#define TRS_EMM_L3MSG_SMC_COM_EV (DWORD)(TRS_EMM_RSP_EVENT + 13)
+#define TRS_EMM_L3MSG_SMC_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 14)
+#define TRS_EMM_L3MSG_TAU_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 15)
+#define TRS_EMM_L3MSG_TAU_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 16)
+#define TRS_EMM_L3MSG_EMMSTATUS_EV (DWORD)(TRS_EMM_RSP_EVENT + 17)
+#define TRS_EMM_DATA_IND_EV (DWORD)(TRS_EMM_RSP_EVENT + 18)
+
+#define ENB_EMM_ESM_DATA_REQ_EV (DWORD)(ENB_EMM_ESM_EVENT_BASE + 0)
+#define ENB_EMM_ESM_DATA_IND_EV (DWORD)(ENB_EMM_ESM_RSP_EVENT + 0)
+/* MME_EMM -> ENBRRC */
+#define ENB_RRC_EMM_DATA_REQ_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 0)
+#define ENB_RRC_EMM_DLSQN_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 1)
+/* ENBRRC -> MME_EMM */
+#define ENB_RRC_EMM_DATA_IND_EV (DWORD)(ENB_RRC_EMM_RSP_EVENT + 0)
+
+
+/* ÆäËüLTE²âÊÔÄ£¿éÏûÏ¢IDºêÌí¼Ó´¦*/
+#define ENBRRC_RRC_CONN_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 0)
+#define ENBRRC_RRC_CONN_SETUP_EV (DWORD)(ENB_RRC_EVENT_BASE + 1)
+#define ENBRRC_RRC_CONN_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 2)
+#define ENBRRC_RRC_CONN_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 3)
+#define ENBRRC_SEC_MODE_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 4)
+#define ENBRRC_SEC_MODE_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 5)
+#define ENBRRC_SEC_MODE_FAIL_EV (DWORD)(ENB_RRC_EVENT_BASE + 6)
+#define ENBRRC_RRC_CONN_RECONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 7)
+#define ENBRRC_RRC_CONN_RECONFIG_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 8)
+#define ENBRRC_RRC_CONN_REEST_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 9)
+#define ENBRRC_RRC_CONN_REEST_EV (DWORD)(ENB_RRC_EVENT_BASE + 10)
+#define ENBRRC_RRC_CONN_REEST_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 11)
+#define ENBRRC_RRC_CONN_REEST_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 12)
+#define ENBRRC_RRC_CONN_REL_EV (DWORD)(ENB_RRC_EVENT_BASE + 13)
+#define ENBRRC_UE_CAP_ENQUIRY_EV (DWORD)(ENB_RRC_EVENT_BASE + 14)
+#define ENBRRC_UE_CAP_INFO_EV (DWORD)(ENB_RRC_EVENT_BASE + 15)
+#define ENBRRC_UE_MEAS_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 16)
+#define ENB_NASRRC_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 17)
+#define ENB_NASRRC_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 18)
+#define TRS_EPHY_UE_MEAS_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 19)
+#define TRS_EPHY_UE_CER_HO_REQ_CTL_EV (DWORD)(ENB_RRC_EVENT_BASE + 20)
+#define ENBRRC_COUNTER_CHECK_SUCC_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 21)
+#define ENBRRC_COUNTER_CHECK_FAIL_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 22)
+#define ENBRRC_MOBILITY_FROM_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 23)
+#define ENBRRC_START_HO_FROM_EUTRA_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 24)
+#define ENBRRC_START_HO_TO_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENBRRC_PROXIMITY_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 26)
+#define ENBRRC_UE_INFO_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 27)
+#define ENBRRC_UE_INFO_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 28)
+#define ENBRRC_MBSFN_AREA_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 29)
+#define ENBRRC_MBMS_COUNTING_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 30)
+#define ENBRRC_TDLINFO_TRANS_EV (DWORD)(ENB_RRC_EVENT_BASE + 31)
+#define ENBRRC_GROUPCALL_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 32)
+#define ENBRRC_GROUPCALL_RELEASE_EV (DWORD)(ENB_RRC_EVENT_BASE + 33)
+#define ENRRC_NEIGHBOURINFO_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+
+#define ENRRC_ENPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 0)
+#define ENRRC_ENPDCP_CONFIG_CIPHER_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 1)
+#define ENRRC_ENPDCP_CONFIG_INTEGRITY_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 2)
+#define ENRRC_ENPDCP_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 3)
+#define ENRRC_ENPDCP_DATA_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 4)
+#define ENRRC_ENPDCP_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 5)
+#define ENRRC_ENPDCP_RELEASE_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 6)
+#define ENRRC_ENPDCP_RESUME_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 7)
+#define ENRRC_ENPDCP_SUSPEND_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 8)
+#define ENRRC_ENPDCP_DECIPHER_AND_INTCHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 9)
+#define ENRRC_ENPDCP_SEC_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 10)
+
+#define ENRRCENPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 0)
+#define ENRRCENPDCP_DATA_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 1)
+#define ENRRCENPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 2)
+#define ENRRCENPDCP_CONFIG_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 3)
+#define ENRRCENPDCP_DATAC_NF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 4)
+#define ENRRCENPDCP_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 5)
+#define ENRRCENPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 6)
+#define ENRRCENPDCP_ENABLE_UL_DECIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 7)
+#define ENRRCENPDCP_COUNTER_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 8)
+#define ENRRCENPDCP_MDT_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 9)
+
+#define ENPDCP_EDCP_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 0)
+#define ENRLC_ENMAC_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 1)
+/* ========================================================================
+ ENPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDCP_DISCARDTIMER_EV (DWORD)(ENPDCP_TIMER_EVENT_BASE + 0)
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDI_DATA_REQ_EV (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 0)
+
+#define ENPDI_DATA_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 0)
+#define ENPDI_NOT_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 1)
+#define ENPDI_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 2)
+
+
+/* ========================================================================
+ TRS ÏûÏ¢ºÅ¶¨ÒåΪGCF ²âÊÔ¶øÌí¼Ó2010/3/8 SHIFANGMING
+======================================================================== */
+
+#define LTE_GCF_STARTCHECK_REQ_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 0)
+#define LTE_GCF_CHECKPASS_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 1)
+#define LTE_GCF_CHECKFAIL_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 2)
+
+#define LTE_GCF_CHECK_TIMER_EV (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ ENRLC - TRS ÏûÏ¢ºÅ¶¨Òå2010/3/1 LIUHUAN
+======================================================================== */
+#define TRS_ENRLC_UMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 0)
+#define TRS_ENRLC_AMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 1)
+#define TRS_ENRLC_SDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 2)
+#define TRS_ENRLC_AUTOACK_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ PDI - TRS ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SIMULATI_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 0)
+#define SIMULATI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 1)
+#define SIMULATI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 2)
+#define SIMULATI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 3)
+#define SIMULATI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 4)
+#define SIMULATI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 5)
+#define SIMULATI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 6)
+#define SIMULATI_DATA_IND_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 7)
+#define SIMULPSI_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 8)
+#define SIMULATI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 9)
+#define SIMULATI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define SIMULATI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 11)
+#define SIMULATI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 12)
+#define SIMULATI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 13)
+
+#define SIMULENPDI_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 0)
+#define SIMULENPDI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 1)
+#define SIMULENPDI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 2)
+#define SIMULENPDI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 3)
+#define SIMULENPDI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 4)
+#define SIMULENPDI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 5)
+#define SIMULENPDI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 6)
+#define SIMULENPDI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 7)
+#define SIMULENPDI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 8)
+#define SIMULENPDI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 9)
+#define SIMULENPDI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define SIMULENPDI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 11)
+/* ========================================================================
+ ENRRCÓëENRLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRRC_ENRLC_CONFIG_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 0)
+#define ENRRC_ENRLC_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 1)
+#define ENRRC_ENRLC_RELEASE_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 2)
+
+#define ENRLC_ENRRC_CONFIG_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 0)
+#define ENRLC_ENRRC_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 1)
+#define ENRLC_ENRRC_RETX_FAIL_IND_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 2)
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define ENRLC_ENPDCP_UMDATA_CNF_EV (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 0)
+
+
+/* ========================================================================
+ ENRLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRLC_REORDERING_TIMER_EV (DWORD)(ENRLC_TIMER_EVENT_BASE + 0)
+/*EPHY--->ENMAC*/
+#define EPHY_ENMAC_DATA_IND_EV (DWORD)(ENMAC_EPHY_RSP_EVENT + 0) /*EUMAC·¢Ë͵ÄÊý¾Ýµ½´ï*/
+
+/***************************************************** ¶ÔÓ¦UE²àRRC Ïà¹ØÏûÏ¢ *********** Êý¾ÝÃæÕâÀïÓ¦¸Ã²»ÐèÒªÕâЩÏûÏ¢ ÕâÀïµÄ¶¨ÒåÊÇÒÔ·ÀÍòÒ» ******************************************************/
+#define ENMAC_CCCH_DATA_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 0) /*RRC²àÇëÇóCCCHÊý¾Ý*/
+#define ENMAC_COMM_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 1) /*RRC²à·¢ËÍͨÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_DEDI_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 2) /*RRC²à·¢ËÍרÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_REL_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 3) /*RRC²àÇëÇóMACÊÍ·Å×ÊÔ´¡¢Í˳öÁ¬½Ó̬*/
+#define ENMAC_RESET_MAC_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 4) /*RRC²àÇëÇóMAC RESET*/
+#define ENMAC_RESUME_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5) /*RRC²àÇëÇó»Ö¸´RB*/
+#define ENMAC_SUSPEND_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6) /*RRC²àÇëÇóÔÝÍ£RB*/
+#define ENMAC_ACTIVE_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 7)
+
+
+
+#define ENMAC_CCCH_DATA_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 0) /*MAC¸æÖªRRC CCCH Êý¾Ýµ½´ï*/
+#define ENMAC_RA_PROBLEM_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 1) /*MAC¸æÖªRRC RA ÖØ´«´ÎÊý¹ý¶à*/
+#define ENMAC_RA_SUCCESS_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 2) /*MAC¸æÖªRRC RA ³É¹¦*/
+
+/*TRS--->EPHY*/
+#define EPHY_TIMER_INTERUPT_EV (DWORD)(TRS_EPHY_EVENT_BASE + 1) /* ×ÓÖ¡Öжϴ¥·¢ÏûÏ¢ */
+#define TRS_EPHY_DUPLICATE_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 2) /*TRSÏòEPHY·¢ËÍÖظ´·¢ËÍÊý¾ÝµÄÅäÖÃÏûÏ¢*/
+#define EPHY_DL_RARESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 3) /*TRSÏòEPHY·¢ËÍ RA³É¹¦Óë·ñµÄÅäÖà */
+#define EPHY_DL_CRRESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 4) /*TRSÏòEPHY·¢ËÍ CR³É¹¦Óë·ñµÄÅäÖà */
+#define TRS_EPHY_DISCARD_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 5) /*TRSÏòEPHY·¢ËÍ ¶ª°üµÄÅäÖà */
+#define TRS_EPHY_GRANT_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 6) /*TRSÏòEPHY·¢ËÍ ÊÚȨµÄÅäÖòÎÊý */
+#define TRS_EPHY_DISORDER_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 7) /*TRSÏòEPHY·¢ËÍÂÒÐò·¢Ë͵ÄÅäÖÃÏûÏ¢*/
+
+#define EPHY_ULGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 8) /*¼¤·¢ÉÏÐÐ×éÖ¡*/
+#define EPHY_DLGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 9) /*¼¤·¢ÏÂÐÐ×éÖ¡*/
+#define EPHY_GRANTARRAYCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 10) /*ÅäÖÃÉÏÏÂÐÐÊÜȨÊý×é*/
+#define EPHY_IDLE_PERIOD_REP_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 11) /*ÅäÖÿÕÏÐʱ¼ä*/
+#define EPHY_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 12) /*¹¤¾ß¶ÔEPHYµÄÅäÖÃ*/
+/* C# adaptor·¢Ë͵½ephyµÄÏûÏ¢£¬ÁÙʱ´æ·ÅÔÚÕâÀï*/
+#define TRS_FREQ_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 13)
+#define TRS_CELL_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 14)
+#define TRS_CELL_DEL_IND (DWORD)(TRS_EPHY_EVENT_BASE + 15)
+#define TRS_CELL_MOD_IND (DWORD)(TRS_EPHY_EVENT_BASE + 16)
+#define TRS_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 17) // ÉèÖÃC#ģʽ£¬0 - auto £¬ 1- manual
+#define TRS_MSG_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 18) // ÉèÖÃij¸öÏûÏ¢µÄģʽ£¬×Ô¶¯»òÊÖ¶¯
+#define EPHY_CELLINFOCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+#define EPHY_EXTGRANTCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 20)
+/*TRS--->ENMAC*/
+#define TRS_ENMAC_TA_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 1) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà TAÃüÁîÏûÏ¢ Я´øWORDÊý¾Ý£¬Îª0ʱ²»×éTA£¬·Ç0ʱ£¬Ê¹ÓøÃÖµ×éTA*/
+#define TRS_ENMAC_DRX_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 2) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà DRXÃüÁî ÏûÏ¢*/
+#define TRS_ENMAC_CCCH_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 3) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡CCCCHÊý¾Ý*/
+#define TRS_ENMAC_CRID_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 4) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡¾ºÕù½â¾öÉí·ÝÊý¾Ý£¬BIT0Ϊ1£¬
+ BIT1Ϊ0ʱ×éÖ¡·ÇÆ¥ÅäÊý¾Ý£¬ BIT0Ϊ1£¬BIT1Ϊ1ʱ£¬×éÖ¡ÕýÈ·Éí·ÝÊý¾Ý*/
+#define TRS_ENMAC_BACKOFF_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 5) /*Я´øBYTEÊý¾Ý Ôݶ¨*/
+
+#define ENMAC_MCCH_DATA_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 0 )
+#define ENRRC_ENMEL2_REL_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 1)
+#define TRS_ENMEL2_RLC_SDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 2)
+#define TRS_ENMEL2_RLC_PDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 3)
+#define TRS_ENMEL2_MSI_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 4)
+#define EUDBG_EMM_PLAIN_DL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 4)
+#define EUDBG_SEND_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 5)
+#define EUDBG_RECV_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 6)
+#define EUDBG_AM_SEND_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 7)
+#define EUDBG_AM_RECV_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 8)
+#define LTE_P_DLSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 9)
+#define LTE_P_ULSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 10)
+#define LTE_P_MAC_SR_REQ_EV (DWORD)(EUDBG_EVENT_BASE + 11)
+#define LTE_EL2_THROUGHPUT_IND_EV (DWORD)(EUDBG_EVENT_BASE + 12)
+#define LTE_EL2_STATE_IND_EV (DWORD)(EUDBG_EVENT_BASE + 13)
+#define EUDBG_EMM_PLAIN_UL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 14)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå END
+======================================================================== */
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ BEGIN
+======================================================================== */
+
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ END
+======================================================================== */
+/* ========================================================================
+ WÏà¹ØʼþºÅ START
+======================================================================== */
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRC£SCIÏûÏ¢ºÅ¶¨Òå W ÓëTD¹²ÓÃ
+======================================================================== */
+
+/* ========================================================================
+ WRRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_READ_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 0)
+#define WRRC_READ_SYSINFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 1)
+#define WRRC_READ_SYSINFO_REJ_EV (DWORD)(WRRC_EVENT_BASE + 2)
+#define WRRC_STOP_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 3)
+#define WRRC_READ_DYN_SIB_REQ_EV (DWORD)(WRRC_EVENT_BASE + 4)
+#define WRRC_READ_DYN_SIB_CNF_EV (DWORD)(WRRC_EVENT_BASE + 5)
+#define WRRC_SIB_MODIFIED_IND_EV (DWORD)(WRRC_EVENT_BASE + 6)
+#define WRRC_CELLUPDATE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 7)
+#define WRRC_CELL_RESEL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 8)
+#define WRRC_CELL_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 9)
+#define WRRC_REL_CONN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 10)
+#define WRRC_RESUME_CELL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 11)
+#define WRRC_RPLMN_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 12)
+#define WRRC_RESOURE_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 13)
+#define WRRC_RESOURCE_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 14)
+#define WRRC_UPDATE_EPLMN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 15)
+#define WRRC_HIGH_MOBILITY_IND (DWORD)(WRRC_EVENT_BASE + 16)
+#define WRRC_HO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 17)
+#define WRRC_HO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 18)
+#define WRRC_HO_TO_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 19)
+#define WRRC_HO_TO_UTRAN_CNF_EV (DWORD)(WRRC_EVENT_BASE + 20)
+#define WRRC_HO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 21)
+#define WRRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 22)
+#define WRRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 23)
+#define WRRC_CCO_TO_UTRAN_IND_EV (DWORD)(WRRC_EVENT_BASE + 24)
+#define WRRC_CCO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 25)
+#define WRRC_RADIO_LINK_FAIL_IND_EV (DWORD)(WRRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define WRRC_NEIBCELL_CHG_IND_EV (DWORD)(WRRC_EVENT_BASE + 27)
+#define WRRC_FACH_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 28)
+#define WRRC_FACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 29)
+#define WRRC_DRX_CHANGE_IND_EV (DWORD)(WRRC_EVENT_BASE + 30)
+#define WRRC_SEND_BUF_EST_REQ_EV (DWORD)(WRRC_EVENT_BASE + 31)
+#define WRRC_ABORT_RATCHG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 32)
+#define WRRC_CHG_CAMPON_TYPE_EV (DWORD)(WRRC_EVENT_BASE + 33)
+#define WRRC_GET_RF_REQ_EV (DWORD)(WRRC_EVENT_BASE + 34) /*WSIR->WCSR*/
+#define WRRC_GET_RF_CNF_EV (DWORD)(WRRC_EVENT_BASE + 35) /*WCSR->WSIR*/
+#define WRRC_SYSINFO_CONTAINER_IND_EV (DWORD)(WRRC_EVENT_BASE + 36) /*WCSR->WSIR*/
+#define WRRC_ETWS_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 37)
+#define WRRC_ETWS_CFG_END_EV (DWORD)(WRRC_EVENT_BASE + 38)
+#define WRRC_ETWS_CONTINUE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 39)
+#define WRRC_EFACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 40) /*WCMR->WRBC*/
+#define WRRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(WRRC_EVENT_BASE + 41)
+#define WRRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(WRRC_EVENT_BASE + 42)
+/* ========================================================================
+ WRLC - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWRLC_CONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 0)
+#define CWRLC_RELEASE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 1)
+#define CWRLC_SUSPEND_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 2)
+#define CWRLC_RESUME_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 3)
+#define CWRLC_CONTINUE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 4)
+#define UWRLC_DATA_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 5)
+#define CWRLC_CBS_RBCONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 6)
+#define CWRLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 7)
+
+#define CWRLC_SUSPEND_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 0)
+#define UWRLC_DATA_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 1)
+#define CWRLC_STATUS_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 2)
+#define UWRLC_DATA_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 3)
+#define CWRLC_CONFIG_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 4)
+#define CWRLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ WMAC - WRRC/WMAC - WMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWMAC_ASC_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 0)
+#define CWMAC_RACH_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 1)
+#define CWMAC_TFC_CTRL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 2)
+#define CWMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 3)
+#define CWMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 4)
+#define CWMAC_CONTINUE_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 5)
+#define CWMAC_DEL_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 6)
+#define CWMAC_RNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 7)
+#define CWMAC_ERNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 8)
+#define CWMAC_HS_RESET_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 9)
+#define CWMAC_SRB_DELAY_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 10)
+#define CWMAC_TV_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 11)
+#define CWMAC_Q_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 12)
+#define CWMAC_UE_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 13)
+#define CWMAC_TV_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 14)
+#define CWMAC_Q_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 15)
+#define CWMAC_UE_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 16)
+#define CWMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 17)
+#define CWMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 18)
+#define CWMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 19)
+#define CWMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 20)
+#define CWMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 21)
+#define CWMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 22)
+#define CWMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 23)
+#define CWMAC_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 24)
+#define CWMAC_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 25)
+
+#define CWMAC_CONFIG_CHG_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 0)
+#define CWMAC_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 1)
+#define CWMAC_EFACH_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 2)
+#define UWMAC_PCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 3)
+#define UWMAC_BCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 4)
+#define CWMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 5)
+#define CWMAC_TV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 6)
+#define CWMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 7)
+#define CWMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 8)
+#define CWMAC_Q_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 9)
+#define CWMAC_UE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 10)
+#define CWMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 11)
+/* ========================================================================
+ WMAC - UL/DL - WMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+
+/* ========================================================================
+ L1W - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1W_GSM_MEAS_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 0)
+#define L1W_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 1)
+#define L1W_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 2)
+#define L1W_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 3)
+#define L1W_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 4)
+#define L1W_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 5)
+#define L1W_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 6)
+#define L1W_GET_RF_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 7)
+#define L1W_PLMN_END_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 8)
+#define L1W_IRAT_RSRC_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 9)
+#define L1W_CM_CONFIG_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 10)
+#define L1W_CM_FALLBACK_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 11)
+#define L1W_WRRC_LEAVE3G_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 12)
+
+#define L1W_GSM_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 0)
+#define L1W_GET_RF_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 1)
+#define L1W_IRAT_RSRC_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 2)
+#define L1W_LTE_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 3)
+#define L1W_CM_FALLBACK_IND (DWORD)(L1W_WRRC_RSP_EVENT + 4)
+#define L1W_CM_OVERLAP_IND (DWORD)(L1W_WRRC_RSP_EVENT + 5)
+#define L1W_CM_INFO_IND (DWORD)(L1W_WRRC_RSP_EVENT + 6)
+/* ========================================================================
+ PDCP - WRRC ÏûÏ¢ºÅ¶¨Òå(PDCPʼþºÅ¹²ÓÃ)
+======================================================================== */
+
+/* ========================================================================
+ WRLC -WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ L1W - WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WISR_FRAME_IND_EV (DWORD)(WMAC_L1W_EVENT_BASE + 0)
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define UWRLC_PDCP_DATA_IND_EV (DWORD)(PDCP_WRLC_EVENT_BASE + 0)
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_BCH_READ_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 0)
+#define W_P_BCH_OPEN_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 1)
+#define W_P_BCH_RELEASE_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 2)
+
+#define W_P_BCH_IND_EV (DWORD)(WSIR_WPHY_RSP_EVENT + 0)
+/* ========================================================================
+ WCSR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_FREQUENCY_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 0)
+#define W_P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 1)
+#define W_P_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 2)
+#define W_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 3)
+#define W_P_CAMPON_A_CELL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 4)
+#define W_P_REL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 5)
+#define W_P_RESET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 6)
+#define W_P_SET_IRAT_MODE_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 7)
+#define W_P_RPI_SET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 8)
+#define W_P_RPI_CFG_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 9)
+
+
+#define W_P_FREQUENCY_SCAN_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 0)
+#define W_P_CELL_SEARCH_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 1)
+#define W_P_RESET_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 2)
+#define W_P_REL_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ WMCR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 0)
+#define W_P_INTER_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 1)
+#define W_P_FMO_INFO_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 2)
+#define W_P_MEAS_REL_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 3)
+
+#define W_P_INTRA_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 1)
+#define W_P_INTER_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 2)
+#define W_P_SERVCELL_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 3)
+
+
+/* ========================================================================
+ WRBC - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 0)
+#define W_P_DL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 1)
+#define W_P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 2)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 3)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_ABORT_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 4)
+#define W_P_UL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 5)
+#define W_P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 6)
+#define W_P_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 7)
+#define W_P_STOP_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 8)
+#define W_P_ADD_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 9)
+#define W_P_REL_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 10)
+#define W_P_REL_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 11)
+#define W_P_ADD_MODIFY_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 12)
+#define W_P_STOP_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 13)
+#define W_P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 14)
+#define W_P_ADD_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 15)
+#define W_P_REL_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 16)
+#define W_P_HSPA_PLUS_FACH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 17)
+#define W_P_HSPA_PLUS_PCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 18)
+#define W_P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 19)
+#define W_P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 20)
+#define W_P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 21)
+#define W_P_ADD_PRACH_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 22)
+#define W_P_DL_FDPCH_SETUP_MODIFY_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 23)
+
+
+#define W_P_IN_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 0)
+#define W_P_OUT_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 1)
+#define W_P_DPCH_SETUP_MODIFY_CNF (DWORD)(WRBC_WPHY_RSP_EVENT + 2)
+#define W_P_HSSCCH_ORDER_IND (DWORD)(WRBC_WPHY_RSP_EVENT + 3)
+
+
+
+/* ========================================================================
+ WMAC_UL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_RACH_PROCEDURE_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 0)
+#define W_P_RACH_PROCEDURE_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 1)
+#define W_P_EFACH_NO_DATA_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 2)
+#define W_P_ETFC_PARAM_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 3)
+#define W_P_POST_VERFY_FAIL_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 4)
+#define W_P_MAC_DTX_CYCLE_INFO_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 5)
+#define W_P_TFCI_CM_INFO_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 6)
+/* ========================================================================
+ WMAC_DL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 0)
+#define W_P_UE_INTERNAL_MEAS_IND_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 1)
+
+/* ========================================================================
+ L1W - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define W_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G L1W_GSM_INACT_TIME_IND_EV*/
+#define W_P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G L1W_ABORT_GSM_GAP_REQ_EV*/
+#define W_P_COMPRESS_MODE_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 3)
+#define W_P_CARD2_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 4) /*T_zW_P_card2_gap_req*/
+#define W_P_CARD2_GAP_REL_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 5) /*T_zW_P_card2_gap_rel_req*/
+#define W_P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 6) /*T_zW_P_card2_stop_gap_req*/
+#define W_P_CARD1_SUSPEND_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 7) /*T_zW_P_card1_suspend_req*/
+#define W_P_CARD1_RESUME_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 8) /*T_zW_P_card1_resume_req*/
+#define W_P_ZWPCG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 9)
+
+#define W_P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 0)
+#define W_P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 1)
+#define W_P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 2)
+#define W_P_BCH_RELEASE_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 3)
+#define W_P_CAMPON_A_CELL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 4)
+#define W_P_DPCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 5)
+#define W_P_REL_SCCPCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 6)
+#define W_P_STOP_PAGING_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 7)
+#define W_P_STOP_CBS_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 8)
+#define W_P_REL_HSDPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 9)
+#define W_P_REL_HSUPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 10)
+#define W_P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 11)
+#define W_P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 12)
+#define W_P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 13)
+#define W_P_CARD2_GAP_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 14) /*T_zW_P_card2_gap_ind*/
+#define W_P_CARD2_GAP_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 15) /*T_zW_P_card2_gap_rel_cnf*/
+#define W_P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 16) /*T_zW_P_card2_stop_gap_cnf*/
+#define W_P_CARD1_SUSPEND_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 17) /*T_zW_P_card1_suspend_cnf*/
+#define W_P_ZWPCG_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 18)
+
+
+/* ========================================================================
+ L1W ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_CHECK_RF_IND_EV (DWORD)(L1W_EVENT_BASE + 0)
+#define W_P_ACTIVE_IND_EV (DWORD)(L1W_EVENT_BASE + 1)
+#define L1W_MEAS_TIMESTAMP_IND_EV (DWORD)(L1W_EVENT_BASE + 2)
+#define L1W_MEAS_TICKTRACE_IND_EV (DWORD)(L1W_EVENT_BASE + 3)
+
+/* ========================================================================
+ WRRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WSIR_T_BCH_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 0)
+#define WSIR_T_SIB7_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 1)
+#define WSIR_T_VTSIB_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 2)
+#define WSIR_T_R_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 3)
+#define WSIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 4)
+#define WCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 5)
+#define WCSR_T_HYSTX_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 6)
+#define WCSR_T_PROTECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 7)
+#define WCSR_T_NCELL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 8)
+#define WCSR_T_OOS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 9)
+#define WCSR_T_CAMP1S_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define WCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 11)
+#define WCSR_T_REDIRECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 12)
+#define WMCR_T_RESELECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 13)
+#define WMCR_T_PERIOD_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 14)
+#define WMCR_T_TRIGGER_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 15)
+#define WMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 16)
+#define WCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 17)
+#define WCER_T_ETWS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 18)
+#define WCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 19)
+#define WRRC_T300_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 20)
+#define WRRC_T302_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 21)
+#define WRRC_T304_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 22)
+#define WRRC_T305_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 23)
+#define WRRC_T307_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 24)
+#define WRRC_T308_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 25)
+#define WRRC_T309_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 26)
+#define WRRC_T312_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 27)
+#define WRRC_T313_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 28)
+#define WRRC_T314_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 29)
+#define WRRC_T315_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 30)
+#define WRRC_T316_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 31)
+#define WRRC_T319_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 32)
+#define WRRC_T320_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 33)
+#define WMCR_T322_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 34)
+#define WRRC_T323_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 35)
+#define WRRC_T325_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 36)
+#define WRRC_T_WAIT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 37)
+
+/* ========================================================================
+ WPDCP¶¨Ê±Æ÷¶¨Òå(wÎÞÐÂÔö£¬Í¬TD)
+======================================================================== */
+
+
+/* ========================================================================
+ WRLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WRLC_T_DISCARD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 0)
+#define WRLC_T_POLL_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 1)
+#define WRLC_T_POLLPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 2)
+#define WRLC_T_POLLPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 3)
+#define WRLC_T_STATUSPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 4)
+#define WRLC_T_STATUSPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 5)
+#define WRLC_T_RESET_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 6)
+#define WRLC_T_MRW_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ WMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 0)
+#define WMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 1)
+#define WMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 2)
+#define WMAC_T_HSTIMER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 3)
+#define WMAC_T_RESET_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 4)
+#define WMAC_T_BO1_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 5)
+#define WMAC_T_TB_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 6)
+#define WMAC_T_AG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 7)
+#define WMAC_T_RG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 8)
+#define WMAC_T_SING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 9)
+#define WMAC_T_SIG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ L1W¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+/* ========================================================================
+ WSIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_WSIR_DECSIB_EV (DWORD)(WSIR_TEST_EVENT_BASE + 0)
+/* ========================================================================
+ NWRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UWRLC_DATA_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 0)
+#define TEST_UWRLC_DATA_IND_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 1)
+#define TEST_CWRLC_CONFIG_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 2)
+#define TEST_WRLC_ACK_CTRL_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NWMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_WMAC_ACK_CTRL_UTRAN_EV (DWORD)(NWMAC_EVENT_BASE + 0)
+#define TEST_WMAC_HSUPA_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 1)
+#define TEST_WMAC_HSUPA_CFG_EV (DWORD)(NWMAC_EVENT_BASE + 2)
+#define TEST_WMAC_HSUPA_SIINFO_EV (DWORD)(NWMAC_EVENT_BASE + 3)
+#define TEST_WMAC_HSUPA_HEADER_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 4)
+#define TEST_WMAC_NOTIFY_DATA_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 5)
+#define TEST_WMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 6)
+#define TEST_WMAC_CRC_RESULT_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 7)
+#define TEST_UWMAC_DATA_IND_EV (DWORD)(NWMAC_EVENT_BASE + 8)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 0)
+#define WRRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 1)
+#define WRRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 2)
+#define WRRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 3)
+#define WRRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 4)
+#define WRRC_FUNC_READ_SIB_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 5)
+#define WRRC_FUNC_READ_SIB_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 6)
+#define WRRC_FUNC_SER_CELL_IND_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 7)
+#define WRRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 8)
+#define WRRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 9)
+#define WRRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 10)
+#define WRRC_FUNC_START_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 11)
+#define WRRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 12)
+#define WRRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 13)
+#define WRRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 14)
+#define WRRC_FUNC_STOP_SYSINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 15)
+#define WRRC_FUNC_CFG_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 16)
+#define WRRC_FUNC_CFG_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 17)
+#define WRRC_FUNC_REL_FACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 18)
+#define WRRC_FUNC_REL_FACH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 19)
+#define WRRC_FUNC_REL_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 20)
+#define WRRC_FUNC_REL_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 21)
+#define WRRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 22)
+#define WRRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 23)
+#define WRRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 24)
+#define WRRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 25)
+#define WRRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 26)
+#define WRRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 27)
+#define WRRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 28)
+#define WRRC_FUNC_READ_CGIINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 29)
+/* ========================================================================
+ RRCº¯ÊýÖµ¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define RRC_FUNC_GET_TICK_COUNT_EV (DWORD)(RRC_FUNC_TRACE_BASE + 0)
+#define RRC_FUNC_GET_NV_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 1)
+#define RRC_FUNC_GET_UICC_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 2)
+#define RRC_FUNC_GET_PLMN_TYPE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 3)
+#define RRC_FUNC_GET_3A_THREOLD_EV (DWORD)(RRC_FUNC_TRACE_BASE + 4)
+#define RRC_FUNC_GET_PSLOCI_INFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 5)
+#define RRC_FUNC_GET_COUNTC_EV (DWORD)(RRC_FUNC_TRACE_BASE + 6)
+#define RRC_FUNC_GET_MASTER_MODE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 7)
+#define RRC_FUNC_GET_SFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 8)
+#define RRC_FUNC_GET_CFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 9)
+#define RRC_FUNC_GET_AMDLPDU_SIZE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 10)
+#define RRC_FUNC_GET_SIB7_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 11)
+#define RRC_FUNC_GET_VTSIB_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 12)
+/*´òÓ¡µ±Ç°ÊÇ·ñÓÐNASÐÅÁîÕýÔÚ½øÐÐ*/
+#define RRC_FUNC_NAS_SIGNAL_PROC_EXIST_EV (DWORD)(RRC_FUNC_TRACE_BASE + 13)
+#define RRC_FUNC_GET_SRB2_UL_ACT_TIME_EV (DWORD)(RRC_FUNC_TRACE_BASE + 14)
+#define RRC_FUNC_GET_SRB2_MAX_HFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 15)
+//as comÖеÄbarÐÅÏ¢ÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define AS_FUNC_CLEARBARFREQINFO (DWORD)(RRC_FUNC_TRACE_BASE + 50)
+#define AS_FUNC_ADDTDFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 51)
+#define AS_FUNC_DELTDFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 52)
+#define AS_FUNC_CLEARBARCELLINFO (DWORD)(RRC_FUNC_TRACE_BASE + 53)
+#define AS_FUNC_ADDTDCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 54)
+#define AS_FUNC_ADDGSMCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 55)
+#define AS_FUNC_ADDWFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 56)
+#define AS_FUNC_DELWFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 57)
+#define AS_FUNC_ADDWCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 58)
+#define AS_FUNC_GETDEDIPRIOINFO (DWORD)(RRC_FUNC_TRACE_BASE + 59)
+#define AS_FUNC_GETBARINFO (DWORD)(RRC_FUNC_TRACE_BASE + 60)
+#define AS_FUNC_SETFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 61)
+#define AS_FUNC_CLEARFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 62)
+//EUSIRÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define EURRC_EUSIR_SIB1_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 63)
+#define EURRC_EUSIR_SIB2_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 64)
+#define EURRC_EUSIR_SIB5_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 65)
+/* ========================================================================
+WÏà¹ØʼþºÅ END
+======================================================================== */
+#ifdef BTRUNK_SUPPORT
+/* ESM --> TSM */
+#define TSM_ESM_DIALED_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 60)
+#define TSM_ESM_BEARER_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 61)
+
+/* TSM --> ESM */
+#define TSM_ESM_SYN_BEARSTATE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 62)
+
+
+/* TSM --> EMM */
+#define TSM_EST_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 70)
+#define TSM_EMM_DATA_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 71)
+#define TSM_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 72)
+#define TSM_LOCATIONINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 73)
+#define TSM_UMM_DETACHLTE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 74)
+
+
+/* EMM/UMM --> TSM */
+#define TSM_EST_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 80)
+#define TSM_REL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 81)
+#define TSM_EMM_ATTACHSTATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 82)
+#define TSM_EMM_DATA_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 83)
+#define TSM_UMM_PTTINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 84)
+#define TSM_EMM_LOCATIONINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 85)
+
+/*TSM->ASC*/
+#define TSM_ASC_GROUP_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 90)
+#define TSM_ASC_SCANSWITCH_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 91)
+
+/*ASC->TSM*/
+#define TSM_ASC_TGCCH_MSG_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 100)
+#define TSM_ASC_SCANGROUPINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 101)
+#define TSM_ASC_SET_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 102)
+#define TSM_ASC_REL_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 103)
+#define TSM_ASC_REL_GROUP_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 104)
+
+
+/* ========================================================================
+ TSM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TSM_TIMER_BASE (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 300)
+#define TSM_TCMEST_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 1)
+#define TSM_T8001_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 2)
+#define TSM_T8003_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 3)
+#define TSM_T8005_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 4)
+#define TSM_T8006_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 5)
+#define TSM_T8011_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 6)
+#define TSM_T8012_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 7)
+#define TSM_T8014_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 8)
+#define TSM_T8016_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 9)
+#define TSM_T8018_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 10)
+#define TSM_T8020_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 11)
+#define TSM_TPERIOD_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 12)
+#define TSM_TGPS_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 13)
+#define TSM_T8123_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 14)
+#define TSM_TREGRETRY_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 15)
+#define TSM_TCONFIRM_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 16)
+#define TSM_T8125_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 17)
+#define TSM_T8026_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 18)
+/**************************************************PS LTE BTRUNK msg range end********************************************************/
+#endif
+
+/* LPP-ECIDʼþºÅ¶¨Ò壬¹²¼Æ50¸ö */
+
+/* LPP --> ASC */
+#define LPP_ASC_ECID_MEAS_START_EV (DWORD)(LPP_ECID_EVENT_BASE + 0)
+#define LPP_ASC_ECID_MEAS_ABORT_EV (DWORD)(LPP_ASC_ECID_MEAS_START_EV + 1)
+/* LPP --> EURRC */
+#define ASC_EUCSR_ECID_MEAS_START_EV (DWORD)(LPP_ASC_ECID_MEAS_ABORT_EV + 1)
+#define ASC_EUCSR_ECID_MEAS_ABORT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_START_EV + 1)
+/* EURRC --> ASC */
+#define EURRC_ASC_ECID_MEAS_RESULT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_ABORT_EV + 1)
+/* ASC --> LPP */
+#define ASC_LPP_ECID_MEAS_RESULT_EV (DWORD)(EURRC_ASC_ECID_MEAS_RESULT_EV + 1)
+/* SS --> LPP */
+#define SS_LPP_MOLR_START_IND_EV (DWORD)(ASC_LPP_ECID_MEAS_RESULT_EV + 1)
+#define SS_LPP_MOLR_END_IND_EV (DWORD)(SS_LPP_MOLR_START_IND_EV + 1)
+#define SS_LPP_MTLR_START_IND_EV (DWORD)(SS_LPP_MOLR_END_IND_EV + 1)
+#define SS_LPP_MTLR_END_IND_EV (DWORD)(SS_LPP_MTLR_START_IND_EV + 1)
+/* UMM -->LPP */
+#define UMM_LPP_CELLCHG_IND_EV (DWORD)(SS_LPP_MTLR_END_IND_EV + 1)
+/* LPP TIMER EXPIRY EVENT */
+#define LPP_TRIRPT_TIMER_EXP_EV (DWORD)(UMM_LPP_CELLCHG_IND_EV + 1)
+#define LPP_RETRANS_TIMER_EXP_EV (DWORD)(LPP_TRIRPT_TIMER_EXP_EV + 1)
+#define LPP_MSG_TRACE_LOG_EV (DWORD)(LPP_RETRANS_TIMER_EXP_EV + 1)
+
+#endif /* PS_EVENTDEF_H */
+