[Feature][T106_eSDK]17.09(SDK4.8)diff_19.00(SDK5.0)
Only Configure: No
Affected branch: master
Affected module: unknow
Is it affected on both ZXIC and MTK: only ZXIC
Self-test: Yes
Doc Update: No
Change-Id: I768f6d42285f04acf919b9f8f6cd34af460c3ef4
diff --git a/upstream/linux-5.10/drivers/mfd/zx234290-core.c b/upstream/linux-5.10/drivers/mfd/zx234290-core.c
new file mode 100755
index 0000000..d43085f
--- /dev/null
+++ b/upstream/linux-5.10/drivers/mfd/zx234290-core.c
@@ -0,0 +1,680 @@
+/*
+ * zx234290-core.c -- Device access for ZX234290 PMICs
+ *
+ * Copyright 2016 ZTE Inc.
+ *
+ * Author: yuxiang<yu.xiang5@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/zx234290.h>
+
+#include <linux/debugfs.h>
+#include <asm/uaccess.h>
+
+#include <linux/of_gpio.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/delay.h>
+#include <dma_cfg.h>
+#include <linux/reboot.h>
+
+
+#define USER_RST_TO_NORMAL 1
+
+//#include <mach/peri_cfg.h>
+extern int zx234290_i2c_write_simple(u8 reg, void *src);
+extern int zx234290_i2c_read_simple(u8 reg, void *dest);
+
+//void __iomem * s_poweron_type_addr;
+ unsigned long s_poweron_type_addr;
+
+/*the power on info, boot_reason */
+typedef enum
+{
+ POWER_ON_NORMAL = 0,
+ POWER_ON_FOTA,
+ POWER_ON_CHARGING,
+ POWER_ON_RTC,
+ POWER_ON_RESET,
+ POWER_ON_HDT_TEST,
+ POWER_ON_EXCEPTRESET,
+ POWER_ON_LOCALUPDATE,
+ POWER_ON_BOOST_IN,
+ POWER_ON_AMT,
+ POWER_ON_PRODUCTION,
+ POWER_ON_INVALID,
+}T_ZDrvSys_PowerOn_Type;
+
+static struct resource regulator_resources[] = {
+ {
+ .name = "bulk-error",
+ .start = ZX234290_INT_BUCK_FAUL,
+ .end = ZX234290_INT_BUCK_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "ldo_error",
+ .start = ZX234290_INT_LDO_FAUL,
+ .end = ZX234290_INT_LDO_FAUL,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource rtc_resources[] = {
+ {
+ .name = "zx234290-rtc-alarm",
+ .start = ZX234290_INT_RTC_ALRM,
+ .end = ZX234290_INT_RTC_ALRM,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-min",
+ .start = ZX234290_INT_RTC_MIN,
+ .end = ZX234290_INT_RTC_MIN,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "zx234290-rtc-hour",
+ .start = ZX234290_INT_RTC_HOUR,
+ .end = ZX234290_INT_RTC_HOUR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct resource powerkey_resources[] = {
+ {
+ .name = "zx234290-pwrkey-int",
+ .start = ZX234290_INT_PWRON,
+ .end = ZX234290_INT_PWRON,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+static struct mfd_cell zx234290_cell[] = {
+ {
+ .name = "zx234290-regulators",
+ .num_resources = 2,
+ .resources = ®ulator_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-rtc",
+ .num_resources = 3,
+ .resources = &rtc_resources[0],
+ .id = -1,
+ },
+ {
+ .name = "zx234290-gpadc",
+ },
+ {
+ .name = "zx234290-powerkey",
+ .num_resources = 1,
+ .resources = &powerkey_resources[0],
+ .id = -1,
+ },
+};
+
+unsigned int boot_reason = POWER_ON_NORMAL;
+struct wakeup_source * adc_wakelock;
+
+unsigned int * get_boot_reason_addr(void)
+{
+ return (unsigned int *)s_poweron_type_addr;
+}
+EXPORT_SYMBOL(get_boot_reason_addr);
+
+static void get_boot_reason(void)
+{
+ //boot_reason = *(unsigned int *)POWERON_TYPE_BASE;
+ if(s_poweron_type_addr){
+ boot_reason = readl(s_poweron_type_addr/*+0xf8*/);
+
+ printk(KERN_INFO "[PMU] get boot_reason = %d from 0x%x.\n",boot_reason,s_poweron_type_addr);
+ }
+ else
+ printk(KERN_INFO "[PMU] boot_reason is unknown.\n");
+}
+
+#if 1
+int zx234290_set_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data |= mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_set_bits);
+
+int zx234290_clear_bits(struct zx234290 *zx234290, u8 reg, u8 mask)
+{
+ u8 data;
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+ err = zx234290->read(zx234290, reg, 1, &data);
+ if (err) {
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+ goto out;
+ }
+
+ data &= ~mask;
+ err = zx234290->write(zx234290, reg, 1, &data);
+ if (err)
+ dev_err(zx234290->dev, "Write to reg 0x%x failed\n", reg);
+
+out:
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_clear_bits);
+#endif
+
+static inline int zx234290_read(struct zx234290 *zx234290, u8 reg)
+{
+ u8 val;
+ int err;
+
+ err = zx234290->read(zx234290, reg, 1, &val);
+ if (err < 0)
+ return err;
+
+ return val;
+}
+
+static inline int zx234290_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ return zx234290->write(zx234290, reg, 1, &val);
+}
+
+#if 1
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg)
+{
+ int data;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ data = zx234290_read(zx234290, reg);
+ if (data < 0)
+ dev_err(zx234290->dev, "Read from reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return data;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_read);
+
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val)
+{
+ int err;
+
+ mutex_lock(&zx234290->io_mutex);
+
+ err = zx234290_write(zx234290, reg, val);
+ if (err < 0)
+ dev_err(zx234290->dev, "Write for reg 0x%x failed\n", reg);
+
+ mutex_unlock(&zx234290->io_mutex);
+ return err;
+}
+EXPORT_SYMBOL_GPL(zx234290_reg_write);
+#endif
+#if 1
+extern int Zx234290_SetUserReg_PSM(unsigned char data);
+
+void zx29_restart(const char * cmd)
+{
+ /*set reset value = 1*/
+ unsigned char status = ZX234290_USER_RST_TO_NORMAL;
+
+ printk(KERN_INFO"restart:enter reboot :reset to normal\n");
+
+ status = ZX234290_USER_RST_TO_NORMAL;
+ Zx234290_SetUserReg_PSM(status);
+}
+
+
+int pmu_reboot_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+
+ printk(" pmu reboot,in user,task is: %s\n", current->comm);
+ zx29_restart((char *) ptr);
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block pmu_reboot_notifier = {
+ .notifier_call = pmu_reboot_event
+};
+
+#endif
+
+
+
+int Zx234290_SetVldo6Onoff(void)
+{
+ int ret = 0;
+ u8 reg_addr=0, reg_val=0;
+ reg_addr = 0x21;
+ ret = zx234290_i2c_read_simple(reg_addr,®_val);
+ if (ret) {
+ return -EIO;
+ }
+ reg_val = reg_val&(~(1<<5));
+ ret = zx234290_i2c_write_simple(reg_addr, ®_val);
+ if (ret) {
+ return -EIO;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(Zx234290_SetVldo6Onoff);
+#if 0
+int zx297510_write_pmu_flag_charging(void)
+{
+ int ret = 0;
+ unsigned char reg = 0;
+ ret = zx234290_i2c_read_simple(0xf, ®);
+ reg = reg|0xff;
+ ret += zx234290_i2c_write_simple(0xf, ®);
+ ret = zx234290_i2c_read_simple(0xe, ®);
+ reg = reg|0x3;
+ ret += zx234290_i2c_write_simple(0xe, ®);
+ return ret;
+}
+#endif
+//static void __iomem* PMU_ADDR_VIR;
+//#define GPIO_PMU_PSHOLD ZX29_GPIO_51
+unsigned int gpio_num_pshold;
+
+void zx234290_pshold_pull_down(void)
+{
+ //PMU_ADDR_VIR = ioremap(0x10d6c0,4);
+ //__raw_writel(0x0,PMU_ADDR_VIR);
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,0);
+ else
+ printk("zx234290_pshold_pull_down error\n");
+}
+
+//extern int zx234290_rtc_disable_timer_alarm();
+EXPORT_SYMBOL(zx234290_pshold_pull_down);
+
+/***********yuwei added at 20170523**************/
+void zx234290_pshold_pull_up(void)
+{
+ if(gpio_num_pshold)
+ gpio_direction_output(gpio_num_pshold,1);
+ else
+ printk("zx234290_pshold_pull_up error\n");
+}
+/**************/
+
+static int zx234290_set_softon(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+static int zx234290_set_softon_PSM(int on)
+{
+ u8 reg = 0;
+ int ret;
+
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+
+ if ((reg >> ZX234290_SOFTON_LSH) != on) {
+ reg ^= (0x01 << ZX234290_SOFTON_LSH);
+ ret = zx234290_i2c_write_simple_PSM(ZX234290_REG_ADDR_SYS_CTRL, ®);
+ if (ret) {
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+
+static bool debug_stop_poweroff = false;
+module_param(debug_stop_poweroff, bool, 0644);
+//extern void zx29_restart(char str,const char * cmd);
+static void zx234290_power_off(void)
+{
+ //void __iomem *reset_charging_reg;
+ //reset_charging_reg = ZX29_TOP_VA;
+ //zx234290_rtc_disable_timer_alarm();
+ //Zx234290_SetVldo6Onoff();
+ u8 reg_poweron = 0;
+ int ret;
+
+ if(debug_stop_poweroff )
+ {
+ printk(KERN_INFO"debug_stop_poweroff= 0x%x, for debug, bug_on!!!!\n", debug_stop_poweroff);
+ panic("poweroff");
+ }
+ zx234290_set_softon_PSM(0);
+ zx234290_pshold_pull_down();
+#if 1
+ while(1){
+ ret = zx234290_i2c_read_simple_PSM(ZX234290_REG_ADDR_STSA, ®_poweron);
+ if (ret) {
+ printk(KERN_INFO"power off pmu i2c read err\n");
+ break;
+ }
+ if((reg_poweron&(1<<ZX234290_STATUSA_POWERON_LSH))== 0)
+ break;
+ }
+ mdelay(50);
+ /*reset to charging*/
+ //zx29_restart(NULL,"drv_key reboot");
+#endif
+}
+
+
+#if defined(CONFIG_DEBUG_FS)
+static ssize_t debugfs_regs_write(struct file *file, const char __user *buf,size_t nbytes, loff_t *ppos)
+{
+ struct zx234290 *zx234290 = file->private_data;
+
+ unsigned int val1, val2;
+ u8 reg, value;
+ int ret;
+ char *kern_buf;
+
+ kern_buf = kzalloc(nbytes, GFP_KERNEL);
+
+ if (!kern_buf) {
+ printk(KERN_INFO "zx234290-core: Failed to allocate buffer\n");
+ return -ENOMEM;
+ }
+
+ if (copy_from_user(kern_buf, (void __user *)buf, nbytes)) {
+ kfree(kern_buf);
+ return -ENOMEM;
+ }
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, kern_buf,nbytes);
+
+ ret = sscanf(kern_buf, "%x:%x", &val1, &val2);
+ if (ret < 2 || val1 > ZX234290_MAX_REGISTER ) {
+ printk(KERN_INFO "zx234290-core: failed to read user buf, ret=%d, input 0x%x:0x%x\n",
+ ret, val1, val2);
+ kfree(kern_buf);
+ return -EINVAL;
+ }
+ kfree(kern_buf);
+
+ reg = val1 & 0xff;
+ value = val2 & 0xff;
+ printk(KERN_INFO "%s input %x,%x; reg=%x,value=%x\n", __func__, val1, val2, reg, value);
+ ret = zx234290_i2c_write_simple(reg, &value);
+
+ return ret ? ret : nbytes;
+}
+
+static int debugfs_regs_show(struct seq_file *s, void *v)
+{
+ int i;
+ u8 value[ZX234290_MAX_REGISTER];
+ int ret=0;
+ u8 reg_rtc_ctrl2 = 0;
+
+ printk(KERN_INFO "%s\n", __func__);
+ memset(value, 0, sizeof(value));
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++){
+ ret = zx234290_i2c_read_simple(i, &(value[i]));
+ if(ret){
+ printk(KERN_INFO "%s err=%d, break\n", __func__, ret);
+ seq_printf(s, "%s err=%d, break", __func__, ret);
+ return ret;
+ }
+ }
+
+ for (i = 0; i < ZX234290_MAX_REGISTER; i++) {
+ if((i+1)%9 == 0)
+ seq_printf(s, "\n");
+
+ seq_printf(s, "[0x%x]%02x ", i, value[i]);
+ }
+
+ reg_rtc_ctrl2 = value[ZX234290_REG_ADDR_RTC_CTRL2];
+ seq_printf(s, "\nAF=%d,TF=%d,Alarm %s,Timer %s\n",(reg_rtc_ctrl2&0x8),(reg_rtc_ctrl2&0x4),
+ (reg_rtc_ctrl2&0x2)? "enable":"disable",(reg_rtc_ctrl2&0x1)? "enable":"disable");
+ if(value[ZX234290_REG_ADDR_BUCK_FAULT_STATUS]||value[ZX234290_REG_ADDR_LDO_FAULT_STATUS])
+ seq_printf(s, "ldo or bulk fault!!!!!\n ");
+ else
+ seq_printf(s, "no ldo or bulk fault\n ");
+ if(value[ZX234290_REG_ADDR_TIMER_CTRL]&0x80)
+ seq_printf(s, "timer enable\n ");
+ else
+ seq_printf(s, "timer disable\n ");
+
+
+ return ret;
+}
+
+#define DEBUGFS_FILE_ENTRY(name) \
+static int debugfs_##name##_open(struct inode *inode, struct file *file) \
+{\
+return single_open(file, debugfs_##name##_show, inode->i_private); \
+}\
+\
+static const struct file_operations debugfs_##name##_fops = { \
+.owner= THIS_MODULE, \
+.open= debugfs_##name##_open, \
+.write=debugfs_##name##_write, \
+.read= seq_read, \
+.llseek= seq_lseek, \
+.release= single_release, \
+}
+
+DEBUGFS_FILE_ENTRY(regs);
+
+int zx234290_rtc_settimer(int sec);
+
+static int debugfs_adc_get(void *data, u64 *val)
+{
+ switch ((int)data) {
+ case 0:
+ *val = get_battery_voltage();
+ //zx234290_rtc_settimer(10);
+ break;
+ case 1:
+ *val = get_adc1_voltage();
+ break;
+ case 2:
+ *val = get_adc2_voltage();
+ break;
+ default:
+ *val = -1;
+ break;
+ }
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fops_adc_ro, debugfs_adc_get, NULL, "%llumV\n");
+
+static struct dentry *g_pmu_root;
+
+extern u32 int_irq_times;
+extern u32 int_thread_times;
+
+static void debugfs_pmu_init(struct zx234290 *zx234290)
+{
+ struct dentry *root;
+ struct dentry *node;
+ int i;
+
+ if(!zx234290)
+ return;
+ //create root
+ root = debugfs_create_dir("pmu_zx29", NULL);
+ if (!root){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(root));
+ goto err;
+ }
+ //print regs;
+ node = debugfs_create_file("regs", S_IRUGO | S_IWUGO, root, zx234290, &debugfs_regs_fops);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc0;
+ node = debugfs_create_file("adc0", S_IRUGO, root, 0, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc1;
+ node = debugfs_create_file("adc1", S_IRUGO, root, 1, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print adc2;
+ node = debugfs_create_file("adc2", S_IRUGO, root, 2, &fops_adc_ro);
+ if (!node){
+ dev_err(zx234290->dev, "debugfs_create_dir err=%d\n", IS_ERR(node));
+ goto err;
+ }
+ //print u32
+ debugfs_create_u32("irq_cnt", S_IRUGO, root, &int_irq_times);
+
+ //print u32
+ debugfs_create_u32("thread_cnt", S_IRUGO, root, &int_thread_times);
+
+ g_pmu_root = (void *)root;
+ return;
+err:
+ dev_err(zx234290->dev, "debugfs_pmu_init err\n");
+}
+
+#endif
+
+
+int zx234290_device_init(struct zx234290 *zx234290)
+{
+ //struct zx234290_board *pmic_plat_data = zx234290->dev->platform_data;
+ enum of_gpio_flags flags;
+ //struct zx234290_platform_data *init_data;
+ int ret;
+ int irq;
+
+ s_poweron_type_addr = (unsigned long)ioremap(POWERON_TYPE_ADDR,0x800);
+ get_boot_reason();
+ /*
+ init_data = kzalloc(sizeof(struct zx234290_platform_data), GFP_KERNEL);
+ if (init_data == NULL)
+ return -ENOMEM;
+ */
+ mutex_init(&zx234290->io_mutex);
+ dev_set_drvdata(zx234290->dev, zx234290);
+
+ ret = mfd_add_devices(zx234290->dev, -1,
+ zx234290_cell, ARRAY_SIZE(zx234290_cell),
+ NULL,0, 0);
+ if (ret < 0)
+ goto err;
+
+ gpio_num_pshold= of_get_gpio_flags(zx234290->dev->of_node, 0, &flags);
+ if (!gpio_is_valid(gpio_num_pshold)) {
+ pr_info("pmu pshold error\n");
+ }
+ gpio_direction_input(gpio_num_pshold);
+
+ //gpio_num_pshold = pmic_plat_data->pshold_gpio_num;//by yuxiang
+ // gpio_func_pshold= pmic_plat_data->pshold_gpio_func;//by yuxiang
+ if (!pm_power_off)
+ pm_power_off = zx234290_power_off;
+
+#ifdef PSHOLD_PULLUP_IN_POWEROFFCHARGING
+ /* CPE MDL don't control ps_hold pin. */
+ if (boot_reason == POWER_ON_CHARGING) {
+ zx234290_pshold_pull_up();
+ }
+#endif
+/***********PJT added **************/
+ zx234290_get_chip_version();
+ adc_wakelock = wakeup_source_register(NULL, "adc_wake");
+ if (!adc_wakelock)
+ return -ENOMEM;
+
+ //init_data->irq = pmic_plat_data->irq;
+ //init_data->irq_base = pmic_plat_data->irq_base;
+ //irq = gpio_to_irq(pmic_plat_data->irq_gpio_num);
+ ret = zx234290_irq_init(zx234290);
+ if (ret < 0)
+ goto err;
+
+ register_reboot_notifier(&pmu_reboot_notifier);
+
+#if defined(CONFIG_DEBUG_FS)
+ debugfs_pmu_init(zx234290);
+#endif
+ //kfree(init_data);
+ return ret;
+
+err:
+ //kfree(init_data);
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+ return ret;
+}
+
+void zx234290_device_exit(struct zx234290 *zx234290)
+{
+#if defined(CONFIG_DEBUG_FS)
+ if(g_pmu_root){
+ printk(KERN_INFO "zx234290_device_exit:debugfs_remove_recursive \n");
+ debugfs_remove_recursive(g_pmu_root);
+ }
+#endif
+ mfd_remove_devices(zx234290->dev);
+ kfree(zx234290);
+}
+
+
+MODULE_AUTHOR("yuxiang");
+MODULE_DESCRIPTION("ZX234290 chip family multi-function driver");
+MODULE_LICENSE("GPL");
diff --git a/upstream/linux-5.10/drivers/mtd/mtdcore.c b/upstream/linux-5.10/drivers/mtd/mtdcore.c
new file mode 100755
index 0000000..a52a2c8
--- /dev/null
+++ b/upstream/linux-5.10/drivers/mtd/mtdcore.c
@@ -0,0 +1,2257 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Core registration and callback routines for MTD
+ * drivers and users.
+ *
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
+ * Copyright © 2006 Red Hat UK Limited
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ptrace.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/major.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/ioctl.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/proc_fs.h>
+#include <linux/idr.h>
+#include <linux/backing-dev.h>
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/reboot.h>
+#include <linux/leds.h>
+#include <linux/debugfs.h>
+#include <linux/nvmem-provider.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include "mtdcore.h"
+
+struct backing_dev_info *mtd_bdi;
+
+#ifdef CONFIG_PM_SLEEP
+
+static int mtd_cls_suspend(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return mtd ? mtd_suspend(mtd) : 0;
+}
+
+static int mtd_cls_resume(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ if (mtd)
+ mtd_resume(mtd);
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mtd_cls_pm_ops, mtd_cls_suspend, mtd_cls_resume);
+#define MTD_CLS_PM_OPS (&mtd_cls_pm_ops)
+#else
+#define MTD_CLS_PM_OPS NULL
+#endif
+
+static struct class mtd_class = {
+ .name = "mtd",
+ .owner = THIS_MODULE,
+ .pm = MTD_CLS_PM_OPS,
+};
+
+static DEFINE_IDR(mtd_idr);
+
+/* These are exported solely for the purpose of mtd_blkdevs.c. You
+ should not use them for _anything_ else */
+DEFINE_MUTEX(mtd_table_mutex);
+EXPORT_SYMBOL_GPL(mtd_table_mutex);
+
+struct mtd_info *__mtd_next_device(int i)
+{
+ return idr_get_next(&mtd_idr, &i);
+}
+EXPORT_SYMBOL_GPL(__mtd_next_device);
+
+static LIST_HEAD(mtd_notifiers);
+
+
+#define MTD_DEVT(index) MKDEV(MTD_CHAR_MAJOR, (index)*2)
+
+/* REVISIT once MTD uses the driver model better, whoever allocates
+ * the mtd_info will probably want to use the release() hook...
+ */
+static void mtd_release(struct device *dev)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ dev_t index = MTD_DEVT(mtd->index);
+
+ /* remove /dev/mtdXro node */
+ device_destroy(&mtd_class, index + 1);
+}
+
+static ssize_t mtd_type_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ char *type;
+
+ switch (mtd->type) {
+ case MTD_ABSENT:
+ type = "absent";
+ break;
+ case MTD_RAM:
+ type = "ram";
+ break;
+ case MTD_ROM:
+ type = "rom";
+ break;
+ case MTD_NORFLASH:
+ type = "nor";
+ break;
+ case MTD_NANDFLASH:
+ type = "nand";
+ break;
+ case MTD_DATAFLASH:
+ type = "dataflash";
+ break;
+ case MTD_UBIVOLUME:
+ type = "ubi";
+ break;
+ case MTD_MLCNANDFLASH:
+ type = "mlc-nand";
+ break;
+ default:
+ type = "unknown";
+ }
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", type);
+}
+static DEVICE_ATTR(type, S_IRUGO, mtd_type_show, NULL);
+
+static ssize_t mtd_flags_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "0x%lx\n", (unsigned long)mtd->flags);
+}
+static DEVICE_ATTR(flags, S_IRUGO, mtd_flags_show, NULL);
+
+static ssize_t mtd_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%llu\n",
+ (unsigned long long)mtd->size);
+}
+static DEVICE_ATTR(size, S_IRUGO, mtd_size_show, NULL);
+
+static ssize_t mtd_erasesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize);
+}
+static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL);
+
+static ssize_t mtd_writesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->writesize);
+}
+static DEVICE_ATTR(writesize, S_IRUGO, mtd_writesize_show, NULL);
+
+static ssize_t mtd_subpagesize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int subpagesize = mtd->writesize >> mtd->subpage_sft;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", subpagesize);
+}
+static DEVICE_ATTR(subpagesize, S_IRUGO, mtd_subpagesize_show, NULL);
+
+static ssize_t mtd_oobsize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->oobsize);
+}
+static DEVICE_ATTR(oobsize, S_IRUGO, mtd_oobsize_show, NULL);
+
+static ssize_t mtd_oobavail_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->oobavail);
+}
+static DEVICE_ATTR(oobavail, S_IRUGO, mtd_oobavail_show, NULL);
+
+static ssize_t mtd_numeraseregions_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->numeraseregions);
+}
+static DEVICE_ATTR(numeraseregions, S_IRUGO, mtd_numeraseregions_show,
+ NULL);
+
+static ssize_t mtd_name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%s\n", mtd->name);
+}
+static DEVICE_ATTR(name, S_IRUGO, mtd_name_show, NULL);
+
+static ssize_t mtd_ecc_strength_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_strength);
+}
+static DEVICE_ATTR(ecc_strength, S_IRUGO, mtd_ecc_strength_show, NULL);
+
+static ssize_t mtd_bitflip_threshold_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->bitflip_threshold);
+}
+
+static ssize_t mtd_bitflip_threshold_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ unsigned int bitflip_threshold;
+ int retval;
+
+ retval = kstrtouint(buf, 0, &bitflip_threshold);
+ if (retval)
+ return retval;
+
+ mtd->bitflip_threshold = bitflip_threshold;
+ return count;
+}
+static DEVICE_ATTR(bitflip_threshold, S_IRUGO | S_IWUSR,
+ mtd_bitflip_threshold_show,
+ mtd_bitflip_threshold_store);
+
+static ssize_t mtd_ecc_step_size_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_step_size);
+
+}
+static DEVICE_ATTR(ecc_step_size, S_IRUGO, mtd_ecc_step_size_show, NULL);
+
+static ssize_t mtd_ecc_stats_corrected_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->corrected);
+}
+static DEVICE_ATTR(corrected_bits, S_IRUGO,
+ mtd_ecc_stats_corrected_show, NULL);
+
+static ssize_t mtd_ecc_stats_errors_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->failed);
+}
+static DEVICE_ATTR(ecc_failures, S_IRUGO, mtd_ecc_stats_errors_show, NULL);
+
+static ssize_t mtd_badblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->badblocks);
+}
+static DEVICE_ATTR(bad_blocks, S_IRUGO, mtd_badblocks_show, NULL);
+
+static ssize_t mtd_bbtblocks_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct mtd_ecc_stats *ecc_stats = &mtd->ecc_stats;
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stats->bbtblocks);
+}
+static DEVICE_ATTR(bbt_blocks, S_IRUGO, mtd_bbtblocks_show, NULL);
+
+static struct attribute *mtd_attrs[] = {
+ &dev_attr_type.attr,
+ &dev_attr_flags.attr,
+ &dev_attr_size.attr,
+ &dev_attr_erasesize.attr,
+ &dev_attr_writesize.attr,
+ &dev_attr_subpagesize.attr,
+ &dev_attr_oobsize.attr,
+ &dev_attr_oobavail.attr,
+ &dev_attr_numeraseregions.attr,
+ &dev_attr_name.attr,
+ &dev_attr_ecc_strength.attr,
+ &dev_attr_ecc_step_size.attr,
+ &dev_attr_corrected_bits.attr,
+ &dev_attr_ecc_failures.attr,
+ &dev_attr_bad_blocks.attr,
+ &dev_attr_bbt_blocks.attr,
+ &dev_attr_bitflip_threshold.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(mtd);
+
+static const struct device_type mtd_devtype = {
+ .name = "mtd",
+ .groups = mtd_groups,
+ .release = mtd_release,
+};
+
+static int mtd_partid_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partid);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partid_debug);
+
+static int mtd_partname_debug_show(struct seq_file *s, void *p)
+{
+ struct mtd_info *mtd = s->private;
+
+ seq_printf(s, "%s\n", mtd->dbg.partname);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mtd_partname_debug);
+
+static struct dentry *dfs_dir_mtd;
+
+static void mtd_debugfs_populate(struct mtd_info *mtd)
+{
+ struct device *dev = &mtd->dev;
+ struct dentry *root;
+
+ if (IS_ERR_OR_NULL(dfs_dir_mtd))
+ return;
+
+ root = debugfs_create_dir(dev_name(dev), dfs_dir_mtd);
+ mtd->dbg.dfs_dir = root;
+
+ if (mtd->dbg.partid)
+ debugfs_create_file("partid", 0400, root, mtd,
+ &mtd_partid_debug_fops);
+
+ if (mtd->dbg.partname)
+ debugfs_create_file("partname", 0400, root, mtd,
+ &mtd_partname_debug_fops);
+}
+
+#ifndef CONFIG_MMU
+unsigned mtd_mmap_capabilities(struct mtd_info *mtd)
+{
+ switch (mtd->type) {
+ case MTD_RAM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ | NOMMU_MAP_WRITE;
+ case MTD_ROM:
+ return NOMMU_MAP_COPY | NOMMU_MAP_DIRECT | NOMMU_MAP_EXEC |
+ NOMMU_MAP_READ;
+ default:
+ return NOMMU_MAP_COPY;
+ }
+}
+EXPORT_SYMBOL_GPL(mtd_mmap_capabilities);
+#endif
+
+static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
+ void *cmd)
+{
+ struct mtd_info *mtd;
+
+ mtd = container_of(n, struct mtd_info, reboot_notifier);
+ mtd->_reboot(mtd);
+
+ return NOTIFY_DONE;
+}
+
+/**
+ * mtd_wunit_to_pairing_info - get pairing information of a wunit
+ * @mtd: pointer to new MTD device info structure
+ * @wunit: write unit we are interested in
+ * @info: returned pairing information
+ *
+ * Retrieve pairing information associated to the wunit.
+ * This is mainly useful when dealing with MLC/TLC NANDs where pages can be
+ * paired together, and where programming a page may influence the page it is
+ * paired with.
+ * The notion of page is replaced by the term wunit (write-unit) to stay
+ * consistent with the ->writesize field.
+ *
+ * The @wunit argument can be extracted from an absolute offset using
+ * mtd_offset_to_wunit(). @info is filled with the pairing information attached
+ * to @wunit.
+ *
+ * From the pairing info the MTD user can find all the wunits paired with
+ * @wunit using the following loop:
+ *
+ * for (i = 0; i < mtd_pairing_groups(mtd); i++) {
+ * info.pair = i;
+ * mtd_pairing_info_to_wunit(mtd, &info);
+ * ...
+ * }
+ */
+int mtd_wunit_to_pairing_info(struct mtd_info *mtd, int wunit,
+ struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int npairs = mtd_wunit_per_eb(master) / mtd_pairing_groups(master);
+
+ if (wunit < 0 || wunit >= npairs)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_info)
+ return master->pairing->get_info(master, wunit, info);
+
+ info->group = 0;
+ info->pair = wunit;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_wunit_to_pairing_info);
+
+/**
+ * mtd_pairing_info_to_wunit - get wunit from pairing information
+ * @mtd: pointer to new MTD device info structure
+ * @info: pairing information struct
+ *
+ * Returns a positive number representing the wunit associated to the info
+ * struct, or a negative error code.
+ *
+ * This is the reverse of mtd_wunit_to_pairing_info(), and can help one to
+ * iterate over all wunits of a given pair (see mtd_wunit_to_pairing_info()
+ * doc).
+ *
+ * It can also be used to only program the first page of each pair (i.e.
+ * page attached to group 0), which allows one to use an MLC NAND in
+ * software-emulated SLC mode:
+ *
+ * info.group = 0;
+ * npairs = mtd_wunit_per_eb(mtd) / mtd_pairing_groups(mtd);
+ * for (info.pair = 0; info.pair < npairs; info.pair++) {
+ * wunit = mtd_pairing_info_to_wunit(mtd, &info);
+ * mtd_write(mtd, mtd_wunit_to_offset(mtd, blkoffs, wunit),
+ * mtd->writesize, &retlen, buf + (i * mtd->writesize));
+ * }
+ */
+int mtd_pairing_info_to_wunit(struct mtd_info *mtd,
+ const struct mtd_pairing_info *info)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+
+ if (!info || info->pair < 0 || info->pair >= npairs ||
+ info->group < 0 || info->group >= ngroups)
+ return -EINVAL;
+
+ if (master->pairing && master->pairing->get_wunit)
+ return mtd->pairing->get_wunit(master, info);
+
+ return info->pair;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_info_to_wunit);
+
+/**
+ * mtd_pairing_groups - get the number of pairing groups
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Returns the number of pairing groups.
+ *
+ * This number is usually equal to the number of bits exposed by a single
+ * cell, and can be used in conjunction with mtd_pairing_info_to_wunit()
+ * to iterate over all pages of a given pair.
+ */
+int mtd_pairing_groups(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->pairing || !master->pairing->ngroups)
+ return 1;
+
+ return master->pairing->ngroups;
+}
+EXPORT_SYMBOL_GPL(mtd_pairing_groups);
+
+static int mtd_nvmem_reg_read(void *priv, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct mtd_info *mtd = priv;
+ size_t retlen;
+ int err;
+
+ err = mtd_read(mtd, offset, bytes, &retlen, val);
+ if (err && err != -EUCLEAN)
+ return err;
+
+ return retlen == bytes ? 0 : -EIO;
+}
+
+static int mtd_nvmem_add(struct mtd_info *mtd)
+{
+ struct nvmem_config config = {};
+
+ config.id = -1;
+ config.dev = &mtd->dev;
+ config.name = dev_name(&mtd->dev);
+ config.owner = THIS_MODULE;
+ config.reg_read = mtd_nvmem_reg_read;
+ config.size = mtd->size;
+ config.word_size = 1;
+ config.stride = 1;
+ config.read_only = true;
+ config.root_only = true;
+ config.no_of_node = true;
+ config.priv = mtd;
+
+ mtd->nvmem = nvmem_register(&config);
+ if (IS_ERR(mtd->nvmem)) {
+ /* Just ignore if there is no NVMEM support in the kernel */
+ if (PTR_ERR(mtd->nvmem) == -EOPNOTSUPP) {
+ mtd->nvmem = NULL;
+ } else {
+ dev_err(&mtd->dev, "Failed to register NVMEM device\n");
+ return PTR_ERR(mtd->nvmem);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * add_mtd_device - register an MTD device
+ * @mtd: pointer to new MTD device info structure
+ *
+ * Add a device to the list of MTD devices present in the system, and
+ * notify each currently active MTD 'user' of its arrival. Returns
+ * zero on success or non-zero on failure.
+ */
+
+int add_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_notifier *not;
+ int i, error;
+
+ /*
+ * May occur, for instance, on buggy drivers which call
+ * mtd_device_parse_register() multiple times on the same master MTD,
+ * especially with CONFIG_MTD_PARTITIONED_MASTER=y.
+ */
+ if (WARN_ONCE(mtd->dev.type, "MTD already registered\n"))
+ return -EEXIST;
+
+ BUG_ON(mtd->writesize == 0);
+
+ /*
+ * MTD drivers should implement ->_{write,read}() or
+ * ->_{write,read}_oob(), but not both.
+ */
+ if (WARN_ON((mtd->_write && mtd->_write_oob) ||
+ (mtd->_read && mtd->_read_oob)))
+ return -EINVAL;
+
+ if (WARN_ON((!mtd->erasesize || !master->_erase) &&
+ !(mtd->flags & MTD_NO_ERASE)))
+ return -EINVAL;
+
+ /*
+ * MTD_SLC_ON_MLC_EMULATION can only be set on partitions, when the
+ * master is an MLC NAND and has a proper pairing scheme defined.
+ * We also reject masters that implement ->_writev() for now, because
+ * NAND controller drivers don't implement this hook, and adding the
+ * SLC -> MLC address/length conversion to this path is useless if we
+ * don't have a user.
+ */
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION &&
+ (!mtd_is_partition(mtd) || master->type != MTD_MLCNANDFLASH ||
+ !master->pairing || master->_writev))
+ return -EINVAL;
+
+ mutex_lock(&mtd_table_mutex);
+
+ i = idr_alloc(&mtd_idr, mtd, 0, 0, GFP_KERNEL);
+ if (i < 0) {
+ error = i;
+ goto fail_locked;
+ }
+
+ mtd->index = i;
+ mtd->usecount = 0;
+
+ /* default value if not set by driver */
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ int ngroups = mtd_pairing_groups(master);
+
+ mtd->erasesize /= ngroups;
+ mtd->size = (u64)mtd_div_by_eb(mtd->size, master) *
+ mtd->erasesize;
+ }
+
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+
+ mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+ mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+
+ /* Some chips always power up locked. Unlock them now */
+ if ((mtd->flags & MTD_WRITEABLE) && (mtd->flags & MTD_POWERUP_LOCK)) {
+ error = mtd_unlock(mtd, 0, mtd->size);
+ if (error && error != -EOPNOTSUPP)
+ printk(KERN_WARNING
+ "%s: unlock failed, writes may not work\n",
+ mtd->name);
+ /* Ignore unlock failures? */
+ error = 0;
+ }
+
+ /* Caller should have set dev.parent to match the
+ * physical device, if appropriate.
+ */
+ mtd->dev.type = &mtd_devtype;
+ mtd->dev.class = &mtd_class;
+ mtd->dev.devt = MTD_DEVT(i);
+ dev_set_name(&mtd->dev, "mtd%d", i);
+ dev_set_drvdata(&mtd->dev, mtd);
+ of_node_get(mtd_get_of_node(mtd));
+ error = device_register(&mtd->dev);
+ if (error)
+ goto fail_added;
+
+ /* Add the nvmem provider */
+ error = mtd_nvmem_add(mtd);
+ if (error)
+ goto fail_nvmem_add;
+
+ mtd_debugfs_populate(mtd);
+
+ device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL,
+ "mtd%dro", i);
+
+ pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name);
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+ /* We _know_ we aren't being removed, because
+ our caller is still holding us here. So none
+ of this try_ nonsense, and no bitching about it
+ either. :) */
+ __module_get(THIS_MODULE);
+ return 0;
+
+fail_nvmem_add:
+ device_unregister(&mtd->dev);
+fail_added:
+ of_node_put(mtd_get_of_node(mtd));
+ idr_remove(&mtd_idr, i);
+fail_locked:
+ mutex_unlock(&mtd_table_mutex);
+ return error;
+}
+
+/**
+ * del_mtd_device - unregister an MTD device
+ * @mtd: pointer to MTD device info structure
+ *
+ * Remove a device from the list of MTD devices present in the system,
+ * and notify each currently active MTD 'user' of its departure.
+ * Returns zero on success or 1 on failure, which currently will happen
+ * if the requested device does not appear to be present in the list.
+ */
+
+int del_mtd_device(struct mtd_info *mtd)
+{
+ int ret;
+ struct mtd_notifier *not;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (idr_find(&mtd_idr, mtd->index) != mtd) {
+ ret = -ENODEV;
+ goto out_error;
+ }
+
+ /* No need to get a refcount on the module containing
+ the notifier, since we hold the mtd_table_mutex */
+ list_for_each_entry(not, &mtd_notifiers, list)
+ not->remove(mtd);
+
+ if (mtd->usecount) {
+ printk(KERN_NOTICE "Removing MTD device #%d (%s) with use count %d\n",
+ mtd->index, mtd->name, mtd->usecount);
+ ret = -EBUSY;
+ } else {
+ debugfs_remove_recursive(mtd->dbg.dfs_dir);
+
+ /* Try to remove the NVMEM provider */
+ if (mtd->nvmem)
+ nvmem_unregister(mtd->nvmem);
+
+ device_unregister(&mtd->dev);
+
+ idr_remove(&mtd_idr, mtd->index);
+ of_node_put(mtd_get_of_node(mtd));
+
+ module_put(THIS_MODULE);
+ ret = 0;
+ }
+
+out_error:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+
+/*
+ * Set a few defaults based on the parent devices, if not provided by the
+ * driver
+ */
+static void mtd_set_dev_defaults(struct mtd_info *mtd)
+{
+ if (mtd->dev.parent) {
+ if (!mtd->owner && mtd->dev.parent->driver)
+ mtd->owner = mtd->dev.parent->driver->owner;
+ if (!mtd->name)
+ mtd->name = dev_name(mtd->dev.parent);
+ } else {
+ pr_debug("mtd device won't show a device symlink in sysfs\n");
+ }
+
+ INIT_LIST_HEAD(&mtd->partitions);
+ mutex_init(&mtd->master.partitions_lock);
+}
+
+/**
+ * mtd_device_parse_register - parse partitions and register an MTD device.
+ *
+ * @mtd: the MTD device to register
+ * @types: the list of MTD partition probes to try, see
+ * 'parse_mtd_partitions()' for more information
+ * @parser_data: MTD partition parser-specific data
+ * @parts: fallback partition information to register, if parsing fails;
+ * only valid if %nr_parts > %0
+ * @nr_parts: the number of partitions in parts, if zero then the full
+ * MTD device is registered if no partition info is found
+ *
+ * This function aggregates MTD partitions parsing (done by
+ * 'parse_mtd_partitions()') and MTD device and partitions registering. It
+ * basically follows the most common pattern found in many MTD drivers:
+ *
+ * * If the MTD_PARTITIONED_MASTER option is set, then the device as a whole is
+ * registered first.
+ * * Then It tries to probe partitions on MTD device @mtd using parsers
+ * specified in @types (if @types is %NULL, then the default list of parsers
+ * is used, see 'parse_mtd_partitions()' for more information). If none are
+ * found this functions tries to fallback to information specified in
+ * @parts/@nr_parts.
+ * * If no partitions were found this function just registers the MTD device
+ * @mtd and exits.
+ *
+ * Returns zero in case of success and a negative error code in case of failure.
+ */
+int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
+ struct mtd_part_parser_data *parser_data,
+ const struct mtd_partition *parts,
+ int nr_parts)
+{
+ int ret;
+
+ mtd_set_dev_defaults(mtd);
+
+ if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) {
+ ret = add_mtd_device(mtd);
+ if (ret)
+ return ret;
+ }
+
+ /* Prefer parsed partitions over driver-provided fallback */
+ ret = parse_mtd_partitions(mtd, types, parser_data);
+ if (ret == -EPROBE_DEFER)
+ goto out;
+
+ if (ret > 0)
+ ret = 0;
+ else if (nr_parts)
+ ret = add_mtd_partitions(mtd, parts, nr_parts);
+ else if (!device_is_registered(&mtd->dev))
+ ret = add_mtd_device(mtd);
+ else
+ ret = 0;
+
+ if (ret)
+ goto out;
+
+ /*
+ * FIXME: some drivers unfortunately call this function more than once.
+ * So we have to check if we've already assigned the reboot notifier.
+ *
+ * Generally, we can make multiple calls work for most cases, but it
+ * does cause problems with parse_mtd_partitions() above (e.g.,
+ * cmdlineparts will register partitions more than once).
+ */
+ WARN_ONCE(mtd->_reboot && mtd->reboot_notifier.notifier_call,
+ "MTD already registered\n");
+ if (mtd->_reboot && !mtd->reboot_notifier.notifier_call) {
+ mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
+ register_reboot_notifier(&mtd->reboot_notifier);
+ }
+
+out:
+ if (ret && device_is_registered(&mtd->dev))
+ del_mtd_device(mtd);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_device_parse_register);
+
+/**
+ * mtd_device_unregister - unregister an existing MTD device.
+ *
+ * @master: the MTD device to unregister. This will unregister both the master
+ * and any partitions if registered.
+ */
+int mtd_device_unregister(struct mtd_info *master)
+{
+ int err;
+
+ if (master->_reboot)
+ unregister_reboot_notifier(&master->reboot_notifier);
+
+ err = del_mtd_partitions(master);
+ if (err)
+ return err;
+
+ if (!device_is_registered(&master->dev))
+ return 0;
+
+ return del_mtd_device(master);
+}
+EXPORT_SYMBOL_GPL(mtd_device_unregister);
+
+/**
+ * register_mtd_user - register a 'user' of MTD devices.
+ * @new: pointer to notifier info structure
+ *
+ * Registers a pair of callbacks function to be called upon addition
+ * or removal of MTD devices. Causes the 'add' callback to be immediately
+ * invoked for each MTD device currently present in the system.
+ */
+void register_mtd_user (struct mtd_notifier *new)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ list_add(&new->list, &mtd_notifiers);
+
+ __module_get(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ new->add(mtd);
+
+ mutex_unlock(&mtd_table_mutex);
+}
+EXPORT_SYMBOL_GPL(register_mtd_user);
+
+/**
+ * unregister_mtd_user - unregister a 'user' of MTD devices.
+ * @old: pointer to notifier info structure
+ *
+ * Removes a callback function pair from the list of 'users' to be
+ * notified upon addition or removal of MTD devices. Causes the
+ * 'remove' callback to be immediately invoked for each MTD device
+ * currently present in the system.
+ */
+int unregister_mtd_user (struct mtd_notifier *old)
+{
+ struct mtd_info *mtd;
+
+ mutex_lock(&mtd_table_mutex);
+
+ module_put(THIS_MODULE);
+
+ mtd_for_each_device(mtd)
+ old->remove(mtd);
+
+ list_del(&old->list);
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(unregister_mtd_user);
+
+/**
+ * get_mtd_device - obtain a validated handle for an MTD device
+ * @mtd: last known address of the required MTD device
+ * @num: internal device number of the required MTD device
+ *
+ * Given a number and NULL address, return the num'th entry in the device
+ * table, if any. Given an address and num == -1, search the device table
+ * for a device with that address and return if it's still present. Given
+ * both, return the num'th driver only if its address matches. Return
+ * error code if not.
+ */
+struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num)
+{
+ struct mtd_info *ret = NULL, *other;
+ int err = -ENODEV;
+
+ mutex_lock(&mtd_table_mutex);
+
+ if (num == -1) {
+ mtd_for_each_device(other) {
+ if (other == mtd) {
+ ret = mtd;
+ break;
+ }
+ }
+ } else if (num >= 0) {
+ ret = idr_find(&mtd_idr, num);
+ if (mtd && mtd != ret)
+ ret = NULL;
+ }
+
+ if (!ret) {
+ ret = ERR_PTR(err);
+ goto out;
+ }
+
+ err = __get_mtd_device(ret);
+ if (err)
+ ret = ERR_PTR(err);
+out:
+ mutex_unlock(&mtd_table_mutex);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(get_mtd_device);
+
+
+int __get_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int err;
+
+ if (!try_module_get(master->owner))
+ return -ENODEV;
+
+ if (master->_get_device) {
+ err = master->_get_device(mtd);
+
+ if (err) {
+ module_put(master->owner);
+ return err;
+ }
+ }
+
+ master->usecount++;
+
+ while (mtd->parent) {
+ mtd->usecount++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(__get_mtd_device);
+
+/**
+ * get_mtd_device_nm - obtain a validated handle for an MTD device by
+ * device name
+ * @name: MTD device name to open
+ *
+ * This function returns MTD device description structure in case of
+ * success and an error code in case of failure.
+ */
+struct mtd_info *get_mtd_device_nm(const char *name)
+{
+ int err = -ENODEV;
+ struct mtd_info *mtd = NULL, *other;
+
+ mutex_lock(&mtd_table_mutex);
+
+ mtd_for_each_device(other) {
+ if (!strcmp(name, other->name)) {
+ mtd = other;
+ break;
+ }
+ }
+
+ if (!mtd)
+ goto out_unlock;
+
+ err = __get_mtd_device(mtd);
+ if (err)
+ goto out_unlock;
+
+ mutex_unlock(&mtd_table_mutex);
+ return mtd;
+
+out_unlock:
+ mutex_unlock(&mtd_table_mutex);
+ return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(get_mtd_device_nm);
+
+void put_mtd_device(struct mtd_info *mtd)
+{
+ mutex_lock(&mtd_table_mutex);
+ __put_mtd_device(mtd);
+ mutex_unlock(&mtd_table_mutex);
+
+}
+EXPORT_SYMBOL_GPL(put_mtd_device);
+
+void __put_mtd_device(struct mtd_info *mtd)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ while (mtd->parent) {
+ --mtd->usecount;
+ BUG_ON(mtd->usecount < 0);
+ mtd = mtd->parent;
+ }
+
+ master->usecount--;
+
+ if (master->_put_device)
+ master->_put_device(master);
+
+ module_put(master->owner);
+}
+EXPORT_SYMBOL_GPL(__put_mtd_device);
+
+/*
+ * Erase is an synchronous operation. Device drivers are epected to return a
+ * negative error code if the operation failed and update instr->fail_addr
+ * to point the portion that was not properly erased.
+ */
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ u64 mst_ofs = mtd_get_master_ofs(mtd, 0);
+ struct erase_info adjinstr;
+ int ret;
+
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ adjinstr = *instr;
+
+ if (!mtd->erasesize || !master->_erase)
+ return -ENOTSUPP;
+
+ if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!instr->len)
+ return 0;
+
+ ledtrig_mtd_activity();
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ adjinstr.addr = (loff_t)mtd_div_by_eb(instr->addr, mtd) *
+ master->erasesize;
+ adjinstr.len = ((u64)mtd_div_by_eb(instr->addr + instr->len, mtd) *
+ master->erasesize) -
+ adjinstr.addr;
+ }
+
+ adjinstr.addr += mst_ofs;
+
+ ret = master->_erase(master, &adjinstr);
+
+ if (adjinstr.fail_addr != MTD_FAIL_ADDR_UNKNOWN) {
+ instr->fail_addr = adjinstr.fail_addr - mst_ofs;
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ instr->fail_addr = mtd_div_by_eb(instr->fail_addr,
+ master);
+ instr->fail_addr *= mtd->erasesize;
+ }
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_erase);
+
+/*
+ * This stuff for eXecute-In-Place. phys is optional and may be set to NULL.
+ */
+int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ void **virt, resource_size_t *phys)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ *virt = NULL;
+ if (phys)
+ *phys = 0;
+ if (!master->_point)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ from = mtd_get_master_ofs(mtd, from);
+ return master->_point(master, from, len, retlen, virt, phys);
+}
+EXPORT_SYMBOL_GPL(mtd_point);
+
+/* We probably shouldn't allow XIP if the unpoint isn't a NULL */
+int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unpoint)
+ return -EOPNOTSUPP;
+ if (from < 0 || from >= mtd->size || len > mtd->size - from)
+ return -EINVAL;
+ if (!len)
+ return 0;
+ return master->_unpoint(master, mtd_get_master_ofs(mtd, from), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unpoint);
+
+/*
+ * Allow NOMMU mmap() to directly map the device (if not NULL)
+ * - return the address to which the offset maps
+ * - return -ENOSYS to indicate refusal to do the mapping
+ */
+unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len,
+ unsigned long offset, unsigned long flags)
+{
+ size_t retlen;
+ void *virt;
+ int ret;
+
+ ret = mtd_point(mtd, offset, len, &retlen, &virt, NULL);
+ if (ret)
+ return ret;
+ if (retlen != len) {
+ mtd_unpoint(mtd, offset, retlen);
+ return -ENOSYS;
+ }
+ return (unsigned long)virt;
+}
+EXPORT_SYMBOL_GPL(mtd_get_unmapped_area);
+
+static void mtd_update_ecc_stats(struct mtd_info *mtd, struct mtd_info *master,
+ const struct mtd_ecc_stats *old_stats)
+{
+ struct mtd_ecc_stats diff;
+
+ if (master == mtd)
+ return;
+
+ diff = master->ecc_stats;
+ diff.failed -= old_stats->failed;
+ diff.corrected -= old_stats->corrected;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.failed += diff.failed;
+ mtd->ecc_stats.corrected += diff.corrected;
+ mtd = mtd->parent;
+ }
+}
+
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+ u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = buf,
+ };
+ int ret;
+
+ ret = mtd_read_oob(mtd, from, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_read);
+
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_oob_ops ops = {
+ .len = len,
+ .datbuf = (u8 *)buf,
+ };
+ int ret;
+
+ ret = mtd_write_oob(mtd, to, &ops);
+ *retlen = ops.retlen;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mtd_write);
+
+/*
+ * In blackbox flight recorder like scenarios we want to make successful writes
+ * in interrupt context. panic_write() is only intended to be called when its
+ * known the kernel is about to panic and we need the write to succeed. Since
+ * the kernel is not going to be running for much longer, this function can
+ * break locks and delay to ensure the write succeeds (but not sleep).
+ */
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+ const u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_panic_write)
+ return -EOPNOTSUPP;
+ if (to < 0 || to >= mtd->size || len > mtd->size - to)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+ if (!len)
+ return 0;
+ if (!master->oops_panic_write)
+ master->oops_panic_write = true;
+
+ return master->_panic_write(master, mtd_get_master_ofs(mtd, to), len,
+ retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_panic_write);
+
+static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs,
+ struct mtd_oob_ops *ops)
+{
+ /*
+ * Some users are setting ->datbuf or ->oobbuf to NULL, but are leaving
+ * ->len or ->ooblen uninitialized. Force ->len and ->ooblen to 0 in
+ * this case.
+ */
+ if (!ops->datbuf)
+ ops->len = 0;
+
+ if (!ops->oobbuf)
+ ops->ooblen = 0;
+
+ if (offs < 0 || offs + ops->len > mtd->size)
+ return -EINVAL;
+
+ if (ops->ooblen) {
+ size_t maxooblen;
+
+ if (ops->ooboffs >= mtd_oobavail(mtd, ops))
+ return -EINVAL;
+
+ maxooblen = ((size_t)(mtd_div_by_ws(mtd->size, mtd) -
+ mtd_div_by_ws(offs, mtd)) *
+ mtd_oobavail(mtd, ops)) - ops->ooboffs;
+ if (ops->ooblen > maxooblen)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtd_read_oob_std(struct mtd_info *mtd, loff_t from,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ from = mtd_get_master_ofs(mtd, from);
+ if (master->_read_oob)
+ ret = master->_read_oob(master, from, ops);
+ else
+ ret = master->_read(master, from, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_write_oob_std(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ to = mtd_get_master_ofs(mtd, to);
+ if (master->_write_oob)
+ ret = master->_write_oob(master, to, ops);
+ else
+ ret = master->_write(master, to, ops->len, &ops->retlen,
+ ops->datbuf);
+
+ return ret;
+}
+
+static int mtd_io_emulated_slc(struct mtd_info *mtd, loff_t start, bool read,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ngroups = mtd_pairing_groups(master);
+ int npairs = mtd_wunit_per_eb(master) / ngroups;
+ struct mtd_oob_ops adjops = *ops;
+ unsigned int wunit, oobavail;
+ struct mtd_pairing_info info;
+ int max_bitflips = 0;
+ u32 ebofs, pageofs;
+ loff_t base, pos;
+
+ ebofs = mtd_mod_by_eb(start, mtd);
+ base = (loff_t)mtd_div_by_eb(start, mtd) * master->erasesize;
+ info.group = 0;
+ info.pair = mtd_div_by_ws(ebofs, mtd);
+ pageofs = mtd_mod_by_ws(ebofs, mtd);
+ oobavail = mtd_oobavail(mtd, ops);
+
+ while (ops->retlen < ops->len || ops->oobretlen < ops->ooblen) {
+ int ret;
+
+ if (info.pair >= npairs) {
+ info.pair = 0;
+ base += master->erasesize;
+ }
+
+ wunit = mtd_pairing_info_to_wunit(master, &info);
+ pos = mtd_wunit_to_offset(mtd, base, wunit);
+
+ adjops.len = ops->len - ops->retlen;
+ if (adjops.len > mtd->writesize - pageofs)
+ adjops.len = mtd->writesize - pageofs;
+
+ adjops.ooblen = ops->ooblen - ops->oobretlen;
+ if (adjops.ooblen > oobavail - adjops.ooboffs)
+ adjops.ooblen = oobavail - adjops.ooboffs;
+
+ if (read) {
+ ret = mtd_read_oob_std(mtd, pos + pageofs, &adjops);
+ if (ret > 0)
+ max_bitflips = max(max_bitflips, ret);
+ } else {
+ ret = mtd_write_oob_std(mtd, pos + pageofs, &adjops);
+ }
+
+ if (ret < 0)
+ return ret;
+
+ max_bitflips = max(max_bitflips, ret);
+ ops->retlen += adjops.retlen;
+ ops->oobretlen += adjops.oobretlen;
+ adjops.datbuf += adjops.retlen;
+ adjops.oobbuf += adjops.oobretlen;
+ adjops.ooboffs = 0;
+ pageofs = 0;
+ info.pair++;
+ }
+
+ return max_bitflips;
+}
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ struct mtd_ecc_stats old_stats = master->ecc_stats;
+ int ret_code;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ ret_code = mtd_check_oob_ops(mtd, from, ops);
+ if (ret_code)
+ return ret_code;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_read */
+ if (!master->_read_oob && (!master->_read || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ret_code = mtd_io_emulated_slc(mtd, from, true, ops);
+ else
+ ret_code = mtd_read_oob_std(mtd, from, ops);
+
+ mtd_update_ecc_stats(mtd, master, &old_stats);
+
+ /*
+ * In cases where ops->datbuf != NULL, mtd->_read_oob() has semantics
+ * similar to mtd->_read(), returning a non-negative integer
+ * representing max bitflips. In other cases, mtd->_read_oob() may
+ * return -EUCLEAN. In all cases, perform similar logic to mtd_read().
+ */
+ if (unlikely(ret_code < 0))
+ return ret_code;
+ if (mtd->ecc_strength == 0)
+ return 0; /* device lacks ecc */
+ //printk("ecc strength = %d.\n",mtd->ecc_strength);
+ //printk("bitflip_threshold = %d.\n",mtd->bitflip_threshold);
+ if (mtd->bitflip_threshold == 0)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+ return ret_code >= mtd->bitflip_threshold ? -EUCLEAN : 0;
+}
+EXPORT_SYMBOL_GPL(mtd_read_oob);
+
+int mtd_write_oob(struct mtd_info *mtd, loff_t to,
+ struct mtd_oob_ops *ops)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ ops->retlen = ops->oobretlen = 0;
+
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ ret = mtd_check_oob_ops(mtd, to, ops);
+ if (ret)
+ return ret;
+
+ ledtrig_mtd_activity();
+
+ /* Check the validity of a potential fallback on mtd->_write */
+ if (!master->_write_oob && (!master->_write || ops->oobbuf))
+ return -EOPNOTSUPP;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ return mtd_io_emulated_slc(mtd, to, false, ops);
+
+ return mtd_write_oob_std(mtd, to, ops);
+}
+EXPORT_SYMBOL_GPL(mtd_write_oob);
+
+/**
+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section
+ * @mtd: MTD device structure
+ * @section: ECC section. Depending on the layout you may have all the ECC
+ * bytes stored in a single contiguous section, or one section
+ * per ECC chunk (and sometime several sections for a single ECC
+ * ECC chunk)
+ * @oobecc: OOB region struct filled with the appropriate ECC position
+ * information
+ *
+ * This function returns ECC section information in the OOB area. If you want
+ * to get all the ECC bytes information, then you should call
+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobecc, 0, sizeof(*oobecc));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->ecc)
+ return -ENOTSUPP;
+
+ return master->ooblayout->ecc(master, section, oobecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
+
+/**
+ * mtd_ooblayout_free - Get the OOB region definition of a specific free
+ * section
+ * @mtd: MTD device structure
+ * @section: Free section you are interested in. Depending on the layout
+ * you may have all the free bytes stored in a single contiguous
+ * section, or one section per ECC chunk plus an extra section
+ * for the remaining bytes (or other funky layout).
+ * @oobfree: OOB region struct filled with the appropriate free position
+ * information
+ *
+ * This function returns free bytes position in the OOB area. If you want
+ * to get all the free bytes information, then you should call
+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ memset(oobfree, 0, sizeof(*oobfree));
+
+ if (!master || section < 0)
+ return -EINVAL;
+
+ if (!master->ooblayout || !master->ooblayout->free)
+ return -ENOTSUPP;
+
+ return master->ooblayout->free(master, section, oobfree);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
+
+/**
+ * mtd_ooblayout_find_region - Find the region attached to a specific byte
+ * @mtd: mtd info structure
+ * @byte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: used to retrieve the ECC position
+ * @iter: iterator function. Should be either mtd_ooblayout_free or
+ * mtd_ooblayout_ecc depending on the region type you're searching for
+ *
+ * This function returns the section id and oobregion information of a
+ * specific byte. For example, say you want to know where the 4th ECC byte is
+ * stored, you'll use:
+ *
+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc);
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte,
+ int *sectionp, struct mtd_oob_region *oobregion,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ int pos = 0, ret, section = 0;
+
+ memset(oobregion, 0, sizeof(*oobregion));
+
+ while (1) {
+ ret = iter(mtd, section, oobregion);
+ if (ret)
+ return ret;
+
+ if (pos + oobregion->length > byte)
+ break;
+
+ pos += oobregion->length;
+ section++;
+ }
+
+ /*
+ * Adjust region info to make it start at the beginning at the
+ * 'start' ECC byte.
+ */
+ oobregion->offset += byte - pos;
+ oobregion->length -= byte - pos;
+ *sectionp = section;
+
+ return 0;
+}
+
+/**
+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific
+ * ECC byte
+ * @mtd: mtd info structure
+ * @eccbyte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: OOB region information
+ *
+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC
+ * byte.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion)
+{
+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion);
+
+/**
+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @buf: destination buffer to store OOB bytes
+ * @oobbuf: OOB buffer
+ * @start: first byte to retrieve
+ * @nbytes: number of bytes to retrieve
+ * @iter: section iterator
+ *
+ * Extract bytes attached to a specific category (ECC or free)
+ * from the OOB buffer and copy them into buf.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf,
+ const u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(buf, oobbuf + oobregion.offset, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @buf: source buffer to get OOB bytes from
+ * @oobbuf: OOB buffer
+ * @start: first OOB byte to set
+ * @nbytes: number of OOB bytes to set
+ * @iter: section iterator
+ *
+ * Fill the OOB buffer with data provided in buf. The category (ECC or free)
+ * is selected by passing the appropriate iterator.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf,
+ u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, §ion,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(oobbuf + oobregion.offset, buf, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category
+ * @mtd: mtd info structure
+ * @iter: category iterator
+ *
+ * Count the number of bytes in a given category.
+ *
+ * Returns a positive value on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section = 0, ret, nbytes = 0;
+
+ while (1) {
+ ret = iter(mtd, section++, &oobregion);
+ if (ret) {
+ if (ret == -ERANGE)
+ ret = nbytes;
+ break;
+ }
+
+ nbytes += oobregion.length;
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes);
+
+/**
+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get ECC bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes);
+
+/**
+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes);
+
+/**
+ * mtd_ooblayout_set_databytes - set data bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: source buffer to get data bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes);
+
+/**
+ * mtd_ooblayout_count_eccbytes - count the number of ECC bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes);
+
+/*
+ * Method to access the protection register area, present in some flash
+ * devices. The user data is one time programmable but the factory data is read
+ * only.
+ */
+int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_fact_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_fact_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_fact_prot_info);
+
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_fact_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_fact_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_fact_prot_reg);
+
+int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+ struct otp_info *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_get_user_prot_info)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_get_user_prot_info(master, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_get_user_prot_info);
+
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!master->_read_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_read_user_prot_reg(master, from, len, retlen, buf);
+}
+EXPORT_SYMBOL_GPL(mtd_read_user_prot_reg);
+
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ *retlen = 0;
+ if (!master->_write_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ ret = master->_write_user_prot_reg(master, to, len, retlen, buf);
+ if (ret)
+ return ret;
+
+ /*
+ * If no data could be written at all, we are out of memory and
+ * must return -ENOSPC.
+ */
+ return (*retlen) ? 0 : -ENOSPC;
+}
+EXPORT_SYMBOL_GPL(mtd_write_user_prot_reg);
+
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock_user_prot_reg)
+ return -EOPNOTSUPP;
+ if (!len)
+ return 0;
+ return master->_lock_user_prot_reg(master, from, len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
+
+/* Chip-supported device locking */
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_lock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_lock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_lock);
+
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_unlock)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_unlock(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_unlock);
+
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (!master->_is_locked)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs)
+ return -EINVAL;
+ if (!len)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION) {
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+ len = (u64)mtd_div_by_eb(len, mtd) * master->erasesize;
+ }
+
+ return master->_is_locked(master, mtd_get_master_ofs(mtd, ofs), len);
+}
+EXPORT_SYMBOL_GPL(mtd_is_locked);
+
+int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isreserved)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isreserved(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isreserved);
+
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!master->_block_isbad)
+ return 0;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ return master->_block_isbad(master, mtd_get_master_ofs(mtd, ofs));
+}
+EXPORT_SYMBOL_GPL(mtd_block_isbad);
+
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+ int ret;
+
+ if (!master->_block_markbad)
+ return -EOPNOTSUPP;
+ if (ofs < 0 || ofs >= mtd->size)
+ return -EINVAL;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (mtd->flags & MTD_SLC_ON_MLC_EMULATION)
+ ofs = (loff_t)mtd_div_by_eb(ofs, mtd) * master->erasesize;
+
+ ret = master->_block_markbad(master, mtd_get_master_ofs(mtd, ofs));
+ if (ret)
+ return ret;
+
+ while (mtd->parent) {
+ mtd->ecc_stats.badblocks++;
+ mtd = mtd->parent;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mtd_block_markbad);
+
+/*
+ * default_mtd_writev - the default writev method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+static int default_mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ unsigned long i;
+ size_t totlen = 0, thislen;
+ int ret = 0;
+
+ for (i = 0; i < count; i++) {
+ if (!vecs[i].iov_len)
+ continue;
+ ret = mtd_write(mtd, to, vecs[i].iov_len, &thislen,
+ vecs[i].iov_base);
+ totlen += thislen;
+ if (ret || thislen != vecs[i].iov_len)
+ break;
+ to += vecs[i].iov_len;
+ }
+ *retlen = totlen;
+ return ret;
+}
+
+/*
+ * mtd_writev - the vector-based MTD write method
+ * @mtd: mtd device description object pointer
+ * @vecs: the vectors to write
+ * @count: count of vectors in @vecs
+ * @to: the MTD device offset to write to
+ * @retlen: on exit contains the count of bytes written to the MTD device.
+ *
+ * This function returns zero in case of success and a negative error code in
+ * case of failure.
+ */
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+ unsigned long count, loff_t to, size_t *retlen)
+{
+ struct mtd_info *master = mtd_get_master(mtd);
+
+ *retlen = 0;
+ if (!(mtd->flags & MTD_WRITEABLE))
+ return -EROFS;
+
+ if (!master->_writev)
+ return default_mtd_writev(mtd, vecs, count, to, retlen);
+
+ return master->_writev(master, vecs, count,
+ mtd_get_master_ofs(mtd, to), retlen);
+}
+EXPORT_SYMBOL_GPL(mtd_writev);
+
+/**
+ * mtd_kmalloc_up_to - allocate a contiguous buffer up to the specified size
+ * @mtd: mtd device description object pointer
+ * @size: a pointer to the ideal or maximum size of the allocation, points
+ * to the actual allocation size on success.
+ *
+ * This routine attempts to allocate a contiguous kernel buffer up to
+ * the specified size, backing off the size of the request exponentially
+ * until the request succeeds or until the allocation size falls below
+ * the system page size. This attempts to make sure it does not adversely
+ * impact system performance, so when allocating more than one page, we
+ * ask the memory allocator to avoid re-trying, swapping, writing back
+ * or performing I/O.
+ *
+ * Note, this function also makes sure that the allocated buffer is aligned to
+ * the MTD device's min. I/O unit, i.e. the "mtd->writesize" value.
+ *
+ * This is called, for example by mtd_{read,write} and jffs2_scan_medium,
+ * to handle smaller (i.e. degraded) buffer allocations under low- or
+ * fragmented-memory situations where such reduced allocations, from a
+ * requested ideal, are allowed.
+ *
+ * Returns a pointer to the allocated buffer on success; otherwise, NULL.
+ */
+void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size)
+{
+ gfp_t flags = __GFP_NOWARN | __GFP_DIRECT_RECLAIM | __GFP_NORETRY;
+ size_t min_alloc = max_t(size_t, mtd->writesize, PAGE_SIZE);
+ void *kbuf;
+
+ *size = min_t(size_t, *size, KMALLOC_MAX_SIZE);
+
+ while (*size > min_alloc) {
+ kbuf = kmalloc(*size, flags);
+ if (kbuf)
+ return kbuf;
+
+ *size >>= 1;
+ *size = ALIGN(*size, mtd->writesize);
+ }
+
+ /*
+ * For the last resort allocation allow 'kmalloc()' to do all sorts of
+ * things (write-back, dropping caches, etc) by using GFP_KERNEL.
+ */
+ return kmalloc(*size, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(mtd_kmalloc_up_to);
+
+#ifdef CONFIG_PROC_FS
+
+/*====================================================================*/
+/* Support for /proc/mtd */
+
+static int mtd_proc_show(struct seq_file *m, void *v)
+{
+ struct mtd_info *mtd;
+
+ seq_puts(m, "dev: size erasesize name\n");
+ mutex_lock(&mtd_table_mutex);
+ mtd_for_each_device(mtd) {
+ seq_printf(m, "mtd%d: %8.8llx %8.8x \"%s\"\n",
+ mtd->index, (unsigned long long)mtd->size,
+ mtd->erasesize, mtd->name);
+ }
+ mutex_unlock(&mtd_table_mutex);
+ return 0;
+}
+#endif /* CONFIG_PROC_FS */
+
+/*====================================================================*/
+/* Init code */
+
+static struct backing_dev_info * __init mtd_bdi_init(char *name)
+{
+ struct backing_dev_info *bdi;
+ int ret;
+
+ bdi = bdi_alloc(NUMA_NO_NODE);
+ if (!bdi)
+ return ERR_PTR(-ENOMEM);
+ bdi->ra_pages = 0;
+ bdi->io_pages = 0;
+
+ /*
+ * We put '-0' suffix to the name to get the same name format as we
+ * used to get. Since this is called only once, we get a unique name.
+ */
+ ret = bdi_register(bdi, "%.28s-0", name);
+ if (ret)
+ bdi_put(bdi);
+
+ return ret ? ERR_PTR(ret) : bdi;
+}
+
+static struct proc_dir_entry *proc_mtd;
+
+static int __init init_mtd(void)
+{
+ int ret;
+
+ ret = class_register(&mtd_class);
+ if (ret)
+ goto err_reg;
+
+ mtd_bdi = mtd_bdi_init("mtd");
+ if (IS_ERR(mtd_bdi)) {
+ ret = PTR_ERR(mtd_bdi);
+ goto err_bdi;
+ }
+
+ proc_mtd = proc_create_single("mtd", 0, NULL, mtd_proc_show);
+
+ ret = init_mtdchar();
+ if (ret)
+ goto out_procfs;
+
+ dfs_dir_mtd = debugfs_create_dir("mtd", NULL);
+
+ return 0;
+
+out_procfs:
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ bdi_put(mtd_bdi);
+err_bdi:
+ class_unregister(&mtd_class);
+err_reg:
+ pr_err("Error registering mtd class or bdi: %d\n", ret);
+ return ret;
+}
+
+static void __exit cleanup_mtd(void)
+{
+ debugfs_remove_recursive(dfs_dir_mtd);
+ cleanup_mtdchar();
+ if (proc_mtd)
+ remove_proc_entry("mtd", NULL);
+ class_unregister(&mtd_class);
+ bdi_put(mtd_bdi);
+ idr_destroy(&mtd_idr);
+}
+
+module_init(init_mtd);
+module_exit(cleanup_mtd);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
+MODULE_DESCRIPTION("Core MTD registration and access routines");
diff --git a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
new file mode 100755
index 0000000..668d9d9
--- /dev/null
+++ b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac.c
@@ -0,0 +1,2063 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include <linux/of.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/device.h>
+#include "zx29_gmac.h"
+
+#define gmac_printk(_format, _args...) do{printk(KERN_INFO"gmac," _format "\n",##_args);}while(0)
+
+static u8 zx29_gmac_addr[MAC_ADDR_LENTH] = {0xec,0x1d,0x7f,0xb0,0x2f,0x32};
+static struct tasklet_struct *g_gmac_tasklet = NULL;
+/*struct zx29_gmac_dev *g_gmac_dev = NULL; */ /* no use possible */
+extern void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void* puf);
+extern int gmac_event_init(const char *name);
+static void gmac_hw_deinit(struct net_device *dev);
+//extern void v7_dma_map_area(const void *, size_t, int);
+//extern unsigned long virt_to_phys_ap(unsigned long virt);
+extern void dma_map(const void *addr, size_t len, int flags);
+extern unsigned long virt_to_phys_ap_new(unsigned long virt_addr);
+extern void kobj_gmac_del(struct kobject *kobject);
+
+
+void dump_pkt_trace(unsigned char *data,int len)
+{
+ int i;
+ len = len > 128?128:len;
+ printk("********************\n");
+ for(i=0;i<len;i++){
+ printk("%.2x ",data[i]);
+ if((i&0xf) == 0xf)
+ printk("\n");
+ }
+ printk("\n");
+ printk("********************\n");
+}
+
+static u32 zx29_gmac_get_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+
+ return prv->link.isup;
+}
+
+
+static void gmac_start(void* io)
+{
+ volatile unsigned *gmac = (unsigned*)io;
+
+ mac_int_enable();
+ dma_enable();
+ mac_enable();
+}
+
+static inline int mod_sub(int left, int right, int mod)
+{
+ return (mod - right + left) % mod;
+}
+
+static struct bd_tx *get_txed_bd(struct net_device *ndev)
+{
+ struct bd_tx *d;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int n = priv->txed_bd;
+
+ d = (struct bd_tx *)priv->dma_tx_vir;
+
+ if (n == priv->tx_bd_offset)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER)
+ return 0;
+
+ if (d[n].skb == NULL)
+ return 0;
+
+ priv->txed_bd++;
+ priv->txed_bd %= GMAC_TX_BD_NUM;
+
+ return &d[n];
+}
+
+static inline struct bd_tx *get_tx_bd(struct net_device *ndev)
+{
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+ int n = priv->tx_bd_offset;
+ struct bd_tx *d = (struct bd_tx*)priv->dma_tx_vir;
+
+ if (mod_sub(priv->tx_bd_offset, priv->txed_bd, GMAC_TX_BD_NUM) > GMAC_TX_BD_NUM - 2)
+ return 0;
+
+ if (d[n].TDES0 & DMA_OWNER) {
+ return 0;
+ } else {
+ return &d[n];
+ }
+}
+
+static struct bd_rx *get_rx_bd(struct net_device *dev)
+{
+ struct zx29_gmac_dev* prv = (struct zx29_gmac_dev*)netdev_priv(dev);
+ int n = prv->rx_bd_offset;
+ struct bd_rx *d = (struct bd_rx*)prv->dma_rx_vir;
+
+ if(d[n].RDES0 & DMA_OWNER)
+ {
+ return 0;
+ }
+ else
+ {
+ return &d[n];
+ }
+}
+
+static void gmac_trig_transmit(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 20) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 6:
+ dma_continue_tx();
+ break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 7:
+ default:
+ break;
+
+ }
+}
+
+static void gmac_trig_receive(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+ register unsigned status = ((MAC(0x1014) >> 17) & 0x07);
+ switch (status) {
+ case 0:
+ dma_enable();
+ break;
+ case 4:
+ dma_continue_rx();
+ break;
+ default:
+ break;
+ }
+}
+
+static inline void gmac_update_mac(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned char *mac = (unsigned char*)ndev->dev_addr;
+
+ MAC(0x0044) = mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24;
+ MAC(0x0040) = mac[4] | mac[5] << 8;
+}
+
+static int zx29mii_read(struct mii_bus *bus, int phy_addr, int regnum)
+{
+ unsigned long flags;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 0 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irqsave(&prv->lock,flags);
+ while(mac_mii_is_busy());
+ MAC(0x0010) = val;
+ spin_unlock_irqrestore(&prv->lock,flags);
+
+ while(mac_mii_is_busy());
+
+ return (MAC(0x0014) & 0xFFFF);
+}
+
+static int zx29mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
+{
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)prv->base_addr;
+
+ unsigned val = ( 1 << 0 | // busy 位
+ 1 << 1 | // R/W操作指示位
+ (PHY_CLOCK << 2) | // 时钟位
+ (regnum & 0x1F) << 6 | // 寄存器
+ (phy_addr & 0x1F) << 11); // 物理芯片
+
+ spin_lock_irq(&prv->lock);
+ while(mac_mii_is_busy());
+ MAC(0x0014) = value;
+ MAC(0x0010) = val;
+
+ spin_unlock_irq(&prv->lock);
+
+ while(mac_mii_is_busy());
+
+ return 0;
+}
+
+static int zx29mii_reset(struct mii_bus *bus)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)bus->priv;
+ volatile unsigned *gmac = (unsigned *)priv->base_addr;
+
+ gmac_start((void *)priv->base_addr);
+ while (mac_mii_is_busy());
+ return 0;
+}
+
+static inline void zx29_gmac_set_macaddr(struct net_device *ndev)
+{
+ int i = 0;
+#if MAC_ADDR_SET
+ for (i = 0; i < MAC_ADDR_LENTH; i++)
+ ndev->dev_addr[i] = zx29_gmac_addr[i];
+
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ random_ether_addr(ndev->dev_addr);
+#else
+ random_ether_addr(ndev->dev_addr);
+#endif
+}
+
+static void zx29_gmac_tx(struct net_device *ndev)
+{
+ register unsigned status;
+ struct net_device_stats s = ndev->stats;
+ struct bd_tx *tx = get_txed_bd(ndev);
+
+
+ while (tx) {
+ status = tx->TDES0;
+
+ if (tx->TDES0 & ERR_TX_ES) {
+ s.tx_errors++;
+ if(status & ERR_TX_LC) s.tx_carrier_errors++;
+ if(status & ERR_TX_NC) s.tx_carrier_errors++;
+ if(status & ERR_TX_EC) s.tx_window_errors++;
+ if(status & ERR_TX_LATECOL) s.tx_window_errors++;
+ if(status & ERR_TX_UF) s.tx_aborted_errors++;
+ if(status & ERR_TX_ED) s.tx_aborted_errors++;
+ if(status & ERR_TX_JT) s.tx_fifo_errors++;
+ if(status & ERR_TX_FF) s.tx_fifo_errors++;
+
+ printk("%s, status=0x%x, err_cnt=%ld\n", __FUNCTION__,status, s.tx_errors);
+ }
+ dev_kfree_skb_any(tx->skb);
+ tx->skb = NULL;
+ tx = get_txed_bd(ndev);
+
+ }
+
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
+}
+
+static int zx29_gmac_rx(struct net_device *ndev)
+{
+ struct bd_rx *rx;
+ struct sk_buff *skb;
+ struct sk_buff *skb_new;
+ unsigned len;
+ int exhausted = 0;
+
+ struct zx29_gmac_dev* priv = (struct zx29_gmac_dev*)netdev_priv(ndev);
+
+ rx = get_rx_bd(ndev);
+
+ if(unlikely(!rx)) goto rcv_done;
+
+ while (rx) {
+ if ((rx->RDES0 & ERR_RX_ES) || (rx->RDES0 & ERR_RX_LE)) {
+ ndev->stats.rx_errors++;
+ if(rx->RDES0 & ERR_RX_LE) ndev->stats.rx_length_errors++;
+ if(rx->RDES0 & ERR_RX_OE) ndev->stats.rx_over_errors++;
+ if(rx->RDES0 & ERR_RX_IPC) ndev->stats.rx_frame_errors++;
+ if(rx->RDES0 & ERR_RX_LC) ndev->stats.rx_fifo_errors++;
+ if(rx->RDES0 & ERR_RX_CE) ndev->stats.rx_crc_errors++;
+ } else {
+
+ len = ((rx->RDES0 >> 16) & 0x3FFF) - 4;
+ if(len > (ETH_FRAME_LEN+8)) {
+ ndev->stats.rx_dropped++;
+ goto rx_bd_reset;
+ }
+
+ skb_new = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb_new)) {
+ ndev->stats.rx_dropped++;
+ exhausted++;
+ } else {
+ exhausted = 0;
+ ndev->stats.rx_packets++;
+ ndev->stats.rx_bytes += len;
+
+ dma_sync_single_for_cpu(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_FROM_DEVICE);
+ skb = rx->skb;
+ skb_put(skb, len); /*in fact , use for?*/
+
+// dump_pkt_trace(skb->data, len);
+ skb->protocol = eth_type_trans(skb, ndev);
+ netif_rx(skb);
+
+ skb_reserve(skb_new, NET_IP_ALIGN);
+// rx->dma_buf = virt_to_phys_ap((unsigned long)skb_new->data);
+ rx->dma_buf = virt_to_phys_ap_new((unsigned long)skb_new->data);
+ if(rx->dma_buf == NULL)
+ rx->dma_buf = __pa((unsigned)skb_new->data);
+ rx->skb = skb_new;
+ wmb();
+ dma_sync_single_for_device(&ndev->dev, rx->dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+ }
+ }
+rx_bd_reset:
+ rx->RDES0 = rx->RDES0 | DMA_OWNER;
+ priv->rx_bd_offset++;
+ priv->rx_bd_offset %= GMAC_RX_BD_NUM;
+ wmb();
+
+ if (exhausted >= 10)
+ break;
+ gmac_trig_receive((void*)ndev->base_addr);
+ rx = get_rx_bd(ndev);
+ }
+
+rcv_done:
+
+ gmac_trig_receive((void*)ndev->base_addr);
+
+ return (exhausted > 10);
+}
+
+
+#ifndef GMAC_NO_INT
+static irqreturn_t zx29_gmac_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned * gmac = (unsigned *)ndev->base_addr;
+
+ priv->int_event = MAC(0x1014);
+ MAC(0x1014) = priv->int_event;
+
+ mac_int_disable();
+ tasklet_schedule(&priv->tasklet);
+
+ return IRQ_HANDLED;
+}
+
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *prv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int events = prv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX)
+ zx29_gmac_rx(ndev);
+
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_TX | INT_ST_RX));
+
+ mac_int_enable();
+}
+
+#else
+void zx29_gmac_tasklet(unsigned long dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned events = priv->int_event;
+
+ do {
+ if (events & INT_ST_TX)
+ zx29_gmac_tx(ndev);
+
+ if (events & INT_ST_RX) {
+ if (zx29_gmac_rx(ndev))
+ break;
+ }
+ events = MAC(0x1014);
+ MAC(0x1014) = events;
+ } while (events & (INT_ST_RX | INT_ST_TX));
+}
+
+enum hrtimer_restart gmac_timer_callback(struct hrtimer *timer)
+{
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+
+ hrtimer_forward_now(timer, gmac_schdule_time);
+ tasklet_schedule(g_gmac_tasklet);
+ return HRTIMER_RESTART;
+}
+#endif
+
+static inline void zx29_gmac_linkisup(struct net_device *dev, int isup)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+
+ priv->link.duplex = phydev->duplex;
+ priv->link.giga = (phydev->speed == 100);
+ if (priv->link.speed != phydev->speed)
+ priv->link.speed = phydev->speed;
+
+
+ priv->link.isup = isup;
+ if (isup)
+ netif_carrier_on(dev);
+ phy_print_status(phydev);
+}
+
+static void zx29_gmac_adjust_link(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *phydev = priv->phydev;
+ volatile unsigned *gmac = (unsigned *)dev->base_addr;
+
+ if (priv->link.isup &&
+ (!phydev->link ||
+ (priv->link.speed != phydev->speed) ||
+ (priv->link.duplex != phydev->duplex))) {
+ priv->link.isup = 0;
+ netif_tx_disable(dev);
+ if (!phydev->link) {
+ netif_carrier_off(dev);
+ phy_print_status(phydev);
+ }
+ }
+
+ if (!priv->link.isup && phydev->link) {
+ if (priv->link.duplex != phydev->duplex) {
+ if (phydev->duplex)
+ mac_set_full_duplex_mode();
+ else
+ mac_set_half_duplex_mode();
+ }
+
+ if (priv->link.giga != (phydev->speed == 100)) {
+ if (phydev->speed == 100)
+ mac_set_speed_100m_mode();
+ else
+ mac_set_speed_10m_mode();
+ }
+ netif_wake_queue(dev);
+ zx29_gmac_linkisup(dev, 1);
+ }
+
+}
+
+static inline int zx29_gmac_phy_start(struct net_device *dev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(dev);
+ struct phy_device *p = NULL;
+ struct mdio_device *mdio_dev = NULL;
+ int ret = 0;
+
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 start
+ int i = 0;
+ for(i = 0;i <= 5;i++)
+ {
+ if (priv->nports == 1) {
+ p = phy_find_first(priv->mii.bus);
+ } else if (priv->rmii_port < PHY_MAX_ADDR) {
+ mdio_dev = priv->mii.bus->mdio_map[priv->rmii_port];
+ p = container_of(mdio_dev, struct phy_device, mdio);
+ }
+
+ if (!p) {
+ if(i == 5){
+ gpio_direction_output(priv->gpio_power[0], 0);
+#ifdef CONFIG_MDIO_C45
+ gpio_direction_output(priv->gpio_power[1], 0);
+#endif
+ }
+ else
+ continue;
+ printk("%s: no PHY found\n", dev->name);
+ return -ENODEV;
+ }
+ else
+ break;
+ }
+ //zw.wang Without phy, gmac's gpio output power is removed on 20240328 end
+
+ ret = phy_connect_direct(dev, p, zx29_gmac_adjust_link, PHY_INTERFACE_MODE_RMII); /* phy_start_machine */
+ /* supported and advertising */
+ priv->phydev = p;
+ return 0;
+}
+
+
+static int gmac_init_rx_bd(struct net_device *ndev, struct zx29_gmac_dev *priv)
+{
+ struct sk_buff *skb = NULL;
+ struct bd_rx *rx = (struct bd_rx *)priv->dma_rx_vir;
+ int i = 0;
+
+ priv->rx_bd_offset = 0;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ skb = netdev_alloc_skb(ndev, GMAC_FRAME_LEN + NET_IP_ALIGN);
+ if (unlikely(!skb)) {
+ gmac_hw_deinit(ndev);
+ return -1;
+ }
+
+ skb_reserve(skb, NET_IP_ALIGN);
+
+ rx[i].RDES0 |= DMA_OWNER; /* when to change? */
+ rx[i].RDES1 = 0;
+ rx[i].RDES1 = GMAC_FRAME_LEN | 1 << 14;
+ rx[i].dma_buf = __pa((unsigned)skb->data); /* __pa ? */
+ rx[i].next = priv->dma_rx_phy + ((i + 1) << 5); /* why phy? */
+ rx[i].skb = skb;
+#if 0
+ if(i%4 != 0)
+ {
+ rx[i].RDES1 |= 0x80000000;
+ }
+#endif
+ dma_sync_single_for_device(&ndev->dev, rx[i].dma_buf, GMAC_FRAME_LEN, DMA_TO_DEVICE);
+
+ }
+ rx[GMAC_RX_BD_NUM - 1].next = priv->dma_rx_phy;
+ rx[GMAC_RX_BD_NUM - 1].RDES1 = GMAC_FRAME_LEN | 1 << 14 | 1 << 15;
+
+ return 0;
+}
+
+static void gmac_init_tx_bd(struct zx29_gmac_dev *priv)
+{
+ struct bd_tx *tx = (struct bd_tx *)priv->dma_tx_vir;
+ int i = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ tx[i].TDES0 = (1 << 20 | 1 << 30);
+ tx[i].TDES1 = GMAC_FRAME_LEN;
+ tx[i].next = priv->dma_tx_phy + ((i + 1) << 5);
+ }
+
+ tx[GMAC_TX_BD_NUM - 1].next = priv->dma_tx_phy;
+ tx[GMAC_TX_BD_NUM - 1].TDES0 = 1 << 20 | 1 << 21 | 1 << 30;
+
+}
+
+static void gmac_stop(void *io)
+{
+ volatile unsigned *gmac = (unsigned *)io;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ dma_clear_tx_fifo();
+ dma_wait_tx_fifo_cleared();
+}
+
+static void gmac_set_speed_duplex(struct net_device *ndev, int speed, int duplex)
+{
+ unsigned val;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+
+ val = MAC(0x0000) | 1 << 11 | 1 << 14;
+ if (SPEED_10 == speed)
+ val &= ~(1 << 14);
+ if (DUPLEX_HALF == duplex) {
+ val &= (~(1 << 11));
+ val |= (1 << 16);
+ }
+ MAC(0x0000) = val;
+}
+
+static void mac_init(struct net_device *ndev)
+{
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ unsigned int i = 0, j = 0, mac_rst = 0;
+ unsigned long long mac_time_start = 0;
+ unsigned long long mac_time_end = 0;
+
+ mac_provide_clock();
+#ifdef __DEAD_LOOP_POLL__
+ mac_reset();
+ mac_set_gmii_mode();
+ mac_wait_reset_finished();
+#else
+ mac_time_start = local_clock();
+ for (i = 0; i < MAC_RESET_NUM; i++) {
+ mac_reset();
+ mac_set_mii_mode();
+ for (j = 0; j < MAC_WAIT_TIME; j++) {
+// printk(".");
+ if (!((MAC(0x1000)) & 1)) {
+ mac_time_end = local_clock();
+ printk("ok:time:%llu ns\n", mac_time_end - mac_time_start);
+ mac_rst = 1;
+ goto mac_reset_option;
+ }
+ udelay(100);
+ }
+ }
+ mac_time_end = local_clock();
+mac_reset_option:
+ if(!mac_rst)
+ printk("gmac reset failed!time:%llu us\n", mac_time_end - mac_time_start);
+#endif
+ while(mac_mii_is_busy());
+}
+
+static void gmac_hw_deinit(struct net_device *ndev)
+{
+ int i;
+ struct bd_rx *rx_bd;
+ struct bd_tx *tx_bd;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ gmac_stop((void *)ndev->base_addr);
+
+ if (priv->dma_rx_phy) {
+ rx_bd = (struct bd_rx *)priv->dma_rx_vir;
+
+ for (i = 0; i < GMAC_RX_BD_NUM; i++) {
+ if (rx_bd[i].skb)
+ dev_kfree_skb_any(rx_bd[i].skb);
+ }
+
+ tx_bd = (struct bd_tx *)priv->dma_tx_vir;
+
+ for (i = 0; i < GMAC_TX_BD_NUM; i++) {
+ if (tx_bd[i].skb)
+ dev_kfree_skb_any(tx_bd[i].skb);
+ }
+ }
+
+ dma_set_tx_buffer(0); //设置首个BD的缓冲区为0；
+ dma_set_rx_buffer(0);
+
+ priv->rx_bd_offset = 0;
+ priv->tx_bd_offset = 0;
+ priv->txed_bd = 0;
+ priv->dma_rx_phy = 0;
+ priv->dma_rx_vir = 0;
+ priv->dma_tx_phy = 0;
+ priv->dma_tx_vir = 0;
+
+}
+
+static int gmac_hw_init(struct net_device *ndev)
+{
+ int ret = -1;
+ unsigned val;
+
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (priv->dma_rx_phy)
+ gmac_hw_deinit(ndev);
+
+ priv->dma_rx_vir = priv->dma_rx_vir_init;
+ priv->dma_rx_phy = priv->dma_rx_phy_init;
+ priv->dma_tx_vir = priv->dma_rx_vir + GMAC_RX_BUF_LEN;
+ priv->dma_tx_phy = priv->dma_rx_phy + GMAC_RX_BUF_LEN; /* ifconfig up, clear fifo*/
+
+ memset(priv->dma_rx_vir, 0, GMAC_BUF_LEN);
+
+ ret = gmac_init_rx_bd(ndev, priv);
+ if (ret < 0) {
+ printk("hw_net_init,init_rx_bd fail\n");
+ return ret;
+ }
+ gmac_init_tx_bd(priv);
+
+ mac_init(ndev);
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ val = MAC(0x1000);
+ val &= ~(0x3F << 8);
+ val |= (0x10 << 8);
+ MAC(0x1000) = val;
+
+ dma_set_rx_buffer(priv->dma_rx_phy);
+ dma_set_tx_buffer(priv->dma_tx_phy);
+
+ mac_int_clear(0x0001FFFF);
+ while (mac_mii_is_busy());
+
+ gmac_set_speed_duplex(ndev, priv->phydev->speed, priv->phydev->duplex);
+
+ mac_rece_all_data();
+
+ gmac_start((void *)ndev->base_addr);
+ return 0;
+}
+
+static int zx29_gmac_open(struct net_device *ndev)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ unsigned long flags;
+ int ret;
+ int err = 0;
+#ifdef GMAC_NO_INT
+ unsigned long delay_in_us = GTIMER_INTERVAL;
+ ktime_t gmac_schdule_time;
+#endif
+ err = phy_read_status(priv->phydev); /*interal, phy drv provide*/
+ if (err < 0)
+ return err;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->link.speed = 0;
+
+ zx29_gmac_linkisup(ndev, priv->phydev->link);
+
+ ret = gmac_hw_init(ndev);
+ if(ret) {
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+
+ netif_carrier_on(ndev);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ phy_start(priv->phydev);
+
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ gmac_schdule_time = ktime_set(0, delay_in_us * 1000);
+ if (priv->timer)
+ hrtimer_start(priv->timer, gmac_schdule_time, HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+
+ printk("TSP zx29 gmac net open\n");
+
+ return 0;
+}
+
+static int zx29_gmac_stop(struct net_device *ndev)
+{
+ unsigned long flags = 0;
+ int ret = 0;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (!priv->stopped) {
+ spin_lock_irqsave(&priv->lock, flags);
+#ifdef GMAC_NO_INT
+ ret = hrtimer_cancel(priv->timer);
+ if (ret < 0) {
+ BUG_ON(1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return ret;
+ }
+#endif
+
+ priv->stopped = 1;
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ phy_stop(priv->phydev);
+ gmac_hw_deinit(ndev);
+
+ memset(&ndev->stats, 0, sizeof(struct net_device_stats));
+ spin_unlock_irqrestore(&priv->lock, flags);
+ printk("TSP zx29 gmac net stop\n");
+ }
+ return 0;
+}
+
+
+static netdev_tx_t zx29_gmac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ unsigned long flags;
+ unsigned len;
+ struct sk_buff *skb_old;
+ struct bd_tx *tx;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (0 == priv->link.isup) {
+ dev_kfree_skb_any(skb);
+ printk("TSP zx29 gmac xmit phy not link\n");
+ return NETDEV_TX_OK; /* ? */
+ }
+
+ spin_lock_irqsave(&priv->lock, flags);
+ if(priv->stopped)
+ {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+
+ printk("zx_net_start_xmit when stopped\n");
+
+ return NETDEV_TX_OK;
+ }
+
+ tx = get_tx_bd(ndev);
+
+ if (!tx) {
+ spin_unlock_irqrestore(&priv->lock,flags);
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+ priv->tx_bd_offset++;
+ priv->tx_bd_offset %= GMAC_TX_BD_NUM;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ if(skb->len > ETH_FRAME_LEN + 4) /* why 4*/
+ printk("TSP zx29 gmac start xmit len too long\n");
+
+// v7_dma_map_area(skb->data, skb->len, DMA_TO_DEVICE);
+ dma_map(skb->data, skb->len, DMA_TO_DEVICE);
+ if (NULL == skb)
+ BUG_ON(1);
+
+ len = MIN(skb->len, GMAC_FRAME_LEN - NET_IP_ALIGN);
+
+ tx->TDES0 |= (0x07 << 28);
+// tx->dma_buf = virt_to_phys_ap((unsigned long)skb->data);
+ tx->dma_buf = virt_to_phys_ap_new((unsigned long)skb->data);
+
+ if(tx->dma_buf == NULL)
+ tx->dma_buf = virt_to_phys((unsigned)skb->data);
+ tx->skb = skb;
+
+ tx->TDES1 = len;
+ tx->TDES0 |= DMA_OWNER;
+
+ wmb();
+ ndev->stats.tx_bytes += len;
+ ndev->stats.tx_packets++;
+/* ndev->trans_start = jiffies; */
+
+
+ gmac_trig_transmit((void*)ndev->base_addr);
+// dump_pkt_trace(skb->data, len);
+// printk("[%s]\n", __func__);
+
+ return NETDEV_TX_OK;
+}
+
+static void zx29_gmac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
+{
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ genphy_update_link(priv->phydev);
+#endif
+ priv->link.isup = priv->phydev->link;
+
+ if (0 == priv->link.isup) {
+ printk("TSP zx29 gmac net timeout phy not link\n"); // PHY 未连接
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ } else {
+ printk("TSP zx29 gmac net timeout phy linked\n");
+ gmac_trig_transmit(ndev);
+ gmac_trig_receive(ndev);
+
+ netif_carrier_on(ndev);
+ netif_wake_queue(ndev);
+/* ndev->trans_start = jiffies; */ /* modify */
+ ndev->stats.tx_errors++;
+ ndev->stats.tx_dropped++;
+ }
+}
+
+void __iomem *base_clk = NULL;
+void __iomem *base_phy_release = NULL;
+
+static int zx29_gmac_phy_disable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+
+ enum of_gpio_flags flags;
+ unsigned long flag;
+ int gpio = 0;
+ int ret = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if (ndev && !priv->stopped) {
+ if (netif_running(ndev)) {
+
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+ printk("[%s] netif_running\n", __func__);
+
+ gpio_direction_output(priv->gpio_power[0], 0);
+
+ gmac_stop((void*)ndev->base_addr);
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+// netif_device_detach(ndev);
+ }
+ pm_relax(&pdev->dev);
+ // printk("[%s] sleep\n");
+ }
+#endif
+ //printk("[%s] exit\n", __func__);
+ return 0;
+}
+
+static int zx29_gmac_phy_enable(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ int ret = 0;
+ int status = 0;
+ int islink = 0;
+ unsigned int num= 0;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ if(ndev && priv->stopped) {
+ pm_stay_awake(&pdev->dev);
+ if( netif_running(ndev)) {
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+// netif_device_attach(ndev);
+ }
+ }
+#endif
+ return 0;
+}
+
+#define C45_READ 1
+#define C45_WRITE 0
+static int zx29_c22_2_c45(struct phy_device *phydev, int addr, u16 devad, u32 regnum, int rw, int write_val)
+{
+ int val = 0;
+ phy_lock_mdio_bus(phydev);
+ /* Write the desired MMD Devad */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL, devad);
+ /* Write the desired MMD register address */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, regnum);
+ /* Select the Function : DATA with no post increment */
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_CTRL,
+ devad | MII_MMD_CTRL_NOINCR);
+ /* Read the content of the MMD's selected register */
+ if (rw == C45_READ)
+ val = __mdiobus_read(phydev->mdio.bus, addr, MII_MMD_DATA);
+ else
+ __mdiobus_write(phydev->mdio.bus, addr, MII_MMD_DATA, write_val);
+ phy_unlock_mdio_bus(phydev);
+
+ return val;
+}
+
+static int zx29_c45_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
+{
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ u16 val = mii_data->val_in;
+ bool change_autoneg = false;
+ int prtad, devad, reg_num;
+
+ switch (cmd) {
+ case SIOCGMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);//phy id
+ devad = mdio_phy_id_devad(mii_data->phy_id);//dev id / mmd
+ reg_num = mii_data->reg_num;
+ mii_data->val_out = zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_READ, 0);
+ return 0;
+
+ case SIOCSMIIREG:
+ prtad = mdio_phy_id_prtad(mii_data->phy_id);
+ devad = mdio_phy_id_devad(mii_data->phy_id);
+ reg_num = mii_data->reg_num;
+
+ if (prtad == phydev->mdio.addr) {
+ switch (devad) {
+ case MII_BMCR:
+ if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0) {
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_DISABLE;
+ if (val & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ if (val & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (val & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else phydev->speed = SPEED_10;
+ }
+ else {
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ change_autoneg = true;
+ phydev->autoneg = AUTONEG_ENABLE;
+ }
+ break;
+ case MII_ADVERTISE:
+ mii_adv_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ case MII_CTRL1000:
+ mii_ctrl1000_mod_linkmode_adv_t(phydev->advertising,
+ val);
+ change_autoneg = true;
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+
+ zx29_c22_2_c45(phydev, prtad, devad, reg_num, C45_WRITE, val);
+
+ if (prtad == phydev->mdio.addr &&
+ devad == MII_BMCR &&
+ val & BMCR_RESET)
+ return phy_init_hw(phydev);
+
+ if (change_autoneg)
+ return phy_start_aneg(phydev);
+
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int zx29_gmac_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
+{
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+ struct mii_ioctl_data *mii_data = if_mii(ifr);
+ int is_c45 = mdio_phy_id_is_c45(mii_data->phy_id);
+
+ if (!(netif_running(ndev)))
+ return -EINVAL;
+ if (!priv->phydev)
+ return -EINVAL;
+ if (cmd == SIOCDISABLEPHY)
+ return zx29_gmac_phy_disable(ndev->dev.parent);
+
+ if (cmd == SIOCENABLEPHY)
+ return zx29_gmac_phy_enable(ndev->dev.parent);
+
+ if (is_c45)
+ return zx29_c45_mii_ioctl(priv->phydev, ifr, cmd);
+
+ return phy_mii_ioctl(priv->phydev, ifr, cmd);
+}
+
+static int eth_change_mtu(struct net_device *ndev, int new_mtu)
+{
+ if (new_mtu < 68 || new_mtu > ETH_DATA_LEN)
+ return -EINVAL;
+ ndev->mtu = new_mtu;
+ return 0;
+}
+
+static int zx29_gmac_set_mac_address(struct net_device *ndev, void *p)
+{
+ int ret = eth_mac_addr(ndev, p);
+ if (!ret) {
+ gmac_update_mac(ndev);
+ printk(" zx29 gmac set mac addr ok\n");
+ }
+ return ret;
+}
+
+
+static int zx29_gmac_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ unsigned long flag;
+
+ if(ndev) {
+ if(netif_running(ndev)) {
+// netif_device_detach(ndev);
+// gmac_stop((void*)ndev->base_addr);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ phy_stop(priv->phydev);
+ spin_lock_irqsave(&priv->lock, flag);
+ netif_stop_queue(ndev);
+ netif_carrier_off(ndev);
+ priv->stopped = 1;
+
+#ifdef GMAC_NO_INT
+ hrtimer_cancel(priv->timer);
+#endif
+
+ printk("[%s] netif_running\n", __func__);
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gmac_stop((void*)ndev->base_addr);
+#else
+ gmac_stop((void*)ndev->base_addr);
+ gpio_direction_output(priv->gpio_power[0], 0);
+#endif
+ spin_unlock_irqrestore(&priv->lock, flag);
+
+#endif
+ }
+ }
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_sleep_state(&pdev->dev);
+#endif
+ return 0;
+}
+
+static int zx29_gmac_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ volatile unsigned int *gmac = NULL;
+ void __iomem *base = NULL;
+ gmac = (unsigned *)ndev->base_addr;
+ unsigned long flag = 0;
+
+#ifndef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ pinctrl_pm_select_default_state(&pdev->dev);
+#endif
+ if(ndev) {
+ if(netif_running(ndev)) {
+// gmac_start((void*)ndev->base_addr);
+// netif_device_attach(ndev);
+// zx29_gmac_phy_enable(dev);
+#ifdef CONFIG_BOOT_WITHOUT_LOCK
+ printk("[%s] enter\n", __func__);
+ spin_lock_irqsave(&priv->lock, flag);
+ gpio_direction_output(priv->gpio_power[0], 1);
+
+ base = base_clk;
+ gmac_set_clk();
+
+ base = base_phy_release;
+ gmac_phy_release();
+
+ mdelay(500); //icplus ping need
+
+ priv->phydev->drv->config_init(priv->phydev);
+ gmac_hw_init(ndev);
+
+ netif_carrier_on(ndev);
+
+ phy_start(priv->phydev);
+ netif_start_queue(ndev);
+
+#ifdef GMAC_NO_INT
+ hrtimer_start(priv->timer, ktime_set(0, GTIMER_INTERVAL * 1000), HRTIMER_MODE_REL);
+#endif
+
+ priv->stopped = 0;
+ spin_unlock_irqrestore(&priv->lock, flag);
+ printk("[%s] enter\n", __func__);
+#endif
+
+ }
+ }
+ return 0;
+}
+
+static const struct ethtool_ops zx29_gmac_ethtool_ops = {
+ .get_link = zx29_gmac_get_link,
+ .get_link_ksettings = phy_ethtool_get_link_ksettings,
+ .set_link_ksettings = phy_ethtool_set_link_ksettings,
+ /* other func */
+};
+
+static const struct net_device_ops zx29_gmac_netdev_ops = {
+ .ndo_open = zx29_gmac_open,
+ .ndo_stop = zx29_gmac_stop,
+ .ndo_start_xmit = zx29_gmac_start_xmit,
+ .ndo_tx_timeout = zx29_gmac_tx_timeout,
+ .ndo_do_ioctl = zx29_gmac_ioctl,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_set_mac_address = zx29_gmac_set_mac_address,
+};
+
+
+
+ssize_t show_fun(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ int status = 0;
+ volatile unsigned *gmac = (unsigned *)ndev->base_addr;
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ printk("MAC(1000) :0x%x\n", MAC(0x1000));
+ printk("MAC(1004) :0x%x\n", MAC(0x1004));
+ printk("MAC(1008) :0x%x\n", MAC(0x1008));
+ printk("MAC(100c) :0x%x\n", MAC(0x100c));
+ printk("MAC(1010) :0x%x\n", MAC(0x1010));
+ printk("MAC(1014) int status:0x%x\n", MAC(0x1014));
+ printk("MAC(1018) :0x%x\n", MAC(0x1018));
+ printk("MAC(101c) :0x%x\n", MAC(0x101c));
+ printk("MAC(0000) :0x%x\n", MAC(0x0000));
+ printk("MAC(0004) :0x%x\n", MAC(0x0004));
+ printk("MAC(0010) :0x%x\n", MAC(0x0010));
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 1);
+ printk("phy status:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 0, 1);
+ printk("phy status port0:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 1, 1);
+ printk("phy status port1:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 2, 1);
+ printk("phy status port2:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 3, 1);
+ printk("phy status port3:0x%x\n", status);
+ status = mdiobus_read(priv->phydev->mdio.bus, 4, 1);
+ printk("phy status port4:0x%x\n", status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 20);
+ status |= 0x4;
+ mdiobus_write(priv->phydev->mdio.bus, 21, 20, status);
+
+ status = mdiobus_read(priv->phydev->mdio.bus, 21, 21);
+ printk("phy status loop port:0x%x\n", status);
+
+
+ return 0;
+}
+
+ssize_t store_fun(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ printk("[%s]", __func__);
+ return 1;
+}
+
+
+ssize_t mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x", &rd_wt, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+ }
+
+ return count;
+}
+
+
+ssize_t free_mdio_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int mmd = 0;
+ int reg = 0;
+
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, 8, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ priv->phydev->mdio.addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e));
+
+ return 0;
+}
+
+ssize_t free_mdio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ int ret = 0;
+ int mmd = 0;
+ int reg = 0;
+ int rd_wt = 0;/* rd:0, wt:1 */
+ int val = 0;
+ int phy_addr = 8;
+ char *kern_buf = NULL;
+
+ printk(KERN_INFO "%s input str=%s,nbytes=%d \n", __func__, buf, count);
+
+ ret = sscanf(buf, "%x,%x,%x,%x,%x", &rd_wt, &phy_addr, &mmd, ®, &val);
+ if (ret < 4) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input 0x%x,0x%x,0x%x,0x%x,0x%x\n",
+ ret, rd_wt, phy_addr, mmd, reg, val);
+ return count;
+ }
+
+ if (rd_wt !=0 && rd_wt !=1) {
+ printk("please input with format: rd_wt,phy_addr,devad,reg,val\n"
+ "0:rd, 1:wt, if rd, val default input 0\n");
+ return ret ? ret : count;
+ }
+
+ if (rd_wt == 0) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ if (rd_wt == 1) {
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, val);
+
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, phy_addr, 0x0d, 0x4000 | mmd);
+ printk("phyaddr:0x%x,devad:0x%x,reg:0x%x,val=0x%x\n",
+ phy_addr,
+ mmd,
+ reg,
+ mdiobus_read(priv->phydev->mdio.bus, phy_addr, 0x0e));
+ }
+
+ return count;
+}
+
+extern int debug_on;
+ssize_t debug_on_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if (ret < 1) {
+ printk(KERN_INFO "gmac: failed to read user buf, ret=%d, input %d\n",
+ ret,val);
+ return count;
+ }
+ debug_on = val;
+ return count;
+}
+
+ssize_t debug_on_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+
+ if (debug_on)
+ memcpy(buf, "on", 3);
+ else
+ memcpy(buf, "off", 4);
+ return 0;
+}
+
+/*jb.qi add for gamc power down on 20231116 start*/
+
+extern int gmac_power = 1;
+int gmac_power_flag = 0;
+
+ssize_t gmac_power_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int val = 0;
+ int ret;
+ ret = sscanf(buf, "%d", &val);
+ if(ret < 1)
+ {
+ printk(KERN_INFO "gmac: failed ti read user buf, ret=%d, input %d\n", ret,val);
+ return count;
+ }
+ gmac_power = val;
+ gpio_direction_output(gmac_power_flag, val);
+ return count;
+}
+
+ssize_t gmac_power_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ if(gmac_power)
+ memcpy(buf, "on",3);
+ else
+ memcpy(buf, "off", 4);
+
+ printk("gmac_power %s\n", buf);
+ return 0;
+
+}
+/*jb.qi add for gamc power down on 20231116 end */
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 start*/
+static int mode_type = -1;
+static int enter_only_one = 0;
+
+ssize_t gmac_master_or_slave_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///read mode_type
+ ret = sscanf(buf, "%d", &mode_type);
+ if (ret < 1) {
+ printk(KERN_ERR "Please enter the number 0-3 to enable the corresponding mode \n"
+ "Enter values in the non-0-3 range to get pattern description \n");
+ return count;
+ }
+
+ ///Judgment model
+ if (mode_type < 0 || mode_type > 3) {
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ return ret ? ret : count;
+ }
+
+ ///Set the Ethernet slave mode
+ if (mode_type == 0) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val & (~BIT(14)));
+ }
+ ///Set the Ethernet master mode
+ else if (mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, val | BIT(14));
+ }
+ return count;
+}
+
+ssize_t gmac_master_or_slave_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ int mmd = 0;
+ int reg = 0;
+ int val = 0;
+ int len = 0;
+ int ret;
+ struct platform_device *pdev = to_platform_device(dev);
+ if(!pdev){
+ printk(KERN_ERR "%s : %s pdev : %x \n", __func__, __LINE__, pdev);
+ return -1;
+ }
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ if(!ndev){
+ printk(KERN_ERR "%s : %s ndev : %x \n", __func__, __LINE__, ndev);
+ return -1;
+ }
+ struct zx29_gmac_dev *priv = (struct zx29_gmac_dev *)netdev_priv(ndev);
+ if(!priv){
+ printk(KERN_ERR "%s : %s priv : %x \n", __func__, __LINE__, priv);
+ return -1;
+ }
+
+ ///Reentrant prevention
+ if(enter_only_one == 1)
+ {
+ return 0;
+ }
+ enter_only_one = 1;
+
+ ///Read the network master/slave
+ if (mode_type == 0 || mode_type == 1) {
+ mmd = 0x1;
+ reg = 0x834;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e) & BIT(14);
+ if(val)
+ memcpy(buf, "Master\n",7);
+ else
+ memcpy(buf, "Slave\n", 6);
+
+ printk(KERN_DEBUG "mode_type %d - gmac_master_or_slave is %s\n", mode_type, buf);
+
+ }
+ ///Obtain the cable quality SQI value
+ else if(mode_type == 2){
+ mmd = 0x1;
+ reg = 0x8B10;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "0x%x\n", val);
+ sprintf(buf, "SQI : 0x%x\n", val);
+ printk(KERN_DEBUG "mode_type %d - SQI is 0x%x", mode_type, val);
+
+ }
+ ///Obtain short circuit, open circuit and normal connection of VCT
+ else if(mode_type == 3){
+ ///--TDR Enable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, BIT(14) | BIT(12));
+ msleep(10);
+ ///--Read VCT
+ mmd = 0x1;
+ reg = 0x8B02;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ printk(KERN_DEBUG "Open status: %s - Short status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ sprintf(buf, "Open status: %s\nShort status: %s\n",
+ (val & BIT(1)) ? "Open" : "Normal", (val & BIT(0)) ? "Short" : "Normal");
+ reg = 0x8B01;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ val = mdiobus_read(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e);
+ sprintf(buf, "%sDistance status: 0x%x\n", buf, val);
+ printk(KERN_DEBUG "mode_type %d - Distance status is 0x%x\n", mode_type, val);
+
+ ///--TDR Disable
+ mmd = 0x1;
+ reg = 0x8B00;
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, reg);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0d, 0x4000 | mmd);
+ mdiobus_write(priv->phydev->mdio.bus, priv->phydev->mdio.addr, 0x0e, 0);
+
+ }
+ ///Get model help information
+ else{
+ sprintf(buf, "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ printk(KERN_DEBUG "Please enter the number range 0-3\n"
+ "0: Set the slave mode \n"
+ "1: Set the main mode \n"
+ "2: indicates setting SQI value view mode \n"
+ "3: Set the VCT value view mode \n"
+ "After the mode is set, the corresponding value can be obtained\n");
+ }
+ enter_only_one = 0;
+ return strlen(buf);
+
+}
+
+/*zw.wang add for switching the primary/secondary mode of gmac on 20240118 end */
+
+static DEVICE_ATTR(gmac_test, 0664, show_fun, store_fun);
+static DEVICE_ATTR(mdio_test, 0664, mdio_show, mdio_store);
+static DEVICE_ATTR(free_mdio, 0664, free_mdio_show, free_mdio_store);
+static DEVICE_ATTR(debug_on, 0664, debug_on_show, debug_on_store);
+static DEVICE_ATTR(gmac_power, 0664, gmac_power_show, gmac_power_store);//jb.qi add for gamc power down on 20231116
+static DEVICE_ATTR(gmac_master_or_slave, 0664, gmac_master_or_slave_show, gmac_master_or_slave_store);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+
+static int zx29_gmac_probe(struct platform_device *pdev)
+{
+ struct zx29_gmac_dev *prv = NULL;
+ struct net_device *ndev = alloc_etherdev(sizeof(struct zx29_gmac_dev));
+ volatile unsigned int *gmac = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ int ret = -1;
+ unsigned long i;
+ struct mii_bus *mb;
+ struct resource *iomem;
+ void __iomem *base = NULL;
+ struct pinctrl *pctrl;
+ struct pinctrl_state *state0;
+ enum of_gpio_flags flags;
+ int gpio = 0;
+ char board_name[128] = {"init_failed"};
+
+ printk("[%s] #########zx29_gmac_probe begin.\n", __func__);
+ if (!ndev)
+ return -ENOMEM;
+
+ device_create_file(&pdev->dev, &dev_attr_gmac_test);
+ device_create_file(&pdev->dev, &dev_attr_mdio_test);
+ device_create_file(&pdev->dev, &dev_attr_free_mdio);
+ device_create_file(&pdev->dev, &dev_attr_debug_on);
+ device_create_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_create_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+
+ prv = netdev_priv(ndev);
+ memset(prv, 0, sizeof(*prv));
+ prv->stopped = 1;
+
+ pctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(pctrl)) {
+ dev_warn(&pdev->dev, "Failed to get test pins");
+ pctrl = NULL;
+ goto errirq;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ state0 = pinctrl_lookup_state(pctrl, "state0");
+#else
+ state0 = pinctrl_lookup_state(pctrl, "default");
+#endif
+ if (IS_ERR(state0)) {
+ dev_err(&pdev->dev, "TEST: missing state0\n");
+ goto pinctrl_init_end;
+ }
+
+ if (pinctrl_select_state(pctrl, state0) < 0) {
+ dev_err(&pdev->dev, "setting state0 failed\n");
+ goto pinctrl_init_end;
+ }
+
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ prv->gpio_power[2] = of_get_gpio_flags(pdev->dev.of_node, 2, &flags);
+ ret = gpio_request(prv->gpio_power[2], "phy_power"); /* gpio 51 */
+ gpio_direction_output(prv->gpio_power[2], 1);
+ mdelay(15);
+#endif
+
+ prv->gpio_power[0] = of_get_gpio_flags(pdev->dev.of_node, 0, &flags);
+ ret = gpio_request(prv->gpio_power[0], "gmac_power"); /* gpio 83/124 */
+ gpio_direction_output(prv->gpio_power[0], 1);
+ mdelay(15);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ prv->gpio_power[1] = of_get_gpio_flags(pdev->dev.of_node, 1, &flags);
+ ret = gpio_request(prv->gpio_power[1], "phy_rst"); /* gpio 63 */
+ gpio_direction_output(prv->gpio_power[1], 0);
+ mdelay(10);
+ gpio_direction_output(prv->gpio_power[1], 1);
+ mdelay(15);
+#endif
+
+ SET_NETDEV_DEV(ndev, &pdev->dev); //if not, will panic
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ gmac_power_flag = prv->gpio_power[0];//jb.qi add for gamc power down on 20231116
+ ndev->base_addr = base;/*iomem->start;*/
+ if (!ndev->base_addr)
+ return -ENXIO;
+
+#ifndef GMAC_NO_INT
+ ndev->irq = platform_get_irq(pdev, 0);
+#endif
+ ndev->netdev_ops = &zx29_gmac_netdev_ops;
+ ndev->ethtool_ops = &zx29_gmac_ethtool_ops;
+
+ gmac = (unsigned *)ndev->base_addr;
+
+ dma_disable();
+ mac_disable();
+ mac_int_disable();
+
+ spin_lock_init(&prv->lock);
+
+
+/* wake_lock_init(&prv->wake_lock, WAKE_LOCK_SUSPEND, "gmac_pm"); //what replace?
+ wake_lock(&prv->wake_lock); */
+ device_init_wakeup(&pdev->dev, true);
+
+
+ zx29_gmac_set_macaddr(ndev);
+
+#ifndef GMAC_NO_INT
+ ret = request_irq(ndev->irq, zx29_gmac_interrupt, 0, ndev->name, ndev);
+ if (ret) {
+ printk(KERN_ERR "irq request failed: %d\n", ndev->irq);
+ goto errirq;
+ }
+#endif
+
+ ret = register_netdev(ndev);
+ if (ret) {
+ printk(KERN_ERR "error registering device %s\n",
+ ndev->name);
+ goto errdev;
+ }
+
+ of_property_read_u32(np, "port-nums", &prv->nports);
+ of_property_read_u32(np, "rmii-ports", &prv->rmii_port);
+ prv->base_addr = ndev->base_addr;
+
+ prv->netdev = ndev;
+
+ mb = mdiobus_alloc();
+ if (!mb) {
+ printk(KERN_ERR "error allocating mii bus\n");
+ goto errmii;
+ }
+ mb->name = "zx29_gmac_mii";
+ mb->read = zx29mii_read;
+ mb->write = zx29mii_write;
+ mb->reset = zx29mii_reset;
+ mb->priv = prv;
+ snprintf(mb->id, MII_BUS_ID_SIZE, "%s-%x", "zx29_gmac", 0);
+ of_property_read_u32(np, "port-mask", &mb->phy_mask);
+/* mb->irq = &prv->mii.irq[0]; */
+ for (i = 0; i < PHY_MAX_ADDR; i++) {
+ int n = platform_get_irq(pdev, i + 1); /* devtrrr modify */
+ if (n < 0)
+ n = PHY_POLL;
+ prv->mii.irq[i] = n;
+ mb->irq[i] = n;
+ }
+
+ base = devm_platform_ioremap_resource(pdev, 2);
+ gmac_set_clk();
+ base_clk = base;
+
+ base = devm_platform_ioremap_resource(pdev, 1);
+ gmac_phy_release();
+ base_phy_release = base;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ mdelay(500);
+#else
+ mdelay(10); //zw.wang@20240306 modify. Here, the jl3103 is set as an example, and other phy peripherals need to be optimized according to different reset stability times
+#endif
+
+ ret = mdiobus_register(mb);
+ if (ret < 0) {
+ printk("[%s] mdiobus register failed!\n", __func__);
+ goto errmdioregister;
+ }
+
+ prv->mii.bus = mb;
+ ret = zx29_gmac_phy_start(ndev);
+ if (ret)
+ goto errphystart;
+
+ if (!(prv->phydev->phy_id == 0x00000000 || prv->phydev->phy_id == 0xffffffff)) {
+#ifndef CONFIG_BOOT_WITHOUT_LOCK
+ pm_stay_awake(&pdev->dev);
+#endif
+ strcpy(board_name, "cpe");
+
+ printk("[%s] phy id = 0x%x \n", __func__, prv->phydev->phy_id);
+ printk("set gmac wakelock!\n");
+ } else {
+ strcpy(board_name, "mdl");
+ netif_device_detach(ndev);
+ }
+
+ platform_set_drvdata(pdev, ndev);
+
+ tasklet_init(&prv->tasklet, zx29_gmac_tasklet, (unsigned long)ndev);
+ g_gmac_tasklet = &prv->tasklet;
+
+
+ prv->dma_rx_vir = dma_alloc_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_phy, GFP_KERNEL);
+ if (!prv->dma_rx_vir) { // null, ndev->dev.parent difference?
+ BUG_ON(1);
+ goto errphystart;
+ }
+
+ prv->dma_rx_phy_init = prv->dma_rx_phy;
+ prv->dma_rx_vir_init = prv->dma_rx_vir;
+ prv->dma_tx_phy = prv->dma_rx_phy + GMAC_RX_BUF_LEN;
+ prv->dma_tx_vir = prv->dma_rx_vir + GMAC_RX_BUF_LEN;
+
+#ifdef GMAC_NO_INT
+ sema_init(&prv->sem, 0);
+
+ prv->timer = kzalloc(sizeof(struct hrtimer), GFP_KERNEL);
+ if (!prv->timer) {
+ BUG_ON(1);
+ goto errmalloc;
+ }
+ hrtimer_init(prv->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+
+ prv->timer->function = gmac_timer_callback;
+#endif
+
+ gmac_event_init(board_name);
+/* g_gmac_dev = prv; */ /* no use possible*/
+
+ printk("[%s] probe end\n", __func__);
+ return 0;
+errmalloc:
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, &prv->dma_rx_vir, prv->dma_rx_phy);
+
+
+errphystart:
+ mdiobus_unregister(mb);
+
+
+errmdioregister:
+ mdiobus_free(mb);
+
+errmii:
+ unregister_netdev(ndev);
+
+errdev:
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+
+pinctrl_init_end:
+
+errirq:
+ free_netdev(ndev);
+
+ printk("#########zx29_gmac_probe fail.\n");
+ return ret;
+}
+
+static int zx29_gmac_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ volatile unsigned *gmac = NULL;
+ if (ndev) {
+ struct zx29_gmac_dev *priv = netdev_priv(ndev);
+
+// gpio_direction_output(priv->gpio_power[0], 1);
+// msleep(500);
+ unregister_netdev(ndev);
+
+ phy_disconnect(priv->phydev);
+
+ kobj_gmac_del(NULL);
+
+ mdiobus_unregister(priv->mii.bus);
+ mdiobus_free(priv->mii.bus);
+#ifndef GMAC_NO_INT
+ free_irq(ndev->irq, ndev);
+#endif
+ tasklet_disable(&priv->tasklet);
+ tasklet_kill(&priv->tasklet);
+
+ if (priv->dma_rx_vir)
+ dma_free_coherent(ndev->dev.parent, GMAC_BUF_LEN, priv->dma_rx_vir, priv->dma_rx_phy);
+
+ pm_relax(&pdev->dev);
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ gpio_free(priv->gpio_power[1]);
+#endif
+ gpio_direction_output(priv->gpio_power[0], 0);
+ gpio_free(priv->gpio_power[0]);
+
+ device_remove_file(&pdev->dev, &dev_attr_gmac_test);
+ device_remove_file(&pdev->dev, &dev_attr_mdio_test);
+ device_remove_file(&pdev->dev, &dev_attr_free_mdio);
+ device_remove_file(&pdev->dev, &dev_attr_debug_on);
+ device_remove_file(&pdev->dev, &dev_attr_gmac_power);//jb.qi add for gamc power down on 20231116
+ device_remove_file(&pdev->dev, &dev_attr_gmac_master_or_slave);//zw.wang add for switching the primary/secondary mode of gmac on 20240118
+ }
+ return 0;
+}
+
+static struct dev_pm_ops zx29_gmac_pm_ops = {
+ .suspend = zx29_gmac_suspend,
+ .resume = zx29_gmac_resume,
+};
+
+static const struct of_device_id gmac_match_table[] = {
+ {.compatible = "zte, zx29_gmac",},
+};
+
+static struct platform_driver zx29_gmac_driver = {
+ .probe = zx29_gmac_probe,
+ .remove = zx29_gmac_remove,
+ .driver = {
+ .name = "zx29_gmac",
+ .owner = THIS_MODULE,
+ .pm = &zx29_gmac_pm_ops,
+ .of_match_table = gmac_match_table,
+ },
+};
+
+static int __init zx29_gmac_init(void)
+{
+ return platform_driver_register(&zx29_gmac_driver);
+}
+
+static void __exit zx29_gmac_exit(void)
+{
+ printk("[%s] start exit!\n", __func__);
+ platform_driver_unregister(&zx29_gmac_driver);
+}
+
+module_init(zx29_gmac_init);
+module_exit(zx29_gmac_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ZX29 on chip Ethernet driver");
+MODULE_AUTHOR("zhu jianlinag <zhu.jianliang@zte.com.cn>");
diff --git a/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
new file mode 100755
index 0000000..750580b
--- /dev/null
+++ b/upstream/linux-5.10/drivers/net/ethernet/zte/zx29_gmac_event.c
@@ -0,0 +1,298 @@
+/*
+ * Ethernet driver for zte zx2975xx gmac on chip network device
+ * (c)2008 http://www.zte.com.cn
+ * Authors: zhang dongdong <zhang.dongdong16@zte.com.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/gmac/gmac.h>
+#include "zx29_gmac.h"
+
+extern void v7_dma_map_area(const void *, size_t, int);
+extern unsigned long virt_to_phys_ap(unsigned long virt);
+
+void dma_map(const void * addr, size_t len, int flags)
+{
+ v7_dma_map_area(addr, len, flags);
+}
+EXPORT_SYMBOL(dma_map);
+
+unsigned long virt_to_phys_ap_new(unsigned long virt_addr)
+{
+ return virt_to_phys_ap(virt_addr);
+}
+EXPORT_SYMBOL(virt_to_phys_ap_new);
+
+int debug_on = 0;
+EXPORT_SYMBOL(debug_on);
+
+struct kset *kset_gmac;
+struct kobject *gmackobj = NULL;
+struct kobject *typekobj = NULL;
+char type[8] = { 0 };
+u32 zx29_gmac_plug_state[3] = {0}; /* 0:phy 1:sw_wan 2:sw_lan */
+
+static struct attribute gmac_phy_plug_attr = {
+ .name = "eth_phy_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_wan_plug_attr = {
+ .name = "eth_sw_wan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute gmac_sw_lan_plug_attr = {
+ .name = "eth_sw_lan_state",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute board_type = {
+ .name = "type",
+ .mode = S_IRWXUGO,
+};
+
+static struct attribute *gmac_status_attrs[] = {
+ &gmac_phy_plug_attr,
+ &gmac_sw_wan_plug_attr,
+ &gmac_sw_lan_plug_attr,
+ &board_type,
+ NULL,
+};
+
+ssize_t kobj_gmac_show(struct kobject *kobject,struct attribute *attr,char *buf)
+{
+ unsigned link =0;
+
+ if(!strcmp(attr->name,"eth_phy_state")) {
+ if(zx29_gmac_plug_state[0] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_wan_state")) {
+ if(zx29_gmac_plug_state[1] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if(!strcmp(attr->name,"eth_sw_lan_state")) {
+ if(zx29_gmac_plug_state[2] == 0)
+ sprintf(buf, "%s","0");
+ else
+ sprintf(buf, "%s","1");
+ } else if (!strcmp(attr->name,"type")) {
+ sprintf(buf, "%s", type);
+ } else {
+ printk("invalidate attr name.\n");
+ }
+
+ return strlen(buf);
+}
+
+ssize_t kobj_gmac_store(struct kobject *kobject, struct attribute *attr, const char *buf, size_t size)
+{
+ unsigned int value = 0;
+ value = simple_strtoul(buf, NULL, 4);
+ printk("attrname: %s.\n", attr->name);
+ if (!strcmp(attr->name, "eth_phy_state")) {
+ zx29_gmac_plug_state[0] = value;
+ } else if (!strcmp(attr->name,"eth_sw_wan_state")) {
+ zx29_gmac_plug_state[1] = value;
+ } else if (!strcmp(attr->name,"eth_sw_lan_state")) {
+ zx29_gmac_plug_state[2] = value;
+ } else {
+ printk("invalidate attr name.\n");
+ }
+ return size;
+}
+
+static struct sysfs_ops obj_gmac_sysops = {
+ .show = kobj_gmac_show,
+ .store = kobj_gmac_store,
+};
+
+static void kobj_gmac_release(struct kobject *kobject)
+{
+ printk("[gmac kobj_test: release!]\n");
+}
+
+static void kobj_type_release(struct kobject *kobject)
+{
+ printk("[type kobj_test: release!]\n");
+}
+
+
+void kobj_gmac_del(struct kobject *kobject)
+{
+ kset_unregister(kset_gmac);
+
+ kobject_uevent(typekobj, KOBJ_REMOVE);
+ kobject_del(typekobj);
+ kobject_put(typekobj);
+ kfree(typekobj);
+
+ kobject_uevent(gmackobj, KOBJ_REMOVE);
+ kobject_del(gmackobj);
+ kobject_put(gmackobj);
+
+ kfree(gmackobj);
+
+ printk("[gmac kobj_test: delete!]\n");
+}
+EXPORT_SYMBOL(kobj_gmac_del);
+
+static struct kobj_type gmacktype =
+{ .release = kobj_gmac_release,
+ .sysfs_ops = &obj_gmac_sysops,
+ .default_attrs = gmac_status_attrs,
+};
+
+static struct kobj_type typektype =
+{ .release = kobj_type_release,
+// .sysfs_ops = &obj_gmac_sysops,
+// .default_attrs = gmac_status_attrs,
+};
+
+
+static int kset_filter(struct kset *kset,struct kobject *kobj)
+{
+ printk("kset Filter: kobj %s.\n",kobj->name);
+ return 1;
+}
+
+static const char *kset_name(struct kset *kset,struct kobject *kobj)
+{
+ static char buf[20];
+ printk("Name: kobj %s.\n",kobj->name);
+ sprintf(buf,"%s","gmac");
+ return buf;
+}
+
+static int kset_uevent(struct kset *kset, struct kobject *kobj, struct kobj_uevent_env *env)
+{
+ int i = 0;
+ printk("uevent: kobj %s.\n",kobj->name);
+ while (i < env->envp_idx) {
+ printk("%s.\n",env->envp[i]);
+ i++;
+ }
+
+ return 0;
+}
+
+static struct kset_uevent_ops gmac_uevent_ops =
+{
+ .filter = kset_filter,
+ .name = kset_name,
+ .uevent = kset_uevent,
+};
+
+void gmac_event_notify(GMAC_NOTIFY_EVENT notify_type, void *puf)
+{
+ int rtv = -1;
+ enum kobject_action action = KOBJ_UNBIND;
+ char *envp_phy_ext[] = {"GMACEVENT=gmac_eth_phy",NULL};
+ char *envp_sw_wan_ext[] = {"GMACEVENT=gmac_eth_sw_wan",NULL};
+ char *envp_sw_lan_ext[] = {"GMACEVENT=gmac_eth_sw_lan",NULL};
+
+ switch (notify_type) {
+ case GMAC_ETH_PHY_PLUGIN:
+ printk("gmac eth phy plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[0] = 1;
+ if (gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action, envp_phy_ext);
+ break;
+
+ case GMAC_ETH_PHY_PLUGOUT:
+ printk("gmac eth phy plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[0] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_phy_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGIN:
+ printk("gmac eth switch wan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[1] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_WAN_PLUGOUT:
+ printk("gmac eth switch wan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[1] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_wan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGIN:
+ printk("gmac eth switch lan plugin \n");
+ action = KOBJ_ADD;
+ zx29_gmac_plug_state[2] = 1;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ case GMAC_ETH_SW_LAN_PLUGOUT:
+ printk("gmac eth switch lan plugout \n");
+ action = KOBJ_REMOVE;
+ zx29_gmac_plug_state[2] = 0;
+ if(gmackobj)
+ rtv = kobject_uevent_env(gmackobj, action,envp_sw_lan_ext);
+ break;
+
+ default:
+ printk(KERN_WARNING "UNKWON GMAC EVENT \n");
+ break;
+ }
+
+ printk(KERN_WARNING "rtv:%d \n",rtv);
+}
+
+EXPORT_SYMBOL(gmac_event_notify);
+
+int gmac_event_init(const char *name)
+{
+ int ret = 0;
+ /* 创建并注册 kset_p */
+ gmackobj = kzalloc(sizeof(*gmackobj),GFP_KERNEL);
+ if(!gmackobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+ kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(gmackobj, &gmacktype);
+ kobject_add(gmackobj,&kset_gmac->kobj,"%s","gmacconfig");
+ gmackobj->kset = kset_gmac;
+
+ typekobj = kzalloc(sizeof(*typekobj),GFP_KERNEL);
+ if(!typekobj){
+ printk(KERN_WARNING "mallock gmackobj failed \n");
+ return 0;
+ }
+// kset_gmac = kset_create_and_add("gmac", &gmac_uevent_ops, NULL);
+ kobject_init(typekobj, &typektype);
+ kobject_add(typekobj,&kset_gmac->kobj,"%s",name);
+ typekobj->kset = kset_gmac;
+
+ strcpy(type, name);
+
+ return ret;
+}
+EXPORT_SYMBOL(gmac_event_init);
diff --git a/upstream/linux-5.10/drivers/net/phy/phy_device.c b/upstream/linux-5.10/drivers/net/phy/phy_device.c
new file mode 100755
index 0000000..d9b53ba
--- /dev/null
+++ b/upstream/linux-5.10/drivers/net/phy/phy_device.c
@@ -0,0 +1,3113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Framework for finding and configuring PHYs.
+ * Also contains generic PHY driver
+ *
+ * Author: Andy Fleming
+ *
+ * Copyright (c) 2004 Freescale Semiconductor, Inc.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/bitmap.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mdio.h>
+#include <linux/mii.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/phy_led_triggers.h>
+#include <linux/property.h>
+#include <linux/sfp.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/unistd.h>
+
+MODULE_DESCRIPTION("PHY library");
+MODULE_AUTHOR("Andy Fleming");
+MODULE_LICENSE("GPL");
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_t1_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_basic_t1_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_fibre_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_fibre_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_gbit_all_ports_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_gbit_all_ports_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_features);
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_fec_features);
+
+const int phy_basic_ports_array[3] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_ports_array);
+
+const int phy_fibre_port_array[1] = {
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_fibre_port_array);
+
+const int phy_all_ports_features_array[7] = {
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_MII_BIT,
+ ETHTOOL_LINK_MODE_FIBRE_BIT,
+ ETHTOOL_LINK_MODE_AUI_BIT,
+ ETHTOOL_LINK_MODE_BNC_BIT,
+ ETHTOOL_LINK_MODE_Backplane_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_all_ports_features_array);
+
+const int phy_10_100_features_array[4] = {
+ ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10_100_features_array);
+
+const int phy_basic_t1_features_array[2] = {
+ ETHTOOL_LINK_MODE_TP_BIT,
+ ETHTOOL_LINK_MODE_100baseT1_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_basic_t1_features_array);
+
+const int phy_gbit_features_array[2] = {
+ ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_gbit_features_array);
+
+const int phy_10gbit_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+EXPORT_SYMBOL_GPL(phy_10gbit_features_array);
+
+static const int phy_10gbit_fec_features_array[1] = {
+ ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
+};
+
+__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;
+EXPORT_SYMBOL_GPL(phy_10gbit_full_features);
+
+static const int phy_10gbit_full_features_array[] = {
+ ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+};
+
+//status = phy_read_cl(phydev, MII_BMSR);
+static int phy_read_cl(struct phy_device *phydev, u32 regnum)
+{
+ int val = 0;
+
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 1);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0e, regnum);
+ mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 0x0d, 0x4000 | 1);
+ val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 0x0e);
+
+ return val;
+}
+
+static void features_init(void)
+{
+ /* 10/100 half/full*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_basic_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_basic_features);
+
+ /* 100 full, TP */
+ linkmode_set_bit_array(phy_basic_t1_features_array,
+ ARRAY_SIZE(phy_basic_t1_features_array),
+ phy_basic_t1_features);
+
+ /* 10/100 half/full + 1000 half/full */
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_features);
+
+ /* 10/100 half/full + 1000 half/full + fibre*/
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_fibre_features);
+ linkmode_set_bit_array(phy_fibre_port_array,
+ ARRAY_SIZE(phy_fibre_port_array),
+ phy_gbit_fibre_features);
+
+ /* 10/100 half/full + 1000 half/full + TP/MII/FIBRE/AUI/BNC/Backplane*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_gbit_all_ports_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_gbit_all_ports_features);
+
+ /* 10/100 half/full + 1000 half/full + 10G full*/
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10_100_features_array,
+ ARRAY_SIZE(phy_10_100_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_gbit_features_array,
+ ARRAY_SIZE(phy_gbit_features_array),
+ phy_10gbit_features);
+ linkmode_set_bit_array(phy_10gbit_features_array,
+ ARRAY_SIZE(phy_10gbit_features_array),
+ phy_10gbit_features);
+
+ /* 10/100/1000/10G full */
+ linkmode_set_bit_array(phy_all_ports_features_array,
+ ARRAY_SIZE(phy_all_ports_features_array),
+ phy_10gbit_full_features);
+ linkmode_set_bit_array(phy_10gbit_full_features_array,
+ ARRAY_SIZE(phy_10gbit_full_features_array),
+ phy_10gbit_full_features);
+ /* 10G FEC only */
+ linkmode_set_bit_array(phy_10gbit_fec_features_array,
+ ARRAY_SIZE(phy_10gbit_fec_features_array),
+ phy_10gbit_fec_features);
+}
+
+void phy_device_free(struct phy_device *phydev)
+{
+ put_device(&phydev->mdio.dev);
+}
+EXPORT_SYMBOL(phy_device_free);
+
+static void phy_mdio_device_free(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_free(phydev);
+}
+
+static void phy_device_release(struct device *dev)
+{
+ kfree(to_phy_device(dev));
+}
+
+static void phy_mdio_device_remove(struct mdio_device *mdiodev)
+{
+ struct phy_device *phydev;
+
+ phydev = container_of(mdiodev, struct phy_device, mdio);
+ phy_device_remove(phydev);
+}
+
+static struct phy_driver genphy_driver;
+
+static LIST_HEAD(phy_fixup_list);
+static DEFINE_MUTEX(phy_fixup_lock);
+
+static bool mdio_bus_phy_may_suspend(struct phy_device *phydev)
+{
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (!drv || !phydrv->suspend)
+ return false;
+
+ /* PHY not attached? May suspend if the PHY has not already been
+ * suspended as part of a prior call to phy_disconnect() ->
+ * phy_detach() -> phy_suspend() because the parent netdev might be the
+ * MDIO bus driver and clock gated at this point.
+ */
+ if (!netdev)
+ goto out;
+
+ if (netdev->wol_enabled)
+ return false;
+
+ /* As long as not all affected network drivers support the
+ * wol_enabled flag, let's check for hints that WoL is enabled.
+ * Don't suspend PHY if the attached netdev parent may wake up.
+ * The parent may point to a PCI device, as in tg3 driver.
+ */
+ if (netdev->dev.parent && device_may_wakeup(netdev->dev.parent))
+ return false;
+
+ /* Also don't suspend PHY if the netdev itself may wakeup. This
+ * is the case for devices w/o underlaying pwr. mgmt. aware bus,
+ * e.g. SoC devices.
+ */
+ if (device_may_wakeup(&netdev->dev))
+ return false;
+
+out:
+ return !phydev->suspended;
+}
+
+static __maybe_unused int mdio_bus_phy_suspend(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ /* We must stop the state machine manually, otherwise it stops out of
+ * control, possibly with the phydev->lock held. Upon resume, netdev
+ * may call phy routines that try to grab the same lock, and that may
+ * lead to a deadlock.
+ */
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_stop_machine(phydev);
+
+ if (!mdio_bus_phy_may_suspend(phydev))
+ return 0;
+
+ phydev->suspended_by_mdio_bus = 1;
+
+ return phy_suspend(phydev);
+}
+
+static __maybe_unused int mdio_bus_phy_resume(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ int ret;
+
+ if (!phydev->suspended_by_mdio_bus)
+ goto no_resume;
+
+ phydev->suspended_by_mdio_bus = 0;
+
+ ret = phy_init_hw(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = phy_resume(phydev);
+ if (ret < 0)
+ return ret;
+no_resume:
+ if (phydev->attached_dev && phydev->adjust_link)
+ phy_start_machine(phydev);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mdio_bus_phy_pm_ops, mdio_bus_phy_suspend,
+ mdio_bus_phy_resume);
+
+/**
+ * phy_register_fixup - creates a new phy_fixup and adds it to the list
+ * @bus_id: A string which matches phydev->mdio.dev.bus_id (or PHY_ANY_ID)
+ * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY)
+ * It can also be PHY_ANY_UID
+ * @phy_uid_mask: Applied to phydev->phy_id and fixup->phy_uid before
+ * comparison
+ * @run: The actual code to be run when a matching PHY is found
+ */
+int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ struct phy_fixup *fixup = kzalloc(sizeof(*fixup), GFP_KERNEL);
+
+ if (!fixup)
+ return -ENOMEM;
+
+ strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id));
+ fixup->phy_uid = phy_uid;
+ fixup->phy_uid_mask = phy_uid_mask;
+ fixup->run = run;
+
+ mutex_lock(&phy_fixup_lock);
+ list_add_tail(&fixup->list, &phy_fixup_list);
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_register_fixup);
+
+/* Registers a fixup to be run on any PHY with the UID in phy_uid */
+int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_uid);
+
+/* Registers a fixup to be run on the PHY with id string bus_id */
+int phy_register_fixup_for_id(const char *bus_id,
+ int (*run)(struct phy_device *))
+{
+ return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run);
+}
+EXPORT_SYMBOL(phy_register_fixup_for_id);
+
+/**
+ * phy_unregister_fixup - remove a phy_fixup from the list
+ * @bus_id: A string matches fixup->bus_id (or PHY_ANY_ID) in phy_fixup_list
+ * @phy_uid: A phy id matches fixup->phy_id (or PHY_ANY_UID) in phy_fixup_list
+ * @phy_uid_mask: Applied to phy_uid and fixup->phy_uid before comparison
+ */
+int phy_unregister_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask)
+{
+ struct list_head *pos, *n;
+ struct phy_fixup *fixup;
+ int ret;
+
+ ret = -ENODEV;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_safe(pos, n, &phy_fixup_list) {
+ fixup = list_entry(pos, struct phy_fixup, list);
+
+ if ((!strcmp(fixup->bus_id, bus_id)) &&
+ ((fixup->phy_uid & phy_uid_mask) ==
+ (phy_uid & phy_uid_mask))) {
+ list_del(&fixup->list);
+ kfree(fixup);
+ ret = 0;
+ break;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_unregister_fixup);
+
+/* Unregisters a fixup of any PHY with the UID in phy_uid */
+int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask)
+{
+ return phy_unregister_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_uid);
+
+/* Unregisters a fixup of the PHY with id string bus_id */
+int phy_unregister_fixup_for_id(const char *bus_id)
+{
+ return phy_unregister_fixup(bus_id, PHY_ANY_UID, 0xffffffff);
+}
+EXPORT_SYMBOL(phy_unregister_fixup_for_id);
+
+/* Returns 1 if fixup matches phydev in bus_id and phy_uid.
+ * Fixups can be set to match any in one or more fields.
+ */
+static int phy_needs_fixup(struct phy_device *phydev, struct phy_fixup *fixup)
+{
+ if (strcmp(fixup->bus_id, phydev_name(phydev)) != 0)
+ if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ return 0;
+
+ if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+ (phydev->phy_id & fixup->phy_uid_mask))
+ if (fixup->phy_uid != PHY_ANY_UID)
+ return 0;
+
+ return 1;
+}
+
+/* Runs any matching fixups for this phydev */
+static int phy_scan_fixups(struct phy_device *phydev)
+{
+ struct phy_fixup *fixup;
+
+ mutex_lock(&phy_fixup_lock);
+ list_for_each_entry(fixup, &phy_fixup_list, list) {
+ if (phy_needs_fixup(phydev, fixup)) {
+ int err = fixup->run(phydev);
+
+ if (err < 0) {
+ mutex_unlock(&phy_fixup_lock);
+ return err;
+ }
+ phydev->has_fixups = true;
+ }
+ }
+ mutex_unlock(&phy_fixup_lock);
+
+ return 0;
+}
+
+static int phy_bus_match(struct device *dev, struct device_driver *drv)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
+ int i;
+
+ if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
+ return 0;
+
+ if (phydrv->match_phy_device)
+ return phydrv->match_phy_device(phydev);
+
+ if (phydev->is_c45) {
+ for (i = 1; i < num_ids; i++) {
+ if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ continue;
+
+ if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->c45_ids.device_ids[i] &
+ phydrv->phy_id_mask))
+ return 1;
+ }
+ return 0;
+ } else {
+ return (phydrv->phy_id & phydrv->phy_id_mask) ==
+ (phydev->phy_id & phydrv->phy_id_mask);
+ }
+}
+
+static ssize_t
+phy_id_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "0x%.8lx\n", (unsigned long)phydev->phy_id);
+}
+static DEVICE_ATTR_RO(phy_id);
+
+static ssize_t
+phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ const char *mode = NULL;
+
+ if (phy_is_internal(phydev))
+ mode = "internal";
+ else
+ mode = phy_modes(phydev->interface);
+
+ return sprintf(buf, "%s\n", mode);
+}
+static DEVICE_ATTR_RO(phy_interface);
+
+static ssize_t
+phy_has_fixups_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", phydev->has_fixups);
+}
+static DEVICE_ATTR_RO(phy_has_fixups);
+
+static struct attribute *phy_dev_attrs[] = {
+ &dev_attr_phy_id.attr,
+ &dev_attr_phy_interface.attr,
+ &dev_attr_phy_has_fixups.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(phy_dev);
+
+static const struct device_type mdio_bus_phy_type = {
+ .name = "PHY",
+ .groups = phy_dev_groups,
+ .release = phy_device_release,
+ .pm = pm_ptr(&mdio_bus_phy_pm_ops),
+};
+
+static int phy_request_driver_module(struct phy_device *dev, u32 phy_id)
+{
+ int ret;
+
+ ret = request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT,
+ MDIO_ID_ARGS(phy_id));
+ /* We only check for failures in executing the usermode binary,
+ * not whether a PHY driver module exists for the PHY ID.
+ * Accept -ENOENT because this may occur in case no initramfs exists,
+ * then modprobe isn't available.
+ */
+ if (IS_ENABLED(CONFIG_MODULES) && ret < 0 && ret != -ENOENT) {
+ phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n",
+ ret, (unsigned long)phy_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
+ bool is_c45,
+ struct phy_c45_device_ids *c45_ids)
+{
+ struct phy_device *dev;
+ struct mdio_device *mdiodev;
+ int ret = 0;
+
+ /* We allocate the device, and initialize the default values */
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ mdiodev = &dev->mdio;
+ mdiodev->dev.parent = &bus->dev;
+ mdiodev->dev.bus = &mdio_bus_type;
+ mdiodev->dev.type = &mdio_bus_phy_type;
+ mdiodev->bus = bus;
+ mdiodev->bus_match = phy_bus_match;
+ mdiodev->addr = addr;
+ mdiodev->flags = MDIO_DEVICE_FLAG_PHY;
+ mdiodev->device_free = phy_mdio_device_free;
+ mdiodev->device_remove = phy_mdio_device_remove;
+
+ dev->speed = SPEED_UNKNOWN;
+ dev->duplex = DUPLEX_UNKNOWN;
+ dev->pause = 0;
+ dev->asym_pause = 0;
+ dev->link = 0;
+ dev->port = PORT_TP;
+ dev->interface = PHY_INTERFACE_MODE_GMII;
+
+ dev->autoneg = AUTONEG_ENABLE;
+
+ dev->is_c45 = is_c45;
+ dev->phy_id = phy_id;
+ if (c45_ids)
+ dev->c45_ids = *c45_ids;
+ dev->irq = bus->irq[addr];
+
+ dev_set_name(&mdiodev->dev, PHY_ID_FMT, bus->id, addr);
+ device_initialize(&mdiodev->dev);
+
+ dev->state = PHY_DOWN;
+
+ mutex_init(&dev->lock);
+ INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
+
+ /* Request the appropriate module unconditionally; don't
+ * bother trying to do so only if it isn't already loaded,
+ * because that gets complicated. A hotplug event would have
+ * done an unconditional modprobe anyway.
+ * We don't do normal hotplug because it won't work for MDIO
+ * -- because it relies on the device staying around for long
+ * enough for the driver to get loaded. With MDIO, the NIC
+ * driver will get bored and give up as soon as it finds that
+ * there's no driver _already_ loaded.
+ */
+ if (is_c45 && c45_ids) {
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ int i;
+
+ for (i = 1; i < num_ids; i++) {
+ if (c45_ids->device_ids[i] == 0xffffffff)
+ continue;
+
+ ret = phy_request_driver_module(dev,
+ c45_ids->device_ids[i]);
+ if (ret)
+ break;
+ }
+ } else {
+ ret = phy_request_driver_module(dev, phy_id);
+ }
+
+ if (ret) {
+ put_device(&mdiodev->dev);
+ dev = ERR_PTR(ret);
+ }
+
+ return dev;
+}
+EXPORT_SYMBOL(phy_device_create);
+
+/* phy_c45_probe_present - checks to see if a MMD is present in the package
+ * @bus: the target MII bus
+ * @prtad: PHY package address on the MII bus
+ * @devad: PHY device (MMD) address
+ *
+ * Read the MDIO_STAT2 register, and check whether a device is responding
+ * at this address.
+ *
+ * Returns: negative error number on bus access error, zero if no device
+ * is responding, or positive if a device is present.
+ */
+static int phy_c45_probe_present(struct mii_bus *bus, int prtad, int devad)
+{
+ int stat2;
+
+ stat2 = mdiobus_c45_read(bus, prtad, devad, MDIO_STAT2);
+ if (stat2 < 0)
+ return stat2;
+
+ return (stat2 & MDIO_STAT2_DEVPRST) == MDIO_STAT2_DEVPRST_VAL;
+}
+
+/* get_phy_c45_devs_in_pkg - reads a MMD's devices in package registers.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @dev_addr: MMD address in the PHY.
+ * @devices_in_package: where to store the devices in package information.
+ *
+ * Description: reads devices in package registers of a MMD at @dev_addr
+ * from PHY at @addr on @bus.
+ *
+ * Returns: 0 on success, -EIO on failure.
+ */
+static int get_phy_c45_devs_in_pkg(struct mii_bus *bus, int addr, int dev_addr,
+ u32 *devices_in_package)
+{
+ int phy_reg;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS2);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, dev_addr, MDIO_DEVS1);
+ if (phy_reg < 0)
+ return -EIO;
+ *devices_in_package |= phy_reg;
+
+ return 0;
+}
+
+/**
+ * get_phy_c45_ids - reads the specified addr for its 802.3-c45 IDs.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @c45_ids: where to store the c45 ID information.
+ *
+ * Read the PHY "devices in package". If this appears to be valid, read
+ * the PHY identifiers for each device. Return the "devices in package"
+ * and identifiers in @c45_ids.
+ *
+ * Returns zero on success, %-EIO on bus access error, or %-ENODEV if
+ * the "devices in package" is invalid.
+ */
+static int get_phy_c45_ids(struct mii_bus *bus, int addr,
+ struct phy_c45_device_ids *c45_ids)
+{
+ const int num_ids = ARRAY_SIZE(c45_ids->device_ids);
+ u32 devs_in_pkg = 0;
+ int i, ret, phy_reg;
+
+ /* Find first non-zero Devices In package. Device zero is reserved
+ * for 802.3 c45 complied PHYs, so don't probe it at first.
+ */
+ for (i = 1; i < MDIO_MMD_NUM && (devs_in_pkg == 0 ||
+ (devs_in_pkg & 0x1fffffff) == 0x1fffffff); i++) {
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Check that there is a device present at this
+ * address before reading the devices-in-package
+ * register to avoid reading garbage from the PHY.
+ * Some PHYs (88x3310) vendor space is not IEEE802.3
+ * compliant.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return -EIO;
+
+ if (!ret)
+ continue;
+ }
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, i, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+ }
+
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff) {
+ /* If mostly Fs, there is no device there, then let's probe
+ * MMD 0, as some 10G PHYs have zero Devices In package,
+ * e.g. Cortina CS4315/CS4340 PHY.
+ */
+ phy_reg = get_phy_c45_devs_in_pkg(bus, addr, 0, &devs_in_pkg);
+ if (phy_reg < 0)
+ return -EIO;
+
+ /* no device there, let's get out of here */
+ if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+ }
+
+ /* Now probe Device Identifiers for each device present. */
+ for (i = 1; i < num_ids; i++) {
+ if (!(devs_in_pkg & (1 << i)))
+ continue;
+
+ if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
+ /* Probe the "Device Present" bits for the vendor MMDs
+ * to ignore these if they do not contain IEEE 802.3
+ * registers.
+ */
+ ret = phy_c45_probe_present(bus, addr, i);
+ if (ret < 0)
+ return ret;
+
+ if (!ret)
+ continue;
+ }
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID1);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] = phy_reg << 16;
+
+ phy_reg = mdiobus_c45_read(bus, addr, i, MII_PHYSID2);
+ if (phy_reg < 0)
+ return -EIO;
+ c45_ids->device_ids[i] |= phy_reg;
+ }
+
+ c45_ids->devices_in_package = devs_in_pkg;
+ /* Bit 0 doesn't represent a device, it indicates c22 regs presence */
+ c45_ids->mmds_present = devs_in_pkg & ~BIT(0);
+
+ return 0;
+}
+
+/**
+ * get_phy_c22_id - reads the specified addr for its clause 22 ID.
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @phy_id: where to store the ID retrieved.
+ *
+ * Read the 802.3 clause 22 PHY ID from the PHY at @addr on the @bus,
+ * placing it in @phy_id. Return zero on successful read and the ID is
+ * valid, %-EIO on bus access error, or %-ENODEV if no device responds
+ * or invalid ID.
+ */
+static int get_phy_c22_id(struct mii_bus *bus, int addr, u32 *phy_id)
+{
+ int phy_reg;
+
+ /* Grab the bits from PHYIR1, and put them in the upper half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#ifdef CONFIG_MDIO_C45 //zw.wang Customer chooses phy c22/c45 issues on 20240301
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 2);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id = phy_reg << 16;
+
+ /* Grab the bits from PHYIR2, and put them in the lower half */
+// phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#ifdef CONFIG_MDIO_C45
+ mdiobus_write(bus, addr, 0x0d, 1);
+ mdiobus_write(bus, addr, 0x0e, 3);
+ mdiobus_write(bus, addr, 0x0d, 0x4000 | 1);
+ phy_reg = mdiobus_read(bus, addr, 0x0e);
+#else
+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2);
+#endif
+ if (phy_reg < 0) {
+ /* returning -ENODEV doesn't stop bus scanning */
+ return (phy_reg == -EIO || phy_reg == -ENODEV) ? -ENODEV : -EIO;
+ }
+
+ *phy_id |= phy_reg;
+
+#ifdef CONFIG_MDIO_C45
+ printk("[%s] read with c45 phy id:0x%x\n", __func__, *phy_id);
+#else
+ printk("[%s] read with c22 phy id:0x%x\n", __func__, *phy_id);
+#endif
+ /* If the phy_id is mostly Fs, there is no device there */
+ if ((*phy_id & 0x1fffffff) == 0x1fffffff)
+ return -ENODEV;
+
+ return 0;
+}
+
+/**
+ * get_phy_device - reads the specified PHY device and returns its @phy_device
+ * struct
+ * @bus: the target MII bus
+ * @addr: PHY address on the MII bus
+ * @is_c45: If true the PHY uses the 802.3 clause 45 protocol
+ *
+ * Probe for a PHY at @addr on @bus.
+ *
+ * When probing for a clause 22 PHY, then read the ID registers. If we find
+ * a valid ID, allocate and return a &struct phy_device.
+ *
+ * When probing for a clause 45 PHY, read the "devices in package" registers.
+ * If the "devices in package" appears valid, read the ID registers for each
+ * MMD, allocate and return a &struct phy_device.
+ *
+ * Returns an allocated &struct phy_device on success, %-ENODEV if there is
+ * no PHY present, or %-EIO on bus access error.
+ */
+struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45)
+{
+ struct phy_c45_device_ids c45_ids;
+ u32 phy_id = 0;
+ int r;
+
+ c45_ids.devices_in_package = 0;
+ c45_ids.mmds_present = 0;
+ memset(c45_ids.device_ids, 0xff, sizeof(c45_ids.device_ids));
+
+ if (is_c45)
+ r = get_phy_c45_ids(bus, addr, &c45_ids);
+ else
+ r = get_phy_c22_id(bus, addr, &phy_id);
+
+ if (r)
+ return ERR_PTR(r);
+
+ return phy_device_create(bus, addr, phy_id, is_c45, &c45_ids);
+}
+EXPORT_SYMBOL(get_phy_device);
+
+/**
+ * phy_device_register - Register the phy device on the MDIO bus
+ * @phydev: phy_device structure to be added to the MDIO bus
+ */
+int phy_device_register(struct phy_device *phydev)
+{
+ int err;
+
+ err = mdiobus_register_device(&phydev->mdio);
+ if (err)
+ return err;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ /* Run all of the fixups for this PHY */
+ err = phy_scan_fixups(phydev);
+ if (err) {
+ phydev_err(phydev, "failed to initialize\n");
+ goto out;
+ }
+
+ err = device_add(&phydev->mdio.dev);
+ if (err) {
+ phydev_err(phydev, "failed to add\n");
+ goto out;
+ }
+
+ return 0;
+
+ out:
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+ return err;
+}
+EXPORT_SYMBOL(phy_device_register);
+
+/**
+ * phy_device_remove - Remove a previously registered phy device from the MDIO bus
+ * @phydev: phy_device structure to remove
+ *
+ * This doesn't free the phy_device itself, it merely reverses the effects
+ * of phy_device_register(). Use phy_device_free() to free the device
+ * after calling this function.
+ */
+void phy_device_remove(struct phy_device *phydev)
+{
+ if (phydev->mii_ts)
+ unregister_mii_timestamper(phydev->mii_ts);
+
+ device_del(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ mdiobus_unregister_device(&phydev->mdio);
+}
+EXPORT_SYMBOL(phy_device_remove);
+
+/**
+ * phy_find_first - finds the first PHY device on the bus
+ * @bus: the target MII bus
+ */
+struct phy_device *phy_find_first(struct mii_bus *bus)
+{
+ struct phy_device *phydev;
+ int addr;
+
+ for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+ phydev = mdiobus_get_phy(bus, addr);
+ if (phydev) {
+ printk("[%s] addr:%d\n", __func__, addr);
+ return phydev;
+ }
+ }
+ return NULL;
+}
+EXPORT_SYMBOL(phy_find_first);
+
+static void phy_link_change(struct phy_device *phydev, bool up)
+{
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (up)
+ netif_carrier_on(netdev);
+ else
+ netif_carrier_off(netdev);
+ phydev->adjust_link(netdev);
+ if (phydev->mii_ts && phydev->mii_ts->link_state)
+ phydev->mii_ts->link_state(phydev->mii_ts, phydev);
+}
+
+/**
+ * phy_prepare_link - prepares the PHY layer to monitor link status
+ * @phydev: target phy_device struct
+ * @handler: callback function for link status change notifications
+ *
+ * Description: Tells the PHY infrastructure to handle the
+ * gory details on monitoring link status (whether through
+ * polling or an interrupt), and to call back to the
+ * connected device driver when the link status changes.
+ * If you want to monitor your own link state, don't call
+ * this function.
+ */
+static void phy_prepare_link(struct phy_device *phydev,
+ void (*handler)(struct net_device *))
+{
+ phydev->adjust_link = handler;
+}
+
+/**
+ * phy_connect_direct - connect an ethernet device to a specific phy_device
+ * @dev: the network device to connect
+ * @phydev: the pointer to the phy device
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ */
+int phy_connect_direct(struct net_device *dev, struct phy_device *phydev,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ int rc;
+
+ if (!dev)
+ return -EINVAL;
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ if (rc)
+ return rc;
+
+ phy_prepare_link(phydev, handler);
+ if (phy_interrupt_is_valid(phydev))
+ phy_request_interrupt(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_connect_direct);
+
+/**
+ * phy_connect - connect an ethernet device to a PHY device
+ * @dev: the network device to connect
+ * @bus_id: the id string of the PHY device to connect
+ * @handler: callback function for state change notifications
+ * @interface: PHY device's interface
+ *
+ * Description: Convenience function for connecting ethernet
+ * devices to PHY devices. The default behavior is for
+ * the PHY infrastructure to handle everything, and only notify
+ * the connected driver when the link status changes. If you
+ * don't want, or can't use the provided functionality, you may
+ * choose to call only the subset of functions which provide
+ * the desired functionality.
+ */
+struct phy_device *phy_connect(struct net_device *dev, const char *bus_id,
+ void (*handler)(struct net_device *),
+ phy_interface_t interface)
+{
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(&mdio_bus_type, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_connect_direct(dev, phydev, handler, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_connect);
+
+/**
+ * phy_disconnect - disable interrupts, stop state machine, and detach a PHY
+ * device
+ * @phydev: target phy_device struct
+ */
+void phy_disconnect(struct phy_device *phydev)
+{
+ if (phy_is_started(phydev))
+ phy_stop(phydev);
+
+ if (phy_interrupt_is_valid(phydev))
+ phy_free_interrupt(phydev);
+
+ phydev->adjust_link = NULL;
+
+ phy_detach(phydev);
+}
+EXPORT_SYMBOL(phy_disconnect);
+
+/**
+ * phy_poll_reset - Safely wait until a PHY reset has properly completed
+ * @phydev: The PHY device to poll
+ *
+ * Description: According to IEEE 802.3, Section 2, Subsection 22.2.4.1.1, as
+ * published in 2008, a PHY reset may take up to 0.5 seconds. The MII BMCR
+ * register must be polled until the BMCR_RESET bit clears.
+ *
+ * Furthermore, any attempts to write to PHY registers may have no effect
+ * or even generate MDIO bus errors until this is complete.
+ *
+ * Some PHYs (such as the Marvell 88E1111) don't entirely conform to the
+ * standard and do not fully reset after the BMCR_RESET bit is set, and may
+ * even *REQUIRE* a soft-reset to properly restart autonegotiation. In an
+ * effort to support such broken PHYs, this function is separate from the
+ * standard phy_init_hw() which will zero all the other bits in the BMCR
+ * and reapply all driver-specific and board-specific fixups.
+ */
+static int phy_poll_reset(struct phy_device *phydev)
+{
+ /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
+ int ret, val;
+
+ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+ 50000, 600000, true);
+ if (ret)
+ return ret;
+ /* Some chips (smsc911x) may still need up to another 1ms after the
+ * BMCR_RESET bit is cleared before they are usable.
+ */
+ msleep(1);
+ return 0;
+}
+
+int phy_init_hw(struct phy_device *phydev)
+{
+ int ret = 0;
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (!phydev->drv)
+ return 0;
+
+ if (phydev->drv->soft_reset) {
+ ret = phydev->drv->soft_reset(phydev);
+ /* see comment in genphy_soft_reset for an explanation */
+ if (!ret)
+ phydev->suspended = 0;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ ret = phy_scan_fixups(phydev);
+ if (ret < 0)
+ return ret;
+
+ if (phydev->drv->config_init) {
+ ret = phydev->drv->config_init(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (phydev->drv->config_intr) {
+ ret = phydev->drv->config_intr(phydev);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_init_hw);
+
+void phy_attached_info(struct phy_device *phydev)
+{
+ phy_attached_print(phydev, NULL);
+}
+EXPORT_SYMBOL(phy_attached_info);
+
+#define ATTACHED_FMT "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%s)"
+char *phy_attached_info_irq(struct phy_device *phydev)
+{
+ char *irq_str;
+ char irq_num[8];
+
+ switch(phydev->irq) {
+ case PHY_POLL:
+ irq_str = "POLL";
+ break;
+ case PHY_IGNORE_INTERRUPT:
+ irq_str = "IGNORE";
+ break;
+ default:
+ snprintf(irq_num, sizeof(irq_num), "%d", phydev->irq);
+ irq_str = irq_num;
+ break;
+ }
+
+ return kasprintf(GFP_KERNEL, "%s", irq_str);
+}
+EXPORT_SYMBOL(phy_attached_info_irq);
+
+void phy_attached_print(struct phy_device *phydev, const char *fmt, ...)
+{
+ const char *drv_name = phydev->drv ? phydev->drv->name : "unbound";
+ char *irq_str = phy_attached_info_irq(phydev);
+
+ if (!fmt) {
+ phydev_info(phydev, ATTACHED_FMT "\n",
+ drv_name, phydev_name(phydev),
+ irq_str);
+ } else {
+ va_list ap;
+
+ phydev_info(phydev, ATTACHED_FMT,
+ drv_name, phydev_name(phydev),
+ irq_str);
+
+ va_start(ap, fmt);
+ vprintk(fmt, ap);
+ va_end(ap);
+ }
+ kfree(irq_str);
+}
+EXPORT_SYMBOL(phy_attached_print);
+
+static void phy_sysfs_create_links(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ int err;
+
+ if (!dev)
+ return;
+
+ err = sysfs_create_link(&phydev->mdio.dev.kobj, &dev->dev.kobj,
+ "attached_dev");
+ if (err)
+ return;
+
+ err = sysfs_create_link_nowarn(&dev->dev.kobj,
+ &phydev->mdio.dev.kobj,
+ "phydev");
+ if (err) {
+ dev_err(&dev->dev, "could not add device link to %s err %d\n",
+ kobject_name(&phydev->mdio.dev.kobj),
+ err);
+ /* non-fatal - some net drivers can use one netdevice
+ * with more then one phy
+ */
+ }
+
+ phydev->sysfs_links = true;
+}
+
+static ssize_t
+phy_standalone_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ return sprintf(buf, "%d\n", !phydev->attached_dev);
+}
+static DEVICE_ATTR_RO(phy_standalone);
+
+/**
+ * phy_sfp_attach - attach the SFP bus to the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .attach member.
+ */
+void phy_sfp_attach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = bus;
+ phydev->sfp_bus_attached = true;
+}
+EXPORT_SYMBOL(phy_sfp_attach);
+
+/**
+ * phy_sfp_detach - detach the SFP bus from the PHY upstream network device
+ * @upstream: pointer to the phy device
+ * @bus: sfp bus representing cage being attached
+ *
+ * This is used to fill in the sfp_upstream_ops .detach member.
+ */
+void phy_sfp_detach(void *upstream, struct sfp_bus *bus)
+{
+ struct phy_device *phydev = upstream;
+
+ if (phydev->attached_dev)
+ phydev->attached_dev->sfp_bus = NULL;
+ phydev->sfp_bus_attached = false;
+}
+EXPORT_SYMBOL(phy_sfp_detach);
+
+/**
+ * phy_sfp_probe - probe for a SFP cage attached to this PHY device
+ * @phydev: Pointer to phy_device
+ * @ops: SFP's upstream operations
+ */
+int phy_sfp_probe(struct phy_device *phydev,
+ const struct sfp_upstream_ops *ops)
+{
+ struct sfp_bus *bus;
+ int ret = 0;
+
+ if (phydev->mdio.dev.fwnode) {
+ bus = sfp_bus_find_fwnode(phydev->mdio.dev.fwnode);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ phydev->sfp_bus = bus;
+
+ ret = sfp_bus_add_upstream(bus, phydev, ops);
+ sfp_bus_put(bus);
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_sfp_probe);
+
+/**
+ * phy_attach_direct - attach a network device to a given PHY device pointer
+ * @dev: network device to attach
+ * @phydev: Pointer to phy_device to attach
+ * @flags: PHY device's dev_flags
+ * @interface: PHY device's interface
+ *
+ * Description: Called by drivers to attach to a particular PHY
+ * device. The phy_device is found, and properly hooked up
+ * to the phy_driver. If no driver is attached, then a
+ * generic driver is used. The phy_device is given a ptr to
+ * the attaching device, and given a callback for link status
+ * change. The phy_device is returned to the attaching driver.
+ * This function takes a reference on the phy device.
+ */
+int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
+ u32 flags, phy_interface_t interface)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct device *d = &phydev->mdio.dev;
+ struct module *ndev_owner = NULL;
+ bool using_genphy = false;
+ int err;
+
+ /* For Ethernet device drivers that register their own MDIO bus, we
+ * will have bus->owner match ndev_mod, so we do not want to increment
+ * our own module->refcnt here, otherwise we would not be able to
+ * unload later on.
+ */
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner && !try_module_get(bus->owner)) {
+ phydev_err(phydev, "failed to get the bus module\n");
+ return -EIO;
+ }
+
+ get_device(d);
+
+ /* Assume that if there is no driver, that it doesn't
+ * exist, and we should use the genphy driver.
+ */
+ if (!d->driver) {
+ if (phydev->is_c45)
+ d->driver = &genphy_c45_driver.mdiodrv.driver;
+ else
+ d->driver = &genphy_driver.mdiodrv.driver;
+
+ using_genphy = true;
+ }
+
+ if (!try_module_get(d->driver->owner)) {
+ phydev_err(phydev, "failed to get the device driver module\n");
+ err = -EIO;
+ goto error_put_device;
+ }
+
+ if (using_genphy) {
+ err = d->driver->probe(d);
+ if (err >= 0)
+ err = device_bind_driver(d);
+
+ if (err)
+ goto error_module_put;
+ }
+
+ if (phydev->attached_dev) {
+ dev_err(&dev->dev, "PHY already attached\n");
+ err = -EBUSY;
+ goto error;
+ }
+
+ phydev->phy_link_change = phy_link_change;
+ if (dev) {
+ phydev->attached_dev = dev;
+ dev->phydev = phydev;
+
+ if (phydev->sfp_bus_attached)
+ dev->sfp_bus = phydev->sfp_bus;
+ }
+
+ /* Some Ethernet drivers try to connect to a PHY device before
+ * calling register_netdevice() -> netdev_register_kobject() and
+ * does the dev->dev.kobj initialization. Here we only check for
+ * success which indicates that the network device kobject is
+ * ready. Once we do that we still need to keep track of whether
+ * links were successfully set up or not for phy_detach() to
+ * remove them accordingly.
+ */
+ phydev->sysfs_links = false;
+
+ phy_sysfs_create_links(phydev);
+
+ if (!phydev->attached_dev) {
+ err = sysfs_create_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+ if (err)
+ phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n");
+ }
+
+ phydev->dev_flags |= flags;
+
+ phydev->interface = interface;
+
+ phydev->state = PHY_READY;
+
+ /* Port is set to PORT_TP by default and the actual PHY driver will set
+ * it to different value depending on the PHY configuration. If we have
+ * the generic PHY driver we can't figure it out, thus set the old
+ * legacy PORT_MII value.
+ */
+ if (using_genphy)
+ phydev->port = PORT_MII;
+
+ /* Initial carrier state is off as the phy is about to be
+ * (re)initialized.
+ */
+ if (dev)
+ netif_carrier_off(phydev->attached_dev);
+
+ /* Do initial configuration here, now that
+ * we have certain key parameters
+ * (dev_flags and interface)
+ */
+ err = phy_init_hw(phydev);
+ if (err)
+ goto error;
+
+ err = phy_disable_interrupts(phydev);
+ if (err)
+ return err;
+
+ phy_resume(phydev);
+ phy_led_triggers_register(phydev);
+
+ return err;
+
+error:
+ /* phy_detach() does all of the cleanup below */
+ phy_detach(phydev);
+ return err;
+
+error_module_put:
+ module_put(d->driver->owner);
+error_put_device:
+ put_device(d);
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+ return err;
+}
+EXPORT_SYMBOL(phy_attach_direct);
+
+/**
+ * phy_attach - attach a network device to a particular PHY device
+ * @dev: network device to attach
+ * @bus_id: Bus ID of PHY device to attach
+ * @interface: PHY device's interface
+ *
+ * Description: Same as phy_attach_direct() except that a PHY bus_id
+ * string is passed instead of a pointer to a struct phy_device.
+ */
+struct phy_device *phy_attach(struct net_device *dev, const char *bus_id,
+ phy_interface_t interface)
+{
+ struct bus_type *bus = &mdio_bus_type;
+ struct phy_device *phydev;
+ struct device *d;
+ int rc;
+
+ if (!dev)
+ return ERR_PTR(-EINVAL);
+
+ /* Search the list of PHY devices on the mdio bus for the
+ * PHY with the requested name
+ */
+ d = bus_find_device_by_name(bus, NULL, bus_id);
+ if (!d) {
+ pr_err("PHY %s not found\n", bus_id);
+ return ERR_PTR(-ENODEV);
+ }
+ phydev = to_phy_device(d);
+
+ rc = phy_attach_direct(dev, phydev, phydev->dev_flags, interface);
+ put_device(d);
+ if (rc)
+ return ERR_PTR(rc);
+
+ return phydev;
+}
+EXPORT_SYMBOL(phy_attach);
+
+static bool phy_driver_is_genphy_kind(struct phy_device *phydev,
+ struct device_driver *driver)
+{
+ struct device *d = &phydev->mdio.dev;
+ bool ret = false;
+
+ if (!phydev->drv)
+ return ret;
+
+ get_device(d);
+ ret = d->driver == driver;
+ put_device(d);
+
+ return ret;
+}
+
+bool phy_driver_is_genphy(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
+
+bool phy_driver_is_genphy_10g(struct phy_device *phydev)
+{
+ return phy_driver_is_genphy_kind(phydev,
+ &genphy_c45_driver.mdiodrv.driver);
+}
+EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
+
+/**
+ * phy_package_join - join a common PHY group
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * This joins a PHY group and provides a shared storage for all phydevs in
+ * this group. This is intended to be used for packages which contain
+ * more than one PHY, for example a quad PHY transceiver.
+ *
+ * The addr parameter serves as a cookie which has to have the same value
+ * for all members of one group and as a PHY address to access generic
+ * registers of a PHY package. Usually, one of the PHY addresses of the
+ * different PHYs in the package provides access to these global registers.
+ * The address which is given here, will be used in the phy_package_read()
+ * and phy_package_write() convenience functions. If your PHY doesn't have
+ * global registers you can just pick any of the PHY addresses.
+ *
+ * This will set the shared pointer of the phydev to the shared storage.
+ * If this is the first call for a this cookie the shared storage will be
+ * allocated. If priv_size is non-zero, the given amount of bytes are
+ * allocated for the priv member.
+ *
+ * Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
+ * with the same cookie but a different priv_size is an error.
+ */
+int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)
+{
+ struct mii_bus *bus = phydev->mdio.bus;
+ struct phy_package_shared *shared;
+ int ret;
+
+ if (addr < 0 || addr >= PHY_MAX_ADDR)
+ return -EINVAL;
+
+ mutex_lock(&bus->shared_lock);
+ shared = bus->shared[addr];
+ if (!shared) {
+ ret = -ENOMEM;
+ shared = kzalloc(sizeof(*shared), GFP_KERNEL);
+ if (!shared)
+ goto err_unlock;
+ if (priv_size) {
+ shared->priv = kzalloc(priv_size, GFP_KERNEL);
+ if (!shared->priv)
+ goto err_free;
+ shared->priv_size = priv_size;
+ }
+ shared->addr = addr;
+ refcount_set(&shared->refcnt, 1);
+ bus->shared[addr] = shared;
+ } else {
+ ret = -EINVAL;
+ if (priv_size && priv_size != shared->priv_size)
+ goto err_unlock;
+ refcount_inc(&shared->refcnt);
+ }
+ mutex_unlock(&bus->shared_lock);
+
+ phydev->shared = shared;
+
+ return 0;
+
+err_free:
+ kfree(shared);
+err_unlock:
+ mutex_unlock(&bus->shared_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(phy_package_join);
+
+/**
+ * phy_package_leave - leave a common PHY group
+ * @phydev: target phy_device struct
+ *
+ * This leaves a PHY group created by phy_package_join(). If this phydev
+ * was the last user of the shared data between the group, this data is
+ * freed. Resets the phydev->shared pointer to NULL.
+ */
+void phy_package_leave(struct phy_device *phydev)
+{
+ struct phy_package_shared *shared = phydev->shared;
+ struct mii_bus *bus = phydev->mdio.bus;
+
+ if (!shared)
+ return;
+
+ if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+ bus->shared[shared->addr] = NULL;
+ mutex_unlock(&bus->shared_lock);
+ kfree(shared->priv);
+ kfree(shared);
+ }
+
+ phydev->shared = NULL;
+}
+EXPORT_SYMBOL_GPL(phy_package_leave);
+
+static void devm_phy_package_leave(struct device *dev, void *res)
+{
+ phy_package_leave(*(struct phy_device **)res);
+}
+
+/**
+ * devm_phy_package_join - resource managed phy_package_join()
+ * @dev: device that is registering this PHY package
+ * @phydev: target phy_device struct
+ * @addr: cookie and PHY address for global register access
+ * @priv_size: if non-zero allocate this amount of bytes for private data
+ *
+ * Managed phy_package_join(). Shared storage fetched by this function,
+ * phy_package_leave() is automatically called on driver detach. See
+ * phy_package_join() for more information.
+ */
+int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+ int addr, size_t priv_size)
+{
+ struct phy_device **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_phy_package_leave, sizeof(*ptr),
+ GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = phy_package_join(phydev, addr, priv_size);
+
+ if (!ret) {
+ *ptr = phydev;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_phy_package_join);
+
+/**
+ * phy_detach - detach a PHY device from its network device
+ * @phydev: target phy_device struct
+ *
+ * This detaches the phy device from its network device and the phy
+ * driver, and drops the reference count taken in phy_attach_direct().
+ */
+void phy_detach(struct phy_device *phydev)
+{
+ struct net_device *dev = phydev->attached_dev;
+ struct module *ndev_owner = NULL;
+ struct mii_bus *bus;
+
+ if (phydev->sysfs_links) {
+ if (dev)
+ sysfs_remove_link(&dev->dev.kobj, "phydev");
+ sysfs_remove_link(&phydev->mdio.dev.kobj, "attached_dev");
+ }
+
+ if (!phydev->attached_dev)
+ sysfs_remove_file(&phydev->mdio.dev.kobj,
+ &dev_attr_phy_standalone.attr);
+
+ phy_suspend(phydev);
+ if (dev) {
+ phydev->attached_dev->phydev = NULL;
+ phydev->attached_dev = NULL;
+ }
+ phydev->phylink = NULL;
+
+ phy_led_triggers_unregister(phydev);
+
+ if (phydev->mdio.dev.driver)
+ module_put(phydev->mdio.dev.driver->owner);
+
+ /* If the device had no specific driver before (i.e. - it
+ * was using the generic driver), we unbind the device
+ * from the generic driver so that there's a chance a
+ * real driver could be loaded
+ */
+ if (phy_driver_is_genphy(phydev) ||
+ phy_driver_is_genphy_10g(phydev))
+ device_release_driver(&phydev->mdio.dev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ /*
+ * The phydev might go away on the put_device() below, so avoid
+ * a use-after-free bug by reading the underlying bus first.
+ */
+ bus = phydev->mdio.bus;
+
+ put_device(&phydev->mdio.dev);
+ if (dev)
+ ndev_owner = dev->dev.parent->driver->owner;
+ if (ndev_owner != bus->owner)
+ module_put(bus->owner);
+}
+EXPORT_SYMBOL(phy_detach);
+
+int phy_suspend(struct phy_device *phydev)
+{
+ struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
+ struct net_device *netdev = phydev->attached_dev;
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ if (phydev->suspended)
+ return 0;
+
+ /* If the device has WOL enabled, we cannot suspend the PHY */
+ phy_ethtool_get_wol(phydev, &wol);
+ if (wol.wolopts || (netdev && netdev->wol_enabled))
+ return -EBUSY;
+
+ if (!phydrv || !phydrv->suspend)
+ return 0;
+
+ ret = phydrv->suspend(phydev);
+ if (!ret)
+ phydev->suspended = true;
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_suspend);
+
+int __phy_resume(struct phy_device *phydev)
+{
+ struct phy_driver *phydrv = phydev->drv;
+ int ret;
+
+ WARN_ON(!mutex_is_locked(&phydev->lock));
+
+ if (!phydrv || !phydrv->resume)
+ return 0;
+
+ ret = phydrv->resume(phydev);
+ if (!ret)
+ phydev->suspended = false;
+
+ return ret;
+}
+EXPORT_SYMBOL(__phy_resume);
+
+int phy_resume(struct phy_device *phydev)
+{
+ int ret;
+
+ mutex_lock(&phydev->lock);
+ ret = __phy_resume(phydev);
+ mutex_unlock(&phydev->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(phy_resume);
+
+int phy_loopback(struct phy_device *phydev, bool enable)
+{
+ struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver);
+ int ret = 0;
+
+ mutex_lock(&phydev->lock);
+
+ if (enable && phydev->loopback_enabled) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ if (!enable && !phydev->loopback_enabled) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (phydev->drv && phydrv->set_loopback)
+ ret = phydrv->set_loopback(phydev, enable);
+ else
+ ret = -EOPNOTSUPP;
+
+ if (ret)
+ goto out;
+
+ phydev->loopback_enabled = enable;
+
+out:
+ mutex_unlock(&phydev->lock);
+ return ret;
+}
+EXPORT_SYMBOL(phy_loopback);
+
+/**
+ * phy_reset_after_clk_enable - perform a PHY reset if needed
+ * @phydev: target phy_device struct
+ *
+ * Description: Some PHYs are known to need a reset after their refclk was
+ * enabled. This function evaluates the flags and perform the reset if it's
+ * needed. Returns < 0 on error, 0 if the phy wasn't reset and 1 if the phy
+ * was reset.
+ */
+int phy_reset_after_clk_enable(struct phy_device *phydev)
+{
+ if (!phydev || !phydev->drv)
+ return -ENODEV;
+
+ if (phydev->drv->flags & PHY_RST_AFTER_CLK_EN) {
+ phy_device_reset(phydev, 1);
+ phy_device_reset(phydev, 0);
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_reset_after_clk_enable);
+
+/* Generic PHY support and helper functions */
+
+/**
+ * genphy_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed.
+ */
+static int genphy_config_advert(struct phy_device *phydev)
+{
+ int err, bmsr, changed = 0;
+ u32 adv;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
+
+ /* Setup standard advertisement */
+ err = phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_100BASE4 |
+ ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ bmsr = phy_read(phydev, MII_BMSR);
+ if (bmsr < 0)
+ return bmsr;
+
+ /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
+ * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
+ * logical 1.
+ */
+ if (!(bmsr & BMSR_ESTATEN))
+ return changed;
+
+ adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+
+ err = phy_modify_changed(phydev, MII_CTRL1000,
+ ADVERTISE_1000FULL | ADVERTISE_1000HALF,
+ adv);
+ if (err < 0)
+ return err;
+ if (err > 0)
+ changed = 1;
+
+ return changed;
+}
+
+/**
+ * genphy_c37_config_advert - sanitize and advertise auto-negotiation parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed. This function is intended
+ * for Clause 37 1000Base-X mode.
+ */
+static int genphy_c37_config_advert(struct phy_device *phydev)
+{
+ u16 adv = 0;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+ phydev->supported);
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XFULL;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPAUSE;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPSE_ASYM;
+
+ return phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
+ ADVERTISE_1000XHALF | ADVERTISE_1000XPSE_ASYM,
+ adv);
+}
+
+/**
+ * genphy_config_eee_advert - disable unwanted eee mode advertisement
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MDIO_AN_EEE_ADV after disabling unsupported energy
+ * efficent ethernet modes. Returns 0 if the PHY's advertisement hasn't
+ * changed, and 1 if it has changed.
+ */
+int genphy_config_eee_advert(struct phy_device *phydev)
+{
+ int err;
+
+ /* Nothing to disable */
+ if (!phydev->eee_broken_modes)
+ return 0;
+
+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ phydev->eee_broken_modes, 0);
+ /* If the call failed, we assume that EEE is not supported */
+ return err < 0 ? 0 : err;
+}
+EXPORT_SYMBOL(genphy_config_eee_advert);
+
+/**
+ * genphy_setup_forced - configures/forces speed/duplex from @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Configures MII_BMCR to force speed/duplex
+ * to the values in phydev. Assumes that the values are valid.
+ * Please see phy_sanitize_settings().
+ */
+int genphy_setup_forced(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (SPEED_1000 == phydev->speed)
+ ctl |= BMCR_SPEED1000;
+ else if (SPEED_100 == phydev->speed)
+ ctl |= BMCR_SPEED100;
+
+ if (DUPLEX_FULL == phydev->duplex)
+ ctl |= BMCR_FULLDPLX;
+
+ return phy_modify(phydev, MII_BMCR,
+ ~(BMCR_LOOPBACK | BMCR_ISOLATE | BMCR_PDOWN), ctl);
+}
+EXPORT_SYMBOL(genphy_setup_forced);
+
+static int genphy_setup_master_slave(struct phy_device *phydev)
+{
+ u16 ctl = 0;
+
+ if (!phydev->is_gigabit_capable)
+ return 0;
+
+ switch (phydev->master_slave_set) {
+ case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+ ctl |= CTL1000_PREFER_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+ break;
+ case MASTER_SLAVE_CFG_MASTER_FORCE:
+ ctl |= CTL1000_AS_MASTER;
+ fallthrough;
+ case MASTER_SLAVE_CFG_SLAVE_FORCE:
+ ctl |= CTL1000_ENABLE_MASTER;
+ break;
+ case MASTER_SLAVE_CFG_UNKNOWN:
+ case MASTER_SLAVE_CFG_UNSUPPORTED:
+ return 0;
+ default:
+ phydev_warn(phydev, "Unsupported Master/Slave mode\n");
+ return -EOPNOTSUPP;
+ }
+
+ return phy_modify_changed(phydev, MII_CTRL1000,
+ (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER |
+ CTL1000_PREFER_MASTER), ctl);
+}
+
+static int genphy_read_master_slave(struct phy_device *phydev)
+{
+ int cfg, state;
+ int val;
+
+ if (!phydev->is_gigabit_capable) {
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
+ return 0;
+ }
+
+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
+
+ val = phy_read(phydev, MII_CTRL1000);
+ if (val < 0)
+ return val;
+
+ if (val & CTL1000_ENABLE_MASTER) {
+ if (val & CTL1000_AS_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_FORCE;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_FORCE;
+ } else {
+ if (val & CTL1000_PREFER_MASTER)
+ cfg = MASTER_SLAVE_CFG_MASTER_PREFERRED;
+ else
+ cfg = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
+ }
+
+ val = phy_read(phydev, MII_STAT1000);
+ if (val < 0)
+ return val;
+
+ if (val & LPA_1000MSFAIL) {
+ state = MASTER_SLAVE_STATE_ERR;
+ } else if (phydev->link) {
+ /* this bits are valid only for active link */
+ if (val & LPA_1000MSRES)
+ state = MASTER_SLAVE_STATE_MASTER;
+ else
+ state = MASTER_SLAVE_STATE_SLAVE;
+ } else {
+ state = MASTER_SLAVE_STATE_UNKNOWN;
+ }
+
+ phydev->master_slave_get = cfg;
+ phydev->master_slave_state = state;
+
+ return 0;
+}
+
+/**
+ * genphy_restart_aneg - Enable and Restart Autonegotiation
+ * @phydev: target phy_device struct
+ */
+int genphy_restart_aneg(struct phy_device *phydev)
+{
+ /* Don't isolate the PHY if we're negotiating */
+ return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+}
+EXPORT_SYMBOL(genphy_restart_aneg);
+
+/**
+ * genphy_check_and_restart_aneg - Enable and restart auto-negotiation
+ * @phydev: target phy_device struct
+ * @restart: whether aneg restart is requested
+ *
+ * Check, and restart auto-negotiation if needed.
+ */
+int genphy_check_and_restart_aneg(struct phy_device *phydev, bool restart)
+{
+ int ret;
+
+ if (!restart) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+
+ if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE))
+ restart = true;
+ }
+
+ if (restart)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_check_and_restart_aneg);
+
+/**
+ * __genphy_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ * @changed: whether autoneg is requested
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR.
+ */
+int __genphy_config_aneg(struct phy_device *phydev, bool changed)
+{
+ int err;
+
+ if (genphy_config_eee_advert(phydev))
+ changed = true;
+
+ err = genphy_setup_master_slave(phydev);
+ if (err < 0)
+ return err;
+ else if (err)
+ changed = true;
+
+ if (AUTONEG_ENABLE != phydev->autoneg)
+ return genphy_setup_forced(phydev);
+
+ err = genphy_config_advert(phydev);
+ if (err < 0) /* error */
+ return err;
+ else if (err)
+ changed = true;
+
+ return genphy_check_and_restart_aneg(phydev, changed);
+}
+EXPORT_SYMBOL(__genphy_config_aneg);
+
+/**
+ * genphy_c37_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR. This function is intended
+ * for use with Clause 37 1000Base-X mode.
+ */
+int genphy_c37_config_aneg(struct phy_device *phydev)
+{
+ int err, changed;
+
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return genphy_setup_forced(phydev);
+
+ err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
+ BMCR_SPEED1000);
+ if (err)
+ return err;
+
+ changed = genphy_c37_config_advert(phydev);
+ if (changed < 0) /* error */
+ return changed;
+
+ if (!changed) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+ * begin with? Or maybe phy was isolated?
+ */
+ int ctl = phy_read(phydev, MII_BMCR);
+
+ if (ctl < 0)
+ return ctl;
+
+ if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
+ changed = 1; /* do restart aneg */
+ }
+
+ /* Only restart aneg if we are advertising something different
+ * than we were before.
+ */
+ if (changed > 0)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_config_aneg);
+
+/**
+ * genphy_aneg_done - return auto-negotiation status
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the status register and returns 0 either if
+ * auto-negotiation is incomplete, or if there was an error.
+ * Returns BMSR_ANEGCOMPLETE if auto-negotiation is done.
+ */
+int genphy_aneg_done(struct phy_device *phydev)
+{
+ int retval = phy_read(phydev, MII_BMSR);
+
+ return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
+}
+EXPORT_SYMBOL(genphy_aneg_done);
+
+/**
+ * genphy_update_link - update link status in @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Update the value in phydev->link to reflect the
+ * current link value. In order to do this, we need to read
+ * the status register twice, keeping the second value.
+ */
+int genphy_update_link(struct phy_device *phydev)
+{
+ int status = 0, bmcr;
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ bmcr = phy_read(phydev, MII_BMCR);
+#endif
+ if (bmcr < 0)
+ return bmcr;
+
+ /* Autoneg is being started, therefore disregard BMSR value and
+ * report link as down.
+ */
+ if (bmcr & BMCR_ANRESTART)
+ goto done;
+
+ /* The link state is latched low so that momentary link
+ * drops can be detected. Do not double-read the status
+ * in polling mode to detect such short link drops except
+ * the link was already down.
+ */
+ if (!phy_polling_mode(phydev) || !phydev->link) {
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+ else if (status & BMSR_LSTATUS)
+ goto done;
+ }
+
+ /* Read link and autonegotiation status */
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ status = phy_read_cl(phydev, MII_BMSR);
+#else
+ status = phy_read(phydev, MII_BMSR);
+#endif
+ if (status < 0)
+ return status;
+done:
+ phydev->link = status & BMSR_LSTATUS ? 1 : 0;
+ phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0;
+
+ /* Consider the case that autoneg was started and "aneg complete"
+ * bit has been reset, but "link up" bit not yet.
+ */
+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete)
+ phydev->link = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_update_link);
+
+int genphy_read_lpa(struct phy_device *phydev)
+{
+ int lpa, lpagb;
+
+ if (phydev->autoneg == AUTONEG_ENABLE) {
+ if (!phydev->autoneg_complete) {
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ 0);
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
+ return 0;
+ }
+
+ if (phydev->is_gigabit_capable) {
+ lpagb = phy_read(phydev, MII_STAT1000);
+ if (lpagb < 0)
+ return lpagb;
+
+ if (lpagb & LPA_1000MSFAIL) {
+ int adv = phy_read(phydev, MII_CTRL1000);
+
+ if (adv < 0)
+ return adv;
+
+ if (adv & CTL1000_ENABLE_MASTER)
+ phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n");
+ else
+ phydev_err(phydev, "Master/Slave resolution failed\n");
+ return -ENOLINK;
+ }
+
+ mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising,
+ lpagb);
+ }
+
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
+ } else {
+ linkmode_zero(phydev->lp_advertising);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_lpa);
+
+/**
+ * genphy_read_status_fixed - read the link parameters for !aneg mode
+ * @phydev: target phy_device struct
+ *
+ * Read the current duplex and speed state for a PHY operating with
+ * autonegotiation disabled.
+ */
+int genphy_read_status_fixed(struct phy_device *phydev)
+{
+#ifdef CONFIG_MARVELL_88Q1110 //zw.wang phy driver support for Marvell_88q1110 on 20240417
+ int bmcr = phy_read_cl(phydev, MII_BMCR);
+#else
+ int bmcr = phy_read(phydev, MII_BMCR);
+#endif
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+
+ if (bmcr & BMCR_SPEED1000)
+ phydev->speed = SPEED_1000;
+ else if (bmcr & BMCR_SPEED100)
+ phydev->speed = SPEED_100;
+ else
+ phydev->speed = SPEED_10;
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status_fixed);
+
+/**
+ * genphy_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. Start by checking the gigabit possibilities,
+ * then move on to 10/100.
+ */
+int genphy_read_status(struct phy_device *phydev)
+{
+ int err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->speed = SPEED_UNKNOWN;
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ err = genphy_read_master_slave(phydev);
+ if (err < 0)
+ return err;
+
+ err = genphy_read_lpa(phydev);
+ if (err < 0)
+ return err;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ err = genphy_read_status_fixed(phydev);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_status);
+
+/**
+ * genphy_c37_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. This function is for Clause 37 1000Base-X mode.
+ */
+int genphy_c37_read_status(struct phy_device *phydev)
+{
+ int lpa, err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->duplex = DUPLEX_UNKNOWN;
+ phydev->pause = 0;
+ phydev->asym_pause = 0;
+
+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
+ lpa = phy_read(phydev, MII_LPA);
+ if (lpa < 0)
+ return lpa;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->lp_advertising, lpa & LPA_LPACK);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->lp_advertising, lpa & LPA_1000XPAUSE);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->lp_advertising,
+ lpa & LPA_1000XPAUSE_ASYM);
+
+ phy_resolve_aneg_linkmode(phydev);
+ } else if (phydev->autoneg == AUTONEG_DISABLE) {
+ int bmcr = phy_read(phydev, MII_BMCR);
+
+ if (bmcr < 0)
+ return bmcr;
+
+ if (bmcr & BMCR_FULLDPLX)
+ phydev->duplex = DUPLEX_FULL;
+ else
+ phydev->duplex = DUPLEX_HALF;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_read_status);
+
+/**
+ * genphy_soft_reset - software reset the PHY via BMCR_RESET bit
+ * @phydev: target phy_device struct
+ *
+ * Description: Perform a software PHY reset using the standard
+ * BMCR_RESET bit and poll for the reset bit to be cleared.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_soft_reset(struct phy_device *phydev)
+{
+ u16 res = BMCR_RESET;
+ int ret;
+
+ if (phydev->autoneg == AUTONEG_ENABLE)
+ res |= BMCR_ANRESTART;
+
+ ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res);
+ if (ret < 0)
+ return ret;
+
+ /* Clause 22 states that setting bit BMCR_RESET sets control registers
+ * to their default value. Therefore the POWER DOWN bit is supposed to
+ * be cleared after soft reset.
+ */
+ phydev->suspended = 0;
+
+ ret = phy_poll_reset(phydev);
+ if (ret)
+ return ret;
+
+ /* BMCR may be reset to defaults */
+ if (phydev->autoneg == AUTONEG_DISABLE)
+ ret = genphy_setup_forced(phydev);
+
+ return ret;
+}
+EXPORT_SYMBOL(genphy_soft_reset);
+
+/**
+ * genphy_read_abilities - read PHY abilities from Clause 22 registers
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the PHY's abilities and populates
+ * phydev->supported accordingly.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_read_abilities(struct phy_device *phydev)
+{
+ int val;
+
+ linkmode_set_bit_array(phy_basic_ports_array,
+ ARRAY_SIZE(phy_basic_ports_array),
+ phydev->supported);
+
+ val = phy_read(phydev, MII_BMSR);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported,
+ val & BMSR_ANEGCAPABLE);
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported,
+ val & BMSR_100FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported,
+ val & BMSR_100HALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported,
+ val & BMSR_10FULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported,
+ val & BMSR_10HALF);
+
+ if (val & BMSR_ESTATEN) {
+ val = phy_read(phydev, MII_ESTATUS);
+ if (val < 0)
+ return val;
+
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_TFULL);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported, val & ESTATUS_1000_THALF);
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->supported, val & ESTATUS_1000_XFULL);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_read_abilities);
+
+/* This is used for the phy device which doesn't support the MMD extended
+ * register access, but it does have side effect when we are trying to access
+ * the MMD register via indirect method.
+ */
+int genphy_read_mmd_unsupported(struct phy_device *phdev, int devad, u16 regnum)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_read_mmd_unsupported);
+
+int genphy_write_mmd_unsupported(struct phy_device *phdev, int devnum,
+ u16 regnum, u16 val)
+{
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(genphy_write_mmd_unsupported);
+
+int genphy_suspend(struct phy_device *phydev)
+{
+ return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_suspend);
+
+int genphy_resume(struct phy_device *phydev)
+{
+ return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
+}
+EXPORT_SYMBOL(genphy_resume);
+
+int genphy_loopback(struct phy_device *phydev, bool enable)
+{
+ return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
+ enable ? BMCR_LOOPBACK : 0);
+}
+EXPORT_SYMBOL(genphy_loopback);
+
+/**
+ * phy_remove_link_mode - Remove a supported link mode
+ * @phydev: phy_device structure to remove link mode from
+ * @link_mode: Link mode to be removed
+ *
+ * Description: Some MACs don't support all link modes which the PHY
+ * does. e.g. a 1G MAC often does not support 1000Half. Add a helper
+ * to remove a link mode.
+ */
+void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode)
+{
+ linkmode_clear_bit(link_mode, phydev->supported);
+ phy_advertise_supported(phydev);
+}
+EXPORT_SYMBOL(phy_remove_link_mode);
+
+static void phy_copy_pause_bits(unsigned long *dst, unsigned long *src)
+{
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, src));
+ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, dst,
+ linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, src));
+}
+
+/**
+ * phy_advertise_supported - Advertise all supported modes
+ * @phydev: target phy_device struct
+ *
+ * Description: Called to advertise all supported modes, doesn't touch
+ * pause mode advertising.
+ */
+void phy_advertise_supported(struct phy_device *phydev)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(new);
+
+ linkmode_copy(new, phydev->supported);
+ phy_copy_pause_bits(new, phydev->advertising);
+ linkmode_copy(phydev->advertising, new);
+}
+EXPORT_SYMBOL(phy_advertise_supported);
+
+/**
+ * phy_support_sym_pause - Enable support of symmetrical pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports symmetrical
+ * Pause, but not asym pause.
+ */
+void phy_support_sym_pause(struct phy_device *phydev)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_sym_pause);
+
+/**
+ * phy_support_asym_pause - Enable support of asym pause
+ * @phydev: target phy_device struct
+ *
+ * Description: Called by the MAC to indicate is supports Asym Pause.
+ */
+void phy_support_asym_pause(struct phy_device *phydev)
+{
+ phy_copy_pause_bits(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_support_asym_pause);
+
+/**
+ * phy_set_sym_pause - Configure symmetric Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ * @autoneg: Auto neg should be used
+ *
+ * Description: Configure advertised Pause support depending on if
+ * receiver pause and pause auto neg is supported. Generally called
+ * from the set_pauseparam .ndo.
+ */
+void phy_set_sym_pause(struct phy_device *phydev, bool rx, bool tx,
+ bool autoneg)
+{
+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
+
+ if (rx && tx && autoneg)
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+
+ linkmode_copy(phydev->advertising, phydev->supported);
+}
+EXPORT_SYMBOL(phy_set_sym_pause);
+
+/**
+ * phy_set_asym_pause - Configure Pause and Asym Pause
+ * @phydev: target phy_device struct
+ * @rx: Receiver Pause is supported
+ * @tx: Transmit Pause is supported
+ *
+ * Description: Configure advertised Pause support depending on if
+ * transmit and receiver pause is supported. If there has been a
+ * change in adverting, trigger a new autoneg. Generally called from
+ * the set_pauseparam .ndo.
+ */
+void phy_set_asym_pause(struct phy_device *phydev, bool rx, bool tx)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(oldadv);
+
+ linkmode_copy(oldadv, phydev->advertising);
+ linkmode_set_pause(phydev->advertising, tx, rx);
+
+ if (!linkmode_equal(oldadv, phydev->advertising) &&
+ phydev->autoneg)
+ phy_start_aneg(phydev);
+}
+EXPORT_SYMBOL(phy_set_asym_pause);
+
+/**
+ * phy_validate_pause - Test if the PHY/MAC support the pause configuration
+ * @phydev: phy_device struct
+ * @pp: requested pause configuration
+ *
+ * Description: Test if the PHY/MAC combination supports the Pause
+ * configuration the user is requesting. Returns True if it is
+ * supported, false otherwise.
+ */
+bool phy_validate_pause(struct phy_device *phydev,
+ struct ethtool_pauseparam *pp)
+{
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported) && pp->rx_pause)
+ return false;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported) &&
+ pp->rx_pause != pp->tx_pause)
+ return false;
+
+ return true;
+}
+EXPORT_SYMBOL(phy_validate_pause);
+
+/**
+ * phy_get_pause - resolve negotiated pause modes
+ * @phydev: phy_device struct
+ * @tx_pause: pointer to bool to indicate whether transmit pause should be
+ * enabled.
+ * @rx_pause: pointer to bool to indicate whether receive pause should be
+ * enabled.
+ *
+ * Resolve and return the flow control modes according to the negotiation
+ * result. This includes checking that we are operating in full duplex mode.
+ * See linkmode_resolve_pause() for further details.
+ */
+void phy_get_pause(struct phy_device *phydev, bool *tx_pause, bool *rx_pause)
+{
+ if (phydev->duplex != DUPLEX_FULL) {
+ *tx_pause = false;
+ *rx_pause = false;
+ return;
+ }
+
+ return linkmode_resolve_pause(phydev->advertising,
+ phydev->lp_advertising,
+ tx_pause, rx_pause);
+}
+EXPORT_SYMBOL(phy_get_pause);
+
+#if IS_ENABLED(CONFIG_OF_MDIO)
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ s32 int_delay;
+ int ret;
+
+ ret = device_property_read_u32(dev, name, &int_delay);
+ if (ret)
+ return ret;
+
+ return int_delay;
+}
+#else
+static int phy_get_int_delay_property(struct device *dev, const char *name)
+{
+ return -EINVAL;
+}
+#endif
+
+/**
+ * phy_get_delay_index - returns the index of the internal delay
+ * @phydev: phy_device struct
+ * @dev: pointer to the devices device struct
+ * @delay_values: array of delays the PHY supports
+ * @size: the size of the delay array
+ * @is_rx: boolean to indicate to get the rx internal delay
+ *
+ * Returns the index within the array of internal delay passed in.
+ * If the device property is not present then the interface type is checked
+ * if the interface defines use of internal delay then a 1 is returned otherwise
+ * a 0 is returned.
+ * The array must be in ascending order. If PHY does not have an ascending order
+ * array then size = 0 and the value of the delay property is returned.
+ * Return -EINVAL if the delay is invalid or cannot be found.
+ */
+s32 phy_get_internal_delay(struct phy_device *phydev, struct device *dev,
+ const int *delay_values, int size, bool is_rx)
+{
+ s32 delay;
+ int i;
+
+ if (is_rx) {
+ delay = phy_get_int_delay_property(dev, "rx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ return 1;
+ else
+ return 0;
+ }
+
+ } else {
+ delay = phy_get_int_delay_property(dev, "tx-internal-delay-ps");
+ if (delay < 0 && size == 0) {
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ return 1;
+ else
+ return 0;
+ }
+ }
+
+ if (delay < 0)
+ return delay;
+
+ if (delay && size == 0)
+ return delay;
+
+ if (delay < delay_values[0] || delay > delay_values[size - 1]) {
+ phydev_err(phydev, "Delay %d is out of range\n", delay);
+ return -EINVAL;
+ }
+
+ if (delay == delay_values[0])
+ return 0;
+
+ for (i = 1; i < size; i++) {
+ if (delay == delay_values[i])
+ return i;
+
+ /* Find an approximate index by looking up the table */
+ if (delay > delay_values[i - 1] &&
+ delay < delay_values[i]) {
+ if (delay - delay_values[i - 1] <
+ delay_values[i] - delay)
+ return i - 1;
+ else
+ return i;
+ }
+ }
+
+ phydev_err(phydev, "error finding internal delay index for %d\n",
+ delay);
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(phy_get_internal_delay);
+
+static bool phy_drv_supports_irq(struct phy_driver *phydrv)
+{
+ return phydrv->config_intr && phydrv->ack_interrupt;
+}
+
+/**
+ * phy_probe - probe and init a PHY device
+ * @dev: device to probe and init
+ *
+ * Description: Take care of setting up the phy_device structure,
+ * set the state to READY (the driver's init function should
+ * set it to STARTING if needed).
+ */
+static int phy_probe(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+ struct device_driver *drv = phydev->mdio.dev.driver;
+ struct phy_driver *phydrv = to_phy_driver(drv);
+ int err = 0;
+
+ phydev->drv = phydrv;
+
+ /* Disable the interrupt if the PHY doesn't support it
+ * but the interrupt is still a valid one
+ */
+ if (!phy_drv_supports_irq(phydrv) && phy_interrupt_is_valid(phydev))
+ phydev->irq = PHY_POLL;
+
+ if (phydrv->flags & PHY_IS_INTERNAL)
+ phydev->is_internal = true;
+
+ mutex_lock(&phydev->lock);
+
+ /* Deassert the reset signal */
+ phy_device_reset(phydev, 0);
+
+ if (phydev->drv->probe) {
+ err = phydev->drv->probe(phydev);
+ if (err)
+ goto out;
+ }
+
+ /* Start out supporting everything. Eventually,
+ * a controller will attach, and may modify one
+ * or both of these values
+ */
+ if (phydrv->features) {
+ linkmode_copy(phydev->supported, phydrv->features);
+ } else if (phydrv->get_features) {
+ err = phydrv->get_features(phydev);
+ } else if (phydev->is_c45) {
+ err = genphy_c45_pma_read_abilities(phydev);
+ } else {
+ err = genphy_read_abilities(phydev);
+ }
+
+ if (err)
+ goto out;
+
+ if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ phydev->supported))
+ phydev->autoneg = 0;
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+ phydev->supported))
+ phydev->is_gigabit_capable = 1;
+
+ of_set_phy_supported(phydev);
+ phy_advertise_supported(phydev);
+
+ /* Get the EEE modes we want to prohibit. We will ask
+ * the PHY stop advertising these mode later on
+ */
+ of_set_phy_eee_broken(phydev);
+
+ /* The Pause Frame bits indicate that the PHY can support passing
+ * pause frames. During autonegotiation, the PHYs will determine if
+ * they should allow pause frames to pass. The MAC driver should then
+ * use that result to determine whether to enable flow control via
+ * pause frames.
+ *
+ * Normally, PHY drivers should not set the Pause bits, and instead
+ * allow phylib to do that. However, there may be some situations
+ * (e.g. hardware erratum) where the driver wants to set only one
+ * of these bits.
+ */
+ if (!test_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported) &&
+ !test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported)) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->supported);
+ }
+
+ /* Set the state to READY by default */
+ phydev->state = PHY_READY;
+
+out:
+ /* Assert the reset signal */
+ if (err)
+ phy_device_reset(phydev, 1);
+
+ mutex_unlock(&phydev->lock);
+
+ return err;
+}
+
+static int phy_remove(struct device *dev)
+{
+ struct phy_device *phydev = to_phy_device(dev);
+
+ cancel_delayed_work_sync(&phydev->state_queue);
+
+ mutex_lock(&phydev->lock);
+ phydev->state = PHY_DOWN;
+ mutex_unlock(&phydev->lock);
+
+ sfp_bus_del_upstream(phydev->sfp_bus);
+ phydev->sfp_bus = NULL;
+
+ if (phydev->drv && phydev->drv->remove)
+ phydev->drv->remove(phydev);
+
+ /* Assert the reset signal */
+ phy_device_reset(phydev, 1);
+
+ phydev->drv = NULL;
+
+ return 0;
+}
+
+/**
+ * phy_driver_register - register a phy_driver with the PHY layer
+ * @new_driver: new phy_driver to register
+ * @owner: module owning this PHY
+ */
+int phy_driver_register(struct phy_driver *new_driver, struct module *owner)
+{
+ int retval;
+
+ /* Either the features are hard coded, or dynamically
+ * determined. It cannot be both.
+ */
+ if (WARN_ON(new_driver->features && new_driver->get_features)) {
+ pr_err("%s: features and get_features must not both be set\n",
+ new_driver->name);
+ return -EINVAL;
+ }
+
+ new_driver->mdiodrv.flags |= MDIO_DEVICE_IS_PHY;
+ new_driver->mdiodrv.driver.name = new_driver->name;
+ new_driver->mdiodrv.driver.bus = &mdio_bus_type;
+ new_driver->mdiodrv.driver.probe = phy_probe;
+ new_driver->mdiodrv.driver.remove = phy_remove;
+ new_driver->mdiodrv.driver.owner = owner;
+ new_driver->mdiodrv.driver.probe_type = PROBE_FORCE_SYNCHRONOUS;
+
+ retval = driver_register(&new_driver->mdiodrv.driver);
+ if (retval) {
+ pr_err("%s: Error %d in registering driver\n",
+ new_driver->name, retval);
+
+ return retval;
+ }
+
+ pr_debug("%s: Registered new driver\n", new_driver->name);
+
+ return 0;
+}
+EXPORT_SYMBOL(phy_driver_register);
+
+int phy_drivers_register(struct phy_driver *new_driver, int n,
+ struct module *owner)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < n; i++) {
+ ret = phy_driver_register(new_driver + i, owner);
+ if (ret) {
+ while (i-- > 0)
+ phy_driver_unregister(new_driver + i);
+ break;
+ }
+ }
+ return ret;
+}
+EXPORT_SYMBOL(phy_drivers_register);
+
+void phy_driver_unregister(struct phy_driver *drv)
+{
+ driver_unregister(&drv->mdiodrv.driver);
+}
+EXPORT_SYMBOL(phy_driver_unregister);
+
+void phy_drivers_unregister(struct phy_driver *drv, int n)
+{
+ int i;
+
+ for (i = 0; i < n; i++)
+ phy_driver_unregister(drv + i);
+}
+EXPORT_SYMBOL(phy_drivers_unregister);
+
+static struct phy_driver genphy_driver = {
+ .phy_id = 0xffffffff,
+ .phy_id_mask = 0xffffffff,
+ .name = "Generic PHY",
+ .get_features = genphy_read_abilities,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .set_loopback = genphy_loopback,
+};
+
+static const struct ethtool_phy_ops phy_ethtool_phy_ops = {
+ .get_sset_count = phy_ethtool_get_sset_count,
+ .get_strings = phy_ethtool_get_strings,
+ .get_stats = phy_ethtool_get_stats,
+ .start_cable_test = phy_start_cable_test,
+ .start_cable_test_tdr = phy_start_cable_test_tdr,
+};
+
+static int __init phy_init(void)
+{
+ int rc;
+
+ rc = mdio_bus_init();
+ if (rc)
+ return rc;
+
+ ethtool_set_ethtool_phy_ops(&phy_ethtool_phy_ops);
+ features_init();
+
+ rc = phy_driver_register(&genphy_c45_driver, THIS_MODULE);
+ if (rc)
+ goto err_c45;
+
+ rc = phy_driver_register(&genphy_driver, THIS_MODULE);
+ if (rc) {
+ phy_driver_unregister(&genphy_c45_driver);
+err_c45:
+ mdio_bus_exit();
+ }
+
+ return rc;
+}
+
+static void __exit phy_exit(void)
+{
+ phy_driver_unregister(&genphy_c45_driver);
+ phy_driver_unregister(&genphy_driver);
+ mdio_bus_exit();
+ ethtool_set_ethtool_phy_ops(NULL);
+}
+
+subsys_initcall(phy_init);
+module_exit(phy_exit);
diff --git a/upstream/linux-5.10/include/linux/mfd/zx234290.h b/upstream/linux-5.10/include/linux/mfd/zx234290.h
new file mode 100755
index 0000000..ea89815
--- /dev/null
+++ b/upstream/linux-5.10/include/linux/mfd/zx234290.h
@@ -0,0 +1,1130 @@
+/*
+ * zx234290.h -- ZTE ZX234290
+ *
+ * Copyright 2016 ZTE Corporation.
+ *
+ * Author: yuxiang
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_ZX234290_H
+#define __LINUX_MFD_ZX234290_H
+
+#include <linux/mutex.h>
+
+#define zx234290_rails(_name) "zx234290_"#_name
+
+#define u8 unsigned char
+
+/* LDOs */
+#define ZX234290_REG_LDO1 0
+#define ZX234290_REG_LDO2 1
+#define ZX234290_REG_LDO3 2
+#define ZX234290_REG_LDO4 3
+#define ZX234290_REG_LDO5 4
+#define ZX234290_REG_LDO6 5
+#define ZX234290_REG_LDO7 6
+#define ZX234290_REG_LDO8 7
+
+#define ZX234290_REG_LDO9 8
+#define ZX234290_REG_LDO10 9
+#define ZX234290_REG_LDO11 10
+
+/* DCDC's */
+#define ZX234290_REG_DCDC0 11
+#define ZX234290_REG_DCDC1 12
+#define ZX234290_REG_DCDC2 13
+#define ZX234290_REG_DCDC3 14
+#define ZX234290_REG_DCDC4 15
+
+/* ZX regulator type list */
+#ifndef ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_PWR_FAUL_PROCESS
+#define ZX234290_INT_LDO_FAUL 0
+#define ZX234290_INT_BUCK_FAUL 1
+#endif
+
+#define ZX234290_INT_EOADC 2 /* xxxx x100 */
+#define ZX234290_INT_PWRON_SHORT 3
+#define ZX234290_INT_PWRON_LONG 4
+#define ZX234290_INT_PWRON 5
+
+#define ZX234290_INT_RTC_ALRM 8
+#define ZX234290_INT_BATT_DET 10
+#define ZX234290_INT_RTC_MIN 11
+#define ZX234290_INT_RTC_HOUR 12
+
+#define ZX234290_NUM_IRQ 13
+
+#ifdef ZX234290_PWR_FAUL_PROCESS
+int zx234290_register_client(struct notifier_block *nb);
+int zx234290_unregister_client(struct notifier_block *nb);
+int zx234290_notifier_call_chain(unsigned long val, void *v);
+#endif
+
+#if 0
+/* External controls requests */
+enum zx234290_ext_control {
+ PWR_REQ_INPUT_NONE = 0x00000000,
+ PWR_REQ_INPUT_PREQ1 = 0x00000001,
+ PWR_REQ_INPUT_PREQ2 = 0x00000002,
+ PWR_REQ_INPUT_PREQ3 = 0x00000004,
+ PWR_OFF_ON_SLEEP = 0x00000008,
+ PWR_ON_ON_SLEEP = 0x00000010,
+};
+#endif
+
+#if 0
+typedef enum
+{
+ RESET_TO_NORMAL, /*reset to idle*/
+ RESET_TO_CHARGER, /*reset to charger*/
+ RESET_TO_ALRAM, /*reset to alarm*/
+ RESET_TO_EXCEPTRESET,
+ MAX_RESET_TYPE,
+} T_ZDrvSys_RESET_TYPE;
+#endif
+
+typedef enum _T_ZDrvPmic_Enable{
+ PM_DISABLE = 0,
+ PM_ENABLE,
+ PM_ENABLE_NOT_SUPPORT = -100,
+ PM_ENABLE_MAX_STATUS = -255
+} T_ZDrvPmic_Enable;
+
+typedef enum _T_ZDrvPmic_NrmMode{
+ PM_NRMMODE_AUTO = 0,
+ PM_NRMMODE_PFM,
+ PM_NRMMODE_PWM,
+ PM_NRMMODE_NOT_SUPPORT = -100,
+ PM_NRMMODE_MAX_STATUS = -255
+}T_ZDrvPmic_NrmMode;
+
+typedef enum _T_ZDrvPmic_SlpMode{
+ PM_SLPMODE_AUTO_NORMAL = 0, //auto in dcdc, normal in ldo
+ PM_SLPMODE_ECO_NRMV, //normal voltage
+ PM_SLPMODE_ECO_SLPV, //sleep voltage
+ PM_SLPMODE_OFF, //OFF
+ PM_SLPMODE_NOT_SUPPORT = -100,
+ PM_SLPMODE_MAX_STATUS = -255
+}T_ZDrvPmic_SlpMode;
+
+//consumer
+typedef enum _T_ZDrvPmic_Regulator{
+ VCORE0 = 0,
+ VCORE1,
+ VDDR,
+ VMMC,
+ VSD0,
+ VSD1,
+ VIO_LO,
+ VIO_HI,
+ VUSB_0V9,
+ VUSB_3V3,
+ VPLL_LO,
+ VPLL_HI,
+ VSIM1,
+ VSIM2,
+ VRF_LO,
+ VRF_HI,
+ VRF_SW,
+ VPA,
+ VCTCXO1,
+ VCTCXO2,
+ VSSBUF,
+ VRTC,
+} T_ZDrvPmic_Regulator;
+
+typedef enum _T_ZDrvPmic_Vcore{
+ PM_VOLT_0_6750 = 0,
+ PM_VOLT_0_6875 ,
+ PM_VOLT_0_7000 ,
+ PM_VOLT_0_7125 ,
+ PM_VOLT_0_7250 = 0x04,
+ PM_VOLT_0_7375 ,
+ PM_VOLT_0_7500 ,
+ PM_VOLT_0_7625 ,
+ PM_VOLT_0_7750 = 0x08 ,
+ PM_VOLT_0_7875 ,
+ PM_VOLT_0_8000 ,
+ PM_VOLT_0_8125 ,
+ PM_VOLT_0_8250 = 0x0c,
+ PM_VOLT_0_8375 ,
+ PM_VOLT_0_8500 ,
+ PM_VOLT_0_8625 ,
+ PM_VOLT_0_8750 = 0x10 ,
+ PM_VOLT_0_8875 ,
+ PM_VOLT_0_9000 ,
+ PM_VOLT_0_9125 ,
+ PM_VOLT_0_9250 = 0x14,
+ PM_VOLT_0_9375 ,
+ PM_VOLT_0_9500 ,
+ PM_VOLT_0_9625 ,
+ PM_VOLT_0_9750 = 0x18 ,
+ PM_VOLT_0_9875 ,
+ PM_VOLT_1_0000 ,
+ PM_VOLT_1_0125 ,
+ PM_VOLT_1_0250 = 0x1c,
+ PM_VOLT_1_0375 ,
+ PM_VOLT_1_0500 ,
+ PM_VOLT_1_0625 ,
+ PM_VOLT_1_0750 = 0x20 ,
+ PM_VOLT_1_0875 ,
+ PM_VOLT_1_1000 ,
+ PM_VOLT_1_1125 ,
+ PM_VOLT_1_1250 = 0x24,
+ PM_VOLT_1_1375 ,
+ PM_VOLT_1_1500 ,
+ PM_VOLT_1_1625 ,
+ PM_VOLT_1_1750 = 0x28 ,
+ PM_VOLT_1_1875 ,
+ PM_VOLT_1_2000 ,
+ PM_VOLT_1_2125 ,
+ PM_VOLT_1_2250 = 0x2c,
+ PM_VOLT_1_2375 ,
+ PM_VOLT_1_2500 = 0x2e,
+ PM_VOLT_1_2625 ,
+ PM_VOLT_1_2750 = 0x30 ,
+ PM_VOLT_1_2875 ,
+ PM_VOLT_1_3000 ,
+ PM_VOLT_1_3125 ,
+ PM_VOLT_1_3250 = 0x34,
+ PM_VOLT_1_3375 ,
+ PM_VOLT_1_3500 ,
+ PM_VOLT_1_3625 ,
+ PM_VOLT_1_3750 = 0x38 ,
+ PM_VOLT_1_3875 ,
+ PM_VOLT_1_4000 ,
+ PM_VOLT_1_4125 ,
+ PM_VOLT_1_4250 = 0x3c,
+ PM_VOLT_1_4375 ,
+ PM_VOLT_1_4500 ,
+ PM_VOLT_1_4625 ,
+ PM_VOLT_1_4750 = 0x40 ,
+ PM_VOLT_1_4875 ,
+ PM_VOLT_1_5000 ,
+ PM_VOLT_1_5125 ,
+ PM_VOLT_1_5250 = 0x44,
+ PM_VOLT_1_5375 ,
+ PM_VOLT_1_5500 ,
+ PM_VOLT_1_5625 ,
+ PM_VOLT_1_5750 = 0x48,
+ PM_VOLT_1_5875 ,
+ PM_VOLT_1_6000 ,
+ PM_VOLT_1_6125 ,
+ PM_VOLT_1_6250 = 0x4c,
+ PM_VOLT_1_6375 ,
+ PM_VOLT_1_6500 ,
+ PM_VOLT_1_6625 ,
+ PM_VOLT_1_6750 = 0x50,
+ PM_VOLT_1_6875 ,
+ PM_VOLT_1_7000 ,
+ PM_VOLT_1_7125 ,
+ PM_VOLT_1_7250 = 0x54,
+ PM_VOLT_1_7375 ,
+ PM_VOLT_1_7500 ,
+ PM_VOLT_1_7625 ,
+ PM_VOLT_1_7750 = 0x58,
+ PM_VOLT_1_7875 ,
+ PM_VOLT_1_8000 ,
+ PM_VOLT_1_8125 ,
+ PM_VOLT_1_8250 = 0x5c,
+ PM_VOLT_1_8375 ,
+ PM_VOLT_1_8500 ,
+ PM_VOLT_1_8625 ,
+ PM_VOLT_1_8750 = 0x60 ,
+ PM_VOLT_1_8875 ,
+ PM_VOLT_1_9000 ,
+ PM_VOLT_1_9125 ,
+ PM_VOLT_1_9250 = 0x64,
+ PM_VOLT_1_9375 ,
+ PM_VOLT_1_9500 ,
+ PM_VOLT_1_9625 ,
+ PM_VOLT_1_9750 = 0x68,
+ PM_VOLT_1_9875 ,
+ PM_VOLT_2_0000 ,
+ PM_VOLT_2_0125 ,
+ PM_VOLT_2_0250 = 0x6c,
+ PM_VOLT_2_0375 ,
+ PM_VOLT_2_0500 ,
+ PM_VOLT_2_0625 ,
+ PM_VOLT_2_0750 = 0x70,
+ PM_VOLT_2_0875 ,
+ PM_VOLT_2_1000 ,
+ PM_VOLT_2_1125 ,
+ PM_VOLT_2_1250 = 0x74,
+ PM_VOLT_2_1375 ,
+ PM_VOLT_2_1500 ,
+ PM_VOLT_2_1625 ,
+ PM_VOLT_2_1750 = 0x78 ,
+ PM_VOLT_2_1875 ,
+ PM_VOLT_2_2000 ,
+ PM_VOLT_2_2125 ,
+ PM_VOLT_2_2250 = 0x7c,
+ PM_VOLT_2_2375 ,
+ PM_VOLT_2_2500 ,
+ PM_VOLT_2_2625 ,
+ PM_VOLT_2_2750 = 0x80,
+ PM_VOLT_2_2875 ,
+ PM_VOLT_2_3000 ,
+ PM_VOLT_2_3125 ,
+ PM_VOLT_2_3250 = 0x84,
+ PM_VOLT_2_3375 ,
+ PM_VOLT_2_3500 ,
+ PM_VOLT_2_3625 ,
+ PM_VOLT_2_3750 = 0x88 ,
+ PM_VOLT_2_3875 ,
+ PM_VOLT_2_4000 ,
+ PM_VOLT_2_4125 ,
+ PM_VOLT_2_4250 = 0x8c,
+ PM_VOLT_2_4375 ,
+ PM_VOLT_2_4500 ,
+ PM_VOLT_2_4625 ,
+ PM_VOLT_2_4750 = 0x90,
+ PM_VOLT_2_4875 ,
+ PM_VOLT_2_5000 ,
+ PM_VOLT_2_5125 ,
+ PM_VOLT_2_5250 = 0x94,
+ PM_VOLT_2_5375 ,
+ PM_VOLT_2_5500 ,
+ PM_VOLT_2_5625 ,
+ PM_VOLT_2_5750 = 0x98 ,
+ PM_VOLT_2_5875 ,
+ PM_VOLT_2_6000 ,
+ PM_VOLT_2_6125 ,
+ PM_VOLT_2_6250 = 0x9c,
+ PM_VOLT_2_6375 ,
+ PM_VOLT_2_6500 ,
+ PM_VOLT_2_6625 ,
+ PM_VOLT_2_6750 = 0xa0,
+ PM_VOLT_2_6875 ,
+ PM_VOLT_2_7000 ,
+ PM_VOLT_2_7125 ,
+ PM_VOLT_2_7250 = 0xa4,
+ PM_VOLT_2_7375 ,
+ PM_VOLT_2_7500 ,
+ PM_VOLT_2_7625 ,
+ PM_VOLT_2_7750 = 0xa8,
+ PM_VOLT_2_7875 ,
+ PM_VOLT_2_8000 ,
+ PM_VOLT_2_8125 ,
+ PM_VOLT_2_8250 = 0xac,
+ PM_VOLT_2_8375 ,
+ PM_VOLT_2_8500 ,
+ PM_VOLT_2_8625 ,
+ PM_VOLT_2_8750 = 0xb0,
+ PM_VOLT_2_8875 ,
+ PM_VOLT_2_9000 ,
+ PM_VOLT_2_9125 ,
+ PM_VOLT_2_9250 = 0xb4,
+ PM_VOLT_2_9375 ,
+ PM_VOLT_2_9500 ,
+ PM_VOLT_2_9625 ,
+ PM_VOLT_2_9750 = 0xb8,
+ PM_VOLT_2_9875 ,
+ PM_VOLT_3_0000 ,
+ PM_VOLT_3_0125 ,
+ PM_VOLT_3_0250 = 0xbc,
+ PM_VOLT_3_0375 ,
+ PM_VOLT_3_0500 ,
+ PM_VOLT_3_0625 ,
+ PM_VOLT_3_0750 = 0xc0 ,
+ PM_VOLT_3_0875 ,
+ PM_VOLT_3_1000 ,
+ PM_VOLT_3_1125 ,
+ PM_VOLT_3_1250 = 0xc4,
+ PM_VOLT_3_1375 ,
+ PM_VOLT_3_1500 ,
+ PM_VOLT_3_1625 ,
+ PM_VOLT_3_1750 = 0xc8 ,
+ PM_VOLT_3_1875 ,
+ PM_VOLT_3_2000 ,
+ PM_VOLT_3_2125 ,
+ PM_VOLT_3_2250 = 0xcc,
+ PM_VOLT_3_2375 ,
+ PM_VOLT_3_2500 ,
+ PM_VOLT_3_2625 ,
+ PM_VOLT_3_2750 = 0xd0 ,
+ PM_VOLT_3_2875 ,
+ PM_VOLT_3_3000 ,
+ PM_VOLT_3_3125 ,
+ PM_VOLT_3_3250 = 0xd4,
+ PM_VOLT_3_3375 ,
+ PM_VOLT_3_3500 ,
+ PM_VOLT_3_3625 ,
+ PM_VOLT_3_3750 = 0xd8 ,
+ PM_VOLT_3_3875 ,
+
+ PM_VOLT_NOT_SUPPORT = -100,
+ PM_VOLT_MAX_STATUS = -255,
+ } T_ZDrvPmic_Voltage;
+
+
+
+
+/**
+ * struct zx234290 - zx234290 sub-driver chip access routines
+ */
+
+struct zx234290 {
+ struct device *dev;
+ /* for read/write acces */
+ struct mutex io_mutex;
+
+ /* For device IO interfaces: I2C or SPI */
+ void *control_data;
+
+ int (*read)(struct zx234290 *zx234290, u8 reg, int size, void *dest);
+ int (*write)(struct zx234290 *zx234290, u8 reg, int size, void *src);
+
+ /* Client devices */
+ struct zx234290_regulator *regulator;
+
+ /* GPIO Handling */
+
+ /* IRQ Handling */
+ struct mutex irq_lock;
+ int chip_irq;
+ int irq_base;
+ struct irq_domain * irq_domain;
+ int irq_num;
+ unsigned int irq_mask;
+};
+int zx234290_i2c_read_simple(u8 reg, void *dest);
+int zx234290_i2c_write_simple(u8 reg, void *src);
+int zx234290_i2c_read_simple_PSM(u8 reg, void *dest);
+int zx234290_i2c_write_simple_PSM(u8 reg, void *src);
+
+int zx234290_reg_read(struct zx234290 *zx234290, u8 reg);
+int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val);
+int zx234290_device_init(struct zx234290 *zx234290);
+void zx234290_device_exit(struct zx234290 *zx234290);
+
+
+/*regulator defines*/
+#if 1
+/*
+ * List of registers for ZX234290
+*/
+
+/////////////////////////////////////////////////
+/*slave address 0x12*/
+/////////////////////////////////////////////////
+#define ZX234290_I2C_SLAVE_ADDR0 (0x12)
+
+ /* interrupt and mask */
+#define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */
+#define ZX234290_REG_ADDR_INTB 0x01
+#define ZX234290_REG_ADDR_INTA_MASK 0x02
+#define ZX234290_REG_ADDR_INTB_MASK 0x03
+
+ /* interrupt status */
+#define ZX234290_REG_ADDR_STSA 0x04
+#define ZX234290_REG_ADDR_STSB 0x05
+#define ZX234290_REG_ADDR_STS_STARTUP 0x06
+
+ /* adc & softon select */
+#define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/
+
+ /* bucks normal voltage and sleep voltage */
+#define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/
+#define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D
+
+ /* bucks mode */
+#define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/
+#define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/
+#define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */
+
+ /* ldo normal voltage */
+#define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */
+#define ZX234290_REG_ADDR_LDO34_VOL 0x13
+#define ZX234290_REG_ADDR_LDO56_VOL 0x14
+#define ZX234290_REG_ADDR_LDO78_VOL 0x15
+#define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */
+#define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/
+
+
+#define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */
+
+ /* ldo sleep voltage */
+#define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/
+#define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */
+#define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/
+#define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */
+#define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */
+
+ /* ldo mode */
+#define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/
+#define ZX234290_REG_ADDR_LDO5678_MODE 0x1F
+#define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */
+
+ /* ldo enable */
+#define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */
+#define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/
+
+ /* adc code */
+#define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/
+#define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/
+#define ZX234290_REG_ADDR_ADC1_MSB 0x25
+#define ZX234290_REG_ADDR_ADC1_LSB 0x26
+#define ZX234290_REG_ADDR_ADC2_MSB 0x27
+#define ZX234290_REG_ADDR_ADC2_LSB 0x28
+
+ /* sink control */
+#define ZX234297_REG_ADDR_SINK_CONTROL 0x29
+
+ /* rtc */
+#define ZX234290_REG_ADDR_RTC_CTRL1 0x30
+#define ZX234290_REG_ADDR_RTC_CTRL2 0x31
+
+ /* date and time */
+#define ZX234290_REG_ADDR_SECONDS 0x32
+#define ZX234290_REG_ADDR_MINUTES 0x33
+#define ZX234290_REG_ADDR_HOURS 0x34
+#define ZX234290_REG_ADDR_DAY 0x35
+#define ZX234290_REG_ADDR_WEEK 0x36
+#define ZX234290_REG_ADDR_MONTH 0x37
+#define ZX234290_REG_ADDR_YEAR 0x38
+
+ /* alarm */
+#define ZX234290_REG_ADDR_ALARM_MINUTE 0x39
+#define ZX234290_REG_ADDR_ALARM_HOUR 0x3A
+#define ZX234290_REG_ADDR_ALARM_DAY 0x3B
+#define ZX234290_REG_ADDR_ALARM_WEEK 0x3C
+#define ZX234290_REG_ADDR_ALARM_SECOND 0x3D
+
+#define ZX234290_REG_ADDR_TIMER_CTRL 0x3E
+#define ZX234290_REG_ADDR_TIMER_CNT 0x3F
+
+ /* enable ldo output discharge resistance */
+#define ZX234290_REG_ADDR_EN_DISCH1 0x40
+#define ZX234290_REG_ADDR_EN_DISCH2 0x41
+
+ /* power key control */
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42
+#define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43
+
+#define ZX234290_REG_ADDR_VERSION 0x44
+
+ /*fault status*/
+#define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45
+#define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46
+
+#define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47
+#define ZX234290_REG_ADDR_LDO_INT_MASK 0x48
+
+#define ZX234290_REG_ADDR_USER_RESERVED 0x50
+#define ZX234290_REG_ADDR_GMT_TESTING 0xf1
+
+#define ZX234290_MAX_REGISTER 0x51 //yuxiang ?
+
+/*0x04 status A*/
+#define ZX234290_STATUSA_POWERON_LSH (5)
+#define ZX234290_STATUSA_POWERON_WID (1)
+#define ZX234290_STATUSA_EOCADC_LSH (2)
+#define ZX234290_STATUSA_EOCADC_WID (1)
+
+/* 0x06 STATUS REG -- STARTUP */
+#define ZX234290_SYSPOR_STATUS_PWRON_STARTUP (0x1 << 0) /* PWR ON button */
+#define ZX234290_SYSPOR_STATUS_RTC_ALARM_STARTUP (0x1 << 1)
+#define ZX234290_SYSPOR_STATUS_PSHOLD_STARTUP (0x1 << 2)
+#define ZX234290_SYSPOR_STATUS_PWRONLLP_STARTUP (0x1 << 3)
+
+/* discharger */
+#define ZX234290_DISCHG1_LSB_LSH (0)
+#define ZX234290_DISCHG1_LSB_WID (4)
+
+#define ZX234290_DISCHG1_MSB_LSH (5)
+#define ZX234290_DISCHG1_MSB_WID (2)
+
+#define ZX234290_DISCHG2_LSH (0)
+#define ZX234290_DISCHG2_WID (8)
+
+
+/* BUCK VOLTAGE */
+#define ZX234290_BUCK01_VSEL_LSH (0)
+#define ZX234290_BUCK01_VSEL_WID (6)
+
+/* BUCK SLEEP VOLTAGE */
+#define ZX234290_BUCK01_SLEEP_VSEL_LSH (0)
+#define ZX234290_BUCK01_SLEEP_VSEL_WID (6)
+
+/* BUCKS MODE CTROL */
+#define ZX234290_REGULATOR_MODE_WID (2)
+
+#define ZX234290_BUCK0_SLPMODE_LSH (0)
+#define ZX234290_BUCK0_NRMMODE_LSH (2)
+#define ZX234290_BUCK1_SLPMODE_LSH (4)
+#define ZX234290_BUCK1_NRMMODE_LSH (6) /*[7:6]*/
+#define ZX234290_BUCK2_SLPMODE_LSH (0)
+#define ZX234290_BUCK2_NRMMODE_LSH (2)
+#define ZX234290_BUCK3_SLPMODE_LSH (4)
+#define ZX234290_BUCK3_NRMMODE_LSH (6)
+#define ZX234290_BUCK4_SLPMODE_LSH (0)
+#define ZX234290_BUCK4_NRMMODE_LSH (2)
+
+/* LDO MODE, ONLY SLEEP MODE */
+#define ZX234290_LDO1_SLPMODE_LSH (0)
+#define ZX234290_LDO2_SLPMODE_LSH (2)
+#define ZX234290_LDO3_SLPMODE_LSH (4)
+#define ZX234290_LDO4_SLPMODE_LSH (6)
+#define ZX234290_LDO5_SLPMODE_LSH (0)
+#define ZX234290_LDO6_SLPMODE_LSH (2)
+#define ZX234290_LDO7_SLPMODE_LSH (4)
+#define ZX234290_LDO8_SLPMODE_LSH (6)
+#define ZX234290_LDO9_SLPMODE_LSH (2)
+#define ZX234290_LDO10_SLPMODE_LSH (4)
+//#define ZX234290_LDO11_SLPMODE_LSH (6)
+
+/* LDO VOLTAGE SELECT */
+#define ZX234290_LDO_VSEL_WID (4)
+
+#define ZX234290_LDO1_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_VSEL_LSH (0)
+#define ZX234290_LDO4_VSEL_LSH (4)
+#define ZX234290_LDO5_VSEL_LSH (0)
+#define ZX234290_LDO6_VSEL_LSH (4)
+#define ZX234290_LDO7_VSEL_LSH (0)
+#define ZX234290_LDO8_VSEL_LSH (4)
+#define ZX234290_LDO9_VSEL_LSH (4)
+#define ZX234290_LDO10_VSEL_LSH (0)
+#define ZX234290_LDO11_VSEL_LSH (0) /* [3:0] */
+
+#define ZX234290_VORTC_VSEL_WID (2)
+#define ZX234290_VORTC_VSEL_LSH (4) /* [5][4] */
+#define ZX234290_LDO5_VSEL_WID (2) /* [1][0]*/
+
+
+/* LDO SLEEP VOLTAGE */
+#define ZX234290_BUCK2_VSEL_WID (5)
+
+#define ZX234290_BUCK2_VSEL_LSH (0)
+
+#define ZX234290_LDO1_SLP_VSEL_LSH (0) /* [3:0] */
+#define ZX234290_LDO2_SLP_VSEL_LSH (4) /* [7:4] */
+#define ZX234290_LDO3_SLP_VSEL_LSH (0)
+#define ZX234290_LDO7_SLP_VSEL_LSH (0)
+#define ZX234290_LDO8_SLP_VSEL_LSH (0)
+#define ZX234290_LDO11_SLP_VSEL_LSH (0) /* [3:0] */
+
+/* ENABLE 0x21-0x22 */
+#define ZX234290_LDOS_ON_WID (1)
+
+#define ZX234290_LDO1_ON_LSH (0)
+#define ZX234290_LDO2_ON_LSH (1)
+#define ZX234290_LDO3_ON_LSH (2)
+#define ZX234290_LDO4_ON_LSH (3)
+#define ZX234290_LDO5_ON_LSH (4)
+#define ZX234290_LDO6_ON_LSH (5)
+#define ZX234290_LDO7_ON_LSH (6)
+#define ZX234290_LDO8_ON_LSH (7)
+
+#define ZX234290_LDO9_ON_LSH (1)
+#define ZX234297_LDO9_ON_LSH (0)
+#define ZX234290_LDO10_ON_LSH (2)
+#define ZX234297_LDO10_ON_LSH (1)
+#define ZX234290_BUCK1_ON_LSH (4)
+#define ZX234290_BUCK2_ON_LSH (5)
+#define ZX234290_BUCK3_ON_LSH (6)
+#define ZX234290_BUCK4_ON_LSH (7)
+
+/* LONG PRESSED TIME */
+#define ZX234290_PWRON_TIME_LSH (0)
+#define ZX234290_PWRON_TIME_WID (2)
+#define ZX234290_PWRON_LONGPRESS_EN_LSH (2)
+#define ZX234290_PWRON_LONGPRESS_EN_WID (1)
+#define ZX234290_PWRON_LLP_TODO_LSH (3) /* LLP long long pressed */
+#define ZX234290_PWRON_LLP_TODO_WID (1)
+
+/* sys ctrol 0x07 */
+#define ZX234290_SINK1_EN_LSH (0)
+#define ZX234290_SINK1_EN_WID (1)
+#define ZX234290_SINK2_EN_LSH (1)
+#define ZX234290_SINK2_EN_WID (1)
+#define ZX234290_ADC1_EN_LSH (4)
+#define ZX234290_ADC1_EN_WID (1)
+#define ZX234290_ADC2_EN_LSH (3)
+#define ZX234290_ADC2_EN_WID (1)
+#define ZX234290_ADC_START_LSH (5)
+#define ZX234290_ADC_START_WID (1)
+#define ZX234290_SOFTON_LSH (7)
+
+/* 0x08 */
+#define ZX234290_SINK2_CURSEL_LSH (0)
+#define ZX234290_SINK2_CURSEL_WID (4)
+/* 0x09 */
+#define ZX234290_SINK1_CURSEL_LSH (0)
+#define ZX234290_SINK1_CURSEL_WID (4)
+
+/* 0x20 */
+#define ZX234297_SINK1_SLP_MODE_LSH (6)
+#define ZX234297_SINK2_SLP_MODE_LSH (7)
+#define ZX234297_SINK_SLP_MODE_WID (1)
+/* 0x22 */
+#define ZX234297_SINK1_ON_LSH (2)
+#define ZX234297_SINK2_ON_LSH (3)
+#define ZX234297_SINK_ON_WID (1)
+/* 0x29 */
+#define ZX234297_SINK1_CURRENT_LSH (0)
+#define ZX234297_SINK2_CURRENT_LSH (4)
+#define ZX234297_SINK_CURRENT_WID (4)
+
+#define ZX234290_LDO_RSTERR_LSH (0)
+#define ZX234290_LDO_RSTERR_WID (1)
+
+#endif /* end of ZX234290 */
+
+#define ZX234290_BITFVAL(var, lsh) ( (var) << (lsh) )
+#define ZX234290_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) )
+#define ZX234290_BITFEXT(var, wid, lsh) ((var & ZX234290_BITFMASK(wid, lsh)) >> (lsh))
+
+/* VBA - BUCK1 6bit */
+typedef enum _T_ZDrvZx234290_VbuckA
+{
+ VBUCKA_0_675 = 0x00,
+ VBUCKA_0_700 = 0x02,
+ VBUCKA_0_750 = 0x06,
+ VBUCKA_0_800 = 0x0a,
+ VBUCKA_0_850 = 0x0e,
+ VBUCKA_0_900 = 0x12,/*default*/
+ VBUCKA_0_950 = 0x16,
+ VBUCKA_1_000 = 0x1a,
+ VBUCKA_1_050 = 0x1e,
+ VBUCKA_1_100 = 0x22,
+ VBUCKA_1_150 = 0x26,
+ VBUCKA_1_200 = 0x2a,
+ VBUCKA_1_250 = 0x2e,
+
+ VBUCKA_MAX
+
+}T_ZDrvZx234290_VbuckA;
+
+/* VBC - BUCK2 */
+typedef enum _T_ZDrvZx234290_VbuckC
+{
+ VBUCKC_0_850 = 0x00,
+ VBUCKC_0_900 = 0x02,
+ VBUCKC_0_950 = 0x04,
+ VBUCKC_1_000 = 0x06,
+ VBUCKC_1_050 = 0x08,
+ VBUCKC_1_100 = 0x0a,
+ VBUCKC_1_150 = 0x0c,
+ VBUCKC_1_200 = 0x0e,/*default*/
+ VBUCKC_1_250 = 0x10,
+ VBUCKC_1_300 = 0x12,
+ VBUCKC_1_350 = 0x14,
+ VBUCKC_1_400 = 0x16,
+ VBUCKC_1_450 = 0x18,
+ VBUCKC_1_500 = 0x1a,
+ VBUCKC_1_550 = 0x1c,
+ VBUCKC_1_600 = 0x1e,
+
+ VBUCKC_MAX
+
+}T_ZDrvZx234290_VbuckC;
+
+/* VLA - ldo1/9/10 */
+typedef enum _T_ZDrvZx234290_VldoA
+{
+ VLDOA_0_725 = 0,
+ VLDOA_0_750 = 1,
+ VLDOA_0_775 = 2,
+ VLDOA_0_800 = 3,
+ VLDOA_0_825 = 4,
+ VLDOA_0_850 = 5,
+ VLDOA_0_875 = 6,
+ VLDOA_0_900 = 7,
+ VLDOA_0_925 = 8,
+ VLDOA_0_950 = 9,
+ VLDOA_0_975 = 10,
+ VLDOA_1_000 = 11,
+ VLDOA_1_025 = 12,
+ VLDOA_1_050 = 13,
+ VLDOA_1_075 = 14,
+ VLDOA_1_100 = 15,
+
+ VLDOA_MAX
+
+}T_ZDrvZx234290_VldoA;
+
+/* VLB - ldo5 2bit */
+typedef enum _T_ZDrvZx234290_VldoB
+{
+ VLDOB_3_300 = 0,
+ VLDOB_3_150 = 1,
+ VLDOB_3_000 = 2,
+ VLDOB_1_800 = 3, /* 11 */
+
+ VLDOB_MAX
+
+}T_ZDrvZx234290_VldoB;
+
+/* VLC - ldo2/ldo3 */
+typedef enum _T_ZDrvZx234290_VldoC
+{
+ VLDOC_0_750 = 0,
+ VLDOC_0_800 = 1,
+ VLDOC_0_850 = 2,
+ VLDOC_0_900 = 3,
+ VLDOC_0_950 = 4,
+ VLDOC_1_000 = 5,
+ VLDOC_1_050 = 6,
+ VLDOC_1_100 = 7,
+ VLDOC_1_200 = 8,
+ VLDOC_1_500 = 9,
+ VLDOC_1_800 = 10,
+ VLDOC_2_000 = 11,
+ VLDOC_2_500 = 12,
+ VLDOC_2_800 = 13,
+ VLDOC_3_000 = 14,
+ VLDOC_3_300 = 15,
+
+ VLDOC_MAX
+
+}T_ZDrvZx234290_VldoC;
+
+/* VLD - ldo4/6/7/8 */
+typedef enum _T_ZDrvZx234290_VldoD
+{
+ VLDOD_1_400 = 0,
+ VLDOD_1_500 = 1,
+ VLDOD_1_600 = 2,
+ VLDOD_1_800 = 3,
+ VLDOD_1_850 = 4,
+ VLDOD_2_000 = 5,
+ VLDOD_2_050 = 6,
+ VLDOD_2_500 = 7,
+ VLDOD_2_550 = 8,
+ VLDOD_2_700 = 9,
+ VLDOD_2_750 = 10,
+ VLDOD_2_800 = 11,
+ VLDOD_2_850 = 12,
+ VLDOD_2_900 = 13,
+ VLDOD_2_950 = 14,
+ VLDOD_3_000 = 15,
+
+ VLDOD_MAX
+
+}T_ZDrvZx234290_VldoD;
+
+/* VORTC 2bit */
+typedef enum _T_ZDrvZx234290_VldoE
+{
+ VLDOE_1_800 = 0,
+ VLDOE_2_500 = 1,
+ VLDOE_3_000 = 2,
+ VLDOE_3_300 = 3, /* 11 */
+
+ VLDOE_MAX
+
+}T_ZDrvZx234290_VldoE;
+
+/* VLF - ldo10 */
+typedef enum _T_ZDrvZx234297_VldoF
+{
+ VLDOF_0_800 = 0,
+ VLDOF_0_850 = 1,
+ VLDOF_0_900 = 2,
+ VLDOF_0_950 = 3,
+
+ VLDOF_1_000 = 4,
+ VLDOF_1_050 = 5,
+ VLDOF_1_100 = 6,
+ VLDOF_1_200 = 7,
+
+ VLDOF_1_300 = 8,
+ VLDOF_1_400 = 9,
+ VLDOF_1_500 = 10,
+ VLDOF_1_800 = 11,
+
+ VLDOF_2_500 = 12,
+ VLDOF_2_800 = 13,
+ VLDOF_3_000 = 14,
+ VLDOF_3_300 = 15,
+
+ VLDOF_MAX
+
+}T_ZDrvZx234297_VldoF;
+
+/* BUCK3/4 EXTERNAL ADJUSTABLE */
+
+typedef enum _T_ZDrvZx234290_LDO_ENABLE
+{
+ LDO_ENABLE_OFF = 0, /* 00 */
+ LDO_ENABLE_ON = 1, /* 10 */
+
+ LDO_AVTICE_MAX
+}T_ZDrvZx234290_LDO_ENABLE;
+
+
+/*
+ ¹ØÓÚ BUCKSµÄģʽ£¬·ÖΪÕý³£Ä£Ê½Óë˯Ãßģʽ£¬ Õý³£Ä£Ê½Ö»¹Ø×¢PFM/PWM£¬²»¹Ø×¢¿ª¹Ø¡£
+ ˯Ãßģʽ¹Ø×¢PFM/PWM/ECO/OFF/NRM£¬Ó¦¸Ã½âÊÍΪ ˯ÃßģʽµÄ״̬²»½ö¹Ø×¢PWM/PFM£¬
+ ¶øÇÒ¹Ø×¢´ò¿ª¹Ø±Õ£¬³ýÁËOFF£¬ÆäËû¶¼ÊÇÔÚ¿ª×ŵÄÇé¿öϵÄģʽ£»¶øĬÈÏ¿ªµÄÇé¿öÔòÊÇ
+ NRMMODE£¬µçѹÓÃ˯Ãßµçѹ£»
+ ¶øLDOSµÄ˯Ãßģʽ£¬Ò»ÑùÓëÕý³£Ä£Ê½²»Ïà¸É¡£ÆäÒ²ÓÐNRM/ECO/OFFÕ⼸ÖÖ״̬
+*/
+
+/* BUCK1/2/3/4 NORMAL MODE */
+typedef enum _T_ZDrvZx234290_BUCK_NRMMODE
+{
+ BUCK_NRM_AUTO_WITH_ECO = 0, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRM_FORCE_PWM = 2, /* 10 FORCE PWM */
+ BUCK_NRM_AUTO_WITHOUT_ECO = 3, /* 00/01 AUTO PWM/PSM ECO */
+ BUCK_NRMMODE_MAX
+}T_ZDrvZx234290_BUCK_NRMMODE;
+
+/* BUCK1 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK1_SLPMODE
+{
+ BUCK1_SLP_AUTO_WITHOUT_ECO = 0, /* 00/11 AUTO PWM/PFM */
+ BUCK1_SLP_AUTO_ECO = 1, /*BUCK1_SLP_AUTO_ECO_VOLT output voltage configred by FBDC1[5:0]*/
+ BUCK1_SLP_AUTO_ECO_SLP = 2, /* output voltage configred by FBDC1_SLP[5:0]*/
+ BUCK1_SLP_SHUTDOWN = 3, /* 11 OFF */
+ BUCK1_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK1_SLPMODE;
+
+/* BUCK2/3/4 SLPMODE */
+typedef enum _T_ZDrvZx234290_BUCK234_SLPMODE
+{
+ BUCK234_SLP_AUTO_WITHOUT_ECO = 0, /* 00 AUTO PWM/PFM without eco*/
+ BUCK234_SLP_ECO_WITH_ECO = 1, /* 01Óë10¾ùÊÇ ECO */
+ BUCK234_SLP_SHUTDOWN = 3, /* 11 OFF */
+
+ BUCK234_SLPMODE_MAX
+}T_ZDrvZx234290_BUCK234_SLPMODE;
+
+/* LDO1/2/3/7/8/9/10 SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOA_SLPMODE
+{
+ LDOA_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOA_SLP_ECO_VOLT_SLP = 2, /* VOLDOx_SLP[3:0] */
+ LDOA_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOA_SLPMODE_MAX
+}T_ZDrvZx234290_LDOA_SLPMODE;
+
+/* LDO4/5/6/ SLPMODE */
+typedef enum _T_ZDrvZx234290_LDOB_SLPMODE
+{
+ LDOB_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */
+ LDOB_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */
+ LDOB_SLP_NRM_MODE_VOLT = 2, /* VOLDOx[3:0] */
+ LDOB_SLP_SHUTDOWN = 3, /* 11 OFF */
+ LDOB_SLPMODE_MAX
+}T_ZDrvZx234290_LDOB_SLPMODE;
+
+typedef enum _T_ZDrvZx234290_LdoDischarger
+{
+ DISCHARGER_LDO_9 = 0,
+ DISCHARGER_LDO_10,
+ DISCHARGER_LDO_X, /*not support*/
+ DISCHARGER_BUCK_4,
+ DISCHARGER_BUCK_3,
+ DISCHARGER_BUCK_2,
+ DISCHARGER_BUCK_1,
+ DISCHARGER_BUCK_X, /*not support*/
+
+ DISCHARGER_LDO_1,
+ DISCHARGER_LDO_2,
+ DISCHARGER_LDO_3,
+ DISCHARGER_LDO_4,
+ DISCHARGER_LDO_5,
+ DISCHARGER_LDO_6,
+ DISCHARGER_LDO_7,
+ DISCHARGER_LDO_8,
+
+ DISCHARGER_MAX
+}T_ZDrvZx234290_LdoDischarger;
+
+typedef enum _T_ZDrvZx234290_DISCHARGER_ENABLE
+{
+ DISCHARGER_DISBALE = 0, /* 00 */
+ DISCHARGER_ENABLE = 1, /* 10 */
+
+ DISCHARGER_ENABLE_MAX
+}T_ZDrvZx234290_DISCHARGER_ENABLE;
+
+typedef enum _T_ZDrvZx234290_LdoList
+{
+ LDOLIST_BUCK_1 = 0,
+ LDOLIST_BUCK_2,
+ LDOLIST_BUCK_3,
+ LDOLIST_BUCK_4,
+ LDOLIST_LDO_1,
+ LDOLIST_LDO_2,
+ LDOLIST_LDO_3,
+
+ LDOLIST_LDO_4,
+ LDOLIST_LDO_5,
+ LDOLIST_LDO_6,//default off
+ LDOLIST_LDO_7,
+ LDOLIST_LDO_8,
+ LDOLIST_LDO_9,//default off
+ LDOLIST_LDO_10,
+ LDOLIST_LDO_RTC,
+
+ LDOLIST_MAX
+}T_ZDrvZx234290_LdoList;
+
+typedef enum _T_ZDrvZx234297_SINK
+{
+ ZX234297_SINK1 = 0, /* 00 */
+ ZX234297_SINK2 = 1, /* 10 */
+
+ ZX234297_SINK_MAX
+}T_ZDrvZx234297_SINK;
+
+typedef enum _T_ZDrvZx234297_SINK_SLPMODE
+{
+ SLPMODE_NORMAL = 0, /* 00 */
+ SLPMODE_SHUTDOWN = 1, /* 10 */
+
+ SLPMODE_MAX
+}T_ZDrvZx234297_SINK_SLPMODE;
+
+typedef enum _T_ZDrvZx234297_SINK_CURRENT
+{
+ SINK_CURRENT_5MA,
+ SINK_CURRENT_10MA,
+ SINK_CURRENT_15MA,
+ SINK_CURRENT_20MA,
+ SINK_CURRENT_30MA,
+ SINK_CURRENT_40MA,
+ SINK_CURRENT_50MA,
+ SINK_CURRENT_60MA,
+ SINK_CURRENT_70MA,
+ SINK_CURRENT_80MA,
+ SINK_CURRENT_90MA,
+ SINK_CURRENT_100MA,
+ SINK_CURRENT_110MA,
+ SINK_CURRENT_120MA,
+
+ SINK_CURRENT_MAX
+}T_ZDrvZx234297_SINK_CURRENT;
+
+typedef enum _T_ZDrvZx234290_ResetType
+{
+#if 0
+ ZX234290_USER_RST_UNDEFINE = 0,
+ ZX234290_USER_RST_TO_NORMAL = 1,
+ ZX234290_USER_RST_TO_CHARGER = 2,
+ ZX234290_USER_RST_TO_ALARM = 3,
+#else
+ ZX234290_USER_RST_UNDEFINE = 3,
+ ZX234290_USER_RST_TO_NORMAL = 0,
+ ZX234290_USER_RST_TO_CHARGER = 1,
+ ZX234290_USER_RST_TO_ALARM = 2,
+#endif
+ ZX234290_USER_RST_TO_EXCEPT = 4,
+
+ ZX234290_USER_RST_MAX
+}T_ZDrvZx234290_ResetType;
+
+
+int zx234290_get_chip_version(void);
+int zx234290_irq_init(struct zx234290 *zx234290);
+
+int zx234290_set_buck1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_buck1_onoff(void);
+int zx234290_set_buck1_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+T_ZDrvZx234290_BUCK_NRMMODE zx234290_get_buck1_active_mode(void);
+int zx234290_set_buck1_voltage(T_ZDrvZx234290_VbuckA vol);
+T_ZDrvZx234290_VbuckA zx234290_get_buck1_voltage(void);
+int zx234290_set_buck1_sleep_mode(T_ZDrvZx234290_BUCK1_SLPMODE status);
+T_ZDrvZx234290_BUCK1_SLPMODE zx234290_get_buck1_sleep_mode(void);
+int zx234290_set_buck1_sleep_voltage(T_ZDrvZx234290_VbuckA vol);
+
+int zx234290_set_buck2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck2_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck2_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+int zx234290_set_buck3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck3_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck3_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+int zx234290_set_buck4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_buck4_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status);
+int zx234290_set_buck4_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status);
+
+
+
+int zx234290_set_ldo1_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo1_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo1_onoff(void);
+int zx234290_set_ldo1_voltage(T_ZDrvZx234290_VldoA vol);
+T_ZDrvZx234290_VldoA zx234290_get_ldo1_voltage(void);
+int zx234290_set_ldo1_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo1_sleep_mode(void);
+
+
+int zx234290_set_ldo2_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo2_onoff(void);
+int zx234290_set_ldo2_voltage(T_ZDrvZx234290_VldoC vol);
+T_ZDrvZx234290_VldoC zx234290_get_ldo2_voltage(void);
+int zx234290_set_ldo2_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo2_sleep_mode(void);
+
+int zx234290_set_ldo3_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo3_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo4_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo4_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+
+
+int zx234290_set_ldo5_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo5_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo5_onoff(void);
+int zx234290_set_ldo5_voltage(T_ZDrvZx234290_VldoB vol);
+T_ZDrvZx234290_VldoB zx234290_get_ldo5_voltage(void);
+int zx234290_set_ldo5_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo5_sleep_mode(void);
+
+int zx234290_set_ldo6_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo6_onoff(void);
+int zx234290_set_ldo6_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo6_voltage(void);
+int zx234290_set_ldo6_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status);
+T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo6_sleep_mode(void);
+
+int zx234290_set_ldo7_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo7_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo8_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo8_onoff(void);
+int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol);
+T_ZDrvZx234290_VldoD zx234290_get_ldo8_voltage(void);
+int zx234290_set_ldo8_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo8_sleep_mode(void);
+int zx234290_set_ldo9_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo9_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+
+int zx234290_set_ldo10_onoff(T_ZDrvZx234290_LDO_ENABLE status);
+int zx234290_set_ldo10_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status);
+T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo10_onoff(void);
+T_ZDrvZx234297_VldoF zx234290_get_ldo10_voltageF(void);
+T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo10_sleep_mode(void);
+int zx234297_set_ldo10_voltageF(T_ZDrvZx234297_VldoF vol);
+
+int zDrvPmic_SetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Onoff_PSM(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable);
+int zDrvPmic_SetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_SetSleep_Voltage(T_ZDrvPmic_Regulator regulator, int voltage);
+int zDrvPmic_GetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable* enable);
+int zDrvPmic_GetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int* voltage);
+
+
+/*adc fun*/
+uint get_battery_voltage(void);
+uint get_adc1_voltage(void);
+uint get_adc2_voltage(void);
+
+
+#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/upstream/linux-5.10/include/linux/mmc/mmc_func.h b/upstream/linux-5.10/include/linux/mmc/mmc_func.h
new file mode 100755
index 0000000..b2636ab
--- /dev/null
+++ b/upstream/linux-5.10/include/linux/mmc/mmc_func.h
@@ -0,0 +1,37 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2014, ÉîÛÚÊÐÖÐÐËͨѶ΢µç×Ó
+*
+* ÎļþÃû³Æ£º emmc_ramdump.c
+* Îļþ±êʶ£º
+* ÄÚÈÝÕªÒª£º
+* ÆäËü˵Ã÷£º
+* µ±Ç°°æ±¾£º 1.0
+* ×÷¡¡¡¡Õߣº
+* Íê³ÉÈÕÆÚ£º
+*******************************************************************************/
+
+
+#ifndef LINUX_MMC_MMC_FUNC_H
+#define LINUX_MMC_MMC_FUNC_H
+
+#include <linux/types.h>
+
+int mmc_ramdump_init(void);
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file stored;
+*/
+int mmc_bwrite(u32 start_addr, u32 data_size, void *src_buf);
+
+/*
+* start_addr: the address is the emmc address you want to write,and it size is
+* an integer multiple of 512. defined by byte
+* data_size: the size of data you want to write .defined by byte
+* src_buf: data buffer where log or file will store;
+*/
+
+int mmc_bread(u32 start_addr, u32 data_size, void *dst);
+
+#endif /* LINUX_MMC_MMC_FUNC_H */
diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c b/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
new file mode 100755
index 0000000..bcb6a53
--- /dev/null
+++ b/upstream/linux-5.10/kernel/ramdump/ramdump_client_cap.c
@@ -0,0 +1,457 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_client_cap.c
+* Îļþ±êʶ: ramdump_client_cap.c
+* ÄÚÈÝÕªÒª: ramdump cap¿Í»§¶ËÒì³£ËÀ»úÏÖ³¡Êý¾Ýµ¼³öʵÏÖ
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2019/10/10 V1.0 Create 00130574 ´´½¨
+*
+*******************************************************************************/
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_arch.h"
+#include <linux/module.h>
+#include <linux/soc/zte/rpmsg.h>
+#include "ram_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* ³£Á¿¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* º¯ÊýÉùÃ÷ *
+*******************************************************************************/
+extern void ramdump_register_callbacks(void);
+extern unsigned char *ramdump_phy_to_vir(unsigned long phy, unsigned long size);
+extern void ramdump_shared_mem_init(void);
+extern void ramdump_data_transfer_to_device(void);
+extern void ramdump_oss_data_trans_init(void);
+extern unsigned char *ramdump_export_flag_base;
+
+/*******************************************************************************
+* ¾Ö²¿¾²Ì¬±äÁ¿¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_ON_DEFAULT_VAL (1)
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿¶¨Òå *
+*******************************************************************************/
+/*
+ * run time control dump or not, use ( echo "0" > ramdump_on ) to close ramdump
+ */
+int sysctl_ramdump_on_panic = RAMDUMP_ON_DEFAULT_VAL;
+int ramdump_cap_init_flag = -1;
+int ramdump_count = 0;
+int ramdump_server_exp_core = RAMDUMP_FALSE;
+#ifdef CONFIG_RAMDUMP_USER
+unsigned int sysctl_ramdump_on_user = 1;
+#endif
+unsigned int ramdump_export_mode = 0xFF;
+/* Cmm file content */
+unsigned char *ramdump_cap_cmm_buf = NULL;
+/* err log file */
+unsigned char *ramdump_cap_error_log = NULL;
+unsigned int *cap_ddr_len_base = NULL;
+unsigned int sysctl_ramdump_emmc_size = 0x0;
+unsigned int sysctl_ramdump_emmc_start_addr = 0xFFFF;
+
+static struct ctl_table cfg_ramdump_array[] = {
+#ifdef CONFIG_RAMDUMP_USER
+ {
+ .procname = "sysctl_ramdump_on_user",
+ .data = &sysctl_ramdump_on_user,
+ .maxlen = sizeof(sysctl_ramdump_on_user),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ .extra1 = SYSCTL_ZERO,
+ .extra2 = SYSCTL_ONE,
+ },
+#endif
+ {
+ .procname = "ramdump_start_addr",
+ .data = &sysctl_ramdump_emmc_start_addr,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_dointvec_minmax,
+ },
+ {
+ .procname = "ramdump_emmc_size",
+ .data = &sysctl_ramdump_emmc_size,
+ .maxlen = sizeof(u64),
+ .mode = 0644,
+ .proc_handler = proc_doulongvec_minmax,
+ },
+
+ { }
+};
+
+static struct ctl_table sysctl_ramdump_table[] = {
+ {
+ .procname = "ramdump_ap",
+ .mode = 0555,
+ .child = cfg_ramdump_array,
+ },
+ { }
+};
+
+/*******************************************************************************
+* ¾Ö²¿º¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_handle
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) buf: icp msg addr
+* len: icp msg len
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp msg handle, common entry
+*******************************************************************************/
+static void ramdump_cap_icp_handle(void *buf, unsigned int len)
+{
+ ramdump_msg_t *icp_msg = (ramdump_msg_t *)buf;
+
+ ramdump_server_exp_core = RAMDUMP_SUCCESS;
+
+ switch(icp_msg->msg_id)
+ {
+ case RAMDUMP_MSG_EXCEPT:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+
+ default:
+ {
+ ramdump_panic("trans server received forced dump request from Ap server!\n");
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_create_channel
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ size: icp channel size
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_create_channel(T_RpMsg_CoreID dstCoreID, T_RpMsg_ChID chID, unsigned int size)
+{
+ return rpmsgCreateChannel(dstCoreID, chID, size);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_oss_icp_regcallback
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) actorID: icp send core id
+ chID: icp channel id
+ callback:icp callback fun
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: int: if msg send success
+* ÆäËü˵Ã÷:
+*******************************************************************************/
+static int ramdump_cap_icp_regcallback (T_RpMsg_CoreID coreID, unsigned int chID, T_RpMsg_Callback callback)
+{
+ return rpmsgRegCallBack(coreID, chID, callback);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init_sysctl_table
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ×¢²ásysctlÃüÁÓû§Ì¬Ê¹ÓÃsysctl¿ØÖÆramdump´æ´¢µØÖ·
+*******************************************************************************/
+void ramdump_init_sysctl_table(void)
+{
+ register_sysctl_table(sysctl_ramdump_table);
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_icp_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump client icp init
+*******************************************************************************/
+static int ramdump_cap_icp_init(void)
+{
+ int ret = 0;
+
+ ret = ramdump_cap_icp_create_channel(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ RAMDUMP_CHANNEL_SIZE);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ ret = ramdump_cap_icp_regcallback(
+ RAMDUMP_SERVER_AP,
+ RAMDUMP_CHANNEL,
+ ramdump_cap_icp_handle);
+
+ if (ret != RAMDUMP_SUCCESS)
+ {
+ return ret;
+ }
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_notify_server_panic
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for cap notify ramdump server to panic
+*******************************************************************************/
+static int ramdump_notify_server_panic(void)
+{
+ int ret = 0;
+ T_RpMsg_Msg rpMsg = {0};
+ ramdump_msg_t ramdumpMsg = {0};
+
+ ramdumpMsg.msg_id = RAMDUMP_MSG_EXCEPT;
+ ramdumpMsg.cpu_id = CORE_AP;
+
+ rpMsg.coreID = RAMDUMP_SERVER_AP;
+ rpMsg.chID = RAMDUMP_CHANNEL;
+ rpMsg.flag = RPMSG_WRITE_INT | RPMSG_WRITE_IRQLOCK;
+ rpMsg.len = sizeof(ramdump_msg_t);
+ rpMsg.buf = &ramdumpMsg;
+
+ ret = rpmsgWrite(&rpMsg);
+ return ret;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_store_ram_conf
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) mem: addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: unsigend char*: changed addr
+* ÆäËü˵Ã÷: This function is used to store ram conf
+*******************************************************************************/
+static unsigned char *ramdump_cap_store_ram_conf(unsigned char *mem)
+{
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_ddr.bin",
+ (unsigned int)DDR_BASE_CAP_ADDR_PA,
+ (unsigned int)(DDR_BASE_CAP_ADDR_PA + *cap_ddr_len_base - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap.cmm",
+ (unsigned int)RAMDUMP_CAP_CMM_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_CMM_BUF_ADDR + RAMDUMP_CAP_CMM_BUF_LEN_REAL - 1));
+ mem += sprintf(
+ mem,
+ "data.load.binary &ramdump_dir\\%s A:0x%x--A:0x%x /noclear\n",
+ "cap_err_log.txt",
+ (unsigned int)RAMDUMP_CAP_LOG_BUF_ADDR,
+ (unsigned int)(RAMDUMP_CAP_LOG_BUF_ADDR + RAMDUMP_CAP_LOG_BUF_LEN - 1));
+ return mem;
+}
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_cap_cmm_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for server to generate cmm scripts
+*******************************************************************************/
+static void ramdump_cap_cmm_create(void)
+{
+ unsigned char *pcmm_buf = ramdump_cap_cmm_buf;
+
+ memset(ramdump_cap_cmm_buf, 0, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+
+ // store the cmm BEGIN
+ pcmm_buf += sprintf(pcmm_buf, "ENTRY &ramdump_dir\n");
+
+ // store procmodes regs
+ pcmm_buf = ramdump_arch_store_modes_regs(pcmm_buf);
+
+ // store ram config
+ pcmm_buf = ramdump_cap_store_ram_conf(pcmm_buf);
+
+ // store memory map control regs
+ pcmm_buf = ramdump_arch_store_mm_regs(pcmm_buf);
+
+ // store end symbol
+ pcmm_buf += sprintf(pcmm_buf, "ENDDO\n");
+
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_trans_cap_error_log_create
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to create err log file
+*******************************************************************************/
+static void ramdump_cap_error_log_create(void)
+{
+ unsigned char *buf = ramdump_cap_error_log;
+
+ memset(ramdump_cap_error_log, 0, RAMDUMP_CAP_LOG_BUF_LEN);
+ buf += sprintf(buf, "dump at core%d,", smp_processor_id());
+ if (current->mm != NULL)
+ buf += sprintf(buf, "in user,task is: %s\n", current->comm);
+ else
+ buf += sprintf(buf, "in kernel,task is: %s\n", current->comm);
+
+ if (ramdump_server_exp_core)
+ buf += sprintf(buf, "recv dumpinfo from ap\n");
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_ram_conf_table_add
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) ram_name: dump ram name
+ ram_start: dump ram start(virtual addr)
+ ram_size: dump ram size
+ ram_virt: dump ram virt addr
+ ram_flag: dump ram flag(copy/exter/callback)
+ ram_extra: dump ram extra access addr
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used to add dump ram conf into public table
+*******************************************************************************/
+void ramdump_ram_conf_table_add(
+ char *ram_name,
+ unsigned long ram_phy,
+ unsigned long ram_size,
+ unsigned long ram_virt,
+ unsigned long ram_flag,
+ unsigned long ram_extra)
+{
+}
+void ramdump_init_cmm_buf(void)
+{
+ /* Cmm file content */
+ ramdump_cap_cmm_buf = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_CMM_BUF_ADDR, RAMDUMP_CAP_CMM_BUF_LEN_REAL);
+ /* err log file */
+ ramdump_cap_error_log = ramdump_phy_to_vir((unsigned long)RAMDUMP_CAP_LOG_BUF_ADDR, RAMDUMP_CAP_LOG_BUF_LEN);
+ cap_ddr_len_base = (unsigned int *)ramdump_phy_to_vir((unsigned long)IRAM_BASE_ADDR_BOOT_DDR, sizeof(unsigned long));
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_init
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: RAMDUMP_SUCCESS or RAMDUMP_FAILED
+* ÆäËü˵Ã÷: This function is used for ramdump init
+*******************************************************************************/
+int __init ramdump_init(void)
+{
+ int ret = 0;
+ ramdump_printf("Ramdump cap init start!!!!!\n");
+
+ if (ramdump_cap_init_flag == RAMDUMP_TRUE)
+ return RAMDUMP_SUCCESS;
+ ramdump_printf("Ramdump cap init rpmsg start!!!!!\n");
+ ret = ramdump_cap_icp_init();
+ if (ret != RAMDUMP_ICP_SUCCESS)
+ return ret;
+
+ ramdump_register_callbacks();
+
+ ramdump_init_cmm_buf();
+
+ ramdump_init_sysctl_table();
+
+ ramdump_shared_mem_init();
+ ramdump_oss_data_trans_init();
+
+ ramdump_printf("Ramdump cap init success!\n");
+ ramdump_cap_init_flag = RAMDUMP_TRUE;
+
+ return RAMDUMP_SUCCESS;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ramdump_entry
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) void
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: This function is used for ramdump entry
+*******************************************************************************/
+void ramdump_entry (void)
+{
+ unsigned long flags;
+ if (sysctl_ramdump_on_panic == false)
+ return;
+
+ /*
+ * we need lock the irq, this can`t be interrupt.
+ */
+ ramdump_irq_lock(flags);
+
+ if (!ramdump_cap_init_flag)
+ while(true); /* endless circle */
+
+ if (++ramdump_count > 1)
+ while(true); /* endless circle */
+
+ /*
+ * save all regs first.
+ */
+ ramdump_arch_save_all_regs();
+ // generate error log
+ ramdump_cap_error_log_create();
+
+ //Éú³Écmm½Å±¾µÄµ¼³öÅäÖÃ
+ ramdump_cap_cmm_create();
+
+ /* notify client ramdump */
+ ramdump_notify_server_panic();
+
+ ramdump_arch_clean_caches();
+ ramdump_export_mode = *(unsigned int *)ramdump_export_flag_base;
+
+ if((ramdump_export_mode == RAMDUMP_MODE_EMMC)
+ || (ramdump_export_mode == RAMDUMP_MODE_SPINAND))
+ ramdump_data_transfer_to_device();
+
+ while(true)
+ ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
new file mode 100755
index 0000000..0c28f27
--- /dev/null
+++ b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.c
@@ -0,0 +1,170 @@
+/**
+ * @file oss_ramdump_osa.c
+ * @brief Implementation of Ramdump os adapt
+ *
+ * Copyright (C) 2017 Sanechips Technology Co., Ltd.
+ * @author Qing Wang <wang.qing@sanechips.com.cn>
+ * @ingroup si_ap_oss_ramdump_id
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/*******************************************************************************
+ * Include header files *
+ ******************************************************************************/
+#include "ramdump.h"
+#include "ramdump_emmc.h"
+#include "ram_config.h"
+#include "ramdump_compress.h"
+#include <linux/lzo.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+* Extern function declarations *
+*******************************************************************************/
+
+/*******************************************************************************
+* Extern variable declarations *
+*******************************************************************************/
+extern unsigned char *ramdump_shared_mem_base;
+extern unsigned char *ramdump_emmc_flag_base;
+extern unsigned int ramdump_compress_flag;
+
+/*******************************************************************************
+ * Macro definitions *
+ ******************************************************************************/
+#define RAMDUMP_DELAY_MS_COUNT (2500)
+
+/*******************************************************************************
+ * Type definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function declarations *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions *
+ ******************************************************************************/
+unsigned int ramdump_emmc_size = 0;
+volatile unsigned int ramdump_emmc_offset = 0;
+extern unsigned int ramdump_device_file_cnt;
+
+/*******************************************************************************
+ * Inline function implementations *
+ ******************************************************************************/
+static inline void ramdump_wait_delay( unsigned long ms)
+{
+ volatile int j = 0;
+ for (j = 0; j < 10000; j++);
+}
+
+/*******************************************************************************
+ * Local function implementations *
+ ******************************************************************************/
+int ramdump_emmc_init(ramdump_file_t *fp)
+{
+ fp->magic = 0x2A2A2A2A;
+ ramdump_emmc_offset = roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE);
+
+ if(RAMDUMP_TRANS_EMMC_LEN > ramdump_emmc_offset)
+ {
+ ramdump_emmc_size = RAMDUMP_TRANS_EMMC_LEN - ramdump_emmc_offset;
+ }
+ else
+ {
+ printk("[ramdump] emmc start addr is %ld, emmc size= %ld, error: size smaller than ramdump file header, return!\n", sysctl_ramdump_emmc_start_addr, sysctl_ramdump_emmc_size);
+ return -1;
+ }
+
+ if(mmc_ramdump_init()){
+ ramdump_printf("EMMC init failed! No ramdump data trans to emmc!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp)
+{
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+ if (ramdump_emmc_offset >= RAMDUMP_TRANS_EMMC_LEN)
+ return -1;
+
+ fp->file_fp[ramdump_device_file_cnt].magic = 0x3A3A3A3A;
+ strncpy(fp->file_fp[ramdump_device_file_cnt].file_name, file_name, RAMDUMP_RAMCONF_FILENAME_MAXLEN - 1);
+ fp->file_fp[ramdump_device_file_cnt].offset = ramdump_emmc_offset;
+ fp->file_fp[ramdump_device_file_cnt].size = file_size;
+ return 0;
+}
+
+int ramdump_emmc_write_file_head(ramdump_file_t *fp)
+{
+ int ret = -1;
+ mmc_bwrite(RAMDUMP_EMMC_ADDR, roundup(sizeof(ramdump_file_t), RAMDUMP_EMMC_ALIGN_SIZE), fp);
+ return ret;
+}
+
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size)
+{
+ int ret = 0;
+ unsigned int buffer = RAMDUMP_EMMC_ADDR + ramdump_emmc_offset;
+
+ if (ramdump_device_file_cnt >= RAMDUMP_FILE_NUM_MAX)
+ return -1;
+
+ while(1){
+ if ((msg->core_flag == 1) && (msg->rw_flag == 2)){
+ if(msg->size >= (ramdump_emmc_size - fp->file_fp[ramdump_device_file_cnt].offset))
+ return -1;
+ ret = mmc_bwrite(buffer, msg->size, msg->buf);
+ ramdump_emmc_offset = ramdump_emmc_offset + roundup(msg->size, RAMDUMP_EMMC_ALIGN_SIZE);
+ msg->core_flag = 1;
+ msg->rw_flag = 1;
+ ret = msg->size;
+ break;
+ }
+ else
+ ramdump_wait_delay(0);
+ }
+ return ret;
+}
+
+int ramdump_emmc_read(char *buffer, ramdump_shmem_t *msg, unsigned int size)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+void ramdump_emmc_close(ramdump_file_t *fp)
+{
+ fp->file_size = ramdump_emmc_offset;
+ ramdump_emmc_write_file_head(fp);
+ ramdump_printf("ramdump trans emmc finished!\n");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
new file mode 100755
index 0000000..1028ab2
--- /dev/null
+++ b/upstream/linux-5.10/kernel/ramdump/ramdump_emmc.h
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* °æȨËùÓÐ (C)2016, ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾¡£
+*
+* ÎļþÃû³Æ: ramdump_emmc.h
+* Îļþ±êʶ: ramdump_emmc.h
+* ÄÚÈÝÕªÒª: ramdump emmcÍ·Îļþ
+* ʹÓ÷½·¨: #include "ramdump_emmc.h"
+*
+* ÐÞ¸ÄÈÕÆÚ °æ±¾ºÅ Ð޸ıê¼Ç ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+* ------------------------------------------------------------------------------
+* 2016/3/10 V1.0 Create ÕÔ¾ü¿ü ´´½¨
+*
+*******************************************************************************/
+
+#ifndef _RAMDUMP_EMMC_H
+#define _RAMDUMP_EMMC_H
+
+/*******************************************************************************
+* Í·Îļþ *
+*******************************************************************************/
+#include "ramdump.h"
+#include <linux/mmc/mmc_func.h>
+
+/*******************************************************************************
+* Íⲿ±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+extern unsigned int sysctl_ramdump_emmc_start_addr;
+extern unsigned int sysctl_ramdump_emmc_size;
+extern volatile unsigned int ramdump_emmc_offset;
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define RAMDUMP_EMMC_ADDR (sysctl_ramdump_emmc_start_addr * 512)
+#define RAMDUMP_TRANS_EMMC_LEN (sysctl_ramdump_emmc_size * 512)
+
+/*******************************************************************************
+* Êý¾ÝÀàÐͶ¨Òå *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ÉùÃ÷ *
+*******************************************************************************/
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+/**
+ * @brief ramdump_emmc_init .
+ *
+ * @param void.
+ *
+ * @return int.
+ * @retval standard error
+ * @note This function is used for ramdump init
+ */
+int ramdump_emmc_init(ramdump_file_t *fp);
+int ramdump_emmc_write_file(char *file_name, unsigned int file_size, ramdump_file_t *fp);
+int ramdump_emmc_write_file_head(ramdump_file_t *fp);
+int ramdump_emmc_modify_file_size(ramdump_file_t *fp, unsigned int file_size);
+int ramdump_emmc_write_data(ramdump_shmem_t *msg, ramdump_file_t *fp, unsigned int size);
+int ramdump_emmc_write_logbuf(ramdump_file_t *fp);
+void ramdump_emmc_close(ramdump_file_t *fp);
+int ramdump_emmc_write_log_txt(ramdump_file_t *fp);
+
+/*******************************************************************************
+* ÄÚÁªº¯ÊýʵÏÖ *
+*******************************************************************************/
+
+#endif //#ifndef _RAMDUMP_EMMC_H
+
diff --git a/upstream/linux-5.10/kernel/tracker.c b/upstream/linux-5.10/kernel/tracker.c
new file mode 100755
index 0000000..6f7e1ab
--- /dev/null
+++ b/upstream/linux-5.10/kernel/tracker.c
@@ -0,0 +1,459 @@
+/*
+ * tracker.c - System accounting over taskstats interface
+ *
+ * Copyright (C) Jay Lan, <jlan@sgi.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <linux/timer.h>
+#include <linux/uaccess.h>
+#include <linux/export.h>
+#include <linux/sched/clock.h>
+#include "ram_config.h"
+
+/*******************************************************************************
+* ºê¶¨Òå *
+*******************************************************************************/
+#define _OS_LINUX 1
+
+#if defined(_OS_TOS)
+# define OS_STATISTIC_IRAM_BASE (IRAM_BASE_ADDR_OS_STATISTIC_PSCPU)
+# define OS_STATISTIC_TIME zDrvTimer_Stamp()
+#elif defined(_OS_LINUX)
+# define OS_STATISTIC_IRAM_BASE g_zxic_trace_apcpu_addr //(IRAM_BASE_ADDR_OS_STATISTIC_APCPU)
+# define OS_STATISTIC_TIME (cpu_clock(0)>>10)
+#else
+# error "unknown os"
+#endif
+
+
+
+#define OS_IRAM_STATISTIC_CNT (5)
+#define OS_IRAM_STATISTIC_NAME_LEN (16)
+#define OS_DDR_STATISTIC_CNT (1000)
+
+#define OS_IRAM_THREAD_SWAPIN (OS_STATISTIC_IRAM_BASE)
+#define OS_IRAM_IRQ_START (OS_IRAM_THREAD_SWAPIN + sizeof(t_os_iram_thread_statistic))
+#define OS_IRAM_IRQ_END (OS_IRAM_IRQ_START + sizeof(t_os_iram_statistic))
+
+#if defined(_OS_TOS)
+#define OS_IRAM_DSR_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_DSR_END (OS_IRAM_DSR_START + sizeof(t_os_iram_statistic))
+#elif defined(_OS_LINUX)
+#define OS_IRAM_SOFTIRQ_START (OS_IRAM_IRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_SOFTIRQ_END (OS_IRAM_SOFTIRQ_START + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_START (OS_IRAM_SOFTIRQ_END + sizeof(t_os_iram_statistic))
+#define OS_IRAM_TIMER_END (OS_IRAM_TIMER_START + sizeof(t_os_iram_statistic))
+#endif
+
+#define os_statistic_check() *((volatile unsigned long *)OS_STATISTIC_IRAM_BASE)
+#define os_statistic_enabled() g_os_statistic_enable
+
+/*******************************************************************************
+* Êý¾Ý½á¹¹¶¨Òå *
+*******************************************************************************/
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned char name[OS_IRAM_STATISTIC_NAME_LEN];
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_thread_statistic;
+
+typedef volatile struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_IRAM_STATISTIC_CNT];
+}t_os_iram_statistic;
+
+typedef struct {
+ unsigned int cnt;
+ unsigned int index;
+ struct {
+ unsigned int data1;
+ unsigned int data2;
+ } statistics[OS_DDR_STATISTIC_CNT];
+}t_os_ddr_statistic;
+
+/*******************************************************************************
+* È«¾Ö±äÁ¿ *
+*******************************************************************************/
+#if defined(_OS_LINUX)
+volatile static char *g_zxic_trace_apcpu_addr;
+#endif
+
+volatile static int g_os_statistic_enable;
+volatile static unsigned int g_os_statistic_cnt;
+
+volatile static t_os_iram_thread_statistic *g_os_iram_swapin_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_iram_statistic *g_os_iram_dsr_start_statistic;
+static t_os_iram_statistic *g_os_iram_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_iram_statistic *g_os_iram_softirq_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_softirq_end_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_start_statistic;
+volatile static t_os_iram_statistic *g_os_iram_timer_end_statistic;
+#endif
+
+volatile static t_os_ddr_statistic *g_os_ddr_swapin_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_irq_end_statistic;
+
+#if defined(_OS_TOS)
+static t_os_ddr_statistic *g_os_ddr_dsr_start_statistic;
+static t_os_ddr_statistic *g_os_ddr_dsr_end_statistic;
+#elif defined(_OS_LINUX)
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_softirq_end_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_start_statistic;
+volatile static t_os_ddr_statistic *g_os_ddr_timer_end_statistic;
+#endif
+
+/*******************************************************************************
+* È«¾Öº¯ÊýÉùÃ÷ *
+*******************************************************************************/
+void os_statistic_enable(void);
+/*******************************************************************************
+* ¾Ö²¿º¯Êý *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_statistic *iram;
+
+ iram = (t_os_iram_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+ iram->statistics[index].data1 = (unsigned int)data;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: Ï̹߳켣ͳ¼Æµ½IRAM
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_thread_in_iram(volatile void *iram_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_iram_thread_statistic *iram;
+
+ iram = (t_os_iram_thread_statistic *)iram_addr;
+
+ index = iram->index;
+ if(index >= OS_IRAM_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+
+#if defined(_OS_TOS)
+ strncpy((char *)(iram->statistics[index].name), cyg_thread_get_name((cyg_handle_t)data), OS_IRAM_STATISTIC_NAME_LEN - 1);
+#elif defined(_OS_LINUX)
+ strncpy((char *)(iram->statistics[index].name), ((struct task_struct *)data)->comm, OS_IRAM_STATISTIC_NAME_LEN - 1);
+#else
+# error "unkown os"
+#endif
+ iram->statistics[index].name[OS_IRAM_STATISTIC_NAME_LEN - 1] = 0;
+ iram->statistics[index].data2 = time;
+ index++;
+
+ iram->index = index;
+ iram->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_in_ddr(void *ddr_addr, void *data, unsigned long time)
+{
+ unsigned long index;
+ t_os_ddr_statistic *ddr;
+
+ ddr = (t_os_ddr_statistic *)ddr_addr;
+
+ index = ddr->index;
+ if (index >= OS_DDR_STATISTIC_CNT)
+ {
+ index = 0;
+ }
+ ddr->statistics[index].data1 = (unsigned int)data;
+ ddr->statistics[index].data2 = time;
+ index++;
+
+ ddr->index = index;
+ ddr->cnt = g_os_statistic_cnt;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static inline void os_statistic_info_update(void)
+{
+ g_os_statistic_cnt++;
+}
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¶¨Ê±Æ÷»Øµ÷¹³×Ó
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý)
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+static int os_statistic_delayed_work_timer_fn(unsigned long data)
+{
+ int sec = 0;
+ msleep(20000);
+ while(!os_statistic_check())
+ {
+ //³¬¹ý40s£¬Ö±½ÓÍ˳ö
+ if(sec >= 4)
+ return 0;
+ msleep(10000);
+ sec++;
+ }
+ os_statistic_enable();
+ return 0;
+}
+
+/*******************************************************************************
+* È«¾Öº¯ÊýʵÏÖ *
+*******************************************************************************/
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ʹÄܹ켣ͳ¼Æ¹¦ÄÜ
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) address: ¼Ç¼µ½IRAMÖеĵØÖ·
+ size: IRAM¿Õ¼ä´óС
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+void os_statistic_enable(void)
+{
+#if defined(_OS_TOS)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_dsr_start_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_START;
+ g_os_iram_dsr_end_statistic = (t_os_iram_statistic *)OS_IRAM_DSR_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_start_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+ g_os_ddr_dsr_end_statistic = (t_os_ddr_statistic *)zOss_Malloc(sizeof(t_os_ddr_statistic));
+#elif defined(_OS_LINUX)
+ g_os_iram_swapin_statistic = (t_os_iram_thread_statistic *)OS_IRAM_THREAD_SWAPIN;
+ g_os_iram_irq_start_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_START;
+ g_os_iram_irq_end_statistic = (t_os_iram_statistic *)OS_IRAM_IRQ_END;
+ g_os_iram_softirq_start_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_START;
+ g_os_iram_softirq_end_statistic = (t_os_iram_statistic *)OS_IRAM_SOFTIRQ_END;
+ g_os_iram_timer_start_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_START;
+ g_os_iram_timer_end_statistic = (t_os_iram_statistic *)OS_IRAM_TIMER_END;
+
+ g_os_ddr_swapin_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_irq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_softirq_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_start_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+ g_os_ddr_timer_end_statistic = (t_os_ddr_statistic *)kmalloc(sizeof(t_os_ddr_statistic), GFP_KERNEL);
+
+#else
+# error "unkown os"
+#endif
+ if ((unsigned int )g_os_iram_timer_end_statistic - (unsigned int )g_os_iram_swapin_statistic > (unsigned int )IRAM_BASE_LEN_OS_STATISTIC_PSCPU )
+ {
+ BUG();
+ }
+ g_os_statistic_enable = 1;
+}
+EXPORT_SYMBOL(os_statistic_enable);
+
+void zxic_trace_task_switch(struct task_struct *next)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_thread_in_iram(g_os_iram_swapin_statistic, next, time);
+ os_statistic_in_ddr(g_os_ddr_swapin_statistic, next, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_enter(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_start_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_start_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_irq_exit(u32 irq)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_irq_end_statistic, irq, time);
+ os_statistic_in_ddr(g_os_ddr_irq_end_statistic, irq, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_enter(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_start_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_start_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_softirq_exit(u32 vec_nr)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_softirq_end_statistic, vec_nr, time);
+ os_statistic_in_ddr(g_os_ddr_softirq_end_statistic, vec_nr, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_enter(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_start_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_start_statistic, func, time);
+ os_statistic_info_update();
+}
+
+void zxic_trace_timer_exit(void *func)
+{
+ unsigned long time;
+ if (!g_os_statistic_enable)
+ return ;
+
+ time = OS_STATISTIC_TIME;
+ os_statistic_in_iram(g_os_iram_timer_end_statistic, func, time);
+ os_statistic_in_ddr(g_os_ddr_timer_end_statistic, func, time);
+ os_statistic_info_update();
+}
+
+
+/*******************************************************************************
+* ¹¦ÄÜÃèÊö: ¹ì¼£Í³¼Æµ½DDR
+* ²ÎÊý˵Ã÷:
+* (´«Èë²ÎÊý) iram_addr: µØÖ·
+ data: ʼþÏî
+ time: ʱ¼ä
+* (´«³ö²ÎÊý) void
+* ·µ »Ø Öµ: void
+* ÆäËü˵Ã÷: ÎÞ
+*******************************************************************************/
+int __init zxic_enable_tracer(void)
+{
+ struct timer_list timer;
+ struct task_struct *task;
+
+#ifdef IRAM_BASE_ADDR_VA
+ g_zxic_trace_apcpu_addr = IRAM_BASE_ADDR_OS_STATISTIC_PSCPU;
+#else
+ g_zxic_trace_apcpu_addr = ioremap(IRAM_BASE_ADDR_OS_STATISTIC_PSCPU, IRAM_BASE_LEN_OS_STATISTIC_PSCPU);
+#endif
+
+ /*
+ init_timer(&timer);
+ timer.expires = jiffies + 40*HZ;//msecs_to_jiffies(40*1000);//ÑÓ³Ù40Ãë
+ timer.data = 0;
+ timer.function = os_statistic_delayed_work_timer_fn;
+ setup_timer(&timer, os_statistic_delayed_work_timer_fn, 0);
+ add_timer(&timer);
+ */
+ //task = kthread_create(os_statistic_delayed_work_timer_fn, 0, "g_zxic_trace_sync_thread", 0);
+ //wake_up_process(task);
+ os_statistic_enable();
+ return 0x0;
+}
+module_init(zxic_enable_tracer);
+
+
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
new file mode 100755
index 0000000..f730067
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_ak4940.c
@@ -0,0 +1,2041 @@
+/*
+ * zx297520v3_es8312.c -- zx29-ak4940 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/ak4940.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0xac
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ak4940_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "ak4940.1-0012",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, voice_platform),
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, ak4940_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940_codec, dummy),
+
+},
+
+#if 0
+
+ [AUDIO_DL_MEDIA] = {
+ .name = "ak4940",
+ .stream_name = "MultiMedia",
+ .nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, ak4940, media_platform),
+ },
+
+ [AUDIO_DL_VOICE] = {
+
+ .name = "voice_call",
+ .stream_name = "voice",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ },
+ [AUDIO_DL_2G_AND_3G_VOICE] = {
+
+ .name = "voice_2g_3g",
+ .stream_name = "voice_2g_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice_2g_3g, ak4940, voice_audio),
+
+ },
+ [AUDIO_DL_VP_LOOP] = {
+
+ .name = "loop_test",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "snd-soc-dummy",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops2,
+ SND_SOC_DAILINK_REG(voice, ak4940, dummy),
+
+ }, .stream_name = "loop_voice",
+
+ [AUDIO_DL_3G_VOICE] = {
+
+ .name = "voice_3g", // 3g nb,wb
+ .stream_name = "voice_3g",
+ //.codec_name = "es8312.1-0018",
+ //.codec_dai_name = "ES8312 HiFi",
+ //.cpu_dai_name = "voice", //"snd-soc-dummy-dai",
+ //.platform_name = "voice_audio",
+ .init = zx29_init_paiftx,
+ .ops = &zx29_ops1,
+ SND_SOC_DAILINK_REG(voice, ak4940, voice_audio),
+
+ }
+#endif
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ak4940_of_match[] = {
+ { .compatible = "zxic,zx29_ak4940", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ak4940_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<15);
+ val |= 0x1<<15;; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+
+ val &= 0xfffffff8;
+ val |= 0x00000001;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ak4940_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_ak4940";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_ak4940",
+ .of_match_table = of_match_ptr(zx29_ak4940_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ak4940");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
new file mode 100755
index 0000000..1a8cf3e
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_dummycodec.c
@@ -0,0 +1,1346 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-dummycodec ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_AK4940_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+};
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_AK4940_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+ unsigned int armRegBit = 0;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x1;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+ u32 armRegBit;
+ //armRegBit = zx_read_reg(AON_WIFI_BT_CLK_CFG2);
+ //armRegBit &= 0xfffffffe;
+ //armRegBit |= 0x0;
+ //zx_write_reg(AON_WIFI_BT_CLK_CFG2, armRegBit);
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ //if (ret < 0){
+ // print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ // return ret;
+ // }
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ //.startup = zx29_startup,
+ //.shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ak4940",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ak4940_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ak4940 */
+#define ZX29_AK4940_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ak4940_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ak4940, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ak4940.1-0012", "ak4940-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(ti3100_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0012", "tlv320aic31xx-hifi")));
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("E1D02000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+
+
+
+
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ //.init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, dummy_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_dummycodec_of_match[] = {
+ { .compatible = "zxic,zx29_dummycodec", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_dummycodec_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+
+
+
+}
+
+
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+ board->name = "zx29_dummycodec";
+ board->dev = &pdev->dev;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_dummycodec_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ //platform_set_drvdata(pdev, board);
+
+
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_dummycodec",
+ .of_match_table = of_match_ptr(zx29_dummycodec_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-dummycodec");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
new file mode 100755
index 0000000..ea874ee
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_max9867.c
@@ -0,0 +1,2012 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/max9867.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define CODEC_CLK_ID 0
+#define CODEC_SCLK_MCLK_ID 0
+#define CODEC_SCLK_PLL_ID 1
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, CODEC_SCLK_MCLK_ID, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+#if 0
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, CODEC_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+#endif
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ #if 0
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+ #endif
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(max9867_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("max9867.1-001a", "max9867-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, max9867_codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, max9867_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_max9867_of_match[] = {
+ { .compatible = "zxic,zx29_max9867", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_max9867_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p,*p2;
+ struct pinctrl_state *s,*s2;
+ int ret = 0;
+ printk("%s start n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s0 end!\n", __func__);
+ /*
+ p2 = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+ */
+
+ s2 = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ ret = pinctrl_select_state(p, s2);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set i2s1 end!\n", __func__);
+
+
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_max9867_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_max9867";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static void zx29_audio_shutdown(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ;
+}
+static int zx29_audio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ int ret;
+ struct device *dev = &pdev->dev;
+
+
+ dev_info(&pdev->dev,"%s:zx29_max9867 end!\n",__func__);
+
+ return ret;
+}
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_max9867",
+ .of_match_table = of_match_ptr(zx29_max9867_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ .shutdown = zx29_audio_shutdown,
+ .suspend = zx29_audio_suspend,
+ .resume = zx29_audio_resume,
+};
+
+
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-max9867");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
new file mode 100755
index 0000000..1e5777d
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_nau8810.c
@@ -0,0 +1,2325 @@
+/*
+ * zx297520v3_nau8810.c -- zx297520v3-nau8810 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/nau8810.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+#define NAU_CLK_ID 0
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZXIC_MCLK,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+ /* Set the Codec DAI clk */
+ ret =snd_soc_dai_set_pll(codec_dai, 0, NAU8810_SCLK_PLL,
+ ZXIC_MCLK, params_rate(params)*256);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+ static int zx29_hw_params_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ //frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_104M, SND_SOC_CLOCK_IN);
+
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_122M88, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice_tdm(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ //ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_PLL, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, NAU8810_SCLK_MCLK, params_rate(params)*256, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+
+
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_tdm,
+#else
+ .hw_params = zx29_hw_params,
+#endif
+
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_lp_tdm,
+#else
+ .hw_params = zx29_hw_params_lp,
+#endif
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+#ifdef CONFIG_USE_TOP_TDM
+ .hw_params = zx29_hw_params_voice_tdm,
+#else
+ .hw_params = zx29_hw_params_voice,
+#endif
+
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx29_nau8810",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to nau8810 */
+#define ZX29_CODEC_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_codec_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+SND_SOC_DAILINK_DEF(cpu_tdm, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1412000.tdm")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(nau8810, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-0012", "nau8810-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+SND_SOC_DAILINK_DEF(nau8810_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("nau8810.1-001a", "nau8810-hifi")));
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+
+ SND_SOC_DAILINK_DEF(media_platform_tdm, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1412000.tdm")));
+
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, dummy_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+#endif
+
+},
+#if 1
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+#ifdef CONFIG_USE_TOP_TDM
+ SND_SOC_DAILINK_REG(cpu_tdm, nau8810_codec, media_platform_tdm),
+#else
+ SND_SOC_DAILINK_REG(cpu_i2s0, nau8810_codec, media_platform),
+#endif
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, nau8810_codec, dummy),
+
+},
+#endif
+
+};
+
+
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_nau8810_of_match[] = {
+ { .compatible = "zxic,zx29_nau8810", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_nau8810_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ struct pinctrl_state *s_sleep;
+ int ret = 0;
+ printk("%s start \n",__func__);
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: board name(%s)!\n", __func__,info->name);
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#if defined(CONFIG_USE_TOP_I2S0)
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#elif defined(CONFIG_USE_TOP_I2S1)//defined(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+#if defined(CONFIG_USE_TOP_I2S0)
+ dev_info(dev, "%s: top_i2s0 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+
+
+#elif defined(CONFIG_USE_TOP_I2S1)
+ dev_info(dev, "%s: top_i2s1 pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s1");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s1_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#elif defined(CONFIG_USE_TOP_TDM)
+ dev_info(dev, "%s: top_tdm pinctrl sel!!\n", __func__);
+ s = pinctrl_lookup_state(p, "top_tdm");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "toptdm_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#else
+ dev_info(dev, "%s: default top_i2s pinctrl sel!!\n", __func__);
+
+ s = pinctrl_lookup_state(p, "top_i2s0");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+ dev_info(dev, "%s: get top_i2s sleep pinctrl sel!!\n", __func__);
+
+ s_sleep = pinctrl_lookup_state(p, "topi2s0_sleep");
+ if (IS_ERR(s_sleep)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+
+#endif
+ if(info != NULL){
+
+ info->p = p;
+ info->s = s;
+ info->s_sleep = s_sleep;
+ }
+
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+/*
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+*/
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_nau8810_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+ board->name = "zx29_nau8810";
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+
+#ifdef CONFIG_PM
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(&pdev->dev);
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(&pdev->dev);
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_sleep_state(dev);
+ if((info->p != NULL)&&(info->s_sleep != NULL)){
+ ret = pinctrl_select_state(info->p, info->s_sleep);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl sleep end!\n", __func__);
+ }
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+ int ret = 0;
+ struct zx29_board_data *info = s_board;
+
+ pr_info("%s: start!\n",__func__);
+
+ //pinctrl_pm_select_default_state(dev);
+ if((info->p != NULL)&&(info->s != NULL)){
+ ret = pinctrl_select_state(info->p, info->s);
+ if (ret < 0) {
+ //devm_pinctrl_put(info->p);
+ dev_err(dev, " select state failure!!\n");
+ //return;
+ }
+ dev_info(dev, "%s: set pinctrl active end!\n", __func__);
+ }
+
+
+ return snd_soc_resume(dev);
+
+}
+
+#else
+static int zx29_audio_suspend(struct platform_device * pdev, pm_message_t state)
+{
+
+ return 0;
+}
+
+static int zx29_audio_resume(struct platform_device *pdev)
+{
+
+
+ return 0;
+}
+
+int zx29_snd_soc_suspend(struct device *dev)
+{
+
+
+ return snd_soc_suspend(dev);
+
+}
+int zx29_snd_soc_resume(struct device *dev)
+{
+
+
+ return snd_soc_resume(dev);
+
+}
+
+
+#endif
+
+
+struct dev_pm_ops zx29_snd_soc_pm_ops = {
+ .suspend = zx29_snd_soc_suspend,
+ .resume = zx29_snd_soc_resume,
+ .freeze = snd_soc_suspend,
+ .thaw = snd_soc_resume,
+ .poweroff = snd_soc_poweroff,
+ .restore = snd_soc_resume,
+};
+
+
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+ .name = "zx29_nau8810",
+ .of_match_table = of_match_ptr(zx29_nau8810_of_match),
+ //.pm = &snd_soc_pm_ops,
+ .pm = &zx29_snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_nau8810_snd_device, &zx29xx_nau8810, sizeof(zx29xx_nau8810));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-nau8810");
diff --git a/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c b/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
new file mode 100755
index 0000000..9959350
--- /dev/null
+++ b/upstream/linux-5.10/sound/soc/sanechips/zx29_ti3100.c
@@ -0,0 +1,2011 @@
+/*
+ * zx297520v3_es8312.c -- zx298501-ti3100 ALSA SoC Audio board driver
+ *
+ * Copyright (C) 2022, ZTE Corporation.
+ *
+ * Based on smdk_wm8994.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "../codecs/tlv320aic31xx.h"
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+
+
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+//#include <sound/tlv.h>
+//#include <sound/soc.h>
+//#include <sound/jack.h>
+//#include <sound/zx29_snd_platform.h>
+//#include <mach/iomap.h>
+//#include <mach/board.h>
+#include <linux/of_gpio.h>
+
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+
+
+#include "i2s.h"
+
+#define ZX29_I2S_TOP_LOOP_REG 0x60
+
+
+#if 1
+
+#define ZXIC_MCLK 26000000
+#define ZX29_TI3100_FREQ 26000000
+
+#define ZXIC_PLL_CLKIN_MCLK 0
+
+
+#define zx_reg_sync_write(v, a) \
+ do { \
+ iowrite32(v, a); \
+ } while (0)
+
+#define zx_read_reg(addr) \
+ ioread32(addr)
+
+#define zx_write_reg(addr, val) \
+ zx_reg_sync_write(val, addr)
+
+
+
+struct zx29_board_data {
+ const char *name;
+ struct device *dev;
+
+ int codec_refclk;
+ int gpio_pwen;
+ int gpio_pdn;
+ void __iomem *sys_base_va;
+
+};
+
+
+struct zx29_board_data *s_board = 0;
+
+//#define AON_WIFI_BT_CLK_CFG2 ((volatile unsigned int *)(ZX_TOP_CRM_BASE + 0x94))
+ /* Default ZX29s */
+static struct zx29_board_data zx29_platform_data = {
+ .codec_refclk = ZX29_TI3100_FREQ,
+};
+ static struct platform_device *zx29_snd_device;
+
+ static DEFINE_RAW_SPINLOCK(codec_pa_lock);
+
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol);
+
+
+#ifdef USE_ALSA_VOICE_FUNC
+ extern int zDrv_Audio_Printf(void *pFormat, ...);
+ extern int zDrvVp_GetVol_Wrap(void);
+ extern int zDrvVp_SetVol_Wrap(int volume);
+ extern int zDrvVp_GetPath_Wrap(void);
+ extern int zDrvVp_SetPath_Wrap(int path);
+ extern int zDrvVp_SetMute_Wrap(bool enable);
+ extern bool zDrvVp_GetMute_Wrap(void);
+ extern int zDrvVp_SetTone_Wrap(int toneNum);
+
+ static int vp_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetVol(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+ static int audio_GetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+ static int audio_SetPath(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
+
+
+ //static const DECLARE_TLV_DB_SCALE(vp_path_tlv, 0, 300, 0);
+
+ static const char * const vpath_in_text[] = {
+ "handset", "speak", "headset", "bluetooth",
+ };
+
+ static const char *tone_class[] = {
+ "Lowpower", "Sms", "Callstd", "Alarm", "Calltime",
+ };
+
+ static const struct soc_enum vpath_in_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vpath_in_text), vpath_in_text);
+
+ static const struct soc_enum tone_class_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tone_class), tone_class),
+ };
+
+ static const struct snd_kcontrol_new vp_snd_controls[] = {
+ SOC_ENUM_EXT("voice processing path select",vpath_in_enum,vp_GetPath,vp_SetPath),
+ //SOC_SINGLE_EXT_TLV("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol,vp_path_tlv),
+ SOC_SINGLE_EXT("voice processing path Volume",0, 5, 5, 0,vp_GetVol, vp_SetVol),
+ SOC_SINGLE_EXT("voice uplink mute", 0, 1, 1, 0,vp_GetMute, vp_SetMute),
+ SOC_ENUM_EXT("voice tone sel", tone_class_enum[0], vp_getTone, vp_SetTone),
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ SOC_ENUM_EXT("audio path select",vpath_in_enum,audio_GetPath,audio_SetPath),
+ };
+
+ static int curtonetype = 0;
+ static int vp_getTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.integer.value[0] = curtonetype;
+ return 0;
+ }
+
+ static int vp_SetTone(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0, tonenum;
+ tonenum = ucontrol->value.integer.value[0];
+ curtonetype = tonenum;
+ //printk("Alsa vp_SetTone tonenum=%d\n", tonenum);
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetTone_Wrap)(tonenum);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetTone fail = %d\n", tonenum);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ int enable = 0,ret = 0;
+ enable = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetMute_Wrap)(enable);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetMute fail = %d\n",enable);
+ return ret;
+ }
+ return 0;
+ }
+
+ static int vp_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetMute_Wrap)();
+ return 0;
+ }
+
+ static int vp_SetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int vol = 0,ret = 0;
+ vol = ucontrol->value.integer.value[0];
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetVol_Wrap)(vol);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetVol fail = %d\n",vol);
+ return ret;
+ }
+ return 0;
+ }
+ static int vp_GetVol(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.integer.value[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetVol_Wrap)();
+ return 0;
+ }
+ static int vp_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //ucontrol->value.enumerated.item[0] = CPPS_FUNC(cpps_callbacks, zDrvVp_GetPath_Wrap)();
+ return 0;
+ }
+ static int vp_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+ path = ucontrol->value.enumerated.item[0];
+
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_SetPath_Wrap)(path);
+ if(ret < 0)
+ {
+ printk(KERN_ERR "vp_SetPath fail = %d\n",path);
+ return ret;
+ }
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ static int curpath = 0;
+ static int audio_GetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ ucontrol->value.enumerated.item[0] = curpath;
+ return 0;
+ }
+
+ static int audio_SetPath(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ int ret = 0,path = 0;
+ unsigned long flags;
+
+ path = ucontrol->value.enumerated.item[0];
+ curpath = path;
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ switch (path) {
+ case 0:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+ break;
+ case 1:
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_39, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_40, GPIO_HIGH);
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default:
+ break;
+ }
+#endif
+ return 0;
+ }
+
+ typedef enum
+ {
+ VP_PATH_HANDSET =0,
+ VP_PATH_SPEAKER,
+ VP_PATH_HEADSET,
+ VP_PATH_BLUETOOTH,
+ VP_PATH_BLUETOOTH_NO_NR,
+ VP_PATH_HSANDSPK,
+
+ VP_PATH_OFF = 255,
+
+ MAX_VP_PATH = VP_PATH_OFF
+ }T_ZDrv_VpPath;
+
+ extern int zDrvVp_Loop(T_ZDrv_VpPath path);
+
+
+//#else
+ static const struct snd_kcontrol_new machine_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("path stauts dump", 0,get_path_stauts_switch, set_path_stauts_switch),
+ };
+
+
+
+ //extern int rt5670_hs_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
+
+ int path_stauts_switch = 0;
+ static int set_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_path *p;
+
+ int path_stauts_switch = ucontrol->value.integer.value[0];
+
+
+ if (path_stauts_switch == 1)
+ {
+ list_for_each_entry(p, &card->paths, list){
+
+ //print_audio("Alsa path name (%s),longname (%s),sink (%s),source (%s),connect %d \n", p->name,p->long_name,p->sink->name,p->source->name,p->connect);
+ //printk("Alsa path longname %s,sink %s,source %s,connect %d \n", p->long_name,p->sink->name,p->source->name,p->connect);
+
+ }
+ }
+ return 0;
+ }
+
+ static int get_path_stauts_switch(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+
+ ucontrol->value.integer.value[0] = path_stauts_switch;
+ return 0;
+ };
+#endif
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ static struct snd_soc_jack codec_headset;
+
+ /* Headset jack detection DAPM pins */
+ static struct snd_soc_jack_pin codec_headset_pins[] = {
+ {
+ .pin = "Headphone",
+ .mask = SND_JACK_HEADPHONE,
+ },
+ };
+
+#endif
+
+
+
+
+
+ static int zx29startup(struct snd_pcm_substream *substream)
+ {
+ // int ret = 0;
+ print_audio("Alsa Entered func %s\n", __func__);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_startup device=%d,stream=%d\n", substream->pcm->device, substream->stream);
+
+ struct snd_pcm *pcmC0D0p = snd_lookup_minor_data(16, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D1p = snd_lookup_minor_data(17, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D2p = snd_lookup_minor_data(18, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ struct snd_pcm *pcmC0D3p = snd_lookup_minor_data(19, SNDRV_DEVICE_TYPE_PCM_PLAYBACK);
+ if ((pcmC0D0p == NULL) || (pcmC0D1p == NULL) || (pcmC0D2p == NULL) || (pcmC0D3p == NULL))
+ return -EINVAL;
+ if ((pcmC0D0p->streams[0].substream_opened && pcmC0D1p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D0p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D2p->streams[0].substream_opened) ||
+ (pcmC0D1p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened) ||
+ (pcmC0D2p->streams[0].substream_opened && pcmC0D3p->streams[0].substream_opened))
+ BUG();
+#if 0
+ unsigned long flags;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ mdelay(1);
+
+ raw_spin_lock_irqsave(&codec_pa_lock, flags);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_LOW);
+ udelay(2);
+ gpio_set_value(ZX29_GPIO_125, GPIO_HIGH);
+ raw_spin_unlock_irqrestore(&codec_pa_lock, flags);
+ }
+#endif
+
+
+ return 0;
+ }
+
+ static void zx29_shutdown(struct snd_pcm_substream *substream)
+ {
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx297520xx_shutdown device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ // print_audio("Alsa Entered func %s, stream=%d\n", __func__, substream->stream);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+
+ }
+
+ static void zx29_shutdown2(struct snd_pcm_substream *substream)
+ {
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ //CPPS_FUNC(cpps_callbacks, zDrv_Audio_Printf)("Alsa: zx29_shutdown2 device=%d, stream=%d\n", substream->pcm->device, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ gpio_set_value(ZX29_GPIO_39, GPIO_LOW);
+ mdelay(1);
+ gpio_set_value(ZX29_GPIO_40, GPIO_LOW);
+#endif
+#ifdef USE_ALSA_VOICE_FUNC
+ //CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_OFF);
+#endif
+
+
+ }
+
+ if (snd_soc_dai_active(cpu_dai))
+ return;
+
+
+ }
+ static int zx29_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+ {
+ //struct snd_soc_codec *codec = rtd->codec;
+ //struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ //snd_soc_dapm_enable_pin(dapm, "HPOL");
+ //snd_soc_dapm_enable_pin(dapm, "HPOR");
+
+ /* Other pins NC */
+ // snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+
+ // print_audio("Alsa Entered func %s\n", __func__);
+
+ return 0;
+ }
+ static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+ //ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+static int zx29_hw_params_lp(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ /*
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+
+
+ /* Set the AP DAI configuration */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: ap dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /*
+ ret = snd_soc_dai_set_sysclk(codec_dai, ES8312_CLKID_MCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ */
+ /* Set the AP DAI clk */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, ZX29_I2S_WCLK_SEL,ZX29_I2S_WCLK_FREQ_26M, SND_SOC_CLOCK_IN);
+
+ if (ret < 0){
+ print_audio("Alsa: cpu dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+}
+
+
+
+
+
+
+ static int zx29_hw_params_voice(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+ {
+ print_audio("Alsa: Entered func %s\n", __func__);
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
+ struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
+
+ int ret;
+ int rfs = 0, frq_out = 0;
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 11025:
+ case 22050:
+ case 24000:
+ case 32000:
+ case 44100:
+ case 48000:
+ rfs = 32;
+ break;
+ default:
+ {
+ ret = -EINVAL;
+ print_audio("Alsa: rate=%d not support,ret=%d!\n", params_rate(params),ret);
+ return ret;
+ }
+ }
+
+ frq_out = params_rate(params) * rfs * 2;
+
+ /* Set the Codec DAI configuration */
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S
+ | SND_SOC_DAIFMT_NB_NF
+ | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai snd_soc_dai_set_fmt fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AIC31XX_PLL_CLKIN_MCLK, ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ /* Set the Codec DAI clk */
+ /*ret =snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_BCLK1,
+ fs*datawidth*2, 256*fs);
+ if (ret < 0){
+
+ print_audio("Alsa: codec dai clk snd_soc_dai_set_pll fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_CLKID_BCLK,ZXIC_MCLK, SND_SOC_CLOCK_IN);
+ if (ret < 0){
+ print_audio("Alsa: codec dai snd_soc_dai_set_sysclk fail,ret=%d!\n",ret);
+ return ret;
+ }
+
+ */
+
+ print_audio("Alsa: Entered func %s end\n", __func__);
+
+ return 0;
+ }
+
+
+ int zx29_prepare2(struct snd_pcm_substream *substream)
+ {
+ int path, ret;
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ //ret = CPPS_FUNC(cpps_callbacks, zDrvVp_Loop)(VP_PATH_SPEAKER);
+ if (ret < 0)
+ return -1;
+ }
+
+ return 0;
+ }
+ static void zx29_i2s_top_reg_cfg(void)
+ {
+ unsigned int i2s_top_reg;
+ int ret = 0;
+
+#ifdef CONFIG_USE_PIN_I2S0
+ ret = gpio_request(PIN_I2S0_WS, "i2s0_ws");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_CLK, "i2s0_clk");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DIN, "i2s0_din");
+ if (ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S0_DOUT, "i2s0_dout");
+ if (ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S0_WS, FUN_I2S0_WS);
+ zx29_gpio_config(PIN_I2S0_CLK, FUN_I2S0_CLK);
+ zx29_gpio_config(PIN_I2S0_DIN, FUN_I2S0_DIN);
+ zx29_gpio_config(PIN_I2S0_DOUT, FUN_I2S0_DOUT);
+
+ //top i2s1 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfffffff8;
+ i2s_top_reg |= 0x00000001; // inter arm_i2s1--top i2s1
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#elif defined (CONFIG_USE_PIN_I2S1)
+
+
+ ret = gpio_request(PIN_I2S1_WS,"i2s1_ws");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_CLK,"i2s1_clk");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DIN,"i2s1_din");
+ if(ret < 0)
+ BUG();
+ ret = gpio_request(PIN_I2S1_DOUT,"i2s1_dout");
+ if(ret < 0)
+ BUG();
+ zx29_gpio_config(PIN_I2S1_WS, FUN_I2S1_WS);
+ zx29_gpio_config(PIN_I2S1_CLK, FUN_I2S1_CLK);
+ zx29_gpio_config(PIN_I2S1_DIN, FUN_I2S1_DIN);
+ zx29_gpio_config(PIN_I2S1_DOUT, FUN_I2S1_DOUT);
+
+ //top i2s2 cfg
+ i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ i2s_top_reg &= 0xfff8ffff;
+ i2s_top_reg |= 0x00010000; // inter arm_i2s1--top i2s2
+ zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+#endif
+
+ // inter loop
+ //i2s_top_reg = zx_read_reg(ZX29_I2S_LOOP_CFG);
+ //i2s_top_reg &= 0xfffffe07;
+ //i2s_top_reg |= 0x000000a8; // inter arm_i2s2--afe i2s
+ //zx_write_reg(ZX29_I2S_LOOP_CFG, i2s_top_reg);
+
+ // print_audio("Alsa %s i2s loop cfg reg=%x\n",__func__, zx_read_reg(ZX29_I2S_LOOP_CFG));
+ }
+
+ static int zx29_late_probe(struct snd_soc_card *card)
+ {
+ //struct snd_soc_codec *codec = card->rtd[0].codec;
+ //struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+ int ret;
+ // print_audio("Alsa zx29_late_probe entry!\n");
+
+#ifdef CONFIG_SND_SOC_JACK_DECTEC
+
+ ret = snd_soc_jack_new(codec, "Headset",
+ SND_JACK_HEADSET |SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2,
+ &codec_headset);
+ if (ret)
+ return ret;
+
+ ret = snd_soc_jack_add_pins(&codec_headset,
+ ARRAY_SIZE(codec_headset_pins),
+ codec_headset_pins);
+ if (ret)
+ return ret;
+ #ifdef CONFIG_SND_SOC_codec
+ //rt5670_hs_detect(codec, &codec_headset);
+ #endif
+#endif
+
+ return 0;
+ }
+
+ static struct snd_soc_ops zx29_ops = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params,
+ };
+ static struct snd_soc_ops zx29_ops_lp = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ .hw_params = zx29_hw_params_lp,
+ };
+ static struct snd_soc_ops zx29_ops1 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown,
+ //.hw_params = zx29_hw_params1,
+ };
+
+ static struct snd_soc_ops zx29_ops2 = {
+ //.startup = zx29_startup,
+ .shutdown = zx29_shutdown2,
+ //.hw_params = zx29_hw_params1,
+ .prepare = zx29_prepare2,
+ };
+ static struct snd_soc_ops voice_ops = {
+ .startup = zx29startup,
+ .shutdown = zx29_shutdown2,
+ .hw_params = zx29_hw_params_voice,
+ //.prepare = zx29_prepare2,
+ };
+
+
+ enum {
+ MERR_DPCM_AUDIO = 0,
+ MERR_DPCM_DEEP_BUFFER,
+ MERR_DPCM_COMPR,
+ };
+
+
+#if 0
+
+ static struct snd_soc_card zxic_soc_card = {
+ .name = "zx298501_ti3100",
+ .owner = THIS_MODULE,
+ .dai_link = &zxic_dai_link,
+ .num_links = ARRAY_SIZE(zxic_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+
+ // .late_probe = zx29_late_probe,
+
+ };
+#endif
+ //static struct zx298501_ti3100_pdata *zx29_platform_data;
+
+ static int zx29_setup_pins(struct zx29_board_data *codec_pins, char *fun)
+ {
+ int ret;
+
+ //ret = gpio_request(codec_pins->codec_refclk, "codec_refclk");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: %s pin already in use\n", fun);
+ return ret;
+ }
+ //zx29_gpio_config(codec_pins->codec_refclk, GPIO17_CLK_OUT2);
+
+#ifdef _USE_7520V3_PHONE_TYPE_C31F
+ ret = gpio_request_one(ZX29_GPIO_39, GPIOF_OUT_INIT_LOW, "codec_pa");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_pa in use\n");
+ return ret;
+ }
+
+ ret = gpio_request_one(ZX29_GPIO_40, GPIOF_OUT_INIT_LOW, "codec_sw");
+ if (ret < 0) {
+ printk(KERN_ERR "zx297520xx SoC Audio: codec_sw in use\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+ }
+#endif
+
+
+ static int zx29_remove(struct platform_device *pdev)
+ {
+ gpio_free(zx29_platform_data.codec_refclk);
+ platform_device_unregister(zx29_snd_device);
+ return 0;
+ }
+
+
+
+#if 0
+
+ /*
+ * Default CFG switch settings to use this driver:
+ * ZX29
+ */
+
+ /*
+ * Configure audio route as :-
+ * $ amixer sset 'DAC1' on,on
+ * $ amixer sset 'Right Headphone Mux' 'DAC'
+ * $ amixer sset 'Left Headphone Mux' 'DAC'
+ * $ amixer sset 'DAC1R Mixer AIF1.1' on
+ * $ amixer sset 'DAC1L Mixer AIF1.1' on
+ * $ amixer sset 'IN2L' on
+ * $ amixer sset 'IN2L PGA IN2LN' on
+ * $ amixer sset 'MIXINL IN2L' on
+ * $ amixer sset 'AIF1ADC1L Mixer ADC/DMIC' on
+ * $ amixer sset 'IN2R' on
+ * $ amixer sset 'IN2R PGA IN2RN' on
+ * $ amixer sset 'MIXINR IN2R' on
+ * $ amixer sset 'AIF1ADC1R Mixer ADC/DMIC' on
+ */
+
+/* ZX29 has a 16.934MHZ crystal attached to ti3100 */
+#define ZX29_TI3100_FREQ 16934000
+
+
+
+
+
+static int zx29_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ unsigned int pll_out;
+ int ret;
+
+ /* AIF1CLK should be >=3MHz for optimal performance */
+ if (params_width(params) == 24)
+ pll_out = params_rate(params) * 384;
+ else if (params_rate(params) == 8000 || params_rate(params) == 11025)
+ pll_out = params_rate(params) * 512;
+ else
+ pll_out = params_rate(params) * 256;
+
+ ret = snd_soc_dai_set_pll(codec_dai, AK4940_FLL1, AK4940_FLL_SRC_MCLK1,
+ ZX29_AK4940_FREQ, pll_out);
+ if (ret < 0)
+ return ret;
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, AK4940_SYSCLK_FLL1,
+ pll_out, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * ZX29 AK4940 DAI operations.
+ */
+static struct snd_soc_ops zx29_ops = {
+ .hw_params = smdk_hw_params,
+};
+
+static int zx29_ti3100_init_paiftx(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_dapm_context *dapm = &rtd->card->dapm;
+
+ /* Other pins NC */
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "HPOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLN");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTLP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRP");
+ snd_soc_dapm_nc_pin(dapm, "SPKOUTRN");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT1P");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2N");
+ snd_soc_dapm_nc_pin(dapm, "LINEOUT2P");
+ snd_soc_dapm_nc_pin(dapm, "IN1LP");
+ snd_soc_dapm_nc_pin(dapm, "IN2LP:VXRN");
+ snd_soc_dapm_nc_pin(dapm, "IN1RP");
+ snd_soc_dapm_nc_pin(dapm, "IN2RP:VXRP");
+
+ return 0;
+}
+#endif
+
+
+
+
+enum {
+ AUDIO_DL_MEDIA = 0,
+ AUDIO_DL_VOICE,
+ AUDIO_DL_2G_AND_3G_VOICE,
+ AUDIO_DL_VP_LOOP,
+ AUDIO_DL_3G_VOICE,
+
+ AUDIO_DL_MAX,
+};
+SND_SOC_DAILINK_DEF(dummy, \
+ DAILINK_COMP_ARRAY(COMP_DUMMY()));
+
+//SND_SOC_DAILINK_DEF(cpu_i2s0, \
+// DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
+SND_SOC_DAILINK_DEF(cpu_i2s0, \
+ DAILINK_COMP_ARRAY(COMP_CPU("1405000.i2s")));
+
+
+SND_SOC_DAILINK_DEF(voice_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:voice_audio")));
+
+SND_SOC_DAILINK_DEF(voice_2g_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_2g_3g-dai")));
+
+SND_SOC_DAILINK_DEF(voice_3g, \
+ DAILINK_COMP_ARRAY(COMP_CPU("voice_3g-dai")));
+
+
+
+//SND_SOC_DAILINK_DEF(ti3100, \
+// DAILINK_COMP_ARRAY(COMP_CODEC("ti3100.1-0012", "ti3100-aif")));
+SND_SOC_DAILINK_DEF(dummy_cpu, \
+ DAILINK_COMP_ARRAY(COMP_CPU("soc:zx29_snd_dummy")));
+//SND_SOC_DAILINK_DEF(dummy_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:zx29_snd_dummy")));
+
+SND_SOC_DAILINK_DEF(dummy_codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("soc:zx29_snd_dummy", "zx29_snd_dummy_dai")));
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic3x-codec.1-0018", "tlv320aic3x-hifi")));
+
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+#else
+
+SND_SOC_DAILINK_DEF(codec, \
+ DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic31xx-codec.1-0018", "tlv320aic31xx-hifi")));
+
+#endif
+
+
+//SND_SOC_DAILINK_DEF(media_platform, \
+// DAILINK_COMP_ARRAY(COMP_PLATFORM("zx29-pcm-audio")));
+SND_SOC_DAILINK_DEF(media_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("1405000.i2s")));
+//SND_SOC_DAILINK_DEF(voice_cpu, \
+// DAILINK_COMP_ARRAY(COMP_CPU("E1D02000.i2s")));
+
+SND_SOC_DAILINK_DEF(voice_platform, \
+ DAILINK_COMP_ARRAY(COMP_PLATFORM("soc:voice_audio")));
+
+
+//static struct snd_soc_dai_link zx29_dai_link[] = {
+struct snd_soc_dai_link zx29_dai_link[] = {
+ {
+ .name = "zx29_snd_dummy",//codec name
+ .stream_name = "zx29_snd_dumy",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops_lp,
+ .init = zx29_init_paiftx,
+ SND_SOC_DAILINK_REG(cpu_i2s0, dummy_codec, media_platform),
+
+},
+{
+ .name = "media",//codec name
+ .stream_name = "MultiMedia",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &zx29_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(cpu_i2s0, codec, media_platform),
+
+},
+{
+ .name = "voice",//codec name
+ .stream_name = "voice",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+{
+ .name = "voice_2g3g_teak",//codec name
+ .stream_name = "voice_2g3g_teak",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "voice_3g",//codec name
+ .stream_name = "voice_3g",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ SND_SOC_DAILINK_REG(voice_cpu, codec, voice_platform),
+
+},
+
+{
+ .name = "loop_test",//codec name
+ .stream_name = "loop_test",
+ //.nonatomic = true,
+ //.dynamic = 1,
+ //.dpcm_playback = 1,
+ //.ops = &zx29_ops,
+ .ops = &voice_ops,
+
+ .init = zx29_init_paiftx,
+
+
+ //SND_SOC_DAILINK_REG(cpu_i2s0, codec, dummy),
+ SND_SOC_DAILINK_REG(voice_cpu, codec, dummy),
+
+},
+
+};
+
+
+
+static struct snd_soc_card zx29_soc_card = {
+ .name = "zx29-sound-card",
+ .owner = THIS_MODULE,
+ .dai_link = zx29_dai_link,
+ .num_links = ARRAY_SIZE(zx29_dai_link),
+#ifdef USE_ALSA_VOICE_FUNC
+ .controls = vp_snd_controls,
+ .num_controls = ARRAY_SIZE(vp_snd_controls),
+#endif
+};
+
+static const struct of_device_id zx29_ti3100_of_match[] = {
+ { .compatible = "zxic,zx29_ti3100", .data = &zx29_platform_data },
+ { .compatible = "zxic,zx29_ti3104", .data = &zx29_platform_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, zx29_ti3100_of_match);
+
+static void zx29_i2s_top_pin_cfg(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pinctrl *p;
+ struct pinctrl_state *s;
+ int ret = 0;
+
+
+ struct resource *res;
+ void __iomem *reg_base;
+ unsigned int val;
+
+
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "soc_sys");
+ if (!res) {
+ dev_err(dev, "Reg region missing (%s)\n", "soc_sys");
+ //return -ENXIO;
+ }
+
+ #if 0
+ reg_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reg_base )) {
+ dev_err(dev, "Reg region ioremap (%s) err=%li\n", "soc_sys",PTR_ERR(reg_base ));
+ //return PTR_ERR(reg_base );
+ }
+
+ #else
+ reg_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ #endif
+
+//#if 1 //CONFIG_USE_PIN_I2S0
+#ifdef CONFIG_USE_TOP_I2S0
+
+ dev_info(dev, "%s: arm i2s1 to top i2s0!!\n", __func__);
+ //9300
+
+ //top i2s1 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ val &= ~(0x7<<0);
+ val |= 0x1<<0; // inter arm_i2s1--top i2s1
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#else //(CONFIG_USE_PIN_I2S1)
+ //8501evb
+
+ dev_info(dev, "%s: arm i2s1 to top i2s1!\n", __func__);
+
+ //top i2s2 cfg
+ val = zx_read_reg(reg_base+ZX29_I2S_TOP_LOOP_REG);
+ //val &= 0xfffffff8;
+ val &= ~(0x7<<16);
+ val |= 0x1<<16;// inter arm_i2s1--top i2s2
+ zx_write_reg(reg_base+ZX29_I2S_TOP_LOOP_REG, val);
+#endif
+
+ p = devm_pinctrl_get(dev);
+ if (IS_ERR(p)) {
+ dev_err(dev, "%s: pinctrl get failure ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+ return;
+ }
+
+ dev_info(dev, "%s: get pinctrl ,p=0x%llx,dev=0x%llx!!\n", __func__,p,dev);
+
+ s = pinctrl_lookup_state(p, "top_i2s");
+ if (IS_ERR(s)) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " get state failure!!\n");
+ return;
+ }
+ ret = pinctrl_select_state(p, s);
+ if (ret < 0) {
+ devm_pinctrl_put(p);
+ dev_err(dev, " select state failure!!\n");
+ return;
+ }
+ dev_info(dev, "%s: set pinctrl end!\n", __func__);
+
+}
+#if 0
+static int codec_power_on(struct zx29_board_data * board,bool on_off)
+{
+ int ret = 0;
+ //struct zx29_board_data *board = dev_get_drvdata(dev);
+ struct device *dev = board->dev;
+
+ dev_info(dev, "%s:start %s board gpio_pwen=%d,gpio_pdn=%d on_off=%d\n",__func__,board->name,board->gpio_pwen,board->gpio_pdn,on_off);
+
+ if(on_off){
+
+ ret = gpio_direction_output(board->gpio_pwen, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 1: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 1);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 1: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+ else{
+ ret = gpio_direction_output(board->gpio_pwen, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen %d direction fail set to 0: %d\n",board->gpio_pwen, ret);
+ return ret;
+ }
+
+ ret = gpio_direction_output(board->gpio_pdn, 0);
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn %d direction fail set to 0: %d\n",board->gpio_pdn, ret);
+ return ret;
+ }
+
+
+ }
+
+ return ret;
+
+}
+#endif
+
+
+#ifdef CONFIG_PA_SA51034
+//sa51034
+#define SA51034_DEBUG
+
+#define SA51034_01_LATCHED_FAULT 0x01
+#define SA51034_02_STATUS_LOAD_DIAGNOSTIC 0x02
+#define SA51034_03_CONTROL 0x03
+#define SA51034_MAX_REGISTER SA51034_03_CONTROL
+
+struct sa51034_priv {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ int pwen_gpio;//add new
+ int mute_gpio;
+ int fs;
+
+};
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute);
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute);
+
+
+
+
+struct sa51034_priv *g_sa51034 = NULL;
+/* ak4940 register cache & default register settings */
+static const struct reg_default sa51034_reg[] = {
+ { 0x01, 0x00 }, /* SA51034_00_LATCHED_FAULT */
+ { 0x02, 0x00 }, /* SA51034_01_STATUS_LOAD_DIAGNOSTIC */
+ { 0x03, 0x00 }, /* SA51034_02_CONTROL */
+
+};
+
+static const char * const pa_gain_select_texts[] = {
+ "20dB", "26dB","30dB", "36dB",
+};
+static const char * const power_limit_select_texts[] = {
+ "PL-5V", "PL-5.9V","PL-7V", "PL-8.4V","PL-9.8V", "PL-11.8V","PL-14V", "PL-disV",
+};
+
+static const struct soc_enum pa_gain_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 6,
+ ARRAY_SIZE(pa_gain_select_texts), pa_gain_select_texts),
+};
+static const struct soc_enum power_limit_enum[] = {
+ SOC_ENUM_SINGLE(SA51034_03_CONTROL, 3,
+ ARRAY_SIZE(power_limit_select_texts), power_limit_select_texts),
+};
+
+static const char * const reg_select[] = {
+ "read PA Reg 01:03",
+};
+
+static const struct soc_enum pa_enum2[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(reg_select),reg_select),
+};
+
+static int get_reg(
+ struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+ u32 currMode = ucontrol->value.enumerated.item[0];
+ int i, ret;
+ int regs, rege;
+ unsigned int value;
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+ component = snd_soc_lookup_component(dev, NULL);
+ regs = 0x1;
+ rege = 0x4;
+
+ for (i = regs; i < rege; i++) {
+ value = snd_soc_component_read(component, i);
+ if (value < 0) {
+ pr_err("pa %s(%d),err value=%d\n", __func__, __LINE__, value);
+ return value;
+ }
+ pr_info("pa 2c_read Addr,Reg=(%x, %x)\n", i, value);
+ }
+
+ return 0;
+}
+
+
+
+ int pa_get_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+
+
+
+
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int val, item;
+ unsigned int reg_val;
+ int ret;
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+
+
+ component = snd_soc_lookup_component(dev, NULL);
+ reg_val = snd_soc_component_read(component, e->reg);
+
+
+ if (reg_val < 0) {
+ pr_err("pa %s(%d),err reg_val=%d\n", __func__, __LINE__, reg_val);
+ return reg_val;
+ }
+
+
+ val = (reg_val >> e->shift_l) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[0] = item;
+ if (e->shift_l != e->shift_r) {
+ val = (reg_val >> e->shift_r) & e->mask;
+ item = snd_soc_enum_val_to_item(e, val);
+ ucontrol->value.enumerated.item[1] = item;
+ }
+
+ return 0;
+ }
+
+ int pa_put_enum_double(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+ {
+ //struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+
+ struct snd_soc_component *component;
+ struct device *dev;
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ unsigned int *item = ucontrol->value.enumerated.item;
+ unsigned int val;
+ unsigned int mask;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ dev = &g_sa51034->i2c->dev;
+ component = snd_soc_lookup_component(dev, NULL);
+
+ if (item[0] >= e->items)
+ return -EINVAL;
+ val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
+ mask = e->mask << e->shift_l;
+ if (e->shift_l != e->shift_r) {
+ if (item[1] >= e->items)
+ return -EINVAL;
+ val |= snd_soc_enum_item_to_val(e, item[1]) << e->shift_r;
+ mask |= e->mask << e->shift_r;
+ }
+
+ return snd_soc_component_update_bits(component, e->reg, mask, val);
+ }
+
+
+static int pa_SetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ mute = ucontrol->value.integer.value[0];
+ ret = sa51034_set_mute(g_sa51034,mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_set_mute fail ret=%d,mute=%d\n",ret,mute);
+ return ret;
+ }
+ return 0;
+}
+
+static int pa_GetMute(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+ int mute = 0,ret = 0;
+
+ if(g_sa51034 == NULL){
+ pr_err("g_sa51034 null return %s\n", __func__);
+ return -1;
+ }
+ ret = sa51034_get_mute(g_sa51034,&mute);
+
+ if(ret < 0)
+ {
+ printk(KERN_ERR "sa51034_get_mute fail ret= %d\n",ret);
+ return ret;
+ }
+ pr_info("[SA51034] %s mute gpio val=%d,integer.value[0]=%d\n", __func__, mute,ucontrol->value.integer.value[0]);
+
+ ucontrol->value.integer.value[0] = mute;
+
+ return 0;
+}
+
+
+
+
+
+const struct snd_kcontrol_new pa_controls[] =
+{
+ SOC_ENUM_EXT("PA gain", pa_gain_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("Power limit", power_limit_enum[0], pa_get_enum_double, pa_put_enum_double),
+ SOC_ENUM_EXT("PA Reg Read", pa_enum2[0], get_reg, NULL),
+ SOC_SINGLE_EXT("pa mute", 0, 0, 1, 0,pa_GetMute, pa_SetMute),
+
+
+};
+
+int pa_controls_size = sizeof(pa_controls) / sizeof(pa_controls[0]);
+
+
+
+
+static bool sa51034_volatile(struct device *dev, unsigned int reg)
+{
+ bool ret;
+
+#ifdef SA51034_DEBUG
+ ret = true;
+#else
+ ret = false;
+#endif
+
+ return ret;
+}
+
+static bool sa51034_readable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+static bool sa51034_writeable(struct device *dev, unsigned int reg)
+{
+ if (reg <= SA51034_MAX_REGISTER)
+ return true;
+ else
+ return false;
+}
+
+
+static const struct regmap_config sa51034_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = SA51034_MAX_REGISTER,
+ .volatile_reg = sa51034_volatile,
+ .writeable_reg = sa51034_writeable,
+ .readable_reg = sa51034_readable,
+
+ .reg_defaults = sa51034_reg,
+ .num_reg_defaults = ARRAY_SIZE(sa51034_reg),
+ .cache_type = REGCACHE_RBTREE,
+
+};
+
+static const struct snd_soc_component_driver pa_asoc_component = {
+ .name = "pa_component",
+
+
+ //.controls = pa_controls,
+ //.num_controls = ARRAY_SIZE(pa_controls),
+
+
+};
+
+static const struct of_device_id sa51034_i2c_dt_ids[] = {
+ { .compatible = "sa51034"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, sa51034_i2c_dt_ids);
+static int sa51034_gpio_request(struct sa51034_priv *sa51034)
+{
+ struct device *dev;
+ struct device_node *np;
+ int ret;
+ dev = &(sa51034->i2c->dev);
+
+ np = dev->of_node;
+
+ if (!np)
+ return 0;
+
+ pr_info( "Read PDN pin from device tree\n");
+
+
+ sa51034->pwen_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 0);
+ if (sa51034->pwen_gpio < 0) {
+ pr_err( "sa51034 pwen pin of_get_named_gpio fail\n");
+
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->pwen_gpio)) {
+ pr_err( "sa51034 pwen_gpio pin(%u) is invalid\n", sa51034->pwen_gpio);
+ sa51034->pwen_gpio = -1;
+ return -1;
+ }
+ sa51034->mute_gpio = of_get_named_gpio(np, "sa51034,ctrl-gpio", 1);
+ if (sa51034->mute_gpio < 0) {
+
+ pr_err( "sa51034 mute_gpio pin of_get_named_gpio fail\n");
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+ if (!gpio_is_valid(sa51034->mute_gpio)) {
+ pr_err( "sa51034 mute_gpio pin(%u) is invalid\n", sa51034->mute_gpio);
+ sa51034->mute_gpio = -1;
+ return -1;
+ }
+
+
+ pr_info( "sa51034 get pwen_gpio pin(%u) mute_gpio pin(%u)\n", sa51034->pwen_gpio,sa51034->mute_gpio);
+
+ if (sa51034->pwen_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->pwen_gpio, "sa51034 pwen");
+ if (ret < 0){
+ pr_err( "sa51034 pwen_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+ pr_info("\t[sa51034] %s :pwen_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->pwen_gpio, 0);
+ }
+
+
+ if (sa51034->mute_gpio != -1) {
+ ret = devm_gpio_request(dev,sa51034->mute_gpio, "sa51034 mute");
+ if (ret < 0){
+ pr_err( "sa51034 mute_gpio request fail,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("\t[AK4940] %s : mute_gpio gpio_request ret = %d\n", __func__, ret);
+ gpio_direction_output(sa51034->mute_gpio, 1);
+ }
+
+
+ return 0;
+}
+
+static int sa51034_set_mute(struct sa51034_priv *sa51034,int mute)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("[SA51034] %s mute=%d\n", __func__, mute);
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ //ndt = 4080000 / sa51034->fs;
+ if (mute) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->mute_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->mute_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+static int sa51034_get_mute(struct sa51034_priv *sa51034,int *mute)
+{
+
+ int ret = 0;
+ if (sa51034->mute_gpio == -1) {
+ pr_err( "sa51034 %s mute_gpio invalid return\n",__func__);
+ return -1;
+ }
+
+ *mute = gpio_get_value(sa51034->mute_gpio);
+ pr_info("[SA51034] %s mute gpio val=%d\n", __func__, *mute);
+
+ return ret;
+}
+
+static int sa51034_set_pwen(struct sa51034_priv *sa51034,int en)
+{
+ //struct snd_soc_component *component = dai->component;
+ //struct ak4940_priv *ak4940 = snd_soc_component_get_drvdata(component);
+ int ret = 0;
+ //int ndt;
+
+ pr_info("\t[SA51034] %s en[%s]\n", __func__, en ? "ON":"OFF");
+ if (sa51034->pwen_gpio == -1) {
+ pr_err( "sa51034 %s pwen_gpio invalid return\n",__func__);
+ return -1;
+ }
+ //ndt = 4080000 / sa51034->fs;
+ if (en) {
+ /* SMUTE: 1 , MUTE */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 1);
+ //mdelay(ndt);
+ } else{
+ /* SMUTE: 0 ,NORMAL operation */
+ ret = gpio_direction_output(sa51034->pwen_gpio, 0);
+ //mdelay(ndt);
+ }
+ return ret;
+}
+
+
+
+static int sa51034_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct sa51034_priv *sa51034;
+ int ret = 0;
+ unsigned int val;
+
+ pr_info("\t[sa51034] %s(%d),i2c->addr=0x%x\n", __func__, __LINE__,i2c->addr);
+
+ sa51034 = devm_kzalloc(&i2c->dev, sizeof(struct sa51034_priv), GFP_KERNEL);
+ if (sa51034 == NULL)
+ return -ENOMEM;
+
+
+ sa51034->regmap = devm_regmap_init_i2c(i2c, &sa51034_regmap);
+
+ if (IS_ERR(sa51034->regmap)) {
+ devm_kfree(&i2c->dev, sa51034);
+ return PTR_ERR(sa51034->regmap);
+ }
+
+
+ i2c_set_clientdata(i2c, sa51034);
+ sa51034->i2c = i2c;
+ ret = devm_snd_soc_register_component(&i2c->dev, &pa_asoc_component,
+ NULL, 0);
+ if (ret) {
+ pr_err( "pa component register failed,ret=%d\n",ret);
+ return ret;
+ }
+
+ pr_info("[sa51034] %s(%d) pa component register end,ret=0x%x\n", __func__, __LINE__,ret);
+
+ sa51034_gpio_request(sa51034);
+
+
+ sa51034_set_pwen(sa51034,1);
+
+ //sa51034_set_mute(sa51034,0);
+
+ g_sa51034 = sa51034;
+
+
+ pr_info("\t[sa51034] %s end\n", __func__);
+ return ret;
+}
+
+static const struct i2c_device_id sa51034_i2c_id[] = {
+
+ { "sa51034", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, sa51034_i2c_id);
+
+static struct i2c_driver sa51034_i2c_driver = {
+ .driver = {
+ .name = "sa51034",
+ .of_match_table = of_match_ptr(sa51034_i2c_dt_ids),
+ },
+ .probe = sa51034_i2c_probe,
+ //.remove = sa51034_i2c_remove,
+ .id_table = sa51034_i2c_id,
+};
+
+static int sa51034_init(void)
+{
+ pr_info("\t[sa51034] %s(%d)\n", __func__, __LINE__);
+
+ return i2c_add_driver(&sa51034_i2c_driver);
+}
+
+#endif
+static int zx29_audio_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct device_node *np = pdev->dev.of_node;
+ struct snd_soc_card *card = &zx29_soc_card;
+ struct zx29_board_data *board;
+ const struct of_device_id *id;
+ enum of_gpio_flags flags;
+ unsigned int idx;
+
+ struct device *dev = &pdev->dev;
+ dev_info(&pdev->dev,"zx29_audio_probe start!\n");
+
+ card->dev = &pdev->dev;
+
+ board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL);
+ if (!board)
+ return -ENOMEM;
+
+ if (np) {
+ zx29_dai_link[0].cpus->dai_name = NULL;
+ zx29_dai_link[0].cpus->of_node = of_parse_phandle(np,
+ "zxic,i2s-controller", 0);
+ if (!zx29_dai_link[0].cpus->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,i2s-controller' missing or invalid\n");
+ ret = -EINVAL;
+ }
+
+ zx29_dai_link[0].platforms->name = NULL;
+ zx29_dai_link[0].platforms->of_node = zx29_dai_link[0].cpus->of_node;
+
+
+#if 0
+ zx29_dai_link[0].codecs->of_node = of_parse_phandle(np,
+ "zxic,audio-codec", 0);
+ if (!zx29_dai_link[0].codecs->of_node) {
+ dev_err(&pdev->dev,
+ "Property 'zxic,audio-codec' missing or invalid\n");
+ return -EINVAL;
+ }
+#endif
+ }
+
+
+
+
+
+
+ id = of_match_device(of_match_ptr(zx29_ti3100_of_match), &pdev->dev);
+ if (id)
+ *board = *((struct zx29_board_data *)id->data);
+
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ board->name = "zx29_ti3104";
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ board->name = "zx29_ti3100";
+#else
+ board->name = "zx29_ti3100";
+
+#endif
+ board->dev = &pdev->dev;
+
+ //platform_set_drvdata(pdev, board);
+ s_board = board;
+
+
+#if 0
+
+ board->gpio_pwen = of_get_gpio_flags(dev->of_node, 0, &flags);
+ if (!gpio_is_valid(board->gpio_pwen)) {
+ dev_err(dev," gpio_pwen no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pwen=0x%x flags = %d\n",board->gpio_pwen,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pwen, "codec_pwen");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pwen request error.\n");
+ return ret;
+
+ }
+
+ board->gpio_pdn = of_get_gpio_flags(dev->of_node, 1, &flags);
+ if (!gpio_is_valid(board->gpio_pdn)) {
+ dev_err(dev," gpio_pdn no found\n");
+ return -EBUSY;
+ }
+ dev_info(dev, "board->gpio_pdn=0x%x flags = %d\n",board->gpio_pdn,flags);
+ ret = devm_gpio_request(&pdev->dev,board->gpio_pdn, "codec_pdn");
+ if (ret < 0) {
+ dev_err(dev,"gpio_pdn request error.\n");
+ return ret;
+
+ }
+#endif
+
+ ret = devm_snd_soc_register_card(&pdev->dev, card);
+
+ if (ret){
+ dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
+ return ret;
+ }
+ zx29_i2s_top_pin_cfg(pdev);
+
+
+ //codec_power_on(board,1);
+#ifdef CONFIG_PA_SA51034
+
+ dev_info(&pdev->dev,"zx29_audio_probe start sa51034_init!\n");
+
+ ret = sa51034_init();
+ if (ret != 0) {
+
+ pr_err("sa51034_init Failed to register I2C driver: %d\n", ret);
+ //return ret;
+
+ }
+ else{
+
+ for (idx = 0; idx < ARRAY_SIZE(pa_controls); idx++) {
+ ret = snd_ctl_add(card->snd_card,
+ snd_ctl_new1(&pa_controls[idx],
+ NULL));
+ if (ret < 0){
+ return ret;
+ }
+ }
+
+ }
+ ret = 0;
+
+#endif
+ dev_info(&pdev->dev,"zx29_audio_probe end!\n");
+
+ return ret;
+}
+
+static struct platform_driver zx29_platform_driver = {
+ .driver = {
+#if defined(CONFIG_SND_SOC_ZX29_TI3104)
+ .name = "zx29_ti3104",
+#elif defined(CONFIG_SND_SOC_ZX29_TI3100)
+ .name = "zx29_ti3100",
+#else
+ .name = "zx29_ti3100",
+
+#endif
+ .of_match_table = of_match_ptr(zx29_ti3100_of_match),
+ .pm = &snd_soc_pm_ops,
+ },
+ .probe = zx29_audio_probe,
+ //.remove = zx29_remove,
+};
+
+
+#if 0
+static int zx29_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ print_audio("Alsa zx297520xx SoC Audio driver\n");
+
+ zx29_platform_data = pdev->dev.platform_data;
+ if (zx29_platform_data == NULL) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: unable to find platform data\n");
+ return -ENODEV;
+ }
+
+ if (zx297520xx_setup_pins(zx29_platform_data, "codec") < 0)
+ return -EBUSY;
+
+ zx29_i2s_top_reg_cfg();
+
+ zx29_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!zx29_snd_device) {
+ printk(KERN_ERR "Alsa zx297520xx SoC Audio: Unable to register\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(zx29_snd_device, &zxic_soc_card);
+// platform_device_add_data(zx29xx_ti3100_snd_device, &zx29xx_ti3100, sizeof(zx29xx_ti3100));
+ ret = platform_device_add(zx29_snd_device);
+ if (ret) {
+ printk(KERN_ERR "Alsa zx29 SoC Audio: Unable to add\n");
+ platform_device_put(zx29_snd_device);
+ }
+
+ return ret;
+}
+#endif
+
+
+
+module_platform_driver(zx29_platform_driver);
+
+MODULE_DESCRIPTION("zx29 ALSA SoC audio driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:zx29-audio-ti3100");
diff --git a/upstream/pub/include/ps_phy/psevent.h b/upstream/pub/include/ps_phy/psevent.h
new file mode 100755
index 0000000..d1fbdf8
--- /dev/null
+++ b/upstream/pub/include/ps_phy/psevent.h
@@ -0,0 +1,5172 @@
+/*****************************************************************************
+ *°æ±¾ËùÓÐ (C)2007ÖÐÐËͨѶ¹É·ÝÓÐÏÞ¹«Ë¾
+ * Ä£¿éÃû £ºPUB
+ * ÎļþÃû £ºpsEvent.h
+ * Îļþ±êʶ£º
+ * Ïà¹ØÎļþ£º
+ * ʵÏÖ¹¦ÄÜ£ºÐÒéÕ»Èí¼þʼþºÅ¶¨Òå
+ * ×÷Õß £º
+ * °æ±¾ £º
+ * Íê³ÉÈÕÆÚ£º
+ * ÆäËü˵Ã÷£º
+ *
+ * Ð޸ļǼºÅ ÈÕÆÚ ÐÞ¸ÄÈË ÐÞ¸ÄÄÚÈÝ
+ 1 2008.02.23 ½ºè 1)ÐÒéÕ»ÐèÒªºÍCOMNEON´úÂ뻥ͨ£¬ÆäʼþºÅ¶¨ÒåΪ16λ¡£¹ÊÏÞÖÆÐÒéջʼþºÅÓÐЧ·¶Î§ÎªµÍ16λ¡£
+ 2 2008.05.14 ½ºè 1)Ôö¼ÓÁËSCIÓëURRC/CCÖ®¼äµÄʼþºÅ¶¨Òå
+ 3 2008.05.15 ½ºè 1)Ôö¼ÓÁËCCÓëURRC¼äµÄʼþºÅ¶¨Òå:GMMAS_CALLTYPENOTIFYREQ_EV
+ 4 2008.05.19 ½ºè 1Ôö¼ÓTAFÓëL1G¼äµÄʼþºÅ¶¨Òå
+ 5 2008.05.29 ½ºè 1)Ôö¼ÓGSM²âÊÔÄ£¿é¼äʼþºÅ
+ 6 2008.06.05 ½ºè 1)Ôö¼ÓGVAR_SCI_GETREQ_EV¡¢GVAR_SCI_GETCNF_EV¡¢CSCI_CONFIGREL_EV
+ 7 2008.06.12 ½ºè 1)Ôö¼ÓATIÓëCSD¼äµÄʼþºÅ¶¨Òå
+ 8 2008.06.12 ½ºè 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁË£º
+ LLGMM_USERDATAPRESENT_EV;
+ GMMAS_ASSIGNREQ_EV¡¢GMMAS_INFOREQ_EV¡¢GMMAS_SUSPENDIND_EV
+ CPDI_SENDDATAIND_EV£»
+ SM_PDCP_RATACTIND_EV¡¢SM_PDCP_RATACTRSP_EV¡¢SM_PDCP_RATDEACTIND_EV¡¢
+ SM_PDCP_RATSEQIND_EV¡¢SM_PDCP_RATSEQRSP_EV¡¢SM_PDCP_READYIND_EV£»
+ SNSM_RATDEACTRSP_EV£»
+ UMMAS_PLMNLISTREJ_EV¡¢UMMAS_PCHPRE_REQ¡¢UMMAS_ABORTHPPLMNREQ_EV¡¢
+ UMMAS_UPDATEPARAMREQ_EV¡¢UMMAS_INACTIVEREQ_EV¡¢UMMAS_INACTIVECNF_EV¡¢
+ UMMAS_RATCHNIND_EV¡¢UMMAS_HOSTARTIND_EV¡¢UMMAS_CCOSTARTIND_EV
+ 9 2008.06.14 ½ºè 1)Ôö¼ÓTOOL_NGMAC_PMO_REQ_EV¡¢TOOL_NGMAC_PSI_REQ_EV¶¨Òå
+ 2)¸üÃû£ºUMMAS_PCHPRE_REQ £½¡·UMMAS_PCHPREREQ_EV
+ 10 2008.06.16 ËïÒÔÀ× 1)Ôö¼ÓSNDCP-SMÖ®¼äʼþºÅ
+ 2)Ôö¼ÓGSMA²âÊÔʼþºÅ:GVAR_GSMA_GETREQ_EV¡¢GVAR_GSMA_GETCNF_EV
+ 11 2008.06.17 ÕÅÅô³Ì 1)Ϊ֧³ÖË«Ä££¬Ôö¼ÓÁËURRC-GRR¡¢URRCÄÚ²¿¡¢URRC-PHYÖ®¼äʼþºÅ
+ 12 2008.06.18 ÕÅÅô³Ì 1)Ôö¼ÓUMMAS_TRYHPPLMNCNF_EV
+ 13 2008.06.18 ½ºè 1)ÐÞ¸ÄÁËURRC-GRRÖ®¼äʼþºÅÃû³Æ
+ 14 2008.06.19 ÍõÀò 1)Ôö¼ÓSNSM_READYIND_EV,ɾ³ýSNSM_RATDEACTRSP_EV
+ 15 2008.06.20 ËïȪ 1)Ôö¼ÓTOOL_L1SIMU_DCCHFAIL_CFG_EV
+ 16 2008.06.20 ÕÅÅô³Ì 1)Ôö¼ÓURRCGRR_CAMPONCELLCNF_EV¡¢URRCGRR_CAMPONCELLIND_EV
+ 17 2008.06.30 Ç®¿¡ 1)Ôö¼ÓNGMACʼþºÅ:
+ TOOL_NGMAC_ULTBF_EST_CFG_EV ¡¢TOOL_NGMAC_DLTBF_EST_CFG_EV
+ TOOL_NGMAC_ULTBF_REL_CFG_EV ¡¢TOOL_NGMAC_DLTBF_REL_CFG_EV
+ TOOL_NGMAC_PKTTSRECFG_REQ_EV ¡¢TOOL_NGMAC_PKTTBFREL_REQ_EV
+ TOOL_NGMAC_PKTPDCHREL_REQ_EV ¡¢TOOL_NGMAC_PKTCCC_REQ_EV
+ TOOL_NGMAC_PKTCCO_REQ_EV ¡¢TOOL_NGMAC_PKTNCD_REQ_EV
+ TOOL_NGMAC_PKTPOLL_REQ_EV ¡¢TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV
+ TOOL_NGMAC_PKTPRACHPARA_REQ_EV ¡¢TOOL_NGMAC_PKTSCD_REQ_EV
+ TOOL_NGMAC_PKTQUENOTI_REQ_EV ¡¢TOOL_NGMAC_PKTACCREJ_REQ_EV
+ NGMAC_TOOL_PKTMEARPT_EV¡¢NGMAC_TOOL_PKTMOBTBFSTA_EV
+ NGMAC_TOOL_PKTPSISTA_EV ¡¢NGMAC_TOOL_PKTPAUSE_EV
+ NGMAC_TOOL_PKTEMEARPT_EV ¡¢NGMAC_TOOL_PKTADDMSRAC_EV
+ NGMAC_TOOL_PKTCCN_EV ¡¢NGMAC_TOOL_PKTSISTA_EV
+ 2)Ôö¼ÓNGRLCʼþºÅ:
+ TOOL_NGRLC_ULTBF_EST_CFG_EV ¡¢TOOL_NRLC_PUAN_REQ_EV
+ TOOL_NGRLC_DLTBF_CFG_EV ¡¢NGRLC_TOOL_DLTBF_HALF_IND_EV
+ NGRLC_TOOL_DLTBF_FINAL_IND_EV ¡¢NGRLC_TOOL_ULTBF_HALF_IND_EV
+ NGRLC_TOOL_ULTBF_FINAL_IND_EV ¡¢TOOL_NGRLC_ULTBF_REL_EV
+ NGRLC_TOOL_ULTBF_FAI_IND_EV
+ 3)À©Õ¹ÁËNGMACʼþ·¶Î§£º50-¡·100
+ 18 2008.07.02 ½¯Õ×´º 1)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄǰ׺°´AP-MMIAʼþºÅǰ׺
+ 2)MMIAÓë´æ´¢¹ÜÀíÄ£¿éµÄʼþºÅµÄ·¶Î§ÓÉÔÀ´µÄMMIA-NASÒƵ½AP-MMIA
+ 19 2008.07.03 ½ºè 1)Ôö¼ÓÉèÖÃNUMAC¡¢NURLCÓ¦´ð¿ØÖÆÏûÏ¢:
+ TEST_URLCACKCTRL_UTRAN_EV¡¢TEST_UMACACKCTRL_UTRAN_EV
+ 20 2008.07.19 ½ºè 1)Ôö¼ÓTOOL_L1SIMU_SYSINFOFAIL_CFG_EV¡¢
+ GMAC_GET_BLOCKS_EV¡¢GMAC_ACK_BLOCKS_EV¡¢TOOL_NGMAC_PKTPGREQ_REQ_EV
+ 2)ÐÞ¸ÄNGRLCʼþºÅ¶¨Òå
+ 21 2008.07.22 ½ºè 1)Ôö¼ÓGSMÄ£ÄâʼþºÅ·¶Î§ºê¶¨Ò壺EVENT_PS_GSM_SIMU_BEGIN/EVENT_PS_GSM_SIMU_END
+ 22 2008.07.25 ÅËÀÚ 1)Ôö¼ÓÓëTCÏà¹ØʼþºÅ¶¨Òå
+ 23 2008.08.13 ½ºè 1)Ôö¼ÓÁËUMCR-GPHYÖ®¼äµÄʼþºÅ·¶Î§¶¨Òå
+ 2)½«UMCRÓëGSM²âÁ¿Ïà¹ØʼþºÅ¶¨ÒåÒÆÈëUMCR-GPHY·¶Î§ÄÚ
+ 3)Ôö¼ÓÁËURRAÄ£¿éµÄ¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 24 2008.08.14 ÕÅÅô³Ì 1)Ôö¼ÓÁËURRC-GRR¼äURRCGRR_HOINFOCNF_EV¡¢URRCGRR_HOINFOIND_EV
+ 2)Ôö¼ÓÁ˺¯ÊýÐÅÁî¸ú×ÙʼþºÅ·¶Î§ºÍURRCÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+ 25 2008.08.15 ÌÀÔ±¦ 1)Ôö¼ÓURRCINTRA_RADIOLINKFAIL_IND_EVÏûÏ¢
+ 26 2008.08.18 ÍõÀò 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_RXLEVREQ_CFG_EV
+ L1SIMU_TOOL_SYNCREQ_CFG_EV
+ L1SIMU_TOOL_SYSREQ_CFG_EV
+ L1SIMU_TOOL_IDLEMODEREQ_CFG_EV
+ L1SIMU_TOOL_NCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_SCELLRXLEVIND_CFG_EV
+ L1SIMU_TOOL_MEAS_REPORT_CFG_EV
+ L1SIMU_TOOL_DLTBFRELIND_EV
+ L1SIMU_TOOL_ULTBFRELIND_EV
+ 2)Ôö¼ÓNGMACʼþºÅ£ºTOOL_NGMAC_CTRLBLOCK_REQ_EV
+ ʯ×ÚÀ¤ 1)Ôö¼ÓURRAÓëTD PHYÖ®¼äʼþºÅ¶¨Òå
+ 2)Ôö¼ÓL1G-GSMAÖ®¼äʼþºÅ¶¨Òå
+ ×ÞÑÞ 1)Ôö¼ÓGMMAS_CCSYNCIND_GSM_EVʼþºÅ
+ ÕŽ¡ 1)Ôö¼ÓNLAPDMºÍTRSÖ®¼äÓÃÓÚ²»Í¬SAPI¼äÏûÏ¢·¢ËͺÍÒì³£²âÊÔµÄʼþºÅ¶¨Òå
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+ TOOL_NLAPDM_EXCEPT_DATA_EV
+ NLAPDM_TOOL_I_IND_EV
+ ׿Խ 1)Ôö¼ÓURRC_FUNC_SUSPENDMEASREQ_EV
+ 27 2008.08.20 ʯ×ÚÀ¤ 1)Ôö¼ÓL1GÐÅÁî¸ú×ÙʼþºÅ¶¨Ò壺L1G_ST_....
+ 2)Ôö¼ÓURRA-GPHYʼþºÅ·¶Î§¶¨Òå
+ 28 2008.08.30 ½ª²¨ 1)ÓÉÓÚ´¦Àí¸ÕפÁôijСÇø1SÄÚ²»ÄܶԲâÁ¿¸üºÃµÄСÇø½øÐÐÖØÑ¡£¬Ôö¼ÓUCSR_TCAMP1S_EXPIRY_EV
+ Ç®¿¡ 2)Ôö¼ÓGSMÐÅÁî¸ú×ÙʼþºÅ¶¨Òå¡£
+ 29 2008.09.03 ½ºè 1)L1G_GSMA_EVENT_BASE/L1G_GSMA_EVENT_END ÐÞ¸ÄΪ£ºL1G_DM_EVENT_BASE/L1G_DM_EVENT_END
+ 2)L1GË«Ä£ÏûϢǰ׺¸ü¸ÄΪ£ºL1G_DM_
+ 3)Ôö¼ÓÁËL1G_DM_TDD_CELL_MEAS_REQ
+ 4)Ôö¼ÓÁËL1SIMU_TOOL_TAFIND_EV¡¢L1SIMU_TOOL_TAFREQ_EV
+ 30 2008.09.16 ÍõÀò 1)Ôö¼Ó3Gʱ,UMMÏòRBCÅäÖÃÑ°ºôµÄÇëÇóʼþºÅ£º
+ UMMAS_PAGEREQ_EV
+ 31 2008.09.19 ½ºè 1)SDLÈÎÎñºÍÆÕͨÈÎÎñ¼äÏûÏ¢¶¨ÒåͳһÔÚSIG_CODE.HÖУ¬ÏÂÁкêÃû±»ÒÆ×ߣº
+ L1G_DM_DEACT_UMTS_REQ¡¢L1G_DM_DEACT_GSM_CNF
+ L1G_DM_TDD_CELL_MEAS_REQ¡¢L1G_UTRAN_MEAS_PERIOD_IND
+ 2)ɾ³ýÁË£º
+ L1G_DM_EVENT_BASE¡¢L1G_DM_EVENT_END
+ P_GSM_INACT_TIME_REQ_EV¡¢P_ABORT_GSM_GAP_REQ_EV¡¢P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ 32 2008.09.22 ÍõС½ø 1)Ôö¼ÓAP_MMIA_SMSABORTMOREQ_EV¡¢MMIASMS_ABORTMOREQ_EV
+ 33 2008.10.10 ÍõÀò 1)Ôö¼ÓUMMAS_PWRONREQ_EV
+ 34 2008.10.15 Íõ¾´Ò¢ 1)Ôö¼ÓNGMACʼþºÅ:
+ NGMAC_TOOL_CCF_IND_EV
+ 35 2008.10.24 ʯ×ÚÀ¤ 1)Ôö¼ÓL1SIMUʼþºÅ£º
+ L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV¡¢
+ L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV
+ 36 2008.11.05 ½ºè 1)ÐÞ¸ÄËùÓÐZ_ǰ׺Ϊ
+ 37 2008.11.13 ÍõÀò 1)Ôö¼ÓGMM_TPOWEROFF_EXPIRY_EV:2G¹Ø»ú¼à¿ØÈ¥»îÁ÷³Ì¶¨Ê±Æ÷
+ 38 2008.11.17 ÑîÎÄÇ¿ 1)È¡ÏûÏûÏ¢NGRLC_START_TIMER_EV(²»ÔÙʹÓÃ)
+ 2)Ôö¼Ó ÏûÏ¢NGRLC_TOOL_DLTBF_FAI_IND_EV¡¢TOOL_NGRLC_BEGINTESTMODE_EV¡¢NGRLC_TOOL_PDANNOTIFY_EV
+ 39 2008.11.27 ¸ßÏè 1)Ôö¼ÓCUMAC_GETTVBOCMPIND_EV£¬ÒÔ֪ͨUMCRÄ£¿é²ÉÑùÍê³É£¬¿ÉÒÔ½øÐÐÏà¹ØÆÀ¹ÀºÍ±¨¸æ¡£
+ ΤÓñÕä 1)Ôö¼ÓP_GSM_MEAS_DONE_REQ_EV
+ 40 2008.11.28 ׿Խ 1)ɾ³ýÁËMAC²âÁ¿²¿·ÖÐÅÁî¸ú×ÙÏûÏ¢URRC_FUNC_SUSPENDMEASREQ_EV,URRC_FUNC_TVMEASREQ_EV,URRC_FUNC_QUAMEASREQ_EV,URRC_FUNC_UEINTERMEASREQ_EV,
+ URRC_FUNC_RESUMEMEASREQ_EV,URRC_FUNC_MACRPT_EV,URRC_FUNC_TVDISTRIBUTE_EV,URRC_FUNC_QUADISTRIBUTE_EV,URRC_FUNC_UEINTERDISTRIBUTE_EV
+ 41 2008.12.10 ½¯Õ×´º 1)Ôö¼ÓUMMAS_ABORTCNF_EV
+ 42 2008.12.29 ½ºè 1)Ϊ֧³Ö½Å±¾¿ØÖÆCSDÒµÎñ£¬Ôö¼ÓTEST_TAFDATAIND_UTRAN_EV
+ ¸ßÏè148725 1)ÐÞ¸ÄSM¶¨Ê±Æ÷ʼþºÅ¶¨Òå
+ 2)Ôö¼ÓMMIASM_PDPAUTOACTIND_EV
+ 43 2008.12.31 ×ÞÑÞ 1)Ôö¼ÓÁËCC¶¨Ê±Æ÷ʼþºÅ £ºCC_TMMCONN_EXPIRY_EV ¼à¿ØMMÁ¬½ÓµÄ½¨Á¢
+ 44 2009.02.10 ÑîÔÊ 1)Ôö¼ÓÁËMMÄ£¿é¶¨Ê±Æ÷ÏûÏ¢£ºMM_T3231_EXPIRY_EV¡¢MM_T3232_EXPIRY_EV
+ 45 2009.02.12 ½ºè 1)TAFÓëL1GÏûÏ¢¶¨ÒåÒÆÈëSIG_CODE.H£¬É¾³ýTAF_L1GÏûÏ¢·¶Î§
+ 2)Ôö¼ÓTAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢£ºTAF_FUNC_L1GDATAREQ_EV
+ 46 2009.02.16 ÍõС½ø 1)UMMÐÂÔöATÃüÁIMSI¼¤»îÈ¥»îÇëÇ󡢶ÔÁ½¸öÓòͬʱ½øÐÐÈ¥»îµÄÇëÇó¡¢ÉèÖÃGPRS×Ô¶¯¸½×ÅÇëÇó£¬
+ Ôö¼ÓÏûÏ¢¶¨Ò壺AP_MMIA_ZATTSETREQ_EV¡¢AP_MMIA_ZATTQUERYREQ_EV¡¢
+ AP_MMIA_ZGAATSETREQ_EV¡¢AP_MMIA_ZGAATQUERYREQ_EV¡¢
+ AP_MMIA_ZATTQUERYCNF_EV¡¢AP_MMIA_ZGAATQUERYCNF_EV
+ 47 2009.02.19 Ëﳤ½ 1)MM/GMM/CC£RRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºGMMAS_CSRABRELIND_EV;
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_ABORTCFGREQ_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_ACTTIMENOTIFY_REQ_EV£»
+ 48 2009.02.21 ×ÞÑÞ 1)Ö§³ÖMODIFY¹ý³Ì£¬Ôö¼ÓCCÓëTAFʼþºÅ¶¨Ò壺
+ CCTAF_PEND_REQ_EV¡¢CCTAF_RESUME_REQ_EV¡¢CCTAF_MODIFYBC_REQ_EV¡¢CCTAF_MODIFYBC_CNF_EV
+ 2)Ôö¼ÓCC¶¨Ê±Æ÷ʼþºÅ¶¨Ò壺
+ CC_TRELTAF_EXPIRY_EV
+ CC_TCONNTAF_EXPIRY_EV
+ CC_TSYNCIND_EXPIRY_EV
+ CC_TMODIFYBC_EXPIRY_EV
+ 49 2009.02.24 ½»¶ 1)Ϊ֧³ÖUSAT¹¦ÄÜ£¬Ôö¼ÓMMIAÓëATI/UICCÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_USAT_ENVELOPREQ_EV
+ AP_MMIA_USAT_ENVELOPCNF_EV
+ AP_MMIA_USAT_TERMNLRSPREQ_EV
+ AP_MMIA_USAT_TERMNLPROFREQ_EV
+ AP_MMIA_USAT_PROCMDIND_EV
+ AP_UICC_USAT_ENVELOPREQ_EV
+ AP_UICC_USAT_ENVELOPCNF_EV
+ AP_UICC_USAT_TERMNLRSPREQ_EV
+ AP_UICC_USAT_TERMNLPROFREQ_EV
+ AP_UICC_USAT_COMMONCNF_EV
+ AP_UICC_USAT_PROVCMDIND_EV
+ 50 2009.03.05 ÍõС½ø 1)UICCNOCARDIND²»ÔÙÉϱ¨¸øATI£¬ËùÒÔɾ³ýAP_MMIA_UICCNOCARDIND_EV
+ 51 2009.03.10 ½ºè Ôö¼ÓÖ§³ÖCBS¹¦ÄÜ
+ 1)Ôö¼ÓMMIA-ATI¡¢MMIA-CBSÖ®¼äʼþºÅ¶¨Ò壺
+ AP_MMIA_CBS_CSCBSETREQ_EV
+ AP_MMIA_CBS_CSCBREADREQ_EV
+ AP_MMIA_CBS_SAVINGSETREQ_EV
+ AP_MMIA_CBS_RESTORESETREQ_EV
+ AP_MMIA_CBS_CSCBREADCNF_EV
+ AP_MMIA_CBS_TCBMIND_EV
+ AP_MMIA_CBS_PCBMIND_EV
+ AP_MMIA_CBS_TCBMLISTCNF_EV
+ AP_MMIA_CBS_PCBMLISTCNF_EV
+ AP_MMIA_CBS_TCBMREADCNF_EV
+ AP_MMIA_CBS_PCBMREADCNF_EV
+ MMIACBS_ACTIVATEREQ_EV
+ MMIACBS_ACTIVATECNF_EV
+ MMIACBS_DATAIND_EV
+ 2)CBSÏà¹ØATÃüÁî¶ÔÓ¦ÏûÏ¢´ÓAP-MMIA SMS²¿·Ö¶¨ÒåÖÐɾ³ý£º
+ AP_MMIA_SMSCSCBREQ_EV
+ AP_MMIA_SMSCSASREQ_EV
+ AP_MMIA_SMSCRESREQ_EV
+ AP_MMIA_SMSTCBMIND_EV
+ AP_MMIA_SMSTCBMREADCNF_EV
+ AP_MMIA_SMSCSCBCNF_EV
+ AP_MMIA_SMSCSASCNF_EV
+ AP_MMIA_SMSCRESCNF_EV
+ AP_MMIA_SMSTCBMLISTCNF_EV
+ 3)CBSÓëURBCµÄÖ®¼äµÄʼþºÅ¶¨Òå:
+ CBSAS_NODRXREQ_EV
+ CBSAS_DRXRSVREQ_EV
+ CBSAS_STOPREQ_EV
+ CBSAS_PCHCELLINFOIND_EV
+ 4)CBSÓëUMMÖ®¼äµÄʼþºÅ¶¨ÒåµÄ¶¨Òå:
+ UMMCBS_STARTREQ_EV
+ UMMCBS_STOPREQ_EV
+ UMMCBS_CELLINFOIND_EV
+ 5)CBS¶¨Ê±Æ÷ÏûϢʼþºÅµÄ¶¨Òå:
+ CBS_TSCHEDCHECK_EXPIRY_EV
+ 6)Ôö¼ÓURBCÓëURLCÖ®¼ä½Ó¿Ú¶¨Ò壺
+ CURLC_CBSRBCONFIGREQ_EV
+ 7)Ôö¼ÓURBCÓëPHYÖ®¼ä½Ó¿Ú¶¨Ò壺
+ P_CBS_NODRX_REQ_EV
+ P_CBS_DRX_REQ_EV
+ P_ADD_MODIFY_CBS_REQ_EV
+ P_STOP_CBS_REQ_EV
+ 52 2009.03.20 ÍõС½ø 1)Ôö¼ÓÖ§³ÖATÃüÁ+ZUSTAT,+ZURDY,+ZUSLOT,+ZPINSTAT
+ AP_MMIA_UICCCOMMANDREQ_EV
+ AP_MMIA_UICCCOMMANDQUERYCNF_EV
+ 53 2009.03.23 ÍõС½ø 1)Ôö¼ÓÏûÏ¢£º
+ AP_MMIA_USAT_LOCINFOCNF_EV
+ AP_MMIA_USAT_LOCINFOREQ_EV
+ 54 2009.03.31 ½»¶ 1)Ôö¼ÓÖ§³Ö¹¤³Ìģʽ£º
+ AP_MMIA_EM_CELLINFOREQ_EV
+ AP_MMIA_EM_CELLINFOQUERYREQ_EV
+ AP_MMIA_EM_LOCKCELLREQ_EV
+ AP_MMIA_EM_HOINFOREQ_EV
+ AP_MMIA_EM_HOINFOQUERYREQ_EV
+ AP_MMIA_EM_CELLINFOIND_EV
+ AP_MMIA_EM_CELLINFOQUERYCNF_EV
+ AP_MMIA_EM_HOINFOIND_EV
+ AP_MMIA_EM_HOINFOQUERYCNF_EV
+ MMIAUMM_EM_LOCKCELLREQ_EV
+ MMIAUMM_EM_LOCKCELLCNF_EV
+ MMIAAS_EM_CELLINFOREQ_EV
+ MMIAAS_EM_HOINFO_REQ
+ MMIAAS_EM_UCELLINFOIND_EV
+ MMIAAS_EM_UHOINFOIND_EV
+ UMMAS_LOCKCELLREQ_EV
+ UMMAS_UNLOCKCELLREQ_EV
+ UMMAS_LOCKCELLCNF_EV
+ MMIA_EM_HOINFO_EXPIRY_EV
+ UMCR_EM_CELLINFO_EXPIRY_EV
+ 55 2009.04.02 ΤÓñÕä 1)ÐÞ¸ÄÐźÅÇ¿¶ÈÉϱ¨·½Ê½£¬Ôö¼Ó£º
+ AP_MMIA_RXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVREQ_EV
+ AP_MMIA_ZRPTRXLEVQUERYREQ_EV
+ AP_MMIA_RXLEVCNF_EV
+ AP_MMIA_ZRPTRXLEVIND_EV
+ AP_MMIA_ZRPTRXLEVQUERYCNF_EV
+ MMIAAS_RPTRXLEV_REQ_EV
+ MMIAAS_QUERYRXLEV_REQ_EV
+ MMIAAS_RPTRXLEV_IND_EV
+ MMIAAS_QUERYRXLEV_IND_EV
+ ɾ³ý:
+ MMIAMCR_RPTPRDREQ_EV
+ MMIAMCR_RSSIIND_EV
+ AP_MMIA_CSQEXEREQ_EV
+ AP_MMIA_ZSQSETREQ_EV
+ AP_MMIA_ZSQQUERYREQ_EV
+ AP_MMIA_ZSQIND_EV
+ AP_MMIA_CSQEXECNF_EV
+ AP_MMIA_ZSQQUERYCNF_EV
+ 56 2009.04.13 ½ºè 1)ΪÔö¼ÓL1GÓëPHYÖ®¼ä˫ģʼþºÅ¶¨Ò壺
+ P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV
+ P_GSM_INACT_TIME_REQ_EV
+ P_ABORT_GSM_GAP_REQ_EV
+ 2)ºô½ÐÐÅÏ¢Éϱ¨£º
+ AP_MMIA_CCPROCINFOIND_EV
+ MMIACC_PROCINFOIND_EV
+ 3)Ϊ±ÜÃⲻͬ½á¹¹¶ÔӦͬÃûÏûÏ¢£¬Ôö¼Ó£º
+ TEST_UURLCDATAIND_UTRAN_EV
+ TEST_UURLCCONFIGREQ_UTRAN_EV
+ 57 2009.05.08 ½ª²¨ 1)Ôö¼ÓUMCRͬUCSRÖ®¼ä֪ͨÁÚÇø¸ü¸ÄµÄURRCÄÚ²¿Ê¼þºÅ:
+ URRCINTRA_NEIBCELLCHGIND_EV
+ 58 2009.05.11 ½ª²¨ 1)ɾ³ýUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CAMPONCELLREQ_EV
+ URRCGRR_CAMPONCELLCNF_EV
+ URRCGRR_CAMPONCELLIND_EV
+ URRCGRR_CAMPONCELLRSP_EV
+ 2)Ôö¼ÓUCSRͬGSMAÖ®¼äµÄʼþºÅ
+ URRCGRR_CELLRESELREQ_EV
+ URRCGRR_ANYCELLRESELREQ_EV
+ URRCGRR_CELLRESELIND_EV
+ URRCGRR_CELLRESELREJ_EV
+
+ 59 2009.05.19 ½¯Õ×´º 1)Ôö¼ÓUMMͬGSMAÖ®¼äµÄʼþºÅ
+ UMMAS_GSMSRVNOTIFYREQ_EV
+ 60 2009.05.20 Ëﳤ½ 1)URLC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCURLC_CONFIGCNF_EV£»
+ ɾ³ýÏûÏ¢ºÅCURLC_STOPREQ_EV£»
+ 2)URRC/CC£SCIÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCSCI_CONFIGCNF_EV£»
+ 3)PDCP£URRCÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCPDCP_CONFIGCNF_EV£»
+ 2)URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºURRCINTRA_FACHCFGREQ_EV£»
+ URRCINTRA_FACHCFGIND_EV;
+ 3)UMAC - URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£ºCUMAC_CONTINUEREQ_EV£»
+
+ 61 2009.5.22 ËïÒÔÀ× 1)Ôö¼ÓGSMA¶¨Ê±Æ÷µÄʼþºÅ¶¨Òå
+ GSMA_PROCTIMER_EXPIRY_EV
+ GSMA_INACTTIMER_EXPIRY_EV
+
+ 62 2009.06.04 ʷѧºì 1)PDCP£URRC ÏûÏ¢ºÅ¶¨ÒåÔö¼Ó£º
+ CPDCP_RELOCREJ_EV
+ CPDCP_RELOCCOMPIND_EV
+ CPDCP_RELOCFAILIND_EV
+ CPDCP_DLPDUSIZECHANGEREQ_EV
+ CPDCP_DLPDUSIZECHANGECNF_EV
+ CPDCP_ROHCTARGETMODEREQ_EV
+ 2)PDCP£URRC ÏûÏ¢ºÅ¶¨Òåɾ³ý£º
+ CPDCP_RELOCCOMPREQ_EV
+
+ 63 2009.06.22 ΤÓñÕä 1)ÐÂÔöMACUL->MACDLÏûÏ¢£º
+ CUMAC_NOTIFYDLPERIODREPORTREQ_EV
+ 2)ɾ³ýÒÔÏÂÏûÏ¢£º
+ CUMAC_MEASRELREQ_EV
+ CUMAC_MEASREPORTIND_EV
+ CUMAC_PERIODMEASDELNOTIFYREQ_EV
+ CUMAC_GETTVBOCMPIND_EV
+ 3)ÐÂÔöRRCÓëUMAC½Ó¿ÚÏûÏ¢£º
+ CUMAC_TRAFFICMEASREQ_EV
+ CUMAC_QUANLITYMEASREQ_EV
+ CUMAC_INTERNALMEASREQ_EV
+ CUMAC_TVMEASRELREQ_EV
+ CUMAC_QMEASRELREQ_EV
+ CUMAC_UEMEASRELREQ_EV
+ CUMAC_TVMEASRESUMEREQ_EV
+ CUMAC_TVMEASSUSPENDREQ_EV
+ CUMAC_DLMEASSUSPENDREQ_EV
+ CUMAC_DLMEASRESUMEREQ_EV
+ CUMAC_ADDTVMEASREPORTREQ_EV
+ CUMAC_ADDQMEASREPORTREQ_EV
+ CUMAC_ADDUEMEASREPORTREQ_EV
+
+65 2009.06.23 ÑîÔÊ 1)Ôö¼ÓGMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ GMM_TWSPN_EXPIRY_EV
+ GMM_TWCRS_EXPIRY_EV
+ GMM_TWTRG_EXPIRY_EV
+
+66 2009.06.24 ½ºè 1)ÐÞ¸ÄTEST_GVAR_XXXΪGVAR_XXX
+ 2)ÖØÐÂÕûÀíÁ˲âÊÔÏûϢʼþ¶¨Ò巶Χ
+ 3)Ôö¼ÓÁËNCBSÏà¹ØÏûÏ¢¶¨Ò壺£¨½ªéª£©
+ TEST_UCBSSCHEDCFG_UTRAN_EV
+ TEST_UCBSDATAREQ_UTRAN_EV
+ TEST_UCBSOUTPUTEND_UTRAN_EV
+ TEST_UCBSUMAC_TFSCFG_UTRAN_EV
+ TEST_UCBSUMAC_SFNINFO_UTRAN_EV
+ TEST_UURLCDATACNF_UTRAN_EV
+ TOOL_L1SIMU_CBSBLK_START_EV
+ TOOL_L1SIMU_CBSFSTBLK_REQ_EV
+ TOOL_L1SIMU_CBSOTHERBLK_REQ_EV
+
+67 2009.06.29 QIANJUN155488 1)Ôö¼ÓÓû§ÃæÐÅÁî¸ú×ÙαÏûÏ¢¶¨Òå
+ ATIPDI_DATAREQ_TRACE_EV
+ UPDI_DATAREQ_TRACE_EV
+ SN_DATA_REQ_TRACE
+ SN_UNITDATA_REQ_TRACE
+ LL_DATA_REQ_TRACE
+ LL_UNITDATA_REQ_TRACE
+ LLC_GET_NEXT_PDU_TRACE_EV
+ GMAC_GET_BLOCKS_TRACE_EV
+ GMAC_ACK_BLOCKS_TRACE_EV
+ PDCP_UPDATA_TRACE_EV
+ URLC_GETBO_TRACE_EV
+ URLC_SENDPDU_TRACE_EV
+ UMAC_TFCSEL_TRACE_EV
+ PH_MAC_DATA_IND_TRACE
+ PH_RLC_DATA_IND_TRACE
+ MAC_RLC_DATA_IND_TRACE
+ RLC_DATA_IND_TRACE
+ RLC_UNITDATA_IND_TRACE
+ LL_DATA_IND_TRACE
+ LL_UNITDATA_IND_TRACE
+ SN_DATA_IND_TRACE
+ SN_UNITDATA_IND_TRACE
+ UPDI_DATAIND_TRACE_EV
+ ATIPDI_DATAIND_TRACE_EV
+ UUMAC_DATAIND_TRACE_EV
+ PDCP_DOWNDATA_TRACE_EV
+ TAF_COUNTER_TRACE_EV
+ TAF_RLP_XID_ULFRAME_TRACE_EV
+ TAF_RLP_XID_DLFRAME_TRACE_EV
+ TAF_RLP_SABM_ULFRAME_TRACE_EV
+ TAF_RLP_SABM_DLFRAME_TRACE_EV
+ TAF_RLP_UA_ULFRAME_TRACE_EV
+ TAF_RLP_UA_DLFRAME_TRACE_EV
+ TAF_RLP_DISC_ULFRAME_TRACE_EV
+ TAF_RLP_DISC_DLFRAME_TRACE_EV
+ TAF_RLP_DM_ULFRAME_TRACE_EV
+ TAF_RLP_DM_DLFRAME_TRACE_EV
+ TAFL1G_DATA_IND_TRACE_EV
+ TAFL1G_DATA_REQ_TRACE_EV
+ TAF_FUNC_UURLCDATAIND_EV
+ TAF_FUNC_UURLCDATAREQ_EV
+68 2009.7.2 ½»¶ 1)Ϊ֧³ÖÖÐÒÆËæEÐÐATÃüÁÔö¼ÓÏÂÁÐÏûÏ¢£º
+ AP_UICC_PINENABLEQUERYREQ_EV
+ AP_UICC_PINENABLEQUERYCNF_EV
+ AP_UICC_PINSTATQUREYREQ_EV
+ AP_UICC_PINSTATQUREYCNF_EV
+ AP_UICC_CARDMODEREQ_EV
+ AP_UICC_CARDMODECNF_EV
+ AP_MMIA_SETPINAPPLREQ_EV
+ AP_MMIA_SETPINAPPLCNF_EV
+ AP_MMIA_PINAPPLREADREQ_EV
+ AP_MMIA_PINAPPLREADCNF_EV
+ AP_MMIA_CPINREQ_EV
+ AP_MMIA_CPINREADREQ_EV
+ AP_MMIA_CPINREADCNF_EV
+ AP_MMIA_CARDMODEREQ_EV
+ AP_MMIA_CARDMODECNF_EV
+ AP_MMIA_MODEREQ_EV
+ AP_MMIA_MODECNF_EV
+69 2009.7.15 ½ºè 1)Òƶ¯L1G_ST_EVENT·¶Î§µ½SIGTRACE_EVENT·¶Î§ÄÚ
+ 2)Ôö¼ÓGVAR_CBS_GETREQ_EV¡¢GVAR_CBS_GETCNF_EV
+70 2009.7.17 Áõµ¤ 1)Ôö¼ÓURRC-URLCµÄʼþºÅ:
+ CURLC_SETDATANOTIFYMODE_EV
+ CURLC_PCHULDATATRREQ_EV
+71 2009.7.21 ½»¶ 1)ɾ³ý£º
+ AP_MMIA_ZBDMDSETREQ_EV
+ AP_MMIA_ZBDMDQUERYREQ_EV
+ AP_MMIA_ZBDMDQUERYCNF_EV
+ 2)ÐÂÔö£º
+ AP_MMIA_ZACTSETREQ_EV
+ AP_MMIA_ZACTQUERYREQ_EV
+ AP_MMIA_ZACTQUERYCNF_EV
+ AP_MMIA_MODEQRYREQ_EV
+ AP_MMIA_MODEQRYCNF_EV
+ AP_MMIA_MODESETREQ_EV
+72 2009.7.23 ÍõÀò 1)Ôö¼Ó£¬UMCRÔÚ½øÈë·ÉÐÐģʽʱ£¬Í¨ÖªURRCA½øÈë¿ÕÏеÄÏûÏ¢£º
+ P_GSM_MEAS_TONULL_REQ_EV
+73 2009.7.28 ΤÓñÕä 1)Ö§³ÖÈý°æÐб꣬Ôö¼ÓURRCÄÚ²¿Ê¼þºÅURBC-UMCR: URRCINTRA_DRXCHGIND_EV
+ Ôö¼ÓUMCR-URRCAµÄʼþºÅ: P_GSM_MEAS_DRX_CHANGE_REQ_EV
+74 2009.7.28 ʷѧºì 1)Ôö¼ÓNPDCP_EVENT_BASE¡¢NPDCP_EVENT_END
+ 2)Ôö¼ÓNPDCPʼþºÅ£º
+ CPDCP_CONFIGREQ_UTRAN_EV
+ CPDCP_RELEASEREQ_UTRAN_EV
+ NPDCP_DATAREQ_UTRAN_EV
+ NPDCP_DATAIND_UTRAN_EV
+ TEST_NPDCP_DATAERRIND_UTRAN_EV
+ TEST_NPDCP_DATACNF_UTRAN_EV
+75 2009.8.11 ÍõÀò CC/SM/SS²¿·ÖÓëATIÓÅ»¯½Ó¿ÚÐÞ¸Ä
+ 1)Ôö¼ÓºÍÐÞ¸ÄCCÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ Ôö¼Ó£ºAP_MMIA_CCQUERYREQ_EV/AP_MMIA_RINGIND_EV/AP_MMIA_CRINGIND_EV/AP_MMIA_CCWAIND_EV
+ AP_MMIA_MOCALLSSNOTIFY_EV/AP_MMIA_MTCALLSSNOTIFY_EV/AP_MMIA_CCQUERYCNF_EV/AP_MMIA_CLIPIND_EV
+ AP_MMIA_CRIND_EV/AP_MMIA_CCSETREQ_EV/AP_MMIA_COLPIND_EV/MMIACC_CSTAQUERYREQ_EV
+ MMIACC_CSTASETREQ_EV/MMIACC_CSTAQUERYCNF_EV/AP_MMIA_MODTOMULTMEDIARSP_EV
+ AP_MMIA_MODTOMULTMEDIAIND_EV/MMIACC_MODTOMULTMEDIARSP_EV/MMIACC_MODTOMULTMEDIAIND_EV
+ ɾ³ý£ºAP_MMIA_CRLPSETREQ_EV/AP_MMIA_CRLPQUERYREQ_EV/AP_MMIA_CHSNSETREQ_EV/AP_MMIA_CHSNQUERYREQ_EV
+ AP_MMIA_ETBMSETREQ_EV/AP_MMIA_ETBMQUERYREQ_EV
+ AP_MMIA_CCSETREQ_EV/AP_MMIA_CCSETUPIND_EV/AP_MMIA_CCCOMMANDCNF_EV/AP_MMIA_SSNOTIFYIND_EV
+ AP_MMIA_CHSNQUERYCNF_EV/AP_MMIA_DSQUERYCNF_EV/AP_MMIA_ETBMQUERYCNF_EV/AP_MMIA_CRLPQUERYCNF_EV
+ AP_MMIA_CCCAUSEQUERYREQ_EV/AP_MMIA_CCCAUSEQUERYCNF_EV
+
+ 2)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£º AP_MMIA_SMQUERYREQ_EV¡¢AP_MMIA_SMHANDLEREQ_EV¡¢AP_MMIA_SMANSREQ_EV
+ AP_MMIA_SMPDPADDRREQ_EV¡¢AP_MMIA_SMNEGQOSREQ_EV¡¢AP_MMIA_SMMODEMMOREQ_EV¡¢
+ AP_MMIA_SMMODEMANSREQ_EV¡¢AP_MMIA_SMCAUSEREQ_EV¡¢AP_MMIA_SMCANCELREQ_EV¡¢
+ AP_MMIA_SMQUERYPDPINFOREQ_EV¡¢AP_MMIA_SMQUERYCNF_EV¡¢AP_MMIA_SMHANDLECNF_EV¡¢
+ AP_MMIA_SMANSCNF_EV¡¢AP_MMIA_SMPDPADDRCNF_EV¡¢AP_MMIA_SMNEGQOSCNF_EV¡¢
+ AP_MMIA_SMMODEMMOCNF_EV¡¢AP_MMIA_SMMODEMANSCNF_EV¡¢AP_MMIA_SMCAUSECNF_EV¡¢
+ AP_MMIA_SMMTDEACTIVATEIND_EV¡¢AP_MMIA_SML2PIND_EV¡¢AP_MMIA_SMQUERYPDPINFOCNF_EV
+ Ôö¼Ó£ºAP_MMIA_SMREADREQ_EV¡¢AP_MMIA_SMQUERYPDPSTATUSREQ_EV¡¢AP_MMIA_SMQUERYACTCIDREQ_EV¡¢
+ AP_MMIA_SMQUERYDEFCIDREQ_EV¡¢AP_MMIA_SMQUERYPDPADDRREQ_EV¡¢AP_MMIA_SMQUERYNEGQOSREQ_EV¡¢
+ AP_MMIA_SMQUERYNEGEQOSREQ_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV¡¢AP_MMIA_SMACTDEACTREQ_EV¡¢
+ AP_MMIA_SMMODREQ_EV¡¢AP_MMIA_SMMTACTANSREQ_EV¡¢AP_MMIA_SMIPPDPACTREQ_EV¡¢
+ AP_MMIA_SMOPENCHRSP_EV¡¢AP_MMIA_SMQUERYIDLECHRSP_EV¡¢AP_MMIA_SMGETPCORSP_EV¡¢
+ AP_MMIA_SMQUERYPDPSTATUSCNF_EV¡¢AP_MMIA_SMQUERYACTCIDCNF_EV¡¢AP_MMIA_SMQUERYDEFCIDCNF_EV¡¢
+ AP_MMIA_SMQUERYPDPADDRCNF_EV¡¢AP_MMIA_SMQUERYNEGQOSCNF_EV¡¢AP_MMIA_SMQUERYNEGEQOSCNF_EV¡¢
+ AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMACTDEACTCNF_EV¡¢AP_MMIA_SMMODCNF_EV¡¢
+ AP_MMIA_SMCGEVIND_EV¡¢AP_MMIA_SMIPPDPACTCNF_EV¡¢AP_MMIA_SMOPENCHIND_EV¡¢
+ AP_MMIA_SMCLOSECHIND_EV¡¢AP_MMIA_SMQUERYIDLECHIND_EV¡¢AP_MMIA_SMGETPCOIND_EV¡¢
+ AP_MMIA_SMCONNECTIND_EV¡¢AP_MMIA_SMNOCARRIERCNF_EV
+
+ 3)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯ºóµÄʼþºÅ AP_MMIAÖ®¼ä
+ ɾ³ý£ºAP_MMIA_CAAPTESTREQ_EV/AP_MMIA_CFCSQUERYREQ_EV/AP_MMIA_CPPSEXEREQ_EV/AP_MMIA_CFCSTESTREQ_EV
+ AP_MMIA_CAAPQUERYREQ_EV/AP_MMIA_CPPSEXECNF_EV/AP_MMIA_CFCSQUERYCNF_EV/AP_MMIA_CFCSTESTCNF_EV
+ Ôö¼Ó£ºAP_MMIA_COLRQUERYREQ_EV/AP_MMIA_COLRQUERYCNF_EV
+ ÆÁ±ÎÔÝδʵÏÖ¹¦ÄܵÄʼþºÅ£ºAP_MMIA_CAEMLPPSETREQ_EV /AP_MMIA_CAEMLPPQUERYREQ_EV /AP_MMIA_CFCSSETREQ_EV
+ AP_MMIA_CAAPSETREQ_EV/AP_MMIA_CAEMLPPQUERYCNF_EV /AP_MMIA_CAAPQUERYCNF_EV
+ AP_MMIA_CAAPTESTCNF_EV
+
+ 4)Ôö¼ÓIMEI/IMSI²éѯºÍ֤ʵµÄÏûϢʼþºÅ AP_MMIAÖ®¼ä
+ AP_MMIA_QUERYIMSIREQ_EV/AP_MMIA_QUERYIMEIREQ_EV/AP_MMIA_QUERYIMSICNF_EV/AP_MMIA_QUERYIMEICNF_EV
+
+ 5)Ôö¼ÓºÍÐÞ¸ÄSSÄ£¿éÓÅ»¯µÄʼþºÅ MMIASSÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ Ôö¼Ó:MMIASS_COLRREADREQ_EV/MMIASS_ABORTREQ_EV/MMIASS_COMMONCNF_EV/SS_WAIT_TIMER_EXPIRY_EV
+ MMIASS_CUSDMTIND_EV
+
+ ɾ³ý:MMIASS_CAEMLPPSETREQ_EV/MMIASS_CAEMLPPREADREQ_EV/MMIASS_CPWDSETCNF_EV/MMIASS_CCFCSETCNF_EV
+ MMIASS_CCWASETCNF_EV/MMIASS_CAEMLPPSETCNF_EV/MMIASS_CAEMLPPREADCNF_EV/MMIASS_FORWARDCHECK_IND_EV
+ SS_T5000_EXPIRY_EV/MMIASS_CUSDUNSCNF_EV
+
+ 6)Ôö¼ÓºÍÐÞ¸ÄSMÄ£¿éÓÅ»¯µÄʼþºÅ MMIASMÖ®¼ä,¶¨Ê±Æ÷ÏûÏ¢
+ ɾ³ý:
+ MMIASM_PDPSTATUSREQ_EV¡¢MMIASM_NEGQOSREQ_EV¡¢MMIASM_PDPADDRREQ_EV¡¢
+ MMIASM_CAUSEREQ_EV¡¢MMIASM_PDPACTREJ_EV¡¢MMIASM_QUERYPDPINFOREQ_EV¡¢
+ MMIASM_PDPDEACTIVATEIND_EV¡¢MMIASM_PDPSTATUSCNF_EV¡¢MMIASM_NEGQOSCNF_EV¡¢
+ MMIASM_PDPADDRCNF_EV¡¢MMIASM_CAUSECNF_EV¡¢MMIASM_QUERYPDPINFOCNF_EV
+ SM_ATHRELEASE_EXPIRY_EV¡¢AP_MMIA_SMQUERYCAUSECNF_EV¡¢AP_MMIA_SMQUERYCAUSEREQ_EV
+ Ôö¼Ó:
+ MMIASM_QUERYNEGQOSREQ_EV¡¢MMIASM_QUERYNEGEQOSREQ_EV¡¢MMIASM_QUERYACTCIDREQ_EV¡¢
+ MMIASM_QUERYPDPSTATUSREQ_EV¡¢MMIASM_QUERYPDPADDRREQ_EV¡¢MMIASM_QUERYPDPCAUSEREQ_EV¡¢
+ MMIASM_MTACTANSREQ_EV¡¢MMIASM_IPPDPACTREQ_EV¡¢MMIASM_OPENCHRSP_EV¡¢
+ MMIASM_QUERYIDLECHRSP_EV¡¢MMIASM_GETPCORSP_EV¡¢MMIASM_QUERYNEGQOSCNF_EV¡¢
+ MMIASM_QUERYNEGEQOSCNF_EV¡¢MMIASM_QUERYACTCIDCNF_EV¡¢MMIASM_QUERYPDPSTATUSCNF_EV¡¢
+ MMIASM_QUERYPDPADDRCNF_EV¡¢MMIASM_QUERYPDPCAUSECNF_EV¡¢MMIASM_CGEVIND_EV¡¢
+ MMIASM_IPPDPACTCNF_EV¡¢MMIASM_OPENCHIND_EV¡¢MMIASM_CLOSECHIND_EV¡¢
+ MMIASM_QUERYIDLECHIND_EV¡¢MMIASM_GETPCOIND_EV¡¢MMIASM_COMMONCNF_EV¡¢
+ MMIASM_CONNECTIND_EV¡¢MMIASM_NOCARRIERCNF_EV
+ SM_AUTOANSMTACT_EXPIRY_EV
+ 7)Ôö¼ÓAP_MMIA_CAUSEQUERYREQ_EV, AP_MMIA_CAUSEQUERYCNF_EV
+ ɾ³ýAP_MMIA_SMSABORTMOREQ_EV/AP_MMIA_ABORTSEARCHPLMNREQ_EV
+
+76 2009.9.10 ºÎ½¨Î° 1)Ôö¼ÓLTEÖÆʽÏÂÏà¹ØµÄʼþºÅ
+ ½»¶ 2)½«AP_MMIA_EVENT_UICC_ENDºêÖµÔö¼Ó1
+
+77 2009.9.16 ÓÈ±ó ½«SIG_CODE.HÖÐÔÀ´²¿·ÖSDLÏûÏ¢£¨ÕâЩÏûÏ¢µÄÔ´ºÍÄ¿Ç°Ä£¿é¶¼¸ÄΪÁËÆÕͨÈÎÎñ£©µÄ¶¨Ò壬¸ÄΪÆÕͨÈÎÎñÏûÏ¢µÄ¶¨Òå
+
+78 2009.9.27 ÍõС½ø ΪʵÏÖ´æ´¢¹ÜÀí¹¦ÄÜÔö¼ÓÈçÏÂÏûÏ¢:
+ AP_MMIA_SMSCPMSTESTREQ_EV,AP_MMIA_SMSZMENAREQ_EV,AP_MMIA_SMSCPMSTESTCNF_EV,
+ AP_MMIA_CPBSTESTREQ_EV,AP_MMIA_CPBRSETENDCNF_EV,AP_MMIA_CPBSTESTCNF_EV,
+ AP_MMIA_PBPREFMSGSTOREQ_EV,AP_MMIA_PBPREFMSGSTOTESTREQ_EV,AP_MMIA_PBTPMRUPDATEREQ_EV,
+ AP_MMIA_PBMEMCAPAREQ_EV,AP_MMIA_PBMTPARAIND_EV,AP_MMIA_PBEMERNUMLISTIND_EV,
+ AP_MMIA_PBSTOSETREQ_EV,AP_MMIA_PBSTOTESTREQ_EV,AP_MMIA_PBFINDINDEXENDCNF_EV,
+ AP_MMIA_PBPREFMSGSTOCNF_EV,AP_MMIA_PBPREFMSGSTOTESTCNF_EV,AP_MMIA_PBCOMMONCNF_EV ,
+ AP_MMIA_PBINITCMPLTIND_EV,AP_MMIA_ZPBICIND_EV,
+
+79 2009.9.28 ΤÓñÕä ±ÜÃâ3GÖ÷ģʽÏ£¬¸ø³öGAPºó£¬ÓÖ·¢ÆðËæ»ú½ÓÈë¹ý³Ì¶øµ¼ÖµÄÉäƵͬÇÀ¶øÔö¼ÓµÄÏûÏ¢:
+ CUMAC_URRCAMEASSUSPENDREQ_EV
+ CUMAC_URRCAMEASRESUMEREQ_EV
+ P_GSM_RACH_ACTIVE_CNF_EV
+80 2009.9.28 ½ª²¨ Ôö¼ÓUSIRÖÜÆÚÐÔ½ÓÊÕϵͳÐÅÏ¢µÄ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ:
+ USIR_TIMER_R_EXPIRY_EV
+
+81 2009.9.28 ³Â¹â»ª 1)AP-MMIA SMSÏûÏ¢ºÅ¶¨Ò壬Ôö¼Ó
+ AP_MMIA_CPMSTESTREQ_EV
+ AP_MMIA_CPMSTESTCNF_EV
+ AP_MMIA_SMSZPBICIND_EV
+82 2009.9.28 ½¯Õ×´º 1)Ôö¼ÓUMM/GSMA½Ó¿ÚÏûÏ¢UMMAS_TBFRELEASEIND_EV
+ 2)Ôö¼ÓUMM¶¨Ê±Æ÷ÏûÏ¢UMM_TLIST_EXPIRY_EV
+
+83 2009.9.28 ½»¶ 1¡¢Ôö¼Ó»ñÈ¡PSDEVÊý¾ÝʼþºÅ
+ GVAR_UICC_DEV_GETREQ_EV
+ GVAR_UICC_DEV_GETCNF_EV
+ 2¡¢Ôö¼Ó¹Ø¿¨È·ÈÏÏûÏ¢£ºAP_UICC_PWROFFCNF_EV
+ 3¡¢È¡Ïû¹Ø¿¨¶¨Ê±Æ÷ÏûÏ¢£ºUICC_TIMER_EXPIRY_EV
+84 2009.9.29 ½»¶ 1¡¢Ôö¼ÓPBʼþºÅ
+ AP_MMIA_PBSTOTESTCNF_EV
+85 2009.9.30 ʯ×ÚÀ¤ 1¡¢AP-MMIA¼äʼþºÅÒÑʹÓÃÁË510¸ö£¬ÐèÔö¼ÓAP_MMIA_EVENT_BASEµÄ¿Õ¼ä£¬´Ó500£>600
+
+86 2009.10.19 ÑîÔÊ 1¡¢ Ôö¼ÓMM¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺 MM_TWRRR_EXPIRY_EV
+87 2009.10.27 Ç®¿¡ 1)Ϊ֧³ÖEGPRS,Ôö¼Ó2GÍø²àÄ£ÄâʼþºÅNGMAC_NGRLC_EPDAN_IND_EV,
+ NGRLC_NGRLC_PUAN_REQ_EV,NGRLC_FILL_DATA_QUEUE_REQ_EV,L1SIMU_NGRLC_DATA_IND_EV
+88 2009.10.27 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+89 2009.11.09 ÑîÔÊ 1¡¢Ôö¼ÓÁËMMIAºÍUMMÖ®¼äÔö¼ÓSYSCONFIGÏà¹ØÏûÏ¢ºê¶¨Ò壺
+ MMIAUMM_SYSCONFIGREQ_EV¡¢MMIAUMM_COMMONCNF_EV£»
+ 2¡¢Ôö¼ÓÁËUMMºÍASÖ®¼äϵͳÅäÖÃÏûÏ¢ºê¶¨Ò壺
+ UMMAS_UPDATESYSCONFIGREQ_EV ¡£
+90 2009.11.12 ½ª²¨/Ëﳤ½ ×Óϵͳ·½°¸ÐÞ¸Ä
+ 1.USIR_TBCCHMOD_EXPIRY_EV,UCSR_TBARGSMCELL_EXPIRY_EV
+ 2.URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨ÒåÖÐÔö¼ÓÏûÏ¢ºÅ:
+ URRC_FUNC_RELSCCPCHSTOPMACREQ_EV
+ URRC_FUNC_RESUMEFACHCFGREQ_EV
+91 2009.11.17 ³Â¹â»ª
+ MMIA£SMSÏûÏ¢ºÅ¶¨ÒåÖÐÐÂÔö£ºMMIASMS_COMMONCNF_EV
+
+92 2009.11.17 ÍõС½ø ËæEÐУ¬Ôö¼ÓʼþºÅ:
+ AP_MMIA_CCMTCRSP_EV,AP_MMIA_CONNIND_EV,AP_MMIA_ORIGIND_EV,
+ AP_MMIA_CONFIND_EV,AP_MMIA_CENDIND_EV,MMIACC_DISCCNF_EV
+
+93 2009.11.18 ÑîÎÄÇ¿ Ôö¼ÓEDGEÖ§³ÖµÄÏà¹ØʼþºÅ:
+ TOOL_NGRLC_MODE_CFG_REQ_EV£¬NGRLC_TOOL_UL_DATABLOCK_IND_EV £¬
+ TOOL_NGRLC_DUMMYBLOCK_REQ_EV £¬DOWNLINK_DUMMY_BLOCK_REQ_EV£¬
+ TOOL_NGRLC_DOWNLINKBLOCK_REQ_EV
+94 2009.12.14 ÑîÔÊ Ôö¼Ó¼à¿ØÑ°ºôµÄ¶¨Ê±Æ÷ÏûÏ¢ºÅ:(CQNJ00137720)
+ GMM_TPAGE_EXPIRY_EV, MM_TWPGR_EXPIRY_EV;
+
+95 2009.12.16 ÍõС½ø 1)Ôö¼ÓËæEÐÐÏà¹ØʼþºÅ:
+ MMIACC_CLOSEVOICECHNLIND_EV,MMIACC_OPENVOICECHNLIND_EV,AP_MMIA_PBSFINDINDEXCNF_EV
+ AP_MMIA_PBSFINDINDEXENDCNF_EV,AP_MMIA_PBSEDITCNF_EV,AP_MMIA_PBSCPBRTESTCNF_EV,
+ AP_MMIA_PBSCPBWTESTCNF_EV,AP_MMIA_PBCNUM_CNF,AP_MMIA_PBCLCKSTATUSCNF_EV
+ AP_MMIA_PBSFINDINDEXREQ_EV,AP_MMIA_PBSEDITREQ_EV,AP_MMIA_PBCNUM_REQ
+ AP_MMIA_PBCLCKSETREQ_EV,AP_MMIA_PBSCPBRTESTREQ_EV,AP_MMIA_PBSCPBWTESTREQ_EV
+ AP_MMIA_PBUICCOKIND_EV,AP_MMIA_SCPBRSETCNF_EV ,AP_MMIA_SCPBRSETENDCNF_EV
+ AP_MMIA_SCPBRTESTCNF_EV,AP_MMIA_SCPBWTESTCNF_EV ,AP_MMIA_CNUMCNF_EV
+ AP_MMIA_SCPBRSETREQ_EV ,AP_MMIA_SCPBRTESTREQ_EV,AP_MMIA_SCPBWTESTREQ_EV
+ AP_MMIA_SCPBWSETREQ_EV ,AP_MMIA_CNUMREQ_EV ,AP_UICC_CRSM_CNF_EV
+ AP_UICC_COMMONCNF_EV,
+ 2)ÐÞ¸ÄPB,UICCʼþºÅ·¶Î§Öµ:
+ AP_MMIA_PB_RSP_EVENT,AP_MMIA_EVENT_PB_END
+ AP_MMIA_EVENT_UICC_END,AP_UICC_EVENT_END
+
+96 2009.12.07 ³ÂÎÄ Ôö¼Ó¶ÁдIMEIµÄʼþºÅTEST_SET_NV_DATA_IMEI_EV
+ Ôö¼ÓCRSMÃüÁîʼþºÅAP_UICC_CRSM_REQ_EV
+ Ôö¼ÓUICCÄ£¿éµÄͨÓÃʼþºÅ AP_UICC_COMMONCNF_EV
+
+97 2010.01.05 ΤÓñÕä Ôö¼ÓURRCINTRA_GETSERVCELLINFO_EV,ÒÔ±ãÔÚMSGTRACEÖÐÏÔʾʵʱСÇøÐÅÏ¢
+
+98 2010.01.08 Ëïºóɽ Ôö¼ÓPDIµãµÆºÍÏúÁ¿Í³¼Æ¶¨Ê±Æ÷³¬Ê±Ê¼þºÅ¶¨Ò壺
+ PDI_SWITCHLEDTIMER_EXPIRY_EV£¬
+ PDI_WAITDNSACKTIMER_EXPIRY_EV£¬
+ PDI_WAITZSSACKTIMER_EXPIRY_EV£¬
+
+99 2010.01.09 ÍõС½ø 1)Ôö¼ÓÏúÁ¿Í³¼ÆÏà¹ØʼþºÅ:
+ AP_MMIA_SELL_STAT_SWITCHSETREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYREQ_EV,AP_MMIA_SELL_STAT_UDPINFOQUERYREQ_EV
+ AP_MMIA_SELL_STAT_TESTSENDREQ_EV,AP_MMIA_SELL_STAT_DOMAINSETREQ_EV,AP_MMIA_SELL_STAT_DOMAINQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_CRCSETREQ_EV,AP_MMIA_SELL_STAT_CRCQUERYREQ_EV,AP_MMIA_SELL_STAT_DEBUGSETREQ_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYREQ_EV,AP_MMIA_SELL_STAT_PORTSETREQ_EV,AP_MMIA_SELL_STAT_PORTQUERYREQ_EV,
+ AP_MMIA_SELL_STAT_TRITYPEQUERYREQ_EV,AP_MMIA_SELL_STAT_DNSCNTQUERYREQ_EV,AP_MMIA_SELL_STAT_SWITCHQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_UDPINFOQUERYCNF_EV,AP_MMIA_SELL_STAT_DOMAINQUERYCNF_EV,AP_MMIA_SELL_STAT_CRCQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DEBUGQUERYCNF_EV,AP_MMIA_SELL_STAT_PORTQUERYCNF_EV,AP_MMIA_SELL_STAT_TRITYPEQUERYCNF_EV,
+ AP_MMIA_SELL_STAT_DNSCNTQUERYCNF_EV,MMIASM_CIDDEACTIND_EV,MMIAPDI_SELLSTAT_STARTSENDPACKETIND_EV,
+ MMIAPDI_SELLSTAT_ABORTIND_EV,MMIA_SELLSTAT_ONEPDP_EXPIRY_EV,MMIA_SELLSTAT_SUMPDP_EXPIRY_EV,
+ MMIA_SELLSTAT_REG_EXPIRY_EV
+ ÐÞ¸ÄAP_MMIA_UICC_RSP_EVENT£¬AP_MMIA_EM_RSP_EVENT
+ 2) Ôö¼ÓZIMGE,ZGIIDFʼþºÅ
+ AP_MMIA_ZIMGREQ_EV,AP_MMIA_ZGIIDFREQ_EV,AP_MMIA_ZIMGCNF_EV,AP_MMIA_ZGIIDFCNF_EV
+ 3)´æ´¢ÁоÙÏûÏ¢µÄ֪ͨÏûÏ¢
+ AP_MMIA_PBCPBRIND_EV,AP_MMIA_PBCPBFIND_EV,AP_MMIA_PBSCPBRIND_EV,AP_MMIA_PBCMGLIND_EV
+
+100 2010.01.21 ʯ×ÚÀ¤ ½«UMCR-UPHY¸ÄΪUMACÉÏÏÂÐÐÁ½¶Î£¬Í¬Ê±½«ÏÂÁÐÏûÏ¢IDµÄ»ùµØÖ·¶¨Òå´ÓUMCR-UPHY¸ÄΪUMAC_DL-UPHY£º
+ P_QUALITY_MEAS_REQ_EV
+ P_UE_INTERNAL_MEAS_REQ_EV
+ P_QUALITY_MEAS_IND_EV
+ P_UE_INTERNAL_MEAS_IND_EV
+
+101 2010.02.05 ³ÂÎÄ Ôö¼ÓUICCʼþºÅ
+ UICC_CARDDETECT_EXPIRY_EV
+ AP_UICC_UICCUNSYNCIND_EV
+
+102 2010.02.20 ÕÅÅô³Ì Ôö¼ÓL1TʼþºÅ
+ P_ABORT_FREQ_SCAN_CNF_EV,P_ABORT_CELL_SEARCH_CNF_EV,P_BCH_RELEASE_CNF_EV,
+ P_CAMPON_A_CELL_CNF_EV,P_CHECK_RF_IND_EV£¨´¦ÀíÉäƵ³åÍ»£©,P_DPCH_CFG_FINAL_EV£¨¸ÃÏûÏ¢²»·¢µ½DPRAM£©,
+ P_DPCH_REL_CNF_EV,P_REL_SCCPCH_CNF_EV,P_STOP_PAGING_CNF_EV,P_STOP_CBS_CNF_EV
+ P_REL_HSDPA_CNF_EV,P_REL_HSUPA_CNF_EV,P_ACTIVE_IND_EV£¨´¦Àí¼¤»îʱ¼äµ½£©
+ P_RACH_PRCEDURE_CNF_EV,P_ERUCCH_PRCEDURE_CNF_EV
+
+103 2010.02.20 YANGYUN ÐÞ¸ÄÖÆʽ¼äÖØÑ¡£¬Ìí¼ÓʼþºÅ£º
+ UMMAS_CELLRESSTARTIND_EV
+
+104 2010.03.09 ʯ×ÚÀ¤ ÐÞ¸ÄL1TµÄÈýÌõÏûÏ¢ID£º
+ P_DPCH_CFG_FINAL_EV¸ÄΪP_L1_RESOURCE_CFG_FINAL_EV
+ P_RACH_PRCEDURE_CNF_EV¸ÄΪP_RACH_PROCEDURE_CNF_EV
+ P_ERUCCH_PRCEDURE_CNF_EV¸ÄΪP_ERUCCH_PROCEDURE_CNF_EV
+
+101 2010 .03.11 ׿Խ/ºÎ« Ôö¼ÓÏûÏ¢£º
+ URRCINTRA_GETNCELLINFO_EV
+ MSGTRACEPS_CELLDISPLAYREQ_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+
+102 2010 .03.12 ËïȪ Ôö¼ÓÏûÏ¢£º
+ MMIASS_USSDCANCELREQ_EV
+
+103 2010 .03.17 ³Â¹â»ª Ôö¼ÓSMS¶¨Ê±Æ÷ʼþºÅ£º
+ SMS_TWSI_EXPIRY_EV
+
+104 2010.3.30 ×ÞÑÞ Ôö¼Ó2GÏÂTCHÊÍ·ÅʱGSMAÉϱ¨¸øCCµÄÏûÏ¢
+ GMMAS_CCTCHRELIND_GSM_EV
+
+105 2010 .04.04 ½ª²¨ ÐÞ¸ÄÁбí¹ý³Ìʱ³¤Ïà¹ØÐÞ¸Ä
+ ½«PS_UMMAS_ABORTPLMNREQ_EV ÐÞ¸ÄΪ UMMAS_STOPPLMNLISTREQ_EV
+ ½«UMMAS_ABORTCNF_EV ÐÞ¸ÄΪ UMMAS_ABORTHPPLMNCNF_EV
+ Ôö¼Ó³¬Ê±ÏûÏ¢: UMM_TPLMNLIST_EXPIRY_EV
+
+106 2010 .04.06 ½ª²¨ Ôö¼ÓURRCÄÚ²¿Ê¼þºÅ£º
+ URRCINTRA_SENDBUFESTREQ_EV
+ URRCINTRA_ABORTCCOREQ_EV
+
+107 2010 .04.13 ½ª²¨ Ð޸ı»BAR´¦ÀíÏà¹Ø£¬Ôö¼ÓÁ½¸öʼþºÅ
+ URRCINTRA_BARRESUMEIND_EV
+ UCSR_TBARFREQ_EXPIRY_EV
+
+108 2010 .04.23 ½»¶ ÐÞ¸ÄSUBMODE,Ôö¼ÓʼþºÅ
+ MMIAAS_SUBMODEIND_EV
+
+ 109 2010 .04.24 ËÕá° Ôö¼ÓUMAC-ULÏòUMAC-DL֪ͨÏÂÐÐÅäÖõı仯
+ CUMAC_ACTDLCFG_EV
+
+110 2010.04.29 ½¯Õ×´º Ôö¼ÓUMM¶ÔMMIAËÑÍøÇëÇóµÄ»Ø¸´£¬Ê¼þºÅ
+ MMIAUMM_SEARCHPLMNCNF_EV
+
+111 2010.04.30 ½¯Õ×´º ɾ³ý UMM_TPROC_EXPIRY_EV
+ Ôö¼Ó UMM_TUICCINIT_EXPIRY_EV
+ UMM_TCAMP_EXPIRY_EV
+ UMM_TDETACH_EXPIRY_EV
+
+ 112 2010 .05.04 ʯ×ÚÀ¤ Ôö¼ÓR7Ö§³Ö
+
+ 113 2010.05.14 Éòº® Ôö¼ÓGSMA֪ͨUCSR2GפÁô³É¹¦µÄָʾ
+ URRCGRR_GSMCAMPSUCCIND_EV
+
+ 114 2010.05.20 ʯ×ÚÀ¤ UICCÏûÏ¢ÒѾ³¬³öÔÓеÄÇø¼ä£¬Õ¼ÓÃÁËÆäËûÄ£¿éµÄÏûÏ¢Çø¼ä£¬µ÷ÕûUICCµÄÏûÏ¢Çø¼ä
+
+115 2010.05.22 ÑîÔÊ Ôö¼ÓCS¡¢PS¸½×Å״̬²éѯÏûÏ¢
+ MMIAUMM_CGATTQUERYREQ_EV
+ MMIAUMM_ZATTQUERYREQ_EV
+ MMIAUMM_CGATTQUERYCNF_EV
+ MMIAUMM_ZATTQUERYCNF_EV
+
+116 2010.05.25 ÑîÔÊ Ôö¼ÓUMM֪ͨGMMÖÆʽ¸ü¸Ä³É¹¦ÏûÏ¢
+ UMM_RATCHNIND_EV
+
+ 117 2010 .05.24 ÍõС½ø Ôö¼ÓAP_MMIA_ESMTFADTESTREQ_EV
+ AP_MMIA_ESMTFADTESTCNF_EV
+
+ 118 2010 .05.29 ³ÂÎÄ Ôö¼Ó£º
+ AP_UICC_ACTIVEORDEACTIVEFILEREQ_EV¡¢AP_UICC_ACTIVEORDEACTIVEFILECNF_EV
+
+119 2010.06.07 ʯ×ÚÀ¤ ÐÞ¸ÄÉϱ¨MSGTRACE·þÎñСÇøºÍÁÚÇøµÄ·½Ê½
+ Ôö¼Ó£ºMSGTRACEPS_SCELLINFOIND_EV£¨·þÎñСÇøÐÅÏ¢£©¡¢MSGTRACEPS_NCELLINFOIND_EV£¨ÁÚÇøÐÅÏ¢£©
+ ɾ³ýÔÓеÄÏûÏ¢£º
+ URRCINTRA_GETSERVCELLINFO_EV
+ GRR_GETSCELL_INFO_EV
+ GRR_CELLINFOLISTIND_EV
+ URRCINTRA_GETNCELLINFO_EV
+
+120 2010.06.08 ÍõС½ø ΪUSATÃüÁîÔÚ90 00ʱÔö¼ÓÖ÷¶¯Éϱ¨ÏûÏ¢
+ AP_UICC_NOPROCNOTIFYIND_EV, AP_MMIA_USAT_NOPROCNOTIFYIND_EV
+
+121 2010.06.08 ʯ×ÚÀ¤ ½«RRAT_RXSTAT_IND¡¢RRMI_RXSTAT_IND¡¢RR_EM_HO_INFO_IND¡¢RR_EM_CELL_INFO_IND
+ ÒƵ½PSEVENT.HÖÐÈ¥
+121 2010.07.02 ÍõÀò£¨Ó¦¸ßÏè148604ÒªÇóÐ޸ģ© Ôö¼Ó
+ P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV¡¢
+
+122 2010.07.08 ʯ×ÚÀ¤ ½«P_RESEL_GSMCELL_START_REQ_EV¡¢P_RESEL_GSMCELL_START_CNF_EVÌ滻Ϊ
+ P_TD_RF_REL_REQ_EV¡¢P_TD_RF_REL_CNF_EV
+ ½«P_RESEL_GSMCELL_SUCC_REQ_EV¡¢P_RESEL_GSMCELL_SUCC_CNF_EVºÍ
+ P_TD_CLOSE_REQ_EV¡¢P_TD_CLOSE_IND_EVÌ滻Ϊ
+ P_TD_RESET_REQ_EV¡¢P_TD_RESET_CNF_EV
+ ÐÂÔöP_TD_RF_RESUME_REQ¡¢P_ABORT_GSM_GAP_CNF_EV
+
+123 2010.07.08 ¸ßÏè È¥³ýÏûÏ¢¶¨ÒåP_INTER_FREQ_BLIND_MEAS_IND_EV
+
+124 2010 .07.10 ¹Ë±¦³É Ôö¼Ó£º
+ SM_PDCP_HCMODIND_EV
+
+125 2010.07.10 ΤÓñÕä Ôö¼ÓRRCÄÚ²¿Ê¼þºÅ£ºURRCINTRA_CHANGECAMPONTYPE_EV CSR֪ͨ
+ MCR ÈÎÒâפÁôתºÏÊÊפÁô»òÕßÊǺÏÊÊתÈÎÒâ
+
+126 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ MMIAESM_ABORTREQ_EV
+
+127 2010.07.10 ÕÔÕñ»Ôɾ³ýÏûÏ¢MMIAESM_MTEPSBEARERACT_CNF_EV
+
+128 2010.07.10 ÍõС½øÔö¼Ó £º
+ AP_UICC_EFSTATUSQUERYREQ_EV, AP_UICC_EFSTATUSMODIFYREQ_EV
+ AP_UICC_EFSTATUSQUERYCNF_EV,AP_UICC_EFSTATUSMODIFYCNF_EV
+
+129 2010.07.10 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢:
+ AP_MMIA_PBCHGINDEXIND_EV
+ AP_MMIA_CHGINDEXIND_EV
+
+130 2010.07.10 ÕÔÕñ»ÔΪ×Û²âÔö¼ÓÏûÏ¢AP_MMIA_AUTOSTARTREQ_EV
+
+131 2010.08.18 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢AP_MMIA_CGEQOSSETREQ_EV¡¢AP_MMIA_CGEQOSQUERYREQ_EV
+ AP_MMIA_CGEQOSQUERYCNF_EV¡¢AP_MMIA_CGEQOSRDPREQ_EV
+ AP_MMIA_CGEQOSRDPCNF_EV¡¢MMIAESM_QUERYPDPADDRCNF_EV
+ ɾ³ýÏûÏ¢MMIAESM_ABORTREQ_EV¡¢AP_MMIA_ESMQOSQUERYREQ_EVºÍAP_MMIA_ESMQOSQUERYCNF_EV
+ µ÷ÕûMMIAºÍATIÏûÏ¢Çø¼ä
+
+132 2010.08.26 ÑîÔÊ Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATELTEACT_EV¡¢MMIAUMM_SETLTEACT_REQ_EV
+
+133 2010.09.13 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_MMIA_ZEACTSETREQ_EV¡¢AP_MMIA_ZEACTREADREQ_EVºÍ
+ AP_MMIA_ZEACTREADCNF_EV
+
+134 2010.09.14 ³Â¹â»ª Ôö¼ÓÏûÏ¢GMMAS_SAPI3RELIND_EV
+
+135 2010.09.25 ÍõС½ø ½â¾ö֪ͨSTMËø¿¨ºÍ½âËø£¬Ôö¼ÓÏûÏ¢AP_UICC_CARDLOCKSTATUSIND_EV
+
+136 2010.09.27 ÀîÎľ² Ôö¼Ó¡¢µ÷ÕûLTEÏà¹ØÏûÏ¢
+
+137 2010.10.18 Ëﳤ½ È¥µôÏûÏ¢ºÅ£ºP_CBS_NODRX_REQ_EV¡¢ P_CBS_DRX_REQ_EVµÄ¶¨Ò壻
+ ºóÃæµÄÏûÏ¢µÄʼþºÅͬʱǰÒÆ£¬ÓУºP_ADD_MODIFY_CBS_REQ_EV¡¢P_STOP_CBS_REQ_EV¡¢P_L1_RESOURCE_CFG_FINAL_EV¡¢
+ P_ADD_HSUPA_REQ_EV¡¢P_REL_HSUPA_REQ_EV¡¢P_PLCCH_ADD_MODIFY_REQ_EV
+
+137 2010.10.28 ΤÓñÕä Ôö¼ÓÏûÏ¢UMCR_TBSIC_EXPIRY_EVÖ§³ÖTD϶ÔGSMСÇøͬ²½ÐÅÏ¢µÄÓÐЧÆÚά»¤
+138 2010.10.29 ÁõÒí Ôö¼ÓÏûÏ¢£ºUMMAS_UPDATESCANUEBANDFG_EV¡¢UMMAS_SCANUEBANDIND_EV
+ ɾ³ýÏûÏ¢£ºUCSR_TFREQSCAN_EXPIRY_EV
+
+139 2010.11.05 YANGYUN Ôö¼ÓUMM_CELLNOCHANGEIND_EV
+
+140 2010.11.15 YANGYUN Ôö¼Ó CM_RRCRELIND_EVÏûÏ¢
+
+141 2010.11.29 ÀîÎľ² ÐÞ¸ÄESM_EPDCP_EVENT_BASEµÄºê¶¨Òå
+
+142 2010.11.30 ÍõС½ø ½â¾ö¿¨³õʼ»¯¹ý³ÌÖйػú»ØÏÔ´íÎóÎÊÌ⣬Ôö¼ÓÏûÏ¢ AP_UICC_PWROFFIND_EV
+ PSDEVÐ޸ķ½°¸£¬Ôö¼ÓÏûÏ¢ AP_UICC_WRITEITEMIND_EV,AP_UICC_UPDATEITEMREQ_EV,AP_UICC_UPDATEITEMCNF_EV
+
+143 2010.12.1 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢GVAR_ATMEM_DEV_GETREQ_EV¡¢GVAR_ATMEM_DEV_GETCNF_EV¡¢GVAR_NV_DEV_GETREQ_EV¡¢
+ GVAR_NV_DEV_GETCNF_EV
+
+144 2010.12.15 ʷѧºì ɾ³ýROHCµÄ¶¨Ê±Æ÷ÏûÏ¢ROHC_FO2IRTIMER_EXPIRY_EV¡¢ROHC_SO2IRTIMER_EXPIRY_EV£¬
+ Ôö¼ÓÒ»¸öÓÉSO¡¢FOµ½IRµÄ¶¨Ê±Æ÷ÏûÏ¢£ºROHC_IRTIMER_EXPIRY_EV
+
+145 2010.12.30 Ëﳤ½ µ¥¶ÀµÄСÇø¸üйý³Ì£¬ÊÕµ½Á½ÌõTI²»Í¬µÄCUCÏûÏ¢µÄ´¦Àí£¬Ðèɾ³ý£º
+ URRCINTRA_ABORTCFGREQ_EV
+
+146 2010.12.31 ׿±Ø²¨ CQNJ00240340 PSEVENT.HÖÐÓÐЩʼþºÅ¶¨ÒåËæ×Å°æ±¾µÄÑݽøÒѾ²»ÔÙʹÓÃ
+
+147 2010.12.31 ÍõС½ø ΪÔö¼Ó¿¨SEARCH¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢ AP_UICC_PREPERSONRECSEARCHREQ_EV,AP_UICC_PREPERSNRECSRCHCNF_EV
+
+148 2011.1.28 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢MMIASM_DISCONNECTREQ_EV¡¢AP_MMIA_DISCONNECTREQ_EV
+
+149 2011.1.30 ׿±Ø²¨ EC 614000686090 ½«MMIA£SMÏûÏ¢ºÅ¶¨Òå°´ÊÇ·ñ
+ ¶ÔÓ¦ATÃüÁî·ÖÀ࣬µ÷ÕûMMIASM_ABORTREQ_EVµÈ3ÌõÏûÏ¢µÄÈ¡Öµ
+150 2011.2.11 ÍõС½ø Ôö¼ÓÏûÏ¢AP_UICC_VERIFYPIN2REQ_EV£¬AP_UICC_VERIFYPIN2CNF_EV
+
+151 2011.01.25 ÕÔÕñ»ÔÔö¼ÓÏûÏ¢
+ AP_MMIA_CAOCSETREQ_EV ¡¢AP_MMIA_CAOCQRYREQ_EV¡¢AP_MMIA_CACMQRYREQ_EV¡¢AP_MMIA_CAMMQRYREQ_EV
+ AP_MMIA_CPUCQRYREQ_EV¡¢AP_MMIA_CCWEQRYREQ_EV¡¢AP_MMIA_CACMSETREQ_EV¡¢AP_MMIA_CAMMSETREQ_EV
+ AP_MMIA_CPUCSETREQ_EV¡¢AP_MMIA_CCWESETREQ_EV¡¢AP_MMIA_CAOCSETCNF_EV¡¢AP_MMIA_CAOCQRYCNF_EV
+ AP_MMIA_CACMQRYCNF_EV¡¢AP_MMIA_CAMMQRYCNF_EV¡¢AP_MMIA_CPUCQRYCNF_EV¡¢AP_MMIA_CCWEQRYCNF_EV
+ AP_MMIA_CCCMIND_EV¡¢AP_MMIA_CCWVIND_EV¡¢MMIACC_CCMQUERYREQ_EV¡¢MMIACC_CCMQUERYCNF_EV
+ MMIACC_CCWVIND_EV¡¢MMIACC_NOTIFYAOCTIMERIND_EV
+
+152 2011.03.01 ÕÔÕñ»Ô Ôö¼ÓÏûÏ¢AP_UICC_ZPUKREQ_EV¡¢AP_MMIA_ZPUKREQ_EV
+
+153 2011.3.2 ÍõС½ø Ôö¼Ó¼Æ·Ñ¹¦ÄÜ£¬Ôö¼ÓÏûÏ¢AP_UICC_INCREASEACMFAILIND_EV£¬
+ AP_UICC_INCREASEREQ_EV£¬AP_UICC_RESETACMREQ_EV
+ ¼Æ·Ñ¹¦ÄÜYUZHIMING²¹³ä CC_TACMUPD_EXPIRY_EV ,CC_TCDUR_EXPIRY_EV
+
+154 2011.3.10 ZHANGCHONG ͬ²½LTEÐÞ¸Ä
+
+155 2011.3.16 ʯ×ÚÀ¤ ÃüÃûÐÞ¸Ä
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼ÓGSM PS HOÏûÏ¢id
+ 2£©Ôö¼Ó¶àÄ£Ïà¹ØÏûÏ¢idºÍASCÏà¹ØÏûÏ¢
+
+156 2011.3.16 ʯ×ÚÀ¤
+ 1£©Ôö¼Ó¿ìËÙ˯ÃßÏûÏ¢CPDCP_SCRI_IND_EV/CPDCP_ULDATA_TRANSFER_REQ_EV
+
+157 2011.04.02 ÕÔÕñ»Ô
+ 1) ΪR9Éý¼¶Ôö¼ÓÏûÏ¢
+
+158 2011.04.23 ÕÔÕñ»Ô
+ Õë¶ÔUICCÓÅ»¯£¬É¾³ýÎÞÓõÄÏûÏ¢AP_MMIA_UICC_INFO_REQ_EV ¡¢
+ AP_MMIA_UICC_INFO_CNF_EV¡¢AP_MMIA_PIN_STATE_IND_EV
+
+159 2011.05.03 ÕÔÕñ»ÔΪ3GÃûƬ¼ÐÔö¼ÓÏûÏ¢AP_MMIA_ZCPBQ_SET_REQ_EV¡¢AP_MMIA_ZCPBQ_QUERY_REQ_EV
+ AP_MMIA_ZEER_READ_REQ_EV¡¢AP_MMIA_ZCPBQ_SET_CNF_EV¡¢AP_MMIA_ZCPBQ_QUERY_CNF_EV
+ AP_MMIA_ZEER_READ_CNF_EV¡¢AP_MMIA_PB_READ_CAPA_REQ_EV¡¢AP_MMIA_PB_READ_SET_NUM_REQ_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_REQ_EV¡¢AP_MMIA_PB_READ_CAPA_CNF_EV¡¢AP_MMIA_PB_READ_SET_NUM_CNF_EV¡¢
+ AP_MMIA_PB_READ_LAST_EXT_ERR_CNF_EV
+160 2011.05.31 ʷѧºì
+ Ôö¼ÓROHCv2¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¶Î,Ôö¼ÓROHCv2_T_IR_EXPIRY_EVÏûÏ¢ºÅ
+
+161 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼Ó´¦Àí+ZIMIµÄÏûÏ¢AP_MMIA_SET_IMSI_REQ_EV
+
+162 2011.06.16 ËÎÑÇÅô
+ Ôö¼ÓGMM¼à¿ØMSÖ÷¶¯ÇëÇóÊÍ·ÅÁ´½Ó¶¨Ê±Æ÷Z_GMM_Twrel³¬Ê±µÄÏûÏ¢GMM_T_WREL_EXPIRY_EV
+ EC614000821119£ºGMMÄ£¿éÊÍ·ÅRRCÁ¬½ÓÔö¼ÓÎÕÊÖ¹ý³Ì£¬Ôö¼Ó¶¨Ê±Æ÷Twrel¼à¿Ø´Ë¹ý³Ì£¬Í¬Ê±ÐèÒªÔö¼Ó¶¨Ê±Æ÷³¬Ê±ÏûÏ¢
+163 2011.06.20 ¹ù·å
+ EC614000815619£ºCM²ãÔÚUMM»»Íø¹ý³ÌÖÐÓÐÒµÎñÁ÷³Ì£¬²»¶ÏµÄ·¢ÆðCM_EST£»Í¨¹ý¶¨Ê±Æ÷À´¿ØÖÆÖØ·¢´ÎÊý
+
+ 164 2011.06.14 ÕÔÕñ»Ô
+ Ôö¼ÓÏûÏ¢AP_MMIA_CS_SRV_IND_EV
+
+165 2011.06.30 Ëﳤ½Ôö¼ÓPA+Éý¼¶ÐÞ¸Ä
+ 1£©URBC_UPHY_RSP_EVENTÓëURBC_UPHY_EVENT_BASEÖ®¼äµÄÆ«ÒÆÓÉ20±äΪ30£»
+ 2£©Ôö¼ÓÏûÏ¢ºÅCSCI_UNRECOVER_ERR_EV£¬URRC_EFACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_REQ_EV£¬CUMAC_HSPA_EPCH_CFG_REQ_EV£¬
+ CUMAC_UPDATE_ERNTI_REQ_EV£¬CUMAC_FACH_CFG_IND_EV£¬CUMAC_CELL_RESEL_CNF_EV£¬P_HSPA_PLUS_FACH_REQ_EV£¬P_HSPA_PLUS_PCH_REQ_EV
+ P_HSPA_PLUS_FACH_REL_REQ_EV£¬P_HSPA_PLUS_PCH_REL_REQ_EV£¬P_EFACH_UPDATE_RNTI_REQ_EV£¬P_CELL_RESEL_REQ_EV£¬P_CELL_RESEL_CNF_EV£¬P_SYNC_CMD_RESP_EV,
+ P_HSPA_PLUS_FACH_REL_CNF_EV,P_HSPA_PLUS_FACH_REL_CNF_EV
+ 3£©P_DL_DPCH_SETUP_MODIFY_CNF_EV¸ÄÃûΪP_DL_RL_SETUP_MODIFY_CNF_EV
+
+ 166 2011.7.1 ¹Ë±¦³ÉÔö¼ÓÄ£ÄâPSIÏûÏ¢SIMULPSI_CONFIG_EV
+
+ 167 2011.7.7 ÕÔÕñ»ÔÔö¼Ó¶ÔCSÑ°ºôµÄÓ¦´ðÏûÏ¢AP_MMIA_CS_SRV_RSP_EV
+ 168 2011.7.15 ÕÅÅô³ÌÔö¼ÓÖ§³ÖLTE±³¾°ËÑË÷¹¦ÄÜÐÂÔöµÄʼþºÅ
+ AP_MMIA_BGPLMNSEL_SETREQ_EV¡¢AP_MMIA_BGPLMNSEL_QUERYCNF_EV¡¢AP_MMIA_BGPLMNSEL_QUERYREQ_EV
+ MMIA_UMM_BGPLMNSEL_REQ_EV
+ UMM_ASC_TRY_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_REQ_EV¡¢UMM_ASC_ABORT_BGPLMN_CNF_EV¡¢UMM_ASC_TRY_BGPLMN_REJ_EV¡¢UMM_ASC_TRY_BGPLMN_CNF_EV
+ ASC_LTE_TRY_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_REQ_EV¡¢ASC_LTE_ABORT_BGPLMN_CNF_EV¡¢ASC_LTE_TRY_BGPLMN_REJ_EV¡¢ASC_LTE_TRY_BGPLMN_CNF_EV
+169 2011.7.18 Ëﳤ½ Õë¶Ô614000878724 ɾ³ýÈçÏÂÏûÏ¢ºÅ
+ AS_LTE_TD_CSHO_REQ_EV¡¢AS_LTE_TD_CSHO_CNF_EV¡¢AS_LTE_TD_CSHO_REJ_EV
+170 2011.7.28 ½ª²¨ Õë¶Ô614000920283 Ôö¼ÓÈçÏÂÏûÏ¢ºÅ
+ ASC_LTE_LOCK_CELL_REQ_EV¡¢ASC_LTE_UNLOCK_CELL_REQ_EV¡¢ASC_LTE_LOCK_CELL_CNF_EV
+171 2011.8.2 ÅËÀÚ Ôö¼ÓÏûÏ¢ºÅUURLC_PDCP_DATA_IND_EV
+172 2011.8.2 Ëﳤ½ ÏûÏ¢ºÅ¶¨ÒåÖظ´ÁË£¬ÐèҪɾ³ýÏûÏ¢ºÅCUMAC_RESEL_REQ_EV£¬CUMAC_RESEL_IND_EV
+173 2011.8.15 ³Â¹â»ªÔö¼ÓCBSÏûÏ¢ºÅCBS_ASC_CMAS_NOTIFY_IND_EV
+174 2011.8.17 ¿µÊé½ÜÔö¼ÓCSGÏûÏ¢ºÅEURRC_CSG_PROXIMITY_IND_EV
+175 2011.8.23 ¿µÊé½Üɾ³ýLTE_P_SWITCH_RF_REQ_EV,LTE_P_START_PAGING_REQ_EV,LTE_P_SWITCH_RF_CNF_EV
+ Ôö¼ÓLTE_P_SLEEP_TIME_IND_EV£¬LTE_P_WAKEUP_REQ_EV
+176 2011.8.23 ÕÔÕñ»ÔΪCMMB/×¼FR/Refresh/·þÎñÁбí/CCOͳ¼ÆÔö¼ÓÏûÏ¢AP_MMIA_MB_AUTH_REQ_EV¡¢
+ AP_MMIA_MB_CELL_ID_REQ_EV¡¢AP_MMIA_PSEUDO_FR_SET_REQ_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_REQ_EV¡¢
+ AP_MMIA_REFRESH_REQ_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_REQ_EV¡¢AP_MMIA_MB_AUTH_CNF_EV ¡¢
+ AP_MMIA_MB_CELL_ID_CNF_EV¡¢AP_MMIA_PSEUDO_FR_QUERY_CNF_EV¡¢AP_MMIA_CARD_SRV_LIST_QRY_CNF_EV¡¢
+ MSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV
+177 2011.8.24 ΤÓñÕäÔö¼Ólte gap±¨¸æ¸øtrs
+178 2011.8.25 ÑîÔÊÔö¼ÓESM_EMM_EMERGENCY_PDN_ONLY_IND_EV,EMM_ESM_DETACH_NORMAL_IND_EV
+179 2011.8.25 ÑÔö¼ÓESM_UMM_LOCAL_DEACT_IND_EV
+180 2011.8.25 ׿±Ø²¨Ôö¼ÓCM_SM_DEACT_NON_EMERGENCY_EV
+181 2011.8.29 ½ª²¨Ôö¼ÓMSGTRACEPS_CELLRESORCCOCOUNT_REQ_EV¡¢MSGTRACEPS_CELLRESORCCO_IND_EV¡¢MMIA_AS_EM_CELLRESORCCOCOUNT_REQ_EV¡¢
+ ASC_LTE_CMAS_NOTIFY_IND_EV¡¢EUSIR_T_ETWS_EXPIRY_EV¡¢EUSIR_T_CMAS_EXPIRY_EV
+ ÐÞ¸ÄEURRC_ETWS_INFO_EV Ϊ EURRC_WARNING_NOTIFY_INFO_EV
+182 2011.8.29 ÓȺ£Ó¢ refresh Ôö¼Ó AP_UICC_REFRESH_REQ_EV AP_UICC_DEACTEND_IND_EV AP_UICC_FILECHANGEEND_IND_EV AP_UICC_FILECHANGE_IND_EV
+183 2011.9.15 ½ª²¨Ôö¼ÓEURRC_SI_END_FOR_HO_EV
+184 2011.9.15 ÍõÖ¾Ôö¼ÓENBRRC_PROXIMITY_RPT_EV
+185 2011.9.16 Ðì¿¡Ôö¼ÓGRRº¯Êý½Ó¿Ú
+186 2011.9.16 Ëﳤ½ÉêÇëÔö¼ÓENBRRC_UE_INFO_REQ_EV¡¢ENBRRC_UE_INFO_RSP_EV
+187 2011.9.26 ð¿¡µ÷ÕûGRR¶¨Ê±Æ÷ÏûÏ¢ºÅ·¶Î§
+
+188 2011.10.12 lh ɾ³ýÁÚÇøÉϱ¨ºÍ·þÎñСÇøÉϱ¨ÏûÏ¢½Ó¿Ú£¬Ôö¼ÓLTEСÇøÐÅÏ¢Éϱ¨Ê¼þºÅ
+189 2011.10.18 ÕÔÕñ»ÔΪLTE±³¾°ËÑË÷Ôö¼ÓÏûÏ¢AP_MMIA_LTEBGPLMN_TESTREQ_EVºÍAP_MMIA_LTEBGPLMN_TESTCNF_EV
+
+190 2011.10.19 ºÎ«Ôö¼Ó¶¨Ê±Æ÷ʼþºÅT_DISABLE_UMTS_MEAS_EV,T_DISABLE_LTE_MEAS_EV
+191 2011.11.3 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SMSOVERIPNET_SETREQ_EV¡¢AP_MMIA_SMSOVERIPNET_QUERYREQ_EV
+ AP_MMIA_SMSOVERIPNET_QUERYCNF_EV¡¢MMIA_UMM_SMSOVERIPNET_SETREQ_EV
+ EC614001128873
+
+192 2011.11.4 ÕÔÕñ»ÔÔö¼ÓËæeÐа汾IccIdµÄÉϱ¨ºÍ»ú¿¨»¥ËøÐèÇó:
+ Ôö¼ÓÏûÏ¢ZPS_ApUicc_ToReadCardReq_Ev¡¢ZPS_ApMmia_Iccid_Ind_EV¡¢ZPS_ApMmia_USAT_ToReadCardReq_Ev
+
+193 2011.11.4 ÕÔÕñ»ÔÔö¼ÓAP_MMIA_SM_DEACT_IND_EV, EC614001103133
+194 2011.11.22 ÓȺ£Ó¢Ôö¼ÓTEST_SET_NV_DATA_SPCLFUNC_EV £¬EC 614001151291
+
+195 2011.12.2 ÁºÐ¡º®Ôö¼ÓÏûÏ¢AP_MMIA_CALL_LINE_SET_REQ_EV¡¢AP_MMIA_CALL_LINE_QRY_REQ_EVºÍAP_MMIA_CALL_LINE_QUERY_CNF_EV 614001181454
+ R9 U115¸£ÖÝ°æ±¾Ò»»úË«ºÅÐèÇó ºÏÈë
+
+196 2011.12.26 EC617001225651,MMIAÔö¼ÓUE InfoµÄÉϱ¨,ÕÔÕñ»ÔÔö¼ÓÏûÏ¢ROADTEST_UEINFO_REQ_EV¡¢ROADTEST_UEINFO_CNF_EV
+197 2011.12.27 ËÎÑÇÅôÐÂÔöPDCP(RABM)֪ͨGMM¹ØÓÚRABÐÅÏ¢
+
+198 2012.1.5 EC617001233064Ôö¼ÓÄ£ÄâPDI·¢Ë͸øGSMAµÄÏûÏ¢PDI_GSM_DATA_REQ_EV
+199 2012.1.11 ¹Ë±¦³ÉÐÂÔöÈýÌõÏûÏ¢ÓÃÓÚÓû§ÃæÌØÊâÐÅÁî¸ú×Ù
+200 2012.03.12 ΤÓñÕä Ôö¼ÓÏûÏ¢P_DETECT_CELL_INFO_IND_EV
+201 2012.03.27 ³ÂΰÐÂÔöLTE_P_DLSCH_DATA_TRACE_EVºÍLTE_P_ULSCH_DATA_TRACE_EVÓÃÓÚEPHYºÍEUMAC¼äµÄÉÏÏÂÐÐÊý¾ÝÐÅÁî¸ú×Ù
+
+202 2012.04.16 ºÎ«ÐÂÔöGRR_RRC_POWEROFF_IND_EVÏûÏ¢ÓÃÀ´Í¨ÖªGRRC(Èí)¹Ø»ú
+203 2012.05.08 Ëﳤ½ÐÂÔöASC_TD_LOSTCOV_CAMP_SUCC_IND_EVÏûÏ¢ÓÃÓÚÆäËüÖÆʽ¶ªÊ§¸²¸ÇÖØÑ¡µ½TD³É¹¦ºó£¬ASC֪ͨUCER±íʾ¿çÖÆʽÖØÑ¡³É¹¦¡£
+204 2012.05.10 ³ÂΰÐÂÔöLTE_P_MAC_SR_REQ_EVÓÃÓÚTMTÐÅÁî¸ú×ÙSRµÄ·¢ËÍ
+205 2012.05.10 Ëﳤ½ÐÂÔöP_UL_PHY_CH_CTRL_REQ_EvÏûÏ¢ÓÃÓÚ½øÐÐUl-DTXÅäÖÃ?
+206 2012.07.15 ÁºÐ¡º®ÐÂÔöMMIA_EUCSR_LTEINFO_REQ_EVµÈÏûÏ¢ÓÃÓÚatÃüÁîÉϱ¨×ÓÖ¡ÅäÖÃÐÅÏ¢
+207 2012.08.02 ÍõС½ø EC617001662142£¬ Ôö¼Ó
+ AP_UICC_CCHO_REQ_EV,AP_UICC_CCHC_REQ_EV,AP_UICC_CGLA_REQ_EV,AP_UICC_CRSM_REQ_EV,
+ AP_UICC_CCHO_CNF_EV,AP_UICC_CGLA_CNF_EV,AP_UICC_CRSM_CNF_EV,AP_UICC_USAT_FETCH_IND_EV,
+208 2012.11.06 W GROUPÐ޸ģºÐÞ¸Äpsenent end,ÔÚÔÀ´µÄ»ù´¡ÉÏÔö¼ÓÁË8000.W·ÇÎïÀí²ãÏûϢλÓÚLTEÏûÏ¢Ö®ºó£¬ÔÚ16384--end
+ WµÄÎïÀí²ãÏûÏ¢·ÅÔÚps+6500---ps+7000µÄµØ·½£¬¶ÔÓÚTW¹²ÓÃÏûÏ¢²ÉÓÃÐÞ¸ÄÃüÃûµÄ·½Ê½TD¸ÄΪUTRA
+209 2012.11.21 ÍõС½ø EC617001860117£¬ ÖÇÄÜ»úÈȲå°ÎÐèÇó£¬Ôö¼ÓÏûÏ¢
+ AP_UICC_MOVECARD_IND_EV AP_UICC_INSERTCARD_IND_EV
+210 2013.10.18 ΤÓñÕäÔö¼ÓATIÓëASµÄÏûÏ¢MMIA_AS_B39_INFO_IND_EV(EUMCR,UMCR->ATI)ºÍMMIA_AS_B39_INFO_REQ_EV(ATI->GRR)
+ *****************************************************************************/
+#ifndef Z_EVENTDEF_H
+#define Z_EVENTDEF_H
+
+#include "atipsevent.h"
+
+/*=====================================================================================================================
+ ÏûÏ¢Çø¼ä£º
+
+ ||______________________|__________UPHY__________|_____________________|_____________________||
+ PS_BASE UPHY_BASE(+6K) UPHY_BASE(+6.5K) PS_LTE_BASE(+10K) PS_END(PS_LTE_END)
+ =====================================================================================================================*/
+
+/*GSM SDLÏûϢʼþºÅ·¶Î§£¬¾ßÌåµÄGSMʼþºÅ¶¨ÒåÔÚSIG_CODE.HÖУ¬½öÔÚpstestÖÐʹÓÃ*/
+#define EVENT_PS_GSM_SDL_BASE (DWORD)0x00010000
+#define EVENT_PS_GSM_SDL_END (DWORD)0xff7d0003
+
+/*LTEʼþºÅ·¶Î§*/
+#define EVENT_PS_LTE_BASE (DWORD)(EVENT_PS_BASE + 10000)
+#define EVENT_PS_LTE_END (DWORD)(EVENT_PS_BASE + 16383)
+
+/*WCDMAʼþºÅ·¶Î§*/
+#define EVENT_PS_W_BASE (DWORD)(EVENT_PS_BASE + 16384)
+#define EVENT_PS_W_END (DWORD)EVENT_PS_END
+/**************************************************PHY msg base-end start********************************************************/
+/*Õⲿ·ÖID²»ÄÜËæÒâÐ޸ģ¬»áÓ°Ïì½Ó¿ÚÖеÄmsgidµÄÖµ£¬´Ó¶øʹÎïÀí²ãµ¼ÖÂÎóÅÐÏûÏ¢*/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define PS_UPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6000)
+/*ÐÒéÕ»ÓëWCDMAÎïÀí²ãÏûÏ¢·¶Î§.TDÓëWÎïÀí²ãÏûÏ¢·¶Î§¹Ì¶¨ÔÚ6000µ½7000.ÆäÖÐÇ°500ÓÃÓÚTD£¬ºó500ÓÃÓÚW*/
+#define PS_WPHY_EVENT_BASE (DWORD)(EVENT_PS_BASE + 6500)
+
+/*ÐÒéÕ»ÓëLTEÎïÀí²ãÏûÏ¢·¶Î§£¬±£Ö¤ÎïÀí²ãºÍÐÒéÕ»IDÆðʼֵµÍ8λȫÁ㣬±£Ö¤Ç¿ÖÆת»»ÎªBYTEΪÕý³£Öµ*/
+#define LTE_PS_EUPHY_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 2544)
+#define LTE_PS_EUPHY_RSP_EVENT (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 60)
+#define LTE_PS_EUPHY_EVENT_END (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 120)
+/**************************************************PHY msg base-end end********************************************************/
+
+/*UMM¡¢MM¡¢GMMÄÚ²¿ÏûÏ¢·¶Î§(50)*/
+#define UMM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2570)
+#define UMM_EVENT_END (DWORD)(UMM_EVENT_BASE + 49)
+
+/*SS/SMS/SM/CC/PDCPÓëMM/GMMµÄÏûÏ¢·¶Î§(50)*/
+#define CM_MM_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2620)
+#define CM_MM_EVENT_END (DWORD)(CM_MM_EVENT_BASE + 49)
+
+/*UMMºÍASCµÄÏûÏ¢·¶Î§ (100)*/
+#define UMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2670)
+#define UMM_ASC_RSP_EVENT (DWORD)(UMM_ASC_EVENT_BASE + 50)
+#define UMM_ASC_EVENT_END (DWORD)(UMM_ASC_EVENT_BASE + 99)
+
+/*GMMºÍASCµÄÏûÏ¢·¶Î§(100) */
+#define GMM_ASC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2770)
+#define GMM_ASC_RSP_EVENT (DWORD)(GMM_ASC_EVENT_BASE + 50)
+#define GMM_ASC_EVENT_END (DWORD)(GMM_ASC_EVENT_BASE + 99)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_UAS_EVENT_BASE (DWORD)(EVENT_PS_BASE + 2870)
+#define ASC_UAS_RSP_EVENT (DWORD)(ASC_UAS_EVENT_BASE + 50)
+#define ASC_UAS_EVENT_END (DWORD)(ASC_UAS_EVENT_BASE + 99)
+
+/*ASCºÍGSM ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_GAS_EVENT_BASE (DWORD)(ASC_UAS_EVENT_END + 1)
+#define ASC_GAS_RSP_EVENT (DWORD)(ASC_GAS_EVENT_BASE + 50)
+#define ASC_GAS_EVENT_END (DWORD)(ASC_GAS_EVENT_BASE + 99)
+
+/*ASCºÍLTE ASµÄÏûÏ¢·¶Î§(100) */
+#define ASC_EUAS_EVENT_BASE (DWORD)(ASC_GAS_EVENT_END + 1)
+#define ASC_EUAS_RSP_EVENT (DWORD)(ASC_EUAS_EVENT_BASE + 50)
+#define ASC_EUAS_EVENT_END (DWORD)(ASC_EUAS_EVENT_BASE + 99)
+
+/*ASCºÍ¸÷AS¹«¹²µÄÏûÏ¢·¶Î§(100) */
+#define ASC_AS_EVENT_BASE (DWORD)(ASC_EUAS_EVENT_END + 1)
+#define ASC_AS_EVENT_END (DWORD)(ASC_AS_EVENT_BASE + 149)
+
+/*CBSºÍRRCµÄÏûÏ¢·¶Î§(30)*/
+#define CBS_RRC_EVENT_BASE (DWORD)(EVENT_PS_BASE + 3320)
+#define CBS_RRC_RSP_EVENT (DWORD)(CBS_RRC_EVENT_BASE + 20)
+#define CBS_RRC_EVENT_END (DWORD)(CBS_RRC_EVENT_BASE + 29)
+
+/*GMMºÍSNDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_SNDCP_EVENT_BASE (DWORD)(CBS_RRC_EVENT_END + 1)
+#define GMM_SNDCP_EVENT_END (DWORD)(GMM_SNDCP_EVENT_BASE + 24)
+
+/*GMMºÍPDCPµÄÏûÏ¢·¶Î§(25)*/
+#define GMM_PDCP_EVENT_BASE (DWORD)(GMM_SNDCP_EVENT_END + 1)
+#define GMM_PDCP_EVENT_END (DWORD)(GMM_PDCP_EVENT_BASE + 24)
+
+/*SMºÍPDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_PDCP_EVENT_BASE (DWORD)(GMM_PDCP_EVENT_END + 1)
+#define SM_PDCP_RSP_EVENT (DWORD)(SM_PDCP_EVENT_BASE + 25)
+#define SM_PDCP_EVNET_END (DWORD)(SM_PDCP_EVENT_BASE + 49)
+
+/*SMºÍSNDCPµÄÏûÏ¢·¶Î§(50)*/
+#define SM_SNDCP_EVENT_BASE (DWORD)(SM_PDCP_EVNET_END + 1)
+#define SM_SNDCP_RSP_EVENT (DWORD)(SM_SNDCP_EVENT_BASE + 20)
+#define SM_SNDCP_EVENT_END (DWORD)(SM_SNDCP_EVENT_BASE + 49)
+
+/*PDIºÍGSMAµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_GSMA_EVENT_BASE (DWORD)(SM_SNDCP_EVENT_END + 1)
+#define PDI_GSMA_RSP_EVENT (DWORD)(PDI_GSMA_EVENT_BASE + 10)
+#define PDI_GSMA_EVENT_END (DWORD)(PDI_GSMA_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(20)*/
+#define PDI_PDCP_EVENT_BASE (DWORD)(PDI_GSMA_EVENT_END + 1)
+#define PDI_PDCP_RSP_EVENT (DWORD)(PDI_PDCP_EVENT_BASE + 10)
+#define PDI_PDCP_EVENT_END (DWORD)(PDI_PDCP_EVENT_BASE + 19)
+
+/*PDIºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_URLC_EVENT_BASE (DWORD)(PDI_PDCP_EVENT_END + 1)
+#define PDCP_URLC_EVENT_END (DWORD)(PDCP_URLC_EVENT_BASE + 9)
+
+/*TAFºÍCCÏûÏ¢·¶Î§(50)*/
+#define CC_TAF_EVENT_BASE (DWORD)(PDCP_URLC_EVENT_END + 1)
+#define CC_TAF_EVENT_END (DWORD)(CC_TAF_EVENT_BASE + 49)
+
+/*UMMºÍCBSÏûÏ¢·¶Î§(50)*/
+#define UMM_CBS_EVENT_BASE (DWORD)(CC_TAF_EVENT_END + 1)
+#define UMM_CBS_RSP_EVENT (DWORD)(UMM_CBS_EVENT_BASE + 20)
+#define UMM_CBS_EVENT_END (DWORD)(UMM_CBS_EVENT_BASE + 49)
+
+/*SCIºÍURRC/CCÏûÏ¢·¶Î§(30)*/
+#define AP_SCI_EVENT_BASE (DWORD)(UMM_CBS_EVENT_END + 1)
+#define AP_SCI_EVENT_END (DWORD)(AP_SCI_EVENT_BASE + 29)
+
+/*URLCºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define URLC_URRC_EVENT_BASE (DWORD)(AP_SCI_EVENT_END + 1)
+#define URLC_URRC_RSP_EVENT (DWORD)(URLC_URRC_EVENT_BASE + 30)
+#define URLC_URRC_EVENT_END (DWORD)(URLC_URRC_EVENT_BASE + 59)
+
+/*UMACºÍURRCµÄÏûÏ¢·¶Î§(70)*/
+#define UMAC_URRC_EVENT_BASE (DWORD)(URLC_URRC_EVENT_END + 1)
+#define UMAC_URRC_RSP_EVENT (DWORD)(UMAC_URRC_EVENT_BASE + 40)
+#define UMAC_URRC_EVENT_END (DWORD)(UMAC_URRC_EVENT_BASE + 69)
+
+/*UMAC-UL/DLºÍUMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define UMAC_UMAC_EVENT_BASE (DWORD)(UMAC_URRC_EVENT_END + 1)
+#define UMAC_UMAC_EVENT_END (DWORD)(UMAC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1T_URRC_EVENT_BASE (DWORD)(UMAC_UMAC_EVENT_END + 1)
+#define L1T_URRC_RSP_EVENT (DWORD)(L1T_URRC_EVENT_BASE + 30)
+#define L1T_URRC_EVENT_END (DWORD)(L1T_URRC_EVENT_BASE + 59)
+
+/*PDCPºÍURRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_URRC_EVENT_BASE (DWORD)(L1T_URRC_EVENT_END + 1)
+#define PDCP_URRC_RSP_EVENT (DWORD)(PDCP_URRC_EVENT_BASE + 30)
+#define PDCP_URRC_EVENT_END (DWORD)(PDCP_URRC_EVENT_BASE + 59)
+
+/*URLCºÍUMACµÄÏûÏ¢·¶Î§(20)*/
+#define URLC_UMAC_EVENT_BASE (DWORD)(PDCP_URRC_EVENT_END + 1)
+#define URLC_UMAC_EVENT_END (DWORD)(URLC_UMAC_EVENT_BASE + 19)
+
+/*L1TºÍUMACµÄÏûÏ¢·¶Î§(10)*/
+#define UMAC_L1T_EVENT_BASE (DWORD)(URLC_UMAC_EVENT_END + 1)
+#define UMAC_L1T_EVENT_END (DWORD)(UMAC_L1T_EVENT_BASE + 9)
+
+/*URRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define URRC_EVENT_BASE (DWORD)(UMAC_L1T_EVENT_END + 1)
+#define URRC_EVENT_END (DWORD)(URRC_EVENT_BASE + 99)
+
+/*L1TÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1T_EVENT_BASE (DWORD)(URRC_EVENT_END + 1)
+#define L1T_EVENT_END (DWORD)(L1T_EVENT_BASE + 19)
+
+/*ÎïÀí²ãÊÊÅä²ãÖ®¼äL1T/L1EÏûÏ¢·¶Î§(30)£¨²»°üº¬L1G£¬ÓëL1G½»»¥µÄÏûϢȫ²¿ÊÇSDLÏûÏ¢£¬¶¨ÒåÔÚsig_code.hÖУ©*/
+#define L1A_EVENT_BASE (DWORD)(L1T_EVENT_END + 1)
+#define L1A_EVENT_END (DWORD)(L1A_EVENT_BASE + 29)
+
+/*ÐÒéÕ»ÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§(530)*/
+#define UMM_TIMER_EVENT_BASE (DWORD)(MMIA_TIMER_EVENT_END + 1)
+#define UMM_TIMER_EVENT_END (DWORD)(UMM_TIMER_EVENT_BASE + 49)
+
+#define MM_TIMER_EVENT_BASE (DWORD)(UMM_TIMER_EVENT_END + 1)
+#define MM_TIMER_EVENT_END (DWORD)(MM_TIMER_EVENT_BASE + 29)
+
+#define GMM_TIMER_EVENT_BASE (DWORD)(MM_TIMER_EVENT_END + 1)
+#define GMM_TIMER_EVENT_END (DWORD)(GMM_TIMER_EVENT_BASE + 29)
+
+#define CC_TIMER_EVENT_BASE (DWORD)(GMM_TIMER_EVENT_END + 1)
+#define CC_TIMER_EVENT_END (DWORD)(CC_TIMER_EVENT_BASE + 49)
+
+#define SMS_TIMER_EVENT_BASE (DWORD)(CC_TIMER_EVENT_END + 1)
+#define SMS_TIMER_EVENT_END (DWORD)(SMS_TIMER_EVENT_BASE + 19)
+
+#define SM_TIMER_EVENT_BASE (DWORD)(SMS_TIMER_EVENT_END + 1)
+#define SM_TIMER_EVENT_END (DWORD)(SM_TIMER_EVENT_BASE + 19)
+
+#define SS_TIMER_EVENT_BASE (DWORD)(SM_TIMER_EVENT_END + 1)
+#define SS_TIMER_EVENT_END (DWORD)(SS_TIMER_EVENT_BASE + 9)
+
+#define CBS_TIMER_EVENT_BASE (DWORD)(SS_TIMER_EVENT_END + 1)
+#define CBS_TIMER_EVENT_END (DWORD)(CBS_TIMER_EVENT_BASE + 9)
+
+#define UICC_TIMER_EVENT_BASE (DWORD)(CBS_TIMER_EVENT_END + 1)
+#define UICC_TIMER_EVENT_END (DWORD)(UICC_TIMER_EVENT_BASE + 19)
+
+#define URRC_TIMER_EVENT_BASE (DWORD)(UICC_TIMER_EVENT_END + 1)
+#define URRC_TIMER_EVENT_END (DWORD)(URRC_TIMER_EVENT_BASE + 79)
+
+#define URLC_TIMER_EVENT_BASE (DWORD)(URRC_TIMER_EVENT_END + 1)
+#define URLC_TIMER_EVENT_END (DWORD)(URLC_TIMER_EVENT_BASE + 19)
+
+#define UMAC_TIMER_EVENT_BASE (DWORD)(URLC_TIMER_EVENT_END + 1)
+#define UMAC_TIMER_EVENT_END (DWORD)(UMAC_TIMER_EVENT_BASE + 19)
+
+#define L1T_TIMER_EVENT_BASE (DWORD)(UMAC_TIMER_EVENT_END + 1)
+#define L1T_TIMER_EVENT_END (DWORD)(L1T_TIMER_EVENT_BASE + 19)
+
+#define PDCP_TIMER_EVENT_BASE (DWORD)(L1T_TIMER_EVENT_END + 1)
+#define PDCP_TIMER_EVENT_END (DWORD)(PDCP_TIMER_EVENT_BASE + 9)
+
+#define ROHCv1_TIMER_EVENT_BASE (DWORD)(PDCP_TIMER_EVENT_END + 1)
+#define ROHCv1_TIMER_EVENT_END (DWORD)(ROHCv1_TIMER_EVENT_BASE + 19)
+
+#define TAF_TIMER_EVENT_BASE (DWORD)(ROHCv1_TIMER_EVENT_END + 1)
+#define TAF_TIMER_EVENT_END (DWORD)(TAF_TIMER_EVENT_BASE + 19)
+
+#define GSMA_TIMER_EVENT_BASE (DWORD)(TAF_TIMER_EVENT_END + 1)
+#define GSMA_TIMER_EVENT_END (DWORD)(GSMA_TIMER_EVENT_BASE + 19)
+
+#define PDI_TIMER_EVENT_BASE (DWORD)(GSMA_TIMER_EVENT_END + 1)
+#define PDI_TIMER_EVENT_END (DWORD)(PDI_TIMER_EVENT_BASE + 19)
+
+#define ROHCv2_TIMER_EVENT_BASE (DWORD)(PDI_TIMER_EVENT_END + 1)
+#define ROHCv2_TIMER_EVENT_END (DWORD)(ROHCv2_TIMER_EVENT_BASE + 19)
+
+#define SCI_TIMER_EVENT_BASE (DWORD)(ROHCv2_TIMER_EVENT_END + 1)
+#define SCI_TIMER_EVENT_END (DWORD)(SCI_TIMER_EVENT_BASE + 9)
+
+#define STM_TIMER_EVENT_BASE (DWORD)(SCI_TIMER_EVENT_END + 1)
+#define STM_TIMER_EVENT_END (DWORD)(STM_TIMER_EVENT_BASE + 9)
+
+#define USAT_TIMER_EVENT_BASE (DWORD)(STM_TIMER_EVENT_END + 1)
+#define USAT_TIMER_EVENT_END (DWORD)(USAT_TIMER_EVENT_BASE + 9)
+
+#define TIMER_EVENT_END (DWORD)USAT_TIMER_EVENT_END
+
+/**************************************************PS msg range end********************************************************/
+
+/**************************************************UPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëTDÎïÀí²ãÏûÏ¢·¶Î§(300)*/
+#define USIR_UPHY_EVENT_BASE (DWORD)PS_UPHY_EVENT_BASE
+#define USIR_UPHY_RSP_EVENT (DWORD)(USIR_UPHY_EVENT_BASE + 20)
+#define USIR_UPHY_EVENT_END (DWORD)(USIR_UPHY_EVENT_BASE + 49)
+
+#define UCSR_UPHY_EVENT_BASE (DWORD)(USIR_UPHY_EVENT_END + 1)
+#define UCSR_UPHY_RSP_EVENT (DWORD)(UCSR_UPHY_EVENT_BASE + 20)
+#define UCSR_UPHY_EVENT_END (DWORD)(UCSR_UPHY_EVENT_BASE + 49)
+
+#define UMCR_UPHY_EVENT_BASE (DWORD)(UCSR_UPHY_EVENT_END + 1)
+#define UMCR_UPHY_RSP_EVENT (DWORD)(UMCR_UPHY_EVENT_BASE + 20)
+#define UMCR_UPHY_EVENT_END (DWORD)(UMCR_UPHY_EVENT_BASE + 49)
+
+#define URBC_UPHY_EVENT_BASE (DWORD)(UMCR_UPHY_EVENT_END + 1)
+#define URBC_UPHY_RSP_EVENT (DWORD)(URBC_UPHY_EVENT_BASE + 30)
+#define URBC_UPHY_EVENT_END (DWORD)(URBC_UPHY_EVENT_BASE + 49)
+
+#define UMAC_UL_UPHY_EVENT_BASE (DWORD)(URBC_UPHY_EVENT_END + 1)
+#define UMAC_UL_UPHY_EVENT_END (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 19)
+
+#define UMAC_DL_UPHY_EVENT_BASE (DWORD)(UMAC_UL_UPHY_EVENT_END + 1)
+#define UMAC_DL_UPHY_EVENT_END (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 29)
+
+/*L1TÓëTDÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1T_UPHY_EVENT_BASE (DWORD)(UMAC_DL_UPHY_EVENT_END + 1)
+#define L1T_UPHY_RSP_EVENT (DWORD)(L1T_UPHY_EVENT_BASE + 20)
+#define L1T_UPHY_EVENT_END (DWORD)(L1T_UPHY_EVENT_BASE + 49)
+
+#define PS_UPHY_EVENT_END (DWORD)L1T_UPHY_EVENT_END
+/**************************************************WPHY msg range start********************************************************/
+/*ÐÒéÕ»ÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define WSIR_WPHY_EVENT_BASE (DWORD)PS_WPHY_EVENT_BASE
+#define WSIR_WPHY_RSP_EVENT (DWORD)(WSIR_WPHY_EVENT_BASE + 20)
+#define WSIR_WPHY_EVENT_END (DWORD)(WSIR_WPHY_EVENT_BASE + 49)
+
+#define WCSR_WPHY_EVENT_BASE (DWORD)(WSIR_WPHY_EVENT_END + 1)
+#define WCSR_WPHY_RSP_EVENT (DWORD)(WCSR_WPHY_EVENT_BASE + 20)
+#define WCSR_WPHY_EVENT_END (DWORD)(WCSR_WPHY_EVENT_BASE + 49)
+
+#define WMCR_WPHY_EVENT_BASE (DWORD)(WCSR_WPHY_EVENT_END + 1)
+#define WMCR_WPHY_RSP_EVENT (DWORD)(WMCR_WPHY_EVENT_BASE + 20)
+#define WMCR_WPHY_EVENT_END (DWORD)(WMCR_WPHY_EVENT_BASE + 49)
+
+#define WRBC_WPHY_EVENT_BASE (DWORD)(WMCR_WPHY_EVENT_END + 1)
+#define WRBC_WPHY_RSP_EVENT (DWORD)(WRBC_WPHY_EVENT_BASE + 30)
+#define WRBC_WPHY_EVENT_END (DWORD)(WRBC_WPHY_EVENT_BASE + 49)
+
+#define WMAC_UL_WPHY_EVENT_BASE (DWORD)(WRBC_WPHY_EVENT_END + 1)
+#define WMAC_UL_WPHY_EVENT_END (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 19)
+
+#define WMAC_DL_WPHY_EVENT_BASE (DWORD)(WMAC_UL_WPHY_EVENT_END + 1)
+#define WMAC_DL_WPHY_EVENT_END (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 29)
+
+/*L1WÓëWÎïÀí²ãÏûÏ¢·¶Î§*/
+#define L1W_WPHY_EVENT_BASE (DWORD)(WMAC_DL_WPHY_EVENT_END + 1)
+#define L1W_WPHY_RSP_EVENT (DWORD)(L1W_WPHY_EVENT_BASE + 20)
+#define L1W_WPHY_EVENT_END (DWORD)(L1W_WPHY_EVENT_BASE + 49)
+
+#define PS_WPHY_EVENT_END (DWORD)L1W_WPHY_EVENT_END
+/**************************************************WPHY msg range end********************************************************/
+
+/**************************************************PS LTE msg range start********************************************************/
+/*EMMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EMM_TIMER_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1)
+#define EMM_TIMER_EVENT_END (DWORD)(EMM_TIMER_EVENT_BASE + 19)
+
+/*ESMÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define ESM_TIMER_EVENT_BASE (DWORD)(EMM_TIMER_EVENT_END + 1)
+#define ESM_TIMER_EVENT_END (DWORD)(ESM_TIMER_EVENT_BASE + 19)
+
+/*EUPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(20)*/
+#define EPDCP_TIMER_EVENT_BASE (DWORD)(ESM_TIMER_EVENT_END + 1)
+#define EPDCP_TIMER_EVENT_END (DWORD)(EPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EURLC_TIMER_EVENT_BASE (DWORD)(EPDCP_TIMER_EVENT_END + 1)
+#define EURLC_TIMER_EVENT_END (DWORD)(EURLC_TIMER_EVENT_BASE + 9)
+
+/*EUMACÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø(10)*/
+#define EUMAC_TIMER_EVENT_BASE (DWORD)(EURLC_TIMER_EVENT_END + 1)
+#define EUMAC_TIMER_EVENT_END (DWORD)(EUMAC_TIMER_EVENT_BASE + 9)
+
+/*EURRCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define EURRC_TIMER_EVENT_BASE (DWORD)(EUMAC_TIMER_EVENT_END + 1)
+
+/*EUCER×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCER_TIMER_EVENT_BASE (DWORD)(EURRC_TIMER_EVENT_BASE + 1)
+#define EUCER_TIMER_EVENT_END (DWORD)(EUCER_TIMER_EVENT_BASE + 19)
+
+/*EUMCR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUMCR_TIMER_EVENT_BASE (DWORD)(EUCER_TIMER_EVENT_END + 1)
+#define EUMCR_TIMER_EVENT_END (DWORD)(EUMCR_TIMER_EVENT_BASE + 19)
+
+/*EUCSR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUCSR_TIMER_EVENT_BASE (DWORD)(EUMCR_TIMER_EVENT_END + 1)
+#define EUCSR_TIMER_EVENT_END (DWORD)(EUCSR_TIMER_EVENT_BASE + 19)
+
+/*EUSIR×ÓÄ£¿é¶¨Ê±Æ÷(20)*/
+#define EUSIR_TIMER_EVENT_BASE (DWORD)(EUCSR_TIMER_EVENT_END + 1)
+#define EUSIR_TIMER_EVENT_END (DWORD)(EUSIR_TIMER_EVENT_BASE + 19)
+
+#define EURRC_TIMER_EVENT_END (DWORD)EUSIR_TIMER_EVENT_END
+
+/*EMMºÍUMMÄ£¿é¼äµÄÏûÏ¢IDºÅ*/
+#define EMM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 200)
+#define EMM_UMM_RSP_EVENT (DWORD)(EMM_UMM_EVENT_BASE + 19)
+#define EMM_UMM_EVENT_END (DWORD)(EMM_UMM_EVENT_BASE + 29)
+
+/*UMMºÍEPDCPÄ£¿éÖ®¼äµÄÏûÏ¢ID */
+#define UMM_EPDCP_EVENT_BASE (DWORD)(EMM_UMM_EVENT_END + 1)
+#define UMM_EPDCP_RSP_EVENT (DWORD)(UMM_EPDCP_EVENT_BASE + 9)
+#define UMM_EPDCP_EVENT_END (DWORD)(UMM_EPDCP_EVENT_BASE + 19)
+
+/* CM²ãºÍESMÄ£¿é¼äÏûÏ¢IDºÅ(ÐÂÔö)*/
+#define CM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 260)
+#define CM_ESM_RSP_EVENT (DWORD)(CM_ESM_EVENT_BASE + 9)
+#define CM_ESM_EVENT_END (DWORD)(CM_ESM_EVENT_BASE + 19)
+
+/* CM²ãºÍEMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define CM_EMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 280)
+#define CM_EMM_RSP_EVENT (DWORD)(CM_EMM_EVENT_BASE + 9)
+#define CM_EMM_EVENT_END (DWORD)(CM_EMM_EVENT_BASE + 19)
+
+/* EMMºÍESMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_EMM_EVENT_BASE (DWORD)(CM_EMM_EVENT_END + 1)
+#define ESM_EMM_RSP_EVENT (DWORD)(ESM_EMM_EVENT_BASE + 19)
+#define ESM_EMM_EVENT_END (DWORD)(ESM_EMM_EVENT_BASE + 29)
+
+/*EMMºÍERRC(CER)Ä£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_ASC_EVENT_BASE (DWORD)(ESM_EMM_EVENT_END + 1)
+#define EMM_ASC_RSP_EVENT (DWORD)(EMM_ASC_EVENT_BASE + 19)
+#define EMM_ASC_EVENT_END (DWORD)(EMM_ASC_EVENT_BASE + 49)
+
+/*EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define EMM_EPDCP_EVENT_BASE (DWORD)(EMM_ASC_EVENT_END + 1)
+#define EMM_EPDCP_RSP_EVENT (DWORD)(EMM_EPDCP_EVENT_BASE + 9)
+#define EMM_EPDCP_EVENT_END (DWORD)(EMM_EPDCP_EVENT_BASE + 19)
+
+/*ESMºÍUMMÄ£¿é¼äÏûÏ¢IDºÅ*/
+#define ESM_UMM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 400)
+#define ESM_UMM_RSP_EVENT (DWORD)(ESM_UMM_EVENT_BASE + 19)
+#define ESM_UMM_EVENT_END (DWORD)(ESM_UMM_EVENT_BASE + 29)
+
+
+/* ESMºÍPDCP Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define ESM_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 430)
+#define ESM_EPDCP_RSP_EVENT (DWORD)(ESM_EPDCP_EVENT_BASE + 9)
+#define ESM_EPDCP_EVENT_END (DWORD)(ESM_EPDCP_EVENT_BASE + 19)
+
+/*EURRCºÍEPDCPÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EPDCP_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 450)
+#define EURRC_EPDCP_RSP_EVENT (DWORD)(EURRC_EPDCP_EVENT_BASE + 25)
+#define EURRC_EPDCP_EVENT_END (DWORD)(EURRC_EPDCP_EVENT_BASE + 49)
+
+/*EURRCºÍEURLCÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EURLC_EVENT_BASE (DWORD)(EURRC_EPDCP_EVENT_END + 1)
+#define EURRC_EURLC_RSP_EVENT (DWORD)(EURRC_EURLC_EVENT_BASE + 19)
+#define EURRC_EURLC_EVENT_END (DWORD)(EURRC_EURLC_EVENT_BASE + 29)
+
+/*EURRCºÍEUMACÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_EUMAC_EVENT_BASE (DWORD)(EURRC_EURLC_EVENT_END + 1)
+#define EURRC_EUMAC_RSP_EVENT (DWORD)(EURRC_EUMAC_EVENT_BASE + 25)
+#define EURRC_EUMAC_EVENT_END (DWORD)(EURRC_EUMAC_EVENT_BASE + 49)
+
+/*EURRCºÍMEL2Ä£¿éÖ®¼äµÄÏûϢʼþ*/
+#define EURRC_MEL2_EVENT_BASE (DWORD)(EURRC_EUMAC_EVENT_END + 1)
+#define EURRC_MEL2_RSP_EVENT (DWORD)(EURRC_MEL2_EVENT_BASE + 4)
+#define EURRC_MEL2_EVENT_END (DWORD)(EURRC_MEL2_EVENT_BASE + 6)
+
+/*SMºÍESMÄ£¿éÖ®¼äµÄÏûϢʼþ*/
+#define SM_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 750) /*Added:KangShuJie*/
+#define SM_ESM_RSP_EVENT (DWORD)(SM_ESM_EVENT_BASE + 25) /*Added:KangShuJie*/
+#define SM_ESM_EVENT_END (DWORD)(SM_ESM_EVENT_BASE + 49) /*Added:KangShuJie*/
+
+/*EURRCÄÚ²¿ÏûϢʼþID*/
+#define EURRC_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1000)
+#define EURRC_EVENT_END (DWORD)(EURRC_EVENT_BASE + 54)
+
+#define EUPDCP_EURLC_EVENT_BASE (DWORD)(EURRC_EVENT_END + 1)
+#define EUPDCP_EURLC_EVENT_END (DWORD)(EUPDCP_EURLC_EVENT_BASE + 4)
+
+/*EURRCºÍL1EÄ£¿éÖ®¼äÏûϢʼþ*/
+#define EURRC_L1E_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1200)
+#define EURRC_L1E_RSP_EVENT (DWORD)(EURRC_L1E_EVENT_BASE + 20)
+#define EURRC_L1E_EVENT_END (DWORD)(EURRC_L1E_EVENT_BASE + 39)
+
+
+#define EUDBG_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1400)
+#define EUDBG_EVENT_END (DWORD)(EUDBG_EVENT_BASE + 19)
+
+#define LPP_ECID_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1450)
+#define LPP_ECID_EVENT_END (DWORD)(EVENT_PS_LTE_BASE + 1499)
+
+/* LTE¼¯³É²âÊÔ¼ÓÈëµÄ²âÊÔÄ£¿éʹÓõÄÏûÏ¢ */
+#define TRS_ESM_EVENT_BASE (DWORD)(EVENT_PS_LTE_BASE + 1500)
+#define TRS_ESM_RSP_EVENT (DWORD)(TRS_ESM_EVENT_BASE + 9)
+#define TRS_ESM_EVENT_END (DWORD)(TRS_ESM_EVENT_BASE + 29)
+
+#define TRS_EMM_EVENT_BASE (DWORD)(TRS_ESM_EVENT_END + 1)
+#define TRS_EMM_RSP_EVENT (DWORD)(TRS_EMM_EVENT_BASE + 5)
+#define TRS_EMM_EVENT_END (DWORD)(TRS_EMM_EVENT_BASE + 29)
+
+#define ENB_EMM_ESM_EVENT_BASE (DWORD)(TRS_EMM_EVENT_END + 1)
+#define ENB_EMM_ESM_RSP_EVENT (DWORD)(ENB_EMM_ESM_EVENT_BASE + 9)
+#define ENB_EMM_ESM_EVENT_END (DWORD)(ENB_EMM_ESM_EVENT_BASE + 19)
+
+#define ENB_RRC_EMM_EVENT_BASE (DWORD)(ENB_EMM_ESM_EVENT_END + 1)
+#define ENB_RRC_EMM_RSP_EVENT (DWORD)(ENB_RRC_EMM_EVENT_BASE + 9)
+#define ENB_RRC_EMM_EVENT_END (DWORD)(ENB_RRC_EMM_EVENT_BASE + 19)
+
+#define ENB_RRC_EVENT_BASE (DWORD)(ENB_RRC_EMM_EVENT_END + 1)
+#define ENB_RRC_RSP_EVENT (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENB_RRC_EVENT_END (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+/* LTE ¼¯³É²âÊÔÊý¾ÝÃæÔö¼ÓµÄÏûÏ¢ÆðʼºêADD BY LIUZHIPENG AT 09-12-28 */
+
+#define ENRRC_ENPDCP_EVENT_BASE (DWORD)(ENB_RRC_EVENT_END + 1)
+#define ENRRC_ENPDCP_RSP_EVENT (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 20)
+#define ENRRC_ENPDCP_EVENT_END (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 44)
+/* EDCP Ó²¼þ¼ÓËÙ½Ó¿ÚÏûÏ¢ */
+#define PS_ENDCP_EVENT_BASE (DWORD)(ENRRC_ENPDCP_EVENT_END + 1)
+#define PS_ENDCP_RSP_EVENT (DWORD)(PS_ENDCP_EVENT_BASE + 9)
+#define PS_ENDCP_EVENT_END (DWORD)(PS_ENDCP_EVENT_BASE + 19)
+
+/* ENPDCPÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENPDCP_TIMER_EVENT_BASE (DWORD)(PS_ENDCP_EVENT_END + 1)
+#define ENPDCP_TIMER_EVENT_END (DWORD)(ENPDCP_TIMER_EVENT_BASE + 19)
+
+/*EURLCÄ£¿é¶¨Ê±Æ÷³¬Ê±ÏûϢʼþºÅ¿ªÊ¼½áÊø*/
+#define ENRLC_TIMER_EVENT_BASE (DWORD)(ENPDCP_TIMER_EVENT_END + 1)
+#define ENRLC_TIMER_EVENT_END (DWORD)(ENRLC_TIMER_EVENT_BASE + 9)
+
+/* ENRRCÓëENRLCµÄÏûÏ¢¿Õ¼ä */
+#define ENRRC_ENRLC_EVENT_BASE (DWORD)(ENRLC_TIMER_EVENT_END + 1)
+#define ENRRC_ENRLC_RSP_EVENT (DWORD)(ENRRC_ENRLC_EVENT_BASE + 9)
+#define ENRRC_ENRLC_EVENT_END (DWORD)(ENRRC_ENRLC_EVENT_BASE + 19)
+/* ENMACÓëEPHYµÄÏûÏ¢¿Õ¼ä*/
+#define ENMAC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENRLC_EVENT_END + 1)
+#define ENMAC_EPHY_RSP_EVENT (DWORD)(ENMAC_EPHY_EVENT_BASE + 9)
+#define ENMAC_EPHY_EVENT_END (DWORD)(ENMAC_EPHY_EVENT_BASE + 19)
+
+#define ENRRC_ENMAC_EVENT_BASE (DWORD)(ENMAC_EPHY_EVENT_END + 1)
+#define ENRRC_ENMAC_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 9)
+#define ENRRC_ENMAC_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 19)
+
+#define ENRRC_EPHY_EVENT_BASE (DWORD)(ENRRC_ENMAC_EVENT_END + 1)
+#define ENRRC_EPHY_RSP_EVENT (DWORD)(ENRRC_EPHY_EVENT_BASE + 9)
+#define ENRRC_EPHY_EVENT_END (DWORD)(ENRRC_EPHY_EVENT_BASE + 19)
+
+#define TRS_EPHY_EVENT_BASE (DWORD)(ENRRC_EPHY_EVENT_END + 1)
+#define TRS_EPHY_RSP_EVENT (DWORD)(TRS_EPHY_EVENT_BASE + 10)
+#define TRS_EPHY_EVENT_END (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+
+#define TRS_ENMAC_EVENT_BASE (DWORD)(TRS_EPHY_EVENT_END + 1)
+#define TRS_ENMAC_RSP_EVENT (DWORD)(TRS_ENMAC_EVENT_BASE + 10)
+#define TRS_ENMAC_EVENT_END (DWORD)(TRS_ENMAC_EVENT_BASE + 19)
+
+#define ENPDI_ENPDCP_EVENT_BASE (DWORD)(TRS_ENMAC_EVENT_END + 1)
+#define ENPDI_ENPDCP_RSP_EVENT (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 10)
+#define ENPDI_ENPDCP_EVENT_END (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 19)
+
+#define TRS_SIMULPDI_EVENT_BASE (DWORD)(ENPDI_ENPDCP_EVENT_END + 1)
+#define TRS_SIMULPDI_RSP_EVENT (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define TRS_SIMULPDI_EVENT_END (DWORD)(TRS_SIMULPDI_EVENT_BASE + 19)
+
+#define TRS_SIMULENPDI_EVENT_BASE (DWORD)(TRS_SIMULPDI_EVENT_END + 1)
+#define TRS_SIMULENPDI_RSP_EVENT (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define TRS_SIMULENPDI_EVENT_END (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 19)
+
+/* =========================================================================
+ TRS --ΪÁËGCF²âÊÔ¶ø¶¨Òå2010/3/3 SHIFANGMING
+=========================================================================*/
+#define LTE_GCF_TRS_EVENT_BASE (DWORD)(TRS_SIMULENPDI_EVENT_END + 1)
+#define LTE_GCF_TRS_RSP_EVENT (DWORD)(LTE_GCF_TRS_EVENT_BASE + 10)
+#define LTE_GCF_TRS_EVENT_END (DWORD)(LTE_GCF_TRS_EVENT_BASE + 19)
+
+#define LTE_GCF_TIMER_EVENT_BASE (DWORD)(LTE_GCF_TRS_EVENT_END + 1)
+#define LTE_GCF_TIMER_EVENT_END (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 19)
+
+
+/*TRSºÍENRLCÄ£¿éÖ®¼äµÄÏûϢʼþ2010/3/1 LIUHUAN*/
+#define TRS_ENRLC_EVENT_BASE (DWORD)(LTE_GCF_TIMER_EVENT_END + 1)
+#define TRS_ENRLC_RSP_EVENT (DWORD)(TRS_ENRLC_EVENT_BASE + 10)
+#define TRS_ENRLC_EVENT_END (DWORD)(TRS_ENRLC_EVENT_BASE + 19)
+
+#define ENPDCP_ENRLC_EVENT_BASE (DWORD)(TRS_ENRLC_EVENT_END + 1)
+#define ENPDCP_ENRLC_EVENT_END (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 9)
+
+//--ENMEL2ÏûϢʼþ
+#define ENMEL2_EVENT_BASE (DWORD)(ENPDCP_ENRLC_EVENT_END + 1)
+#define ENMEL2_RSP_EVENT (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5)
+#define ENMEL2_EVENT_END (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6)
+/**************************************************PS LTE msg range end********************************************************/
+
+
+/**************************************************PS W msg range start********************************************************/
+
+/*WRLCºÍPDCPµÄÏûÏ¢·¶Î§(10)*/
+#define PDCP_WRLC_EVENT_BASE (DWORD)(EVENT_PS_W_BASE + 1)
+#define PDCP_WRLC_EVENT_END (DWORD)(PDCP_WRLC_EVENT_BASE + 9)
+
+
+/*WRLCºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define WRLC_WRRC_EVENT_BASE (DWORD)(PDCP_WRLC_EVENT_END + 1)
+#define WRLC_WRRC_RSP_EVENT (DWORD)(WRLC_WRRC_EVENT_BASE + 30)
+#define WRLC_WRRC_EVENT_END (DWORD)(WRLC_WRRC_EVENT_BASE + 59)
+
+/*WMACºÍWRRCµÄÏûÏ¢·¶Î§(70)*/
+#define WMAC_WRRC_EVENT_BASE (DWORD)(WRLC_WRRC_EVENT_END + 1)
+#define WMAC_WRRC_RSP_EVENT (DWORD)(WMAC_WRRC_EVENT_BASE + 40)
+#define WMAC_WRRC_EVENT_END (DWORD)(WMAC_WRRC_EVENT_BASE + 69)
+
+/*WMAC-UL/DLºÍWMAC-CµÄÏûÏ¢·¶Î§(20)*/
+#define WMAC_WMAC_EVENT_BASE (DWORD)(WMAC_WRRC_EVENT_END + 1)
+#define WMAC_WMAC_EVENT_END (DWORD)(WMAC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define L1W_WRRC_EVENT_BASE (DWORD)(WMAC_WMAC_EVENT_END + 1)
+#define L1W_WRRC_RSP_EVENT (DWORD)(L1W_WRRC_EVENT_BASE + 30)
+#define L1W_WRRC_EVENT_END (DWORD)(L1W_WRRC_EVENT_BASE + 59)
+
+/*PDCPºÍWRRCµÄÏûÏ¢·¶Î§(60)*/
+#define PDCP_WRRC_EVENT_BASE (DWORD)(L1W_WRRC_EVENT_END + 1)
+#define PDCP_WRRC_RSP_EVENT (DWORD)(PDCP_WRRC_EVENT_BASE + 30)
+#define PDCP_WRRC_EVENT_END (DWORD)(PDCP_WRRC_EVENT_BASE + 59)
+
+/*WRLCºÍWMACµÄÏûÏ¢·¶Î§(20)*/
+#define WRLC_WMAC_EVENT_BASE (DWORD)(PDCP_WRRC_EVENT_END + 1)
+#define WRLC_WMAC_EVENT_END (DWORD)(WRLC_WMAC_EVENT_BASE + 19)
+
+/*L1WºÍWMACµÄÏûÏ¢·¶Î§(10)*/
+#define WMAC_L1W_EVENT_BASE (DWORD)(WRLC_WMAC_EVENT_END + 1)
+#define WMAC_L1W_EVENT_END (DWORD)(WMAC_L1W_EVENT_BASE + 9)
+
+/*WRRCÄÚ²¿ÏûÏ¢·¶Î§(100)*/
+#define WRRC_EVENT_BASE (DWORD)(WMAC_L1W_EVENT_END + 1)
+#define WRRC_EVENT_END (DWORD)(WRRC_EVENT_BASE + 99)
+
+/*L1WÄÚ²¿ÏûÏ¢·¶Î§(20)*/
+#define L1W_EVENT_BASE (DWORD)(WRRC_EVENT_END + 1)
+#define L1W_EVENT_END (DWORD)(L1W_EVENT_BASE + 19)
+
+/*ASCºÍUMTS ASµÄÏûÏ¢·¶Î§ (100)*/
+#define ASC_WAS_EVENT_BASE (DWORD)(L1W_EVENT_END + 1)
+#define ASC_WAS_RSP_EVENT (DWORD)(ASC_WAS_EVENT_BASE + 50)
+#define ASC_WAS_EVENT_END (DWORD)(ASC_WAS_EVENT_BASE + 99)
+
+/*WÄÚ¶¨Ê±Æ÷³¬Ê±ÏûÏ¢·¶Î§140()*/
+
+#define WRRC_TIMER_EVENT_BASE (DWORD)(ASC_WAS_EVENT_END + 1)
+#define WRRC_TIMER_EVENT_END (DWORD)(WRRC_TIMER_EVENT_BASE + 79)
+
+#define WRLC_TIMER_EVENT_BASE (DWORD)(WRRC_TIMER_EVENT_END + 1)
+#define WRLC_TIMER_EVENT_END (DWORD)(WRLC_TIMER_EVENT_BASE + 19)
+
+#define WMAC_TIMER_EVENT_BASE (DWORD)(WRLC_TIMER_EVENT_END + 1)
+#define WMAC_TIMER_EVENT_END (DWORD)(WMAC_TIMER_EVENT_BASE + 19)
+
+#define L1W_TIMER_EVENT_BASE (DWORD)(WMAC_TIMER_EVENT_END + 1)
+#define L1W_TIMER_EVENT_END (DWORD)(L1W_TIMER_EVENT_BASE + 19)
+
+/*W²âÊÔÏûÏ¢·¶Î§(40)*/
+
+#define WSIR_TEST_EVENT_BASE (DWORD)(L1W_TIMER_EVENT_END + 1)
+#define WSIR_TEST_EVENT_END (DWORD)(WSIR_TEST_EVENT_BASE + 9)
+
+#define NWRLC_EVENT_BASE (DWORD)(WSIR_TEST_EVENT_END + 1)
+#define NWRLC_EVENT_END (DWORD)(NWRLC_EVENT_BASE + 19)
+
+#define NWMAC_EVENT_BASE (DWORD)(NWRLC_EVENT_END + 1)
+#define NWMAC_EVENT_END (DWORD)(NWMAC_EVENT_BASE + 9)
+
+/*º¯ÊýÐÅÁî¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define WRRC_FUNC_EVENT_BASE (DWORD)(NWMAC_EVENT_END + 1)
+#define WRRC_FUNC_EVENT_END (DWORD)(WRRC_FUNC_EVENT_BASE + 49)
+
+/*º¯Êý·µ»ØÖµ¸ú×ÙÏûÏ¢·¶Î§(50)*/
+#define RRC_FUNC_TRACE_BASE (DWORD)(WRRC_FUNC_EVENT_END + 1)
+#define RRC_FUNC_TRACE_END (DWORD)(RRC_FUNC_TRACE_BASE + 49)
+
+/**************************************************PS W msg range end********************************************************/
+/* ========================================================================
+ CM-MM/GMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 0)
+#define CM_EST_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 1)
+#define CM_REL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 2)
+#define CM_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 3)
+#define CM_CANCEL_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 4)
+#define CM_REEST_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 5)
+#define CM_CMSRV_IND_EV (DWORD)(CM_MM_EVENT_BASE + 6)
+#define CM_IN_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 7)
+#define CM_OUT_FLY_MODE_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 8)
+#define CM_DATA_IND_EV (DWORD)(CM_MM_EVENT_BASE + 9)
+#define CM_RATCHG_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 10)
+#define CM_RATCHG_END_IND_EV (DWORD)(CM_MM_EVENT_BASE + 11)
+#define CM_RRC_REL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 12)
+#define CM_SRVCC_START_IND_EV (DWORD)(CM_MM_EVENT_BASE + 13)
+#define CM_SRVCC_SUCC_IND_EV (DWORD)(CM_MM_EVENT_BASE + 14)
+#define CM_SRVCC_FAIL_IND_EV (DWORD)(CM_MM_EVENT_BASE + 15)
+#define CM_SM_ONLY_ONE_EPDNCON_EV (DWORD)(CM_MM_EVENT_BASE + 16)
+#define CM_ESM_DETACH_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 17)
+#define CM_SM_DEACT_NON_EMERGENCY_EV (DWORD)(CM_MM_EVENT_BASE + 18)
+#define CC_UMM_RETURN_IMS_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 19)
+#define UMM_CC_RETURN_IMS_CNF_EV (DWORD)(CM_MM_EVENT_BASE + 20)
+/*IVSÏ߳̽ÓÊÕÏûÏ¢*/
+#define IVS_DL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 21)
+#define CC_IVS_RESET_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 22)
+#define CC_IVS_MSD_IND_EV (DWORD)(CM_MM_EVENT_BASE + 23)
+/*IVS·¢¸øCC*/
+#define IVS_CC_MSD_REQ_EV (DWORD)(CM_MM_EVENT_BASE + 24)
+#define IVS_CC_MSD_STATE_IND_EV (DWORD)(CM_MM_EVENT_BASE + 25)
+
+#define PSAP_UL_PCM_IND_EV (DWORD)(CM_MM_EVENT_BASE + 26)
+
+/* ========================================================================
+ UMM£MM/GMM/EMMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 0)
+#define UMM_DETACH_REQ_EV (DWORD)(UMM_EVENT_BASE + 1)
+#define UMM_PENDING_REQ_EV (DWORD)(UMM_EVENT_BASE + 2)
+#define UMM_RESUME_REQ_EV (DWORD)(UMM_EVENT_BASE + 3)
+#define UMM_ABORT_REQ_EV (DWORD)(UMM_EVENT_BASE + 4)
+#define UMM_EMERGENCY_UPDATE_REQ_EV (DWORD)(UMM_EVENT_BASE + 5)
+#define UMM_CSEST_REQ_EV (DWORD)(UMM_EVENT_BASE + 6)
+#define UMM_PAGE_IND_EV (DWORD)(UMM_EVENT_BASE + 7)
+#define UMM_CCO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 8)
+#define UMM_HO_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 9)
+#define UMM_CELL_RESEL_START_REQ_EV (DWORD)(UMM_EVENT_BASE + 10)
+#define UMM_LU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 11)
+#define UMM_FAIL_IND_EV (DWORD)(UMM_EVENT_BASE + 12)
+#define UMM_RU_SUCC_IND_EV (DWORD)(UMM_EVENT_BASE + 13)
+#define UMM_DETACH_IND_EV (DWORD)(UMM_EVENT_BASE + 14)
+#define UMM_DETACH_CNF_EV (DWORD)(UMM_EVENT_BASE + 15)
+#define UMM_MM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 16)
+#define UMM_GMM_CURRENT_STATE_IND_EV (DWORD)(UMM_EVENT_BASE + 17)
+#define UMM_EMERGENCY_T3412_EXPIRY_IND_EV (DWORD)(UMM_EVENT_BASE + 18)
+#define UMM_CELL_NO_CHG_IND_EV (DWORD)(UMM_EVENT_BASE + 19)
+#define UMM_CS_EST_REJ_EV (DWORD)(UMM_EVENT_BASE + 20)
+#define UMM_CS_SRV_NOTIFY_IND_EV (DWORD)(UMM_EVENT_BASE + 21)
+#define UMM_CCO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 22)
+#define UMM_HO_END_IND_EV (DWORD)(UMM_EVENT_BASE + 23)
+#define UMM_CELL_RESEL_END_IND_EV (DWORD)(UMM_EVENT_BASE + 24)
+#define UMM_ATTACH_STATE_SYNC_REQ_EV (DWORD)(UMM_EVENT_BASE + 25)
+#define UMM_CHECK_REL_RRC_REQ_EV (DWORD)(UMM_EVENT_BASE + 26)
+#define UMM_PS_CONTEXT_IND_EV (DWORD)(UMM_EVENT_BASE + 27)
+#define UMM_START_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 28)
+#define UMM_STOP_TEMPERATURE_CTRL_REQ_EV (DWORD)(UMM_EVENT_BASE + 29)
+#define UMM_POWEROFF_IND_RV (DWORD)(UMM_EVENT_BASE + 30)
+#define UMM_SWITCH_CARD_END_EV (DWORD)(UMM_EVENT_BASE + 31)
+/* ========================================================================
+ UMM£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_ASC_CAMPON_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 0)
+#define UMM_ASC_CAMPON_ANYCELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 1)
+#define UMM_ASC_UPDATE_PLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 2)
+#define UMM_ASC_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 3)
+#define UMM_ASC_SWITCH_RADIO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 4)
+#define UMM_ASC_TRY_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 5)
+#define UMM_ASC_STOP_PLMN_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 6)
+#define UMM_ASC_PCH_PRE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 7)
+#define UMM_ASC_ABORT_HPPLMN_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 8)
+#define UMM_ASC_UPDATE_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 9)
+#define UMM_ASC_INACTIVE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 10)
+#define UMM_ASC_PAGE_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 11)
+#define UMM_ASC_LOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 12)
+#define UMM_ASC_UNLOCK_CELL_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 13)
+#define UMM_ASC_GSM_SRV_NOTIFY_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 14)
+#define UMM_ASC_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 15)
+#define UMM_ASC_UPDATE_SYSCONFIG_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 16)
+#define UMM_ASC_UPDATE_LTE_ACT_EV (DWORD)(UMM_ASC_EVENT_BASE + 17)
+#define UMM_ASC_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(UMM_ASC_EVENT_BASE + 18)
+#define UMM_ASC_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 19)
+#define UMM_ASC_STOP_CSG_LIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 20)
+#define UMM_ASC_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 21)
+#define UMM_ASC_SYS_CAMP_LTESUBACT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 22)
+#define UMM_ASC_DELFORBIDDENLAILIST_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 23)
+#define UMM_ASC_HPPLMN_END_IND_EV (DWORD)(UMM_ASC_EVENT_BASE + 24)
+#define UMM_ASC_XCELLINFO_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 25)
+#define UMM_ASC_XCELLINFO_ABORT_REQ_EV (DWORD)(UMM_ASC_EVENT_BASE + 26)
+#define UMM_ASC_UPDATE_ECALLMODE_EV (DWORD)(UMM_ASC_EVENT_BASE + 27)
+
+#define UMM_ASC_CELL_INFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 0)
+#define UMM_ASC_NOCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 1)
+#define UMM_ASC_PLMN_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 2)
+#define UMM_ASC_SWITCH_RADIO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 3)
+#define UMM_ASC_CNINFO_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 4)
+#define UMM_ASC_TRY_HPPLMN_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 5)
+#define UMM_ASC_PLMN_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 6)
+#define UMM_ASC_INACTIVE_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 7)
+#define UMM_ASC_HO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 9)
+#define UMM_ASC_CCO_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 10)
+#define UMM_ASC_CELL_RESEL_START_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 11)
+#define UMM_ASC_HO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 12)
+#define UMM_ASC_CCO_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 13)
+#define UMM_ASC_CELL_RESEL_END_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 14)
+#define UMM_ASC_TRY_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 15)
+#define UMM_ASC_ABORT_HPPLMN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 16)
+#define UMM_ASC_LOCK_CELL_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 17)
+#define UMM_ASC_CSG_LIST_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 18)
+#define UMM_ASC_CSG_LIST_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 19)
+#define UMM_ASC_TBF_RELEASE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 20)
+#define UMM_ASC_SCAN_UE_BAND_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 21)
+#define UMM_ASC_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(UMM_ASC_RSP_EVENT + 22)
+#define UMM_ASC_CELL_UPDATE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 23) /*GRR֪ͨUMM×öСÇø¸üÐÂ*/
+#define UMM_ASC_RECONST_PSRES_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 24)
+#define UMM_ASC_SUBMODE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 25)
+#define UMM_ASC_CELL_LOST_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 26)
+#define UMM_ASC_CELL_RECOVERAGE_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 27)
+#define UMM_ASC_XCELLINFO_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 28)
+#define UMM_ASC_XCELLINFO_REJ_EV (DWORD)(UMM_ASC_RSP_EVENT + 29)
+#define UMM_ASC_NEIGCELL_IND_EV (DWORD)(UMM_ASC_RSP_EVENT + 30)
+#define UMM_ASC_SCAN_CNF_EV (DWORD)(UMM_ASC_RSP_EVENT + 31)
+/* ========================================================================
+ MM/GMM/CC£ASCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_ASC_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 0)
+#define GMM_ASC_REL_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 1)
+#define GMM_ASC_DATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 2)
+#define GMM_ASC_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 3)
+#define GMM_ASC_GRR_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 4)
+#define GMM_ASC_GRR_INFO_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 5)
+#define GMM_ASC_LL_ASSIGN_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 6)
+#define GMM_ASC_LL_TRIGGER_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 7)
+#define GMM_ASC_LL_SUSPEND_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 8)
+#define GMM_ASC_LL_RESUME_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 9)
+#define GMM_ASC_LL_UNITDATA_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 10)
+#define GMM_ASC_CLEAN_PEND_EST_REQ_EV (DWORD)(GMM_ASC_EVENT_BASE + 11)
+
+#define GMM_ASC_EST_CNF_EV (DWORD)(GMM_ASC_RSP_EVENT + 0)
+#define GMM_ASC_EST_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 1)
+#define GMM_ASC_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 2)
+#define GMM_ASC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 3)
+#define GMM_ASC_CCSYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 4)
+#define GMM_ASC_PAGE_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 5)
+#define GMM_ASC_DATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 6)
+#define GMM_ASC_SUSPEND_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 7)
+#define GMM_ASC_GSM_CC_SYNC_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 8)
+#define GMM_ASC_CS_RAB_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 9)
+#define GMM_ASC_GSM_CC_TCH_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 10)
+#define GMM_ASC_SAPI3_REL_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 11)
+#define GMM_ASC_SRVCC_START_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 12)
+#define GMM_ASC_SRVCC_END_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 13)
+#define GMM_ASC_LL_UNITDATA_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 14)
+#define GMM_ASC_LL_TRIGGER_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 15)
+#define GMM_ASC_LL_STATUS_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 16)
+#define GMM_ASC_LL_USER_DATA_PRESENT_EV (DWORD)(GMM_ASC_RSP_EVENT + 17)
+#define GMM_ASC_GSM_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 18)
+#define GMM_ASC_UTRA_SM_CURR_BEAR_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 19)/*WCDMA*//*¶ÔÓ¦AS²ãµÄASC_TD_CURR_BEAR_IND_EVºÍASC_W_CURR_BEAR_IND_EV*/
+#define GMM_ASC_PSHO_INFO_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 20) /*LLC֪ͨGMMÇл»Ïà¹Ø¼ÓÃÜËã·¨ ASC£>GMM*/
+#define GMM_ASC_SEND_CMP_IND_EV (DWORD)(GMM_ASC_RSP_EVENT + 21)
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* ========================================================================
+ ASC£TD ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->UCSR*/
+#define ASC_TD_SWITCH_RADIO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 0)
+#define ASC_TD_CAMPON_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 1)
+#define ASC_TD_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 2)
+#define ASC_TD_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 3)
+#define ASC_TD_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 4)
+#define ASC_TD_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 5)
+#define ASC_TD_TRY_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 6)
+#define ASC_TD_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 7)
+#define ASC_TD_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_UAS_EVENT_BASE + 8)
+#define ASC_TD_IRAT_CAMPON_REJ_EV (DWORD)(ASC_UAS_EVENT_BASE + 9)
+#define ASC_TD_IRAT_CAMPON_CNF_EV (DWORD)(ASC_UAS_EVENT_BASE + 10)
+#define ASC_TD_ABORT_RSP_EV (DWORD)(ASC_UAS_EVENT_BASE + 11)
+
+/*NAS->ASC->AS*/
+#define ASC_TD_LOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 12)
+#define ASC_TD_UNLOCK_CELL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 13)
+#define ASC_TD_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 14)
+#define ASC_TD_DATA_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 15)
+#define ASC_TD_REL_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 16)
+#define ASC_TD_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 17)
+#define ASC_TD_PAGE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 18)
+#define ASC_TD_INACTIVE_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 19)
+#define ASC_TD_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 20)
+#define ASC_TD_NO_DRX_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 21)
+#define ASC_TD_DRX_RSV_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 22)
+#define ASC_TD_STOP_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 23)
+#define ASC_TD_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 24)
+#define ASC_TD_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_UAS_EVENT_BASE + 25)
+#define ASC_TD_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 26)
+#define ASC_TD_XCELLINFO_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 27)
+#define ASC_TD_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_UAS_EVENT_BASE + 28)
+
+/*UCSR->ASC */
+#define ASC_TD_SWITCH_RADIO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 0)
+#define ASC_TD_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 1)
+#define ASC_TD_IRAT_CAMPON_REQ_EV (DWORD)(ASC_UAS_RSP_EVENT + 2)
+#define ASC_TD_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 3)
+#define ASC_TD_TRY_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 4)
+
+#define ASC_TD_NOCELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 5)
+#define ASC_TD_PLMN_LIST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 6)
+#define ASC_TD_PLMN_LIST_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 7)
+#define ASC_TD_TRY_HPPLMN_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 8)
+#define ASC_TD_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 9)
+#define ASC_TD_ABORT_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 10)
+#define ASC_TD_SUBMODE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 11)
+#define ASC_TD_LOCK_CELL_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 12)
+#define ASC_TD_SCAN_UE_BAND_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 13)
+
+/*UCSR->ASC or UCER->ASC*/
+#define ASC_TD_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_UAS_RSP_EVENT + 14)
+#define ASC_TD_INACTIVE_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 15)
+#define ASC_TD_EST_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 16)
+#define ASC_TD_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 17)
+#define ASC_TD_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 18)
+#define ASC_TD_PAGING_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 19)
+#define ASC_TD_SYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 20)
+#define ASC_TD_PCH_CELL_INFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 21)
+#define ASC_TD_UURLC_DATA_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 22)
+#define ASC_TD_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 23)
+#define ASC_TD_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 24)
+#define ASC_TD_SRVCC_START_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 25)
+#define ASC_TD_SRVCC_END_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 26)
+#define ASC_TD_CCSYNC_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 27)
+#define ASC_TD_CS_RAB_REL_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 28)
+#define ASC_TD_CNINFO_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 29)
+
+/* URBC->ASC */
+#define ASC_TD_CURR_BEAR_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 30)
+#define ASC_TD_RECONST_PSRES_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 31)
+#define ASC_TD_CELL_LOST_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 32)
+#define ASC_TD_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_UAS_RSP_EVENT + 33)
+
+/*UCSR->ASC add*/
+#define ASC_TD_XCELLINFO_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 34)
+#define ASC_TD_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_UAS_RSP_EVENT + 35)
+#define ASC_TD_XCELLINFO_REJ_EV (DWORD)(ASC_UAS_RSP_EVENT + 36)
+
+/* ========================================================================
+ ASC£WCDMA ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->WCSR*/
+#define ASC_W_SWITCH_RADIO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 0)
+#define ASC_W_CAMPON_CELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 1)
+#define ASC_W_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 2)
+#define ASC_W_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 3)
+#define ASC_W_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 4)
+#define ASC_W_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 5)
+#define ASC_W_TRY_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 6)
+#define ASC_W_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 7)
+#define ASC_W_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_WAS_EVENT_BASE + 8)
+#define ASC_W_IRAT_CAMPON_REJ_EV (DWORD)(ASC_WAS_EVENT_BASE + 9)
+#define ASC_W_IRAT_CAMPON_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 10)
+#define ASC_W_ABORT_RSP_EV (DWORD)(ASC_WAS_EVENT_BASE + 11)
+#define ASC_W_IRAT_INACTIVE_CNF_EV (DWORD)(ASC_WAS_EVENT_BASE + 12)
+
+/*NAS->ASC->AS*/
+#define ASC_W_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 13)
+#define ASC_W_DATA_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 14)
+#define ASC_W_REL_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 15)
+#define ASC_W_CALL_TYPE_NOTIFY_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 16)
+#define ASC_W_PAGE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 17)
+#define ASC_W_INACTIVE_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 18)
+#define ASC_W_CLEAN_PEND_EST_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 19)
+#define ASC_W_NO_DRX_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 20)
+#define ASC_W_DRX_RSV_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 21)
+#define ASC_W_STOP_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 22)
+#define ASC_W_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 23)
+#define ASC_W_LOSTCOV_CAMP_SUCC_IND_EV (DWORD)(ASC_WAS_EVENT_BASE + 24)
+#define ASC_W_UPDATE_AUTH_PARAM_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 25)
+#define ASC_W_XCELLINFO_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 26)
+#define ASC_W_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_WAS_EVENT_BASE + 27)
+
+/*WCSR->ASC */
+#define ASC_W_SWITCH_RADIO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 0)
+#define ASC_W_IRAT_CAMPON_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 1)
+#define ASC_W_IRAT_CAMPON_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 2)
+#define ASC_W_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 3)
+#define ASC_W_TRY_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 4)
+#define ASC_W_IRAT_INACTIVE_REQ_EV (DWORD)(ASC_WAS_RSP_EVENT + 5)
+
+#define ASC_W_NOCELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 6)
+#define ASC_W_PLMN_LIST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 7)
+#define ASC_W_PLMN_LIST_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 8)
+#define ASC_W_TRY_HPPLMN_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 9)
+#define ASC_W_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 10)
+#define ASC_W_ABORT_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 11)
+#define ASC_W_SUBMODE_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 12)
+#define ASC_W_SCAN_UE_BAND_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 13)
+
+/*WCSR->ASC or WCER->ASC*/
+#define ASC_W_UPDATE_ACCESS_CLASS_INFO_EV (DWORD)(ASC_WAS_RSP_EVENT + 14)
+#define ASC_W_INACTIVE_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 15)
+#define ASC_W_EST_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 16)
+#define ASC_W_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 17)
+#define ASC_W_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 18)
+#define ASC_W_PAGING_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 19)
+#define ASC_W_SYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 20)
+#define ASC_W_PCH_CELL_INFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 21)
+#define ASC_W_UURLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 22)
+#define ASC_W_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 23)
+#define ASC_W_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 24)
+#define ASC_W_SRVCC_START_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 25)
+#define ASC_W_SRVCC_END_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 26)
+#define ASC_W_CCSYNC_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 27)
+#define ASC_W_CS_RAB_REL_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 28)
+#define ASC_W_CNINFO_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 29)
+/* WRBC->ASC */
+#define ASC_W_CURR_BEAR_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 30)
+#define ASC_W_RECONST_PSRES_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 31)
+/*WCDMA*/
+#define ASC_W_UWRLC_DATA_IND_EV (DWORD)(ASC_WAS_RSP_EVENT + 32)
+/*WCSR/UCSR -> ASC*/
+#define ASC_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 33)
+#define ASC_UTRA_RESEL_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 34)
+#define ASC_UTRA_COMPLETE_EV (DWORD)(ASC_WAS_RSP_EVENT + 35)
+#define ASC_W_XCELLINFO_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 36)
+#define ASC_W_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_WAS_RSP_EVENT + 37)
+#define ASC_W_XCELLINFO_REJ_EV (DWORD)(ASC_WAS_RSP_EVENT + 38)
+
+/* ========================================================================
+ ASC£GSM ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC->GSMAÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 0)
+#define ASC_GSM_CAMPON_CELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 1)
+#define ASC_GSM_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 2)
+#define ASC_GSM_INACTIVE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 3)
+#define ASC_GSM_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 4)
+#define ASC_GSM_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 5)
+#define ASC_GSM_TRY_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 6)
+#define ASC_GSM_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 7)
+#define ASC_GSM_UPDATE_PARAM_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 8)
+#define ASC_GSM_UPDATE_EPLMN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 9)
+#define ASC_GSM_GSM_SRV_NOTIFY_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 10)
+#define ASC_GSM_PCHPRE_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 11)
+#define ASC_GSM_UPDATE_REPLMN_FAILED_LAI_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 12)
+#define ASC_GSM_EST_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 13)
+#define ASC_GSM_DATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 14)
+#define ASC_GSM_REL_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 15)
+#define ASC_GSM_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 16)
+#define ASC_GSM_INFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 17)
+#define ASC_GSM_ABORT_RSP_EV (DWORD)(ASC_GAS_EVENT_BASE + 18)
+
+/*ASC->GSMAµÄ,GSMAÊÊÅäLLCµÄÏûϢʼþºÅ*/
+#define ASC_LLC_ASSIGN_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 19)
+#define ASC_LLC_TRIGGER_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 20)
+#define ASC_LLC_SUSPEND_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 21)
+#define ASC_LLC_RESUME_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 22)
+#define ASC_LLC_UNITDATA_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 23)
+#define ASC_SNP_GMM_SEQ_IND_EV (DWORD)(ASC_GAS_EVENT_BASE + 24)
+
+//ÁÚÇøÐÅÏ¢»ñÈ¡ÏûÏ¢
+#define ASC_GSM_XCELLINFO_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 25)
+#define ASC_GSM_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_GAS_EVENT_BASE + 26)
+
+/*GSMA->ASCÏûÏ¢*/
+#define ASC_GSM_SWITCH_RADIO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 0)
+#define ASC_GSM_CELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 1)
+#define ASC_GSM_NOCELL_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 2)
+#define ASC_GSM_INACTIVE_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 3)
+#define ASC_GSM_PLMN_LIST_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 4)
+#define ASC_GSM_PLMN_LIST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 5)
+#define ASC_GSM_ABORT_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 6)
+#define ASC_GSM_TRY_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 7)
+#define ASC_GSM_TRY_HPPLMN_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 8)
+#define ASC_GSM_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 9)
+#define ASC_GSM_CELL_UPDATE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 10)
+#define ASC_GSM_SUBMODE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 11)
+#define ASC_GSM_EST_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 12)
+#define ASC_GSM_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 13)
+#define ASC_GSM_SYNC_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 14)
+#define ASC_GSM_CCSYNC_IND_GSM_EV (DWORD)(ASC_GAS_RSP_EVENT + 15)
+#define ASC_GSM_SUSPEND_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 16)
+#define ASC_GSM_PAGE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 17)
+#define ASC_GSM_EST_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 18)
+#define ASC_GSM_DATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 19)
+#define ASC_GSM_SAPI3_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 20)
+#define ASC_GSM_CCTCH_REL_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 21)
+#define ASC_GSM_TBF_RELEASE_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 22)
+#define ASC_GSM_UTRA_CSHO_ENDIND_EV (DWORD)(ASC_GAS_RSP_EVENT + 23)
+
+#define ASC_LLC_UNITDATA_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 24)
+#define ASC_LLC_TRIGGER_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 25)
+#define ASC_LLC_STATUS_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 26)
+#define ASC_LLC_USER_DATA_PRESENT_EV (DWORD)(ASC_GAS_RSP_EVENT + 27)
+#define ASC_LLC_PSHO_INFO_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 28)
+
+/*GSMA->ASC->CBS (ASC͸´«)*/
+#define ASC_GSM_ETWS_NOTIFY_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 29)
+/*AS_GSM_LTE_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_REDIRECT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 30)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_GSM_RESEL_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 31)
+
+/*GSMA->ASC->SM (ASC͸´«)*/
+#define ASC_GSM_CURR_BEAR_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 32)
+#define ASC_SNP_GMM_SEQ_RSP_EV (DWORD)(ASC_GAS_RSP_EVENT + 33)
+
+/*GSMA->ASC->SMS (ASC͸´«)*/
+#define ASC_GSM_SEND_CMP_IND_EV (DWORD)(ASC_GAS_RSP_EVENT + 34)
+
+#define ASC_GSM_XCELLINFO_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 35)
+#define ASC_GSM_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_GAS_RSP_EVENT + 36)
+#define ASC_GSM_XCELLINFO_REJ_EV (DWORD)(ASC_GAS_RSP_EVENT + 37)
+
+/* ========================================================================
+ ASC£LTE ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ASC-->EURRC*/
+#define ASC_LTE_SWITCH_RADIO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 0)
+#define ASC_LTE_CAMPON_CELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 1)
+#define ASC_LTE_CAMPON_ANYCELL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 2)
+#define ASC_LTE_UPDATE_PLMN_FTAI_IND_EV (DWORD)(ASC_EUAS_EVENT_BASE + 3)
+#define ASC_LTE_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 4)
+#define ASC_LTE_STOP_PLMN_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 5)
+#define ASC_LTE_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 6)
+#define ASC_LTE_STOP_CSG_LIST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 7)
+#define ASC_LTE_TRY_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 8)
+#define ASC_LTE_ABORT_HPPLMN_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 9)
+#define ASC_LTE_EST_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 10)
+#define ASC_LTE_EST_ABT_EV (DWORD)(ASC_EUAS_EVENT_BASE + 11)
+#define ASC_LTE_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 12)
+#define ASC_LTE_KENB_RSP_EV (DWORD)(ASC_EUAS_EVENT_BASE + 13)
+#define ASC_LTE_REL_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 14)
+#define ASC_LTE_DATA_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 15)
+#define ASC_LTE_INACTIVE_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 16)
+#define ASC_LTE_UPDATE_SCAN_UE_BAND_FG_EV (DWORD)(ASC_EUAS_EVENT_BASE + 17)
+#define ASC_LTE_DETACH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 18)
+#define ASC_LTE_GROUP_REL_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 19)
+#define ASC_LTE_SCANSWITCH_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 20)
+#define ASC_LTE_XCELLINFO_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 21)
+#define ASC_LTE_XCELLINFO_ABORT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 22)
+#define ASC_LTE_UPDATE_CAMP_ACT_REQ_EV (DWORD)(ASC_EUAS_EVENT_BASE + 23)
+
+/* EURRC->ASC */
+#define ASC_LTE_SWITCH_RADIO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 0)
+#define ASC_LTE_CELL_INFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 1)
+#define ASC_LTE_NOCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 2)
+#define ASC_LTE_PAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 3)
+#define ASC_LTE_PLMN_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 4)
+#define ASC_LTE_PLMN_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 5)
+#define ASC_LTE_CSG_LIST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 6)
+#define ASC_LTE_CSG_LIST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 7)
+#define ASC_LTE_TRY_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 8)
+#define ASC_LTE_TRY_HPPLMN_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 9)
+#define ASC_LTE_ABORT_HPPLMN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 10)
+#define ASC_LTE_ABORT_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 11)
+#define ASC_LTE_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 13)
+#define ASC_LTE_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 14)
+#define ASC_LTE_DATA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 15)
+#define ASC_LTE_EST_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 16)
+#define ASC_LTE_EST_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 17)
+#define ASC_LTE_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 18)
+#define ASC_LTE_ABA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 19)
+#define ASC_LTE_DRB_SETUP_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 20)
+#define ASC_LTE_TRANS_FAIL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 21)
+#define ASC_LTE_KENB_REQ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 22)
+#define ASC_LTE_UE_INFO_CHANGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 23)
+#define ASC_LTE_DATA_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 24)
+#define ASC_LTE_SEC_PARA_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 25)
+#define ASC_LTE_INACTIVE_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 26)
+#define ASC_LTE_ABORT_RSP_EV (DWORD)(ASC_EUAS_RSP_EVENT + 27)
+/*AS_LTE_TD_REDIRECT_CNF_EV/AS_GSM_TD_REDIRECT_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_REDIRECT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 28)
+/*AS_GSM_LTE_RESEL_CNF_EV/AS_GSM_TD_RESEL_CNF_EVµ½ASCºó£¬ÓÉASC¸øGSM¿ÕÏûϢȷÈÏ*/
+#define ASC_LTE_RESEL_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 29)
+#define ASC_LTE_SRVCC_START_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 30)
+#define ASC_LTE_SRVCC_END_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 31)
+#define ASC_LTE_CMAS_NOTIFY_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 32)
+#define ASC_LTE_SCAN_UE_BAND_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 33)
+#define ASC_LTE_CELL_LOST_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 34)
+#define ASC_LTE_CELL_RECOVERAGE_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 35)
+#define ASC_LTE_GROUP_REL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 36)
+#define ASC_LTE_TGCCH_MSG_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 37)
+#define ASC_LTE_SCANGROUPINFO_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 38)
+#define ASC_LTE_SET_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 39)
+#define ASC_LTE_REL_ACTIVEGID_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 40)
+#define ASC_LTE_XCELLINFO_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 41)
+#define ASC_LTE_XCELLINFO_ABORT_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 42)
+#define ASC_LTE_XCELLINFO_REJ_EV (DWORD)(ASC_EUAS_RSP_EVENT + 43)
+#define ASC_LTE_NEIGCELL_IND_EV (DWORD)(ASC_EUAS_RSP_EVENT + 44)
+#define ASC_LTE_SCAN_CNF_EV (DWORD)(ASC_EUAS_RSP_EVENT + 45)
+/* ========================================================================
+ ASC£¸÷AS¹«¹²ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*LTE->UTRAÖØÑ¡*/
+#define AS_LTE_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 0)
+#define AS_LTE_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 1)
+#define AS_LTE_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 2)
+
+/*LTE->UTRAÖض¨Ïò*/
+#define AS_LTE_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 3)
+#define AS_LTE_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 4)
+#define AS_LTE_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 5)
+
+/*LTE->UTRA PSÇл»*/
+#define AS_LTE_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 6)
+#define AS_LTE_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 7)
+#define AS_LTE_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 8)
+
+/*LTE->GSMÖØÑ¡*/
+#define AS_LTE_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 9)
+#define AS_LTE_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 10)
+#define AS_LTE_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 11)
+
+/*LTE->GSMÖض¨Ïò*/
+#define AS_LTE_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 12)
+#define AS_LTE_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 13)
+#define AS_LTE_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 14)
+
+/*LTE->TD CSÇл»*/
+#define AS_LTE_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 15)
+#define AS_LTE_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 16)
+#define AS_LTE_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 17)
+
+/*LTE->GSM CCO*/
+#define AS_LTE_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 18)
+#define AS_LTE_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 19)
+#define AS_LTE_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 20)
+
+/*LTE->GSM PSÇл»*/
+#define AS_LTE_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 21)
+#define AS_LTE_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 22)
+#define AS_LTE_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 23)
+
+/*UTRA->LTEÖØÑ¡*/
+#define AS_UTRA_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 24)
+#define AS_UTRA_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 25)
+#define AS_UTRA_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 26)
+
+/*UTRA->LTEÖض¨Ïò*/
+#define AS_UTRA_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 27)
+#define AS_UTRA_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 28)
+#define AS_UTRA_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 29)
+
+/*UTRA->LTE PSÇл»*/
+#define AS_UTRA_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 30)
+#define AS_UTRA_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 31)
+#define AS_UTRA_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 32)
+
+/*UTRA->GSMÖØÑ¡*/
+#define AS_UTRA_GSM_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 33)
+#define AS_UTRA_GSM_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 34)
+#define AS_UTRA_GSM_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 35)
+
+/*UTRA>GSMÖض¨Ïò*/
+#define AS_UTRA_GSM_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 36)
+#define AS_UTRA_GSM_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 37)
+#define AS_UTRA_GSM_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 38)
+
+/*UTRA->GSM CSÇл»*/
+#define AS_UTRA_GSM_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 39)
+#define AS_UTRA_GSM_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 40)
+#define AS_UTRA_GSM_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 41)
+
+/*UTRA->GSM CCO*/
+#define AS_UTRA_GSM_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 42)
+#define AS_UTRA_GSM_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 43)
+#define AS_UTRA_GSM_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 44)
+
+/*UTRA->GSM PSÇл»*/
+#define AS_UTRA_GSM_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 45)
+#define AS_UTRA_GSM_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 46)
+#define AS_UTRA_GSM_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 47)
+
+/*UTRA->GSM Êý¾Ý°áÒÆ*/
+#define AS_UTRA_GSM_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 48)
+
+/*GSM->LTEÖØÑ¡*/
+#define AS_GSM_LTE_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 49)
+#define AS_GSM_LTE_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 50)
+#define AS_GSM_LTE_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 51)
+
+/*GSM->LTEÖض¨Ïò*/
+#define AS_GSM_LTE_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 52)
+#define AS_GSM_LTE_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 53)
+#define AS_GSM_LTE_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 54)
+
+/*GSM->LTE PSÇл»*/
+#define AS_GSM_LTE_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 55)
+#define AS_GSM_LTE_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 56)
+#define AS_GSM_LTE_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 57)
+
+/*GSM->LTE CCO*/
+#define AS_GSM_LTE_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 58)
+#define AS_GSM_LTE_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 59)
+#define AS_GSM_LTE_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 60)
+
+/*GSM->UTRAÖØÑ¡*/
+#define AS_GSM_UTRA_RESEL_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 61)
+#define AS_GSM_UTRA_RESEL_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 62)
+#define AS_GSM_UTRA_RESEL_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 63)
+
+/*GSM->UTRAÖض¨Ïò*/
+#define AS_GSM_UTRA_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 64)
+#define AS_GSM_UTRA_REDIRECT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 65)
+#define AS_GSM_UTRA_REDIRECT_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 66)
+
+/*GSM->UTRA CSÇл»*/
+#define AS_GSM_UTRA_CSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 67)
+#define AS_GSM_UTRA_CSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 68)
+#define AS_GSM_UTRA_CSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 69)
+
+/*GSM->UTRA PSÇл»*/
+#define AS_GSM_UTRA_PSHO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 70)
+#define AS_GSM_UTRA_PSHO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 71)
+#define AS_GSM_UTRA_PSHO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 72)
+
+/*GSM->UTRA CCO*/
+#define AS_GSM_UTRA_CCO_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 73)
+#define AS_GSM_UTRA_CCO_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 74)
+#define AS_GSM_UTRA_CCO_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 75)
+
+/*GSM->UTRA Êý¾Ý°áÒÆ*/
+#define AS_GSM_UTRA_DATA_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 76)
+/*WCDMA PREDEF*/
+#define AS_GSM_UTRA_READ_PREDEF_CONF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 77)
+#define AS_GSM_UTRA_READ_PREDEF_CONF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 78)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 79)
+#define AS_GSM_UTRA_ABORT_READ_PREDEF_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 80)
+
+
+/*NAS->ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_UPDATE_SYSCONFIG_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 81)
+#define AS_UPDATE_WHITE_CSGLIST_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 82)
+
+/*ASC->AS(UCSR EUCSR GSMA)*/
+#define AS_L1_RSRC_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 83)
+#define AS_L1_RSRC_REJ_EV (DWORD)(ASC_AS_EVENT_BASE + 84)
+#define AS_L1_RSRC_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 85)
+#define AS_L1_RSRC_FREE_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 86)
+
+/*.(UCSR EUCSR GSMA)AS->ASC*/
+#define AS_IRAT_CCO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 87)
+#define AS_IRAT_HO_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 88)
+#define AS_IRAT_CELL_RESEL_START_IND_EV (DWORD)(ASC_AS_EVENT_BASE + 89)
+
+#define AS_LTE_GSM_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 90)
+#define AS_LTE_GSM_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 91)
+#define AS_LTE_GSM_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 92)
+#define AS_LTE_GSM_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 93)
+
+#define AS_LTE_UTRA_CGI_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 94)
+#define AS_LTE_UTRA_CGI_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 95)
+#define AS_LTE_UTRA_CGI_ABORT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 96)
+#define AS_LTE_UTRA_CGI_ABORT_CNF_EV (DWORD)(ASC_AS_EVENT_BASE + 97)
+
+#define AS_LTE_TD_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 98)
+#define AS_LTE_W_REDIRECT_REQ_EV (DWORD)(ASC_AS_EVENT_BASE + 99)
+
+/* ========================================================================
+ CBS£ASCÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_ASC_NO_DRX_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 0)
+#define CBS_ASC_DRX_RSV_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 1)
+#define CBS_ASC_STOP_REQ_EV (DWORD)(CBS_RRC_EVENT_BASE + 2)
+
+#define CBS_ASC_PCH_CELL_INFO_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 0)
+#define CBS_ASC_UURLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 1)
+#define CBS_ASC_ETWS_PRIMARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 2)
+#define CBS_ASC_ETWS_SECONDARY_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 3)
+#define CBS_ASC_CMAS_NOTIFY_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 4)
+/*WCDMA*/
+#define CBS_ASC_UWRLC_DATA_IND_EV (DWORD)(CBS_RRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ GMM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_GMM_SEQ_IND_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 0)
+#define SNP_GMM_SEQ_RSP_EV (DWORD)(GMM_SNDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ GMM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDCP_GMM_NW_REL_ANYRB_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 0)
+#define GMM_PDCP_RB_CHG_IND_EV (DWORD)(GMM_PDCP_EVENT_BASE + 1)
+
+/* ========================================================================
+ SM£SNDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SNP_SM_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 0)
+#define SNP_SM_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 1)
+#define SNP_SM_MOD_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 2)
+#define SNP_SM_RAT_ACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 3)
+#define SNP_SM_RAT_DEACT_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 4)
+#define SNP_SM_RAT_SEQ_IND_EV (DWORD)(SM_SNDCP_EVENT_BASE + 5)
+#define SNP_SM_RAT_CHG_COMP_EV (DWORD)(SM_SNDCP_EVENT_BASE + 6)
+
+#define SNP_SM_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 0)
+#define SNP_SM_MOD_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 1)
+#define SNP_SM_STATUS_REQ_EV (DWORD)(SM_SNDCP_RSP_EVENT + 2)
+#define SNP_SM_RAT_ACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 3)
+#define SNP_SM_RAT_SEQ_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 4)
+#define SNP_SM_RAT_DEACT_RSP_EV (DWORD)(SM_SNDCP_RSP_EVENT + 5)
+
+/* ========================================================================
+ TAF£CCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_TAF_CONNECT_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 0)
+#define CC_TAF_CONNECT_CNF_EV (DWORD)(CC_TAF_EVENT_BASE + 1)
+#define CC_TAF_CONNECT_CNF_NEG_EV (DWORD)(CC_TAF_EVENT_BASE + 2)
+#define CC_TAF_RELEASE_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 3)
+#define CC_TAF_RELEASE_IND_EV (DWORD)(CC_TAF_EVENT_BASE + 4)
+#define CC_TAF_PEND_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 5)
+#define CC_TAF_RESUME_REQ_EV (DWORD)(CC_TAF_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS-UMMÖ®¼äµÄÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define UMM_CBS_START_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 0)
+#define UMM_CBS_STOP_REQ_EV (DWORD)(UMM_CBS_EVENT_BASE + 1)
+
+#define UMM_CBS_CELL_INFO_IND_EV (DWORD)(UMM_CBS_RSP_EVENT + 0)
+
+/* ========================================================================
+ URRC/CC£SCIÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CSCI_CONFIG_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 0)
+#define CSCI_CDEC_CTRL_REQ_EV (DWORD)(AP_SCI_EVENT_BASE + 1)
+#define CSCI_CONFIG_REL_EV (DWORD)(AP_SCI_EVENT_BASE + 2)
+#define CSCI_CONFIG_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 3)
+#define CSCI_UNRECOVER_ERR_EV (DWORD)(AP_SCI_EVENT_BASE + 4)
+#define CSCI_CDEC_CTRL_CNF_EV (DWORD)(AP_SCI_EVENT_BASE + 5)
+
+/* ========================================================================
+ URRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_READ_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 0)
+#define URRC_READ_SYSINFO_IND_EV (DWORD)(URRC_EVENT_BASE + 1)
+#define URRC_READ_SYSINFO_REJ_EV (DWORD)(URRC_EVENT_BASE + 2)
+#define URRC_STOP_SYSINFO_REQ_EV (DWORD)(URRC_EVENT_BASE + 3)
+#define URRC_READ_DYN_SIB_REQ_EV (DWORD)(URRC_EVENT_BASE + 4)
+#define URRC_READ_DYN_SIB_CNF_EV (DWORD)(URRC_EVENT_BASE + 5)
+#define URRC_SIB_MODIFIED_IND_EV (DWORD)(URRC_EVENT_BASE + 6)
+#define URRC_CELLUPDATE_REQ_EV (DWORD)(URRC_EVENT_BASE + 7)
+#define URRC_CELL_RESEL_REQ_EV (DWORD)(URRC_EVENT_BASE + 8)
+#define URRC_CELL_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 9)
+#define URRC_REL_CONN_REQ_EV (DWORD)(URRC_EVENT_BASE + 10)
+#define URRC_RESUME_CELL_REQ_EV (DWORD)(URRC_EVENT_BASE + 11)
+#define URRC_RPLMN_INFO_IND_EV (DWORD)(URRC_EVENT_BASE + 12)
+#define URRC_RESOURE_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 13)
+#define URRC_RESOURCE_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 14)
+#define URRC_UPDATE_EPLMN_REQ_EV (DWORD)(URRC_EVENT_BASE + 15)
+#define URRC_HIGH_MOBILITY_IND (DWORD)(URRC_EVENT_BASE + 16)
+#define URRC_HO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 17)
+#define URRC_HO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 18)
+#define URRC_HO_TO_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 19)
+#define URRC_HO_TO_UTRAN_CNF_EV (DWORD)(URRC_EVENT_BASE + 20)
+#define URRC_HO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 21)
+#define URRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(URRC_EVENT_BASE + 22)
+#define URRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 23)
+#define URRC_CCO_TO_UTRAN_IND_EV (DWORD)(URRC_EVENT_BASE + 24)
+#define URRC_CCO_TO_UTRAN_REJ_EV (DWORD)(URRC_EVENT_BASE + 25)
+#define URRC_RADIO_LINK_FAIL_IND_EV (DWORD)(URRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define URRC_NEIBCELL_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 27)
+#define URRC_FACH_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 28)
+#define URRC_FACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 29)
+#define URRC_DRX_CHG_IND_EV (DWORD)(URRC_EVENT_BASE + 30)
+#define URRC_SEND_BUF_EST_REQ_EV (DWORD)(URRC_EVENT_BASE + 31)
+#define URRC_ABORT_RATCHG_REQ_EV (DWORD)(URRC_EVENT_BASE + 32)
+#define URRC_BAR_RESUME_IND_EV (DWORD)(URRC_EVENT_BASE + 33)
+#define URRC_CHG_CAMPON_TYPE_EV (DWORD)(URRC_EVENT_BASE + 34)
+#define URRC_GET_RF_REQ_EV (DWORD)(URRC_EVENT_BASE + 35) /*USIR->UCSR*/
+#define URRC_GET_RF_CNF_EV (DWORD)(URRC_EVENT_BASE + 36) /*UCSR->USIR*/
+#define URRC_SYSINFO_CONTAINER_IND_EV (DWORD)(URRC_EVENT_BASE + 37) /*UCSR->USIR*/
+#define URRC_ETWS_CFG_REQ_EV (DWORD)(URRC_EVENT_BASE + 38)
+#define URRC_ETWS_CFG_END_EV (DWORD)(URRC_EVENT_BASE + 39)
+#define URRC_ETWS_CONTINUE_REQ_EV (DWORD)(URRC_EVENT_BASE + 40)
+#define URRC_DRX_CHANGE_IND_EV (DWORD)(URRC_EVENT_BASE + 41) /*URBC->UMCR*/
+#define URRC_EFACH_CFG_IND_EV (DWORD)(URRC_EVENT_BASE + 42)/*UCMR->URBC*/
+#define URRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(URRC_EVENT_BASE + 43)
+#define URRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(URRC_EVENT_BASE + 44)
+#define URRC_OUT_OF_SYNC_EV (DWORD)(URRC_EVENT_BASE + 45)
+#define URRC_RESUME_IN_SYNC_EV (DWORD)(URRC_EVENT_BASE + 46)
+#define URRC_LBS_MEAS_IND (DWORD)(URRC_EVENT_BASE + 47)
+/* ========================================================================
+ URLC - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CURLC_CONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 0)
+#define CURLC_RELEASE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 1)
+#define CURLC_LOOP_TEST_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 2)
+#define CURLC_SUSPEND_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 3)
+#define CURLC_RESUME_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 4)
+#define CURLC_CONTINUE_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 5)
+#define UURLC_DATA_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 6)
+#define CURLC_CBS_RBCONFIG_REQ_EV (DWORD)(URLC_URRC_EVENT_BASE + 7)
+#define CURLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(URLC_URRC_EVENT_BASE + 8)
+
+#define CURLC_SUSPEND_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 0)
+#define CURLC_LOOP_TEST_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 1)
+#define UURLC_DATA_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 2)
+#define CURLC_STATUS_IND_EV (DWORD)(URLC_URRC_RSP_EVENT + 3)
+#define UURLC_DATA_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 4)
+#define CURLC_CONFIG_CNF_EV (DWORD)(URLC_URRC_RSP_EVENT + 5)
+#define CURLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(URLC_URRC_RSP_EVENT + 6)
+
+/* ========================================================================
+ UMAC - URRC/UMAC - UMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 0)
+#define CUMAC_RACH_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 1)
+#define CUMAC_RNTI_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 2)
+#define CUMAC_HS_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 3)
+#define CUMAC_HS_RESET_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 4)
+#define CUMAC_TFC_CTRL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 5)
+#define CUMAC_CONFIG_ABORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 6)
+#define CUMAC_ASC_PARA_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 7)
+#define CUMAC_DEL_CONFIG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 8)
+#define CUMAC_TV_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 9)
+#define CUMAC_Q_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 10)
+#define CUMAC_UE_MEAS_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 11)
+#define CUMAC_TV_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 12)
+#define CUMAC_Q_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 13)
+#define CUMAC_UE_MEAS_REL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 14)
+#define CUMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 15)
+#define CUMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 16)
+#define CUMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 17)
+#define CUMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 18)
+#define CUMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 19)
+#define CUMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 20)
+#define CUMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 21)
+#define CUMAC_CRC_RESULT_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 22)
+#define CUMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 23)
+#define CUMAC_CONTINUE_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 24)
+#define CUMAC_IDLE_PERIOD_EV (DWORD)(UMAC_URRC_EVENT_BASE + 25)
+#define CUMAC_CELL_RESEL_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 26)
+#define CUMAC_HSPA_EPCH_CFG_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 27)
+#define CUMAC_UPDATE_ERNTI_REQ_EV (DWORD)(UMAC_URRC_EVENT_BASE + 28)
+
+#define CUMAC_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 0)
+#define UUMAC_PCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 1)
+#define UUMAC_BCCH_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 2)
+#define CUMAC_CONFIG_CHG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 3)
+#define CUMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 4)
+#define CUMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 5)
+#define CUMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 6)
+#define CUMAC_TV_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 7)
+#define CUMAC_Q_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 8)
+#define CUMAC_UE_MEAS_REPORT_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 9)
+#define CUMAC_ERUCCH_STATUS_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 10)
+#define CUMAC_FACH_CFG_IND_EV (DWORD)(UMAC_URRC_RSP_EVENT + 11)
+#define CUMAC_CELL_RESEL_CNF_EV (DWORD)(UMAC_URRC_RSP_EVENT + 12)
+/* ========================================================================
+ UMAC - UL/DL - UMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CUMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(UMAC_UMAC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1T - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_GSM_MEAS_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 0)
+#define L1T_GSM_BSIC_VERIFY_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 1)
+#define L1T_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 3)
+#define L1T_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 4)
+#define L1T_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 5)
+#define L1T_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 6)
+#define L1T_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 7)
+#define L1T_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 8)
+#define L1T_TD_GET_RF_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 9)
+#define L1T_PLMN_END_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 10)
+#define L1T_IRAT_RSRC_REQ_EV (DWORD)(L1T_URRC_EVENT_BASE + 11)
+
+#define L1T_GSM_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 0)
+#define L1T_TD_GET_RF_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 1)
+#define L1T_IRAT_RSRC_CNF_EV (DWORD)(L1T_URRC_RSP_EVENT + 2)
+#define L1T_LTE_MEAS_IND_EV (DWORD)(L1T_URRC_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDCP - URRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 1)
+#define CPDCP_RELOC_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 2)
+#define CPDCP_RELOC_COMP_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 3)
+#define CPDCP_RELOC_FAIL_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 4)
+#define CPDCP_DL_PDU_SIZE_CHG_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 5)
+#define CPDCP_ROHC_TARGET_MODE_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 6)
+#define CPDCP_SCRI_IND_EV (DWORD)(PDCP_URRC_EVENT_BASE + 7)
+#define CPDCP_FD_MONITOR_REQ_EV (DWORD)(PDCP_URRC_EVENT_BASE + 8)
+#define CPDCP_FD_NO_DATA_CNF_EV (DWORD)(PDCP_URRC_EVENT_BASE + 9)
+
+
+#define CPDCP_RELOC_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 0)
+#define CPDCP_CONFIG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 1)
+#define CPDCP_RELOC_REJ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 2)
+#define CPDCP_DL_PDU_SIZE_CHG_CNF_EV (DWORD)(PDCP_URRC_RSP_EVENT + 3)
+#define CPDCP_DATA_TRANSFER_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 4)
+#define CPDCP_FD_NO_DATA_REQ_EV (DWORD)(PDCP_URRC_RSP_EVENT + 5)
+
+
+/* ========================================================================
+ URLC - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UUMAC_DATA_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 0)
+#define CUMAC_HS_RESET_IND_EV (DWORD)(URLC_UMAC_EVENT_BASE + 2)
+#define UURLC_DL_CTRL_PDU_REQ_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 3)
+#define UURLC_MAKE_AMDPDU_Ev (DWORD)(URLC_UMAC_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T - UMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ISR_FRAME_IND_EV (DWORD)(UMAC_L1T_EVENT_BASE + 0)
+
+/* ========================================================================
+ SM£PDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_PDCP_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 0)
+#define SM_PDCP_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 1)
+#define SM_PDCP_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 2)
+#define SM_PDCP_ACT_ALREADY_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 3)
+#define SM_PDCP_RAT_ACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 4)
+#define SM_PDCP_RAT_DEACT_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 5)
+#define SM_PDCP_RAT_SEQ_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 6)
+#define SM_PDCP_HC_MOD_IND_EV (DWORD)(SM_PDCP_EVENT_BASE + 7)
+#define SM_PDCP_RAT_CHG_COMP_EV (DWORD)(SM_PDCP_EVENT_BASE + 8)
+#define SM_PDCP_MODIFY_CNF_EV (DWORD)(SM_PDCP_EVENT_BASE + 9)
+
+#define SM_PDCP_STATUS_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 0)
+#define SM_PDCP_RAT_ACT_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 1)
+#define SM_PDCP_RAT_SEQ_RSP_EV (DWORD)(SM_PDCP_RSP_EVENT + 2)
+#define SM_PDCP_MODIFY_REQ_EV (DWORD)(SM_PDCP_RSP_EVENT + 3)
+
+/* ========================================================================
+ PDI - GSMA ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define PDI_GSM_DATA_REQ_EV (DWORD)(PDI_GSMA_EVENT_BASE + 0)
+
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UPDI_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 0)
+#define UPDI_DATA_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 1)
+#define CPDI_NOT_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 2)
+#define CPDI_READY_IND_EV (DWORD)(PDI_PDCP_EVENT_BASE + 3)
+#define PDI_EPDCP_DATA_REQ_EV (DWORD)(PDI_PDCP_EVENT_BASE + 4)
+
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UURLC_PDCP_DATA_REQ_EV (DWORD)(PDCP_URLC_EVENT_BASE + 0)
+#define UURLC_PDCP_DATA_IND_EV (DWORD)(PDCP_URLC_EVENT_BASE + 1)
+/* ========================================================================
+ PDCP - RLC ÏûÏ¢ºÅ¶¨Òå(²Î¿¼RLC - RRC)
+======================================================================== */
+
+
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_BCH_READ_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 1)
+#define P_BCH_OPEN_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 2)
+#define P_BCH_RELEASE_REQ_EV (DWORD)(USIR_UPHY_EVENT_BASE + 3)
+
+#define P_SFN_DECODE_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 1)
+#define P_BCH_IND_EV (DWORD)(USIR_UPHY_RSP_EVENT + 2)
+#define P_BCH_OPEN_REJ_EV (DWORD)(USIR_UPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ UCSR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_FREQUENCY_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 1)
+#define P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 2)
+#define P_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 3)
+#define P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 4)
+#define P_CAMPON_A_CELL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 5)
+#define P_TD_REL_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 6)
+#define P_TD_RESET_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 7)
+#define P_TD_SLEEP_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 8)
+#define P_TD_SET_IRAT_MODE_REQ_EV (DWORD)(UCSR_UPHY_EVENT_BASE + 9)
+
+#define P_FREQUENCY_SCAN_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 1)
+#define P_CELL_SEARCH_IND_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 2)
+#define P_TD_RESET_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 3)
+#define P_TD_REL_CNF_EV (DWORD)(UCSR_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMCR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 1)
+#define P_INTER_FREQ_MEAS_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 2)
+#define P_MEAS_REL_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 5)
+#define P_FMO_INFO_REQ_EV (DWORD)(UMCR_UPHY_EVENT_BASE + 6)
+
+#define P_INTRA_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 1)
+#define P_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 2)
+#define P_BLIND_UARFCN_INTER_FREQ_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 3)
+#define P_DETECT_CELL_INFO_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 4)
+#define P_SERVCELL_MEAS_IND_EV (DWORD)(UMCR_UPHY_RSP_EVENT + 7)
+/* ========================================================================
+ URBC - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 1)
+#define P_DL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 2)
+#define P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 3)
+#define P_UL_DPCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 4)
+#define P_DL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 5)
+#define P_UL_TRCH_RECONFIG_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 6)
+#define P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 7)
+#define P_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 8)
+#define P_STOP_PAGING_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 9)
+#define P_ADD_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 10)
+#define P_REL_HSDPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 11)
+#define P_REL_SCCPCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 12)
+#define P_ADD_MODIFY_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 13)
+#define P_STOP_CBS_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 14)
+#define P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(URBC_UPHY_EVENT_BASE + 15)
+#define P_ADD_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 16)
+#define P_REL_HSUPA_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 17)
+#define P_PLCCH_ADD_MODIFY_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 18)
+#define P_HSPA_PLUS_FACH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 19)
+#define P_HSPA_PLUS_PCH_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 20)
+#define P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 21)
+#define P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 22)
+#define P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 23)
+#define P_UL_PHY_CH_CTRL_REQ_EV (DWORD)(URBC_UPHY_EVENT_BASE + 24)
+
+#define P_DL_RL_SETUP_MODIFY_CNF_EV (DWORD)(URBC_UPHY_RSP_EVENT + 1)
+#define P_IN_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 2)
+#define P_OUT_SYNC_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 3)
+#define P_UL_ESTABLISH_IND_EV (DWORD)(URBC_UPHY_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMAC_UL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_RACH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 0)
+#define P_DL_DATA_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 1)
+#define P_TFC_POWER_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 2)
+#define P_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 3)
+#define P_UL_DATA_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 4)
+#define P_ABORT_RACH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 5)
+#define P_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 6)
+#define P_ERUCCH_PROCEDURE_IND_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 7)
+#define P_ABORT_ERUCCH_PROCEDURE_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 8)
+#define P_SET_AGCH_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 9)
+#define P_CELL_RESEL_REQ_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 10)
+#define P_CELL_RESEL_CNF_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 11)
+#define P_SYNC_CMD_RESP_EV (DWORD)(UMAC_UL_UPHY_EVENT_BASE + 12)
+/* ========================================================================
+ UMAC_DL - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_QUALITY_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 0)
+#define P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 1)
+#define P_QUALITY_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 2)
+#define P_UE_INTERNAL_MEAS_IND_EV (DWORD)(UMAC_DL_UPHY_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1T - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G_L1T_GSM_INACT_TIME_IND_EV*/
+#define P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G_L1T_ABORT_GSM_GAP_REQ_EV*/
+#define P_TD_DCH_GAP_CONFIG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 3)
+#define P_CARD2_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 4) /*T_zTD_P_card2_gap_req*/
+#define P_CARD2_GAP_REL_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 5) /*T_zTD_P_card2_gap_rel_req*/
+#define P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 6) /*T_zTD_P_card2_stop_gap_req*/
+#define P_CARD1_SUSPEND_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 7) /*T_zTD_P_card1_suspend_req*/
+#define P_CARD1_RESUME_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 8) /*T_zTD_P_card1_resume_req*/
+#define P_TD_ZTPCG_REQ_EV (DWORD)(L1T_UPHY_EVENT_BASE + 9)
+
+#define P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 1)
+#define P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 2)
+#define P_BCH_RELEASE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 3)
+#define P_CAMPON_A_CELL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 4)
+#define P_DPCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 5)
+#define P_REL_SCCPCH_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 6)
+#define P_STOP_PAGING_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 7)
+#define P_STOP_CBS_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 8)
+#define P_REL_HSDPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 9)
+#define P_REL_HSUPA_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 10)
+#define P_RACH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 11)
+#define P_ERUCCH_PROCEDURE_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 12)
+#define P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 13)
+#define P_UMTS_TIMER_SNAPSHOT_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 14)
+#define P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 15)
+#define P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 16)
+#define P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 17)
+#define P_CARD2_GAP_IND_EV (DWORD)(L1T_UPHY_RSP_EVENT + 18) /*T_zTD_P_card2_gap_ind*/
+#define P_CARD2_GAP_REL_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 19) /*T_zTD_P_card2_gap_rel_cnf*/
+#define P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 20) /*T_zTD_P_card2_stop_gap_cnf*/
+#define P_CARD1_SUSPEND_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 21) /*T_zTD_P_card1_suspend_cnf*/
+#define P_TD_ZTPCG_CNF_EV (DWORD)(L1T_UPHY_RSP_EVENT + 22)
+
+/* ========================================================================
+ L1T ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define P_CHECK_RF_IND_EV (DWORD)(L1T_EVENT_BASE + 1)
+#define P_ACTIVE_IND_EV (DWORD)(L1T_EVENT_BASE + 2)
+#define L1T_GSM_MEAS_DONE_REQ_EV (DWORD)(L1T_EVENT_BASE + 3)
+
+/* ========================================================================
+ L1E/L1Gµ÷L1T º¯ÊýÉèÖÃÖ÷¸¨Ä£Ê½µÄº¯ÊýÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1T_FUNC_SET_MODE_REQ_EV (DWORD)(L1T_EVENT_BASE + 4)
+
+/* ========================================================================
+ L1T/L1E/L1WÖ®¼äÏûÏ¢ºÅ¶¨Òå(ÎïÀí²ãÊÊÅä²ãL1A)
+======================================================================== */
+#define L1_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 0)
+#define L1_GET_RF_CNF_EV (DWORD)(L1A_EVENT_BASE + 1)
+#define UTRAN_IRAT_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 2)
+#define UTRAN_BLIND_MEAS_IND_EV (DWORD)(L1A_EVENT_BASE + 3)
+/*WCDMA*/
+#define L1A_FUNC_SET_MODE_REQ_EV (DWORD)(L1A_EVENT_BASE + 4)
+#define L1A_TD_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 5)/*TDÏòÖ÷ÖÆʽҪÉäƵÇëÇóÏûÏ¢*/
+#define L1A_GET_RF_FROM_TD_CNF_EV (DWORD)(L1A_EVENT_BASE + 6)/*TDÈóöÉäƵºó¸øÆäËûÖÆʽµÄ»Ø¸´ÏûÏ¢*/
+#define L1A_W_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 7)
+#define L1A_GET_RF_FROM_W_CNF_EV (DWORD)(L1A_EVENT_BASE + 8)
+#define L1A_LTE_GET_RF_REQ_EV (DWORD)(L1A_EVENT_BASE + 9)
+#define L1A_GET_RF_FROM_LTE_CNF_EV (DWORD)(L1A_EVENT_BASE + 10)
+/*w¸¨Ä£Ï²âÁ¿Éϱ¨¹²ÓÃW_P_INTER_FREQ_MEAS_IND_EV*/
+/*** ÔSIG_CODE.HÖÐÒÆÖ²¹ýÀ´µÄÏûÏ¢ ***/
+ /* START OF DLL */
+#define L2_CONNECT_IND (DWORD)(LAPDM_EVENT_BASE + 0)
+#define L2_DATA_IND (DWORD)(LAPDM_EVENT_BASE + 1)
+#define DL_UNIT_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 2)
+#define DL_DATA_REQ (DWORD)(LAPDM_EVENT_BASE + 3)
+#define DL_ESTABLISH_REQ (DWORD)(LAPDM_EVENT_BASE + 4)
+#define DL_IRAT_HO_REQ (DWORD)(LAPDM_EVENT_BASE + 5)
+#define DL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 6)
+#define DL_RECONNECT_REQ (DWORD)(LAPDM_EVENT_BASE + 7)
+#define DL_RESUME_REQ (DWORD)(LAPDM_EVENT_BASE + 8)
+#define DL_SUSPEND_REQ (DWORD)(LAPDM_EVENT_BASE + 9)
+#define MDL_CONFIG (DWORD)(LAPDM_EVENT_BASE + 10)
+#define MDL_RELEASE_REQ (DWORD)(LAPDM_EVENT_BASE + 11)
+#define PH_START_T200 (DWORD)(LAPDM_EVENT_BASE + 12)
+#define T200 (DWORD)(LAPDM_EVENT_BASE + 13)
+ /* END OF DLL */
+
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äBEGIN**************************/
+#define T_SI2N_AVAIL (DWORD)(GRR_EVENT_BASE + 83)
+#define T3206 (DWORD)(GRR_EVENT_BASE + 84)
+#define T3208 (DWORD)(GRR_EVENT_BASE + 85)
+#define T3210 (DWORD)(GRR_EVENT_BASE + 86)
+#define T_NCELL_VALID_TIMER (DWORD)(GRR_EVENT_BASE + 87)
+#define T_P_SI_STATUS_TIMER (DWORD)(GRR_EVENT_BASE + 88)
+#define T_CELL_SUPERVISION (DWORD)(GRR_EVENT_BASE + 89)
+#define T_PENALTY_0 (DWORD)(GRR_EVENT_BASE + 90)
+#define T_PENALTY_1 (DWORD)(GRR_EVENT_BASE + 91)
+#define T_PENALTY_2 (DWORD)(GRR_EVENT_BASE + 92)
+#define T_PENALTY_3 (DWORD)(GRR_EVENT_BASE + 93)
+#define T_PENALTY_4 (DWORD)(GRR_EVENT_BASE + 94)
+#define T_PENALTY_5 (DWORD)(GRR_EVENT_BASE + 95)
+#define T_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 96)
+#define T_RESELECTION_DELAY (DWORD)(GRR_EVENT_BASE + 97)
+#define T_SCELL_RESEL_DELAY (DWORD)(GRR_EVENT_BASE + 98)
+#define T_SYS_INFO_READ (DWORD)(GRR_EVENT_BASE + 99)
+#define T_PSI_CYCLE (DWORD)(GRR_EVENT_BASE + 100)
+#define T_NCELL_SI_READ (DWORD)(GRR_EVENT_BASE + 101)
+#define T_CALL_REEST_TIMEOUT (DWORD)(GRR_EVENT_BASE + 102)
+#define T3122 (DWORD)(GRR_EVENT_BASE + 103)
+#define T3142 (DWORD)(GRR_EVENT_BASE + 104)
+#define T3172 (DWORD)(GRR_EVENT_BASE + 105)
+#define T3200 (DWORD)(GRR_EVENT_BASE + 106)
+#define T_SYS_INFO_VALID (DWORD)(GRR_EVENT_BASE + 107)
+#define T_RXLEV_VALID (DWORD)(GRR_EVENT_BASE + 108)
+#define T_BETTER_C2 (DWORD)(GRR_EVENT_BASE + 109)
+#define T_SYNC_READ (DWORD)(GRR_EVENT_BASE + 110)
+#define T_NON_DRX (DWORD)(GRR_EVENT_BASE + 111)
+#define T_MONITOR_OLD_SCELL (DWORD)(GRR_EVENT_BASE + 112)
+#define T_TWO_IA_SUPERVISION (DWORD)(GRR_EVENT_BASE + 113)
+#define T_SENT_MEAS_REPORT (DWORD)(GRR_EVENT_BASE + 114)
+#define T_PSI_UNSOLICITED (DWORD)(GRR_EVENT_BASE + 115)
+#define T_ABN_CELL_RESEL_TIMEOUT (DWORD)(GRR_EVENT_BASE + 116)
+#define T_ABN_CELL_RESEL_SCELL (DWORD)(GRR_EVENT_BASE + 117)
+#define T_TESTPARAM (DWORD)(GRR_EVENT_BASE + 118)
+#define T_CELL_BARRED_TIMER (DWORD)(GRR_EVENT_BASE + 119)
+#define T_CELL_SEL_IND (DWORD)(GRR_EVENT_BASE + 120)
+#define T3218 (DWORD)(GRR_EVENT_BASE + 121)
+#define T309 (DWORD)(GRR_EVENT_BASE + 122)
+#define T_BETTER_UTRAN (DWORD)(GRR_EVENT_BASE + 123)
+#define T_IR_WAIT_TIMER (DWORD)(GRR_EVENT_BASE + 124)
+#define T_IR_CELL_INVALID_TIMER (DWORD)(GRR_EVENT_BASE + 125)
+#define T3232_EV (DWORD)(GRR_EVENT_BASE + 126)
+#define T_RESELECTION_EV (DWORD)(GRR_EVENT_BASE + 127)
+#define T3230_EV (DWORD)(GRR_EVENT_BASE + 128)
+#define T_DISABLE_UMTS_MEAS_EV (DWORD)(GRR_EVENT_BASE + 129)
+#define T_DISABLE_LTE_MEAS_EV (DWORD)(GRR_EVENT_BASE + 130)
+
+#define T_IR_READ_PREDEF_CONF_TIMER (DWORD)(GRR_EVENT_BASE + 139)//¸ø¶¨Ê±Æ÷ÏûÏ¢ºÅÔ¤Áô10¸ö
+/****************************¶¨Ê±Æ÷ÏûÏ¢ºÅÇø¼äEND*****************************/
+ /* END OF GRR */
+
+ /* START OF MAC */
+#define MAC_PDCH_REL_REQ (DWORD)(GMAC_EVENT_BASE + 0)
+#define MAC_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 1)
+#define RLC_MAC_TLLI_ASSIGN_REQ (DWORD)(GMAC_EVENT_BASE + 2)
+#define RLC_MAC_UPLINK_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 3)
+#define RLC_MAC_REL_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 4)
+#define RLC_MAC_DEACT_CNF (DWORD)(GMAC_EVENT_BASE + 5)
+#define RLC_MAC_CTRL_BLOCK_REQ (DWORD)(GMAC_EVENT_BASE + 6)
+#define GRR_MAC_CLASSMARK_IND (DWORD)(GMAC_EVENT_BASE + 7)
+#define GRR_MAC_UPDATE_PARAM_REQ (DWORD)(GMAC_EVENT_BASE + 8)
+#define GRR_MAC_FREQ_UPDATE_REQ (DWORD)(GMAC_EVENT_BASE + 9)
+#define GRR_MAC_PDCH_REQ (DWORD)(GMAC_EVENT_BASE + 10)
+#define GRR_MAC_POLLING_REQ (DWORD)(GMAC_EVENT_BASE + 11)
+#define GRR_MAC_CIRCUIT_REQ (DWORD)(GMAC_EVENT_BASE + 12)
+#define GRR_MAC_CIRCUIT_ABORT_REQ (DWORD)(GMAC_EVENT_BASE + 13)
+#define GRR_MAC_DEACT_REQ (DWORD)(GMAC_EVENT_BASE + 14)
+#define GRR_MAC_IDLE_CHN_CNF (DWORD)(GMAC_EVENT_BASE + 15)
+#define GRR_MAC_CELL_CHANGE_IND (DWORD)(GMAC_EVENT_BASE + 16)
+#define GRR_MAC_START_TIMER (DWORD)(GMAC_EVENT_BASE + 17)
+#define GRR_MAC_STOP_TIMER (DWORD)(GMAC_EVENT_BASE + 18)
+#define GRR_MAC_TESTPARAM_REQ (DWORD)(GMAC_EVENT_BASE + 19)
+#define GRR_MAC_SUSPEND_REQ (DWORD)(GMAC_EVENT_BASE + 20)
+#define T3126 (DWORD)(GMAC_EVENT_BASE + 21)
+#define T3146 (DWORD)(GMAC_EVENT_BASE + 22)
+#define T3162 (DWORD)(GMAC_EVENT_BASE + 23)
+#define T3164 (DWORD)(GMAC_EVENT_BASE + 24)
+#define T3166 (DWORD)(GMAC_EVENT_BASE + 25)
+#define T3168_MAC (DWORD)(GMAC_EVENT_BASE + 26)
+#define T3170 (DWORD)(GMAC_EVENT_BASE + 27)
+#define T3174 (DWORD)(GMAC_EVENT_BASE + 28)
+#define T3176 (DWORD)(GMAC_EVENT_BASE + 29)
+#define T3180 (DWORD)(GMAC_EVENT_BASE + 30)
+#define T3184 (DWORD)(GMAC_EVENT_BASE + 31)
+#define T3186 (DWORD)(GMAC_EVENT_BASE + 32)
+#define T3190 (DWORD)(GMAC_EVENT_BASE + 33)
+#define T3192 (DWORD)(GMAC_EVENT_BASE + 34)
+#define T_SINGLE_DL_BLOCK (DWORD)(GMAC_EVENT_BASE + 35)
+#define XPOLLING_RESPONSE (DWORD)(GMAC_EVENT_BASE + 36)
+#define XBLOCK_DL_RELEASE (DWORD)(GMAC_EVENT_BASE + 37)
+#define XBLOCK_UL_RELEASE (DWORD)(GMAC_EVENT_BASE + 38)
+#define GRR_MAC_T3218_EXP_EV (DWORD)(GMAC_EVENT_BASE + 39)
+#define GRR_MAC_PSHO_REQ_EV (DWORD)(GMAC_EVENT_BASE + 40)
+#define GRR_MAC_PSHO_RETURN_REQ_EV (DWORD)(GMAC_EVENT_BASE + 41)
+#define GRR_MAC_PSHO_DEACT_REQ_EV (DWORD)(GMAC_EVENT_BASE + 42)
+#define GMAC_T3216_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 43)
+#define GMAC_T_MULTI_DL_BLOCK_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 44)
+#define GMAC_T3200_EXPIRY_EV (DWORD)(GMAC_EVENT_BASE + 45)
+
+ /* END OF MAC */
+
+ /* START OF RLC */
+#define RLC_WAKE_UP (DWORD)(GRLC_EVENT_BASE + 0)
+#define RLC_FILL_DATA_QUEUE (DWORD)(GRLC_EVENT_BASE + 1)
+#define RLC_START_TIMER_T3182 (DWORD)(GRLC_EVENT_BASE + 2)
+#define RLC_START_TIMER_T3168 (DWORD)(GRLC_EVENT_BASE + 3)
+#define RLC_FILL_GPRS_TEST_MODE (DWORD)(GRLC_EVENT_BASE + 4)
+#define RLC_UNEXPECTED_INPUT_RECEIVED (DWORD)(GRLC_EVENT_BASE + 5)
+#define RLC_UPL_DEBUG (DWORD)(GRLC_EVENT_BASE + 6)
+#define OM_RLC_TEST_MODE_REQ (DWORD)(GRLC_EVENT_BASE + 7)
+#define GRR_RLC_SUSPEND_REQ (DWORD)(GRLC_EVENT_BASE + 8)
+#define GRR_RLC_RESUME_REQ (DWORD)(GRLC_EVENT_BASE + 9)
+#define GRR_RLC_UPDATE_PARAM_REQ (DWORD)(GRLC_EVENT_BASE + 10)
+#define GRR_RLC_ACCESS_CNF (DWORD)(GRLC_EVENT_BASE + 11)
+#define GRR_RLC_ACCESS_REJ (DWORD)(GRLC_EVENT_BASE + 12)
+#define GRR_RLC_REL_PDCH_REQ (DWORD)(GRLC_EVENT_BASE + 13)
+#define GRR_RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 14)
+#define GRR_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 15)
+#define GRR_RLC_TBF_FAILURE (DWORD)(GRLC_EVENT_BASE + 16)
+#define GRR_RLC_TESTPARAM_REQ (DWORD)(GRLC_EVENT_BASE + 17)
+#define RLC_DATA_REQ (DWORD)(GRLC_EVENT_BASE + 18)
+#define RLC_UNITDATA_REQ (DWORD)(GRLC_EVENT_BASE + 19)
+#define RLC_CLEAR_QUEUE_REQ (DWORD)(GRLC_EVENT_BASE + 20)
+#define LL_RLC_RESUME_MM_REQ (DWORD)(GRLC_EVENT_BASE + 21)
+#define LL_RLC_RESUME_ALL_REQ (DWORD)(GRLC_EVENT_BASE + 22)
+#define RLC_ASSIGN_REQ (DWORD)(GRLC_EVENT_BASE + 23)
+#define RLC_RESET_REQ (DWORD)(GRLC_EVENT_BASE + 24)
+#define MAC_RLC_UPLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 25)
+#define MAC_RLC_UPLINK_PDCH_FAIL (DWORD)(GRLC_EVENT_BASE + 26)
+#define MAC_RLC_REL_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 27)
+#define MAC_RLC_UPLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 28)
+#define MAC_RLC_UPLINK_PDCH_CNF (DWORD)(GRLC_EVENT_BASE + 29)
+#define MAC_RLC_DOWNLINK_PDCH_IND (DWORD)(GRLC_EVENT_BASE + 30)
+#define MAC_RLC_DATA_IND (DWORD)(GRLC_EVENT_BASE + 31)
+#define MAC_RLC_UPLINK_DATA_IND (DWORD)(GRLC_EVENT_BASE + 32)
+#define MAC_RLC_ERROR_IND (DWORD)(GRLC_EVENT_BASE + 33)
+#define MAC_RLC_DEACT_REQ (DWORD)(GRLC_EVENT_BASE + 34)
+#define MAC_RLC_STATUS_IND (DWORD)(GRLC_EVENT_BASE + 35)
+#define MAC_RLC_TLLI_IND (DWORD)(GRLC_EVENT_BASE + 36)
+#define MAC_RLC_DOWNLINK_PDCH_REL_IND (DWORD)(GRLC_EVENT_BASE + 37)
+#define UPL_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 38)
+#define PTBF_REL_TIMER (DWORD)(GRLC_EVENT_BASE + 39)
+#define T3168 (DWORD)(GRLC_EVENT_BASE + 40)
+#define T3182 (DWORD)(GRLC_EVENT_BASE + 41)
+#define RLC_ENG_MODE_TIMER (DWORD)(GRLC_EVENT_BASE + 42)
+#define GRR_RLC_PSHO_REQ_EV (DWORD)(GRLC_EVENT_BASE + 43)
+#define GRR_RLC_PSHO_SUCC_EV (DWORD)(GRLC_EVENT_BASE + 44)
+#define GRR_RLC_PSHO_FAIL_EV (DWORD)(GRLC_EVENT_BASE + 45)
+
+ /* END OF RLC */
+
+ /* START OF SNP */
+#define SN_DL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 0)
+#define SN_UL_REGISTER_REQ (DWORD)(SNDCP_EVENT_BASE + 1)
+#define SN_NPDU_DEL_REQ (DWORD)(SNDCP_EVENT_BASE + 2)
+#define SN_NPDU_AVAIL_REQ (DWORD)(SNDCP_EVENT_BASE + 3)
+#define SN_DATA_REQ (DWORD)(SNDCP_EVENT_BASE + 4)
+#define SN_UNITDATA_REQ (DWORD)(SNDCP_EVENT_BASE + 5)
+#define SN_IR_UL_SUSPEND_RSP (DWORD)(SNDCP_EVENT_BASE + 6)
+#define SN_XID_REQ (DWORD)(SNDCP_EVENT_BASE + 7)
+#define SNSM_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 8)
+#define SNSM_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 9)
+#define SNSM_ASSIGN_IND (DWORD)(SNDCP_EVENT_BASE + 10)
+#define SNSM_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 11)
+#define SNSM_MODIFY_IND (DWORD)(SNDCP_EVENT_BASE + 12)
+#define SNSM_IR_ACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 13)
+#define SNSM_IR_DEACTIVATE_IND (DWORD)(SNDCP_EVENT_BASE + 14)
+#define SNSM_IR_SEQUENCE_IND (DWORD)(SNDCP_EVENT_BASE + 15)
+#define SNPDU_AVAIL_IND (DWORD)(SNDCP_EVENT_BASE + 16)
+#define SNPDU_DEL_CNF (DWORD)(SNDCP_EVENT_BASE + 17)
+#define SNPDU_DEL_IND (DWORD)(SNDCP_EVENT_BASE + 18)
+#define LL_ESTABLISH_CNF (DWORD)(SNDCP_EVENT_BASE + 19)
+#define LL_ESTABLISH_IND (DWORD)(SNDCP_EVENT_BASE + 20)
+#define LL_RELEASE_CNF (DWORD)(SNDCP_EVENT_BASE + 21)
+#define LL_RELEASE_IND (DWORD)(SNDCP_EVENT_BASE + 22)
+#define LL_STATUS_IND (DWORD)(SNDCP_EVENT_BASE + 23)
+#define LL_RESET_IND (DWORD)(SNDCP_EVENT_BASE + 24)
+#define LL_RESET_PSHO_IND (DWORD)(SNDCP_EVENT_BASE + 25)
+#define LL_DATA_CNF (DWORD)(SNDCP_EVENT_BASE + 26)
+#define LL_XID_CNF (DWORD)(SNDCP_EVENT_BASE + 27)
+#define LL_XID_IND (DWORD)(SNDCP_EVENT_BASE + 28)
+#define LL_DATA_IND (DWORD)(SNDCP_EVENT_BASE + 29)
+#define LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 30)
+#define TIME_REEST (DWORD)(SNDCP_EVENT_BASE + 31)
+#define TIME_LL_UNITDATA_IND (DWORD)(SNDCP_EVENT_BASE + 32)
+#define TIME_UACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 33)
+#define TIME_ACK_XOFF (DWORD)(SNDCP_EVENT_BASE + 34)
+ /* END OF SNP */
+
+ /* START OF GSMA */
+#define LLSMS_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 0)
+#define SN_NPDU_DEL_IND (DWORD)(GSMA_EVENT_BASE + 1)
+#define SN_NPDU_AVAIL_IND (DWORD)(GSMA_EVENT_BASE + 2)
+#define SN_DATA_IND (DWORD)(GSMA_EVENT_BASE + 3)
+#define SN_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 4)
+#define SN_IR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 5)
+#define SN_IR_TO_UMTS_IND (DWORD)(GSMA_EVENT_BASE + 6)
+#define RR_TESTPARAM_IND (DWORD)(GSMA_EVENT_BASE + 7)
+#define RR_ABORT_IND (DWORD)(GSMA_EVENT_BASE + 8)
+#define RR_ACT_CNF (DWORD)(GSMA_EVENT_BASE + 9)
+#define RR_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 10)
+#define RR_ACT_FAIL (DWORD)(GSMA_EVENT_BASE + 11)
+#define RR_CELL_PARAMETER_IND (DWORD)(GSMA_EVENT_BASE + 12)
+#define RR_ACT_IND (DWORD)(GSMA_EVENT_BASE + 13)
+#define RR_DEACT_CNF (DWORD)(GSMA_EVENT_BASE + 14)
+#define RR_PLMN_CNF (DWORD)(GSMA_EVENT_BASE + 15)
+#define RR_PLMN_REJ (DWORD)(GSMA_EVENT_BASE + 16)
+#define RR_PLMN_IND (DWORD)(GSMA_EVENT_BASE + 17)
+#define RR_PLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 18)
+#define RR_REL_IND (DWORD)(GSMA_EVENT_BASE + 19)
+#define RR_TBF_EST_IND (DWORD)(GSMA_EVENT_BASE + 20)
+#define RR_TBF_REL_IND (DWORD)(GSMA_EVENT_BASE + 21)
+#define RR_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 22)
+#define RR_HPLMN_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 23)
+#define RR_HPLMN_ACT_REJ (DWORD)(GSMA_EVENT_BASE + 24)
+#define RR_EST_CNF (DWORD)(GSMA_EVENT_BASE + 25)
+#define RR_EST_IND (DWORD)(GSMA_EVENT_BASE + 26)
+#define RR_CELL_IND (DWORD)(GSMA_EVENT_BASE + 27)
+#define RR_DATA_IND (DWORD)(GSMA_EVENT_BASE + 28)
+#define RR_SYNC_IND (DWORD)(GSMA_EVENT_BASE + 29)
+#define GMMRR_PAGE_IND (DWORD)(GSMA_EVENT_BASE + 30)
+#define GMMRR_SUSPEND_IND (DWORD)(GSMA_EVENT_BASE + 31)
+#define GMMRR_CELL_UPDATE_IND (DWORD)(GSMA_EVENT_BASE + 32)
+#define RR_DATA_REJ (DWORD)(GSMA_EVENT_BASE + 33)
+#define RR_EST_REJ (DWORD)(GSMA_EVENT_BASE + 34)
+#define RR_HO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 35)
+#define RR_HO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 36)
+#define RR_HO_START_IND (DWORD)(GSMA_EVENT_BASE + 37)
+#define RR_IRAT_RESEL_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 38)
+#define RR_IRAT_RESEL_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 39)
+#define RR_IRAT_RESEL_START_IND (DWORD)(GSMA_EVENT_BASE + 40)
+#define RR_CCO_COMPLETE_IND (DWORD)(GSMA_EVENT_BASE + 41)
+#define RR_CCO_FAIL_IND (DWORD)(GSMA_EVENT_BASE + 42)
+#define RR_CCO_START_IND (DWORD)(GSMA_EVENT_BASE + 43)
+#define RR_RAT_CHN_IND (DWORD)(GSMA_EVENT_BASE + 44)
+#define RR_TEST_COUNT_CNF (DWORD)(GSMA_EVENT_BASE + 45)
+#define LLGMM_STATUS_IND (DWORD)(GSMA_EVENT_BASE + 46)
+#define LLGMM_TRIGGER_IND (DWORD)(GSMA_EVENT_BASE + 47)
+#define LLGMM_USER_DATA_PRESENT (DWORD)(GSMA_EVENT_BASE + 48)
+#define LLGMM_UNITDATA_IND (DWORD)(GSMA_EVENT_BASE + 49)
+#define RR_START_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 50)
+#define RR_END_CELL_RESEL_IND (DWORD)(GSMA_EVENT_BASE + 51)
+#define RR_ADD_CELL_RESEL_INFO_IND (DWORD)(GSMA_EVENT_BASE + 52)
+#define RLC_BLOCK_INFO_IND (DWORD)(GSMA_EVENT_BASE + 53)
+#define RRMN_MEAS_RESULTS_CNF (DWORD)(GSMA_EVENT_BASE + 54)
+#define MNRR_CIPHERING_IND (DWORD)(GSMA_EVENT_BASE + 55)
+#define SN_XID_CNF (DWORD)(GSMA_EVENT_BASE + 56)
+#define RR_RRL_DATA_IND (DWORD)(GSMA_EVENT_BASE + 57)
+#define RR_RRL_ABORT_EVENT_IND (DWORD)(GSMA_EVENT_BASE + 58)
+#define RR_RRL_CLASSMARK_IND (DWORD)(GSMA_EVENT_BASE + 59)
+#define SNSM_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 60)
+#define SNSM_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 61)
+#define SNSM_MODIFY_RSP (DWORD)(GSMA_EVENT_BASE + 62)
+#define SNSM_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 63)
+#define SNSM_STATUS_REQ (DWORD)(GSMA_EVENT_BASE + 64)
+#define SNSM_IR_ACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 65)
+#define SNSM_IR_DEACTIVATE_RSP (DWORD)(GSMA_EVENT_BASE + 66)
+#define SNSM_IR_SEQUENCE_RSP (DWORD)(GSMA_EVENT_BASE + 67)
+#define URRC_RESEL_REQ (DWORD)(GSMA_EVENT_BASE + 68)
+#define URRC_SET_INACTIVE_REQ (DWORD)(GSMA_EVENT_BASE + 69)
+#define RR_SET_INACTIVE_CNF (DWORD)(GSMA_EVENT_BASE + 70)
+#define URRC_READ_PREDEF_CONF_REQ (DWORD)(GSMA_EVENT_BASE + 71)/*WCDMAÏÂʹÓÃ*/
+#define URRC_ABORT_READ_PREDEF_REQ (DWORD)(GSMA_EVENT_BASE + 72)/*WCDMAÏÂʹÓÃ*/
+#define URRC_L1_RSRC_REQ (DWORD)(GSMA_EVENT_BASE + 73)
+#define URRC_L1_RSRC_FREE_IND (DWORD)(GSMA_EVENT_BASE + 74)
+#define RR_L1_RSRC_CNF (DWORD)(GSMA_EVENT_BASE + 75)
+#define RR_L1_RSRC_REJ (DWORD)(GSMA_EVENT_BASE + 76)
+#define RR_CELL_SEARCH_CNF (DWORD)(GSMA_EVENT_BASE + 77)
+#define RR_CELL_SEARCH_REJ (DWORD)(GSMA_EVENT_BASE + 78)
+#define URRC_CELL_SEARCH_REQ (DWORD)(GSMA_EVENT_BASE + 79)
+#define URRC_HO_INFO_REQ (DWORD)(GSMA_EVENT_BASE + 80)
+#define URRC_HO_REQ (DWORD)(GSMA_EVENT_BASE + 81)
+#define URRC_VSD_INFO (DWORD)(GSMA_EVENT_BASE + 82)
+#define RR_HO_CNF (DWORD)(GSMA_EVENT_BASE + 83)
+#define RR_HO_REJ (DWORD)(GSMA_EVENT_BASE + 84)
+#define URRC_CELL_CHANGE_REQ (DWORD)(GSMA_EVENT_BASE + 85)
+#define RR_CELL_CHANGE_CNF (DWORD)(GSMA_EVENT_BASE + 86)
+#define RR_CELL_CHANGE_REJ (DWORD)(GSMA_EVENT_BASE + 87)
+#define RR_RESEL_CNF (DWORD)(GSMA_EVENT_BASE + 88)
+#define RR_RESEL_REJ (DWORD)(GSMA_EVENT_BASE + 89)
+
+#define ERRC_RESEL_REQ_EV (DWORD)(GSMA_EVENT_BASE + 90)
+#define ERRC_CELL_SEARCH_REQ_EV (DWORD)(GSMA_EVENT_BASE + 91)
+#define RR_IRAT_PSHO_START_IND_EV (DWORD)(GSMA_EVENT_BASE + 92)
+#define RR_IRAT_PSHO_COMPLETE_IND_EV (DWORD)(GSMA_EVENT_BASE + 93)
+#define RR_IRAT_PSHO_FAIL_IND_EV (DWORD)(GSMA_EVENT_BASE + 94)
+#define URRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 95)
+#define ERRC_PSHO_REQ_EV (DWORD)(GSMA_EVENT_BASE + 96)
+#define RR_PSHO_CNF_EV (DWORD)(GSMA_EVENT_BASE + 97)
+#define RR_PSHO_REJ_EV (DWORD)(GSMA_EVENT_BASE + 98)
+#define ERRC_CELL_CHANGE_REQ_EV (DWORD)(GSMA_EVENT_BASE + 99)
+#define RR_ETWS_DATA_IND_EV (DWORD)(GSMA_EVENT_BASE + 100)
+#define LLGMM_PSHO_IND_EV (DWORD)(GSMA_EVENT_BASE + 101)
+#define RLC_SM_CURR_BEAR_IND_EV (DWORD)(GSMA_EVENT_BASE + 102)
+#define RR_SENDCMP_IND_EV (DWORD)(GSMA_EVENT_BASE + 103)
+#define RR_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 104)
+#define RR_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 105)
+#define RR_ABORT_CGI_REQ (DWORD)(GSMA_EVENT_BASE + 106)
+#define RR_ABORT_CGI_CNF (DWORD)(GSMA_EVENT_BASE + 107)
+#define RR_XCELLINFO_CNF (DWORD)(GSMA_EVENT_BASE + 108)
+#define RR_XCELLINFO_REJ (DWORD)(GSMA_EVENT_BASE + 109)
+#define RR_XCELLINFO_ABORT_CNF (DWORD)(GSMA_EVENT_BASE + 110)
+
+
+ /* START OF LLC */
+#define LLC_START_TIMER_T200 (DWORD)(GLLC_EVENT_BASE + 0)
+#define LLC_START_TIMER_T201 (DWORD)(GLLC_EVENT_BASE + 1)
+#define LLSMS_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 2)
+#define LLGMM_ASSIGN_REQ (DWORD)(GLLC_EVENT_BASE + 3)
+#define LLGMM_RESUME_REQ (DWORD)(GLLC_EVENT_BASE + 4)
+#define LLGMM_SUSPEND_REQ (DWORD)(GLLC_EVENT_BASE + 5)
+#define LLGMM_TRIGGER_REQ (DWORD)(GLLC_EVENT_BASE + 6)
+#define LLGMM_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 7)
+#define LLGMM_CELL_NOTIFICATION_REQ (DWORD)(GLLC_EVENT_BASE + 8)
+#define SNPDU_AVAIL_REQ (DWORD)(GLLC_EVENT_BASE + 9)
+#define SNPDU_DEL_REQ (DWORD)(GLLC_EVENT_BASE + 10)
+#define SNPDU_DEL_RSP (DWORD)(GLLC_EVENT_BASE + 11)
+#define LL_CONFIG_REQ (DWORD)(GLLC_EVENT_BASE + 12)
+#define LL_ESTABLISH_REQ (DWORD)(GLLC_EVENT_BASE + 13)
+#define LL_ESTABLISH_RSP (DWORD)(GLLC_EVENT_BASE + 14)
+#define LL_RELEASE_REQ (DWORD)(GLLC_EVENT_BASE + 15)
+#define LL_DATA_REQ (DWORD)(GLLC_EVENT_BASE + 16)
+#define LL_UNITDATA_REQ (DWORD)(GLLC_EVENT_BASE + 17)
+#define LL_XID_REQ (DWORD)(GLLC_EVENT_BASE + 18)
+#define LL_XID_RSP (DWORD)(GLLC_EVENT_BASE + 19)
+#define GRR_LLC_PSHO_SUCCESS_IND (DWORD)(GLLC_EVENT_BASE + 20)
+#define RRC_LLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 21)
+#define RLC_DATA_IND (DWORD)(GLLC_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND (DWORD)(GLLC_EVENT_BASE + 23)
+#define RLC_DATA_CNF (DWORD)(GLLC_EVENT_BASE + 24)
+#define RLC_UNITDATA_CNF (DWORD)(GLLC_EVENT_BASE + 25)
+#define RLC_CLEAR_QUEUE_CNF (DWORD)(GLLC_EVENT_BASE + 26)
+#define RLC_CLEAR_QUEUE_IND (DWORD)(GLLC_EVENT_BASE + 27)
+#define RLC_DATA_BUFF_IND (DWORD)(GLLC_EVENT_BASE + 28)
+#define LLC_T200 (DWORD)(GLLC_EVENT_BASE + 29)
+#define T201 (DWORD)(GLLC_EVENT_BASE + 30)
+#define LLC_T100_EV (DWORD)(GLLC_EVENT_BASE + 31)
+ /* END OF LLC */
+
+/* ========================================================================
+ MM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define MM_T3210_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 0)
+#define MM_T3211_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 1)
+#define MM_T3212_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 2)
+#define MM_T3213_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 3)
+#define MM_T3214_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 4)
+#define MM_T3216_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 5)
+#define MM_T3218_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 6)
+#define MM_T3220_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 7)
+#define MM_T3221_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 8)
+#define MM_T3230_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 9)
+#define MM_T3240_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 10)
+#define MM_T3241_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 11)
+#define MM_T3225_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 12)
+#define MM_T3222_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 13)
+#define MM_T3231_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 14)
+#define MM_T3232_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 15)
+#define MM_TWRRR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 16)
+#define MM_TWPGR_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 17)
+#define MM_TCCSRV_EXPIRY_EV (DWORD)(MM_TIMER_EVENT_BASE + 18)
+
+/* ========================================================================
+ GMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define GMM_T_READY_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 0)
+#define GMM_T3310_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 1)
+#define GMM_T3330_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 2)
+#define GMM_T3317_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 3)
+#define GMM_T3321_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 4)
+#define GMM_T3316_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 5)
+#define GMM_T3318_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 6)
+#define GMM_T3320_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 7)
+#define GMM_T_WRRC_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 8)
+#define GMM_T_WRRR_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 9)
+#define GMM_T_POWER_OFF_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 10)
+#define GMM_T_WSPN_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 11)
+#define GMM_T_WCRS_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 12)
+#define GMM_T_WTRG_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 13)
+#define GMM_T_PAGE_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 14)
+#define GMM_T3319_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 15)
+#define GMM_T_WREL_EXPIRY_EV (DWORD)(GMM_TIMER_EVENT_BASE + 16)/*EC614000821119*/
+/* ========================================================================
+ UMM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_T3212_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 0)
+#define UMM_T3311_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 1)
+#define UMM_T3302_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 2)
+#define UMM_T3312_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 3)
+#define UMM_T_NOCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 4)
+#define UMM_T_LIMIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 5)
+#define UMM_T_DELLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 6)
+#define UMM_T_SHHPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 7)
+#define UMM_T_UICCINIT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 8) /* ¼àÊÓ¿¨³õʼ»¯¶¨Ê±Æ÷ */
+#define UMM_T_CAMPON_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 9) /* ¼àÊÓפÁô¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_DETACH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 10) /* ¼àÊӹػúÈ¥»î¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T_LIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 11) /* ÖØÊÔPLMNÁÐ±í¶¨Ê±Æ÷ */
+#define UMM_T_PLMNLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 12) /* Áбí¹ý³Ì¶¨Ê±Æ÷ */
+#define UMM_T3411_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 13)
+#define UMM_T3402_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 14)
+#define UMM_T3412_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 15)
+#define UMM_T3442_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 16)
+#define UMM_T_PROC_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 17)
+#define UMM_T_FOCSGLIST_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 18)
+#define UMM_T3323_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 19)
+#define UMM_T3423_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 20)
+#define UMM_TBGSEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 21) /*LTE±³¾°ËÑË÷ÖÜÆÚ¶¨Ê±Æ÷*/
+#define UMM_T_IMSREG_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 22)
+#define UMM_T_NORMALFAILPLMN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 23)
+#define UMM_T_ENABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 24)
+#define UMM_T_DISABLE_EUTRAN_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 25)
+#define UMM_T_LOOPTIME_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 26)
+#define UMM_T_DISFRESEARCH_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 27)
+#define UMM_T_RESETCAUSEPAR_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 28)
+#define UMM_T_SWITCHCARD_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 29)
+#define UMM_T_ARREARS_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 30)
+#define UMM_TSEARCHECALLCELL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 31)
+#define UMM_TECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 32)
+#define UMM_TTESTECALL_INACT_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 33)
+#define UMM_T_IMSREL_EXPIRY_EV (DWORD)(UMM_TIMER_EVENT_BASE + 34)
+/* ========================================================================
+ CC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CC_T303_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 0)
+#define CC_T305_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 1)
+#define CC_T308_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 2)
+#define CC_T310_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 3)
+#define CC_T313_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 4)
+#define CC_T335_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 5) /*CCBS*/
+#define CC_T332_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 6)
+#define CC_T323_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 7)
+#define CC_T336_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 8)
+#define CC_T337_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 9)
+
+/* ADD A TIMER FOR CALL CONFIRM MESSAGE */
+#define CC_T_CALLCNF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 10)
+
+/* ADD TIMER FOR AOC */
+#define CC_T_ACMUPD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 11)
+#define CC_T_CDUR_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 12)
+
+#define CC_T_HOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 13)
+#define CC_T_RETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 14)
+
+#define CC_T_MPTYBUILD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 15)
+#define CC_T_MPTYHOLD_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 16)
+#define CC_T_MPTYRETRIEVE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 17)
+#define CC_T_MPTYSPLIT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 18)
+
+#define CC_T322_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 19)
+#define CC_T_SUPPER_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 20)
+#define CC_T_MMCONN_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 21)
+
+#define CC_T_RELTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 22)
+#define CC_T_CONNTAF_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 23)
+#define CC_T_SYNCIND_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 24)
+#define CC_T_MODIFYBC_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 25)
+#define CC_T_DTMFDURA_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 26)
+#define CC_T_MMCONNRETRY_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 27)
+#define CC_T_ALLOWEDCALL_TIME_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 28)
+#define CC_T_ECT_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 29)
+#define CC_T_T2_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 30)
+#define CC_T_T5_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 31)
+#define CC_T_T6_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 32)
+#define CC_T_T7_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 33)
+#define CC_T_TIDLE_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 34)
+#define CC_T_T9_EXPIRY_EV (DWORD)(CC_TIMER_EVENT_BASE + 35)
+
+/* ========================================================================
+ SMS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SMS_TR1M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 0) /* FOR MO SM.*/
+#define SMS_TRAM_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 1) /* FOR MO SM.*/
+#define SMS_TC1M_MO_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 2) /* FOR MO SM.*/
+#define SMS_TMMS_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 3) /* FOR MO SM.*/
+#define SMS_TR2M_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 4) /* FOR MT SM.*/
+#define SMS_TC1M_MT_EXPIRY_EV (DWORD)(SMS_TIMER_EVENT_BASE + 5) /* FOR MT SM.*/
+/* ========================================================================
+ SS¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SS_T_WAIT_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 0)
+#define SS_T_MOLRTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 1)
+#define SS_T_MOLRINTERTIME_EXPIRY_EV (DWORD)(SS_TIMER_EVENT_BASE + 2)
+#ifdef _USE_SIG_TRACE
+#define SS_DL_L3FACILITY_EV (DWORD)(SS_TIMER_EVENT_BASE + 3)
+#define SS_DL_L3MTREG_EV (DWORD)(SS_TIMER_EVENT_BASE + 4)
+#define SS_DL_L3RELCOMP_EV (DWORD)(SS_TIMER_EVENT_BASE + 5)
+#endif
+
+
+/* ========================================================================
+ SM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SM_T3380_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 0)
+#define SM_T3381_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 1)
+#define SM_T3390_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 2)
+#define SM_T_CMEST_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 3)
+#define SM_T_PDPHANDLE_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 4)
+#define SM_T_APPANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 5)
+#define SM_T_AUTOANSMTACT_EXPIRY_EV (DWORD)(SM_TIMER_EVENT_BASE + 6)
+
+/* ========================================================================
+ CBS¶¨Ê±Æ÷ ÏûÏ¢ºÅµÄ¶¨Òå
+======================================================================== */
+#define CBS_T_SCHEDCHECK_EXPIRY_EV (DWORD)(CBS_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ UICC¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UICC_CARD_DETECT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 0)
+#define UICC_CARD_USAT_EXPIRY_EV (DWORD)(UICC_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ URRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define USIR_T_BCH_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 0)
+#define USIR_T_SIB7_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 1)
+#define USIR_T_VTSIB_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 2)
+#define USIR_T_R_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 3)
+#define USIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 4)
+#define UCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 5)
+#define UCSR_T_HYSTX_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 6)
+#define UCSR_T_PROTECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 7)
+#define UCSR_T_NCELL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 8)
+#define UCSR_T_OOS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 9)
+#define UCSR_T_CAMP1S_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define UCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 11)
+#define UCSR_T_REDIRECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 12)
+#define UMCR_T_RESELECT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 13)
+#define UMCR_T_PERIOD_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 14)
+#define UMCR_T_TRIGGER_EV (DWORD)(URRC_TIMER_EVENT_BASE + 15)
+#define UMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 16)
+#define UCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 17)
+#define UCER_T_ETWS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 18)
+#define UCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 19)
+#define URRC_T300_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 20)
+#define URRC_T302_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 21)
+#define URRC_T304_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 22)
+#define URRC_T305_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 23)
+#define URRC_T307_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 24)
+#define URRC_T308_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 25)
+#define URRC_T309_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 26)
+#define URRC_T312_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 27)
+#define URRC_T313_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 28)
+#define URRC_T314_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 29)
+#define URRC_T315_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 30)
+#define URRC_T316_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 31)
+#define URRC_T319_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 32)
+#define URRC_T320_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 33)
+#define UMCR_T322_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 34)
+#define URRC_T323_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 35)
+#define URRC_T325_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 36)
+#define URRC_T_WAIT_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 37)
+#define UCSR_T_LBS_EXPIRY_EV (DWORD)(URRC_TIMER_EVENT_BASE + 38)
+
+/* ========================================================================
+ UPDCP¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDCP_T_RABREEST_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 0)
+#define PDCP_T_SNSYNC_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 1)
+#define PDCP_T_DATAMONITOR_EXPIRY_EV (DWORD)(PDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ URLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define URLC_T_DISCARD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 0)
+#define URLC_T_POLL_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 1)
+#define URLC_T_POLLPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 2)
+#define URLC_T_POLLPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 3)
+#define URLC_T_STATUSPROH_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 4)
+#define URLC_T_STATUSPRD_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 5)
+#define URLC_T_RESET_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 6)
+#define URLC_T_MRW_EXPIRY_EV (DWORD)(URLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ UMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define UMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 0)
+#define UMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 1)
+#define UMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 2)
+#define UMAC_T_RACHPROC_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 3)
+#define UMAC_T_HSTIMER_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 4)
+#define UMAC_T_RESET_EXPIRY_EV (DWORD)(UMAC_TIMER_EVENT_BASE + 5)
+
+
+/* ========================================================================
+ L1T¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define L1T_T_BSIC_EXPIRY_EV (DWORD)(L1T_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ TAF¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define TAF_T_PROC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 0)
+#define TAF_T_DISC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 1)
+#define TAF_T_RA_TSYNC_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 2)
+#define TAF_T_RA_TSYNCEND_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 3)
+#define TAF_T_RA_TSBFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 4)
+#define TAF_T_RA_TXFILTER_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 5)
+#define TAF_T_RLP_TRCVR_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 6)
+#define TAF_T_RLP_TRCVS_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 7)
+#define TAF_T_RLP_TTEST_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 8)
+#define TAF_T_RLP_TXID_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 9)
+#define TAF_T_RLP_T_EXPIRY_EV (DWORD)(TAF_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ GSMA¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ ROHCv1¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 0)
+#define ROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 1)
+#define ENROHCv1_T_IR_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 2)
+#define ENROHCv1_T_SO2FO_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 3)
+#define ROHCv1_T_NACK_FDBK_CNT_EXPIRY_EV (DWORD)(ROHCv1_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ ROHCv2¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define ROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 0)
+#define ENROHCv2_T_IR_EXPIRY_EV (DWORD)(ROHCv2_TIMER_EVENT_BASE + 1)
+
+/* ========================================================================
+ PDI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define PDI_T_SWITCHLED_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 0)
+#define PDI_T_WAITDNSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 1)
+#define PDI_T_WAITZSSACK_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 2)
+#define PDI_T_WAIT_BUF_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 3)
+#define PDI_LOOPB_TIMER_EXPIRY_EV (DWORD)(PDI_TIMER_EVENT_BASE + 4)
+
+/* ========================================================================
+ SCI¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define SCI_T_VOICE_FRAME_EXPIRY_EV (DWORD)(SCI_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ STM¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define STM_MEMAVAILD_EXPIRY_EV (DWORD)(STM_TIMER_EVENT_BASE + 0)
+
+/*========================================================================
+USAT¶¨Ê±Æ÷¶¨Òå
+========================================================================*/
+#define USAT_TIMERMNG_TIMER1_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 0)
+#define USAT_TIMERMNG_TIMER2_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 1)
+#define USAT_TIMERMNG_TIMER3_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 2)
+#define USAT_TIMERMNG_TIMER4_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 3)
+#define USAT_TIMERMNG_TIMER5_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 4)
+#define USAT_TIMERMNG_TIMER6_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 5)
+#define USAT_TIMERMNG_TIMER7_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 6)
+#define USAT_TIMERMNG_TIMER8_EXPIRY_EV (DWORD)(USAT_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ È«¾ÖÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define FOR_TEST_TEMP_EV (DWORD)(PRI_TEST_EVENT_BASE + 0)
+#define TEST_SET_UICC_RLT_EV (DWORD)(PRI_TEST_EVENT_BASE + 1)
+#define TEST_SET_UICC_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 2)
+#define TEST_SET_NV_DATA_EV (DWORD)(PRI_TEST_EVENT_BASE + 3)
+#define TEST_SET_NV_DATA_IMEI_EV (DWORD)(PRI_TEST_EVENT_BASE + 4)
+#define TEST_SET_NV_DATA_SPCLFUNC_EV (DWORD)(PRI_TEST_EVENT_BASE + 5)
+#define TEST_SET_COMP_IND_EV (DWORD)(PRI_TEST_EVENT_BASE + 6)
+/* ========================================================================
+ Ä£ÄâTAFÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_TAFDATAIND_UTRAN_EV (DWORD)(TAF_TEST_EVENT_BASE + 0)
+
+/* ========================================================================
+ USIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_BIGSIB_IND_EV (DWORD)(USIR_TEST_EVENT_BASE + 0)
+#define TEST_USIR_DECSIB_EV (DWORD)(USIR_TEST_EVENT_BASE + 1)
+
+/* ========================================================================
+ NURLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UURLC_DATA_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 0)
+#define TEST_UURLC_DATA_IND_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 1)
+#define TEST_CURLC_CONFIG_REQ_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 2)
+#define TEST_URLC_ACK_CTRL_UTRAN_EV (DWORD)(NURLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NPDCPÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CPDCP_CONFIG_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 0)
+#define CPDCP_RELEASE_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 1)
+#define NPDCP_DATA_REQ_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 2)
+#define NPDCP_DATA_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 3)
+#define TEST_NPDCP_DATA_ERR_IND_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 4)
+#define TEST_NPDCP_DATA_CNF_UTRAN_EV (DWORD)(NPDCP_EVENT_BASE + 5)
+
+/* ========================================================================
+ NUMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UMAC_ACK_CTRL_UTRAN_EV (DWORD)(NUMAC_EVENT_BASE + 0)
+#define TEST_UMAC_HSUPA_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 1)
+#define TEST_UMAC_HSUPA_CFG_EV (DWORD)(NUMAC_EVENT_BASE + 2)
+#define TEST_UMAC_HSUPA_SIINFO_EV (DWORD)(NUMAC_EVENT_BASE + 3)
+#define TEST_UMAC_HSUPA_HEADER_INFO_EV (DWORD)(NUMAC_EVENT_BASE + 4)
+#define TEST_UMAC_NOTIFY_DATA_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 5)
+#define TEST_UMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NUMAC_EVENT_BASE + 6)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UCBS_SCHED_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 0)
+#define TEST_UCBS_DATA_REQ_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 1)
+#define TEST_UCBS_OUTPUT_END_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 2)
+#define TEST_UCBS_UMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 3)
+#define TEST_UCBS_UMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 4)
+#define TEST_UURLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 5)
+/*WCDMA NCBS_EVENT_BASE=20 */
+#define TEST_UWRLC_DATA_CNF_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 6)
+#define TEST_UCBS_WMAC_TFS_CFG_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 7)
+#define TEST_UCBS_WMAC_SFN_INFO_UTRAN_EV (DWORD)(NCBS_EVENT_BASE + 8)
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TC_ACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 0)
+#define TC_ACTIVE_TEST_CNF_EV (DWORD)(TC_EVENT_BASE + 1)
+#define TC_DEACTIVE_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 2)
+#define TC_CLOSE_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 3)
+#define TC_CLOSE_LOOP_CNF_EV (DWORD)(TC_EVENT_BASE + 4)
+#define TC_CLOSE_LOOP_REQ_URLC_EV (DWORD)(TC_EVENT_BASE + 5)
+#define TC_OPEN_LOOP_REQ_EV (DWORD)(TC_EVENT_BASE + 6)
+/*wcdma TC_EVENT_BASE=30*/
+#define TC_CLOSE_LOOP_REQ_WRLC_EV (DWORD)(TC_EVENT_BASE + 7)
+//lte TC_EVERNT
+#define EMM_TC_TEST_CONTROL_REQ_EV (DWORD)(TC_EVENT_BASE + 8)
+#define TC_EMM_TEST_CONTROL_CNF_EV (DWORD)(TC_EVENT_BASE + 9)
+#define TC_PDI_OPEN_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 10)
+#define TC_PDI_CLOSE_LOOP_TEST_REQ_EV (DWORD)(TC_EVENT_BASE + 11)
+/* ========================================================================
+ L1SIMUÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1SIMU_START_EV (DWORD)(L1SIMU_EVENT_BASE + 0) /*Æô¶¯L1_SIMUÄ£¿é*/
+#define L1SIMU_NGMAC_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 1) /*L1_SIMU·¢ËÍÊý¾Ýµ½MAC_N*/
+#define L1SIMU_DLLN_DATA_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 2) /*L1_SIMU·¢ËÍÊý¾Ýµ½LAPDM*/
+#define TOOL_L1SIMU_CELL_MEAS_INFO_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 3) /*¹¤¾ß·¢ËÍFCBSBÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_SYSINFO_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 4) /*¹¤¾ß·¢ËÍϵͳÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_PAGING_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 5) /*¹¤¾ß·¢ËÍÑ°ºôÐÅÏ¢µ½L1_SIMU*/
+#define TOOL_L1SIMU_DCCH_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 6)
+#define TOOL_L1SIMU_DCCH_REL_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 7)
+#define L1SIMU_DLLN_CONNECT_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 8)
+#define L1SIMU_FRAME_INT_EV (DWORD)(L1SIMU_EVENT_BASE + 9)
+#define TOOL_L1SIMU_SYNC_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 10)
+#define TOOL_L1SIMU_SYSINFO_REJ_EV (DWORD)(L1SIMU_EVENT_BASE + 11)
+#define L1SIMU_DLLN_DATA_SENT_CMP_EV (DWORD)(L1SIMU_EVENT_BASE + 12) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define TOOL_L1SIMU_DCCH_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 13) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define TOOL_L1SIMU_SYSINFO_FAIL_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 14)
+#define L1SIMU_TOOL_RXLEV_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 15)
+#define L1SIMU_TOOL_SYNCREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 16)
+#define L1SIMU_TOOL_SYSREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 17)
+#define L1SIMU_TOOL_IDLE_MODE_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 18)
+#define L1SIMU_TOOL_NCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 19) /*L1SIMU֪ͨLAPDMN»º³åÇøÖÐÊý¾ÝÒÑ·¢Ë͵ô*/
+#define L1SIMU_TOOL_SCELL_RXLEV_IND_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 20) /*Á´Â·Ê§°ÜµÄ¿éÊý¿ØÖÆ*/
+#define L1SIMU_TOOL_MEAS_REPORT_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 21)
+#define L1SIMU_TOOL_DL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 22)
+#define L1SIMU_TOOL_UL_TBF_REL_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 23)
+#define L1SIMU_TOOL_TAF_IND_EV (DWORD)(L1SIMU_EVENT_BASE + 24)
+#define L1SIMU_TOOL_TAF_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 25)
+#define L1SIMU_TOOL_ASYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 26)
+#define L1SIMU_TOOL_SYNC_HO_REQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 27)
+#define TOOL_L1SIMU_CBS_BLK_START_EV (DWORD)(L1SIMU_EVENT_BASE + 28)
+#define TOOL_L1SIMU_CBS_FST_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 29)
+#define TOOL_L1SIMU_CBS_OTHER_BLK_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 30)
+#define L1SIMU_TOOL_PSHOREQ_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 31)
+#define L1SIMU_TOOL_DEACTIATE_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 32)
+#define TOOL_L1SIMU_ABNORMAL_TA_CFG_EV (DWORD)(L1SIMU_EVENT_BASE + 33)
+#define L1SIMU_TOOL_L1G_L1E_GSM_INACT_TIME_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 34)
+#define L1SIMU_TOOL_L1G_L1E_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 35)
+#define L1SIMU_TOOL_L1G_L1E_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 36)
+#define L1SIMU_TOOL_CHANNEL_ASSIGN_REQ_EV (DWORD)(L1SIMU_EVENT_BASE + 37)
+#define L1SIMU_TOOL_CHANNEL_TYPE_INFO_EV (DWORD)(L1SIMU_EVENT_BASE + 38)
+
+/* ========================================================================
+ NLAPDMÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLAPDM_UNIT_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 0) /*¹¤¾ßÏòLADPN·¢ËÍ·ÇÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_UNIT_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 1) /*LADPNÏò¹¤¾ßÉÏ´«·ÇÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_DATA_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 2) /*¹¤¾ßÏòLADPN·¢ËÍÈ·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 3) /*LADPNÏò¹¤¾ßÉÏ´«È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_ESTABLISH_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 4) /*¹¤¾ßÏòLADPN·¢Ëͽ¨Á´ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 5) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_ESTABLISH_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 6) /*LADPNÏò¹¤¾ß·¢Ëͽ¨Á´È·ÈÏÏûÏ¢*/
+#define NLAPDM_TOOL_SUSPEND_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 7) /*LADPNÏò¹¤¾ß·¢Ë͹ÒÆðÈ·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_RECONNECT_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 8) /*¹¤¾ßÏòLADPN·¢ËÍÖØÁ¬ÇëÇóÏûÏ¢*/
+#define TOOL_NLAPDM_RELEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 9) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·ÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 10) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·Ö¸Ê¾ÏûÏ¢*/
+#define NLAPDM_TOOL_RELEASE_CON_EV (DWORD)(NLAPDM_EVENT_BASE + 11) /*¹¤¾ßÏòLADPN·¢ËÍÊÍ·ÅÁ´Â·È·ÈÏÏûÏ¢*/
+#define TOOL_NLAPDM_MDL_CONFIG_EV (DWORD)(NLAPDM_EVENT_BASE + 12) /*¹¤¾ßÏòLADPN·¢ËͳõʼÅäÖÃÏûÏ¢*/
+#define NLAPDM_TOOL_MDL_ERROR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 13) /*LADPNÏò¹¤¾ß·¢ËÍ´íÎ󱨸æ*/
+#define TOOL_NLAPDM_MDL_REALEASE_REQ_EV (DWORD)(NLAPDM_EVENT_BASE + 14) /*¹¤¾ß·¢ÆðÒì³£±¾µØÊÍ·ÅÏûÏ¢*/
+#define NLAPDM_L2_DATA_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 15) /*SAPI0·¢ËÍÏûÏ¢µ½SAPI3*/
+#define NLAPDM_TOOL_SABM_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 16) /*NLAPDMÏò¹¤¾ß·¢ËÍÆÕͨ½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 17) /*¹¤¾ßÏòNLAPDM·¢ËÍÆÕͨ½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define NLAPDM_TOOL_SABM_COR_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 18) /*NLAPDMÏò¹¤¾ß·¢ËͳåÍ»½â¾ö½¨Á´ÇëÇóָʾÏûÏ¢*/
+#define TOOL_NLAPDM_UA_COR_RSP_EV (DWORD)(NLAPDM_EVENT_BASE + 19) /*¹¤¾ßÏòNLAPDM·¢ËͳåÍ»½â¾ö½¨Á´ÏìÓ¦ÏûÏ¢*/
+#define TOOL_NLAPDM_EXCEPT_DATA_EV (DWORD)(NLAPDM_EVENT_BASE + 20) /*¹¤¾ßÏòNLAPDM·¢ËÍÒì³£Êý¾ÝÇëÇóÏûÏ¢*/
+#define NLAPDM_TOOL_I_IND_EV (DWORD)(NLAPDM_EVENT_BASE + 21) /*NLAPDMÏò¹¤¾ß·¢ËÍÈ·ÈÏÊý¾ÝÉϱ¨Ö¸Ê¾ÏûÏ¢*/
+
+
+/* ========================================================================
+ NGMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NGMAC_START_EV (DWORD)(NGMAC_EVENT_BASE + 0) /*NGMACÄ£¿éÆô¶¯*/
+#define NGMAC_NGRLC_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 1) /*NGMAC¸øNGRLC·¢ËÍPDANÏûÏ¢*/
+#define NGMAC_NGRLC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 2) /*NGMAC¸øNGRLC·¢ËÍUPLINKÊý¾Ý¿é*/
+#define NGRLC_NGMAC_PUAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 3) /*NGRLC¸øNGMAC·¢ËÍPUANµÄ²ÎÊý*/
+#define NGMAC_NGRLC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 4) /*NGMAC֪ͨNGRLCÊÍ·ÅUPLINK TBF*/
+#define NGRLC_NGMAC_FBI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 5) /*RLC·ÇÈ·ÈÏģʽ£¬NGRLC֪ͨNGMAC×îÖÕ¿éÒÑ·¢³ö£¬NGMACµÈ´ýPCA*/
+#define NGMAC_NGRLC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 6) /*RLC·ÇÈ·ÈÏģʽ£¬NGMAC֪ͨNGRLCÊÍ·ÅTBF*/
+#define NGRLC_NGMAC_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 7) /*RLCÈ·ÈÏģʽ£¬NGRLC֪ͨNGMACÊÍ·ÅDOWNLINK TBF*/
+#define NGRLC_NGMAC_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 8) /*NGRLC֪ͨNGMACÒì³£ÊÍ·ÅUPLINK TBF*/
+#define NGMAC_NGRLC_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 9) /*NGMAC֪ͨNGRLC DOWNLINK_TBFÒѾÍêÈ«µÃµ½È·ÈÏ*/
+#define TOOL_NGMAC_PUA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 10) /*TOOL¸øNGMAC·¢ËÍPUA*/
+#define NGMAC_TOOL_PRR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 11) /*NGMAC¸øTOOL·¢ËÍPRR£¬Çé¿ö°üÀ¨£ºIDLE̬½¨Á¢µÄUPLINK TBF¡¢ULONULµÄTBF¡¢ULONDLµÄTBF*/
+#define NGMAC_TOOL_PDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 12) /*NGMAC¸øTOOL·¢ËÍPDANÏûÏ¢£¬½öÔÚÐèÒª½¨Á¢ULONDL TBFʱ²Å·¢*/
+#define TOOL_NGMAC_PUAN_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 13) /*TOOL¸øNGMAC·¢ËÍPUAN£¬½öÔÚ±àÂ뷽ʽ¡¢´°¿Ú´óС¡¢RESEGMENTµÈ¸Ä±äʱ²Å·¢*/
+#define TOOL_NGMAC_PDA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 14) /*TOOL¸øNGMAC·¢ËÍPDA*/
+#define NGMAC_TOOL_PCA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 15) /*NGMAC¸øTOOL·¢ËÍPCA£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR8_IND_EV (DWORD)(NGMAC_EVENT_BASE + 16) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_PCR11_IND_EV (DWORD)(NGMAC_EVENT_BASE + 17) /*NGMAC¸øTOOL·¢ËÍPCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_CR_IND_EV (DWORD)(NGMAC_EVENT_BASE + 18) /*NGMAC¸øTOOL·¢ËÍCR£¬Ö¸Ã÷½ÓÈëÀàÐÍÒÔ±ãTOOL´¦Àí*/
+#define NGMAC_TOOL_DLTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 19) /*NGMAC֪ͨTOOLÊÍ·ÅDOWNLINK TBF*/
+#define NGMAC_TOOL_ULTBF_REL_IND_EV (DWORD)(NGMAC_EVENT_BASE + 20) /*NGMAC֪ͨTOOLÊÍ·ÅUPLINK TBF*/
+#define NGMAC_TOOL_TLLI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 21) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬NGMAC¸øTOOLÇëÇóCONT_RES_TLLI*/
+#define TOOL_NGMAC_TLLI_IND_EV (DWORD)(NGMAC_EVENT_BASE + 22) /*Ò»²½½ÓÈë³åÍ»½â¾ö¹ý³Ì£¬TOOL¸øNGMAC·¢ËÍCONT_RES_TLLI*/
+#define TOOL_NGMAC_IMM_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 23) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨*/
+#define TOOL_NGMAC_IMM_EX_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 24) /*TOOL¸øNGMAC·¢ËÍÀ©Õ¹Á¢¼´É趨*/
+#define TOOL_NGMAC_IMM_REJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 25) /*TOOL¸øNGMAC·¢ËÍÁ¢¼´É趨¾Ü¾ø*/
+#define L1_NGMAC_DATA_IND_EV (DWORD)(NGMAC_EVENT_BASE + 26) /*L1_SIMU°Ñ´ÓL1G½ÓÊÕµ½µÄÉÏÐÐÊý¾Ý·¢Ë͵½MAC_N*/
+#define NGMAC_NGMAC_TMS_FBI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 27) /*FBI¶¨Ê±Æ÷³¬Ê±*/
+#define NGMAC_NGMAC_TMS_FAI_EXP_EV (DWORD)(NGMAC_EVENT_BASE + 28) /*FAI¶¨Ê±Æ÷³¬Ê±*/
+#define TOOL_NGMAC_PMO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 29) /*TOOL¸øNGMAC·¢ËÍPMO*/
+#define TOOL_NGMAC_PSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 30) /*TOOL¸øNGMAC·¢ËÍPSI*/
+#define NGMAC_TOOL_MSACC_IND_EV (DWORD)(NGMAC_EVENT_BASE + 31) /*NGMACÏòTOOLÇëÇóUPLINK TBF½¨Á¢»òÇëÇó½¨Á¢RRÁ¬½Ó*/
+#define TOOL_NGMAC_ULTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 32) /*TOOLÅäÖÃNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_EST_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 33) /*TOOLÅäÖÃNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_ULTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 34) /*TOOLÊÍ·ÅNGMACµÄULTBF²ÎÊý*/
+#define TOOL_NGMAC_DLTBF_REL_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 35) /*TOOLÊÍ·ÅNGMACµÄDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PKTTSRECFG_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 36) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TIMESLOT_RECONFIGUREµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTTBFREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 37) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_TBF_RELEASEµ½ÊÖ»ú²à*/
+#define TOOL_NGMAC_PKTPDCHREL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 38) /*TOOLÒªÇóNGMAC·¢ËÍPACKET_PDCH_RELEASEÏûÏ¢*/
+#define TOOL_NGMAC_PKTCCC_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 39) /*TOOLÒªÇóNGMAC·¢ËÍPACKET CELL CHANGE CONTINUE*/
+#define TOOL_NGMAC_PKTCCO_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 40) /*TOOLÇëÇóNGMAC·¢ËÍPACKET CELL CHANGE ORDER*/
+#define TOOL_NGMAC_PKTNCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 41) /*TOOLÇëÇóNGMAC·¢ËÍPACKET NEIGHBOUR CELL DATA*/
+#define TOOL_NGMAC_PKTPOLL_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 42) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POLLING REQUEST*/
+#define TOOL_NGMAC_PKTPWRCTRLTA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 43) /*TOOLÇëÇóNGMAC·¢ËÍPACKET POWER CTRL/TA*/
+#define TOOL_NGMAC_PKTPRACHPARA_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 44) /*TOOLÇëÇóNGMAC·¢ËÍPACKET PRACH PARAMETERS*/
+#define TOOL_NGMAC_PKTSCD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 45) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVE CELL DATA*/
+#define TOOL_NGMAC_PKTQUENOTI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 46) /*TOOLÇëÇóNGMAC·¢ËÍPACKET QUEUING NOTIFICATION*/
+#define TOOL_NGMAC_PKTACCREJ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 47) /*TOOLÇëÇóNGMAC·¢ËÍ·Ö×é½ÓÈë¾Ü¾ø*/
+#define NGMAC_TOOL_PKTMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 48) /*NGMAC½ÓÊÕµ½MS PACKET MEAS REPORT ºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTMOBTBFSTA_EV (DWORD)(NGMAC_EVENT_BASE + 49) /*NGMAC½ÓÊÕµ½MS PACKET MOBILE TBF STATUSºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTPSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 50) /*NGMAC½ÓÊÕµ½MS PACKET PSI STATUSºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTPAUSE_EV (DWORD)(NGMAC_EVENT_BASE + 51) /*NGMAC½ÓÊÕµ½MS PACKET PAUSEºó·¢ËÍÏûÏ¢µ½TOOL*/
+#define NGMAC_TOOL_PKTEMEARPT_EV (DWORD)(NGMAC_EVENT_BASE + 52) /*NGMAC½ÓÊÕµ½MS PACKET ENHANCED MEAS REPORTºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTADDMSRAC_EV (DWORD)(NGMAC_EVENT_BASE + 53) /*NGMAC½ÓÊÕµ½MS PACKET ADDITION MS RACºó·¢Ë͵½TOOL*/
+#define NGMAC_TOOL_PKTCCN_EV (DWORD)(NGMAC_EVENT_BASE + 54) /*NGMAC½ÓÊÕµ½MS PACKET CELL CHANGE NOTIFICATIONºó·¢Ë͵½¹¤¾ß*/
+#define NGMAC_TOOL_PKTSISTA_EV (DWORD)(NGMAC_EVENT_BASE + 55) /*NGMAC½ÓÊÕµ½MS PACKET SI STATUSºó·¢Ë͵½¹¤¾ß*/
+#define GMAC_GET_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 56) /*GMAC·¢ËÍÉÏÐÐÊý¾Ýʱµ÷Óú¯ÊýMAC_GET_BLOCKS,ΪÔö¼ÓTRACEÌí¼ÓµÄʼþºÅ*/
+#define GMAC_ACK_BLOCKS_EV (DWORD)(NGMAC_EVENT_BASE + 57) /*L1Gµ÷ÓÃMAC_ACK_BLOCKSʱΪÔö¼ÓÐÅÁî¸ú×Ù¶øÔö¼ÓµÄʼþºÅ*/
+#define TOOL_NGMAC_PKTPGREQ_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 58)
+#define TOOL_NGMAC_CTRLBLOCK_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 59)
+#define NGMAC_TOOL_CCF_IND_EV (DWORD)(NGMAC_EVENT_BASE + 60) /*NGMACÏòTOOL·¢Ë͵ÄPACKET CELL CHANGE FAILUREÏûÏ¢*/
+#define NGMAC_NGRLC_EPDAN_IND_EV (DWORD)(NGMAC_EVENT_BASE + 61) /*NGMAC¸øNGRLC·¢ËÍEPDANÏûÏ¢*/
+#define TOOL_NGMAC_PSHOCMD_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 62) /*TOOLÇëÇóNGMAC·¢ËÍPs Handover Command*/
+#define TOOL_NGMAC_PPI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 63) /*TOOLÇëÇóNGMAC·¢ËÍPacket Physical Information*/
+#define TOOL_NGMAC_PSHO_ULTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 64) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_DLTBF_CFG_EV (DWORD)(NGMAC_EVENT_BASE + 65) /*TOOLÅäÖÃNGMACµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGMAC_PSHO_RETURN_EV (DWORD)(NGMAC_EVENT_BASE + 66) /*TOOL ֪ͨNGMAC ×ÊÔ´»ØÍË*/
+#define TOOL_NGMAC_PSHO_REL_EV (DWORD)(NGMAC_EVENT_BASE + 67) /*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGMAC_TOOL_PSHO_ACC_EV (DWORD)(NGMAC_EVENT_BASE + 68) /*NGMACÏòTOOLÇëÇóPacket Physical Information*/
+#define TOOL_NGMAC_PKTSCELLSI_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 69) /*TOOLÇëÇóNGMAC·¢ËÍPACKET SERVING CELL SI*/
+#define TOOL_NGMAC_PKTAPPINF_REQ_EV (DWORD)(NGMAC_EVENT_BASE + 70) /*TOOLÇëÇóNGMAC·¢ËÍPACKET APPLICATION INFORMATION*/
+
+
+/* ========================================================================
+ NLLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TOOL_NLLC_START_EV (DWORD)(NLLC_EVENT_BASE + 0) /*NLLCÄ£¿éÆô¶¯*/
+#define NLLC_NRLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 1) /*֪ͨNRLCÒÔ·ÇÈ·ÈÏģʽ´«ÊäLLC-PDU*/
+#define NRLC_NLLC_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 2) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸öÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define NRLC_NLLC_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 3) /*RLC-NÉϱ¨LLC-N½ÓÊÕµ½ÁËÒ»¸ö·ÇÈ·ÈÏģʽµÄÉÏÐÐLLC PDU*/
+#define TOOL_NLLC_ASSIGN_REQ_EV (DWORD)(NLLC_EVENT_BASE + 4) /*¹¤¾ß֪ͨ NLLCÓÐеļÓÃÜËã·¨ºÍ²ÎÊý£¬ÒÔ¼°·ÖÅäTLLI*/
+#define TOOL_NLLC_UNITDATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 5) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÓÃÎÞÓ¦´ð´«Êä*/
+#define NLLC_TOOL_UNITDATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 6) /*NLLC²ãÏòÉϲ㴫ËÍÒÔ·ÇÈ·ÈÏģʽ½ÓÊÕµ½µÄL3_PDU*/
+#define TOOL_NLLC_DATA_REQ_EV (DWORD)(NLLC_EVENT_BASE + 7) /*Éϲã֪ͨNLLC²ã¶ÔÉϲãPDUµÄÈ·ÈÏ´«Êä*/
+#define NLLC_TOOL_FRMR_RSP_EV (DWORD)(NLLC_EVENT_BASE + 8) /*ÊÕµ½¾Ü¾øÖ¡*/
+#define NLLC_TOOL_DATA_IND_EV (DWORD)(NLLC_EVENT_BASE + 9) /*NLLCÏòÉϲ㴫ËͽÓÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_DATA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 10) /*¹¤¾ß²àÏìÓ¦ÊÕµ½µÄÊý¾Ý*/
+#define TOOL_NLLC_ESTABLISH_REQ_EV (DWORD)(NLLC_EVENT_BASE + 11) /*ÓÃÓÚΪNLLC²ãÖÐÒ»¸öSAPI½¨Á¢»òÖؽ¨ABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_ESTABLISH_RSP_EV (DWORD)(NLLC_EVENT_BASE + 12) /*ÉϲãÔÚ½ÓÊÕµ½LL_ESTABLISHָʾÔÓïÖ®ºóʹÓÃ.Ö÷ÒªÊÇÐÉÌXID²ÎÊý*/
+#define NLLC_TOOL_UA_RSP_EV (DWORD)(NLLC_EVENT_BASE + 13) /*ÊÕµ½UA·µ»Ø*/
+#define NLLC_TOOL_ESTABLISH_IND_EV (DWORD)(NLLC_EVENT_BASE + 14) /*ÓÃÓÚ֪ͨÉϲã²ã¶ÔNLLC²ãÖеÄÒ»¸öSAPIÒѾ½¨Á¢»òÒѾÖؽ¨ÆðÁËABM¹¤×÷ģʽ*/
+#define TOOL_NLLC_RELEASE_REQ_EV (DWORD)(NLLC_EVENT_BASE + 15) /*ÓÃÓÚÊÍ·ÅΪNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽ*/
+#define NLLC_TOOL_DM_RSP_EV (DWORD)(NLLC_EVENT_BASE + 16) /*ÊÕµ½DM·µ»Ø*/
+#define NLLC_TOOL_RELEASE_IND_EV (DWORD)(NLLC_EVENT_BASE + 17) /*ÓÃÓÚָʾNLLC²ãÖеÄij¸öSAPIµÄABM¹¤×÷ģʽÒѱ»ÊÍ·Å*/
+#define TOOL_NLLC_RELEASE_RSP_EV (DWORD)(NLLC_EVENT_BASE + 18) /*ÓÃÓÚ¹¤¾ß֪ͨNLLC·µ»Ø³É¹¦ÊÍ·ÅÏìÓ¦*/
+#define TOOL_NLLC_XID_REQ_EV (DWORD)(NLLC_EVENT_BASE + 19) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÇëÇó*/
+#define TOOL_NLLC_XID_RSP_EV (DWORD)(NLLC_EVENT_BASE + 20) /*¹¤¾ß֪ͨNLLC·¢Æð²ÎÊýÐÉÌÏìÓ¦*/
+#define NLLC_TOOL_XID_CNF_EV (DWORD)(NLLC_EVENT_BASE + 21) /*ÓÃÓÚÈ·ÈÏÉϲãXID²ÎÊýÐÉÌÍê³É*/
+#define NLLC_TOOL_XID_IND_EV (DWORD)(NLLC_EVENT_BASE + 22) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐXID²ÎÊýÐèÒªÐÉÌ*/
+#define NLLC_TOOL_NULL_IND_EV (DWORD)(NLLC_EVENT_BASE + 23) /*ÓÃÓÚָʾÉϲãÊÖ»ú²àÓÐNULLÖ¡*/
+
+
+/* ========================================================================
+ NRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define NRLC_DATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 0)
+#define NRLC_UNITDATA_REQ_EV (DWORD)(NRLC_EVENT_BASE + 1)
+#define NRLC_ASSIGN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 2)
+#define TOOL_NGRLC_ULTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 3)
+#define TOOL_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 4)
+#define TOOL_NGRLC_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 5)
+#define NGRLC_TOOL_DLTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 6)
+#define NGRLC_TOOL_DLTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 7)
+#define NGRLC_TOOL_ULTBF_HALF_IND_EV (DWORD)(NRLC_EVENT_BASE + 8)
+#define NGRLC_TOOL_ULTBF_FINAL_IND_EV (DWORD)(NRLC_EVENT_BASE + 9)
+#define TOOL_NGRLC_ULTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 10)
+#define NGRLC_TOOL_ULTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 11)
+#define TOOL_NGRLC_DLTBF_REL_CFG_EV (DWORD)(NRLC_EVENT_BASE + 12)
+#define TOOL_NGRLC_DLTBF_EST_CFG_EV (DWORD)(NRLC_EVENT_BASE + 13)
+#define TOOL_NGRLC_EXTBF_ON_EV (DWORD)(NRLC_EVENT_BASE + 14)
+#define TOOL_NGRLC_EXTBF_OFF_EV (DWORD)(NRLC_EVENT_BASE + 15)
+#define NGRLC_TOOL_DLTBF_TRIGGER_IND_EV (DWORD)(NRLC_EVENT_BASE + 16)
+#define NGRLC_START_TIMER_EV (DWORD)(NRLC_EVENT_BASE + 17) /*ÄÚ²¿ÏûÏ¢£¬ÆäËûÄ£¿é²»»áʹÓÃ*/
+#define NGRLC_TOOL_DLTBF_FAI_IND_EV (DWORD)(NRLC_EVENT_BASE + 18)
+#define TOOL_NGRLC_BEGINTEST_MODE_EV (DWORD)(NRLC_EVENT_BASE + 19)
+#define NGRLC_TOOL_PDANNOTIFY_EV (DWORD)(NRLC_EVENT_BASE + 20)
+#define NGRLC_NGRLC_PUAN_REQ_EV (DWORD)(NRLC_EVENT_BASE + 21)
+#define NGRLC_FILL_DATA_QUEUE_REQ_EV (DWORD)(NRLC_EVENT_BASE + 22)
+#define L1SIMU_NGRLC_DATA_IND_EV (DWORD)(NRLC_EVENT_BASE + 23)
+#define TOOL_NGRLC_MODE_CFG_REQ_EV (DWORD)(NRLC_EVENT_BASE + 24)
+#define NGRLC_TOOL_UL_DATA_BLOCK_IND_EV (DWORD)(NRLC_EVENT_BASE + 25)
+#define TOOL_NGRLC_DUMMYBLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 26)
+#define DOWNLINK_DUMMY_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 27)
+#define TOOL_NGRLC_DOWNLINK_BLOCK_REQ_EV (DWORD)(NRLC_EVENT_BASE + 28)
+#define TOOL_NGRLC_PSHO_ULTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 29)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøULTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_DLTBF_CFG_EV (DWORD)(NRLC_EVENT_BASE + 30)/*TOOLÅäÖÃNGRLCµÄPSHO Ä¿±êСÇøDLTBF²ÎÊý*/
+#define TOOL_NGRLC_PSHO_RETURN_EV (DWORD)(NRLC_EVENT_BASE + 31)/*TOOL ֪ͨNGRLC ×ÊÔ´»ØÍË*/
+#define TOOL_NGRLC_PSHO_REL_EV (DWORD)(NRLC_EVENT_BASE + 32)/*TOOL ֪ͨNGMAC Çå³ýPSHO Çл»×ÊÔ´*/
+#define NGRLC_TOOL_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 33)/*NGRLC ֪ͨTOOL PSHO ³É¹¦*/
+#define NGRLC_NGMAC_PSHOSUCC_IND_EV (DWORD)(NRLC_EVENT_BASE + 34)/*NGRLC ֪ͨNGMAC PSHO ³É¹¦*/
+/* ========================================================================
+ URRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define URRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 0)
+#define URRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 1)
+#define URRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 2)
+#define URRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 3)
+#define URRC_FUNC_ENTER_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 4)
+#define URRC_FUNC_READ_SIB_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 5)
+#define URRC_FUNC_READ_SIB_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 6)
+#define URRC_FUNC_SER_CELL_IND_EV (DWORD)(URRC_FUNC_EVENT_BASE + 7)
+#define URRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 8)
+#define URRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 9)
+#define URRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 10)
+#define URRC_FUNC_START_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 11)
+#define URRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 12)
+#define URRC_FUNC_PAGING_TYPE1_EV (DWORD)(URRC_FUNC_EVENT_BASE + 13)
+#define URRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 14)
+#define URRC_FUNC_GET_UE_CAP_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 15)
+#define URRC_FUNC_CFG_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 16)
+#define URRC_FUNC_CFG_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 17)
+#define URRC_FUNC_REL_FACH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 18)
+#define URRC_FUNC_REL_FACH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 19)
+#define URRC_FUNC_REL_PCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 20)
+#define URRC_FUNC_REL_PCH_CNF_EV (DWORD)(URRC_FUNC_EVENT_BASE + 21)
+#define URRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 22)
+#define URRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(URRC_FUNC_EVENT_BASE + 23)
+#define URRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 24)
+#define URRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 25)
+#define URRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 26)
+#define URRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(URRC_FUNC_EVENT_BASE + 27)
+#define URRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(URRC_FUNC_EVENT_BASE + 28)
+#define URRC_FUNC_STOP_SYSINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 29)
+#define URRC_FUNC_READ_CGIINFO_EV (DWORD)(URRC_FUNC_EVENT_BASE + 30)
+#define URRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 31)
+#define URRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(URRC_FUNC_EVENT_BASE + 32)
+
+/* ========================================================================
+ TAFº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TAF_FUNC_L1G_DATA_REQ_EV (DWORD)(TAF_FUNC_EVENT_BASE + 0)
+
+/* ========================================================================
+ L1GÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1G_ST_MEAS_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 0)
+#define L1G_ST_MEAS_IND_EV (DWORD)(L1G_ST_EVENT_BASE + 1)
+#define L1G_ST_FCB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 2)
+#define L1G_ST_FCB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 3)
+#define L1G_ST_SYNC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 4)
+#define L1G_ST_BSIC_SB_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 5)
+#define L1G_ST_SB_RESULT_EV (DWORD)(L1G_ST_EVENT_BASE + 6)
+#define L1G_ST_RX_REQ_EV (DWORD)(L1G_ST_EVENT_BASE + 7)
+#define L1G_ST_RX_EQU_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 8)
+#define L1G_ST_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 9)
+#define L1G_ST_RACH_EV (DWORD)(L1G_ST_EVENT_BASE + 10)
+#define L1G_ST_SDCCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 11)
+#define L1G_ST_SACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 12)
+#define L1G_ST_SACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 13)
+#define L1G_ST_FACCH_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 14)
+#define L1G_ST_FACCH_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 15)
+#define L1G_ST_DS_TX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 16)
+#define L1G_ST_DS_RX_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 17)
+#define L1G_ST_TCH_CTRL_DATA_EV (DWORD)(L1G_ST_EVENT_BASE + 18)
+
+/* ========================================================================
+ GRRº¯Êý¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GRR_FUNC_SUSPEND_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 0)
+#define GRR_FUNC_RESUME_UTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 1)
+#define GRR_FUNC_SUSPEND_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 2)
+#define GRR_FUNC_RESUME_EUTRAN_MEAS_EV (DWORD)(GRR_FUNC_EVENT_BASE + 3)
+#define GRR_FUNC_IDLE_MODE_SETTING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 4)
+#define GRR_FUNC_LIST_HANDLING_EV (DWORD)(GRR_FUNC_EVENT_BASE + 5)
+#define GRR_FUNC_SCELL_UPDATE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 6)
+#define GRR_FUNC_INIT_SCELL_PARAM_EV (DWORD)(GRR_FUNC_EVENT_BASE + 7)
+#define GRR_FUNC_INIT_GRR_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 8)
+#define GRR_FUNC_INIT_GRR_SCELL_TMP_EV (DWORD)(GRR_FUNC_EVENT_BASE + 9)
+#define GRR_FUNC_INIT_MI_EV (DWORD)(GRR_FUNC_EVENT_BASE + 10)
+#define GRR_FUNC_SI2QUATER_COMPLETE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 11)
+#define GRR_FUNC_CELL_SEL_BCCH_ALL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 12)
+#define GRR_FUNC_CELL_SEL_BCCH_MIN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 13)
+#define GRR_FUNC_RESET_SYSINFO_EV (DWORD)(GRR_FUNC_EVENT_BASE + 14)
+#define GRR_FUNC_STORE_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 15)
+#define GRR_FUNC_STORE_MODIFY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 16)
+#define GRR_FUNC_COPY_ORIG_UTRAN_EV (DWORD)(GRR_FUNC_EVENT_BASE + 17)
+#define GRR_FUNC_INDIVID_PRIORITY_CHANGE_EV (DWORD)(GRR_FUNC_EVENT_BASE + 18)
+#define GRR_FUNC_GET_QSEARCH_EV (DWORD)(GRR_FUNC_EVENT_BASE + 19)
+#define GRR_FUNC_COPY_SCELL_EV (DWORD)(GRR_FUNC_EVENT_BASE + 20)
+
+
+/* ========================================================================
+ αÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ¶¨Òå
+======================================================================== */
+#define GAS_ST_CTRL_BLOCK_TLV_EV (DWORD)(SIGTRACE_EVENT_BASE + 0) /*GRRÏûÏ¢¶ÔµÈ²ãÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_UL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 1) /*GMAC¶ÔµÈ²ãÉÏÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DL_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 2) /*GMAC¶ÔµÈ²ãÏÂÐÐÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_SEG_CTRL_BLOCK_CSN1_EV (DWORD)(SIGTRACE_EVENT_BASE + 3) /*GMAC¶ÔµÈ²ãÏÂÐзֶÎÏûÏ¢ÐÅÁî¸ú×ÙʼþºÅ*/
+#define GAS_ST_DLL_READ_DCCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 4)
+#define GAS_ST_DLL_READ_SACCH_EV (DWORD)(SIGTRACE_EVENT_BASE + 5)
+#define ATI_PDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 6)
+#define UPDI_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 7)
+#define SN_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 8)
+#define SN_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 9)
+#define LL_DATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 10)
+#define LL_UNITDATA_REQ_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 11)
+#define LLC_GET_NEXT_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 12)
+#define GMAC_GET_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 13)
+#define GMAC_ACK_BLOCKS_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 14)
+#define PDCP_RLC_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 15)
+#define URLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 16)
+#define URLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 17)
+#define UMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 18)
+#define PH_MAC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 19)
+#define PH_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 20)
+#define MAC_RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 21)
+#define RLC_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 22)
+#define RLC_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 23)
+#define LL_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 24)
+#define LL_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 25)
+#define SN_DATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 26)
+#define SN_UNITDATA_IND_TRACE (DWORD)(SIGTRACE_EVENT_BASE + 27)
+#define UPDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 28)
+#define ATI_PDI_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 29)
+#define UUMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 30)
+#define PDCP_RLC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 31)
+#define TAF_COUNTER_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 32)
+#define TAF_RLP_XID_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 33)
+#define TAF_RLP_XID_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 34)
+#define TAF_RLP_SABM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 35)
+#define TAF_RLP_SABM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 36)
+#define TAF_RLP_UA_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 37)
+#define TAF_RLP_UA_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 38)
+#define TAF_RLP_DISC_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 39)
+#define TAF_RLP_DISC_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 40)
+#define TAF_RLP_DM_ULFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 41)
+#define TAF_RLP_DM_DLFRAME_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 42)
+#define TAFL1G_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 43)
+#define TAFL1G_DATA_REQ_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 44)
+#define TAF_FUNC_UURLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 45)
+#define TAF_FUNC_UURLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 46)
+#define PDI_PDCP_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 47)
+#define PDCP_DATA_BACK_PDI_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 48)
+/*WCDMA(SIGIRACE=100)*/
+#define WRLC_GET_BO_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 49)
+#define WRLC_SEND_PDU_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 50)
+#define WMAC_TFC_SEL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 51)
+#define UWMAC_DATA_IND_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 52)
+#define TAF_FUNC_UWRLC_DATA_IND_EV (DWORD)(SIGTRACE_EVENT_BASE + 53)
+#define TAF_FUNC_UWRLC_DATA_REQ_EV (DWORD)(SIGTRACE_EVENT_BASE + 54)
+#define WMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 55)
+#define WMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 56)
+#define EUMAC_START_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 57)
+#define EUMAC_STOP_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 58)
+#define EUMAC_HOLD_TEMPERATURE_CTRL_TRACE_EV (DWORD)(SIGTRACE_EVENT_BASE + 59)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ EMM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_T3410_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 0)
+#define EMM_T3416_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 1)
+#define EMM_T3417_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 2)
+#define EMM_T3418_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 3)
+#define EMM_T3420_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 4)
+#define EMM_T3421_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 5)
+#define EMM_T3430_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 6)
+#define EMM_T3440_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 7)
+#define EMM_T_POWEROFF_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 8)
+#define EMM_T3417EXT_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 9)
+#define EMM_T_WAITRELIND_EXPIRY (DWORD)(EMM_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ ESM TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_TIMER3480_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 0)
+#define ESM_TIMER3481_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 1)
+#define ESM_TIMER3482_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 2)
+#define ESM_TIMER3492_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 3)
+#define ESM_T_MTACTANSWER_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 4)
+#define ESM_T_WAITINGATH_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 5)
+#define ESM_T_PTIBUF_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 6)
+#define ESM_T_CMEST_EXPIRY_EV (DWORD)(ESM_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ EPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_T_DISCARD_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 0)
+#define EPDCP_T_DELAYMODEB_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 1)
+#define EPDCP_T_EXPIRY_EV (DWORD)(EPDCP_TIMER_EVENT_BASE + 2)
+
+/* ========================================================================
+ EURLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURLC_T_POLL_RETRANSMIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 0)
+#define EURLC_T_STATUS_PROHIBIT_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 1)
+#define EURLC_T_REORDERING_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 2)
+#define EUL2LOG_T_EXPIRY_EV (DWORD)(EURLC_TIMER_EVENT_BASE + 3)
+
+/* ========================================================================
+ EUMAC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMAC_T_EXPIRY_EV (DWORD)(EUMAC_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ EUCER×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_T300_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 0)
+#define EURRC_T301_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 1)
+#define EURRC_T302_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 2)
+#define EURRC_T303_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 3)
+#define EURRC_T304_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 4)
+#define EURRC_T305_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 5)
+#define EURRC_T310_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 6)
+#define EURRC_T311_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 7)
+#define EURRC_T60MS_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 8)
+#define EURRC_T3174_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 9)
+#define EURRC_VARRLF_VALID_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 10)
+#define EURRC_T306_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 11)
+#define EURRC_MCCH_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 12)
+#define EURRC_1SECOND_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 13)
+#define EURRC_TGPAGING_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 14)
+#define EURRC_PERIDOSTATUSREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 15)
+#define EURRC_SELFHOREPORT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 16)
+#define EURRC_SINGLEUSEREXIT_EXPIRY_EV (DWORD)(EUCER_TIMER_EVENT_BASE + 17)
+
+/* ========================================================================
+ EUMCR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUMCR_T320_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 0)
+#define EUMCR_T321_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 1)
+#define EUMCR_T_REMAIN_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 2)
+#define EUMCR_T_LEAVE_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 3)
+#define EUMCR_T_HYSTNORMAL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 4)
+#define EUMCR_T_PROXIMITY_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 5)
+#define EUMCR_T_CELLINFO_REPORT_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 6)
+#define EUMCR_T_RESEL_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 7)
+#define EUMCR_T_MDT_LOG_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 8)
+#define EUMCR_T330_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 9)
+#define EUMCR_T_48HOURS_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 10)
+#define EUMCR_T_LISTEN_HANDOVER_EXPIRY_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 11)
+#define EUMCR_T_MONITOR_PERIOD_CHG_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 12)
+#define EUMCR_T_MONITOR_HO_EXPIR_EV (DWORD)(EUMCR_TIMER_EVENT_BASE + 13)
+/* ========================================================================
+ EUCSR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUCSR_T_SI_MODI_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 0)
+#define EUCSR_T_ABORT_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 1)
+#define EUCSR_T_FREQ_SCAN_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 2)
+#define EUCSR_T_CELL_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 3)
+#define EUCSR_T_PLMN_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 4)
+#define EUCSR_T_CSG_SEARCH_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 5)
+#define EUCSR_T_3HOUR_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 6)
+#define EUCSR_T_OOS_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 7)
+#define EUCSR_T_SWITCH_RADIO_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 8)
+#define EUCSR_T_REDIRECT_TO_LTE_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 9)
+#define EUCSR_T_SYNC_BARREDLIST_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 10)
+#define EUCSR_T_WAIT_RESEL_TO_UTRA_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 11)
+#define EUCSR_T_REDIRECT_TO_LTE_OP_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 12)
+#define EUCSR_T_LISTEN_RESEL_SUCC_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 13)
+#define EUCSR_T_LBS_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 14)
+#define EUCSR_T_ECID_RPT_EXPIRY_EV (DWORD)(EUCSR_TIMER_EVENT_BASE + 15)
+
+
+/* ========================================================================
+ EUSIR×ÓÄ£¿é¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EUSIR_T_SIB1GUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 0)
+#define EUSIR_T_SIMSGGUARD_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 1)
+#define EUSIR_T_ETWS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 2)
+#define EUSIR_T_CMAS_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 3)
+#define EUSIR_T_SIBVALID_EXPIRY_EV (DWORD)(EUSIR_TIMER_EVENT_BASE + 4)
+/* ========================================================================
+ EMMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define UMM_TU_SUCC_IND_EV (DWORD)(EMM_UMM_EVENT_BASE + 0)
+
+#define UMM_CONFIG_REQ_EV (DWORD)(EMM_UMM_RSP_EVENT + 0)
+
+/* ========================================================================
+ UMMºÍEPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EPDCP_UMM_EST_REJ_EV (DWORD)(UMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_UMM_EST_REQ_EV (DWORD)(UMM_EPDCP_RSP_EVENT + 0)
+
+/* ========================================================================
+ CM²ãºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CM_EMM_DATA_REQ_EV (DWORD)(CM_EMM_EVENT_BASE + 0)
+/* ========================================================================
+ ESMºÍEMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESM->EMM*/
+#define ESM_EMM_DEFAULT_ACT_REJ_EV (DWORD)(ESM_EMM_EVENT_BASE + 0)
+#define ESM_EMM_EMERGENCY_PDN_EST_SUCC_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 1)
+#define ESM_EMM_EMERGENCY_PDN_ONLY_IND_EV (DWORD)(ESM_EMM_EVENT_BASE + 2)
+
+/* EMM->ESM*/
+#define ESM_EMM_DATA_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 0)
+#define ESM_EMM_ATTACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 1)
+#define ESM_EMM_ATTACH_REJ_EV (DWORD)(ESM_EMM_RSP_EVENT + 2)
+#define ESM_EMM_CONTEXT_STATUS_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 3)
+#define ESM_EMM_DETACH_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 4)
+#define ESM_EMM_DETACH_EMERGENCY_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 5)
+#define EMM_ESM_DETACH_NORMAL_IND_EV (DWORD)(ESM_EMM_RSP_EVENT + 6)
+
+/* ========================================================================
+ EMMºÍASC(ERRC(CER))Ä£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EMM_ASC_EST_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 1)
+#define EMM_ASC_EST_ABT_EV (DWORD)(EMM_ASC_EVENT_BASE + 2)
+#define EMM_ASC_REL_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 3)
+#define EMM_ASC_KENB_RSP_EV (DWORD)(EMM_ASC_EVENT_BASE + 4)
+#define EMM_ASC_REL_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 5)
+#define EMM_ASC_DATA_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 6)
+#define EMM_ASC_DETACH_REQ_EV (DWORD)(EMM_ASC_EVENT_BASE + 7)
+
+/* EURRC->ASC */
+#define EMM_ASC_DATA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 0)
+#define EMM_ASC_EST_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 1)
+#define EMM_ASC_EST_REJ_EV (DWORD)(EMM_ASC_RSP_EVENT + 2)
+#define EMM_ASC_REL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 3)
+#define EMM_ASC_ABA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 4)
+#define EMM_ASC_DRB_SETUP_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 5)
+#define EMM_ASC_TRANS_FAIL_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 6)
+#define EMM_ASC_KENB_REQ_EV (DWORD)(EMM_ASC_RSP_EVENT + 7)
+#define EMM_ASC_UE_INFO_CHANGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 8)
+#define EMM_ASC_DATA_CNF_EV (DWORD)(EMM_ASC_RSP_EVENT + 9)
+#define EMM_ASC_PAGE_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 10)
+#define EMM_ASC_SEC_PARA_IND_EV (DWORD)(EMM_ASC_RSP_EVENT + 11)
+/* ========================================================================
+ EMMºÍEUPDCPÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EPDCP_EMM_EST_REJ_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 0)
+#define EPDCP_EMM_BAR_ALLEVIATE_NOTIFY_EV (DWORD)(EMM_EPDCP_EVENT_BASE + 1)
+/* ========================================================================
+ ESMºÍUMMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*ESMºÍUMMÄ£¿éÖ®¼äµÄÏûϢʼþºÅ--
+* 1.CM_EST_REQ_EV£¬
+* 2.CM_EST_CNF_EV£¬
+* 3.CM_RELIND_EVÑØÓÃÒÔÇ°90AµÄ½Ó¿Ú*/
+/*ESM->UMM*/
+#define ESM_UMM_DETACH_REQ_EV (DWORD)(ESM_UMM_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_UMM_LOCAL_DEACT_IND_EV (DWORD)(ESM_UMM_EVENT_BASE + 1)
+
+/* ========================================================================
+ SMºÍESMÄ£¿é¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/*SM->ESM*/
+#define SM_ESM_DATA_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 0) /*Added:KangShuJie*/
+#define SM_ESM_RAT_ACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define SM_ESM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define SM_ESM_DEACT_IND_EV (DWORD)(SM_ESM_EVENT_BASE + 3) /*Added:KangShuJie*/
+/*ESM->SM*/
+#define ESM_SM_DATA_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 0) /*Added:KangShuJie*/
+#define ESM_SM_RAT_ACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 1) /*Added:KangShuJie*/
+#define ESM_SM_RAT_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 2) /*Added:KangShuJie*/
+#define ESM_SM_DEACT_IND_EV (DWORD)(SM_ESM_RSP_EVENT + 3) /*Added:KangShuJie*/
+
+
+/* ========================================================================
+ ESMºÍEPDCP*Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ESM_EPDCP_DEACTIVATE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_MOVE_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 1) /*Added:KangShuJie*/
+#define ESM_EPDCP_RAT_DATA_DEL_REQ_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 2) /*Added:KangShuJie*/
+#define ESM_EPDCP_DIAL_IND_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 3)
+#define DEL_USER_PLANE_BUFFER_DATA_EV (DWORD)(ESM_EPDCP_EVENT_BASE + 4)
+
+#define ESM_EPDCP_LOCAL_DEACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 0)
+#define ESM_EPDCP_RAT_SEQ_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 1)
+#define ESM_EPDCP_RAT_ACT_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 2)
+#define ESM_EPDCP_RAT_CHANGE_COMP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 3) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_SEQ_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 4) /*Added:KangShuJie*/
+#define EPDCP_ESM_RAT_ACT_RSP_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 5) /*Added:KangShuJie*/
+#define EPDCP_ESM_STATUS_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 6) /*Added:KangShuJie*/
+#define ESM_EPDCP_CURR_BEAR_IND_EV (DWORD)(ESM_EPDCP_RSP_EVENT + 7)
+
+/* ========================================================================
+ EURRCºÍEPDCPÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 0)
+#define EURRC_EPDCP_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 1)
+#define EURRC_EPDCP_DATA_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 2)
+#define EURRC_EPDCP_REESTABLISH_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 3)
+#define EURRC_EPDCP_RELEASE_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 4)
+#define EURRC_EPDCP_RESUME_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 5)
+#define EURRC_EPDCP_SUSPEND_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 6)
+#define EURRC_EPDCP_DECIPHER_AND_INT_CHECK_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 7)
+#define EURRC_EPDCP_HO_SUCC_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 8)
+#define EURRC_EPDCP_HO_FAIL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 9)
+#define EURRC_EPDCP_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 10)/*Added:KangShuJie*/
+#define EURRC_EPDCP_SMC_END_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 11)
+#define EURRC_EPDCP_TRUNKING_SEC_CONFIG_REQ_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 12)
+#define EURRC_EPDCP_CELL_RESEL_IND_EV (DWORD)(EURRC_EPDCP_EVENT_BASE + 13)
+
+
+#define EURRC_EPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 0)
+#define EURRC_EPDCP_DATA_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 1)
+#define EURRC_EPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 2)
+#define EURRC_EPDCP_CONFIG_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 3)
+#define EURRC_EPDCP_DATA_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 4)
+#define EURRC_EPDCP_REESTABLISH_CNF_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 5)
+#define EURRC_EPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(EURRC_EPDCP_RSP_EVENT + 6)
+/* ========================================================================
+ EURRCºÍEURLCÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EURLC_CONFIG_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EURLC_RELEASE_REQ_EV (DWORD)(EURRC_EURLC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+
+#define EURRC_EURLC_CONFIG_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EURRC_EURLC_REESTABLISH_CNF_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EL2_EURRC_RADIOLINK_FAIL_IND_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EURRC_EL2_TRUNKCH_ERROR_EV (DWORD)(EURRC_EURLC_RSP_EVENT + 3)
+/* ========================================================================
+ EURRCºÍEUMACÄ£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define EURRC_EUMAC_CCCH_DATA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 0) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_COMM_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 1) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_DEDI_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 2) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_REL_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 3) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESET_MAC_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 4) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RESUME_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 5) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_SUSPEND_RB_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 6) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_RA_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 7) /*Modified:KangShuJie*/
+#define EURRC_EUMAC_HO_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 8)
+#define EURRC_EUMAC_REL_DEDI_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 11)
+#define EURRC_EUMAC_GRNTI_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 12)
+#define EURRC_EUMAC_SR_CONFIG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 13)
+#define EURRC_EUMAC_LISTENINGCFG_REQ_EV (DWORD)(EURRC_EUMAC_EVENT_BASE + 14)
+
+#define EUMAC_EURRC_CCCH_DATA_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 0) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_PROBLEM_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 1) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_RA_SUCC_IND_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 2) /*Modified:KangShuJie*/
+#define EUMAC_EURRC_HO_CNF_EV (DWORD)(EURRC_EUMAC_RSP_EVENT + 3)
+#define EUMAC_EURRC_PUCCH_SRS_REL_REQ (DWORD)(EURRC_EUMAC_RSP_EVENT + 4)
+
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define EURLC_EPDCP_UM_DATA_CNF_EV (DWORD)(EUPDCP_EURLC_EVENT_BASE + 0)
+
+/* ========================================================================
+ EURRCºÍMEL2Ä£¿éÖ®¼äÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define EURRC_EUMAC_MCH_CONFIG_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 0)
+#define EURRC_EUMAC_MCH_REL_REQ_EV (DWORD)(EURRC_MEL2_EVENT_BASE + 1)
+#define MEL2_DMA_COMPLETE_IND (DWORD)(EURRC_MEL2_EVENT_BASE + 2)
+#define EUMAC_EURRC_MCCH_DATA_IND_EV (DWORD)(EURRC_MEL2_RSP_EVENT + 0)
+
+/* ========================================================================
+ EURRCÄÚ²¿ÏûϢʼþºÅ¶¨Òå
+======================================================================== */
+/*EUCER-EUMCR*/
+#define EURRC_MCR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 0)
+#define EURRC_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 1)
+#define EURRC_IDLE_INFO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 2)
+
+#define EURRC_SCELL_UNSUITABLE_IND_EV (DWORD)(EURRC_EVENT_BASE + 3)
+#define EURRC_CER_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 4)
+
+/*EUCER-EUCSR*/
+#define EURRC_CSR_STATE_REQ_EV (DWORD)(EURRC_EVENT_BASE + 5)
+#define EURRC_CELL_INFO2NAS_EV (DWORD)(EURRC_EVENT_BASE + 6)
+#define EURRC_BARRED_CELL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 7)
+#define EURRC_REL_EPHY_CNF_EV (DWORD)(EURRC_EVENT_BASE + 8)
+
+#define EURRC_CER_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 9)
+#define EURRC_CELL_SEL_SUCC_IND_EV (DWORD)(EURRC_EVENT_BASE + 10)
+#define EUCER_TRS_TEST_IND_EV (DWORD)(EURRC_EVENT_BASE + 11)
+#define EURRC_REL_EPHY_REQ_EV (DWORD)(EURRC_EVENT_BASE + 12)
+/*EUCER-EUSIR*/
+
+#define EURRC_CER_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 13)
+
+/*EUCSR-EUMCR*/
+#define EURRC_CELL_RESEL_REJ_EV (DWORD)(EURRC_EVENT_BASE + 14)
+#define EURRC_PLMN_SEL_IND_EV (DWORD)(EURRC_EVENT_BASE + 15)
+#define EURRC_MCR_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 16)
+
+#define EURRC_CELL_RESEL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 17)
+#define EURRC_CSR_OUTOF_SERVICE_IND_EV (DWORD)(EURRC_EVENT_BASE + 18)
+/*EUCSR-EUSIR*/
+
+#define EURRC_READ_SI_REQ_EV (DWORD)(EURRC_EVENT_BASE + 19)
+#define EURRC_ABORT_SI_READ_REQ_EV (DWORD)(EURRC_EVENT_BASE + 20)
+
+#define EURRC_CSR_CELL_STATE_IND_EV (DWORD)(EURRC_EVENT_BASE + 21)
+#define EURRC_CSG_IND_EV (DWORD)(EURRC_EVENT_BASE + 22)
+#define EURRC_WARNING_NOTIFY_INFO_EV (DWORD)(EURRC_EVENT_BASE + 23)
+
+/*EUCSR-EUCER*/
+#define EURRC_CER_RAT_IND_EV (DWORD)(EURRC_EVENT_BASE + 24)
+
+
+/*UMCR-EUSIR*/
+ /*UMCR-EUSIR ͬEURRC_READSI_REQ_EV
+ EURRC_ABORTSIREAD_REQ_EV */
+
+#define EURRC_MCR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 25)
+#define EURRC_CGI_CNF_EV (DWORD)(EURRC_EVENT_BASE + 26)
+#define EURRC_GET_RF_REQ_EV (DWORD)(EURRC_EVENT_BASE + 27)
+#define EURRC_GET_RF_CNF_EV (DWORD)(EURRC_EVENT_BASE + 28)
+#define EURRC_CSG_PROXIMITY_IND_EV (DWORD)(EURRC_EVENT_BASE + 29)
+#define EURRC_SI_END_FOR_HO_EV (DWORD)(EURRC_EVENT_BASE + 30)
+#define EURRC_MDT_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 31)
+#define EURRC_MCR_CGI_PEND_REQ_EV (DWORD)(EURRC_EVENT_BASE + 32)
+#define EURRC_MCR_CGI_PEND_CNF_EV (DWORD)(EURRC_EVENT_BASE + 33)
+#define EURRC_INTEREST_FREQ_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 34)
+#define EURRC_CER_SELFHO_REQ_EV (DWORD)(EURRC_EVENT_BASE + 35)
+#define EURRC_NETWORK_TIME_INFO_IND_EV (DWORD)(EURRC_EVENT_BASE + 36)
+#define EURRC_RRC_STATE_CHNG_IND_EV (DWORD)(EURRC_EVENT_BASE + 37)
+#define EURRC_EUCER_RESUME_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 38)
+#define EURRC_EUCER_ABORT_MBMS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 39)
+#define EURRC_CSR_XCELL_IND_EV (DWORD)(EURRC_EVENT_BASE + 40)
+#define EURRC_EUMCR_START_MEAS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 41)
+#define EURRC_CSR_RESEL_START_EV (DWORD)(EURRC_EVENT_BASE + 42)
+#define EURRC_CSR_RESEL_END_EV (DWORD)(EURRC_EVENT_BASE + 43)
+#define EURRC_CSR_SI_CHGED_IND_EV (DWORD)(EURRC_EVENT_BASE + 44)
+//LBS
+#define EURRC_CELL_MEAS_IND_EV (DWORD)(EURRC_EVENT_BASE + 45)
+#define EURRC_EUMCR_START_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 46)
+#define EURRC_EUMCR_STOP_LBS_REQ_EV (DWORD)(EURRC_EVENT_BASE + 47)
+#define EURRC_EUCER_UE_INFO_RLF_9E0_EV (DWORD)(EURRC_EVENT_BASE + 48)
+#define EURRC_EUCER_UE_CAPA_LTE_9D0_EV (DWORD)(EURRC_EVENT_BASE + 49)
+#define EURRC_MEAS_GAP_CONFIG_REQ_EV (DWORD)(EURRC_EVENT_BASE + 50)
+#define EURRC_CER_REL_REQ_EV (DWORD)(EURRC_EVENT_BASE + 51)
+
+
+/*EURRC<->L1E*/
+#define EURRC_L1E_MEAS_SUSPEND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 0)
+#define EURRC_L1E_MEAS_RESUME_EV (DWORD)(EURRC_L1E_EVENT_BASE + 1)
+#define EURRC_L1E_GSM_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 2)
+#define EURRC_L1E_UTRA_MEAS_STOP_EV (DWORD)(EURRC_L1E_EVENT_BASE + 3)
+#define EURRC_L1E_GSM_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 4)
+#define EURRC_L1E_TD_MEAS_CONFIG_EV (DWORD)(EURRC_L1E_EVENT_BASE + 5)
+#define EURRC_L1E_RESOURCE_REL_EV (DWORD)(EURRC_L1E_EVENT_BASE + 6)
+#define EURRC_L1E_RESOURCE_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 7)
+#define EURRC_L1E_SI_END_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 8)
+#define EURRC_L1E_GET_RF_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 9)
+#define EURRC_L1E_STATE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 10)
+#define EURRC_L1E_TRACE_IND_EV (DWORD)(EURRC_L1E_EVENT_BASE + 11)
+#define EURRC_L1E_W_MEAS_CONFIG_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 12)
+#define EURRC_L1E_IRAT_CGI_REQ_EV (DWORD)(EURRC_L1E_EVENT_BASE + 13)
+#define EURRC_L1E_IRAT_CGI_END_EV (DWORD)(EURRC_L1E_EVENT_BASE + 14)
+
+#define L1E_EURRC_RESOURCE_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 0)
+#define L1E_EURRC_GSM_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 1)
+#define L1E_EURRC_TD_LIST_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 2)
+#define L1E_EURRC_TD_BLIND_MEAS_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 3)
+#define EURRC_L1E_GET_RF_CNF_EV (DWORD)(EURRC_L1E_RSP_EVENT + 4)
+#define L1E_EURRC_W_MEAS_RLT_IND_EV (DWORD)(EURRC_L1E_RSP_EVENT + 5)
+/* ========================================================================
+ LTEÐÒéÕ»ºÍÎïÀí²ãÏûϢʼþÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+/* PS -> EPHY MSG ID */
+#define LTE_P_FREQ_SCAN_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 0)
+#define LTE_P_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 1)
+#define LTE_P_READ_SIB1_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 2)
+#define LTE_P_SCHED_SI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 3)
+#define LTE_P_ABORT_SI_READ_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 4)
+#define LTE_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 5)
+#define LTE_P_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 6)
+#define LTE_P_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 7)
+#define LTE_P_MEAS_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 8)
+#define LTE_P_ABORT_MEAS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 9)
+#define LTE_P_EARFCN_BAND_INFO_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 10)
+#define LTE_P_COMMON_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 11)
+#define LTE_P_DEDICATED_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 12)
+#define LTE_P_HANDOVER_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 13)
+#define LTE_P_MAC_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 14)
+#define LTE_P_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 15)
+#define LTE_P_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 16)
+#define LTE_P_ABORT_ACCESS_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 17)
+#define LTE_P_TA_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 18)
+#define LTE_P_DRX_CMD_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 19)
+#define LTE_P_TA_TIMER_STOP_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 20)
+#define LTE_P_FREQ_LIST_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 21)
+#define LTE_P_IRAT_MEAS_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 22)
+#define LTE_P_ABORT_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 23)
+#define LTE_P_IRAT_MEAS_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 24)
+#define LTE_P_IDLE_PERIOD_REP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 25)
+#define LTE_P_SET_MODE_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 26)
+#define LTE_P_RESET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 27)
+#define LTE_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 28)
+#define LTE_P_WAKEUP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 29)
+#define ZPS_LTE_ZEPCG_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 30)
+#define LTE_P_GRNTI_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 31)
+#define LTE_P_BTRUNK_TTCH_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 32)
+#define LTE_P_DEDICATECD_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 33)
+#define LTE_P_BTRUNK_CONFIG_REL_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 34)
+#define LTE_P_ACT_DEACT_SCELL_CTRL_ELEMNT_IND_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 35)
+#define LTE_P_MCCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 36)
+#define LTE_P_MTCH_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 37)
+#define LTE_P_MTCH_MASK_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 38)
+#define LTE_P_PMCH_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 39)
+#define LTE_P_MSI_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 40)
+#define LTE_P_CARD2_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 41) /*T_zLTE_P_card2_gap_req*/
+#define LTE_P_CARD2_GAP_REL_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 42) /*T_zLTE_P_card2_gap_rel_req*/
+#define LTE_P_CARD2_STOP_GAP_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 43) /*T_zLTE_P_card2_stop_gap_req*/
+#define LTE_P_CARD1_SUSPEND_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 44) /*T_zLTE_P_card1_suspend_req*/
+#define LTE_P_CARD1_RESUME_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 45) /*T_zLTE_P_card1_resume_req*/
+#define LTE_P_MEAS_PERIOD_CHG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 46)
+#define LTE_P_AMT_MSG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 47)
+#define LTE_P_RPI_SET_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 48)
+#define LTE_P_RPI_CFG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 49)
+#define LTE_P_OTDOA_CONFIG_REQ_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 50)
+#define LTE_P_OTDOA_MEAS_ABORT_EV (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 51)
+#define ZPS_LTE_CARD_SWITCH_REQ (DWORD)(LTE_PS_EUPHY_EVENT_BASE + 52)
+
+
+
+/* EPHY -> PS MSG ID */
+#define LTE_P_SI_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 0)
+#define LTE_P_PBCH_READ_FAIL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 1)
+#define LTE_P_FREQ_SCAN_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 2)
+#define LTE_P_CELL_SEARCH_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 3)
+#define LTE_P_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 4)
+#define LTE_P_INTRA_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 5)
+#define LTE_P_INTER_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 6)
+#define LTE_P_DRX_STATE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 7)
+#define LTE_P_HANDOVER_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 8)
+#define LTE_P_OUT_OF_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 9)
+#define LTE_P_RECOVERY_SYNC_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 10)
+#define LTE_P_PUCCH_SRS_REL_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 11)
+#define LTE_P_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 12)
+#define LTE_P_ACCESS_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 13)
+#define LTE_P_EUMAC_INIT_RA_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 14)
+#define LTE_P_RA_RESPONSE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 15)
+#define LTE_P_DLSCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 16)
+#define LTE_P_IRAT_MEAS_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 17)
+#define LTE_P_ABORT_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 18)
+#define LTE_P_RESET_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 19)
+#define LTE_P_INACTIVE_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 20)
+#define LTE_P_SLEEP_TIME_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 21)
+#define ZPS_LTE_ZEPCG_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 22)
+#define LTE_P_EMBMS_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 23)
+#define LTE_P_ULGRANT_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 24)
+#define LTE_P_OTDOA_MEAS_RLT_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 25)
+#define LTE_P_C0_SAVE_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 26)
+#define LTE_P_BTRUNK_CQI_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 27)
+#define LTE_P_LISTENINGHO_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 28)
+#define LTE_P_BTRUNK_PCH_DATA_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 29)
+#define EPDCP_EDCP_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 30)
+#define EURLC_EMAC_COMPLETE_IND (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 31)
+#define LTE_P_CARD2_GAP_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 32) /*T_zLTE_P_card2_gap_ind*/
+#define LTE_P_CARD2_GAP_REL_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 33)
+#define LTE_P_CARD2_STOP_GAP_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 34)
+#define LTE_P_CARD1_SUSPEND_CNF_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 35)
+#define LTE_P_PHYWAKEUPPS_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 36)
+#define LTE_P_ICP_REQ_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 37)
+#define LTE_P_AMT_MSG_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 38)
+#define ZPS_LTE_CARD_SWITCH_CNF (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 39)
+
+
+#if 0
+#define LTE_P_RF_ERR_IND_EV (DWORD)(LTE_PS_EUPHY_RSP_EVENT + 40)
+#endif
+
+
+/* ========================================================================
+ LTEÐÒéÕ»ºÍTRSÖ®¼äµÄÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TRS_ESM_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 0)
+#define TRS_ESM_L3TC_DATA_REQ_EV (DWORD)(TRS_ESM_EVENT_BASE + 1)
+#define TRS_ESM_ACT_DED_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 0)
+#define TRS_ESM_ACT_DED_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 1)
+#define TRS_ESM_ACT_DEF_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 2)
+#define TRS_ESM_ACT_DEF_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 3)
+#define TRS_ESM_BR_ALLOC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 4)
+#define TRS_ESM_BR_MOD_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 5)
+#define TRS_ESM_DEACT_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 6)
+#define TRS_ESM_ESMINFO_RSP_EV (DWORD)(TRS_ESM_RSP_EVENT + 7)
+#define TRS_ESM_ESMSTATUS_EV (DWORD)(TRS_ESM_RSP_EVENT + 8)
+#define TRS_ESM_MOD_EBCON_ACC_EV (DWORD)(TRS_ESM_RSP_EVENT + 9)
+#define TRS_ESM_MOD_EBCON_REJ_EV (DWORD)(TRS_ESM_RSP_EVENT + 10)
+#define TRS_ESM_PDN_CON_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 11)
+#define TRS_ESM_PDN_DISC_REQ_EV (DWORD)(TRS_ESM_RSP_EVENT + 12)
+#define TRS_ESM_L3TC_CLOSE_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 13)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 14)
+#define TRS_ESM_L3TC_ACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 15)
+#define TRS_ESM_L3TC_DEACT_TEST_MODE_CMP_EV (DWORD)(TRS_ESM_RSP_EVENT + 16)
+#define TRS_ESM_L3TC_OPEN_UETEST_LOOP_CMBMSPACKETCNT_RESP_EV (DWORD)(TRS_ESM_RSP_EVENT + 17)
+/* TRS -> MME_EMM */
+#define TRS_EMM_DATA_REQ_EV (DWORD)(TRS_EMM_EVENT_BASE + 0)
+#define TRS_EMM_MAPPED_SEC_PARAM_Ev (DWORD)(TRS_EMM_EVENT_BASE + 1)
+#define TRS_EMM_PS_HO_FROM_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 2)
+#define TRS_EMM_PS_HO_TO_EUTRA_Ev (DWORD)(TRS_EMM_EVENT_BASE + 3)
+/* MME_EMM ->TRS */
+#define ENB_TRS_ESM_CMD_EV (DWORD)(TRS_EMM_RSP_EVENT + 0)
+#define TRS_EMM_L3MSG_ATTACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 1)
+#define TRS_EMM_L3MSG_ATTACH_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 2)
+#define TRS_EMM_L3MSG_AUTH_FAIL_EV (DWORD)(TRS_EMM_RSP_EVENT + 3)
+#define TRS_EMM_L3MSG_AUTH_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 4)
+#define TRS_EMM_L3MSG_AUTH_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 5)
+#define TRS_EMM_L3MSG_DETACH_APT_EV (DWORD)(TRS_EMM_RSP_EVENT + 6)
+#define TRS_EMM_L3MSG_DETACH_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 7)
+#define TRS_EMM_L3MSG_ULNAS_TRANS_EV (DWORD)(TRS_EMM_RSP_EVENT + 8)
+#define TRS_EMM_L3MSG_SERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 9)
+#define TRS_EMM_L3MSG_EXSERVICE_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 10)
+#define TRS_EMM_L3MSG_GUTI_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 11)
+#define TRS_EMM_L3MSG_IDNT_RSP_EV (DWORD)(TRS_EMM_RSP_EVENT + 12)
+#define TRS_EMM_L3MSG_SMC_COM_EV (DWORD)(TRS_EMM_RSP_EVENT + 13)
+#define TRS_EMM_L3MSG_SMC_REJ_EV (DWORD)(TRS_EMM_RSP_EVENT + 14)
+#define TRS_EMM_L3MSG_TAU_REQ_EV (DWORD)(TRS_EMM_RSP_EVENT + 15)
+#define TRS_EMM_L3MSG_TAU_CMP_EV (DWORD)(TRS_EMM_RSP_EVENT + 16)
+#define TRS_EMM_L3MSG_EMMSTATUS_EV (DWORD)(TRS_EMM_RSP_EVENT + 17)
+#define TRS_EMM_DATA_IND_EV (DWORD)(TRS_EMM_RSP_EVENT + 18)
+
+#define ENB_EMM_ESM_DATA_REQ_EV (DWORD)(ENB_EMM_ESM_EVENT_BASE + 0)
+#define ENB_EMM_ESM_DATA_IND_EV (DWORD)(ENB_EMM_ESM_RSP_EVENT + 0)
+/* MME_EMM -> ENBRRC */
+#define ENB_RRC_EMM_DATA_REQ_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 0)
+#define ENB_RRC_EMM_DLSQN_EV (DWORD)(ENB_RRC_EMM_EVENT_BASE + 1)
+/* ENBRRC -> MME_EMM */
+#define ENB_RRC_EMM_DATA_IND_EV (DWORD)(ENB_RRC_EMM_RSP_EVENT + 0)
+
+
+/* ÆäËüLTE²âÊÔÄ£¿éÏûÏ¢IDºêÌí¼Ó´¦*/
+#define ENBRRC_RRC_CONN_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 0)
+#define ENBRRC_RRC_CONN_SETUP_EV (DWORD)(ENB_RRC_EVENT_BASE + 1)
+#define ENBRRC_RRC_CONN_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 2)
+#define ENBRRC_RRC_CONN_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 3)
+#define ENBRRC_SEC_MODE_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 4)
+#define ENBRRC_SEC_MODE_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 5)
+#define ENBRRC_SEC_MODE_FAIL_EV (DWORD)(ENB_RRC_EVENT_BASE + 6)
+#define ENBRRC_RRC_CONN_RECONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 7)
+#define ENBRRC_RRC_CONN_RECONFIG_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 8)
+#define ENBRRC_RRC_CONN_REEST_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 9)
+#define ENBRRC_RRC_CONN_REEST_EV (DWORD)(ENB_RRC_EVENT_BASE + 10)
+#define ENBRRC_RRC_CONN_REEST_REJ_EV (DWORD)(ENB_RRC_EVENT_BASE + 11)
+#define ENBRRC_RRC_CONN_REEST_CMP_EV (DWORD)(ENB_RRC_EVENT_BASE + 12)
+#define ENBRRC_RRC_CONN_REL_EV (DWORD)(ENB_RRC_EVENT_BASE + 13)
+#define ENBRRC_UE_CAP_ENQUIRY_EV (DWORD)(ENB_RRC_EVENT_BASE + 14)
+#define ENBRRC_UE_CAP_INFO_EV (DWORD)(ENB_RRC_EVENT_BASE + 15)
+#define ENBRRC_UE_MEAS_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 16)
+#define ENB_NASRRC_CMD_EV (DWORD)(ENB_RRC_EVENT_BASE + 17)
+#define ENB_NASRRC_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 18)
+#define TRS_EPHY_UE_MEAS_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 19)
+#define TRS_EPHY_UE_CER_HO_REQ_CTL_EV (DWORD)(ENB_RRC_EVENT_BASE + 20)
+#define ENBRRC_COUNTER_CHECK_SUCC_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 21)
+#define ENBRRC_COUNTER_CHECK_FAIL_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 22)
+#define ENBRRC_MOBILITY_FROM_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 23)
+#define ENBRRC_START_HO_FROM_EUTRA_IND_EV (DWORD)(ENB_RRC_EVENT_BASE + 24)
+#define ENBRRC_START_HO_TO_EUTRA_EV (DWORD)(ENB_RRC_EVENT_BASE + 25)
+#define ENBRRC_PROXIMITY_RPT_EV (DWORD)(ENB_RRC_EVENT_BASE + 26)
+#define ENBRRC_UE_INFO_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 27)
+#define ENBRRC_UE_INFO_RSP_EV (DWORD)(ENB_RRC_EVENT_BASE + 28)
+#define ENBRRC_MBSFN_AREA_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 29)
+#define ENBRRC_MBMS_COUNTING_REQ_EV (DWORD)(ENB_RRC_EVENT_BASE + 30)
+#define ENBRRC_TDLINFO_TRANS_EV (DWORD)(ENB_RRC_EVENT_BASE + 31)
+#define ENBRRC_GROUPCALL_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 32)
+#define ENBRRC_GROUPCALL_RELEASE_EV (DWORD)(ENB_RRC_EVENT_BASE + 33)
+#define ENRRC_NEIGHBOURINFO_CONFIG_EV (DWORD)(ENB_RRC_EVENT_BASE + 34)
+
+
+#define ENRRC_ENPDCP_SMC_INTEGRITY_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 0)
+#define ENRRC_ENPDCP_CONFIG_CIPHER_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 1)
+#define ENRRC_ENPDCP_CONFIG_INTEGRITY_KEY_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 2)
+#define ENRRC_ENPDCP_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 3)
+#define ENRRC_ENPDCP_DATA_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 4)
+#define ENRRC_ENPDCP_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 5)
+#define ENRRC_ENPDCP_RELEASE_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 6)
+#define ENRRC_ENPDCP_RESUME_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 7)
+#define ENRRC_ENPDCP_SUSPEND_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 8)
+#define ENRRC_ENPDCP_DECIPHER_AND_INTCHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 9)
+#define ENRRC_ENPDCP_SEC_CONFIG_REQ_EV (DWORD)(ENRRC_ENPDCP_EVENT_BASE + 10)
+
+#define ENRRCENPDCP_SMC_INTEGRITY_CHECK_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 0)
+#define ENRRCENPDCP_DATA_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 1)
+#define ENRRCENPDCP_INTEGIRTY_FAIL_IND_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 2)
+#define ENRRCENPDCP_CONFIG_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 3)
+#define ENRRCENPDCP_DATAC_NF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 4)
+#define ENRRCENPDCP_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 5)
+#define ENRRCENPDCP_ENABLE_UL_CIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 6)
+#define ENRRCENPDCP_ENABLE_UL_DECIPHER_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 7)
+#define ENRRCENPDCP_COUNTER_CHECK_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 8)
+#define ENRRCENPDCP_MDT_REQ_EV (DWORD)(ENRRC_ENPDCP_RSP_EVENT + 9)
+
+#define ENPDCP_EDCP_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 0)
+#define ENRLC_ENMAC_COMPLETE_IND (DWORD)(PS_ENDCP_RSP_EVENT + 1)
+/* ========================================================================
+ ENPDCP TIMER ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDCP_DISCARDTIMER_EV (DWORD)(ENPDCP_TIMER_EVENT_BASE + 0)
+/* ========================================================================
+ PDI - PDCP ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENPDI_DATA_REQ_EV (DWORD)(ENPDI_ENPDCP_EVENT_BASE + 0)
+
+#define ENPDI_DATA_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 0)
+#define ENPDI_NOT_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 1)
+#define ENPDI_READY_IND_EV (DWORD)(ENPDI_ENPDCP_RSP_EVENT + 2)
+
+
+/* ========================================================================
+ TRS ÏûÏ¢ºÅ¶¨ÒåΪGCF ²âÊÔ¶øÌí¼Ó2010/3/8 SHIFANGMING
+======================================================================== */
+
+#define LTE_GCF_STARTCHECK_REQ_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 0)
+#define LTE_GCF_CHECKPASS_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 1)
+#define LTE_GCF_CHECKFAIL_IND_EV (DWORD)(LTE_GCF_TRS_EVENT_BASE + 2)
+
+#define LTE_GCF_CHECK_TIMER_EV (DWORD)(LTE_GCF_TIMER_EVENT_BASE + 0)
+
+/* ========================================================================
+ ENRLC - TRS ÏûÏ¢ºÅ¶¨Òå2010/3/1 LIUHUAN
+======================================================================== */
+#define TRS_ENRLC_UMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 0)
+#define TRS_ENRLC_AMPDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 1)
+#define TRS_ENRLC_SDU_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 2)
+#define TRS_ENRLC_AUTOACK_REQ_EV (DWORD)(TRS_ENRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ PDI - TRS ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define SIMULATI_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 0)
+#define SIMULATI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 1)
+#define SIMULATI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 2)
+#define SIMULATI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 3)
+#define SIMULATI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 4)
+#define SIMULATI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 5)
+#define SIMULATI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 6)
+#define SIMULATI_DATA_IND_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 7)
+#define SIMULPSI_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 8)
+#define SIMULATI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 9)
+#define SIMULATI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 10)
+#define SIMULATI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 11)
+#define SIMULATI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 12)
+#define SIMULATI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULPDI_EVENT_BASE + 13)
+
+#define SIMULENPDI_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 0)
+#define SIMULENPDI_PERIOD_DATA_REQ_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 1)
+#define SIMULENPDI_SEND_DATA_TIMER_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 2)
+#define SIMULENPDI_PERIOD_DATA_STOP_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 3)
+#define SIMULENPDI_CLEAR_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 4)
+#define SIMULENPDI_SHOW_STATISTICS_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 5)
+#define SIMULENPDI_DATA_REQ_EX_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 6)
+#define SIMULENPDI_ROHC_IPV4_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 7)
+#define SIMULENPDI_ROHC_IPV6_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 8)
+#define SIMULENPDI_ROHC_UDP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 9)
+#define SIMULENPDI_ROHC_RTP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 10)
+#define SIMULENPDI_ROHC_ESP_DATA_CONFIG_EV (DWORD)(TRS_SIMULENPDI_EVENT_BASE + 11)
+/* ========================================================================
+ ENRRCÓëENRLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRRC_ENRLC_CONFIG_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 0)
+#define ENRRC_ENRLC_REESTABLISH_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 1)
+#define ENRRC_ENRLC_RELEASE_REQ_EV (DWORD)(ENRRC_ENRLC_EVENT_BASE + 2)
+
+#define ENRLC_ENRRC_CONFIG_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 0)
+#define ENRLC_ENRRC_REESTABLISH_CNF_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 1)
+#define ENRLC_ENRRC_RETX_FAIL_IND_EV (DWORD)(ENRRC_ENRLC_RSP_EVENT + 2)
+/* ========================================================================
+ UMģʽÉÏÐÐÊý¾ÝÈ·ÈÏÏûÏ¢
+======================================================================== */
+#define ENRLC_ENPDCP_UMDATA_CNF_EV (DWORD)(ENPDCP_ENRLC_EVENT_BASE + 0)
+
+
+/* ========================================================================
+ ENRLC ¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define ENRLC_REORDERING_TIMER_EV (DWORD)(ENRLC_TIMER_EVENT_BASE + 0)
+/*EPHY--->ENMAC*/
+#define EPHY_ENMAC_DATA_IND_EV (DWORD)(ENMAC_EPHY_RSP_EVENT + 0) /*EUMAC·¢Ë͵ÄÊý¾Ýµ½´ï*/
+
+/***************************************************** ¶ÔÓ¦UE²àRRC Ïà¹ØÏûÏ¢ *********** Êý¾ÝÃæÕâÀïÓ¦¸Ã²»ÐèÒªÕâЩÏûÏ¢ ÕâÀïµÄ¶¨ÒåÊÇÒÔ·ÀÍòÒ» ******************************************************/
+#define ENMAC_CCCH_DATA_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 0) /*RRC²àÇëÇóCCCHÊý¾Ý*/
+#define ENMAC_COMM_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 1) /*RRC²à·¢ËÍͨÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_DEDI_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 2) /*RRC²à·¢ËÍרÓÃÅäÖÃÊý¾Ý*/
+#define ENMAC_REL_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 3) /*RRC²àÇëÇóMACÊÍ·Å×ÊÔ´¡¢Í˳öÁ¬½Ó̬*/
+#define ENMAC_RESET_MAC_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 4) /*RRC²àÇëÇóMAC RESET*/
+#define ENMAC_RESUME_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 5) /*RRC²àÇëÇó»Ö¸´RB*/
+#define ENMAC_SUSPEND_RB_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 6) /*RRC²àÇëÇóÔÝÍ£RB*/
+#define ENMAC_ACTIVE_CONFIG_REQ_EV (DWORD)(ENRRC_ENMAC_EVENT_BASE + 7)
+
+
+
+#define ENMAC_CCCH_DATA_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 0) /*MAC¸æÖªRRC CCCH Êý¾Ýµ½´ï*/
+#define ENMAC_RA_PROBLEM_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 1) /*MAC¸æÖªRRC RA ÖØ´«´ÎÊý¹ý¶à*/
+#define ENMAC_RA_SUCCESS_IND_EV (DWORD)(ENRRC_ENMAC_RSP_EVENT + 2) /*MAC¸æÖªRRC RA ³É¹¦*/
+
+/*TRS--->EPHY*/
+#define EPHY_TIMER_INTERUPT_EV (DWORD)(TRS_EPHY_EVENT_BASE + 1) /* ×ÓÖ¡Öжϴ¥·¢ÏûÏ¢ */
+#define TRS_EPHY_DUPLICATE_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 2) /*TRSÏòEPHY·¢ËÍÖظ´·¢ËÍÊý¾ÝµÄÅäÖÃÏûÏ¢*/
+#define EPHY_DL_RARESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 3) /*TRSÏòEPHY·¢ËÍ RA³É¹¦Óë·ñµÄÅäÖà */
+#define EPHY_DL_CRRESULT_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 4) /*TRSÏòEPHY·¢ËÍ CR³É¹¦Óë·ñµÄÅäÖà */
+#define TRS_EPHY_DISCARD_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 5) /*TRSÏòEPHY·¢ËÍ ¶ª°üµÄÅäÖà */
+#define TRS_EPHY_GRANT_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 6) /*TRSÏòEPHY·¢ËÍ ÊÚȨµÄÅäÖòÎÊý */
+#define TRS_EPHY_DISORDER_SEND_CONFIG_EV (DWORD)(TRS_EPHY_EVENT_BASE + 7) /*TRSÏòEPHY·¢ËÍÂÒÐò·¢Ë͵ÄÅäÖÃÏûÏ¢*/
+
+#define EPHY_ULGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 8) /*¼¤·¢ÉÏÐÐ×éÖ¡*/
+#define EPHY_DLGRANT_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 9) /*¼¤·¢ÏÂÐÐ×éÖ¡*/
+#define EPHY_GRANTARRAYCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 10) /*ÅäÖÃÉÏÏÂÐÐÊÜȨÊý×é*/
+#define EPHY_IDLE_PERIOD_REP_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 11) /*ÅäÖÿÕÏÐʱ¼ä*/
+#define EPHY_CONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 12) /*¹¤¾ß¶ÔEPHYµÄÅäÖÃ*/
+/* C# adaptor·¢Ë͵½ephyµÄÏûÏ¢£¬ÁÙʱ´æ·ÅÔÚÕâÀï*/
+#define TRS_FREQ_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 13)
+#define TRS_CELL_SCAN_IND (DWORD)(TRS_EPHY_EVENT_BASE + 14)
+#define TRS_CELL_DEL_IND (DWORD)(TRS_EPHY_EVENT_BASE + 15)
+#define TRS_CELL_MOD_IND (DWORD)(TRS_EPHY_EVENT_BASE + 16)
+#define TRS_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 17) // ÉèÖÃC#ģʽ£¬0 - auto £¬ 1- manual
+#define TRS_MSG_MODE_SET_IND (DWORD)(TRS_EPHY_EVENT_BASE + 18) // ÉèÖÃij¸öÏûÏ¢µÄģʽ£¬×Ô¶¯»òÊÖ¶¯
+#define EPHY_CELLINFOCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 19)
+#define EPHY_EXTGRANTCONFIG_REQ_EV (DWORD)(TRS_EPHY_EVENT_BASE + 20)
+/*TRS--->ENMAC*/
+#define TRS_ENMAC_TA_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 1) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà TAÃüÁîÏûÏ¢ Я´øWORDÊý¾Ý£¬Îª0ʱ²»×éTA£¬·Ç0ʱ£¬Ê¹ÓøÃÖµ×éTA*/
+#define TRS_ENMAC_DRX_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 2) /*TRSÏòENMACUL·¢ËÍ×éÖ¡¹ý³ÌÊÇ·ñʹÓà DRXÃüÁî ÏûÏ¢*/
+#define TRS_ENMAC_CCCH_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 3) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡CCCCHÊý¾Ý*/
+#define TRS_ENMAC_CRID_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 4) /*Я´øBYTEÊý¾Ý£¬BIT0Ϊ0ʱ£¬²»×éÖ¡¾ºÕù½â¾öÉí·ÝÊý¾Ý£¬BIT0Ϊ1£¬
+ BIT1Ϊ0ʱ×éÖ¡·ÇÆ¥ÅäÊý¾Ý£¬ BIT0Ϊ1£¬BIT1Ϊ1ʱ£¬×éÖ¡ÕýÈ·Éí·ÝÊý¾Ý*/
+#define TRS_ENMAC_BACKOFF_CONFIG_REQ_EV (DWORD)(TRS_ENMAC_EVENT_BASE + 5) /*Я´øBYTEÊý¾Ý Ôݶ¨*/
+
+#define ENMAC_MCCH_DATA_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 0 )
+#define ENRRC_ENMEL2_REL_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 1)
+#define TRS_ENMEL2_RLC_SDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 2)
+#define TRS_ENMEL2_RLC_PDU_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 3)
+#define TRS_ENMEL2_MSI_CONFIG_REQ_EV (DWORD)(ENMEL2_EVENT_BASE + 4)
+#define EUDBG_EMM_PLAIN_DL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 4)
+#define EUDBG_SEND_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 5)
+#define EUDBG_RECV_RLCSRBPDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 6)
+#define EUDBG_AM_SEND_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 7)
+#define EUDBG_AM_RECV_STATUS_PDU_INFO_Ev (DWORD)(EUDBG_EVENT_BASE + 8)
+#define LTE_P_DLSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 9)
+#define LTE_P_ULSCH_DATA_TRACE_EV (DWORD)(EUDBG_EVENT_BASE + 10)
+#define LTE_P_MAC_SR_REQ_EV (DWORD)(EUDBG_EVENT_BASE + 11)
+#define LTE_EL2_THROUGHPUT_IND_EV (DWORD)(EUDBG_EVENT_BASE + 12)
+#define LTE_EL2_STATE_IND_EV (DWORD)(EUDBG_EVENT_BASE + 13)
+#define EUDBG_EMM_PLAIN_UL_MSG_EV (DWORD)(EUDBG_EVENT_BASE + 14)
+/* ========================================================================
+ LTEÏà¹ØµÄÏûÏ¢ºÅ¶¨Òå END
+======================================================================== */
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ BEGIN
+======================================================================== */
+
+
+/* ========================================================================
+ ·²âÈí¼þÏà¹ØʼþºÅ END
+======================================================================== */
+/* ========================================================================
+ WÏà¹ØʼþºÅ START
+======================================================================== */
+/* ========================================================================
+ ASC£UMTS ASÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRC£SCIÏûÏ¢ºÅ¶¨Òå W ÓëTD¹²ÓÃ
+======================================================================== */
+
+/* ========================================================================
+ WRRC - ÄÚ²¿ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_READ_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 0)
+#define WRRC_READ_SYSINFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 1)
+#define WRRC_READ_SYSINFO_REJ_EV (DWORD)(WRRC_EVENT_BASE + 2)
+#define WRRC_STOP_SYSINFO_REQ_EV (DWORD)(WRRC_EVENT_BASE + 3)
+#define WRRC_READ_DYN_SIB_REQ_EV (DWORD)(WRRC_EVENT_BASE + 4)
+#define WRRC_READ_DYN_SIB_CNF_EV (DWORD)(WRRC_EVENT_BASE + 5)
+#define WRRC_SIB_MODIFIED_IND_EV (DWORD)(WRRC_EVENT_BASE + 6)
+#define WRRC_CELLUPDATE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 7)
+#define WRRC_CELL_RESEL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 8)
+#define WRRC_CELL_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 9)
+#define WRRC_REL_CONN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 10)
+#define WRRC_RESUME_CELL_REQ_EV (DWORD)(WRRC_EVENT_BASE + 11)
+#define WRRC_RPLMN_INFO_IND_EV (DWORD)(WRRC_EVENT_BASE + 12)
+#define WRRC_RESOURE_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 13)
+#define WRRC_RESOURCE_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 14)
+#define WRRC_UPDATE_EPLMN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 15)
+#define WRRC_HIGH_MOBILITY_IND (DWORD)(WRRC_EVENT_BASE + 16)
+#define WRRC_HO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 17)
+#define WRRC_HO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 18)
+#define WRRC_HO_TO_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 19)
+#define WRRC_HO_TO_UTRAN_CNF_EV (DWORD)(WRRC_EVENT_BASE + 20)
+#define WRRC_HO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 21)
+#define WRRC_CCO_FROM_UTRAN_REQ_EV (DWORD)(WRRC_EVENT_BASE + 22)
+#define WRRC_CCO_FROM_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 23)
+#define WRRC_CCO_TO_UTRAN_IND_EV (DWORD)(WRRC_EVENT_BASE + 24)
+#define WRRC_CCO_TO_UTRAN_REJ_EV (DWORD)(WRRC_EVENT_BASE + 25)
+#define WRRC_RADIO_LINK_FAIL_IND_EV (DWORD)(WRRC_EVENT_BASE + 26) /*UECAPABILITYINFOÖØ´«Ê§°Üµ¼ÖÂСÇø¸üÐÂ*/
+#define WRRC_NEIBCELL_CHG_IND_EV (DWORD)(WRRC_EVENT_BASE + 27)
+#define WRRC_FACH_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 28)
+#define WRRC_FACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 29)
+#define WRRC_DRX_CHANGE_IND_EV (DWORD)(WRRC_EVENT_BASE + 30)
+#define WRRC_SEND_BUF_EST_REQ_EV (DWORD)(WRRC_EVENT_BASE + 31)
+#define WRRC_ABORT_RATCHG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 32)
+#define WRRC_CHG_CAMPON_TYPE_EV (DWORD)(WRRC_EVENT_BASE + 33)
+#define WRRC_GET_RF_REQ_EV (DWORD)(WRRC_EVENT_BASE + 34) /*WSIR->WCSR*/
+#define WRRC_GET_RF_CNF_EV (DWORD)(WRRC_EVENT_BASE + 35) /*WCSR->WSIR*/
+#define WRRC_SYSINFO_CONTAINER_IND_EV (DWORD)(WRRC_EVENT_BASE + 36) /*WCSR->WSIR*/
+#define WRRC_ETWS_CFG_REQ_EV (DWORD)(WRRC_EVENT_BASE + 37)
+#define WRRC_ETWS_CFG_END_EV (DWORD)(WRRC_EVENT_BASE + 38)
+#define WRRC_ETWS_CONTINUE_REQ_EV (DWORD)(WRRC_EVENT_BASE + 39)
+#define WRRC_EFACH_CFG_IND_EV (DWORD)(WRRC_EVENT_BASE + 40) /*WCMR->WRBC*/
+#define WRRC_NEIGHBORCELL_HSSCCH_ORDER_REQ_EV (DWORD)(WRRC_EVENT_BASE + 41)
+#define WRRC_RBC_BUFFER_MSG_PROC_REQ_EV (DWORD)(WRRC_EVENT_BASE + 42)
+/* ========================================================================
+ WRLC - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWRLC_CONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 0)
+#define CWRLC_RELEASE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 1)
+#define CWRLC_SUSPEND_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 2)
+#define CWRLC_RESUME_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 3)
+#define CWRLC_CONTINUE_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 4)
+#define UWRLC_DATA_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 5)
+#define CWRLC_CBS_RBCONFIG_REQ_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 6)
+#define CWRLC_SET_DATA_NOTIFY_MODE_EV (DWORD)(WRLC_WRRC_EVENT_BASE + 7)
+
+#define CWRLC_SUSPEND_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 0)
+#define UWRLC_DATA_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 1)
+#define CWRLC_STATUS_IND_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 2)
+#define UWRLC_DATA_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 3)
+#define CWRLC_CONFIG_CNF_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 4)
+#define CWRLC_PCH_ULDATA_TRANSFER_REQ_EV (DWORD)(WRLC_WRRC_RSP_EVENT + 5)
+
+/* ========================================================================
+ WMAC - WRRC/WMAC - WMAC_MCR ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define CWMAC_ASC_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 0)
+#define CWMAC_RACH_PARA_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 1)
+#define CWMAC_TFC_CTRL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 2)
+#define CWMAC_CCTRCH_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 3)
+#define CWMAC_ACTTIME_NOTIFY_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 4)
+#define CWMAC_CONTINUE_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 5)
+#define CWMAC_DEL_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 6)
+#define CWMAC_RNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 7)
+#define CWMAC_ERNTI_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 8)
+#define CWMAC_HS_RESET_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 9)
+#define CWMAC_SRB_DELAY_CONFIG_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 10)
+#define CWMAC_TV_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 11)
+#define CWMAC_Q_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 12)
+#define CWMAC_UE_MEAS_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 13)
+#define CWMAC_TV_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 14)
+#define CWMAC_Q_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 15)
+#define CWMAC_UE_MEAS_REL_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 16)
+#define CWMAC_TV_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 17)
+#define CWMAC_TV_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 18)
+#define CWMAC_DL_MEAS_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 19)
+#define CWMAC_DL_MEAS_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 20)
+#define CWMAC_ADDTV_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 21)
+#define CWMAC_ADDQ_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 22)
+#define CWMAC_ADDUE_MEAS_REPORT_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 23)
+#define CWMAC_SUSPEND_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 24)
+#define CWMAC_RESUME_REQ_EV (DWORD)(WMAC_WRRC_EVENT_BASE + 25)
+
+#define CWMAC_CONFIG_CHG_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 0)
+#define CWMAC_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 1)
+#define CWMAC_EFACH_STATUS_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 2)
+#define UWMAC_PCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 3)
+#define UWMAC_BCCH_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 4)
+#define CWMAC_ADDTV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 5)
+#define CWMAC_TV_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 6)
+#define CWMAC_ADDQ_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 7)
+#define CWMAC_ADDUE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 8)
+#define CWMAC_Q_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 9)
+#define CWMAC_UE_MEAS_REPORT_IND_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 10)
+#define CWMAC_NOTIFY_DL_PERIOD_REPORT_REQ_EV (DWORD)(WMAC_WRRC_RSP_EVENT + 11)
+/* ========================================================================
+ WMAC - UL/DL - WMAC-CÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+
+/* ========================================================================
+ L1W - WRRC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define L1W_GSM_MEAS_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 0)
+#define L1W_GSM_MEAS_DELETE_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 1)
+#define L1W_GSM_MEAS_RESUME_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 2)
+#define L1W_GSM_MEAS_SUSPEND_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 3)
+#define L1W_GSM_MEAS_TONULL_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 4)
+#define L1W_LTE_FREQ_LIST_CONFIG_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 5)
+#define L1W_LTE_MEAS_MASK_SET_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 6)
+#define L1W_GET_RF_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 7)
+#define L1W_PLMN_END_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 8)
+#define L1W_IRAT_RSRC_REQ_EV (DWORD)(L1W_WRRC_EVENT_BASE + 9)
+#define L1W_CM_CONFIG_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 10)
+#define L1W_CM_FALLBACK_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 11)
+#define L1W_WRRC_LEAVE3G_REQ (DWORD)(L1W_WRRC_EVENT_BASE + 12)
+
+#define L1W_GSM_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 0)
+#define L1W_GET_RF_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 1)
+#define L1W_IRAT_RSRC_CNF_EV (DWORD)(L1W_WRRC_RSP_EVENT + 2)
+#define L1W_LTE_MEAS_IND_EV (DWORD)(L1W_WRRC_RSP_EVENT + 3)
+#define L1W_CM_FALLBACK_IND (DWORD)(L1W_WRRC_RSP_EVENT + 4)
+#define L1W_CM_OVERLAP_IND (DWORD)(L1W_WRRC_RSP_EVENT + 5)
+#define L1W_CM_INFO_IND (DWORD)(L1W_WRRC_RSP_EVENT + 6)
+/* ========================================================================
+ PDCP - WRRC ÏûÏ¢ºÅ¶¨Òå(PDCPʼþºÅ¹²ÓÃ)
+======================================================================== */
+
+/* ========================================================================
+ WRLC -WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ L1W - WMAC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WISR_FRAME_IND_EV (DWORD)(WMAC_L1W_EVENT_BASE + 0)
+/* ========================================================================
+ PDCP - URLC ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+#define UWRLC_PDCP_DATA_IND_EV (DWORD)(PDCP_WRLC_EVENT_BASE + 0)
+/* ========================================================================
+ USIR - UPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_BCH_READ_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 0)
+#define W_P_BCH_OPEN_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 1)
+#define W_P_BCH_RELEASE_REQ_EV (DWORD)(WSIR_WPHY_EVENT_BASE + 2)
+
+#define W_P_BCH_IND_EV (DWORD)(WSIR_WPHY_RSP_EVENT + 0)
+/* ========================================================================
+ WCSR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_FREQUENCY_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 0)
+#define W_P_ABORT_FREQ_SCAN_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 1)
+#define W_P_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 2)
+#define W_P_ABORT_CELL_SEARCH_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 3)
+#define W_P_CAMPON_A_CELL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 4)
+#define W_P_REL_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 5)
+#define W_P_RESET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 6)
+#define W_P_SET_IRAT_MODE_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 7)
+#define W_P_RPI_SET_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 8)
+#define W_P_RPI_CFG_REQ_EV (DWORD)(WCSR_WPHY_EVENT_BASE + 9)
+
+
+#define W_P_FREQUENCY_SCAN_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 0)
+#define W_P_CELL_SEARCH_IND_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 1)
+#define W_P_RESET_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 2)
+#define W_P_REL_CNF_EV (DWORD)(WCSR_WPHY_RSP_EVENT + 3)
+
+/* ========================================================================
+ WMCR - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_INTRA_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 0)
+#define W_P_INTER_FREQ_MEAS_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 1)
+#define W_P_FMO_INFO_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 2)
+#define W_P_MEAS_REL_REQ_EV (DWORD)(WMCR_WPHY_EVENT_BASE + 3)
+
+#define W_P_INTRA_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 1)
+#define W_P_INTER_FREQ_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 2)
+#define W_P_SERVCELL_MEAS_IND_EV (DWORD)(WMCR_WPHY_RSP_EVENT + 3)
+
+
+/* ========================================================================
+ WRBC - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_DL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 0)
+#define W_P_DL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 1)
+#define W_P_UL_DPCH_SETUP_MODIFY_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 2)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 3)
+#define W_P_NEIGHBORCELL_HSSCCH_ORDER_ABORT_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 4)
+#define W_P_UL_DPCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 5)
+#define W_P_ADD_MODIFY_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 6)
+#define W_P_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 7)
+#define W_P_STOP_PAGING_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 8)
+#define W_P_ADD_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 9)
+#define W_P_REL_HSDPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 10)
+#define W_P_REL_SCCPCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 11)
+#define W_P_ADD_MODIFY_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 12)
+#define W_P_STOP_CBS_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 13)
+#define W_P_L1_RESOURCE_CFG_FINAL_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 14)
+#define W_P_ADD_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 15)
+#define W_P_REL_HSUPA_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 16)
+#define W_P_HSPA_PLUS_FACH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 17)
+#define W_P_HSPA_PLUS_PCH_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 18)
+#define W_P_HSPA_PLUS_FACH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 19)
+#define W_P_HSPA_PLUS_PCH_REL_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 20)
+#define W_P_EFACH_UPDATE_RNTI_REQ_EV (DWORD)(WRBC_WPHY_EVENT_BASE + 21)
+#define W_P_ADD_PRACH_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 22)
+#define W_P_DL_FDPCH_SETUP_MODIFY_REQ (DWORD)(WRBC_WPHY_EVENT_BASE + 23)
+
+
+#define W_P_IN_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 0)
+#define W_P_OUT_SYNC_IND_EV (DWORD)(WRBC_WPHY_RSP_EVENT + 1)
+#define W_P_DPCH_SETUP_MODIFY_CNF (DWORD)(WRBC_WPHY_RSP_EVENT + 2)
+#define W_P_HSSCCH_ORDER_IND (DWORD)(WRBC_WPHY_RSP_EVENT + 3)
+
+
+
+/* ========================================================================
+ WMAC_UL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_RACH_PROCEDURE_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 0)
+#define W_P_RACH_PROCEDURE_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 1)
+#define W_P_EFACH_NO_DATA_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 2)
+#define W_P_ETFC_PARAM_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 3)
+#define W_P_POST_VERFY_FAIL_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 4)
+#define W_P_MAC_DTX_CYCLE_INFO_REQ_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 5)
+#define W_P_TFCI_CM_INFO_IND_EV (DWORD)(WMAC_UL_WPHY_EVENT_BASE + 6)
+/* ========================================================================
+ WMAC_DL - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UE_INTERNAL_MEAS_REQ_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 0)
+#define W_P_UE_INTERNAL_MEAS_IND_EV (DWORD)(WMAC_DL_WPHY_EVENT_BASE + 1)
+
+/* ========================================================================
+ L1W - WPHY ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_UMTS_IDLE_PERIOD_REPMODE_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 0) /*µÈ¼ÛÓÚL1G_UMTS_IDLE_PERIOD_REPMODE_REQ_EV*/
+#define W_P_IRAT_GAP_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 1) /*µÈ¼ÛÓÚL1G L1W_GSM_INACT_TIME_IND_EV*/
+#define W_P_ABORT_IRAT_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 2) /*µÈ¼ÛÓÚL1G L1W_ABORT_GSM_GAP_REQ_EV*/
+#define W_P_COMPRESS_MODE_CONFIG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 3)
+#define W_P_CARD2_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 4) /*T_zW_P_card2_gap_req*/
+#define W_P_CARD2_GAP_REL_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 5) /*T_zW_P_card2_gap_rel_req*/
+#define W_P_CARD2_STOP_GAP_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 6) /*T_zW_P_card2_stop_gap_req*/
+#define W_P_CARD1_SUSPEND_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 7) /*T_zW_P_card1_suspend_req*/
+#define W_P_CARD1_RESUME_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 8) /*T_zW_P_card1_resume_req*/
+#define W_P_ZWPCG_REQ_EV (DWORD)(L1W_WPHY_EVENT_BASE + 9)
+
+#define W_P_UMTS_INACTIVE_TIME_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 0)
+#define W_P_ABORT_FREQ_SCAN_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 1)
+#define W_P_ABORT_CELL_SEARCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 2)
+#define W_P_BCH_RELEASE_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 3)
+#define W_P_CAMPON_A_CELL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 4)
+#define W_P_DPCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 5)
+#define W_P_REL_SCCPCH_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 6)
+#define W_P_STOP_PAGING_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 7)
+#define W_P_STOP_CBS_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 8)
+#define W_P_REL_HSDPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 9)
+#define W_P_REL_HSUPA_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 10)
+#define W_P_HSPA_PLUS_FACH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 11)
+#define W_P_HSPA_PLUS_PCH_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 12)
+#define W_P_ABORT_IRAT_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 13)
+#define W_P_CARD2_GAP_IND_EV (DWORD)(L1W_WPHY_RSP_EVENT + 14) /*T_zW_P_card2_gap_ind*/
+#define W_P_CARD2_GAP_REL_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 15) /*T_zW_P_card2_gap_rel_cnf*/
+#define W_P_CARD2_STOP_GAP_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 16) /*T_zW_P_card2_stop_gap_cnf*/
+#define W_P_CARD1_SUSPEND_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 17) /*T_zW_P_card1_suspend_cnf*/
+#define W_P_ZWPCG_CNF_EV (DWORD)(L1W_WPHY_RSP_EVENT + 18)
+
+
+/* ========================================================================
+ L1W ÄÚ²¿ ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define W_P_CHECK_RF_IND_EV (DWORD)(L1W_EVENT_BASE + 0)
+#define W_P_ACTIVE_IND_EV (DWORD)(L1W_EVENT_BASE + 1)
+#define L1W_MEAS_TIMESTAMP_IND_EV (DWORD)(L1W_EVENT_BASE + 2)
+#define L1W_MEAS_TICKTRACE_IND_EV (DWORD)(L1W_EVENT_BASE + 3)
+
+/* ========================================================================
+ WRRC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WSIR_T_BCH_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 0)
+#define WSIR_T_SIB7_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 1)
+#define WSIR_T_VTSIB_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 2)
+#define WSIR_T_R_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 3)
+#define WSIR_T_BCCHMODIFY_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 4)
+#define WCSR_T_HIGHSPEED_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 5)
+#define WCSR_T_HYSTX_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 6)
+#define WCSR_T_PROTECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 7)
+#define WCSR_T_NCELL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 8)
+#define WCSR_T_OOS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 9)
+#define WCSR_T_CAMP1S_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 10) /*פÁôijСÇø1S³¬Ê±*/
+#define WCSR_T_L1_RELATED_EVENT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 11)
+#define WCSR_T_REDIRECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 12)
+#define WMCR_T_RESELECT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 13)
+#define WMCR_T_PERIOD_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 14)
+#define WMCR_T_TRIGGER_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 15)
+#define WMCR_T_EM_CELLINFO_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 16)
+#define WCER_T_SIGCONNRELIND_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 17)
+#define WCER_T_ETWS_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 18)
+#define WCER_T_FACHCONNREL_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 19)
+#define WRRC_T300_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 20)
+#define WRRC_T302_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 21)
+#define WRRC_T304_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 22)
+#define WRRC_T305_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 23)
+#define WRRC_T307_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 24)
+#define WRRC_T308_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 25)
+#define WRRC_T309_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 26)
+#define WRRC_T312_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 27)
+#define WRRC_T313_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 28)
+#define WRRC_T314_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 29)
+#define WRRC_T315_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 30)
+#define WRRC_T316_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 31)
+#define WRRC_T319_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 32)
+#define WRRC_T320_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 33)
+#define WMCR_T322_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 34)
+#define WRRC_T323_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 35)
+#define WRRC_T325_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 36)
+#define WRRC_T_WAIT_EXPIRY_EV (DWORD)(WRRC_TIMER_EVENT_BASE + 37)
+
+/* ========================================================================
+ WPDCP¶¨Ê±Æ÷¶¨Òå(wÎÞÐÂÔö£¬Í¬TD)
+======================================================================== */
+
+
+/* ========================================================================
+ WRLC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WRLC_T_DISCARD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 0)
+#define WRLC_T_POLL_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 1)
+#define WRLC_T_POLLPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 2)
+#define WRLC_T_POLLPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 3)
+#define WRLC_T_STATUSPROH_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 4)
+#define WRLC_T_STATUSPRD_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 5)
+#define WRLC_T_RESET_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 6)
+#define WRLC_T_MRW_EXPIRY_EV (DWORD)(WRLC_TIMER_EVENT_BASE + 7)
+
+/* ========================================================================
+ WMAC¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+#define WMAC_MCR_T_TRIGGER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 0)
+#define WMAC_MCR_T_PERIOD_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 1)
+#define WMAC_MCR_T_PENDING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 2)
+#define WMAC_T_HSTIMER_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 3)
+#define WMAC_T_RESET_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 4)
+#define WMAC_T_BO1_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 5)
+#define WMAC_T_TB_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 6)
+#define WMAC_T_AG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 7)
+#define WMAC_T_RG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 8)
+#define WMAC_T_SING_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 9)
+#define WMAC_T_SIG_EXPIRY_EV (DWORD)(WMAC_TIMER_EVENT_BASE + 10)
+
+/* ========================================================================
+ L1W¶¨Ê±Æ÷¶¨Òå
+======================================================================== */
+/* ========================================================================
+ WSIRÓ빤¾ß½»»¥Ê¼þºÅ¶¨Òå
+======================================================================== */
+#define TEST_WSIR_DECSIB_EV (DWORD)(WSIR_TEST_EVENT_BASE + 0)
+/* ========================================================================
+ NWRLCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_UWRLC_DATA_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 0)
+#define TEST_UWRLC_DATA_IND_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 1)
+#define TEST_CWRLC_CONFIG_REQ_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 2)
+#define TEST_WRLC_ACK_CTRL_UTRAN_EV (DWORD)(NWRLC_EVENT_BASE + 3)
+
+/* ========================================================================
+ NWMACÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TEST_WMAC_ACK_CTRL_UTRAN_EV (DWORD)(NWMAC_EVENT_BASE + 0)
+#define TEST_WMAC_HSUPA_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 1)
+#define TEST_WMAC_HSUPA_CFG_EV (DWORD)(NWMAC_EVENT_BASE + 2)
+#define TEST_WMAC_HSUPA_SIINFO_EV (DWORD)(NWMAC_EVENT_BASE + 3)
+#define TEST_WMAC_HSUPA_HEADER_INFO_EV (DWORD)(NWMAC_EVENT_BASE + 4)
+#define TEST_WMAC_NOTIFY_DATA_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 5)
+#define TEST_WMAC_PA_PLUS_CFG_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 6)
+#define TEST_WMAC_CRC_RESULT_REQ_EV (DWORD)(NWMAC_EVENT_BASE + 7)
+#define TEST_UWMAC_DATA_IND_EV (DWORD)(NWMAC_EVENT_BASE + 8)
+/* ========================================================================
+ NCBSÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ TCÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+
+/* ========================================================================
+ WRRCº¯ÊýÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define WRRC_FUNC_GET_REPLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 0)
+#define WRRC_FUNC_GET_REPLMN_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 1)
+#define WRRC_FUNC_CHECK_PLMN_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 2)
+#define WRRC_FUNC_CHECK_LAI_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 3)
+#define WRRC_FUNC_MEAS_LEAVE3G_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 4)
+#define WRRC_FUNC_READ_SIB_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 5)
+#define WRRC_FUNC_READ_SIB_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 6)
+#define WRRC_FUNC_SER_CELL_IND_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 7)
+#define WRRC_FUNC_SYSINFO_MODIFY_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 8)
+#define WRRC_FUNC_SET_SERVCELL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 9)
+#define WRRC_FUNC_MEAS_ON_RACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 10)
+#define WRRC_FUNC_START_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 11)
+#define WRRC_FUNC_DEL_MEAS_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 12)
+#define WRRC_FUNC_MEAS_TONULL_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 13)
+#define WRRC_FUNC_RESEL_IDLE_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 14)
+#define WRRC_FUNC_STOP_SYSINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 15)
+#define WRRC_FUNC_CFG_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 16)
+#define WRRC_FUNC_CFG_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 17)
+#define WRRC_FUNC_REL_FACH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 18)
+#define WRRC_FUNC_REL_FACH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 19)
+#define WRRC_FUNC_REL_PCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 20)
+#define WRRC_FUNC_REL_PCH_CNF_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 21)
+#define WRRC_FUNC_SEND_SINGLE_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 22)
+#define WRRC_FUNC_SEND_CS_BUF_MSG_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 23)
+#define WRRC_FUNC_REL_SCCPCH_STOP_MAC_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 24)
+#define WRRC_FUNC_RESUME_FACH_CFG_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 25)
+#define WRRC_FUNC_REL_SER_CELL_BCH_REQ_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 26)
+#define WRRC_FUNC_RESTART_SCELL_SIB7_TIMER_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 27)
+#define WRRC_FUNC_RESUME_READ_SER_CELL_BCH_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 28)
+#define WRRC_FUNC_READ_CGIINFO_EV (DWORD)(WRRC_FUNC_EVENT_BASE + 29)
+/* ========================================================================
+ RRCº¯ÊýÖµ¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define RRC_FUNC_GET_TICK_COUNT_EV (DWORD)(RRC_FUNC_TRACE_BASE + 0)
+#define RRC_FUNC_GET_NV_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 1)
+#define RRC_FUNC_GET_UICC_ITEM_EV (DWORD)(RRC_FUNC_TRACE_BASE + 2)
+#define RRC_FUNC_GET_PLMN_TYPE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 3)
+#define RRC_FUNC_GET_3A_THREOLD_EV (DWORD)(RRC_FUNC_TRACE_BASE + 4)
+#define RRC_FUNC_GET_PSLOCI_INFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 5)
+#define RRC_FUNC_GET_COUNTC_EV (DWORD)(RRC_FUNC_TRACE_BASE + 6)
+#define RRC_FUNC_GET_MASTER_MODE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 7)
+#define RRC_FUNC_GET_SFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 8)
+#define RRC_FUNC_GET_CFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 9)
+#define RRC_FUNC_GET_AMDLPDU_SIZE_EV (DWORD)(RRC_FUNC_TRACE_BASE + 10)
+#define RRC_FUNC_GET_SIB7_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 11)
+#define RRC_FUNC_GET_VTSIB_TIMEOUT_CELLINFO_EV (DWORD)(RRC_FUNC_TRACE_BASE + 12)
+/*´òÓ¡µ±Ç°ÊÇ·ñÓÐNASÐÅÁîÕýÔÚ½øÐÐ*/
+#define RRC_FUNC_NAS_SIGNAL_PROC_EXIST_EV (DWORD)(RRC_FUNC_TRACE_BASE + 13)
+#define RRC_FUNC_GET_SRB2_UL_ACT_TIME_EV (DWORD)(RRC_FUNC_TRACE_BASE + 14)
+#define RRC_FUNC_GET_SRB2_MAX_HFN_EV (DWORD)(RRC_FUNC_TRACE_BASE + 15)
+//as comÖеÄbarÐÅÏ¢ÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define AS_FUNC_CLEARBARFREQINFO (DWORD)(RRC_FUNC_TRACE_BASE + 50)
+#define AS_FUNC_ADDTDFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 51)
+#define AS_FUNC_DELTDFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 52)
+#define AS_FUNC_CLEARBARCELLINFO (DWORD)(RRC_FUNC_TRACE_BASE + 53)
+#define AS_FUNC_ADDTDCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 54)
+#define AS_FUNC_ADDGSMCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 55)
+#define AS_FUNC_ADDWFREQTOBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 56)
+#define AS_FUNC_DELWFREQFROMBARFREQLIST (DWORD)(RRC_FUNC_TRACE_BASE + 57)
+#define AS_FUNC_ADDWCELLTOBARCELLLIST (DWORD)(RRC_FUNC_TRACE_BASE + 58)
+#define AS_FUNC_GETDEDIPRIOINFO (DWORD)(RRC_FUNC_TRACE_BASE + 59)
+#define AS_FUNC_GETBARINFO (DWORD)(RRC_FUNC_TRACE_BASE + 60)
+#define AS_FUNC_SETFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 61)
+#define AS_FUNC_CLEARFRTOLTEFLAG (DWORD)(RRC_FUNC_TRACE_BASE + 62)
+//EUSIRÐÅÁî¸ú×ÙÏûÏ¢ºÅ¶¨Òå
+#define EURRC_EUSIR_SIB1_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 63)
+#define EURRC_EUSIR_SIB2_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 64)
+#define EURRC_EUSIR_SIB5_V8H0_IEs_INFO (DWORD)(RRC_FUNC_TRACE_BASE + 65)
+/* ========================================================================
+WÏà¹ØʼþºÅ END
+======================================================================== */
+#ifdef BTRUNK_SUPPORT
+/* ESM --> TSM */
+#define TSM_ESM_DIALED_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 60)
+#define TSM_ESM_BEARER_STATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 61)
+
+/* TSM --> ESM */
+#define TSM_ESM_SYN_BEARSTATE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 62)
+
+
+/* TSM --> EMM */
+#define TSM_EST_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 70)
+#define TSM_EMM_DATA_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 71)
+#define TSM_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 72)
+#define TSM_LOCATIONINFO_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 73)
+#define TSM_UMM_DETACHLTE_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 74)
+
+
+/* EMM/UMM --> TSM */
+#define TSM_EST_CNF_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 80)
+#define TSM_REL_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 81)
+#define TSM_EMM_ATTACHSTATE_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 82)
+#define TSM_EMM_DATA_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 83)
+#define TSM_UMM_PTTINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 84)
+#define TSM_EMM_LOCATIONINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 85)
+
+/*TSM->ASC*/
+#define TSM_ASC_GROUP_REL_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 90)
+#define TSM_ASC_SCANSWITCH_REQ_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 91)
+
+/*ASC->TSM*/
+#define TSM_ASC_TGCCH_MSG_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 100)
+#define TSM_ASC_SCANGROUPINFO_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 101)
+#define TSM_ASC_SET_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 102)
+#define TSM_ASC_REL_ACTIVEGID_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 103)
+#define TSM_ASC_REL_GROUP_IND_EV (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 104)
+
+
+/* ========================================================================
+ TSM¶¨Ê±Æ÷ÏûÏ¢ºÅ¶¨Òå
+======================================================================== */
+#define TSM_TIMER_BASE (DWORD)(EVENT_PS_LTE_BTRUNK_BASE + 300)
+#define TSM_TCMEST_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 1)
+#define TSM_T8001_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 2)
+#define TSM_T8003_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 3)
+#define TSM_T8005_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 4)
+#define TSM_T8006_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 5)
+#define TSM_T8011_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 6)
+#define TSM_T8012_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 7)
+#define TSM_T8014_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 8)
+#define TSM_T8016_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 9)
+#define TSM_T8018_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 10)
+#define TSM_T8020_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 11)
+#define TSM_TPERIOD_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 12)
+#define TSM_TGPS_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 13)
+#define TSM_T8123_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 14)
+#define TSM_TREGRETRY_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 15)
+#define TSM_TCONFIRM_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 16)
+#define TSM_T8125_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 17)
+#define TSM_T8026_EXPIRY_EV (DWORD)(TSM_TIMER_BASE + 18)
+/**************************************************PS LTE BTRUNK msg range end********************************************************/
+#endif
+
+/* LPP-ECIDʼþºÅ¶¨Ò壬¹²¼Æ50¸ö */
+
+/* LPP --> ASC */
+#define LPP_ASC_ECID_MEAS_START_EV (DWORD)(LPP_ECID_EVENT_BASE + 0)
+#define LPP_ASC_ECID_MEAS_ABORT_EV (DWORD)(LPP_ASC_ECID_MEAS_START_EV + 1)
+/* LPP --> EURRC */
+#define ASC_EUCSR_ECID_MEAS_START_EV (DWORD)(LPP_ASC_ECID_MEAS_ABORT_EV + 1)
+#define ASC_EUCSR_ECID_MEAS_ABORT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_START_EV + 1)
+/* EURRC --> ASC */
+#define EURRC_ASC_ECID_MEAS_RESULT_EV (DWORD)(ASC_EUCSR_ECID_MEAS_ABORT_EV + 1)
+/* ASC --> LPP */
+#define ASC_LPP_ECID_MEAS_RESULT_EV (DWORD)(EURRC_ASC_ECID_MEAS_RESULT_EV + 1)
+/* SS --> LPP */
+#define SS_LPP_MOLR_START_IND_EV (DWORD)(ASC_LPP_ECID_MEAS_RESULT_EV + 1)
+#define SS_LPP_MOLR_END_IND_EV (DWORD)(SS_LPP_MOLR_START_IND_EV + 1)
+#define SS_LPP_MTLR_START_IND_EV (DWORD)(SS_LPP_MOLR_END_IND_EV + 1)
+#define SS_LPP_MTLR_END_IND_EV (DWORD)(SS_LPP_MTLR_START_IND_EV + 1)
+/* UMM -->LPP */
+#define UMM_LPP_CELLCHG_IND_EV (DWORD)(SS_LPP_MTLR_END_IND_EV + 1)
+/* LPP TIMER EXPIRY EVENT */
+#define LPP_TRIRPT_TIMER_EXP_EV (DWORD)(UMM_LPP_CELLCHG_IND_EV + 1)
+#define LPP_RETRANS_TIMER_EXP_EV (DWORD)(LPP_TRIRPT_TIMER_EXP_EV + 1)
+#define LPP_MSG_TRACE_LOG_EV (DWORD)(LPP_RETRANS_TIMER_EXP_EV + 1)
+
+#endif /* PS_EVENTDEF_H */
+