blob: e8d8e88c5fd64dedbddf8499df19c1e3cd85d4f4 [file] [log] [blame]
/*
*
* Copyright (C) 2015-2022 ZTE-TSP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/refcount.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <linux/soc/sc/common.h>
#include <linux/soc/sc/spinlock.h>
#include <linux/soc/sc/pcu.h>
#include <linux/soc/sc/rpmsg.h>
#include <dt-bindings/soc/zx297520v3-irq.h>
#include <uapi/linux/sc_bsp/bsp_api.h>
#include <pub_debug_info.h>
#include "pcu-common.h"
#if 0
#define pm_ram_log(fmt, args...) \
{ \
pm_printk("[SLP] " fmt, ##args); \
}
#else
#define pm_ram_log(fmt, args...) \
{ \
printk(KERN_INFO "[SLP] " fmt, ##args); \
}
#endif
#define ZX_IRQ_NUM (IRQ_ZX297520V3_SPI_NUM + 32)
#define PCU_LOCK reg_spin_lock();
#define PCU_UNLOCK reg_spin_unlock();
static struct zx_pcu_int_info zx297520v3_pcu_int_info[] =
{
{
.pcu_index = PCU_AP_TIMER1_INT,
.gic_index = AP_TIMER1_INT,
.status_index = 51,
.wake_index = 0,
.int_name = "ap_timer1",
.irq_type = IRQ_TYPE_EDGE_RISING,
.wl_type = PM_WL_EVENT_AP_TIMER1,
},
{
.pcu_index = PCU_AP_TIMER2_INT,
.gic_index = AP_TIMER2_INT,
.status_index = 52,
.wake_index = 1,
.int_name = "ap_timer2",
.irq_type = IRQ_TYPE_EDGE_RISING,
.wl_type = PM_WL_EVENT_AP_TIMER2,
},
{
.pcu_index = PCU_ICP_PS2AP_INT,
.gic_index = ICP_PS2AP_INT,
.status_index = 53,
.wake_index = 2,
.int_name = "icp_ps_ap",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_ICP_PS2AP,
},
{
.pcu_index = PCU_USB_POWERDWN_UP_INT,
.gic_index = USB_POWERDWN_UP_INT,
.status_index = 6,
.wake_index = 3,
.int_name = "usb_up",
.irq_type = IRQ_TYPE_EDGE_RISING,
.wl_type = PM_WL_EVENT_USB_POWERDWN_UP,
},
{
.pcu_index = PCU_USB_POWERDWN_DOWN_INT,
.gic_index = USB_POWERDWN_DOWN_INT,
.status_index = 7,
.wake_index = 4,
.int_name = "usb_down",
.irq_type = IRQ_TYPE_EDGE_FALLING,
.wl_type = PM_WL_EVENT_USB_POWERDWN_DOWN,
},
{
.pcu_index = PCU_HSIC_POWERDWN_UP_INT,
.gic_index = HSIC_POWERDWN_UP_INT,
.status_index = 8,
.wake_index = 5,
.int_name = "hsic_up",
.irq_type = IRQ_TYPE_EDGE_RISING,
.wl_type = PM_WL_EVENT_HSIC_POWERDWN_UP,
},
{
.pcu_index = PCU_HSIC_POWERDWN_DOWN_INT,
.gic_index = HSIC_POWERDWN_DOWN_INT,
.status_index = 9,
.wake_index = 6,
.int_name = "hsic_down",
.irq_type = IRQ_TYPE_EDGE_FALLING,
.wl_type = PM_WL_EVENT_HSIC_POWERDWN_DOWN,
},
{
.pcu_index = PCU_ICP_M02AP_INT,
.gic_index = ICP_M02AP_INT,
.status_index = 54,
.wake_index = 7,
.int_name = "icp_m0_ap",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_ICP_M02AP,
},
{
.pcu_index = PCU_RTC_ALARM_INT,
.gic_index = RTC_ALARM_INT,
.status_index = 12,
.wake_index = 8,
.int_name = "rtc_alarm",
.irq_type = IRQ_TYPE_LEVEL_LOW,
.wl_type = PM_WL_EVENT_ALARM,
},
{
.pcu_index = PCU_RTC_TIMER_INT,
.gic_index = RTC_TIMER_INT,
.status_index = 13,
.wake_index = 9,
.int_name = "rtc_timer",
.irq_type = IRQ_TYPE_LEVEL_LOW,
.wl_type = PM_WL_EVENT_RTC_TIMER,
},
{
.pcu_index = PCU_KEYPAD_INT,
.gic_index = KEYPAD_INT,
.status_index = 14,
.wake_index = 10,
.int_name = "kpd",
.irq_type = IRQ_TYPE_EDGE_RISING,
.wl_type = PM_WL_EVENT_KEYPAD,
},
{
.pcu_index = PCU_SD1_DATA1_INT,
.gic_index = SD1_DATA1_INT,
.status_index = 15,
.wake_index = 11,
.int_name = "sd1_d1",
.irq_type = IRQ_TYPE_LEVEL_LOW,
.wl_type = PM_WL_EVENT_SD1_DATA1,
},
{
.pcu_index = PCU_EX0_INT,
.gic_index = EX0_INT,
.status_index = 30,
.wake_index = 14,
.int_name = "ext0",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT0,
},
{
.pcu_index = PCU_EX1_INT,
.gic_index = EX1_INT,
.status_index = 31,
.wake_index = 15,
.int_name = "ext1",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT1,
},
{
.pcu_index = PCU_EX2_INT,
.gic_index = EX2_INT,
.status_index = 32,
.wake_index = 16,
.int_name = "ext2",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT2,
},
{
.pcu_index = PCU_EX3_INT,
.gic_index = EX3_INT,
.status_index = 33,
.wake_index = 17,
.int_name = "ext3",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT3,
},
{
.pcu_index = PCU_EX4_INT,
.gic_index = EX4_INT,
.status_index = 34,
.wake_index = 18,
.int_name = "ext4",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT4,
},
{
.pcu_index = PCU_EX5_INT,
.gic_index = EX5_INT,
.status_index = 35,
.wake_index = 19,
.int_name = "ext5",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT5,
},
{
.pcu_index = PCU_EX6_INT,
.gic_index = EX6_INT,
.status_index = 36,
.wake_index = 20,
.int_name = "ext6",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT6,
},
{
.pcu_index = PCU_EX7_INT,
.gic_index = EX7_INT,
.status_index = 37,
.wake_index = 21,
.int_name = "ext7",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT7,
},
{
.pcu_index = PCU_EX8_INT,
.gic_index = EX8IN1_INT,
.status_index = 38,
.wake_index = 22,
.int_name = "ext8",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT8,
},
{
.pcu_index = PCU_EX9_INT,
.gic_index = EX8IN1_INT,
.status_index = 39,
.wake_index = 23,
.int_name = "ext9",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT9,
},
{
.pcu_index = PCU_EX10_INT,
.gic_index = EX8IN1_INT,
.status_index = 40,
.wake_index = 24,
.int_name = "ext10",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT10,
},
{
.pcu_index = PCU_EX11_INT,
.gic_index = EX8IN1_INT,
.status_index = 41,
.wake_index = 25,
.int_name = "ext11",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT11,
},
{
.pcu_index = PCU_EX12_INT,
.gic_index = EX8IN1_INT,
.status_index = 42,
.wake_index = 26,
.int_name = "ext12",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT12,
},
{
.pcu_index = PCU_EX13_INT,
.gic_index = EX8IN1_INT,
.status_index = 43,
.wake_index = 27,
.int_name = "ext13",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT13,
},
{
.pcu_index = PCU_EX14_INT,
.gic_index = EX8IN1_INT,
.status_index = 44,
.wake_index = 28,
.int_name = "ext14",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT14,
},
{
.pcu_index = PCU_EX15_INT,
.gic_index = EX8IN1_INT,
.status_index = 45,
.wake_index = 29,
.int_name = "ext15",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_EXT15,
},
{
.pcu_index = PCU_SD0_DATA1_INT,
.gic_index = SD0_DATA1_INT,
.status_index = 2,
.wake_index = 30,
.int_name = "sd0_d1",
.irq_type = IRQ_TYPE_LEVEL_LOW,
.wl_type = PM_WL_EVENT_SD0_DATA1,
},
{
.pcu_index = PCU_ICP_PHY2AP_INT,
.gic_index = ICP_PHY2AP_INT,
.status_index = 55,
.wake_index = 31,
.int_name = "icp_phy_ap",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = PM_WL_EVENT_ICP_PHY2AP,
},
{
.pcu_index = PCU_GMACPHY_WAKE_INT,
.gic_index = GMACPHY_WAKE_INT,
.status_index = 60,
.wake_index = 0xff,
.int_name = "gmacphy_wake",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = 0xff,
},
{
.pcu_index = PCU_UART0_RXD_INT,
.gic_index = UART0_RXD_INT,
.status_index = 59,
.wake_index = 42,
.int_name = "uart0_rxd",
.irq_type = IRQ_TYPE_EDGE_FALLING,
.wl_type = 0xff,
},
{
.pcu_index = PCU_GMAC_INT,
.gic_index = GMAC_INT,
.status_index = 16,
.wake_index = 0xff,
.int_name = "gmac",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = 0xff,
},
{
.pcu_index = PCU_GMACPHY_INT,
.gic_index = GMACPHY_INT,
.status_index = 61,
.wake_index = 0xff,
.int_name = "gmacphy",
.irq_type = IRQ_TYPE_LEVEL_HIGH,
.wl_type = 0xff,
},
};
static int zx_pcu_get_irqchip_state(struct irq_data *data,
enum irqchip_irq_state which, bool *val)
{
data = data->parent_data;
if (data->chip->irq_get_irqchip_state)
return data->chip->irq_get_irqchip_state(data, which, val);
return -ENOSYS;
}
static int zx_pcu_set_irqchip_state(struct irq_data *data,
enum irqchip_irq_state which, bool val)
{
data = data->parent_data;
if (data->chip->irq_set_irqchip_state)
return data->chip->irq_set_irqchip_state(data, which, val);
return -ENOSYS;
}
static int zx_pcu_nmi_setup(struct irq_data *data)
{
data = data->parent_data;
if (data->chip->irq_nmi_setup)
return data->chip->irq_nmi_setup(data);
return -ENOSYS;
}
static void zx_pcu_nmi_teardown(struct irq_data *data)
{
data = data->parent_data;
if (data->chip->irq_nmi_teardown)
data->chip->irq_nmi_teardown(data);
}
static int zx_pcu_set_wake(struct irq_data *data, unsigned int on)
{
pcu_set_irq_wake(data->hwirq, on);
/* pr_info("irq:%d, onoff:%d", data->hwirq, on);*/
return 0;
}
static void zx_pcu_eoi_irq(struct irq_data *data)
{
pcu_clr_irq_pending(data->hwirq);
irq_chip_eoi_parent(data);
}
static int zx_pcu_set_type(struct irq_data *data, unsigned int type)
{
unsigned int new_type = type;
if(!pcu_set_irq_type(data->hwirq, type))
new_type = IRQ_TYPE_LEVEL_HIGH;
return irq_chip_set_type_parent(data, new_type);
}
static int zx_pcu_set_affinity(struct irq_data *data,
const struct cpumask *dest, bool force)
{
/*
if (data->hwirq == IRQ_ZX298501_AP_TIMER1)
return irq_chip_set_affinity_parent(data, cpumask_of(0), force); // ???
else
*/ return irq_chip_set_affinity_parent(data, dest, force);
}
static struct irq_chip zx_pcu_chip = {
.name = "PCU",
.irq_eoi = zx_pcu_eoi_irq,
.irq_mask = irq_chip_mask_parent,
.irq_unmask = irq_chip_unmask_parent,
.irq_set_wake = zx_pcu_set_wake,
.irq_set_type = zx_pcu_set_type,
.irq_set_affinity = zx_pcu_set_affinity,
.irq_get_irqchip_state = zx_pcu_get_irqchip_state,
.irq_set_irqchip_state = zx_pcu_set_irqchip_state,
.irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
.irq_nmi_setup = zx_pcu_nmi_setup,
.irq_nmi_teardown = zx_pcu_nmi_teardown,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED,
};
static int zx_pcu_domain_translate(struct irq_domain *d,
struct irq_fwspec *fwspec,
unsigned long *hwirq,
unsigned int *type)
{
if (is_of_node(fwspec->fwnode)) {
if (fwspec->param_count != 3)
return -EINVAL;
/* No PPI should point to this domain */
if (fwspec->param[0] != 0)
return -EINVAL;
*hwirq = fwspec->param[1];
*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
return 0;
}
return -EINVAL;
}
static int zx_pcu_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs, void *data)
{
struct irq_fwspec *fwspec = data;
struct irq_fwspec parent_fwspec;
struct zx_pcu_dev *pcu = domain->host_data;
irq_hw_number_t hwirq;
unsigned int i;
if (fwspec->param_count != 3)
return -EINVAL; /* Not GIC compliant */
if (fwspec->param[0] != GIC_SPI)
return -EINVAL; /* No PPI should point to this domain */
hwirq = fwspec->param[1];
if (hwirq >= ZX_IRQ_NUM)
return -EINVAL;
for (i = 0; i < nr_irqs; i++) {
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
&zx_pcu_chip,
(void __force *)pcu->top_reg_base);
}
parent_fwspec = *fwspec;
parent_fwspec.fwnode = domain->parent->fwnode;
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
&parent_fwspec);
}
static const struct irq_domain_ops zx_pcu_domain_ops = {
.translate = zx_pcu_domain_translate,
.alloc = zx_pcu_domain_alloc,
.free = irq_domain_free_irqs_common,
};
static int __init zx_pcu_init(struct device_node *node,
struct device_node *parent)
{
struct irq_domain *parent_domain, *domain;
struct zx_pcu_dev *pcu;
if (!parent) {
pr_err("%pOF: no parent found\n", node);
return -ENODEV;
}
parent_domain = irq_find_host(parent);
if (!parent_domain) {
pr_err("%pOF: unable to obtain parent domain\n", node);
return -ENXIO;
}
pcu = &pcu_dev;
pcu->np = node;
pcu->top_reg_base = of_iomap(node, 0);
WARN(!pcu->top_reg_base, "unable to map top pcu registers\n");
pcu->int_info = zx297520v3_pcu_int_info;
pcu->int_count = ARRAY_SIZE(zx297520v3_pcu_int_info);
pcu_init();
domain = irq_domain_add_hierarchy(parent_domain, 0, ZX_IRQ_NUM,
node, &zx_pcu_domain_ops,
pcu);
if (!domain) {
pr_err("%pOF: failed to allocated domain\n", node);
return -ENOMEM;
}
// set_smp_cross_call();
pm_pcu_init();
return 0;
}
IRQCHIP_DECLARE(zx297520v3_pcu, "zte,zx297520v3-pcu", zx_pcu_init);
/* pcu debug */
#ifdef CONFIG_PM
#define PCU_TOP (pcu_dev.top_reg_base)
#define ARM_AP_CONFIG_REG (PCU_TOP + 0x0)
#define ARM_AP_SLEEP_TIME_REG (PCU_TOP + 4*0x3C)
#define AP_INT_WAKE_DIS_REG (PCU_TOP + 4*0xD)
#define CORE_SWITCH_CONFIG_REG (PCU_TOP + 4*0x2b)
#define M0_INT_WAKE_DIS_REG (PCU_TOP + 4*0xE)
#define PCU_INT_READOUT_REG1 (PCU_TOP + 4*0x1EB)
#define PCU_INT_READOUT_REG2 (PCU_TOP + 4*0x1EC)
#define PCU_INT_READOUT_REG3 (PCU_TOP + 4*0x1ED)
/*ARM_AP_CONFIG_REG*/
#define PCU_SLEEP_MODE (1U << 0)
#define PCU_POWEROFF_MODE (1U << 1)
#define PCU_L2_CLK_GATE (1U << 2) /*1-can turn off*/
#define PCU_SLEEP_2M0 (1U << 3)
#define PCU_SLEEP_DONE_BYPASS (1U << 4)
#define PCU_SW_CONFIG_MASK (1U << 5) /* ????? */
#define PCU_MODE_MASK (0x3U << 0)
/*ARM_AP_SLEEP_TIME_REG*/
#define PCU_AP_SLEEP_TIME_DIS (1U << 31)
/* low power function */
extern unsigned int pm_get_wakesource(void);
/**
* clear pcu sleep mode.
*
*/
void pm_clear_pcu(void)
{
zx_clr_reg(ARM_AP_CONFIG_REG, PCU_MODE_MASK);
}
void pm_pcu_init(void)
{
zx_clr_reg(ARM_AP_CONFIG_REG, PCU_MODE_MASK);
zx_set_reg(ARM_AP_CONFIG_REG, PCU_L2_CLK_GATE);
zx_write_reg(AP_INT_WAKE_DIS_REG, ~(pm_get_wakesource()));
}
void zx_apmgclken_set(unsigned en)
{
unsigned tmp;
if(en){
//set ps_clk_switch=1
tmp = zx_read_reg(CORE_SWITCH_CONFIG_REG);
tmp |= (0x1<<2);
zx_write_reg(CORE_SWITCH_CONFIG_REG, tmp);
} else{
//set ps_clk_switch=0
tmp = zx_read_reg(CORE_SWITCH_CONFIG_REG);
tmp &= ~(0x1<<2);
zx_write_reg(CORE_SWITCH_CONFIG_REG, tmp);
}
}
/**
* config pcu before poweroff
*
*/
void pm_set_pcu_poweroff(u32 sleep_time)
{
zx_set_reg(ARM_AP_CONFIG_REG, PCU_POWEROFF_MODE);
zx_write_reg(ARM_AP_SLEEP_TIME_REG, sleep_time);
}
EXPORT_SYMBOL(pm_set_pcu_poweroff);
/**
* config pcu before sleep
*
*/
void pm_set_pcu_sleep(u32 sleep_time)
{
zx_set_reg(ARM_AP_CONFIG_REG, PCU_SLEEP_MODE);
zx_write_reg(ARM_AP_SLEEP_TIME_REG, sleep_time);
}
/**
* get wakeup setting.
*
*/
unsigned int pcu_get_wakeup_setting(void)
{
return zx_read_reg(AP_INT_WAKE_DIS_REG);
}
/**
* set wakeup enable by gic.
*
*
*/
unsigned int gic_wake_enable[3]=
{
(1<<ICP_PS2AP_INT) |(1<<ICP_M02AP_INT) | (1<<AP_TIMER1_INT) | (1<<EX8IN1_INT),
0,
0
};
extern void show_icp_state(T_RpMsg_CoreID actorID);
void pm_get_wake_cause(void)
{
unsigned int int_status[2];
int i = 0;
int index_found = 0xff;
unsigned int pcu_wake_setting[2];
/* when wake up, the level is high&the value is 0*/
int_status[0] = zx_read_reg(PCU_INT_READOUT_REG1);
int_status[1] = zx_read_reg(PCU_INT_READOUT_REG2);
pcu_wake_setting[0] = zx_read_reg(AP_INT_WAKE_DIS_REG);
pcu_wake_setting[1] = zx_read_reg(M0_INT_WAKE_DIS_REG);
for(i=0; i<ARRAY_SIZE(zx297520v3_pcu_int_info); i++)
{
if (zx297520v3_pcu_int_info[i].wake_index == 0xff)
continue;
if(pcu_wake_setting[0]&BIT(zx297520v3_pcu_int_info[i].wake_index))
continue;
if(int_status[zx297520v3_pcu_int_info[i].status_index/32]&(1<<(zx297520v3_pcu_int_info[i].status_index%32)))
continue;
index_found = i;
break;
}
if(index_found != 0xff)
{
pm_ram_log(" wake: %d [%s]\n", zx297520v3_pcu_int_info[index_found].gic_index, zx297520v3_pcu_int_info[index_found].int_name);
sc_debug_info_record(MODULE_ID_CAP_PM, " wake: %d [%s]\n", zx297520v3_pcu_int_info[index_found].gic_index, zx297520v3_pcu_int_info[index_found].int_name);
if(zx297520v3_pcu_int_info[index_found].gic_index ==ICP_PS2AP_INT) {
show_icp_state(CORE_PS0);
}
pm_ram_log(" pcu int status:0x%x 0x%x\n",int_status[0], int_status[1]);
pm_wl_set_event(pcu_get_wl_index_by_gic(zx297520v3_pcu_int_info[index_found].gic_index));
}
else
{
pm_ram_log(" wake abnormal\n");
pm_ram_log(" pcu int status:0x%x 0x%x\n",int_status[0], int_status[1]);
}
}
static struct wakeup_source *zx_main_ws;
static int zx_pcu_pm_callback(struct notifier_block *nb,
unsigned long action, void *ptr)
{
switch (action) {
case PM_POST_SUSPEND:
__pm_wakeup_event(zx_main_ws, 500);//LYNQ_AUTOSUSPEND add for bug-view-372 by jb.qi on 20241114
break;
default:
return NOTIFY_DONE;
}
return NOTIFY_OK;
}
static int pcu_pm_suspend(void)
{
int ret = 0;
return ret;
}
static void pcu_pm_resume(void)
{
// pcu_get_wake_cause();
}
static struct syscore_ops pcu_pm_syscore_ops = {
.suspend = pcu_pm_suspend,
.resume = pcu_pm_resume,
};
static int pcu_pm_init(void)
{
zx_main_ws = wakeup_source_register(NULL, "zx_main");
if (!zx_main_ws)
return -ENOMEM;
pm_notifier(zx_pcu_pm_callback, 0);
register_syscore_ops(&pcu_pm_syscore_ops);
return 0;
}
core_initcall(pcu_pm_init);
#endif
/* --------------------------------------------------------------------
* extint_8in1
* -------------------------------------------------------------------- */
struct ext8in1_info {
struct irq_domain *domain;
struct regmap *regmap;
int parent_irq;
};
struct ext8in1_info ext8in1_dev = {0};
/*
* return external interrupt number from ex8-ex15,
* return value is 0-7
*/
static unsigned int pcu_get_8in1_int_source(void)
{
unsigned int vector_8in1 = 0;
vector_8in1 = zx_read_reg(pcu_dev.top_reg_base+0x12C);
return (vector_8in1&0x7);
}
/*external int 8-15 need extra clear*/
static void pcu_int_clear_8in1(unsigned int pcu_index)
{
unsigned int vector=0;
if ( (pcu_index >= PCU_EX8_INT)&&(pcu_index <= PCU_EX15_INT) )
{
/*
*in 7510 platform, 8in1 interrupt would be used by different cores.
*when any core installs a new 8in1 interrupt, another core may be
* responding another 8in1 interrupt, so 8in1 interrupt shouldn't be
*cleared. in this case, nothing to be done. but a new problem comes,
* the core install new 8in1 interrupt will receive a fake interrupt.
*/
vector = pcu_get_8in1_int_source();
if (pcu_index != (vector + PCU_EX8_INT) )
return;
PCU_LOCK
zx_write_reg(pcu_dev.top_reg_base+0x128, 0x1);
PCU_UNLOCK
pcu_int_clear(pcu_index);
}
}
static void ext8in1_irq_lock(struct irq_data *data){}
static void ext8in1_irq_sync_unlock(struct irq_data *data){}
static void ext8in1_irq_mask(struct irq_data *data){}
static void ext8in1_irq_unmask(struct irq_data *data){}
static int ext8in1_irq_set_wake(struct irq_data *data, unsigned int on)
{
if (!data)
return -EINVAL;
pcu_set_irq_wake_by_pcu(data->hwirq + PCU_EX8_INT, on);
return 0;
}
static int ext8in1_irq_set_type(struct irq_data *data, unsigned int type)
{
if (!data)
return -EINVAL;
pcu_int_set_type(data->hwirq + PCU_EX8_INT, type);
pcu_int_clear_8in1(data->hwirq + PCU_EX8_INT);
return 0;
}
static struct irq_chip ext8in1_irq_chip =
{
.name = "ext8in1",
.irq_set_wake = ext8in1_irq_set_wake,
.irq_set_type = ext8in1_irq_set_type,
.irq_mask = ext8in1_irq_mask,
.irq_unmask = ext8in1_irq_unmask,
.irq_bus_lock = ext8in1_irq_lock,
.irq_bus_sync_unlock = ext8in1_irq_sync_unlock,
};
static void ext8in1_handle_irq(struct irq_desc *desc)
{
struct ext8in1_info *data = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int virq;
int hwirq, new_hwirq;
chained_irq_enter(chip, desc);
hwirq = pcu_get_8in1_int_source();
while(1) {
pcu_int_clear_8in1(hwirq + PCU_EX8_INT);
virq = irq_find_mapping(data->domain, hwirq);
if (virq > 0)
generic_handle_irq(virq);
new_hwirq = pcu_get_8in1_int_source();
if (hwirq == new_hwirq)
break;
else
hwirq = new_hwirq;
}
chained_irq_exit(chip, desc);
}
extern void mask_irq(struct irq_desc *desc);
extern void unmask_irq(struct irq_desc *desc);
static int ext8in1_irq_resume(struct device *dev)
{
unmask_irq(irq_to_desc(ext8in1_dev.parent_irq));
return 0;
}
static int ext8in1_irq_suspend(struct device *dev)
{
mask_irq(irq_to_desc(ext8in1_dev.parent_irq));
return 0;
}
static int zx_ext8in1_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *parent_np;
struct regmap *regmap;
struct ext8in1_info *data = &ext8in1_dev;
int i;
parent_np = of_parse_phandle(pdev->dev.of_node, "parent-syscon", 0);
if (!parent_np) {
dev_err(&pdev->dev, "Can't get parent-syscon\n");
return -EINVAL;
}
regmap = syscon_node_to_regmap(parent_np);
if (IS_ERR(regmap)) {
of_node_put(parent_np);
return PTR_ERR(regmap);
}
data->regmap = regmap;
data->parent_irq = platform_get_irq(pdev, 0);
if (data->parent_irq <= 0)
return -EPROBE_DEFER;
data->domain = irq_domain_add_linear(np, 8, &irq_domain_simple_ops, NULL);
if (!data->domain)
return -ENODEV;
for (i = EX8_INT; i <= EX15_INT; i++) {
int virq = irq_create_mapping(data->domain, i);
irq_set_chip_and_handler(virq, &ext8in1_irq_chip,
handle_simple_irq);
irq_set_chip_data(virq, data);
}
irq_set_chained_handler_and_data(data->parent_irq,
ext8in1_handle_irq, data);
enable_irq_wake(data->parent_irq);
pr_info("zx_ext8in1 init OK. \n");
return 0;
}
static const struct of_device_id zx_ext8in1_match[] = {
{ .compatible = "zte,zx297520v3-ext8in1" },
{ }
};
static const struct dev_pm_ops ext8in1_irq_pm_ops = {
.resume = ext8in1_irq_resume,
.suspend = ext8in1_irq_suspend,
};
static struct platform_driver zx_ext8in1_driver = {
.probe = zx_ext8in1_probe,
.driver = {
.name = "zx_ext8in1_drv",
.of_match_table = zx_ext8in1_match,
.pm = &ext8in1_irq_pm_ops,
},
};
static int __init zx_ext8in1_driver_init(void)
{
return platform_driver_register(&zx_ext8in1_driver);
}
core_initcall(zx_ext8in1_driver_init);