Blame - upstream/linux-5.10/drivers/tty/serial/zx29_uart.c - T106_eSDK

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xf.li	2f42418	2024-08-20 00:47:34 -0700	[diff] [blame^]	1	/****************************************************************************/
				2	/*
				3	* zx29_uart.c sanchips
				4	*
				5	* (C) Copyright 2003-2007, gaowei
				6	* (C) Copyright 2003-2007, sanchips
				7	* This program is free software; you can redistribute it and/or modify
				8	* it under the terms of the GNU General Public License as published by
				9	* the Free Software Foundation; either version 2 of the License, or
				10	* (at your option) any later version.
				11	*/
				12
				13	/****************************************************************************/
				14	#include <linux/kernel.h>
				15	#include <linux/init.h>
				16	#include <linux/timer.h>
				17	#include <linux/interrupt.h>
				18	#include <linux/module.h>
				19	#include <linux/console.h>
				20	#include <linux/tty.h>
				21	#include <linux/tty_flip.h>
				22	#include <linux/serial.h>
				23	#include <linux/serial_core.h>
				24	#include <linux/platform_device.h>
				25	#include <linux/of.h>
				26	#include <linux/of_irq.h>
				27	#include <linux/io.h>
				28	#include <linux/printk.h>
				29	#include <linux/clk.h>
				30	#include <linux/gpio.h>
				31	#include <linux/delay.h>
				32	#include <linux/dmaengine.h>
				33	#include <linux/dma-mapping.h>
				34	#include <linux/slab.h>
				35	#include <linux/scatterlist.h>
				36	#include <linux/device.h>
				37	#include <linux/ioport.h>
				38	#include <linux/sched/clock.h>
				39	#include <linux/soc/zte/spinlock.h>
				40
				41	#if 0
				42	#include <mach/gpio_def.h>
				43	#include <mach/irqs.h>
				44	#include <mach/board.h>
				45	#include <mach/gpio.h>
				46	#include <mach/debug.h>
				47	#include <mach/iomap.h>
				48	#include <mach/dma.h>
				49	#include <mach/dma_cfg.h>
				50	#endif
				51	//#include <linux/wakelock.h>
				52	#include <linux/kthread.h>
				53	#include <linux/semaphore.h>
				54
				55	#include <linux/dma/zx-dma.h>
				56	//#include "../../dma/zte/zx298501_dma.h"
				57
				58	#include "zx29_uart.h"
				59	#include <linux/soc/zte/rpmsg.h>
				60	#include <linux/soc/sc/drv_idle.h>
				61	#include "pub_debug_info.h"
				62	//#include <linux/soc/zte/pm/drv_idle.h>
				63	//#include <mach/pcu.h>
				64	//#define DEBUG_UART
				65
				66	#ifdef DEBUG_UART
				67	#pragma GCC optimize("O0")
				68	#endif
				69
				70	#define UART_WCLK_NAME "uartclk"
				71	#define UART_APBCLK_NAME "apb_pclk"
				72
				73	#define CONFIG_SERIAL_ZX29_DMA 1
				74
				75
				76	extern bool xp2xp_Ap2CpIsApWakeup(void);
				77	extern int xp2xp_enable_4line(void);
				78
				79	extern signed int zx29_dma_stop(unsigned int channel_id);
				80	extern signed int zx29_dma_get_transfer_num(unsigned int channel_id);
				81
				82
				83
				84	char uart_names[5][12] = {
				85	"zx29_uart.0",
				86	"zx29_uart.1",
				87	"zx29_uart.2",
				88	"zx29_uart.3",
				89	"zx29_uart.4"
				90	};
				91
				92	#if CONFIG_SERIAL_ZX29_DMA
				93	#define ZX29_DMA_BUFFER_SIZE PAGE_SIZE
				94	#define UART_DMA_RX_MAX_COUNT 2
				95	//#define RX_DMA_TIMEOUT (HZ / 10)//60
				96	#define RX_DMA_TIMEOUT (HZ / 100)
				97	#define RX_DMA_WORK 1
				98	struct zx29_sgbuf {
				99	struct scatterlist sg;
				100	dma_addr_t dma_addr;
				101	char *buf;
				102	};
				103
				104	struct zx29_dmarx_data {
				105	struct dma_chan *chan;
				106	struct completion complete;
				107	dma_channel_def rx_def[UART_DMA_RX_MAX_COUNT];
				108	u32 rx_index;
				109	bool use_buf_b;
				110	struct zx29_sgbuf sgbuf_a;
				111	struct zx29_sgbuf sgbuf_b;
				112	dma_cookie_t cookie;
				113	bool running;
				114	atomic_t count;
				115	bool used;
				116	};
				117
				118	struct zx29_dmatx_data {
				119	struct dma_chan *chan;
				120	struct completion complete;
				121	dma_channel_def tx_def;
				122	struct scatterlist sg;
				123	char *buf;
				124	bool queued;
				125	atomic_t count;
				126	};
				127	#define UART_DMA_CYCLE_RX_CONFIG_COUNT 5
				128	struct zx29_dma_cycle_data{
				129	int id;
				130	int flg_enter_th;
				131	int flg_enter_to;
				132	char flg_overrun;
				133	char flg_pe;
				134	char flg_be;
				135	char flg_fe;
				136	char from_resume;
				137	unsigned long cnt_callback_total;
				138	unsigned long cnt_th_total;
				139	int cnt_callback;
				140	int cnt_th;
				141	struct zx29_sgbuf sgbuf[UART_DMA_CYCLE_RX_CONFIG_COUNT];
				142	dma_channel_def rxdef[UART_DMA_CYCLE_RX_CONFIG_COUNT];
				143	};
				144	struct zx29_dma_cycle_data uart_dma_cycle[5];
				145	#endif
				146
				147
				148
				149	#define UART_NUM 5
				150	int g_uart_overrun[5];
				151	ktime_t g_hr_interval;
				152
				153
				154	int g_cons_id_cmdline;
				155	EXPORT_SYMBOL(g_cons_id_cmdline);
				156
				157	#ifdef DEBUG_CONSOLE
				158	#undef DEBUG_CONSOLE
				159	#endif
				160	#define DEBUG_CONSOLE g_cons_id_cmdline
				161	/****************************************************************************/
				162
				163	/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
				164	* name, but it is legally reserved for the 8250 driver. */
				165	#define SERIAL_zx29_MAJOR TTY_MAJOR
				166	#define SERIAL_MINOR_START 64
				167
				168	#define UART_PORT_AUTOBAUD_ON 1
				169	#define UART_PORT_AUTOBAUD_OFF 0
				170	#define UART_PORT_AUTOBAUD_BYTE 2
				171	#define UART_AT_SENDOK_NUM 6
				172	#define UART_AUTOBAUD_LEVEL 5
				173	#define UART_AUTOBAUD_CHECKBYTE 4
				174	#define UART_AUTOBAUD_RATE 115200
				175	#define UART1_AUTOBAUD_RATE 921600
				176
				177
				178	unsigned char uart_port_autobaud_buffer[UART_PORT_AUTOBAUD_BYTE] = {0};
				179	unsigned char uart_port_autobaud_gtflag = 0 ;
				180	unsigned char uart_port_autobaud_suflag = 0 ;
				181	unsigned char g_console_open_flag = 1;
				182
				183
				184	unsigned char UART_AT_send_ok[UART_AT_SENDOK_NUM] =
				185	{
				186	0x0d,0x0a,0x4F,0x4B,0x0d,0x0a
				187	};
				188
				189	unsigned char UART_baud_check[UART_AUTOBAUD_LEVEL][UART_AUTOBAUD_CHECKBYTE]=
				190	{
				191	{0x61,0x74,0x41,0x54},{0x06,0x9e,0x06,0x98},{0x1c,0x80,0x1c,0x00},
				192	{0xe0,0x00,0xe0,0x00},{0x00,0x00,0x00,0x00},
				193	};
				194	unsigned int UART_baud[UART_AUTOBAUD_LEVEL] =
				195	{
				196	115200,57600,38400,19200,9600
				197	};
				198	unsigned int UART_termios_cflag[UART_AUTOBAUD_LEVEL] =
				199	{
				200	B115200,B57600,B38400,B19200,B9600
				201	};
				202
				203	#ifdef CONFIG_SERIAL_CORE_CONSOLE
				204	#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
				205	#else
				206	#define uart_console(port) (0)
				207	#endif
				208
				209	/****************************************************************************/
				210	/*
				211	* Local per-uart structure.
				212	*/
				213	struct zx29_uart_port
				214	{
				215	struct uart_port port;
				216	unsigned int sigs; /* Local copy of line sigs */
				217	unsigned int old_status;
				218	unsigned char imr; /* Local interrupt mask reg mirror */
				219	#if CONFIG_SERIAL_ZX29_DMA
				220	unsigned char dmacr; /* DMA reg*/
				221	#endif
				222	bool rts_state;
				223	bool autorts; /* hardware flow control */
				224	struct clk wclk; / uart work clock */
				225	struct clk busclk; / uart apb clock */
				226	bool autobaud;
				227	bool autobaud_state;
				228	unsigned int baudrate;
				229	bool uartwake;
				230
				231	int irq;
				232	int irq_state;
				233	int rxd_irq;
				234	struct tasklet_struct write_wakeup;
				235	bool rxd_wakeup;
				236	int rxd_int_depth;
				237	bool enter_suspend;
				238	#if CONFIG_SERIAL_ZX29_DMA
				239	/* DMA stuff */
				240	bool using_tx_dma;
				241	bool using_rx_dma;
				242	struct zx29_dmarx_data dmarx;
				243	struct zx29_dmatx_data dmatx;
				244	struct timer_list rx_dma_timer;
				245	struct hrtimer rx_dma_hrtimer;
				246	struct task_struct *dma_compl_th;
				247	struct semaphore sema;
				248	struct semaphore sema_cyclic;
				249	bool port_close;
				250	bool work_state;
				251	size_t pre_pending;
				252	struct zx29_sgbuf *sg2tty;
				253	size_t sg2tty_len;
				254	struct zx29_sgbuf *curr_sg;
				255	int enable_ctsrts;
				256	int enable_wakeup;
				257
				258	struct notifier_block wakeup_notifier;
				259
				260	#endif
				261	//means application decide close and release DMA &wakelock
				262	int app_ctrl;
				263	int sleep_state;
				264	//if app_ctrl is set or using kernel control sleep,set this flag
				265	int uart_power_mode;
				266	};
				267
				268
				269
				270	static struct zx29_uart_port zx29_uart_ports[UART_NUM];
				271
				272	#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
				273	typedef struct __UART_STATIC{
				274	int cnt;
				275	char head[16];
				276	unsigned long long s_time;
				277	int func_step;
				278	unsigned int fr;
				279	unsigned int ris;
				280	}uart_static;
				281	#define STATIC_UART_ID 0
				282	uart_static g_uart_static[256] = {0};
				283	int g_uart_static_cnt = 0;
				284	void test_uart_static(int uart_id, char *buf, int cnt, int steps)
				285	{
				286	if(uart_id != STATIC_UART_ID)
				287	return;
				288	if(buf){
				289	if(cnt >= 16){
				290	strncpy(g_uart_static[g_uart_static_cnt].head, buf, 16);
				291	}else{
				292	memcpy(g_uart_static[g_uart_static_cnt].head, buf, cnt);
				293	}
				294	}
				295	g_uart_static[g_uart_static_cnt].cnt = cnt;
				296	g_uart_static[g_uart_static_cnt].s_time = local_clock();
				297	g_uart_static[g_uart_static_cnt].func_step = steps;
				298	g_uart_static[g_uart_static_cnt].fr = UART_GET_FR(&zx29_uart_ports[uart_id].port);
				299	g_uart_static[g_uart_static_cnt].ris = UART_GET_RIS(&zx29_uart_ports[uart_id].port);
				300
				301	if(++g_uart_static_cnt >= 256)
				302	g_uart_static_cnt = 0;
				303	}
				304
				305
				306
				307
				308	#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
				309	void zx29_uart_stop_rx(struct uart_port *port);
				310
				311	#if CONFIG_SERIAL_ZX29_DMA
				312	static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup);
				313	static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup);
				314	static bool zx29_dma_tx_irq(struct zx29_uart_port *zup);
				315	static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup);
				316	void uart_dma_rx_callback(void *data);
				317	void uart_dma_rx_callback_use_dma_cyclic(void * data);
				318	static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
				319	//u32 pending, bool use_buf_b,
				320	u32 pending, struct zx29_sgbuf *sgbuf,
				321	bool readfifo, unsigned long *flags);
				322	static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup);
				323	static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup);
				324	static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup);
				325	static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup);
				326	static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup);
				327
				328	static void zx29_uart_rx_dma_chars(struct zx29_uart_port zup, unsigned long flags);
				329	dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup);
				330
				331	#if RX_DMA_WORK
				332	static void zx29_uart_rx_timeout_chars(struct zx29_uart_port zup, unsigned long flags);
				333	static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup);
				334
				335	static void zx29_uart_rt_dma(struct zx29_uart_port zup, unsigned long flags);
				336	static void uart_dma_cycle_deinit(struct zx29_uart_port *zup);
				337	#endif
				338	#endif
				339
				340
				341
				342	/*******************************************************************************
				343	* Function: uart_wakeup_callback.
				344	* Description: uart_wakeup_callback.
				345	* Parameters:
				346	* Input:val:means wakeup or sleep notify to other device
				347	*
				348	* Output:v:means devices been called return result
				349	*
				350	* Returns:
				351	*
				352	* Others:
				353	********************************************************************************/
				354	int uart_wakeup_callback(struct notifier_block * nb, unsigned long val, void * v)
				355	{
				356	int call_result = (int )v;
				357	unsigned long flags = 0;
				358	struct zx29_uart_port *zup = container_of(nb, struct zx29_uart_port, wakeup_notifier);
				359
				360	if(!zup \|\| zup->port_close){
				361	*call_result \|= 0;
				362	return 0;
				363	}
				364	struct platform_device *pdev = zup->port.private_data;
				365	raw_spin_lock_irqsave(&zup->port.lock, flags);
				366	if(val == 1){//wakeup
				367	zup->sleep_state = 0;
				368	pm_stay_awake(&pdev->dev);
				369	zx29_uart_rx_dma_chars(zup, &flags);
				370
				371	}else{//sleep
				372	zup->sleep_state = 1;
				373	zx29_uart_stop_rx(&zup->port);
				374	pm_relax(&pdev->dev);
				375
				376	}
				377	*call_result \|= 0;
				378	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				379	return 0;
				380	}
				381
				382	int zx29_get_sleep_state(int uart_index)
				383	{
				384	if(uart_index < 0 \|\| uart_index > 2){
				385	printk("invalid uart index\n");
				386	return -1;
				387	}
				388
				389	return zx29_uart_ports[uart_index].sleep_state;
				390	}
				391	EXPORT_SYMBOL_GPL(zx29_get_sleep_state);
				392
				393	void zx29_set_sleep_state(int state, int uart_index)
				394	{
				395	if(uart_index < 0 \|\| uart_index > 2){
				396	printk("invalid uart index\n");
				397	return ;
				398	}
				399	printk(" uart %d, state change to:%d\n", uart_index, state);
				400	zx29_uart_ports[uart_index].sleep_state = (state ? 1: 0);
				401	}
				402	EXPORT_SYMBOL_GPL(zx29_set_sleep_state);
				403
				404	static ssize_t sleep_state_show(struct device *_dev,
				405	struct device_attribute attr, char buf)
				406	{
				407	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				408	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				409
				410	return sprintf(buf, "\n wakeup_enable = %d\n",zx29_uart_ports[pdev->id].sleep_state);
				411	}
				412
				413	static ssize_t sleep_state_store(struct device *_dev,
				414	struct device_attribute *attr,
				415	const char *buf, size_t count)
				416	{
				417	uint32_t flag = 0;
				418	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				419	struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				420	flag = simple_strtoul(buf, NULL, 16);
				421	//pdata->uart_wakeup_enable = flag;
				422	zx29_uart_ports[pdev->id].sleep_state = (flag ? 1: 0);
				423	return count;
				424	}
				425
				426	DEVICE_ATTR(sleep_state, S_IRUGO \| S_IWUSR, sleep_state_show,
				427	sleep_state_store);
				428	//bool uart_dma_filter_fn (struct dma_chan chan, void param)
				429	//{
				430	// dma_peripheral_id peri_id = (dma_peripheral_id) param;
				431	// if (chan->chan_id == (unsigned int)peri_id){
				432	// printk("uart_dma_filter_fn, peri_id:%d, ok\n", peri_id);
				433	// return true;
				434	// }
				435	// chan->private = param;
				436	//
				437	// return false;
				438	//}
				439	static void zx29_uart_console_putc(struct uart_port *port, int c);
				440	void zx29_uart_putc(struct uart_port *port, int c);
				441
				442	#if CONFIG_SERIAL_ZX29_DMA
				443	void uart_mod_timer(struct zx29_uart_port zup, unsigned long flags)
				444	{
				445	unsigned long t_delay = 0;
				446	t_delay = msecs_to_jiffies(RX_DMA_TIMEOUT);
				447	spin_unlock_irqrestore(&zup->port.lock, *flags);
				448	//printk("uart_mod_timer, delay %d jiffies\n", t_delay);
				449	mod_timer(&(zup->rx_dma_timer), jiffies + t_delay);
				450
				451	spin_lock_irqsave(&zup->port.lock, *flags);
				452	}
				453	#endif
				454	/**
				455	* Show the console_input attribute.
				456	*/
				457	static ssize_t console_input_show(struct device *_dev,
				458	struct device_attribute attr, char buf)
				459	{
				460	return sprintf(buf, "\n console_input = %d\n",g_console_open_flag);
				461	}
				462
				463	/**
				464	* Store the console_input attribure.
				465	* 0: disable console input function,only out put log
				466	* 1: able console input, can input commands
				467	*/
				468	static ssize_t console_input_store(struct device *_dev,
				469	struct device_attribute *attr,
				470	const char *buf, size_t count)
				471	{
				472	uint32_t flag = 0;
				473	flag = simple_strtoul(buf, NULL, 16);
				474	g_console_open_flag = flag;
				475
				476	return count;
				477	}
				478
				479	DEVICE_ATTR(console_input, S_IRUGO \| S_IWUSR, console_input_show,
				480	console_input_store);
				481
				482	static ssize_t ctsrts_input_show(struct device *_dev,
				483	struct device_attribute attr, char buf)
				484	{
				485	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				486	// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				487	if(pdev->id < 0 \|\| pdev->id >= UART_NUM){
				488	printk("ctsrts_input_store, invalid uart id, return error\n");
				489	return 0;
				490	}
				491	// return sprintf(buf, "\n ctsrts_input = %d\n",pdata->uart_ctsrtsuse);
				492	return sprintf(buf, "\n uart %d ctsrts_input = %d\n", pdev->id, zx29_uart_ports[pdev->id].enable_ctsrts);
				493
				494	}
				495
				496	static ssize_t ctsrts_input_store(struct device *_dev,
				497	struct device_attribute *attr,
				498	const char *buf, size_t count)
				499	{
				500	uint32_t flag = 0;
				501	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				502
				503	if(pdev->id != 0){
				504	printk("ctsrts_input_store, invalid uart id, only uart support hardware control\n");
				505	}
				506	flag = simple_strtoul(buf, NULL, 16);
				507	zx29_uart_ports[pdev->id].enable_ctsrts = flag;
				508
				509	return count;
				510	}
				511
				512	DEVICE_ATTR(ctsrts_input, S_IRUGO \| S_IWUSR, ctsrts_input_show,
				513	ctsrts_input_store);
				514
				515	static ssize_t wakeup_enable_show(struct device *_dev,
				516	struct device_attribute attr, char buf)
				517	{
				518	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				519	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				520
				521	return sprintf(buf, "\n wakeup_enable = %d\n",1);
				522	}
				523
				524	static ssize_t wakeup_enable_store(struct device *_dev,
				525	struct device_attribute *attr,
				526	const char *buf, size_t count)
				527	{
				528	uint32_t flag = 0;
				529	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				530	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				531	if(pdev->id != 4){
				532	printk("\nctsrts_input_store, invalid uart id, only lp_uart(uart 4) support wakeup\n");
				533	}
				534	flag = simple_strtoul(buf, NULL, 16);
				535	zx29_uart_ports[pdev->id].enable_wakeup = flag;
				536
				537	return count;
				538	}
				539
				540	DEVICE_ATTR(wakeup_enable, S_IRUGO \| S_IWUSR, wakeup_enable_show,
				541	wakeup_enable_store);
				542
				543	static ssize_t app_ctrl_show(struct device *_dev,
				544	struct device_attribute attr, char buf)
				545	{
				546	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				547	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				548
				549	return sprintf(buf, "%d\n",zx29_uart_ports[pdev->id].app_ctrl);
				550	}
				551
				552	static ssize_t app_ctrl_store(struct device *_dev,
				553	struct device_attribute *attr,
				554	const char *buf, size_t count)
				555	{
				556	uint32_t flag = 0;
				557	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				558	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				559	flag = simple_strtoul(buf, NULL, 16);
				560	// pdata->uart_wakeup_enable = flag;
				561	zx29_uart_ports[pdev->id].app_ctrl = (flag == 0) ? 0 : 1;
				562
				563	return count;
				564	}
				565	DEVICE_ATTR(app_ctrl, S_IRUGO \| S_IWUSR, app_ctrl_show,
				566	app_ctrl_store);
				567
				568	int rxd_wake_cnt = 0;
				569	static ssize_t statics_show(struct device *_dev,
				570	struct device_attribute attr, char buf)
				571	{
				572	struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
				573	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				574
				575	return sprintf(buf, "\n RX:%u,TX:%u,OE:%u,brk:%u,FE:%u,PE:%u ,rxd_wake_cnt:%d\n",
				576	zx29_uart_ports[pdev->id].port.icount.rx,
				577	zx29_uart_ports[pdev->id].port.icount.tx,
				578	zx29_uart_ports[pdev->id].port.icount.overrun,
				579	zx29_uart_ports[pdev->id].port.icount.brk,
				580	zx29_uart_ports[pdev->id].port.icount.frame,
				581	zx29_uart_ports[pdev->id].port.icount.parity,
				582	rxd_wake_cnt
				583	);
				584	}
				585	DEVICE_ATTR(statics, S_IRUGO, statics_show, NULL);
				586	#define VEHICLE_USE_ONE_UART_LOG 1
				587	#if VEHICLE_USE_ONE_UART_LOG
				588	#define ICP_CORE_ID_PS CORE_PS0
				589	#define ICP_CORE_ID_CAP 1
				590	#define ICP_CHANNEL_CONSOLE_UART 7
				591	#define ICP_MSG_LEN_CONSOLE_UART 2
				592	#define ICP_BUFFERSIZE_CONSOLE_TOGGLE 16
				593	#define SYMB_PS_CORE_ID ICP_CORE_ID_PS
				594	#define SYMB_CAP_CORE_ID ICP_CORE_ID_CAP
				595	#define SYMB_WHAT_CORE_ID 3
				596	#define ENABLE_CURRENT_CONSOLE_UART 1
				597	#define DISABLE_CURRENT_CONSOLE_UART 0
				598	#define ENABLE_TOGGLE 1
				599	#define DISABLE_TOGGLE 0
				600	unsigned char g_core_id_occupy_uart = 0;
				601	unsigned char g_cap_uart_toggle = 0;
				602	static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id);
				603	static void restart_current_cons_uart(void)
				604	{
				605	struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
				606	struct uart_port *port = &zup->port;
				607	enable_irq(port->irq);
				608	g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
				609	spin_lock(&zup->port.lock);
				610	tasklet_schedule(&zup->write_wakeup);
				611	spin_unlock(&zup->port.lock);
				612	}
				613	static void forbid_current_cons_uart(void)
				614	{
				615	struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
				616	struct uart_port *port = &zup->port;
				617	disable_irq(port->irq);
				618	g_core_id_occupy_uart = SYMB_PS_CORE_ID;
				619	}
				620	static void process_ps2cap_rpmsg(char *arr)
				621	{
				622	if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == ENABLE_CURRENT_CONSOLE_UART)){
				623	restart_current_cons_uart();
				624	}else if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == DISABLE_CURRENT_CONSOLE_UART)){
				625	printk("current console uart not enable.\n");
				626	g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
				627	}else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_PS_CORE_ID)){
				628	g_core_id_occupy_uart = SYMB_PS_CORE_ID;
				629	forbid_current_cons_uart();
				630	}else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_CAP_CORE_ID)){
				631	g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
				632	}
				633	else{
				634	printk("%s error!!\n",__func__);
				635	}
				636	}
				637	static void icp_callback_ps2cap(void *buf, unsigned int len)
				638	{
				639	char *arr_ps2cap;
				640	if (len==0){
				641	printk("%s empty.\n", __func__);
				642	return ;
				643	}
				644	arr_ps2cap = (char *)buf;
				645	process_ps2cap_rpmsg(arr_ps2cap);
				646	}
				647	static void echo_to_change_other_uart(uint32_t val)
				648	{
				649	int ret;
				650	if(val > ENABLE_TOGGLE)
				651	{
				652	printk("echo para error!!!\n");
				653	return;
				654	}
				655	char arr[2] = {0};
				656	arr[0] = SYMB_PS_CORE_ID;
				657	arr[1] = val;
				658	T_RpMsg_Msg icp_msg;
				659	icp_msg.coreID = CORE_PS0;
				660	icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
				661	icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
				662	icp_msg.buf = arr;
				663	icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
				664	ret = rpmsgWrite(&icp_msg);
				665	if(ret == 0){
				666	if(val == ENABLE_TOGGLE)
				667	g_core_id_occupy_uart = SYMB_PS_CORE_ID;
				668	else if(val == DISABLE_TOGGLE)
				669	g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
				670	}else
				671	printk("echo_to_change_ohter_uart fail.\n");
				672	}
				673	static ssize_t console_uart_toggle_show(struct device *_dev,
				674	struct device_attribute attr, char buf)
				675	{
				676	return sprintf(buf, "\n console_uart_toggle_show %d. \n", g_cap_uart_toggle);
				677	}
				678	static ssize_t console_uart_toggle_store(struct device *_dev,
				679	struct device_attribute *attr,
				680	const char *buf, size_t count)
				681	{
				682	uint32_t flag = 0;
				683	flag = simple_strtoul(buf, NULL, 16);
				684	if(flag == ENABLE_TOGGLE){
				685	g_cap_uart_toggle = 1;
				686	forbid_current_cons_uart();
				687	echo_to_change_other_uart(flag);
				688	}else if(flag == DISABLE_TOGGLE){
				689	g_cap_uart_toggle = 0;
				690	g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
				691	}
				692	return count;
				693	}
				694	DEVICE_ATTR(console_uart_toggle, S_IRUGO \| S_IWUSR, console_uart_toggle_show,
				695	console_uart_toggle_store);
				696	static void notify_occupy_uart_coreid_to_other(void)
				697	{
				698	char arr[2] = {0};
				699	arr[0] = SYMB_WHAT_CORE_ID;
				700	arr[1] = g_core_id_occupy_uart;
				701	T_RpMsg_Msg icp_msg;
				702	icp_msg.coreID = CORE_AP;
				703	icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
				704	icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
				705	icp_msg.buf = arr;
				706	icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
				707	rpmsgWrite(&icp_msg);
				708	}
				709	static ssize_t coreid_occupy_uart_show(struct device *_dev,
				710	struct device_attribute attr, char buf)
				711	{
				712	return sprintf(buf, "\n core %d occupy cons uart now! \n",g_core_id_occupy_uart);
				713	}
				714	static ssize_t coreid_occupy_uart_store(struct device *_dev,
				715	struct device_attribute *attr,
				716	const char *buf, size_t count)
				717	{
				718	uint32_t flag = 0;
				719	flag = simple_strtoul(buf, NULL, 16);
				720	g_core_id_occupy_uart = flag;
				721	if(flag == SYMB_CAP_CORE_ID){
				722	g_cap_uart_toggle = 0;
				723	}else if(SYMB_PS_CORE_ID){
				724	g_cap_uart_toggle = 1;
				725	}
				726	return count;
				727	}
				728	DEVICE_ATTR(coreid_occupy_uart, S_IRUGO \| S_IWUSR, coreid_occupy_uart_show,
				729	coreid_occupy_uart_store);
				730	#endif
				731
				732	//extern int (*pm_callback_fn)(void);
				733	#ifdef CONFIG_CPU_IDLE
				734	typedef int (*pm_callback_fn)(void);
				735	extern int zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb);
				736
				737	extern void disable_irq_nosync(unsigned int irq);
				738	extern void enable_irq(unsigned int irq);
				739
				740	void uart_rxd_int_disable(struct uart_port *port)
				741	{
				742	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				743	zup->rxd_int_depth++;
				744	}
				745	EXPORT_SYMBOL(uart_rxd_int_disable);
				746
				747	int uart_0_pm_enter(void)
				748	{
				749	struct zx29_uart_port *zup = &zx29_uart_ports[0];
				750
				751	//zDrvInt_UnmaskIrq(UART0_RXD_INT);
				752	if(zup->irq_state == 0 \|\| zup->imr== 0)
				753	return 0;
				754
				755	//pcu_int_clear(PCU_UART0_RXD_INT);
				756	if(!zup->rxd_int_depth){
				757	//enable_irq(UART0_RXD_INT);
				758	zup->rxd_int_depth++;
				759	}
				760	return 0;
				761	}
				762
				763	int uart_0_pm_exit(void)
				764	{
				765
				766	return 0;
				767	}
				768	#endif
				769	/****************************************************************************/
				770
				771	static int zx29_sgbuf_init(struct dma_chan chan, struct zx29_sgbuf sg,
				772	enum dma_data_direction dir)
				773	{
				774	dma_addr_t dma_addr;
				775
				776	sg->buf = dma_alloc_coherent(chan->device->dev,
				777	ZX29_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
				778	if (!sg->buf){
				779	printk("zx29_sgbuf_init fail, no mem\n");
				780	return -ENOMEM;
				781	}
				782	sg_init_table(&sg->sg, 1);
				783	sg_set_page(&sg->sg, phys_to_page(dma_addr),
				784	ZX29_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
				785	sg_dma_address(&sg->sg) = dma_addr;
				786	sg_dma_len(&sg->sg) = ZX29_DMA_BUFFER_SIZE;
				787	sg->dma_addr = dma_addr;
				788	return 0;
				789	}
				790
				791	static void zx29_sgbuf_free(struct dma_chan chan, struct zx29_sgbuf sg,
				792	enum dma_data_direction dir)
				793	{
				794	if (sg->buf) {
				795	dma_free_coherent(chan->device->dev,
				796	ZX29_DMA_BUFFER_SIZE, sg->buf,
				797	sg_dma_address(&sg->sg));
				798	sg->dma_addr = NULL;
				799	}
				800	}
				801
				802
				803	/****************************************************************************/
				804	static unsigned int zx29_uart_tx_empty(struct uart_port *port)
				805	{
				806	return (UART_GET_FR(port)&(UART_FR_TXBUSY\|UART_FR_TXFF)) ? 0 : TIOCSER_TEMT;
				807	}
				808
				809	/****************************************************************************/
				810	static void zx29_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
				811	{
				812	unsigned int control = 0;
				813	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				814	zup->sigs = mctrl;
				815	control = UART_GET_CR(&zup->port);
				816	if(mctrl & TIOCM_DTR)
				817	control \|= UART_CR_DTR;
				818	else
				819	control &= ~ UART_CR_DTR;
				820
				821	if(mctrl & TIOCM_RTS)
				822	control \|= UART_CR_RTS;
				823	else
				824	control &= ~UART_CR_RTS;
				825
				826	if(mctrl & TIOCM_LOOP)
				827	control \|= UART_CR_LBE;
				828	else
				829	control &= ~UART_CR_LBE;
				830
				831	/* We need to disable auto-RTS if we want to turn RTS off */
				832	if (zup->autorts) {
				833	if (mctrl & TIOCM_RTS)
				834	control \|= UART_CR_RTSEN;
				835	else
				836	control &= ~UART_CR_RTSEN;
				837	}
				838	UART_PUT_CR(port, control);
				839	}
				840
				841	/****************************************************************************/
				842	static unsigned int zx29_uart_get_mctrl(struct uart_port *port)
				843	{
				844	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				845	unsigned int mctrl = 0;
				846	unsigned int uart_flag = 0;
				847
				848	uart_flag = UART_GET_FR(port);
				849
				850	mctrl = (uart_flag&UART_FR_CTS) ?TIOCM_CTS : 0;
				851	mctrl \|= (zup->sigs & TIOCM_RTS);
				852	mctrl \|= (uart_flag&UART_FR_DCD) ? TIOCM_CD : 0;
				853	mctrl \|= (uart_flag&UART_FR_DSR) ? TIOCM_DSR : 0;
				854	mctrl \|= (uart_flag&UART_FR_RI) ? TIOCM_RI : 0;
				855
				856	return mctrl;
				857	}
				858
				859	/****************************************************************************/
				860	static void zx29_uart_start_tx(struct uart_port *port)
				861	{
				862	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				863	unsigned int control = 0;
				864	unsigned int reg_bak[10] = {0};
				865	struct circ_buf *xmit = &zup->port.state->xmit;
				866	int count = 0;
				867	#if VEHICLE_USE_ONE_UART_LOG
				868	if((port->line == DEBUG_CONSOLE))
				869	{
				870	if(g_core_id_occupy_uart == SYMB_PS_CORE_ID){
				871	#if 1
				872	count = uart_circ_chars_pending(xmit);
				873	while(count-- > 0)
				874	{
				875	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
				876	if (uart_circ_empty(xmit))
				877	break;
				878	}
				879	#endif
				880	return;
				881	}
				882	count = uart_circ_chars_pending(xmit);
				883	while(count-- > 0)
				884	{
				885	zx29_uart_console_putc(&zup->port, xmit->buf[xmit->tail]);
				886	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
				887	zup->port.icount.tx++;
				888	if (uart_circ_empty(xmit)){
				889	break;
				890	}
				891	}
				892
				893	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
				894	{
				895	spin_lock(&zup->port.lock);
				896	tasklet_schedule(&zup->write_wakeup);
				897	spin_unlock(&zup->port.lock);
				898	return;
				899	}
				900	return;
				901	}
				902	else
				903	#endif
				904	{
				905	if(!(UART_GET_RIS(port)&UART_TXIS) && (UART_GET_FR(port) & UART_FR_TXFE))
				906	{
				907	if(!(UART_GET_RIS(port)&UART_TXIS))
				908	{
				909	count = uart_circ_chars_pending(xmit);
				910	if(count >= zup->port.fifosize)
				911	count = 15;//sent data more than TX ifls, TXIS will coming soon
				912	if(count != 0){
				913	do {
				914	zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
				915	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
				916	zup->port.icount.tx++;
				917	if (uart_circ_empty(xmit) \|\| (UART_GET_RIS(port)&UART_TXIS))
				918	break;
				919	} while (--count > 0);
				920	}
				921	}
				922
				923	}
				924	}
				925	#if CONFIG_SERIAL_ZX29_DMA
				926	if(!uart_console(port))
				927	{
				928	if (!zx29_dma_tx_start(zup))
				929	{
				930	zup->imr \|= UART_TXIM;
				931	UART_PUT_IMSC(port, zup->imr);
				932	if(!(UART_GET_RIS(port)&UART_TXIS)){
				933	if((UART_GET_FR(port) & UART_FR_TXFF))
				934	return;
				935	count = uart_circ_chars_pending(xmit);
				936	while (count > 0) {
				937	UART_PUT_CHAR(&zup->port, xmit->buf[xmit->tail]);
				938	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
				939	zup->port.icount.tx++;
				940	if (uart_circ_empty(xmit) \|\| (UART_GET_RIS(port)&UART_TXIS) \|\|
				941	(UART_GET_FR(port) & UART_FR_TXFF))
				942	break;
				943	}
				944	}
				945	}
				946	}
				947	else
				948	{
				949	zup->imr \|= UART_TXIM;
				950	UART_PUT_IMSC(port, zup->imr);
				951	}
				952	#else
				953	zup->imr \|= UART_TXIM;
				954	UART_PUT_IMSC(port, zup->imr);
				955	#endif
				956	}
				957
				958	static void uart_write_wakeup_task(unsigned long _port)
				959	{
				960	struct uart_port port = (void )_port;
				961	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				962	struct platform_device *pdev=port->private_data;
				963	//printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
				964
				965	if(zup->rxd_wakeup){
				966	//rxd wake
				967	printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
				968	pm_wakeup_dev_event(&pdev->dev, 5000, false);
				969	disable_irq(zup->rxd_irq);
				970	zup->rxd_wakeup = false;
				971	} else {
				972	uart_write_wakeup(port);
				973	}
				974
				975	}
				976
				977	#if CONFIG_SERIAL_ZX29_DMA
				978	int dma_complete_thread_use_dma_cyclic(void *ptr)
				979	{
				980	unsigned long flags;
				981	struct zx29_uart_port zup = (struct zx29_uart_port )ptr;
				982	size_t pending;
				983	int dma_count = 0;
				984	struct device *dev = NULL;
				985	dev = zup->dmarx.chan->device->dev;
				986	int uart_id = zup->port.line;
				987	while(down_interruptible(&zup->sema_cyclic) == 0)
				988	{
				989	if(zup->port_close \|\| !uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th].dma_addr)
				990	break;
				991	spin_lock_irqsave(&zup->port.lock, flags);
				992	uart_dma_cycle[uart_id].cnt_th_total++;
				993	uart_dma_cycle[uart_id].cnt_th++;
				994	zup->sg2tty = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
				995	zup->sg2tty_len = 4096;
				996	pending = zup->sg2tty_len;
				997	if(uart_dma_cycle[uart_id].flg_be \|\| uart_dma_cycle[uart_id].flg_fe\|\| uart_dma_cycle[uart_id].flg_pe){
				998	printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
				999	zup->port.icount.brk,zup->port.icount.parity);
				1000	uart_dma_cycle[uart_id].flg_be = 0;
				1001	uart_dma_cycle[uart_id].flg_fe = 0;
				1002	uart_dma_cycle[uart_id].flg_pe = 0;
				1003	}
				1004	dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
				1005	spin_unlock_irqrestore(&zup->port.lock, flags);
				1006	dma_count = tty_insert_flip_string(&zup->port.state->port,
				1007	zup->sg2tty->buf, pending);
				1008	tty_flip_buffer_push(&zup->port.state->port);
				1009	spin_lock_irqsave(&zup->port.lock, flags);
				1010	dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
				1011	zup->sg2tty = NULL;
				1012	zup->sg2tty_len = 0;
				1013	zup->port.icount.rx += dma_count;
				1014	if (dma_count < pending)
				1015	dev_info(zup->port.dev,
				1016	"couldn't insert all characters (TTY is full?)\n");
				1017	uart_dma_cycle[uart_id].flg_enter_th = (uart_dma_cycle[uart_id].flg_enter_th+1)%UART_DMA_CYCLE_RX_CONFIG_COUNT;
				1018	uart_dma_cycle[uart_id].cnt_callback--;
				1019	if(!hrtimer_active(&zup->rx_dma_hrtimer))
				1020	hrtimer_restart(&zup->rx_dma_hrtimer);
				1021	spin_unlock_irqrestore(&zup->port.lock, flags);
				1022	}
				1023	return 0;
				1024	}
				1025	int dma_complete_thread(void *ptr)
				1026	{
				1027	unsigned long flags;
				1028	struct zx29_uart_port zup = (struct zx29_uart_port )ptr;
				1029
				1030	size_t pending;
				1031	struct dma_tx_state state;
				1032	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				1033	struct dma_chan *rxchan = dmarx->chan;
				1034	bool lastbuf;
				1035	int dma_count = 0;
				1036	struct zx29_sgbuf *sgbuf = NULL;
				1037	struct device *dev = NULL;
				1038	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				1039	dev = zup->dmarx.chan->device->dev;
				1040
				1041	while(down_interruptible(&zup->sema) == 0)
				1042	{
				1043	if(zup->port_close)
				1044	break;
				1045	spin_lock_irqsave(&zup->port.lock, flags);
				1046	// tty = zup->port.state->port.tty;
				1047	if(!zup->sg2tty)
				1048	panic("dma_complete_thread, buffer 2 tty is invalid\n");
				1049	// dev = zup->dmarx.chan->device->dev;
				1050	pending = zup->sg2tty_len;
				1051	if(zx29_dma_rx_running(zup)){
				1052
				1053	test_uart_static(zup->port.line, NULL, 0, 10);
				1054	//uart_mod_timer(zup, &flags);
				1055	if(!hrtimer_active(&zup->rx_dma_hrtimer))
				1056	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				1057	}
				1058	/* Pick everything from the DMA first */
				1059	if (pending) {
				1060	/* Sync in buffer */
				1061	dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
				1062	//BUG();
				1063
				1064	spin_unlock_irqrestore(&zup->port.lock, flags);
				1065	dma_count = tty_insert_flip_string(&zup->port.state->port,
				1066	zup->sg2tty->buf, pending);
				1067	test_uart_static(zup->port.line, zup->sg2tty->buf, pending, 11);
				1068	tty_flip_buffer_push(&zup->port.state->port);
				1069
				1070	spin_lock_irqsave(&zup->port.lock, flags);
				1071	/* Return buffer to device */
				1072	dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
				1073
				1074	zup->sg2tty = NULL;
				1075	zup->sg2tty_len = 0;
				1076	zup->port.icount.rx += dma_count;
				1077
				1078	//if(zup->port.line == 0)
				1079	//printk("yanming dma_complete_thread, dma2tty:%d\n", dma_count);
				1080	if (dma_count < pending){
				1081	sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d couldn't insert all characters \n",zup->port.line);
				1082	dev_info(zup->port.dev,
				1083	"couldn't insert all characters (TTY is full?)\n");
				1084	}
				1085
				1086
				1087	}
				1088	#if 0
				1089	zup->work_state = false;
				1090	zup->pre_pending = 0;
				1091	zup->imr \|= UART_RXIM;
				1092	UART_PUT_IMSC(&zup->port, zup->imr);
				1093	#endif
				1094	spin_unlock_irqrestore(&zup->port.lock, flags);
				1095	}
				1096
				1097	return 0;
				1098	}
				1099	#endif
				1100
				1101	/****************************************************************************/
				1102	static void zx29_uart_stop_tx(struct uart_port *port)
				1103	{
				1104	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				1105	zup->imr &= ~UART_TXIM;
				1106	UART_PUT_IMSC(port, zup->imr);
				1107	#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
				1108	if((port->line == DEBUG_CONSOLE) && uart_tx_stopped(port))
				1109	{
				1110	//uart_write_wakeup(port);
				1111	tasklet_schedule(&zup->write_wakeup);
				1112	}
				1113	#endif
				1114
				1115	#if CONFIG_SERIAL_ZX29_DMA
				1116	zx29_dma_tx_stop(zup);
				1117	#endif
				1118
				1119	zx_cpuidle_set_free(IDLE_FLAG_UART);
				1120
				1121	}
				1122
				1123	/****************************************************************************/
				1124	void zx29_uart_stop_rx(struct uart_port *port)
				1125	{
				1126	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				1127
				1128	zup->imr &= ~(UART_RXIM\|UART_RTIM\|UART_FEIM\|UART_PEIM\|UART_BEIM\|UART_OEIM);
				1129	UART_PUT_IMSC(port, zup->imr);
				1130	#if CONFIG_SERIAL_ZX29_DMA
				1131	zx29_dma_rx_stop(zup);
				1132	#endif
				1133	}
				1134
				1135	/****************************************************************************/
				1136	static void zx29_uart_break_ctl(struct uart_port *port, int break_state)
				1137	{
				1138	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				1139	unsigned long flags;
				1140	unsigned int lcr_h;
				1141	spin_lock_irqsave(&zup->port.lock, flags);
				1142	lcr_h = UART_GET_LCRH(port);
				1143	if (break_state == -1)
				1144	lcr_h \|= UART_LCRH_BRK;
				1145	else
				1146	lcr_h &= ~UART_LCRH_BRK;
				1147	UART_PUT_LCRH(port, lcr_h);
				1148	spin_unlock_irqrestore(&zup->port.lock, flags);
				1149	}
				1150
				1151	/****************************************************************************/
				1152	static void zx29_uart_enable_ms(struct uart_port *port)
				1153	{
				1154	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				1155	zup->imr \|= UART_RIMIM\|UART_CTSMIM\|UART_DCDMIM\|UART_DSRMIM;
				1156	UART_PUT_IMSC(port, zup->imr);
				1157	}
				1158
				1159	/****************************************************************************/
				1160	/*--------------------------------------------------------------------
				1161	* Reads up to 256 characters from the FIFO or until it's empty and
				1162	* inserts them into the TTY layer. Returns the number of characters
				1163	* read from the FIFO.
				1164	--------------------------------------------------------------------*/
				1165	static int zx29_uart_fifo_to_tty(struct zx29_uart_port *zup)
				1166	{
				1167	struct uart_port *port = &zup->port;
				1168	u32 status, ch, i = 0;
				1169	unsigned int flag, max_count = 256;
				1170	int fifotaken = 0;
				1171	u8 uart_poll_char[16] ={0};
				1172
				1173	while (max_count--) {
				1174	status = UART_GET_FR(port);
				1175	if (status & UART_FR_RXFE)
				1176	break;
				1177
				1178	/* Take chars from the FIFO and update status */
				1179	ch = UART_GET_CHAR(port) \| UART_DUMMY_DR_RX;
				1180
				1181	#if 0
				1182	if(g_console_open_flag == 0 &&
				1183	port->line == DEBUG_CONSOLE){
				1184	if((ch&0xff) == 't'){
				1185	memset(uart_poll_char, 0, sizeof(uart_poll_char));
				1186	uart_poll_char[0] = 't';
				1187	i = 0;
				1188	printk("ch = %c i = %d\n",ch,i);
				1189	}else if ((ch&0xff) == 'y' && (i == 1)){
				1190	uart_poll_char[1] = 'y';
				1191	printk("ch = %c i = %d\n",ch,i);
				1192	}else if ((ch&0xff) == 'o' && (i == 2)){
				1193	uart_poll_char[2] = 'o';
				1194	printk("ch = %c i = %d\n",ch,i);
				1195	}else if ((ch&0xff) == 'p' && (i == 3)){
				1196	uart_poll_char[3] = 'p';
				1197	printk("ch = %c i = %d\n",ch,i);
				1198
				1199	}else if ((ch&0xff) == 'e' && (i == 4)){
				1200	uart_poll_char[4] = 'e';
				1201	printk("ch = %c i = %d\n",ch,i);
				1202
				1203	}else if ((ch&0xff) == 'n' && (i == 5)){
				1204	uart_poll_char[5] = 'n';
				1205	printk("ch = %c i = %d\n",ch,i);
				1206	g_console_open_flag = 1;
				1207	printk("ch = %c i = %d,g_console_open_flag:%d\n",ch,i,g_console_open_flag);
				1208	}else {
				1209	i = 10;
				1210	}
				1211	i++;
				1212	}
				1213	#endif
				1214	flag = TTY_NORMAL;
				1215	if(zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
				1216	{
				1217	if(zup->port.icount.rx < UART_PORT_AUTOBAUD_BYTE)
				1218	{
				1219	uart_port_autobaud_buffer[zup->port.icount.rx] = ch;
				1220	}
				1221	else
				1222	{
				1223	uart_port_autobaud_gtflag = 1 ;
				1224	}
				1225	}
				1226	zup->port.icount.rx++;
				1227	if(zup->autobaud_state == UART_PORT_AUTOBAUD_OFF)
				1228	{
				1229	if(fifotaken < 16){
				1230	uart_poll_char[fifotaken] = ch & 0xFF;
				1231	}
				1232	fifotaken++;
				1233
				1234	if (unlikely(ch & UART_DR_ERROR)) {
				1235	if (ch & UART_DR_BE) {
				1236	ch &= ~(UART_DR_FE \| UART_DR_PE);
				1237	zup->port.icount.brk++;
				1238	if (uart_handle_break(&zup->port))
				1239	continue;
				1240	} else if (ch & UART_DR_PE)
				1241	zup->port.icount.parity++;
				1242	else if (ch & UART_DR_FE)
				1243	zup->port.icount.frame++;
				1244	else if (ch & UART_DR_OE){
				1245	zup->port.icount.overrun++;
				1246	//if(!uart_console(&zup->port))
				1247	// BUG_ON(1);
				1248	}
				1249	ch &= zup->port.read_status_mask;
				1250
				1251	if (ch & UART_DR_BE)
				1252	flag = TTY_BREAK;
				1253	else if (ch & UART_DR_PE)
				1254	flag = TTY_PARITY;
				1255	else if (ch & UART_DR_FE)
				1256	flag = TTY_FRAME;
				1257	}
				1258
				1259	if (uart_handle_sysrq_char(&zup->port, ch & 255))
				1260	continue;
				1261	if(g_console_open_flag \|\| port->line != DEBUG_CONSOLE){
				1262	uart_insert_char(&zup->port, ch, UART_DR_OE, ch, flag);
				1263	}
				1264	}
				1265	}
				1266
				1267	test_uart_static(zup->port.line, uart_poll_char, fifotaken, 3);
				1268
				1269	return fifotaken;
				1270	}
				1271
				1272	/****************************************************************************/
				1273	static void zx29_uart_rx_chars(struct zx29_uart_port *zup)
				1274	{
				1275	unsigned long flags;
				1276
				1277	//struct tty_struct *tty = zup->port.state->port.tty;
				1278
				1279	zx29_uart_fifo_to_tty(zup);
				1280	spin_unlock(&zup->port.lock);
				1281
				1282	tty_flip_buffer_push(&zup->port.state->port);
				1283
				1284	#if CONFIG_SERIAL_ZX29_DMA
				1285	if(!uart_console(&zup->port)){//console doesn't use dma rcv data
				1286	if (zx29_dma_rx_available(zup)) {
				1287	if (zx29_dma_rx_trigger_dma(zup)) {
				1288	dev_dbg(zup->port.dev, "could not trigger RX DMA job "
				1289	"fall back to interrupt mode again\n");
				1290	zup->imr \|= UART_RXIM;
				1291	} else{
				1292	zup->imr &= ~UART_RXIM;
				1293	}
				1294	UART_PUT_IMSC(&zup->port,zup->imr);
				1295	}
				1296	}
				1297	#endif
				1298	RX_END:
				1299	spin_lock(&zup->port.lock);
				1300
				1301	}
				1302
				1303	/****************************************************************************/
				1304	static void zx29_uart_tx_chars(struct zx29_uart_port *zup)
				1305	{
				1306	struct circ_buf *xmit = &zup->port.state->xmit;
				1307	unsigned long flags;
				1308	int count;
				1309
				1310	if (zup->port.x_char) {
				1311	UART_PUT_CHAR(&zup->port, zup->port.x_char);
				1312	zup->port.icount.tx++;
				1313	zup->port.x_char = 0;
				1314	return;
				1315	}
				1316	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(&zup->port)) {
				1317	zx29_uart_stop_tx(&zup->port);
				1318	return;
				1319	}
				1320	#if CONFIG_SERIAL_ZX29_DMA
				1321	/* If we are using DMA mode, try to send some characters. */
				1322	if(!uart_console(&(zup->port)))
				1323	{
				1324	if (zx29_dma_tx_irq(zup))
				1325	return;
				1326	}
				1327	#endif
				1328	count = zup->port.fifosize >> 1;
				1329	do {
				1330	zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
				1331	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
				1332	zup->port.icount.tx++;
				1333	if (uart_circ_empty(xmit))
				1334	break;
				1335	} while (--count > 0);
				1336
				1337	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
				1338	{
				1339	spin_unlock(&zup->port.lock);
				1340	//uart_write_wakeup(&zup->port);
				1341	tasklet_schedule(&zup->write_wakeup);
				1342	spin_lock(&zup->port.lock);
				1343	}
				1344
				1345	if (uart_circ_empty(xmit))
				1346	zx29_uart_stop_tx(&zup->port);
				1347	}
				1348
				1349	#if CONFIG_SERIAL_ZX29_DMA
				1350
				1351	dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup)
				1352	{
				1353	struct uart_port *port = &zup->port;
				1354	if(port->line < UART0 \|\| port->line > UART4){
				1355	printk("get_rx_dma_peripheral_id,fail, invalid port->line:%d\n", port->line);
				1356	}
				1357	if(port->line == UART0){
				1358	return DMA_CH_UART0_RX;
				1359	} else if(port->line == UART1){
				1360	return DMA_CH_UART1_RX;
				1361	}else if(port->line == UART2){
				1362	return DMA_CH_UART2_RX;
				1363	}
				1364	// else if(port->line == UART3){
				1365	// return DMA_CH_UART3_RX;
				1366	// }else if(port->line == UART4){
				1367	// return DMA_CH_UART4_RX;
				1368	// }
				1369
				1370	return DMA_CH_NUM;
				1371	}
				1372
				1373	/*
				1374	* We received a transmit interrupt without a pending X-char but with
				1375	* pending characters.
				1376	* Locking: called with port lock held and IRQs disabled.
				1377	* Returns:
				1378	* false if we want to use PIO to transmit
				1379	* true if we queued a DMA buffer
				1380	*/
				1381	static bool zx29_dma_tx_irq(struct zx29_uart_port *zup)
				1382	{
				1383	if (!zup->using_tx_dma)
				1384	return false;
				1385
				1386	/*
				1387	* If we already have a TX buffer queued, but received a
				1388	* TX interrupt, it will be because we've just sent an X-char.
				1389	* Ensure the TX DMA is enabled and the TX IRQ is disabled.
				1390	*/
				1391	if (zup->dmatx.queued) {
				1392	zup->dmacr \|= UART_TXDMAE;
				1393	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1394	zup->imr &= ~UART_TXIM;
				1395	UART_PUT_IMSC(&zup->port,zup->imr);
				1396	return true;
				1397	}
				1398
				1399	/*
				1400	* We don't have a TX buffer queued, so try to queue one.
				1401	* If we successfully queued a buffer, mask the TX IRQ.
				1402	*/
				1403	if (zx29_uart_dma_tx_chars(zup) > 0) {
				1404	zup->imr &= ~UART_TXIM;
				1405	UART_PUT_IMSC(&zup->port,zup->imr);
				1406	return true;
				1407	}
				1408	return false;
				1409	}
				1410
				1411
				1412	/*
				1413	* Stop the DMA transmit (eg, due to received XOFF).
				1414	* Locking: called with port lock held and IRQs disabled.
				1415	*/
				1416	static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup)
				1417	{
				1418	if (zup->dmatx.queued) {
				1419	zup->dmacr &= ~UART_TXDMAE;
				1420	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1421	}
				1422	}
				1423
				1424
				1425	/*
				1426	* Try to start a DMA transmit, or in the case of an XON/OFF
				1427	* character queued for send, try to get that character out ASAP.
				1428	* Locking: called with port lock held and IRQs disabled.
				1429	* Returns:
				1430	* false if we want the TX IRQ to be enabled
				1431	* true if we have a buffer queued
				1432	*/
				1433	static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup)
				1434	{
				1435	u16 dmacr;
				1436
				1437	if (!zup->using_tx_dma)
				1438	return false;
				1439
				1440	if (!zup->port.x_char) {
				1441	/* no X-char, try to push chars out in DMA mode */
				1442	bool ret = true;
				1443
				1444	if (!zup->dmatx.queued) {
				1445	if (zx29_uart_dma_tx_chars(zup) > 0) {
				1446	zup->imr &= ~UART_TXIM;
				1447	ret = true;
				1448	} else {
				1449	zup->imr \|= UART_TXIM;
				1450	ret = false;
				1451	}
				1452	UART_PUT_IMSC(&zup->port,zup->imr);
				1453	} else if (!(zup->dmacr & UART_TXDMAE)) {
				1454	zup->dmacr \|= UART_TXDMAE;
				1455	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1456	}
				1457	return ret;
				1458	}
				1459
				1460	/*
				1461	* We have an X-char to send. Disable DMA to prevent it loading
				1462	* the TX fifo, and then see if we can stuff it into the FIFO.
				1463	*/
				1464	dmacr = zup->dmacr;
				1465	zup->dmacr &= ~UART_TXDMAE;
				1466	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1467
				1468	if (UART_GET_FR(&zup->port) & UART_FR_TXFF) {
				1469	/*
				1470	* No space in the FIFO, so enable the transmit interrupt
				1471	* so we know when there is space. Note that once we've
				1472	* loaded the character, we should just re-enable DMA.
				1473	*/
				1474	return false;
				1475	}
				1476
				1477	UART_PUT_CHAR(&zup->port, zup->port.x_char);
				1478	//writew(uap->port.x_char, uap->port.membase + UART01x_DR);
				1479	zup->port.icount.tx++;
				1480	zup->port.x_char = 0;
				1481
				1482	/* Success - restore the DMA state */
				1483	zup->dmacr = dmacr;
				1484	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1485	//writew(dmacr, uap->port.membase + UART011_DMACR);
				1486
				1487	return true;
				1488	}
				1489
				1490	/****************************************************************************/
				1491
				1492	//#if CONFIG_SERIAL_ZX29_DMA
				1493	/*
				1494	* Flush the transmit buffer.
				1495	* Locking: called with port lock held and IRQs disabled.
				1496	*/
				1497	static void zx29_dma_flush_buffer(struct uart_port *port)
				1498	{
				1499	struct zx29_uart_port zup = (struct zx29_uart_port )port;
				1500	if (!zup->using_tx_dma)
				1501	return;
				1502
				1503	/* Avoid deadlock with the DMA engine callback */
				1504	//dmaengine_terminate_all(zup->dmatx.chan);
				1505	if (zup->dmatx.queued) {
				1506
				1507	//printk(KERN_INFO "zx29_dma_flush_buffer enter[%s][%d] Port[%d]\n",__func__,__LINE__,port->line);
				1508	dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
				1509	DMA_TO_DEVICE);
				1510	zup->dmatx.queued = false;
				1511	zup->dmacr &= ~UART_TXDMAE;
				1512	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1513	}
				1514	}
				1515
				1516	static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup)
				1517	{
				1518	struct dma_chan *rxchan = zup->dmarx.chan;
				1519	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				1520	struct dma_async_tx_descriptor *desc;
				1521	struct zx29_sgbuf *sgbuf;
				1522
				1523	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				1524	if (!rxchan)
				1525	{
				1526	printk("[%s][%d]\n",__func__,__LINE__);
				1527	return -EIO;
				1528	}
				1529
				1530	/* Start the RX DMA job */
				1531
				1532	sgbuf = zup->dmarx.use_buf_b ?
				1533	&zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
				1534	/*
				1535
				1536	sgbuf = zup->dmarx.use_buf_b ?
				1537	&zup->dmarx.sgbuf_a : &zup->dmarx.sgbuf_b;
				1538	*/
				1539	zup->dmarx.rx_def[zup->dmarx.rx_index].link_addr=0;
				1540	zup->dmarx.rx_def[zup->dmarx.rx_index].dest_addr=(unsigned int)(sgbuf->dma_addr);
				1541	zup->dmarx.rx_def[zup->dmarx.rx_index].count=ZX29_DMA_BUFFER_SIZE;//fifo or max buffer?
				1542	wmb();
				1543
				1544	dmaengine_slave_config(rxchan, (struct dma_slave_config*)&zup->dmarx.rx_def[zup->dmarx.rx_index]);
				1545	desc = rxchan->device->device_prep_interleaved_dma(rxchan,NULL,0);
				1546
				1547
				1548	/*
				1549	* If the DMA engine is busy and cannot prepare a
				1550	* channel, no big deal, the driver will fall back
				1551	* to interrupt mode as a result of this error code.
				1552	*/
				1553	if (!desc) {
				1554	printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
				1555	sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d ERROR DESC \n",zup->port.line);
				1556	zup->dmarx.running = false;
				1557	dmaengine_terminate_all(rxchan);
				1558	//zx29_dma_force_stop(rx_id);
				1559	return -EBUSY;
				1560	}
				1561
				1562	/* Some data to go along to the callback */
				1563	desc->callback = uart_dma_rx_callback;
				1564	desc->callback_param = zup;
				1565	zup->curr_sg = sgbuf;
				1566	wmb();
				1567
				1568	dmarx->cookie = dmaengine_submit(desc);
				1569	dma_async_issue_pending(rxchan);
				1570	atomic_inc(&zup->dmarx.count);
				1571	zup->dmarx.rx_index = (zup->dmarx.rx_index +1)%UART_DMA_RX_MAX_COUNT;
				1572	zup->dmacr \|= UART_RXDMAE;
				1573	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1574	zup->dmarx.running = true;
				1575	zup->dmarx.used = true;
				1576	zup->imr &= ~(UART_RXIM \| UART_RTIM);
				1577	UART_PUT_IMSC(&zup->port,zup->imr);
				1578
				1579
				1580	return 0;
				1581	}
				1582	static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup)
				1583	{
				1584	struct dma_chan *rxchan = zup->dmarx.chan;
				1585	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				1586	struct dma_async_tx_descriptor *desc;
				1587	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				1588	int uart_id = zup->port.line;
				1589	if (!rxchan)
				1590	{
				1591	printk("[%s][%d]\n",__func__,__LINE__);
				1592	return -EIO;
				1593	}
				1594	dmaengine_slave_config(rxchan, (struct dma_slave_config*)&uart_dma_cycle[uart_id].rxdef);
				1595	desc = rxchan->device->device_prep_dma_cyclic(rxchan,NULL,(ZX29_DMA_BUFFER_SIZE *5) , ZX29_DMA_BUFFER_SIZE,0,0);
				1596	if (!desc) {
				1597	printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
				1598	zup->dmarx.running = false;
				1599	dmaengine_terminate_all(rxchan);
				1600	return -EBUSY;
				1601	}
				1602	desc->callback = uart_dma_rx_callback_use_dma_cyclic;
				1603	desc->callback_param = zup;
				1604	wmb();
				1605	dmarx->cookie = dmaengine_submit(desc);
				1606	dma_async_issue_pending(rxchan);
				1607	zup->dmacr \|= UART_RXDMAE;
				1608	UART_PUT_DMACR(&zup->port, zup->dmacr);
				1609	uart_dma_cycle[uart_id].flg_enter_th = 0;
				1610	zup->dmarx.running = true;
				1611	zup->dmarx.used = true;
				1612	zup->imr &= ~(UART_RXIM \| UART_RTIM);
				1613	UART_PUT_IMSC(&zup->port,zup->imr);
				1614	return 0;
				1615	}
				1616
				1617	void uart_dma_rx_callback(void *data)
				1618	{
				1619	unsigned long flags;
				1620
				1621	struct zx29_uart_port zup = (struct zx29_uart_port )data;
				1622	int uart_id = zup->port.line;
				1623	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				1624	struct dma_chan *rxchan = dmarx->chan;
				1625	struct device *dev = NULL;
				1626	// struct dma_tx_state state;
				1627	unsigned int ris_status;
				1628
				1629	bool lastbuf;
				1630	int dma_count = 0;
				1631	struct zx29_sgbuf *sgbuf = zup->curr_sg;
				1632	size_t pending;
				1633
				1634	spin_lock_irqsave(&zup->port.lock, flags);
				1635	ris_status = UART_GET_RIS(&zup->port);
				1636	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				1637	if(ris_status & UART_OEIS){
				1638	zup->port.icount.overrun++;
				1639	g_uart_overrun[uart_id] = 4;
				1640	test_uart_static(zup->port.line, NULL, 0, 20);
				1641	//if(!uart_console(&zup->port))
				1642	// BUG_ON(1);
				1643	}
				1644	if(ris_status & UART_BEIS)
				1645	zup->port.icount.brk++;
				1646	if(ris_status & UART_PEIS)
				1647	zup->port.icount.parity++;
				1648	if(ris_status & UART_FEIS)
				1649	zup->port.icount.frame++;
				1650	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				1651	}
				1652	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				1653	zx29_dma_stop(rx_id);
				1654
				1655	dev = zup->dmarx.chan->device->dev;
				1656	zup->dmacr &= ~UART_RXDMAE;
				1657	UART_PUT_DMACR(&zup->port,zup->dmacr);
				1658
				1659	//spin_lock_irqsave(&zup->port.lock, flags);
				1660	zup->sg2tty = sgbuf;
				1661	// rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
				1662	zup->sg2tty_len = zup->sg2tty->sg.length - zx29_dma_get_transfer_num(rx_id);
				1663	//zx29_dma_force_stop(rx_id);
				1664	// dmaengine_terminate_all(rxchan);
				1665	dmarx->use_buf_b = ! dmarx->use_buf_b;
				1666	wmb();
				1667	//BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
				1668	/* Then we terminate the transfer - we now know our residue */
				1669	//dmaengine_terminate_all(rxchan);
				1670
				1671	zup->dmarx.running = false;
				1672	zup->dmarx.used = false;
				1673	test_uart_static(zup->port.line, NULL, 0, 9);
				1674	if (zx29_dma_rx_trigger_dma(zup)) {
				1675	printk("rx_dma_chars RXDMA start fail\n");
				1676	zup->imr \|= UART_RXIM;
				1677	UART_PUT_IMSC(&zup->port,zup->imr);
				1678	}else{
				1679	zup->pre_pending = 0;
				1680	zup->dmarx.used = true;
				1681	zup->work_state = true;
				1682	}
				1683	spin_unlock_irqrestore(&zup->port.lock, flags);
				1684
				1685	up(&zup->sema);
				1686	}
				1687
				1688	void uart_dma_rx_callback_use_dma_cyclic(void *data)
				1689	{
				1690	unsigned long flags;
				1691	struct zx29_uart_port zup = (struct zx29_uart_port )data;
				1692	unsigned int ris_status;
				1693	int uart_id = zup->port.line;
				1694	spin_lock_irqsave(&zup->port.lock, flags);
				1695	uart_dma_cycle[uart_id].cnt_callback_total++;
				1696	uart_dma_cycle[uart_id].cnt_callback++;
				1697	ris_status = UART_GET_RIS(&zup->port);
				1698	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				1699	if(ris_status & UART_OEIS){
				1700	zup->port.icount.overrun++;
				1701	uart_dma_cycle[uart_id].flg_overrun = 1;
				1702	}
				1703	if(ris_status & UART_BEIS){
				1704	uart_dma_cycle[uart_id].flg_be = 1;
				1705	zup->port.icount.brk++;
				1706	}
				1707	if(ris_status & UART_PEIS){
				1708	uart_dma_cycle[uart_id].flg_pe = 1;
				1709	zup->port.icount.parity++;
				1710	}
				1711	if(ris_status & UART_FEIS){
				1712	uart_dma_cycle[uart_id].flg_fe = 1;
				1713	zup->port.icount.frame++;
				1714	}
				1715	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				1716	}
				1717	spin_unlock_irqrestore(&zup->port.lock, flags);
				1718	test_uart_static(zup->port.line, NULL, 0, 26);
				1719	up(&zup->sema_cyclic);
				1720	}
				1721	static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup)
				1722	{
				1723	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				1724	//zx29_dma_force_stop(rx_id);
				1725	//dmaengine_terminate_all(zup->dmarx.chan);
				1726	/* FIXME. Just disable the DMA enable */
				1727	zup->dmacr &= ~UART_RXDMAE;
				1728	UART_PUT_DMACR(&zup->port,zup->dmacr);
				1729	zx29_dma_stop(rx_id);
				1730	#if 0
				1731	//do we need check data received?
				1732	if(zup->pre_pending){
				1733	printk("pre_pending :%d\n ", zup->pre_pending);
				1734	}
				1735	#endif
				1736	zup->curr_sg = NULL;
				1737	}
				1738
				1739	static void zx29_dma_remove(struct zx29_uart_port *zup)
				1740	{
				1741	/* TODO: remove the initcall if it has not yet executed */
				1742	if (zup->dmatx.chan)
				1743	dma_release_channel(zup->dmatx.chan);
				1744	if (zup->dmarx.chan)
				1745	dma_release_channel(zup->dmarx.chan);
				1746	}
				1747
				1748
				1749	static void zx29_dma_shutdown(struct zx29_uart_port *zup)
				1750	{
				1751	unsigned long flags;
				1752	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				1753
				1754	if (!(zup->using_tx_dma \|\| zup->using_rx_dma))
				1755	return;
				1756	/* Disable RX and TX DMA */
				1757	while(UART_GET_FR(&zup->port) & (UART_FR_TXBUSY \| UART_FR_TXBUSY))
				1758	barrier();
				1759
				1760	spin_lock_irqsave(&zup->port.lock, flags);
				1761	//zx29_dma_force_stop(rx_id);
				1762	// dmaengine_terminate_all(zup->dmarx.chan);
				1763	zup->dmacr &= ~(UART_DMAONERR \| UART_RXDMAE \| UART_TXDMAE);
				1764	UART_PUT_DMACR(&zup->port,zup->dmacr);
				1765	zx29_dma_stop(rx_id);
				1766	zup->curr_sg = NULL;
				1767	spin_unlock_irqrestore(&zup->port.lock, flags);
				1768	if (zup->using_tx_dma) {
				1769	/* In theory, this should already be done by zx29_dma_flush_buffer */
				1770	dmaengine_terminate_all(zup->dmatx.chan);
				1771	if (zup->dmatx.queued) {
				1772	dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
				1773	DMA_TO_DEVICE);
				1774	zup->dmatx.queued = false;
				1775	}
				1776	if(!zup->dmatx.buf)
				1777	kfree(zup->dmatx.buf);
				1778	zup->dmatx.buf = NULL;
				1779	zup->using_tx_dma = false;
				1780	}
				1781	if (zup->using_rx_dma) {
				1782	//dmaengine_terminate_all(zup->dmarx.chan);
				1783	/* Clean up the RX DMA */
				1784	if(!zup->uart_power_mode){
				1785	zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a, DMA_FROM_DEVICE);
				1786	zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_b, DMA_FROM_DEVICE);
				1787	}else if(zup->uart_power_mode == 1){
				1788	uart_dma_cycle_deinit(zup);
				1789	}else
				1790	printk("uart%d dma shutdown fail.\n",zup->port.line);
				1791	zup->using_rx_dma = false;
				1792	zup->dmarx.used = false;
				1793	zup->dmarx.running = false;
				1794	zup->dmarx.use_buf_b = false;
				1795	zup->dmarx.rx_index = 0;
				1796	}
				1797	zup->pre_pending = 0;
				1798	zup->work_state = false;
				1799
				1800	}
				1801
				1802	static void zx29_shutdown_channel(struct zx29_uart_port *zup,
				1803	unsigned int lcrh)
				1804	{
				1805	unsigned long val;
				1806
				1807	val = UART_GET_LCRH(&zup->port);
				1808	val &= ~(UART_LCRH_BRK \| UART_LCRH_FEN);
				1809	UART_PUT_LCRH(&zup->port, val);
				1810	}
				1811
				1812
				1813	static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup)
				1814	{
				1815	return zup->using_rx_dma;
				1816	}
				1817
				1818	static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup)
				1819	{
				1820	return zup->using_rx_dma && zup->dmarx.running;
				1821	}
				1822
				1823	static inline bool zx29_dma_rx_used(struct zx29_uart_port *zup)
				1824	{
				1825	return zup->using_rx_dma && zup->dmarx.used;
				1826	}
				1827
				1828	static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup)
				1829	{
				1830	return zup->using_rx_dma && zup->work_state;
				1831	}
				1832
				1833
				1834	void uart_dma_tx_callback(void *data)
				1835	{
				1836	struct zx29_uart_port *zup = data;
				1837	struct zx29_dmatx_data *dmatx = &zup->dmatx;
				1838
				1839	unsigned long flags;
				1840	u16 dmacr;
				1841	spin_lock_irqsave(&zup->port.lock, flags);
				1842	if (zup->dmatx.queued)
				1843	dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
				1844	DMA_TO_DEVICE);
				1845
				1846	dmacr = zup->dmacr;
				1847	zup->dmacr = dmacr & ~UART_TXDMAE;
				1848	UART_PUT_DMACR(&zup->port,zup->dmacr);
				1849
				1850	/*
				1851	* If TX DMA was disabled, it means that we've stopped the DMA for
				1852	* some reason (eg, XOFF received, or we want to send an X-char.)
				1853	*
				1854	* Note: we need to be careful here of a potential race between DMA
				1855	* and the rest of the driver - if the driver disables TX DMA while
				1856	* a TX buffer completing, we must update the tx queued status to
				1857	* get further refills (hence we check dmacr).
				1858	*/
				1859	if (!(dmacr & UART_TXDMAE) \|\| uart_tx_stopped(&zup->port) \|\|
				1860	uart_circ_empty(&zup->port.state->xmit)) {
				1861	zup->dmatx.queued = false;
				1862
				1863
				1864	zx_cpuidle_set_free(IDLE_FLAG_UART);
				1865
				1866
				1867	spin_unlock_irqrestore(&zup->port.lock, flags);
				1868	return;
				1869	}
				1870
				1871	if (zx29_uart_dma_tx_chars(zup) <= 0) {
				1872	/*
				1873	* We didn't queue a DMA buffer for some reason, but we
				1874	* have data pending to be sent. Re-enable the TX IRQ.
				1875	*/
				1876	zup->imr \|= UART_TXIM;
				1877	UART_PUT_IMSC(&zup->port, zup->imr);
				1878	}
				1879	spin_unlock_irqrestore(&zup->port.lock, flags);
				1880	}
				1881
				1882	static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup)
				1883	{
				1884	struct zx29_dmatx_data *dmatx = &zup->dmatx;
				1885	struct dma_chan *tx_chan = dmatx->chan;
				1886	struct dma_device *dma_dev = tx_chan->device;
				1887	struct dma_async_tx_descriptor *desc;
				1888	struct circ_buf *xmit = &zup->port.state->xmit;
				1889	unsigned int count;
				1890
				1891	/*
				1892	* Try to avoid the overhead involved in using DMA if the
				1893	* transaction fits in the first half of the FIFO, by using
				1894	* the standard interrupt handling. This ensures that we
				1895	* issue a uart_write_wakeup() at the appropriate time.
				1896	*/
				1897
				1898	count = uart_circ_chars_pending(xmit);
				1899	if (count < (16 >> 1)) {
				1900	zup->dmatx.queued = false;
				1901	return 0;
				1902	}
				1903
				1904	if (xmit->tail < xmit->head)
				1905	memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
				1906	else {
				1907	size_t first = UART_XMIT_SIZE - xmit->tail;
				1908	size_t second ;//= xmit->head;
				1909
				1910	if (first > count)
				1911	first = count;
				1912	second = count - first;
				1913	memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
				1914	if (second)
				1915	memcpy(&dmatx->buf[first], &xmit->buf[0], second);
				1916	}
				1917	dmatx->sg.length = count;
				1918
				1919	if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
				1920	zup->dmatx.queued = false;
				1921	dev_dbg(zup->port.dev, "unable to map TX DMA\n");
				1922	return -EBUSY;
				1923	}
				1924
				1925
				1926	zup->dmatx.tx_def.link_addr=0;
				1927	zup->dmatx.tx_def.src_addr=(unsigned int)(dmatx->sg.dma_address);
				1928	zup->dmatx.tx_def.count=count;
				1929	wmb();
				1930	dmaengine_slave_config(tx_chan, (struct dma_slave_config*)&zup->dmatx.tx_def);
				1931	desc = tx_chan->device->device_prep_interleaved_dma(tx_chan,NULL,0);
				1932
				1933	if (!desc) {
				1934	printk(KERN_INFO "!!!!!ERROR TX DESC[%s][%d]\n",__func__,__LINE__);
				1935	dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
				1936	zup->dmatx.queued = false;
				1937	/*
				1938	* If DMA cannot be used right now, we complete this
				1939	* transaction via IRQ and let the TTY layer retry.
				1940	*/
				1941	dev_dbg(zup->port.dev, "TX DMA busy\n");
				1942	return -EBUSY;
				1943	}
				1944	desc->callback = (dma_async_tx_callback)uart_dma_tx_callback;
				1945	desc->callback_param = (void *)zup;
				1946	dmaengine_submit(desc);
				1947	dma_async_issue_pending(tx_chan);
				1948	atomic_inc(&zup->dmatx.count);
				1949	zup->dmacr \|= UART_TXDMAE;
				1950	UART_PUT_DMACR(&zup->port,zup->dmacr);
				1951	zup->dmatx.queued = true;
				1952
				1953	/*
				1954	* Now we know that DMA will fire, so advance the ring buffer
				1955	* with the stuff we just dispatched.
				1956	*/
				1957	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
				1958	zup->port.icount.tx += count;
				1959
				1960	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
				1961	//uart_write_wakeup(&zup->port);
				1962	tasklet_schedule(&zup->write_wakeup);
				1963
				1964	return 1;
				1965	}
				1966
				1967	static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
				1968	//u32 pending, bool use_buf_b,
				1969	u32 pending, struct zx29_sgbuf *sgbuf,
				1970	bool readfifo, unsigned long *flags)
				1971	{
				1972	struct tty_struct *tty = zup->port.state->port.tty;
				1973	#if 0
				1974	struct zx29_sgbuf *sgbuf = use_buf_b ?
				1975	&zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
				1976	#endif
				1977	struct device *dev = zup->dmarx.chan->device->dev;
				1978	int dma_count = 0;
				1979	u32 fifotaken = 0; /* only used for vdbg() */
				1980	//unsigned long flags;
				1981
				1982	/* Pick everything from the DMA first */
				1983	if (pending) {
				1984	/* Sync in buffer */
				1985
				1986	dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
				1987
				1988	/*
				1989	* First take all chars in the DMA pipe, then look in the FIFO.
				1990	* Note that tty_insert_flip_buf() tries to take as many chars
				1991	* as it can.
				1992	*/
				1993
				1994	spin_unlock_irqrestore(&zup->port.lock, *flags);
				1995
				1996	dma_count = tty_insert_flip_string(&zup->port.state->port,
				1997	sgbuf->buf, pending);
				1998
				1999	test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
				2000	spin_lock_irqsave(&zup->port.lock, *flags);
				2001	/* Return buffer to device */
				2002	dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
				2003
				2004	zup->port.icount.rx += dma_count;
				2005	if (dma_count < pending)
				2006	dev_info(zup->port.dev,
				2007	"couldn't insert all characters (TTY is full?)\n");
				2008	}
				2009
				2010	/*
				2011	* Only continue with trying to read the FIFO if all DMA chars have
				2012	* been taken first.
				2013	*/
				2014	//if (dma_count == pending && readfifo) {
				2015	if (readfifo) {
				2016	/* Clear any error flags */
				2017	//UART_PUT_ICR(&zup->port,UART_OEIC \| UART_BEIC \| UART_PEIC \| UART_FEIC);
				2018	/*
				2019	* If we read all the DMA'd characters, and we had an
				2020	* incomplete buffer, that could be due to an rx error, or
				2021	* maybe we just timed out. Read any pending chars and check
				2022	* the error status.
				2023	*
				2024	* Error conditions will only occur in the FIFO, these will
				2025	* trigger an immediate interrupt and stop the DMA job, so we
				2026	* will always find the error in the FIFO, never in the DMA
				2027	* buffer.
				2028	*/
				2029	test_uart_static(zup->port.line, NULL, 0, 7);
				2030	fifotaken = zx29_uart_fifo_to_tty(zup);
				2031	}
				2032	if((pending > 0) \|\| (fifotaken > 0)) {
				2033	spin_unlock(&zup->port.lock);
				2034	tty_flip_buffer_push(&zup->port.state->port);
				2035	spin_lock(&zup->port.lock);
				2036	}
				2037	}
				2038	static void zx29_uart_deal_dma_fifo_rx_chars_cyclic(struct zx29_uart_port *zup,
				2039	u32 pending, struct zx29_sgbuf *sgbuf,
				2040	unsigned long flags, char fifo_buf, int fifo_len)
				2041	{
				2042	struct tty_struct *tty = zup->port.state->port.tty;
				2043	struct device *dev = zup->dmarx.chan->device->dev;
				2044	int dma_count = 0;
				2045	int fifo_count = 0;
				2046	u32 fifotaken = 0; /* only used for vdbg() */
				2047	if ((pending) && (pending != 4096)) {
				2048	dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
				2049	spin_unlock_irqrestore(&zup->port.lock, *flags);
				2050	dma_count = tty_insert_flip_string(&zup->port.state->port,
				2051	sgbuf->buf, pending);
				2052	test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
				2053	spin_lock_irqsave(&zup->port.lock, *flags);
				2054	dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
				2055	zup->port.icount.rx += dma_count;
				2056	if (dma_count < pending)
				2057	dev_info(zup->port.dev,
				2058	"couldn't insert all characters (TTY is full?)\n");
				2059	}
				2060	if(fifo_len){
				2061	spin_unlock_irqrestore(&zup->port.lock, *flags);
				2062	fifo_count = tty_insert_flip_string(&zup->port.state->port,
				2063	fifo_buf, fifo_len);
				2064	fifo_buf[0] = '\0';
				2065	fifo_buf[1] = '\0';
				2066	fifo_buf[2] = '\0';
				2067	spin_lock_irqsave(&zup->port.lock, *flags);
				2068	}
				2069	zup->port.icount.rx += fifo_count;
				2070	if(((pending) && (pending != 4096)) \|\| (fifo_len > 0)){
				2071	spin_unlock(&zup->port.lock);
				2072	tty_flip_buffer_push(&zup->port.state->port);
				2073	spin_lock(&zup->port.lock);
				2074	}
				2075	}
				2076
				2077	static void zx29_uart_deal_dma_fifo_rx_chars(struct zx29_uart_port *zup,
				2078	u32 pending, struct zx29_sgbuf *sgbuf,
				2079	unsigned long flags, char fifo_buf, int fifo_len)
				2080	{
				2081	struct tty_struct *tty = zup->port.state->port.tty;
				2082
				2083	struct device *dev = zup->dmarx.chan->device->dev;
				2084	int dma_count = 0;
				2085	int fifo_count = 0;
				2086	u32 fifotaken = 0; /* only used for vdbg() */
				2087	if (pending) {
				2088	dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
				2089	spin_unlock_irqrestore(&zup->port.lock, *flags);
				2090	dma_count = tty_insert_flip_string(&zup->port.state->port,
				2091	sgbuf->buf, pending);
				2092	test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
				2093	spin_lock_irqsave(&zup->port.lock, *flags);
				2094	dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
				2095	spin_unlock_irqrestore(&zup->port.lock, *flags);
				2096	zup->port.icount.rx += dma_count;
				2097	if (dma_count < pending)
				2098	dev_info(zup->port.dev,
				2099	"couldn't insert all characters (TTY is full?)\n");
				2100	}
				2101
				2102	if(fifo_len){
				2103	//printk("qq >> fifo len %d.\n",fifo_len);
				2104	fifo_count = tty_insert_flip_string(&zup->port.state->port,
				2105	fifo_buf, fifo_len);
				2106	//printk("qq >>fifo count %d,buf is %x %x %x .\n",fifo_count, fifo_buf[0],fifo_buf[1],fifo_buf[2]);
				2107	fifo_buf[0] = '\0';
				2108	fifo_buf[1] = '\0';
				2109	fifo_buf[2] = '\0';
				2110	//memset(fifo_buf, '\0', 4);
				2111	}
				2112
				2113	zup->port.icount.rx += fifo_count;
				2114	test_uart_static(zup->port.line, fifo_buf, fifo_count, 18);
				2115	if(pending > 0 \|\| (fifo_len > 0)){
				2116	tty_flip_buffer_push(&zup->port.state->port);
				2117	spin_lock_irqsave(&zup->port.lock, *flags);
				2118	}
				2119	}
				2120
				2121	#if 0
				2122	static void zx29_dma_rx_irq(struct zx29_uart_port zup, unsigned long flags)
				2123	{
				2124	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				2125	struct dma_chan *rxchan = dmarx->chan;
				2126	struct zx29_sgbuf *sgbuf = dmarx->use_buf_b ?
				2127	&dmarx->sgbuf_b : &dmarx->sgbuf_a;
				2128	size_t pending;
				2129	struct dma_tx_state state;
				2130	enum dma_status dmastat;
				2131	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				2132
				2133	uint32_t ris_status = UART_GET_RIS(&zup->port);
				2134	//printk("rx irq\n");
				2135	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				2136	if(ris_status & UART_OEIS){
				2137	zup->port.icount.overrun++;
				2138	//if(!uart_console(&zup->port))
				2139	// BUG_ON(1);
				2140	}
				2141	if(ris_status & UART_BEIS)
				2142	zup->port.icount.brk++;
				2143	if(ris_status & UART_PEIS)
				2144	zup->port.icount.parity++;
				2145	if(ris_status & UART_FEIS)
				2146	zup->port.icount.frame++;
				2147
				2148	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				2149	}
				2150
				2151	if(zx29_dma_rx_running(zup)){
				2152	/*
				2153	* Pause the transfer so we can trust the current counter,
				2154	* do this before we pause the block, else we may
				2155	* overflow the FIFO.
				2156	*/
				2157	// if(zx29_dma_stop(rx_id))
				2158	// printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
				2159	//rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
				2160	//zx29_dma_force_stop(rx_id);
				2161	//dmaengine_terminate_all(rxchan);
				2162
				2163	//dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
				2164
				2165	/* Disable RX DMA - incoming data will wait in the FIFO */
				2166	zup->dmacr &= ~UART_RXDMAE;
				2167	UART_PUT_DMACR(&zup->port,zup->dmacr);
				2168	zx29_dma_stop(rx_id);
				2169	zup->dmarx.running = false;
				2170	zup->dmarx.used = false;
				2171	pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
				2172	BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
				2173	/* Then we terminate the transfer - we now know our residue */
				2174	//dmaengine_terminate_all(rxchan);
				2175
				2176	dmarx->use_buf_b = !dmarx->use_buf_b;
				2177	/*
				2178	* This will take the chars we have so far and insert
				2179	* into the framework.
				2180	*/
				2181	zx29_uart_dma_rx_chars(zup, pending, sgbuf, false, flags);
				2182	}
				2183
				2184	/* Switch buffer & re-trigger DMA job */
				2185	if (zx29_dma_rx_trigger_dma(zup)) {
				2186	printk("uart%d could not retrigger RX DMA job\n",zup->port.line);
				2187	zup->imr \|= UART_RXIM;
				2188	UART_PUT_IMSC(&zup->port, zup->imr);
				2189	}
				2190	#if RX_DMA_WORK
				2191	//printk("add timer\n");
				2192	else{
				2193	// mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
				2194	uart_mod_timer(zup, flags);
				2195	zup->pre_pending = 0;
				2196	zup->work_state = true;
				2197	}
				2198	#endif
				2199
				2200	}
				2201	#endif
				2202	/****************************************************************************/
				2203	static void zx29_uart_rx_dma_chars(struct zx29_uart_port zup, unsigned long flags)
				2204	{
				2205
				2206	struct tty_struct *tty = zup->port.state->port.tty;
				2207	//zx29_uart_fifo_to_tty(zup);
				2208	// spin_unlock(&zup->port.lock);
				2209	if (zx29_dma_rx_available(zup)) {
				2210	if (zx29_dma_rx_trigger_dma(zup)) {
				2211	printk("rx_dma_chars RXDMA start fail\n");
				2212	zup->imr \|= UART_RXIM \| UART_RTIM;
				2213	UART_PUT_IMSC(&zup->port,zup->imr);
				2214	}
				2215	#if RX_DMA_WORK
				2216	//printk("add timer\n");
				2217	else{
				2218	//mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
				2219	uart_mod_timer(zup, flags);
				2220	zup->pre_pending = 0;
				2221	zup->work_state = true;
				2222	}
				2223	#endif
				2224	}
				2225
				2226	//tty_flip_buffer_push(tty);
				2227	//spin_lock(&zup->port.lock);
				2228	}
				2229
				2230
				2231	/****************************************************************************/
				2232	static void zx29_uart_rx_timeout_chars(struct zx29_uart_port zup, unsigned long flags)
				2233	{
				2234	int rt_cnt = 0;
				2235	// unsigned long flags;
				2236
				2237	int fr = UART_GET_FR(&zup->port);
				2238	//printk("rx_timeout_chars\n");
				2239
				2240	rt_cnt = zx29_uart_fifo_to_tty(zup);
				2241	if(rt_cnt){
				2242	if(g_console_open_flag == 1 \|\| zup->port.line != DEBUG_CONSOLE){
				2243	spin_unlock(&zup->port.lock);
				2244	tty_flip_buffer_push(&zup->port.state->port);
				2245	spin_lock(&zup->port.lock);
				2246	}
				2247	}
				2248	}
				2249
				2250	static void zx29_uart_rt_dma(struct zx29_uart_port zup, unsigned long flags)
				2251	{
				2252	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				2253	struct dma_chan *rxchan = dmarx->chan;
				2254	struct zx29_sgbuf *sgbuf = zup->curr_sg;
				2255	size_t pending;
				2256	struct dma_tx_state state;
				2257	enum dma_status dmastat;
				2258
				2259	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				2260	uint32_t ris_status = UART_GET_RIS(&zup->port);
				2261
				2262	//rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
				2263	pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2264	//printk("---zx29_uart_rt_dma, pending:%d, residue:%d\n", pending, state.residue);
				2265	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				2266	if(ris_status & UART_OEIS){
				2267	zup->port.icount.overrun++;
				2268	// if(!uart_console(&zup->port))
				2269	//BUG_ON(1);
				2270	}
				2271	if(ris_status & UART_BEIS)
				2272	zup->port.icount.brk++;
				2273	if(ris_status & UART_PEIS)
				2274	zup->port.icount.parity++;
				2275	if(ris_status & UART_FEIS)
				2276	zup->port.icount.frame++;
				2277
				2278	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				2279	}
				2280
				2281	if(zx29_dma_rx_running(zup)){
				2282	/*
				2283	* Pause the transfer so we can trust the current counter,
				2284	* do this before we pause the block, else we may
				2285	* overflow the FIFO.
				2286	*/
				2287	zup->dmacr &= ~UART_RXDMAE;
				2288	UART_PUT_DMACR(&zup->port,zup->dmacr);
				2289	zx29_dma_stop(rx_id);
				2290	//rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
				2291	//printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
				2292	//dmastat = rxchan->device->device_tx_status(rxchan,
				2293	// dmarx->cookie, &state);
				2294	// dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
				2295
				2296	//zx29_dma_force_stop(rx_id);
				2297	//dmaengine_terminate_all(rxchan);
				2298
				2299	/* Disable RX DMA - incoming data will wait in the FIFO */
				2300	zup->dmarx.running = false;
				2301	zup->dmarx.used = false;
				2302	zup->curr_sg = zup->sg2tty = NULL;
				2303	zup->sg2tty_len = 0;
				2304	zup->imr \|= (UART_RTIM\|UART_RXIM);
				2305	UART_PUT_IMSC(&zup->port, zup->imr);
				2306	pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
				2307
				2308	//printk("---zx29_uart_rt_dma, after stop pending:%d, residue:%d\n", pending, state.residue);
				2309	BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
				2310	/* Then we terminate the transfer - we now know our residue */
				2311	//dmaengine_terminate_all(rxchan);
				2312
				2313	dmarx->use_buf_b = !dmarx->use_buf_b;
				2314	wmb();
				2315	/*
				2316	* This will take the chars we have so far and insert
				2317	* into the framework.
				2318	*/
				2319	test_uart_static(zup->port.line, NULL, 0, 5);
				2320	zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, flags);
				2321	}
				2322
				2323	#if 0
				2324	//printk("rt dma\n");
				2325	/* Switch buffer & re-trigger DMA job */
				2326	if (zx29_dma_rx_trigger_dma(zup)) {
				2327	printk("zx29_dma_rx_trigger_dma fail,uart:%d\n", zup->port.line);
				2328	zup->imr \|= UART_RXIM;
				2329	UART_PUT_IMSC(&zup->port, zup->imr);
				2330	}
				2331	#if RX_DMA_WORK
				2332	//printk("add timer\n");
				2333	else{
				2334	//mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
				2335	uart_mod_timer(zup, flags);
				2336	zup->pre_pending = 0;
				2337	zup->work_state = true;
				2338	zup->dmarx.used = true;
				2339	}
				2340	#endif
				2341
				2342	#endif
				2343
				2344	}
				2345	char g_fifo_residue_buf[5][4];
				2346	char g_fifo_residue_all[5][20];
				2347	unsigned char g_fifo_cnt[5];
				2348	static void zx29_uart_rx_dma_timeout(struct timer_list *t)
				2349	{
				2350	struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_timer);
				2351
				2352	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				2353	static bool dma_timeout_flag = false;
				2354	size_t pending, tmp_len;
				2355	uint32_t ris_status = 0;
				2356	int cancel_timer = 0;
				2357	int sg_idx = (dmarx->use_buf_b ? 1 : 0);
				2358
				2359	unsigned long flags;
				2360	struct zx29_sgbuf *sgbuf = NULL;
				2361	int uart_id = zup->port.line;
				2362	if(!zx29_dma_rx_running(zup))
				2363	//printk("---uart_rx_dma_timeout enter, dma stopped\n");
				2364	return;
				2365	raw_spin_lock_irqsave(&zup->port.lock, flags);
				2366	if(zup->port_close \|\| (zup->curr_sg == NULL)){
				2367	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2368	return;
				2369	}
				2370	//rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
				2371	if(zup->sg2tty) {//dma complete now, later check again
				2372	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2373	test_uart_static(zup->port.line, NULL, 0, 14);
				2374	mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
				2375	return;
				2376	}
				2377	sgbuf = zup->curr_sg;
				2378	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				2379	pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2380	//pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2381	//printk("---uart_rx_dma_timeout enter,sg.length:%d, pending:%d, state.residue:%d\n", sgbuf->sg.length, pending, state.residue);
				2382	if(pending == zup->pre_pending){
				2383	int fr = UART_GET_FR(&zup->port);
				2384	//if RXBUSY,means data come again
				2385
				2386	if((fr & UART_FR_RXBUSY)){
				2387
				2388	uart_mod_timer(zup, &flags);
				2389	test_uart_static(zup->port.line, NULL, 0, 12);
				2390	goto deal_end;
				2391
				2392	}
				2393
				2394	ris_status = UART_GET_RIS(&zup->port);
				2395
				2396	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				2397	if(ris_status & UART_OEIS){
				2398	zup->port.icount.overrun++;
				2399	g_uart_overrun[uart_id] = 1;
				2400	test_uart_static(zup->port.line, NULL, 0, 19);
				2401	//if(!uart_console(&zup->port))
				2402	// BUG_ON(1);
				2403	}
				2404	if(ris_status & UART_BEIS)
				2405	zup->port.icount.brk++;
				2406	if(ris_status & UART_PEIS)
				2407	zup->port.icount.parity++;
				2408	if(ris_status & UART_FEIS)
				2409	zup->port.icount.frame++;
				2410
				2411	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				2412	}
				2413
				2414	zup->dmacr &= ~UART_RXDMAE;
				2415	UART_PUT_DMACR(&zup->port,zup->dmacr);
				2416	zx29_dma_stop(rx_id);
				2417	zup->dmarx.running = false;
				2418	zup->dmarx.used = false;
				2419	tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2420	if(tmp_len != pending){
				2421	pending = tmp_len;
				2422	}
				2423	dmarx->use_buf_b = !dmarx->use_buf_b;
				2424	wmb();
				2425	if(zup->uart_power_mode){
				2426	int i;
				2427	for(i= 0;i < 3;i++){
				2428	fr = UART_GET_FR(&zup->port);
				2429	if((fr & UART_FR_RXFE) == 0){
				2430	g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) \| UART_DUMMY_DR_RX;
				2431	g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
				2432	if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
				2433	}
				2434	else
				2435	break;
				2436	}
				2437	if(i){
				2438	g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
				2439	if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
				2440	}
				2441
				2442	//zup->sg2tty = sgbuf;
				2443	//when app ctrl sleep ,always start dma receive
				2444	if(zup->sleep_state == 0){
				2445	//now start dma again
				2446	if (zx29_dma_rx_trigger_dma(zup)) {
				2447	printk("rx_dma_chars RXDMA start fail\n");
				2448	zup->imr \|= UART_RXIM;
				2449	UART_PUT_IMSC(&zup->port,zup->imr);
				2450	}else{
				2451	uart_mod_timer(zup, &flags);
				2452	zup->pre_pending = 0;
				2453	zup->dmarx.used = true;
				2454	zup->work_state = true;
				2455	}
				2456	}
				2457	if(pending \|\| (i > 0)){
				2458	test_uart_static(zup->port.line, NULL, 0, 13);
				2459	zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
				2460	}
				2461
				2462	}else{
				2463	//for normal mode, dma start only on rx busy after timeout came
				2464	if(pending \|\| (( fr & UART_FR_RXFE) == 0)){
				2465	test_uart_static(zup->port.line, NULL, 0, 13);
				2466	zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
				2467	}
				2468	zup->imr \|= (UART_RTIM\|UART_RXIM);
				2469	UART_PUT_IMSC(&zup->port, zup->imr);
				2470	zup->pre_pending = 0;
				2471	zup->work_state = false;
				2472	if((UART_GET_RIS(&zup->port) & (UART_RXIS \| UART_RTIS)) \|\|
				2473	(UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
				2474	zup->imr &= ~(UART_RXIM);
				2475	UART_PUT_IMSC(&zup->port, zup->imr);
				2476
				2477	if (zx29_dma_rx_trigger_dma(zup)) {
				2478	printk("rx_dma_chars RXDMA start fail\n");
				2479	zup->imr \|= (UART_RTIM\|UART_RXIM);
				2480	UART_PUT_IMSC(&zup->port,zup->imr);
				2481	}else{
				2482	uart_mod_timer(zup, &flags);
				2483	zup->pre_pending = 0;
				2484	zup->dmarx.used = true;
				2485	zup->work_state = true;
				2486	UART_PUT_ICR(&zup->port,(UART_RTIS\|UART_RXIS));
				2487	}
				2488	}
				2489
				2490	}
				2491	deal_end:
				2492
				2493	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2494	}else{
				2495	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2496	zup->pre_pending = pending;
				2497	mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
				2498	//uart_mod_timer(zup, &flags);
				2499	}
				2500
				2501
				2502	}
				2503	enum hrtimer_restart zx29_uart_rx_dma_hrtimeout(struct hrtimer *t)
				2504	{
				2505	struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
				2506	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				2507	static bool dma_timeout_flag = false;
				2508	size_t pending, tmp_len;
				2509	uint32_t ris_status = 0;
				2510	int cancel_timer = 0;
				2511	int sg_idx = (dmarx->use_buf_b ? 1 : 0);
				2512	int uart_id = zup->port.line;
				2513	unsigned long flags;
				2514	struct zx29_sgbuf *sgbuf = NULL;
				2515	if(!zx29_dma_rx_running(zup))
				2516	return HRTIMER_NORESTART;
				2517	raw_spin_lock_irqsave(&zup->port.lock, flags);
				2518	if(zup->port_close \|\| (zup->curr_sg == NULL)){
				2519	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2520	return HRTIMER_NORESTART;
				2521	}
				2522	if(zup->sg2tty) {//dma complete now, later check again
				2523	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2524	test_uart_static(zup->port.line, NULL, 0, 14);
				2525	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2526	return HRTIMER_RESTART;
				2527	}
				2528	if(zup->enter_suspend){
				2529	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2530	test_uart_static(zup->port.line, NULL, 0, 15);
				2531	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2532	return HRTIMER_RESTART;
				2533	}
				2534	sgbuf = zup->curr_sg;
				2535	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				2536	pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2537	if((pending == zup->pre_pending)) {
				2538	int fr = UART_GET_FR(&zup->port);
				2539	if((fr & UART_FR_RXBUSY)){
				2540	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2541	test_uart_static(zup->port.line, NULL, 0, 12);
				2542	goto deal_end;
				2543	}
				2544	ris_status = UART_GET_RIS(&zup->port);
				2545	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				2546	if(ris_status & UART_OEIS){
				2547	zup->port.icount.overrun++;
				2548	g_uart_overrun[uart_id] = 1;
				2549	test_uart_static(zup->port.line, NULL, 0, 19);
				2550	}
				2551	if(ris_status & UART_BEIS)
				2552	zup->port.icount.brk++;
				2553	if(ris_status & UART_PEIS)
				2554	zup->port.icount.parity++;
				2555	if(ris_status & UART_FEIS)
				2556	zup->port.icount.frame++;
				2557	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				2558	}
				2559	zup->dmacr &= ~UART_RXDMAE;
				2560	UART_PUT_DMACR(&zup->port,zup->dmacr);
				2561	zx29_dma_stop(rx_id);
				2562	zup->dmarx.running = false;
				2563	zup->dmarx.used = false;
				2564	tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2565	if(tmp_len != pending){
				2566	pending = tmp_len;
				2567	}
				2568	dmarx->use_buf_b = !dmarx->use_buf_b;
				2569	wmb();
				2570	if(zup->uart_power_mode){
				2571	int i;
				2572	for(i= 0;i < 3;i++){
				2573	fr = UART_GET_FR(&zup->port);
				2574	if((fr & UART_FR_RXFE) == 0){
				2575	g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) \| UART_DUMMY_DR_RX;
				2576	g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
				2577	if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
				2578	}
				2579	else
				2580	break;
				2581	}
				2582	if(i){
				2583	g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
				2584	if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
				2585	}
				2586	if(zup->sleep_state == 0){
				2587	if (zx29_dma_rx_trigger_dma(zup)) {
				2588	printk("rx_dma_chars RXDMA start fail\n");
				2589	zup->imr \|= UART_RXIM;
				2590	UART_PUT_IMSC(&zup->port,zup->imr);
				2591	}else{
				2592	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2593	zup->pre_pending = 0;
				2594	zup->dmarx.used = true;
				2595	zup->work_state = true;
				2596	}
				2597	}
				2598	if(pending \|\| (i > 0)){
				2599	test_uart_static(zup->port.line, NULL, 0, 13);
				2600	zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
				2601	}
				2602	}else{
				2603	if(pending \|\| (( fr & UART_FR_RXFE) == 0)){
				2604	test_uart_static(zup->port.line, NULL, 0, 13);
				2605	zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
				2606	printk("at pending %d.\n",pending);
				2607	}
				2608	zup->imr \|= (UART_RTIM\|UART_RXIM);
				2609	UART_PUT_IMSC(&zup->port, zup->imr);
				2610	zup->pre_pending = 0;
				2611	zup->work_state = false;
				2612	if((UART_GET_RIS(&zup->port) & (UART_RXIS \| UART_RTIS)) \|\|
				2613	(UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
				2614	zup->imr &= ~(UART_RXIM);
				2615	UART_PUT_IMSC(&zup->port, zup->imr);
				2616	if (zx29_dma_rx_trigger_dma(zup)) {
				2617	printk("rx_dma_chars RXDMA start fail\n");
				2618	zup->imr \|= (UART_RTIM\|UART_RXIM);
				2619	UART_PUT_IMSC(&zup->port,zup->imr);
				2620	}else{
				2621	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2622	zup->pre_pending = 0;
				2623	zup->dmarx.used = true;
				2624	zup->work_state = true;
				2625	UART_PUT_ICR(&zup->port,(UART_RTIS\|UART_RXIS));
				2626	}
				2627	}
				2628	}
				2629	deal_end:
				2630	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2631	return HRTIMER_RESTART;
				2632	}else{
				2633	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				2634	zup->pre_pending = pending;
				2635	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2636	test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
				2637	return HRTIMER_RESTART;
				2638	}
				2639	}
				2640	enum hrtimer_restart zx29_uart_rx_dma_hrtimeout_cyclic(struct hrtimer *t)
				2641	{
				2642	struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
				2643	struct zx29_dmarx_data *dmarx = &zup->dmarx;
				2644	struct dma_chan *rxchan = dmarx->chan;
				2645	size_t pending, tmp_len;
				2646	uint32_t ris_status = 0;
				2647	unsigned long flags;
				2648	struct zx29_sgbuf *sgbuf = NULL;
				2649	int uart_id = zup->port.line;
				2650	if(!zx29_dma_rx_running(zup))
				2651	return HRTIMER_NORESTART;
				2652	if(uart_dma_cycle[uart_id].cnt_callback > 0){
				2653	return HRTIMER_NORESTART;
				2654	}
				2655
				2656	spin_lock_irqsave(&zup->port.lock, flags);
				2657	sgbuf = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
				2658	if(zup->port_close \|\| (sgbuf == NULL)){
				2659	spin_unlock_irqrestore(&zup->port.lock, flags);
				2660	return HRTIMER_RESTART;
				2661	}
				2662	if(zup->sema_cyclic.count > 0){
				2663	printk("uart has th not deal.\n");
				2664	spin_unlock_irqrestore(&zup->port.lock, flags);
				2665	return HRTIMER_RESTART;
				2666	}
				2667	if((zup->sg2tty)){//dma not complete now, later check again
				2668	printk("dmath_cyclic not end.\n");
				2669	spin_unlock_irqrestore(&zup->port.lock, flags);
				2670	test_uart_static(zup->port.line, NULL, 0, 14);
				2671	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2672	return HRTIMER_RESTART;
				2673	}
				2674	if(zup->enter_suspend){
				2675	spin_unlock_irqrestore(&zup->port.lock, flags);
				2676	test_uart_static(zup->port.line, NULL, 0, 15);
				2677	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2678	return HRTIMER_RESTART;
				2679	}
				2680	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				2681	pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
				2682	if(((pending == zup->pre_pending) && pending) \|\| uart_dma_cycle[uart_id].from_resume){
				2683	uart_dma_cycle[uart_id].from_resume = 0;
				2684	#if 0
				2685	if(uart_dma_cycle[uart_id].flg_enter_th == 0)
				2686	uart_dma_cycle[uart_id].flg_enter_to = 4;
				2687	else
				2688	uart_dma_cycle[uart_id].flg_enter_to = uart_dma_cycle[uart_id].flg_enter_th - 1;
				2689	struct zx29_sgbuf *sgbuf_tmp = NULL;
				2690	sgbuf_tmp = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_to];
				2691	test_uart_static(zup->port.line, NULL, 0, 61);
				2692	if (sgbuf->sg.dma_address != (zx29_dma_cur_dst(rx_id)&0xfffff000)){
				2693	if(sgbuf_tmp->sg.dma_address != ((zx29_dma_cur_dst(rx_id)&0xfffff000)-0x1000)){
				2694	printk("uart lose dma isr enter self resume.\n");
				2695	up(&zup->sema_cyclic);
				2696	spin_unlock_irqrestore(&zup->port.lock, flags);
				2697	return;
				2698	}
				2699	}
				2700	#endif
				2701	int fr = UART_GET_FR(&zup->port);
				2702	if((fr & UART_FR_RXBUSY)){
				2703	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2704	test_uart_static(zup->port.line, NULL, 0, 12);
				2705	goto deal_end;
				2706	}
				2707	ris_status = UART_GET_RIS(&zup->port);
				2708	if(ris_status & (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS)){
				2709	if(ris_status & UART_OEIS){
				2710	zup->port.icount.overrun++;
				2711	uart_dma_cycle[uart_id].flg_overrun = 1;
				2712	}
				2713	if(ris_status & UART_BEIS)
				2714	zup->port.icount.brk++;
				2715	if(ris_status & UART_PEIS)
				2716	zup->port.icount.parity++;
				2717	if(ris_status & UART_FEIS)
				2718	zup->port.icount.frame++;
				2719	UART_PUT_ICR(&zup->port, (UART_OEIS \| UART_BEIS \| UART_PEIS \| UART_FEIS));
				2720	printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
				2721	zup->port.icount.brk,zup->port.icount.parity);
				2722	}
				2723	zup->dmacr &= ~UART_RXDMAE;
				2724	UART_PUT_DMACR(&zup->port,zup->dmacr);
				2725	dmaengine_terminate_all(rxchan);
				2726	test_uart_static(zup->port.line, NULL, 0, 60);
				2727	zup->dmarx.running = false;
				2728	zup->dmarx.used = false;
				2729	wmb();
				2730	int i = 0;
				2731	for(i= 0;i < 3;i++){
				2732	fr = UART_GET_FR(&zup->port);
				2733	if((fr & UART_FR_RXFE) == 0){
				2734	g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) \| UART_DUMMY_DR_RX;
				2735	g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
				2736	if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
				2737	}
				2738	else
				2739	break;
				2740	}
				2741	if(i){
				2742	g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
				2743	if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
				2744	}
				2745	if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
				2746	printk("rx_dma_chars RXDMA start fail\n");
				2747	zup->imr \|= UART_RXIM;
				2748	UART_PUT_IMSC(&zup->port,zup->imr);
				2749	}else{
				2750	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2751	zup->pre_pending = 0;
				2752	zup->dmarx.used = true;
				2753	zup->work_state = true;
				2754	}
				2755	if((pending && (pending != 4096)) \|\| (i > 0)){
				2756	zx29_uart_deal_dma_fifo_rx_chars_cyclic(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
				2757	}
				2758	uart_dma_cycle[uart_id].cnt_th = 0;
				2759	uart_dma_cycle[uart_id].cnt_callback=0;
				2760	deal_end:
				2761	spin_unlock_irqrestore(&zup->port.lock, flags);
				2762	return HRTIMER_RESTART;
				2763	}else{
				2764	spin_unlock_irqrestore(&zup->port.lock, flags);
				2765	zup->pre_pending = pending;
				2766	hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
				2767	test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
				2768	return HRTIMER_RESTART;
				2769	}
				2770	}
				2771	#endif
				2772
				2773
				2774	static void zx29_uart_modem_status(struct zx29_uart_port *zup)
				2775	{
				2776	unsigned int status, delta;
				2777
				2778	status = UART_GET_FR(&zup->port)& UART_FR_MODEM_ANY;
				2779
				2780	delta = status ^ zup->old_status;
				2781	zup->old_status = status;
				2782
				2783	if (!delta)
				2784	return;
				2785
				2786	if (delta & UART_FR_DCD)
				2787	uart_handle_dcd_change(&zup->port, status & UART_FR_DCD);
				2788
				2789	if (delta & UART_FR_DSR)
				2790	zup->port.icount.dsr++;
				2791
				2792	if (delta & UART_FR_CTS)
				2793	uart_handle_cts_change(&zup->port, status & UART_FR_CTS);
				2794
				2795	wake_up_interruptible(&zup->port.state->port.delta_msr_wait);
				2796	}
				2797
				2798	/****************************************************************************/
				2799	static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id)
				2800	{
				2801	struct uart_port port = (struct uart_port )dev_id;
				2802	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				2803	unsigned long flags;
				2804	unsigned int status,ris, pass_counter = 256;
				2805	int handled = 0;
				2806	int uart_id = zup->port.line;
				2807	spin_lock_irqsave(&zup->port.lock, flags);
				2808	status = UART_GET_MIS(port) & zup->imr;
				2809	ris = UART_GET_RIS(port);
				2810	if (status) {
				2811	do {
				2812	UART_PUT_ICR(port,(status & ~(UART_TXIS\|UART_RTIS\|UART_RXIS)));
				2813	if(uart_console(&zup->port)){
				2814	if (status & (UART_RTIS\|UART_RXIS))
				2815	zx29_uart_rx_chars(zup);
				2816	}else{
				2817	#ifdef CONFIG_CPU_IDLE
				2818	zup->rxd_int_depth = 0;
				2819	#endif
				2820	if (status & (UART_RXIS)){
				2821	#if CONFIG_SERIAL_ZX29_DMA
				2822	if(ris & UART_OEIS){
				2823	zup->port.icount.overrun++;
				2824	g_uart_overrun[uart_id] = 8;
				2825	test_uart_static(zup->port.line, NULL, 0, 21);
				2826	//if(!uart_console(&zup->port))
				2827	// BUG_ON(1);
				2828	}
				2829	if (zx29_dma_rx_used(zup)){
				2830	UART_PUT_ICR(port,UART_RXIS);
				2831	if(!(zup->imr & UART_RTIM)){
				2832	zup->imr \|= UART_RTIM;
				2833	UART_PUT_IMSC(port,zup->imr);
				2834	}
				2835
				2836	test_uart_static(port->line, NULL, 0, 8);
				2837	uart_mod_timer(zup, &flags);
				2838
				2839	}else{
				2840	test_uart_static(port->line, NULL, 0, 1);
				2841
				2842	zup->imr &= ~UART_RXIM;
				2843	UART_PUT_IMSC(&zup->port,zup->imr);
				2844	zx29_uart_rx_dma_chars(zup, &flags);
				2845
				2846	zup->dmarx.used = true;
				2847	//when RX&RT comes both, we trigger dma and add timer,so clear RT,waiting the timer
				2848	if(status & (UART_RTIS))
				2849	status &= ~UART_RTIS;
				2850	}
				2851	#else
				2852	zx29_uart_rx_chars(zup);
				2853	#endif
				2854	}
				2855
				2856	if (status & (UART_RTIS)){
				2857	#if CONFIG_SERIAL_ZX29_DMA
				2858	if(!zx29_dma_rx_running(zup)){
				2859	test_uart_static(port->line, NULL, 0, 2);
				2860	zx29_uart_rx_timeout_chars(zup, &flags);
				2861	}else{
				2862	UART_PUT_ICR(port, UART_RTIS);
				2863	test_uart_static(port->line, NULL, 0, 4);
				2864	zx29_uart_rt_dma(zup, &flags);
				2865	}
				2866	#else
				2867	zx29_uart_rx_chars(zup);
				2868	#endif
				2869	}
				2870	}
				2871
				2872	if (status & (UART_DSRMIS\|UART_DCDMIS\|UART_CTSMIS\|UART_RIMIS))
				2873	zx29_uart_modem_status(zup);
				2874
				2875	if (status & UART_TXIS)
				2876	zx29_uart_tx_chars(zup);
				2877
				2878	if (pass_counter-- == 0)
				2879	break;
				2880
				2881	status = UART_GET_MIS(port);
				2882	} while (status != 0);
				2883	handled = IRQ_HANDLED;
				2884	}
				2885	spin_unlock_irqrestore(&zup->port.lock, flags);
				2886
				2887	return IRQ_RETVAL(handled);
				2888	}
				2889
				2890	#if CONFIG_SERIAL_ZX29_DMA
				2891	extern bool zx29_dma_filter_fn(struct dma_chan chan, void param);
				2892	static void uart_dma_init(struct zx29_uart_port *zup)
				2893	{
				2894	int i=0;
				2895	struct dma_chan *chan = NULL;
				2896
				2897	atomic_set(&zup->dmarx.count, 1);
				2898	atomic_set(&zup->dmatx.count, 1);
				2899	#if 1
				2900	if(zup->port.line == UART0)
				2901	{
				2902	zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART0_BASE +zx29_UART_DR);
				2903	}
				2904	else if(zup->port.line == UART1)
				2905	{
				2906	zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART1_BASE+zx29_UART_DR);
				2907	}
				2908	else if(zup->port.line == UART2)
				2909	{
				2910	zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART2_BASE+zx29_UART_DR);
				2911	}
				2912
				2913	zup->dmatx.tx_def.dma_control.tran_mode = TRAN_MEM_TO_PERI;
				2914	zup->dmatx.tx_def.dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
				2915	zup->dmatx.tx_def.dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
				2916	zup->dmatx.tx_def.dma_control.src_burst_len = DMA_BURST_LEN_4;
				2917	zup->dmatx.tx_def.dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
				2918	zup->dmatx.tx_def.dma_control.dest_burst_len = DMA_BURST_LEN_4;
				2919
				2920	dma_cap_mask_t mask;
				2921	dma_cap_zero(mask);
				2922	dma_cap_set(DMA_SLAVE, mask);
				2923
				2924	if(zup->port.line == UART0)
				2925	{
				2926	chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_TX);
				2927	}
				2928	else if(zup->port.line == UART1)
				2929	{
				2930	chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_TX);
				2931	}
				2932	else if(zup->port.line == UART2)
				2933	{
				2934	chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_TX);
				2935	}
				2936	if(!chan){
				2937	printk("UART%d DMA TX channel request fail.\n", zup->port.line);
				2938	return;
				2939	}
				2940	zup->dmatx.chan = chan;
				2941
				2942
				2943
				2944	for(i=0;i<UART_DMA_RX_MAX_COUNT;i++)
				2945	{
				2946	if(zup->port.line == UART0)
				2947	{
				2948	zup->dmarx.rx_def[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
				2949	}
				2950	else if(zup->port.line == UART1)
				2951	{
				2952	zup->dmarx.rx_def[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
				2953	}
				2954	else if(zup->port.line == UART2)
				2955	{
				2956	zup->dmarx.rx_def[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
				2957	}
				2958
				2959	zup->dmarx.rx_def[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
				2960	zup->dmarx.rx_def[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
				2961	zup->dmarx.rx_def[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
				2962	zup->dmarx.rx_def[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
				2963	zup->dmarx.rx_def[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
				2964	zup->dmarx.rx_def[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
				2965	}
				2966
				2967	zup->dmarx.rx_index = 0;
				2968	chan = NULL;
				2969
				2970	dma_cap_zero(mask);
				2971	dma_cap_set(DMA_SLAVE, mask);
				2972
				2973	if(zup->port.line == UART0)
				2974	{
				2975	chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_RX);
				2976	}
				2977	else if(zup->port.line == UART1)
				2978	{
				2979	chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_RX);
				2980	}
				2981	else if(zup->port.line == UART2)
				2982	{
				2983	chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_RX);
				2984	}
				2985	if(!chan){
				2986	printk("UART%d DMA RX channel request fail.\n", zup->port.line);
				2987	return;
				2988	}
				2989	zup->dmarx.chan = chan;
				2990	#endif
				2991	}
				2992
				2993	static int uart_dma_cycle_init(struct zx29_uart_port *zup)
				2994	{
				2995	int ret;
				2996	int uart_id = zup->port.line;
				2997	uart_dma_cycle[uart_id].id = zup->port.line;
				2998	int i,j;
				2999	for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
				3000	ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
				3001	if(ret){
				3002	printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", zup->port.line, ret);
				3003	for(j=0;j<i;j++){
				3004	zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[j],DMA_FROM_DEVICE);
				3005	}
				3006	return -1;
				3007	}
				3008	}
				3009	for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
				3010	if(zup->port.line == UART0)
				3011	uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
				3012	else if(zup->port.line == UART1)
				3013	uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
				3014	else{
				3015	uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
				3016	}
				3017	uart_dma_cycle[uart_id].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id].sgbuf[i].dma_addr);
				3018	uart_dma_cycle[uart_id].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
				3019	uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
				3020	uart_dma_cycle[uart_id].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
				3021	uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
				3022	uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
				3023	uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
				3024	uart_dma_cycle[uart_id].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
				3025	uart_dma_cycle[uart_id].rxdef[i].link_addr = 1;
				3026	}
				3027	return 0;
				3028	}
				3029	static void uart_dma_cycle_deinit(struct zx29_uart_port *zup)
				3030	{
				3031	int i;
				3032	int uart_id = zup->port.line;
				3033	for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
				3034	zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
				3035	}
				3036	memset(uart_dma_cycle[uart_id].rxdef, 0, sizeof(uart_dma_cycle[uart_id].rxdef));
				3037	}
				3038	static void uart_dma_startup(struct zx29_uart_port *zup)
				3039	{
				3040	int ret = 0;
				3041	if (!zup->dmatx.chan)
				3042	{
				3043	printk("tx_chan is error[%s][%d]\n",__func__,__LINE__);
				3044	return;
				3045	}
				3046
				3047	zup->dmatx.buf = kmalloc(ZX29_DMA_BUFFER_SIZE, GFP_KERNEL \| __GFP_DMA);
				3048	if (!zup->dmatx.buf) {
				3049	printk("tx_buf is error[%s][%d]\n",__func__,__LINE__);
				3050	return;
				3051	}
				3052
				3053	sg_init_one(&zup->dmatx.sg, zup->dmatx.buf, ZX29_DMA_BUFFER_SIZE);
				3054
				3055	/* The DMA buffer is now the FIFO the TTY subsystem can use */
				3056	zup->port.fifosize = 16;//ZX29_DMA_BUFFER_SIZE;
				3057	zup->using_tx_dma = true;
				3058
				3059	if(!zup->uart_power_mode)
				3060	{
				3061	if (!zup->dmarx.chan)
				3062	{
				3063	printk(KERN_INFO "[%s][%d]uart_%d rx_chan is error\n",__func__,__LINE__, zup->port.line);
				3064	goto skip_rx;
				3065	}
				3066
				3067	/* Allocate and map DMA RX buffers */
				3068	ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
				3069	DMA_FROM_DEVICE);
				3070	if (ret) {
				3071	printk(KERN_INFO "[%s][%d] uart_%d rx_buf_a is error\n",__func__,__LINE__, zup->port.line);
				3072	//dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
				3073	// "RX buffer A", ret);
				3074	goto skip_rx;
				3075	}
				3076
				3077	ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_b,
				3078	DMA_FROM_DEVICE);
				3079	if (ret) {
				3080	printk( "failed to init DMA uart: %d RX buffer B ,ret:%d\n", zup->port.line, ret);
				3081	zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
				3082	DMA_FROM_DEVICE);
				3083	goto skip_rx;
				3084	}
				3085
				3086	zup->using_rx_dma = true;
				3087	zup->sg2tty = NULL;
				3088	zup->sg2tty_len = 0;
				3089	zup->curr_sg = NULL;
				3090	#if RX_DMA_WORK
				3091	timer_setup(&(zup->rx_dma_timer), zx29_uart_rx_dma_timeout, 0);
				3092	hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
				3093	zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout;
				3094	g_hr_interval = ktime_set(0, 1500000);
				3095	zup->dmarx.running = false;
				3096	zup->dmarx.used = false;
				3097	zup->dmarx.use_buf_b = false;
				3098	zup->dmarx.rx_index = 0;
				3099
				3100	zup->pre_pending = 0;
				3101	zup->work_state = false;
				3102
				3103	zup->dma_compl_th = kthread_run(dma_complete_thread, zup, "uart_dma_compl");
				3104	BUG_ON(IS_ERR(zup->dma_compl_th));
				3105	#endif
				3106
				3107	skip_rx:
				3108
				3109	/* Turn on DMA error (RX/TX will be enabled on demand) */
				3110	printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
				3111	zup->dmacr &= ~UART_DMAONERR;
				3112	//zup->dmacr \|= UART_DMAONERR;
				3113	UART_PUT_DMACR(&zup->port, zup->dmacr);
				3114	if(zup->uart_power_mode){
				3115	if (zup->using_rx_dma) {
				3116	//printk(KERN_INFO "[%s][%d]\n",__func__,__LINE__);
				3117	if (zx29_dma_rx_trigger_dma(zup)){
				3118	dev_dbg(zup->port.dev, "could not trigger initial "
				3119	"RX DMA job, fall back to interrupt mode\n");
				3120	}else{
				3121	mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
				3122	zup->pre_pending = 0;
				3123	zup->work_state = true;
				3124	}
				3125	}
				3126	}
				3127	}
				3128	else if(zup->uart_power_mode == 1)
				3129	{
				3130	ret = uart_dma_cycle_init(zup);
				3131	if(ret){
				3132	printk("uart%d dma cycle init failed,ret %d.\n",zup->port.line,ret);
				3133	return;
				3134	}
				3135	zup->using_rx_dma = true;
				3136	zup->sg2tty = NULL;
				3137	zup->sg2tty_len = 0;
				3138	zup->curr_sg = NULL;
				3139	#if RX_DMA_WORK
				3140	hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
				3141	zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout_cyclic;
				3142	g_hr_interval = ktime_set(0, 1500000);
				3143	zup->dmarx.running = false;
				3144	zup->dmarx.used = false;
				3145	zup->dmarx.use_buf_b = false;
				3146	zup->dmarx.rx_index = 0;
				3147	zup->pre_pending = 0;
				3148	zup->work_state = false;
				3149	sema_init(&zup->sema_cyclic, 0);
				3150	zup->dma_compl_th = kthread_run(dma_complete_thread_use_dma_cyclic, zup, "uart_dma_th_cyc");
				3151	BUG_ON(IS_ERR(zup->dma_compl_th));
				3152	#endif
				3153	printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
				3154	zup->dmacr &= ~UART_DMAONERR;
				3155	UART_PUT_DMACR(&zup->port, zup->dmacr);
				3156	if(zup->uart_power_mode){
				3157	if (zup->using_rx_dma) {
				3158	if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)){
				3159	dev_dbg(zup->port.dev, "could not trigger initial "
				3160	"RX DMA job, fall back to interrupt mode\n");
				3161	}else{
				3162	hrtimer_start(&zup->rx_dma_hrtimer, g_hr_interval, HRTIMER_MODE_REL);
				3163	//mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
				3164	zup->pre_pending = 0;
				3165	zup->work_state = true;
				3166	}
				3167	}
				3168	}
				3169	}else
				3170	printk("uart%d power mode set error,dma dont startup.\n",zup->port.line);
				3171	}
				3172
				3173
				3174	#endif
				3175
				3176	static irqreturn_t zx29_uart_rxd_irq(int irq, void *dev_id)
				3177	{
				3178	struct zx29_uart_port zup = (struct zx29_uart_port )dev_id;
				3179
				3180	rxd_wake_cnt++;
				3181	zup->rxd_wakeup = true;
				3182	tasklet_schedule(&zup->write_wakeup);
				3183	zup->rxd_int_depth = 0;
				3184	return IRQ_HANDLED;//IRQ_RETVAL(retval);
				3185	}
				3186
				3187	/****************************************************************************/
				3188	static int zx29_uart_startup(struct uart_port *port)
				3189	{
				3190	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				3191	unsigned long flags = 0;
				3192	unsigned long control = 0;
				3193	int retval = 0;
				3194	struct platform_device *pdev=port->private_data;
				3195	// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				3196	int i = 0,j = 0,iflag = 0;
				3197	struct tty_struct *tty = port->state->port.tty;
				3198	unsigned int ibrd, fbrd,lcr_h, old_cr;
				3199	int ret=0;
				3200	printk("-----zx29_uart_startup, port:%d\n", port->line);
				3201	#if 0//def CONFIG_ARCH_ZX297520V3_WATCH
				3202
				3203	if(port->line == 0)
				3204	{
				3205	gpio_free(pdata->uart_txd.gpionum);
				3206	gpio_free(pdata->uart_rxd.gpionum);
				3207	//printk("gpio_free err err!\n");
				3208	}
				3209
				3210	wmb();
				3211
				3212	#endif
				3213	if(DEBUG_CONSOLE != pdev->id){
				3214	char temp_buf[TASK_COMM_LEN]= {0};
				3215	int th_ctrl = 0;
				3216	if((strlen(get_task_comm(temp_buf,get_current())) > 0) && (strcmp(get_task_comm(temp_buf,get_current()),"at_ctl") != 0))
				3217	th_ctrl = 1;
				3218
				3219	//app ctrl or kernel ctrl set this
				3220	int kernel_ctrl = xp2xp_enable_4line();
				3221	zup->uart_power_mode = (kernel_ctrl \| zup->app_ctrl \| th_ctrl);
				3222	printk("zx29_uart%d open task is %s,power_mode is %d.\n",pdev->id, get_task_comm(temp_buf,get_current()),zup->uart_power_mode);
				3223	if(zup->uart_power_mode){
				3224	//pm_stay_awake(&pdev->dev);
				3225	}
				3226	}
				3227	//when open, clear last statistic info
				3228	port->icount.brk = port->icount.buf_overrun = port->icount.frame = 0;
				3229	port->icount.overrun = port->icount.parity = port->icount.rng = 0;
				3230	port->icount.rx = port->icount.tx = 0;
				3231	/*
				3232	*enable uart clock
				3233	*if uart is used for console, don't need do these, these was done before
				3234	*/
				3235	if (DEBUG_CONSOLE != port->line) {
				3236	/* config uart apb_clk */
				3237	clk_prepare_enable(zup->busclk);
				3238	/* enable uart work clock */
				3239	clk_prepare_enable(zup->wclk);
				3240	}
				3241
				3242	/* Clear all pending error and receive interrupts */
				3243	UART_PUT_ICR(port, 0xfff);
				3244
				3245	/* Allocate the IRQ */
				3246	retval = request_irq(port->irq, zx29_uart_interrupt, 0, "uart-zx29", zup);
				3247	if (retval){
				3248	printk("[UART]unable to attach zx29 UART %d "
				3249	"interrupt vector=%d\n", port->line, port->irq);
				3250	return retval;
				3251	}
				3252
				3253	/* set interrupt fifo level RX:1/2 Full, TX:1/2 Full */
				3254	#if 0//CONFIG_SERIAL_ZX29_DMA
				3255	UART_PUT_IFLS(port, UART_IFLS_RX2_8\|UART_IFLS_TX6_8);
				3256	#else
				3257	UART_PUT_IFLS(port, UART_IFLS_RX2_8\|UART_IFLS_TX4_8);
				3258	#endif
				3259
				3260	#if 0
				3261	/* Provoke TX FIFO interrupt into asserting. */
				3262	control = UART_CR_UARTEN \| UART_CR_TXE \| UART_CR_LBE;
				3263	UART_PUT_CR(port, control);
				3264	UART_PUT_FBRD(port, 0);
				3265	UART_PUT_IBRD(port, 1);
				3266	UART_PUT_LCRH(port, 0);
				3267	UART_PUT_CHAR(port, 0);
				3268	while (UART_GET_FR(port) & UART_FR_TXBUSY)
				3269	barrier();
				3270	#endif
				3271	control = UART_CR_UARTEN \| UART_CR_RXE \| UART_CR_TXE;
				3272	//console & lp_uart don't need dma
				3273	if ((DEBUG_CONSOLE != port->line) && (port->line != 4)) {
				3274	#if CONFIG_SERIAL_ZX29_DMA
				3275	UART_PUT_DMACR(port, UART_TXDMAE \| UART_RXDMAE);
				3276	uart_dma_startup(zup);
				3277	#endif
				3278	}
				3279
				3280	tasklet_init(&zup->write_wakeup, uart_write_wakeup_task, (unsigned long) port);
				3281	if((pdev->id == 0) && (zup->irq_state == 0) && (zup->uart_power_mode == 0)){
				3282	ret = request_irq(zup->rxd_irq,
				3283	zx29_uart_rxd_irq,
				3284	0,
				3285	"uart0_rxd_wake",
				3286	zup);
				3287	if(ret<0){
				3288	panic("request uart0 rxd wake irq fail\n");
				3289	}
				3290	printk("--------rxd wake up interrupt ok\n");
				3291	enable_irq_wake(zup->rxd_irq);
				3292	zup->irq_state = 1;
				3293	zup->rxd_int_depth = 1;
				3294	}
				3295	#if 0
				3296	/configure gpio pin to UART/
				3297	if((pdata->uart_use)/&&(port->line == UART0 )/)
				3298	{
				3299	retval=gpio_request(pdata->uart_rxd.gpionum,pdata->uart_rxd.gpioname);
				3300	if(retval)
				3301	BUG();
				3302	retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_txd.gpioname);
				3303	if(retval)
				3304	BUG();
				3305	/uart rxd/
				3306	zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
				3307	if(pdata->uart_rxd.gpionum == ZX29_GPIO_121 ) {
				3308	//pull up gpio121
				3309	(volatile unsigned int )0xf843c82c \|= 0xf0;
				3310	}
				3311	/uart txd/
				3312	zx29_gpio_config(pdata->uart_txd.gpionum, pdata->uart_txd.gpiofnc);
				3313	#ifdef CONFIG_ARCH_ZX297520V3
				3314	if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 0)){
				3315	zup->irq = platform_get_irq_byname(pdev, "zx29_uart_rxd_wakeup");
				3316	printk(KERN_INFO"zx29_uart_startup,irq:%d,%s.%d\n",zup->irq,pdata->uart_cts.gpioname,zup->irq_state);
				3317	if(zup->irq >= 0){
				3318
				3319	pcu_int_set_type(PCU_UART0_RXD_INT, IRQF_TRIGGER_FALLING);
				3320	pcu_int_clear(PCU_UART0_RXD_INT);
				3321	ret = request_irq(zup->irq, zx29_uart_rxd_irq,
				3322	IRQF_ONESHOT , "uart_rxd_irq",
				3323	zup);
				3324	printk(KERN_INFO"zx29_uart_startup, retval:%d\n",ret);
				3325	irq_set_irq_wake(zup->irq,1);
				3326	#ifdef CONFIG_CPU_IDLE
				3327	zup->rxd_int_depth = rxd_wake_cnt = 0;
				3328	zx_pm_register_callback(uart_0_pm_enter, uart_0_pm_exit);
				3329	disable_irq_nosync(UART0_RXD_INT);
				3330	#endif
				3331	zup->irq_state = 1;
				3332	}else{
				3333	printk("uart_startup, request wake irq fail:%d\n",zup->irq);
				3334	}
				3335	}
				3336	#endif
				3337	if(pdata->uart_ctsrtsuse)
				3338	{
				3339	retval=gpio_request(pdata->uart_cts.gpionum,pdata->uart_cts.gpioname);
				3340	if(retval)
				3341	BUG();
				3342
				3343	retval=gpio_request(pdata->uart_rts.gpionum,pdata->uart_rts.gpioname);
				3344	if(retval)
				3345	BUG();
				3346	/uart cts/
				3347	zx29_gpio_config(pdata->uart_cts.gpionum, pdata->uart_cts.gpiofnc);
				3348	/uart rts/
				3349	zx29_gpio_config(pdata->uart_rts.gpionum, pdata->uart_rts.gpiofnc);
				3350
				3351	control \|= (UART_CR_RTSEN \|UART_CR_CTSEN );
				3352	control \|= UART_CR_RTS; //wl write1 for allow send
				3353	}
				3354	zup->autobaud = pdata->uart_abauduse ;
				3355	}
				3356	#if 0
				3357	if((pdata->uart_use)&&(port->line == UART1 ))
				3358	{
				3359	retval=gpio_request(pdata->uart_rx.gpionum,pdata->uart_rx.gpioname);
				3360	if(retval)
				3361	BUG();
				3362	retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_tx.gpioname);
				3363	if(retval)
				3364	BUG();
				3365	/uart rxd/
				3366	zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
				3367	/uart txd/
				3368	zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
				3369
				3370	if(pdata->uart_ctsrtsuse)
				3371	{
				3372	retval=gpio_request(pdata->uart_ctsnum,"uart1_cts");
				3373	if(retval)
				3374	BUG();
				3375	retval=gpio_request(pdata->uart_rtsnum,"uart1_rts");
				3376	if(retval)
				3377	BUG();
				3378	/uart cts/
				3379	zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
				3380	/uart rts/
				3381	zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
				3382
				3383	control \|= (UART_CR_RTSEN \|UART_CR_CTSEN );
				3384	control \|= UART_CR_RTS; //wl write1 for allow send
				3385	}
				3386	zup->autobaud = pdata->uart_abauduse;
				3387	}
				3388	if((pdata->uart_use)&&(port->line == UART2 ))
				3389	{
				3390	retval=gpio_request(pdata->uart_rxdnum,"uart2_rxd");
				3391	if(retval)
				3392	BUG();
				3393	retval=gpio_request(pdata->uart_txdnum,"uart2_txd");
				3394	if(retval)
				3395	BUG();
				3396
				3397	/uart rxd/
				3398	zx29_gpio_config(pdata->uart_rxdnum, pdata->uart_rxdfnc);
				3399	if(pdata->uart_rxdnum == ZX29_GPIO_121 ) {
				3400	//pull up gpio121
				3401	(volatile unsigned int )0xf843c82c \|= 0xf0;
				3402	}
				3403	/uart txd/
				3404	zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
				3405
				3406	if(pdata->uart_ctsrtsuse)
				3407	{
				3408	retval=gpio_request(pdata->uart_ctsnum,"uart2_cts");
				3409	if(retval)
				3410	BUG();
				3411
				3412	retval=gpio_request(pdata->uart_rtsnum,"uart2_rts");
				3413	if(retval)
				3414	BUG();
				3415	/uart cts/
				3416	zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
				3417	/uart rts/
				3418	zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
				3419
				3420	control \|= (UART_CR_RTSEN \|UART_CR_CTSEN );
				3421	control \|= UART_CR_RTS; //wl write1 for allow send
				3422	}
				3423	zup->autobaud = pdata->uart_abauduse ;
				3424	}
				3425	#endif
				3426	#endif
				3427	zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
				3428	UART_PUT_CR(port, control);
				3429
				3430	/*
				3431	* Finally, enable interrupts, only timeouts when using DMA
				3432	* if initial RX DMA job failed, start in interrupt mode
				3433	* as well.
				3434	*/
				3435	spin_lock_irqsave(&zup->port.lock, flags);
				3436	/* Clear out any spuriously appearing RX interrupts */
				3437	UART_PUT_ICR(port, (UART_RTIS \| UART_RXIS));
				3438	//when dma not running,set UART_RTIM \| UART_RXIM
				3439	if(!zx29_dma_rx_running(zup)){
				3440	zup->imr = UART_RTIM \| UART_RXIM;
				3441	UART_PUT_IMSC(port, zup->imr);
				3442	}
				3443	#if CONFIG_SERIAL_ZX29_DMA
				3444	zup->port_close = false;
				3445	#endif
				3446	spin_unlock_irqrestore(&zup->port.lock, flags);
				3447
				3448
				3449	return 0;
				3450	}
				3451
				3452	/****************************************************************************/
				3453	static void zx29_uart_shutdown(struct uart_port *port)
				3454	{
				3455	printk("zx29_uart%d_shutdown.\n",port->line);
				3456	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				3457	unsigned long flags;
				3458	uint32_t val;
				3459	int retval = 0;
				3460	struct platform_device *pdev=port->private_data;
				3461	//struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				3462	#if CONFIG_SERIAL_ZX29_DMA
				3463	zup->port_close = true;
				3464	up(&zup->sema);
				3465	#endif
				3466	int ret;
				3467	tasklet_kill(&zup->write_wakeup);
				3468	#if RX_DMA_WORK
				3469	if(zx29_dma_rx_work_scheduled(zup)){
				3470	ret = del_timer_sync(&(zup->rx_dma_timer));
				3471	ret = hrtimer_cancel(&zup->rx_dma_hrtimer);
				3472	zup->work_state = 0;
				3473	}
				3474	#endif
				3475	/* Disable and clear all interrupts now */
				3476	spin_lock_irqsave(&port->lock, flags);
				3477	zup->imr = 0;
				3478	UART_PUT_IMSC(port, zup->imr);
				3479	UART_PUT_ICR(port, 0xFFFF);
				3480
				3481	spin_unlock_irqrestore(&port->lock, flags);
				3482	#if CONFIG_SERIAL_ZX29_DMA
				3483	zx29_dma_shutdown(zup);
				3484	#endif
				3485	/* Free the interrupt */
				3486	free_irq(zup->port.irq, zup);
				3487
				3488	/* Disable UART transmitter and receiver */
				3489	zup->autorts = false;
				3490	val = UART_GET_CR(port);
				3491	if (val & UART_CR_RTS) {
				3492	zup->rts_state = true;
				3493	val = UART_CR_RTS;
				3494	} else
				3495	zup->rts_state = false;
				3496	val = UART_CR_UARTEN \| UART_CR_TXE;
				3497	UART_PUT_CR(port, val);
				3498
				3499	/* disable break condition and fifos */
				3500	val = UART_GET_LCRH(port);
				3501	val &= ~(UART_LCRH_BRK \| UART_LCRH_FEN);
				3502	UART_PUT_LCRH(port, val);
				3503	if(zup->uart_power_mode){
				3504	//pm_relax(&pdev->dev);
				3505	zup->app_ctrl = 0;
				3506	zup->uart_power_mode = 0;
				3507	}
				3508
				3509	if((pdev->id == 0) && (zup->irq_state == 1) && (zup->uart_power_mode == 0)){
				3510	free_irq(zup->rxd_irq, zup);
				3511	disable_irq_wake(zup->rxd_irq);
				3512	zup->irq_state = 0;
				3513	}
				3514
				3515	#if 0
				3516	if(pdata->uart_use)
				3517	{
				3518	if(pdata->uart_ctsrtsuse)
				3519	{
				3520	gpio_free(pdata->uart_cts.gpionum);
				3521	gpio_free(pdata->uart_rts.gpionum);
				3522	}
				3523	#ifdef CONFIG_ARCH_ZX297520V3
				3524	if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 1)){
				3525	printk(KERN_INFO"zx29_uart_shutdown,irq:%d,%s\n",zup->irq,pdata->uart_cts.gpioname);
				3526	if(zup->irq){
				3527	free_irq(zup->irq, zup);
				3528	pcu_int_clear(PCU_UART0_RXD_INT);
				3529	irq_set_irq_wake(zup->irq, 0);
				3530	zup->irq_state = 0;
				3531	zup->rxd_int_depth = 0;
				3532	}
				3533	}
				3534	#endif
				3535	gpio_free(pdata->uart_rxd.gpionum);
				3536	gpio_free(pdata->uart_txd.gpionum);
				3537
				3538	#ifdef CONFIG_ARCH_ZX297520V3_WATCH
				3539	if(port->line == 0)
				3540	{
				3541	retval = gpio_request(pdata->uart_txd.gpionum, pdata->uart_txd.gpioname);
				3542	if(retval)
				3543	{
				3544	BUG();
				3545	}
				3546	zx29_gpio_config(pdata->uart_txd.gpionum, GPIO30_GPIO30);
				3547	gpio_direction_input(pdata->uart_txd.gpionum);
				3548
				3549	retval = gpio_request(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpioname);
				3550	if(retval)
				3551	{
				3552	BUG();
				3553	}
				3554	zx29_gpio_config(pdata->uart_rxd.gpionum, GPIO29_GPIO29);
				3555	gpio_direction_input(pdata->uart_rxd.gpionum);
				3556	}
				3557	#endif
				3558
				3559	}
				3560	#endif
				3561	/* Shutdown uart clock */
				3562	}
				3563
				3564	/****************************************************************************/
				3565	static void zx29_uart_set_termios(struct uart_port port, struct ktermios termios,
				3566	struct ktermios *old)
				3567	{
				3568	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				3569	unsigned int lcr_h, old_cr;
				3570	unsigned long flags;
				3571	unsigned int baud, ibrd, fbrd,j;
				3572
				3573	//temple change,using setting from cmm script
				3574	//if(port->line == DEBUG_CONSOLE)
				3575	//return;
				3576
				3577	/* Set baud rate */
				3578	/* Ask the core to calculate the divisor for us. */
				3579	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
				3580	printk("uart port %d baud is %d.\n",port->line,baud);
				3581
				3582	//this should not hapend
				3583	if(baud == 0)
				3584	BUG_ON(1);
				3585	zup->baudrate = baud;
				3586	ibrd = port->uartclk / (baud<<4);
				3587	fbrd = ((port->uartclk % (baud<<4) )8 + baud)/(2baud);
				3588	UART_PUT_FBRD(port, fbrd);
				3589	UART_PUT_IBRD(port, ibrd);
				3590
				3591	printk("-------zx29_uart_set_termios,line:%d, new baud:%d, uartclk:%d,ibrd:%d, fbrd:%d \n", port->line,
				3592	baud, port->uartclk, ibrd, fbrd);
				3593
				3594	switch (termios->c_cflag & CSIZE) {
				3595	case CS5:
				3596	lcr_h = UART_LCRH_WLEN_5;
				3597	break;
				3598	case CS6:
				3599	lcr_h = UART_LCRH_WLEN_6;
				3600	break;
				3601	case CS7:
				3602	lcr_h = UART_LCRH_WLEN_7;
				3603	break;
				3604	default: // CS8
				3605	lcr_h = UART_LCRH_WLEN_8;
				3606	break;
				3607	}
				3608	if (termios->c_cflag & CSTOPB)
				3609	lcr_h \|= UART_LCRH_STP2;
				3610	if (termios->c_cflag & PARENB) {
				3611	lcr_h \|= UART_LCRH_PEN;
				3612	if (!(termios->c_cflag & PARODD))
				3613	lcr_h \|= UART_LCRH_EPS;
				3614	}
				3615	if (port->fifosize > 1)
				3616	lcr_h \|= UART_LCRH_FEN;
				3617
				3618	spin_lock_irqsave(&port->lock, flags);
				3619
				3620	/*
				3621	* Update the per-port timeout.
				3622	*/
				3623	uart_update_timeout(port, termios->c_cflag, baud);
				3624
				3625	port->read_status_mask = UART_DR_OE \| 255;
				3626	if (termios->c_iflag & INPCK)
				3627	port->read_status_mask \|= UART_DR_FE \| UART_DR_PE;
				3628	if (termios->c_iflag & (BRKINT \| PARMRK))
				3629	port->read_status_mask \|= UART_DR_BE;
				3630
				3631	/*
				3632	* Characters to ignore
				3633	*/
				3634	port->ignore_status_mask = 0;
				3635	if (termios->c_iflag & IGNPAR)
				3636	port->ignore_status_mask \|= UART_DR_FE \| UART_DR_PE;
				3637	if (termios->c_iflag & IGNBRK) {
				3638	port->ignore_status_mask \|= UART_DR_BE;
				3639	/*
				3640	* If we're ignoring parity and break indicators,
				3641	* ignore overruns too (for real raw support).
				3642	*/
				3643	if (termios->c_iflag & IGNPAR)
				3644	port->ignore_status_mask \|= UART_DR_OE;
				3645	}
				3646
				3647	/*
				3648	* Ignore all characters if CREAD is not set.
				3649	*/
				3650	if ((termios->c_cflag & CREAD) == 0)
				3651	port->ignore_status_mask \|= UART_DUMMY_DR_RX;
				3652
				3653	if (UART_ENABLE_MS(port, termios->c_cflag))
				3654	zx29_uart_enable_ms(port);
				3655
				3656	/* first, disable everything */
				3657	old_cr = UART_GET_CR(port);
				3658	UART_PUT_CR(port, 0);
				3659
				3660	if (termios->c_cflag & CRTSCTS) {
				3661	if (old_cr & UART_CR_RTS)
				3662	old_cr \|= UART_CR_RTSEN;
				3663
				3664	old_cr \|= UART_CR_CTSEN;
				3665	port->status \|= UPSTAT_AUTOCTS \| UPSTAT_AUTORTS;
				3666	zup->autorts = true;
				3667	} else {
				3668	old_cr &= ~(UART_CR_CTSEN \| UART_CR_RTSEN);
				3669	zup->autorts = false;
				3670	port->status &= ~(UPSTAT_AUTOCTS \| UPSTAT_AUTORTS);
				3671	}
				3672
				3673	/*
				3674	* ----------v----------v----------v----------v-----
				3675	* NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
				3676	* ----------^----------^----------^----------^-----
				3677	*/
				3678	UART_PUT_LCRH(port, lcr_h);
				3679	UART_PUT_CR(port, old_cr);
				3680
				3681	spin_unlock_irqrestore(&port->lock, flags);
				3682	if( zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
				3683	{
				3684	msleep(50);
				3685	zup->port.icount.rx = 0;
				3686
				3687	for( j = 0; j<UART_AT_SENDOK_NUM; j++)
				3688	{
				3689	while (UART_GET_FR(port) & UART_FR_TXFF)
				3690	barrier();
				3691	UART_PUT_CHAR(&zup->port, UART_AT_send_ok[j]);
				3692	}
				3693
				3694	zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
				3695	}
				3696	}
				3697
				3698	/****************************************************************************/
				3699	static const char zx29_uart_type(struct uart_port port)
				3700	{
				3701	return (port->type == PORT_ZX29) ? "zx29_UART" : NULL;
				3702	}
				3703
				3704	/****************************************************************************/
				3705
				3706	static int zx29_uart_request_port(struct uart_port *port)
				3707	{
				3708	/* UARTs always present */
				3709	// return request_mem_region(port->mapbase, SZ_4K, "uart-zx29")!= NULL ? 0 : -EBUSY;
				3710	return 0;
				3711	}
				3712
				3713	/****************************************************************************/
				3714	static void zx29_uart_config_port(struct uart_port *port, int flags)
				3715	{
				3716	if (flags & UART_CONFIG_TYPE) {
				3717	port->type = PORT_ZX29;
				3718	zx29_uart_request_port(port);
				3719	}
				3720	}
				3721
				3722	/****************************************************************************/
				3723
				3724	static void zx29_uart_release_port(struct uart_port *port)
				3725	{
				3726	// release_mem_region(port->mapbase, SZ_4K);
				3727	}
				3728
				3729	/****************************************************************************/
				3730
				3731	static int zx29_uart_verify_port(struct uart_port port, struct serial_struct ser)
				3732	{
				3733	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ZX29))
				3734	return -EINVAL;
				3735	return 0;
				3736	}
				3737
				3738
				3739	void zx29_uart_putc(struct uart_port *port, int c)
				3740	{
				3741	while (UART_GET_FR(port) & UART_FR_TXFF)
				3742	barrier();
				3743	UART_PUT_CHAR(port, c);
				3744	}
				3745
				3746
				3747	#ifdef CONFIG_CONSOLE_POLL
				3748	/****************************************************************************/
				3749	static int zx29_get_poll_char(struct uart_port *port)
				3750	{
				3751	if (UART_GET_FR(port) & UART_FR_RXFE)
				3752	return NO_POLL_CHAR;
				3753
				3754	return UART_PUT_CHAR(port);
				3755	}
				3756
				3757	/****************************************************************************/
				3758	static void zx29_put_poll_char(struct uart_port *port, unsigned char ch)
				3759	{
				3760	while (UART_GET_FR(port) & UART_FR_TXFF)
				3761	barrier();
				3762	UART_PUT_CHAR(port, ch);
				3763	}
				3764	#endif /* CONFIG_CONSOLE_POLL */
				3765	static void zx29_uart_throttle_rx(struct uart_port *port)
				3766	{
				3767	unsigned long flags;
				3768	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				3769	dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
				3770	while(zx29_dma_get_transfer_num(rx_id) != 4096)
				3771	msleep(1);
				3772	spin_lock_irqsave(&port->lock, flags);
				3773	zup->dmacr &= ~UART_RXDMAE;
				3774	UART_PUT_DMACR(&zup->port,zup->dmacr);
				3775	zx29_dma_stop(rx_id);
				3776	zup->dmarx.running = false;
				3777	zup->dmarx.used = false;
				3778	spin_unlock_irqrestore(&port->lock, flags);
				3779	}
				3780	static void zx29_uart_unthrottle_rx(struct uart_port *port)
				3781	{
				3782	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				3783	unsigned long flags;
				3784	spin_lock_irqsave(&port->lock, flags);
				3785	if (zx29_dma_rx_trigger_dma(zup)) {
				3786	printk("rx_dma_chars RXDMA start fail\n");
				3787	zup->imr \|= (UART_RTIM\|UART_RXIM);
				3788	UART_PUT_IMSC(&zup->port,zup->imr);
				3789	}else{
				3790	uart_mod_timer(zup, &flags);
				3791	zup->pre_pending = 0;
				3792	zup->dmarx.used = true;
				3793	zup->work_state = true;
				3794	UART_PUT_ICR(&zup->port,(UART_RTIS\|UART_RXIS));
				3795	}
				3796	spin_unlock_irqrestore(&port->lock, flags);
				3797	}
				3798
				3799	/****************************************************************************/
				3800	/*
				3801	* Define the basic serial functions we support.
				3802	*/
				3803	static const struct uart_ops zx29_uart_ops = {
				3804	.tx_empty = zx29_uart_tx_empty,
				3805	.set_mctrl = zx29_uart_set_mctrl,
				3806	.get_mctrl = zx29_uart_get_mctrl,
				3807	.start_tx = zx29_uart_start_tx,
				3808	.stop_tx = zx29_uart_stop_tx,
				3809	.stop_rx = zx29_uart_stop_rx,
				3810	.throttle = zx29_uart_throttle_rx,
				3811	.unthrottle = zx29_uart_unthrottle_rx,
				3812	.enable_ms = zx29_uart_enable_ms,
				3813	.break_ctl = zx29_uart_break_ctl,
				3814	.startup = zx29_uart_startup,
				3815	.shutdown = zx29_uart_shutdown,
				3816	.set_termios = zx29_uart_set_termios,
				3817	#if CONFIG_SERIAL_ZX29_DMA
				3818	.flush_buffer = zx29_dma_flush_buffer,
				3819	#endif
				3820	.type = zx29_uart_type,
				3821	.request_port = zx29_uart_request_port,
				3822	.release_port = zx29_uart_release_port,
				3823	.config_port = zx29_uart_config_port,
				3824	.verify_port = zx29_uart_verify_port,
				3825	#ifdef CONFIG_CONSOLE_POLL
				3826	.poll_get_char = zx29_get_poll_char,
				3827	.poll_put_char = zx29_put_poll_char,
				3828	#endif
				3829
				3830	};
				3831
				3832
				3833	/****************************************************************************/
				3834	static int zx29_init_ports(struct zx29_uart_port *zx29_port,
				3835	struct platform_device *pdev)
				3836	{
				3837	int ret = 0;
				3838	struct uart_port *port=&zx29_port->port;
				3839	unsigned int offset=(unsigned int)(pdev->id);
				3840	struct device_node *np = pdev->dev.of_node;
				3841	unsigned int baud, ibrd, fbrd;
				3842	/cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start/
				3843	unsigned int max_bus_clk;
				3844	/cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end/
				3845	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
				3846	//struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
				3847
				3848	if(!regs){
				3849	dev_err(&pdev->dev, "zx29_init_ports, get resource fail,\n");
				3850	return -ENODEV;
				3851	}
				3852	/get apb clock/
				3853	zx29_port->busclk = devm_clk_get(&pdev->dev, UART_APBCLK_NAME);
				3854	if (IS_ERR(zx29_port->busclk)) {
				3855	ret = PTR_ERR(zx29_port->busclk);
				3856	printk("failed to get zx29_port->busclk: %d\n", ret);
				3857	return ret;
				3858	}
				3859
				3860	/get work clock/
				3861	zx29_port->wclk = devm_clk_get(&pdev->dev, UART_WCLK_NAME);
				3862
				3863	if (IS_ERR(zx29_port->wclk)) {
				3864	ret = PTR_ERR(zx29_port->wclk);
				3865	printk("failed to get zx29_port->wclk: %d\n", ret);
				3866	return ret;
				3867	}
				3868	/cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start/
				3869	if(0 == pdev->id \|\| 2 == pdev->id){
				3870	device_property_read_u32(&pdev->dev, "uart-max-bus-freq", &max_bus_clk);
				3871	clk_set_rate(zx29_port->wclk, max_bus_clk);
				3872	}
				3873	/cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end/
				3874	if(offset == 0){
				3875	clk_set_rate(zx29_port->wclk, 104 * 1000000);
				3876	}
				3877	port->line = offset;
				3878	port->type = PORT_ZX29;
				3879	port->fifosize = UART_TXFIFO_SIZE;
				3880	//port->iotype = UPIO_MEM;
				3881	//port->irq = irq->start;
				3882	port->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
				3883	if(pdev->id == 0){
				3884	zx29_port->rxd_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
				3885	}
				3886	//port->membase = devm_ioremap_nocache(&pdev->dev, regs->start,
				3887	// resource_size(regs));
				3888	port->membase = devm_platform_ioremap_resource(pdev, 0);
				3889
				3890	if (!port->membase)
				3891	return -ENODEV;
				3892	port->mapbase = regs->start;
				3893	port->mapsize = resource_size(regs);
				3894
				3895	//port->flags = UPF_BOOT_AUTOCONF;
				3896	port->ops = &zx29_uart_ops;
				3897	port->uartclk = clk_get_rate(zx29_port->wclk);
				3898
				3899	port->private_data = pdev;
				3900	//here is temple def
				3901	if(port->uartclk == 0){
				3902	printk("---zx29_init_ports, uartclk hard set to 26M\n");
				3903	/cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 start/
				3904	if(0 == pdev->id \|\| 2 == pdev->id)
				3905	port->uartclk = 104000000;
				3906	else
				3907	/cz.li add for uart1 2 change baudrate to 4M on 2023/8/15 end/
				3908	port->uartclk = 26000000;
				3909	}
				3910	printk("---zx29_init_ports, line:%d, irq:%d, membase:%08x, uartclk:%d\n", port->line, port->irq, port->membase, port->uartclk);
				3911	/*
				3912	* just configure clock,
				3913	* actually pin configuration is needed, but now gpio driver is not OK
				3914	* use bootloader default configuration
				3915	*/
				3916	if(DEBUG_CONSOLE == pdev->id){
				3917	/* config uart apb_clk */
				3918	clk_prepare_enable(zx29_port->busclk);
				3919
				3920	/* enable uart work clock */
				3921	clk_prepare_enable(zx29_port->wclk);
				3922	}
				3923	return 0;
				3924	}
				3925
				3926
				3927	#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
				3928
				3929	#if VEHICLE_USE_ONE_UART_LOG
				3930	static void zx29_uart_console_putc(struct uart_port *port, int c)
				3931	{
				3932	if(g_core_id_occupy_uart == SYMB_PS_CORE_ID)
				3933	return;
				3934	int ret = soft_spin_lock_printf(UART_SFLOCK);
				3935	if(ret)
				3936	return;
				3937	while (UART_GET_FR(port) & UART_FR_TXFF)
				3938	barrier();
				3939	UART_PUT_CHAR(port, c);
				3940	soft_spin_unlock(UART_SFLOCK);
				3941	}
				3942	#else
				3943	static void zx29_uart_console_putc(struct uart_port *port, int c)
				3944	{
				3945	while (UART_GET_FR(port) & UART_FR_TXFF)
				3946	barrier();
				3947	UART_PUT_CHAR(port, c);
				3948	}
				3949
				3950	#endif
				3951
				3952
				3953
				3954	/****************************************************************************/
				3955	static void zx29_uart_console_write(struct console co, const char s, unsigned int count)
				3956	{
				3957	struct uart_port *port = &zx29_uart_ports[co->index].port;
				3958
				3959	//spin_lock(&port->lock);
				3960	for (; (count); count--, s++) {
				3961	zx29_uart_console_putc(port, *s);
				3962	if (*s == '\n')
				3963	zx29_uart_console_putc(port, '\r');
				3964	}
				3965
				3966	//spin_unlock(&port->lock);
				3967	}
				3968
				3969	/***************************************************************************
				3970	* If the port was already initialised (eg, by a boot loader),
				3971	* try to determine the current setup.
				3972	****************************************************************************/
				3973	static void __init zx29_console_get_options(struct uart_port port, int baud,
				3974	int parity, int bits)
				3975	{
				3976	if (UART_GET_CR(port) & UART_CR_UARTEN) {
				3977	unsigned int lcr_h, ibrd, fbrd;
				3978
				3979	lcr_h = UART_GET_LCRH(port);
				3980	*parity = 'n';
				3981	if (lcr_h & UART_LCRH_PEN) {
				3982	if (lcr_h & UART_LCRH_EPS)
				3983	*parity = 'e';
				3984	else
				3985	*parity = 'o';
				3986	}
				3987	if ((lcr_h & 0x60) == UART_LCRH_WLEN_7)
				3988	*bits = 7;
				3989	else
				3990	*bits = 8;
				3991
				3992	ibrd = UART_GET_IBRD(port);
				3993	fbrd = UART_GET_FBRD(port);
				3994
				3995	baud = port->uartclk 8 / (168 ibrd + 2*fbrd-1);
				3996	}
				3997	}
				3998
				3999	/****************************************************************************/
				4000	static int __init zx29_uart_console_setup(struct console co, char options)
				4001	{
				4002	printk("zx29_uart_console_setup.\n");
				4003	struct uart_port *port;
				4004	int baud = 115200;
				4005	int bits = 8;
				4006	int parity = 'n';
				4007	int flow = 'n';
				4008	unsigned int uart_cr = 0;
				4009
				4010	if ((co->index < 0) \|\| (co->index >= zx29_MAXPORTS))
				4011	co->index = CONFIG_UART_CONSOLE_ID;
				4012
				4013	port = &zx29_uart_ports[co->index].port;
				4014	if (port->membase == NULL)
				4015	return -ENODEV;
				4016
				4017	uart_cr = UART_GET_CR(port);
				4018	uart_cr \|= UART_CR_UARTEN \| UART_CR_TXE;
				4019	UART_PUT_CR(port,uart_cr);
				4020
				4021	if (options)
				4022	uart_parse_options(options, &baud, &parity, &bits, &flow);
				4023	else
				4024	zx29_console_get_options(port, &baud, &parity, &bits);
				4025
				4026	return uart_set_options(port, co, baud, parity, bits, flow);
				4027	}
				4028
				4029	/****************************************************************************/
				4030
				4031	static struct uart_driver zx29_uart_driver;
				4032	int zx29_get_console_index(void)
				4033	{
				4034	#if 0
				4035	int dev_cnt = zx29_device_table_num;
				4036	int idx = 0;
				4037	struct platform_device *pdev = NULL;
				4038	for(idx = 0; idx < dev_cnt; idx++)
				4039	{
				4040	pdev = zx29_device_table[idx];
				4041	if(strcmp(pdev->name,"zx29_uart") == 0 && pdev->id == CONFIG_UART_CONSOLE_ID)
				4042	return idx;
				4043	}
				4044	#endif
				4045	return CONFIG_UART_CONSOLE_ID;
				4046	//return -1;
				4047	}
				4048	static struct console zx29_uart_console = {
				4049	.name = "ttyS",
				4050	.write = zx29_uart_console_write,
				4051	.device = uart_console_device,
				4052	.setup = zx29_uart_console_setup,
				4053	.flags = CON_PRINTBUFFER,
				4054	.index = -1,
				4055	.data = &zx29_uart_driver,
				4056	};
				4057	static int __init zx29_uart_console_init(void)
				4058	{
				4059	int console_dev_id = zx29_get_console_index();
				4060
				4061	if(console_dev_id < 0){
				4062	printk("console init fail, uart config fail, console_dev_id is: %d", console_dev_id);
				4063	return -1;
				4064	}
				4065	//zx29_init_ports(&zx29_uart_ports[DEBUG_CONSOLE], zx29_device_table[console_dev_id]);
				4066	register_console(&zx29_uart_console);
				4067	pr_info("[UART]register_console: zx29 console registered!\n");
				4068
				4069	return 0;
				4070	}
				4071
				4072	//console_initcall(zx29_uart_console_init);
				4073
				4074	#define zx29_UART_CONSOLE (&zx29_uart_console)
				4075
				4076
				4077	static void zx29_uart_early_write(struct console con, const char s, unsigned n)
				4078	{
				4079	struct earlycon_device *dev = con->data;
				4080
				4081	uart_console_write(&dev->port, s, n, zx29_uart_console_putc);
				4082	}
				4083
				4084	static int __init zx29_uart_early_console_setup(struct earlycon_device *device,
				4085	const char *opt)
				4086	{
				4087	if (!device->port.membase)
				4088	return -ENODEV;
				4089
				4090	device->con->write = zx29_uart_early_write;
				4091
				4092	return 0;
				4093	}
				4094
				4095	OF_EARLYCON_DECLARE(zx29_uart, "zxic,zx29-uart", zx29_uart_early_console_setup);
				4096	#else
				4097	#define zx29_UART_CONSOLE NULL
				4098	#endif /* CONFIG_zx29_UART_CONSOLE */
				4099	static void zx29_uart_pin_ctrl(struct platform_device *pdev)
				4100	{
				4101	struct pinctrl *pin_ctrl;
				4102	struct pinctrl_state *state0;
				4103	pin_ctrl = devm_pinctrl_get(&pdev->dev);
				4104	switch(pdev->id){
				4105	case 0:
				4106	printk("zx29_uart %d use default pinctrl.",pdev->id);
				4107	break;
				4108	case 1:
				4109	printk("zx29_uart %d use default pinctrl.",pdev->id);
				4110	break;
				4111
				4112	case 2:
				4113	if(IS_ERR(pin_ctrl)){
				4114	dev_warn(&pdev->dev, "fail to get uart2 pins.");
				4115	pin_ctrl = NULL;
				4116	return;
				4117	}
				4118	state0 = pinctrl_lookup_state(pin_ctrl, "default");
				4119	if(IS_ERR(state0)){
				4120	dev_err(&pdev->dev, "uart2 pinstate get fail.\n");
				4121	}
				4122	if(pinctrl_select_state(pin_ctrl, state0)){
				4123	dev_err(&pdev->dev, "uart2 select pinstate fail.\n");
				4124	}
				4125	break;
				4126	}
				4127	}
				4128
				4129	/*
				4130	* Define the zx29 UART driver structure.
				4131	*/
				4132	static struct uart_driver zx29_uart_driver = {
				4133	.owner = THIS_MODULE,
				4134	.driver_name = "zx29_uart",
				4135	.dev_name = "ttyS",
				4136	.major = SERIAL_zx29_MAJOR,
				4137	.minor = SERIAL_MINOR_START,
				4138	.nr = zx29_MAXPORTS,
				4139	.cons = zx29_UART_CONSOLE,
				4140	};
				4141
				4142	unsigned char uart_wakelock_name[zx29_MAXPORTS][20]={{0}};
				4143	/****************************************************************************/
				4144
				4145
				4146	#ifdef CONFIG_PM_SLEEP
				4147	static int zx29_uart_suspend(struct device *dev)
				4148	{
				4149	int ret = 0;
				4150	struct zx29_uart_port *zup = dev_get_drvdata(dev);
				4151	unsigned int flags;
				4152	if (!zup)
				4153	return -EINVAL;
				4154	if(zup->port.line == UART1)
				4155	return 0;
				4156	#if 1
				4157	pinctrl_pm_select_sleep_state(dev);
				4158	#endif
				4159
				4160	printk("zx29_uart%d suspend.\n",zup->port.line);
				4161
				4162	raw_spin_lock_irqsave(&zup->port.lock, flags);
				4163	zup->enter_suspend = 1;
				4164	if(zup->port.line == UART2){
				4165	zx29_dma_stop(DMA_CH_UART2_RX);
				4166	zx29_dma_stop(DMA_CH_UART2_TX);
				4167	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				4168	return 0;
				4169	}
				4170
				4171	zx29_dma_stop(DMA_CH_UART0_RX);
				4172	zx29_dma_stop(DMA_CH_UART0_TX);
				4173	raw_spin_unlock_irqrestore(&zup->port.lock, flags);
				4174	#if 0
				4175	ret = irq_set_irq_type(unsigned int irq, unsigned int type);
				4176
				4177	#endif
				4178	//pcu_int_clear(PCU_UART0_RXD_INT);
				4179	if(zup->irq_state && (zup->rxd_int_depth == 0)){
				4180	struct irq_data *data_rxd;
				4181	data_rxd= irq_get_irq_data(zup->rxd_irq);
				4182	if(data_rxd){
				4183	if(irqd_irq_disabled(data_rxd))
				4184	enable_irq(zup->rxd_irq);
				4185	}
				4186	zup->rxd_int_depth = 1;
				4187	}
				4188
				4189	return 0;
				4190	}
				4191
				4192	static int zx29_uart_resume(struct device *dev)
				4193	{
				4194	struct zx29_uart_port *zup = dev_get_drvdata(dev);
				4195
				4196	if (!zup)
				4197	return -EINVAL;
				4198	int uart_id = zup->port.line;
				4199	if(zup->port.line == UART1)
				4200	return 0;
				4201	#if 1
				4202	pinctrl_pm_select_default_state(dev);
				4203	#endif
				4204
				4205	printk("zx29_uart%d resume.\n",zup->port.line);
				4206
				4207	zup->enter_suspend = 0;
				4208	uart_dma_cycle[uart_id].from_resume = 1;
				4209	return 0;
				4210	}
				4211
				4212
				4213	#endif
				4214
				4215	static SIMPLE_DEV_PM_OPS(zx29_uart_dev_pm_ops, zx29_uart_suspend, zx29_uart_resume);
				4216
				4217
				4218
				4219	static int zx29_uart_probe(struct platform_device *pdev)
				4220	{
				4221	int ret=0;
				4222	int error;
				4223	char wakelock_name[20];
				4224	struct device_node *np = pdev->dev.of_node;
				4225	ret = of_alias_get_id(np, "uart");
				4226
				4227	if(ret < 0){
				4228	printk("-----zx29_uart_probe,of_alias_get_id fail ret:%d\n", ret);
				4229	return -ENODEV;
				4230	}
				4231	pdev->id = ret;
				4232	printk("-----zx29_uart_probe,ret:%d\n", ret);
				4233	// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
				4234	struct zx29_uart_port *port = &zx29_uart_ports[pdev->id];
				4235
				4236
				4237	#if 0//def CONFIG_SERIAL_ZX29_UART_CONSOLE
				4238	if(DEBUG_CONSOLE != pdev->id){
				4239	ret = zx29_init_ports(port,pdev);
				4240	}
				4241	#else
				4242	ret = zx29_init_ports(port,pdev);
				4243
				4244	#endif
				4245	if(ret < 0){
				4246	printk("-----zx29_uart_probe,zx29_init_ports fail ret:%d\n", ret);
				4247	}
				4248	zx29_uart_pin_ctrl(pdev);
				4249	#if CONFIG_SERIAL_ZX29_DMA
				4250	if((DEBUG_CONSOLE != pdev->id ) && (pdev->id != 4))
				4251	{
				4252	uart_dma_init(port);
				4253	printk(KERN_INFO "[%s][%d]UART_%d DMA is OPENED\n",__func__,__LINE__,pdev->id);
				4254	}
				4255	#endif
				4256	ret = 0;
				4257	ret=uart_add_one_port(&zx29_uart_driver, &port->port);
				4258
				4259	if(ret)
				4260	{
				4261	#if CONFIG_SERIAL_ZX29_DMA
				4262	zx29_dma_remove(port);
				4263	#endif
				4264	return ret;
				4265	}
				4266	#if CONFIG_SERIAL_ZX29_DMA
				4267	sema_init(&port->sema, 0);
				4268	#endif
				4269
				4270	platform_set_drvdata(pdev, port);
				4271
				4272	if(pdev->id == DEBUG_CONSOLE){
				4273	//g_console_open_flag = pdata->uart_input_enable ? pdata->uart_input_enable : 0;
				4274	error = device_create_file(&pdev->dev, &dev_attr_console_input);
				4275	#if VEHICLE_USE_ONE_UART_LOG
				4276	error = device_create_file(&pdev->dev, &dev_attr_console_uart_toggle);
				4277	error = device_create_file(&pdev->dev, &dev_attr_coreid_occupy_uart);
				4278	int ret;
				4279	ret = rpmsgCreateChannel(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, ICP_BUFFERSIZE_CONSOLE_TOGGLE);
				4280	if(ret){
				4281	printk("linux5 request icp channel for uart fail %d.\n",ret);
				4282	}
				4283	rpmsgRegCallBack(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, icp_callback_ps2cap);
				4284	#endif
				4285	}
				4286
				4287	if(pdev->id != DEBUG_CONSOLE){
				4288	error = device_create_file(&pdev->dev, &dev_attr_ctsrts_input);
				4289	error = device_create_file(&pdev->dev, &dev_attr_wakeup_enable);
				4290	error = device_create_file(&pdev->dev, &dev_attr_sleep_state);
				4291	error = device_create_file(&pdev->dev, &dev_attr_app_ctrl);
				4292
				4293	}
				4294	error = device_create_file(&pdev->dev, &dev_attr_statics);
				4295	device_init_wakeup(&pdev->dev, true);
				4296	/*
				4297	strcpy(wakelock_name, "uart_wakelock_x");
				4298	wakelock_name[14] = '0' + pdev->id;
				4299	strcpy(uart_wakelock_name[pdev->id], wakelock_name);
				4300	wake_lock_init(&(port->port.port_wakelock),WAKE_LOCK_SUSPEND,uart_wakelock_name[pdev->id]);
				4301	*/
				4302
				4303	printk(KERN_INFO "TSP zx29 UART_%d probe OK\n",pdev->id);
				4304	return 0;
				4305	}
				4306
				4307	/****************************************************************************/
				4308	static int /__devexit/ zx29_uart_remove(struct platform_device *pdev)
				4309	{
				4310	struct uart_port *port = NULL;
				4311	#if CONFIG_SERIAL_ZX29_DMA
				4312	struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
				4313	#endif
				4314	int i;
				4315	if(pdev->id == DEBUG_CONSOLE){
				4316	device_remove_file(&pdev->dev, &dev_attr_console_input);
				4317	}
				4318
				4319	if(pdev->id != DEBUG_CONSOLE){
				4320	device_remove_file(&pdev->dev, &dev_attr_ctsrts_input);
				4321	device_remove_file(&pdev->dev, &dev_attr_wakeup_enable);
				4322	}
				4323
				4324	for (i = 0; (i < zx29_MAXPORTS); i++) {
				4325	port = &zx29_uart_ports[i].port;
				4326	if (port){
				4327	uart_remove_one_port(&zx29_uart_driver, port);
				4328
				4329
				4330	#if CONFIG_SERIAL_ZX29_DMA
				4331	zup=container_of(port,struct zx29_uart_port,port);
				4332	zx29_dma_remove(zup);
				4333
				4334	#endif
				4335	}
				4336	}
				4337	return 0;
				4338	}
				4339
				4340	static const struct of_device_id zx29_uart_of_match[] = {
				4341	{ .compatible = "zxic,zx29-uart"},
				4342	{},
				4343	};
				4344	MODULE_DEVICE_TABLE(of, zx29_uart_of_match);
				4345
				4346	static struct platform_driver zx29_uart_platform_driver = {
				4347	.probe = zx29_uart_probe,
				4348	//.remove = __devexit_p(zx29_uart_remove),
				4349	.remove = zx29_uart_remove,
				4350	.driver = {
				4351	.name = "zx29_uart",
				4352	.pm = &zx29_uart_dev_pm_ops,
				4353	.of_match_table = of_match_ptr(zx29_uart_of_match),
				4354	.owner = THIS_MODULE,
				4355	},
				4356	};
				4357
				4358	static int __init zx29_uart_init(void)
				4359	{
				4360	int rc;
				4361
				4362	rc = uart_register_driver(&zx29_uart_driver);
				4363	if (rc)
				4364	return rc;
				4365	rc = platform_driver_register(&zx29_uart_platform_driver);
				4366	if (rc){
				4367	uart_unregister_driver(&zx29_uart_driver);
				4368	return rc;
				4369	}
				4370
				4371	printk(KERN_INFO "zx29 UART driver registered\n");
				4372
				4373	return 0;
				4374	}
				4375
				4376	static void __exit zx29_uart_exit(void)
				4377	{
				4378	#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
				4379	unregister_console(&zx29_uart_console);
				4380	#endif
				4381	platform_driver_unregister(&zx29_uart_platform_driver);
				4382	uart_unregister_driver(&zx29_uart_driver);
				4383	}
				4384	//arch_initcall(zx29_uart_init);
				4385
				4386	//subsys_initcall(zx29_uart_init);
				4387	module_init(zx29_uart_init);
				4388	module_exit(zx29_uart_exit);
				4389