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192.168.1.100 / T106_eSDK / ed996a287b57501f34dfea753d673f7162b4ec2a / . / upstream / linux-5.10 / drivers / tty / serial / zx29_uart.c
blob: b29437aca4cc3c1cf6d8fac1fb9d3821c9998ad4 [file] [log] [blame]
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1/****************************************************************************/
2/*
3 * zx29_uart.c sanchips
4 *
5 * (C) Copyright 2003-2007, gaowei
6 * (C) Copyright 2003-2007, sanchips
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13/****************************************************************************/
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/console.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/platform_device.h>
25#include <linux/of.h>
26#include <linux/of_irq.h>
27#include <linux/io.h>
28#include <linux/printk.h>
29#include <linux/clk.h>
30#include <linux/gpio.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/slab.h>
35#include <linux/scatterlist.h>
36#include <linux/device.h>
37#include <linux/ioport.h>
38#include <linux/sched/clock.h>
39#include <linux/soc/zte/spinlock.h>
40
41#if 0
42#include <mach/gpio_def.h>
43#include <mach/irqs.h>
44#include <mach/board.h>
45#include <mach/gpio.h>
46#include <mach/debug.h>
47#include <mach/iomap.h>
48#include <mach/dma.h>
49#include <mach/dma_cfg.h>
50#endif
51//#include <linux/wakelock.h>
52#include <linux/kthread.h>
53#include <linux/semaphore.h>
54
55#include <linux/dma/zx-dma.h>
56//#include "../../dma/zte/zx298501_dma.h"
57
58#include "zx29_uart.h"
59#include <linux/soc/zte/rpmsg.h>
60#include <linux/soc/sc/drv_idle.h>
61#include "pub_debug_info.h"
62//#include <linux/soc/zte/pm/drv_idle.h>
63//#include <mach/pcu.h>
64//#define DEBUG_UART
65
66#ifdef DEBUG_UART
67#pragma GCC optimize("O0")
68#endif
69
70#define UART_WCLK_NAME "uartclk"
71#define UART_APBCLK_NAME "apb_pclk"
72
73#define CONFIG_SERIAL_ZX29_DMA 1
74
75
76extern bool xp2xp_Ap2CpIsApWakeup(void);
77extern int xp2xp_enable_4line(void);
78
79extern signed int zx29_dma_stop(unsigned int channel_id);
80extern signed int zx29_dma_get_transfer_num(unsigned int channel_id);
81
82
83
84char uart_names[5][12] = {
85 "zx29_uart.0",
86 "zx29_uart.1",
87 "zx29_uart.2",
88 "zx29_uart.3",
89 "zx29_uart.4"
90};
91
92#if CONFIG_SERIAL_ZX29_DMA
93#define ZX29_DMA_BUFFER_SIZE PAGE_SIZE
94#define UART_DMA_RX_MAX_COUNT 2
95//#define RX_DMA_TIMEOUT (HZ / 10)//60
96#define RX_DMA_TIMEOUT (HZ / 100)
97#define RX_DMA_WORK 1
98struct zx29_sgbuf {
99 struct scatterlist sg;
100 dma_addr_t dma_addr;
101 char *buf;
102};
103
104struct zx29_dmarx_data {
105 struct dma_chan *chan;
106 struct completion complete;
107 dma_channel_def rx_def[UART_DMA_RX_MAX_COUNT];
108 u32 rx_index;
109 bool use_buf_b;
110 struct zx29_sgbuf sgbuf_a;
111 struct zx29_sgbuf sgbuf_b;
112 dma_cookie_t cookie;
113 bool running;
114 atomic_t count;
115 bool used;
116};
117
118struct zx29_dmatx_data {
119 struct dma_chan *chan;
120 struct completion complete;
121 dma_channel_def tx_def;
122 struct scatterlist sg;
123 char *buf;
124 bool queued;
125 atomic_t count;
126};
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]127#define UART_DEBUG_RECORDER_BYTE 0
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]128#define UART_DMA_CYCLE_RX_CONFIG_COUNT 5
129struct zx29_dma_cycle_data{
130 int id;
131 int flg_enter_th;
132 int flg_enter_to;
133 char flg_overrun;
134 char flg_pe;
135 char flg_be;
136 char flg_fe;
137 char from_resume;
138 unsigned long cnt_callback_total;
139 unsigned long cnt_th_total;
140 int cnt_callback;
141 int cnt_th;
142 struct zx29_sgbuf sgbuf[UART_DMA_CYCLE_RX_CONFIG_COUNT];
143 dma_channel_def rxdef[UART_DMA_CYCLE_RX_CONFIG_COUNT];
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]144 bool enter_throttle;
145 bool from_unthrottle;
146 bool used;
147 unsigned int cnt_throttle;
148 unsigned int cnt_unthrottle;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]149};
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]150struct zx29_dma_cycle_data uart_dma_cycle[6];
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]151#endif
152
153
154
155#define UART_NUM 5
156int g_uart_overrun[5];
157ktime_t g_hr_interval;
158
159
160int g_cons_id_cmdline;
161EXPORT_SYMBOL(g_cons_id_cmdline);
162
163#ifdef DEBUG_CONSOLE
164#undef DEBUG_CONSOLE
165#endif
166#define DEBUG_CONSOLE g_cons_id_cmdline
167/****************************************************************************/
168
169/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
170 * name, but it is legally reserved for the 8250 driver. */
171#define SERIAL_zx29_MAJOR TTY_MAJOR
172#define SERIAL_MINOR_START 64
173
174#define UART_PORT_AUTOBAUD_ON 1
175#define UART_PORT_AUTOBAUD_OFF 0
176#define UART_PORT_AUTOBAUD_BYTE 2
177#define UART_AT_SENDOK_NUM 6
178#define UART_AUTOBAUD_LEVEL 5
179#define UART_AUTOBAUD_CHECKBYTE 4
180#define UART_AUTOBAUD_RATE 115200
181#define UART1_AUTOBAUD_RATE 921600
182
183
184unsigned char uart_port_autobaud_buffer[UART_PORT_AUTOBAUD_BYTE] = {0};
185unsigned char uart_port_autobaud_gtflag = 0 ;
186unsigned char uart_port_autobaud_suflag = 0 ;
187unsigned char g_console_open_flag = 1;
188
189
190unsigned char UART_AT_send_ok[UART_AT_SENDOK_NUM] =
191 {
192 0x0d,0x0a,0x4F,0x4B,0x0d,0x0a
193 };
194
195unsigned char UART_baud_check[UART_AUTOBAUD_LEVEL][UART_AUTOBAUD_CHECKBYTE]=
196 {
197 {0x61,0x74,0x41,0x54},{0x06,0x9e,0x06,0x98},{0x1c,0x80,0x1c,0x00},
198 {0xe0,0x00,0xe0,0x00},{0x00,0x00,0x00,0x00},
199 };
200unsigned int UART_baud[UART_AUTOBAUD_LEVEL] =
201 {
202 115200,57600,38400,19200,9600
203 };
204unsigned int UART_termios_cflag[UART_AUTOBAUD_LEVEL] =
205 {
206 B115200,B57600,B38400,B19200,B9600
207 };
208
209#ifdef CONFIG_SERIAL_CORE_CONSOLE
210#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
211#else
212#define uart_console(port) (0)
213#endif
214
215/****************************************************************************/
216/*
217 * Local per-uart structure.
218 */
219struct zx29_uart_port
220{
221 struct uart_port port;
222 unsigned int sigs; /* Local copy of line sigs */
223 unsigned int old_status;
224 unsigned char imr; /* Local interrupt mask reg mirror */
225#if CONFIG_SERIAL_ZX29_DMA
226 unsigned char dmacr; /* DMA reg*/
227#endif
228 bool rts_state;
229 bool autorts; /* hardware flow control */
230 struct clk *wclk; /* uart work clock */
231 struct clk *busclk; /* uart apb clock */
232 bool autobaud;
233 bool autobaud_state;
234 unsigned int baudrate;
235 bool uartwake;
236
237 int irq;
238 int irq_state;
239 int rxd_irq;
240 struct tasklet_struct write_wakeup;
241 bool rxd_wakeup;
242 int rxd_int_depth;
243 bool enter_suspend;
244#if CONFIG_SERIAL_ZX29_DMA
245 /* DMA stuff */
246 bool using_tx_dma;
247 bool using_rx_dma;
248 struct zx29_dmarx_data dmarx;
249 struct zx29_dmatx_data dmatx;
250 struct timer_list rx_dma_timer;
251 struct hrtimer rx_dma_hrtimer;
252 struct task_struct *dma_compl_th;
253 struct semaphore sema;
254 struct semaphore sema_cyclic;
255 bool port_close;
256 bool work_state;
257 size_t pre_pending;
258 struct zx29_sgbuf *sg2tty;
259 size_t sg2tty_len;
260 struct zx29_sgbuf *curr_sg;
261 int enable_ctsrts;
262 int enable_wakeup;
263
264 struct notifier_block wakeup_notifier;
265
266#endif
267 //means application decide close and release DMA &wakelock
268 int app_ctrl;
269 int sleep_state;
270 //if app_ctrl is set or using kernel control sleep,set this flag
271 int uart_power_mode;
272};
273
274
275
276static struct zx29_uart_port zx29_uart_ports[UART_NUM];
277
278#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
279typedef struct __UART_STATIC{
280 int cnt;
281 char head[16];
282 unsigned long long s_time;
283 int func_step;
284 unsigned int fr;
285 unsigned int ris;
286}uart_static;
287#define STATIC_UART_ID 0
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]288#define UART_STATIC_COUNT 512
289#define UART_STATIC_NUM 4
290uart_static g_uart_static[UART_STATIC_NUM][UART_STATIC_COUNT] = {0};
291int g_uart_static_cnt[UART_STATIC_NUM] = {0};
292void test_uart_static(int uart_id, char *buf, unsigned int cnt, int steps)
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]293{
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]294 //if(uart_id != STATIC_UART_ID)
295 // return;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]296 if(buf){
297 if(cnt >= 16){
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]298 memcpy(g_uart_static[uart_id][g_uart_static_cnt[uart_id]].head, buf, 16);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]299 }else{
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]300 memcpy(g_uart_static[uart_id][g_uart_static_cnt[uart_id]].head, buf, cnt);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]301 }
302 }
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]303 g_uart_static[uart_id][g_uart_static_cnt[uart_id]].cnt = cnt;
304 g_uart_static[uart_id][g_uart_static_cnt[uart_id]].s_time = local_clock();
305 g_uart_static[uart_id][g_uart_static_cnt[uart_id]].func_step = steps;
306 g_uart_static[uart_id][g_uart_static_cnt[uart_id]].fr = UART_GET_FR(&zx29_uart_ports[uart_id].port);
307 g_uart_static[uart_id][g_uart_static_cnt[uart_id]].ris = UART_GET_RIS(&zx29_uart_ports[uart_id].port);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]308
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]309 if(++g_uart_static_cnt[uart_id] >= UART_STATIC_COUNT)
310 g_uart_static_cnt[uart_id] = 0;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]311}
312
313
314
315
316#define zx29_MAXPORTS ARRAY_SIZE(zx29_uart_ports)
317void zx29_uart_stop_rx(struct uart_port *port);
318
319#if CONFIG_SERIAL_ZX29_DMA
320static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup);
321static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup);
322static bool zx29_dma_tx_irq(struct zx29_uart_port *zup);
323static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup);
324void uart_dma_rx_callback(void *data);
325void uart_dma_rx_callback_use_dma_cyclic(void * data);
326static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
327 //u32 pending, bool use_buf_b,
328 u32 pending, struct zx29_sgbuf *sgbuf,
329 bool readfifo, unsigned long *flags);
330static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup);
331static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup);
332static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup);
333static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup);
334static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup);
335
336static void zx29_uart_rx_dma_chars(struct zx29_uart_port *zup, unsigned long *flags);
337dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup);
338
339#if RX_DMA_WORK
340static void zx29_uart_rx_timeout_chars(struct zx29_uart_port *zup, unsigned long *flags);
341static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup);
342
343static void zx29_uart_rt_dma(struct zx29_uart_port *zup, unsigned long *flags);
344static void uart_dma_cycle_deinit(struct zx29_uart_port *zup);
345#endif
346#endif
347
348
349
350/*******************************************************************************
351* Function: uart_wakeup_callback.
352* Description: uart_wakeup_callback.
353* Parameters:
354* Input:val:means wakeup or sleep notify to other device
355*
356* Output:v:means devices been called return result
357*
358* Returns:
359*
360* Others:
361********************************************************************************/
362int uart_wakeup_callback(struct notifier_block * nb, unsigned long val, void * v)
363{
364 int *call_result = (int *)v;
365 unsigned long flags = 0;
366 struct zx29_uart_port *zup = container_of(nb, struct zx29_uart_port, wakeup_notifier);
367
368 if(!zup || zup->port_close){
369 *call_result |= 0;
370 return 0;
371 }
372 struct platform_device *pdev = zup->port.private_data;
373 raw_spin_lock_irqsave(&zup->port.lock, flags);
374 if(val == 1){//wakeup
375 zup->sleep_state = 0;
376 pm_stay_awake(&pdev->dev);
377 zx29_uart_rx_dma_chars(zup, &flags);
378
379 }else{//sleep
380 zup->sleep_state = 1;
381 zx29_uart_stop_rx(&zup->port);
382 pm_relax(&pdev->dev);
383
384 }
385 *call_result |= 0;
386 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
387 return 0;
388}
389
390int zx29_get_sleep_state(int uart_index)
391{
392 if(uart_index < 0 || uart_index > 2){
393 printk("invalid uart index\n");
394 return -1;
395 }
396
397 return zx29_uart_ports[uart_index].sleep_state;
398}
399EXPORT_SYMBOL_GPL(zx29_get_sleep_state);
400
401void zx29_set_sleep_state(int state, int uart_index)
402{
403 if(uart_index < 0 || uart_index > 2){
404 printk("invalid uart index\n");
405 return ;
406 }
407 printk(" uart %d, state change to:%d\n", uart_index, state);
408 zx29_uart_ports[uart_index].sleep_state = (state ? 1: 0);
409}
410EXPORT_SYMBOL_GPL(zx29_set_sleep_state);
411
412static ssize_t sleep_state_show(struct device *_dev,
413 struct device_attribute *attr, char *buf)
414{
415 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
416 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
417
418 return sprintf(buf, "\n wakeup_enable = %d\n",zx29_uart_ports[pdev->id].sleep_state);
419}
420
421static ssize_t sleep_state_store(struct device *_dev,
422 struct device_attribute *attr,
423 const char *buf, size_t count)
424{
425 uint32_t flag = 0;
426 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
427 struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
428 flag = simple_strtoul(buf, NULL, 16);
429 //pdata->uart_wakeup_enable = flag;
430 zx29_uart_ports[pdev->id].sleep_state = (flag ? 1: 0);
431 return count;
432}
433
434DEVICE_ATTR(sleep_state, S_IRUGO | S_IWUSR, sleep_state_show,
435 sleep_state_store);
436//bool uart_dma_filter_fn (struct dma_chan *chan, void *param)
437//{
438// dma_peripheral_id peri_id = (dma_peripheral_id) param;
439// if (chan->chan_id == (unsigned int)peri_id){
440// printk("uart_dma_filter_fn, peri_id:%d, ok\n", peri_id);
441// return true;
442// }
443// chan->private = param;
444//
445// return false;
446//}
447static void zx29_uart_console_putc(struct uart_port *port, int c);
448void zx29_uart_putc(struct uart_port *port, int c);
449
450#if CONFIG_SERIAL_ZX29_DMA
451void uart_mod_timer(struct zx29_uart_port *zup, unsigned long *flags)
452{
453 unsigned long t_delay = 0;
454 t_delay = msecs_to_jiffies(RX_DMA_TIMEOUT);
455 spin_unlock_irqrestore(&zup->port.lock, *flags);
456 //printk("uart_mod_timer, delay %d jiffies\n", t_delay);
457 mod_timer(&(zup->rx_dma_timer), jiffies + t_delay);
458
459 spin_lock_irqsave(&zup->port.lock, *flags);
460}
461#endif
462/**
463* Show the console_input attribute.
464*/
465static ssize_t console_input_show(struct device *_dev,
466 struct device_attribute *attr, char *buf)
467{
468 return sprintf(buf, "\n console_input = %d\n",g_console_open_flag);
469}
470
471/**
472 * Store the console_input attribure.
473 * 0: disable console input function,only out put log
474 * 1: able console input, can input commands
475 */
476static ssize_t console_input_store(struct device *_dev,
477 struct device_attribute *attr,
478 const char *buf, size_t count)
479{
480 uint32_t flag = 0;
481 flag = simple_strtoul(buf, NULL, 16);
482 g_console_open_flag = flag;
483
484 return count;
485}
486
487DEVICE_ATTR(console_input, S_IRUGO | S_IWUSR, console_input_show,
488 console_input_store);
489
490static ssize_t ctsrts_input_show(struct device *_dev,
491 struct device_attribute *attr, char *buf)
492{
493 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
494// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
495 if(pdev->id < 0 || pdev->id >= UART_NUM){
496 printk("ctsrts_input_store, invalid uart id, return error\n");
497 return 0;
498 }
499// return sprintf(buf, "\n ctsrts_input = %d\n",pdata->uart_ctsrtsuse);
500return sprintf(buf, "\n uart %d ctsrts_input = %d\n", pdev->id, zx29_uart_ports[pdev->id].enable_ctsrts);
501
502}
503
504static ssize_t ctsrts_input_store(struct device *_dev,
505 struct device_attribute *attr,
506 const char *buf, size_t count)
507{
508 uint32_t flag = 0;
509 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
510
511 if(pdev->id != 0){
512 printk("ctsrts_input_store, invalid uart id, only uart support hardware control\n");
513 }
514 flag = simple_strtoul(buf, NULL, 16);
515 zx29_uart_ports[pdev->id].enable_ctsrts = flag;
516
517 return count;
518}
519
520DEVICE_ATTR(ctsrts_input, S_IRUGO | S_IWUSR, ctsrts_input_show,
521 ctsrts_input_store);
522
523static ssize_t wakeup_enable_show(struct device *_dev,
524 struct device_attribute *attr, char *buf)
525{
526 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
527 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
528
529 return sprintf(buf, "\n wakeup_enable = %d\n",1);
530}
531
532static ssize_t wakeup_enable_store(struct device *_dev,
533 struct device_attribute *attr,
534 const char *buf, size_t count)
535{
536 uint32_t flag = 0;
537 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
538 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
539 if(pdev->id != 4){
540 printk("\nctsrts_input_store, invalid uart id, only lp_uart(uart 4) support wakeup\n");
541 }
542 flag = simple_strtoul(buf, NULL, 16);
543 zx29_uart_ports[pdev->id].enable_wakeup = flag;
544
545 return count;
546}
547
548DEVICE_ATTR(wakeup_enable, S_IRUGO | S_IWUSR, wakeup_enable_show,
549 wakeup_enable_store);
550
551static ssize_t app_ctrl_show(struct device *_dev,
552 struct device_attribute *attr, char *buf)
553{
554 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
555 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
556
557 return sprintf(buf, "%d\n",zx29_uart_ports[pdev->id].app_ctrl);
558}
559
560static ssize_t app_ctrl_store(struct device *_dev,
561 struct device_attribute *attr,
562 const char *buf, size_t count)
563{
564 uint32_t flag = 0;
565 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
566 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
567 flag = simple_strtoul(buf, NULL, 16);
568 // pdata->uart_wakeup_enable = flag;
569 zx29_uart_ports[pdev->id].app_ctrl = (flag == 0) ? 0 : 1;
570
571 return count;
572}
573DEVICE_ATTR(app_ctrl, S_IRUGO | S_IWUSR, app_ctrl_show,
574 app_ctrl_store);
575
576int rxd_wake_cnt = 0;
577static ssize_t statics_show(struct device *_dev,
578 struct device_attribute *attr, char *buf)
579{
580 struct platform_device *pdev = container_of(_dev, struct platform_device, dev);
581 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
582
583 return sprintf(buf, "\n RX:%u,TX:%u,OE:%u,brk:%u,FE:%u,PE:%u ,rxd_wake_cnt:%d\n",
584 zx29_uart_ports[pdev->id].port.icount.rx,
585 zx29_uart_ports[pdev->id].port.icount.tx,
586 zx29_uart_ports[pdev->id].port.icount.overrun,
587 zx29_uart_ports[pdev->id].port.icount.brk,
588 zx29_uart_ports[pdev->id].port.icount.frame,
589 zx29_uart_ports[pdev->id].port.icount.parity,
590 rxd_wake_cnt
591 );
592}
593DEVICE_ATTR(statics, S_IRUGO, statics_show, NULL);
594#define VEHICLE_USE_ONE_UART_LOG 1
595#if VEHICLE_USE_ONE_UART_LOG
596#define ICP_CORE_ID_PS CORE_PS0
597#define ICP_CORE_ID_CAP 1
598#define ICP_CHANNEL_CONSOLE_UART 7
599#define ICP_MSG_LEN_CONSOLE_UART 2
600#define ICP_BUFFERSIZE_CONSOLE_TOGGLE 16
601#define SYMB_PS_CORE_ID ICP_CORE_ID_PS
602#define SYMB_CAP_CORE_ID ICP_CORE_ID_CAP
603#define SYMB_WHAT_CORE_ID 3
604#define ENABLE_CURRENT_CONSOLE_UART 1
605#define DISABLE_CURRENT_CONSOLE_UART 0
606#define ENABLE_TOGGLE 1
607#define DISABLE_TOGGLE 0
608unsigned char g_core_id_occupy_uart = 0;
609unsigned char g_cap_uart_toggle = 0;
610static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id);
611static void restart_current_cons_uart(void)
612{
613 struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
614 struct uart_port *port = &zup->port;
615 enable_irq(port->irq);
616 g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
617 spin_lock(&zup->port.lock);
618 tasklet_schedule(&zup->write_wakeup);
619 spin_unlock(&zup->port.lock);
620}
621static void forbid_current_cons_uart(void)
622{
623 struct zx29_uart_port *zup = &zx29_uart_ports[DEBUG_CONSOLE];
624 struct uart_port *port = &zup->port;
625 disable_irq(port->irq);
626 g_core_id_occupy_uart = SYMB_PS_CORE_ID;
627}
628static void process_ps2cap_rpmsg(char *arr)
629{
630 if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == ENABLE_CURRENT_CONSOLE_UART)){
631 restart_current_cons_uart();
632 }else if((arr[0] == SYMB_CAP_CORE_ID) && (arr[1] == DISABLE_CURRENT_CONSOLE_UART)){
633 printk("current console uart not enable.\n");
634 g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
635 }else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_PS_CORE_ID)){
636 g_core_id_occupy_uart = SYMB_PS_CORE_ID;
637 forbid_current_cons_uart();
638 }else if((arr[0] == SYMB_WHAT_CORE_ID) && (arr[1] == SYMB_CAP_CORE_ID)){
639 g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
640 }
641 else{
642 printk("%s error!!\n",__func__);
643 }
644}
645static void icp_callback_ps2cap(void *buf, unsigned int len)
646{
647 char *arr_ps2cap;
648 if (len==0){
649 printk("%s empty.\n", __func__);
650 return ;
651 }
652 arr_ps2cap = (char *)buf;
653 process_ps2cap_rpmsg(arr_ps2cap);
654}
655static void echo_to_change_other_uart(uint32_t val)
656{
657 int ret;
658 if(val > ENABLE_TOGGLE)
659 {
660 printk("echo para error!!!\n");
661 return;
662 }
663 char arr[2] = {0};
664 arr[0] = SYMB_PS_CORE_ID;
665 arr[1] = val;
666 T_RpMsg_Msg icp_msg;
667 icp_msg.coreID = CORE_PS0;
668 icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
669 icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
670 icp_msg.buf = arr;
671 icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
672 ret = rpmsgWrite(&icp_msg);
673 if(ret == 0){
674 if(val == ENABLE_TOGGLE)
675 g_core_id_occupy_uart = SYMB_PS_CORE_ID;
676 else if(val == DISABLE_TOGGLE)
677 g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
678 }else
679 printk("echo_to_change_ohter_uart fail.\n");
680}
681static ssize_t console_uart_toggle_show(struct device *_dev,
682 struct device_attribute *attr, char *buf)
683{
684 return sprintf(buf, "\n console_uart_toggle_show %d. \n", g_cap_uart_toggle);
685}
686static ssize_t console_uart_toggle_store(struct device *_dev,
687 struct device_attribute *attr,
688 const char *buf, size_t count)
689{
690 uint32_t flag = 0;
691 flag = simple_strtoul(buf, NULL, 16);
692 if(flag == ENABLE_TOGGLE){
693 g_cap_uart_toggle = 1;
694 forbid_current_cons_uart();
695 echo_to_change_other_uart(flag);
696 }else if(flag == DISABLE_TOGGLE){
697 g_cap_uart_toggle = 0;
698 g_core_id_occupy_uart = SYMB_CAP_CORE_ID;
699 }
700 return count;
701}
702DEVICE_ATTR(console_uart_toggle, S_IRUGO | S_IWUSR, console_uart_toggle_show,
703 console_uart_toggle_store);
704static void notify_occupy_uart_coreid_to_other(void)
705{
706 char arr[2] = {0};
707 arr[0] = SYMB_WHAT_CORE_ID;
708 arr[1] = g_core_id_occupy_uart;
709 T_RpMsg_Msg icp_msg;
710 icp_msg.coreID = CORE_AP;
711 icp_msg.chID = ICP_CHANNEL_CONSOLE_UART;
712 icp_msg.flag = RPMSG_WRITE_INT; /* 1- means send an icp interrupt> */
713 icp_msg.buf = arr;
714 icp_msg.len = ICP_MSG_LEN_CONSOLE_UART;
715 rpmsgWrite(&icp_msg);
716}
717static ssize_t coreid_occupy_uart_show(struct device *_dev,
718 struct device_attribute *attr, char *buf)
719{
720 return sprintf(buf, "\n core %d occupy cons uart now! \n",g_core_id_occupy_uart);
721}
722static ssize_t coreid_occupy_uart_store(struct device *_dev,
723 struct device_attribute *attr,
724 const char *buf, size_t count)
725{
726 uint32_t flag = 0;
727 flag = simple_strtoul(buf, NULL, 16);
728 g_core_id_occupy_uart = flag;
729 if(flag == SYMB_CAP_CORE_ID){
730 g_cap_uart_toggle = 0;
731 }else if(SYMB_PS_CORE_ID){
732 g_cap_uart_toggle = 1;
733 }
734 return count;
735}
736DEVICE_ATTR(coreid_occupy_uart, S_IRUGO | S_IWUSR, coreid_occupy_uart_show,
737 coreid_occupy_uart_store);
738#endif
739
740//extern int (*pm_callback_fn)(void);
741#ifdef CONFIG_CPU_IDLE
742typedef int (*pm_callback_fn)(void);
743extern int zx_pm_register_callback(pm_callback_fn enter_cb, pm_callback_fn exit_cb);
744
745extern void disable_irq_nosync(unsigned int irq);
746extern void enable_irq(unsigned int irq);
747
748void uart_rxd_int_disable(struct uart_port *port)
749{
750 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
751 zup->rxd_int_depth++;
752}
753EXPORT_SYMBOL(uart_rxd_int_disable);
754
755int uart_0_pm_enter(void)
756{
757 struct zx29_uart_port *zup = &zx29_uart_ports[0];
758
759 //zDrvInt_UnmaskIrq(UART0_RXD_INT);
760 if(zup->irq_state == 0 || zup->imr== 0)
761 return 0;
762
763 //pcu_int_clear(PCU_UART0_RXD_INT);
764 if(!zup->rxd_int_depth){
765 //enable_irq(UART0_RXD_INT);
766 zup->rxd_int_depth++;
767 }
768 return 0;
769}
770
771int uart_0_pm_exit(void)
772{
773
774 return 0;
775}
776#endif
777/****************************************************************************/
778
779static int zx29_sgbuf_init(struct dma_chan *chan, struct zx29_sgbuf *sg,
780 enum dma_data_direction dir)
781{
782 dma_addr_t dma_addr;
783
784 sg->buf = dma_alloc_coherent(chan->device->dev,
785 ZX29_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
786 if (!sg->buf){
787 printk("zx29_sgbuf_init fail, no mem\n");
788 return -ENOMEM;
789 }
790 sg_init_table(&sg->sg, 1);
791 sg_set_page(&sg->sg, phys_to_page(dma_addr),
792 ZX29_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
793 sg_dma_address(&sg->sg) = dma_addr;
794 sg_dma_len(&sg->sg) = ZX29_DMA_BUFFER_SIZE;
795 sg->dma_addr = dma_addr;
796 return 0;
797}
798
799static void zx29_sgbuf_free(struct dma_chan *chan, struct zx29_sgbuf *sg,
800 enum dma_data_direction dir)
801{
802 if (sg->buf) {
803 dma_free_coherent(chan->device->dev,
804 ZX29_DMA_BUFFER_SIZE, sg->buf,
805 sg_dma_address(&sg->sg));
806 sg->dma_addr = NULL;
807 }
808}
809
810
811/****************************************************************************/
812static unsigned int zx29_uart_tx_empty(struct uart_port *port)
813{
814 return (UART_GET_FR(port)&(UART_FR_TXBUSY|UART_FR_TXFF)) ? 0 : TIOCSER_TEMT;
815}
816
817/****************************************************************************/
818static void zx29_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
819{
820 unsigned int control = 0;
821 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
822 zup->sigs = mctrl;
823 control = UART_GET_CR(&zup->port);
824 if(mctrl & TIOCM_DTR)
825 control |= UART_CR_DTR;
826 else
827 control &= ~ UART_CR_DTR;
828
829 if(mctrl & TIOCM_RTS)
830 control |= UART_CR_RTS;
831 else
832 control &= ~UART_CR_RTS;
833
834 if(mctrl & TIOCM_LOOP)
835 control |= UART_CR_LBE;
836 else
837 control &= ~UART_CR_LBE;
838
839 /* We need to disable auto-RTS if we want to turn RTS off */
840 if (zup->autorts) {
841 if (mctrl & TIOCM_RTS)
842 control |= UART_CR_RTSEN;
843 else
844 control &= ~UART_CR_RTSEN;
845 }
846 UART_PUT_CR(port, control);
847}
848
849/****************************************************************************/
850static unsigned int zx29_uart_get_mctrl(struct uart_port *port)
851{
852 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
853 unsigned int mctrl = 0;
854 unsigned int uart_flag = 0;
855
856 uart_flag = UART_GET_FR(port);
857
858 mctrl = (uart_flag&UART_FR_CTS) ?TIOCM_CTS : 0;
859 mctrl |= (zup->sigs & TIOCM_RTS);
860 mctrl |= (uart_flag&UART_FR_DCD) ? TIOCM_CD : 0;
861 mctrl |= (uart_flag&UART_FR_DSR) ? TIOCM_DSR : 0;
862 mctrl |= (uart_flag&UART_FR_RI) ? TIOCM_RI : 0;
863
864 return mctrl;
865}
866
867/****************************************************************************/
868static void zx29_uart_start_tx(struct uart_port *port)
869{
870 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
871 unsigned int control = 0;
872 unsigned int reg_bak[10] = {0};
873 struct circ_buf *xmit = &zup->port.state->xmit;
874 int count = 0;
875#if VEHICLE_USE_ONE_UART_LOG
876 if((port->line == DEBUG_CONSOLE))
877 {
878 if(g_core_id_occupy_uart == SYMB_PS_CORE_ID){
879 #if 1
880 count = uart_circ_chars_pending(xmit);
881 while(count-- > 0)
882 {
883 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
884 if (uart_circ_empty(xmit))
885 break;
886 }
887 #endif
888 return;
889 }
890 count = uart_circ_chars_pending(xmit);
891 while(count-- > 0)
892 {
893 zx29_uart_console_putc(&zup->port, xmit->buf[xmit->tail]);
894 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
895 zup->port.icount.tx++;
896 if (uart_circ_empty(xmit)){
897 break;
898 }
899 }
900
901 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
902 {
903 spin_lock(&zup->port.lock);
904 tasklet_schedule(&zup->write_wakeup);
905 spin_unlock(&zup->port.lock);
906 return;
907 }
908 return;
909 }
910else
911#endif
912{
913 if(!(UART_GET_RIS(port)&UART_TXIS) && (UART_GET_FR(port) & UART_FR_TXFE))
914 {
915 if(!(UART_GET_RIS(port)&UART_TXIS))
916 {
917 count = uart_circ_chars_pending(xmit);
918 if(count >= zup->port.fifosize)
919 count = 15;//sent data more than TX ifls, TXIS will coming soon
920 if(count != 0){
921 do {
922 zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
923 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
924 zup->port.icount.tx++;
925 if (uart_circ_empty(xmit) || (UART_GET_RIS(port)&UART_TXIS))
926 break;
927 } while (--count > 0);
928 }
929 }
930
931 }
932 }
933#if CONFIG_SERIAL_ZX29_DMA
934 if(!uart_console(port))
935 {
936 if (!zx29_dma_tx_start(zup))
937 {
938 zup->imr |= UART_TXIM;
939 UART_PUT_IMSC(port, zup->imr);
940 if(!(UART_GET_RIS(port)&UART_TXIS)){
941 if((UART_GET_FR(port) & UART_FR_TXFF))
942 return;
943 count = uart_circ_chars_pending(xmit);
944 while (count > 0) {
945 UART_PUT_CHAR(&zup->port, xmit->buf[xmit->tail]);
946 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
947 zup->port.icount.tx++;
948 if (uart_circ_empty(xmit) || (UART_GET_RIS(port)&UART_TXIS) ||
949 (UART_GET_FR(port) & UART_FR_TXFF))
950 break;
951 }
952 }
953 }
954 }
955 else
956 {
957 zup->imr |= UART_TXIM;
958 UART_PUT_IMSC(port, zup->imr);
959 }
960#else
961 zup->imr |= UART_TXIM;
962 UART_PUT_IMSC(port, zup->imr);
963#endif
964}
965
966static void uart_write_wakeup_task(unsigned long _port)
967{
968 struct uart_port *port = (void *)_port;
969struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
970 struct platform_device *pdev=port->private_data;
971 //printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
972
973 if(zup->rxd_wakeup){
974 //rxd wake
975 printk("wakeup_task,port:%d, rxd_wakeup:%d\n", port->line, zup->rxd_wakeup);
976 pm_wakeup_dev_event(&pdev->dev, 5000, false);
977 disable_irq(zup->rxd_irq);
978 zup->rxd_wakeup = false;
979 } else {
980 uart_write_wakeup(port);
981 }
982
983}
984
985#if CONFIG_SERIAL_ZX29_DMA
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]986#if UART_DEBUG_RECORDER_BYTE
987#define UART_DRIVER_DEBUG_COUNT (4*1024*1024)
988u32 cnt_uart_driver_debug = 0;
989u8 uart_driver_debug[UART_DRIVER_DEBUG_COUNT]={};
990void uart_debug(char *debug_buf, u32 count){
991 if(cnt_uart_driver_debug > (UART_DRIVER_DEBUG_COUNT-1)){
992 cnt_uart_driver_debug = 0;
993 }else{
994 memcpy(uart_driver_debug+cnt_uart_driver_debug,debug_buf,count);
995 cnt_uart_driver_debug = cnt_uart_driver_debug+count;
996 }
997}
998#endif
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]999int dma_complete_thread_use_dma_cyclic(void *ptr)
1000{
1001 unsigned long flags;
1002 struct zx29_uart_port *zup = (struct zx29_uart_port *)ptr;
1003 size_t pending;
1004 int dma_count = 0;
1005 struct device *dev = NULL;
1006 dev = zup->dmarx.chan->device->dev;
1007 int uart_id = zup->port.line;
1008 while(down_interruptible(&zup->sema_cyclic) == 0)
1009 {
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]1010 if(uart_dma_cycle[zup->port.line].cnt_callback > 0)
1011 uart_id = zup->port.line;
1012 else if(uart_dma_cycle[zup->port.line+3].cnt_callback > 0)
1013 uart_id = zup->port.line + 3;
1014
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1015 if(zup->port_close || !uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th].dma_addr)
1016 break;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]1017
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1018 spin_lock_irqsave(&zup->port.lock, flags);
1019 uart_dma_cycle[uart_id].cnt_th_total++;
1020 uart_dma_cycle[uart_id].cnt_th++;
1021 zup->sg2tty = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
1022 zup->sg2tty_len = 4096;
1023 pending = zup->sg2tty_len;
1024 if(uart_dma_cycle[uart_id].flg_be || uart_dma_cycle[uart_id].flg_fe|| uart_dma_cycle[uart_id].flg_pe){
1025 printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
1026 zup->port.icount.brk,zup->port.icount.parity);
1027 uart_dma_cycle[uart_id].flg_be = 0;
1028 uart_dma_cycle[uart_id].flg_fe = 0;
1029 uart_dma_cycle[uart_id].flg_pe = 0;
1030 }
1031 dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
1032 spin_unlock_irqrestore(&zup->port.lock, flags);
1033 dma_count = tty_insert_flip_string(&zup->port.state->port,
1034 zup->sg2tty->buf, pending);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]1035 test_uart_static(zup->port.line, zup->sg2tty->buf, uart_dma_cycle[zup->port.line].used, 27);
1036#if UART_DEBUG_RECORDER_BYTE
1037 uart_debug(zup->sg2tty->buf, pending);
1038#endif
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1039 tty_flip_buffer_push(&zup->port.state->port);
1040 spin_lock_irqsave(&zup->port.lock, flags);
1041 dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
1042 zup->sg2tty = NULL;
1043 zup->sg2tty_len = 0;
1044 zup->port.icount.rx += dma_count;
1045 if (dma_count < pending)
1046 dev_info(zup->port.dev,
1047 "couldn't insert all characters (TTY is full?)\n");
1048 uart_dma_cycle[uart_id].flg_enter_th = (uart_dma_cycle[uart_id].flg_enter_th+1)%UART_DMA_CYCLE_RX_CONFIG_COUNT;
1049 uart_dma_cycle[uart_id].cnt_callback--;
1050 if(!hrtimer_active(&zup->rx_dma_hrtimer))
1051 hrtimer_restart(&zup->rx_dma_hrtimer);
1052 spin_unlock_irqrestore(&zup->port.lock, flags);
1053 }
1054 return 0;
1055}
1056int dma_complete_thread(void *ptr)
1057{
1058 unsigned long flags;
1059 struct zx29_uart_port *zup = (struct zx29_uart_port *)ptr;
1060
1061 size_t pending;
1062 struct dma_tx_state state;
1063 struct zx29_dmarx_data *dmarx = &zup->dmarx;
1064 struct dma_chan *rxchan = dmarx->chan;
1065 bool lastbuf;
1066 int dma_count = 0;
1067 struct zx29_sgbuf *sgbuf = NULL;
1068 struct device *dev = NULL;
1069 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
1070 dev = zup->dmarx.chan->device->dev;
1071
1072 while(down_interruptible(&zup->sema) == 0)
1073 {
1074 if(zup->port_close)
1075 break;
1076 spin_lock_irqsave(&zup->port.lock, flags);
1077 // tty = zup->port.state->port.tty;
1078 if(!zup->sg2tty)
1079 panic("dma_complete_thread, buffer 2 tty is invalid\n");
1080 // dev = zup->dmarx.chan->device->dev;
1081 pending = zup->sg2tty_len;
1082 if(zx29_dma_rx_running(zup)){
1083
1084 test_uart_static(zup->port.line, NULL, 0, 10);
1085 //uart_mod_timer(zup, &flags);
1086 if(!hrtimer_active(&zup->rx_dma_hrtimer))
1087 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
1088 }
1089 /* Pick everything from the DMA first */
1090 if (pending) {
1091 /* Sync in buffer */
1092 dma_sync_sg_for_cpu(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
1093 //BUG();
1094
1095 spin_unlock_irqrestore(&zup->port.lock, flags);
1096 dma_count = tty_insert_flip_string(&zup->port.state->port,
1097 zup->sg2tty->buf, pending);
1098 test_uart_static(zup->port.line, zup->sg2tty->buf, pending, 11);
1099 tty_flip_buffer_push(&zup->port.state->port);
1100
1101 spin_lock_irqsave(&zup->port.lock, flags);
1102 /* Return buffer to device */
1103 dma_sync_sg_for_device(dev, &zup->sg2tty->sg, 1, DMA_FROM_DEVICE);
1104
1105 zup->sg2tty = NULL;
1106 zup->sg2tty_len = 0;
1107 zup->port.icount.rx += dma_count;
1108
1109 //if(zup->port.line == 0)
1110 //printk("yanming dma_complete_thread, dma2tty:%d\n", dma_count);
1111 if (dma_count < pending){
1112 sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d couldn't insert all characters \n",zup->port.line);
1113 dev_info(zup->port.dev,
1114 "couldn't insert all characters (TTY is full?)\n");
1115 }
1116
1117
1118 }
1119#if 0
1120 zup->work_state = false;
1121 zup->pre_pending = 0;
1122 zup->imr |= UART_RXIM;
1123 UART_PUT_IMSC(&zup->port, zup->imr);
1124#endif
1125 spin_unlock_irqrestore(&zup->port.lock, flags);
1126 }
1127
1128 return 0;
1129}
1130#endif
1131
1132/****************************************************************************/
1133static void zx29_uart_stop_tx(struct uart_port *port)
1134{
1135 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
1136 zup->imr &= ~UART_TXIM;
1137 UART_PUT_IMSC(port, zup->imr);
1138#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
1139 if((port->line == DEBUG_CONSOLE) && uart_tx_stopped(port))
1140 {
1141 //uart_write_wakeup(port);
1142 tasklet_schedule(&zup->write_wakeup);
1143 }
1144#endif
1145
1146#if CONFIG_SERIAL_ZX29_DMA
1147 zx29_dma_tx_stop(zup);
1148#endif
1149
1150 zx_cpuidle_set_free(IDLE_FLAG_UART);
1151
1152}
1153
1154/****************************************************************************/
1155void zx29_uart_stop_rx(struct uart_port *port)
1156{
1157 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
1158
1159 zup->imr &= ~(UART_RXIM|UART_RTIM|UART_FEIM|UART_PEIM|UART_BEIM|UART_OEIM);
1160 UART_PUT_IMSC(port, zup->imr);
1161#if CONFIG_SERIAL_ZX29_DMA
1162 zx29_dma_rx_stop(zup);
1163#endif
1164}
1165
1166/****************************************************************************/
1167static void zx29_uart_break_ctl(struct uart_port *port, int break_state)
1168{
1169 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
1170 unsigned long flags;
1171 unsigned int lcr_h;
1172 spin_lock_irqsave(&zup->port.lock, flags);
1173 lcr_h = UART_GET_LCRH(port);
1174 if (break_state == -1)
1175 lcr_h |= UART_LCRH_BRK;
1176 else
1177 lcr_h &= ~UART_LCRH_BRK;
1178 UART_PUT_LCRH(port, lcr_h);
1179 spin_unlock_irqrestore(&zup->port.lock, flags);
1180}
1181
1182/****************************************************************************/
1183static void zx29_uart_enable_ms(struct uart_port *port)
1184{
1185 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
1186 zup->imr |= UART_RIMIM|UART_CTSMIM|UART_DCDMIM|UART_DSRMIM;
1187 UART_PUT_IMSC(port, zup->imr);
1188}
1189
1190/****************************************************************************/
1191/*--------------------------------------------------------------------
1192 * Reads up to 256 characters from the FIFO or until it's empty and
1193 * inserts them into the TTY layer. Returns the number of characters
1194 * read from the FIFO.
1195 --------------------------------------------------------------------*/
1196static int zx29_uart_fifo_to_tty(struct zx29_uart_port *zup)
1197{
1198 struct uart_port *port = &zup->port;
1199 u32 status, ch, i = 0;
1200 unsigned int flag, max_count = 256;
1201 int fifotaken = 0;
1202 u8 uart_poll_char[16] ={0};
1203
1204 while (max_count--) {
1205 status = UART_GET_FR(port);
1206 if (status & UART_FR_RXFE)
1207 break;
1208
1209 /* Take chars from the FIFO and update status */
1210 ch = UART_GET_CHAR(port) | UART_DUMMY_DR_RX;
1211
1212#if 0
1213 if(g_console_open_flag == 0 &&
1214 port->line == DEBUG_CONSOLE){
1215 if((ch&0xff) == 't'){
1216 memset(uart_poll_char, 0, sizeof(uart_poll_char));
1217 uart_poll_char[0] = 't';
1218 i = 0;
1219 printk("ch = %c i = %d\n",ch,i);
1220 }else if ((ch&0xff) == 'y' && (i == 1)){
1221 uart_poll_char[1] = 'y';
1222 printk("ch = %c i = %d\n",ch,i);
1223 }else if ((ch&0xff) == 'o' && (i == 2)){
1224 uart_poll_char[2] = 'o';
1225 printk("ch = %c i = %d\n",ch,i);
1226 }else if ((ch&0xff) == 'p' && (i == 3)){
1227 uart_poll_char[3] = 'p';
1228 printk("ch = %c i = %d\n",ch,i);
1229
1230 }else if ((ch&0xff) == 'e' && (i == 4)){
1231 uart_poll_char[4] = 'e';
1232 printk("ch = %c i = %d\n",ch,i);
1233
1234 }else if ((ch&0xff) == 'n' && (i == 5)){
1235 uart_poll_char[5] = 'n';
1236 printk("ch = %c i = %d\n",ch,i);
1237 g_console_open_flag = 1;
1238 printk("ch = %c i = %d,g_console_open_flag:%d\n",ch,i,g_console_open_flag);
1239 }else {
1240 i = 10;
1241 }
1242 i++;
1243 }
1244#endif
1245 flag = TTY_NORMAL;
1246 if(zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
1247 {
1248 if(zup->port.icount.rx < UART_PORT_AUTOBAUD_BYTE)
1249 {
1250 uart_port_autobaud_buffer[zup->port.icount.rx] = ch;
1251 }
1252 else
1253 {
1254 uart_port_autobaud_gtflag = 1 ;
1255 }
1256 }
1257 zup->port.icount.rx++;
1258 if(zup->autobaud_state == UART_PORT_AUTOBAUD_OFF)
1259 {
1260 if(fifotaken < 16){
1261 uart_poll_char[fifotaken] = ch & 0xFF;
1262 }
1263 fifotaken++;
1264
1265 if (unlikely(ch & UART_DR_ERROR)) {
1266 if (ch & UART_DR_BE) {
1267 ch &= ~(UART_DR_FE | UART_DR_PE);
1268 zup->port.icount.brk++;
1269 if (uart_handle_break(&zup->port))
1270 continue;
1271 } else if (ch & UART_DR_PE)
1272 zup->port.icount.parity++;
1273 else if (ch & UART_DR_FE)
1274 zup->port.icount.frame++;
1275 else if (ch & UART_DR_OE){
1276 zup->port.icount.overrun++;
1277 //if(!uart_console(&zup->port))
1278 // BUG_ON(1);
1279 }
1280 ch &= zup->port.read_status_mask;
1281
1282 if (ch & UART_DR_BE)
1283 flag = TTY_BREAK;
1284 else if (ch & UART_DR_PE)
1285 flag = TTY_PARITY;
1286 else if (ch & UART_DR_FE)
1287 flag = TTY_FRAME;
1288 }
1289
1290 if (uart_handle_sysrq_char(&zup->port, ch & 255))
1291 continue;
1292 if(g_console_open_flag || port->line != DEBUG_CONSOLE){
1293 uart_insert_char(&zup->port, ch, UART_DR_OE, ch, flag);
1294 }
1295 }
1296 }
1297
1298 test_uart_static(zup->port.line, uart_poll_char, fifotaken, 3);
1299
1300 return fifotaken;
1301}
1302
1303/****************************************************************************/
1304static void zx29_uart_rx_chars(struct zx29_uart_port *zup)
1305{
1306 unsigned long flags;
1307
1308 //struct tty_struct *tty = zup->port.state->port.tty;
1309
1310 zx29_uart_fifo_to_tty(zup);
1311 spin_unlock(&zup->port.lock);
1312
1313 tty_flip_buffer_push(&zup->port.state->port);
1314
1315#if CONFIG_SERIAL_ZX29_DMA
1316 if(!uart_console(&zup->port)){//console doesn't use dma rcv data
1317 if (zx29_dma_rx_available(zup)) {
1318 if (zx29_dma_rx_trigger_dma(zup)) {
1319 dev_dbg(zup->port.dev, "could not trigger RX DMA job "
1320 "fall back to interrupt mode again\n");
1321 zup->imr |= UART_RXIM;
1322 } else{
1323 zup->imr &= ~UART_RXIM;
1324 }
1325 UART_PUT_IMSC(&zup->port,zup->imr);
1326 }
1327 }
1328#endif
1329RX_END:
1330 spin_lock(&zup->port.lock);
1331
1332}
1333
1334/****************************************************************************/
1335static void zx29_uart_tx_chars(struct zx29_uart_port *zup)
1336{
1337 struct circ_buf *xmit = &zup->port.state->xmit;
1338 unsigned long flags;
1339 int count;
1340
1341 if (zup->port.x_char) {
1342 UART_PUT_CHAR(&zup->port, zup->port.x_char);
1343 zup->port.icount.tx++;
1344 zup->port.x_char = 0;
1345 return;
1346 }
1347 if (uart_circ_empty(xmit) || uart_tx_stopped(&zup->port)) {
1348 zx29_uart_stop_tx(&zup->port);
1349 return;
1350 }
1351#if CONFIG_SERIAL_ZX29_DMA
1352 /* If we are using DMA mode, try to send some characters. */
1353 if(!uart_console(&(zup->port)))
1354 {
1355 if (zx29_dma_tx_irq(zup))
1356 return;
1357 }
1358#endif
1359 count = zup->port.fifosize >> 1;
1360 do {
1361 zx29_uart_putc(&zup->port, xmit->buf[xmit->tail]);
1362 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1363 zup->port.icount.tx++;
1364 if (uart_circ_empty(xmit))
1365 break;
1366 } while (--count > 0);
1367
1368 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1369 {
1370 spin_unlock(&zup->port.lock);
1371 //uart_write_wakeup(&zup->port);
1372 tasklet_schedule(&zup->write_wakeup);
1373 spin_lock(&zup->port.lock);
1374 }
1375
1376 if (uart_circ_empty(xmit))
1377 zx29_uart_stop_tx(&zup->port);
1378}
1379
1380#if CONFIG_SERIAL_ZX29_DMA
1381
1382dma_peripheral_id uart_get_rx_dma_peripheral_id(struct zx29_uart_port *zup)
1383{
1384 struct uart_port *port = &zup->port;
1385 if(port->line < UART0 || port->line > UART4){
1386 printk("get_rx_dma_peripheral_id,fail, invalid port->line:%d\n", port->line);
1387 }
1388 if(port->line == UART0){
1389 return DMA_CH_UART0_RX;
1390 } else if(port->line == UART1){
1391 return DMA_CH_UART1_RX;
1392 }else if(port->line == UART2){
1393 return DMA_CH_UART2_RX;
1394 }
1395// else if(port->line == UART3){
1396// return DMA_CH_UART3_RX;
1397// }else if(port->line == UART4){
1398// return DMA_CH_UART4_RX;
1399// }
1400
1401 return DMA_CH_NUM;
1402}
1403
1404/*
1405 * We received a transmit interrupt without a pending X-char but with
1406 * pending characters.
1407 * Locking: called with port lock held and IRQs disabled.
1408 * Returns:
1409 * false if we want to use PIO to transmit
1410 * true if we queued a DMA buffer
1411 */
1412static bool zx29_dma_tx_irq(struct zx29_uart_port *zup)
1413{
1414 if (!zup->using_tx_dma)
1415 return false;
1416
1417 /*
1418 * If we already have a TX buffer queued, but received a
1419 * TX interrupt, it will be because we've just sent an X-char.
1420 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
1421 */
1422 if (zup->dmatx.queued) {
1423 zup->dmacr |= UART_TXDMAE;
1424 UART_PUT_DMACR(&zup->port, zup->dmacr);
1425 zup->imr &= ~UART_TXIM;
1426 UART_PUT_IMSC(&zup->port,zup->imr);
1427 return true;
1428 }
1429
1430 /*
1431 * We don't have a TX buffer queued, so try to queue one.
1432 * If we successfully queued a buffer, mask the TX IRQ.
1433 */
1434 if (zx29_uart_dma_tx_chars(zup) > 0) {
1435 zup->imr &= ~UART_TXIM;
1436 UART_PUT_IMSC(&zup->port,zup->imr);
1437 return true;
1438 }
1439 return false;
1440}
1441
1442
1443/*
1444 * Stop the DMA transmit (eg, due to received XOFF).
1445 * Locking: called with port lock held and IRQs disabled.
1446 */
1447static inline void zx29_dma_tx_stop(struct zx29_uart_port *zup)
1448{
1449 if (zup->dmatx.queued) {
1450 zup->dmacr &= ~UART_TXDMAE;
1451 UART_PUT_DMACR(&zup->port, zup->dmacr);
1452 }
1453}
1454
1455
1456/*
1457 * Try to start a DMA transmit, or in the case of an XON/OFF
1458 * character queued for send, try to get that character out ASAP.
1459 * Locking: called with port lock held and IRQs disabled.
1460 * Returns:
1461 * false if we want the TX IRQ to be enabled
1462 * true if we have a buffer queued
1463 */
1464static inline bool zx29_dma_tx_start(struct zx29_uart_port *zup)
1465{
1466 u16 dmacr;
1467
1468 if (!zup->using_tx_dma)
1469 return false;
1470
1471 if (!zup->port.x_char) {
1472 /* no X-char, try to push chars out in DMA mode */
1473 bool ret = true;
1474
1475 if (!zup->dmatx.queued) {
1476 if (zx29_uart_dma_tx_chars(zup) > 0) {
1477 zup->imr &= ~UART_TXIM;
1478 ret = true;
1479 } else {
1480 zup->imr |= UART_TXIM;
1481 ret = false;
1482 }
1483 UART_PUT_IMSC(&zup->port,zup->imr);
1484 } else if (!(zup->dmacr & UART_TXDMAE)) {
1485 zup->dmacr |= UART_TXDMAE;
1486 UART_PUT_DMACR(&zup->port, zup->dmacr);
1487 }
1488 return ret;
1489 }
1490
1491 /*
1492 * We have an X-char to send. Disable DMA to prevent it loading
1493 * the TX fifo, and then see if we can stuff it into the FIFO.
1494 */
1495 dmacr = zup->dmacr;
1496 zup->dmacr &= ~UART_TXDMAE;
1497 UART_PUT_DMACR(&zup->port, zup->dmacr);
1498
1499 if (UART_GET_FR(&zup->port) & UART_FR_TXFF) {
1500 /*
1501 * No space in the FIFO, so enable the transmit interrupt
1502 * so we know when there is space. Note that once we've
1503 * loaded the character, we should just re-enable DMA.
1504 */
1505 return false;
1506 }
1507
1508 UART_PUT_CHAR(&zup->port, zup->port.x_char);
1509 //writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1510 zup->port.icount.tx++;
1511 zup->port.x_char = 0;
1512
1513 /* Success - restore the DMA state */
1514 zup->dmacr = dmacr;
1515 UART_PUT_DMACR(&zup->port, zup->dmacr);
1516 //writew(dmacr, uap->port.membase + UART011_DMACR);
1517
1518 return true;
1519}
1520
1521/****************************************************************************/
1522
1523//#if CONFIG_SERIAL_ZX29_DMA
1524/*
1525 * Flush the transmit buffer.
1526 * Locking: called with port lock held and IRQs disabled.
1527 */
1528static void zx29_dma_flush_buffer(struct uart_port *port)
1529{
1530 struct zx29_uart_port *zup = (struct zx29_uart_port *)port;
1531 if (!zup->using_tx_dma)
1532 return;
1533
1534 /* Avoid deadlock with the DMA engine callback */
1535 //dmaengine_terminate_all(zup->dmatx.chan);
1536 if (zup->dmatx.queued) {
1537
1538 //printk(KERN_INFO "zx29_dma_flush_buffer enter[%s][%d] Port[%d]\n",__func__,__LINE__,port->line);
1539 dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
1540 DMA_TO_DEVICE);
1541 zup->dmatx.queued = false;
1542 zup->dmacr &= ~UART_TXDMAE;
1543 UART_PUT_DMACR(&zup->port, zup->dmacr);
1544 }
1545}
1546
1547static int zx29_dma_rx_trigger_dma(struct zx29_uart_port *zup)
1548{
1549 struct dma_chan *rxchan = zup->dmarx.chan;
1550 struct zx29_dmarx_data *dmarx = &zup->dmarx;
1551 struct dma_async_tx_descriptor *desc;
1552 struct zx29_sgbuf *sgbuf;
1553
1554 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
1555 if (!rxchan)
1556 {
1557 printk("[%s][%d]\n",__func__,__LINE__);
1558 return -EIO;
1559 }
1560
1561 /* Start the RX DMA job */
1562
1563 sgbuf = zup->dmarx.use_buf_b ?
1564 &zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
1565 /*
1566
1567 sgbuf = zup->dmarx.use_buf_b ?
1568 &zup->dmarx.sgbuf_a : &zup->dmarx.sgbuf_b;
1569 */
1570 zup->dmarx.rx_def[zup->dmarx.rx_index].link_addr=0;
1571 zup->dmarx.rx_def[zup->dmarx.rx_index].dest_addr=(unsigned int)(sgbuf->dma_addr);
1572 zup->dmarx.rx_def[zup->dmarx.rx_index].count=ZX29_DMA_BUFFER_SIZE;//fifo or max buffer?
1573 wmb();
1574
1575 dmaengine_slave_config(rxchan, (struct dma_slave_config*)&zup->dmarx.rx_def[zup->dmarx.rx_index]);
1576 desc = rxchan->device->device_prep_interleaved_dma(rxchan,NULL,0);
1577
1578
1579 /*
1580 * If the DMA engine is busy and cannot prepare a
1581 * channel, no big deal, the driver will fall back
1582 * to interrupt mode as a result of this error code.
1583 */
1584 if (!desc) {
1585 printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
1586 sc_debug_info_record(MODULE_ID_CAP_UART, "uart%d ERROR DESC \n",zup->port.line);
1587 zup->dmarx.running = false;
1588 dmaengine_terminate_all(rxchan);
1589 //zx29_dma_force_stop(rx_id);
1590 return -EBUSY;
1591 }
1592
1593 /* Some data to go along to the callback */
1594 desc->callback = uart_dma_rx_callback;
1595 desc->callback_param = zup;
1596 zup->curr_sg = sgbuf;
1597 wmb();
1598
1599 dmarx->cookie = dmaengine_submit(desc);
1600 dma_async_issue_pending(rxchan);
1601 atomic_inc(&zup->dmarx.count);
1602 zup->dmarx.rx_index = (zup->dmarx.rx_index +1)%UART_DMA_RX_MAX_COUNT;
1603 zup->dmacr |= UART_RXDMAE;
1604 UART_PUT_DMACR(&zup->port, zup->dmacr);
1605 zup->dmarx.running = true;
1606 zup->dmarx.used = true;
1607 zup->imr &= ~(UART_RXIM | UART_RTIM);
1608 UART_PUT_IMSC(&zup->port,zup->imr);
1609
1610
1611 return 0;
1612}
1613static int zx29_dma_rx_trigger_dma_use_dma_cyclic(struct zx29_uart_port *zup)
1614{
1615 struct dma_chan *rxchan = zup->dmarx.chan;
1616 struct zx29_dmarx_data *dmarx = &zup->dmarx;
1617 struct dma_async_tx_descriptor *desc;
1618 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
1619 int uart_id = zup->port.line;
1620 if (!rxchan)
1621 {
1622 printk("[%s][%d]\n",__func__,__LINE__);
1623 return -EIO;
1624 }
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]1625
1626 if(uart_dma_cycle[zup->port.line].used)
1627 uart_id = uart_id + 3;
1628
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1629 dmaengine_slave_config(rxchan, (struct dma_slave_config*)&uart_dma_cycle[uart_id].rxdef);
1630 desc = rxchan->device->device_prep_dma_cyclic(rxchan,NULL,(ZX29_DMA_BUFFER_SIZE *5) , ZX29_DMA_BUFFER_SIZE,0,0);
1631 if (!desc) {
1632 printk(KERN_INFO "!!ERROR DESC !!![%s][%d]Port:[%d]\n",__func__,__LINE__,zup->port.line);
1633 zup->dmarx.running = false;
1634 dmaengine_terminate_all(rxchan);
1635 return -EBUSY;
1636 }
1637 desc->callback = uart_dma_rx_callback_use_dma_cyclic;
1638 desc->callback_param = zup;
1639 wmb();
1640 dmarx->cookie = dmaengine_submit(desc);
1641 dma_async_issue_pending(rxchan);
1642 zup->dmacr |= UART_RXDMAE;
1643 UART_PUT_DMACR(&zup->port, zup->dmacr);
1644 uart_dma_cycle[uart_id].flg_enter_th = 0;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]1645 if(uart_dma_cycle[zup->port.line].used){
1646 uart_dma_cycle[zup->port.line].used = false;
1647 uart_dma_cycle[zup->port.line+3].used = true;
1648 }else{
1649 uart_dma_cycle[zup->port.line].used = true;
1650 uart_dma_cycle[zup->port.line+3].used = false;
1651 }
1652
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1653 zup->dmarx.running = true;
1654 zup->dmarx.used = true;
1655 zup->imr &= ~(UART_RXIM | UART_RTIM);
1656 UART_PUT_IMSC(&zup->port,zup->imr);
1657 return 0;
1658}
1659
1660void uart_dma_rx_callback(void *data)
1661{
1662 unsigned long flags;
1663
1664 struct zx29_uart_port *zup = (struct zx29_uart_port *)data;
1665 int uart_id = zup->port.line;
1666 struct zx29_dmarx_data *dmarx = &zup->dmarx;
1667 struct dma_chan *rxchan = dmarx->chan;
1668 struct device *dev = NULL;
1669// struct dma_tx_state state;
1670 unsigned int ris_status;
1671
1672 bool lastbuf;
1673 int dma_count = 0;
1674 struct zx29_sgbuf *sgbuf = zup->curr_sg;
1675 size_t pending;
1676
1677 spin_lock_irqsave(&zup->port.lock, flags);
1678 ris_status = UART_GET_RIS(&zup->port);
1679 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
1680 if(ris_status & UART_OEIS){
1681 zup->port.icount.overrun++;
1682 g_uart_overrun[uart_id] = 4;
1683 test_uart_static(zup->port.line, NULL, 0, 20);
1684 //if(!uart_console(&zup->port))
1685 // BUG_ON(1);
1686 }
1687 if(ris_status & UART_BEIS)
1688 zup->port.icount.brk++;
1689 if(ris_status & UART_PEIS)
1690 zup->port.icount.parity++;
1691 if(ris_status & UART_FEIS)
1692 zup->port.icount.frame++;
1693 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
1694 }
1695 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
1696 zx29_dma_stop(rx_id);
1697
1698 dev = zup->dmarx.chan->device->dev;
1699 zup->dmacr &= ~UART_RXDMAE;
1700 UART_PUT_DMACR(&zup->port,zup->dmacr);
1701
1702 //spin_lock_irqsave(&zup->port.lock, flags);
1703 zup->sg2tty = sgbuf;
1704// rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1705 zup->sg2tty_len = zup->sg2tty->sg.length - zx29_dma_get_transfer_num(rx_id);
1706 //zx29_dma_force_stop(rx_id);
1707 // dmaengine_terminate_all(rxchan);
1708 dmarx->use_buf_b = ! dmarx->use_buf_b;
1709 wmb();
1710 //BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
1711 /* Then we terminate the transfer - we now know our residue */
1712 //dmaengine_terminate_all(rxchan);
1713
1714 zup->dmarx.running = false;
1715 zup->dmarx.used = false;
1716 test_uart_static(zup->port.line, NULL, 0, 9);
1717 if (zx29_dma_rx_trigger_dma(zup)) {
1718 printk("rx_dma_chars RXDMA start fail\n");
1719 zup->imr |= UART_RXIM;
1720 UART_PUT_IMSC(&zup->port,zup->imr);
1721 }else{
1722 zup->pre_pending = 0;
1723 zup->dmarx.used = true;
1724 zup->work_state = true;
1725 }
1726 spin_unlock_irqrestore(&zup->port.lock, flags);
1727
1728 up(&zup->sema);
1729}
1730
1731void uart_dma_rx_callback_use_dma_cyclic(void *data)
1732{
1733 unsigned long flags;
1734 struct zx29_uart_port *zup = (struct zx29_uart_port *)data;
1735 unsigned int ris_status;
1736 int uart_id = zup->port.line;
1737 spin_lock_irqsave(&zup->port.lock, flags);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]1738 if(!uart_dma_cycle[zup->port.line].used)
1739 uart_id = uart_id + 3;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1740 uart_dma_cycle[uart_id].cnt_callback_total++;
1741 uart_dma_cycle[uart_id].cnt_callback++;
1742 ris_status = UART_GET_RIS(&zup->port);
1743 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
1744 if(ris_status & UART_OEIS){
1745 zup->port.icount.overrun++;
1746 uart_dma_cycle[uart_id].flg_overrun = 1;
1747 }
1748 if(ris_status & UART_BEIS){
1749 uart_dma_cycle[uart_id].flg_be = 1;
1750 zup->port.icount.brk++;
1751 }
1752 if(ris_status & UART_PEIS){
1753 uart_dma_cycle[uart_id].flg_pe = 1;
1754 zup->port.icount.parity++;
1755 }
1756 if(ris_status & UART_FEIS){
1757 uart_dma_cycle[uart_id].flg_fe = 1;
1758 zup->port.icount.frame++;
1759 }
1760 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
1761 }
1762 spin_unlock_irqrestore(&zup->port.lock, flags);
1763 test_uart_static(zup->port.line, NULL, 0, 26);
1764 up(&zup->sema_cyclic);
1765}
1766static inline void zx29_dma_rx_stop(struct zx29_uart_port *zup)
1767{
1768 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
1769 //zx29_dma_force_stop(rx_id);
1770 //dmaengine_terminate_all(zup->dmarx.chan);
1771 /* FIXME. Just disable the DMA enable */
1772 zup->dmacr &= ~UART_RXDMAE;
1773 UART_PUT_DMACR(&zup->port,zup->dmacr);
1774 zx29_dma_stop(rx_id);
1775#if 0
1776 //do we need check data received?
1777 if(zup->pre_pending){
1778 printk("pre_pending :%d\n ", zup->pre_pending);
1779 }
1780#endif
1781 zup->curr_sg = NULL;
1782}
1783
1784static void zx29_dma_remove(struct zx29_uart_port *zup)
1785{
1786 /* TODO: remove the initcall if it has not yet executed */
1787 if (zup->dmatx.chan)
1788 dma_release_channel(zup->dmatx.chan);
1789 if (zup->dmarx.chan)
1790 dma_release_channel(zup->dmarx.chan);
1791}
1792
1793
1794static void zx29_dma_shutdown(struct zx29_uart_port *zup)
1795{
1796 unsigned long flags;
1797 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
1798
1799 if (!(zup->using_tx_dma || zup->using_rx_dma))
1800 return;
1801 /* Disable RX and TX DMA */
1802 while(UART_GET_FR(&zup->port) & (UART_FR_TXBUSY | UART_FR_TXBUSY))
1803 barrier();
1804
1805 spin_lock_irqsave(&zup->port.lock, flags);
1806 //zx29_dma_force_stop(rx_id);
1807 // dmaengine_terminate_all(zup->dmarx.chan);
1808 zup->dmacr &= ~(UART_DMAONERR | UART_RXDMAE | UART_TXDMAE);
1809 UART_PUT_DMACR(&zup->port,zup->dmacr);
1810 zx29_dma_stop(rx_id);
1811 zup->curr_sg = NULL;
1812 spin_unlock_irqrestore(&zup->port.lock, flags);
1813 if (zup->using_tx_dma) {
1814 /* In theory, this should already be done by zx29_dma_flush_buffer */
1815 dmaengine_terminate_all(zup->dmatx.chan);
1816 if (zup->dmatx.queued) {
1817 dma_unmap_sg(zup->dmatx.chan->device->dev, &zup->dmatx.sg, 1,
1818 DMA_TO_DEVICE);
1819 zup->dmatx.queued = false;
1820 }
1821 if(!zup->dmatx.buf)
1822 kfree(zup->dmatx.buf);
1823 zup->dmatx.buf = NULL;
1824 zup->using_tx_dma = false;
1825 }
1826 if (zup->using_rx_dma) {
1827 //dmaengine_terminate_all(zup->dmarx.chan);
1828 /* Clean up the RX DMA */
1829 if(!zup->uart_power_mode){
1830 zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1831 zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1832 }else if(zup->uart_power_mode == 1){
1833 uart_dma_cycle_deinit(zup);
1834 }else
1835 printk("uart%d dma shutdown fail.\n",zup->port.line);
1836 zup->using_rx_dma = false;
1837 zup->dmarx.used = false;
1838 zup->dmarx.running = false;
1839 zup->dmarx.use_buf_b = false;
1840 zup->dmarx.rx_index = 0;
1841 }
1842 zup->pre_pending = 0;
1843 zup->work_state = false;
1844
1845}
1846
1847static void zx29_shutdown_channel(struct zx29_uart_port *zup,
1848 unsigned int lcrh)
1849{
1850 unsigned long val;
1851
1852 val = UART_GET_LCRH(&zup->port);
1853 val &= ~(UART_LCRH_BRK | UART_LCRH_FEN);
1854 UART_PUT_LCRH(&zup->port, val);
1855}
1856
1857
1858static inline bool zx29_dma_rx_available(struct zx29_uart_port *zup)
1859{
1860 return zup->using_rx_dma;
1861}
1862
1863static inline bool zx29_dma_rx_running(struct zx29_uart_port *zup)
1864{
1865 return zup->using_rx_dma && zup->dmarx.running;
1866}
1867
1868static inline bool zx29_dma_rx_used(struct zx29_uart_port *zup)
1869{
1870 return zup->using_rx_dma && zup->dmarx.used;
1871}
1872
1873static inline bool zx29_dma_rx_work_scheduled(struct zx29_uart_port *zup)
1874{
1875 return zup->using_rx_dma && zup->work_state;
1876}
1877
1878
1879void uart_dma_tx_callback(void *data)
1880{
1881 struct zx29_uart_port *zup = data;
1882 struct zx29_dmatx_data *dmatx = &zup->dmatx;
1883
1884 unsigned long flags;
1885 u16 dmacr;
1886 spin_lock_irqsave(&zup->port.lock, flags);
1887 if (zup->dmatx.queued)
1888 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
1889 DMA_TO_DEVICE);
1890
1891 dmacr = zup->dmacr;
1892 zup->dmacr = dmacr & ~UART_TXDMAE;
1893 UART_PUT_DMACR(&zup->port,zup->dmacr);
1894
1895 /*
1896 * If TX DMA was disabled, it means that we've stopped the DMA for
1897 * some reason (eg, XOFF received, or we want to send an X-char.)
1898 *
1899 * Note: we need to be careful here of a potential race between DMA
1900 * and the rest of the driver - if the driver disables TX DMA while
1901 * a TX buffer completing, we must update the tx queued status to
1902 * get further refills (hence we check dmacr).
1903 */
1904 if (!(dmacr & UART_TXDMAE) || uart_tx_stopped(&zup->port) ||
1905 uart_circ_empty(&zup->port.state->xmit)) {
1906 zup->dmatx.queued = false;
1907
1908
1909 zx_cpuidle_set_free(IDLE_FLAG_UART);
1910
1911
1912 spin_unlock_irqrestore(&zup->port.lock, flags);
1913 return;
1914 }
1915
1916 if (zx29_uart_dma_tx_chars(zup) <= 0) {
1917 /*
1918 * We didn't queue a DMA buffer for some reason, but we
1919 * have data pending to be sent. Re-enable the TX IRQ.
1920 */
1921 zup->imr |= UART_TXIM;
1922 UART_PUT_IMSC(&zup->port, zup->imr);
1923 }
1924 spin_unlock_irqrestore(&zup->port.lock, flags);
1925}
1926
1927static int zx29_uart_dma_tx_chars(struct zx29_uart_port *zup)
1928{
1929 struct zx29_dmatx_data *dmatx = &zup->dmatx;
1930 struct dma_chan *tx_chan = dmatx->chan;
1931 struct dma_device *dma_dev = tx_chan->device;
1932 struct dma_async_tx_descriptor *desc;
1933 struct circ_buf *xmit = &zup->port.state->xmit;
1934 unsigned int count;
1935
1936 /*
1937 * Try to avoid the overhead involved in using DMA if the
1938 * transaction fits in the first half of the FIFO, by using
1939 * the standard interrupt handling. This ensures that we
1940 * issue a uart_write_wakeup() at the appropriate time.
1941 */
1942
1943 count = uart_circ_chars_pending(xmit);
1944 if (count < (16 >> 1)) {
1945 zup->dmatx.queued = false;
1946 return 0;
1947 }
1948
1949 if (xmit->tail < xmit->head)
1950 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
1951 else {
1952 size_t first = UART_XMIT_SIZE - xmit->tail;
1953 size_t second ;//= xmit->head;
1954
1955 if (first > count)
1956 first = count;
1957 second = count - first;
1958 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
1959 if (second)
1960 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
1961 }
1962 dmatx->sg.length = count;
1963
1964 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
1965 zup->dmatx.queued = false;
1966 dev_dbg(zup->port.dev, "unable to map TX DMA\n");
1967 return -EBUSY;
1968 }
1969
1970
1971 zup->dmatx.tx_def.link_addr=0;
1972 zup->dmatx.tx_def.src_addr=(unsigned int)(dmatx->sg.dma_address);
1973 zup->dmatx.tx_def.count=count;
1974 wmb();
1975 dmaengine_slave_config(tx_chan, (struct dma_slave_config*)&zup->dmatx.tx_def);
1976 desc = tx_chan->device->device_prep_interleaved_dma(tx_chan,NULL,0);
1977
1978 if (!desc) {
1979 printk(KERN_INFO "!!!!!ERROR TX DESC[%s][%d]\n",__func__,__LINE__);
1980 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
1981 zup->dmatx.queued = false;
1982 /*
1983 * If DMA cannot be used right now, we complete this
1984 * transaction via IRQ and let the TTY layer retry.
1985 */
1986 dev_dbg(zup->port.dev, "TX DMA busy\n");
1987 return -EBUSY;
1988 }
1989 desc->callback = (dma_async_tx_callback)uart_dma_tx_callback;
1990 desc->callback_param = (void *)zup;
1991 dmaengine_submit(desc);
1992 dma_async_issue_pending(tx_chan);
1993 atomic_inc(&zup->dmatx.count);
1994 zup->dmacr |= UART_TXDMAE;
1995 UART_PUT_DMACR(&zup->port,zup->dmacr);
1996 zup->dmatx.queued = true;
1997
1998 /*
1999 * Now we know that DMA will fire, so advance the ring buffer
2000 * with the stuff we just dispatched.
2001 */
2002 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
2003 zup->port.icount.tx += count;
2004
2005 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
2006 //uart_write_wakeup(&zup->port);
2007 tasklet_schedule(&zup->write_wakeup);
2008
2009 return 1;
2010}
2011
2012static void zx29_uart_dma_rx_chars(struct zx29_uart_port *zup,
2013 //u32 pending, bool use_buf_b,
2014 u32 pending, struct zx29_sgbuf *sgbuf,
2015 bool readfifo, unsigned long *flags)
2016{
2017 struct tty_struct *tty = zup->port.state->port.tty;
2018#if 0
2019 struct zx29_sgbuf *sgbuf = use_buf_b ?
2020 &zup->dmarx.sgbuf_b : &zup->dmarx.sgbuf_a;
2021#endif
2022 struct device *dev = zup->dmarx.chan->device->dev;
2023 int dma_count = 0;
2024 u32 fifotaken = 0; /* only used for vdbg() */
2025 //unsigned long flags;
2026
2027 /* Pick everything from the DMA first */
2028 if (pending) {
2029 /* Sync in buffer */
2030
2031 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
2032
2033 /*
2034 * First take all chars in the DMA pipe, then look in the FIFO.
2035 * Note that tty_insert_flip_buf() tries to take as many chars
2036 * as it can.
2037 */
2038
2039 spin_unlock_irqrestore(&zup->port.lock, *flags);
2040
2041 dma_count = tty_insert_flip_string(&zup->port.state->port,
2042 sgbuf->buf, pending);
2043
2044 test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
2045 spin_lock_irqsave(&zup->port.lock, *flags);
2046 /* Return buffer to device */
2047 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
2048
2049 zup->port.icount.rx += dma_count;
2050 if (dma_count < pending)
2051 dev_info(zup->port.dev,
2052 "couldn't insert all characters (TTY is full?)\n");
2053 }
2054
2055 /*
2056 * Only continue with trying to read the FIFO if all DMA chars have
2057 * been taken first.
2058 */
2059 //if (dma_count == pending && readfifo) {
2060 if (readfifo) {
2061 /* Clear any error flags */
2062 //UART_PUT_ICR(&zup->port,UART_OEIC | UART_BEIC | UART_PEIC | UART_FEIC);
2063 /*
2064 * If we read all the DMA'd characters, and we had an
2065 * incomplete buffer, that could be due to an rx error, or
2066 * maybe we just timed out. Read any pending chars and check
2067 * the error status.
2068 *
2069 * Error conditions will only occur in the FIFO, these will
2070 * trigger an immediate interrupt and stop the DMA job, so we
2071 * will always find the error in the FIFO, never in the DMA
2072 * buffer.
2073 */
2074 test_uart_static(zup->port.line, NULL, 0, 7);
2075 fifotaken = zx29_uart_fifo_to_tty(zup);
2076 }
2077 if((pending > 0) || (fifotaken > 0)) {
2078 spin_unlock(&zup->port.lock);
2079 tty_flip_buffer_push(&zup->port.state->port);
2080 spin_lock(&zup->port.lock);
2081 }
2082}
2083static void zx29_uart_deal_dma_fifo_rx_chars_cyclic(struct zx29_uart_port *zup,
2084 u32 pending, struct zx29_sgbuf *sgbuf,
2085 unsigned long *flags, char *fifo_buf, int fifo_len)
2086{
2087 struct tty_struct *tty = zup->port.state->port.tty;
2088 struct device *dev = zup->dmarx.chan->device->dev;
2089 int dma_count = 0;
2090 int fifo_count = 0;
2091 u32 fifotaken = 0; /* only used for vdbg() */
2092 if ((pending) && (pending != 4096)) {
2093 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
2094 spin_unlock_irqrestore(&zup->port.lock, *flags);
2095 dma_count = tty_insert_flip_string(&zup->port.state->port,
2096 sgbuf->buf, pending);
2097 test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2098#if UART_DEBUG_RECORDER_BYTE
2099 uart_debug(sgbuf->buf, pending);
2100#endif
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2101 spin_lock_irqsave(&zup->port.lock, *flags);
2102 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
2103 zup->port.icount.rx += dma_count;
2104 if (dma_count < pending)
2105 dev_info(zup->port.dev,
2106 "couldn't insert all characters (TTY is full?)\n");
2107 }
2108 if(fifo_len){
2109 spin_unlock_irqrestore(&zup->port.lock, *flags);
2110 fifo_count = tty_insert_flip_string(&zup->port.state->port,
2111 fifo_buf, fifo_len);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2112 test_uart_static(zup->port.line, fifo_buf, fifo_len, 50);
2113#if UART_DEBUG_RECORDER_BYTE
2114 uart_debug(fifo_buf, fifo_len);
2115#endif
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2116 fifo_buf[0] = '\0';
2117 fifo_buf[1] = '\0';
2118 fifo_buf[2] = '\0';
2119 spin_lock_irqsave(&zup->port.lock, *flags);
2120 }
2121 zup->port.icount.rx += fifo_count;
2122 if(((pending) && (pending != 4096)) || (fifo_len > 0)){
2123 spin_unlock(&zup->port.lock);
2124 tty_flip_buffer_push(&zup->port.state->port);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2125 test_uart_static(zup->port.line, NULL, (fifo_count+dma_count), 51);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2126 spin_lock(&zup->port.lock);
2127 }
2128}
2129
2130static void zx29_uart_deal_dma_fifo_rx_chars(struct zx29_uart_port *zup,
2131 u32 pending, struct zx29_sgbuf *sgbuf,
2132 unsigned long *flags, char *fifo_buf, int fifo_len)
2133{
2134 struct tty_struct *tty = zup->port.state->port.tty;
2135
2136 struct device *dev = zup->dmarx.chan->device->dev;
2137 int dma_count = 0;
2138 int fifo_count = 0;
2139 u32 fifotaken = 0; /* only used for vdbg() */
2140 if (pending) {
2141 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
2142 spin_unlock_irqrestore(&zup->port.lock, *flags);
2143 dma_count = tty_insert_flip_string(&zup->port.state->port,
2144 sgbuf->buf, pending);
2145 test_uart_static(zup->port.line, sgbuf->buf, pending, 6);
2146 spin_lock_irqsave(&zup->port.lock, *flags);
2147 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
2148 spin_unlock_irqrestore(&zup->port.lock, *flags);
2149 zup->port.icount.rx += dma_count;
2150 if (dma_count < pending)
2151 dev_info(zup->port.dev,
2152 "couldn't insert all characters (TTY is full?)\n");
2153 }
2154
2155 if(fifo_len){
2156 //printk("qq >> fifo len %d.\n",fifo_len);
2157 fifo_count = tty_insert_flip_string(&zup->port.state->port,
2158 fifo_buf, fifo_len);
2159 //printk("qq >>fifo count %d,buf is %x %x %x .\n",fifo_count, fifo_buf[0],fifo_buf[1],fifo_buf[2]);
2160 fifo_buf[0] = '\0';
2161 fifo_buf[1] = '\0';
2162 fifo_buf[2] = '\0';
2163 //memset(fifo_buf, '\0', 4);
2164 }
2165
2166 zup->port.icount.rx += fifo_count;
2167 test_uart_static(zup->port.line, fifo_buf, fifo_count, 18);
2168 if(pending > 0 || (fifo_len > 0)){
2169 tty_flip_buffer_push(&zup->port.state->port);
2170 spin_lock_irqsave(&zup->port.lock, *flags);
2171 }
2172}
2173
2174#if 0
2175static void zx29_dma_rx_irq(struct zx29_uart_port *zup, unsigned long *flags)
2176{
2177 struct zx29_dmarx_data *dmarx = &zup->dmarx;
2178 struct dma_chan *rxchan = dmarx->chan;
2179 struct zx29_sgbuf *sgbuf = dmarx->use_buf_b ?
2180 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
2181 size_t pending;
2182 struct dma_tx_state state;
2183 enum dma_status dmastat;
2184 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
2185
2186 uint32_t ris_status = UART_GET_RIS(&zup->port);
2187 //printk("rx irq\n");
2188 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
2189 if(ris_status & UART_OEIS){
2190 zup->port.icount.overrun++;
2191 //if(!uart_console(&zup->port))
2192 // BUG_ON(1);
2193 }
2194 if(ris_status & UART_BEIS)
2195 zup->port.icount.brk++;
2196 if(ris_status & UART_PEIS)
2197 zup->port.icount.parity++;
2198 if(ris_status & UART_FEIS)
2199 zup->port.icount.frame++;
2200
2201 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
2202 }
2203
2204 if(zx29_dma_rx_running(zup)){
2205 /*
2206 * Pause the transfer so we can trust the current counter,
2207 * do this before we pause the block, else we may
2208 * overflow the FIFO.
2209 */
2210 // if(zx29_dma_stop(rx_id))
2211 // printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
2212 //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
2213 //zx29_dma_force_stop(rx_id);
2214 //dmaengine_terminate_all(rxchan);
2215
2216 //dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
2217
2218 /* Disable RX DMA - incoming data will wait in the FIFO */
2219 zup->dmacr &= ~UART_RXDMAE;
2220 UART_PUT_DMACR(&zup->port,zup->dmacr);
2221 zx29_dma_stop(rx_id);
2222 zup->dmarx.running = false;
2223 zup->dmarx.used = false;
2224 pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
2225 BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
2226 /* Then we terminate the transfer - we now know our residue */
2227 //dmaengine_terminate_all(rxchan);
2228
2229 dmarx->use_buf_b = !dmarx->use_buf_b;
2230 /*
2231 * This will take the chars we have so far and insert
2232 * into the framework.
2233 */
2234 zx29_uart_dma_rx_chars(zup, pending, sgbuf, false, flags);
2235 }
2236
2237 /* Switch buffer & re-trigger DMA job */
2238 if (zx29_dma_rx_trigger_dma(zup)) {
2239 printk("uart%d could not retrigger RX DMA job\n",zup->port.line);
2240 zup->imr |= UART_RXIM;
2241 UART_PUT_IMSC(&zup->port, zup->imr);
2242 }
2243#if RX_DMA_WORK
2244 //printk("add timer\n");
2245 else{
2246 // mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
2247 uart_mod_timer(zup, flags);
2248 zup->pre_pending = 0;
2249 zup->work_state = true;
2250 }
2251#endif
2252
2253}
2254#endif
2255/****************************************************************************/
2256static void zx29_uart_rx_dma_chars(struct zx29_uart_port *zup, unsigned long *flags)
2257{
2258
2259 struct tty_struct *tty = zup->port.state->port.tty;
2260 //zx29_uart_fifo_to_tty(zup);
2261// spin_unlock(&zup->port.lock);
2262 if (zx29_dma_rx_available(zup)) {
2263 if (zx29_dma_rx_trigger_dma(zup)) {
2264 printk("rx_dma_chars RXDMA start fail\n");
2265 zup->imr |= UART_RXIM | UART_RTIM;
2266 UART_PUT_IMSC(&zup->port,zup->imr);
2267 }
2268#if RX_DMA_WORK
2269//printk("add timer\n");
2270 else{
2271 //mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
2272 uart_mod_timer(zup, flags);
2273 zup->pre_pending = 0;
2274 zup->work_state = true;
2275 }
2276#endif
2277 }
2278
2279 //tty_flip_buffer_push(tty);
2280 //spin_lock(&zup->port.lock);
2281}
2282
2283
2284/****************************************************************************/
2285static void zx29_uart_rx_timeout_chars(struct zx29_uart_port *zup, unsigned long *flags)
2286{
2287 int rt_cnt = 0;
2288// unsigned long flags;
2289
2290 int fr = UART_GET_FR(&zup->port);
2291 //printk("rx_timeout_chars\n");
2292
2293 rt_cnt = zx29_uart_fifo_to_tty(zup);
2294 if(rt_cnt){
2295 if(g_console_open_flag == 1 || zup->port.line != DEBUG_CONSOLE){
2296 spin_unlock(&zup->port.lock);
2297 tty_flip_buffer_push(&zup->port.state->port);
2298 spin_lock(&zup->port.lock);
2299 }
2300 }
2301}
2302
2303static void zx29_uart_rt_dma(struct zx29_uart_port *zup, unsigned long *flags)
2304{
2305 struct zx29_dmarx_data *dmarx = &zup->dmarx;
2306 struct dma_chan *rxchan = dmarx->chan;
2307 struct zx29_sgbuf *sgbuf = zup->curr_sg;
2308 size_t pending;
2309 struct dma_tx_state state;
2310 enum dma_status dmastat;
2311
2312 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
2313 uint32_t ris_status = UART_GET_RIS(&zup->port);
2314
2315 //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
2316 pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2317 //printk("---zx29_uart_rt_dma, pending:%d, residue:%d\n", pending, state.residue);
2318 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
2319 if(ris_status & UART_OEIS){
2320 zup->port.icount.overrun++;
2321 // if(!uart_console(&zup->port))
2322 //BUG_ON(1);
2323 }
2324 if(ris_status & UART_BEIS)
2325 zup->port.icount.brk++;
2326 if(ris_status & UART_PEIS)
2327 zup->port.icount.parity++;
2328 if(ris_status & UART_FEIS)
2329 zup->port.icount.frame++;
2330
2331 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
2332 }
2333
2334 if(zx29_dma_rx_running(zup)){
2335 /*
2336 * Pause the transfer so we can trust the current counter,
2337 * do this before we pause the block, else we may
2338 * overflow the FIFO.
2339 */
2340 zup->dmacr &= ~UART_RXDMAE;
2341 UART_PUT_DMACR(&zup->port,zup->dmacr);
2342 zx29_dma_stop(rx_id);
2343 //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
2344 //printk( "uart%d unable to pause DMA transfer\n", zup->port.line);
2345 //dmastat = rxchan->device->device_tx_status(rxchan,
2346 // dmarx->cookie, &state);
2347 // dmastat = zx29_dma_get_status();//Normally,this value is insignificance.
2348
2349 //zx29_dma_force_stop(rx_id);
2350 //dmaengine_terminate_all(rxchan);
2351
2352 /* Disable RX DMA - incoming data will wait in the FIFO */
2353 zup->dmarx.running = false;
2354 zup->dmarx.used = false;
2355 zup->curr_sg = zup->sg2tty = NULL;
2356 zup->sg2tty_len = 0;
2357 zup->imr |= (UART_RTIM|UART_RXIM);
2358 UART_PUT_IMSC(&zup->port, zup->imr);
2359 pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);//state.residue;
2360
2361 //printk("---zx29_uart_rt_dma, after stop pending:%d, residue:%d\n", pending, state.residue);
2362 BUG_ON(pending > ZX29_DMA_BUFFER_SIZE);
2363 /* Then we terminate the transfer - we now know our residue */
2364 //dmaengine_terminate_all(rxchan);
2365
2366 dmarx->use_buf_b = !dmarx->use_buf_b;
2367 wmb();
2368 /*
2369 * This will take the chars we have so far and insert
2370 * into the framework.
2371 */
2372 test_uart_static(zup->port.line, NULL, 0, 5);
2373 zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, flags);
2374 }
2375
2376#if 0
2377//printk("rt dma\n");
2378 /* Switch buffer & re-trigger DMA job */
2379 if (zx29_dma_rx_trigger_dma(zup)) {
2380 printk("zx29_dma_rx_trigger_dma fail,uart:%d\n", zup->port.line);
2381 zup->imr |= UART_RXIM;
2382 UART_PUT_IMSC(&zup->port, zup->imr);
2383 }
2384#if RX_DMA_WORK
2385 //printk("add timer\n");
2386 else{
2387 //mod_timer(&(zup->rx_dma_timer), jiffies + msecs_to_jiffies(RX_DMA_TIMEOUT));
2388 uart_mod_timer(zup, flags);
2389 zup->pre_pending = 0;
2390 zup->work_state = true;
2391 zup->dmarx.used = true;
2392 }
2393#endif
2394
2395#endif
2396
2397}
2398char g_fifo_residue_buf[5][4];
2399char g_fifo_residue_all[5][20];
2400unsigned char g_fifo_cnt[5];
2401static void zx29_uart_rx_dma_timeout(struct timer_list *t)
2402{
2403 struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_timer);
2404
2405 struct zx29_dmarx_data *dmarx = &zup->dmarx;
2406 static bool dma_timeout_flag = false;
2407 size_t pending, tmp_len;
2408 uint32_t ris_status = 0;
2409 int cancel_timer = 0;
2410 int sg_idx = (dmarx->use_buf_b ? 1 : 0);
2411
2412 unsigned long flags;
2413 struct zx29_sgbuf *sgbuf = NULL;
2414 int uart_id = zup->port.line;
2415 if(!zx29_dma_rx_running(zup))
2416 //printk("---uart_rx_dma_timeout enter, dma stopped\n");
2417 return;
2418 raw_spin_lock_irqsave(&zup->port.lock, flags);
2419 if(zup->port_close || (zup->curr_sg == NULL)){
2420 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2421 return;
2422 }
2423 //rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
2424 if(zup->sg2tty) {//dma complete now, later check again
2425 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2426 test_uart_static(zup->port.line, NULL, 0, 14);
2427 mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
2428 return;
2429 }
2430 sgbuf = zup->curr_sg;
2431 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
2432 pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2433 //pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2434 //printk("---uart_rx_dma_timeout enter,sg.length:%d, pending:%d, state.residue:%d\n", sgbuf->sg.length, pending, state.residue);
2435 if(pending == zup->pre_pending){
2436 int fr = UART_GET_FR(&zup->port);
2437 //if RXBUSY,means data come again
2438
2439 if((fr & UART_FR_RXBUSY)){
2440
2441 uart_mod_timer(zup, &flags);
2442 test_uart_static(zup->port.line, NULL, 0, 12);
2443 goto deal_end;
2444
2445 }
2446
2447 ris_status = UART_GET_RIS(&zup->port);
2448
2449 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
2450 if(ris_status & UART_OEIS){
2451 zup->port.icount.overrun++;
2452 g_uart_overrun[uart_id] = 1;
2453 test_uart_static(zup->port.line, NULL, 0, 19);
2454 //if(!uart_console(&zup->port))
2455 // BUG_ON(1);
2456 }
2457 if(ris_status & UART_BEIS)
2458 zup->port.icount.brk++;
2459 if(ris_status & UART_PEIS)
2460 zup->port.icount.parity++;
2461 if(ris_status & UART_FEIS)
2462 zup->port.icount.frame++;
2463
2464 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
2465 }
2466
2467 zup->dmacr &= ~UART_RXDMAE;
2468 UART_PUT_DMACR(&zup->port,zup->dmacr);
2469 zx29_dma_stop(rx_id);
2470 zup->dmarx.running = false;
2471 zup->dmarx.used = false;
2472 tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2473 if(tmp_len != pending){
2474 pending = tmp_len;
2475 }
2476 dmarx->use_buf_b = !dmarx->use_buf_b;
2477 wmb();
2478 if(zup->uart_power_mode){
2479 int i;
2480 for(i= 0;i < 3;i++){
2481 fr = UART_GET_FR(&zup->port);
2482 if((fr & UART_FR_RXFE) == 0){
2483 g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
2484 g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
2485 if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
2486 }
2487 else
2488 break;
2489 }
2490 if(i){
2491 g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
2492 if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
2493 }
2494
2495 //zup->sg2tty = sgbuf;
2496 //when app ctrl sleep ,always start dma receive
2497 if(zup->sleep_state == 0){
2498 //now start dma again
2499 if (zx29_dma_rx_trigger_dma(zup)) {
2500 printk("rx_dma_chars RXDMA start fail\n");
2501 zup->imr |= UART_RXIM;
2502 UART_PUT_IMSC(&zup->port,zup->imr);
2503 }else{
2504 uart_mod_timer(zup, &flags);
2505 zup->pre_pending = 0;
2506 zup->dmarx.used = true;
2507 zup->work_state = true;
2508 }
2509 }
2510 if(pending || (i > 0)){
2511 test_uart_static(zup->port.line, NULL, 0, 13);
2512 zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
2513 }
2514
2515 }else{
2516 //for normal mode, dma start only on rx busy after timeout came
2517 if(pending || (( fr & UART_FR_RXFE) == 0)){
2518 test_uart_static(zup->port.line, NULL, 0, 13);
2519 zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
2520 }
2521 zup->imr |= (UART_RTIM|UART_RXIM);
2522 UART_PUT_IMSC(&zup->port, zup->imr);
2523 zup->pre_pending = 0;
2524 zup->work_state = false;
2525 if((UART_GET_RIS(&zup->port) & (UART_RXIS | UART_RTIS)) ||
2526 (UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
2527 zup->imr &= ~(UART_RXIM);
2528 UART_PUT_IMSC(&zup->port, zup->imr);
2529
2530 if (zx29_dma_rx_trigger_dma(zup)) {
2531 printk("rx_dma_chars RXDMA start fail\n");
2532 zup->imr |= (UART_RTIM|UART_RXIM);
2533 UART_PUT_IMSC(&zup->port,zup->imr);
2534 }else{
2535 uart_mod_timer(zup, &flags);
2536 zup->pre_pending = 0;
2537 zup->dmarx.used = true;
2538 zup->work_state = true;
2539 UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
2540 }
2541 }
2542
2543 }
2544deal_end:
2545
2546 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2547 }else{
2548 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2549 zup->pre_pending = pending;
2550 mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
2551 //uart_mod_timer(zup, &flags);
2552 }
2553
2554
2555}
2556enum hrtimer_restart zx29_uart_rx_dma_hrtimeout(struct hrtimer *t)
2557{
2558 struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
2559 struct zx29_dmarx_data *dmarx = &zup->dmarx;
2560 static bool dma_timeout_flag = false;
2561 size_t pending, tmp_len;
2562 uint32_t ris_status = 0;
2563 int cancel_timer = 0;
2564 int sg_idx = (dmarx->use_buf_b ? 1 : 0);
2565 int uart_id = zup->port.line;
2566 unsigned long flags;
2567 struct zx29_sgbuf *sgbuf = NULL;
2568 if(!zx29_dma_rx_running(zup))
2569 return HRTIMER_NORESTART;
2570 raw_spin_lock_irqsave(&zup->port.lock, flags);
2571 if(zup->port_close || (zup->curr_sg == NULL)){
2572 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2573 return HRTIMER_NORESTART;
2574 }
2575 if(zup->sg2tty) {//dma complete now, later check again
2576 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2577 test_uart_static(zup->port.line, NULL, 0, 14);
2578 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2579 return HRTIMER_RESTART;
2580 }
2581 if(zup->enter_suspend){
2582 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2583 test_uart_static(zup->port.line, NULL, 0, 15);
2584 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2585 return HRTIMER_RESTART;
2586 }
2587 sgbuf = zup->curr_sg;
2588 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
2589 pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2590 if((pending == zup->pre_pending)) {
2591 int fr = UART_GET_FR(&zup->port);
2592 if((fr & UART_FR_RXBUSY)){
2593 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2594 test_uart_static(zup->port.line, NULL, 0, 12);
2595 goto deal_end;
2596 }
2597 ris_status = UART_GET_RIS(&zup->port);
2598 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
2599 if(ris_status & UART_OEIS){
2600 zup->port.icount.overrun++;
2601 g_uart_overrun[uart_id] = 1;
2602 test_uart_static(zup->port.line, NULL, 0, 19);
2603 }
2604 if(ris_status & UART_BEIS)
2605 zup->port.icount.brk++;
2606 if(ris_status & UART_PEIS)
2607 zup->port.icount.parity++;
2608 if(ris_status & UART_FEIS)
2609 zup->port.icount.frame++;
2610 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
2611 }
2612 zup->dmacr &= ~UART_RXDMAE;
2613 UART_PUT_DMACR(&zup->port,zup->dmacr);
2614 zx29_dma_stop(rx_id);
2615 zup->dmarx.running = false;
2616 zup->dmarx.used = false;
2617 tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2618 if(tmp_len != pending){
2619 pending = tmp_len;
2620 }
2621 dmarx->use_buf_b = !dmarx->use_buf_b;
2622 wmb();
2623 if(zup->uart_power_mode){
2624 int i;
2625 for(i= 0;i < 3;i++){
2626 fr = UART_GET_FR(&zup->port);
2627 if((fr & UART_FR_RXFE) == 0){
2628 g_fifo_residue_buf[uart_id][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
2629 g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++] = g_fifo_residue_buf[uart_id][i];
2630 if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
2631 }
2632 else
2633 break;
2634 }
2635 if(i){
2636 g_fifo_residue_all[uart_id][g_fifo_cnt[uart_id]++]=i;
2637 if(g_fifo_cnt[uart_id] >= 20) g_fifo_cnt[uart_id] = 0;
2638 }
2639 if(zup->sleep_state == 0){
2640 if (zx29_dma_rx_trigger_dma(zup)) {
2641 printk("rx_dma_chars RXDMA start fail\n");
2642 zup->imr |= UART_RXIM;
2643 UART_PUT_IMSC(&zup->port,zup->imr);
2644 }else{
2645 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2646 zup->pre_pending = 0;
2647 zup->dmarx.used = true;
2648 zup->work_state = true;
2649 }
2650 }
2651 if(pending || (i > 0)){
2652 test_uart_static(zup->port.line, NULL, 0, 13);
2653 zx29_uart_deal_dma_fifo_rx_chars(zup, pending, sgbuf, &flags, g_fifo_residue_buf[uart_id],i);
2654 }
2655 }else{
2656 if(pending || (( fr & UART_FR_RXFE) == 0)){
2657 test_uart_static(zup->port.line, NULL, 0, 13);
2658 zx29_uart_dma_rx_chars(zup, pending, sgbuf, true, &flags);
2659 printk("at pending %d.\n",pending);
2660 }
2661 zup->imr |= (UART_RTIM|UART_RXIM);
2662 UART_PUT_IMSC(&zup->port, zup->imr);
2663 zup->pre_pending = 0;
2664 zup->work_state = false;
2665 if((UART_GET_RIS(&zup->port) & (UART_RXIS | UART_RTIS)) ||
2666 (UART_GET_FR(&zup->port) & UART_FR_RXBUSY)){
2667 zup->imr &= ~(UART_RXIM);
2668 UART_PUT_IMSC(&zup->port, zup->imr);
2669 if (zx29_dma_rx_trigger_dma(zup)) {
2670 printk("rx_dma_chars RXDMA start fail\n");
2671 zup->imr |= (UART_RTIM|UART_RXIM);
2672 UART_PUT_IMSC(&zup->port,zup->imr);
2673 }else{
2674 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2675 zup->pre_pending = 0;
2676 zup->dmarx.used = true;
2677 zup->work_state = true;
2678 UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
2679 }
2680 }
2681 }
2682deal_end:
2683 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2684 return HRTIMER_RESTART;
2685 }else{
2686 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2687 zup->pre_pending = pending;
2688 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2689 test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
2690 return HRTIMER_RESTART;
2691 }
2692}
2693enum hrtimer_restart zx29_uart_rx_dma_hrtimeout_cyclic(struct hrtimer *t)
2694{
2695 struct zx29_uart_port *zup = from_timer(zup, t, rx_dma_hrtimer);
2696 struct zx29_dmarx_data *dmarx = &zup->dmarx;
2697 struct dma_chan *rxchan = dmarx->chan;
2698 size_t pending, tmp_len;
2699 uint32_t ris_status = 0;
2700 unsigned long flags;
2701 struct zx29_sgbuf *sgbuf = NULL;
2702 int uart_id = zup->port.line;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2703
2704
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2705 if(!zx29_dma_rx_running(zup))
2706 return HRTIMER_NORESTART;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2707 raw_spin_lock_irqsave(&zup->port.lock, flags);
2708
2709 if((uart_dma_cycle[zup->port.line].cnt_callback > 0) || (uart_dma_cycle[zup->port.line+3].cnt_callback > 0)){
2710 test_uart_static(zup->port.line, NULL, uart_dma_cycle[zup->port.line].used, 46);
2711 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2712 return HRTIMER_NORESTART;
2713 }
2714
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2715 if(!uart_dma_cycle[zup->port.line].used)
2716 uart_id = uart_id + 3;
2717
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2718 sgbuf = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_th];
2719 if(zup->port_close || (sgbuf == NULL)){
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2720 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2721 return HRTIMER_NORESTART;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2722 }
2723 if(zup->sema_cyclic.count > 0){
2724 printk("uart has th not deal.\n");
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2725 //test_uart_static(zup->port.line, NULL, uart_id, 11);
2726 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
2727 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2728 return HRTIMER_RESTART;
2729 }
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2730
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2731 if((zup->sg2tty)){//dma not complete now, later check again
2732 printk("dmath_cyclic not end.\n");
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2733 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2734 test_uart_static(zup->port.line, NULL, 0, 14);
2735 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2736 return HRTIMER_RESTART;
2737 }
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2738 if(zup->enter_suspend || uart_dma_cycle[uart_id].enter_throttle){
2739 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2740 test_uart_static(zup->port.line, NULL, 0, 15);
2741 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2742 return HRTIMER_RESTART;
2743 }
2744 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
2745 pending = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2746 if(((pending == zup->pre_pending) && pending) || uart_dma_cycle[uart_id].from_resume
2747 || uart_dma_cycle[uart_id].from_unthrottle){
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2748 uart_dma_cycle[uart_id].from_resume = 0;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2749 uart_dma_cycle[uart_id].from_unthrottle = false;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2750#if 0
2751 if(uart_dma_cycle[uart_id].flg_enter_th == 0)
2752 uart_dma_cycle[uart_id].flg_enter_to = 4;
2753 else
2754 uart_dma_cycle[uart_id].flg_enter_to = uart_dma_cycle[uart_id].flg_enter_th - 1;
2755 struct zx29_sgbuf *sgbuf_tmp = NULL;
2756 sgbuf_tmp = &uart_dma_cycle[uart_id].sgbuf[uart_dma_cycle[uart_id].flg_enter_to];
2757 test_uart_static(zup->port.line, NULL, 0, 61);
2758 if (sgbuf->sg.dma_address != (zx29_dma_cur_dst(rx_id)&0xfffff000)){
2759 if(sgbuf_tmp->sg.dma_address != ((zx29_dma_cur_dst(rx_id)&0xfffff000)-0x1000)){
2760 printk("uart lose dma isr enter self resume.\n");
2761 up(&zup->sema_cyclic);
2762 spin_unlock_irqrestore(&zup->port.lock, flags);
2763 return;
2764 }
2765 }
2766 #endif
2767 int fr = UART_GET_FR(&zup->port);
2768 if((fr & UART_FR_RXBUSY)){
2769 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2770 test_uart_static(zup->port.line, NULL, 0, 12);
2771 goto deal_end;
2772 }
2773 ris_status = UART_GET_RIS(&zup->port);
2774 if(ris_status & (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS)){
2775 if(ris_status & UART_OEIS){
2776 zup->port.icount.overrun++;
2777 uart_dma_cycle[uart_id].flg_overrun = 1;
2778 }
2779 if(ris_status & UART_BEIS)
2780 zup->port.icount.brk++;
2781 if(ris_status & UART_PEIS)
2782 zup->port.icount.parity++;
2783 if(ris_status & UART_FEIS)
2784 zup->port.icount.frame++;
2785 UART_PUT_ICR(&zup->port, (UART_OEIS | UART_BEIS | UART_PEIS | UART_FEIS));
2786 printk("error in uart%d: fe %u ,be %u pe %u.\n",zup->port.line,zup->port.icount.frame,
2787 zup->port.icount.brk,zup->port.icount.parity);
2788 }
2789 zup->dmacr &= ~UART_RXDMAE;
2790 UART_PUT_DMACR(&zup->port,zup->dmacr);
2791 dmaengine_terminate_all(rxchan);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2792 zup->dmarx.running = false;
2793 zup->dmarx.used = false;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2794 tmp_len = sgbuf->sg.length - zx29_dma_get_transfer_num(rx_id);
2795 if(tmp_len != pending){
2796 pending = tmp_len;
2797 //test_uart_static(zup->port.line, NULL, tmp_len, 48);
2798 }
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2799 wmb();
2800 int i = 0;
2801 for(i= 0;i < 3;i++){
2802 fr = UART_GET_FR(&zup->port);
2803 if((fr & UART_FR_RXFE) == 0){
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2804 g_fifo_residue_buf[zup->port.line][i] = UART_GET_CHAR(&zup->port) | UART_DUMMY_DR_RX;
2805 g_fifo_residue_all[zup->port.line][g_fifo_cnt[zup->port.line]++] = g_fifo_residue_buf[zup->port.line][i];
2806 if(g_fifo_cnt[zup->port.line] >= 20) g_fifo_cnt[zup->port.line] = 0;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2807 }
2808 else
2809 break;
2810 }
2811 if(i){
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2812 g_fifo_residue_all[zup->port.line][g_fifo_cnt[zup->port.line]++]=i;
2813 if(g_fifo_cnt[zup->port.line] >= 20) g_fifo_cnt[zup->port.line] = 0;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2814 }
2815 if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
2816 printk("rx_dma_chars RXDMA start fail\n");
2817 zup->imr |= UART_RXIM;
2818 UART_PUT_IMSC(&zup->port,zup->imr);
2819 }else{
2820 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2821 test_uart_static(zup->port.line, NULL, (pending+i), 49);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2822 zup->pre_pending = 0;
2823 zup->dmarx.used = true;
2824 zup->work_state = true;
2825 }
2826 if((pending && (pending != 4096)) || (i > 0)){
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2827 zx29_uart_deal_dma_fifo_rx_chars_cyclic(zup, pending, sgbuf, &flags, g_fifo_residue_buf[zup->port.line],i);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2828 }
2829 uart_dma_cycle[uart_id].cnt_th = 0;
2830 uart_dma_cycle[uart_id].cnt_callback=0;
2831deal_end:
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2832 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2833 return HRTIMER_RESTART;
2834 }else{
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]2835 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]2836 zup->pre_pending = pending;
2837 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
2838 test_uart_static(zup->port.line, NULL, zup->pre_pending, 22);
2839 return HRTIMER_RESTART;
2840 }
2841}
2842#endif
2843
2844
2845static void zx29_uart_modem_status(struct zx29_uart_port *zup)
2846{
2847 unsigned int status, delta;
2848
2849 status = UART_GET_FR(&zup->port)& UART_FR_MODEM_ANY;
2850
2851 delta = status ^ zup->old_status;
2852 zup->old_status = status;
2853
2854 if (!delta)
2855 return;
2856
2857 if (delta & UART_FR_DCD)
2858 uart_handle_dcd_change(&zup->port, status & UART_FR_DCD);
2859
2860 if (delta & UART_FR_DSR)
2861 zup->port.icount.dsr++;
2862
2863 if (delta & UART_FR_CTS)
2864 uart_handle_cts_change(&zup->port, status & UART_FR_CTS);
2865
2866 wake_up_interruptible(&zup->port.state->port.delta_msr_wait);
2867}
2868
2869/****************************************************************************/
2870static irqreturn_t zx29_uart_interrupt(int irq, void *dev_id)
2871{
2872 struct uart_port *port = (struct uart_port *)dev_id;
2873 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
2874 unsigned long flags;
2875 unsigned int status,ris, pass_counter = 256;
2876 int handled = 0;
2877 int uart_id = zup->port.line;
2878 spin_lock_irqsave(&zup->port.lock, flags);
2879 status = UART_GET_MIS(port) & zup->imr;
2880 ris = UART_GET_RIS(port);
2881 if (status) {
2882 do {
2883 UART_PUT_ICR(port,(status & ~(UART_TXIS|UART_RTIS|UART_RXIS)));
2884 if(uart_console(&zup->port)){
2885 if (status & (UART_RTIS|UART_RXIS))
2886 zx29_uart_rx_chars(zup);
2887 }else{
2888#ifdef CONFIG_CPU_IDLE
2889 zup->rxd_int_depth = 0;
2890#endif
2891 if (status & (UART_RXIS)){
2892#if CONFIG_SERIAL_ZX29_DMA
2893 if(ris & UART_OEIS){
2894 zup->port.icount.overrun++;
2895 g_uart_overrun[uart_id] = 8;
2896 test_uart_static(zup->port.line, NULL, 0, 21);
2897 //if(!uart_console(&zup->port))
2898 // BUG_ON(1);
2899 }
2900 if (zx29_dma_rx_used(zup)){
2901 UART_PUT_ICR(port,UART_RXIS);
2902 if(!(zup->imr & UART_RTIM)){
2903 zup->imr |= UART_RTIM;
2904 UART_PUT_IMSC(port,zup->imr);
2905 }
2906
2907 test_uart_static(port->line, NULL, 0, 8);
2908 uart_mod_timer(zup, &flags);
2909
2910 }else{
2911 test_uart_static(port->line, NULL, 0, 1);
2912
2913 zup->imr &= ~UART_RXIM;
2914 UART_PUT_IMSC(&zup->port,zup->imr);
2915 zx29_uart_rx_dma_chars(zup, &flags);
2916
2917 zup->dmarx.used = true;
2918 //when RX&RT comes both, we trigger dma and add timer,so clear RT,waiting the timer
2919 if(status & (UART_RTIS))
2920 status &= ~UART_RTIS;
2921 }
2922#else
2923 zx29_uart_rx_chars(zup);
2924#endif
2925 }
2926
2927 if (status & (UART_RTIS)){
2928#if CONFIG_SERIAL_ZX29_DMA
2929 if(!zx29_dma_rx_running(zup)){
2930 test_uart_static(port->line, NULL, 0, 2);
2931 zx29_uart_rx_timeout_chars(zup, &flags);
2932 }else{
2933 UART_PUT_ICR(port, UART_RTIS);
2934 test_uart_static(port->line, NULL, 0, 4);
2935 zx29_uart_rt_dma(zup, &flags);
2936 }
2937#else
2938 zx29_uart_rx_chars(zup);
2939#endif
2940 }
2941 }
2942
2943 if (status & (UART_DSRMIS|UART_DCDMIS|UART_CTSMIS|UART_RIMIS))
2944 zx29_uart_modem_status(zup);
2945
2946 if (status & UART_TXIS)
2947 zx29_uart_tx_chars(zup);
2948
2949 if (pass_counter-- == 0)
2950 break;
2951
2952 status = UART_GET_MIS(port);
2953 } while (status != 0);
2954 handled = IRQ_HANDLED;
2955 }
2956 spin_unlock_irqrestore(&zup->port.lock, flags);
2957
2958 return IRQ_RETVAL(handled);
2959}
2960
2961#if CONFIG_SERIAL_ZX29_DMA
2962extern bool zx29_dma_filter_fn(struct dma_chan *chan, void *param);
2963static void uart_dma_init(struct zx29_uart_port *zup)
2964{
2965 int i=0;
2966 struct dma_chan *chan = NULL;
2967
2968 atomic_set(&zup->dmarx.count, 1);
2969 atomic_set(&zup->dmatx.count, 1);
2970#if 1
2971 if(zup->port.line == UART0)
2972 {
2973 zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART0_BASE +zx29_UART_DR);
2974 }
2975 else if(zup->port.line == UART1)
2976 {
2977 zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART1_BASE+zx29_UART_DR);
2978 }
2979 else if(zup->port.line == UART2)
2980 {
2981 zup->dmatx.tx_def.dest_addr = (unsigned int)(ZX_UART2_BASE+zx29_UART_DR);
2982 }
2983
2984 zup->dmatx.tx_def.dma_control.tran_mode = TRAN_MEM_TO_PERI;
2985 zup->dmatx.tx_def.dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
2986 zup->dmatx.tx_def.dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
2987 zup->dmatx.tx_def.dma_control.src_burst_len = DMA_BURST_LEN_4;
2988 zup->dmatx.tx_def.dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
2989 zup->dmatx.tx_def.dma_control.dest_burst_len = DMA_BURST_LEN_4;
2990
2991 dma_cap_mask_t mask;
2992 dma_cap_zero(mask);
2993 dma_cap_set(DMA_SLAVE, mask);
2994
2995 if(zup->port.line == UART0)
2996 {
2997 chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_TX);
2998 }
2999 else if(zup->port.line == UART1)
3000 {
3001 chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_TX);
3002 }
3003 else if(zup->port.line == UART2)
3004 {
3005 chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_TX);
3006 }
3007 if(!chan){
3008 printk("UART%d DMA TX channel request fail.\n", zup->port.line);
3009 return;
3010 }
3011 zup->dmatx.chan = chan;
3012
3013
3014
3015 for(i=0;i<UART_DMA_RX_MAX_COUNT;i++)
3016 {
3017 if(zup->port.line == UART0)
3018 {
3019 zup->dmarx.rx_def[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
3020 }
3021 else if(zup->port.line == UART1)
3022 {
3023 zup->dmarx.rx_def[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
3024 }
3025 else if(zup->port.line == UART2)
3026 {
3027 zup->dmarx.rx_def[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
3028 }
3029
3030 zup->dmarx.rx_def[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
3031 zup->dmarx.rx_def[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
3032 zup->dmarx.rx_def[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
3033 zup->dmarx.rx_def[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
3034 zup->dmarx.rx_def[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
3035 zup->dmarx.rx_def[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
3036 }
3037
3038 zup->dmarx.rx_index = 0;
3039 chan = NULL;
3040
3041 dma_cap_zero(mask);
3042 dma_cap_set(DMA_SLAVE, mask);
3043
3044 if(zup->port.line == UART0)
3045 {
3046 chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART0_RX);
3047 }
3048 else if(zup->port.line == UART1)
3049 {
3050 chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART1_RX);
3051 }
3052 else if(zup->port.line == UART2)
3053 {
3054 chan = dma_request_channel(mask, zx29_dma_filter_fn, (void*)DMA_CH_UART2_RX);
3055 }
3056 if(!chan){
3057 printk("UART%d DMA RX channel request fail.\n", zup->port.line);
3058 return;
3059 }
3060 zup->dmarx.chan = chan;
3061#endif
3062}
3063
3064static int uart_dma_cycle_init(struct zx29_uart_port *zup)
3065{
3066 int ret;
3067 int uart_id = zup->port.line;
3068 uart_dma_cycle[uart_id].id = zup->port.line;
3069 int i,j;
3070 for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
3071 ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
3072 if(ret){
3073 printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", zup->port.line, ret);
3074 for(j=0;j<i;j++){
3075 zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[j],DMA_FROM_DEVICE);
3076 }
3077 return -1;
3078 }
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3079
3080 ret = zx29_sgbuf_init(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[i],DMA_FROM_DEVICE);
3081 if(ret){
3082 printk( "init uart_dma_cycle sgbuf failed,uart: %d,ret:%d\n", (zup->port.line+3), ret);
3083 for(j=0;j<i;j++){
3084 zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[j],DMA_FROM_DEVICE);
3085 }
3086 return -1;
3087 }
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3088 }
3089 for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3090 if(zup->port.line == UART0){
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3091 uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3092 uart_dma_cycle[uart_id].used = false;
3093 uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART0_BASE+zx29_UART_DR;
3094 uart_dma_cycle[uart_id+3].used = false;
3095 }
3096 else if(zup->port.line == UART1){
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3097 uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3098 uart_dma_cycle[uart_id].used = false;
3099 uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART1_BASE+zx29_UART_DR;
3100 uart_dma_cycle[uart_id+3].used = false;
3101 }
3102 else if(zup->port.line == UART2){
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3103 uart_dma_cycle[uart_id].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3104 uart_dma_cycle[uart_id].used = false;
3105 uart_dma_cycle[uart_id+3].rxdef[i].src_addr = ZX_UART2_BASE+zx29_UART_DR;
3106 uart_dma_cycle[uart_id+3].used = false;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3107 }
3108 uart_dma_cycle[uart_id].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id].sgbuf[i].dma_addr);
3109 uart_dma_cycle[uart_id].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
3110 uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
3111 uart_dma_cycle[uart_id].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
3112 uart_dma_cycle[uart_id].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
3113 uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
3114 uart_dma_cycle[uart_id].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
3115 uart_dma_cycle[uart_id].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3116 uart_dma_cycle[uart_id].rxdef[i].link_addr = 1;
3117
3118 uart_dma_cycle[uart_id+3].rxdef[i].dest_addr = (unsigned int)(uart_dma_cycle[uart_id+3].sgbuf[i].dma_addr);
3119 uart_dma_cycle[uart_id+3].rxdef[i].dma_control.tran_mode = TRAN_PERI_TO_MEM;
3120 uart_dma_cycle[uart_id+3].rxdef[i].dma_control.src_burst_len = DMA_BURST_LEN_4;
3121 uart_dma_cycle[uart_id+3].rxdef[i].count = ZX29_DMA_BUFFER_SIZE;
3122 uart_dma_cycle[uart_id+3].rxdef[i].dma_control.src_burst_size = DMA_BURST_SIZE_8BIT;
3123 uart_dma_cycle[uart_id+3].rxdef[i].dma_control.dest_burst_size = DMA_BURST_SIZE_8BIT;
3124 uart_dma_cycle[uart_id+3].rxdef[i].dma_control.dest_burst_len = DMA_BURST_LEN_4;
3125 uart_dma_cycle[uart_id+3].rxdef[i].dma_control.irq_mode = DMA_ALL_IRQ_ENABLE;
3126 uart_dma_cycle[uart_id+3].rxdef[i].link_addr = 1;
3127
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3128 }
3129 return 0;
3130}
3131static void uart_dma_cycle_deinit(struct zx29_uart_port *zup)
3132{
3133 int i;
3134 int uart_id = zup->port.line;
3135 for(i=0;i<UART_DMA_CYCLE_RX_CONFIG_COUNT;i++){
3136 zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id].sgbuf[i],DMA_FROM_DEVICE);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3137 zx29_sgbuf_free(zup->dmarx.chan, &uart_dma_cycle[uart_id+3].sgbuf[i],DMA_FROM_DEVICE);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3138 }
3139 memset(uart_dma_cycle[uart_id].rxdef, 0, sizeof(uart_dma_cycle[uart_id].rxdef));
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3140 memset(uart_dma_cycle[uart_id+3].rxdef, 0, sizeof(uart_dma_cycle[uart_id+3].rxdef));
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3141}
3142static void uart_dma_startup(struct zx29_uart_port *zup)
3143{
3144 int ret = 0;
3145 if (!zup->dmatx.chan)
3146 {
3147 printk("tx_chan is error[%s][%d]\n",__func__,__LINE__);
3148 return;
3149 }
3150
3151 zup->dmatx.buf = kmalloc(ZX29_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
3152 if (!zup->dmatx.buf) {
3153 printk("tx_buf is error[%s][%d]\n",__func__,__LINE__);
3154 return;
3155 }
3156
3157 sg_init_one(&zup->dmatx.sg, zup->dmatx.buf, ZX29_DMA_BUFFER_SIZE);
3158
3159 /* The DMA buffer is now the FIFO the TTY subsystem can use */
3160 zup->port.fifosize = 16;//ZX29_DMA_BUFFER_SIZE;
3161 zup->using_tx_dma = true;
3162
3163 if(!zup->uart_power_mode)
3164 {
3165 if (!zup->dmarx.chan)
3166 {
3167 printk(KERN_INFO "[%s][%d]uart_%d rx_chan is error\n",__func__,__LINE__, zup->port.line);
3168 goto skip_rx;
3169 }
3170
3171 /* Allocate and map DMA RX buffers */
3172 ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
3173 DMA_FROM_DEVICE);
3174 if (ret) {
3175 printk(KERN_INFO "[%s][%d] uart_%d rx_buf_a is error\n",__func__,__LINE__, zup->port.line);
3176 //dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
3177 // "RX buffer A", ret);
3178 goto skip_rx;
3179 }
3180
3181 ret = zx29_sgbuf_init(zup->dmarx.chan, &zup->dmarx.sgbuf_b,
3182 DMA_FROM_DEVICE);
3183 if (ret) {
3184 printk( "failed to init DMA uart: %d RX buffer B ,ret:%d\n", zup->port.line, ret);
3185 zx29_sgbuf_free(zup->dmarx.chan, &zup->dmarx.sgbuf_a,
3186 DMA_FROM_DEVICE);
3187 goto skip_rx;
3188 }
3189
3190 zup->using_rx_dma = true;
3191 zup->sg2tty = NULL;
3192 zup->sg2tty_len = 0;
3193 zup->curr_sg = NULL;
3194#if RX_DMA_WORK
3195 timer_setup(&(zup->rx_dma_timer), zx29_uart_rx_dma_timeout, 0);
3196 hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3197 zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout;
3198 g_hr_interval = ktime_set(0, 1500000);
3199 zup->dmarx.running = false;
3200 zup->dmarx.used = false;
3201 zup->dmarx.use_buf_b = false;
3202 zup->dmarx.rx_index = 0;
3203
3204 zup->pre_pending = 0;
3205 zup->work_state = false;
3206
3207 zup->dma_compl_th = kthread_run(dma_complete_thread, zup, "uart_dma_compl");
3208 BUG_ON(IS_ERR(zup->dma_compl_th));
3209#endif
3210
3211skip_rx:
3212
3213 /* Turn on DMA error (RX/TX will be enabled on demand) */
3214 printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
3215 zup->dmacr &= ~UART_DMAONERR;
3216 //zup->dmacr |= UART_DMAONERR;
3217 UART_PUT_DMACR(&zup->port, zup->dmacr);
3218 if(zup->uart_power_mode){
3219 if (zup->using_rx_dma) {
3220 //printk(KERN_INFO "[%s][%d]\n",__func__,__LINE__);
3221 if (zx29_dma_rx_trigger_dma(zup)){
3222 dev_dbg(zup->port.dev, "could not trigger initial "
3223 "RX DMA job, fall back to interrupt mode\n");
3224 }else{
3225 mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
3226 zup->pre_pending = 0;
3227 zup->work_state = true;
3228 }
3229 }
3230 }
3231 }
3232 else if(zup->uart_power_mode == 1)
3233 {
3234 ret = uart_dma_cycle_init(zup);
3235 if(ret){
3236 printk("uart%d dma cycle init failed,ret %d.\n",zup->port.line,ret);
3237 return;
3238 }
3239 zup->using_rx_dma = true;
3240 zup->sg2tty = NULL;
3241 zup->sg2tty_len = 0;
3242 zup->curr_sg = NULL;
3243#if RX_DMA_WORK
3244 hrtimer_init(&zup->rx_dma_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3245 zup->rx_dma_hrtimer.function = zx29_uart_rx_dma_hrtimeout_cyclic;
3246 g_hr_interval = ktime_set(0, 1500000);
3247 zup->dmarx.running = false;
3248 zup->dmarx.used = false;
3249 zup->dmarx.use_buf_b = false;
3250 zup->dmarx.rx_index = 0;
3251 zup->pre_pending = 0;
3252 zup->work_state = false;
3253 sema_init(&zup->sema_cyclic, 0);
3254 zup->dma_compl_th = kthread_run(dma_complete_thread_use_dma_cyclic, zup, "uart_dma_th_cyc");
3255 BUG_ON(IS_ERR(zup->dma_compl_th));
3256#endif
3257 printk("uart_dma_startup, port:%d, ret:%d\n", zup->port.line,ret );
3258 zup->dmacr &= ~UART_DMAONERR;
3259 UART_PUT_DMACR(&zup->port, zup->dmacr);
3260 if(zup->uart_power_mode){
3261 if (zup->using_rx_dma) {
3262 if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)){
3263 dev_dbg(zup->port.dev, "could not trigger initial "
3264 "RX DMA job, fall back to interrupt mode\n");
3265 }else{
3266 hrtimer_start(&zup->rx_dma_hrtimer, g_hr_interval, HRTIMER_MODE_REL);
3267 //mod_timer(&(zup->rx_dma_timer), jiffies + RX_DMA_TIMEOUT);
3268 zup->pre_pending = 0;
3269 zup->work_state = true;
3270 }
3271 }
3272 }
3273 }else
3274 printk("uart%d power mode set error,dma dont startup.\n",zup->port.line);
3275}
3276
3277
3278#endif
3279
3280static irqreturn_t zx29_uart_rxd_irq(int irq, void *dev_id)
3281{
3282 struct zx29_uart_port *zup = (struct zx29_uart_port *)dev_id;
3283
3284 rxd_wake_cnt++;
3285 zup->rxd_wakeup = true;
3286 tasklet_schedule(&zup->write_wakeup);
3287 zup->rxd_int_depth = 0;
3288 return IRQ_HANDLED;//IRQ_RETVAL(retval);
3289}
3290
3291/****************************************************************************/
3292static int zx29_uart_startup(struct uart_port *port)
3293{
3294 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
3295 unsigned long flags = 0;
3296 unsigned long control = 0;
3297 int retval = 0;
3298 struct platform_device *pdev=port->private_data;
3299// struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
3300 int i = 0,j = 0,iflag = 0;
3301 struct tty_struct *tty = port->state->port.tty;
3302 unsigned int ibrd, fbrd,lcr_h, old_cr;
3303 int ret=0;
3304 printk("-----zx29_uart_startup, port:%d\n", port->line);
3305 #if 0//def CONFIG_ARCH_ZX297520V3_WATCH
3306
3307 if(port->line == 0)
3308 {
3309 gpio_free(pdata->uart_txd.gpionum);
3310 gpio_free(pdata->uart_rxd.gpionum);
3311 //printk("gpio_free err err!\n");
3312 }
3313
3314 wmb();
3315
3316 #endif
3317 if(DEBUG_CONSOLE != pdev->id){
3318 char temp_buf[TASK_COMM_LEN]= {0};
3319 int th_ctrl = 0;
3320 if((strlen(get_task_comm(temp_buf,get_current())) > 0) && (strcmp(get_task_comm(temp_buf,get_current()),"at_ctl") != 0))
3321 th_ctrl = 1;
3322
3323 //app ctrl or kernel ctrl set this
3324 int kernel_ctrl = xp2xp_enable_4line();
3325 zup->uart_power_mode = (kernel_ctrl | zup->app_ctrl | th_ctrl);
3326 printk("zx29_uart%d open task is %s,power_mode is %d.\n",pdev->id, get_task_comm(temp_buf,get_current()),zup->uart_power_mode);
3327 if(zup->uart_power_mode){
3328 //pm_stay_awake(&pdev->dev);
3329 }
3330 }
3331 //when open, clear last statistic info
3332 port->icount.brk = port->icount.buf_overrun = port->icount.frame = 0;
3333 port->icount.overrun = port->icount.parity = port->icount.rng = 0;
3334 port->icount.rx = port->icount.tx = 0;
3335 /*
3336 *enable uart clock
3337 *if uart is used for console, don't need do these, these was done before
3338 */
3339 if (DEBUG_CONSOLE != port->line) {
3340 /* config uart apb_clk */
3341 clk_prepare_enable(zup->busclk);
3342 /* enable uart work clock */
3343 clk_prepare_enable(zup->wclk);
3344 }
3345
3346 /* Clear all pending error and receive interrupts */
3347 UART_PUT_ICR(port, 0xfff);
3348
3349 /* Allocate the IRQ */
3350 retval = request_irq(port->irq, zx29_uart_interrupt, 0, "uart-zx29", zup);
3351 if (retval){
3352 printk("[UART]unable to attach zx29 UART %d "
3353 "interrupt vector=%d\n", port->line, port->irq);
3354 return retval;
3355 }
3356
3357 /* set interrupt fifo level RX:1/2 Full, TX:1/2 Full */
3358#if 0//CONFIG_SERIAL_ZX29_DMA
3359 UART_PUT_IFLS(port, UART_IFLS_RX2_8|UART_IFLS_TX6_8);
3360#else
3361 UART_PUT_IFLS(port, UART_IFLS_RX2_8|UART_IFLS_TX4_8);
3362#endif
3363
3364#if 0
3365 /* Provoke TX FIFO interrupt into asserting. */
3366 control = UART_CR_UARTEN | UART_CR_TXE | UART_CR_LBE;
3367 UART_PUT_CR(port, control);
3368 UART_PUT_FBRD(port, 0);
3369 UART_PUT_IBRD(port, 1);
3370 UART_PUT_LCRH(port, 0);
3371 UART_PUT_CHAR(port, 0);
3372 while (UART_GET_FR(port) & UART_FR_TXBUSY)
3373 barrier();
3374#endif
3375 control = UART_CR_UARTEN | UART_CR_RXE | UART_CR_TXE;
3376 //console & lp_uart don't need dma
3377 if ((DEBUG_CONSOLE != port->line) && (port->line != 4)) {
3378#if CONFIG_SERIAL_ZX29_DMA
3379 UART_PUT_DMACR(port, UART_TXDMAE | UART_RXDMAE);
3380 uart_dma_startup(zup);
3381#endif
3382 }
3383
3384 tasklet_init(&zup->write_wakeup, uart_write_wakeup_task, (unsigned long) port);
3385 if((pdev->id == 0) && (zup->irq_state == 0) && (zup->uart_power_mode == 0)){
3386 ret = request_irq(zup->rxd_irq,
3387 zx29_uart_rxd_irq,
3388 0,
3389 "uart0_rxd_wake",
3390 zup);
3391 if(ret<0){
3392 panic("request uart0 rxd wake irq fail\n");
3393 }
3394 printk("--------rxd wake up interrupt ok\n");
3395 enable_irq_wake(zup->rxd_irq);
3396 zup->irq_state = 1;
3397 zup->rxd_int_depth = 1;
3398 }
3399#if 0
3400 /*configure gpio pin to UART*/
3401 if((pdata->uart_use)/*&&(port->line == UART0 )*/)
3402 {
3403 retval=gpio_request(pdata->uart_rxd.gpionum,pdata->uart_rxd.gpioname);
3404 if(retval)
3405 BUG();
3406 retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_txd.gpioname);
3407 if(retval)
3408 BUG();
3409 /*uart rxd*/
3410 zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
3411 if(pdata->uart_rxd.gpionum == ZX29_GPIO_121 ) {
3412 //pull up gpio121
3413 *(volatile unsigned int *)0xf843c82c |= 0xf0;
3414 }
3415 /*uart txd*/
3416 zx29_gpio_config(pdata->uart_txd.gpionum, pdata->uart_txd.gpiofnc);
3417#ifdef CONFIG_ARCH_ZX297520V3
3418 if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 0)){
3419 zup->irq = platform_get_irq_byname(pdev, "zx29_uart_rxd_wakeup");
3420 printk(KERN_INFO"zx29_uart_startup,irq:%d,%s.%d\n",zup->irq,pdata->uart_cts.gpioname,zup->irq_state);
3421 if(zup->irq >= 0){
3422
3423 pcu_int_set_type(PCU_UART0_RXD_INT, IRQF_TRIGGER_FALLING);
3424 pcu_int_clear(PCU_UART0_RXD_INT);
3425 ret = request_irq(zup->irq, zx29_uart_rxd_irq,
3426 IRQF_ONESHOT , "uart_rxd_irq",
3427 zup);
3428 printk(KERN_INFO"zx29_uart_startup, retval:%d\n",ret);
3429 irq_set_irq_wake(zup->irq,1);
3430#ifdef CONFIG_CPU_IDLE
3431 zup->rxd_int_depth = rxd_wake_cnt = 0;
3432 zx_pm_register_callback(uart_0_pm_enter, uart_0_pm_exit);
3433 disable_irq_nosync(UART0_RXD_INT);
3434#endif
3435 zup->irq_state = 1;
3436 }else{
3437 printk("uart_startup, request wake irq fail:%d\n",zup->irq);
3438 }
3439 }
3440#endif
3441 if(pdata->uart_ctsrtsuse)
3442 {
3443 retval=gpio_request(pdata->uart_cts.gpionum,pdata->uart_cts.gpioname);
3444 if(retval)
3445 BUG();
3446
3447 retval=gpio_request(pdata->uart_rts.gpionum,pdata->uart_rts.gpioname);
3448 if(retval)
3449 BUG();
3450/*uart cts*/
3451 zx29_gpio_config(pdata->uart_cts.gpionum, pdata->uart_cts.gpiofnc);
3452/*uart rts*/
3453 zx29_gpio_config(pdata->uart_rts.gpionum, pdata->uart_rts.gpiofnc);
3454
3455 control |= (UART_CR_RTSEN |UART_CR_CTSEN );
3456 control |= UART_CR_RTS; //wl write1 for allow send
3457 }
3458 zup->autobaud = pdata->uart_abauduse ;
3459 }
3460#if 0
3461 if((pdata->uart_use)&&(port->line == UART1 ))
3462 {
3463 retval=gpio_request(pdata->uart_rx.gpionum,pdata->uart_rx.gpioname);
3464 if(retval)
3465 BUG();
3466 retval=gpio_request(pdata->uart_txd.gpionum,pdata->uart_tx.gpioname);
3467 if(retval)
3468 BUG();
3469/*uart rxd*/
3470 zx29_gpio_config(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpiofnc);
3471/*uart txd*/
3472 zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
3473
3474 if(pdata->uart_ctsrtsuse)
3475 {
3476 retval=gpio_request(pdata->uart_ctsnum,"uart1_cts");
3477 if(retval)
3478 BUG();
3479 retval=gpio_request(pdata->uart_rtsnum,"uart1_rts");
3480 if(retval)
3481 BUG();
3482/*uart cts*/
3483 zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
3484/*uart rts*/
3485 zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
3486
3487 control |= (UART_CR_RTSEN |UART_CR_CTSEN );
3488 control |= UART_CR_RTS; //wl write1 for allow send
3489 }
3490 zup->autobaud = pdata->uart_abauduse;
3491 }
3492 if((pdata->uart_use)&&(port->line == UART2 ))
3493 {
3494 retval=gpio_request(pdata->uart_rxdnum,"uart2_rxd");
3495 if(retval)
3496 BUG();
3497 retval=gpio_request(pdata->uart_txdnum,"uart2_txd");
3498 if(retval)
3499 BUG();
3500
3501/*uart rxd*/
3502 zx29_gpio_config(pdata->uart_rxdnum, pdata->uart_rxdfnc);
3503 if(pdata->uart_rxdnum == ZX29_GPIO_121 ) {
3504 //pull up gpio121
3505 *(volatile unsigned int *)0xf843c82c |= 0xf0;
3506 }
3507/*uart txd*/
3508 zx29_gpio_config(pdata->uart_txdnum, pdata->uart_txdfnc);
3509
3510 if(pdata->uart_ctsrtsuse)
3511 {
3512 retval=gpio_request(pdata->uart_ctsnum,"uart2_cts");
3513 if(retval)
3514 BUG();
3515
3516 retval=gpio_request(pdata->uart_rtsnum,"uart2_rts");
3517 if(retval)
3518 BUG();
3519/*uart cts*/
3520 zx29_gpio_config(pdata->uart_ctsnum, pdata->uart_ctsfnc);
3521/*uart rts*/
3522 zx29_gpio_config(pdata->uart_rtsnum, pdata->uart_rtsfnc);
3523
3524 control |= (UART_CR_RTSEN |UART_CR_CTSEN );
3525 control |= UART_CR_RTS; //wl write1 for allow send
3526 }
3527 zup->autobaud = pdata->uart_abauduse ;
3528 }
3529#endif
3530#endif
3531 zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
3532 UART_PUT_CR(port, control);
3533
3534 /*
3535 * Finally, enable interrupts, only timeouts when using DMA
3536 * if initial RX DMA job failed, start in interrupt mode
3537 * as well.
3538 */
3539 spin_lock_irqsave(&zup->port.lock, flags);
3540 /* Clear out any spuriously appearing RX interrupts */
3541 UART_PUT_ICR(port, (UART_RTIS | UART_RXIS));
3542 //when dma not running,set UART_RTIM | UART_RXIM
3543 if(!zx29_dma_rx_running(zup)){
3544 zup->imr = UART_RTIM | UART_RXIM;
3545 UART_PUT_IMSC(port, zup->imr);
3546 }
3547#if CONFIG_SERIAL_ZX29_DMA
3548 zup->port_close = false;
3549#endif
3550 spin_unlock_irqrestore(&zup->port.lock, flags);
3551
3552
3553 return 0;
3554}
3555
3556/****************************************************************************/
3557static void zx29_uart_shutdown(struct uart_port *port)
3558{
3559 printk("zx29_uart%d_shutdown.\n",port->line);
3560 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
3561 unsigned long flags;
3562 uint32_t val;
3563 int retval = 0;
3564 struct platform_device *pdev=port->private_data;
3565 //struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
3566#if CONFIG_SERIAL_ZX29_DMA
3567 zup->port_close = true;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3568 if(zup->uart_power_mode)
3569 up(&zup->sema_cyclic);
3570 else
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3571 up(&zup->sema);
3572#endif
3573 int ret;
3574 tasklet_kill(&zup->write_wakeup);
3575#if RX_DMA_WORK
3576 if(zx29_dma_rx_work_scheduled(zup)){
3577 ret = del_timer_sync(&(zup->rx_dma_timer));
3578 ret = hrtimer_cancel(&zup->rx_dma_hrtimer);
3579 zup->work_state = 0;
3580 }
3581#endif
3582 /* Disable and clear all interrupts now */
3583 spin_lock_irqsave(&port->lock, flags);
3584 zup->imr = 0;
3585 UART_PUT_IMSC(port, zup->imr);
3586 UART_PUT_ICR(port, 0xFFFF);
3587
3588 spin_unlock_irqrestore(&port->lock, flags);
3589#if CONFIG_SERIAL_ZX29_DMA
3590 zx29_dma_shutdown(zup);
3591#endif
3592 /* Free the interrupt */
3593 free_irq(zup->port.irq, zup);
3594
3595 /* Disable UART transmitter and receiver */
3596 zup->autorts = false;
3597 val = UART_GET_CR(port);
3598 if (val & UART_CR_RTS) {
3599 zup->rts_state = true;
3600 val = UART_CR_RTS;
3601 } else
3602 zup->rts_state = false;
3603 val = UART_CR_UARTEN | UART_CR_TXE;
3604 UART_PUT_CR(port, val);
3605
3606 /* disable break condition and fifos */
3607 val = UART_GET_LCRH(port);
3608 val &= ~(UART_LCRH_BRK | UART_LCRH_FEN);
3609 UART_PUT_LCRH(port, val);
3610 if(zup->uart_power_mode){
3611 //pm_relax(&pdev->dev);
3612 zup->app_ctrl = 0;
3613 zup->uart_power_mode = 0;
3614 }
3615
3616 if((pdev->id == 0) && (zup->irq_state == 1) && (zup->uart_power_mode == 0)){
3617 free_irq(zup->rxd_irq, zup);
3618 disable_irq_wake(zup->rxd_irq);
3619 zup->irq_state = 0;
3620 }
3621
3622#if 0
3623 if(pdata->uart_use)
3624 {
3625 if(pdata->uart_ctsrtsuse)
3626 {
3627 gpio_free(pdata->uart_cts.gpionum);
3628 gpio_free(pdata->uart_rts.gpionum);
3629 }
3630#ifdef CONFIG_ARCH_ZX297520V3
3631 if((pdev->id != DEBUG_CONSOLE) && (pdata->uart_wakeup_enable == 1) && (zup->irq_state == 1)){
3632 printk(KERN_INFO"zx29_uart_shutdown,irq:%d,%s\n",zup->irq,pdata->uart_cts.gpioname);
3633 if(zup->irq){
3634 free_irq(zup->irq, zup);
3635 pcu_int_clear(PCU_UART0_RXD_INT);
3636 irq_set_irq_wake(zup->irq, 0);
3637 zup->irq_state = 0;
3638 zup->rxd_int_depth = 0;
3639 }
3640 }
3641#endif
3642 gpio_free(pdata->uart_rxd.gpionum);
3643 gpio_free(pdata->uart_txd.gpionum);
3644
3645#ifdef CONFIG_ARCH_ZX297520V3_WATCH
3646 if(port->line == 0)
3647 {
3648 retval = gpio_request(pdata->uart_txd.gpionum, pdata->uart_txd.gpioname);
3649 if(retval)
3650 {
3651 BUG();
3652 }
3653 zx29_gpio_config(pdata->uart_txd.gpionum, GPIO30_GPIO30);
3654 gpio_direction_input(pdata->uart_txd.gpionum);
3655
3656 retval = gpio_request(pdata->uart_rxd.gpionum, pdata->uart_rxd.gpioname);
3657 if(retval)
3658 {
3659 BUG();
3660 }
3661 zx29_gpio_config(pdata->uart_rxd.gpionum, GPIO29_GPIO29);
3662 gpio_direction_input(pdata->uart_rxd.gpionum);
3663 }
3664#endif
3665
3666 }
3667#endif
3668 /* Shutdown uart clock */
3669}
3670
3671/****************************************************************************/
3672static void zx29_uart_set_termios(struct uart_port *port, struct ktermios *termios,
3673 struct ktermios *old)
3674{
3675 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
3676 unsigned int lcr_h, old_cr;
3677 unsigned long flags;
3678 unsigned int baud, ibrd, fbrd,j;
3679
3680 //temple change,using setting from cmm script
3681 //if(port->line == DEBUG_CONSOLE)
3682 //return;
3683
3684 /* Set baud rate */
3685 /* Ask the core to calculate the divisor for us. */
3686 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
3687 printk("uart port %d baud is %d.\n",port->line,baud);
3688
3689 //this should not hapend
3690 if(baud == 0)
3691 BUG_ON(1);
3692 zup->baudrate = baud;
3693 ibrd = port->uartclk / (baud<<4);
3694 fbrd = ((port->uartclk % (baud<<4) )*8 + baud)/(2*baud);
3695 UART_PUT_FBRD(port, fbrd);
3696 UART_PUT_IBRD(port, ibrd);
3697
3698printk("-------zx29_uart_set_termios,line:%d, new baud:%d, uartclk:%d,ibrd:%d, fbrd:%d \n", port->line,
3699 baud, port->uartclk, ibrd, fbrd);
3700
3701 switch (termios->c_cflag & CSIZE) {
3702 case CS5:
3703 lcr_h = UART_LCRH_WLEN_5;
3704 break;
3705 case CS6:
3706 lcr_h = UART_LCRH_WLEN_6;
3707 break;
3708 case CS7:
3709 lcr_h = UART_LCRH_WLEN_7;
3710 break;
3711 default: // CS8
3712 lcr_h = UART_LCRH_WLEN_8;
3713 break;
3714 }
3715 if (termios->c_cflag & CSTOPB)
3716 lcr_h |= UART_LCRH_STP2;
3717 if (termios->c_cflag & PARENB) {
3718 lcr_h |= UART_LCRH_PEN;
3719 if (!(termios->c_cflag & PARODD))
3720 lcr_h |= UART_LCRH_EPS;
3721 }
3722 if (port->fifosize > 1)
3723 lcr_h |= UART_LCRH_FEN;
3724
3725 spin_lock_irqsave(&port->lock, flags);
3726
3727 /*
3728 * Update the per-port timeout.
3729 */
3730 uart_update_timeout(port, termios->c_cflag, baud);
3731
3732 port->read_status_mask = UART_DR_OE | 255;
3733 if (termios->c_iflag & INPCK)
3734 port->read_status_mask |= UART_DR_FE | UART_DR_PE;
3735 if (termios->c_iflag & (BRKINT | PARMRK))
3736 port->read_status_mask |= UART_DR_BE;
3737
3738 /*
3739 * Characters to ignore
3740 */
3741 port->ignore_status_mask = 0;
3742 if (termios->c_iflag & IGNPAR)
3743 port->ignore_status_mask |= UART_DR_FE | UART_DR_PE;
3744 if (termios->c_iflag & IGNBRK) {
3745 port->ignore_status_mask |= UART_DR_BE;
3746 /*
3747 * If we're ignoring parity and break indicators,
3748 * ignore overruns too (for real raw support).
3749 */
3750 if (termios->c_iflag & IGNPAR)
3751 port->ignore_status_mask |= UART_DR_OE;
3752 }
3753
3754 /*
3755 * Ignore all characters if CREAD is not set.
3756 */
3757 if ((termios->c_cflag & CREAD) == 0)
3758 port->ignore_status_mask |= UART_DUMMY_DR_RX;
3759
3760 if (UART_ENABLE_MS(port, termios->c_cflag))
3761 zx29_uart_enable_ms(port);
3762
3763 /* first, disable everything */
3764 old_cr = UART_GET_CR(port);
3765 UART_PUT_CR(port, 0);
3766
3767 if (termios->c_cflag & CRTSCTS) {
3768 if (old_cr & UART_CR_RTS)
3769 old_cr |= UART_CR_RTSEN;
3770
3771 old_cr |= UART_CR_CTSEN;
3772 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
3773 zup->autorts = true;
3774 } else {
3775 old_cr &= ~(UART_CR_CTSEN | UART_CR_RTSEN);
3776 zup->autorts = false;
3777 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
3778 }
3779
3780 /*
3781 * ----------v----------v----------v----------v-----
3782 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
3783 * ----------^----------^----------^----------^-----
3784 */
3785 UART_PUT_LCRH(port, lcr_h);
3786 UART_PUT_CR(port, old_cr);
3787
3788 spin_unlock_irqrestore(&port->lock, flags);
3789 if( zup->autobaud_state == UART_PORT_AUTOBAUD_ON)
3790 {
3791 msleep(50);
3792 zup->port.icount.rx = 0;
3793
3794 for( j = 0; j<UART_AT_SENDOK_NUM; j++)
3795 {
3796 while (UART_GET_FR(port) & UART_FR_TXFF)
3797 barrier();
3798 UART_PUT_CHAR(&zup->port, UART_AT_send_ok[j]);
3799 }
3800
3801 zup->autobaud_state = UART_PORT_AUTOBAUD_OFF;
3802 }
3803}
3804
3805/****************************************************************************/
3806static const char *zx29_uart_type(struct uart_port *port)
3807{
3808 return (port->type == PORT_ZX29) ? "zx29_UART" : NULL;
3809}
3810
3811/****************************************************************************/
3812
3813static int zx29_uart_request_port(struct uart_port *port)
3814{
3815 /* UARTs always present */
3816// return request_mem_region(port->mapbase, SZ_4K, "uart-zx29")!= NULL ? 0 : -EBUSY;
3817 return 0;
3818}
3819
3820/****************************************************************************/
3821static void zx29_uart_config_port(struct uart_port *port, int flags)
3822{
3823 if (flags & UART_CONFIG_TYPE) {
3824 port->type = PORT_ZX29;
3825 zx29_uart_request_port(port);
3826 }
3827}
3828
3829/****************************************************************************/
3830
3831static void zx29_uart_release_port(struct uart_port *port)
3832{
3833// release_mem_region(port->mapbase, SZ_4K);
3834}
3835
3836/****************************************************************************/
3837
3838static int zx29_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
3839{
3840 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ZX29))
3841 return -EINVAL;
3842 return 0;
3843}
3844
3845
3846void zx29_uart_putc(struct uart_port *port, int c)
3847{
3848 while (UART_GET_FR(port) & UART_FR_TXFF)
3849 barrier();
3850 UART_PUT_CHAR(port, c);
3851}
3852
3853
3854#ifdef CONFIG_CONSOLE_POLL
3855/****************************************************************************/
3856static int zx29_get_poll_char(struct uart_port *port)
3857{
3858 if (UART_GET_FR(port) & UART_FR_RXFE)
3859 return NO_POLL_CHAR;
3860
3861 return UART_PUT_CHAR(port);
3862}
3863
3864/****************************************************************************/
3865static void zx29_put_poll_char(struct uart_port *port, unsigned char ch)
3866{
3867 while (UART_GET_FR(port) & UART_FR_TXFF)
3868 barrier();
3869 UART_PUT_CHAR(port, ch);
3870}
3871#endif /* CONFIG_CONSOLE_POLL */
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3872extern int tty_buffer_space_avail(struct tty_port *port);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3873static void zx29_uart_throttle_rx(struct uart_port *port)
3874{
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3875 test_uart_static(port->line, NULL, 0, 80);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3876 unsigned long flags;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3877 int uart_id = port->line;
3878
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3879 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
3880 dma_peripheral_id rx_id = uart_get_rx_dma_peripheral_id(zup);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3881 spin_lock_irqsave(&port->lock, flags);
3882 if(!uart_dma_cycle[port->line].used)
3883 uart_id = uart_id + 3;
3884 if(!tty_buffer_space_avail(&port->state->port)){
3885 zx29_dma_stop(DMA_CH_UART0_RX);
3886 uart_dma_cycle[uart_id].enter_throttle = true;
3887 uart_dma_cycle[uart_id].cnt_throttle++;
3888 }
3889 spin_unlock_irqrestore(&port->lock, flags);
3890 #if 0
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3891 while(zx29_dma_get_transfer_num(rx_id) != 4096)
3892 msleep(1);
3893 spin_lock_irqsave(&port->lock, flags);
3894 zup->dmacr &= ~UART_RXDMAE;
3895 UART_PUT_DMACR(&zup->port,zup->dmacr);
3896 zx29_dma_stop(rx_id);
3897 zup->dmarx.running = false;
3898 zup->dmarx.used = false;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3899 uart_dma_cycle[port->line].enter_throttle = true;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3900 spin_unlock_irqrestore(&port->lock, flags);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3901 #endif
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3902}
3903static void zx29_uart_unthrottle_rx(struct uart_port *port)
3904{
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3905 test_uart_static(port->line, NULL, 0, 81);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3906 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
3907 unsigned long flags;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3908 int uart_id = port->line;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3909 spin_lock_irqsave(&port->lock, flags);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3910 if(!uart_dma_cycle[port->line].used)
3911 uart_id = uart_id + 3;
3912 uart_dma_cycle[uart_id].enter_throttle = false;
3913 uart_dma_cycle[uart_id].from_unthrottle = true;
3914 uart_dma_cycle[uart_id].cnt_unthrottle++;
3915 #if 0
3916 if (zx29_dma_rx_trigger_dma_use_dma_cyclic(zup)) {
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3917 printk("rx_dma_chars RXDMA start fail\n");
3918 zup->imr |= (UART_RTIM|UART_RXIM);
3919 UART_PUT_IMSC(&zup->port,zup->imr);
3920 }else{
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3921 hrtimer_forward_now(&zup->rx_dma_hrtimer, g_hr_interval);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3922 zup->pre_pending = 0;
3923 zup->dmarx.used = true;
3924 zup->work_state = true;
3925 UART_PUT_ICR(&zup->port,(UART_RTIS|UART_RXIS));
3926 }
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3927 #endif
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3928 spin_unlock_irqrestore(&port->lock, flags);
3929}
3930
3931/****************************************************************************/
3932/*
3933 * Define the basic serial functions we support.
3934 */
3935static const struct uart_ops zx29_uart_ops = {
3936 .tx_empty = zx29_uart_tx_empty,
3937 .set_mctrl = zx29_uart_set_mctrl,
3938 .get_mctrl = zx29_uart_get_mctrl,
3939 .start_tx = zx29_uart_start_tx,
3940 .stop_tx = zx29_uart_stop_tx,
3941 .stop_rx = zx29_uart_stop_rx,
3942 .throttle = zx29_uart_throttle_rx,
3943 .unthrottle = zx29_uart_unthrottle_rx,
3944 .enable_ms = zx29_uart_enable_ms,
3945 .break_ctl = zx29_uart_break_ctl,
3946 .startup = zx29_uart_startup,
3947 .shutdown = zx29_uart_shutdown,
3948 .set_termios = zx29_uart_set_termios,
3949#if CONFIG_SERIAL_ZX29_DMA
3950 .flush_buffer = zx29_dma_flush_buffer,
3951#endif
3952 .type = zx29_uart_type,
3953 .request_port = zx29_uart_request_port,
3954 .release_port = zx29_uart_release_port,
3955 .config_port = zx29_uart_config_port,
3956 .verify_port = zx29_uart_verify_port,
3957#ifdef CONFIG_CONSOLE_POLL
3958 .poll_get_char = zx29_get_poll_char,
3959 .poll_put_char = zx29_put_poll_char,
3960#endif
3961
3962};
3963
3964
3965/****************************************************************************/
3966static int zx29_init_ports(struct zx29_uart_port *zx29_port,
3967 struct platform_device *pdev)
3968{
3969 int ret = 0;
3970 struct uart_port *port=&zx29_port->port;
3971 unsigned int offset=(unsigned int)(pdev->id);
3972 struct device_node *np = pdev->dev.of_node;
3973 unsigned int baud, ibrd, fbrd;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]3974
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3975 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3976 //struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3977
3978 if(!regs){
3979 dev_err(&pdev->dev, "zx29_init_ports, get resource fail,\n");
3980 return -ENODEV;
3981 }
3982/*get apb clock*/
3983 zx29_port->busclk = devm_clk_get(&pdev->dev, UART_APBCLK_NAME);
3984 if (IS_ERR(zx29_port->busclk)) {
3985 ret = PTR_ERR(zx29_port->busclk);
3986 printk("failed to get zx29_port->busclk: %d\n", ret);
3987 return ret;
3988 }
3989
3990 /*get work clock*/
3991 zx29_port->wclk = devm_clk_get(&pdev->dev, UART_WCLK_NAME);
3992
3993 if (IS_ERR(zx29_port->wclk)) {
3994 ret = PTR_ERR(zx29_port->wclk);
3995 printk("failed to get zx29_port->wclk: %d\n", ret);
3996 return ret;
3997 }
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]3998 if(offset == 0){
3999 clk_set_rate(zx29_port->wclk, 104 * 1000000);
4000 }
4001 port->line = offset;
4002 port->type = PORT_ZX29;
4003 port->fifosize = UART_TXFIFO_SIZE;
4004 //port->iotype = UPIO_MEM;
4005 //port->irq = irq->start;
4006 port->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
4007 if(pdev->id == 0){
4008 zx29_port->rxd_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
4009 }
4010 //port->membase = devm_ioremap_nocache(&pdev->dev, regs->start,
4011 // resource_size(regs));
4012 port->membase = devm_platform_ioremap_resource(pdev, 0);
4013
4014 if (!port->membase)
4015 return -ENODEV;
4016 port->mapbase = regs->start;
4017 port->mapsize = resource_size(regs);
4018
4019 //port->flags = UPF_BOOT_AUTOCONF;
4020 port->ops = &zx29_uart_ops;
4021 port->uartclk = clk_get_rate(zx29_port->wclk);
4022
4023 port->private_data = pdev;
4024 //here is temple def
4025 if(port->uartclk == 0){
4026 printk("---zx29_init_ports, uartclk hard set to 26M\n");
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]4027 port->uartclk = 26000000;
4028 }
4029 printk("---zx29_init_ports, line:%d, irq:%d, membase:%08x, uartclk:%d\n", port->line, port->irq, port->membase, port->uartclk);
4030 /*
4031 * just configure clock,
4032 * actually pin configuration is needed, but now gpio driver is not OK
4033 * use bootloader default configuration
4034 */
4035 if(DEBUG_CONSOLE == pdev->id){
4036 /* config uart apb_clk */
4037 clk_prepare_enable(zx29_port->busclk);
4038
4039 /* enable uart work clock */
4040 clk_prepare_enable(zx29_port->wclk);
4041 }
4042 return 0;
4043}
4044
4045
4046#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
4047
4048#if VEHICLE_USE_ONE_UART_LOG
4049static void zx29_uart_console_putc(struct uart_port *port, int c)
4050{
4051 if(g_core_id_occupy_uart == SYMB_PS_CORE_ID)
4052 return;
4053 int ret = soft_spin_lock_printf(UART_SFLOCK);
4054 if(ret)
4055 return;
4056 while (UART_GET_FR(port) & UART_FR_TXFF)
4057 barrier();
4058 UART_PUT_CHAR(port, c);
4059 soft_spin_unlock(UART_SFLOCK);
4060}
4061#else
4062static void zx29_uart_console_putc(struct uart_port *port, int c)
4063{
4064 while (UART_GET_FR(port) & UART_FR_TXFF)
4065 barrier();
4066 UART_PUT_CHAR(port, c);
4067}
4068
4069#endif
4070
4071
4072
4073/****************************************************************************/
4074static void zx29_uart_console_write(struct console *co, const char *s, unsigned int count)
4075{
4076 struct uart_port *port = &zx29_uart_ports[co->index].port;
4077
4078 //spin_lock(&port->lock);
4079 for (; (count); count--, s++) {
4080 zx29_uart_console_putc(port, *s);
4081 if (*s == '\n')
4082 zx29_uart_console_putc(port, '\r');
4083 }
4084
4085 //spin_unlock(&port->lock);
4086}
4087
4088/***************************************************************************
4089 * If the port was already initialised (eg, by a boot loader),
4090 * try to determine the current setup.
4091 ****************************************************************************/
4092static void __init zx29_console_get_options(struct uart_port *port, int *baud,
4093 int *parity, int *bits)
4094{
4095 if (UART_GET_CR(port) & UART_CR_UARTEN) {
4096 unsigned int lcr_h, ibrd, fbrd;
4097
4098 lcr_h = UART_GET_LCRH(port);
4099 *parity = 'n';
4100 if (lcr_h & UART_LCRH_PEN) {
4101 if (lcr_h & UART_LCRH_EPS)
4102 *parity = 'e';
4103 else
4104 *parity = 'o';
4105 }
4106 if ((lcr_h & 0x60) == UART_LCRH_WLEN_7)
4107 *bits = 7;
4108 else
4109 *bits = 8;
4110
4111 ibrd = UART_GET_IBRD(port);
4112 fbrd = UART_GET_FBRD(port);
4113
4114 *baud = port->uartclk * 8 / (16*8 * ibrd + 2*fbrd-1);
4115 }
4116}
4117
4118/****************************************************************************/
4119static int __init zx29_uart_console_setup(struct console *co, char *options)
4120{
4121 printk("zx29_uart_console_setup.\n");
4122 struct uart_port *port;
4123 int baud = 115200;
4124 int bits = 8;
4125 int parity = 'n';
4126 int flow = 'n';
4127 unsigned int uart_cr = 0;
4128
4129 if ((co->index < 0) || (co->index >= zx29_MAXPORTS))
4130 co->index = CONFIG_UART_CONSOLE_ID;
4131
4132 port = &zx29_uart_ports[co->index].port;
4133 if (port->membase == NULL)
4134 return -ENODEV;
4135
4136 uart_cr = UART_GET_CR(port);
4137 uart_cr |= UART_CR_UARTEN | UART_CR_TXE;
4138 UART_PUT_CR(port,uart_cr);
4139
4140 if (options)
4141 uart_parse_options(options, &baud, &parity, &bits, &flow);
4142 else
4143 zx29_console_get_options(port, &baud, &parity, &bits);
4144
4145 return uart_set_options(port, co, baud, parity, bits, flow);
4146}
4147
4148/****************************************************************************/
4149
4150static struct uart_driver zx29_uart_driver;
4151int zx29_get_console_index(void)
4152{
4153#if 0
4154 int dev_cnt = zx29_device_table_num;
4155 int idx = 0;
4156 struct platform_device *pdev = NULL;
4157 for(idx = 0; idx < dev_cnt; idx++)
4158 {
4159 pdev = zx29_device_table[idx];
4160 if(strcmp(pdev->name,"zx29_uart") == 0 && pdev->id == CONFIG_UART_CONSOLE_ID)
4161 return idx;
4162 }
4163#endif
4164 return CONFIG_UART_CONSOLE_ID;
4165 //return -1;
4166}
4167static struct console zx29_uart_console = {
4168 .name = "ttyS",
4169 .write = zx29_uart_console_write,
4170 .device = uart_console_device,
4171 .setup = zx29_uart_console_setup,
4172 .flags = CON_PRINTBUFFER,
4173 .index = -1,
4174 .data = &zx29_uart_driver,
4175};
4176static int __init zx29_uart_console_init(void)
4177{
4178 int console_dev_id = zx29_get_console_index();
4179
4180 if(console_dev_id < 0){
4181 printk("console init fail, uart config fail, console_dev_id is: %d", console_dev_id);
4182 return -1;
4183 }
4184 //zx29_init_ports(&zx29_uart_ports[DEBUG_CONSOLE], zx29_device_table[console_dev_id]);
4185 register_console(&zx29_uart_console);
4186 pr_info("[UART]register_console: zx29 console registered!\n");
4187
4188 return 0;
4189}
4190
4191//console_initcall(zx29_uart_console_init);
4192
4193#define zx29_UART_CONSOLE (&zx29_uart_console)
4194
4195
4196static void zx29_uart_early_write(struct console *con, const char *s, unsigned n)
4197{
4198 struct earlycon_device *dev = con->data;
4199
4200 uart_console_write(&dev->port, s, n, zx29_uart_console_putc);
4201}
4202
4203static int __init zx29_uart_early_console_setup(struct earlycon_device *device,
4204 const char *opt)
4205{
4206 if (!device->port.membase)
4207 return -ENODEV;
4208
4209 device->con->write = zx29_uart_early_write;
4210
4211 return 0;
4212}
4213
4214OF_EARLYCON_DECLARE(zx29_uart, "zxic,zx29-uart", zx29_uart_early_console_setup);
4215#else
4216#define zx29_UART_CONSOLE NULL
4217#endif /* CONFIG_zx29_UART_CONSOLE */
4218static void zx29_uart_pin_ctrl(struct platform_device *pdev)
4219{
4220 struct pinctrl *pin_ctrl;
4221 struct pinctrl_state *state0;
4222 pin_ctrl = devm_pinctrl_get(&pdev->dev);
4223 switch(pdev->id){
4224 case 0:
4225 printk("zx29_uart %d use default pinctrl.",pdev->id);
4226 break;
4227 case 1:
4228 printk("zx29_uart %d use default pinctrl.",pdev->id);
4229 break;
4230
4231 case 2:
4232 if(IS_ERR(pin_ctrl)){
4233 dev_warn(&pdev->dev, "fail to get uart2 pins.");
4234 pin_ctrl = NULL;
4235 return;
4236 }
4237 state0 = pinctrl_lookup_state(pin_ctrl, "default");
4238 if(IS_ERR(state0)){
4239 dev_err(&pdev->dev, "uart2 pinstate get fail.\n");
4240 }
4241 if(pinctrl_select_state(pin_ctrl, state0)){
4242 dev_err(&pdev->dev, "uart2 select pinstate fail.\n");
4243 }
4244 break;
4245 }
4246}
4247
4248/*
4249 * Define the zx29 UART driver structure.
4250 */
4251static struct uart_driver zx29_uart_driver = {
4252 .owner = THIS_MODULE,
4253 .driver_name = "zx29_uart",
4254 .dev_name = "ttyS",
4255 .major = SERIAL_zx29_MAJOR,
4256 .minor = SERIAL_MINOR_START,
4257 .nr = zx29_MAXPORTS,
4258 .cons = zx29_UART_CONSOLE,
4259};
4260
4261unsigned char uart_wakelock_name[zx29_MAXPORTS][20]={{0}};
4262/****************************************************************************/
4263
4264
4265#ifdef CONFIG_PM_SLEEP
4266static int zx29_uart_suspend(struct device *dev)
4267{
4268 int ret = 0;
4269 struct zx29_uart_port *zup = dev_get_drvdata(dev);
4270 unsigned int flags;
4271 if (!zup)
4272 return -EINVAL;
4273 if(zup->port.line == UART1)
4274 return 0;
4275#if 1
4276 pinctrl_pm_select_sleep_state(dev);
4277#endif
4278
4279 printk("zx29_uart%d suspend.\n",zup->port.line);
4280
4281 raw_spin_lock_irqsave(&zup->port.lock, flags);
4282 zup->enter_suspend = 1;
4283 if(zup->port.line == UART2){
4284 zx29_dma_stop(DMA_CH_UART2_RX);
4285 zx29_dma_stop(DMA_CH_UART2_TX);
4286 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
4287 return 0;
4288 }
4289
4290 zx29_dma_stop(DMA_CH_UART0_RX);
4291 zx29_dma_stop(DMA_CH_UART0_TX);
4292 raw_spin_unlock_irqrestore(&zup->port.lock, flags);
4293#if 0
4294 ret = irq_set_irq_type(unsigned int irq, unsigned int type);
4295
4296#endif
4297 //pcu_int_clear(PCU_UART0_RXD_INT);
4298 if(zup->irq_state && (zup->rxd_int_depth == 0)){
4299 struct irq_data *data_rxd;
4300 data_rxd= irq_get_irq_data(zup->rxd_irq);
4301 if(data_rxd){
4302 if(irqd_irq_disabled(data_rxd))
4303 enable_irq(zup->rxd_irq);
4304 }
4305 zup->rxd_int_depth = 1;
4306 }
4307
4308 return 0;
4309}
4310
4311static int zx29_uart_resume(struct device *dev)
4312{
4313 struct zx29_uart_port *zup = dev_get_drvdata(dev);
4314
4315 if (!zup)
4316 return -EINVAL;
4317 int uart_id = zup->port.line;
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]4318 if(!uart_dma_cycle[zup->port.line].used)
4319 uart_id = uart_id + 3;
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]4320 if(zup->port.line == UART1)
4321 return 0;
4322#if 1
4323 pinctrl_pm_select_default_state(dev);
4324#endif
4325
4326 printk("zx29_uart%d resume.\n",zup->port.line);
4327
4328 zup->enter_suspend = 0;
4329 uart_dma_cycle[uart_id].from_resume = 1;
4330 return 0;
4331}
4332
4333
4334#endif
4335
4336static SIMPLE_DEV_PM_OPS(zx29_uart_dev_pm_ops, zx29_uart_suspend, zx29_uart_resume);
4337
4338
4339
4340static int zx29_uart_probe(struct platform_device *pdev)
4341{
4342 int ret=0;
4343 int error;
4344 char wakelock_name[20];
4345 struct device_node *np = pdev->dev.of_node;
4346 ret = of_alias_get_id(np, "uart");
4347
4348 if(ret < 0){
4349 printk("-----zx29_uart_probe,of_alias_get_id fail ret:%d\n", ret);
4350 return -ENODEV;
4351 }
4352 pdev->id = ret;
4353 printk("-----zx29_uart_probe,ret:%d\n", ret);
4354 // struct zx29_uart_platdata *pdata = pdev->dev.platform_data;
4355 struct zx29_uart_port *port = &zx29_uart_ports[pdev->id];
4356
4357
4358#if 0//def CONFIG_SERIAL_ZX29_UART_CONSOLE
4359 if(DEBUG_CONSOLE != pdev->id){
4360 ret = zx29_init_ports(port,pdev);
4361 }
4362#else
4363 ret = zx29_init_ports(port,pdev);
4364
4365#endif
4366 if(ret < 0){
4367 printk("-----zx29_uart_probe,zx29_init_ports fail ret:%d\n", ret);
4368 }
4369 zx29_uart_pin_ctrl(pdev);
4370#if CONFIG_SERIAL_ZX29_DMA
4371 if((DEBUG_CONSOLE != pdev->id ) && (pdev->id != 4))
4372 {
4373 uart_dma_init(port);
4374 printk(KERN_INFO "[%s][%d]UART_%d DMA is OPENED\n",__func__,__LINE__,pdev->id);
4375 }
4376#endif
4377 ret = 0;
4378 ret=uart_add_one_port(&zx29_uart_driver, &port->port);
4379
4380 if(ret)
4381 {
4382#if CONFIG_SERIAL_ZX29_DMA
4383 zx29_dma_remove(port);
4384#endif
4385 return ret;
4386 }
4387#if CONFIG_SERIAL_ZX29_DMA
4388 sema_init(&port->sema, 0);
4389#endif
4390
4391 platform_set_drvdata(pdev, port);
4392
4393 if(pdev->id == DEBUG_CONSOLE){
4394 //g_console_open_flag = pdata->uart_input_enable ? pdata->uart_input_enable : 0;
4395 error = device_create_file(&pdev->dev, &dev_attr_console_input);
4396#if VEHICLE_USE_ONE_UART_LOG
4397 error = device_create_file(&pdev->dev, &dev_attr_console_uart_toggle);
4398 error = device_create_file(&pdev->dev, &dev_attr_coreid_occupy_uart);
4399 int ret;
4400 ret = rpmsgCreateChannel(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, ICP_BUFFERSIZE_CONSOLE_TOGGLE);
4401 if(ret){
4402 printk("linux5 request icp channel for uart fail %d.\n",ret);
4403 }
4404 rpmsgRegCallBack(CORE_PS0, ICP_CHANNEL_CONSOLE_UART, icp_callback_ps2cap);
4405#endif
4406 }
4407
4408 if(pdev->id != DEBUG_CONSOLE){
4409 error = device_create_file(&pdev->dev, &dev_attr_ctsrts_input);
4410 error = device_create_file(&pdev->dev, &dev_attr_wakeup_enable);
4411 error = device_create_file(&pdev->dev, &dev_attr_sleep_state);
4412 error = device_create_file(&pdev->dev, &dev_attr_app_ctrl);
4413
4414 }
4415 error = device_create_file(&pdev->dev, &dev_attr_statics);
4416 device_init_wakeup(&pdev->dev, true);
4417/*
4418 strcpy(wakelock_name, "uart_wakelock_x");
4419 wakelock_name[14] = '0' + pdev->id;
4420 strcpy(uart_wakelock_name[pdev->id], wakelock_name);
4421 wake_lock_init(&(port->port.port_wakelock),WAKE_LOCK_SUSPEND,uart_wakelock_name[pdev->id]);
4422*/
4423
4424 printk(KERN_INFO "TSP zx29 UART_%d probe OK\n",pdev->id);
4425 return 0;
4426}
4427
4428/****************************************************************************/
4429static int /*__devexit*/ zx29_uart_remove(struct platform_device *pdev)
4430{
4431 struct uart_port *port = NULL;
4432#if CONFIG_SERIAL_ZX29_DMA
4433 struct zx29_uart_port *zup = container_of(port, struct zx29_uart_port, port);
4434#endif
4435 int i;
4436 if(pdev->id == DEBUG_CONSOLE){
4437 device_remove_file(&pdev->dev, &dev_attr_console_input);
4438 }
4439
4440 if(pdev->id != DEBUG_CONSOLE){
4441 device_remove_file(&pdev->dev, &dev_attr_ctsrts_input);
4442 device_remove_file(&pdev->dev, &dev_attr_wakeup_enable);
4443 }
4444
4445 for (i = 0; (i < zx29_MAXPORTS); i++) {
4446 port = &zx29_uart_ports[i].port;
4447 if (port){
4448 uart_remove_one_port(&zx29_uart_driver, port);
4449
4450
4451#if CONFIG_SERIAL_ZX29_DMA
4452 zup=container_of(port,struct zx29_uart_port,port);
4453 zx29_dma_remove(zup);
4454
4455#endif
4456 }
4457 }
4458 return 0;
4459}
4460
4461static const struct of_device_id zx29_uart_of_match[] = {
4462 { .compatible = "zxic,zx29-uart"},
4463 {},
4464};
4465MODULE_DEVICE_TABLE(of, zx29_uart_of_match);
4466
4467static struct platform_driver zx29_uart_platform_driver = {
4468 .probe = zx29_uart_probe,
4469 //.remove = __devexit_p(zx29_uart_remove),
4470 .remove = zx29_uart_remove,
4471 .driver = {
4472 .name = "zx29_uart",
4473 .pm = &zx29_uart_dev_pm_ops,
4474 .of_match_table = of_match_ptr(zx29_uart_of_match),
4475 .owner = THIS_MODULE,
4476 },
4477};
4478
4479static int __init zx29_uart_init(void)
4480{
4481 int rc;
4482
4483 rc = uart_register_driver(&zx29_uart_driver);
4484 if (rc)
4485 return rc;
4486 rc = platform_driver_register(&zx29_uart_platform_driver);
4487 if (rc){
4488 uart_unregister_driver(&zx29_uart_driver);
4489 return rc;
4490 }
4491
4492 printk(KERN_INFO "zx29 UART driver registered\n");
4493
4494 return 0;
4495}
4496
4497static void __exit zx29_uart_exit(void)
4498{
4499#ifdef CONFIG_SERIAL_ZX29_UART_CONSOLE
4500 unregister_console(&zx29_uart_console);
4501#endif
4502 platform_driver_unregister(&zx29_uart_platform_driver);
4503 uart_unregister_driver(&zx29_uart_driver);
4504}
4505//arch_initcall(zx29_uart_init);
4506
4507//subsys_initcall(zx29_uart_init);
4508module_init(zx29_uart_init);
4509module_exit(zx29_uart_exit);
4510