xf.li | 3dd5374 | 2024-09-27 00:06:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright (C) 2015-2022 ZTE-TSP |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | */ |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/errno.h> |
| 12 | #include <linux/irq.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/of_device.h> |
| 16 | #include <linux/of_irq.h> |
| 17 | #include <linux/of_address.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/irqdomain.h> |
| 20 | #include <linux/irqchip/chained_irq.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_address.h> |
| 23 | #include <linux/of_irq.h> |
| 24 | #include <linux/percpu.h> |
| 25 | #include <linux/refcount.h> |
| 26 | #include <linux/slab.h> |
| 27 | #include <linux/irqchip.h> |
| 28 | #include <linux/suspend.h> |
| 29 | #include <linux/syscore_ops.h> |
| 30 | #include <linux/mfd/syscon.h> |
| 31 | #include <linux/regmap.h> |
| 32 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 33 | |
| 34 | #include <linux/soc/sc/common.h> |
| 35 | #include <linux/soc/sc/spinlock.h> |
| 36 | #include <linux/soc/sc/pcu.h> |
| 37 | #include <linux/soc/sc/rpmsg.h> |
| 38 | #include <dt-bindings/soc/zx297520v3-irq.h> |
| 39 | #include <uapi/linux/sc_bsp/bsp_api.h> |
| 40 | |
| 41 | #include "pcu-common.h" |
| 42 | |
| 43 | #if 0 |
| 44 | |
| 45 | #define pm_ram_log(fmt, args...) \ |
| 46 | { \ |
| 47 | pm_printk("[SLP] " fmt, ##args); \ |
| 48 | } |
| 49 | #else |
| 50 | #define pm_ram_log(fmt, args...) \ |
| 51 | { \ |
| 52 | printk(KERN_INFO "[SLP] " fmt, ##args); \ |
| 53 | } |
| 54 | |
| 55 | #endif |
| 56 | |
| 57 | #define ZX_IRQ_NUM (IRQ_ZX297520V3_SPI_NUM + 32) |
| 58 | |
| 59 | #define PCU_LOCK reg_spin_lock(); |
| 60 | #define PCU_UNLOCK reg_spin_unlock(); |
| 61 | |
| 62 | static struct zx_pcu_int_info zx297520v3_pcu_int_info[] = |
| 63 | { |
| 64 | { |
| 65 | .pcu_index = PCU_AP_TIMER1_INT, |
| 66 | .gic_index = AP_TIMER1_INT, |
| 67 | .status_index = 51, |
| 68 | .wake_index = 0, |
| 69 | .int_name = "ap_timer1", |
| 70 | .irq_type = IRQ_TYPE_EDGE_RISING, |
| 71 | .wl_type = PM_WL_EVENT_AP_TIMER1, |
| 72 | }, |
| 73 | { |
| 74 | .pcu_index = PCU_AP_TIMER2_INT, |
| 75 | .gic_index = AP_TIMER2_INT, |
| 76 | .status_index = 52, |
| 77 | .wake_index = 1, |
| 78 | .int_name = "ap_timer2", |
| 79 | .irq_type = IRQ_TYPE_EDGE_RISING, |
| 80 | .wl_type = PM_WL_EVENT_AP_TIMER2, |
| 81 | }, |
| 82 | { |
| 83 | .pcu_index = PCU_ICP_PS2AP_INT, |
| 84 | .gic_index = ICP_PS2AP_INT, |
| 85 | .status_index = 53, |
| 86 | .wake_index = 2, |
| 87 | .int_name = "icp_ps_ap", |
| 88 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 89 | .wl_type = PM_WL_EVENT_ICP_PS2AP, |
| 90 | }, |
| 91 | { |
| 92 | .pcu_index = PCU_USB_POWERDWN_UP_INT, |
| 93 | .gic_index = USB_POWERDWN_UP_INT, |
| 94 | .status_index = 6, |
| 95 | .wake_index = 3, |
| 96 | .int_name = "usb_up", |
| 97 | .irq_type = IRQ_TYPE_EDGE_RISING, |
| 98 | .wl_type = PM_WL_EVENT_USB_POWERDWN_UP, |
| 99 | }, |
| 100 | { |
| 101 | .pcu_index = PCU_USB_POWERDWN_DOWN_INT, |
| 102 | .gic_index = USB_POWERDWN_DOWN_INT, |
| 103 | .status_index = 7, |
| 104 | .wake_index = 4, |
| 105 | .int_name = "usb_down", |
| 106 | .irq_type = IRQ_TYPE_EDGE_FALLING, |
| 107 | .wl_type = PM_WL_EVENT_USB_POWERDWN_DOWN, |
| 108 | }, |
| 109 | { |
| 110 | .pcu_index = PCU_HSIC_POWERDWN_UP_INT, |
| 111 | .gic_index = HSIC_POWERDWN_UP_INT, |
| 112 | .status_index = 8, |
| 113 | .wake_index = 5, |
| 114 | .int_name = "hsic_up", |
| 115 | .irq_type = IRQ_TYPE_EDGE_RISING, |
| 116 | .wl_type = PM_WL_EVENT_HSIC_POWERDWN_UP, |
| 117 | }, |
| 118 | { |
| 119 | .pcu_index = PCU_HSIC_POWERDWN_DOWN_INT, |
| 120 | .gic_index = HSIC_POWERDWN_DOWN_INT, |
| 121 | .status_index = 9, |
| 122 | .wake_index = 6, |
| 123 | .int_name = "hsic_down", |
| 124 | .irq_type = IRQ_TYPE_EDGE_FALLING, |
| 125 | .wl_type = PM_WL_EVENT_HSIC_POWERDWN_DOWN, |
| 126 | }, |
| 127 | { |
| 128 | .pcu_index = PCU_ICP_M02AP_INT, |
| 129 | .gic_index = ICP_M02AP_INT, |
| 130 | .status_index = 54, |
| 131 | .wake_index = 7, |
| 132 | .int_name = "icp_m0_ap", |
| 133 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 134 | .wl_type = PM_WL_EVENT_ICP_M02AP, |
| 135 | }, |
| 136 | { |
| 137 | .pcu_index = PCU_RTC_ALARM_INT, |
| 138 | .gic_index = RTC_ALARM_INT, |
| 139 | .status_index = 12, |
| 140 | .wake_index = 8, |
| 141 | .int_name = "rtc_alarm", |
| 142 | .irq_type = IRQ_TYPE_LEVEL_LOW, |
| 143 | .wl_type = PM_WL_EVENT_ALARM, |
| 144 | }, |
| 145 | { |
| 146 | .pcu_index = PCU_RTC_TIMER_INT, |
| 147 | .gic_index = RTC_TIMER_INT, |
| 148 | .status_index = 13, |
| 149 | .wake_index = 9, |
| 150 | .int_name = "rtc_timer", |
| 151 | .irq_type = IRQ_TYPE_LEVEL_LOW, |
| 152 | .wl_type = PM_WL_EVENT_RTC_TIMER, |
| 153 | }, |
| 154 | { |
| 155 | .pcu_index = PCU_KEYPAD_INT, |
| 156 | .gic_index = KEYPAD_INT, |
| 157 | .status_index = 14, |
| 158 | .wake_index = 10, |
| 159 | .int_name = "kpd", |
| 160 | .irq_type = IRQ_TYPE_EDGE_RISING, |
| 161 | .wl_type = PM_WL_EVENT_KEYPAD, |
| 162 | }, |
| 163 | { |
| 164 | .pcu_index = PCU_SD1_DATA1_INT, |
| 165 | .gic_index = SD1_DATA1_INT, |
| 166 | .status_index = 15, |
| 167 | .wake_index = 11, |
| 168 | .int_name = "sd1_d1", |
| 169 | .irq_type = IRQ_TYPE_LEVEL_LOW, |
| 170 | .wl_type = PM_WL_EVENT_SD1_DATA1, |
| 171 | }, |
| 172 | { |
| 173 | .pcu_index = PCU_EX0_INT, |
| 174 | .gic_index = EX0_INT, |
| 175 | .status_index = 30, |
| 176 | .wake_index = 14, |
| 177 | .int_name = "ext0", |
| 178 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 179 | .wl_type = PM_WL_EVENT_EXT0, |
| 180 | }, |
| 181 | { |
| 182 | .pcu_index = PCU_EX1_INT, |
| 183 | .gic_index = EX1_INT, |
| 184 | .status_index = 31, |
| 185 | .wake_index = 15, |
| 186 | .int_name = "ext1", |
| 187 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 188 | .wl_type = PM_WL_EVENT_EXT1, |
| 189 | }, |
| 190 | { |
| 191 | .pcu_index = PCU_EX2_INT, |
| 192 | .gic_index = EX2_INT, |
| 193 | .status_index = 32, |
| 194 | .wake_index = 16, |
| 195 | .int_name = "ext2", |
| 196 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 197 | .wl_type = PM_WL_EVENT_EXT2, |
| 198 | }, |
| 199 | { |
| 200 | .pcu_index = PCU_EX3_INT, |
| 201 | .gic_index = EX3_INT, |
| 202 | .status_index = 33, |
| 203 | .wake_index = 17, |
| 204 | .int_name = "ext3", |
| 205 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 206 | .wl_type = PM_WL_EVENT_EXT3, |
| 207 | }, |
| 208 | { |
| 209 | .pcu_index = PCU_EX4_INT, |
| 210 | .gic_index = EX4_INT, |
| 211 | .status_index = 34, |
| 212 | .wake_index = 18, |
| 213 | .int_name = "ext4", |
| 214 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 215 | .wl_type = PM_WL_EVENT_EXT4, |
| 216 | }, |
| 217 | { |
| 218 | .pcu_index = PCU_EX5_INT, |
| 219 | .gic_index = EX5_INT, |
| 220 | .status_index = 35, |
| 221 | .wake_index = 19, |
| 222 | .int_name = "ext5", |
| 223 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 224 | .wl_type = PM_WL_EVENT_EXT5, |
| 225 | }, |
| 226 | { |
| 227 | .pcu_index = PCU_EX6_INT, |
| 228 | .gic_index = EX6_INT, |
| 229 | .status_index = 36, |
| 230 | .wake_index = 20, |
| 231 | .int_name = "ext6", |
| 232 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 233 | .wl_type = PM_WL_EVENT_EXT6, |
| 234 | }, |
| 235 | { |
| 236 | .pcu_index = PCU_EX7_INT, |
| 237 | .gic_index = EX7_INT, |
| 238 | .status_index = 37, |
| 239 | .wake_index = 21, |
| 240 | .int_name = "ext7", |
| 241 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 242 | .wl_type = PM_WL_EVENT_EXT7, |
| 243 | }, |
| 244 | { |
| 245 | .pcu_index = PCU_EX8_INT, |
| 246 | .gic_index = EX8IN1_INT, |
| 247 | .status_index = 38, |
| 248 | .wake_index = 22, |
| 249 | .int_name = "ext8", |
| 250 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 251 | .wl_type = PM_WL_EVENT_EXT8, |
| 252 | }, |
| 253 | { |
| 254 | .pcu_index = PCU_EX9_INT, |
| 255 | .gic_index = EX8IN1_INT, |
| 256 | .status_index = 39, |
| 257 | .wake_index = 23, |
| 258 | .int_name = "ext9", |
| 259 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 260 | .wl_type = PM_WL_EVENT_EXT9, |
| 261 | }, |
| 262 | { |
| 263 | .pcu_index = PCU_EX10_INT, |
| 264 | .gic_index = EX8IN1_INT, |
| 265 | .status_index = 40, |
| 266 | .wake_index = 24, |
| 267 | .int_name = "ext10", |
| 268 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 269 | .wl_type = PM_WL_EVENT_EXT10, |
| 270 | }, |
| 271 | { |
| 272 | .pcu_index = PCU_EX11_INT, |
| 273 | .gic_index = EX8IN1_INT, |
| 274 | .status_index = 41, |
| 275 | .wake_index = 25, |
| 276 | .int_name = "ext11", |
| 277 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 278 | .wl_type = PM_WL_EVENT_EXT11, |
| 279 | }, |
| 280 | { |
| 281 | .pcu_index = PCU_EX12_INT, |
| 282 | .gic_index = EX8IN1_INT, |
| 283 | .status_index = 42, |
| 284 | .wake_index = 26, |
| 285 | .int_name = "ext12", |
| 286 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 287 | .wl_type = PM_WL_EVENT_EXT12, |
| 288 | }, |
| 289 | { |
| 290 | .pcu_index = PCU_EX13_INT, |
| 291 | .gic_index = EX8IN1_INT, |
| 292 | .status_index = 43, |
| 293 | .wake_index = 27, |
| 294 | .int_name = "ext13", |
| 295 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 296 | .wl_type = PM_WL_EVENT_EXT13, |
| 297 | }, |
| 298 | { |
| 299 | .pcu_index = PCU_EX14_INT, |
| 300 | .gic_index = EX8IN1_INT, |
| 301 | .status_index = 44, |
| 302 | .wake_index = 28, |
| 303 | .int_name = "ext14", |
| 304 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 305 | .wl_type = PM_WL_EVENT_EXT14, |
| 306 | }, |
| 307 | { |
| 308 | .pcu_index = PCU_EX15_INT, |
| 309 | .gic_index = EX8IN1_INT, |
| 310 | .status_index = 45, |
| 311 | .wake_index = 29, |
| 312 | .int_name = "ext15", |
| 313 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 314 | .wl_type = PM_WL_EVENT_EXT15, |
| 315 | }, |
| 316 | { |
| 317 | .pcu_index = PCU_SD0_DATA1_INT, |
| 318 | .gic_index = SD0_DATA1_INT, |
| 319 | .status_index = 2, |
| 320 | .wake_index = 30, |
| 321 | .int_name = "sd0_d1", |
| 322 | .irq_type = IRQ_TYPE_LEVEL_LOW, |
| 323 | .wl_type = PM_WL_EVENT_SD0_DATA1, |
| 324 | }, |
| 325 | { |
| 326 | .pcu_index = PCU_ICP_PHY2AP_INT, |
| 327 | .gic_index = ICP_PHY2AP_INT, |
| 328 | .status_index = 55, |
| 329 | .wake_index = 31, |
| 330 | .int_name = "icp_phy_ap", |
| 331 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 332 | .wl_type = PM_WL_EVENT_ICP_PHY2AP, |
| 333 | }, |
| 334 | { |
| 335 | .pcu_index = PCU_GMACPHY_WAKE_INT, |
| 336 | .gic_index = GMACPHY_WAKE_INT, |
| 337 | .status_index = 60, |
| 338 | .wake_index = 0xff, |
| 339 | .int_name = "gmacphy_wake", |
| 340 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 341 | .wl_type = 0xff, |
| 342 | }, |
| 343 | { |
| 344 | .pcu_index = PCU_UART0_RXD_INT, |
| 345 | .gic_index = UART0_RXD_INT, |
| 346 | .status_index = 59, |
| 347 | .wake_index = 42, |
| 348 | .int_name = "uart0_rxd", |
| 349 | .irq_type = IRQ_TYPE_EDGE_FALLING, |
| 350 | .wl_type = 0xff, |
| 351 | |
| 352 | }, |
| 353 | { |
| 354 | .pcu_index = PCU_GMAC_INT, |
| 355 | .gic_index = GMAC_INT, |
| 356 | .status_index = 16, |
| 357 | .wake_index = 0xff, |
| 358 | .int_name = "gmac", |
| 359 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 360 | .wl_type = 0xff, |
| 361 | }, |
| 362 | { |
| 363 | .pcu_index = PCU_GMACPHY_INT, |
| 364 | .gic_index = GMACPHY_INT, |
| 365 | .status_index = 61, |
| 366 | .wake_index = 0xff, |
| 367 | .int_name = "gmacphy", |
| 368 | .irq_type = IRQ_TYPE_LEVEL_HIGH, |
| 369 | .wl_type = 0xff, |
| 370 | }, |
| 371 | }; |
| 372 | |
| 373 | static int zx_pcu_get_irqchip_state(struct irq_data *data, |
| 374 | enum irqchip_irq_state which, bool *val) |
| 375 | { |
| 376 | data = data->parent_data; |
| 377 | |
| 378 | if (data->chip->irq_get_irqchip_state) |
| 379 | return data->chip->irq_get_irqchip_state(data, which, val); |
| 380 | |
| 381 | return -ENOSYS; |
| 382 | } |
| 383 | |
| 384 | static int zx_pcu_set_irqchip_state(struct irq_data *data, |
| 385 | enum irqchip_irq_state which, bool val) |
| 386 | { |
| 387 | data = data->parent_data; |
| 388 | |
| 389 | if (data->chip->irq_set_irqchip_state) |
| 390 | return data->chip->irq_set_irqchip_state(data, which, val); |
| 391 | |
| 392 | return -ENOSYS; |
| 393 | } |
| 394 | |
| 395 | static int zx_pcu_nmi_setup(struct irq_data *data) |
| 396 | { |
| 397 | data = data->parent_data; |
| 398 | |
| 399 | if (data->chip->irq_nmi_setup) |
| 400 | return data->chip->irq_nmi_setup(data); |
| 401 | |
| 402 | return -ENOSYS; |
| 403 | } |
| 404 | |
| 405 | static void zx_pcu_nmi_teardown(struct irq_data *data) |
| 406 | { |
| 407 | data = data->parent_data; |
| 408 | |
| 409 | if (data->chip->irq_nmi_teardown) |
| 410 | data->chip->irq_nmi_teardown(data); |
| 411 | } |
| 412 | |
| 413 | static int zx_pcu_set_wake(struct irq_data *data, unsigned int on) |
| 414 | { |
| 415 | pcu_set_irq_wake(data->hwirq, on); |
| 416 | |
| 417 | /* pr_info("irq:%d, onoff:%d", data->hwirq, on);*/ |
| 418 | |
| 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | static void zx_pcu_eoi_irq(struct irq_data *data) |
| 423 | { |
| 424 | pcu_clr_irq_pending(data->hwirq); |
| 425 | |
| 426 | irq_chip_eoi_parent(data); |
| 427 | } |
| 428 | |
| 429 | static int zx_pcu_set_type(struct irq_data *data, unsigned int type) |
| 430 | { |
| 431 | unsigned int new_type = type; |
| 432 | |
| 433 | if(!pcu_set_irq_type(data->hwirq, type)) |
| 434 | new_type = IRQ_TYPE_LEVEL_HIGH; |
| 435 | |
| 436 | return irq_chip_set_type_parent(data, new_type); |
| 437 | } |
| 438 | |
| 439 | static int zx_pcu_set_affinity(struct irq_data *data, |
| 440 | const struct cpumask *dest, bool force) |
| 441 | { |
| 442 | /* |
| 443 | if (data->hwirq == IRQ_ZX298501_AP_TIMER1) |
| 444 | return irq_chip_set_affinity_parent(data, cpumask_of(0), force); // ??? |
| 445 | else |
| 446 | */ return irq_chip_set_affinity_parent(data, dest, force); |
| 447 | } |
| 448 | |
| 449 | static struct irq_chip zx_pcu_chip = { |
| 450 | .name = "PCU", |
| 451 | .irq_eoi = zx_pcu_eoi_irq, |
| 452 | .irq_mask = irq_chip_mask_parent, |
| 453 | .irq_unmask = irq_chip_unmask_parent, |
| 454 | .irq_set_wake = zx_pcu_set_wake, |
| 455 | .irq_set_type = zx_pcu_set_type, |
| 456 | |
| 457 | .irq_set_affinity = zx_pcu_set_affinity, |
| 458 | .irq_get_irqchip_state = zx_pcu_get_irqchip_state, |
| 459 | .irq_set_irqchip_state = zx_pcu_set_irqchip_state, |
| 460 | .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, |
| 461 | .irq_nmi_setup = zx_pcu_nmi_setup, |
| 462 | .irq_nmi_teardown = zx_pcu_nmi_teardown, |
| 463 | .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED, |
| 464 | }; |
| 465 | |
| 466 | static int zx_pcu_domain_translate(struct irq_domain *d, |
| 467 | struct irq_fwspec *fwspec, |
| 468 | unsigned long *hwirq, |
| 469 | unsigned int *type) |
| 470 | { |
| 471 | if (is_of_node(fwspec->fwnode)) { |
| 472 | if (fwspec->param_count != 3) |
| 473 | return -EINVAL; |
| 474 | |
| 475 | /* No PPI should point to this domain */ |
| 476 | if (fwspec->param[0] != 0) |
| 477 | return -EINVAL; |
| 478 | |
| 479 | *hwirq = fwspec->param[1]; |
| 480 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | return -EINVAL; |
| 485 | } |
| 486 | |
| 487 | static int zx_pcu_domain_alloc(struct irq_domain *domain, |
| 488 | unsigned int virq, |
| 489 | unsigned int nr_irqs, void *data) |
| 490 | { |
| 491 | struct irq_fwspec *fwspec = data; |
| 492 | struct irq_fwspec parent_fwspec; |
| 493 | struct zx_pcu_dev *pcu = domain->host_data; |
| 494 | irq_hw_number_t hwirq; |
| 495 | unsigned int i; |
| 496 | |
| 497 | if (fwspec->param_count != 3) |
| 498 | return -EINVAL; /* Not GIC compliant */ |
| 499 | if (fwspec->param[0] != GIC_SPI) |
| 500 | return -EINVAL; /* No PPI should point to this domain */ |
| 501 | |
| 502 | hwirq = fwspec->param[1]; |
| 503 | if (hwirq >= ZX_IRQ_NUM) |
| 504 | return -EINVAL; |
| 505 | |
| 506 | for (i = 0; i < nr_irqs; i++) { |
| 507 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, |
| 508 | &zx_pcu_chip, |
| 509 | (void __force *)pcu->top_reg_base); |
| 510 | } |
| 511 | |
| 512 | parent_fwspec = *fwspec; |
| 513 | parent_fwspec.fwnode = domain->parent->fwnode; |
| 514 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, |
| 515 | &parent_fwspec); |
| 516 | } |
| 517 | |
| 518 | static const struct irq_domain_ops zx_pcu_domain_ops = { |
| 519 | .translate = zx_pcu_domain_translate, |
| 520 | .alloc = zx_pcu_domain_alloc, |
| 521 | .free = irq_domain_free_irqs_common, |
| 522 | }; |
| 523 | |
| 524 | static int __init zx_pcu_init(struct device_node *node, |
| 525 | struct device_node *parent) |
| 526 | { |
| 527 | struct irq_domain *parent_domain, *domain; |
| 528 | struct zx_pcu_dev *pcu; |
| 529 | |
| 530 | if (!parent) { |
| 531 | pr_err("%pOF: no parent found\n", node); |
| 532 | return -ENODEV; |
| 533 | } |
| 534 | |
| 535 | parent_domain = irq_find_host(parent); |
| 536 | if (!parent_domain) { |
| 537 | pr_err("%pOF: unable to obtain parent domain\n", node); |
| 538 | return -ENXIO; |
| 539 | } |
| 540 | |
| 541 | pcu = &pcu_dev; |
| 542 | pcu->np = node; |
| 543 | pcu->top_reg_base = of_iomap(node, 0); |
| 544 | WARN(!pcu->top_reg_base, "unable to map top pcu registers\n"); |
| 545 | |
| 546 | pcu->int_info = zx297520v3_pcu_int_info; |
| 547 | pcu->int_count = ARRAY_SIZE(zx297520v3_pcu_int_info); |
| 548 | |
| 549 | pcu_init(); |
| 550 | |
| 551 | domain = irq_domain_add_hierarchy(parent_domain, 0, ZX_IRQ_NUM, |
| 552 | node, &zx_pcu_domain_ops, |
| 553 | pcu); |
| 554 | if (!domain) { |
| 555 | pr_err("%pOF: failed to allocated domain\n", node); |
| 556 | return -ENOMEM; |
| 557 | } |
| 558 | |
| 559 | // set_smp_cross_call(); |
| 560 | pm_pcu_init(); |
| 561 | |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | IRQCHIP_DECLARE(zx297520v3_pcu, "zte,zx297520v3-pcu", zx_pcu_init); |
| 566 | |
| 567 | /* pcu debug */ |
| 568 | #ifdef CONFIG_PM |
| 569 | #define PCU_TOP (pcu_dev.top_reg_base) |
| 570 | |
| 571 | #define ARM_AP_CONFIG_REG (PCU_TOP + 0x0) |
| 572 | #define ARM_AP_SLEEP_TIME_REG (PCU_TOP + 4*0x3C) |
| 573 | #define AP_INT_WAKE_DIS_REG (PCU_TOP + 4*0xD) |
| 574 | #define CORE_SWITCH_CONFIG_REG (PCU_TOP + 4*0x2b) |
| 575 | |
| 576 | #define M0_INT_WAKE_DIS_REG (PCU_TOP + 4*0xE) |
| 577 | #define PCU_INT_READOUT_REG1 (PCU_TOP + 4*0x1EB) |
| 578 | #define PCU_INT_READOUT_REG2 (PCU_TOP + 4*0x1EC) |
| 579 | #define PCU_INT_READOUT_REG3 (PCU_TOP + 4*0x1ED) |
| 580 | |
| 581 | |
| 582 | /*ARM_AP_CONFIG_REG*/ |
| 583 | #define PCU_SLEEP_MODE (1U << 0) |
| 584 | #define PCU_POWEROFF_MODE (1U << 1) |
| 585 | #define PCU_L2_CLK_GATE (1U << 2) /*1-can turn off*/ |
| 586 | #define PCU_SLEEP_2M0 (1U << 3) |
| 587 | #define PCU_SLEEP_DONE_BYPASS (1U << 4) |
| 588 | #define PCU_SW_CONFIG_MASK (1U << 5) /* ????? */ |
| 589 | |
| 590 | #define PCU_MODE_MASK (0x3U << 0) |
| 591 | |
| 592 | /*ARM_AP_SLEEP_TIME_REG*/ |
| 593 | #define PCU_AP_SLEEP_TIME_DIS (1U << 31) |
| 594 | |
| 595 | |
| 596 | |
| 597 | /* low power function */ |
| 598 | extern unsigned int pm_get_wakesource(void); |
| 599 | |
| 600 | /** |
| 601 | * clear pcu sleep mode. |
| 602 | * |
| 603 | */ |
| 604 | void pm_clear_pcu(void) |
| 605 | { |
| 606 | zx_clr_reg(ARM_AP_CONFIG_REG, PCU_MODE_MASK); |
| 607 | } |
| 608 | |
| 609 | void pm_pcu_init(void) |
| 610 | { |
| 611 | zx_clr_reg(ARM_AP_CONFIG_REG, PCU_MODE_MASK); |
| 612 | zx_set_reg(ARM_AP_CONFIG_REG, PCU_L2_CLK_GATE); |
| 613 | zx_write_reg(AP_INT_WAKE_DIS_REG, ~(pm_get_wakesource())); |
| 614 | } |
| 615 | |
| 616 | void zx_apmgclken_set(unsigned en) |
| 617 | { |
| 618 | unsigned tmp; |
| 619 | if(en){ |
| 620 | //set ps_clk_switch=1 |
| 621 | tmp = zx_read_reg(CORE_SWITCH_CONFIG_REG); |
| 622 | tmp |= (0x1<<2); |
| 623 | zx_write_reg(CORE_SWITCH_CONFIG_REG, tmp); |
| 624 | } else{ |
| 625 | //set ps_clk_switch=0 |
| 626 | tmp = zx_read_reg(CORE_SWITCH_CONFIG_REG); |
| 627 | tmp &= ~(0x1<<2); |
| 628 | zx_write_reg(CORE_SWITCH_CONFIG_REG, tmp); |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | |
| 633 | /** |
| 634 | * config pcu before poweroff |
| 635 | * |
| 636 | */ |
| 637 | void pm_set_pcu_poweroff(u32 sleep_time) |
| 638 | { |
| 639 | zx_set_reg(ARM_AP_CONFIG_REG, PCU_POWEROFF_MODE); |
| 640 | zx_write_reg(ARM_AP_SLEEP_TIME_REG, sleep_time); |
| 641 | } |
| 642 | EXPORT_SYMBOL(pm_set_pcu_poweroff); |
| 643 | |
| 644 | |
| 645 | /** |
| 646 | * config pcu before sleep |
| 647 | * |
| 648 | */ |
| 649 | void pm_set_pcu_sleep(u32 sleep_time) |
| 650 | { |
| 651 | zx_set_reg(ARM_AP_CONFIG_REG, PCU_SLEEP_MODE); |
| 652 | zx_write_reg(ARM_AP_SLEEP_TIME_REG, sleep_time); |
| 653 | } |
| 654 | |
| 655 | /** |
| 656 | * get wakeup setting. |
| 657 | * |
| 658 | */ |
| 659 | unsigned int pcu_get_wakeup_setting(void) |
| 660 | { |
| 661 | return zx_read_reg(AP_INT_WAKE_DIS_REG); |
| 662 | } |
| 663 | /** |
| 664 | * set wakeup enable by gic. |
| 665 | * |
| 666 | * |
| 667 | */ |
| 668 | unsigned int gic_wake_enable[3]= |
| 669 | { |
| 670 | (1<<ICP_PS2AP_INT) |(1<<ICP_M02AP_INT) | (1<<AP_TIMER1_INT) | (1<<EX8IN1_INT), |
| 671 | 0, |
| 672 | 0 |
| 673 | }; |
| 674 | |
| 675 | extern void show_icp_state(T_RpMsg_CoreID actorID); |
| 676 | void pm_get_wake_cause(void) |
| 677 | { |
| 678 | unsigned int int_status[2]; |
| 679 | int i = 0; |
| 680 | int index_found = 0xff; |
| 681 | unsigned int pcu_wake_setting[2]; |
| 682 | |
| 683 | /* when wake up, the level is high&the value is 0*/ |
| 684 | int_status[0] = zx_read_reg(PCU_INT_READOUT_REG1); |
| 685 | int_status[1] = zx_read_reg(PCU_INT_READOUT_REG2); |
| 686 | |
| 687 | pcu_wake_setting[0] = zx_read_reg(AP_INT_WAKE_DIS_REG); |
| 688 | pcu_wake_setting[1] = zx_read_reg(M0_INT_WAKE_DIS_REG); |
| 689 | |
| 690 | for(i=0; i<ARRAY_SIZE(zx297520v3_pcu_int_info); i++) |
| 691 | { |
| 692 | if (zx297520v3_pcu_int_info[i].wake_index == 0xff) |
| 693 | continue; |
| 694 | |
| 695 | if(pcu_wake_setting[0]&BIT(zx297520v3_pcu_int_info[i].wake_index)) |
| 696 | continue; |
| 697 | |
| 698 | if(int_status[zx297520v3_pcu_int_info[i].status_index/32]&(1<<(zx297520v3_pcu_int_info[i].status_index%32))) |
| 699 | continue; |
| 700 | |
| 701 | index_found = i; |
| 702 | break; |
| 703 | } |
| 704 | |
| 705 | if(index_found != 0xff) |
| 706 | { |
| 707 | pm_ram_log(" wake: %d [%s]\n", zx297520v3_pcu_int_info[index_found].gic_index, zx297520v3_pcu_int_info[index_found].int_name); |
xf.li | 3dd5374 | 2024-09-27 00:06:23 -0700 | [diff] [blame] | 708 | |
| 709 | if(zx297520v3_pcu_int_info[index_found].gic_index ==ICP_PS2AP_INT) { |
| 710 | show_icp_state(CORE_PS0); |
| 711 | } |
| 712 | pm_ram_log(" pcu int status:0x%x 0x%x\n",int_status[0], int_status[1]); |
| 713 | |
| 714 | pm_wl_set_event(pcu_get_wl_index_by_gic(zx297520v3_pcu_int_info[index_found].gic_index)); |
| 715 | } |
| 716 | else |
| 717 | { |
| 718 | pm_ram_log(" wake abnormal\n"); |
| 719 | pm_ram_log(" pcu int status:0x%x 0x%x\n",int_status[0], int_status[1]); |
| 720 | } |
| 721 | } |
| 722 | |
| 723 | static struct wakeup_source *zx_main_ws; |
| 724 | static int zx_pcu_pm_callback(struct notifier_block *nb, |
| 725 | unsigned long action, void *ptr) |
| 726 | { |
| 727 | switch (action) { |
| 728 | |
| 729 | case PM_POST_SUSPEND: |
| 730 | __pm_wakeup_event(zx_main_ws, 1000); |
| 731 | break; |
| 732 | |
| 733 | default: |
| 734 | return NOTIFY_DONE; |
| 735 | } |
| 736 | |
| 737 | return NOTIFY_OK; |
| 738 | } |
| 739 | |
| 740 | static int pcu_pm_suspend(void) |
| 741 | { |
| 742 | int ret = 0; |
| 743 | |
| 744 | return ret; |
| 745 | } |
| 746 | |
| 747 | static void pcu_pm_resume(void) |
| 748 | { |
| 749 | // pcu_get_wake_cause(); |
| 750 | } |
| 751 | |
| 752 | static struct syscore_ops pcu_pm_syscore_ops = { |
| 753 | .suspend = pcu_pm_suspend, |
| 754 | .resume = pcu_pm_resume, |
| 755 | }; |
| 756 | |
| 757 | static int pcu_pm_init(void) |
| 758 | { |
| 759 | zx_main_ws = wakeup_source_register(NULL, "zx_main"); |
| 760 | if (!zx_main_ws) |
| 761 | return -ENOMEM; |
| 762 | |
| 763 | pm_notifier(zx_pcu_pm_callback, 0); |
| 764 | |
| 765 | register_syscore_ops(&pcu_pm_syscore_ops); |
| 766 | return 0; |
| 767 | } |
| 768 | core_initcall(pcu_pm_init); |
| 769 | #endif |
| 770 | |
| 771 | /* -------------------------------------------------------------------- |
| 772 | * extint_8in1 |
| 773 | * -------------------------------------------------------------------- */ |
| 774 | |
| 775 | struct ext8in1_info { |
| 776 | struct irq_domain *domain; |
| 777 | struct regmap *regmap; |
| 778 | int parent_irq; |
| 779 | |
| 780 | }; |
| 781 | |
| 782 | struct ext8in1_info ext8in1_dev = {0}; |
| 783 | |
| 784 | /* |
| 785 | * return external interrupt number from ex8-ex15, |
| 786 | * return value is 0-7 |
| 787 | */ |
| 788 | static unsigned int pcu_get_8in1_int_source(void) |
| 789 | { |
| 790 | unsigned int vector_8in1 = 0; |
| 791 | |
| 792 | vector_8in1 = zx_read_reg(pcu_dev.top_reg_base+0x12C); |
| 793 | |
| 794 | return (vector_8in1&0x7); |
| 795 | } |
| 796 | |
| 797 | |
| 798 | /*external int 8-15 need extra clear*/ |
| 799 | static void pcu_int_clear_8in1(unsigned int pcu_index) |
| 800 | { |
| 801 | unsigned int vector=0; |
| 802 | |
| 803 | if ( (pcu_index >= PCU_EX8_INT)&&(pcu_index <= PCU_EX15_INT) ) |
| 804 | { |
| 805 | /* |
| 806 | *in 7510 platform, 8in1 interrupt would be used by different cores. |
| 807 | *when any core installs a new 8in1 interrupt, another core may be |
| 808 | * responding another 8in1 interrupt, so 8in1 interrupt shouldn't be |
| 809 | *cleared. in this case, nothing to be done. but a new problem comes, |
| 810 | * the core install new 8in1 interrupt will receive a fake interrupt. |
| 811 | */ |
| 812 | vector = pcu_get_8in1_int_source(); |
| 813 | if (pcu_index != (vector + PCU_EX8_INT) ) |
| 814 | return; |
| 815 | |
| 816 | PCU_LOCK |
| 817 | zx_write_reg(pcu_dev.top_reg_base+0x128, 0x1); |
| 818 | PCU_UNLOCK |
| 819 | |
| 820 | pcu_int_clear(pcu_index); |
| 821 | } |
| 822 | } |
| 823 | |
| 824 | static void ext8in1_irq_lock(struct irq_data *data){} |
| 825 | static void ext8in1_irq_sync_unlock(struct irq_data *data){} |
| 826 | static void ext8in1_irq_mask(struct irq_data *data){} |
| 827 | static void ext8in1_irq_unmask(struct irq_data *data){} |
| 828 | static int ext8in1_irq_set_wake(struct irq_data *data, unsigned int on) |
| 829 | { |
| 830 | if (!data) |
| 831 | return -EINVAL; |
| 832 | |
| 833 | pcu_set_irq_wake_by_pcu(data->hwirq + PCU_EX8_INT, on); |
| 834 | |
| 835 | return 0; |
| 836 | } |
| 837 | |
| 838 | static int ext8in1_irq_set_type(struct irq_data *data, unsigned int type) |
| 839 | { |
| 840 | if (!data) |
| 841 | return -EINVAL; |
| 842 | |
| 843 | pcu_int_set_type(data->hwirq + PCU_EX8_INT, type); |
| 844 | |
| 845 | pcu_int_clear_8in1(data->hwirq + PCU_EX8_INT); |
| 846 | |
| 847 | return 0; |
| 848 | } |
| 849 | |
| 850 | static struct irq_chip ext8in1_irq_chip = |
| 851 | { |
| 852 | .name = "ext8in1", |
| 853 | |
| 854 | .irq_set_wake = ext8in1_irq_set_wake, |
| 855 | .irq_set_type = ext8in1_irq_set_type, |
| 856 | .irq_mask = ext8in1_irq_mask, |
| 857 | .irq_unmask = ext8in1_irq_unmask, |
| 858 | .irq_bus_lock = ext8in1_irq_lock, |
| 859 | .irq_bus_sync_unlock = ext8in1_irq_sync_unlock, |
| 860 | }; |
| 861 | |
| 862 | static void ext8in1_handle_irq(struct irq_desc *desc) |
| 863 | { |
| 864 | struct ext8in1_info *data = irq_desc_get_handler_data(desc); |
| 865 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 866 | int virq; |
| 867 | int hwirq, new_hwirq; |
| 868 | |
| 869 | chained_irq_enter(chip, desc); |
| 870 | |
| 871 | hwirq = pcu_get_8in1_int_source(); |
| 872 | |
| 873 | while(1) { |
| 874 | pcu_int_clear_8in1(hwirq + PCU_EX8_INT); |
| 875 | |
| 876 | virq = irq_find_mapping(data->domain, hwirq); |
| 877 | if (virq > 0) |
| 878 | generic_handle_irq(virq); |
| 879 | |
| 880 | new_hwirq = pcu_get_8in1_int_source(); |
| 881 | if (hwirq == new_hwirq) |
| 882 | break; |
| 883 | else |
| 884 | hwirq = new_hwirq; |
| 885 | } |
| 886 | |
| 887 | chained_irq_exit(chip, desc); |
| 888 | } |
| 889 | |
| 890 | extern void mask_irq(struct irq_desc *desc); |
| 891 | extern void unmask_irq(struct irq_desc *desc); |
| 892 | static int ext8in1_irq_resume(struct device *dev) |
| 893 | { |
| 894 | unmask_irq(irq_to_desc(ext8in1_dev.parent_irq)); |
| 895 | |
| 896 | return 0; |
| 897 | } |
| 898 | |
| 899 | static int ext8in1_irq_suspend(struct device *dev) |
| 900 | { |
| 901 | mask_irq(irq_to_desc(ext8in1_dev.parent_irq)); |
| 902 | |
| 903 | return 0; |
| 904 | } |
| 905 | |
| 906 | static int zx_ext8in1_probe(struct platform_device *pdev) |
| 907 | { |
| 908 | struct device_node *np = pdev->dev.of_node; |
| 909 | struct device_node *parent_np; |
| 910 | struct regmap *regmap; |
| 911 | struct ext8in1_info *data = &ext8in1_dev; |
| 912 | int i; |
| 913 | |
| 914 | parent_np = of_parse_phandle(pdev->dev.of_node, "parent-syscon", 0); |
| 915 | if (!parent_np) { |
| 916 | dev_err(&pdev->dev, "Can't get parent-syscon\n"); |
| 917 | return -EINVAL; |
| 918 | } |
| 919 | |
| 920 | regmap = syscon_node_to_regmap(parent_np); |
| 921 | if (IS_ERR(regmap)) { |
| 922 | of_node_put(parent_np); |
| 923 | return PTR_ERR(regmap); |
| 924 | } |
| 925 | data->regmap = regmap; |
| 926 | |
| 927 | data->parent_irq = platform_get_irq(pdev, 0); |
| 928 | if (data->parent_irq <= 0) |
| 929 | return -EPROBE_DEFER; |
| 930 | |
| 931 | data->domain = irq_domain_add_linear(np, 8, &irq_domain_simple_ops, NULL); |
| 932 | if (!data->domain) |
| 933 | return -ENODEV; |
| 934 | |
| 935 | for (i = EX8_INT; i <= EX15_INT; i++) { |
| 936 | int virq = irq_create_mapping(data->domain, i); |
| 937 | |
| 938 | irq_set_chip_and_handler(virq, &ext8in1_irq_chip, |
| 939 | handle_simple_irq); |
| 940 | irq_set_chip_data(virq, data); |
| 941 | } |
| 942 | |
| 943 | irq_set_chained_handler_and_data(data->parent_irq, |
| 944 | ext8in1_handle_irq, data); |
| 945 | enable_irq_wake(data->parent_irq); |
| 946 | |
| 947 | pr_info("zx_ext8in1 init OK. \n"); |
| 948 | |
| 949 | return 0; |
| 950 | } |
| 951 | |
| 952 | static const struct of_device_id zx_ext8in1_match[] = { |
| 953 | { .compatible = "zte,zx297520v3-ext8in1" }, |
| 954 | { } |
| 955 | }; |
| 956 | |
| 957 | static const struct dev_pm_ops ext8in1_irq_pm_ops = { |
| 958 | .resume = ext8in1_irq_resume, |
| 959 | .suspend = ext8in1_irq_suspend, |
| 960 | }; |
| 961 | |
| 962 | static struct platform_driver zx_ext8in1_driver = { |
| 963 | .probe = zx_ext8in1_probe, |
| 964 | .driver = { |
| 965 | .name = "zx_ext8in1_drv", |
| 966 | .of_match_table = zx_ext8in1_match, |
| 967 | .pm = &ext8in1_irq_pm_ops, |
| 968 | }, |
| 969 | }; |
| 970 | |
| 971 | static int __init zx_ext8in1_driver_init(void) |
| 972 | { |
| 973 | return platform_driver_register(&zx_ext8in1_driver); |
| 974 | } |
| 975 | core_initcall(zx_ext8in1_driver_init); |
| 976 | |