Gitiles
Code Review Sign In
192.168.1.100 / T106_eSDK / a06dd22e952cce4dcc1e759cbad3051c1ac06162 / . / upstream / linux-5.10 / sound / soc / codecs / es8311.c
blob: fef445f938a94b875333989af093637c1e0f2471 [file] [log] [blame]
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * es8311.c -- ES8311/ES8312 ALSA SoC Audio Codec
4 *
5 * Copyright (C) 2018 Everest Semiconductor Co., Ltd
6 *
7 * Authors: David Yang(yangxiaohua@everest-semi.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/clk.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/i2c.h>
19#include <linux/regmap.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/tlv.h>
24#include <sound/soc.h>
25
26#include <linux/of.h>
27#include <linux/of_gpio.h>
28#include <linux/clk-provider.h>
29
30#include "es8311.h"
31#ifndef CONFIG_OF
32#define CONFIG_OF
33#endif
34
35/* component private data */
36
37struct es8311_private {
38 struct snd_soc_component *component;
39 struct regmap *regmap;
40 struct device *dev;
41
42 struct clk *mclk;
43 unsigned int mclk_rate;
44 int mastermode;
45 bool sclkinv;
46 bool mclkinv;
47 bool dmic_enable;
48 unsigned int mclk_src;
49 enum snd_soc_bias_level bias_level;
50 //add new
51 struct pinctrl *pctrl;
52 struct pinctrl_state *state0;
53 struct clk *clk;
54
55
56};
57
58#if 0
59struct aic31xx_priv {
60 struct snd_soc_component *component;
61 u8 i2c_regs_status;
62 struct device *dev;
63 struct regmap *regmap;
64 enum aic31xx_type codec_type;
65 struct gpio_desc *gpio_reset;
66 int micbias_vg;
67 struct aic31xx_pdata pdata;
68 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
69 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
70 struct snd_soc_jack *jack;
71 unsigned int sysclk;
72 u8 p_div;
73 int rate_div_line;
74 bool master_dapm_route_applied;
75 int irq;
76 u8 ocmv; /* output common-mode voltage */
77};
78#endif
79
80struct es8311_private *es8311_data;
81struct snd_soc_component *es8311_component;
82
83static bool es8311_volatile_register(struct device *dev,
84 unsigned int reg)
85{
86 //printk("Enter into %s()\n", __func__);
87
88 if ((reg <= 0xff))
89 return true;
90 else
91 return false;
92 }
93
94static bool es8311_readable_register(struct device *dev,
95 unsigned int reg)
96{
97 //printk("Enter into %s()\n", __func__);
98
99 if ((reg <= 0xff))
100 return true;
101 else
102 return false;
103 }
104
105static bool es8311_writable_register(struct device *dev,
106 unsigned int reg)
107{
108 //printk("Enter into %s()\n", __func__);
109
110 if ((reg <= 0xff))
111 return true;
112 else
113 return false;
114}
115
116static const DECLARE_TLV_DB_SCALE(vdac_tlv, -9550, 50, 1);
117static const DECLARE_TLV_DB_SCALE(vadc_tlv, -9550, 50, 1);
118static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 300, 1);
119static const DECLARE_TLV_DB_SCALE(adc_scale_tlv, 0, 600, 0);
120static const DECLARE_TLV_DB_SCALE(alc_winsize_tlv, 0, 25, 0);
121static const DECLARE_TLV_DB_SCALE(alc_maxlevel_tlv, -3600, 200, 0);
122static const DECLARE_TLV_DB_SCALE(alc_minlevel_tlv, -3600, 200, 0);
123static const DECLARE_TLV_DB_SCALE(alc_noisegate_tlv, -9600, 600, 0);
124static const DECLARE_TLV_DB_SCALE(alc_noisegate_winsize_tlv, 2048, 2048, 0);
125static const DECLARE_TLV_DB_SCALE(alc_automute_gain_tlv, 0, -400, 0);
126static const DECLARE_TLV_DB_SCALE(adc_ramprate_tlv, 0, 25, 0);
127
128static const char * const dmic_type_txt[] = {
129 "dmic at high level",
130 "dmic at low level"
131};
132static const struct soc_enum dmic_type =
133SOC_ENUM_SINGLE(ES8311_ADC_REG15, 0, 2, dmic_type_txt);
134
135static const char * const automute_type_txt[] = {
136 "automute disabled",
137 "automute enable"
138};
139static const struct soc_enum alc_automute_type =
140SOC_ENUM_SINGLE(ES8311_ADC_REG18, 6, 2, automute_type_txt);
141
142static const char * const dacdsm_mute_type_txt[] = {
143 "mute to 8",
144 "mute to 7/9"
145};
146static const struct soc_enum dacdsm_mute_type =
147SOC_ENUM_SINGLE(ES8311_DAC_REG31, 7, 2, dacdsm_mute_type_txt);
148
149static const char * const aec_type_txt[] = {
150 "adc left, adc right",
151 "adc left, null right",
152 "null left, adc right",
153 "null left, null right",
154 "dac left, adc right",
155 "adc left, dac right",
156 "dac left, dac right",
157 "N/A"
158};
159static const struct soc_enum aec_type =
160SOC_ENUM_SINGLE(ES8311_GPIO_REG44, 4, 7, aec_type_txt);
161
162static const char * const adc2dac_sel_txt[] = {
163 "disable",
164 "adc data to dac",
165};
166static const struct soc_enum adc2dac_sel =
167SOC_ENUM_SINGLE(ES8311_GPIO_REG44, 7, 2, adc2dac_sel_txt);
168
169static const char * const mclk_sel_txt[] = {
170 "from mclk pin",
171 "from bclk",
172};
173static const struct soc_enum mclk_src =
174SOC_ENUM_SINGLE(ES8311_CLK_MANAGER_REG01, 7, 2, mclk_sel_txt);
175
176/*
177 * es8311 Controls
178 */
179static const struct snd_kcontrol_new es8311_snd_controls[] = {
180 SOC_SINGLE_TLV("MIC PGA GAIN", ES8311_SYSTEM_REG14,
181 0, 10, 0, mic_pga_tlv),
182 SOC_SINGLE_TLV("ADC SCALE", ES8311_ADC_REG16,
183 0, 7, 0, adc_scale_tlv),
184 SOC_ENUM("DMIC TYPE", dmic_type),
185 SOC_SINGLE_TLV("ADC RAMP RATE", ES8311_ADC_REG15,
186 4, 15, 0, adc_ramprate_tlv),
187 SOC_SINGLE("ADC SDP MUTE", ES8311_SDPOUT_REG0A, 6, 1, 0),
188 SOC_SINGLE("ADC INVERTED", ES8311_ADC_REG16, 4, 1, 0),
189 SOC_SINGLE("ADC SYNC", ES8311_ADC_REG16, 5, 1, 1),
190 SOC_SINGLE("ADC RAM CLR", ES8311_ADC_REG16, 3, 1, 0),
191 SOC_SINGLE_TLV("ADC VOLUME", ES8311_ADC_REG17,
192 0, 255, 0, vadc_tlv),
193 SOC_SINGLE("ALC ENABLE", ES8311_ADC_REG18, 7, 1, 0),
194 SOC_ENUM("ALC AUTOMUTE TYPE", alc_automute_type),
195 SOC_SINGLE_TLV("ALC WIN SIZE", ES8311_ADC_REG18,
196 0, 15, 0, alc_winsize_tlv),
197 SOC_SINGLE_TLV("ALC MAX LEVEL", ES8311_ADC_REG19,
198 4, 15, 0, alc_maxlevel_tlv),
199 SOC_SINGLE_TLV("ALC MIN LEVEL", ES8311_ADC_REG19,
200 0, 15, 0, alc_minlevel_tlv),
201 SOC_SINGLE_TLV("ALC AUTOMUTE WINSIZE", ES8311_ADC_REG1A,
202 4, 15, 0, alc_noisegate_winsize_tlv),
203 SOC_SINGLE_TLV("ALC AUTOMUTE GATE THRESHOLD", ES8311_ADC_REG1A,
204 0, 15, 0, alc_noisegate_tlv),
205 SOC_SINGLE_TLV("ALC AUTOMUTE VOLUME", ES8311_ADC_REG1B,
206 5, 7, 0, alc_automute_gain_tlv),
207 SOC_SINGLE("ADC FS MODE", ES8311_CLK_MANAGER_REG03, 6, 1, 0),
208 SOC_SINGLE("DAC SDP MUTE", ES8311_SDPIN_REG09, 6, 1, 0),
209 SOC_SINGLE("DAC DEM MUTE", ES8311_DAC_REG31, 5, 1, 0),
210 SOC_SINGLE("DAC INVERT", ES8311_DAC_REG31, 4, 1, 0),
211 SOC_SINGLE("DAC RAM CLR", ES8311_DAC_REG31, 3, 1, 0),
212 SOC_ENUM("DAC DSM MUTE", dacdsm_mute_type),
213 SOC_SINGLE("DAC OFFSET", ES8311_DAC_REG33, 0, 255, 0),
214 SOC_SINGLE_TLV("DAC VOLUME", ES8311_DAC_REG32,
215 0, 255, 0, vdac_tlv),
216 SOC_SINGLE("DRC ENABLE", ES8311_DAC_REG34, 7, 1, 0),
217 SOC_SINGLE_TLV("DRC WIN SIZE", ES8311_DAC_REG34,
218 0, 15, 0, alc_winsize_tlv),
219 SOC_SINGLE_TLV("DRC MAX LEVEL", ES8311_DAC_REG35,
220 4, 15, 0, alc_maxlevel_tlv),
221 SOC_SINGLE_TLV("DRC MIN LEVEL", ES8311_DAC_REG35,
222 0, 15, 0, alc_minlevel_tlv),
223 SOC_SINGLE_TLV("DAC RAMP RATE", ES8311_DAC_REG37,
224 4, 15, 0, adc_ramprate_tlv),
225 SOC_ENUM("AEC MODE", aec_type),
226 SOC_ENUM("ADC DATA TO DAC TEST MODE", adc2dac_sel),
227 SOC_SINGLE("MCLK INVERT", ES8311_CLK_MANAGER_REG01, 6, 1, 0),
228 SOC_SINGLE("BCLK INVERT", ES8311_CLK_MANAGER_REG06, 5, 1, 0),
229 SOC_ENUM("MCLK SOURCE", mclk_src),
230};
231
232/*
233 * DAPM Controls
234 */
235static const char * const es8311_dmic_mux_txt[] = {
236 "DMIC DISABLE",
237 "DMIC ENABLE"
238};
239static const unsigned int es8311_dmic_mux_values[] = {
240 0, 1
241};
242static const struct soc_enum es8311_dmic_mux_enum =
243 SOC_VALUE_ENUM_SINGLE(ES8311_SYSTEM_REG14, 6, 1,
244 ARRAY_SIZE(es8311_dmic_mux_txt),
245 es8311_dmic_mux_txt,
246 es8311_dmic_mux_values);
247static const struct snd_kcontrol_new es8311_dmic_mux_controls =
248 SOC_DAPM_ENUM("DMIC ROUTE", es8311_dmic_mux_enum);
249static const char * const es8311_adc_sdp_mux_txt[] = {
250 "FROM EQUALIZER",
251 "FROM ADC OUT",
252};
253static const unsigned int es8311_adc_sdp_mux_values[] = {
254 0, 1
255};
256static const struct soc_enum es8311_adc_sdp_mux_enum =
257 SOC_VALUE_ENUM_SINGLE(ES8311_ADC_REG1C, 6, 1,
258 ARRAY_SIZE(es8311_adc_sdp_mux_txt),
259 es8311_adc_sdp_mux_txt,
260 es8311_adc_sdp_mux_values);
261static const struct snd_kcontrol_new es8311_adc_sdp_mux_controls =
262 SOC_DAPM_ENUM("ADC SDP ROUTE", es8311_adc_sdp_mux_enum);
263
264/*
265 * DAC data soure
266 */
267static const char * const es8311_dac_data_mux_txt[] = {
268 "SELECT SDP LEFT DATA",
269 "SELECT SDP RIGHT DATA",
270};
271static const unsigned int es8311_dac_data_mux_values[] = {
272 0, 1
273};
274static const struct soc_enum es8311_dac_data_mux_enum =
275 SOC_VALUE_ENUM_SINGLE(ES8311_SDPIN_REG09, 7, 1,
276 ARRAY_SIZE(es8311_dac_data_mux_txt),
277 es8311_dac_data_mux_txt,
278 es8311_dac_data_mux_values);
279static const struct snd_kcontrol_new es8311_dac_data_mux_controls =
280 SOC_DAPM_ENUM("DAC SDP ROUTE", es8311_dac_data_mux_enum);
281
282static const struct snd_soc_dapm_widget es8311_dapm_widgets[] = {
283 /* Input*/
284 SND_SOC_DAPM_INPUT("DMIC"),
285 SND_SOC_DAPM_INPUT("AMIC"),
286
287 //SND_SOC_DAPM_PGA("INPUT PGA", ES8311_SYSTEM_REG0E,
288 // 6, 0, NULL, 0),
289 SND_SOC_DAPM_PGA("INPUT PGA", SND_SOC_NOPM,
290 0, 0, NULL, 0),
291 /* ADCs */
292 //SND_SOC_DAPM_ADC("MONO ADC", NULL, ES8311_SYSTEM_REG0E, 5, 0),
293
294 SND_SOC_DAPM_ADC("MONO ADC", NULL, SND_SOC_NOPM, 0, 0),
295 /* Dmic MUX */
296 SND_SOC_DAPM_MUX("DMIC MUX", SND_SOC_NOPM, 0, 0,
297 &es8311_dmic_mux_controls),
298 /* sdp MUX */
299 SND_SOC_DAPM_MUX("SDP OUT MUX", SND_SOC_NOPM, 0, 0,
300 &es8311_adc_sdp_mux_controls),
301 /* Digital Interface */
302 //SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 1,
303 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0,
304 SND_SOC_NOPM, 0, 0),
305 /* Render path */
306 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0,
307 SND_SOC_NOPM, 0, 0),
308 /*DACs SDP DATA SRC MUX */
309 SND_SOC_DAPM_MUX("DAC SDP SRC MUX", ES8311_SDPIN_REG09, 7, 2,
310 &es8311_dac_data_mux_controls),
311 SND_SOC_DAPM_DAC("MONO DAC", NULL, SND_SOC_NOPM, 0, 0),
312 /* Output Lines */
313 SND_SOC_DAPM_OUTPUT("DIFFERENTIAL OUT"),
314
315};
316
317
318static const struct snd_soc_dapm_route es8311_dapm_routes[] = {
319 /* record route map */
320 {"INPUT PGA", NULL, "AMIC"},
321 {"MONO ADC", NULL, "INPUT PGA"},
322 {"DMIC MUX", "DMIC DISABLE", "MONO ADC"},
323 {"DMIC MUX", "DMIC ENABLE", "DMIC"},
324 {"SDP OUT MUX", "FROM ADC OUT", "DMIC MUX"},
325 {"SDP OUT MUX", "FROM EQUALIZER", "DMIC MUX"},
326 {"I2S OUT", NULL, "SDP OUT MUX"},
327 /* playback route map */
328 {"DAC SDP SRC MUX", "SELECT SDP LEFT DATA", "I2S IN"},
329 {"DAC SDP SRC MUX", "SELECT SDP RIGHT DATA", "I2S IN"},
330 {"MONO DAC", NULL, "DAC SDP SRC MUX"},
331 {"DIFFERENTIAL OUT", NULL, "MONO DAC"},
332};
333
334struct _coeff_div {
335 u32 mclk; /* mclk frequency */
336 u32 rate; /* sample rate */
337 u8 prediv; /* the pre divider with range from 1 to 8 */
338 u8 premulti; /* the pre multiplier with x1, x2, x4 and x8 selection */
339 u8 adcdiv; /* adcclk divider */
340 u8 dacdiv; /* dacclk divider */
341 u8 fsmode; /* double speed or single speed, =0, ss, =1, ds */
342 u8 lrck_h; /* adclrck divider and daclrck divider */
343 u8 lrck_l;
344 u8 bclkdiv; /* sclk divider */
345 u8 adcosr; /* adc osr */
346 u8 dacosr; /* dac osr */
347 u8 adcscale;
348};
349
350
351/* component hifi mclk clock divider coefficients */
352static const struct _coeff_div coeff_div[] = {
353 //mclk rate prediv mult adcdiv dacdiv fsmode lrch lrcl bckdiv osr adcscale
354 /* 8k */
355 {12288000, 8000, 0x06, 0x01, 0x01, 0x01, 0x00, 0x05, 0xff, 0x04, 0x10, 0x20, 0x04}, //1536
356 {18432000, 8000, 0x03, 0x01, 0x03, 0x03, 0x00, 0x08, 0xff, 0x18, 0x10, 0x20, 0x04}, //2304
357 {16384000, 8000, 0x08, 0x01, 0x01, 0x01, 0x00, 0x07, 0xff, 0x04, 0x10, 0x20, 0x04}, //2048
358 {8192000, 8000, 0x04, 0x01, 0x01, 0x01, 0x00, 0x03, 0xff, 0x04, 0x10, 0x20, 0x04}, //1024
359 {6144000, 8000, 0x03, 0x01, 0x01, 0x01, 0x00, 0x02, 0xff, 0x04, 0x10, 0x20, 0x04}, //768
360 {4096000, 8000, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x20, 0x04}, //512
361 {3072000, 8000, 0x03, 0x02, 0x01, 0x01, 0x00, 0x01, 0x7f, 0x04, 0x10, 0x20, 0x04}, //384
362 {2048000, 8000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x20, 0x04}, //256
363 {1536000, 8000, 0x01, 0x04, 0x03, 0x03, 0x00, 0x00, 0xbf, 0x04, 0x10, 0x20, 0x04}, //192
364 {1024000, 8000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x20, 0x04}, //128
365 {12000000, 8000, 0x05, 0x04, 0x03, 0x03, 0x00, 0x05, 0xDB, 0x04, 0x19, 0x19, 0x01}, //1500
366 {26000000, 8000 , 0x04, 0x03, 0x0C, 0x0C, 0x00, 0x06, 0x58, 0x18, 0x1B, 0x1B, 0x01},
367
368 /* 11.025k */
369 {11289600, 11025, 0x04, 0x01, 0x01, 0x01, 0x00, 0x03, 0xff, 0x04, 0x10, 0x20, 0x04}, //1024
370 {5644800, 11025, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x20, 0x04}, //512
371 {2822400, 11025, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x20, 0x04}, //256
372 {1411200, 11025, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x20, 0x04}, //128
373
374 /* 12k */
375 {12288000, 12000, 0x04, 0x01, 0x01, 0x01, 0x00, 0x03, 0xff, 0x04, 0x10, 0x20, 0x04}, //1024
376 {6144000, 12000, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x20, 0x04}, //512
377 {3072000, 12000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x20, 0x04}, //256
378 {1536000, 12000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x20, 0x04}, //128
379
380 /* 16k */
381 //{24576000, 16000, 0x06, 0x01, 0x01, 0x01, 0x00, 0x05, 0xff, 0x04, 0x10, 0x20, 0x04}, //1536
382 {12288000, 16000, 0x03, 0x01, 0x01, 0x01, 0x00, 0x02, 0xff, 0x04, 0x10, 0x20, 0x04}, //768
383 {18432000, 16000, 0x03, 0x02, 0x03, 0x03, 0x00, 0x04, 0x7f, 0x0c, 0x10, 0x20, 0x04}, //1152
384 {16384000, 16000, 0x04, 0x01, 0x01, 0x01, 0x00, 0x03, 0xff, 0x04, 0x10, 0x20, 0x04}, //1024
385 {8192000, 16000, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x20, 0x04}, //512
386 {6144000, 16000, 0x03, 0x02, 0x01, 0x01, 0x00, 0x01, 0x7f, 0x04, 0x10, 0x20, 0x04}, //384
387 {4096000, 16000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x20, 0x04}, //256
388 {3072000, 16000, 0x03, 0x04, 0x01, 0x01, 0x00, 0x00, 0xbf, 0x04, 0x10, 0x20, 0x04}, //192
389 {2048000, 16000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x20, 0x04}, //128
390 {1536000, 16000, 0x01, 0x08, 0x03, 0x03, 0x00, 0x00, 0x5f, 0x02, 0x10, 0x20, 0x04}, //96
391 {1024000, 16000, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x20, 0x04}, //64
392 {12000000, 16000, 0x05, 0x08, 0x03, 0x03, 0x00, 0x02, 0xED, 0x04, 0x19, 0x19, 0x01}, //750
393 {26000000, 16000 , 0x04, 0x03, 0x06, 0x06, 0x00, 0x06, 0x58, 0x18, 0x1B, 0x1B, 0x01},
394
395
396 /* 22.05k */
397 {11289600, 22050, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x20, 0x04}, //512
398 {5644800, 22050, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x20, 0x04}, //256
399 {2822400, 22050, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x20, 0x04}, //128
400 {1411200, 22050, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x20, 0x04}, //64
401
402 /* 24k */
403 //{24576000, 24000, 0x04, 0x01, 0x01, 0x01, 0x00, 0x03, 0xff, 0x04, 0x10, 0x20, 0x04}, //1024
404 {12288000, 24000, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x20, 0x04}, //512
405 {18432000, 24000, 0x03, 0x01, 0x01, 0x01, 0x00, 0x02, 0xff, 0x04, 0x10, 0x20, 0x04}, //768
406 {6144000, 24000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x20, 0x04}, //256
407 {3072000, 24000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x20, 0x04}, //128
408 {1536000, 24000, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x20, 0x04}, //64
409 {12000000, 24000, 0x05, 0x04, 0x01, 0x01, 0x00, 0x01, 0xF3, 0x04, 0x19, 0x19, 0x01}, //500
410
411 /* 32k */
412 //{24576000, 32000, 0x03, 0x01, 0x01, 0x01, 0x00, 0x02, 0xff, 0x04, 0x10, 0x10, 0x04}, //768
413 {12288000, 32000, 0x03, 0x02, 0x01, 0x01, 0x00, 0x01, 0x7f, 0x04, 0x10, 0x10, 0x04}, //384
414 {18432000, 32000, 0x03, 0x04, 0x03, 0x03, 0x00, 0x02, 0x3f, 0x0c, 0x10, 0x10, 0x04}, //576
415 {16384000, 32000, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x10, 0x04}, //512
416 {8192000, 32000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x10, 0x04}, //256
417 {6144000, 32000, 0x03, 0x04, 0x01, 0x01, 0x00, 0x00, 0xbf, 0x04, 0x10, 0x10, 0x04}, //192
418 {4096000, 32000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x10, 0x04}, //128
419 {3072000, 32000, 0x03, 0x08, 0x01, 0x01, 0x00, 0x00, 0x5f, 0x02, 0x10, 0x10, 0x04}, //96
420 {2048000, 32000, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x10, 0x04}, //64
421 {1536000, 32000, 0x01, 0x08, 0x03, 0x03, 0x01, 0x00, 0x2f, 0x02, 0x10, 0x10, 0x04}, //48
422 {1024000, 32000, 0x01, 0x08, 0x01, 0x01, 0x00, 0x00, 0x1f, 0x02, 0x10, 0x10, 0x04}, //32
423
424 /* 44.1k */
425 //{22579200, 44100, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x10, 0x04}, //512
426 {11289600, 44100, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x10, 0x04}, //256
427 {5644800, 44100, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x10, 0x04}, //128
428 {2822400, 44100, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x10, 0x04}, //64
429 {1411200, 44100, 0x01, 0x08, 0x01, 0x01, 0x00, 0x00, 0x1f, 0x02, 0x10, 0x10, 0x04}, //32
430
431 /* 48k */
432 {24576000, 48000, 0x02, 0x01, 0x01, 0x01, 0x00, 0x01, 0xff, 0x04, 0x10, 0x10, 0x04}, //512
433 {12288000, 48000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x10, 0x04}, //256
434 {18432000, 48000, 0x03, 0x02, 0x01, 0x01, 0x00, 0x01, 0x7f, 0x04, 0x10, 0x10, 0x04}, //384
435 {6144000, 48000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x10, 0x04}, //128
436 {3072000, 48000, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x10, 0x04}, //64
437 {1536000, 48000, 0x01, 0x08, 0x01, 0x01, 0x00, 0x00, 0x1f, 0x02, 0x10, 0x10, 0x04}, //32
438 {12000000, 48000, 0x05, 0x08, 0x01, 0x01, 0x00, 0x00, 0xF9, 0x04, 0x19, 0x19, 0x01}, //250
439
440 /* 64k */
441 {12288000, 64000, 0x03, 0x04, 0x01, 0x01, 0x00, 0x00, 0xbf, 0x04, 0x10, 0x10, 0x04}, //192
442 {18432000, 64000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x01, 0x1f, 0x06, 0x12, 0x12, 0x03}, //288
443 {16384000, 64000, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xff, 0x04, 0x10, 0x10, 0x04}, //256
444 {8192000, 64000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x10, 0x04}, //128
445 {6144000, 64000, 0x03, 0x08, 0x01, 0x01, 0x01, 0x00, 0x5f, 0x02, 0x10, 0x10, 0x04}, //96
446 {4096000, 64000, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x10, 0x04}, //64
447 {3072000, 64000, 0x03, 0x08, 0x01, 0x01, 0x01, 0x00, 0x2f, 0x02, 0x10, 0x10, 0x04}, //48
448 {2048000, 64000, 0x01, 0x08, 0x01, 0x01, 0x00, 0x00, 0x1f, 0x02, 0x10, 0x10, 0x04}, //32
449
450 /* 88.2k */
451 {11289600, 88200, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x10, 0x04}, //128
452 {5644800, 88200, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x10, 0x04}, //64
453 {2822400, 88200, 0x01, 0x08, 0x01, 0x01, 0x00, 0x00, 0x1f, 0x02, 0x10, 0x10, 0x04}, //32
454
455 /* 96k */
456 {12288000, 96000, 0x01, 0x02, 0x01, 0x01, 0x00, 0x00, 0x7f, 0x04, 0x10, 0x10, 0x04}, //128
457 {18432000, 96000, 0x03, 0x04, 0x01, 0x01, 0x00, 0x00, 0xbf, 0x04, 0x10, 0x10, 0x04}, //192
458 {6144000, 96000, 0x01, 0x04, 0x01, 0x01, 0x00, 0x00, 0x3f, 0x02, 0x10, 0x10, 0x04}, //64
459 {3072000, 96000, 0x01, 0x08, 0x01, 0x01, 0x00, 0x00, 0x1f, 0x02, 0x10, 0x10, 0x04}, //32
460};
461static inline int get_coeff(int mclk, int rate)
462{
463 int i;
464
465 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
466 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
467 return i;
468 }
469 return -EINVAL;
470}
471
472/*
473 * if PLL not be used, use internal clk1 for mclk,otherwise, use internal clk2 for PLL source.
474 */
475static int es8311_set_dai_sysclk(struct snd_soc_dai *dai,
476 int clk_id, unsigned int freq, int dir)
477{
478 struct snd_soc_component *component = dai->component;
479 struct es8311_private *es8311 = snd_soc_component_get_drvdata(component);
480
481 printk("Enter into %s(), freq:%d\n", __func__,freq);
482 switch (freq) {
483 case 11289600:
484 case 22579200:
485 case 5644800:
486 case 2822400:
487 case 1411200:
488 case 12288000:
489 case 16384000:
490 case 18432000:
491 case 24576000:
492 case 8192000:
493 case 6144000:
494 case 4096000:
495 case 2048000:
496 case 3072000:
497 case 1536000:
498 case 1024000:
499 case 12000000:
500 case 26000000:
501
502 es8311->mclk_rate = freq;
503 return 0;
504 }
505
506 return -EINVAL;
507}
508
509static int es8311_set_dai_fmt(struct snd_soc_dai *component_dai, unsigned int fmt)
510{
511 struct snd_soc_component *component = component_dai->component;
512 struct es8311_private *es8311 = snd_soc_component_get_drvdata(component);
513 u8 iface = 0;
514 u8 adciface = 0;
515 u8 daciface = 0;
516 printk("Enter into %s()\n", __func__);
517
518 dev_dbg(component->dev, "Enter into %s()\n", __func__);
519 iface = snd_soc_component_read(component, ES8311_RESET_REG00);
520 adciface = snd_soc_component_read(component, ES8311_SDPOUT_REG0A);
521 daciface = snd_soc_component_read(component, ES8311_SDPIN_REG09);
522
523 /* set master/slave audio interface */
524 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
525 case SND_SOC_DAIFMT_CBM_CFM: /* MASTER MODE */
526 pr_info("%s mastermode\n", __func__);
527 es8311->mastermode = 1;
528 dev_dbg(component->dev, "ES8311 in Master mode\n");
529 iface |= 0x40;
530 break;
531 case SND_SOC_DAIFMT_CBS_CFS: /* SLAVE MODE */
532 es8311->mastermode = 0;
533 dev_dbg(component->dev, "ES8311 in Slave mode\n");
534 iface &= 0xBF;
535 break;
536 default:
537 return -EINVAL;
538 }
539 snd_soc_component_write(component, ES8311_RESET_REG00, iface);
540
541
542 /* interface format */
543 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
544 case SND_SOC_DAIFMT_I2S:
545 dev_dbg(component->dev, "ES8311 in I2S Format\n");
546 adciface &= 0xFC;
547 daciface &= 0xFC;
548 break;
549 case SND_SOC_DAIFMT_RIGHT_J:
550 return -EINVAL;
551 case SND_SOC_DAIFMT_LEFT_J:
552 dev_dbg(component->dev, "ES8311 in LJ Format\n");
553 adciface &= 0xFC;
554 daciface &= 0xFC;
555 adciface |= 0x01;
556 daciface |= 0x01;
557 break;
558 case SND_SOC_DAIFMT_DSP_A:
559 dev_dbg(component->dev, "ES8311 in DSP-A Format\n");
560 adciface &= 0xDC;
561 daciface &= 0xDC;
562 adciface |= 0x03;
563 daciface |= 0x03;
564 break;
565 case SND_SOC_DAIFMT_DSP_B:
566 dev_dbg(component->dev, "ES8311 in DSP-B Format\n");
567 adciface &= 0xDC;
568 daciface &= 0xDC;
569 adciface |= 0x23;
570 daciface |= 0x23;
571 break;
572 default:
573 return -EINVAL;
574 }
575
576 iface = snd_soc_component_read(component, ES8311_CLK_MANAGER_REG06);
577 /* clock inversion */
578 if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) ||
579 ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LEFT_J)) {
580 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
581 case SND_SOC_DAIFMT_NB_NF:
582
583 iface &= 0xDF;
584 adciface &= 0xDF;
585 daciface &= 0xDF;
586 break;
587 case SND_SOC_DAIFMT_IB_IF:
588 iface |= 0x20;
589 adciface |= 0x20;
590 daciface |= 0x20;
591 break;
592 case SND_SOC_DAIFMT_IB_NF:
593 iface |= 0x20;
594 adciface &= 0xDF;
595 daciface &= 0xDF;
596 break;
597 case SND_SOC_DAIFMT_NB_IF:
598 iface &= 0xDF;
599 adciface |= 0x20;
600 daciface |= 0x20;
601 break;
602 default:
603 return -EINVAL;
604 }
605 }
606
607 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG06, iface);
608 snd_soc_component_write(component, ES8311_SDPOUT_REG0A, adciface);
609 snd_soc_component_write(component, ES8311_SDPIN_REG09, daciface);
610 return 0;
611}
612static int es8311_pcm_startup(struct snd_pcm_substream *substream,
613 struct snd_soc_dai *dai)
614{
615 printk("Enter into %s()\n", __func__);
616
617 return 0;
618}
619
620static int es8311_pcm_hw_params(struct snd_pcm_substream *substream,
621 struct snd_pcm_hw_params *params,
622 struct snd_soc_dai *dai)
623{
624 struct snd_soc_component *component = dai->component;
625 struct es8311_private *es8311 = snd_soc_component_get_drvdata(component);
626 u16 iface;
627 int coeff;
628 u8 regv, datmp;
629 int rate;
630
631 printk("Enter into %s()\n", __func__);
632 /* we need mclk rate to configure registers. Set MCLK here if failed
633 * to get mclk from set_sysclk.
634 *
635 * If the es8311->mclk_rate is a constant value, for example 12.288M,
636 * set es8311->mclk_rate = 12288000;
637 * else if es8311->mclk_rate is dynamic, for example 128Fs,
638 * set es8311->mclk_rate = 128 * params_rate(params);
639 */
640 if (es8311->mclk_src == ES8311_BCLK_PIN) {
641 /*
642 * Here 64 is ratio of BCLK/LRCK.
643 * If BCLK/LRCK isn't 64, please change it according to actual ratio.
644 */
645 snd_soc_component_update_bits(component,
646 ES8311_CLK_MANAGER_REG01, 0x80, 0x80);
647 es8311->mclk_rate = 64 * params_rate(params);
648 }
649
650 pr_info("%s, mclk = %d, lrck = %d\n", __func__,
651 es8311->mclk_rate, params_rate(params));
652
653 rate = params_rate(params);
654 printk("yanming rate:%d\n",rate);
655 coeff = get_coeff(es8311->mclk_rate, params_rate(params));
656 if (coeff < 0) {
657 pr_info("Unable to configure sample rate %dHz with %dHz MCLK\n",
658 params_rate(params), es8311->mclk_rate);
659 //return -EINVAL;
660 }
661 /*
662 * set clock parammeters
663 */
664 if (coeff >= 0) {
665 regv = snd_soc_component_read(component,
666 ES8311_CLK_MANAGER_REG02) & 0x07;
667
668 regv |= (coeff_div[coeff].prediv - 1) << 5;
669 datmp = 0;
670 switch (coeff_div[coeff].premulti) {
671 case 1:
672 datmp = 0;
673 break;
674 case 2:
675 datmp = 1;
676 break;
677 case 4:
678 datmp = 2;
679 break;
680 case 8:
681 datmp = 3;
682 break;
683 default:
684 break;
685 }
686 regv |= (datmp) << 3;
687 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, regv);
688
689 regv = snd_soc_component_read(component,
690 ES8311_CLK_MANAGER_REG05) & 0x00;
691 regv |= (coeff_div[coeff].adcdiv - 1) << 4;
692 regv |= (coeff_div[coeff].dacdiv - 1) << 0;
693 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, regv);
694
695 regv = snd_soc_component_read(component,
696 ES8311_CLK_MANAGER_REG03) & 0x80;
697 regv |= coeff_div[coeff].fsmode << 6;
698 regv |= coeff_div[coeff].adcosr << 0;
699 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, regv);
700
701 regv = snd_soc_component_read(component,
702 ES8311_CLK_MANAGER_REG04) & 0x80;
703 regv |= coeff_div[coeff].dacosr << 0;
704 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, regv);
705
706 regv = snd_soc_component_read(component,
707 ES8311_CLK_MANAGER_REG07) & 0xf0;
708 regv |= coeff_div[coeff].lrck_h << 0;
709 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG07, regv);
710
711 regv = snd_soc_component_read(component,
712 ES8311_CLK_MANAGER_REG08) & 0x00;
713 regv |= coeff_div[coeff].lrck_l << 0;
714 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG08, regv);
715
716 regv = snd_soc_component_read(component,
717 ES8311_CLK_MANAGER_REG06) & 0xE0;
718 if (coeff_div[coeff].bclkdiv < 19)
719 regv |= (coeff_div[coeff].bclkdiv - 1) << 0;
720 else
721 regv |= coeff_div[coeff].bclkdiv << 0;
722
723 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG06, regv);
724
725 regv = snd_soc_component_read(component, ES8311_ADC_REG16) & 0x38;
726 regv |= (coeff_div[coeff].adcscale) << 0;
727 snd_soc_component_write(component, ES8311_ADC_REG16, regv);
728 }
729
730 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
731 iface = snd_soc_component_read(component,
732 ES8311_SDPIN_REG09) & 0xE3;
733 /* bit size */
734 switch (params_format(params)) {
735 case SNDRV_PCM_FORMAT_S16_LE:
736 iface |= 0x0c;
737 break;
738 case SNDRV_PCM_FORMAT_S20_3LE:
739 iface |= 0x04;
740 break;
741 case SNDRV_PCM_FORMAT_S24_LE:
742 break;
743 case SNDRV_PCM_FORMAT_S32_LE:
744 iface |= 0x10;
745 break;
746 }
747 /* set iface */
748 snd_soc_component_write(component, ES8311_SDPIN_REG09, iface);
749 } else {
750 iface = snd_soc_component_read(component,
751 ES8311_SDPOUT_REG0A) & 0xE3;
752 /* bit size */
753 switch (params_format(params)) {
754 case SNDRV_PCM_FORMAT_S16_LE:
755 iface |= 0x0c;
756 break;
757 case SNDRV_PCM_FORMAT_S20_3LE:
758 iface |= 0x04;
759 break;
760 case SNDRV_PCM_FORMAT_S24_LE:
761 break;
762 case SNDRV_PCM_FORMAT_S32_LE:
763 iface |= 0x10;
764 break;
765 }
766 /* set iface */
767 snd_soc_component_write(component, ES8311_SDPOUT_REG0A, iface);
768 }
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]769/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
770#ifdef CONFIG_USE_TOP_TDM
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]771#else
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]772 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x98);
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]773 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x1b);
774 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x1b);
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]775 /*
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]776 if(rate == 8000){
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]777 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0xbb);
778 pr_info("%s rate:%d\n",__FUNCTION__,rate);
xf.li39d99112024-09-28 04:05:58 -0700[diff] [blame]779
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]780 }
xf.li39d99112024-09-28 04:05:58 -0700[diff] [blame]781 if(rate == 16000){
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]782 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x55);
783 pr_info("%s rate:%d\n",__FUNCTION__,rate);
xf.li39d99112024-09-28 04:05:58 -0700[diff] [blame]784
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]785 }
786 */
xf.li39d99112024-09-28 04:05:58 -0700[diff] [blame]787 if(rate == 44100){
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]788
789 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x90);
790 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x1d);
791 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x1d);
792 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x00);
793 pr_info("%s rate:%d\n",__FUNCTION__,rate);
794
795 }
796#endif
797/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]798 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG06, 0x18);
799 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG07, 0x06);
800
801 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG08, 0x58);
802
803
804 return 0;
805}
806
807static int es8311_set_bias_level(struct snd_soc_component *component,
808 enum snd_soc_bias_level level)
809{
810 int regv;
811 struct es8311_private *es8311 = snd_soc_component_get_drvdata(component);
812
813 printk("Enter into %s(), level = %d\n", __func__, level);
814 switch (level) {
815 case SND_SOC_BIAS_ON:
816 printk("%s on\n", __func__);
817 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
818 if (es8311->mclk_src == ES8311_MCLK_PIN) {
819 snd_soc_component_write(component,
820 ES8311_CLK_MANAGER_REG01, 0x30);
821 } else {
822 snd_soc_component_write(component,
823 ES8311_CLK_MANAGER_REG01, 0xB0);
824 }
825 //snd_soc_component_write(component, ES8311_ADC_REG16, 0x24);
826 snd_soc_component_write(component, ES8311_SYSTEM_REG0B, 0x00);
827 snd_soc_component_write(component, ES8311_SYSTEM_REG0C, 0x00);
828 if (ES8311_AVDD == ES8311_1V8) {
829 snd_soc_component_write(component,
830 ES8311_SYSTEM_REG10, 0x61);
831 snd_soc_component_write(component,
832 ES8311_SYSTEM_REG11, 0x7B);
833 } else {
834 snd_soc_component_write(component,
835 ES8311_SYSTEM_REG10, 0x03);
836 snd_soc_component_write(component,
837 ES8311_SYSTEM_REG11, 0x57);
838 }
839
840 if (es8311->mclk_src == ES8311_MCLK_PIN) {
841 snd_soc_component_write(component,
842 ES8311_CLK_MANAGER_REG01, 0x3F);
843 } else {
844 snd_soc_component_write(component,
845 ES8311_CLK_MANAGER_REG01, 0xBF);
846 }
847 if (es8311->mclkinv == true) {
848 snd_soc_component_update_bits(component,
849 ES8311_CLK_MANAGER_REG01, 0x40, 0x40);
850 } else {
851 snd_soc_component_update_bits(component,
852 ES8311_CLK_MANAGER_REG01, 0x40, 0x00);
853 }
854 if (es8311->sclkinv == true) {
855 snd_soc_component_update_bits(component,
856 ES8311_CLK_MANAGER_REG06, 0x20, 0x20);
857 } else {
858 snd_soc_component_update_bits(component,
859 ES8311_CLK_MANAGER_REG06, 0x20, 0x00);
860 }
861
862 //digital reset
863 snd_soc_component_write(component, ES8311_RESET_REG00, 0x1f);
864 usleep_range(1000, 2000);
865 if (es8311->mastermode == 1) {
866 snd_soc_component_write(component,
867 ES8311_RESET_REG00, 0xC0);
868 } else {
869 snd_soc_component_write(component,
870 ES8311_RESET_REG00, 0x80);
871 }
872 usleep_range(1500, 3000);
873
874 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0x01);
875
876 regv = snd_soc_component_read(component, ES8311_SYSTEM_REG14) & 0xCF;
877 regv |= 0x1A;
878 snd_soc_component_write(component, ES8311_SYSTEM_REG14, regv);
879
880 if (es8311->dmic_enable == true) {
881 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14,
882 0x40, 0x40);
883 } else {
884 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14,
885 0x40, 0x00);
886 }
887 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x00);
888 snd_soc_component_write(component, ES8311_SYSTEM_REG13, 0x10);
889 snd_soc_component_write(component, ES8311_SYSTEM_REG0E, 0x02);
890 printk("%s biason REG0E=0X%X\n", __func__,snd_soc_component_read(component, ES8311_SYSTEM_REG0E));
891
892 snd_soc_component_write(component, ES8311_SYSTEM_REG0F, 0x7F);
893 snd_soc_component_write(component, ES8311_ADC_REG15, 0x40);
894 snd_soc_component_write(component, ES8311_ADC_REG1B, 0x0A);
895 snd_soc_component_write(component, ES8311_ADC_REG1C, 0x6A);
xf.lia06dd222024-10-14 09:07:20 +0000[diff] [blame^]896 snd_soc_component_write(component, ES8311_DAC_REG37, 0x48);
xf.li1867bfa2024-08-20 02:32:16 -0700[diff] [blame]897/* yu.dong@20240718[ZXW-277]Optimizing Recording in CODEC 8311 TDM Mode start*/
898#if defined(CONFIG_USE_TOP_TDM)
899 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x9f);
900 snd_soc_component_write(component, ES8311_ADC_REG15, 0x00);
901#endif
902/* yu.dong@20240718[ZXW-277]Optimizing Recording in CODEC 8311 TDM Mode end*/
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]903 //snd_soc_component_write(component, ES8311_ADC_REG17, 0xBF);
904 //snd_soc_component_write(component, ES8311_DAC_REG32, 0xBF);
905 break;
906 case SND_SOC_BIAS_PREPARE:
907 printk("%s prepare\n", __func__);
908 break;
909 case SND_SOC_BIAS_STANDBY:
910 printk("%s standby\n", __func__);
911 if (es8311->bias_level == SND_SOC_BIAS_PREPARE) {
912 //snd_soc_component_write(component, ES8311_DAC_REG32, 0x00);
913 //snd_soc_component_write(component, ES8311_ADC_REG17, 0x00);
914 snd_soc_component_write(component, ES8311_SYSTEM_REG0E, 0xFF);
915 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x02);
916 snd_soc_component_write(component, ES8311_SYSTEM_REG14, 0x00);
917 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0xF9);
918 snd_soc_component_write(component, ES8311_ADC_REG15, 0x00);
919 snd_soc_component_write(component, ES8311_DAC_REG37, 0x08);
920 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x10);
921 snd_soc_component_write(component, ES8311_RESET_REG00, 0x00);
922 snd_soc_component_write(component, ES8311_RESET_REG00, 0x1F);
923/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
924#ifdef CONFIG_USE_TOP_TDM
925 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0xB0);
926#else
927 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x30);
928#endif
929 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x00);
930 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
931 }
932 break;
933 case SND_SOC_BIAS_OFF:
934 printk("%s off\n", __func__);
935 if (es8311->bias_level == SND_SOC_BIAS_STANDBY) {
936 //snd_soc_component_write(component, ES8311_DAC_REG32, 0x00);
937 //snd_soc_component_write(component, ES8311_ADC_REG17, 0x00);
938 snd_soc_component_write(component, ES8311_SYSTEM_REG0E, 0xFF);
939 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x02);
940 snd_soc_component_write(component, ES8311_SYSTEM_REG14, 0x00);
941 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0xF9);
942 snd_soc_component_write(component, ES8311_ADC_REG15, 0x00);
943 snd_soc_component_write(component, ES8311_DAC_REG37, 0x08);
944 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x10);
945 snd_soc_component_write(component, ES8311_RESET_REG00, 0x00);
946 snd_soc_component_write(component, ES8311_RESET_REG00, 0x1F);
947#ifdef CONFIG_USE_TOP_TDM
948 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0xB0);
949#else
950 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x30);
951#endif
952/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
953 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x00);
954 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
955 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0xFC);
956 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x00);
957 }
958 break;
959 }
960 es8311->bias_level = level;
961 printk("%s END bias_level(%d),REG0E=0X%X\n", __func__,level,snd_soc_component_read(component, ES8311_SYSTEM_REG0E));
962
963 return 0;
964}
965
966static int es8311_set_tristate(struct snd_soc_dai *dai, int tristate)
967{
968 struct snd_soc_component *component = dai->component;
969
970 printk("Enter into %s(), tristate = %d\n", __func__, tristate);
971 if (tristate) {
972 snd_soc_component_update_bits(component,
973 ES8311_CLK_MANAGER_REG07, 0x30, 0x30);
974 } else {
975 snd_soc_component_update_bits(component,
976 ES8311_CLK_MANAGER_REG07, 0x30, 0x00);
977 }
978 return 0;
979}
980
981static int es8311_mute(struct snd_soc_dai *dai, int mute, int direction)
982{
983 struct snd_soc_component *component = dai->component;
984
985 printk("Enter into %s(), mute = %d\n", __func__, mute);
986
987 if (mute) {
988 snd_soc_component_write(component, ES8311_SYSTEM_REG12,
989 0x02);
990 snd_soc_component_update_bits(component, ES8311_DAC_REG31,
991 0x60, 0x60);
992 //snd_soc_component_write(component, ES8311_DAC_REG32, 0x00);
993 } else {
994 snd_soc_component_update_bits(component, ES8311_DAC_REG31,
995 0x60, 0x00);
996 snd_soc_component_write(component, ES8311_SYSTEM_REG12,
997 0x00);
998 //snd_soc_component_write(component, ES8311_DAC_REG32, 0xbf);
999 }
1000 printk("%s mute=%d biason REG0E=0X%X\n", __func__,mute,snd_soc_component_read(component, ES8311_SYSTEM_REG0E));
1001
1002 return 0;
1003}
1004
1005#define es8311_RATES SNDRV_PCM_RATE_8000_96000
1006
1007#define es8311_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1008 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1009
1010static const struct snd_soc_dai_ops es8311_ops = {
1011 .startup = es8311_pcm_startup,
1012 .hw_params = es8311_pcm_hw_params,
1013 .set_fmt = es8311_set_dai_fmt,
1014 .set_sysclk = es8311_set_dai_sysclk,
1015 .mute_stream = es8311_mute,
1016 .set_tristate = es8311_set_tristate,
1017};
1018
1019static struct snd_soc_dai_driver es8311_dai = {
1020 .name = "ES8311 HiFi",
1021 .playback = {
1022 .stream_name = "Playback",
1023 .channels_min = 1,
1024 .channels_max = 2,
1025 .rates = es8311_RATES,
1026 .formats = es8311_FORMATS,
1027 },
1028 .capture = {
1029 .stream_name = "Capture",
1030 .channels_min = 1,
1031 .channels_max = 2,
1032 .rates = es8311_RATES,
1033 .formats = es8311_FORMATS,
1034 },
1035 .ops = &es8311_ops,
1036 .symmetric_rates = 1,
1037};
1038
1039static int es8311_suspend(struct snd_soc_component *component)
1040{
1041 printk("Enter into %s()\n", __func__);
1042
1043 //snd_soc_component_write(component, ES8311_DAC_REG32, 0x00);
1044 //snd_soc_component_write(component, ES8311_ADC_REG17, 0x00);
1045 snd_soc_component_write(component, ES8311_SYSTEM_REG0E, 0xFF);
1046 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x02);
1047 snd_soc_component_write(component, ES8311_SYSTEM_REG14, 0x00);
1048 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0xF9);
1049 snd_soc_component_write(component, ES8311_ADC_REG15, 0x00);
1050 snd_soc_component_write(component, ES8311_DAC_REG37, 0x08);
1051 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x10);
1052 snd_soc_component_write(component, ES8311_RESET_REG00, 0x00);
1053 snd_soc_component_write(component, ES8311_RESET_REG00, 0x1F);
1054 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x30);
1055 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x00);
1056 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
1057 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0xFC);
1058 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x00);
1059
1060 return 0;
1061}
1062
1063static int es8311_resume(struct snd_soc_component *component)
1064{
1065 printk("Enter into %s()\n", __func__);
1066 //yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment
1067 return 0;
1068}
1069
1070static int es8311_probe(struct snd_soc_component *component)
1071{
1072 int ret = 0;
1073 struct es8311_private *es8311 = es8311_data;
1074
1075 printk("Enter into %s()\n", __func__);
1076
1077 snd_soc_component_set_drvdata(component, es8311);
1078 if (component == NULL) {
1079 dev_err(component->dev, "Codec device not registered\n");
1080 return -ENODEV;
1081 }
1082 es8311_component = component;
1083 es8311->component = component;
1084
1085 es8311->mastermode = 0;
1086/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
1087#ifdef CONFIG_USE_TOP_TDM
1088 es8311->mclk_src = ES8311_BCLK_PIN;
1089#else
1090 es8311->mclk_src = ES8311_MCLK_SOURCE;
1091#endif
1092/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
1093 /* Enable the following code if there is no mclk.
1094 * a clock named "mclk" need to be defined in the dts (see sample dts)
1095 *
1096 * No need to enable the following code to get mclk if:
1097 * 1. sclk/bclk is used as mclk
1098 * 2. mclk is controled by soc I2S
1099 */
1100 //if (es8311->mclk_src == ES8311_MCLK_PIN) {
1101 if (0) {
1102
1103 es8311->mclk = devm_clk_get(component->dev, "mclk");
1104 if (IS_ERR(es8311->mclk)) {
1105 dev_err(component->dev, "%s,unable to get mclk\n", __func__);
1106 return PTR_ERR(es8311->mclk);
1107 }
1108 if (!es8311->mclk)
1109 dev_err(component->dev, "%s, assuming static mclk\n", __func__);
1110
1111 ret = clk_prepare_enable(es8311->mclk);
1112 if (ret) {
1113 dev_err(component->dev, "%s, unable to enable mclk\n", __func__);
1114 return ret;
1115 }
1116 }
1117/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
1118 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
1119#ifdef CONFIG_USE_TOP_TDM
1120 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0xB0);
1121#else
1122 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x30);
1123#endif
1124 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x00);
1125 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x10);
1126 //snd_soc_component_write(component, ES8311_ADC_REG16, 0x24);
1127 snd_soc_component_write(component, ES8311_ADC_REG16, 0x21);
1128 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x10);
1129 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x00);
1130 snd_soc_component_write(component, ES8311_SDPIN_REG09, 0x00);
1131 snd_soc_component_write(component, ES8311_SDPOUT_REG0A, 0x00);
1132 snd_soc_component_write(component, ES8311_SYSTEM_REG0B, 0x00);
1133 snd_soc_component_write(component, ES8311_SYSTEM_REG0C, 0x00);
1134 if (ES8311_AVDD == ES8311_1V8) {
1135 snd_soc_component_write(component, ES8311_SYSTEM_REG10, 0x61);
1136 snd_soc_component_write(component, ES8311_SYSTEM_REG11, 0x7B);
1137 } else {
1138 snd_soc_component_write(component, ES8311_SYSTEM_REG10, 0x03);
1139 snd_soc_component_write(component, ES8311_SYSTEM_REG11, 0x57);
1140 }
1141
1142 if (es8311->mclk_src == ES8311_MCLK_PIN)
1143 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x3F);
1144 else
1145 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0xBF);
1146
1147 if (es8311->mastermode == 1)
1148 snd_soc_component_write(component, ES8311_RESET_REG00, 0xC0);
1149 else
1150 snd_soc_component_write(component, ES8311_RESET_REG00, 0x80);
1151
1152 usleep_range(1500, 3000);
1153 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0x01);
1154
1155 if (es8311->mclkinv == true) {
1156 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG01,
1157 0x40, 0x40);
1158 } else {
1159 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG01,
1160 0x40, 0x00);
1161 }
1162 if (es8311->sclkinv == true) {
1163 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG06,
1164 0x20, 0x20);
1165 } else {
1166 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG06,
1167 0x20, 0x00);
1168 }
1169 snd_soc_component_write(component, ES8311_SYSTEM_REG14, 0x1A);
1170 if (es8311->dmic_enable == true) {
1171 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14,
1172 0x40, 0x40);
1173 } else {
1174 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14,
1175 0x40, 0x00);
1176 }
1177 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x00);
1178 snd_soc_component_write(component, ES8311_SYSTEM_REG13, 0x10);
1179 snd_soc_component_write(component, ES8311_SYSTEM_REG0E, 0x02);
1180 snd_soc_component_write(component, ES8311_SYSTEM_REG0F, 0x7F);
1181 snd_soc_component_write(component, ES8311_ADC_REG15, 0x40);
1182 snd_soc_component_write(component, ES8311_ADC_REG1B, 0x0A);
1183 snd_soc_component_write(component, ES8311_ADC_REG1C, 0x6A);
1184 snd_soc_component_write(component, ES8311_DAC_REG37, 0x48);
1185 snd_soc_component_write(component, ES8311_ADC_REG17, 0xBF);
1186 snd_soc_component_write(component, ES8311_DAC_REG32, 0xBF);
1187#ifdef CONFIG_USE_TOP_TDM
1188 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x1A);
1189 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x1b);
1190 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x1b);
1191 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x00);
1192 snd_soc_component_write(component, ES8311_SDPIN_REG09,0x0F);
1193 snd_soc_component_write(component, ES8311_SDPOUT_REG0A,0x0F);
1194#else
1195 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x98);
1196 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x1b);
1197 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x1b);
1198 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0xbb);
1199#endif
1200/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
1201 msleep(100);
1202 es8311_set_bias_level(component, SND_SOC_BIAS_STANDBY);
1203
1204 printk("%s end\n", __func__);
1205
1206
1207 return ret;
1208}
1209
1210static void es8311_remove(struct snd_soc_component *component)
1211{
1212 printk("Enter into %s()\n", __func__);
1213
1214 es8311_set_bias_level(component, SND_SOC_BIAS_OFF);
1215}
1216static int clkout_init_pinctrl(struct device *dev)
1217{
1218
1219 struct pinctrl *pctrl;
1220 struct pinctrl_state *state0;
1221 struct clk *clk;
1222 int ret;
1223 struct es8311_private *info = dev_get_drvdata(dev);
1224 struct device_node *np = dev->of_node;
1225
1226 //yu.dong@20240416[T106BUG-551][codec] codec 8311 sleep power consumption does not go down
1227
1228 dev_info(dev, "%s:start!\n", __func__);
1229
1230 if(dev == NULL){
1231 dev_err(dev, "%s:dev is null ,return\n",__func__);
1232 return -EINVAL;
1233
1234 }
1235 dev_info(dev, "%s: get clk pinctrl\n", __func__);
1236
1237 pctrl = devm_pinctrl_get(dev);
1238 if (IS_ERR(pctrl)) {
1239 dev_warn(dev, "Failed to get clk_test pins\n");
1240 pctrl = NULL;
1241 return -EINVAL;
1242 }
1243
1244
1245 state0 = pinctrl_lookup_state(pctrl, "clk_out2");
1246 if (IS_ERR(state0)) {
1247 devm_pinctrl_put(pctrl);
1248 dev_err(dev, "missing clk_out\n");
1249 return -EINVAL;
1250 }
1251
1252 dev_info(dev, "%s: select pinctrl\n", __func__);
1253
1254 if ( pinctrl_select_state(pctrl, state0) < 0) {
1255 //devm_pinctrl_put(pctrl);
1256 dev_err(dev, "setting clk_out failed\n");
1257 ret = -EINVAL;
1258 goto err_put_pinctrl;
1259 }
1260
1261
1262 dev_info(dev, "%s: get clk\n", __func__);
1263
1264
1265
1266
1267 clk = of_clk_get_by_name(np, "clk_out2");
1268 if (IS_ERR(clk)) {
1269 dev_err(dev, "Could not get clk_out\n");
1270 ret = PTR_ERR(clk);
1271 goto err_put_pinctrl;
1272 }
1273
1274
1275
1276#if 1
1277 dev_info(dev, "%s: clk prepare\n", __func__);
1278
1279 ret = clk_prepare(clk);
1280 if (ret) {
1281 dev_err(dev, "failed to clk prepare\n");
1282 goto err_put_clk;
1283
1284 }
1285
1286#else
1287 dev_info(dev, "%s: clk enable\n", __func__);
1288
1289 ret = clk_prepare_enable(clk);
1290 if (ret) {
1291 dev_err(dev, "failed to enable clkout");
1292 goto err_put_clk;
1293
1294 }
1295
1296#endif
1297 if(info != NULL){
1298
1299 dev_info(dev, "%s: set drvdata\n", __func__);
1300 info->pctrl = pctrl;
1301 info->state0 = state0;
1302 info->clk = clk;
1303 }
1304 else{
1305 dev_info(dev, "%s: info is null\n", __func__);
1306
1307 }
1308 dev_info(dev, "%s: init clkout end!\n",__func__);
1309 return 0;
1310err_put_clk:
1311 clk_put(clk);
1312err_put_pinctrl:
1313 devm_pinctrl_put(pctrl);
1314
1315
1316 return ret;
1317
1318
1319}
1320
1321//yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment start
1322static void es8311_reinit(struct snd_soc_component *component, struct es8311_private *es8311)
1323{
1324 pr_info("%s:begin!\n", __func__);
1325
1326/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
1327 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
1328#ifdef CONFIG_USE_TOP_TDM
1329 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0xB0);
1330#else
1331 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x30);
1332#endif
1333 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x00);
1334 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x10);
1335 //snd_soc_component_write(component, ES8311_ADC_REG16, 0x24);
1336 snd_soc_component_write(component, ES8311_ADC_REG16, 0x21);
1337 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x10);
1338 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x00);
1339 snd_soc_component_write(component, ES8311_SDPIN_REG09, 0x00);
1340 snd_soc_component_write(component, ES8311_SDPOUT_REG0A, 0x00);
1341 snd_soc_component_write(component, ES8311_SYSTEM_REG0B, 0x00);
1342 snd_soc_component_write(component, ES8311_SYSTEM_REG0C, 0x00);
1343
1344 if (ES8311_AVDD == ES8311_1V8) {
1345 snd_soc_component_write(component, ES8311_SYSTEM_REG10, 0x61);
1346 snd_soc_component_write(component, ES8311_SYSTEM_REG11, 0x7B);
1347 } else {
1348 snd_soc_component_write(component, ES8311_SYSTEM_REG10, 0x03);
1349 snd_soc_component_write(component, ES8311_SYSTEM_REG11, 0x57);
1350 }
1351
1352 if (es8311->mclk_src == ES8311_MCLK_PIN) {
1353 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x3F);
1354 } else {
1355 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0xBF);
1356 }
1357
1358 if (es8311->mastermode == 1) {
1359 snd_soc_component_write(component, ES8311_RESET_REG00, 0xC0);
1360 } else {
1361 snd_soc_component_write(component, ES8311_RESET_REG00, 0x80);
1362 }
1363
1364 usleep_range(1500, 3000);
1365 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0x01);
1366
1367 if (es8311->mclkinv == true) {
1368 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG01, 0x40, 0x40);
1369 } else {
1370 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG01, 0x40, 0x00);
1371 }
1372
1373 if (es8311->sclkinv == true) {
1374 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG06, 0x20, 0x20);
1375 } else {
1376 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG06, 0x20, 0x00);
1377 }
1378
1379 snd_soc_component_write(component, ES8311_SYSTEM_REG14, 0x1A);
1380
1381 if (es8311->dmic_enable == true) {
1382 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14, 0x40, 0x40);
1383 } else {
1384 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14, 0x40, 0x00);
1385 }
1386 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x00);
1387 snd_soc_component_write(component, ES8311_SYSTEM_REG13, 0x10);
1388 snd_soc_component_write(component, ES8311_SYSTEM_REG0E, 0x02);
1389 snd_soc_component_write(component, ES8311_SYSTEM_REG0F, 0x7F);
1390 snd_soc_component_write(component, ES8311_ADC_REG15, 0x40);
1391 snd_soc_component_write(component, ES8311_ADC_REG1B, 0x0A);
1392 snd_soc_component_write(component, ES8311_ADC_REG1C, 0x6A);
1393 snd_soc_component_write(component, ES8311_DAC_REG37, 0x48);
1394 snd_soc_component_write(component, ES8311_ADC_REG17, 0xBF);
1395 snd_soc_component_write(component, ES8311_DAC_REG32, 0xBF);
1396#ifdef CONFIG_USE_TOP_TDM
1397 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x1A);
1398 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x1b);
1399 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x1b);
1400 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x00);
1401 snd_soc_component_write(component, ES8311_SDPIN_REG09,0x0F);
1402 snd_soc_component_write(component, ES8311_SDPOUT_REG0A,0x0F);
1403#else
1404 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x98);
1405 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x1b);
1406 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x1b);
1407 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0xbb);
1408#endif
1409/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
1410 msleep(100);
1411 es8311_set_bias_level(component, SND_SOC_BIAS_STANDBY);
1412 pr_info("%s:end!\n", __func__);
1413}
1414
1415extern int zx29_i2s_config_sleep_pin(void);
1416extern int zx29_i2s_config_default_pin(void);
1417
1418static int component_open(struct snd_soc_component *component,
1419 struct snd_pcm_substream *substream)
1420{
1421
1422 int ret = 0;
1423 struct es8311_private *info = snd_soc_component_get_drvdata(component);
1424 printk("Enter into %s()\n", __func__);
1425
1426 if(info->clk != NULL){
1427
1428 ret = clk_enable(info->clk);
1429 if (ret) {
1430 pr_err( "failed to enable clkout");
1431 }
1432 }
1433/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1434 ret = zx29_i2s_config_default_pin();
1435 if(ret < 0) {
1436 pr_err("%s select state failure %d !! \n", __func__, ret);
1437 }
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1438 es8311_reinit(component, info);
1439/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
1440 pr_info("%s:clk en end!\n",__func__);
1441 return ret;
1442
1443
1444
1445
1446}
1447static int component_close(struct snd_soc_component *component,
1448 struct snd_pcm_substream *substream)
1449{
1450
1451 int ret = 0;
1452 struct es8311_private *info = snd_soc_component_get_drvdata(component);
1453 printk("Enter into %s()\n", __func__);
1454
1455
1456 if(info->clk != NULL){
1457
1458 clk_disable(info->clk);
1459
1460 }
1461 pr_info("%s:clk dis end!\n",__func__);
1462/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1463 ret = zx29_i2s_config_sleep_pin();
1464 if(ret < 0) {
1465 pr_err("%s select state failure %d !! \n", __func__, ret);
1466 }
xf.li2f424182024-08-20 00:47:34 -0700[diff] [blame]1467/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
1468 return ret;
1469}
1470
1471//yu.dong@20240416[ZXW-268]Added codec re-initialization for power down and I2S default configuration adjustment end
1472static const struct snd_soc_component_driver soc_component_dev_es8311 = {
1473 .probe = es8311_probe,
1474 .remove = es8311_remove,
1475 .suspend = es8311_suspend,
1476 .resume = es8311_resume,
1477 .set_bias_level = es8311_set_bias_level,
1478 .suspend_bias_off = 1,
1479 .idle_bias_on = 1,
1480
1481 .controls = es8311_snd_controls,
1482 .num_controls = ARRAY_SIZE(es8311_snd_controls),
1483 .dapm_widgets = es8311_dapm_widgets,
1484 .num_dapm_widgets = ARRAY_SIZE(es8311_dapm_widgets),
1485 .dapm_routes = es8311_dapm_routes,
1486 .num_dapm_routes = ARRAY_SIZE(es8311_dapm_routes),
1487 .open = component_open,
1488 .close = component_close,
1489};
1490
1491static struct regmap_config es8311_regmap = {
1492 .name= "ES8311",
1493 .reg_bits = 8,
1494 .val_bits = 8,
1495
1496 .max_register = ES8311_MAX_REGISTER,
1497
1498 .volatile_reg = es8311_volatile_register,
1499 .writeable_reg = es8311_writable_register,
1500 .readable_reg = es8311_readable_register,
1501 .cache_type = REGCACHE_RBTREE,
1502};
1503
1504#ifdef CONFIG_OF
1505static const struct of_device_id es8311_if_dt_ids[] = {
1506 {.compatible = "everest,es8311", },
1507 { }
1508};
1509MODULE_DEVICE_TABLE(of, es8311_if_dt_ids);
1510#endif
1511
1512static void es8311_i2c_shutdown(struct i2c_client *i2c)
1513{
1514 printk("Enter into %s()\n", __func__);
1515
1516}
1517
1518static u32 cur_reg;
1519
1520static ssize_t es8311_show(struct device *dev,
1521 struct device_attribute *attr, char *_buf)
1522{
1523 int ret;
1524 int i ;
1525 int reg_max = 256;
1526 for( i = 0;i < reg_max;i++){
1527 //sprintf(_buf, "%s(): get reg0x%04x=0x%04x\n", __func__, i,
1528 //snd_soc_component_read(es8311_component, i));
1529 printk("%s(): get reg0x%04x=0x%04x\n", __func__, i,
1530 snd_soc_component_read(es8311_component, i));
1531 }
1532 return 0;
1533}
1534
1535static ssize_t es8311_store(struct device *dev, struct device_attribute *attr,
1536 const char *buf, size_t count)
1537{
1538 int val = 0, flag = 0;
1539 u8 i = 0, reg, num, value_w, value_r;
1540
1541 val = simple_strtol(buf, NULL, 16);
1542 flag = (val >> 16) & 0xFF;
1543
1544 if (flag) {
1545 reg = (val >> 8) & 0xFF;
1546 value_w = val & 0xFF;
1547 pr_info("\nWrite: start REG:0x%02x,val:0x%02x,count:0x%02x\n",
1548 reg, value_w, flag);
1549 while (flag--) {
1550 snd_soc_component_write(es8311_component, reg, value_w);
1551 pr_info("Write 0x%02x to REG:0x%02x\n", value_w, reg);
1552 reg++;
1553 }
1554 } else {
1555 reg = (val >> 8) & 0xFF;
1556 num = val & 0xff;
1557 pr_info("\nRead: start REG:0x%02x,count:0x%02x\n", reg, num);
1558 do {
1559 value_r = 0;
1560 value_r = snd_soc_component_read(es8311_component, reg);
1561 pr_info("REG[0x%02x]: 0x%02x;\n", reg, value_r);
1562 reg++;
1563 i++;
1564 } while (i < num);
1565 }
1566
1567 return count;
1568}
1569
1570static DEVICE_ATTR(es8311, 0664, es8311_show, es8311_store);
1571
1572static ssize_t codec_info_show(struct kobject *kobj, struct kobj_attribute *attr,
1573 char *buf)
1574{
1575
1576 ssize_t count = 0;
1577
1578 struct device *dev = container_of(kobj, struct device, kobj);
1579 struct es8311_private *info;
1580 char cmd_str[16] = {0};
1581
1582 int ret,i;
1583 int regs, rege;
1584 unsigned int val;
1585 struct snd_soc_component *component;
1586
1587
1588 info = (struct es8311_private *) dev_get_drvdata(dev);
1589
1590 component = snd_soc_lookup_component(dev,NULL);
1591 if (!component){
1592 pr_err(" %s:(%d), snd_soc_lookup_component fail !\n", __func__, __LINE__ );
1593
1594 return count;
1595 }
1596
1597 dev_info(dev," %s:(%d),snd_soc_lookup_component ,name=%s\n", __func__, __LINE__, component->name);
1598 //info->component = component;
1599
1600
1601 regs = 0x0;
1602 rege = 0x45;
1603
1604 for (i = regs; i < rege; i++) {
1605
1606 //val = snd_soc_component_read(info->component, i);
1607 regmap_read(info->regmap, i, &val);
1608
1609 dev_info(dev,"cocec reg read ,Reg(0x%x)=0x%x \n",i, val);
1610 }
1611
1612 return count;
1613
1614
1615}
1616
1617
1618static ssize_t codec_info_store(struct kobject *kobj, struct kobj_attribute *attr,
1619 const char *buf, size_t n)
1620
1621{
1622 ssize_t ret =0;
1623 unsigned int val = 0;
1624 struct device *dev = container_of(kobj, struct device, kobj);
1625 struct es8311_private *info;
1626 char cmd_str[17] = {0};
1627
1628 u32 param1 = 0,param2 = 0,param3 = 0;
1629
1630 int i;
1631
1632 struct snd_soc_component *component;
1633
1634 info = (struct es8311_private *) dev_get_drvdata(dev);
1635
1636 component = snd_soc_lookup_component(dev, NULL);
1637 if (!component){
1638 pr_err(" %s:(%d), snd_soc_lookup_component fail !\n", __func__, __LINE__ );
1639
1640 return n;
1641 }
1642
1643 dev_info(dev," %s:(%d),snd_soc_lookup_component ,name=%s\n", __func__, __LINE__, component->name);
1644 //info->component = component;
1645
1646 //dev_info(dev, "pcieinfo_store name %s \n", pdev->name);
1647
1648
1649 sscanf(buf, "%16s %x %x %x", cmd_str,&param1,&param2,&param3);
1650 dev_info(dev, "cmd_str:%s,param1:%x,param2:%x,param3:%x\n",cmd_str,param1,param2,param3);
1651
1652
1653
1654 dev_info(dev, "%s:cmd_str=%s \n",__func__,cmd_str);
1655
1656 ret = strcmp(cmd_str,"reg_read");
1657 if( ret == 0)
1658 {
1659 dev_info(dev, "reg_read start\n");
1660 if(param1 > 0xff){
1661 dev_err(dev, "reg_read param invalidate fail,param1=%d \n",param1);
1662 return -1;
1663 }
1664
1665 //val = snd_soc_component_read(info->component, param1);
1666 regmap_read(info->regmap, param1,&val);
1667
1668
1669 dev_info(dev, "reg_read reg(%d)=0x%x \n",param1,val);
1670
1671
1672 }
1673
1674 ret = strcmp(cmd_str,"reg_write");
1675 if( ret == 0)
1676 {
1677 //u32 offset = param1;
1678 //u32 mask = param2;
1679 dev_info(dev, "reg_write start\n");
1680
1681 if(param1 > 0xff){
1682 dev_err(dev, "reg_write param invalidate fail,param1=%d \n",param1);
1683 return -1;
1684 }
1685 val = param2;
1686 //ret = snd_soc_component_write(info->component, param1, val);
1687 regmap_write(info->regmap, param1, val);
1688 if (ret){
1689 pr_err(" %s:(%d), cocec reg write fail - ret=%d\n", __func__, __LINE__ ,ret);
1690 //return ret;
1691 }
1692
1693 dev_info(dev, "reg_write reg(%d)=0x%x \n",param1,val);
1694
1695 }
1696
1697
1698
1699 return n;
1700
1701}
1702#define CODEC_ATTR(_name) \
1703static struct kobj_attribute _name##_attr = { \
1704 .attr = { \
1705 .name = __stringify(_name), \
1706 .mode = 0644, \
1707 }, \
1708 .show = _name##_show, \
1709 .store = _name##_store, \
1710}
1711
1712
1713
1714CODEC_ATTR(codec_info);
1715
1716static struct attribute *es8311_debug_attrs[] = {
1717 &dev_attr_es8311.attr,
1718 &codec_info_attr.attr,
1719 NULL,
1720};
1721
1722static struct attribute_group es8311_debug_attr_group = {
1723 .name = "es8311_debug",
1724 .attrs = es8311_debug_attrs,
1725};
1726
1727static int es8311_i2c_probe(struct i2c_client *i2c_client,
1728 const struct i2c_device_id *id)
1729{
1730 struct es8311_private *es8311;
1731 int ret = -1;
1732 unsigned int val;
1733
1734 pr_info("Enter into %s\n", __func__);
1735 es8311 = devm_kzalloc(&i2c_client->dev,
1736 sizeof(*es8311), GFP_KERNEL);
1737 if (es8311 == NULL)
1738 return -ENOMEM;
1739
1740 es8311->dmic_enable = false; // dmic interface disabled
1741 /* the edge of lrck is always at the falling edge of mclk */
1742 es8311->mclkinv = false;
1743 /* the edge of lrck is always at the falling edge of sclk */
1744 es8311->sclkinv = false;
1745
1746 i2c_set_clientdata(i2c_client, es8311);
1747 es8311->regmap = devm_regmap_init_i2c(i2c_client, &es8311_regmap);
1748 if (IS_ERR(es8311->regmap)) {
1749 ret = PTR_ERR(es8311->regmap);
1750 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1751 return ret;
1752 }
1753 es8311->dev = &i2c_client->dev;
1754 /* verify that we have an es8311 */
1755 ret = regmap_read(es8311->regmap, ES8311_CHD1_REGFD, &val);
1756 if (ret < 0) {
1757 dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n",
1758 i2c_client->addr);
1759 return ret;
1760 }
1761 /* The first ID should be 0x83 */
1762 if (val != 0x83) {
1763 dev_err(&i2c_client->dev, "device at addr %X is not an es8311\n",
1764 i2c_client->addr);
1765 return -ENODEV;
1766 }
1767 ret = regmap_read(es8311->regmap, ES8311_CHD2_REGFE, &val);
1768 /* The NEXT ID should be 0x11 */
1769 if (val != 0x11) {
1770 dev_err(&i2c_client->dev, "device at addr %X is not an es8311\n",
1771 i2c_client->addr);
1772 return -ENODEV;
1773 }
1774 es8311_data = es8311;
1775
1776 es8311->pctrl = NULL;
1777 es8311->state0 = NULL;
1778 es8311->clk = NULL;
1779/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes start */
1780#ifndef CONFIG_USE_TOP_TDM
1781 clkout_init_pinctrl(&i2c_client->dev);
1782#endif
1783/* yu.dong@20240508[ZXW-277]Modified Platform CODEC ES8311 Compatible with I2S and TDM Modes end */
1784 ret = snd_soc_register_component(&i2c_client->dev,
1785 &soc_component_dev_es8311,
1786 &es8311_dai,
1787 1);
1788 if (ret < 0) {
1789 kfree(es8311);
1790 return ret;
1791 }
1792
1793 pr_info("Enter into %s-----4\n", __func__);
1794 ret = sysfs_create_group(&i2c_client->dev.kobj,
1795 &es8311_debug_attr_group);
1796 if (ret)
1797 pr_err("failed to create attr group\n");
1798
1799
1800 printk("%s end\n", __func__);
1801
1802
1803 return ret;
1804}
1805
1806static const struct i2c_device_id es8311_i2c_id[] = {
1807 {"es8311", 0 },
1808 { }
1809};
1810MODULE_DEVICE_TABLE(i2c, es8311_i2c_id);
1811
1812static struct i2c_driver es8311_i2c_driver = {
1813 .driver = {
1814 .name = "es8311",
1815 .owner = THIS_MODULE,
1816 .of_match_table = es8311_if_dt_ids,
1817 },
1818 .shutdown = es8311_i2c_shutdown,
1819 .probe = es8311_i2c_probe,
1820 .id_table = es8311_i2c_id,
1821};
1822
1823static int __init es8311_init(void)
1824{
1825 int ret;
1826 printk("Enter into %s()\n", __func__);
1827
1828 ret = i2c_add_driver(&es8311_i2c_driver);
1829 if (ret != 0)
1830 pr_info("Failed to register es8311 i2c driver\n");
1831 return ret;
1832}
1833
1834static void __exit es8311_exit(void)
1835{
1836 printk("Enter into %s()\n", __func__);
1837
1838 return i2c_del_driver(&es8311_i2c_driver);
1839}
1840
1841late_initcall(es8311_init);
1842module_exit(es8311_exit);
1843
1844MODULE_DESCRIPTION("ASoC es8311 driver");
1845MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>");
1846MODULE_LICENSE("GPL");
1847
1848