| l.yang | b8fdece | 2024-10-10 14:56:17 +0800 | [diff] [blame] | 1 | |
| l.yang | afee7ee | 2024-10-10 15:01:10 +0800 | [diff] [blame^] | 2 | #define _USE_VEHICLE_DC |
| 3 | #include "ram_base_config_7520v3.h" |
| 4 | |
| l.yang | b8fdece | 2024-10-10 14:56:17 +0800 | [diff] [blame] | 5 | #define GIC_DIST_BASE (0xF2000000) |
| 6 | #define GIC_RDIST_BASE (0xF2040000) |
| 7 | |
| 8 | #define REAL_TXT_ADDR (CONFIG_PHYS_OFFSET + 0x8000) |
| l.yang | afee7ee | 2024-10-10 15:01:10 +0800 | [diff] [blame^] | 9 | #define DTB_ADDR (DDR_BASE_CAP_DTB_ADDR) |
| l.yang | b8fdece | 2024-10-10 14:56:17 +0800 | [diff] [blame] | 10 | |
| 11 | secure_init: |
| 12 | |
| 13 | #if 0 |
| 14 | mov r5, r0 |
| 15 | mov r6, r1 |
| 16 | mov r7, r2 |
| 17 | #endif |
| 18 | mov r4, lr |
| 19 | |
| 20 | #if 1 |
| 21 | /* use r0--r4 only */ |
| 22 | bl get_core_id |
| 23 | mov r1, r0 |
| 24 | bl get_cluster_id |
| 25 | mov r2, r0 |
| 26 | |
| 27 | ldr r3, =GIC_DIST_BASE |
| 28 | ldr r0, =0x50 |
| 29 | str r0, [r3] |
| 30 | |
| 31 | ldr r3, =GIC_RDIST_BASE |
| 32 | lsl r2, r2, #2 |
| 33 | add r1, r1, r2 |
| 34 | lsl r1, r1, #17 |
| 35 | |
| 36 | add r1, r1, r3 |
| 37 | add r1, r1, #0x14 |
| 38 | |
| 39 | LDR R0, [R1] |
| 40 | LDR R2, =0xfffffffd |
| 41 | AND R0, R0, R2 |
| 42 | STR R0, [R1] |
| 43 | |
| 44 | LDR R2, = 0xFFFFFFFB |
| 45 | wait: |
| 46 | LDR R0, [R1] |
| 47 | AND R0, R0, R2 |
| 48 | CMP R0, #0 |
| 49 | BNE wait |
| 50 | |
| 51 | SUB R1, R1, #0x14 |
| 52 | LDR R2, =0x10080 |
| 53 | ADD R1, R1, R2 |
| 54 | LDR R2, =0xFFFFFFFF |
| 55 | STR R2, [R1] |
| 56 | #endif |
| 57 | |
| 58 | MRS R0, CPSR |
| 59 | BIC R0, #0x1F |
| 60 | ORR R0, #0xD6 |
| 61 | MSR CPSR_c, R0 |
| 62 | |
| 63 | MOV r3, #0xD |
| 64 | MCR p15,#0x6,r3,c12,c12,#5 |
| 65 | MCR p15,0,r3,c12,c12,#5 |
| 66 | |
| 67 | MRC p15,0,r1,c1,c1,0 |
| 68 | MOV r2, r1 |
| 69 | ORR r2, #0x1 |
| 70 | MCR p15,0,r2,c1,c1,0 |
| 71 | |
| 72 | MCR p15,#0x4,r3,c12,c9,#5 |
| 73 | |
| 74 | MRS R0, CPSR |
| 75 | BIC R0, #0x1F |
| 76 | ORR R0, #0xD3 |
| 77 | MSR CPSR_c, R0 |
| 78 | |
| 79 | #if 0 |
| 80 | mov r0, r5 |
| 81 | mov r1, r6 |
| 82 | mov r2, r7 |
| 83 | #else |
| 84 | ldr r0, =0 |
| 85 | ldr r1, =REAL_TXT_ADDR |
| 86 | ldr r2, =DTB_ADDR |
| 87 | #endif |
| 88 | mov lr, r4 |
| 89 | |
| 90 | ret lr |
| 91 | ENDPROC(secure_init) |
| 92 | |
| 93 | get_core_id: |
| 94 | MRC p15, 0, R0, c0, c0, 5 |
| 95 | AND R0, R0, #0xFF |
| 96 | BX R14 |
| 97 | ENDPROC(get_core_id) |
| 98 | |
| 99 | get_cluster_id: |
| 100 | MRC p15, 0, r0, c0, c0, 5 |
| 101 | AND r0, r0, #0xFF00 |
| 102 | LSR r0, r0, #0x8 |
| 103 | BX lr |
| 104 | ENDPROC(get_cluster_id) |