xf.li | ed996a2 | 2025-03-13 23:49:05 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * zx234290.h -- ZTE ZX234290 |
| 3 | * |
| 4 | * Copyright 2016 ZTE Corporation. |
| 5 | * |
| 6 | * Author: yuxiang |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef __LINUX_MFD_ZX234290_H |
| 16 | #define __LINUX_MFD_ZX234290_H |
| 17 | |
| 18 | #include <linux/mutex.h> |
| 19 | |
| 20 | #define zx234290_rails(_name) "zx234290_"#_name |
| 21 | |
| 22 | #define u8 unsigned char |
| 23 | |
| 24 | /* LDOs */ |
| 25 | #define ZX234290_REG_LDO1 0 |
| 26 | #define ZX234290_REG_LDO2 1 |
| 27 | #define ZX234290_REG_LDO3 2 |
| 28 | #define ZX234290_REG_LDO4 3 |
| 29 | #define ZX234290_REG_LDO5 4 |
| 30 | #define ZX234290_REG_LDO6 5 |
| 31 | #define ZX234290_REG_LDO7 6 |
| 32 | #define ZX234290_REG_LDO8 7 |
| 33 | |
| 34 | #define ZX234290_REG_LDO9 8 |
| 35 | #define ZX234290_REG_LDO10 9 |
| 36 | #define ZX234290_REG_LDO11 10 |
| 37 | |
| 38 | /* DCDC's */ |
| 39 | #define ZX234290_REG_DCDC0 11 |
| 40 | #define ZX234290_REG_DCDC1 12 |
| 41 | #define ZX234290_REG_DCDC2 13 |
| 42 | #define ZX234290_REG_DCDC3 14 |
| 43 | #define ZX234290_REG_DCDC4 15 |
| 44 | |
| 45 | /* ZX regulator type list */ |
| 46 | #ifndef ZX234290_PWR_FAUL_PROCESS |
| 47 | #define ZX234290_PWR_FAUL_PROCESS |
| 48 | #define ZX234290_INT_LDO_FAUL 0 |
| 49 | #define ZX234290_INT_BUCK_FAUL 1 |
| 50 | #endif |
| 51 | |
| 52 | #define ZX234290_INT_EOADC 2 /* xxxx x100 */ |
| 53 | #define ZX234290_INT_PWRON_SHORT 3 |
| 54 | #define ZX234290_INT_PWRON_LONG 4 |
| 55 | #define ZX234290_INT_PWRON 5 |
| 56 | |
| 57 | #define ZX234290_INT_RTC_ALRM 8 |
| 58 | #define ZX234290_INT_BATT_DET 10 |
| 59 | #define ZX234290_INT_RTC_MIN 11 |
| 60 | #define ZX234290_INT_RTC_HOUR 12 |
| 61 | |
| 62 | #define ZX234290_NUM_IRQ 13 |
| 63 | |
| 64 | #ifdef ZX234290_PWR_FAUL_PROCESS |
| 65 | int zx234290_register_client(struct notifier_block *nb); |
| 66 | int zx234290_unregister_client(struct notifier_block *nb); |
| 67 | int zx234290_notifier_call_chain(unsigned long val, void *v); |
| 68 | #endif |
| 69 | |
| 70 | #if 0 |
| 71 | /* External controls requests */ |
| 72 | enum zx234290_ext_control { |
| 73 | PWR_REQ_INPUT_NONE = 0x00000000, |
| 74 | PWR_REQ_INPUT_PREQ1 = 0x00000001, |
| 75 | PWR_REQ_INPUT_PREQ2 = 0x00000002, |
| 76 | PWR_REQ_INPUT_PREQ3 = 0x00000004, |
| 77 | PWR_OFF_ON_SLEEP = 0x00000008, |
| 78 | PWR_ON_ON_SLEEP = 0x00000010, |
| 79 | }; |
| 80 | #endif |
| 81 | |
| 82 | #if 0 |
| 83 | typedef enum |
| 84 | { |
| 85 | RESET_TO_NORMAL, /*reset to idle*/ |
| 86 | RESET_TO_CHARGER, /*reset to charger*/ |
| 87 | RESET_TO_ALRAM, /*reset to alarm*/ |
| 88 | RESET_TO_EXCEPTRESET, |
| 89 | MAX_RESET_TYPE, |
| 90 | } T_ZDrvSys_RESET_TYPE; |
| 91 | #endif |
| 92 | |
| 93 | typedef enum _T_ZDrvPmic_Enable{ |
| 94 | PM_DISABLE = 0, |
| 95 | PM_ENABLE, |
| 96 | PM_ENABLE_NOT_SUPPORT = -100, |
| 97 | PM_ENABLE_MAX_STATUS = -255 |
| 98 | } T_ZDrvPmic_Enable; |
| 99 | |
| 100 | typedef enum _T_ZDrvPmic_NrmMode{ |
| 101 | PM_NRMMODE_AUTO = 0, |
| 102 | PM_NRMMODE_PFM, |
| 103 | PM_NRMMODE_PWM, |
| 104 | PM_NRMMODE_NOT_SUPPORT = -100, |
| 105 | PM_NRMMODE_MAX_STATUS = -255 |
| 106 | }T_ZDrvPmic_NrmMode; |
| 107 | |
| 108 | typedef enum _T_ZDrvPmic_SlpMode{ |
| 109 | PM_SLPMODE_AUTO_NORMAL = 0, //auto in dcdc, normal in ldo |
| 110 | PM_SLPMODE_ECO_NRMV, //normal voltage |
| 111 | PM_SLPMODE_ECO_SLPV, //sleep voltage |
| 112 | PM_SLPMODE_OFF, //OFF |
| 113 | PM_SLPMODE_NOT_SUPPORT = -100, |
| 114 | PM_SLPMODE_MAX_STATUS = -255 |
| 115 | }T_ZDrvPmic_SlpMode; |
| 116 | |
| 117 | //consumer |
| 118 | typedef enum _T_ZDrvPmic_Regulator{ |
| 119 | VCORE0 = 0, |
| 120 | VCORE1, |
| 121 | VDDR, |
| 122 | VMMC, |
| 123 | VSD0, |
| 124 | VSD1, |
| 125 | VIO_LO, |
| 126 | VIO_HI, |
| 127 | VUSB_0V9, |
| 128 | VUSB_3V3, |
| 129 | VPLL_LO, |
| 130 | VPLL_HI, |
| 131 | VSIM1, |
| 132 | VSIM2, |
| 133 | VRF_LO, |
| 134 | VRF_HI, |
| 135 | VRF_SW, |
| 136 | VPA, |
| 137 | VCTCXO1, |
| 138 | VCTCXO2, |
| 139 | VSSBUF, |
| 140 | VRTC, |
| 141 | } T_ZDrvPmic_Regulator; |
| 142 | |
| 143 | typedef enum _T_ZDrvPmic_Vcore{ |
| 144 | PM_VOLT_0_6750 = 0, |
| 145 | PM_VOLT_0_6875 , |
| 146 | PM_VOLT_0_7000 , |
| 147 | PM_VOLT_0_7125 , |
| 148 | PM_VOLT_0_7250 = 0x04, |
| 149 | PM_VOLT_0_7375 , |
| 150 | PM_VOLT_0_7500 , |
| 151 | PM_VOLT_0_7625 , |
| 152 | PM_VOLT_0_7750 = 0x08 , |
| 153 | PM_VOLT_0_7875 , |
| 154 | PM_VOLT_0_8000 , |
| 155 | PM_VOLT_0_8125 , |
| 156 | PM_VOLT_0_8250 = 0x0c, |
| 157 | PM_VOLT_0_8375 , |
| 158 | PM_VOLT_0_8500 , |
| 159 | PM_VOLT_0_8625 , |
| 160 | PM_VOLT_0_8750 = 0x10 , |
| 161 | PM_VOLT_0_8875 , |
| 162 | PM_VOLT_0_9000 , |
| 163 | PM_VOLT_0_9125 , |
| 164 | PM_VOLT_0_9250 = 0x14, |
| 165 | PM_VOLT_0_9375 , |
| 166 | PM_VOLT_0_9500 , |
| 167 | PM_VOLT_0_9625 , |
| 168 | PM_VOLT_0_9750 = 0x18 , |
| 169 | PM_VOLT_0_9875 , |
| 170 | PM_VOLT_1_0000 , |
| 171 | PM_VOLT_1_0125 , |
| 172 | PM_VOLT_1_0250 = 0x1c, |
| 173 | PM_VOLT_1_0375 , |
| 174 | PM_VOLT_1_0500 , |
| 175 | PM_VOLT_1_0625 , |
| 176 | PM_VOLT_1_0750 = 0x20 , |
| 177 | PM_VOLT_1_0875 , |
| 178 | PM_VOLT_1_1000 , |
| 179 | PM_VOLT_1_1125 , |
| 180 | PM_VOLT_1_1250 = 0x24, |
| 181 | PM_VOLT_1_1375 , |
| 182 | PM_VOLT_1_1500 , |
| 183 | PM_VOLT_1_1625 , |
| 184 | PM_VOLT_1_1750 = 0x28 , |
| 185 | PM_VOLT_1_1875 , |
| 186 | PM_VOLT_1_2000 , |
| 187 | PM_VOLT_1_2125 , |
| 188 | PM_VOLT_1_2250 = 0x2c, |
| 189 | PM_VOLT_1_2375 , |
| 190 | PM_VOLT_1_2500 = 0x2e, |
| 191 | PM_VOLT_1_2625 , |
| 192 | PM_VOLT_1_2750 = 0x30 , |
| 193 | PM_VOLT_1_2875 , |
| 194 | PM_VOLT_1_3000 , |
| 195 | PM_VOLT_1_3125 , |
| 196 | PM_VOLT_1_3250 = 0x34, |
| 197 | PM_VOLT_1_3375 , |
| 198 | PM_VOLT_1_3500 , |
| 199 | PM_VOLT_1_3625 , |
| 200 | PM_VOLT_1_3750 = 0x38 , |
| 201 | PM_VOLT_1_3875 , |
| 202 | PM_VOLT_1_4000 , |
| 203 | PM_VOLT_1_4125 , |
| 204 | PM_VOLT_1_4250 = 0x3c, |
| 205 | PM_VOLT_1_4375 , |
| 206 | PM_VOLT_1_4500 , |
| 207 | PM_VOLT_1_4625 , |
| 208 | PM_VOLT_1_4750 = 0x40 , |
| 209 | PM_VOLT_1_4875 , |
| 210 | PM_VOLT_1_5000 , |
| 211 | PM_VOLT_1_5125 , |
| 212 | PM_VOLT_1_5250 = 0x44, |
| 213 | PM_VOLT_1_5375 , |
| 214 | PM_VOLT_1_5500 , |
| 215 | PM_VOLT_1_5625 , |
| 216 | PM_VOLT_1_5750 = 0x48, |
| 217 | PM_VOLT_1_5875 , |
| 218 | PM_VOLT_1_6000 , |
| 219 | PM_VOLT_1_6125 , |
| 220 | PM_VOLT_1_6250 = 0x4c, |
| 221 | PM_VOLT_1_6375 , |
| 222 | PM_VOLT_1_6500 , |
| 223 | PM_VOLT_1_6625 , |
| 224 | PM_VOLT_1_6750 = 0x50, |
| 225 | PM_VOLT_1_6875 , |
| 226 | PM_VOLT_1_7000 , |
| 227 | PM_VOLT_1_7125 , |
| 228 | PM_VOLT_1_7250 = 0x54, |
| 229 | PM_VOLT_1_7375 , |
| 230 | PM_VOLT_1_7500 , |
| 231 | PM_VOLT_1_7625 , |
| 232 | PM_VOLT_1_7750 = 0x58, |
| 233 | PM_VOLT_1_7875 , |
| 234 | PM_VOLT_1_8000 , |
| 235 | PM_VOLT_1_8125 , |
| 236 | PM_VOLT_1_8250 = 0x5c, |
| 237 | PM_VOLT_1_8375 , |
| 238 | PM_VOLT_1_8500 , |
| 239 | PM_VOLT_1_8625 , |
| 240 | PM_VOLT_1_8750 = 0x60 , |
| 241 | PM_VOLT_1_8875 , |
| 242 | PM_VOLT_1_9000 , |
| 243 | PM_VOLT_1_9125 , |
| 244 | PM_VOLT_1_9250 = 0x64, |
| 245 | PM_VOLT_1_9375 , |
| 246 | PM_VOLT_1_9500 , |
| 247 | PM_VOLT_1_9625 , |
| 248 | PM_VOLT_1_9750 = 0x68, |
| 249 | PM_VOLT_1_9875 , |
| 250 | PM_VOLT_2_0000 , |
| 251 | PM_VOLT_2_0125 , |
| 252 | PM_VOLT_2_0250 = 0x6c, |
| 253 | PM_VOLT_2_0375 , |
| 254 | PM_VOLT_2_0500 , |
| 255 | PM_VOLT_2_0625 , |
| 256 | PM_VOLT_2_0750 = 0x70, |
| 257 | PM_VOLT_2_0875 , |
| 258 | PM_VOLT_2_1000 , |
| 259 | PM_VOLT_2_1125 , |
| 260 | PM_VOLT_2_1250 = 0x74, |
| 261 | PM_VOLT_2_1375 , |
| 262 | PM_VOLT_2_1500 , |
| 263 | PM_VOLT_2_1625 , |
| 264 | PM_VOLT_2_1750 = 0x78 , |
| 265 | PM_VOLT_2_1875 , |
| 266 | PM_VOLT_2_2000 , |
| 267 | PM_VOLT_2_2125 , |
| 268 | PM_VOLT_2_2250 = 0x7c, |
| 269 | PM_VOLT_2_2375 , |
| 270 | PM_VOLT_2_2500 , |
| 271 | PM_VOLT_2_2625 , |
| 272 | PM_VOLT_2_2750 = 0x80, |
| 273 | PM_VOLT_2_2875 , |
| 274 | PM_VOLT_2_3000 , |
| 275 | PM_VOLT_2_3125 , |
| 276 | PM_VOLT_2_3250 = 0x84, |
| 277 | PM_VOLT_2_3375 , |
| 278 | PM_VOLT_2_3500 , |
| 279 | PM_VOLT_2_3625 , |
| 280 | PM_VOLT_2_3750 = 0x88 , |
| 281 | PM_VOLT_2_3875 , |
| 282 | PM_VOLT_2_4000 , |
| 283 | PM_VOLT_2_4125 , |
| 284 | PM_VOLT_2_4250 = 0x8c, |
| 285 | PM_VOLT_2_4375 , |
| 286 | PM_VOLT_2_4500 , |
| 287 | PM_VOLT_2_4625 , |
| 288 | PM_VOLT_2_4750 = 0x90, |
| 289 | PM_VOLT_2_4875 , |
| 290 | PM_VOLT_2_5000 , |
| 291 | PM_VOLT_2_5125 , |
| 292 | PM_VOLT_2_5250 = 0x94, |
| 293 | PM_VOLT_2_5375 , |
| 294 | PM_VOLT_2_5500 , |
| 295 | PM_VOLT_2_5625 , |
| 296 | PM_VOLT_2_5750 = 0x98 , |
| 297 | PM_VOLT_2_5875 , |
| 298 | PM_VOLT_2_6000 , |
| 299 | PM_VOLT_2_6125 , |
| 300 | PM_VOLT_2_6250 = 0x9c, |
| 301 | PM_VOLT_2_6375 , |
| 302 | PM_VOLT_2_6500 , |
| 303 | PM_VOLT_2_6625 , |
| 304 | PM_VOLT_2_6750 = 0xa0, |
| 305 | PM_VOLT_2_6875 , |
| 306 | PM_VOLT_2_7000 , |
| 307 | PM_VOLT_2_7125 , |
| 308 | PM_VOLT_2_7250 = 0xa4, |
| 309 | PM_VOLT_2_7375 , |
| 310 | PM_VOLT_2_7500 , |
| 311 | PM_VOLT_2_7625 , |
| 312 | PM_VOLT_2_7750 = 0xa8, |
| 313 | PM_VOLT_2_7875 , |
| 314 | PM_VOLT_2_8000 , |
| 315 | PM_VOLT_2_8125 , |
| 316 | PM_VOLT_2_8250 = 0xac, |
| 317 | PM_VOLT_2_8375 , |
| 318 | PM_VOLT_2_8500 , |
| 319 | PM_VOLT_2_8625 , |
| 320 | PM_VOLT_2_8750 = 0xb0, |
| 321 | PM_VOLT_2_8875 , |
| 322 | PM_VOLT_2_9000 , |
| 323 | PM_VOLT_2_9125 , |
| 324 | PM_VOLT_2_9250 = 0xb4, |
| 325 | PM_VOLT_2_9375 , |
| 326 | PM_VOLT_2_9500 , |
| 327 | PM_VOLT_2_9625 , |
| 328 | PM_VOLT_2_9750 = 0xb8, |
| 329 | PM_VOLT_2_9875 , |
| 330 | PM_VOLT_3_0000 , |
| 331 | PM_VOLT_3_0125 , |
| 332 | PM_VOLT_3_0250 = 0xbc, |
| 333 | PM_VOLT_3_0375 , |
| 334 | PM_VOLT_3_0500 , |
| 335 | PM_VOLT_3_0625 , |
| 336 | PM_VOLT_3_0750 = 0xc0 , |
| 337 | PM_VOLT_3_0875 , |
| 338 | PM_VOLT_3_1000 , |
| 339 | PM_VOLT_3_1125 , |
| 340 | PM_VOLT_3_1250 = 0xc4, |
| 341 | PM_VOLT_3_1375 , |
| 342 | PM_VOLT_3_1500 , |
| 343 | PM_VOLT_3_1625 , |
| 344 | PM_VOLT_3_1750 = 0xc8 , |
| 345 | PM_VOLT_3_1875 , |
| 346 | PM_VOLT_3_2000 , |
| 347 | PM_VOLT_3_2125 , |
| 348 | PM_VOLT_3_2250 = 0xcc, |
| 349 | PM_VOLT_3_2375 , |
| 350 | PM_VOLT_3_2500 , |
| 351 | PM_VOLT_3_2625 , |
| 352 | PM_VOLT_3_2750 = 0xd0 , |
| 353 | PM_VOLT_3_2875 , |
| 354 | PM_VOLT_3_3000 , |
| 355 | PM_VOLT_3_3125 , |
| 356 | PM_VOLT_3_3250 = 0xd4, |
| 357 | PM_VOLT_3_3375 , |
| 358 | PM_VOLT_3_3500 , |
| 359 | PM_VOLT_3_3625 , |
| 360 | PM_VOLT_3_3750 = 0xd8 , |
| 361 | PM_VOLT_3_3875 , |
| 362 | |
| 363 | PM_VOLT_NOT_SUPPORT = -100, |
| 364 | PM_VOLT_MAX_STATUS = -255, |
| 365 | } T_ZDrvPmic_Voltage; |
| 366 | |
| 367 | |
| 368 | |
| 369 | |
| 370 | /** |
| 371 | * struct zx234290 - zx234290 sub-driver chip access routines |
| 372 | */ |
| 373 | |
| 374 | struct zx234290 { |
| 375 | struct device *dev; |
| 376 | /* for read/write acces */ |
| 377 | struct mutex io_mutex; |
| 378 | |
| 379 | /* For device IO interfaces: I2C or SPI */ |
| 380 | void *control_data; |
| 381 | |
| 382 | int (*read)(struct zx234290 *zx234290, u8 reg, int size, void *dest); |
| 383 | int (*write)(struct zx234290 *zx234290, u8 reg, int size, void *src); |
| 384 | |
| 385 | /* Client devices */ |
| 386 | struct zx234290_regulator *regulator; |
| 387 | |
| 388 | /* GPIO Handling */ |
| 389 | |
| 390 | /* IRQ Handling */ |
| 391 | struct mutex irq_lock; |
| 392 | int chip_irq; |
| 393 | int irq_base; |
| 394 | struct irq_domain * irq_domain; |
| 395 | int irq_num; |
| 396 | unsigned int irq_mask; |
| 397 | }; |
| 398 | int zx234290_i2c_read_simple(u8 reg, void *dest); |
| 399 | int zx234290_i2c_write_simple(u8 reg, void *src); |
| 400 | int zx234290_i2c_read_simple_PSM(u8 reg, void *dest); |
| 401 | int zx234290_i2c_write_simple_PSM(u8 reg, void *src); |
| 402 | |
| 403 | int zx234290_reg_read(struct zx234290 *zx234290, u8 reg); |
| 404 | int zx234290_reg_write(struct zx234290 *zx234290, u8 reg, u8 val); |
| 405 | int zx234290_device_init(struct zx234290 *zx234290); |
| 406 | void zx234290_device_exit(struct zx234290 *zx234290); |
| 407 | |
| 408 | |
| 409 | /*regulator defines*/ |
| 410 | #if 1 |
| 411 | /* |
| 412 | * List of registers for ZX234290 |
| 413 | */ |
| 414 | |
| 415 | ///////////////////////////////////////////////// |
| 416 | /*slave address 0x12*/ |
| 417 | ///////////////////////////////////////////////// |
| 418 | #define ZX234290_I2C_SLAVE_ADDR0 (0x12) |
| 419 | |
| 420 | /* interrupt and mask */ |
| 421 | #define ZX234290_REG_ADDR_INTA 0x00 /* INTERRUPT */ |
| 422 | #define ZX234290_REG_ADDR_INTB 0x01 |
| 423 | #define ZX234290_REG_ADDR_INTA_MASK 0x02 |
| 424 | #define ZX234290_REG_ADDR_INTB_MASK 0x03 |
| 425 | |
| 426 | /* interrupt status */ |
| 427 | #define ZX234290_REG_ADDR_STSA 0x04 |
| 428 | #define ZX234290_REG_ADDR_STSB 0x05 |
| 429 | #define ZX234290_REG_ADDR_STS_STARTUP 0x06 |
| 430 | |
| 431 | /* adc & softon select */ |
| 432 | #define ZX234290_REG_ADDR_SYS_CTRL 0x07 /*0x8 0x9Ìø¹ý*/ |
| 433 | |
| 434 | /* bucks normal voltage and sleep voltage */ |
| 435 | #define ZX234290_REG_ADDR_BUCK1_VOL 0x0A /*[00xx xxxx]0xB 0xC Ìø¹ý*/ |
| 436 | #define ZX234290_REG_ADDR_BUCK1_SLPVOL 0x0D |
| 437 | |
| 438 | /* bucks mode */ |
| 439 | #define ZX234290_REG_ADDR_BUCK1_MODE 0x0E /* [xx] NRM [xx] SLP [00 00]*/ |
| 440 | #define ZX234290_REG_ADDR_BUCK23_MODE 0x0F /*[xx]BUCK3 NRM [xx]BUCK3 SLP [xx]BUCK2 NRM [xx]BUCK2 SLP*/ |
| 441 | #define ZX234290_REG_ADDR_BUCK4_MODE 0x11 /* [00 00] [xx] NRM [xx] SLP 0X10Ìø¹ý */ |
| 442 | |
| 443 | /* ldo normal voltage */ |
| 444 | #define ZX234290_REG_ADDR_LDO12_VOL 0x12 /* [xxxx xxxx] */ |
| 445 | #define ZX234290_REG_ADDR_LDO34_VOL 0x13 |
| 446 | #define ZX234290_REG_ADDR_LDO56_VOL 0x14 |
| 447 | #define ZX234290_REG_ADDR_LDO78_VOL 0x15 |
| 448 | #define ZX234290_REG_ADDR_LDO9_VOL 0x16 /* [xxxx 0000] */ |
| 449 | #define ZX234290_REG_ADDR_LDO10_RTCLDO_VOL 0x17 /* [00 xx]VORTC [xx xx]LDO10*/ |
| 450 | |
| 451 | |
| 452 | #define ZX234290_REG_ADDR_BUCK2_VOL 0x1A /* BUCK2 VLOT */ |
| 453 | |
| 454 | /* ldo sleep voltage */ |
| 455 | #define ZX234290_REG_ADDR_LDO12_SLPVOL 0x18 /* [xx xx]ldo2 [xx xx]ldo1*/ |
| 456 | #define ZX234290_REG_ADDR_LDO3_SLPVOL 0x19 /* [00 00] [xx xx] */ |
| 457 | #define ZX234290_REG_ADDR_LDO78_SLPVOL 0x1B /* [xx xx]ldo8 [xx xx]ldo7*/ |
| 458 | #define ZX234290_REG_ADDR_LDO9_SLPVOL 0x1C /* [xx xx] [00 00] */ |
| 459 | #define ZX234290_REG_ADDR_LDO10_SLPVOL 0x1D /* [00 00] [xx xx] */ |
| 460 | |
| 461 | /* ldo mode */ |
| 462 | #define ZX234290_REG_ADDR_LDO1234_MODE 0x1E /* [xx][xx][xx][xx]*/ |
| 463 | #define ZX234290_REG_ADDR_LDO5678_MODE 0x1F |
| 464 | #define ZX234290_REG_ADDR_LDO910_MODE 0x20 /* [00] [xx] [xx] [00] */ |
| 465 | |
| 466 | /* ldo enable */ |
| 467 | #define ZX234290_REG_ADDR_LDO_EN1 0x21 /* LDO8-1 */ |
| 468 | #define ZX234290_REG_ADDR_LDO_EN2 0x22 /* [xx xx]BUCK4-1, [0xx0]LDO10-9*/ |
| 469 | |
| 470 | /* adc code */ |
| 471 | #define ZX234290_REG_ADDR_VBATADC_MSB 0x23 /*[xxxx xxxx]*/ |
| 472 | #define ZX234290_REG_ADDR_VBATADC_LSB 0x24 /*[xxxx 0000]*/ |
| 473 | #define ZX234290_REG_ADDR_ADC1_MSB 0x25 |
| 474 | #define ZX234290_REG_ADDR_ADC1_LSB 0x26 |
| 475 | #define ZX234290_REG_ADDR_ADC2_MSB 0x27 |
| 476 | #define ZX234290_REG_ADDR_ADC2_LSB 0x28 |
| 477 | |
| 478 | /* sink control */ |
| 479 | #define ZX234297_REG_ADDR_SINK_CONTROL 0x29 |
| 480 | |
| 481 | /* rtc */ |
| 482 | #define ZX234290_REG_ADDR_RTC_CTRL1 0x30 |
| 483 | #define ZX234290_REG_ADDR_RTC_CTRL2 0x31 |
| 484 | |
| 485 | /* date and time */ |
| 486 | #define ZX234290_REG_ADDR_SECONDS 0x32 |
| 487 | #define ZX234290_REG_ADDR_MINUTES 0x33 |
| 488 | #define ZX234290_REG_ADDR_HOURS 0x34 |
| 489 | #define ZX234290_REG_ADDR_DAY 0x35 |
| 490 | #define ZX234290_REG_ADDR_WEEK 0x36 |
| 491 | #define ZX234290_REG_ADDR_MONTH 0x37 |
| 492 | #define ZX234290_REG_ADDR_YEAR 0x38 |
| 493 | |
| 494 | /* alarm */ |
| 495 | #define ZX234290_REG_ADDR_ALARM_MINUTE 0x39 |
| 496 | #define ZX234290_REG_ADDR_ALARM_HOUR 0x3A |
| 497 | #define ZX234290_REG_ADDR_ALARM_DAY 0x3B |
| 498 | #define ZX234290_REG_ADDR_ALARM_WEEK 0x3C |
| 499 | #define ZX234290_REG_ADDR_ALARM_SECOND 0x3D |
| 500 | |
| 501 | #define ZX234290_REG_ADDR_TIMER_CTRL 0x3E |
| 502 | #define ZX234290_REG_ADDR_TIMER_CNT 0x3F |
| 503 | |
| 504 | /* enable ldo output discharge resistance */ |
| 505 | #define ZX234290_REG_ADDR_EN_DISCH1 0x40 |
| 506 | #define ZX234290_REG_ADDR_EN_DISCH2 0x41 |
| 507 | |
| 508 | /* power key control */ |
| 509 | #define ZX234290_REG_ADDR_PWRKEY_CONTROL1 0x42 |
| 510 | #define ZX234290_REG_ADDR_PWRKEY_CONTROL2 0x43 |
| 511 | |
| 512 | #define ZX234290_REG_ADDR_VERSION 0x44 |
| 513 | |
| 514 | /*fault status*/ |
| 515 | #define ZX234290_REG_ADDR_BUCK_FAULT_STATUS 0x45 |
| 516 | #define ZX234290_REG_ADDR_LDO_FAULT_STATUS 0x46 |
| 517 | |
| 518 | #define ZX234290_REG_ADDR_BUCK_INT_MASK 0x47 |
| 519 | #define ZX234290_REG_ADDR_LDO_INT_MASK 0x48 |
| 520 | |
| 521 | #define ZX234290_REG_ADDR_USER_RESERVED 0x50 |
| 522 | #define ZX234290_REG_ADDR_GMT_TESTING 0xf1 |
| 523 | |
| 524 | #define ZX234290_MAX_REGISTER 0x51 //yuxiang ? |
| 525 | |
| 526 | /*0x04 status A*/ |
| 527 | #define ZX234290_STATUSA_POWERON_LSH (5) |
| 528 | #define ZX234290_STATUSA_POWERON_WID (1) |
| 529 | #define ZX234290_STATUSA_EOCADC_LSH (2) |
| 530 | #define ZX234290_STATUSA_EOCADC_WID (1) |
| 531 | |
| 532 | /* 0x06 STATUS REG -- STARTUP */ |
| 533 | #define ZX234290_SYSPOR_STATUS_PWRON_STARTUP (0x1 << 0) /* PWR ON button */ |
| 534 | #define ZX234290_SYSPOR_STATUS_RTC_ALARM_STARTUP (0x1 << 1) |
| 535 | #define ZX234290_SYSPOR_STATUS_PSHOLD_STARTUP (0x1 << 2) |
| 536 | #define ZX234290_SYSPOR_STATUS_PWRONLLP_STARTUP (0x1 << 3) |
| 537 | |
| 538 | /* discharger */ |
| 539 | #define ZX234290_DISCHG1_LSB_LSH (0) |
| 540 | #define ZX234290_DISCHG1_LSB_WID (4) |
| 541 | |
| 542 | #define ZX234290_DISCHG1_MSB_LSH (5) |
| 543 | #define ZX234290_DISCHG1_MSB_WID (2) |
| 544 | |
| 545 | #define ZX234290_DISCHG2_LSH (0) |
| 546 | #define ZX234290_DISCHG2_WID (8) |
| 547 | |
| 548 | |
| 549 | /* BUCK VOLTAGE */ |
| 550 | #define ZX234290_BUCK01_VSEL_LSH (0) |
| 551 | #define ZX234290_BUCK01_VSEL_WID (6) |
| 552 | |
| 553 | /* BUCK SLEEP VOLTAGE */ |
| 554 | #define ZX234290_BUCK01_SLEEP_VSEL_LSH (0) |
| 555 | #define ZX234290_BUCK01_SLEEP_VSEL_WID (6) |
| 556 | |
| 557 | /* BUCKS MODE CTROL */ |
| 558 | #define ZX234290_REGULATOR_MODE_WID (2) |
| 559 | |
| 560 | #define ZX234290_BUCK0_SLPMODE_LSH (0) |
| 561 | #define ZX234290_BUCK0_NRMMODE_LSH (2) |
| 562 | #define ZX234290_BUCK1_SLPMODE_LSH (4) |
| 563 | #define ZX234290_BUCK1_NRMMODE_LSH (6) /*[7:6]*/ |
| 564 | #define ZX234290_BUCK2_SLPMODE_LSH (0) |
| 565 | #define ZX234290_BUCK2_NRMMODE_LSH (2) |
| 566 | #define ZX234290_BUCK3_SLPMODE_LSH (4) |
| 567 | #define ZX234290_BUCK3_NRMMODE_LSH (6) |
| 568 | #define ZX234290_BUCK4_SLPMODE_LSH (0) |
| 569 | #define ZX234290_BUCK4_NRMMODE_LSH (2) |
| 570 | |
| 571 | /* LDO MODE, ONLY SLEEP MODE */ |
| 572 | #define ZX234290_LDO1_SLPMODE_LSH (0) |
| 573 | #define ZX234290_LDO2_SLPMODE_LSH (2) |
| 574 | #define ZX234290_LDO3_SLPMODE_LSH (4) |
| 575 | #define ZX234290_LDO4_SLPMODE_LSH (6) |
| 576 | #define ZX234290_LDO5_SLPMODE_LSH (0) |
| 577 | #define ZX234290_LDO6_SLPMODE_LSH (2) |
| 578 | #define ZX234290_LDO7_SLPMODE_LSH (4) |
| 579 | #define ZX234290_LDO8_SLPMODE_LSH (6) |
| 580 | #define ZX234290_LDO9_SLPMODE_LSH (2) |
| 581 | #define ZX234290_LDO10_SLPMODE_LSH (4) |
| 582 | //#define ZX234290_LDO11_SLPMODE_LSH (6) |
| 583 | |
| 584 | /* LDO VOLTAGE SELECT */ |
| 585 | #define ZX234290_LDO_VSEL_WID (4) |
| 586 | |
| 587 | #define ZX234290_LDO1_VSEL_LSH (0) /* [3:0] */ |
| 588 | #define ZX234290_LDO2_VSEL_LSH (4) /* [7:4] */ |
| 589 | #define ZX234290_LDO3_VSEL_LSH (0) |
| 590 | #define ZX234290_LDO4_VSEL_LSH (4) |
| 591 | #define ZX234290_LDO5_VSEL_LSH (0) |
| 592 | #define ZX234290_LDO6_VSEL_LSH (4) |
| 593 | #define ZX234290_LDO7_VSEL_LSH (0) |
| 594 | #define ZX234290_LDO8_VSEL_LSH (4) |
| 595 | #define ZX234290_LDO9_VSEL_LSH (4) |
| 596 | #define ZX234290_LDO10_VSEL_LSH (0) |
| 597 | #define ZX234290_LDO11_VSEL_LSH (0) /* [3:0] */ |
| 598 | |
| 599 | #define ZX234290_VORTC_VSEL_WID (2) |
| 600 | #define ZX234290_VORTC_VSEL_LSH (4) /* [5][4] */ |
| 601 | #define ZX234290_LDO5_VSEL_WID (2) /* [1][0]*/ |
| 602 | |
| 603 | |
| 604 | /* LDO SLEEP VOLTAGE */ |
| 605 | #define ZX234290_BUCK2_VSEL_WID (5) |
| 606 | |
| 607 | #define ZX234290_BUCK2_VSEL_LSH (0) |
| 608 | |
| 609 | #define ZX234290_LDO1_SLP_VSEL_LSH (0) /* [3:0] */ |
| 610 | #define ZX234290_LDO2_SLP_VSEL_LSH (4) /* [7:4] */ |
| 611 | #define ZX234290_LDO3_SLP_VSEL_LSH (0) |
| 612 | #define ZX234290_LDO7_SLP_VSEL_LSH (0) |
| 613 | #define ZX234290_LDO8_SLP_VSEL_LSH (0) |
| 614 | #define ZX234290_LDO11_SLP_VSEL_LSH (0) /* [3:0] */ |
| 615 | |
| 616 | /* ENABLE 0x21-0x22 */ |
| 617 | #define ZX234290_LDOS_ON_WID (1) |
| 618 | |
| 619 | #define ZX234290_LDO1_ON_LSH (0) |
| 620 | #define ZX234290_LDO2_ON_LSH (1) |
| 621 | #define ZX234290_LDO3_ON_LSH (2) |
| 622 | #define ZX234290_LDO4_ON_LSH (3) |
| 623 | #define ZX234290_LDO5_ON_LSH (4) |
| 624 | #define ZX234290_LDO6_ON_LSH (5) |
| 625 | #define ZX234290_LDO7_ON_LSH (6) |
| 626 | #define ZX234290_LDO8_ON_LSH (7) |
| 627 | |
| 628 | #define ZX234290_LDO9_ON_LSH (1) |
| 629 | #define ZX234297_LDO9_ON_LSH (0) |
| 630 | #define ZX234290_LDO10_ON_LSH (2) |
| 631 | #define ZX234297_LDO10_ON_LSH (1) |
| 632 | #define ZX234290_BUCK1_ON_LSH (4) |
| 633 | #define ZX234290_BUCK2_ON_LSH (5) |
| 634 | #define ZX234290_BUCK3_ON_LSH (6) |
| 635 | #define ZX234290_BUCK4_ON_LSH (7) |
| 636 | |
| 637 | /* LONG PRESSED TIME */ |
| 638 | #define ZX234290_PWRON_TIME_LSH (0) |
| 639 | #define ZX234290_PWRON_TIME_WID (2) |
| 640 | #define ZX234290_PWRON_LONGPRESS_EN_LSH (2) |
| 641 | #define ZX234290_PWRON_LONGPRESS_EN_WID (1) |
| 642 | #define ZX234290_PWRON_LLP_TODO_LSH (3) /* LLP long long pressed */ |
| 643 | #define ZX234290_PWRON_LLP_TODO_WID (1) |
| 644 | |
| 645 | /* sys ctrol 0x07 */ |
| 646 | #define ZX234290_SINK1_EN_LSH (0) |
| 647 | #define ZX234290_SINK1_EN_WID (1) |
| 648 | #define ZX234290_SINK2_EN_LSH (1) |
| 649 | #define ZX234290_SINK2_EN_WID (1) |
| 650 | #define ZX234290_ADC1_EN_LSH (4) |
| 651 | #define ZX234290_ADC1_EN_WID (1) |
| 652 | #define ZX234290_ADC2_EN_LSH (3) |
| 653 | #define ZX234290_ADC2_EN_WID (1) |
| 654 | #define ZX234290_ADC_START_LSH (5) |
| 655 | #define ZX234290_ADC_START_WID (1) |
| 656 | #define ZX234290_SOFTON_LSH (7) |
| 657 | |
| 658 | /* 0x08 */ |
| 659 | #define ZX234290_SINK2_CURSEL_LSH (0) |
| 660 | #define ZX234290_SINK2_CURSEL_WID (4) |
| 661 | /* 0x09 */ |
| 662 | #define ZX234290_SINK1_CURSEL_LSH (0) |
| 663 | #define ZX234290_SINK1_CURSEL_WID (4) |
| 664 | |
| 665 | /* 0x20 */ |
| 666 | #define ZX234297_SINK1_SLP_MODE_LSH (6) |
| 667 | #define ZX234297_SINK2_SLP_MODE_LSH (7) |
| 668 | #define ZX234297_SINK_SLP_MODE_WID (1) |
| 669 | /* 0x22 */ |
| 670 | #define ZX234297_SINK1_ON_LSH (2) |
| 671 | #define ZX234297_SINK2_ON_LSH (3) |
| 672 | #define ZX234297_SINK_ON_WID (1) |
| 673 | /* 0x29 */ |
| 674 | #define ZX234297_SINK1_CURRENT_LSH (0) |
| 675 | #define ZX234297_SINK2_CURRENT_LSH (4) |
| 676 | #define ZX234297_SINK_CURRENT_WID (4) |
| 677 | |
| 678 | #define ZX234290_LDO_RSTERR_LSH (0) |
| 679 | #define ZX234290_LDO_RSTERR_WID (1) |
| 680 | |
| 681 | #endif /* end of ZX234290 */ |
| 682 | |
| 683 | #define ZX234290_BITFVAL(var, lsh) ( (var) << (lsh) ) |
| 684 | #define ZX234290_BITFMASK(wid, lsh) ( ((1U << (wid)) - 1) << (lsh) ) |
| 685 | #define ZX234290_BITFEXT(var, wid, lsh) ((var & ZX234290_BITFMASK(wid, lsh)) >> (lsh)) |
| 686 | |
| 687 | /* VBA - BUCK1 6bit */ |
| 688 | typedef enum _T_ZDrvZx234290_VbuckA |
| 689 | { |
| 690 | VBUCKA_0_675 = 0x00, |
| 691 | VBUCKA_0_700 = 0x02, |
| 692 | VBUCKA_0_750 = 0x06, |
| 693 | VBUCKA_0_800 = 0x0a, |
| 694 | VBUCKA_0_850 = 0x0e, |
| 695 | VBUCKA_0_900 = 0x12,/*default*/ |
| 696 | VBUCKA_0_950 = 0x16, |
| 697 | VBUCKA_1_000 = 0x1a, |
| 698 | VBUCKA_1_050 = 0x1e, |
| 699 | VBUCKA_1_100 = 0x22, |
| 700 | VBUCKA_1_150 = 0x26, |
| 701 | VBUCKA_1_200 = 0x2a, |
| 702 | VBUCKA_1_250 = 0x2e, |
| 703 | |
| 704 | VBUCKA_MAX |
| 705 | |
| 706 | }T_ZDrvZx234290_VbuckA; |
| 707 | |
| 708 | /* VBC - BUCK2 */ |
| 709 | typedef enum _T_ZDrvZx234290_VbuckC |
| 710 | { |
| 711 | VBUCKC_0_850 = 0x00, |
| 712 | VBUCKC_0_900 = 0x02, |
| 713 | VBUCKC_0_950 = 0x04, |
| 714 | VBUCKC_1_000 = 0x06, |
| 715 | VBUCKC_1_050 = 0x08, |
| 716 | VBUCKC_1_100 = 0x0a, |
| 717 | VBUCKC_1_150 = 0x0c, |
| 718 | VBUCKC_1_200 = 0x0e,/*default*/ |
| 719 | VBUCKC_1_250 = 0x10, |
| 720 | VBUCKC_1_300 = 0x12, |
| 721 | VBUCKC_1_350 = 0x14, |
| 722 | VBUCKC_1_400 = 0x16, |
| 723 | VBUCKC_1_450 = 0x18, |
| 724 | VBUCKC_1_500 = 0x1a, |
| 725 | VBUCKC_1_550 = 0x1c, |
| 726 | VBUCKC_1_600 = 0x1e, |
| 727 | |
| 728 | VBUCKC_MAX |
| 729 | |
| 730 | }T_ZDrvZx234290_VbuckC; |
| 731 | |
| 732 | /* VLA - ldo1/9/10 */ |
| 733 | typedef enum _T_ZDrvZx234290_VldoA |
| 734 | { |
| 735 | VLDOA_0_725 = 0, |
| 736 | VLDOA_0_750 = 1, |
| 737 | VLDOA_0_775 = 2, |
| 738 | VLDOA_0_800 = 3, |
| 739 | VLDOA_0_825 = 4, |
| 740 | VLDOA_0_850 = 5, |
| 741 | VLDOA_0_875 = 6, |
| 742 | VLDOA_0_900 = 7, |
| 743 | VLDOA_0_925 = 8, |
| 744 | VLDOA_0_950 = 9, |
| 745 | VLDOA_0_975 = 10, |
| 746 | VLDOA_1_000 = 11, |
| 747 | VLDOA_1_025 = 12, |
| 748 | VLDOA_1_050 = 13, |
| 749 | VLDOA_1_075 = 14, |
| 750 | VLDOA_1_100 = 15, |
| 751 | |
| 752 | VLDOA_MAX |
| 753 | |
| 754 | }T_ZDrvZx234290_VldoA; |
| 755 | |
| 756 | /* VLB - ldo5 2bit */ |
| 757 | typedef enum _T_ZDrvZx234290_VldoB |
| 758 | { |
| 759 | VLDOB_3_300 = 0, |
| 760 | VLDOB_3_150 = 1, |
| 761 | VLDOB_3_000 = 2, |
| 762 | VLDOB_1_800 = 3, /* 11 */ |
| 763 | |
| 764 | VLDOB_MAX |
| 765 | |
| 766 | }T_ZDrvZx234290_VldoB; |
| 767 | |
| 768 | /* VLC - ldo2/ldo3 */ |
| 769 | typedef enum _T_ZDrvZx234290_VldoC |
| 770 | { |
| 771 | VLDOC_0_750 = 0, |
| 772 | VLDOC_0_800 = 1, |
| 773 | VLDOC_0_850 = 2, |
| 774 | VLDOC_0_900 = 3, |
| 775 | VLDOC_0_950 = 4, |
| 776 | VLDOC_1_000 = 5, |
| 777 | VLDOC_1_050 = 6, |
| 778 | VLDOC_1_100 = 7, |
| 779 | VLDOC_1_200 = 8, |
| 780 | VLDOC_1_500 = 9, |
| 781 | VLDOC_1_800 = 10, |
| 782 | VLDOC_2_000 = 11, |
| 783 | VLDOC_2_500 = 12, |
| 784 | VLDOC_2_800 = 13, |
| 785 | VLDOC_3_000 = 14, |
| 786 | VLDOC_3_300 = 15, |
| 787 | |
| 788 | VLDOC_MAX |
| 789 | |
| 790 | }T_ZDrvZx234290_VldoC; |
| 791 | |
| 792 | /* VLD - ldo4/6/7/8 */ |
| 793 | typedef enum _T_ZDrvZx234290_VldoD |
| 794 | { |
| 795 | VLDOD_1_400 = 0, |
| 796 | VLDOD_1_500 = 1, |
| 797 | VLDOD_1_600 = 2, |
| 798 | VLDOD_1_800 = 3, |
| 799 | VLDOD_1_850 = 4, |
| 800 | VLDOD_2_000 = 5, |
| 801 | VLDOD_2_050 = 6, |
| 802 | VLDOD_2_500 = 7, |
| 803 | VLDOD_2_550 = 8, |
| 804 | VLDOD_2_700 = 9, |
| 805 | VLDOD_2_750 = 10, |
| 806 | VLDOD_2_800 = 11, |
| 807 | VLDOD_2_850 = 12, |
| 808 | VLDOD_2_900 = 13, |
| 809 | VLDOD_2_950 = 14, |
| 810 | VLDOD_3_000 = 15, |
| 811 | |
| 812 | VLDOD_MAX |
| 813 | |
| 814 | }T_ZDrvZx234290_VldoD; |
| 815 | |
| 816 | /* VORTC 2bit */ |
| 817 | typedef enum _T_ZDrvZx234290_VldoE |
| 818 | { |
| 819 | VLDOE_1_800 = 0, |
| 820 | VLDOE_2_500 = 1, |
| 821 | VLDOE_3_000 = 2, |
| 822 | VLDOE_3_300 = 3, /* 11 */ |
| 823 | |
| 824 | VLDOE_MAX |
| 825 | |
| 826 | }T_ZDrvZx234290_VldoE; |
| 827 | |
| 828 | /* VLF - ldo10 */ |
| 829 | typedef enum _T_ZDrvZx234297_VldoF |
| 830 | { |
| 831 | VLDOF_0_800 = 0, |
| 832 | VLDOF_0_850 = 1, |
| 833 | VLDOF_0_900 = 2, |
| 834 | VLDOF_0_950 = 3, |
| 835 | |
| 836 | VLDOF_1_000 = 4, |
| 837 | VLDOF_1_050 = 5, |
| 838 | VLDOF_1_100 = 6, |
| 839 | VLDOF_1_200 = 7, |
| 840 | |
| 841 | VLDOF_1_300 = 8, |
| 842 | VLDOF_1_400 = 9, |
| 843 | VLDOF_1_500 = 10, |
| 844 | VLDOF_1_800 = 11, |
| 845 | |
| 846 | VLDOF_2_500 = 12, |
| 847 | VLDOF_2_800 = 13, |
| 848 | VLDOF_3_000 = 14, |
| 849 | VLDOF_3_300 = 15, |
| 850 | |
| 851 | VLDOF_MAX |
| 852 | |
| 853 | }T_ZDrvZx234297_VldoF; |
| 854 | |
| 855 | /* BUCK3/4 EXTERNAL ADJUSTABLE */ |
| 856 | |
| 857 | typedef enum _T_ZDrvZx234290_LDO_ENABLE |
| 858 | { |
| 859 | LDO_ENABLE_OFF = 0, /* 00 */ |
| 860 | LDO_ENABLE_ON = 1, /* 10 */ |
| 861 | |
| 862 | LDO_AVTICE_MAX |
| 863 | }T_ZDrvZx234290_LDO_ENABLE; |
| 864 | |
| 865 | |
| 866 | /* |
| 867 | ¹ØÓÚ BUCKSµÄģʽ£¬·ÖΪÕý³£Ä£Ê½Óë˯Ãßģʽ£¬ Õý³£Ä£Ê½Ö»¹Ø×¢PFM/PWM£¬²»¹Ø×¢¿ª¹Ø¡£ |
| 868 | ˯Ãßģʽ¹Ø×¢PFM/PWM/ECO/OFF/NRM£¬Ó¦¸Ã½âÊÍΪ ˯ÃßģʽµÄ״̬²»½ö¹Ø×¢PWM/PFM£¬ |
| 869 | ¶øÇÒ¹Ø×¢´ò¿ª¹Ø±Õ£¬³ýÁËOFF£¬ÆäËû¶¼ÊÇÔÚ¿ª×ŵÄÇé¿öϵÄģʽ£»¶øÄ¬ÈÏ¿ªµÄÇé¿öÔòÊÇ |
| 870 | NRMMODE£¬µçѹÓÃ˯Ãßµçѹ£» |
| 871 | ¶øLDOSµÄ˯Ãßģʽ£¬Ò»ÑùÓëÕý³£Ä£Ê½²»Ïà¸É¡£ÆäÒ²ÓÐNRM/ECO/OFFÕ⼸ÖÖ״̬ |
| 872 | */ |
| 873 | |
| 874 | /* BUCK1/2/3/4 NORMAL MODE */ |
| 875 | typedef enum _T_ZDrvZx234290_BUCK_NRMMODE |
| 876 | { |
| 877 | BUCK_NRM_AUTO_WITH_ECO = 0, /* 00/01 AUTO PWM/PSM ECO */ |
| 878 | BUCK_NRM_FORCE_PWM = 2, /* 10 FORCE PWM */ |
| 879 | BUCK_NRM_AUTO_WITHOUT_ECO = 3, /* 00/01 AUTO PWM/PSM ECO */ |
| 880 | BUCK_NRMMODE_MAX |
| 881 | }T_ZDrvZx234290_BUCK_NRMMODE; |
| 882 | |
| 883 | /* BUCK1 SLPMODE */ |
| 884 | typedef enum _T_ZDrvZx234290_BUCK1_SLPMODE |
| 885 | { |
| 886 | BUCK1_SLP_AUTO_WITHOUT_ECO = 0, /* 00/11 AUTO PWM/PFM */ |
| 887 | BUCK1_SLP_AUTO_ECO = 1, /*BUCK1_SLP_AUTO_ECO_VOLT output voltage configred by FBDC1[5:0]*/ |
| 888 | BUCK1_SLP_AUTO_ECO_SLP = 2, /* output voltage configred by FBDC1_SLP[5:0]*/ |
| 889 | BUCK1_SLP_SHUTDOWN = 3, /* 11 OFF */ |
| 890 | BUCK1_SLPMODE_MAX |
| 891 | }T_ZDrvZx234290_BUCK1_SLPMODE; |
| 892 | |
| 893 | /* BUCK2/3/4 SLPMODE */ |
| 894 | typedef enum _T_ZDrvZx234290_BUCK234_SLPMODE |
| 895 | { |
| 896 | BUCK234_SLP_AUTO_WITHOUT_ECO = 0, /* 00 AUTO PWM/PFM without eco*/ |
| 897 | BUCK234_SLP_ECO_WITH_ECO = 1, /* 01Óë10¾ùÊÇ ECO */ |
| 898 | BUCK234_SLP_SHUTDOWN = 3, /* 11 OFF */ |
| 899 | |
| 900 | BUCK234_SLPMODE_MAX |
| 901 | }T_ZDrvZx234290_BUCK234_SLPMODE; |
| 902 | |
| 903 | /* LDO1/2/3/7/8/9/10 SLPMODE */ |
| 904 | typedef enum _T_ZDrvZx234290_LDOA_SLPMODE |
| 905 | { |
| 906 | LDOA_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */ |
| 907 | LDOA_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */ |
| 908 | LDOA_SLP_ECO_VOLT_SLP = 2, /* VOLDOx_SLP[3:0] */ |
| 909 | LDOA_SLP_SHUTDOWN = 3, /* 11 OFF */ |
| 910 | LDOA_SLPMODE_MAX |
| 911 | }T_ZDrvZx234290_LDOA_SLPMODE; |
| 912 | |
| 913 | /* LDO4/5/6/ SLPMODE */ |
| 914 | typedef enum _T_ZDrvZx234290_LDOB_SLPMODE |
| 915 | { |
| 916 | LDOB_SLP_NRM_MODE = 0, /* VOLDOx[3:0] */ |
| 917 | LDOB_SLP_ECO_VOLT = 1, /* VOLDOx[3:0] */ |
| 918 | LDOB_SLP_NRM_MODE_VOLT = 2, /* VOLDOx[3:0] */ |
| 919 | LDOB_SLP_SHUTDOWN = 3, /* 11 OFF */ |
| 920 | LDOB_SLPMODE_MAX |
| 921 | }T_ZDrvZx234290_LDOB_SLPMODE; |
| 922 | |
| 923 | typedef enum _T_ZDrvZx234290_LdoDischarger |
| 924 | { |
| 925 | DISCHARGER_LDO_9 = 0, |
| 926 | DISCHARGER_LDO_10, |
| 927 | DISCHARGER_LDO_X, /*not support*/ |
| 928 | DISCHARGER_BUCK_4, |
| 929 | DISCHARGER_BUCK_3, |
| 930 | DISCHARGER_BUCK_2, |
| 931 | DISCHARGER_BUCK_1, |
| 932 | DISCHARGER_BUCK_X, /*not support*/ |
| 933 | |
| 934 | DISCHARGER_LDO_1, |
| 935 | DISCHARGER_LDO_2, |
| 936 | DISCHARGER_LDO_3, |
| 937 | DISCHARGER_LDO_4, |
| 938 | DISCHARGER_LDO_5, |
| 939 | DISCHARGER_LDO_6, |
| 940 | DISCHARGER_LDO_7, |
| 941 | DISCHARGER_LDO_8, |
| 942 | |
| 943 | DISCHARGER_MAX |
| 944 | }T_ZDrvZx234290_LdoDischarger; |
| 945 | |
| 946 | typedef enum _T_ZDrvZx234290_DISCHARGER_ENABLE |
| 947 | { |
| 948 | DISCHARGER_DISBALE = 0, /* 00 */ |
| 949 | DISCHARGER_ENABLE = 1, /* 10 */ |
| 950 | |
| 951 | DISCHARGER_ENABLE_MAX |
| 952 | }T_ZDrvZx234290_DISCHARGER_ENABLE; |
| 953 | |
| 954 | typedef enum _T_ZDrvZx234290_LdoList |
| 955 | { |
| 956 | LDOLIST_BUCK_1 = 0, |
| 957 | LDOLIST_BUCK_2, |
| 958 | LDOLIST_BUCK_3, |
| 959 | LDOLIST_BUCK_4, |
| 960 | LDOLIST_LDO_1, |
| 961 | LDOLIST_LDO_2, |
| 962 | LDOLIST_LDO_3, |
| 963 | |
| 964 | LDOLIST_LDO_4, |
| 965 | LDOLIST_LDO_5, |
| 966 | LDOLIST_LDO_6,//default off |
| 967 | LDOLIST_LDO_7, |
| 968 | LDOLIST_LDO_8, |
| 969 | LDOLIST_LDO_9,//default off |
| 970 | LDOLIST_LDO_10, |
| 971 | LDOLIST_LDO_RTC, |
| 972 | |
| 973 | LDOLIST_MAX |
| 974 | }T_ZDrvZx234290_LdoList; |
| 975 | |
| 976 | typedef enum _T_ZDrvZx234297_SINK |
| 977 | { |
| 978 | ZX234297_SINK1 = 0, /* 00 */ |
| 979 | ZX234297_SINK2 = 1, /* 10 */ |
| 980 | |
| 981 | ZX234297_SINK_MAX |
| 982 | }T_ZDrvZx234297_SINK; |
| 983 | |
| 984 | typedef enum _T_ZDrvZx234297_SINK_SLPMODE |
| 985 | { |
| 986 | SLPMODE_NORMAL = 0, /* 00 */ |
| 987 | SLPMODE_SHUTDOWN = 1, /* 10 */ |
| 988 | |
| 989 | SLPMODE_MAX |
| 990 | }T_ZDrvZx234297_SINK_SLPMODE; |
| 991 | |
| 992 | typedef enum _T_ZDrvZx234297_SINK_CURRENT |
| 993 | { |
| 994 | SINK_CURRENT_5MA, |
| 995 | SINK_CURRENT_10MA, |
| 996 | SINK_CURRENT_15MA, |
| 997 | SINK_CURRENT_20MA, |
| 998 | SINK_CURRENT_30MA, |
| 999 | SINK_CURRENT_40MA, |
| 1000 | SINK_CURRENT_50MA, |
| 1001 | SINK_CURRENT_60MA, |
| 1002 | SINK_CURRENT_70MA, |
| 1003 | SINK_CURRENT_80MA, |
| 1004 | SINK_CURRENT_90MA, |
| 1005 | SINK_CURRENT_100MA, |
| 1006 | SINK_CURRENT_110MA, |
| 1007 | SINK_CURRENT_120MA, |
| 1008 | |
| 1009 | SINK_CURRENT_MAX |
| 1010 | }T_ZDrvZx234297_SINK_CURRENT; |
| 1011 | |
| 1012 | typedef enum _T_ZDrvZx234290_ResetType |
| 1013 | { |
| 1014 | #if 0 |
| 1015 | ZX234290_USER_RST_UNDEFINE = 0, |
| 1016 | ZX234290_USER_RST_TO_NORMAL = 1, |
| 1017 | ZX234290_USER_RST_TO_CHARGER = 2, |
| 1018 | ZX234290_USER_RST_TO_ALARM = 3, |
| 1019 | #else |
| 1020 | ZX234290_USER_RST_UNDEFINE = 3, |
| 1021 | ZX234290_USER_RST_TO_NORMAL = 0, |
| 1022 | ZX234290_USER_RST_TO_CHARGER = 1, |
| 1023 | ZX234290_USER_RST_TO_ALARM = 2, |
| 1024 | #endif |
| 1025 | ZX234290_USER_RST_TO_EXCEPT = 4, |
| 1026 | |
| 1027 | ZX234290_USER_RST_MAX |
| 1028 | }T_ZDrvZx234290_ResetType; |
| 1029 | |
| 1030 | |
| 1031 | int zx234290_get_chip_version(void); |
| 1032 | int zx234290_irq_init(struct zx234290 *zx234290); |
| 1033 | |
| 1034 | int zx234290_set_buck1_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1035 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_buck1_onoff(void); |
| 1036 | int zx234290_set_buck1_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status); |
| 1037 | T_ZDrvZx234290_BUCK_NRMMODE zx234290_get_buck1_active_mode(void); |
| 1038 | int zx234290_set_buck1_voltage(T_ZDrvZx234290_VbuckA vol); |
| 1039 | T_ZDrvZx234290_VbuckA zx234290_get_buck1_voltage(void); |
| 1040 | int zx234290_set_buck1_sleep_mode(T_ZDrvZx234290_BUCK1_SLPMODE status); |
| 1041 | T_ZDrvZx234290_BUCK1_SLPMODE zx234290_get_buck1_sleep_mode(void); |
| 1042 | int zx234290_set_buck1_sleep_voltage(T_ZDrvZx234290_VbuckA vol); |
| 1043 | |
| 1044 | int zx234290_set_buck2_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1045 | int zx234290_set_buck2_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status); |
| 1046 | int zx234290_set_buck2_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status); |
| 1047 | |
| 1048 | int zx234290_set_buck3_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1049 | int zx234290_set_buck3_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status); |
| 1050 | int zx234290_set_buck3_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status); |
| 1051 | |
| 1052 | |
| 1053 | int zx234290_set_buck4_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1054 | int zx234290_set_buck4_active_mode(T_ZDrvZx234290_BUCK_NRMMODE status); |
| 1055 | int zx234290_set_buck4_sleep_mode(T_ZDrvZx234290_BUCK234_SLPMODE status); |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | int zx234290_set_ldo1_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1060 | int zx234290_set_ldo1_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status); |
| 1061 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo1_onoff(void); |
| 1062 | int zx234290_set_ldo1_voltage(T_ZDrvZx234290_VldoA vol); |
| 1063 | T_ZDrvZx234290_VldoA zx234290_get_ldo1_voltage(void); |
| 1064 | int zx234290_set_ldo1_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1065 | T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo1_sleep_mode(void); |
| 1066 | |
| 1067 | |
| 1068 | int zx234290_set_ldo2_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1069 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo2_onoff(void); |
| 1070 | int zx234290_set_ldo2_voltage(T_ZDrvZx234290_VldoC vol); |
| 1071 | T_ZDrvZx234290_VldoC zx234290_get_ldo2_voltage(void); |
| 1072 | int zx234290_set_ldo2_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1073 | T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo2_sleep_mode(void); |
| 1074 | |
| 1075 | int zx234290_set_ldo3_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1076 | int zx234290_set_ldo3_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1077 | |
| 1078 | int zx234290_set_ldo4_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1079 | int zx234290_set_ldo4_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status); |
| 1080 | |
| 1081 | |
| 1082 | int zx234290_set_ldo5_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1083 | int zx234290_set_ldo5_onoff_PSM(T_ZDrvZx234290_LDO_ENABLE status); |
| 1084 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo5_onoff(void); |
| 1085 | int zx234290_set_ldo5_voltage(T_ZDrvZx234290_VldoB vol); |
| 1086 | T_ZDrvZx234290_VldoB zx234290_get_ldo5_voltage(void); |
| 1087 | int zx234290_set_ldo5_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status); |
| 1088 | T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo5_sleep_mode(void); |
| 1089 | |
| 1090 | int zx234290_set_ldo6_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1091 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo6_onoff(void); |
| 1092 | int zx234290_set_ldo6_voltage(T_ZDrvZx234290_VldoD vol); |
| 1093 | T_ZDrvZx234290_VldoD zx234290_get_ldo6_voltage(void); |
| 1094 | int zx234290_set_ldo6_sleep_mode(T_ZDrvZx234290_LDOB_SLPMODE status); |
| 1095 | T_ZDrvZx234290_LDOB_SLPMODE zx234290_get_ldo6_sleep_mode(void); |
| 1096 | |
| 1097 | int zx234290_set_ldo7_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1098 | int zx234290_set_ldo7_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1099 | |
| 1100 | int zx234290_set_ldo8_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1101 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo8_onoff(void); |
| 1102 | int zx234290_set_ldo8_voltage(T_ZDrvZx234290_VldoD vol); |
| 1103 | T_ZDrvZx234290_VldoD zx234290_get_ldo8_voltage(void); |
| 1104 | int zx234290_set_ldo8_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1105 | T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo8_sleep_mode(void); |
| 1106 | int zx234290_set_ldo9_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1107 | int zx234290_set_ldo9_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1108 | |
| 1109 | int zx234290_set_ldo10_onoff(T_ZDrvZx234290_LDO_ENABLE status); |
| 1110 | int zx234290_set_ldo10_sleep_mode(T_ZDrvZx234290_LDOA_SLPMODE status); |
| 1111 | T_ZDrvZx234290_LDO_ENABLE zx234290_get_ldo10_onoff(void); |
| 1112 | T_ZDrvZx234297_VldoF zx234290_get_ldo10_voltageF(void); |
| 1113 | T_ZDrvZx234290_LDOA_SLPMODE zx234290_get_ldo10_sleep_mode(void); |
| 1114 | int zx234297_set_ldo10_voltageF(T_ZDrvZx234297_VldoF vol); |
| 1115 | |
| 1116 | int zDrvPmic_SetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable); |
| 1117 | int zDrvPmic_SetNormal_Onoff_PSM(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable enable); |
| 1118 | int zDrvPmic_SetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int voltage); |
| 1119 | int zDrvPmic_SetSleep_Voltage(T_ZDrvPmic_Regulator regulator, int voltage); |
| 1120 | int zDrvPmic_GetNormal_Onoff(T_ZDrvPmic_Regulator regulator, T_ZDrvPmic_Enable* enable); |
| 1121 | int zDrvPmic_GetNormal_Voltage(T_ZDrvPmic_Regulator regulator, int* voltage); |
| 1122 | |
| 1123 | |
| 1124 | /*adc fun*/ |
| 1125 | uint get_battery_voltage(void); |
| 1126 | uint get_adc1_voltage(void); |
| 1127 | uint get_adc2_voltage(void); |
| 1128 | |
| 1129 | |
| 1130 | #endif /* __LINUX_MFD_TPS65912_H */ |