Baseline update from LYNQ_SDK_ASR_T108_V05.03.01.00(kernel build error.)
Change-Id: I56fc72cd096e82c589920026553170e5cb9692eb
diff --git a/marvell/linux/arch/arm/boot/dts/asr1806-p301.dts b/marvell/linux/arch/arm/boot/dts/asr1806-p301.dts
index 639c387..2743ced 100755
--- a/marvell/linux/arch/arm/boot/dts/asr1806-p301.dts
+++ b/marvell/linux/arch/arm/boot/dts/asr1806-p301.dts
@@ -62,14 +62,15 @@
ptp-support;
ptp-clk-rate = <100000000>;
status = "okay";
-
- reset-gpio = <&gpio 23 0>;
+ enable-suspend;
+ reset-gpio = <&gpio 42 0>;
reset-active-low;
- reset-delays-us = <0 100000 100000>;
-
- ldo-gpio = <&gpio 40 0>;
- ldo-active-low;
- ldo-delays-us = <0 100000 100000>;
+ reset-delays-us = <100000 100000 100000>;
+ //ldo-gpio = <&gpio 40 0>;
+ //ldo-active-low;
+ // ldo-delays-us = <0 100000 100000>;
+ //vmmc-supply = <0x19>;
+ mdio-clk-div = <254>;
flow-control-threshold = <60 90>;
clk-tuning-enable;
/* clk-config(32bit)
@@ -91,10 +92,10 @@
#if 0
/* enable 1000M phy*/
3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
- phy-handle = <&phy0>;
+ phy-handle = <&phy3>;
#else
/* enable 100M phy*/
- 3v3-enable = <1>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
+ 3v3-enable = <0>; /* IO voltage, 1 - 3.3v, 0 - 1.8v */
phy-handle = <&phy3>;
#endif
/* enable fix link for ethernet switch */
@@ -119,13 +120,13 @@
};
/* YT8512B 10M/100M 3.3V RMII PHY */
- phy3: phy@3 {
- compatible = "ethernet-phy-ieee802.3-c22";
- device_type = "ethernet-phy";
- reg = <0x3>; /* set phy address*/
- phy-mode = "rmii";
- driver_strength = <0x3>;
- };
+ // phy3: phy@3 {
+ // compatible = "ethernet-phy-ieee802.3-c22";
+ // device_type = "ethernet-phy";
+ // reg = <0x3>; /* set phy address*/
+ // phy-mode = "rmii";
+ // driver_strength = <0x3>;
+ // };
/* IP175D 10M/100M 3.3V RMII SWITCH */
phy1: phy@1 {
@@ -134,6 +135,16 @@
reg = <0x1>; /* set phy address*/
phy-mode = "rmii";
};
+
+
+ /* jl 3103 phy */
+ phy3: phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ device_type = "ethernet-phy";
+ reg = <0x3>; /* set phy address*/
+ phy-mode = "rgmii-id";
+ lynq,jl3103=<100 0>;
+ };
};
};
qspi: spi@0xd420b000 {
@@ -210,9 +221,9 @@
/* SDIO */
sdh1: sdh@d4280800 {
pinctrl-names = "default", "fast", "sleep";
- pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2 &sdh1_pmx_func3>;
- pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast &sdh1_pmx_func3>;
- pinctrl-2 = <&sdh1_pmx_edge_wakeup>;
+ pinctrl-0 = <&sdh1_pmx_func1 &sdh1_pmx_func2>;
+ pinctrl-1 = <&sdh1_pmx_func1_fast &sdh1_pmx_func2_fast>;
+ /* pinctrl-2 = <&sdh1_pmx_edge_wakeup>;*/
bus-width = <4>;
no-mmc;
no-sd;
@@ -247,13 +258,14 @@
<PXA_MMC_TIMING_SD_HS PXA_SDH_DTR_45M PXA_SDH_DTR_89M 0 0 0 0>,
<PXA_MMC_TIMING_UHS_DDR50 PXA_SDH_DTR_52M PXA_SDH_DTR_104M 0 0 0 3>,
<PXA_MMC_TIMING_UHS_SDR50 PXA_SDH_DTR_83M PXA_SDH_DTR_83M 0 0 0 3>,
- <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
+ //<PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_208M PXA_SDH_DTR_208M 0 0 0 0>,
+ <PXA_MMC_TIMING_UHS_SDR104 PXA_SDH_DTR_52M PXA_SDH_DTR_52M 0 0 0 0>,
<PXA_MMC_TIMING_MAX PXA_SDH_DTR_PS_NONE PXA_SDH_DTR_89M 0 0 0 0>;
status = "okay";
};
pcie0: pcie@0xd4288000{
reset-gpios = <&gpio 42 0 >;
- status = "okay";
+ status = "disbabled";
};
pciephy0: pcie-phy@d4206000 {
status = "okay";
@@ -303,23 +315,24 @@
pinctrl-names = "default","sleep";
pinctrl-0 = <&uart1_pmx_func1 &uart1_pmx_func2>;
pinctrl-1 = <&uart1_pmx_func1_sleep &uart1_pmx_func2>;
- edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
+ //edge-wakeup-gpio = <&gpio 29 0>; /* GPIO29: AP UART rx pin */
status = "okay";
};
uart2: uart@d4036000 {
pinctrl-names = "default";
- pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd>;
+ pinctrl-0 = <&gps_pmx_uart_rxd &gps_pmx_uart_txd &gps_pmx_func_cts_rts>;
status = "okay";
};
uart3: uart@d4018000 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pmx_func>;
- status = "disabled";
+ status = "okay";
};
uart4: uart@d401f000 {
pinctrl-names = "default";
- pinctrl-0 = <&uart4_pmx_func>;
- status = "disabled";
+ pinctrl-0 = <&uart4_pmx_func>; /*BAUD :9600*/
+ /*pinctrl-0 = <&uart4_pmx_func_rxd &uart4_pmx_func_txd &uart4_pmx_func_cts_rts>;*/
+ status = "okay";
};
rtc: rtc@d4010000 {
status = "okay";
@@ -348,13 +361,22 @@
/*GPIO34 AF0*/ /* FRM *//* DXS101 Use the config of Cs-gpios */
GPIO33 AF1 /* SCLK */
>;
- DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
+ };
+ ssp2_pmx_func: ssp2_pmx_func {
+ pinctrl-single,pins = <
+ GPIO37 AF3 /* TXD */
+ GPIO38 AF3 /* SCLK */
+ GPIO39 AF3 /* FRM */
+ GPIO40 AF3 /* RXD */
+ >;
+ DS_SLOW0;PULL_NONE;EDGE_NONE;SL_NORMAL; //DS_MEDIUM modify for overvoltage
};
lcd_bl_func: lcd_bl_func {
pinctrl-single,pins = <
- VCXO_OUT AF1 /* GPIO126, lcd bl */
- GPIO24 AF0 /* reset */
- GPIO22 AF0 /* lcd d/c */
+ /* VCXO_OUT AF1 GPIO126, lcd bl */
+ /* GPIO24 AF0 reset */
+ /* GPIO22 AF0 lcd d/c */
>;
MFP_DEFAULT;
};
@@ -374,36 +396,36 @@
pinctrl-single,pins = <
GPIO29 AF1
>;
- DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
};
twsi0_pmx_func: twsi0_pmx_func {
pinctrl-single,pins = <
GPIO49 AF1
GPIO50 AF1
>;
- MFP_LPM_FLOAT;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
};
twsi0_pmx_gpio: twsi0_pmx_gpio {
pinctrl-single,pins = <
GPIO49 AF0
GPIO50 AF0
>;
- MFP_LPM_FLOAT;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT;
};
-#if 0
+#if 1
twsi1_pmx_func: twsi1_pmx_func {
pinctrl-single,pins = <
GPIO10 AF1
GPIO11 AF1
>;
- MFP_LPM_FLOAT;
+ DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
};
twsi1_pmx_gpio: twsi1_pmx_gpio {
pinctrl-single,pins = <
GPIO10 AF0
GPIO11 AF0
>;
- MFP_LPM_FLOAT;
+ DS_SLOW0;PULL_NONE;EDGE_NONE;LPM_FLOAT;
};
#endif
/* no pull, no LPM */
@@ -436,13 +458,27 @@
>;
DS_MEDIUM;PULL_DOWN;EDGE_NONE;SL_NORMAL;
};
+
+ //zqy
+ gnss_clk_on: gnss_clk_on {
+ pinctrl-single,pins = <
+ GPIO43 AF2 /*32K CLK */
+
+ /*VCXO_REQ AF1 GPIO[125] GPS_WAKE_HOST */
+ GPIO47 AF0 /* HOST_WAKE_GPS */
+ GPIO45 AF0 /*RESET */
+ CLK_REQ AF1 /*sleep en*/
+
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_LOW;
+ };
gps_pmx_uart_rxd: gps_pmx_uart_rxd {
/* gps dedicated uart */
pinctrl-single,pins = <
GPIO51 AF1
GPIO32 AF1
>;
- MFP_DEFAULT;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
};
gps_pmx_uart_txd: gps_pmx_uart_txd {
/* gps dedicated uart */
@@ -450,8 +486,16 @@
GPIO52 AF1
GPIO31 AF1
>;
- MFP_DEFAULT;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
};
+ gps_pmx_func_cts_rts: gps_pmx_func_cts_rts {
+ pinctrl-single,pins = <
+ GPIO31 AF1 /* cts */
+ GPIO32 AF1 /* rts */
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
+
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
GPIO53 AF1 /* RX */
@@ -459,12 +503,36 @@
>;
MFP_DEFAULT;
};
+
+
+ uart4_pmx_func_rxd: uart4_pmx_func_rxd {
+ pinctrl-single,pins = <
+ GPIO37 AF2
+ GPIO40 AF2
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
+ uart4_pmx_func_txd: uart4_pmx_func_txd {
+ pinctrl-single,pins = <
+ GPIO38 AF2
+ GPIO39 AF2
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
+
+ uart4_pmx_func_cts_rts: uart4_pmx_func_cts_rts {
+ pinctrl-single,pins = <
+ GPIO39 AF2
+ GPIO40 AF2
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
GPIO44 AF1 /* RX */
GPIO45 AF1 /* TX */
>;
- MFP_DEFAULT;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
};
panel_rst_func: panel_rst_func {
pinctrl-single,pins = <
@@ -585,28 +653,61 @@
};
sdh1_pmx_pd_rst_off: sdh1_pmx_pd_rst_off {
pinctrl-single,pins = <
- GPIO11 AF0 /* GPIO31 AF0 WLAN_PDn */
- GPIO08 AF0 /* GPIO32 AF0 LDO_EN */
+ /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
+ /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
+ MMC1_CD AF1
>;
MFP_PULL_DOWN;
};
sdh1_pmx_pd_rst_on: sdh1_pmx_pd_rst_on {
pinctrl-single,pins = <
- GPIO11 AF0 /* GPIO31 AF0 WLAN_PDn */
- GPIO08 AF0 /* GPIO32 AF0 LDO_EN */
+ /* GPIO11 AF0 GPIO31 AF0 WLAN_PDn */
+ /* GPIO08 AF0 GPIO32 AF0 LDO_EN */
+ MMC1_CD AF1
+ >;
+ MFP_PULL_UP;
+ };
+
+
+ mbtk_sdh_pmx_off: mbtk_sdh_pmx_off {
+ pinctrl-single,pins = <
+ VCXO_REQ AF1 //gpio125 wlan en
+ GPIO123 AF1 //wlan pwr en
+ VCXO_OUT AF1 /*gpio127 wifi wake*/
+ >;
+ MFP_PULL_DOWN;
+ };
+ mbtk_sdh_pmx_on: mbtk_sdh_pmx_on {
+ pinctrl-single,pins = <
+ VCXO_REQ AF1 //gpio125 wlan en
+ GPIO123 AF1 //wlan pwr en
+ VCXO_OUT AF1 /*gpio127 wifi wake*/
>;
MFP_PULL_UP;
};
alc5616_pmx_func1: alc5616_pmx_func1 {
pinctrl-single,pins = <
- GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
+ /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
GPIO20 AF7 /* MCLK:I2S_SYSCLK */
>;
MFP_DEFAULT;
};
alc5616_pmx_func2: alc5616_pmx_func2 {
pinctrl-single,pins = <
- GPIO08 AF0 /* AP_UART1_DCD_N -> CODEC_IRQ */
+ /* GPIO08 AF0 AP_UART1_DCD_N -> CODEC_IRQ */
+ GPIO20 AF7 /* MCLK:I2S_SYSCLK */
+ >;
+ MFP_DEFAULT;
+ };
+
+ es8311_pa_func1: es8311_pa_func1 {
+ pinctrl-single,pins = <
+ GPIO20 AF7 /* MCLK:I2S_SYSCLK */
+ >;
+ MFP_DEFAULT;
+ };
+ es8311_pa_func2: es8311_pa_func2 {
+ pinctrl-single,pins = <
GPIO20 AF7 /* MCLK:I2S_SYSCLK */
>;
MFP_DEFAULT;
@@ -646,7 +747,7 @@
otg_vbus_func: otg_vbus_func {
pinctrl-single,pins = <
- VBUS_DRV AF1 /* GPIO[122] */
+ /* VBUS_DRV AF1 GPIO[122] */
>;
DS_MEDIUM;PULL_DOWN;EDGE_NONE;
};
@@ -689,8 +790,8 @@
};
emac_pmx_func3: emac_pmx_func3 {
pinctrl-single,pins = <
- GPIO23 AF0 /* RESET */
- GPIO40 AF0 /* LDO_EN */
+ GPIO42 AF0 /* RESET */
+ /* GPIO40 AF0 LDO_EN */
>;
DS_SLOW0;PULL_FLOAT;EDGE_NONE;SL_NORMAL;
};
@@ -732,13 +833,113 @@
>;
MFP_PULL_UP;
};
+ pin_func_work: pin_func_work {
+ pinctrl-single,pins = <
+
+ GPIO08 AF0 /*T108 status led* /
+
+ VBUS_DRV AF2 /*32k*/
+
+
+ GPIO46 AF0 /*wifi en*/
+
+ GPIO19 AF0 /*bt en*/
+
+ >;
+ MFP_DEFAULT;
+ };
+
+
+ sc_ext_int0: sc_ext_int0 {
+ pinctrl-single,pins = <
+ GPIO21 AF0
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
+ };
+ sc_ext_int1: sc_ext_int1 {
+ pinctrl-single,pins = <
+ GPIO22 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+ sc_ext_int2: sc_ext_int2 {
+ pinctrl-single,pins = <
+ GPIO23 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+
+ sc_ext_int3: sc_ext_int3 {
+ pinctrl-single,pins = <
+ GPIO24 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+
+ mbtk_plat_irq_func: mbtk_plat_irq_func {
+ pinctrl-single,pins = <
+
+ GPIO21 AF0
+ GPIO22 AF0
+ GPIO23 AF0
+ GPIO24 AF0
+
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
+ mbtk_plat_irq_func_sleep: mbtk_plat_irq_func_sleep {
+ pinctrl-single,pins = <
+ GPIO21 AF0
+ GPIO22 AF0
+ GPIO23 AF0
+ GPIO24 AF0
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
+ };
+
+
gpiokey_pmx_func: gpiokey_pmx_func {
pinctrl-single,pins = <
GPIO09 AF0
>;
DS_MEDIUM;PULL_UP;EDGE_NONE;SL_NORMAL;
};
- usb_id_pinmux: usb_id_pinmux {
+
+ wake_pmx_func1: wake_pmx_func1 {
+ pinctrl-single,pins = <
+ USB_ID AF1
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
+
+
+ wake_pmx_func: wake_pmx_func {
+ pinctrl-single,pins = <
+ PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
+
+ PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
+ GPIO41 AF0
+ PRI_TDO AF1 /*GPIO120*/
+
+
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_NONE;SL_NORMAL;
+ };
+ wake_pmx_func_sleep: wake_pmx_func_sleep {
+ pinctrl-single,pins = <
+ PRI_TDI AF1 /*GPIO117 WAKEUP_OUT*/
+
+ PRI_TMS AF1 /*GPIO118 WAKEUP_IN*/
+ GPIO41 AF0
+ PRI_TDO AF1 /*GPIO120*/
+
+ >;
+ DS_MEDIUM;PULL_NONE;EDGE_BOTH;SL_NORMAL;
+ };
+ usb_id_pinmux: usb_id_pinmux {
pinctrl-single,pins = <
USB_ID AF1/* usbid-gpio99 */
>;
@@ -790,8 +991,8 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "spilcd";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_bl_func>;
+ // pinctrl-names = "default";
+ // pinctrl-0 = <&lcd_bl_func>;
reg = <0>;
/* ST7735: need to set spi-max-frequency to 26M
* ST7789V: can set spi-max-frequency to 52M
@@ -801,7 +1002,7 @@
yres = <128>;
bits = <8>; /* 8: 4line, 9: 3line */
rst_gpio = <&gpio 24 0>;
- bl_gpio = <&gpio 126 0>;
+ // bl_gpio = <&gpio 126 0>;
rs_gpio = <&gpio 22 0>;
/* if comment the following statement, it means
* the avdd is sit on the "always-on" ldo.
@@ -821,9 +1022,26 @@
};
#endif
};
+ ssp2: spi@d401c000{
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ssp2_pmx_func>;
+ asr,spi-inc-mode;
+ cs-gpios = <&gpio 39 0>;
+ status = "okay";
+ mbtk: spidev@0{
+ compatible = "asr,spidev";
+ reg = <0>;
+ status = "okay";
+ spi-cpol;
+ spi-cpha;
+ spi-max-frequency = <6500000>;
+ };
+ };
twsi0: i2c@d4011000 {
status= "okay";
alc5616@1b {
+ status= "disabled";
compatible = "asrmicro,alc5616";
reg = <0x1b>;
pinctrl-names = "default", "sleep";
@@ -839,6 +1057,37 @@
#endif
};
+ nau8810@1a {
+ compatible = "marvell,nau8810";
+ clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
+ clock-names = "i2s_sys_clk";
+
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&es8311_pa_func1>;
+ pinctrl-1 = <&es8311_pa_func2>;
+ reg = <0x1a>;
+ status= "disabled";
+ };
+
+ es8311@18 {
+ compatible = "ambarella,es8311";
+ reg = <0x18>;
+ clocks = <&soc_clocks ASR1803_CLK_I2S_SYSCLK>;
+ clock-names = "i2s_sys_clk";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&es8311_pa_func1>;
+ pinctrl-1 = <&es8311_pa_func2>;
+
+ // gpios = <&gpio 21 0>,
+ // <&gpio 23 0>,
+ // <&gpio 24 0>,
+ // <&gpio 22 0>;
+
+ status= "okay";
+ };
+
/*
pmic4: 88pm805@38 {
compatible = "marvell,88pm805";
@@ -847,17 +1096,19 @@
*/
};
twsi1: i2c@d4010800 {
-#if 0
+#if 1
pinctrl-names = "default","gpio";
pinctrl-0 = <&twsi1_pmx_func>;
pinctrl-1 = <&twsi1_pmx_gpio>;
i2c-gpio = <&gpio 10 0 &gpio 11 0>;
#endif
- status= "disabled";
- nau8810@1a {
- compatible = "marvell,nau8810";
- reg = <0x1a>;
- };
+ status= "okay";
+ //nau8810@1a {
+ // compatible = "marvell,nau8810";
+ // reg = <0x1a>;
+ //};
+
+
};
twsi2: i2c@d4037000 {
status = "okay";
@@ -1011,12 +1262,12 @@
vcc_sdh1: sd-regulator {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&sd_ldo_en>;
+ /*pinctrl-names = "default";*/
+ /*pinctrl-0 = <&sd_ldo_en>;*/
regulator-name = "SDH1 VCC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- gpio = <&gpio 45 0>;
+ /* gpio = <&gpio 45 0>;*/
enable-active-high;
status = "okay";
};
@@ -1026,10 +1277,35 @@
pinctrl-names = "off", "on";
pinctrl-0 = <&sdh1_pmx_pd_rst_off>;
pinctrl-1 = <&sdh1_pmx_pd_rst_on>;
- sd-host = <&sdh1>;
- pd-gpio = <&gpio 11 0>;
- 3v3-ldo-gpio = <&gpio 8 0>;
- edge-wakeup-gpio = <&gpio 10 0>;
+ sd-host = <&sdh0>;
+ //pd-gpio = <&gpio 90 0>;
+ rst-gpio = <&gpio 90 0>;
+
+ /*3v3-ldo-gpio = <&gpio 8 0>;*/
+ /*edge-wakeup-gpio = <&gpio 10 0>;*/
+ status = "okay";
+ };
+
+ mbtk-sdh{
+ compatible = "mbtk,mbtk-sdh";
+ pinctrl-names = "off", "on";
+ pinctrl-0 = <&mbtk_sdh_pmx_off>;
+ pinctrl-1 = <&mbtk_sdh_pmx_on>;
+ sd-host = <&sdh1>;
+ 1v8-ldo-gpio = <&gpio 123 0>;
+ host-wakeup-wlan-gpio = <&gpio 127 0>;
+ wlan_en_gpio = <&gpio 125 0>;
+ status = "okay";
+ };
+
+ asr-gps {
+ compatible = "asr,asr-gnss";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gnss_clk_on>;
+ enable_vctcxo_out1;
+ host-wakeup-gnss-gpio = <&gpio 47 0>;
+ /*gnss-wakeup-host-gpio = <&gpio 47 0>;*/
+ rst-gpio = <&gpio 45 0>;
status = "okay";
};
@@ -1040,7 +1316,7 @@
pinctrl-1 = <&pcie_pmx_pd_rst_on>;
rst-gpio = <&gpio 42 0>;
3v3-ldo-gpio = <&gpio 24 0>;
- status = "okay";
+ status = "disabled";
};
sound {
@@ -1048,6 +1324,42 @@
ssp-controllers = <&ssp_dai1>;
};
+ asr-adc {
+ compatible = "asr,adc";
+ //pinctrl-names = "default";
+ //pinctrl-0 = <&pin_func_work>;
+ status = "okay";
+ };
+
+#if 0
+
+ mbtk_PlatIrq{
+ compatible = "mbtk,plat-irq";
+ pinctrl-names = "sc_irq0", "sc_irq1", "sc_irq2", "sc_irq3";
+
+ pinctrl-0 = <&sc_ext_int0>;
+ pinctrl-1 = <&sc_ext_int1>;
+ pinctrl-2 = <&sc_ext_int2>;
+ pinctrl-3 = <&sc_ext_int3>;
+ status = "okay";
+ };
+
+#else
+
+ mbtk_PlatIrq{
+ compatible = "mbtk,plat-irq";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mbtk_plat_irq_func>;
+ pinctrl-1 = <&mbtk_plat_irq_func_sleep>;
+ gpio_irq0 = <&gpio 21 0>;
+ gpio_irq1 = <&gpio 22 0>;
+ gpio_irq2 = <&gpio 23 0>;
+ gpio_irq3 = <&gpio 24 0>;
+ status = "okay";
+ };
+
+#endif
+
ecall {
compatible = "asr,ecall-event";
pinctrl-names = "default";
@@ -1105,8 +1417,17 @@
pinctrl-names = "default";
pinctrl-0 = <&audio_pa_pmx_func>;
pa-gpio = <&gpio 14 0>;
- status = "okay";
+ status = "disabled";
};
+ mbtk_GpioWakeUp {
+ compatible = "mbtk,GpioWakeUp";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&wake_pmx_func &wake_pmx_func1>;
+ pinctrl-1 = <&wake_pmx_func_sleep>;
+ wakeup-in-gpio = <&gpio 118 0>;
+ wakeup-out-gpio = <&gpio 117 0>;
+ status = "okay";
+ };
audio_regs {
compatible = "ASRMICRO,audio-registers";
diff --git a/marvell/linux/arch/arm/boot/dts/asr1806_ab_flash_layout.dtsi b/marvell/linux/arch/arm/boot/dts/asr1806_ab_flash_layout.dtsi
index 5651a77..a6cb340 100755
--- a/marvell/linux/arch/arm/boot/dts/asr1806_ab_flash_layout.dtsi
+++ b/marvell/linux/arch/arm/boot/dts/asr1806_ab_flash_layout.dtsi
@@ -10,154 +10,154 @@
partition@0 {
label = "bootloader";
- reg = <0x0 0xA0000>;
- };
-
- partition@A0000 {
- label = "cp_reliabledata";
- reg = <0xA0000 0x20000>;
- };
-
- partition@C0000 {
- label = "ap_reliabledata";
- reg = <0xC0000 0x20000>;
- };
-
- partition@E0000 {
- label = "cp_reliabledata_backup";
- reg = <0xE0000 0x20000>;
- };
-
- partition@100000 {
- label = "ap_reliabledata_backup";
- reg = <0x100000 0x20000>;
- };
-
- partition@120000 {
- label = "mep-ota";
- reg = <0x120000 0x20000>;
+ reg = <0x0 0x140000>;
};
partition@140000 {
+ label = "cp_reliabledata";
+ reg = <0x140000 0x40000>;
+ };
+
+ partition@180000 {
+ label = "ap_reliabledata";
+ reg = <0x180000 0x40000>;
+ };
+
+ partition@1C0000 {
+ label = "cp_reliabledata_backup";
+ reg = <0x1C0000 0x40000>;
+ };
+
+ partition@200000 {
+ label = "ap_reliabledata_backup";
+ reg = <0x200000 0x40000>;
+ };
+
+ partition@240000 {
+ label = "mep-ota";
+ reg = <0x240000 0x40000>;
+ };
+
+ partition@280000 {
label = "mep-ota_backup";
- reg = <0x140000 0x20000>;
+ reg = <0x280000 0x40000>;
};
- partition@160000 {
+ partition@2C0000 {
label = "asr_flag";
- reg = <0x160000 0x100000>;
+ reg = <0x2C0000 0x200000>;
};
- partition@260000 {
+ partition@4C0000 {
label = "dtim-a";
- reg = <0x260000 0x40000>;
+ reg = <0x4C0000 0x80000>;
};
- partition@2A0000 {
+ partition@540000 {
label = "dtim-b";
- reg = <0x2A0000 0x40000>;
+ reg = <0x540000 0x80000>;
};
#ifdef CONFIG_OPTEE
- partition@2E0000 {
+ partition@5C0000 {
label = "cpimage-a";
- reg = <0x2E0000 0xCE0000>;
+ reg = <0x5C0000 0x19C0000>;
};
- partition@FC0000 {
+ partition@1F80000 {
label = "tos-a";
- reg = <0xFC0000 0x100000>;
+ reg = <0x1F80000 0x200000>;
};
- partition@10C0000 {
+ partition@2180000 {
label = "cpimage-b";
- reg = <0x10C0000 0xCE0000>;
+ reg = <0x2180000 0x19C0000>;
};
- partition@1DA0000 {
+ partition@3B40000 {
label = "tos-b";
- reg = <0x1DA0000 0x100000>;
+ reg = <0x3B40000 0x200000>;
};
#else
- partition@2E0000 {
+ partition@5C0000 {
label = "cpimage-a";
- reg = <0x2E0000 0xDE0000>;
+ reg = <0x5C0000 0x1BC0000>;
};
- partition@10C0000 {
+ partition@2180000 {
label = "cpimage-b";
- reg = <0x10C0000 0xDE0000>;
+ reg = <0x2180000 0x1BC0000>;
};
#endif
- partition@1EA0000 {
+ partition@3D40000 {
label = "u-boot-a";
- reg = <0x1EA0000 0xC0000>;
+ reg = <0x3D40000 0x180000>;
};
- partition@1F60000 {
+ partition@3EC0000 {
label = "u-boot-b";
- reg = <0x1F60000 0xC0000>;
+ reg = <0x3EC0000 0x180000>;
};
- partition@2020000 {
+ partition@4040000 {
label = "kernel-a";
- reg = <0x2020000 0x500000>;
+ reg = <0x4040000 0xA00000>;
};
- partition@2520000 {
+ partition@4A40000 {
label = "kernel-b";
- reg = <0x2520000 0x500000>;
+ reg = <0x4A40000 0xA00000>;
};
-
- partition@2A20000 {
+
+ partition@5440000 {
label = "device_info";
- reg = <0x2A20000 0x40000>;
+ reg = <0x5440000 0x40000>;
};
-
- /* Afterwards, the content can be edited.*/
- partition@2A60000 {
+
+ /* Only after this can modifications be made */
+ partition@5480000 {
label = "OTA";
- reg = <0x2A60000 0x2800000>;
+ reg = <0x5480000 0x2800000>;
};
- partition@5260000 {
+ partition@7C80000 {
label = "cust_info";
- reg = <0x5260000 0x40000>;
+ reg = <0x7C80000 0x40000>;
};
- partition@52A0000 {
+ partition@7CC0000 {
label = "rootfs-a";
- reg = <0x52A0000 0x1E00000>;
+ reg = <0x7CC0000 0x1E00000>;
sdtim-fs;
};
- partition@70A0000 {
+ partition@9AC0000 {
label = "rootfs-b";
- reg = <0x70A0000 0x1E00000>;
+ reg = <0x9AC0000 0x1E00000>;
sdtim-fs;
};
- partition@8EA0000 {
+ partition@B8C0000 {
label = "oem_data-a";
- reg = <0x8EA0000 0x700000>;
+ reg = <0xB8C0000 0x700000>;
sdtim-fs;
};
- partition@95A0000 {
+ partition@BFC0000 {
label = "oem_data-b";
- reg = <0x95A0000 0x700000>;
+ reg = <0xBFC0000 0x700000>;
sdtim-fs;
};
- partition@9CA0000 {
+ partition@C6C0000 {
label = "rootfs_data";
- reg = <0x9CA0000 0x1E00000>;
+ reg = <0xC6C0000 0x1E00000>;
};
-
- partition@BAA0000 {
+
+ partition@E4C0000 {
label = "user_data";
- reg = <0xBAA0000 0>;
+ reg = <0xE4C0000 0>;
};
};
};
diff --git a/marvell/linux/arch/arm/boot/dts/asr18xx-pinfunc.h b/marvell/linux/arch/arm/boot/dts/asr18xx-pinfunc.h
old mode 100644
new mode 100755
index 9d32811..5acbd29
--- a/marvell/linux/arch/arm/boot/dts/asr18xx-pinfunc.h
+++ b/marvell/linux/arch/arm/boot/dts/asr18xx-pinfunc.h
@@ -258,6 +258,11 @@
#define GPIO82 0x284
#define GPIO83 0x288
#define GPIO86 0x204
+// Add by liubin
+#define GPIO117 0xB4
+#define GPIO118 0xB8
+#define GPIO119 0xBC
+#define GPIO120 0xC0
#define GPIO123 0xCC
#define GPIO124 0xD0
#define GPIO126 0xD8
diff --git a/marvell/linux/arch/arm/boot/dts/asr_pm802.dtsi b/marvell/linux/arch/arm/boot/dts/asr_pm802.dtsi
old mode 100644
new mode 100755
index ec6f729..186b8a0
--- a/marvell/linux/arch/arm/boot/dts/asr_pm802.dtsi
+++ b/marvell/linux/arch/arm/boot/dts/asr_pm802.dtsi
@@ -58,7 +58,7 @@
regulator-max-microvolt = <3950000>;
regulator-always-on;
};
- LDO1 {
+ pm802ldo1:LDO1 {
regulator-compatible = "PM802-LDO1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -77,6 +77,7 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};*/
+ /* ldo4 works as LDO4_3V0_USIM2 shouldn't be configed in uboot/linux. It is only controled in CP */
pm802ldo4: LDO4 {
regulator-compatible = "PM802-LDO4";
regulator-min-microvolt = <1800000>;
@@ -86,13 +87,15 @@
regulator-compatible = "PM802-LDO5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
+ //regulator-boot-on;
+ //regulator-always-on;
};
pm802ldo6: LDO6 {
regulator-compatible = "PM802-LDO6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on; /*add by mbtk*/
+ regulator-always-on; /*add by mbtk*/
};
};
dvc {