| /* |
| * Copyright (C) 2018 ASR Microelectronics Ltd. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * publishhed by the Free Software Foundation. |
| */ |
| /dts-v1/; |
| #include "asr1901-pinfunc.h" |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/asr-pm.h> |
| /* #include <dt-bindings/usb/mv_usb_phy.h> */ |
| #include <dt-bindings/clock/asr,asr1803.h> |
| #include <dt-bindings/clock/timer-mmp.h> |
| #include <dt-bindings/mmc/asr_sdhci.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <generated/autoconf.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| i2c0 = &twsi0; |
| i2c1 = &twsi1; |
| i2c2 = &twsi2; |
| i2c3 = &twsi3; |
| i2c4 = &twsi4; |
| }; |
| |
| gic: interrupt-controller@d8002000 { |
| compatible = "arm,cortex-a7-gic"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0xd8001000 0x1000>, |
| <0xd8002000 0x2000>; |
| dist-power-domain = "always-on"; |
| cpuif-power-domain = "always-on"; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| clock: clock-controller { |
| compatible = "marvell,asr1901-clock"; |
| reg = <0xc0000000 0x880>; |
| reg-names = "dmcu"; |
| }; |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| ranges; |
| ddr@c0000000 { /* DDR memory controller */ |
| compatible = "marvell,devfreq-ddr"; |
| reg = <0xc0000000 0x880>, |
| <0xc0058500 0x80>; |
| interrupts = <0 99 0x4>; |
| interrupt-names = "nezas-mc-irq"; |
| marvell,qos; |
| status = "okay"; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a7-pmu"; |
| interrupts = <0 58 0x4>; |
| }; |
| |
| axi@d4200000 { /* AXI */ |
| compatible = "mrvl,axi-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0xd4200000 0x00200000>; |
| ranges; |
| |
| intc: interrupt-controller@d4282000 { |
| compatible = "mrvl,mmp-intc"; |
| status = "disabled"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0xd4282000 0x1000>; |
| mrvl,intc-nr-irqs = <64>; |
| }; |
| usb3phy: usb3phy@c0230000 { |
| compatible = "asr,asr-usb3-phy"; |
| reg = <0xc0230000 0x1000>; |
| clocks = <&soc_clocks ASR1803_CLK_USB>; |
| clock-names = "usb_clk"; |
| status = "disabled"; |
| }; |
| usb3_1: usb3-1 { |
| compatible = "asr,dwc3"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interrupts = <0 89 0x4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&usb_vbus_pinmux &usb_typec_pinmux>; |
| clocks = <&soc_clocks ASR1803_CLK_USB>; |
| clock-names = "usb_clk"; |
| usb_dwc3_1: dwc31@c0200000 { |
| compatible = "snps,dwc3"; |
| reg = <0xc0200000 0x30000>; |
| interrupts = <0 106 0x4>; |
| usb-phy = <&usb3phy>; |
| maximum-speed = "super-speed-plus"; |
| dr_mode = "peripheral"; |
| phy_type = "utmi"; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| snps,dis_u3_susphy_quirk; |
| /* allow-suspend; */ |
| status = "okay"; |
| }; |
| }; |
| sdh1: sdh@d4280000 { |
| compatible = "asr,nezhas-mmc"; |
| reg = <0xd4280000 0x200>; |
| interrupts = <0 39 0x4>; |
| clocks = <&soc_clocks ASR1803_CLK_SDH0 |
| &soc_clocks ASR1803_CLK_SDH_AXI |
| >; |
| clock-names = "sdh-io", "sdh-core"; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "disabled"; |
| }; |
| sdh2: sdh@d4280800 { |
| compatible = "asr,nezhas-mmc"; |
| reg = <0xd4280800 0x200>; |
| interrupts = <0 39 0x4>; |
| clocks = <&soc_clocks ASR1803_CLK_SDH1 |
| &soc_clocks ASR1803_CLK_SDH_AXI |
| >; |
| clock-names = "sdh-io", "sdh-core"; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "disabled"; |
| }; |
| toe: asr-toe@0xd4208000 { |
| compatible = "asr,asr-toe"; |
| reg = <0xc0900000 0x45c>; |
| interrupts = <0 108 0x4>, |
| <0 109 0x4>, |
| <0 3 0x4>, |
| <0 101 0x4>; |
| |
| status = "okay"; |
| }; |
| |
| ssp1: spi@d42a0c00 { |
| compatible = "asr,asr-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd42a0c00 0x30>; |
| asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| asr,ssp-clock-rate = <13000000>; |
| asr,ssp-id = <2>; |
| interrupts = <0 49 0x4>; |
| asr,ssp-disable-dma; /* squ dma */ |
| /* asr,ssp-slave-mode; */ |
| /* asr,slave-rxtimer-to-ms = <0>; */ |
| /* asr,ssp-hold-frame-low; */ |
| /* asr,spi-master-rxto = <8000>; */ |
| /* asr,spi-slave-rxto = <262144>; */ |
| /* asr,spi-pio-interval = <5>; */ |
| clocks = <&soc_clocks ASR1803_CLK_SSP1>; |
| status = "disabled"; |
| }; |
| |
| sram: squ@d1000000 { |
| compatible = "mmio-sram"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| no-memory-wc; |
| reg = <0xd1000000 0x20000>; |
| ranges; |
| |
| /* Add reserved area below */ |
| sram@d100ff00 { |
| /* reserved for obm special flags */ |
| reg = <0xd100ff00 0x100>; |
| }; |
| |
| sram@d101c000 { |
| /* reserved for audio debug */ |
| reg = <0xd101c000 0x4000>; |
| }; |
| }; |
| |
| qspi: spi@0xd420b000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "asr,qspi"; |
| reg = <0xd420b000 0x1000>, <0x80000000 0x8000000>; |
| reg-names = "qspi-base", "qspi-mmap"; |
| asr,qspi-sfa1ad = <0x8000000>; |
| asr,qspi-sfa2ad = <0x8000000>; |
| asr,qspi-sfb1ad = <0x8000000>; |
| asr,qspi-sfb2ad = <0x8000000>; |
| clocks = <&soc_clocks ASR1803_CLK_QSPI |
| &soc_clocks ASR1803_CLK_QSPI_BUS>; |
| clock-names = "qspi_clk", "qspi_bus_clk"; |
| asr,qspi-pmuap-reg = <0xd4282860>; |
| /* asr,qspi-id = <0>; */ |
| asr,qspi-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| interrupts = <0 110 4>; |
| dmas = <&pdma0 45 0xf00>; |
| dma-names = "tx-dma"; |
| asr,qspi-sram = <&sram>; |
| status = "disabled"; |
| }; |
| debug: debug@d42a0000 { |
| compatible = "mrvl,mmp-debug"; |
| reg = <0xd42a0000 0x800>; |
| }; |
| geu: geu { |
| compatible = "asr,asr-geu"; |
| reg = <0xD4292800 0x1000>; |
| interrupts = <0 91 0x4>; |
| asr,asr-fuse; |
| asr,aes-int-mode; |
| dmas = <&pdma0 68 1 |
| &pdma0 69 1>; |
| dma-names = "tx", "rx"; |
| clocks = <&soc_clocks ASR1803_CLK_GEU>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "okay"; |
| }; |
| bcm: bcm { |
| compatible = "asr,asr-bcm"; |
| reg = <0xD4290000 0x2800>; |
| asr,asr-sha; |
| interrupts = <0 91 0x4>; |
| clocks = <&soc_clocks ASR1803_CLK_GEU>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "okay"; |
| }; |
| rng: rng { |
| compatible = "asr,asr-hwrng"; |
| reg = <0xD4293800 0x100>; |
| clocks = <&soc_clocks ASR1803_CLK_GEU>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "okay"; |
| }; |
| pcie0: pcie@d4c00000 { |
| compatible = "asr,kst-pcie", "snps,dw-pcie"; |
| device_type = "pci"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| linux,pci-domain = <0>; |
| reg = <0xd4c00000 0x400000>, /* Kestrel PCIe dbi registers */ |
| <0xc0410000 0x80000>, /* Kestrel PCIe PHY registers */ |
| <0xd4c00000 0x400000>, |
| <0xc0230400 0x10000>; /* eanble usb3-phy if USB is disable */ |
| reg-names = "pcie-dbi", "pcie-phy", "config", "usb3-phy"; |
| ranges = <0x00000800 0 0xE0020000 0xE0020000 0 0x00001000 /* configuration space */ |
| 0x81000000 0 0 0xE0010000 0 0x00010000 /* downstream I/O */ |
| 0x82000000 0 0xE8200000 0xE8200000 0 0x04000000>; /* non-prefetchable memory */ |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| num-lanes = <1>; |
| num-slot = <0>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-parent = <&gic>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&soc_clocks ASR1803_CLK_PCIE0>; |
| status = "disabled"; |
| }; |
| pcie1: pcie@0xd4800000{ |
| compatible = "asr,kst-pcie", "snps,dw-pcie"; |
| device_type = "pci"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| linux,pci-domain = <1>; |
| reg = <0xd4800000 0x400000>, /* Kestrel PCIe dbi registers */ |
| <0xc0510000 0x80000>, /* Kestrel PCIe PHY registers */ |
| <0xc0230400 0x10000>, |
| <0xd4800000 0x400000>; |
| reg-names = "pcie-dbi", "pcie-phy", "usb3-phy", "config"; |
| ranges = <0x00000800 0 0xB8020000 0xB8020000 0 0x00001000 /* configuration space */ |
| 0x81000000 0 0 0xB8010000 0 0x00010000 /* downstream I/O */ |
| 0x82000000 0 0xB8200000 0xB8200000 0 0x04000000>; /* non-prefetchable memory */ |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| num-lanes = <1>; |
| num-slot = <1>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-parent = <&gic>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&soc_clocks ASR1803_CLK_PCIE1>; |
| status = "disabled"; |
| }; |
| |
| xgmacphy: xgmac-phy@c0100000 { |
| compatible = "syscon"; |
| reg = <0xc0100000 0x2000>; |
| }; |
| |
| xgmac: ethernet@d4270000 { |
| compatible = "asr,dwc-xgmac", "snps,dwxgmac"; |
| reg = <0xd4270000 0x8000>; |
| reg-names = "asrmaceth"; |
| interrupts = <0 111 0x4 |
| 0 112 0x4>; |
| interrupt-names = "macirq", "eth_wake_irq"; |
| status = "disabled"; |
| |
| clock-names = "xgmac-clk"; |
| clocks = <&soc_clocks ASR1901_CLK_XGMAC>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| xgmac,phy = <&xgmacphy 0x4>; |
| snps,pbl = <8>; |
| snps,txpbl = <32>; |
| snps,rxpbl = <32>; |
| snps,no-pbl-x8; |
| snps,mixed-burst; |
| snps,ps-speed = <1000>; |
| snps,tso; |
| snps,aal; |
| snps,force_sf_dma_mode; |
| max-speed = <5000>; |
| |
| snps,axi-config = <&xgmac_axi_setup>; |
| snps,mtl-rx-config = <&mtl_rx_setup>; |
| snps,mtl-tx-config = <&mtl_tx_setup>; |
| |
| xgmac_axi_setup: snps-axi-config { |
| snps,blen = <4 8 16 0 0 0 0>; |
| }; |
| |
| mtl_rx_setup: snps-mtl-rx-config { |
| snps,rx-sched-sp; |
| snps,rx-queues-to-use = <2>; |
| queue0 { |
| snps,dcb-algorithm; |
| /* snps,map-to-dma-channel = <2>; */ |
| }; |
| queue1 { |
| snps,dcb-algorithm; |
| /* snps,map-to-dma-channel = <2>; */ |
| }; |
| }; |
| mtl_tx_setup: snps-mtl-tx-config { |
| snps,tx-sched-wrr; |
| snps,tx-queues-to-use = <2>; |
| queue0 { |
| snps,dcb-algorithm; |
| }; |
| queue1 { |
| snps,dcb-algorithm; |
| }; |
| }; |
| }; |
| }; |
| |
| apb@d4000000 { /* APB */ |
| compatible = "mrvl,apb-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0xd4000000 0x00200000>; |
| ranges; |
| |
| pdma0: pdma@d4000000 { |
| compatible = "asr,pdma-1.0"; |
| reg = <0xd4000000 0x10000>; |
| interrupts = <0 56 0x4>; |
| #dma-cells= <2>; |
| #dma-channels = <32>; |
| #dma-channels-tz = <30>; |
| #dma-channels-dedicated = <0x8000>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "okay"; |
| }; |
| |
| thermal: thermal@d4013300 { |
| compatible = "asr,asr1901-thermal"; |
| reg = <0xd4013300 0x74>; |
| interrupts = <0 40 0x4>; |
| clocks = <&soc_clocks ASR1803_CLK_TSEN>; |
| clock-names = "tsen_clk"; |
| status = "okay"; |
| }; |
| |
| timer0: timer@d4014000 { |
| compatible = "mrvl,mmp-timer"; |
| reg = <0xd4014000 0xD0>; |
| marvell,timer-id = <0>; |
| marvell,timer-flag = <0>; |
| marvell,timer-fastclk-frequency = <3250000>; |
| marvell,timer-apb-frequency = <38400000>; |
| clocks = <&soc_clocks ASR1803_CLK_TIMER0>; |
| |
| counter0 { |
| interrupts = <0 7 0x4>; |
| marvell,timer-counter-id = <0>; |
| marvell,timer-counter-cpu = <0>; |
| marvell,timer-counter-frequency = <32768>; |
| marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>; |
| marvell,timer-counter-rating = <200>; |
| }; |
| |
| counter1 { |
| interrupts = <0 8 0x4>; |
| marvell,timer-counter-id = <1>; |
| marvell,timer-counter-frequency = <32768>; |
| marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKSRC>; |
| marvell,timer-counter-rating = <200>; |
| }; |
| |
| counter2 { |
| interrupts = <0 9 0x4>; |
| marvell,timer-counter-id = <2>; |
| marvell,timer-counter-frequency = <3250000>; |
| marvell,timer-counter-usage = <MMP_TIMER_COUNTER_DELAY>; |
| }; |
| }; |
| timer1: timer@d401f000 { |
| compatible = "mrvl,mmp-timer"; |
| reg = <0xd401f000 0xD0>; |
| marvell,timer-id = <1>; |
| marvell,timer-flag = <0>; |
| marvell,timer-fastclk-frequency = <3250000>; |
| marvell,timer-apb-frequency = <38400000>; |
| clocks = <&soc_clocks ASR1803_CLK_TIMER2>; |
| |
| counter0 { |
| interrupts = <0 13 0x4>; |
| marvell,timer-counter-id = <0>; |
| marvell,timer-counter-cpu = <1>; |
| marvell,timer-counter-frequency = <32768>; |
| marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>; |
| marvell,timer-counter-rating = <200>; |
| }; |
| |
| counter1 { |
| interrupts = <0 14 0x4>; |
| marvell,timer-counter-id = <1>; |
| marvell,timer-counter-cpu = <2>; |
| marvell,timer-counter-frequency = <32768>; |
| marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>; |
| marvell,timer-counter-rating = <200>; |
| }; |
| |
| counter2 { |
| interrupts = <0 15 0x4>; |
| marvell,timer-counter-id = <2>; |
| marvell,timer-counter-cpu = <3>; |
| marvell,timer-counter-frequency = <32768>; |
| marvell,timer-counter-usage = <MMP_TIMER_COUNTER_CLKEVT>; |
| marvell,timer-counter-rating = <200>; |
| }; |
| }; |
| |
| |
| uart1: uart@d4017000 { |
| compatible = "asr,mmp-uart"; |
| reg = <0xd4017000 0x100>; |
| interrupts = <0 32 0x4>; |
| uart-drcmr-rx = <3>; |
| uart-drcmr-tx = <4>; |
| dmas = <&pdma0 3 1 |
| &pdma0 4 1>; |
| dma-names = "rx", "tx"; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| clocks = <&soc_clocks ASR1803_CLK_UART0>; |
| resets = <&soc_clocks ASR1803_CLK_UART0>; |
| status = "disabled"; |
| }; |
| |
| uart2: uart@d4018000 { |
| compatible = "asr,mmp-uart"; |
| reg = <0xd4018000 0x1000>; |
| interrupts = <0 33 0x4>; |
| uart-drcmr-rx = <5>; |
| uart-drcmr-tx = <6>; |
| dmas = <&pdma0 5 1 |
| &pdma0 6 1>; |
| dma-names = "rx", "tx"; |
| clocks = <&soc_clocks ASR1803_CLK_UART1>; |
| resets = <&soc_clocks ASR1803_CLK_UART1>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "disabled"; |
| }; |
| |
| uart3: uart@d4017800 { |
| compatible = "asr,mmp-uart"; |
| reg = <0xd4017800 0x1000>; |
| interrupts = <0 34 0x4>; |
| uart-drcmr-rx = <19>; |
| uart-drcmr-tx = <20>; |
| dmas = <&pdma0 19 1 |
| &pdma0 20 1>; |
| dma-names = "rx", "tx"; |
| clocks = <&soc_clocks ASR1803_CLK_UART2>; |
| resets = <&soc_clocks ASR1803_CLK_UART2>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "disabled"; |
| }; |
| |
| gpio: gpio@d4019000 { |
| compatible = "marvell,mmp-gpio"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0xd4019000 0x800>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupts = <0 37 0x4>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-names = "gpio_mux"; |
| clocks = <&soc_clocks ASR1803_CLK_GPIO>; |
| resets = <&soc_clocks ASR1803_CLK_GPIO>; |
| status = "okay"; |
| gpio-ranges = <&pmx 0 55 32>, <&pmx 0 87 23>, |
| <&pmx 3 110 29>, <&pmx 0 139 3 >, |
| <&pmx 28 51 3>; |
| }; |
| |
| mfpr: mfpr@d401e000 { |
| compatible = "asr,mfp-leftover"; |
| pinctrl-names = "default"; |
| reg = <0xd401e000 0x280>; |
| /* pinctrl-0 = <&mfp_pins_group_0 &mfp_pins_group_1 &mfp_pins_group_2 >;*/ |
| status = "disabled"; |
| }; |
| |
| edgewakeup: edgewakeup@d4019800 { |
| compatible = "mrvl,mmp-edge-wakeup"; |
| reg = <0xd4019800 0x10>; |
| status = "disabled"; |
| }; |
| twsi0: i2c@d4011000 { |
| compatible = "mrvl,mmp-twsi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd4011000 0x60>, |
| <0xd40b0300 0x10>; |
| interrupts = <0 20 0x4>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>; |
| mrvl,i2c-fast-mode; |
| /* |
| *ilcr: fast mode b17~9=0x23, 390k |
| * standard mode b8~0=0x9f, 97k |
| *iwcr: b5~0=b01010 recommended value from spec |
| */ |
| marvell,i2c-ilcr = <0x82c469f>; |
| marvell,i2c-iwcr = <0x1434>; |
| pinctrl-names = "default","gpio"; |
| pinctrl-0 = <&twsi0_pmx_func>; |
| pinctrl-1 = <&twsi0_pmx_gpio>; |
| soc-bus-reset; |
| clocks = <&soc_clocks ASR1803_CLK_TWSI0>; |
| clock-names = "twsi0_clk"; |
| status = "disabled"; |
| }; |
| twsi1: i2c@d4010800 { |
| compatible = "mrvl,mmp-twsi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd4010800 0x60>; |
| interrupts = <0 21 0x4>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>; |
| mrvl,i2c-fast-mode; |
| marvell,i2c-ilcr = <0x82c469f>; |
| marvell,i2c-iwcr = <0x1434>; |
| pinctrl-names = "default","gpio"; |
| pinctrl-0 = <&twsi1_pmx_func>; |
| pinctrl-1 = <&twsi1_pmx_gpio>; |
| soc-bus-reset; |
| clocks = <&soc_clocks ASR1803_CLK_TWSI1>; |
| clock-names = "twsi1_clk"; |
| status = "disabled"; |
| }; |
| twsi2: i2c@d4013800 { |
| compatible = "mrvl,mmp-twsi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd4013800 0x60>; |
| interrupts = <0 22 0x4>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>; |
| mrvl,i2c-fast-mode; |
| marvell,i2c-ilcr = <0x82c469f>; |
| marvell,i2c-iwcr = <0x1434>; |
| pinctrl-names = "default","gpio"; |
| pinctrl-0 = <&twsi2_pmx_func>; |
| pinctrl-1 = <&twsi2_pmx_gpio>; |
| soc-bus-reset; |
| clocks = <&soc_clocks ASR1803_CLK_TWSI2>; |
| clock-names = "twsi2_clk"; |
| status = "disabled"; |
| }; |
| twsi3: i2c@d4018800 { |
| compatible = "mrvl,mmp-twsi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd4018800 0x60>, |
| <0xd40b0300 0x10>; |
| interrupts = <0 23 0x4>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>; |
| marvell,i2c-always-on; |
| mrvl,i2c-fast-mode; |
| marvell,i2c-ilcr = <0x82c469f>; |
| marvell,i2c-iwcr = <0x1434>; |
| soc-bus-reset; |
| clocks = <&soc_clocks ASR1803_CLK_TWSI3>; |
| clock-names = "twsi3_clk"; |
| status = "disabled"; |
| }; |
| twsi4: i2c@d4020000 { |
| compatible = "mrvl,mmp-twsi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd4020000 0x60>; |
| interrupts = <0 24 0x4>; |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_DDR>; |
| mrvl,i2c-fast-mode; |
| marvell,i2c-ilcr = <0x82c469f>; |
| marvell,i2c-iwcr = <0x1434>; |
| pinctrl-names = "default","gpio"; |
| pinctrl-0 = <&twsi4_pmx_func>; |
| pinctrl-1 = <&twsi4_pmx_gpio>; |
| i2c-gpio = <&gpio 35 0 &gpio 36 0>; |
| clocks = <&soc_clocks ASR1803_CLK_TWSI4>; |
| clock-names = "twsi4_clk"; |
| status = "disabled"; |
| }; |
| |
| ssp0: spi@d401b000 { |
| compatible = "asr,asr-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd401b000 0x30>; |
| |
| /* DMA: change 0x10000 to 0x0 in SPI slave mode */ |
| dmas = <&pdma0 9 0x10000 |
| &pdma0 10 0x10000>; |
| dma-names = "rx", "tx"; |
| |
| asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| asr,ssp-clock-rate = <13000000>; |
| asr,ssp-id = <1>; |
| interrupts = <0 35 0x4>; |
| asr,ssp-enhancement; |
| asr,ssp-disable-dma; |
| /* asr,ssp-slave-mode; */ |
| /* asr,slave-rxtimer-to-ms = <0>; */ |
| /* asr,ssp-hold-frame-low; */ |
| /* asr,spi-master-rxto = <8000>; */ |
| /* asr,spi-slave-rxto = <262144>; */ |
| /* asr,spi-pio-interval = <5>; */ |
| clocks = <&soc_clocks ASR1803_CLK_SSP0>; |
| status = "disabled"; |
| }; |
| |
| ssp2: spi@d401c000 { |
| compatible = "asr,asr-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd401c000 0x30>; |
| |
| /* DMA: change 0x10000 to 0x0 in SPI slave mode */ |
| dmas = <&pdma0 11 0x10000 |
| &pdma0 12 0x10000>; |
| dma-names = "rx", "tx"; |
| |
| asr,ssp-lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| asr,ssp-clock-rate = <13000000>; |
| asr,ssp-id = <3>; |
| interrupts = <0 36 0x4>; |
| asr,ssp-enhancement; |
| /* asr,ssp-disable-dma; */ |
| /* asr,ssp-slave-mode; */ |
| /* asr,slave-rxtimer-to-ms = <0>; */ |
| /* asr,ssp-hold-frame-low; */ |
| /* asr,spi-master-rxto = <8000>; */ |
| /* asr,spi-slave-rxto = <262144>; */ |
| /* asr,spi-pio-interval = <5>; */ |
| clocks = <&soc_clocks ASR1803_CLK_SSP2>; |
| status = "disabled"; |
| }; |
| rtc: rtc@d4010000 { |
| compatible = "mrvl,mmp-rtc"; |
| reg = <0xd4010000 0x100>; |
| interrupts = <0 5 0x4 |
| 0 6 0x4>; |
| interrupt-names = "rtc 1Hz", "rtc alarm"; |
| clocks = <&soc_clocks ASR1803_CLK_RTC>; |
| resets = <&soc_clocks ASR1803_CLK_RTC>; |
| status = "disabled"; |
| }; |
| |
| pmx: pinmux@d401e000 { |
| compatible = "pinconf-single"; |
| reg = <0xd401e000 0x330>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| #pinctrl-cells = <1>; |
| #gpio-range-cells = <3>; |
| ranges; |
| |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <7>; |
| |
| range: gpio-range { |
| #pinctrl-single,gpio-range-cells = <3>; |
| }; |
| }; |
| |
| acipc: acipc@d401d000 { |
| compatible = "mrvl,mmp-acipc"; |
| reg = <0xD401d000 0x100>; |
| interrupts = <0 29 0x4>; |
| interrupt-names = "IPC_AP_MUX"; |
| status = "okay"; |
| }; |
| |
| auxadc: auxadc@d4013400 { |
| compatible = "asr,auxadc"; |
| reg = <0xd4013400 0x80>; |
| clocks = <&soc_clocks ASR1803_CLK_AUXADC>; |
| clock-names = "auxadc_clk"; |
| status = "okay"; |
| }; |
| |
| adsp: adsp@d401d100 { |
| compatible = "asr,adsp"; |
| reg = <0xd101c000 0x4000>, |
| <0xd6000000 0x40000>, |
| <0xd6a00000 0x4000>, |
| <0xd6200000 0x10000>, |
| <0xd401d100 0x20>, |
| <0xd401e178 0x10>, |
| <0xd6800014 0x4>, |
| <0xd6800048 0x4>, |
| <0xd4015090 0x4>, |
| <0xd42828f0 0x4>, |
| <0xd428294c 0x4>; |
| interrupts = <0 30 0x4>; |
| interrupt-names = "ipc_adsp2ap_int"; |
| status = "okay"; |
| }; |
| |
| seh { |
| compatible = "mrvl,seh"; |
| /* use CP TIMER for watchdog to notify cp assert */ |
| reg = <0xffffffff 0xff>, <0xd40B0300 0x4>; |
| interrupts = <0 0 0x4>; |
| interrupt-names = "CP_TIMER3"; |
| watchdog-type = <2>; /* wdt CP timer3 */ |
| status = "okay"; |
| }; |
| |
| sulog: ripc1@d40b0100 { |
| compatible = "mrvl,mmp-sulog"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xd40b0100 0x20> , |
| <0xd4050210 0x4>; |
| interrupts = <0 31 0x4>; |
| interrupt-names = "RIPC1_INT"; |
| status = "disabled"; |
| }; |
| |
| cp-load { |
| compatible = "marvell,cp_load"; |
| cp-type = <0x30393838>; /* NZ_MODEM */ |
| lpm-qos = <PM_QOS_CPUIDLE_BLOCK_AXI>; |
| status = "okay"; |
| }; |
| |
| data-path { |
| compatible = "marvell,data-path"; |
| version = <3>; |
| status = "okay"; |
| }; |
| }; |
| |
| soc_clocks: clocks{ |
| compatible = "asr,asr1803-clock"; |
| reg = <0xd4050000 0x3000>, |
| <0xd4282800 0x400>, |
| <0xd4015000 0x1000>, |
| <0xd4090000 0x1000>, |
| <0xd4282c00 0x400>, |
| <0xc0100000 0x5000>; |
| reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "ddrc"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| shared-timer { |
| compatible = "marvell,timer1"; |
| dev_name = "timer1_TS"; |
| version = "build1"; |
| reg = <0xD4016000 0xD0>; |
| status = "okay"; |
| }; |
| |
| mmplog { |
| compatible = "marvell,mmplog-heap"; |
| mmplog-base = <0x01f00000>; |
| mmplog-size = <0x8000>; |
| status = "okay"; |
| }; |
| |
| regs_addr_ioremap { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| mpmu: pmu@d4050000 { |
| compatible = "marvell,mmp-pmu-mpmu"; |
| reg = <0xd4050000 0x2000>; |
| }; |
| apmu: pmu@d4282800 { |
| compatible = "marvell,mmp-pmu-apmu"; |
| reg = <0xd4282800 0x400>; |
| }; |
| apbc: pmu@d4015000 { |
| compatible = "marvell,mmp-pmu-apbc"; |
| reg = <0xd4015000 0x100>; |
| }; |
| apbs: pmu@d4090000 { |
| compatible = "marvell,mmp-apb-spare"; |
| reg = <0xd4090000 0x200>; |
| }; |
| ciu: ciu@d4282c00 { |
| compatible = "marvell,mmp-ciu"; |
| reg = <0xd4282c00 0x300>; |
| }; |
| squ: squ@0xd42a0000 { |
| compatible = "marvell,mmp-squ"; |
| reg = <0xd42a0000 0x1000>; |
| }; |
| mcu: mcu@0xc0100000 { |
| compatible = "marvell,mmp-mcu"; |
| reg = <0xc0100000 0x5000>; |
| }; |
| }; |
| profile { |
| compatible = "marvell,profile"; |
| marvell,profile-number = <0>; |
| }; |
| |
| optee-loglevel { |
| compatible = "asr,log-level"; |
| status = "ok"; |
| }; |
| }; |