| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (C) 2015 STMicroelectronics R&D Limited |
| */ |
| #include <dt-bindings/clock/stih418-clks.h> |
| / { |
| /* |
| * Fixed 30MHz oscillator inputs to SoC |
| */ |
| clk_sysin: clk-sysin { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <30000000>; |
| clock-output-names = "CLK_SYSIN"; |
| }; |
| |
| clk_tmdsout_hdmi: clk-tmdsout-hdmi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| compatible = "st,stih418-clk", "simple-bus"; |
| |
| /* |
| * A9 PLL. |
| */ |
| clockgen-a9@92b0000 { |
| compatible = "st,clkgen-c32"; |
| reg = <0x92b0000 0xffff>; |
| |
| clockgen_a9_pll: clockgen-a9-pll { |
| #clock-cells = <1>; |
| compatible = "st,stih418-clkgen-plla9"; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clockgen-a9-pll-odf"; |
| }; |
| }; |
| |
| /* |
| * ARM CPU related clocks. |
| */ |
| clk_m_a9: clk-m-a9@92b0000 { |
| #clock-cells = <0>; |
| compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; |
| reg = <0x92b0000 0x10000>; |
| |
| clocks = <&clockgen_a9_pll 0>, |
| <&clockgen_a9_pll 0>, |
| <&clk_s_c0_flexgen 13>, |
| <&clk_m_a9_ext2f_div2>; |
| |
| /* |
| * ARM Peripheral clock for timers |
| */ |
| arm_periph_clk: clk-m-a9-periphs { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&clk_m_a9>; |
| clock-div = <2>; |
| clock-mult = <1>; |
| }; |
| }; |
| |
| clockgen-a@90ff000 { |
| compatible = "st,clkgen-c32"; |
| reg = <0x90ff000 0x1000>; |
| |
| clk_s_a0_pll: clk-s-a0-pll { |
| #clock-cells = <1>; |
| compatible = "st,clkgen-pll0"; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-a0-pll-ofd-0"; |
| }; |
| |
| clk_s_a0_flexgen: clk-s-a0-flexgen { |
| compatible = "st,flexgen"; |
| |
| #clock-cells = <1>; |
| |
| clocks = <&clk_s_a0_pll 0>, |
| <&clk_sysin>; |
| |
| clock-output-names = "clk-ic-lmi0", |
| "clk-ic-lmi1"; |
| }; |
| }; |
| |
| clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { |
| #clock-cells = <1>; |
| compatible = "st,quadfs-pll"; |
| reg = <0x9103000 0x1000>; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-c0-fs0-ch0", |
| "clk-s-c0-fs0-ch1", |
| "clk-s-c0-fs0-ch2", |
| "clk-s-c0-fs0-ch3"; |
| }; |
| |
| clk_s_c0: clockgen-c@9103000 { |
| compatible = "st,clkgen-c32"; |
| reg = <0x9103000 0x1000>; |
| |
| clk_s_c0_pll0: clk-s-c0-pll0 { |
| #clock-cells = <1>; |
| compatible = "st,clkgen-pll0"; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-c0-pll0-odf-0"; |
| }; |
| |
| clk_s_c0_pll1: clk-s-c0-pll1 { |
| #clock-cells = <1>; |
| compatible = "st,clkgen-pll1"; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-c0-pll1-odf-0"; |
| }; |
| |
| clk_s_c0_flexgen: clk-s-c0-flexgen { |
| #clock-cells = <1>; |
| compatible = "st,flexgen"; |
| |
| clocks = <&clk_s_c0_pll0 0>, |
| <&clk_s_c0_pll1 0>, |
| <&clk_s_c0_quadfs 0>, |
| <&clk_s_c0_quadfs 1>, |
| <&clk_s_c0_quadfs 2>, |
| <&clk_s_c0_quadfs 3>, |
| <&clk_sysin>; |
| |
| clock-output-names = "clk-icn-gpu", |
| "clk-fdma", |
| "clk-nand", |
| "clk-hva", |
| "clk-proc-stfe", |
| "clk-tp", |
| "clk-rx-icn-dmu", |
| "clk-rx-icn-hva", |
| "clk-icn-cpu", |
| "clk-tx-icn-dmu", |
| "clk-mmc-0", |
| "clk-mmc-1", |
| "clk-jpegdec", |
| "clk-icn-reg", |
| "clk-proc-bdisp-0", |
| "clk-proc-bdisp-1", |
| "clk-pp-dmu", |
| "clk-vid-dmu", |
| "clk-dss-lpc", |
| "clk-st231-aud-0", |
| "clk-st231-gp-1", |
| "clk-st231-dmu", |
| "clk-icn-lmi", |
| "clk-tx-icn-1", |
| "clk-icn-sbc", |
| "clk-stfe-frc2", |
| "clk-eth-phyref", |
| "clk-eth-ref-phyclk", |
| "clk-flash-promip", |
| "clk-main-disp", |
| "clk-aux-disp", |
| "clk-compo-dvp", |
| "clk-tx-icn-hades", |
| "clk-rx-icn-hades", |
| "clk-icn-reg-16", |
| "clk-pp-hevc", |
| "clk-clust-hevc", |
| "clk-hwpe-hevc", |
| "clk-fc-hevc", |
| "clk-proc-mixer", |
| "clk-proc-sc", |
| "clk-avsp-hevc"; |
| |
| /* |
| * ARM Peripheral clock for timers |
| */ |
| clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| |
| clocks = <&clk_s_c0_flexgen 13>; |
| |
| clock-output-names = "clk-m-a9-ext2f-div2"; |
| |
| clock-div = <2>; |
| clock-mult = <1>; |
| }; |
| }; |
| }; |
| |
| clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { |
| #clock-cells = <1>; |
| compatible = "st,quadfs"; |
| reg = <0x9104000 0x1000>; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-d0-fs0-ch0", |
| "clk-s-d0-fs0-ch1", |
| "clk-s-d0-fs0-ch2", |
| "clk-s-d0-fs0-ch3"; |
| }; |
| |
| clockgen-d0@9104000 { |
| compatible = "st,clkgen-c32"; |
| reg = <0x9104000 0x1000>; |
| |
| clk_s_d0_flexgen: clk-s-d0-flexgen { |
| #clock-cells = <1>; |
| compatible = "st,flexgen-audio", "st,flexgen"; |
| |
| clocks = <&clk_s_d0_quadfs 0>, |
| <&clk_s_d0_quadfs 1>, |
| <&clk_s_d0_quadfs 2>, |
| <&clk_s_d0_quadfs 3>, |
| <&clk_sysin>; |
| |
| clock-output-names = "clk-pcm-0", |
| "clk-pcm-1", |
| "clk-pcm-2", |
| "clk-spdiff", |
| "clk-pcmr10-master", |
| "clk-usb2-phy"; |
| }; |
| }; |
| |
| clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { |
| #clock-cells = <1>; |
| compatible = "st,quadfs"; |
| reg = <0x9106000 0x1000>; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-d2-fs0-ch0", |
| "clk-s-d2-fs0-ch1", |
| "clk-s-d2-fs0-ch2", |
| "clk-s-d2-fs0-ch3"; |
| }; |
| |
| clockgen-d2@9106000 { |
| compatible = "st,clkgen-c32"; |
| reg = <0x9106000 0x1000>; |
| |
| clk_s_d2_flexgen: clk-s-d2-flexgen { |
| #clock-cells = <1>; |
| compatible = "st,flexgen-video", "st,flexgen"; |
| |
| clocks = <&clk_s_d2_quadfs 0>, |
| <&clk_s_d2_quadfs 1>, |
| <&clk_s_d2_quadfs 2>, |
| <&clk_s_d2_quadfs 3>, |
| <&clk_sysin>, |
| <&clk_sysin>, |
| <&clk_tmdsout_hdmi>; |
| |
| clock-output-names = "clk-pix-main-disp", |
| "", |
| "", |
| "", |
| "", |
| "clk-tmds-hdmi-div2", |
| "clk-pix-aux-disp", |
| "clk-denc", |
| "clk-pix-hddac", |
| "clk-hddac", |
| "clk-sddac", |
| "clk-pix-dvo", |
| "clk-dvo", |
| "clk-pix-hdmi", |
| "clk-tmds-hdmi", |
| "clk-ref-hdmiphy", |
| "", "", "", "", "", |
| "", "", "", "", "", |
| "", "", "", "", "", |
| "", "", "", "", "", |
| "", "", "", "", "", |
| "", "", "", "", "", |
| "", "clk-vp9"; |
| }; |
| }; |
| |
| clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { |
| #clock-cells = <1>; |
| compatible = "st,quadfs"; |
| reg = <0x9107000 0x1000>; |
| |
| clocks = <&clk_sysin>; |
| |
| clock-output-names = "clk-s-d3-fs0-ch0", |
| "clk-s-d3-fs0-ch1", |
| "clk-s-d3-fs0-ch2", |
| "clk-s-d3-fs0-ch3"; |
| }; |
| |
| clockgen-d3@9107000 { |
| compatible = "st,clkgen-c32"; |
| reg = <0x9107000 0x1000>; |
| |
| clk_s_d3_flexgen: clk-s-d3-flexgen { |
| #clock-cells = <1>; |
| compatible = "st,flexgen"; |
| |
| clocks = <&clk_s_d3_quadfs 0>, |
| <&clk_s_d3_quadfs 1>, |
| <&clk_s_d3_quadfs 2>, |
| <&clk_s_d3_quadfs 3>, |
| <&clk_sysin>; |
| |
| clock-output-names = "clk-stfe-frc1", |
| "clk-tsout-0", |
| "clk-tsout-1", |
| "clk-mchi", |
| "clk-vsens-compo", |
| "clk-frc1-remote", |
| "clk-lpc-0", |
| "clk-lpc-1"; |
| }; |
| }; |
| }; |
| }; |