| /* |
| * Copyright (C) 2021 ASR Ltd. |
| */ |
| #ifndef __PCIE_FALCON_H__ |
| #define __PCIE_FALCON_H__ |
| |
| /* Host Bridge Identification */ |
| #define DEVICE_NAME "ASR Falcon PCIe Host" |
| #define FALCON_MSI_IRQS_NUM 32 |
| |
| #define PHY1_BASE 0xd4210400 |
| #define PHY2_BASE 0xd4220400 |
| |
| #ifdef CONFIG_CPU_ASR1903 |
| #define APMU_PCIE_CLK_RST_CTRL 0x170 |
| #else |
| #define APMU_PCIE_CLK_RST_CTRL 0x164 |
| #define APMU_PCIE2_CLK_RST_CTRL 0x16C |
| #endif |
| #define PCIE_RESET_ASSERT (~(0xff)) |
| #define PCIE_RESET_DEASSERT (0xff) |
| |
| #define INT_STATUS1 0xc |
| #define INT_STATUS2 0x10 |
| #define RX_MSI_INT (0x1<<28) |
| |
| #define PCIE_CFGCTRL 0x84 |
| #define PCIE_BAR0 0xE4 |
| #define PCIE_BAR1 0xE8 |
| #define PCIE_CFGNUM 0x140 |
| #define IMSI_ADDR 0x190 |
| |
| #define FALCON_PCIE_CONFIG_OFFSET 0x1000 |
| |
| #define CFG_DEVICE_VENDOR 0x1000 |
| #define CFG_STATUS_COMMAND 0x1004 |
| #define CFG_BAR0_REG 0x1010 |
| #define CFG_BAR1_REG 0x1014 |
| #define CFG_SUBSEC_PRIM 0x1018 |
| #define CFG_DEVICE_CAP 0x1084 |
| #define CFG_DEVICE_CTRL 0x1088 |
| #define CFG_DEVICE_GEN_SPEED 0x10B0 |
| |
| #define BAR0_ADDR 0xF0000000 |
| |
| #define PUPHY_LTSSM 0x8 |
| |
| #define PUPHY_CLK_CFG 0x408 |
| #define PUPHY_MODE_CFG 0x40c |
| #define PUPHY_PLL_REG1 0x448 |
| |
| #define INTX_SHIFT 16 |
| |
| /* Host Bridge Internal Registers */ |
| #define XR3PCI_BASIC_STATUS 0x18 |
| #define XR3PCI_BS_LINK_MASK 0xff |
| #define XR3PCI_BS_GEN_MASK (0xf << 8) |
| #define XR3PCI_BS_NEG_PAYLOAD_MASK (0xf << 24) |
| #define XR3PCI_BS_NEG_REQSIZE_MASK (0xf << 28) |
| |
| #define XR3PCI_LOCAL_INT_MASK 0x180 |
| #define XR3PCI_LOCAL_INT_STATUS 0x184 |
| #define XR3PCI_HOST_INT_STATUS 0x18C |
| #define XR3PCI_MSI_INT_STATUS 0x194 |
| |
| #define XR3PCI_INT_A (1 << 24) |
| #define XR3PCI_INT_B (1 << 25) |
| #define XR3PCI_INT_C (1 << 26) |
| #define XR3PCI_INT_D (1 << 27) |
| #define XR3PCI_INT_INTx (XR3PCI_INT_A | XR3PCI_INT_B | \ |
| XR3PCI_INT_C | XR3PCI_INT_D) |
| #define XR3PCI_INT_MSI (1 << 28) |
| |
| #define XR3PCI_VIRTCHAN_CREDITS 0x90 |
| #define XR3PCI_PEX_SPC2 0xd8 |
| |
| /* Address Translation Register */ |
| #define XR3PCI_ATR_PCIE_WIN0 0x600 |
| #define XR3PCI_ATR_PCIE_WIN1 0x700 |
| #define XR3PCI_ATR_AXI4_SLV0 0x800 |
| |
| #define XR3PCI_ATR_TABLE_SIZE 0x20 |
| #define XR3PCI_ATR_SRC_ADDR_LOW 0x0 |
| #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 |
| #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 |
| #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc |
| #define XR3PCI_ATR_TRSL_PARAM 0x10 |
| |
| /* IDs used in the XR3PCI_ATR_TRSL_PARAM */ |
| #define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004) |
| #define XR3PCI_ATR_TRSLID_AXIMEMORY 0x4 |
| #define XR3PCI_ATR_TRSLID_PCIE_CONF 0x0 |
| #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000) |
| #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000) |
| |
| #endif |
| |