| /* SPDX-License-Identifier: GPL-2.0 */ |
| #ifndef __DTS_MARVELL_ASR1803_CLOCK_H |
| #define __DTS_MARVELL_ASR1803_CLOCK_H |
| |
| /* fixed clocks and plls */ |
| #define ASR1803_CLK_CLK32 1 |
| #define ASR1803_CLK_VCTCXO 2 |
| #define ASR1803_CLK_PLL1 3 |
| #define ASR1803_CLK_PLL1_2 8 |
| #define ASR1803_CLK_PLL1_4 9 |
| #define ASR1803_CLK_PLL1_8 10 |
| #define ASR1803_CLK_PLL1_16 11 |
| #define ASR1803_CLK_PLL1_6 12 |
| #define ASR1803_CLK_PLL1_12 13 |
| #define ASR1803_CLK_PLL1_24 14 |
| #define ASR1803_CLK_PLL1_48 15 |
| #define ASR1803_CLK_PLL1_96 16 |
| #define ASR1803_CLK_PLL1_13 17 |
| #define ASR1803_CLK_PLL1_13_1_5 18 |
| #define ASR1803_CLK_PLL1_2_1_5 19 |
| #define ASR1803_CLK_PLL1_3_16 20 |
| #define ASR1803_CLK_PLL1_192 21 |
| #define ASR1803_CLK_PLL1_384 22 |
| #define ASR1803_CLK_PLL1_768 23 |
| #define ASR1803_CLK_CLK16 24 |
| |
| #define ASR1803_CLK_UART_PLL2 26 |
| #define ASR1803_CLK_UART_PLL 27 |
| #define ASR1803_CLK_USB_PLL 28 |
| #define ASR1803_CLK_PLL1_1248 29 |
| #define ASR1803_CLK_PLL1_832 30 |
| #define ASR1803_CLK_PLL1_416 31 |
| #define ASR1803_CLK_PLL1_312 32 |
| #define ASR1803_CLK_PLL1_208 33 |
| #define ASR1803_CLK_PLL1_156 34 |
| #define ASR1803_CLK_DPLL 35 |
| #define ASR1803_CLK_PLL1_1475 36 |
| #define ASR1803_CLK_PLL1_983 37 |
| #define ASR1803_CLK_DPLL_1600 38 |
| #define ASR1803_CLK_DPLL_2133 39 |
| |
| #define ASR1803_CLK_I2S_PLL 40 |
| #define ASR1803_CLK_I2S_SYSCLK 41 |
| #define ASR1803_CLK_I2S_SSP 42 |
| #define ASR1803_CLK_DPLL_2000 43 |
| #define ASR1803_CLK_I2S_PLL_2 44 |
| #define ASR1803_CLK_VCTCXO_REQ 45 |
| |
| #define ASR1803_CLK_PLL1_356 46 |
| #define ASR1803_CLK_PLL1_375 47 |
| #define ASR1803_CLK_PLL1_277 48 |
| #define ASR1803_CLK_PLL1_108 49 |
| #define ASR1803_CLK_PLL1_499 50 |
| #define ASR1803_CLK_PLL1_192M 51 |
| |
| #define ASR1803_CLK_PLL2_1500 52 |
| |
| #define ASR1803_CLK_PLL1_249 53 |
| #define ASR1803_CLK_PLL1_52 54 |
| #define ASR1803_CLK_PLL1_227 55 |
| #define ASR1803_CLK_UART_58P5M 56 |
| #define ASR1803_CLK_UART_PLL1P 57 |
| #define ASR1803_CLK_UART_PLL2P 58 |
| #define ASR1803_CLK_UART_PLLNE 59 |
| |
| /* apb periphrals */ |
| #define ASR1803_CLK_TWSI0 60 |
| #define ASR1803_CLK_TWSI1 61 |
| #define ASR1803_CLK_TWSI2 62 |
| #define ASR1803_CLK_TWSI3 63 |
| #define ASR1803_CLK_GPIO 64 |
| #define ASR1803_CLK_KPC 65 |
| #define ASR1803_CLK_RTC 66 |
| #define ASR1803_CLK_PWM0 67 |
| #define ASR1803_CLK_PWM1 68 |
| #define ASR1803_CLK_PWM2 69 |
| #define ASR1803_CLK_PWM3 70 |
| #define ASR1803_CLK_UART0 71 |
| #define ASR1803_CLK_UART1 72 |
| #define ASR1803_CLK_UART2 73 |
| #define ASR1803_CLK_SSP0 74 |
| #define ASR1803_CLK_SSP1 75 |
| #define ASR1803_CLK_SSP2 76 |
| #define ASR1803_CLK_TIMER0 77 |
| #define ASR1803_CLK_TIMER1 78 |
| #define ASR1803_CLK_ONWIRE 79 |
| #define ASR1803_CLK_TSEN 80 |
| #define ASR1803_CLK_IPC 81 |
| #define ASR1803_CLK_RIPC 82 |
| #define ASR1803_CLK_TIMER2 83 |
| #define ASR1803_CLK_TWSI4 84 |
| #define ASR1806_CLK_TSC 85 |
| #define ASR1803_CLK_AUXADC 86 |
| #define ASR1803_CLK_UART3 87 |
| |
| /* axi periphrals */ |
| #define ASR1803_CLK_DFC 100 |
| #define ASR1803_CLK_SDH0 101 |
| #define ASR1803_CLK_SDH1 102 |
| #define ASR1803_CLK_SDH2 103 |
| #define ASR1803_CLK_USB 104 |
| #define ASR1803_CLK_SPH 105 |
| #define ASR1803_CLK_GEU 106 |
| #define ASR1803_CLK_EMAC 107 |
| #define ASR1901_CLK_XGMAC 107 |
| #define ASR1803_CLK_SDH_AXI 108 |
| #define ASR1803_CLK_QSPI_FCLK 109 |
| #define ASR1803_CLK_QSPI 110 |
| #define ASR1803_CLK_DBG 111 |
| #define ASR1803_CLK_TRACE 112 |
| #define ASR1803_CLK_QSPI_BUS 113 |
| #define ASR1803_CLK_PCIE0 114 |
| #define ASR1803_CLK_PCIE1 115 |
| #define ASR1803_CLK_SDH0_TUNE 116 |
| #define ASR1803_CLK_SDH1_TUNE 117 |
| #define ASR1803_CLK_CAMERA 118 |
| #define ASR1803_CLK_QSPI_DTR 119 |
| #define ASR1803_CLK_PLL1_VCO 120 |
| #define ASR1803_CLK_PLL2_VCO 121 |
| #define ASR1803_CLK_PLL1_38M4 122 |
| #define ASR1803_CLK_EMAC_PTP 123 |
| #define ASR1803_CLK_XGMAC_DUMMY 124 |
| |
| /* ddr/axi etc */ |
| #define ASR1803_CLK_DDR 180 |
| #define ASR1803_CLK_AXI 181 |
| #define ASR1803_CLK_CPU 182 |
| |
| /*alias*/ |
| #define ASR1803_CLK_CPUART ASR1803_CLK_UART2 |
| #define ASR1803_CLK_APUART1 ASR1803_CLK_UART0 |
| #define ASR1803_CLK_APUART2 ASR1803_CLK_UART1 |
| #define ASR1803_CLK_APUART3 ASR1803_CLK_UART3 |
| /* only for ASR1903 */ |
| #define ASR1803_CLK_APUART4 ASR1803_CLK_UART2 |
| |
| #define ASR1803_NR_CLKS 200 |
| #endif |