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192.168.1.100 / T108 / c2023d5d03be91dbb983606f0ec5e9e4ea36c8c2 / . / marvell / linux / sound / soc / pxa / pxa-ssp.c
blob: 0f0b36078315cf48fc8cca1e34618ec0839951f9 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pxa-ssp.c -- ALSA Soc Audio Layer
*
* Copyright 2005,2008 Wolfson Microelectronics PLC.
* Author: Liam Girdwood
* Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* TODO:
* o Test network mode for > 16bit sample size
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/pxa2xx_ssp.h>
#include <linux/of.h>
#include <linux/dmaengine.h>
#include <linux/delay.h>
#include <linux/platform_data/mmp_audio.h>
#include <linux/pinctrl/consumer.h>
#include <linux/of_gpio.h>
#include <linux/features.h>
#include <linux/debugfs.h>
#include <asm/irq.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <sound/dmaengine_pcm.h>
#include <linux/dma-mapping.h>
#include "pxa-ssp.h"
#include <linux/pxa2xx_ssp.h>
extern u32 top_ctrl_hifi;
extern u32 fifo_ctrl_hifi;
extern u32 rwot_ctrl_hifi;
extern u32 network_ctrl_hifi;
extern u32 int_en_hifi;
extern void set_ssp_role(int role);
extern int get_ssp_role(void);
static int reg_ssp = 0xffff;
struct dentry *ssp_dump_reg = NULL;
struct ssp_device *g_ssp = NULL;
#define APBC_SSP1_CLK_RST_ADDR (0xD4015020)
#define PMU_SQU_CLK_GATE_CTRL_ADDR (0xD428281C)
#define SQU_CTRL_0_ADDR (0xD42A0000)
#define FCCR_ADDR (0xD4050008)
#define ISCCR2_ADDR (0xD4050044)
#define ICU_DMA_SEAGULL_INT_STATUS_ADDR (0xD4282120)
#define DMA_BASE_ADDR (0xD4000000)
static void __iomem *APBC_SSP1_CLK_RST_reg = NULL;
static void __iomem *PMU_SQU_CLK_GATE_CTRL_reg = NULL;
static void __iomem *SQU_CTRL_0_reg = NULL;
static void __iomem *FCCR_reg = NULL;
static void __iomem *ISCCR2_reg = NULL;
static void __iomem *ICU_DMA_SEAGULL_INT_STATUS_reg = NULL;
static void __iomem *DMA_BASE_reg = NULL;
/* Debug Master/SLave, Frame sync, BitClk for SSP */
typedef enum{
SSP_BCLK_16_FS = 0,
SSP_BCLK_32_FS,
SSP_BCLK_64_FS,
SSP_BCLK_MAX_FS = SSP_BCLK_64_FS
} SSP_BCLK_TYPE;
typedef enum{
SAMPLE_FREQUENCY_8000 = 0,
SAMPLE_FREQUENCY_16000,
SAMPLE_FREQUENCY_44100,
MAX_SAMPLE_FREQUENCY = SAMPLE_FREQUENCY_44100
} SAMPLE_FREQUENCY_ID;
typedef enum{
SSP_FRAME_BITS_16FS = 0,
SSP_FRAME_BITS_32FS,
SSP_FRAME_BITS_64FS,
SSP_FRAME_BITS_MAX_FS = SSP_FRAME_BITS_64FS
} SSP_FRAME_BITS;
static int g_gssp_bclk_type = SSP_BCLK_32_FS;
static int g_switch_frame_bits = SSP_FRAME_BITS_32FS;
static int g_enable_switch_frame_bits = 0;
static int g_status_debug_tools = 0;/* debug tools for ssp register */
static int g_status_IFS = 1;/* SSP_TOP_CTRL bit15 */
static int g_status_SFRMP = 0;/* SSP_PSP_CTRL bit4 */
static int g_status_SCMODE = 1;/* SSP_PSP_CTRL bit1~0 0x0~0x3 */
static int g_frame_bits = (1 << SSP_FRAME_BITS_32FS) * 16;
static int Audio_WB_AMR_Enable = 0;
u32 top_ctrl_UI = 0;
u32 fifo_ctrl_UI = 0;
u32 int_en_UI = 0;
u32 psp_ctrl_UI = 0;
u32 network_ctrl_UI = 0;
u32 get_reg_value_from_UI(int offset)
{
if (TOP_CTRL == offset) {
/* SSP_TOP_CTRL */
return top_ctrl_UI;
} else if (FIFO_CTRL == offset) {
/* SSP_FIFO_CTRL */
return fifo_ctrl_UI;
} else if (INT_EN == offset) {
/* SSP_INT_CTRL */
return int_en_UI;
} else if (PSP_CTRL == offset) {
/* SSP_PSP_CTRL */
return psp_ctrl_UI;
} else if (NET_WORK_CTRL == offset) {
/* SSP_NET_WORK_CTRL */
return network_ctrl_UI;
}
return 0;
}
/* Enable the clk */
static void UI_enable_clk(struct ssp_device *ssp)
{
clk_prepare_enable(ssp->clk);
return;
}
/* Disable the clk */
static void UI_disable_clk(struct ssp_device *ssp)
{
clk_disable_unprepare(ssp->clk);
return;
}
/* Enable the ssp */
static void UI_enable_ssp(struct ssp_device *ssp)
{
uint32_t top_ctrl;
top_ctrl = __raw_readl(ssp->mmio_base + TOP_CTRL) | TOP_SSE;
__raw_writel(top_ctrl, ssp->mmio_base + TOP_CTRL);
return;
}
/* Disable the ssp */
static void UI_disable_ssp(struct ssp_device *ssp)
{
uint32_t top_ctrl;
top_ctrl = __raw_readl(ssp->mmio_base + TOP_CTRL) & ~TOP_SSE;
__raw_writel(top_ctrl, ssp->mmio_base + TOP_CTRL);
return;
}
/* Master/Slave switch */
static void UI_switch_SSP_role(void)
{
int ssp_role;
ssp_role = get_ssp_role();
set_ssp_role(++ssp_role % 2);
return;
}
/* Frame sync */
static void UI_Reverse_WBNB(void)
{
if (Audio_WB_AMR_Enable)
Audio_WB_AMR_Enable = 0;
else
Audio_WB_AMR_Enable = 1;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, Audio_WB_AMR_Enable is %s.\n", __FUNCTION__, __LINE__, Audio_WB_AMR_Enable?"WB":"NB");
#endif
return;
}
/* BitClk */
static int set_BCLK_type(int bclk_type)
{
if(bclk_type > SSP_BCLK_MAX_FS){
printk(KERN_INFO"BCLK_MAX_FS = %d, bclk_type = %d.\n", g_gssp_bclk_type, bclk_type);
return -1;
}
#ifdef DEBUG_SSP1
printk(KERN_INFO"old = %d, new = %d.\n", g_gssp_bclk_type, bclk_type);
#endif
g_gssp_bclk_type = bclk_type;
return 0;
}
static void UI_switch_bitclk_FS(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"switch_bitclk_fs.\n");
#endif
set_BCLK_type((g_gssp_bclk_type + 1) % 4);
return;
}
/* FRAME BITS */
static int set_frame_bits(int switch_frame_bits)
{
g_switch_frame_bits = switch_frame_bits;
g_frame_bits = (1 << switch_frame_bits) * 16;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_switch_frame_bits=%d, g_frame_bits=%d.\n", __FUNCTION__, g_switch_frame_bits, g_frame_bits);
#endif
return 0;
}
int get_frame_bits(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_frame_bits=%d.\n", __FUNCTION__, g_frame_bits);
#endif
return g_frame_bits;
}
static void UI_switch_frame_bits(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"switch frame bits.\n");
#endif
set_frame_bits((g_switch_frame_bits + 1) % 3);
return;
}
/* Enable/Disable switch frame bits */
static int enable_switch_frame_bits(int status)
{
g_enable_switch_frame_bits = status;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_enable_switch_frame_bits=%d.\n", __FUNCTION__, g_enable_switch_frame_bits);
#endif
return 0;
}
int get_status_switch_frame_bits(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_enable_switch_frame_bits=%d.\n", __FUNCTION__, g_enable_switch_frame_bits);
#endif
return g_enable_switch_frame_bits;
}
static void UI_enable_switch_frame_bits(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"enable/disable switch frame bits.\n");
#endif
enable_switch_frame_bits((g_enable_switch_frame_bits + 1) % 2);
return;
}
/* open debug interface for several registers control in pxa_88pm805_hifi_prepare() pxa-88pm805.c */
static int switch_debug_tools(int status)
{
g_status_debug_tools = status;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_debug_tools=%d.\n", __FUNCTION__, g_status_debug_tools);
#endif
return 0;
}
int get_status_debug_tools(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_debug_tools=%d.\n", __FUNCTION__, g_status_debug_tools);
#endif
return g_status_debug_tools;
}
static void UI_switch_debug_tools(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"UI_switch_debug_tools.\n");
#endif
switch_debug_tools((g_status_debug_tools + 1) % 2);
return;
}
/* Display all global control variables */
static void UI_display_global_ctrl_var(void)
{
printk(KERN_INFO"g_gssp_bclk_type = %d.\n", g_gssp_bclk_type);
printk(KERN_INFO"g_switch_frame_bits = %d.\n", g_switch_frame_bits);
printk(KERN_INFO"g_enable_switch_frame_bits = %d.\n", g_enable_switch_frame_bits);
printk(KERN_INFO"g_status_debug_tools = %d.\n", g_status_debug_tools);
printk(KERN_INFO"g_status_IFS = %d.\n", g_status_IFS);
printk(KERN_INFO"g_status_SFRMP = %d.\n", g_status_SFRMP);
printk(KERN_INFO"g_status_SCMODE = %d.\n", g_status_SCMODE);
printk(KERN_INFO"g_frame_bits = %d.\n", g_frame_bits);
printk(KERN_INFO"Audio_WB_AMR_Enable = %d.\n", Audio_WB_AMR_Enable);
return;
}
/* SSP_TOP_CTRL bit15: IFS = Invert Frame Signal */
static int switch_IFS(int status)
{
g_status_IFS = status;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_IFS=%d.\n", __FUNCTION__, g_status_IFS);
#endif
return 0;
}
int get_status_IFS(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_IFS=%d.\n", __FUNCTION__, g_status_IFS);
#endif
return g_status_IFS;
}
static void UI_switch_IFS(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"UI_switch_IFS.\n");
#endif
switch_IFS((g_status_IFS + 1) % 2);
return;
}
/* SSP_PSP_CTRL bit4: SFRMP = Serial Frame Polarity */
static int switch_SFRMP(int status)
{
g_status_SFRMP = status;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_SFRMP=%d.\n", __FUNCTION__, g_status_SFRMP);
#endif
return 0;
}
int get_status_SFRMP(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_SFRMP=%d.\n", __FUNCTION__, g_status_SFRMP);
#endif
return g_status_SFRMP;
}
static void UI_switch_SFRMP(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"UI_switch_SFRMP.\n");
#endif
switch_SFRMP((g_status_SFRMP + 1) % 2);
return;
}
/* SSP_PSP_CTRL bit1~0: SCMODE = Serial Bit-rate Clock Mode */
static int switch_SCMODE(int status)
{
g_status_SCMODE = status;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_SCMODE=%d.\n", __FUNCTION__, g_status_SCMODE);
#endif
return 0;
}
int get_status_SCMODE(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: g_status_SCMODE=%d.\n", __FUNCTION__, g_status_SCMODE);
#endif
return g_status_SCMODE;
}
static void UI_switch_SCMODE(void)
{
#ifdef DEBUG_SSP1
printk(KERN_INFO"UI_switch_SCMODE.\n");
#endif
switch_SCMODE((g_status_SCMODE + 1) % 4);
return;
}
#if 0
/* config I2S format */
static void UI_config_SSP_I2S_format(void)
{
/* write the register */
pxa_ssp_write_reg(g_ssp, 0x00, 0x0002a3e7);
pxa_ssp_write_reg(g_ssp, 0x04, 0x00000c63);
pxa_ssp_write_reg(g_ssp, 0x08, 0x0000000f);
pxa_ssp_write_reg(g_ssp, 0x0C, 0x00000200);
pxa_ssp_write_reg(g_ssp, 0x18, 0x00010009);
pxa_ssp_write_reg(g_ssp, 0x1C, 0x00000000);
/* Enable the ssp */
UI_enable_ssp(g_ssp);
return;
}
/* Open SSP clock */
static void UI_config_APBC_SSP1_CLK_RST(void)
{
uint32_t reg_value = 0;
#if 1
int i;
/* APBC_SSP1_CLK_RST */
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read before write 0x07: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
/* Reset ssp1 clock */
reg_value = 0x7;
iowrite32(reg_value, APBC_SSP1_CLK_RST_reg);
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read after write 0x07: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
for (i=0; i<5; i++)
{
}
/* Enable SSP1 clock */
reg_value = 0x3;
iowrite32(reg_value, APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read after write 0x03: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
#endif
}
/* init the SSP clock */
static void UI_init_SSP_clk(void)
{
uint32_t reg_value = 0;
#if 0
int i;
/* APBC_SSP1_CLK_RST */
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read before write 0x07: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
/* Reset ssp1 clock */
reg_value = 0x7;
iowrite32(reg_value, APBC_SSP1_CLK_RST_reg);
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read after write 0x07: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
for (i=0; i<5; i++)
{
}
/* Enable SSP1 clock */
reg_value = 0x3;
iowrite32(reg_value, APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read after write 0x03: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
#endif
/* PMU_SQU_CLK_GATE_CTRL */
reg_value = ioread32(PMU_SQU_CLK_GATE_CTRL_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, PMU_SQU_CLK_GATE_CTRL: read before write: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
reg_value &= ~(0x1<<30);
iowrite32(reg_value, PMU_SQU_CLK_GATE_CTRL_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(PMU_SQU_CLK_GATE_CTRL_reg);
printk(KERN_INFO"%s/L%d, PMU_SQU_CLK_GATE_CTRL: read after write: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
/* SQU_CTRL_0 */
reg_value = ioread32(SQU_CTRL_0_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, SQU_CTRL_0: read before write: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
reg_value |= (0x7<<2);
iowrite32(reg_value, SQU_CTRL_0_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(SQU_CTRL_0_reg);
printk(KERN_INFO"%s/L%d, SQU_CTRL_0 : read after write: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
/* FCCR */
reg_value = ioread32(FCCR_reg);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, FCCR: read before write: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
reg_value &= ~(0x1<<28);
iowrite32(reg_value, FCCR_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(FCCR_reg);
printk(KERN_INFO"%s/L%d, FCCR : read after write: reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
#endif
return;
}
/* test BitClk of ISCCR2 */
static void UI_read_ISCCR2(void)
{
uint32_t reg_value = 0;
reg_value = ioread32(ISCCR2_reg);
printk(KERN_INFO"%s/L%d, ISCCR2: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
return;
}
#endif
static void UI_write_ISCCR2(uint32_t write_reg_value)
{
#ifdef DEBUG_SSP1
uint32_t reg_value;
reg_value = ioread32(ISCCR2_reg);
printk(KERN_INFO"%s/L%d,ISCCR2: read before write: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
#endif
iowrite32(write_reg_value, ISCCR2_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(ISCCR2_reg);
printk(KERN_INFO"%s/L%d,ISCCR2: read after write: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
#endif
return;
}
static void UI_read_SSP_regs(void)
{
uint32_t reg_value = 0;
int i;
/* APBC_SSP1_CLK_RST */
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read : reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
/* PMU_SQU_CLK_GATE_CTRL */
reg_value = ioread32(PMU_SQU_CLK_GATE_CTRL_reg);
printk(KERN_INFO"%s/L%d, PMU_SQU_CLK_GATE_CTRL: read : reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
/* SQU_CTRL_0 */
reg_value = ioread32(SQU_CTRL_0_reg);
printk(KERN_INFO"%s/L%d, SQU_CTRL_0: read : reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
/* FCCR */
reg_value = ioread32(FCCR_reg);
printk(KERN_INFO"%s/L%d, FCCR: read : reg_value=0x%x.\n", __FUNCTION__, __LINE__, reg_value);
/* ISCCR2 */
reg_value = ioread32(ISCCR2_reg);
printk(KERN_INFO"%s/L%d, ISCCR2: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
/* ICU_DMA_SEAGULL_INT_STATUS */
reg_value = ioread32(ICU_DMA_SEAGULL_INT_STATUS_reg);
printk(KERN_INFO"%s/L%d, DMA_DADRX[0xD4282120]: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
for (i=0; i<=15; i++)
{
reg_value = ioread32(DMA_BASE_reg + 4*i);
printk(KERN_INFO"%s/L%d, DMA_BASE[0xD4000000 + 0x%x]: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, (4*i), reg_value);
}
reg_value = ioread32(DMA_BASE_reg + 0xF0);
printk(KERN_INFO"%s/L%d, DMA_BASE[0xD4000000 + 0xF0]: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
for (i=0; i<=64; i++)
{
reg_value = ioread32(DMA_BASE_reg + 0x200 + 4*i);
printk(KERN_INFO"%s/L%d, DMA_BASE[0xD4000000 + 0x%x]: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, (0x200 + 4*i), reg_value);
}
return;
}
/* SSP1 Clock: APBC_SSP1_CLK_RST */
#if 0
static void UI_read_APBC_SSP1_CLK_RST(void)
{
uint32_t reg_value = 0;
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
return;
}
#endif
static void UI_write_APBC_SSP1_CLK_RST(uint32_t write_reg_value)
{
#ifdef DEBUG_SSP1
uint32_t reg_value;
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read before write: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
#endif
iowrite32(write_reg_value, APBC_SSP1_CLK_RST_reg);
#ifdef DEBUG_SSP1
reg_value = ioread32(APBC_SSP1_CLK_RST_reg);
printk(KERN_INFO"%s/L%d, APBC_SSP1_CLK_RST: read after write: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
#endif
return;
}
/* config SSP bitclk */
void UI_config_SSP_BCLK(SSP_BCLK_TYPE bclk_type, SAMPLE_FREQUENCY_ID sample_frequency_id)
{
/****************************************************************
* Base Clock is 156MHz *
*****************************************************************
*F_bit-clock = (156*1024K)*(M/N)/(4,6,8Div)
*F_frame-clock = F_bit-clock/Frame-width
* = (156*1024K)*(M/N)/[(4,6,8Div)*Frame_width]
* = (156*1024K)*M/[(4,6,8Div)*Frame_width*N]
*
*Example:2channels, 44.1KHz, 16bits
*M=0x211=529; N=0x07242=29250; Frame_width = 32; (4,6,8Div)=2;
*F_frame-clock = (156*1024K)*M/[(4,6,8Div)*Frame_width*N]
* ~=44.1 KHz
*
****************************************************************/
unsigned int numerator = 0x07242; /* 29250 */
unsigned int denominator = 0x060;
unsigned int isscr = 0;
#ifdef DEBUG_SSP1
uint32_t reg_value = 0;
#endif
//unsigned int sscr0_frdc = 0;
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s/L%d, bclk_type=%d, sample_frequency_id=%d.\n", __FUNCTION__, __LINE__, bclk_type, sample_frequency_id);
#endif
if (sample_frequency_id > MAX_SAMPLE_FREQUENCY)
{
sample_frequency_id = SAMPLE_FREQUENCY_44100;
}
if (bclk_type > SSP_BCLK_MAX_FS)
{
printk(KERN_INFO"Error. bclk_type=%d.\n", bclk_type);
return;
}
/*
*bit14~0:NOM
*/
isscr = numerator;
/*
*bit26~15:DENOM
*/
if (sample_frequency_id == SAMPLE_FREQUENCY_8000)
{
/* 8000 Hz */
#if 1
isscr |= (denominator << (15 + sample_frequency_id + bclk_type - 1));
#else
if (SSP_BCLK_64_FS == bclk_type) {
isscr |= (denominator << (15 + sample_frequency_id + 1));
} else if (SSP_BCLK_32_FS == bclk_type) {
isscr |= (denominator << (15 + sample_frequency_id + 0));
} else {
/* SSP_BCLK_16_FS */
isscr |= (denominator << (15 + sample_frequency_id - 1));
}
#endif
}
else if (sample_frequency_id == SAMPLE_FREQUENCY_16000)
{
/* 16000 Hz */
#if 1
isscr |= (denominator << (15 + sample_frequency_id + bclk_type - 1));
#else
if (SSP_BCLK_64_FS == bclk_type) {
isscr |= (denominator << (15 + sample_frequency_id + 1));
} else if (SSP_BCLK_32_FS == bclk_type) {
isscr |= (denominator << (15 + sample_frequency_id + 0));
} else {
/* SSP_BCLK_16_FS */
isscr |= (denominator << (15 + sample_frequency_id - 1));
}
#endif
}
else if (sample_frequency_id == SAMPLE_FREQUENCY_44100)
{
/* 44100 Hz */
denominator = 0x211; /* 529 */
#if 1
isscr |= (denominator << (15 + bclk_type - 1));
#else
if (SSP_BCLK_64_FS == bclk_type) {
isscr |= (denominator << (15 + 1 ));
} else if (SSP_BCLK_32_FS == bclk_type) {
isscr |= (denominator << (15 + 0));
} else {
/* SSP_BCLK_16_FS */
isscr |= (denominator << (15 - 1));
}
#endif
}
/*
*bit31:SYSCLK_EN
*bit30:SYSCLK_BASE <0>=26MHz,<1>=156MHz
*bit29:BITCLK_EN
*bit28~27:BITCLK_DIV_468
*/
#if 1
/* DIV_468 = 2 = reserved */
isscr |= 0xE0000000;
#else
if (SSP_BCLK_64_FS == bclk_type) {
/* DIV_468 = 2 = reserved */
isscr |= 0xE0000000;
} else if (SSP_BCLK_32_FS == bclk_type) {
/* DIV_468 = 2 = reserved */
isscr |= 0xE0000000;
} else if (SSP_BCLK_16_FS == bclk_type) {
/* DIV_468 = 2 = reserved */
isscr |= 0xE0000000;
/* DIV_468 = 4 */
//isscr |= 0xE8000000;
}
#endif
#ifdef DEBUG_SSP1
reg_value = ioread32(ISCCR2_reg);
printk(KERN_INFO"%s/L%d,ISCCR2: read before write: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
#endif
/* ISCCR2 */
iowrite32(isscr, ISCCR2_reg);
#if 0
if (wb)
{
/* Sample frequece: 16K */
iowrite32(0xF840130B, ISCCR2_reg);
}
else
{
/* Sample frequece: 8K */
iowrite32(0xF820130B, ISCCR2_reg);
}
#endif
#ifdef DEBUG_SSP1
reg_value = ioread32(ISCCR2_reg);
printk(KERN_INFO"%s/L%d, ISCCR2: read after write: reg_value=0x%x\n", __FUNCTION__, __LINE__, reg_value);
#endif
#if 0
sscr0_frdc = (1 << bclk_type) - 1;
sspConfiguration->SSCR0_HIGH &= (~(0x07 << 8));
sspConfiguration->SSCR0_HIGH |= (sscr0_frdc << 8);
printk(KERN_INFO"GSSP_CLOCK_REG_ADDR:0x%lx, sscr0_frdc: 0x%lx, wb:%d", *(UINT32 *)GSSP_CLOCK_REG_ADDR, sscr0_frdc, wb);
#endif
return;
}
#if 0
static void test_ssp1(void)
{
UI_config_APBC_SSP1_CLK_RST();
UI_init_SSP_clk();
//UI_config_SSP_BCLK(g_gssp_bclk_type, Audio_WB_AMR_Enable);
UI_config_SSP_BCLK(SSP_BCLK_32_FS, SAMPLE_FREQUENCY_44100);
UI_config_SSP_I2S_format();
return;
}
#endif
/*
* SSP audio private data
*/
struct ssp_priv {
struct ssp_device *ssp;
unsigned int sysclk;
int dai_fmt;
unsigned int burst_size;
struct pinctrl *pinctrl;
struct pinctrl_state *pin_ssp;
struct pinctrl_state *pin_gpio;
int mfp;
int usr_cnt;
bool mfp_init;
#ifdef CONFIG_PM
uint32_t cr0;
uint32_t cr1;
uint32_t to;
uint32_t psp;
uint32_t top_ctrl;
uint32_t fifo_ctrl;
uint32_t int_en;
uint32_t network_ctrl;
uint32_t rwot_ctrl;
#endif
/*
* FixMe: for port 5 (gssp), it is shared by ap
* and cp. When AP want to handle it, AP need to
* configure APB to connect gssp. Also reset gssp
* clk to clear the potential impact from cp
*/
void __iomem *apbcp_base;
};
static ssize_t ssp_mfp_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct ssp_priv *priv = dev_get_drvdata(dev);
if (!priv)
return sprintf(buf, "%s\n", "get ssp-priv failed!!!\n");
if (priv->ssp->port_id == 2)
printk(KERN_INFO"i2s pin mfp setting:\n");
else if (priv->ssp->port_id == 5)
printk(KERN_INFO"gssp pin mfp setting:\n");
return sprintf(buf, "%s\n", (priv->mfp ? "ssp" : "gpio"));
}
static ssize_t ssp_mfp_set(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
int ret, i;
u32 pins_ssp;
struct ssp_priv *priv = dev_get_drvdata(dev);
struct device_node *np = dev->of_node;
if (!priv)
return -EINVAL;
if (IS_ERR(priv->pin_ssp) || IS_ERR(priv->pin_gpio))
return -EINVAL;
ret = kstrtoint(buf, 10, &priv->mfp);
if (ret)
return ret;
/* mfp = 0, set to gpio; mfp = 1, set to ssp */
if (priv->mfp) {
ret = pinctrl_select_state(priv->pinctrl, priv->pin_ssp);
if (ret) {
dev_err(dev, "could not set ssp pins\n");
goto err_out;
}
} else {
ret = pinctrl_select_state(priv->pinctrl, priv->pin_gpio);
if (ret) {
dev_err(dev, "could not set default(gpio) pins\n");
goto err_out;
}
for (i = 0; i < 4; i++) {
pins_ssp = of_get_named_gpio(np, "ssp-gpio", i);
gpio_request(pins_ssp, NULL);
gpio_direction_input(pins_ssp);
gpio_free(pins_ssp);
}
}
if (priv->ssp->port_id == 2)
printk(KERN_INFO"i2s pin set to %s\n", (priv->mfp ? "ssp" : "gpio"));
else if (priv->ssp->port_id == 5)
printk(KERN_INFO"gssp pin set to %s\n", (priv->mfp ? "ssp" : "gpio"));
err_out:
return count;
}
static DEVICE_ATTR(gssp_mfp, 0644, ssp_mfp_show, ssp_mfp_set);
static DEVICE_ATTR(ssp_mfp, 0644, ssp_mfp_show, ssp_mfp_set);
static void dump_registers(struct ssp_device *ssp)
{
dev_dbg(&ssp->pdev->dev, "TOP_CTRL 0x%08x FIFO_CTRL 0x%08x INT_EN 0x%08x\n",
pxa_ssp_read_reg(ssp, TOP_CTRL), pxa_ssp_read_reg(ssp, FIFO_CTRL),
pxa_ssp_read_reg(ssp, INT_EN));
dev_dbg(&ssp->pdev->dev, "NET_WORK_CTRL 0x%08x RWOT_CTRL 0x%08x TO 0x%08x\n",
pxa_ssp_read_reg(ssp, NET_WORK_CTRL), pxa_ssp_read_reg(ssp, RWOT_CTRL),
pxa_ssp_read_reg(ssp, TO));
dev_dbg(&ssp->pdev->dev, "PSP_CTRL 0x%08x STATUS 0x%08x NET_WORK_STATUS 0x%08x\n",
pxa_ssp_read_reg(ssp, PSP_CTRL), pxa_ssp_read_reg(ssp, STATUS),
pxa_ssp_read_reg(ssp, NET_WORK_STATUS));
}
static void pxa_ssp_enable(struct ssp_device *ssp)
{
uint32_t top_ctrl;
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id)) {
top_ctrl_hifi |= TOP_SSE;
__raw_writel(top_ctrl_hifi, ssp->mmio_base + TOP_CTRL);
} else {
top_ctrl = __raw_readl(ssp->mmio_base + TOP_CTRL) | TOP_SSE;
__raw_writel(top_ctrl, ssp->mmio_base + TOP_CTRL);
}
}
static void pxa_ssp_disable(struct ssp_device *ssp)
{
uint32_t top_ctrl;
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id)) {
top_ctrl_hifi |= TOP_SSE;
__raw_writel(top_ctrl_hifi, ssp->mmio_base + TOP_CTRL);
} else {
top_ctrl = __raw_readl(ssp->mmio_base + TOP_CTRL) & ~TOP_SSE;
__raw_writel(top_ctrl, ssp->mmio_base + TOP_CTRL);
}
}
static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
int out, struct snd_dmaengine_dai_dma_data *dma)
{
dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
DMA_SLAVE_BUSWIDTH_2_BYTES;
if (dma->maxburst > PXA_SSP_FIFO_DEPTH)
dma->maxburst = PXA_SSP_FIFO_DEPTH;
dma->addr = ssp->phys_base + DATAR;
}
static int pxa_ssp_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
struct snd_dmaengine_dai_dma_data *dma;
int ret = 0;
ret = pinctrl_select_state(priv->pinctrl, priv->pin_ssp);
if (ret) {
dev_err(cpu_dai->dev, "could not set ssp pins\n");
return ret;
}
priv->mfp_init = true;
priv->mfp = 1;
if (!cpu_dai->active)
{
clk_prepare_enable(ssp->clk);
priv->usr_cnt = 0;
}
dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
if (!dma)
return -ENOMEM;
#if 0
dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
&ssp->drcmr_tx : &ssp->drcmr_rx;
#endif
snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
#ifdef DEBUG_SSP1
printk(KERN_INFO"%s: drcmr_tx=%d, drcmr_rx=%d.\n", __FUNCTION__, ssp->drcmr_tx, ssp->drcmr_rx);
#endif
return ret;
}
static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
int ret = 0;
if (!cpu_dai->active) {
pxa_ssp_disable(ssp);
clk_disable_unprepare(ssp->clk);
ret = pinctrl_select_state(priv->pinctrl, priv->pin_gpio);
if (ret) {
dev_err(cpu_dai->dev, "could not set GPIO pins\n");
}
}
kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
}
#ifdef CONFIG_PM
static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
{
return 0;
}
static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
{
return 0;
}
#else
#define pxa_ssp_suspend NULL
#define pxa_ssp_resume NULL
#endif
/*
* Set the SSP ports SYSCLK.
*/
static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
return 0;
}
/*
* Set the SSP clock dividers.
*/
static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
int div_id, int div)
{
return 0;
}
/*
* Configure the PLL frequency pxa27x and (afaik - pxa320 only)
*/
static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
int source, unsigned int freq_in, unsigned int freq_out)
{
return 0;
}
/*
* Set the active slots in TDM/Network mode
*/
static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
u32 network_ctrl, top_ctrl;
network_ctrl = pxa_ssp_read_reg(ssp, NET_WORK_CTRL);
top_ctrl = pxa_ssp_read_reg(ssp, TOP_CTRL);
network_ctrl &= ~(NET_FRDC(8) | NET_WORK_MODE | RTSA_MASK | TTSA_MASK);
top_ctrl &= ~TOP_DSS_MASK;
top_ctrl |= TOP_DSS(slot_width);
if (slots > 1) {
/* enable network mode */
network_ctrl |= NET_WORK_MODE;
/* set number of active slots */
network_ctrl |= NET_FRDC(slots);
/* set active slot mask */
network_ctrl |= TTSA(tx_mask);
network_ctrl |= RTSA(rx_mask);
}
pxa_ssp_write_reg(ssp, TOP_CTRL, top_ctrl);
pxa_ssp_write_reg(ssp, NET_WORK_CTRL, network_ctrl);
return 0;
}
/*
* Tristate the SSP DAI lines
*/
static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
int tristate)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
u32 top_ctrl;
top_ctrl = pxa_ssp_read_reg(ssp, TOP_CTRL);
if (tristate)
top_ctrl &= ~TOP_TTE;
else
top_ctrl |= TOP_TTE;
pxa_ssp_write_reg(ssp, TOP_CTRL, top_ctrl);
return 0;
}
/*
* Set up the SSP DAI format.
* The SSP Port must be inactive before calling this function as the
* physical interface format is changed.
*/
static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
u32 network_ctrl, fifo_ctrl, top_ctrl, psp_ctrl, rwot_ctrl;
/* check if we need to change anything at all */
if (priv->dai_fmt == fmt)
return 0;
/* we can only change the settings if the port is not in use */
if (priv->usr_cnt) {
dev_err(&ssp->pdev->dev,
"can't change hardware dai format: stream is in use");
return -EINVAL;
}
/* reset port settings */
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id))
network_ctrl = network_ctrl_hifi & ~NET_WORK_MODE;
else
network_ctrl = pxa_ssp_read_reg(ssp, NET_WORK_CTRL) &
~NET_WORK_MODE;
fifo_ctrl = FIFO_RFT(7) | FIFO_TFT(7);
psp_ctrl = pxa_ssp_read_reg(ssp, PSP_CTRL);
top_ctrl = pxa_ssp_read_reg(ssp, TOP_CTRL);
rwot_ctrl =pxa_ssp_read_reg(ssp, RWOT_CTRL);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
top_ctrl |= TOP_SFRMDIR | TOP_SCLKDIR | TOP_SCFR;
break;
case SND_SOC_DAIFMT_CBM_CFS:
top_ctrl |= TOP_SCLKDIR | TOP_SCFR;
break;
case SND_SOC_DAIFMT_CBS_CFS:
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
//psp_ctrl |= PSP_SFRMP;
psp_ctrl |= 0;
break;
case SND_SOC_DAIFMT_NB_IF:
break;
case SND_SOC_DAIFMT_IB_IF:
psp_ctrl |= PSP_SCMODE(2);
break;
case SND_SOC_DAIFMT_IB_NF:
//psp_ctrl |= PSP_SCMODE(2) | PSP_SFRMP;
psp_ctrl |= PSP_SCMODE(2);
break;
default:
return -EINVAL;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
top_ctrl |= TOP_FRF_PSP;
top_ctrl |= TOP_TRAIL;
rwot_ctrl = RWOT_RWOT;
/* See hw_params() */
break;
case SND_SOC_DAIFMT_DSP_A:
psp_ctrl |= PSP_FSRT;
case SND_SOC_DAIFMT_DSP_B:
top_ctrl |= TOP_FRF_PSP;
top_ctrl |= TOP_TRAIL;
network_ctrl |= NET_WORK_MODE;
rwot_ctrl = RWOT_RWOT;
break;
default:
return -EINVAL;
}
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id)) {
top_ctrl_hifi = top_ctrl;
fifo_ctrl_hifi = fifo_ctrl;
rwot_ctrl_hifi = rwot_ctrl;
network_ctrl_hifi = network_ctrl;
}
pxa_ssp_write_reg(ssp, TOP_CTRL, top_ctrl);
pxa_ssp_write_reg(ssp, FIFO_CTRL, fifo_ctrl);
pxa_ssp_write_reg(ssp, NET_WORK_CTRL, network_ctrl);
pxa_ssp_write_reg(ssp, RWOT_CTRL, rwot_ctrl);
pxa_ssp_write_reg(ssp, PSP_CTRL, psp_ctrl);
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
case SND_SOC_DAIFMT_CBM_CFS:
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id))
top_ctrl = top_ctrl_hifi | TOP_SCFR;
else
top_ctrl = pxa_ssp_read_reg(ssp, TOP_CTRL) | TOP_SCFR;
pxa_ssp_write_reg(ssp, TOP_CTRL, top_ctrl);
while (pxa_ssp_read_reg(ssp, STATUS) & STATUS_BSY)
cpu_relax();
break;
}
dump_registers(ssp);
#if 0
if (get_ssp_role())
{
/* parameters: 32FS, 44.1k */
UI_config_SSP_BCLK(0, 2);
/* parameters: 32FS, WB:16k */
//UI_config_SSP_BCLK(0, 1);
/* parameters: 32FS, NB:8k */
//UI_config_SSP_BCLK(0, 0);
}
#endif
/* Since we are configuring the timings for the format by hand
* we have to defer some things until hw_params() where we
* know parameters like the sample size.
*/
priv->dai_fmt = fmt;
return 0;
}
/*
* Set the SSP audio DMA parameters and sample size.
* Can be called multiple times by oss emulation.
*/
static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *cpu_dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
int chn = params_channels(params);
u32 top_ctrl;
u32 psp_ctrl;
u32 network_ctrl;
int ttsa;
int width = snd_pcm_format_physical_width(params_format(params));
struct snd_dmaengine_dai_dma_data *dma_data;
unsigned int rate = params_rate(params);
#if 0
unsigned int sample_bits = snd_pcm_format_physical_width(params_format(params));
unsigned int frame_bits = sample_bits * channels;
if (get_ssp_role())
{
if (get_status_switch_frame_bits()){
/* for debug */
frame_bits = get_frame_bits();
} else {
/* get frame length from file format */
frame_bits = sample_bits * channels;
}
//clk_set_rate(ssp->clk, 2048000);//2.048MHz
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
clk_set_rate(ssp->clk, rate * 32);
} else {
//clk_set_rate(ssp->clk, 6500000);//Record ok
clk_set_rate(ssp->clk, rate * 32);
}
//UI_read_SSP_regs();
if ((8000 == rate) && (64 == frame_bits))
{
/* parameters: 64FS, NB:8k */
UI_config_SSP_BCLK(SSP_BCLK_64_FS, SAMPLE_FREQUENCY_8000);
}
else if ((16000 == rate) && (64 == frame_bits))
{
/* parameters: 64FS, WB:16k */
UI_config_SSP_BCLK(SSP_BCLK_64_FS, SAMPLE_FREQUENCY_16000);
}
else if ((44100 == rate) && (64 == frame_bits))
{
/* parameters: 64FS, 44.1k */
UI_config_SSP_BCLK(SSP_BCLK_64_FS, SAMPLE_FREQUENCY_44100);
}
else if ((8000 == rate) && (32 == frame_bits))
{
/* parameters: 32FS, NB:8k */
UI_config_SSP_BCLK(SSP_BCLK_32_FS, SAMPLE_FREQUENCY_8000);
}
else if ((16000 == rate) && (32 == frame_bits))
{
/* parameters: 32FS, WB:16k */
UI_config_SSP_BCLK(SSP_BCLK_32_FS, SAMPLE_FREQUENCY_16000);
}
else if ((44100 == rate) && (32 == frame_bits))
{
/* parameters: 32FS, 44.1k */
UI_config_SSP_BCLK(SSP_BCLK_32_FS, SAMPLE_FREQUENCY_44100);
}
else if ((8000 == rate) && (16 == frame_bits))
{
/* parameters: 16FS, NB:8k */
UI_config_SSP_BCLK(SSP_BCLK_16_FS, SAMPLE_FREQUENCY_8000);
}
else if ((16000 == rate) && (16 == frame_bits))
{
/* parameters: 16FS, WB:16k */
UI_config_SSP_BCLK(SSP_BCLK_16_FS, SAMPLE_FREQUENCY_16000);
}
else if ((44100 == rate) && (16 == frame_bits))
{
/* parameters: 16FS, 44.1k */
UI_config_SSP_BCLK(SSP_BCLK_16_FS, SAMPLE_FREQUENCY_44100);
}
}
#endif
/* the bitclk rate depends on the sample rate, the sample size and chn*/
clk_set_rate(ssp->clk, rate * width * chn);
network_ctrl = pxa_ssp_read_reg(ssp, NET_WORK_CTRL);
ttsa = (network_ctrl & TTSA_MASK) >> TTSA_BASE;
dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
dma_data->maxburst = priv->burst_size;
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id))
ttsa = 0;
/* Network mode with one active slot (ttsa == 1) can be used
* to force 16-bit frame width on the wire (for S16_LE), even
* with two channels. Use 16-bit DMA transfers for this case.
*/
pxa_ssp_set_dma_params(ssp,
((chn == 2) && (ttsa != 1)) || (width == 32),
substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
/* we can only change the settings if the port is not in use */
if (priv->usr_cnt)
return 0;
/* clear selected SSP bits */
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id))
top_ctrl = top_ctrl_hifi & ~(TOP_DSS_MASK);
else
top_ctrl = pxa_ssp_read_reg(ssp, TOP_CTRL) &
~(TOP_DSS_MASK);
/* bit size */
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
top_ctrl |= TOP_DSS(16);
break;
case SNDRV_PCM_FORMAT_S24_LE:
top_ctrl |= TOP_DSS(24);
break;
case SNDRV_PCM_FORMAT_S32_LE:
top_ctrl |= TOP_DSS(32);
break;
}
if ((has_feat_hifi_gssp_record())
&& (2 == ssp->port_id))
top_ctrl_hifi = top_ctrl;
pxa_ssp_write_reg(ssp, TOP_CTRL, top_ctrl);
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
psp_ctrl = pxa_ssp_read_reg(ssp, PSP_CTRL);
/* The frame width is the width the LRCLK is
* asserted for; the delay is expressed in
* half cycle units. We need the extra cycle
* because the data starts clocking out one BCLK
* after LRCLK changes polarity.
*/
psp_ctrl |= PSP_SFRMWDTH(width + 1);
psp_ctrl |= PSP_FSRT;
pxa_ssp_write_reg(ssp, PSP_CTRL, psp_ctrl);
break;
default:
break;
}
/* When we use a network mode, we always require TDM slots
* - complain loudly and fail if they've not been set up yet.
*/
if ((network_ctrl & NET_WORK_MODE) && !ttsa) {
dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
return -EINVAL;
}
dump_registers(ssp);
return 0;
}
static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
struct ssp_device *ssp, int value)
{
uint32_t fifo_ctrl = pxa_ssp_read_reg(ssp, FIFO_CTRL);
/*
* here we only enable/disable SSP TX/RX DMA request. ssp enable/
* disable is handled in startup/shutdown to avoid noise.
*/
if ((has_feat_hifi_gssp_record())
&& (ssp->port_id == 2))
fifo_ctrl = fifo_ctrl_hifi;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (value)
fifo_ctrl |= FIFO_TSRE;
else
fifo_ctrl &= ~FIFO_TSRE;
} else {
if (value)
fifo_ctrl |= FIFO_RSRE;
else
fifo_ctrl &= ~FIFO_RSRE;
}
if ((has_feat_hifi_gssp_record())
&& (ssp->port_id == 2))
fifo_ctrl_hifi = fifo_ctrl;
pxa_ssp_write_reg(ssp, FIFO_CTRL, fifo_ctrl);
}
static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
int ret = 0;
struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
struct ssp_device *ssp = priv->ssp;
int val;
switch (cmd) {
case SNDRV_PCM_TRIGGER_RESUME:
pxa_ssp_enable(ssp);
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
pxa_ssp_set_running_bit(substream, ssp, 1);
val = pxa_ssp_read_reg(ssp, STATUS);
pxa_ssp_write_reg(ssp, STATUS, val);
break;
case SNDRV_PCM_TRIGGER_START:
priv->usr_cnt++;
pxa_ssp_set_running_bit(substream, ssp, 1);
if(1 == priv->usr_cnt){
pxa_ssp_enable(ssp);
}
break;
case SNDRV_PCM_TRIGGER_STOP:
priv->usr_cnt--;
pxa_ssp_set_running_bit(substream, ssp, 0);
if(0 == priv->usr_cnt){
pxa_ssp_disable(ssp);
}
break;
case SNDRV_PCM_TRIGGER_SUSPEND:
pxa_ssp_disable(ssp);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
pxa_ssp_set_running_bit(substream, ssp, 0);
break;
default:
ret = -EINVAL;
}
dump_registers(ssp);
return ret;
}
/* ssp_dump_reg */
/* debug fs for ssp register interface of read and write. */
void ssp_dump_registers(struct ssp_device *ssp)
{
printk(KERN_INFO"[SSP_TOP_CTRL:0xD401B800]=0x%08x.\n", pxa_ssp_read_reg(ssp, TOP_CTRL));/* 0x00 */
printk(KERN_INFO"[SSP_FIFO_CTRL:0xD401B804]=0x%08x.\n", pxa_ssp_read_reg(ssp, FIFO_CTRL));/* 0x04 */
printk(KERN_INFO"[SSP_INT_EN:0xD401B808]=0x%08x.\n", pxa_ssp_read_reg(ssp, INT_EN));/* 0x08 */
printk(KERN_INFO"[SSP_TO:0xD401B80C]=0x%08x\n", pxa_ssp_read_reg(ssp, TO));/* 0x0C */
printk(KERN_INFO"[SSP_DATAR:0xD401B810]=0x%08x.\n", pxa_ssp_read_reg(ssp, DATAR));/* 0x10 */
printk(KERN_INFO"[SSP_STATUS:0xD401B814]=0x%08x.\n", pxa_ssp_read_reg(ssp, STATUS));/* 0x14 */
printk(KERN_INFO"[SSP_PSP_CTRL:0xD401B818]=0x%08x.\n", pxa_ssp_read_reg(ssp, PSP_CTRL));/* 0x18 */
printk(KERN_INFO"[SSP_NET_WORK_CTRL:0xD401B81C]=0x%08x.\n", pxa_ssp_read_reg(ssp, NET_WORK_CTRL));/* 0x1C */
printk(KERN_INFO"[SSP_NET_WORK_STATUS:0xD401B820]=0x%08x.\n", pxa_ssp_read_reg(ssp, NET_WORK_STATUS));/* 0x20 */
printk(KERN_INFO"[SSP_RWOT_CTRL:0xD401B824]=0x%08x\n", pxa_ssp_read_reg(ssp, RWOT_CTRL));/* 0x24 */
printk(KERN_INFO"[SSP_RWOT_CCM:0xD401B828]=0x%08x.\n", pxa_ssp_read_reg(ssp, RWOT_CCM));/* 0x28 */
printk(KERN_INFO"[SSP_RWOT_CVWRn:0xD401B82C]=0x%08x.\n", pxa_ssp_read_reg(ssp, RWOT_CVWRn));/* 0x2C */
UI_read_SSP_regs();
printk(KERN_INFO"[top_ctrl_UI=0x%08x. suggested value Slave=0x0002a3fe, Master=0x0002a3e6 for L/R 16bits.\n", top_ctrl_UI);/* 0x00 */
printk(KERN_INFO"[fifo_ctrl_UI=0x%08x.suggested value=0x00000c63 for L/R 16bits.\n", fifo_ctrl_UI);/* 0x04 */
printk(KERN_INFO"[int_en_UI=0x%08x.suggested value=0x0000000f for L/R 16bits.\n", int_en_UI);/* 0x08 */
printk(KERN_INFO"[psp_ctrl_UI=0x%08x.suggested value=0x00010009 for L/R 16bits.\n", psp_ctrl_UI);/* 0x18 */
printk(KERN_INFO"[network_ctrl_UI=0x%08x.suggested value=0x00000000 for L/R 16bits.\n", network_ctrl_UI);/* 0x1C */
}
static ssize_t ssp_dump_read(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
uint32_t reg_val = 0;
if (reg_ssp == 0xffff) {
/* dump all registers */
printk(KERN_INFO"%s/L%d:dump all registers.\n", __FUNCTION__, __LINE__);
ssp_dump_registers(g_ssp);
} else {
/* read the register for reg_ssp */
reg_val = pxa_ssp_read_reg(g_ssp, reg_ssp);
printk(KERN_INFO"%s/L%d:[0x%02x]=0x%08x.\n", __FUNCTION__, __LINE__, reg_ssp, reg_val);
}
return 0;
}
/*
*read all registers:
*echo + > /sys/kernel/debug/ssp_reg
*
*read offset of register:
*echo 0x00 > /sys/kernel/debug/ssp_reg
*
*write offset of register:
*echo 0x00 0x0000a3ff > /sys/kernel/debug/ssp_reg
*
*/
static ssize_t ssp_dump_write(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
uint32_t reg_val;
//uint32_t reg_val_SSP_TOP_CTRL;
int i = 0;
char messages[20];
memset(messages, '\0', 20);
if (copy_from_user(messages, user_buf, count))
return -EFAULT;
if ('+' == messages[0]) {
/* enable to get all the reg value */
reg_ssp = 0xffff;
/* dump all registers */
printk(KERN_INFO"%s/L%d:dump all registers.\n", __FUNCTION__, __LINE__);
ssp_dump_registers(g_ssp);
} else {
if (messages[1] != 'x') {
pr_err("Right format: 0x[addr]\n");
return -EINVAL;
}
if (strlen(messages) > 5) {
while (messages[i] != ' ')
i++;
messages[i] = '\0';
if (kstrtouint(messages, 16, &reg_ssp) < 0)
return -EINVAL;
i++;
if (kstrtouint(messages + i, 16, &reg_val) < 0)
return -EINVAL;
printk(KERN_INFO"%s/L%d: [0x%02x]=0x%08x.\n", __FUNCTION__, __LINE__, reg_ssp, reg_val);
if (reg_ssp == 0xFF)
{
/* write the ISCCR2 */
UI_write_ISCCR2(reg_val);
}
else if (reg_ssp == 0xEE)
{
/* write the APBC_SSP1_CLK_RST */
UI_write_APBC_SSP1_CLK_RST(reg_val);
}
else
{
if (TOP_CTRL == reg_ssp) {
/* SSP_TOP_CTRL */
top_ctrl_UI = reg_val;
printk(KERN_INFO"suggest top_ctrl_UI with Slave=0x0002a3fe, Master=0x0002a3e6 for L/R 16bits.\n");/* 0x00 */
} else if (FIFO_CTRL == reg_ssp) {
/* SSP_FIFO_CTRL */
fifo_ctrl_UI = reg_val;
printk(KERN_INFO"suggest fifo_ctrl_UI with 0x00000c63 for L/R 16bits.\n");
} else if (INT_EN == reg_ssp) {
/* SSP_INT_CTRL */
int_en_UI = reg_val;
printk(KERN_INFO"suggest int_en_UI with 0x0000000f for L/R 16bits.\n");
} else if (PSP_CTRL == reg_ssp) {
/* SSP_PSP_CTRL */
psp_ctrl_UI = reg_val;
printk(KERN_INFO"suggest psp_ctrl_UI with 0x00010009 for L/R 16bits.\n");
} else if (NET_WORK_CTRL == reg_ssp) {
/* SSP_NET_WORK_CTRL */
network_ctrl_UI = reg_val;
printk(KERN_INFO"suggest psp_ctrl_UI with 0x00000000 for L/R 16bits.\n");
}
}
} else {
/* point out the register address for read. */
if (kstrtouint(messages, 16, &reg_ssp) < 0)
return -EINVAL;
/* read the register for reg_ssp */
reg_val = pxa_ssp_read_reg(g_ssp, reg_ssp);
//reg_val = ioread32(ssp1_reg_addr);
printk(KERN_INFO"%s/L%d:[0x%02x]=0x%08x.\n", __FUNCTION__, __LINE__, reg_ssp, reg_val);
}
}
return count;
}
static const struct file_operations ssp_dump_ops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = ssp_dump_read,
.write = ssp_dump_write,
};
static inline int ssp_dump_debugfs_init(void)
{
ssp_dump_reg = debugfs_create_file("ssp_reg", S_IRUGO | S_IFREG,
NULL, NULL, &ssp_dump_ops);
if (ssp_dump_reg == NULL) {
pr_err("create ssp debugfs error!\n");
return -ENOENT;
} else if (ssp_dump_reg == ERR_PTR(-ENODEV)) {
pr_err("CONFIG_DEBUG_FS is not enabled!\n");
return -ENOENT;
}
return 0;
}
static void ssp_dump_debugfs_remove(void)
{
if (NULL != ssp_dump_reg){
debugfs_remove_recursive(ssp_dump_reg);
}
return;
}
/* ssp_ctrl */
struct dentry *ssp_ctrl = NULL;
static ssize_t ssp_ctrl_read(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
return 0;
}
/*
*control command:
*: echo 1 > /sys/kernel/debug/ssp_ctrl
*: echo 2 > /sys/kernel/debug/ssp_ctrl
*
*: echo 3 > /sys/kernel/debug/ssp_ctrl
*: echo 4 > /sys/kernel/debug/ssp_ctrl
*
*: echo 5 > /sys/kernel/debug/ssp_ctrl
*: echo 6 > /sys/kernel/debug/ssp_ctrl
*/
static char msg[10];
void init_ssp_i2s_addr(void);
static ssize_t ssp_ctrl_write(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
int ret = 0;
size_t tmp_count = 0;
int rate;
printk(KERN_INFO"%s/L%d.\n", __FUNCTION__, __LINE__);
memset(msg, 0x00, sizeof(msg));
tmp_count = count;
if (tmp_count >= sizeof(msg)){
tmp_count = sizeof(msg) - 1;
}
/* copy the content from user space to kernel space */
ret = copy_from_user(msg, user_buf, tmp_count);
if (ret){
printk(KERN_ALERT"copy from user fail \n");
return -EFAULT;
}
switch (msg[0]){
case '0':/* input command# echo 0 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
rate = clk_get_rate(g_ssp->clk);
clk_set_rate(g_ssp->clk, 6500000);
rate = clk_get_rate(g_ssp->clk);
#if 0
UI_read_ISCCR2();
UI_read_APBC_SSP1_CLK_RST();
#endif
break;
case '1':/* input command# echo 1 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
rate = clk_get_rate(g_ssp->clk);
UI_read_SSP_regs();
//test_ssp1();
#if 0
UI_config_APBC_SSP1_CLK_RST();
UI_init_SSP_clk();
UI_config_SSP_BCLK(g_gssp_bclk_type, Audio_WB_AMR_Enable);
UI_config_SSP_I2S_format();
#endif
break;
case '2':/* input command# echo 2 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_SSP_role();
break;
case '3':/* input command# echo 3 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
break;
case '4':/* input command# echo 4 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_Reverse_WBNB();
break;
case '5':/* input command# echo 5 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_bitclk_FS();
break;
case '6':/* input command# echo 6 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_enable_clk(g_ssp);
break;
case '7':/* input command# echo 7 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_disable_clk(g_ssp);
break;
case '8':/* input command# echo 8 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_enable_ssp(g_ssp);
break;
case '9':/* input command# echo 9 > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_disable_ssp(g_ssp);
break;
case 'a':/* input command# echo a > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_frame_bits();
break;
case 'b':/* input command# echo b > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_enable_switch_frame_bits();
break;
case 'c':/* input command# echo c > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_IFS();
break;
case 'd':/* input command# echo d > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_SFRMP();
break;
case 'e':/* input command# echo e > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_SCMODE();
break;
case 'f':/* input command# echo f > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_switch_debug_tools();
break;
case 'g':/* input command# echo g > /sys/kernel/debug/ssp_ctrl */
printk(KERN_INFO "input %c. \n", msg[0]);
UI_display_global_ctrl_var();
break;
default:/* input command# */
printk(KERN_INFO "input invalid. \n");
break;
}
return tmp_count;
}
static const struct file_operations ssp_ctrl_ops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = ssp_ctrl_read,
.write = ssp_ctrl_write,
};
static inline int ssp_ctrl_debugfs_init(void)
{
ssp_ctrl = debugfs_create_file("ssp_ctrl", S_IRUGO | S_IFREG,
NULL, NULL, &ssp_ctrl_ops);
if (ssp_ctrl == NULL) {
pr_err("create ssp_ctrl debugfs error!\n");
return -ENOENT;
} else if (ssp_ctrl == ERR_PTR(-ENODEV)) {
pr_err("CONFIG_DEBUG_FS is not enabled!\n");
return -ENOENT;
}
return 0;
}
static void ssp_ctrl_debugfs_remove(void)
{
if (NULL != ssp_ctrl){
debugfs_remove_recursive(ssp_ctrl);
}
return;
}
void init_ssp_i2s_addr(void)
{
/* APBC_SSP1_CLK_RST */
#if 0
if (!request_mem_region(APBC_SSP1_CLK_RST_ADDR, 4, "APBC_SSP1_CLK_RST_REG")) {
printk(KERN_INFO"%s:L%d, error request_mem_region\n", __FUNCTION__, __LINE__);
return;
}
#endif
APBC_SSP1_CLK_RST_reg = ioremap_nocache(APBC_SSP1_CLK_RST_ADDR, 4);
if (APBC_SSP1_CLK_RST_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
/* PMU_SQU_CLK_GATE_CTRL */
#if 0
if (!request_mem_region(PMU_SQU_CLK_GATE_CTRL_ADDR, 4, "PMU_SQU_CLK_GATE_CTRL_REG")) {
printk(KERN_INFO"%s:L%d, error request_mem_region\n", __FUNCTION__, __LINE__);
return;
}
#endif
PMU_SQU_CLK_GATE_CTRL_reg = ioremap_nocache(PMU_SQU_CLK_GATE_CTRL_ADDR, 4);
if (PMU_SQU_CLK_GATE_CTRL_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
/* SQU_CTRL_0 */
#if 0
if (!request_mem_region(SQU_CTRL_0_ADDR, 4, "SQU_CTRL_0_REG")) {
printk(KERN_INFO"%s:L%d, error request_mem_region\n", __FUNCTION__, __LINE__);
return;
}
#endif
SQU_CTRL_0_reg = ioremap_nocache(SQU_CTRL_0_ADDR, 4);
if (SQU_CTRL_0_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
/* FCCR */
#if 0
if (!request_mem_region(FCCR_ADDR, 4, "FCCR_REG")) {
printk(KERN_INFO"%s:L%d, error request_mem_region\n", __FUNCTION__, __LINE__);
return;
}
#endif
FCCR_reg = ioremap_nocache(FCCR_ADDR, 4);
if ( FCCR_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
/* ISCCR2 */
#if 0
if (!request_mem_region(ISCCR2_ADDR, 4, "ISCCR2_REG")) {
printk(KERN_INFO"%s:L%d, error request_mem_region\n", __FUNCTION__, __LINE__);
return;
}
#endif
ISCCR2_reg = ioremap_nocache(ISCCR2_ADDR, 4);
if ( ISCCR2_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
/* ICU_DMA_SEAGULL_INT_STATUS */
ICU_DMA_SEAGULL_INT_STATUS_reg = ioremap_nocache(ICU_DMA_SEAGULL_INT_STATUS_ADDR, 4);
if ( ICU_DMA_SEAGULL_INT_STATUS_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
/* DMA_BASE */
DMA_BASE_reg = ioremap_nocache(DMA_BASE_ADDR, 0x304);
if ( DMA_BASE_reg == NULL) {
printk(KERN_INFO"%s:L%d, error ioremap\n", __FUNCTION__, __LINE__);
return;
}
return;
}
static void free_ssp_i2s_clk(void)
{
/* APBC_SSP1_CLK_RST */
iounmap(APBC_SSP1_CLK_RST_reg);
//release_mem_region(APBC_SSP1_CLK_RST_ADDR, 4);
/* PMU_SQU_CLK_GATE_CTRL */
iounmap(PMU_SQU_CLK_GATE_CTRL_reg);
//release_mem_region(PMU_SQU_CLK_GATE_CTRL_ADDR, 4);
/* SQU_CTRL_0 */
iounmap(SQU_CTRL_0_reg);
//release_mem_region(SQU_CTRL_0_ADDR, 4);
/* FCCR */
iounmap(FCCR_reg);
//release_mem_region(FCCR_ADDR, 4);
/* ISCCR2 */
iounmap(ISCCR2_reg);
//release_mem_region(ISCCR2_ADDR, 4);
/* ICU_DMA_SEAGULL_INT_STATUS */
iounmap(ICU_DMA_SEAGULL_INT_STATUS_reg);
/* DMA_BASE */
iounmap(DMA_BASE_reg);
return;
}
static int pxa_ssp_probe(struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct ssp_priv *priv;
struct mmp_audio_sspdata *pdata;
int ret;
priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
if (dev->of_node) {
struct device_node *ssp_handle;
ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
if (!ssp_handle) {
dev_err(dev, "unable to get 'port' phandle\n");
ret = -ENODEV;
goto err_priv;
}
priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
if (priv->ssp == NULL) {
ret = -ENODEV;
goto err_priv;
}
of_property_read_u32(dev->of_node, "burst_size",
&priv->burst_size);
} else {
priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
if (priv->ssp == NULL) {
ret = -ENODEV;
goto err_priv;
}
pdata = dev_get_platdata(dai->dev);
priv->burst_size = 4;
}
priv->burst_size = 4;
/*
* FixMe: for port 5 (gssp), it is shared by ap
* and cp. When AP want to handle it, AP need to
* configure APB to connect gssp. Also reset gssp
* clk to clear the potential impact from cp
*/
if (priv->ssp->port_id == 5) {
priv->apbcp_base = devm_ioremap(dev, APBCONTROL_BASE,
APBCONTROL_SIZE);
if (priv->apbcp_base == NULL) {
dev_err(dev, "failed to ioremap() registers\n");
ret = -ENODEV;
goto err_priv;
}
}
priv->pinctrl = devm_pinctrl_get(dev);
if (IS_ERR(priv->pinctrl)) {
ret = PTR_ERR(priv->pinctrl);
goto err_priv;
}
priv->pin_ssp = pinctrl_lookup_state(priv->pinctrl, "ssp");
if (IS_ERR(priv->pin_ssp)) {
dev_err(dev, "could not get ssp pinstate\n");
ret = IS_ERR(priv->pin_ssp);
goto err_priv;
}
priv->pin_gpio = pinctrl_lookup_state(priv->pinctrl, "default");
if (IS_ERR(priv->pin_gpio)) {
dev_err(dev, "could not get default(gpio) pinstate\n");
ret = IS_ERR(priv->pin_gpio);
goto err_priv;
}
ret = pinctrl_select_state(priv->pinctrl, priv->pin_ssp);
if (ret) {
printk(KERN_INFO"could not set ssp pins\n");
goto err_priv;
}
priv->dai_fmt = (unsigned int) -1;
snd_soc_dai_set_drvdata(dai, priv);
priv->usr_cnt = 0;
priv->mfp_init = false;
/* clear gssp init clock status */
clk_prepare_enable(priv->ssp->clk);
clk_disable_unprepare(priv->ssp->clk);
/* init the global variable */
g_ssp = priv->ssp;
/* init debug tool */
ssp_dump_debugfs_init();
ssp_ctrl_debugfs_init();
/* init register address */
init_ssp_i2s_addr();
return 0;
err_priv:
kfree(priv);
return ret;
}
static int pxa_ssp_remove(struct snd_soc_dai *dai)
{
struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
pxa_ssp_free(priv->ssp);
kfree(priv);
//free debug tool
ssp_dump_debugfs_remove();
ssp_ctrl_debugfs_remove();
free_ssp_i2s_clk();
return 0;
}
#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE | \
SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
.startup = pxa_ssp_startup,
.shutdown = pxa_ssp_shutdown,
.trigger = pxa_ssp_trigger,
.hw_params = pxa_ssp_hw_params,
.set_sysclk = pxa_ssp_set_dai_sysclk,
.set_clkdiv = pxa_ssp_set_dai_clkdiv,
.set_pll = pxa_ssp_set_dai_pll,
.set_fmt = pxa_ssp_set_dai_fmt,
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
.set_tristate = pxa_ssp_set_dai_tristate,
};
static struct snd_soc_dai_driver pxa_ssp_dai = {
.probe = pxa_ssp_probe,
.remove = pxa_ssp_remove,
.suspend = pxa_ssp_suspend,
.resume = pxa_ssp_resume,
.playback = {
.channels_min = 1,
.channels_max = 8,
.rates = PXA_SSP_RATES,
.formats = PXA_SSP_FORMATS,
},
.capture = {
.channels_min = 1,
.channels_max = 8,
.rates = PXA_SSP_RATES,
.formats = PXA_SSP_FORMATS,
},
.ops = &pxa_ssp_dai_ops,
};
static const struct snd_soc_component_driver pxa_ssp_component = {
.name = "pxa-ssp",
};
#ifdef CONFIG_OF
static const struct of_device_id pxa_ssp_of_ids[] = {
{ .compatible = "asr,pxa-ssp-dai" },
};
#endif
static int asoc_ssp_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
char const *platform_driver_name;
int ret;
if (of_property_read_string(np,
"platform_driver_name",
&platform_driver_name)) {
dev_err(&pdev->dev,
"Missing platform_driver_name property in the DT\n");
return -EINVAL;
}
ret = snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
&pxa_ssp_dai, 1);
if (ret != 0) {
dev_err(&pdev->dev, "Failed to register DAI\n");
return ret;
}
if (strcmp(platform_driver_name, "tdma_platform") == 0) {
//ret = mmp_pcm_platform_register(&pdev->dev);
/* add ssp_mfp sysfs entries */
ret = device_create_file(&pdev->dev, &dev_attr_ssp_mfp);
if (ret < 0)
dev_err(&pdev->dev,
"%s: failed to add ssp_mfp sysfs files: %d\n",
__func__, ret);
} else if (strcmp(platform_driver_name, "pdma_platform") == 0) {
ret = pxa_pcm_platform_register(&pdev->dev);
/* add gssp_mfp sysfs entries */
ret = device_create_file(&pdev->dev, &dev_attr_gssp_mfp);
if (ret < 0)
dev_err(&pdev->dev,
"%s: failed to add gssp_mfp sysfs files: %d\n",
__func__, ret);
}
return ret;
}
static int asoc_ssp_remove(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
char const *platform_driver_name;
if (of_property_read_string(np,
"platform_driver_name",
&platform_driver_name)) {
dev_err(&pdev->dev,
"Missing platform_driver_name property in the DT\n");
return -EINVAL;
}
if (strcmp(platform_driver_name, "tdma_platform") == 0) {
device_remove_file(&pdev->dev, &dev_attr_ssp_mfp);
//mmp_pcm_platform_unregister(&pdev->dev);
} else if (strcmp(platform_driver_name, "pdma_platform") == 0) {
device_remove_file(&pdev->dev, &dev_attr_gssp_mfp);
snd_soc_unregister_component(&pdev->dev);
}
return 0;
}
static struct platform_driver asoc_ssp_driver = {
.driver = {
.name = "pxa-ssp-dai",
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(pxa_ssp_of_ids),
},
.probe = asoc_ssp_probe,
.remove = asoc_ssp_remove,
};
module_platform_driver(asoc_ssp_driver);
/* Module information */
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa-ssp-dai");