marvell/obm/Common/Download/DWC2_USB/snps_usb.h

#ifndef __ASR_USB2_REGS_H__
#define __ASR_USB2_REGS_H__

#include "Typedef.h"
#include "USB_PHY.h"
/**
 * @file
 *
 * This file contains the data structures for accessing the DWC_otg core registers.
 *
 * The application interfaces with the HS OTG core by reading from and
 * writing to the Control and Status Register (CSR) space through the
 * AHB Slave interface. These registers are 32 bits wide, and the
 * addresses are 32-bit-block aligned.
 * CSRs are classified as follows:
 * - Core Global Registers
 * - Device Mode Registers
 * - Device Global Registers
 * - Device Endpoint Specific Registers
 *
 * Only the Core Global registers can be accessed in both Device and
 * Host modes. When the HS OTG core is operating in one mode, either
 * Device or Host, the application must not access registers from the
 * other mode. When the core switches from one mode to another, the
 * registers in the new mode of operation must be reprogrammed as they
 * would be after a power-on reset.
 */

#define USB_PACKET_16           0x10
#define USB_PACKET_32           0x20
#define USB_PACKET_64           0x40
#define USB_PACKET_128          0x80
#define USB_PACKET_256          0x100
#define USB_PACKET_512          0x200
#define USB_PACKET_1024         0x400

typedef enum
{
	USB_EP_TYPE_CONTROL   = 0,
	USB_EP_TYPE_ISO 		 ,
	USB_EP_TYPE_BULK		 ,
	USB_EP_TYPE_INTERRUPT	 ,
	USB_EP_TYPE_MAX
} USB_EP_TYPE_E;

enum dwc2_ep0_next {
	USB2D_EP0_UNKNOWN = 0,
	USB2D_EP0_COMPLETE,
	USB2D_EP0_NRDY_DATA,
	USB2D_EP0_NRDY_STATUS,
};

enum dwc2_ep0_state {
	EP0_UNCONNECTED		= 0,
	EP0_SETUP_PHASE,
	EP0_DATA_PHASE,
	EP0_STATUS_PHASE,
};

#define USB_REG_BASE  (0xc0000000)

#define DSTS_SOFFN_MASK			(0x3fff << 8)
#define DSTS_SOFFN_SHIFT		8
#define DSTS_SOFFN_LIMIT		0x3fff
#define DSTS_SOFFN(_x)			((_x) << 8)
#define DSTS_ERRATICERR			(0x1 << 3)
#define DSTS_ENUMSPD_MASK		(0x3 << 1)
#define DSTS_ENUMSPD_SHIFT		1
#define DSTS_ENUMSPD_HS			0
#define DSTS_ENUMSPD_FS			1
#define DSTS_ENUMSPD_LS			2
#define DSTS_ENUMSPD_FS48		3
#define DSTS_SUSPSTS			(0x1 << 0)

/**Core Global CSR */
#define USB_GOTGCTL                     (USB_REG_BASE + 0x0000)
#define USB_GOTGINT                     (USB_REG_BASE + 0x0004)
#define USB_GAHBCFG                     (USB_REG_BASE + 0x0008)
#define USB_GUSBCFG                     (USB_REG_BASE + 0x000c)
#define USB_GRSTCTL                     (USB_REG_BASE + 0x0010)
#define USB_GINTSTS                     (USB_REG_BASE + 0x0014)
#define USB_GINTMSK                     (USB_REG_BASE + 0x0018)
#define USB_GRXSTSR                     (USB_REG_BASE + 0x001c)
#define USB_GRXSTSP                     (USB_REG_BASE + 0x0020)
#define USB_GRXFSIZ                     (USB_REG_BASE + 0x0024)
#define USB_GNPTXFSIZ                   (USB_REG_BASE + 0x0028)
#define USB_GNPTXSTS                    (USB_REG_BASE + 0x002c)
#define USB_GI2CCTL                     (USB_REG_BASE + 0x0030)
#define USB_GPVNDCTL                    (USB_REG_BASE + 0x0034)
#define USB_GGPIO                       (USB_REG_BASE + 0x0038)
#define USB_GUID                        (USB_REG_BASE + 0x003c)
#define USB_GSNPSID                     (USB_REG_BASE + 0x0040)
#define USB_GHWCFG1                     (USB_REG_BASE + 0x0044)
#define USB_GHWCFG2                     (USB_REG_BASE + 0x0048)
#define USB_GHWCFG3                     (USB_REG_BASE + 0x004c)
#define USB_GHWCFG4                     (USB_REG_BASE + 0x0050)
#define USB_GLPMCFG                     (USB_REG_BASE + 0x0054)
#define USB_HPTXFSIZ                    (USB_REG_BASE + 0x0100)
#define USB_DPTXFSIZ(n)                 (USB_REG_BASE + 0x0104+(n-1)*0x04)   // n(1-15)
#define USB_DIEPTXF(n)                  (USB_REG_BASE + 0x0104+(n-1)*0x04)   // n(1-15)

/** Power and Clock geting  CSR */
#define USB_PCGCR                       (USB_REG_BASE + 0x0E00)

/** Device CSR */
#define USB_DCFG                        (USB_REG_BASE + 0x0800)
#define USB_DCTL                        (USB_REG_BASE + 0x0804)
#define USB_DSTS                        (USB_REG_BASE + 0x0808)
#define USB_DIEPMSK                     (USB_REG_BASE + 0x0810)
#define USB_DOEPMSK                     (USB_REG_BASE + 0x0814)
#define USB_DAINT                       (USB_REG_BASE + 0x0818)
#define USB_DAINTMSK                    (USB_REG_BASE + 0x081c)
#define USB_DTKNQR1                     (USB_REG_BASE + 0x0820)
#define USB_DTKNQR2                     (USB_REG_BASE + 0x0824)
#define USB_DTKNQR3                     (USB_REG_BASE + 0x0830)
#define USB_DTKNQR4                     (USB_REG_BASE + 0x0834)
#define USB_DVBUSDIS                    (USB_REG_BASE + 0x0828)
#define USB_DVBUSPULSE                  (USB_REG_BASE + 0x082c)
#define USB_DTHRCTL                     (USB_REG_BASE + 0x0830)
#define USB_DIEPEMPMSK                  (USB_REG_BASE + 0x0834)
#define USB_DEACHINT                    (USB_REG_BASE + 0x0838)
#define USB_DEACHINTMSK                 (USB_REG_BASE + 0x083c)
#define USB_DIACHINTMSK(n)              (USB_REG_BASE + 0x0840+(n)*0x04)  // n(0-15)
#define USB_DOACHINTMSK(n)              (USB_REG_BASE + 0x0880+(n)*0x04)  // n(0-15)
#define USB_DIEP0CTL                    (USB_REG_BASE + 0x0900)
#define USB_DIEPCTL(n)                  (USB_REG_BASE + 0x0900+(n)*0x20)  // n(1-15)
#define USB_DIEPINT(n)                  (USB_REG_BASE + 0x0908+(n)*0x20)  // n(0-15)
#define USB_DIEP0TSIZ                   (USB_REG_BASE + 0x0910)
#define USB_DIEPTSIZ(n)                 (USB_REG_BASE + 0x0910+(n)*0x20)  // n(1-15)
#define USB_DIEPDMA(n)                  (USB_REG_BASE + 0x0914+(n)*0x20)  // n(0-15)
#define USB_DTXFSTS(n)                  (USB_REG_BASE + 0x0918+(n)*0x20)  // n(0-15)
#define USB_DIEPDMAB(n)                 (USB_REG_BASE + 0x091c+n*0x20)  // n(0-15)
#define USB_DOEP0CTL                    (USB_REG_BASE + 0x0b00)
#define USB_DOEPCTL(n)                  (USB_REG_BASE + 0x0b00+(n)*0x20)  // n(1-15)
#define USB_DOEPINT(n)                  (USB_REG_BASE + 0x0b08+(n)*0x20)  // n(0-15)
#define USB_DOEP0TSIZ                   (USB_REG_BASE + 0x0b10)
#define USB_DOEPTSIZ(n)                 (USB_REG_BASE + 0x0b10+(n)*0x20)  // n(1-15)
#define USB_DOEPDMA(n)                  (USB_REG_BASE + 0x0b14+(n)*0x20)  // n(0-15)
#define USB_DOEPDMAB(n)                 (USB_REG_BASE + 0x0b1c+(n)*0x20)  // n(0-15)
#define USB_PCGCCTL                     (USB_REG_BASE + 0xE00)
#define USB_DEPFIFOBA(n)                (USB_REG_BASE + (n+1)*0x1000)   // n(0-15)

#define MAX_EPS_CHANNELS 16

#define DXEPCTL_NAKSTS					(1 << 17)
#define DXEPCTL_EPENA					(1 << 31)
#define DXEPINT_EPDISBLD                (1 << 1)
#define DXEPINT_INEPNAKEFF              (1 << 6)
#define DCTL_CGOUTNAK                   (1 << 10)
#define DCTL_SGOUTNAK                   (1 << 9)
#define GINTSTS_GOUTNAKEFF              (1 << 7)
#define GINTSTS_GINNAKEFF               (1 << 6)

/****************************************************************************/
/** DWC_otg Core registers .
 * The dwc_otg_core_global_regs structure defines the size
 * and relative field offsets for the Core Global registers.
 */
typedef struct dwc_otg_core_global_regs {
	/** OTG Control and Status Register.  <i>Offset: 000h</i> */
	volatile UINT_T gotgctl;
	/** OTG Interrupt Register.	 <i>Offset: 004h</i> */
	volatile UINT_T gotgint;
	/**Core AHB Configuration Register.	 <i>Offset: 008h</i> */
	volatile UINT_T gahbcfg;

#define DWC_GLBINTRMASK		0x0001
#define DWC_DMAENABLE		0x0020
#define DWC_NPTXEMPTYLVL_EMPTY	0x0080
#define DWC_NPTXEMPTYLVL_HALFEMPTY	0x0000
#define DWC_PTXEMPTYLVL_EMPTY	0x0100
#define DWC_PTXEMPTYLVL_HALFEMPTY	0x0000

	/**Core USB Configuration Register.	 <i>Offset: 00Ch</i> */
	volatile UINT_T gusbcfg;
	/**Core Reset Register.	 <i>Offset: 010h</i> */
	volatile UINT_T grstctl;
	/**Core Interrupt Register.	 <i>Offset: 014h</i> */
	volatile UINT_T gintsts;
	/**Core Interrupt Mask Register.  <i>Offset: 018h</i> */
	volatile UINT_T gintmsk;
	/**Receive Status Queue Read Register (Read Only).	<i>Offset: 01Ch</i> */
	volatile UINT_T grxstsr;
	/**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/
	volatile UINT_T grxstsp;
	/**Receive FIFO Size Register.	<i>Offset: 024h</i> */
	volatile UINT_T grxfsiz;
	/**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */
	volatile UINT_T gnptxfsiz;
	/**Non Periodic Transmit FIFO/Queue Status Register (Read
	 * Only). <i>Offset: 02Ch</i> */
	volatile UINT_T gnptxsts;
	/**I2C Access Register.	 <i>Offset: 030h</i> */
	volatile UINT_T gi2cctl;
	/**PHY Vendor Control Register.	 <i>Offset: 034h</i> */
	volatile UINT_T gpvndctl;
	/**General Purpose Input/Output Register.  <i>Offset: 038h</i> */
	volatile UINT_T ggpio;
	/**User ID Register.  <i>Offset: 03Ch</i> */
	volatile UINT_T guid;
	/**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */
	volatile UINT_T gsnpsid;
	/**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */
	volatile UINT_T ghwcfg1;
	/**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */
	volatile UINT_T ghwcfg2;
#define DWC_SLAVE_ONLY_ARCH 0
#define DWC_EXT_DMA_ARCH 1
#define DWC_INT_DMA_ARCH 2

#define DWC_MODE_HNP_SRP_CAPABLE	0
#define DWC_MODE_SRP_ONLY_CAPABLE	1
#define DWC_MODE_NO_HNP_SRP_CAPABLE		2
#define DWC_MODE_SRP_CAPABLE_DEVICE		3
#define DWC_MODE_NO_SRP_CAPABLE_DEVICE	4
#define DWC_MODE_SRP_CAPABLE_HOST	5
#define DWC_MODE_NO_SRP_CAPABLE_HOST	6

	/**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */
	volatile UINT_T ghwcfg3;
	/**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/
	volatile UINT_T ghwcfg4;
	/** Core LPM Configuration register <i>Offset: 054h</i>*/
	volatile UINT_T glpmcfg;
	/** Global PowerDn Register <i>Offset: 058h</i> */
	volatile UINT_T gpwrdn;
	/** Global DFIFO SW Config Register  <i>Offset: 05Ch</i> */
	volatile UINT_T gdfifocfg;
	/** ADP Control Register  <i>Offset: 060h</i> */
	volatile UINT_T adpctl;
	/** Reserved  <i>Offset: 064h-0FFh</i> */
	volatile UINT_T reserved39[39];
	/** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
	volatile UINT_T hptxfsiz;
	/** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
		otherwise Device Transmit FIFO#n Register.
	 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
	volatile UINT_T dtxfsiz[15];

} dwc_otg_core_global_regs_t;

/**
 * This union represents the bit fields of the Core OTG Control
 * and Status Register (GOTGCTL).  Set the bits using the bit
 * fields then write the <i>d32</i> value to the register.
 */
typedef union gotgctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned sesreqscs:1;
		unsigned sesreq:1;
		unsigned vbvalidoven:1;
		unsigned vbvalidovval:1;
		unsigned avalidoven:1;
		unsigned avalidovval:1;
		unsigned bvalidoven:1;
		unsigned bvalidovval:1;
		unsigned hstnegscs:1;
		unsigned hnpreq:1;
		unsigned hstsethnpen:1;
		unsigned devhnpen:1;
		unsigned reserved12_15:4;
		unsigned conidsts:1;
		unsigned dbnctime:1;
		unsigned asesvld:1;
		unsigned bsesvld:1;
		unsigned otgver:1;
		unsigned reserved1:1;
		unsigned multvalidbc:5;
		unsigned chirpen:1;
		unsigned reserved28_31:4;
	} b;
} gotgctl_data_t;

/**
 * This union represents the bit fields of the Core OTG Interrupt Register
 * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>
 * value to the register.
 */
typedef union gotgint_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Current Mode */
		unsigned reserved0_1:2;

		/** Session End Detected */
		unsigned sesenddet:1;

		unsigned reserved3_7:5;

		/** Session Request Success Status Change */
		unsigned sesreqsucstschng:1;
		/** Host Negotiation Success Status Change */
		unsigned hstnegsucstschng:1;

		unsigned reserved10_16:7;

		/** Host Negotiation Detected */
		unsigned hstnegdet:1;
		/** A-Device Timeout Change */
		unsigned adevtoutchng:1;
		/** Debounce Done */
		unsigned debdone:1;
		/** Multi-Valued input changed */
		unsigned mvic:1;

		unsigned reserved31_21:11;

	} b;
} gotgint_data_t;

/**
 * This union represents the bit fields of the Core AHB Configuration
 * Register (GAHBCFG). Set/clear the bits using the bit fields then
 * write the <i>d32</i> value to the register.
 */
typedef union gahbcfg_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned glblintrmsk:1;
#define DWC_GAHBCFG_GLBINT_ENABLE		1

		unsigned hburstlen:4;
#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE	0
#define DWC_GAHBCFG_INT_DMA_BURST_INCR		1
#define DWC_GAHBCFG_INT_DMA_BURST_INCR4		3
#define DWC_GAHBCFG_INT_DMA_BURST_INCR8		5
#define DWC_GAHBCFG_INT_DMA_BURST_INCR16	7

		unsigned dmaenable:1;
#define DWC_GAHBCFG_DMAENABLE			1
		unsigned reserved:1;
		unsigned nptxfemplvl_txfemplvl:1;
		unsigned ptxfemplvl:1;
#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY		1
#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY	0
		unsigned reserved9_20:12;
		unsigned remmemsupp:1;
		unsigned notialldmawrit:1;
		unsigned ahbsingle:1;
		unsigned reserved24_31:8;
	} b;
} gahbcfg_data_t;

/**
 * This union represents the bit fields of the Core USB Configuration
 * Register (GUSBCFG). Set the bits using the bit fields then write
 * the <i>d32</i> value to the register.
 */
typedef union gusbcfg_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned toutcal:3;
		unsigned phyif:1;
		unsigned ulpi_utmi_sel:1;
		unsigned fsintf:1;
		unsigned physel:1;
		unsigned ddrsel:1;
		unsigned srpcap:1;
		unsigned hnpcap:1;
		unsigned usbtrdtim:4;
		unsigned reserved1:1;
		unsigned phylpwrclksel:1;
		unsigned otgutmifssel:1;
		unsigned ulpi_fsls:1;
		unsigned ulpi_auto_res:1;
		unsigned ulpi_clk_sus_m:1;
		unsigned ulpi_ext_vbus_drv:1;
		unsigned ulpi_int_vbus_indicator:1;
		unsigned term_sel_dl_pulse:1;
		unsigned indicator_complement:1;
		unsigned indicator_pass_through:1;
		unsigned ulpi_int_prot_dis:1;
		unsigned ic_usb_cap:1;
		unsigned ic_traffic_pull_remove:1;
		unsigned tx_end_delay:1;
		unsigned force_host_mode:1;
		unsigned force_dev_mode:1;
		unsigned reserved31:1;
	} b;
} gusbcfg_data_t;

/**
 * This union represents the bit fields of the Core Reset Register
 * (GRSTCTL).  Set/clear the bits using the bit fields then write the
 * <i>d32</i> value to the register.
 */
typedef union grstctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Core Soft Reset (CSftRst) (Device and Host)
		 *
		 * The application can flush the control logic in the
		 * entire core using this bit. This bit resets the
		 * pipelines in the AHB Clock domain as well as the
		 * PHY Clock domain.
		 *
		 * The state machines are reset to an IDLE state, the
		 * control bits in the CSRs are cleared, all the
		 * transmit FIFOs and the receive FIFO are flushed.
		 *
		 * The status mask bits that control the generation of
		 * the interrupt, are cleared, to clear the
		 * interrupt. The interrupt status bits are not
		 * cleared, so the application can get the status of
		 * any events that occurred in the core after it has
		 * set this bit.
		 *
		 * Any transactions on the AHB are terminated as soon
		 * as possible following the protocol. Any
		 * transactions on the USB are terminated immediately.
		 *
		 * The configuration settings in the CSRs are
		 * unchanged, so the software doesn't have to
		 * reprogram these registers (Device
		 * Configuration/Host Configuration/Core System
		 * Configuration/Core PHY Configuration).
		 *
		 * The application can write to this bit, any time it
		 * wants to reset the core. This is a self clearing
		 * bit and the core clears this bit after all the
		 * necessary logic is reset in the core, which may
		 * take several clocks, depending on the current state
		 * of the core.
		 */
		unsigned csftrst:1;
		/** Hclk Soft Reset
		 *
		 * The application uses this bit to reset the control logic in
		 * the AHB clock domain. Only AHB clock domain pipelines are
		 * reset.
		 */
		unsigned hsftrst:1;
		/** Host Frame Counter Reset (Host Only)<br>
		 *
		 * The application can reset the (micro)frame number
		 * counter inside the core, using this bit. When the
		 * (micro)frame counter is reset, the subsequent SOF
		 * sent out by the core, will have a (micro)frame
		 * number of 0.
		 */
		unsigned hstfrm:1;
		/** In Token Sequence Learning Queue Flush
		 * (INTknQFlsh) (Device Only)
		 */
		unsigned intknqflsh:1;
		/** RxFIFO Flush (RxFFlsh) (Device and Host)
		 *
		 * The application can flush the entire Receive FIFO
		 * using this bit. The application must first
		 * ensure that the core is not in the middle of a
		 * transaction. The application should write into
		 * this bit, only after making sure that neither the
		 * DMA engine is reading from the RxFIFO nor the MAC
		 * is writing the data in to the FIFO. The
		 * application should wait until the bit is cleared
		 * before performing any other operations. This bit
		 * will takes 8 clocks (slowest of PHY or AHB clock)
		 * to clear.
		 */
		unsigned rxfflsh:1;
		/** TxFIFO Flush (TxFFlsh) (Device and Host).
		 *
		 * This bit is used to selectively flush a single or
		 * all transmit FIFOs. The application must first
		 * ensure that the core is not in the middle of a
		 * transaction. The application should write into
		 * this bit, only after making sure that neither the
		 * DMA engine is writing into the TxFIFO nor the MAC
		 * is reading the data out of the FIFO. The
		 * application should wait until the core clears this
		 * bit, before performing any operations. This bit
		 * will takes 8 clocks (slowest of PHY or AHB clock)
		 * to clear.
		 */
		unsigned txfflsh:1;

		/** TxFIFO Number (TxFNum) (Device and Host).
		 *
		 * This is the FIFO number which needs to be flushed,
		 * using the TxFIFO Flush bit. This field should not
		 * be changed until the TxFIFO Flush bit is cleared by
		 * the core.
		 *	 - 0x0 : Non Periodic TxFIFO Flush
		 *	 - 0x1 : Periodic TxFIFO #1 Flush in device mode
		 *	   or Periodic TxFIFO in host mode
		 *	 - 0x2 : Periodic TxFIFO #2 Flush in device mode.
		 *	 - ...
		 *	 - 0xF : Periodic TxFIFO #15 Flush in device mode
		 *	 - 0x10: Flush all the Transmit NonPeriodic and
		 *	   Transmit Periodic FIFOs in the core
		 */
		unsigned txfnum:5;
		/** Reserved */
		unsigned reserved11_29:19;
		/** DMA Request Signal.	 Indicated DMA request is in
		 * probress. Used for debug purpose. */
		unsigned dmareq:1;
		/** AHB Master Idle.  Indicates the AHB Master State
		 * Machine is in IDLE condition. */
		unsigned ahbidle:1;
	} b;
} grstctl_t;

/**
 * This union represents the bit fields of the Core Interrupt Mask
 * Register (GINTMSK). Set/clear the bits using the bit fields then
 * write the <i>d32</i> value to the register.
 */
typedef union gintmsk_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned reserved0:1;
		unsigned modemismatch:1;
		unsigned otgintr:1;
		unsigned sofintr:1;
		unsigned rxstsqlvl:1;
		unsigned nptxfempty:1;
		unsigned ginnakeff:1;
		unsigned goutnakeff:1;
		unsigned ulpickint:1;
		unsigned i2cintr:1;
		unsigned erlysuspend:1;
		unsigned usbsuspend:1;
		unsigned usbreset:1;
		unsigned enumdone:1;
		unsigned isooutdrop:1;
		unsigned eopframe:1;
		unsigned restoredone:1;
		unsigned epmismatch:1;
		unsigned inepintr:1;
		unsigned outepintr:1;
		unsigned incomplisoin:1;
		unsigned incomplisoout:1;
		unsigned fetsusp:1;
		unsigned resetdet:1;
		unsigned portintr:1;
		unsigned hcintr:1;
		unsigned ptxfempty:1;
		unsigned lpmtranrcvd:1;
		unsigned conidstschng:1;
		unsigned disconnect:1;
		unsigned sessreqintr:1;
		unsigned wkupintr:1;
	} b;
} gintmsk_data_t;
/**
 * This union represents the bit fields of the Core Interrupt Register
 * (GINTSTS).  Set/clear the bits using the bit fields then write the
 * <i>d32</i> value to the register.
 */
typedef union gintsts_data {
	/** raw register data */
	UINT_T d32;
#define DWC_SOF_INTR_MASK 0x0008
	/** register bits */
	struct {
#define DWC_HOST_MODE 1
		unsigned curmode:1;
		unsigned modemismatch:1;
		unsigned otgintr:1;
		unsigned sofintr:1;
		unsigned rxstsqlvl:1;
		unsigned nptxfempty:1;
		unsigned ginnakeff:1;
		unsigned goutnakeff:1;
		unsigned ulpickint:1;
		unsigned i2cintr:1;
		unsigned erlysuspend:1;
		unsigned usbsuspend:1;
		unsigned usbreset:1;
		unsigned enumdone:1;
		unsigned isooutdrop:1;
		unsigned eopframe:1;
		unsigned restoredone:1;
		unsigned epmismatch:1;
		unsigned inepint:1;
		unsigned outepintr:1;
		unsigned incomplisoin:1;
		unsigned incomplisoout:1;
		unsigned fetsusp:1;
		unsigned resetdet:1;
		unsigned portintr:1;
		unsigned hcintr:1;
		unsigned ptxfempty:1;
		unsigned lpmtranrcvd:1;
		unsigned conidstschng:1;
		unsigned disconnect:1;
		unsigned sessreqintr:1;
		unsigned wkupintr:1;
	} b;
} gintsts_data_t;

/**
 * This union represents the bit fields in the Device Receive Status Read and
 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
 * element then read out the bits using the <i>b</i>it elements.
 */
typedef union device_grxsts_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned epnum:4;
		unsigned bcnt:11;
		unsigned dpid:2;

#define DWC_STS_DATA_UPDT		0x2	// OUT Data Packet
#define DWC_STS_XFER_COMP		0x3	// OUT Data Transfer Complete

#define DWC_DSTS_GOUT_NAK		0x1	// Global OUT NAK
#define DWC_DSTS_SETUP_COMP		0x4	// Setup Phase Complete
#define DWC_DSTS_SETUP_UPDT 0x6	// SETUP Packet
		unsigned pktsts:4;
		unsigned fn:4;
		unsigned reserved25_31:7;
	} b;
} device_grxsts_data_t;

/**
 * This union represents the bit fields in the Host Receive Status Read and
 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
 * element then read out the bits using the <i>b</i>it elements.
 */
typedef union host_grxsts_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned chnum:4;
		unsigned bcnt:11;
		unsigned dpid:2;

		unsigned pktsts:4;
#define DWC_GRXSTS_PKTSTS_IN			  0x2
#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP	  0x3
#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
#define DWC_GRXSTS_PKTSTS_CH_HALTED		  0x7

		unsigned reserved21_31:11;
	} b;
} host_grxsts_data_t;

/**
 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
 * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
 * then read out the bits using the <i>b</i>it elements.
 */
typedef union fifosize_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned startaddr:16;
		unsigned depth:16;
	} b;
} fifosize_data_t;

/**
 * This union represents the bit fields in the Non-Periodic Transmit
 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
 * <i>d32</i> element then read out the bits using the <i>b</i>it
 * elements.
 */
typedef union gnptxsts_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned nptxfspcavail:16;
		unsigned nptxqspcavail:8;
		/** Top of the Non-Periodic Transmit Request Queue
		 *	- bit 24 - Terminate (Last entry for the selected
		 *	  channel/EP)
		 *	- bits 26:25 - Token Type
		 *	  - 2'b00 - IN/OUT
		 *	  - 2'b01 - Zero Length OUT
		 *	  - 2'b10 - PING/Complete Split
		 *	  - 2'b11 - Channel Halt
		 *	- bits 30:27 - Channel/EP Number
		 */
		unsigned nptxqtop_terminate:1;
		unsigned nptxqtop_token:2;
		unsigned nptxqtop_chnep:4;
		unsigned reserved:1;
	} b;
} gnptxsts_data_t;

/**
 * This union represents the bit fields in the Transmit
 * FIFO Status Register (DTXFSTS). Read the register into the
 * <i>d32</i> element then read out the bits using the <i>b</i>it
 * elements.
 */
typedef union dtxfsts_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned txfspcavail:16;
		unsigned reserved:16;
	} b;
} dtxfsts_data_t;

/**
 * This union represents the bit fields in the I2C Control Register
 * (I2CCTL). Read the register into the <i>d32</i> element then read out the
 * bits using the <i>b</i>it elements.
 */
typedef union gi2cctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned rwdata:8;
		unsigned regaddr:8;
		unsigned addr:7;
		unsigned i2cen:1;
		unsigned ack:1;
		unsigned i2csuspctl:1;
		unsigned i2cdevaddr:2;
		unsigned i2cdatse0:1;
		unsigned reserved:1;
		unsigned rw:1;
		unsigned bsydne:1;
	} b;
} gi2cctl_data_t;

/**
 * This union represents the bit fields in the PHY Vendor Control Register
 * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
 * bits using the <i>b</i>it elements.
 */
typedef union gpvndctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned regdata:8;
		unsigned vctrl:8;
		unsigned regaddr16_21:6;
		unsigned regwr:1;
		unsigned reserved23_24:2;
		unsigned newregreq:1;
		unsigned vstsbsy:1;
		unsigned vstsdone:1;
		unsigned reserved28_30:3;
		unsigned disulpidrvr:1;
	} b;
} gpvndctl_data_t;

/**
 * This union represents the bit fields in the General Purpose
 * Input/Output Register (GGPIO).
 * Read the register into the <i>d32</i> element then read out the
 * bits using the <i>b</i>it elements.
 */
typedef union ggpio_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned gpi:16;
		unsigned gpo:16;
	} b;
} ggpio_data_t;

/**
 * This union represents the bit fields in the User ID Register
 * (GUID). Read the register into the <i>d32</i> element then read out the
 * bits using the <i>b</i>it elements.
 */
typedef union guid_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned rwdata:32;
	} b;
} guid_data_t;

/**
 * This union represents the bit fields in the Synopsys ID Register
 * (GSNPSID). Read the register into the <i>d32</i> element then read out the
 * bits using the <i>b</i>it elements.
 */
typedef union gsnpsid_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned rwdata:32;
	} b;
} gsnpsid_data_t;

/**
 * This union represents the bit fields in the User HW Config1
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg1_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned ep_dir0:2;
		unsigned ep_dir1:2;
		unsigned ep_dir2:2;
		unsigned ep_dir3:2;
		unsigned ep_dir4:2;
		unsigned ep_dir5:2;
		unsigned ep_dir6:2;
		unsigned ep_dir7:2;
		unsigned ep_dir8:2;
		unsigned ep_dir9:2;
		unsigned ep_dir10:2;
		unsigned ep_dir11:2;
		unsigned ep_dir12:2;
		unsigned ep_dir13:2;
		unsigned ep_dir14:2;
		unsigned ep_dir15:2;
	} b;
} hwcfg1_data_t;

/**
 * This union represents the bit fields in the User HW Config2
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg2_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/* GHWCFG2 */
		unsigned op_mode:3;
#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6

		unsigned architecture:2;
		unsigned point2point:1;
		unsigned hs_phy_type:2;
#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3

		unsigned fs_phy_type:2;
		unsigned num_dev_ep:4;
		unsigned num_host_chan:4;
		unsigned perio_ep_supported:1;
		unsigned dynamic_fifo:1;
		unsigned multi_proc_int:1;
		unsigned reserved21:1;
		unsigned nonperio_tx_q_depth:2;
		unsigned host_perio_tx_q_depth:2;
		unsigned dev_token_q_depth:5;
		unsigned otg_enable_ic_usb:1;
	} b;
} hwcfg2_data_t;

/**
 * This union represents the bit fields in the User HW Config3
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg3_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/* GHWCFG3 */
		unsigned xfer_size_cntr_width:4;
		unsigned packet_size_cntr_width:3;
		unsigned otg_func:1;
		unsigned i2c:1;
		unsigned vendor_ctrl_if:1;
		unsigned optional_features:1;
		unsigned synch_reset_type:1;
		unsigned adp_supp:1;
		unsigned otg_enable_hsic:1;
		unsigned bc_support:1;
		unsigned otg_lpm_en:1;
		unsigned dfifo_depth:16;
	} b;
} hwcfg3_data_t;

/**
 * This union represents the bit fields in the User HW Config4
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg4_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		unsigned num_dev_perio_in_ep:4;
		unsigned power_optimiz:1;
		unsigned min_ahb_freq:1;
		unsigned hiber:1;
		unsigned xhiber:1;
		unsigned reserved:6;
		unsigned utmi_phy_data_width:2;
		unsigned num_dev_mode_ctrl_ep:4;
		unsigned iddig_filt_en:1;
		unsigned vbus_valid_filt_en:1;
		unsigned a_valid_filt_en:1;
		unsigned b_valid_filt_en:1;
		unsigned session_end_filt_en:1;
		unsigned ded_fifo_en:1;
		unsigned num_in_eps:4;
		unsigned desc_dma:1;
		unsigned desc_dma_dyn:1;
	} b;
} hwcfg4_data_t;

/**
 * This union represents the bit fields of the Core LPM Configuration
 * Register (GLPMCFG). Set the bits using bit fields then write
 * the <i>d32</i> value to the register.
 */
typedef union glpmctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** LPM-Capable (LPMCap) (Device and Host)
		 * The application uses this bit to control
		 * the DWC_otg core LPM capabilities.
		 */
		unsigned lpm_cap_en:1;
		/** LPM response programmed by application (AppL1Res) (Device)
		 * Handshake response to LPM token pre-programmed
		 * by device application software.
		 */
		unsigned appl_resp:1;
		/** Host Initiated Resume Duration (HIRD) (Device and Host)
		 * In Host mode this field indicates the value of HIRD
		 * to be sent in an LPM transaction.
		 * In Device mode this field is updated with the
		 * Received LPM Token HIRD bmAttribute
		 * when an ACK/NYET/STALL response is sent
		 * to an LPM transaction.
		 */
		unsigned hird:4;
		/** RemoteWakeEnable (bRemoteWake) (Device and Host)
		 * In Host mode this bit indicates the value of remote
		 * wake up to be sent in wIndex field of LPM transaction.
		 * In Device mode this field is updated with the
		 * Received LPM Token bRemoteWake bmAttribute
		 * when an ACK/NYET/STALL response is sent
		 * to an LPM transaction.
		 */
		unsigned rem_wkup_en:1;
		/** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
		 * The application uses this bit to control
		 * the utmi_sleep_n assertion to the PHY when in L1 state.
		 */
		unsigned en_utmi_sleep:1;
		/** HIRD Threshold (HIRD_Thres) (Device and Host)
		 */
		unsigned hird_thres:5;
		/** LPM Response (CoreL1Res) (Device and Host)
		 * In Host mode this bit contains handsake response to
		 * LPM transaction.
		 * In Device mode the response of the core to
		 * LPM transaction received is reflected in these two bits.
		 	- 0x0 : ERROR (No handshake response)
			- 0x1 : STALL
			- 0x2 : NYET
			- 0x3 : ACK
		 */
		unsigned lpm_resp:2;
		/** Port Sleep Status (SlpSts) (Device and Host)
		 * This bit is set as long as a Sleep condition
		 * is present on the USB bus.
		 */
		unsigned prt_sleep_sts:1;
		/** Sleep State Resume OK (L1ResumeOK) (Device and Host)
		 * Indicates that the application or host
		 * can start resume from Sleep state.
		 */
		unsigned sleep_state_resumeok:1;
		/** LPM channel Index (LPM_Chnl_Indx) (Host)
		 * The channel number on which the LPM transaction
		 * has to be applied while sending
		 * an LPM transaction to the local device.
		 */
		unsigned lpm_chan_index:4;
		/** LPM Retry Count (LPM_Retry_Cnt) (Host)
		 * Number host retries that would be performed
		 * if the device response was not valid response.
		 */
		unsigned retry_count:3;
		/** Send LPM Transaction (SndLPM) (Host)
		 * When set by application software,
		 * an LPM transaction containing two tokens
		 * is sent.
		 */
		unsigned send_lpm:1;
		/** LPM Retry status (LPM_RetryCnt_Sts) (Host)
		 * Number of LPM Host Retries still remaining
		 * to be transmitted for the current LPM sequence
		 */
		unsigned retry_count_sts:3;
		/** Enable Best Effort Service Latency (BESL) (Device and Host)
		 *  This bit enables the BESL features as defined in the LPM errata
		 */
		unsigned en_besl:1;

		unsigned reserved29:1;
		/** In host mode once this bit is set, the host
		 * configures to drive the HSIC Idle state on the bus.
		 * It then waits for the  device to initiate the Connect sequence.
		 * In device mode once this bit is set, the device waits for
		 * the HSIC Idle line state on the bus. Upon receving the Idle
		 * line state, it initiates the HSIC Connect sequence.
		 */
		unsigned hsic_connect:1;
		/** This bit overrides and functionally inverts
		 * the if_select_hsic input port signal.
		 */
		unsigned inv_sel_hsic:1;
	} b;
} glpmcfg_data_t;

/**
 * This union represents the bit fields of the Core ADP Timer, Control and
 * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
 * the <i>d32</i> value to the register.
 */
typedef union adpctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Probe Discharge (PRB_DSCHG)
		 *  These bits set the times for TADP_DSCHG.
		 *  These bits are defined as follows:
		 *  2'b00 - 4 msec
		 *  2'b01 - 8 msec
		 *  2'b10 - 16 msec
		 *  2'b11 - 32 msec
		 */
		unsigned prb_dschg:2;
		/** Probe Delta (PRB_DELTA)
		 *  These bits set the resolution for RTIM   value.
		 *  The bits are defined in units of 32 kHz clock cycles as follows:
		 *  2'b00  -  1 cycles
		 *  2'b01  -  2 cycles
		 *  2'b10 -  3 cycles
		 *  2'b11 - 4 cycles
		 *  For example if this value is chosen to 2'b01, it means that RTIM
		 *  increments for every 3(three) 32Khz clock cycles.
		 */
		unsigned prb_delta:2;
		/** Probe Period (PRB_PER)
		 *  These bits sets the TADP_PRD as shown in Figure 4 as follows:
		 *  2'b00  -  0.625 to 0.925 sec (typical 0.775 sec)
		 *  2'b01  -  1.25 to 1.85 sec (typical 1.55 sec)
		 *  2'b10  -  1.9 to 2.6 sec (typical 2.275 sec)
		 *  2'b11  -  Reserved
		 */
		unsigned prb_per:2;
		/** These bits capture the latest time it took for VBUS to ramp from
		 *  VADP_SINK to VADP_PRB.
		 *  0x000  -  1 cycles
		 *  0x001  -  2 cycles
		 *  0x002  -  3 cycles
		 *  etc
		 *  0x7FF  -  2048 cycles
		 *  A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
		*/
		unsigned rtim:11;
		/** Enable Probe (EnaPrb)
		 *  When programmed to 1'b1, the core performs a probe operation.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned enaprb:1;
		/** Enable Sense (EnaSns)
		 *  When programmed to 1'b1, the core performs a Sense operation.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned enasns:1;
		/** ADP Reset (ADPRes)
		 *  When set, ADP controller is reset.
		 *  This bit is valid only if OTG_Ver = 1'b1.
 		 */
		unsigned adpres:1;
		/** ADP Enable (ADPEn)
		 *  When set, the core performs either ADP probing or sensing
		 *  based on EnaPrb or EnaSns.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adpen:1;
		/** ADP Probe Interrupt (ADP_PRB_INT)
		 *  When this bit is set, it means that the VBUS
		 *  voltage is greater than VADP_PRB or VADP_PRB is reached.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adp_prb_int:1;
		/**
		 *  ADP Sense Interrupt (ADP_SNS_INT)
		 *  When this bit is set, it means that the VBUS voltage is greater than
		 *  VADP_SNS value or VADP_SNS is reached.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adp_sns_int:1;
		/** ADP Tomeout Interrupt (ADP_TMOUT_INT)
		 *  This bit is relevant only for an ADP probe.
		 *  When this bit is set, it means that the ramp time has
		 *  completed ie ADPCTL.RTIM has reached its terminal value
		 *  of 0x7FF.  This is a debug feature that allows software
		 *  to read the ramp time after each cycle.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adp_tmout_int:1;
		/** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
		 *  When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adp_prb_int_msk:1;
		/** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
		 *  When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adp_sns_int_msk:1;
		/** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
		 *  When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
		 *  This bit is valid only if OTG_Ver = 1'b1.
		 */
		unsigned adp_tmout_int_msk:1;
		/** Access Request
		 * 2'b00 - Read/Write Valid (updated by the core)
		 * 2'b01 - Read
		 * 2'b00 - Write
		 * 2'b00 - Reserved
		 */
		unsigned ar:2;
		 /** Reserved */
		unsigned reserved29_31:3;
	} b;
} adpctl_data_t;

////////////////////////////////////////////
// Device Registers
/**
 * Device Global Registers. <i>Offsets 800h-BFFh</i>
 *
 * The following structures define the size and relative field offsets
 * for the Device Mode Registers.
 *
 * <i>These registers are visible only in Device mode and must not be
 * accessed in Host mode, as the results are unknown.</i>
 */
typedef struct dwc_otg_dev_global_regs {
	/** Device Configuration Register. <i>Offset 800h</i> */
	volatile UINT_T dcfg;
	/** Device Control Register. <i>Offset: 804h</i> */
	volatile UINT_T dctl;
	/** Device Status Register (Read Only). <i>Offset: 808h</i> */
	volatile UINT_T dsts;
	/** Reserved. <i>Offset: 80Ch</i> */
	UINT_T unused;
	/** Device IN Endpoint Common Interrupt Mask
	 * Register. <i>Offset: 810h</i> */
	volatile UINT_T diepmsk;
	/** Device OUT Endpoint Common Interrupt Mask
	 * Register. <i>Offset: 814h</i> */
	volatile UINT_T doepmsk;
	/** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
	volatile UINT_T daint;
	/** Device All Endpoints Interrupt Mask Register.  <i>Offset:
	 * 81Ch</i> */
	volatile UINT_T daintmsk;
	/** Device IN Token Queue Read Register-1 (Read Only).
	 * <i>Offset: 820h</i> */
	volatile UINT_T dtknqr1;
	/** Device IN Token Queue Read Register-2 (Read Only).
	 * <i>Offset: 824h</i> */
	volatile UINT_T dtknqr2;
	/** Device VBUS	 discharge Register.  <i>Offset: 828h</i> */
	volatile UINT_T dvbusdis;
	/** Device VBUS Pulse Register.	 <i>Offset: 82Ch</i> */
	volatile UINT_T dvbuspulse;
	/** Device IN Token Queue Read Register-3 (Read Only). /
	 *	Device Thresholding control register (Read/Write)
	 * <i>Offset: 830h</i> */
	volatile UINT_T dtknqr3_dthrctl;
	/** Device IN Token Queue Read Register-4 (Read Only). /
	 *	Device IN EPs empty Inr. Mask Register (Read/Write)
	 * <i>Offset: 834h</i> */
	volatile UINT_T dtknqr4_fifoemptymsk;
	/** Device Each Endpoint Interrupt Register (Read Only). /
	 * <i>Offset: 838h</i> */
	volatile UINT_T deachint;
	/** Device Each Endpoint Interrupt mask Register (Read/Write). /
	 * <i>Offset: 83Ch</i> */
	volatile UINT_T deachintmsk;
	/** Device Each In Endpoint Interrupt mask Register (Read/Write). /
	 * <i>Offset: 840h</i> */
	volatile UINT_T diepeachintmsk[MAX_EPS_CHANNELS];
	/** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
	 * <i>Offset: 880h</i> */
	volatile UINT_T doepeachintmsk[MAX_EPS_CHANNELS];
} dwc_otg_device_global_regs_t;

/**
 * This union represents the bit fields in the Device Configuration
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.  Write the
 * <i>d32</i> member to the dcfg register.
 */
typedef union dcfg_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Device Speed */
		unsigned devspd:2;
		/** Non Zero Length Status OUT Handshake */
		unsigned nzstsouthshk:1;
#define DWC_DCFG_SEND_STALL 1

		unsigned ena32khzs:1;
		/** Device Addresses */
		unsigned devaddr:7;
		/** Periodic Frame Interval */
		unsigned perfrint:2;
#define DWC_DCFG_FRAME_INTERVAL_80 0
#define DWC_DCFG_FRAME_INTERVAL_85 1
#define DWC_DCFG_FRAME_INTERVAL_90 2
#define DWC_DCFG_FRAME_INTERVAL_95 3

		/** Enable Device OUT NAK for bulk in DDMA mode */
		unsigned endevoutnak:1;

		unsigned reserved14_17:4;
		/** In Endpoint Mis-match count */
		unsigned epmscnt:5;
		/** Enable Descriptor DMA in Device mode */
		unsigned descdma:1;
		unsigned perschintvl:2;
		unsigned resvalid:6;
	} b;
} dcfg_data_t;

/**
 * This union represents the bit fields in the Device Control
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union dctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Remote Wakeup */
		unsigned rmtwkupsig:1;
		/** Soft Disconnect */
		unsigned sftdiscon:1;
		/** Global Non-Periodic IN NAK Status */
		unsigned gnpinnaksts:1;
		/** Global OUT NAK Status */
		unsigned goutnaksts:1;
		/** Test Control */
		unsigned tstctl:3;
		/** Set Global Non-Periodic IN NAK */
		unsigned sgnpinnak:1;
		/** Clear Global Non-Periodic IN NAK */
		unsigned cgnpinnak:1;
		/** Set Global OUT NAK */
		unsigned sgoutnak:1;
		/** Clear Global OUT NAK */
		unsigned cgoutnak:1;
		/** Power-On Programming Done */
		unsigned pwronprgdone:1;
		/** Reserved */
		unsigned reserved:1;
		/** Global Multi Count */
		unsigned gmc:2;
		/** Ignore Frame Number for ISOC EPs */
		unsigned ifrmnum:1;
		/** NAK on Babble */
		unsigned nakonbble:1;
		/** Enable Continue on BNA */
		unsigned encontonbna:1;
		/** Enable deep sleep besl reject feature*/
		unsigned besl_reject:1;

		unsigned reserved17_31:13;
	} b;
} dctl_data_t;

/**
 * This union represents the bit fields in the Device Status
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union dsts_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Suspend Status */
		unsigned suspsts:1;
		/** Enumerated Speed */
		unsigned enumspd:2;
#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ		   2
#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ		   3
		/** Erratic Error */
		unsigned errticerr:1;
		unsigned reserved4_7:4;
		/** Frame or Microframe Number of the received SOF */
		unsigned soffn:14;
		unsigned reserved22_31:10;
	} b;
} dsts_data_t;

/**
 * This union represents the bit fields in the Device IN EP Interrupt
 * Register and the Device IN EP Common Mask Register.
 *
 * - Read the register into the <i>d32</i> member then set/clear the
 *	 bits using the <i>b</i>it elements.
 */
typedef union diepint_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Transfer complete mask */
		unsigned xfercompl:1;
		/** Endpoint disable mask */
		unsigned epdisabled:1;
		/** AHB Error mask */
		unsigned ahberr:1;
		/** TimeOUT Handshake mask (non-ISOC EPs) */
		unsigned timeout:1;
		/** IN Token received with TxF Empty mask */
		unsigned intktxfemp:1;
		/** IN Token Received with EP mismatch mask */
		unsigned intknepmis:1;
		/** IN Endpoint NAK Effective mask */
		unsigned inepnakeff:1;
		/** Reserved */
		unsigned emptyintr:1;

		unsigned txfifoundrn:1;

		/** BNA Interrupt mask */
		unsigned bna:1;

		unsigned reserved10_12:3;
		/** BNA Interrupt mask */
		unsigned nak:1;

		unsigned reserved14_31:18;
	} b;
} diepint_data_t;

/**
 * This union represents the bit fields in the Device IN EP
 * Common/Dedicated Interrupt Mask Register.
 */
typedef union diepint_data diepmsk_data_t;

/**
 * This union represents the bit fields in the Device OUT EP Interrupt
 * Registerand Device OUT EP Common Interrupt Mask Register.
 *
 * - Read the register into the <i>d32</i> member then set/clear the
 *	 bits using the <i>b</i>it elements.
 */
typedef union doepint_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Transfer complete */
		unsigned xfercompl:1;
		/** Endpoint disable  */
		unsigned epdisabled:1;
		/** AHB Error */
		unsigned ahberr:1;
		/** Setup Phase Done (contorl EPs) */
		unsigned setup:1;
		/** OUT Token Received when Endpoint Disabled */
		unsigned outtknepdis:1;

		unsigned stsphsercvd:1;
		/** Back-to-Back SETUP Packets Received */
		unsigned back2backsetup:1;

		unsigned reserved7:1;
		/** OUT packet Error */
		unsigned outpkterr:1;
		/** BNA Interrupt */
		unsigned bna:1;

		unsigned reserved10:1;
		/** Packet Drop Status */
		unsigned pktdrpsts:1;
		/** Babble Interrupt */
		unsigned babble:1;
		/** NAK Interrupt */
		unsigned nak:1;
		/** NYET Interrupt */
		unsigned nyet:1;
		/** Bit indicating setup packet received */
		unsigned sr:1;

		unsigned reserved16_31:16;
	} b;
} doepint_data_t;

/**
 * This union represents the bit fields in the Device OUT EP
 * Common/Dedicated Interrupt Mask Register.
 */
typedef union doepint_data doepmsk_data_t;

/**
 * This union represents the bit fields in the Device All EP Interrupt
 * and Mask Registers.
 * - Read the register into the <i>d32</i> member then set/clear the
 *	 bits using the <i>b</i>it elements.
 */
typedef union daint_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** IN Endpoint bits */
		unsigned in:16;
		/** OUT Endpoint bits */
		unsigned out:16;
	} ep;
	struct {
		/** IN Endpoint bits */
		unsigned inep0:1;
		unsigned inep1:1;
		unsigned inep2:1;
		unsigned inep3:1;
		unsigned inep4:1;
		unsigned inep5:1;
		unsigned inep6:1;
		unsigned inep7:1;
		unsigned inep8:1;
		unsigned inep9:1;
		unsigned inep10:1;
		unsigned inep11:1;
		unsigned inep12:1;
		unsigned inep13:1;
		unsigned inep14:1;
		unsigned inep15:1;
		/** OUT Endpoint bits */
		unsigned outep0:1;
		unsigned outep1:1;
		unsigned outep2:1;
		unsigned outep3:1;
		unsigned outep4:1;
		unsigned outep5:1;
		unsigned outep6:1;
		unsigned outep7:1;
		unsigned outep8:1;
		unsigned outep9:1;
		unsigned outep10:1;
		unsigned outep11:1;
		unsigned outep12:1;
		unsigned outep13:1;
		unsigned outep14:1;
		unsigned outep15:1;
	} b;
} daint_data_t;

/**
 * This union represents the bit fields in the Device IN Token Queue
 * Read Registers.
 * - Read the register into the <i>d32</i> member.
 * - READ-ONLY Register
 */
typedef union dtknq1_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** In Token Queue Write Pointer */
		unsigned intknwptr:5;
		/** Reserved */
		unsigned reserved05_06:2;
		/** write pointer has wrapped. */
		unsigned wrap_bit:1;
		/** EP Numbers of IN Tokens 0 ... 4 */
		unsigned epnums0_5:24;
	} b;
} dtknq1_data_t;

/**
 * This union represents Threshold control Register
 * - Read and write the register into the <i>d32</i> member.
 * - READ-WRITABLE Register
 */
typedef union dthrctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** non ISO Tx Thr. Enable */
		unsigned non_iso_thr_en:1;
		/** ISO Tx Thr. Enable */
		unsigned iso_thr_en:1;
		/** Tx Thr. Length */
		unsigned tx_thr_len:9;
		/** AHB Threshold ratio */
		unsigned ahb_thr_ratio:2;
		/** Reserved */
		unsigned reserved13_15:3;
		/** Rx Thr. Enable */
		unsigned rx_thr_en:1;
		/** Rx Thr. Length */
		unsigned rx_thr_len:9;
		unsigned reserved26:1;
		/** Arbiter Parking Enable*/
		unsigned arbprken:1;
		/** Reserved */
		unsigned reserved28_31:4;
	} b;
} dthrctl_data_t;

/**
 * Device Logical IN Endpoint-Specific Registers. <i>Offsets
 * 900h-AFCh</i>
 *
 * There will be one set of endpoint registers per logical endpoint
 * implemented.
 *
 * <i>These registers are visible only in Device mode and must not be
 * accessed in Host mode, as the results are unknown.</i>
 */
typedef struct dwc_otg_dev_in_ep_regs {
	/** Device IN Endpoint Control Register. <i>Offset:900h +
	 * (ep_num * 20h) + 00h</i> */
	volatile UINT_T diepctl;
	/** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
	UINT_T reserved04;
	/** Device IN Endpoint Interrupt Register. <i>Offset:900h +
	 * (ep_num * 20h) + 08h</i> */
	volatile UINT_T diepint;
	/** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
	UINT_T reserved0C;
	/** Device IN Endpoint Transfer Size
	 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
	volatile UINT_T dieptsiz;
	/** Device IN Endpoint DMA Address Register. <i>Offset:900h +
	 * (ep_num * 20h) + 14h</i> */
	volatile UINT_T diepdma;
	/** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
	 * (ep_num * 20h) + 18h</i> */
	volatile UINT_T dtxfsts;
	/** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
	 * (ep_num * 20h) + 1Ch</i> */
	volatile UINT_T diepdmab;
} dwc_otg_dev_in_ep_regs_t;

/**
 * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
 * B00h-CFCh</i>
 *
 * There will be one set of endpoint registers per logical endpoint
 * implemented.
 *
 * <i>These registers are visible only in Device mode and must not be
 * accessed in Host mode, as the results are unknown.</i>
 */
typedef struct dwc_otg_dev_out_ep_regs {
	/** Device OUT Endpoint Control Register. <i>Offset:B00h +
	 * (ep_num * 20h) + 00h</i> */
	volatile UINT_T doepctl;
	/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
	UINT_T reserved04;
	/** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
	 * (ep_num * 20h) + 08h</i> */
	volatile UINT_T doepint;
	/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
	UINT_T reserved0C;
	/** Device OUT Endpoint Transfer Size Register. <i>Offset:
	 * B00h + (ep_num * 20h) + 10h</i> */
	volatile UINT_T doeptsiz;
	/** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
	 * + (ep_num * 20h) + 14h</i> */
	volatile UINT_T doepdma;
	/** Reserved. <i>Offset:B00h + 	 * (ep_num * 20h) + 18h</i> */
	UINT_T unused;
	/** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
	 * + (ep_num * 20h) + 1Ch</i> */
	UINT_T doepdmab;
} dwc_otg_dev_out_ep_regs_t;

/**
 * This union represents the bit fields in the Device EP Control
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union depctl_data {
	/** raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** Maximum Packet Size
		 * IN/OUT EPn
		 * IN/OUT EP0 - 2 bits
		 *	 2'b00: 64 Bytes
		 *	 2'b01: 32
		 *	 2'b10: 16
		 *	 2'b11: 8 */
		unsigned mps:11;
#define DWC_DEP0CTL_MPS_64	 0
#define DWC_DEP0CTL_MPS_32	 1
#define DWC_DEP0CTL_MPS_16	 2
#define DWC_DEP0CTL_MPS_8	 3

		/** Next Endpoint
		 * IN EPn/IN EP0
		 * OUT EPn/OUT EP0 - reserved */
		unsigned nextep:4;

		/** USB Active Endpoint */
		unsigned usbactep:1;

		/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
		 * This field contains the PID of the packet going to
		 * be received or transmitted on this endpoint. The
		 * application should program the PID of the first
		 * packet going to be received or transmitted on this
		 * endpoint , after the endpoint is
		 * activated. Application use the SetD1PID and
		 * SetD0PID fields of this register to program either
		 * D0 or D1 PID.
		 *
		 * The encoding for this field is
		 *	 - 0: D0
		 *	 - 1: D1
		 */
		unsigned dpid:1;

		/** NAK Status */
		unsigned naksts:1;

		/** Endpoint Type
		 *	2'b00: Control
		 *	2'b01: Isochronous
		 *	2'b10: Bulk
		 *	2'b11: Interrupt */
		unsigned eptype:2;

		/** Snoop Mode
		 * OUT EPn/OUT EP0
		 * IN EPn/IN EP0 - reserved */
		unsigned snp:1;

		/** Stall Handshake */
		unsigned stall:1;

		/** Tx Fifo Number
		 * IN EPn/IN EP0
		 * OUT EPn/OUT EP0 - reserved */
		unsigned txfnum:4;

		/** Clear NAK */
		unsigned cnak:1;
		/** Set NAK */
		unsigned snak:1;
		/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
		 * Writing to this field sets the Endpoint DPID (DPID)
		 * field in this register to DATA0. Set Even
		 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
		 * Writing to this field sets the Even/Odd
		 * (micro)frame (EO_FrNum) field to even (micro)
		 * frame.
		 */
		unsigned setd0pid:1;
		/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
		 * Writing to this field sets the Endpoint DPID (DPID)
		 * field in this register to DATA1 Set Odd
		 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
		 * Writing to this field sets the Even/Odd
		 * (micro)frame (EO_FrNum) field to odd (micro) frame.
		 */
		unsigned setd1pid:1;

		/** Endpoint Disable */
		unsigned epdis:1;
		/** Endpoint Enable */
		unsigned epena:1;
	} b;
} depctl_data_t;

/**
 * This union represents the bit fields in the Device EP Transfer
 * Size Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union deptsiz_data {
		/** raw register data */
	UINT_T d32;
		/** register bits */
	struct {
		/** Transfer size */
		unsigned xfersize:19;
/** Max packet count for EP (pow(2,10)-1) */
#define MAX_PKT_CNT 1023
		/** Packet Count */
		unsigned pktcnt:10;
		/** Multi Count - Periodic IN endpoints */
		unsigned mc:2;
		unsigned reserved:1;
	} b;
} deptsiz_data_t;

/**
 * This union represents the bit fields in the Device EP 0 Transfer
 * Size Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union deptsiz0_data {
		/** raw register data */
	UINT_T d32;
		/** register bits */
	struct {
		/** Transfer size */
		unsigned xfersize:7;
				/** Reserved */
		unsigned reserved7_18:12;
		/** Packet Count */
		unsigned pktcnt:2;
				/** Reserved */
		unsigned reserved21_28:8;
				/**Setup Packet Count (DOEPTSIZ0 Only) */
		unsigned supcnt:2;
		unsigned reserved31;
	} b;
} deptsiz0_data_t;

/**
 * This union represents the bit fields in the Power and Clock Gating Control
 * Register. Read the register into the <i>d32</i> member then set/clear the
 * bits using the <i>b</i>it elements.
 */
typedef union pcgcctl_data {
	/** raw register data */
	UINT_T d32;

	/** register bits */
	struct {
		/** Stop Pclk */
		unsigned stoppclk:1;
		/** Gate Hclk */
		unsigned gatehclk:1;
		/** Power Clamp */
		unsigned pwrclmp:1;
		/** Reset Power Down Modules */
		unsigned rstpdwnmodule:1;
		/** Reserved */
		unsigned reserved:1;
		/** Enable Sleep Clock Gating (Enbl_L1Gating) */
		unsigned enbl_sleep_gating:1;
		/** PHY In Sleep (PhySleep) */
		unsigned phy_in_sleep:1;
		/** Deep Sleep*/
		unsigned deep_sleep:1;
		unsigned resetaftsusp:1;
		unsigned restoremode:1;
		unsigned enbl_extnd_hiber:1;
		unsigned extnd_hiber_pwrclmp:1;
		unsigned extnd_hiber_switch:1;
		unsigned ess_reg_restored:1;
		unsigned prt_clk_sel:2;
		unsigned port_power:1;
		unsigned max_xcvrselect:2;
		unsigned max_termsel:1;
		unsigned mac_dev_addr:7;
		unsigned p2hd_dev_enum_spd:2;
		unsigned p2hd_prt_spd:2;
		unsigned if_dev_mode:1;
	} b;
} pcgcctl_data_t;

/**
 * This union represents the bit fields in the Global Data FIFO Software
 * Configuration Register. Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union gdfifocfg_data {
	/* raw register data */
	UINT_T d32;
	/** register bits */
	struct {
		/** OTG Data FIFO depth */
		unsigned gdfifocfg:16;
		/** Start address of EP info controller */
		unsigned epinfobase:16;
	} b;
} gdfifocfg_data_t;

/**
 * This union represents the bit fields in the Global Power Down Register
 * Register. Read the register into the <i>d32</i> member then set/clear the
 * bits using the <i>b</i>it elements.
 */
typedef union gpwrdn_data {
	/* raw register data */
	UINT_T d32;

	/** register bits */
	struct {
		/** PMU Interrupt Select */
		unsigned pmuintsel:1;
		/** PMU Active */
		unsigned pmuactv:1;
		/** Restore */
		unsigned restore:1;
		/** Power Down Clamp */
		unsigned pwrdnclmp:1;
		/** Power Down Reset */
		unsigned pwrdnrstn:1;
		/** Power Down Switch */
		unsigned pwrdnswtch:1;
		/** Disable VBUS */
		unsigned dis_vbus:1;
		/** Line State Change */
		unsigned lnstschng:1;
		/** Line state change mask */
		unsigned lnstchng_msk:1;
		/** Reset Detected */
		unsigned rst_det:1;
		/** Reset Detect mask */
		unsigned rst_det_msk:1;
		/** Disconnect Detected */
		unsigned disconn_det:1;
		/** Disconnect Detect mask */
		unsigned disconn_det_msk:1;
		/** Connect Detected*/
		unsigned connect_det:1;
		/** Connect Detected Mask*/
		unsigned connect_det_msk:1;
		/** SRP Detected */
		unsigned srp_det:1;
		/** SRP Detect mask */
		unsigned srp_det_msk:1;
		/** Status Change Interrupt */
		unsigned sts_chngint:1;
		/** Status Change Interrupt Mask */
		unsigned sts_chngint_msk:1;
		/** Line State */
		unsigned linestate:2;
		/** Indicates current mode(status of IDDIG signal) */
		unsigned idsts:1;
		/** B Session Valid signal status*/
		unsigned bsessvld:1;
		/** ADP Event Detected */
		unsigned adp_int:1;
		/** Multi Valued ID pin */
		unsigned mult_val_id_bc:5;
		/** Reserved 24_31 */
		unsigned reserved29_31:3;
	} b;
} gpwrdn_data_t;

typedef struct asr_usb_device{
	UINT_T *base;
#define CORE_GLOBAL_OFFSET 0x0
	dwc_otg_core_global_regs_t *core_glb_regs;
#define CORE_DEVICE_OFFSET 0x800
	dwc_otg_device_global_regs_t *dev_glb_regs;
#define IN_EP_OFFSET 0x900

	dwc_otg_dev_in_ep_regs_t *dev_in_ep_regs[16];
#define OUT_EP_OFFSET 0xB00

	dwc_otg_dev_out_ep_regs_t *dev_out_ep_regs[16];

} asr_usb_device_t;

static inline UINT_T dwc_read_reg32(UINT_T reg)
{
	return (*(volatile UINT_T *)(reg));
}

static inline void dwc_write_reg32(UINT_T reg, UINT_T value)
{
	(*(volatile UINT_T *)(reg)) = value;
}

static inline void dwc_modify_reg32(UINT_T reg, UINT_T clear_mask, UINT_T set_mask)
{
	dwc_write_reg32(reg, ((dwc_read_reg32(reg) & (~clear_mask)) | (set_mask)));
}
#endif