marvell/obm/Common/Flash/SPI/NZA3/spi.c

/******************************************************************************
 *
 *  (C)Copyright 2014 Marvell Hefei Branch. All Rights Reserved.
 *
 *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
 *  The copyright notice above does not evidence any actual or intended
 *  publication of such source code.
 *  This Module contains Proprietary Information of Marvell and should be
 *  treated as Confidential.
 *  The information in this file is provided for the exclusive use of the
 *  licensees of Marvell.
 *  Such users have the right to use, modify, and incorporate this code into
 *  products for purposes authorized by the license agreement provided they
 *  include this notice and the associated copyright notice with any such
 *  product.
 *  The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

#include "spi.h"
#include "xllp_dmac.h"

VUINT_T ssp_52mhz = 0;

__attribute__ ((aligned(16))) XLLP_DMAC_DESCRIPTOR_T pRX_data, pTX_cmd;
__attribute__ ((aligned(16)))unsigned int	 tx_command[2112] = {0};
UINT_T spi_tx_dma, spi_rx_dma;

void Assert_CS(void)
{
	*pGPIO_CR |= GPIO_CS_SET;
	
	while (*pGPIO_LR & GPIO_CS_SET);
}

void Deassert_CS(void)
{
	*pGPIO_SR |= GPIO_CS_SET;
	
	while (!(*pGPIO_LR & GPIO_CS_SET));
}

void ROW_DELAY(UINT_T x)
{
	while (x > 0)
	{
		x--;
	}
}

void SPI_DisableSSP(void)
{
	//make sure SSP is disabled
	reg_bit_clr(SSP_CR0, SSP_CR0_SSE);
	//reset SSP CR's
	reg_write(SSP_CR0, SSP_CR0_INITIAL);
	reg_write(SSP_CR1, SSP_CR1_INITIAL);
}

void SPI_WaitSSPComplete(void)
{
	while (*SSP_SR & (SSP_SSSR_BSY | SSP_SSSR_TFL))
	{
		ROW_DELAY(DEFAULT_TIMEOUT);
	}
}

/***********************************************************
*   SPI_Write_Read
*   	PIO mode to write and then read out the data
*   Returns:
*	    None
*************************************************************/
void SPI_Write_Read(unsigned char *cmd, unsigned char *data, unsigned char len)
{
	unsigned char i;
	
	for (i = 0; i < len; i++)
	{
		BU_REG_WRITE8(SSP_DR, cmd[i]);
		SPI_WaitSSPComplete();

		data[i] = BU_REG_READ8(SSP_DR);
	}
}

void SPI_GetSSPDMAReqNum(UINT_T *tx, UINT_T *rx)
{
	UINT_T SPI_DMA_TXReqNum = DMAC_SSP_2_TX;
	UINT_T SPI_DMA_RXReqNum = DMAC_SSP_2_RX;

#if NZA3
	switch (PlatformGetRevisionID())
	{
		case 0xF0:
		case 0xF2:
			SPI_DMA_TXReqNum = DMAC_SSP_2_TX_Z2;
			SPI_DMA_RXReqNum = DMAC_SSP_2_RX_Z2;
			break;

		case 0xF3: 
		default: // here we suppose next step uses same SPI DMA reqest number as Z3
			break;
	}
#endif

	*tx = SPI_DMA_TXReqNum;
	*rx = SPI_DMA_RXReqNum;
}