marvell/obm/Common/Include/general.h

/******************************************************************************
**
** INTEL CONFIDENTIAL
** Copyright 2003-2004 Intel Corporation All Rights Reserved.
**
** The source code contained or described herein and all documents
** related to the source code (Material) are owned by Intel Corporation
** or its suppliers or licensors.  Title to the Material remains with
** Intel Corporation or its suppliers and licensors. The Material contains
** trade secrets and proprietary and confidential information of Intel
** or its suppliers and licensors. The Material is protected by worldwide
** copyright and trade secret laws and treaty provisions. No part of the
** Material may be used, copied, reproduced, modified, published, uploaded,
** posted, transmitted, distributed, or disclosed in any way without Intel's
** prior express written permission.
**
** No license under any patent, copyright, trade secret or other intellectual
** property right is granted to or conferred upon you by disclosure or
** delivery of the Materials, either expressly, by implication, inducement,
** estoppel or otherwise. Any license under such intellectual property rights
** must be express and approved by Intel in writing.
**
**	 general.h
******************************************************************************//******************************************************************************
 *
 *  (C)Copyright 2005 - 2011 Marvell. All Rights Reserved.
 *
 *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MARVELL.
 *  The copyright notice above does not evidence any actual or intended
 *  publication of such source code.
 *  This Module contains Proprietary Information of Marvell and should be
 *  treated as Confidential.
 *  The information in this file is provided for the exclusive use of the
 *  licensees of Marvell.
 *  Such users have the right to use, modify, and incorporate this code into
 *  products for purposes authorized by the license agreement provided they
 *  include this notice and the associated copyright notice with any such
 *  product.
 *  The information in this file is provided "AS IS" without warranty.
 
 ******************************************************************************/
#ifndef _general_h
#define _general_h

#include "Typedef.h"

#ifndef BYTES_PER_WORD
	#define BYTES_PER_WORD (sizeof( UINT_T ))
#endif

#define MAXRSAKEYSIZEWORDS	 	64				// 2048 bits
#define MAXECCKEYSIZEWORDS 		17				// 521 bits+


/*
 *  Fuse definition structure
 */
#if NZA3
struct PLATFORM_FUSES
{												// The bit fields in the following comments don't hold for ADIR, see ADIR's own definitions!
	UINT DebugDisable						:1;		// Bit 0 of SYS_BOOT_CNTRL and bit 79 dis_strap_override of AP config bits 
	UINT PlatformState						:6;		// Bit 62-66 of AP config bits and bits 22-26 of SYS_BOOT_CNTRL
	UINT NotUsed							:3;		// Not used
	UINT VerifyOEMKey						:1; 	// Bit when OEM key needs to be validated: trusted + initialized OEM key data
	UINT EscapeSeqDisable					:1;		// Bit 17 of SYS_BOOT_CNTRL (Tavor TD only)
	UINT USBDisable							:1;		// Bits 12 USBDisable of SYS_BOOT_CNTRL
	UINT UARTDisable						:1;		// Bits 13 UARTDisable of SYS_BOOT_CNTRL
	UINT MMCHighSpeedTiming					:1;		// Bit [20] of SYS_BOOT_CNTRL and Bits[71] of fuses
	UINT Resume								:1;		// Resume status bit
	UINT USBWakeup							:1;		// Bit 16 of SYS_BOOT_CNTRL
	UINT NotUsed2							:1;		// Not used
	UINT DDRInitialized						:1; 	// Bit 18: If the BootROM already initializes the DDR
	UINT Download_Disable					:1;		// Bit 19 of SYS_BOOT_CNTRL
	UINT SBE								:1;		// Bit 20 of SYS_BOOT_CNTRL (Not for MRNA or MMP2)
	UINT OverrideDisable					:1;		// Bit 78 of AP fuse config bits dis_aib_override
	UINT BootPlatformState					:6;		// There are the bits the BootROM booted from
    UINT NotUsed3							:4;		// Not used
	UINT TBROpMode							:2;		// Bits 10,11 od SYS_BOOT_CNTRL (MRNA and MMP2) only.
	UINT VerifyPIN							:1;		// Enable/Disable Pin Insertion feature
	UINT EBE								:2;		// Enable/Disable Encrypted Boot
	UINT BackUpBoot							:1;		// TBR BackUpBoot: 0 -> Boot with primary TIM, 1 -> Boot with backup TIM
	UINT MMCBootClock						:2;		// 0 - 25 MHz, 1 - 50 MHz, 2 - 100 MHz, 3 - 200 MHz
	UINT JTAGOverrideDisable				:1;		// ADIR only - majority Voting of bits[200:198] of Block3
	UINT JTAGDebugDisable					:1;		// ADIR only 
	UINT EarlyEnableUSB						:1;		// Based on fused USB VID/PID: if set, enable USB as soon as possible
	UINT GPIOToggleDisable					:1;		// ADIR only - disable GPIO toggling
	UINT NotUsed4							:1;		// Not used                                      
	UINT KeyPaddingDisable					:1;		// Set flag to disable key padding before hash
	UINT HSIOversample						:1;		// HSI Oversampling
	UINT HSICEnable							:1;		// Enable HSIC on the platform
	UINT LongKeys							:2;		// Use SHA-512 for hashing keys
	UINT HSIClock							:1;		// Enable HSIC on the platform
	UINT MMCDisable							:1;		// Use SHA-512 for hashing keys
	UINT DisableFixedNonceInJTAGProtocol	:1;		// Disable using signed UUID for JTAG enablement
	UINT Reserved							:11;	// Reserved for future use
};
#endif

#if NZAS || KSTR
struct PLATFORM_FUSES
{
	unsigned int DebugDisable		:1;		//Bit 0   dis_strap_override of AP config bits   0
	unsigned int PlatformState		:5;		//Bit 1-5 Bit 62-66 of AP config bits and bits 22-26 of SYS_BOOT_CNTRL               
	unsigned int TZInitialized		:1;		//Bit 6   TrustZone Initialized
	unsigned int JTAG_Disable		:1;		//Bit 7   Bit 6 of SYS_BOOT_CNTRL	
	unsigned int SSP52M_Disable		:1;		//Bit 8   Disable SSP 52M clock boot
	unsigned int VerifyOEMKey		:1; 	//Bit 9   Force checking Platform Verification keys on Probe.
	unsigned int EscapeSeqDisable	:1;		//Bit 10  Deprecated
	unsigned int USBDisable			:1;		//Bit 11  Deprecated
	unsigned int UARTDisable		:1;		//Bit 12  Deprecated
	unsigned int SPINAND_Disable 	:1;		//Bit 13
	unsigned int Resume				:1;		//Bit 14  
	unsigned int USBWakeup			:1;		//Bit 15  Deprecated
	unsigned int PortEnabled		:1;		//Bit 16  Deprecated
	unsigned int DDRInitialized		:1; 	//Bit 17  If the BootROM already initializes the DDR
	unsigned int Download_Disable	:1;		//Bit 18  Deprecated
	unsigned int SBE				:1;		//Bit 19  Trusted or not
	unsigned int OverrideDisable	:1;		//Bit 20  Bit 78 of AP fuse config bits dis_aib_override
	unsigned int BootPlatformState	:5;		//Bit 21-25 There are the bits the BootROM booted from
	unsigned int USBPort            :2;     //Bit 26-27 Deprecated
	unsigned int UARTPort           :2;     //Bit 28-29 Deprecated
	unsigned int TBROpMode			:2;		//Bit 30-31 OP mode
	unsigned int reserved           :32;
};
#endif

typedef enum 
{
	FFUART_PORT = 0,
	ALTUART_PORT = 1
} UART_PORTS; 

typedef enum 
{
	USB_DIFF_PORT = 0,
	USB_SE_PORT = 1,
	USB_U2D_PORT = 2,
	USB_CI2_PORT = 3
} USB_PORTS; 


typedef union{
	unsigned int value[2];
	struct PLATFORM_FUSES bits;
}FUSE_SET, *pFUSE_SET;

struct BR_ExtraStates
{
	unsigned int BkupTIM        :1;
	unsigned int BkupOBM        :1;
	unsigned int HwHash         :1;
	unsigned int HwRSAV         :1;
	unsigned int EmmcPN         :2;
	unsigned int A7Fdis         :1;
	unsigned int Reserved       :25;
};

typedef union{
	unsigned int value;
	struct BR_ExtraStates bits;
}BR_ESTATE, *pBR_ESTATE;

//list of IDS for use in XFER structure
typedef enum
{
	TIM_DATA = 0x54494D48,		// "TIMH" - refers to tim image
	PT_DATA = 0x4D505420, 		// "MPT " - refers to partition table
	BBT_DATA = 0x4D424254, 		// "MBBT" - refers to bad block table
	RD_DATA = 0x52444953,		// "RDIS" - refers to read disturb list
	TIMFAIL_DATA = 0x54494D46,	// "TIMF" - refers to Tim Boot Failure Structure
	PERF_DATA = 0x50455246		// "PERF" - refers to the Performace data list	
} XFER_DATA;

typedef struct
{
	XFER_DATA data_id;
	UINT_T location;
}	XFER_DATA_PAIR_T, *P_XFER_DATA_PAIR_T;

// This is the Transfer Structure.
//  The first word is the id = 'TBRX'
//  The next few words are fixed data
//  lastly, there is a key/value array to indicate what the bootrom is passing to next image
typedef struct
{
	UINT_T TransferID;
	UINT_T SOD_ACCR0;
	UINT_T FuseVal;
	UINT_T ErrorCode;
	UINT_T ResumeParam[4];
	UINT_T num_data_pairs;
	XFER_DATA_PAIR_T data_pairs[1];
} TRANSFER_STRUCT, *P_TRANSFER_STRUCT;

// This is the Transfer Structure v2.
//  The first word is the id = 'TXv2'
//  The next few words are fixed data
//  Note that the FuseVal is increased to two words. 
//  lastly, there is a key/value array to indicate what the bootrom is passing to next image
typedef struct
{
	UINT_T TransferID;
	UINT_T SOD_ACCR0;
	UINT_T FuseVal[2];
	UINT_T ErrorCode;
	UINT_T ResumeParam[4];
	UINT_T num_data_pairs;
	XFER_DATA_PAIR_T data_pairs[1];
} TRANSFER_STRUCT_v2, *P_TRANSFER_STRUCT_v2;

// Needed to support/differentiate both TRANSFER_STRUCT and TRANSFER_STRUCT_v2
#define TBR_XFER_v2			0x54587632		// "TXv2"

typedef enum
{
	Load_Failure 	   = 0,
	Validation_Failure = 1
} FailureCause;

typedef struct
{
	UINT_T ImageId;
	FailureCause Cause;
} TIM_FAILURE_STRUCT, *pTIM_FAILURE_STRUCT;


typedef enum
{
	BACKUPTIM_NOTINUSE  = 0, //This is the initial state of backup boot when the platform is booting with 
							 //TIM and BootRom hasn't gotten to BackupTim yet
	BACKUPTIM_INUSE     = 1,
	BACKUPTIM_FAILED	= 2,
	BACKUPTIM_NOTSUPPORTED = 3
} BACKUPTIM_STATUS;


// **************** Flash Boot State Offsets *************
// Default TIM flash locations
#define TIMOffset_CS2						0x00000000
#define TIMOffset_NAND						0x00000000
#define TIMOffset_ONENAND					0x00000000
#define TIMOffset_SDMMC						0x00000000	// Could be in Partition 1

// For debug purposes only
#define HEX_LED_CONTROL (volatile unsigned long *)( 0x08000040 )
#define HEX_LED_WRITE (volatile unsigned long *)( 0x08000010 )


#define ALIGN_UP(addr, align)   (((unsigned int)(addr) + (unsigned int)(align) - 1) & (~ ((unsigned int)(align) - 1)))
#define ALIGN_DN(addr, align)   (((unsigned int)(addr)) & (~ ((unsigned int)(align) - 1)))

#endif