marvell/uboot/drivers/crypto/bcm/asr_bcm.h

#ifndef _ASR_BCM_H_
#define _ASR_BCM_H_

#include <common.h>

#define BCM_BASE                 0xD4290000

#define BIU_OFFSET           (BCM_BASE + 0x00000000L)
#define ADEC_OFFSET          (BCM_BASE + 0x00000400L)
#define DMA_OFFSET           (BCM_BASE + 0x00000800L)
#define ABUS_OFFSET          (BCM_BASE + 0x00000C00L)
#define CRYPTO_REG_OFFSET    (BCM_BASE + 0x00001000L)
#define HASH_OFFSET          (BCM_BASE + 0x00001800L)
#define SCRATCH_TBL_OFFSET   (BCM_BASE + 0x00001C00L)

#define BIU_HST_INTERRUPT_MASK   (BIU_OFFSET + 0x00CC)
#define BIU_SP_INTERRUPT_MASK    (BIU_OFFSET + 0x021C)
#define BIU_SP_CONTROL           (BIU_OFFSET + 0x0220)

#define ADEC_CTRL                (ADEC_OFFSET + 0x0000)
#define ADEC_CTRL2               (ADEC_OFFSET + 0x0004)
#define AXI_SL_CTRL              (ADEC_OFFSET + 0x0008)
#define ADEC_INT                 (ADEC_OFFSET + 0x000C)
#define ADEC_INT_MSK             (ADEC_OFFSET + 0x0010)
#define ADEC_ACC_ERR_ADR         (ADEC_OFFSET + 0x0014)
#define ADEC_MP_FIFO_ERR_ADR     (ADEC_OFFSET + 0x0018)

#define DMA_IN_CTRL                  (DMA_OFFSET + 0x0000)
#define DMA_IN_STATUS                (DMA_OFFSET + 0x0004)
#define DMA_IN_SRC_ADR               (DMA_OFFSET + 0x0008)
#define DMA_IN_XFER_CNTR             (DMA_OFFSET + 0x000C)
#define DMA_IN_NX_LL_ADR             (DMA_OFFSET + 0x0010)
#define DMA_IN_INT                   (DMA_OFFSET + 0x0014)
#define DMA_IN_INT_MSK               (DMA_OFFSET + 0x0018)
#define DMA_OUT_CTRL                 (DMA_OFFSET + 0x001C)
#define DMA_OUT_STATUS               (DMA_OFFSET + 0x0020)
#define DMA_OUT_DEST_ADR             (DMA_OFFSET + 0x0024)
#define DMA_OUT_XFER_CNTR            (DMA_OFFSET + 0x0028)
#define DMA_OUT_NX_LL_ADR            (DMA_OFFSET + 0x002C)
#define DMA_OUT_INT                  (DMA_OFFSET + 0x0030)
#define DMA_OUT_INT_MSK              (DMA_OFFSET + 0x0034)

#define ABUS_BUS_CTRL            (ABUS_OFFSET + 0x0000)

#define HASH_CONFIG              (HASH_OFFSET + 0x0000)
#define HASH_CONTROL             (HASH_OFFSET + 0x0004)
#define HASH_COMMAND             (HASH_OFFSET + 0x0008)
#define HASH_STATUS              (HASH_OFFSET + 0x000C)
#define HASH_INCOME_SEG_SZ       (HASH_OFFSET + 0x0010)
#define HASH_TOTAL_MSG_SZ_L      (HASH_OFFSET + 0x0018)
#define HASH_TOTAL_MSG_SZ_H      (HASH_OFFSET + 0x001C)
#define HASH_DIGEST_BASE         (HASH_OFFSET + 0x0020)
#define HASH_DIGEST(a)           (HASH_DIGEST_BASE + ((a) << 2))
#define HASH_DIGEST_H_BASE       (HASH_OFFSET + 0x0040)
#define HASH_DIGEST_H(a)         (HASH_DIGEST_H_BASE + ((a) << 2))

#define CRYPTO_AES_CONFIG_REG            (CRYPTO_REG_OFFSET + 0x0000)
#define CRYPTO_AES_CONTROL_REG           (CRYPTO_REG_OFFSET + 0x0004)
#define CRYPTO_AES_COMMAND_REG           (CRYPTO_REG_OFFSET + 0x0008)
#define CRYPTO_AES_STATUS_REG            (CRYPTO_REG_OFFSET + 0x000C)
#define CRYPTO_AES_INTRPT_SRC_REG        (CRYPTO_REG_OFFSET + 0x0010)
#define CRYPTO_AES_INTRPT_SRC_EN_REG     (CRYPTO_REG_OFFSET + 0x0014)
#define CRYPTO_AES_STREAM_SIZE_REG       (CRYPTO_REG_OFFSET + 0x0018)
#define CRYPTO_ENGINE_SEL_REG            (CRYPTO_REG_OFFSET + 0x00A8)

#define CRYPTO_K2_BASE                   (CRYPTO_REG_OFFSET + 0x0058)
#define CRYPTO_K2_W_REG(a)               (CRYPTO_K2_BASE + a*0x04)
#define CRYPTO_K1_BASE                   (CRYPTO_REG_OFFSET + 0x0078)
#define CRYPTO_K1_W_REG(a)               (CRYPTO_K1_BASE + a*0x04)
#define CRYPTO_IV_BASE                   (CRYPTO_REG_OFFSET + 0x0098)
#define CRYPTO_IV_REG(a)                 (CRYPTO_IV_BASE + a*0x04)

#define KSTR_PLATFORM_APMU_BASE	    0xD4282800
#define AES_CLK_RES_CTRL	        (KSTR_PLATFORM_APMU_BASE + 0x68)

typedef enum {
    ABUS_GRP_A_HASH = 0x0,
    ABUS_GRP_A_RC4 = 0x4,
    ABUS_GRP_A_ECP = 0x5,
    ABUS_GRP_A_ZMODP = 0x6,
} ABUS_GRP_A_T;

typedef enum {
    ABUS_GRP_B_AES = 0x0,
    ABUS_GRP_B_DES = 0x1,
    ABUS_GRP_B_BYPASS = 0x2,
    ABUS_GRP_B_RC4 = 0x4,
} ABUS_GRP_B_T;

typedef enum {
    ABUS_STRAIGHT = 0,
    ABUS_CROSS,
} ABUS_CROSS_BAR_T;

typedef enum {
    /* reset bit */
    ACC_ENG_DMA = 1,
    ACC_ENG_HASH = 5,
    ACC_ENG_CRYPTO = 3,
    ACC_ENG_EBG = 10,
    ACC_ENG_MCT = 8,
    ACC_ENG_SCRATCH_PAD = 6,
    ACC_ENG_ZMOP = 7,
    ACC_ENG_ALL,    
} ADEC_ACC_ENG_T;

#define bcm_write32(reg_addr, value)    \
    (( (* ( (volatile uint32_t*)(reg_addr) ) ) = (value)))


#define bcm_read32(reg_addr)            \
    (* ( (volatile uint32_t*)(reg_addr)))


void bcm_enable(int enable);
int dma_input_config(int rid_ext, int rid);
int dma_input_address(uint32_t src_addr, uint32_t src_size, int chained);
void dma_input_start(void);
void dma_input_stop(void);
int dma_wait_input_finish(void);
int adec_engine_hw_reset(ADEC_ACC_ENG_T engine);
int abus_set_mode(ABUS_GRP_A_T grp_a_mode, ABUS_GRP_B_T grp_b_mode,
                  ABUS_CROSS_BAR_T input_bar, ABUS_CROSS_BAR_T output_bar);
void dma_output_start(void);
void dma_output_stop(void);
int dma_wait_output_finish(void);
int dma_output_config(int wid_ext, int wid);
int dma_output_address(uint32_t dst_addr, uint32_t dst_size, int chained);

#endif