marvell/uboot/drivers/geu/asr_geu.h

#ifndef _ASR_GEU_H_
#define _ASR_GEU_H_

#include <common.h>
#include <ubi_uboot.h>

enum {
	AES_ECB = 0,
	AES_CBC,
};

enum {
	AES_DECRYPT = 0,
	AES_ENCRYPT = 1,
};

#define EACH_DMA_PROCESS_SIZE	(64*1024)

/* mem align, align: align mask of bytes */
#define buf_align(buf, align) (void *)(((unsigned long)(buf) + (align)) & ~(align))

#define GEU_BASE			(0xD4201000)
#define APMU_BASE			(0xD4282800)

#define GEU_STATUS				(0x0000)
#define GEU_CONFIG				(0x0004)

#define GEU_FUSE_APCFG1			(0x0404)
#define GEU_FUSE_APCFG2			(0x0408)
#define GEU_FUSE_APCFG3			(0x040C)

/* All AES related setting, need to clear before configure AES */
#define GEU_CFG_AES_MSK			(0xA100394F)

/* ASR1803/1806/1828/1903 */
#define GEU_SECURE_KEY_ACCESS_DISABLED	(1 << 29)

/* 1901/1906 registers */
#define GEU_KSTR_BANK6_LCS					(0x0168)
#define GEU_KSTR_LCS_DM_BASE				(3)
#define GEU_KSTR_LCS_MASK					(0x7)
#define GEU_FUSE_WORD_BANK0					(0x0104)


#define GEU_FUSE_BANK0_127_96		(0x0410)
#define GEU_FUSE_BANK0_159_128		(0x04A8)
#define GEU_FUSE_BANK0_191_160		(0x048C)
#define GEU_FUSE_BANK0_207_192		(0x0418)
#define GEU_FUSE_BANK0_239_208		(0x0414)
#define GEU_FUSE_BANK0_255_240		(0x04C8)

#define GEU_FUSE_VAL_ROOT_KEY(n)		(0x424 + (n)*4)
#define GEU_FUSE_VAL_OEM_HASH_KEY(n)	(0x444 + (n)*4)

#define GEU_FUSE_BANK3_223_192		(0x041C)
#define GEU_FUSE_BANK3_255_224		(0x0420)
#define GEU_BLOCK3_RESERVED(n)		(0x490 + (n)*4)

#define GEU_CFG_DMA_MODE_EN		(1 << 31)
#define GEU_CFG_CBC_ECB			(1 << 29)
#define GEU_CFG_PWR_BYP			(1 << 28)
#define GEU_CFG_WRITE_IV		(1 << 24)
#define GEU_CFG_ENA_RKEK		(1 << 13)
#define GEU_CFG_ENC_DEC			(1 << 3)
#define GEU_CFG_OCB_BYP			(1 << 2)
#define GEU_CFG_KEY_SIZE(x)		((x) << 0)

#define GEU_STATUS_DATA_ENCDEC_READY	(1 << 3)
#define GEU_STATUS_ROUND_KEY_READY		(1 << 2)
#define GEU_STATUS_DATA_ENCDEC_ENA		(1 << 1)
#define	GEU_STATUS_ROUND_KEY_START		(1 << 0)

#define GEU_INIT_KEY(x)			(0x08 + (x << 2))
#define GEU_IN_DATA(x)			(0x28 + (x << 2))
#define GEU_INIT_IV(x)			(0x38 + (x << 2))
#define GEU_OUT_DATA(x)			(0x58 + (x << 2))

/* rndom relevant regs */
#define GEU_HW_RANDOM_NUM_GEN		(0x488)
#define GEU_HW_RANDOM_NUM_SEED		(0x038)
#define GEU_PRNG_CTRL_REG			(0x3A8)

#define GEU_PRNG_EN				(1 << 24)

/* APMU regs offset */
#define AES_CLK_RES_CTRL	0x68
#define STBL_TIMER			0x084
#define DEBUG_REG			0x088
#define MP_IDLE_CFG0		0x120
#define CORE0_IDLE			0x124

#define GEU_RX_CHANNEL		30
#define GEU_TX_CHANNEL		31

#define DMA_DEVICE_GEU_RXREQ		(68)
#define DMA_DEVICE_GEU_TXREQ		(69)

struct geu_data {
	volatile uint32_t geu_phybase;
	uint32_t apmu_phybase;
	uint32_t clk_en;
	struct mutex clk_lock;
	struct mutex eng_lock;
};

void geu_write32(uint32_t reg, uint32_t val);
uint32_t geu_read32(uint32_t reg);
void asr_geu_get(void);
void asr_geu_put(void);
void geu_enable_clk(void);
void geu_disable_clk(void);

int aes_ecb_encrypt_geu(const uint8_t *key, uint32_t keylen, bool use_rkek,\
						const void* plaintext, void* ciphertext, size_t size);

int aes_ecb_decrypt_geu(const uint8_t *key, uint32_t keylen, bool use_rkek,\
						const void* ciphertext, void* plaintext, size_t size);	

int aes_cbc_encrypt_geu(const uint8_t *iv, const uint8_t *key, uint32_t keylen, \
						bool use_rkek, const void* plaintext, void* ciphertext, size_t size);

int aes_cbc_decrypt_geu(const uint8_t *iv, const uint8_t *key, uint32_t keylen, \
						bool use_rkek, const void* plaintext, void* ciphertext, size_t size);

#ifdef GEU_SELFTEST
void asr_geu_test_init(void);
#endif

#endif