blob: 66196693d3eb4a4bb4b01e52cd15fe7570483816 [file] [log] [blame]
#ifndef _SPI_DRV_H_
#define _SPI_DRV_H_
struct s_lcd_cmd_des;
enum {
SPI_EDGE_RISING = 0,
SPI_EDGE_FALLING = 1,
SPI_EDGE_LIMIT
};
enum {
SPI_ENDIAN_LSB = 0,
SPI_ENDIAN_MSB = 1,
SPI_ENDIAN_LIMIT
};
enum {
SPI_PATH_IMAGE = 0,
SPI_PATH_REGISTER = 1,
SPI_PATH_LIMIT
};
enum {
SPI_FORMAT_RGB565 = 0,
SPI_FORMAT_RGB666 = 1,
SPI_FORMAT_RGB666_2_3 = 2,
SPI_FORMAT_RGB888 = 3,
SPI_FORMAT_RGB888_2_3 = 4,
SPI_FORMAT_LIMIT
};
enum {
SPI_STATUS_UNINIT = 0,
SPI_STATUS_INIT = 1,
SPI_STATUS_LIMIT
};
struct timing_spi {
unsigned int wclk; /*KHz*/
unsigned int rclk; /*KHz*/
};
struct spi_info {
unsigned short line_num; /*3 or 4*/
unsigned short interface_id; /*1 or 2*/
unsigned short data_lane_num; /*1 or 2*/
unsigned short format;
unsigned short device_id; /*0 or 1*/
unsigned short sample_edge;
unsigned short force_cs; /*0-disable, 1-enable*/
unsigned short endian;
unsigned short reserved;
struct timing_spi *timing;
};
struct s_spi_ctx {
unsigned int base_addr;
unsigned int sclk; /*KHz*/
unsigned short cur_path;
unsigned short cur_cs;
unsigned short status;
unsigned short reserved;
struct spi_info info;
};
struct s_spi_ctx *spi_init(unsigned int sclk, struct spi_info *info);
int spi_set_cs(struct s_spi_ctx *spi_ctx, unsigned int enable);
int spi_write_cmd(struct s_spi_ctx *spi_ctx, unsigned int cmd, unsigned int bits);
int spi_write_data(struct s_spi_ctx *spi_ctx, unsigned int data, unsigned int bits);
int spi_read_data(struct s_spi_ctx *spi_ctx, unsigned int cmd, unsigned int cmd_bits,
unsigned int *data, unsigned int data_bits);
int spi_write_array(struct s_spi_ctx *spi_ctx, struct s_lcd_cmd_des *cmds, int cmd_len, int fast_mode);
int spi_before_refresh(struct s_spi_ctx *spi_ctx);
int spi_after_refresh(struct s_spi_ctx *spi_ctx);
void spi_uninit(struct s_spi_ctx *mcu_ctx);
#endif /*_SPI_DRV_H_*/