marvell/uboot/include/spi_flash_chip.h

#ifndef _SPI_FLASH_H
#define _SPI_FLASH_H

#include "linux/mtd/mtd.h"

#define false	0
#define true	1

#ifndef min
#define min(a, b)    ((a) < (b) ? (a) : (b))
#endif

#ifndef max
#define max(a, b)    ((a) > (b) ? (a) : (b))
#endif

/* Vendor Manufacture ID */
#define SPIFLASH_MFR_MICRON		0x2C
#define SPIFLASH_MFR_GIGADEVICE		0xC8
#define SPIFLASH_MFR_WINBOND		0xEF
#define SPIFLASH_MFR_MXIC		0xC2
#define SPIFLASH_MFR_DOSILICON		0xE5
#define SPIFLASH_MFR_ZETTADEVICE	0xBA
#define SPIFLASH_MFR_DOUQI		0x54
#define SPIFLASH_MFR_DOSILICON_NOR	0xF8
#define SPIFLASH_MFR_PUYA		0x85
#define SPIFLASH_MFR_XM			0x20
#define SPIFLASH_MFR_FMSH		0xA1

struct spi_flash_cmd;
struct spi_flash_chip;

struct spi_flash_info {
	uint64_t totalsize; /* Total size of the MTD */
	u_int32_t erasesize;
	u_int32_t pagesize;
};

struct micron_onfi_specific {
	u8		two_plane_page_read;		/*166*/
	u8		reserved0[8];			/*167-174*/
	u8		otp_mode;			/*175*/
	u8		otp_page_start;			/*176*/
	u8		otp_data_protect_addr;		/*177*/
	u8		otp_page_number;		/*178*/
	u8		otp_feature_addr;		/*179*/
	u8		reserved1[68];			/*180-247*/
	u8		ecc_ability;			/*248*/
	u8		die_selection;			/*249*/
	u8		reserved2[3];			/*250-252*/
	u8		parameter_page_version;		/*253*/
}__attribute__((packed));

union spi_nand_vendor_specific {
	u8		vendor_specific[88];
	struct micron_onfi_specific micron_sepcific;
};

struct spi_nand_onfi_params {
	/* rev info and features block */
	/* 'O' 'N' 'F' 'I'  */
	u8		sig[4];				/*0-3*/
	u16		revision;			/*4-5*/
	u16		features;			/*6-7*/
	u16		opt_cmd;			/*8-9*/
	u8		reserved0[22];			/*10-31*/

	/* manufacturer information block */
	char		manufacturer[12];		/*32-43*/
	char		model[20];			/*44-63*/
	u8		mfr_id;				/*64*/
	u16		date_code;			/*65-66*/
	u8		reserved1[13];			/*67-79*/

	/* memory organization block */
	u32		byte_per_page;			/*80-83*/
	u16		spare_bytes_per_page;		/*84*85*/
	u32		data_bytes_per_ppage;		/*86-89*/
	u16		spare_bytes_per_ppage;		/*90-91*/
	u32		pages_per_block;		/*92-95*/
	u32		blocks_per_lun;			/*96-99*/
	u8		lun_count;			/*100*/
	u8		addr_cycles;			/*101*/
	u8		bits_per_cell;			/*102*/
	u16		bb_per_lun;			/*103-104*/
	u16		block_endurance;		/*105-106*/
	u8		guaranteed_good_blocks;		/*107*/
	u16		guaranteed_block_endurance;	/*108-109*/
	u8		programs_per_page;		/*110*/
	u8		ppage_attr;			/*111*/
	u8		ecc_bits;			/*112*/
	u8		interleaved_bits;		/*113*/
	u8		interleaved_ops;		/*114*/
	u8		reserved2[13];			/*115-127*/

	/* electrical parameter block */
	u8		io_pin_capacitance_max;		/*128*/
	u16		timing_mode;			/*129-130*/
	u16		program_cache_timing_mode;	/*131-132*/
	u16		t_prog;				/*133-134*/
	u16		t_bers;				/*135-136*/
	u16		t_r;				/*137-138*/
	u16		t_ccs;				/*139-140*/
	u8		reserved3[23];			/*141-163*/

	/* vendor */
	u16		vendor_specific_revision;	/*164-165*/
	union spi_nand_vendor_specific vendor;		/*166-253*/

	u16		crc;				/*254-255*/
} __attribute__((packed));

#define ONFI_CRC_BASE	0x4F4E

/**
 * struct spi_flash_chip - SPI-NAND Private Flash Chip Data
 * @name:		name of the chip
 * @spi:		[INTERN] point to spi device structure
 * @mfr_id:		[BOARDSPECIFIC] manufacture id
 * @dev_id:		[BOARDSPECIFIC] device id
 * @read_cache_op:	[REPLACEABLE] Opcode of read from cache
 * @write_cache_op:	[REPLACEABLE] Opcode of program load
 * @write_cache_rdm_op:	[REPLACEABLE] Opcode of program load random
 * @oobbuf:		[INTERN] buffer for read/write oob
 * @size:		[INTERN] the size of chip
 * @block_size:		[INTERN] the size of eraseblock
 * @page_size:		[INTERN] the size of page
 * @oob_size:	[INTERN] the size of page oob size
 * @block_shift:	[INTERN] number of address bits in a eraseblock
 * @page_shift:		[INTERN] number of address bits in a page (column
 *			address bits).
 * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
 * @options:		[BOARDSPECIFIC] various chip options. They can partly
 *			be set to inform nand_scan about special functionality.
 * @ecc_strength:	[INTERN] ECC correctability
 * @refresh_threshold:	[INTERN] Bitflip threshold to return -EUCLEAN
 * @ecclayout:		[BOARDSPECIFIC] ECC layout control structure
 *			See the defines for further explanation.
 * @onfi_params:	[INTERN] holds the ONFI page parameter
 */
struct spi_flash_chip {
	char *name;
	struct spi_flash_cmd_cfg *table;
	struct qspi_host *host;

	u8		cs;
	u8		mfr_id;
	u16		dev_id;
	u32		tx_max_len;
	u32		rx_max_len;
	int		state;
	struct mtd_info	*mtd;

	int		xip_read;
	int		bus_clk;
	u8		read_op;
	u8		read_cache_op;
	u8		write_op;
	u8		write_cache_op;
	u8		write_cache_rdm_op;
	u32		tclqv; /* in nanosecond*/
	u32		tset; /* in nanosecond*/
	u32		thold; /* in nanosecond*/

	int (*issue_cmd)(struct spi_flash_chip *chip,
			 struct spi_flash_cmd *cmd);
	int (*check_dtr)(struct spi_flash_chip *chip);
	int (*setup_memmap_read)(struct spi_flash_chip *chip,
				 struct spi_flash_cmd_cfg *xip_cfg);
	int (*memmap_read)(struct spi_flash_chip *chip,
				u8 *buf, u32 from, u32 len);
	int (*search_bbm_table)(struct spi_flash_chip *chip, int addr);
	int (*low_level_scrub)(struct spi_flash_chip *chip, int page_addr,
				int corrected);
	int (*enable_ecc)(struct spi_flash_chip *chip);
	int (*disable_ecc)(struct spi_flash_chip *chip);
	void (*get_ecc_status)(struct spi_flash_chip *chip, u8 status,
				u32 *corrected, u32 *ecc_error);

	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
	int (*scan_bbt)(struct mtd_info *mtd);

	u8		*buf;
	u8		*oobbuf;
	int		cached_page;
	u32		cached_page_bitflips;
	u8		cached_page_ecc_off;

	u8		en_addr_4byte;
	u8		qpi_enabled;
	u8		qpi_dummy;
	u64		size;
	u32		block_size;
	u16		page_size;
	u16		oob_size;
	u8		lun_shift;
	u8		block_shift;
	u8		page_shift;
	u16		page_mask;
	u32		options;
	u32		bbt_options;
	u32		ecc_strength;
	u8		refresh_threshold;
	u8		lun;
	u32		max_mhz;
	void *		flash_info;
	u8		rx_mode;
	u8		tx_mode;
	struct nand_ecclayout *ecclayout;
	u8		*bbt;
	struct spi_nand_onfi_params onfi_params;
	void		*priv;
};

#define SPINAND_MAX_ADDR_LEN		4

enum {
	CMD_W_NO_DATA = 0,
	CMD_W_RX_DATA = 1,
	CMD_W_TX_DATA = 2,
};

struct spi_flash_cmd_cfg {
	u8		opcode;
	u8		cmd_dtr;
	u8		addr_bytes;
	u8		addr_pins;
	u8		addr_dtr;
	u8		mode_bits;
	u8		mode_pins;
	u8		mode_dtr;
	u8		dummy_cycles;
	u8		dummy_pins;
	u8		data_pins;
	u8		data_dtr;
	s8		seq_id;
	s8		type;
};

#define SPI_CMD_DTR(_opcode,_cmd_dtr,_addr_bytes,_addr_pins,_addr_dtr, \
		_mode_bits,_mode_pins,_mode_dtr,_dummy_cycles,_dummy_pins, \
		_data_pins,_data_dtr, _seq_id, _type) \
	{ \
		.opcode		= _opcode,		\
		.cmd_dtr	= _cmd_dtr,		\
		.addr_bytes	= _addr_bytes,		\
		.addr_pins	= _addr_pins,		\
		.addr_dtr	= _addr_dtr,		\
		.mode_bits	= _mode_bits,		\
		.mode_pins	= _mode_pins,		\
		.mode_dtr	= _mode_dtr,		\
		.dummy_cycles	= _dummy_cycles,	\
		.dummy_pins	= _dummy_pins,		\
		.data_pins	= _data_pins,		\
		.data_dtr	= _data_dtr,		\
		.seq_id		= _seq_id,		\
		.type		= _type,		\
	}

#define SPI_CMD(_opcode,_addr_bytes,_addr_pins,_mode_bits, \
		_mode_pins,_dummy_cycles,_dummy_pins,_data_pins, \
		_seq_id, _type) \
	SPI_CMD_DTR(_opcode,0,_addr_bytes,_addr_pins,0, \
		_mode_bits,_mode_pins,0,_dummy_cycles,_dummy_pins, \
		_data_pins,0, _seq_id, _type)
enum {
	RST_AHB_DOMAIN = 1 << 0,
	AHB_MAP_SIZE_PAGE = 1 << 1,
};

struct spi_flash_cmd {
	struct spi_flash_cmd_cfg *cmd_cfg;
	u8		n_addr;		/* Number of address */
	u8		addr[SPINAND_MAX_ADDR_LEN];	/* Reg Offset */
	u32		n_tx;		/* Number of tx bytes */
	const u8	*tx_buf;	/* Tx buf */
	u32		n_rx;		/* Number of rx bytes */
	u8		*rx_buf;	/* Rx buf */
	u8		mode;
	u8		flag;
	int		error;
};

/* feature registers */
#define REG_BLOCK_LOCK		0xa0
#define REG_CFG			0xb0
#define REG_STATUS		0xc0
#define REG_DIE_SELECT		0xd0

/* status */
#define STATUS_OIP_MASK		0x01
#define STATUS_CRBSY_MASK	0x80
#define STATUS_READY		(0 << 0)
#define STATUS_BUSY		(1 << 0)

#define STATUS_E_FAIL_MASK	0x04
#define STATUS_E_FAIL		(1 << 2)

#define STATUS_P_FAIL_MASK	0x08
#define STATUS_P_FAIL		(1 << 3)

enum {
	NORMAL_MODE,
	OTP_MODE,
	OTP_PROTECT_MODE,
	SNOR_READ_ENABLE_MODE,
};

/* Ability of SPI Controllers */
#define SPI_OPM_RX_QUAD		1 << 2 /* Support 4 pin RX */
#define SPI_OPM_RX_DUAL		1 << 1 /* Support 2 pin RX */
#define SPI_OPM_RX		1 << 0 /* Support 1 pin RX */
#define SPI_OPM_TX_QUAD		1 << 2 /* Support 4 pin TX */
#define SPI_OPM_TX		1 << 0 /* Support 1 pin TX */

static u8 ilog2(unsigned int v)
{
	u8 l = 0;
	while ((1UL << l) < v)
		l++;
	return l;
}

void spi_flash_chip_init(void);
extern struct spi_flash_chip *cur_sf_chip;

#endif