| From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001 |
| From: Jonas Gorski <jogo@openwrt.org> |
| Date: Sun, 8 Dec 2013 14:17:50 +0100 |
| Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals |
| |
| --- |
| arch/mips/bcm63xx/reset.c | 39 ++++++++++++++-------- |
| arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++ |
| arch/mips/pci/pci-bcm63xx.c | 7 ++++ |
| 3 files changed, 34 insertions(+), 14 deletions(-) |
| |
| --- a/arch/mips/bcm63xx/reset.c |
| +++ b/arch/mips/bcm63xx/reset.c |
| @@ -29,7 +29,9 @@ |
| [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \ |
| [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \ |
| [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ |
| - [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, |
| + [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \ |
| + [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \ |
| + [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD, |
| |
| #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK |
| #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK |
| @@ -43,6 +45,8 @@ |
| #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK |
| #define BCM3368_RESET_PCIE 0 |
| #define BCM3368_RESET_PCIE_EXT 0 |
| +#define BCM3368_RESET_PCIE_CORE 0 |
| +#define BCM3368_RESET_PCIE_HARD 0 |
| |
| |
| #define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK |
| @@ -55,11 +59,10 @@ |
| #define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK |
| #define BCM6318_RESET_PCM 0 |
| #define BCM6318_RESET_MPI 0 |
| -#define BCM6318_RESET_PCIE \ |
| - (SOFTRESET_6318_PCIE_MASK | \ |
| - SOFTRESET_6318_PCIE_CORE_MASK | \ |
| - SOFTRESET_6318_PCIE_HARD_MASK) |
| +#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK |
| #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK |
| +#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK |
| +#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK |
| |
| #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK |
| #define BCM6328_RESET_ENET 0 |
| @@ -71,11 +74,10 @@ |
| #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK |
| #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK |
| #define BCM6328_RESET_MPI 0 |
| -#define BCM6328_RESET_PCIE \ |
| - (SOFTRESET_6328_PCIE_MASK | \ |
| - SOFTRESET_6328_PCIE_CORE_MASK | \ |
| - SOFTRESET_6328_PCIE_HARD_MASK) |
| +#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK |
| #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK |
| +#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK |
| +#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK |
| |
| #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK |
| #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK |
| @@ -89,6 +91,8 @@ |
| #define BCM6338_RESET_MPI 0 |
| #define BCM6338_RESET_PCIE 0 |
| #define BCM6338_RESET_PCIE_EXT 0 |
| +#define BCM6338_RESET_PCIE_CORE 0 |
| +#define BCM6338_RESET_PCIE_HARD 0 |
| |
| #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK |
| #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK |
| @@ -102,6 +106,8 @@ |
| #define BCM6348_RESET_MPI 0 |
| #define BCM6348_RESET_PCIE 0 |
| #define BCM6348_RESET_PCIE_EXT 0 |
| +#define BCM6348_RESET_PCIE_CORE 0 |
| +#define BCM6348_RESET_PCIE_HARD 0 |
| |
| #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK |
| #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK |
| @@ -115,6 +121,8 @@ |
| #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK |
| #define BCM6358_RESET_PCIE 0 |
| #define BCM6358_RESET_PCIE_EXT 0 |
| +#define BCM6358_RESET_PCIE_CORE 0 |
| +#define BCM6358_RESET_PCIE_HARD 0 |
| |
| #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK |
| #define BCM6362_RESET_ENET 0 |
| @@ -126,9 +134,10 @@ |
| #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK |
| #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK |
| #define BCM6362_RESET_MPI 0 |
| -#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \ |
| - SOFTRESET_6362_PCIE_CORE_MASK) |
| +#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK |
| #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK |
| +#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK |
| +#define BCM6362_RESET_PCIE_HARD 0 |
| |
| #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK |
| #define BCM6368_RESET_ENET 0 |
| @@ -142,6 +151,8 @@ |
| #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK |
| #define BCM6368_RESET_PCIE 0 |
| #define BCM6368_RESET_PCIE_EXT 0 |
| +#define BCM6368_RESET_PCIE_CORE 0 |
| +#define BCM6368_RESET_PCIE_HARD 0 |
| |
| #define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK |
| #define BCM63268_RESET_ENET 0 |
| @@ -153,10 +164,10 @@ |
| #define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK |
| #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK |
| #define BCM63268_RESET_MPI 0 |
| -#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ |
| - SOFTRESET_63268_PCIE_CORE_MASK | \ |
| - SOFTRESET_63268_PCIE_HARD_MASK) |
| +#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK |
| #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK |
| +#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK |
| +#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK |
| |
| /* |
| * core reset bits |
| --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |
| +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |
| @@ -15,6 +15,8 @@ enum bcm63xx_core_reset { |
| BCM63XX_RESET_MPI, |
| BCM63XX_RESET_PCIE, |
| BCM63XX_RESET_PCIE_EXT, |
| + BCM63XX_RESET_PCIE_CORE, |
| + BCM63XX_RESET_PCIE_HARD, |
| }; |
| |
| void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset); |
| --- a/arch/mips/pci/pci-bcm63xx.c |
| +++ b/arch/mips/pci/pci-bcm63xx.c |
| @@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo |
| |
| /* reset the PCIe core */ |
| bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); |
| + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); |
| bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); |
| + if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) { |
| + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1); |
| + mdelay(10); |
| + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); |
| + } |
| mdelay(10); |
| |
| + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); |
| bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); |
| mdelay(10); |
| |